Update U-boot to v2017.01 with the merge history
Bug: 34811400
Test: Booted a rpi3 with the new version
Change-Id: Ib7bf20ef73c8dd9153d12c157dcb1825f190827c
diff --git a/.gitignore b/.gitignore
index 33abbd3..7fac5b3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -31,7 +31,7 @@
# Top-level generic files
#
/MLO*
-/SPL
+/SPL*
/System.map
/u-boot*
/boards.cfg
diff --git a/.travis.yml b/.travis.yml
index 18bf2ed..6c4ea59 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -3,7 +3,8 @@
# build U-Boot on Travis CI - https://travis-ci.org/
-sudo: true
+sudo: required
+dist: trusty
language: c
@@ -18,58 +19,90 @@
- libsdl1.2-dev
- python
- python-virtualenv
-
-cache:
- - apt
+ - gcc-powerpc-linux-gnu
+ - gcc-arm-linux-gnueabihf
+ - gcc-aarch64-linux-gnu
+ - iasl
+ - grub-efi-ia32-bin
+ - rpm2cpio
+ - wget
install:
# install latest device tree compiler
- - git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ - git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
- make -j4 -C /tmp/dtc
+ # Clone uboot-test-hooks
+ - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
+ - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
+ - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
# prepare buildman environment
- - export BUILDMAN_ROOT="root:"
- - export BUILDMAN_PPC="ppc:"
- - export BUILDMAN_ARM="arm:"
- - export BUILDMAN_SANDBOX="sandbox:"
- - echo -e "[toolchain]\n${BUILDMAN_ROOT} /\n" > ~/.buildman
- - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/\n" >> ~/.buildman
- - echo -e "${BUILDMAN_ARM} /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/\n" >> ~/.buildman
- - echo -e "${BUILDMAN_SANDBOX} /usr/bin/gcc\n" >> ~/.buildman
- - export BUILDMAN_ALIAS="x86:"
- - export BUILDMAN_ALIAS_ARM="arm:"
- - echo -e "\n\n[toolchain-alias]\n${BUILDMAN_ALIAS} i386\n" >> ~/.buildman
- - echo -e "${BUILDMAN_ALIAS_ARM} armv5te\n" >> ~/.buildman
+ - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
+ - echo -e "\n[toolchain-alias]\nblackfin = bfin\nsh = sh4\nopenrisc = or32" >> ~/.buildman
- cat ~/.buildman
- virtualenv /tmp/venv
- . /tmp/venv/bin/activate
- pip install pytest
+ - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+ - mkdir ~/grub2-arm
+ - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
env:
global:
- - PATH=/tmp/dtc:$PATH
+ - PATH=/tmp/dtc:/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:$PATH
+ - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
- BUILD_DIR=build
- HOSTCC="cc"
- HOSTCXX="c++"
before_script:
# install toolchains based on TOOLCHAIN} variable
- - if [[ "${TOOLCHAIN}" == *aarch64* ]]; then ./tools/buildman/buildman --fetch-arch aarch64 ; fi
- - if [[ "${TOOLCHAIN}" == *arm* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh ; fi
- - if [[ "${TOOLCHAIN}" == *arm* ]]; then sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi
- if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
- - if [[ "${TOOLCHAIN}" == *i386* ]]; then ./tools/buildman/buildman sandbox --fetch-arch i386 ; fi
+ - if [[ "${TOOLCHAIN}" == *bfin* ]]; then ./tools/buildman/buildman --fetch-arch bfin ; fi
- if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
+ - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
- if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
- - if [[ "${TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi
- - if [[ "${TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
+ - if [[ "${TOOLCHAIN}" == *or32* ]]; then ./tools/buildman/buildman --fetch-arch or32 ; fi
+ - if [[ "${TOOLCHAIN}" == *sh4* ]]; then ./tools/buildman/buildman --fetch-arch sh4 ; fi
+ - if [[ "${TOOLCHAIN}" == *x86_64* ]]; then
+ ./tools/buildman/buildman --fetch-arch x86_64;
+ echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
+ fi
+ - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then ./tools/buildman/buildman --fetch-arch xtensa ; fi
+ - if [[ "${QEMU_TARGET}" != "" ]]; then
+ git clone git://git.qemu.org/qemu.git /tmp/qemu;
+ pushd /tmp/qemu;
+ git submodule update --init dtc &&
+ git checkout v2.8.0-rc3 &&
+ ./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
+ make -j4 all install;
+ popd;
+ fi
script:
- # the execution sequence for each test
- - if [[ "${TEST_CMD}" != "" ]]; then
- ${TEST_CMD};
- fi
+ # Comments must be outside the command strings below, or the Travis parser
+ # will get confused.
+ #
+ # Exit code 129 means warnings only.
- if [[ "${BUILDMAN}" != "" ]]; then
- tools/buildman/buildman ${BUILDMAN};
+ set +e;
+ tools/buildman/buildman -P ${BUILDMAN};
+ ret=$?;
+ if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+ tools/buildman/buildman -sdeP ${BUILDMAN};
+ exit $ret;
+ fi;
+ fi
+ # "not a_test_which_does_not_exist" is a dummy -k parameter which will
+ # never prevent any test from running. That way, we can always pass
+ # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom
+ # value.
+ - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD};
+ cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/;
+ cp ~/grub2-arm/usr/lib/grub2/arm-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi;
+ if [[ "${TEST_PY_BD}" != "" ]]; then
+ ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
+ -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
+ --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
fi
matrix:
@@ -77,113 +110,207 @@
# we need to build by vendor due to 50min time limit for builds
# each env setting here is a dedicated build
- env:
- - BUILDMAN="arm1136"
- TOOLCHAIN="arm"
+ - BUILDMAN="arm11"
- env:
- - BUILDMAN="arm1136"
- TOOLCHAIN="arm"
- - env:
- - BUILDMAN="arm1176"
- TOOLCHAIN="arm"
- - env:
- - BUILDMAN="arm720t"
- TOOLCHAIN="arm"
+ - BUILDMAN="arm7"
- env:
- BUILDMAN="arm920t"
- TOOLCHAIN="arm"
+ - env:
+ - JOB="arm926ejs"
+ BUILDMAN="arm926ejs -x mx,siemens,atmel"
+ - env:
+ - BUILDMAN="arm946es"
- env:
- BUILDMAN="atmel -x avr32"
- TOOLCHAIN="arm"
- env:
- BUILDMAN="avr32"
TOOLCHAIN="avr32"
- env:
- - BUILDMAN="davinci"
- TOOLCHAIN="arm"
- - env:
- BUILDMAN="denx"
- TOOLCHAIN="arm"
- env:
- - BUILDMAN="freescale -x powerpc,m68k,aarch64"
- TOOLCHAIN="arm"
+ - JOB="Freescale ARM32"
+ BUILDMAN="freescale -x powerpc,m68k,aarch64"
+ - env:
+ - JOB="Freescale AArch64"
+ BUILDMAN="freescale -x powerpc,m68k,armv7,arm9,arm11"
+ - env:
+ - JOB="i.MX (non-Freescale)"
+ BUILDMAN="mx -x freescale"
+ - env:
+ - BUILDMAN="samsung"
+ - env:
+ - BUILDMAN="sun4i"
+ - env:
+ - BUILDMAN="sun5i"
+ - env:
+ - BUILDMAN="sun6i"
+ - env:
+ - BUILDMAN="sun7i"
+ - env:
+ - BUILDMAN="sun8i"
+ - env:
+ - BUILDMAN="sun9i"
+ - env:
+ - BUILDMAN="sun50i"
+ - env:
+ - JOB="Catch-all ARM"
+ BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,denx,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip"
- env:
- BUILDMAN="sandbox x86"
- TOOLCHAIN="i386"
+ TOOLCHAIN="x86_64"
- env:
- BUILDMAN="kirkwood"
- TOOLCHAIN="arm"
+ - env:
+ - BUILDMAN="mvebu"
+ - env:
+ - BUILDMAN="pxa"
- env:
- BUILDMAN="m68k"
TOOLCHAIN="m68k"
- env:
+ - BUILDMAN="microblaze"
+ TOOLCHAIN="microblaze"
+ - env:
- BUILDMAN="mips"
TOOLCHAIN="mips"
- env:
- BUILDMAN="mpc512x"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="mpc5xx"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="mpc5xxx"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="mpc8260"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="mpc83xx"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="mpc85xx -x freescale"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="t208xrdb t4qds t102*"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="p1_p2_rdb_pc p1010rdb"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="mpc86xx"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="mpc8xx"
- TOOLCHAIN="ppc"
- env:
- BUILDMAN="siemens"
- TOOLCHAIN="arm"
- env:
- - BUILDMAN="ti"
- TOOLCHAIN="arm"
+ - BUILDMAN="tegra"
- env:
- - BUILDMAN="aarch64"
+ - JOB="am33xx"
+ BUILDMAN="am33xx -x siemens"
+ - env:
+ - BUILDMAN="omap3"
+ - env:
+ - BUILDMAN="omap4"
+ - env:
+ - BUILDMAN="omap5"
+ - env:
+ - BUILDMAN="uniphier"
+ - env:
+ - BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip"
TOOLCHAIN="aarch64"
+ - env:
+ - BUILDMAN="rockchip"
+ - env:
+ - BUILDMAN="sh4"
+ TOOLCHAIN="sh4"
+ - env:
+ - BUILDMAN="xtensa"
+ TOOLCHAIN="xtensa"
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
- env:
- - TEST_CMD="cppcheck --force --quiet --inline-suppr ."
+ - JOB="cppcheck"
+ script:
+ - cppcheck --force --quiet --inline-suppr .
# search for TODO within source tree
- env:
- - TEST_CMD="grep -r TODO ."
+ - JOB="grep TODO"
+ script:
+ - grep -r TODO .
# search for FIXME within source tree
- env:
- - TEST_CMD="grep -r FIXME ."
+ - JOB="grep FIXME HACK"
+ script:
+ - grep -r FIXME .
# search for HACK within source tree and ignore HACKKIT board
- - env:
- - TEST_CMD="grep -r HACK . | grep -v HACKKIT"
script:
- grep -r HACK . | grep -v HACKKIT
# some statistics about the code base
- env:
- - TEST_CMD="sloccount ."
+ - JOB="sloccount"
+ script:
+ - sloccount .
+
# test/py
- env:
- - TEST_CMD="./test/py/test.py --bd sandbox --build"
+ - TEST_PY_BD="sandbox"
+ BUILDMAN="^sandbox$"
+ TOOLCHAIN="x86_64"
+ - env:
+ - TEST_PY_BD="vexpress_ca15_tc2"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="arm-softmmu"
+ BUILDMAN="^vexpress_ca15_tc2$"
+ - env:
+ - TEST_PY_BD="vexpress_ca9x4"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="arm-softmmu"
+ BUILDMAN="^vexpress_ca9x4$"
+ - env:
+ - TEST_PY_BD="integratorcp_cm926ejs"
+ TEST_PY_TEST_SPEC="not sleep"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="arm-softmmu"
+ BUILDMAN="^integratorcp_cm926ejs$"
+ - env:
+ - TEST_PY_BD="qemu_mips"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="mips-softmmu"
+ BUILDMAN="^qemu_mips$"
+ TOOLCHAIN="mips"
+ - env:
+ - TEST_PY_BD="qemu_mipsel"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="mipsel-softmmu"
+ BUILDMAN="^qemu_mipsel$"
+ TOOLCHAIN="mips"
+ - env:
+ - TEST_PY_BD="qemu_mips64"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="mips64-softmmu"
+ BUILDMAN="^qemu_mips64$"
+ TOOLCHAIN="mips"
+ - env:
+ - TEST_PY_BD="qemu_mips64el"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="mips64el-softmmu"
+ BUILDMAN="^qemu_mips64el$"
+ TOOLCHAIN="mips"
+ - env:
+ - TEST_PY_BD="qemu-ppce500"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="ppc-softmmu"
+ BUILDMAN="^qemu-ppce500$"
+ - env:
+ - TEST_PY_BD="qemu-x86"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="i386-softmmu"
+ BUILDMAN="^qemu-x86$"
+ TOOLCHAIN="x86_64"
+ BUILD_ROM="yes"
+ - env:
+ - TEST_PY_BD="zynq_zc702"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="arm-softmmu"
+ TEST_PY_ID="--id qemu"
+ BUILDMAN="^zynq_zc702$"
# TODO make it perfect ;-r
diff --git a/Kconfig b/Kconfig
index fdea71e..a44ac91 100644
--- a/Kconfig
+++ b/Kconfig
@@ -55,11 +55,13 @@
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
- default y if ARCH_SUNXI
+ default y if ARCH_SUNXI || TEGRA
+ default y if ARCH_LS2080A
default n
select CMD_BOOTZ if ARM && !ARM64
select CMD_BOOTI if ARM64
select CMD_DHCP
+ select CMD_PXE
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
@@ -83,7 +85,6 @@
config SYS_MALLOC_F_LEN
hex "Size of malloc() pool before relocation"
depends on SYS_MALLOC_F
- default 0x2000 if SPL_DM && SPL_OF_CONTROL
default 0x400
help
Before relocation, memory is very limited on many platforms. Still,
@@ -138,74 +139,6 @@
menu "Boot images"
-config SUPPORT_SPL
- bool
-
-config SUPPORT_TPL
- bool
-
-config SPL
- bool
- depends on SUPPORT_SPL
- prompt "Enable SPL"
- help
- If you want to build SPL as well as the normal image, say Y.
-
-config SPL_SYS_MALLOC_SIMPLE
- bool
- depends on SPL
- prompt "Only use malloc_simple functions in the SPL"
- help
- Say Y here to only use the *_simple malloc functions from
- malloc_simple.c, rather then using the versions from dlmalloc.c;
- this will make the SPL binary smaller at the cost of more heap
- usage as the *_simple malloc functions do not re-use free-ed mem.
-
-config SPL_STACK_R
- depends on SPL
- bool "Enable SDRAM location for SPL stack"
- help
- SPL starts off execution in SRAM and thus typically has only a small
- stack available. Since SPL sets up DRAM while in its board_init_f()
- function, it is possible for the stack to move there before
- board_init_r() is reached. This option enables a special SDRAM
- location for the SPL stack. U-Boot SPL switches to this after
- board_init_f() completes, and before board_init_r() starts.
-
-config SPL_STACK_R_ADDR
- depends on SPL_STACK_R
- hex "SDRAM location for SPL stack"
- help
- Specify the address in SDRAM for the SPL stack. This will be set up
- before board_init_r() is called.
-
-config SPL_STACK_R_MALLOC_SIMPLE_LEN
- depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
- hex "Size of malloc_simple heap after switching to DRAM SPL stack"
- default 0x100000
- help
- Specify the amount of the stack to use as memory pool for
- malloc_simple after switching the stack to DRAM. This may be set
- to give board_init_r() a larger heap then the initial heap in
- SRAM which is limited to SYS_MALLOC_F_LEN bytes.
-
-config SPL_SEPARATE_BSS
- depends on SPL
- bool "BSS section is in a different memory region from text"
- help
- Some platforms need a large BSS region in SPL and can provide this
- because RAM is already set up. In this case BSS can be moved to RAM.
- This option should then be enabled so that the correct device tree
- location is used. Normally we put the device tree at the end of BSS
- but with this option enabled, it goes at _image_binary_end.
-
-config TPL
- bool
- depends on SPL && SUPPORT_TPL
- prompt "Enable TPL"
- help
- If you want to build TPL as well as the normal image and SPL, say Y.
-
config FIT
bool "Support Flattened Image Tree"
help
@@ -366,9 +299,8 @@
help
TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
-config ARCH_FIXUP_FDT
- bool "Enable arch_fixup_fdt() call"
- depends on ARM || MIPS
+config ARCH_FIXUP_FDT_MEMORY
+ bool "Enable arch_fixup_memory_banks() call"
default y
help
Enable FDT memory map syncup before OS boot. This feature can be
diff --git a/MAINTAINERS b/MAINTAINERS
index 8e67202..793ff49 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -69,8 +69,7 @@
M: Marek Vasut <marex@denx.de>
S: Maintainted
T: git git://git.denx.de/u-boot-socfpga.git
-F: arch/arm/cpu/armv7/socfpga/
-F: board/altera/socfpga/
+F: arch/arm/mach-socfpga/
ARM ATMEL AT91
M: Andreas Bießmann <andreas@biessmann.org>
@@ -167,9 +166,8 @@
F: arch/arm/include/asm/arch-stv0991/
ARM SUNXI
-M: Ian Campbell <ijc@hellion.org.uk>
-M: Hans De Goede <hdegoede@redhat.com>
-S: Maintained
+M: Jagan Teki <jagan@openedev.com>
+M: Maxime Ripard <maxime.ripard@free-electrons.com>
T: git git://git.denx.de/u-boot-sunxi.git
F: arch/arm/cpu/armv7/sunxi/
F: arch/arm/include/asm/arch-sunxi/
@@ -244,7 +242,7 @@
F: arch/m68k/
DFU
-M: Lukasz Majewski <l.majewski@samsung.com>
+M: Lukasz Majewski <l.majewski@majess.pl>
S: Maintained
T: git git://git.denx.de/u-boot-dfu.git
F: drivers/dfu/
@@ -273,7 +271,7 @@
F: lib/libfdt/
F: include/fdt*
F: include/libfdt*
-F. common/cmd_fdt.c
+F: cmd/fdt.c
F: common/fdt_support.c
FREEBSD
@@ -368,6 +366,12 @@
T: git git://git.denx.de/u-boot-ppc4xx.git
F: arch/powerpc/cpu/ppc4xx/
+POWER
+M: Jaehoon Chung <jh80.chung@samsung.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-pmic.git
+F: drivers/power/
+
NETWORK
M: Joe Hershberger <joe.hershberger@ni.com>
S: Maintained
@@ -394,8 +398,8 @@
F: arch/nios2/
ONENAND
-M: Lukasz Majewski <l.majewski@samsung.com>
-S: Maintained
+#M: Lukasz Majewski <l.majewski@majess.pl>
+S: Orphaned (Since 2017-01)
T: git git://git.denx.de/u-boot-onenand.git
F: drivers/mtd/onenand/
@@ -417,7 +421,7 @@
F: arch/sparc/
SPI
-M: Jagan Teki <jteki@openedev.com>
+M: Jagan Teki <jagan@openedev.com>
S: Maintained
T: git git://git.denx.de/u-boot-spi.git
F: drivers/mtd/spi/
diff --git a/Makefile b/Makefile
index 1cf15ce..262df7c 100644
--- a/Makefile
+++ b/Makefile
@@ -2,8 +2,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-VERSION = 2016
-PATCHLEVEL = 09
+VERSION = 2017
+PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION =
NAME =
@@ -527,6 +527,15 @@
endif
endif
+# These are set by the arch-specific config.mk. Make sure they are exported
+# so they can be used when building an EFI application.
+export EFI_LDS # Filename of EFI link script in arch/$(ARCH)/lib
+export EFI_CRT0 # Filename of EFI CRT0 in arch/$(ARCH)/lib
+export EFI_RELOC # Filename of EFU relocation code in arch/$(ARCH)/lib
+export CFLAGS_EFI # Compiler flags to add when building EFI app
+export CFLAGS_NON_EFI # Compiler flags to remove when building EFI app
+export EFI_TARGET # binutils target if EFI is natively supported
+
# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
# that (or fail if absent). Otherwise, search for a linker script in a
# standard location.
@@ -655,6 +664,7 @@
libs-y += drivers/spi/
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/serial/
libs-y += drivers/usb/dwc3/
@@ -740,7 +750,7 @@
endif
# Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg binary_size_check
+ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check
ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
@@ -753,7 +763,11 @@
endif
endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
+ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy)
+ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
+else
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
+endif
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb
ifeq ($(CONFIG_SPL_FRAMEWORK),y)
@@ -799,9 +813,11 @@
quiet_cmd_efipayload = OBJCOPY $@
cmd_efipayload = $(OBJCOPY) -I binary -O $(EFIPAYLOAD_BFDTARGET) -B $(EFIPAYLOAD_BFDARCH) $< $@
+MKIMAGEOUTPUT ?= /dev/null
+
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+ $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
quiet_cmd_cat = CAT $@
cmd_cat = cat $(filter-out $(PHONY), $^) > $@
@@ -811,6 +827,8 @@
quiet_cmd_pad_cat = CAT $@
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
+cfg: u-boot.cfg
+
all: $(ALL-y)
ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo "===================== WARNING ======================"
@@ -819,6 +837,11 @@
@echo "before sending patches to the mailing list."
@echo "===================================================="
endif
+ @# Check that this build does not use CONFIG options that we do not
+ @# know about unless they are in Kconfig. All the existing CONFIG
+ @# options are whitelisted, so new ones should not be added.
+ $(srctree)/scripts/check-config.sh u-boot.cfg \
+ $(srctree)/scripts/config_whitelist.txt ${srctree} 1>&2
PHONY += dtbs
dtbs: dts/dt.dtb
@@ -843,6 +866,12 @@
%.imx: %.bin
$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+%.vyb: %.imx
+ $(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
+
+quiet_cmd_copy = COPY $@
+ cmd_copy = cp $< $@
+
u-boot.dtb: dts/dt.dtb
$(call cmd,copy)
@@ -880,6 +909,12 @@
$(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS)
$(BOARD_SIZE_CHECK)
+# binman
+# ---------------------------------------------------------------------------
+quiet_cmd_binman = BINMAN $@
+cmd_binman = $(srctree)/tools/binman/binman -d u-boot.dtb -O . \
+ -I . -I $(srctree)/board/$(BOARDDIR) $<
+
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
@@ -909,6 +944,11 @@
MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
+MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
+u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
+CLEAN_FILES += u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log
endif
MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
@@ -922,7 +962,7 @@
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
-u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl: \
+u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
$(call if_changed,mkimage)
@@ -935,9 +975,6 @@
u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
-u-boot.cfg: include/config.h FORCE
- $(call if_changed,cpp_cfg)
-
ifdef CONFIG_TPL
SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
else
@@ -1027,50 +1064,11 @@
# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
-# the middle.
+# the middle. This is handled by binman based on an image description in the
+# board's device tree.
ifneq ($(CONFIG_X86_RESET_VECTOR),)
rom: u-boot.rom FORCE
-IFDTOOL=$(objtree)/tools/ifdtool
-IFDTOOL_FLAGS = -f 0:$(objtree)/u-boot.dtb
-IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
-IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-nodtb.bin
-IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
-IFDTOOL_FLAGS += -C
-
-ifneq ($(CONFIG_HAVE_INTEL_ME),)
-IFDTOOL_ME_FLAGS = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin
-IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
-endif
-
-ifneq ($(CONFIG_HAVE_MRC),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
-endif
-
-ifneq ($(CONFIG_HAVE_FSP),)
-IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
-endif
-
-ifneq ($(CONFIG_HAVE_CMC),)
-IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
-endif
-
-ifneq ($(CONFIG_HAVE_VGA_BIOS),)
-IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
-endif
-
-ifneq ($(CONFIG_HAVE_REFCODE),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_REFCODE_ADDR):refcode.bin
-endif
-
-quiet_cmd_ifdtool = IFDTOOL $@
-cmd_ifdtool = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
-ifneq ($(CONFIG_HAVE_INTEL_ME),)
-cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp;
-endif
-cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
-cmd_ifdtool += mv u-boot.tmp $@
-
refcode.bin: $(srctree)/board/$(BOARDDIR)/refcode.bin FORCE
$(call if_changed,copy)
@@ -1080,18 +1078,16 @@
u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
$(if $(CONFIG_HAVE_REFCODE),refcode.bin)
- $(call if_changed,ifdtool)
+ $(call if_changed,binman)
OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
u-boot-x86-16bit.bin: u-boot FORCE
$(call if_changed,objcopy)
endif
-ifneq ($(CONFIG_SUNXI),)
-OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
- --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
- $(call if_changed,pad_cat)
+ifneq ($(CONFIG_ARCH_SUNXI),)
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
+ $(call if_changed,binman)
endif
ifneq ($(CONFIG_TEGRA),)
@@ -1122,7 +1118,7 @@
cmd_u-boot_payload ?= $(LD) $(LDFLAGS_EFI_PAYLOAD) -o $@ \
-T u-boot-payload.lds arch/x86/cpu/call32.o \
lib/efi/efi.o lib/efi/efi_stub.o u-boot.bin.o \
- $(addprefix arch/$(ARCH)/lib/efi/,$(EFISTUB))
+ $(addprefix arch/$(ARCH)/lib/,$(EFISTUB))
u-boot-payload: u-boot.bin.o u-boot-payload.lds FORCE
$(call if_changed,u-boot_payload)
@@ -1509,6 +1505,7 @@
@echo ' cscope - Generate cscope index'
@echo ' ubootrelease - Output the release version string (use with make -s)'
@echo ' ubootversion - Output the version stored in Makefile (use with make -s)'
+ @echo " cfg - Don't build, just create the .cfg files"
@echo ''
@echo 'Static analysers'
@echo ' checkstack - Generate a list of stack hogs'
diff --git a/README b/README
index a74aa22..51cfd57 100644
--- a/README
+++ b/README
@@ -127,7 +127,7 @@
Examples:
U-Boot v2009.11 - Release November 2009
U-Boot v2009.11.1 - Release 1 in version November 2009 stable tree
- U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
+ U-Boot v2010.09-rc1 - Release candidate 1 for September 2010 release
Directory Hierarchy:
@@ -325,27 +325,6 @@
- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
Define exactly one, e.g. CONFIG_ATSTK1002
-- CPU Module Type: (if CONFIG_COGENT is defined)
- Define exactly one of
- CONFIG_CMA286_60_OLD
---- FIXME --- not tested yet:
- CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P,
- CONFIG_CMA287_23, CONFIG_CMA287_50
-
-- Motherboard Type: (if CONFIG_COGENT is defined)
- Define exactly one of
- CONFIG_CMA101, CONFIG_CMA102
-
-- Motherboard I/O Modules: (if CONFIG_COGENT is defined)
- Define one or more of
- CONFIG_CMA302
-
-- Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
- Define one or more of
- CONFIG_LCD_HEARTBEAT - update a character position on
- the LCD display every second with
- a "rotator" |\-/|\-/
-
- Marvell Family Member
CONFIG_SYS_MVFS - define it if you want to enable
multiple fs option at one time
@@ -397,15 +376,6 @@
Defines the string to utilize when trying to match PCIe device
tree nodes for the given platform.
- CONFIG_SYS_PPC_E500_DEBUG_TLB
-
- Enables a temporary TLB entry to be used during boot to work
- around limitations in e500v1 and e500v2 external debugger
- support. This reduces the portions of the boot code where
- breakpoints and single stepping do not work. The value of this
- symbol should be set to the TLB1 entry to be used for this
- purpose.
-
CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set,
@@ -578,20 +548,6 @@
CONFIG_SYS_FSL_SEC_LE
Defines the SEC controller register space as Little Endian
-- Intel Monahans options:
- CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
-
- Defines the Monahans run mode to oscillator
- ratio. Valid values are 8, 16, 24, 31. The core
- frequency is this value multiplied by 13 MHz.
-
- CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
-
- Defines the Monahans turbo mode to oscillator
- ratio. Valid values are 1 (default if undefined) and
- 2. The core frequency as calculated above is multiplied
- by this value.
-
- MIPS CPU options:
CONFIG_SYS_INIT_SP_OFFSET
@@ -730,11 +686,6 @@
This causes ft_system_setup() to be called before booting
the kernel.
- CONFIG_OF_BOOT_CPU
-
- This define fills in the correct boot CPU in the boot
- param header, the default value is zero if undefined.
-
CONFIG_OF_IDE_FIXUP
U-Boot can detect if an IDE device is present or not.
@@ -810,59 +761,6 @@
port routines must be defined elsewhere
(i.e. serial_init(), serial_getc(), ...)
- CONFIG_CFB_CONSOLE
- Enables console device for a color framebuffer. Needs following
- defines (cf. smiLynxEM, i8042)
- VIDEO_FB_LITTLE_ENDIAN graphic memory organisation
- (default big endian)
- VIDEO_HW_RECTFILL graphic chip supports
- rectangle fill
- (cf. smiLynxEM)
- VIDEO_HW_BITBLT graphic chip supports
- bit-blit (cf. smiLynxEM)
- VIDEO_VISIBLE_COLS visible pixel columns
- (cols=pitch)
- VIDEO_VISIBLE_ROWS visible pixel rows
- VIDEO_PIXEL_SIZE bytes per pixel
- VIDEO_DATA_FORMAT graphic data format
- (0-5, cf. cfb_console.c)
- VIDEO_FB_ADRS framebuffer address
- VIDEO_KBD_INIT_FCT keyboard int fct
- (i.e. rx51_kp_init())
- VIDEO_TSTC_FCT test char fct
- (i.e. rx51_kp_tstc)
- VIDEO_GETC_FCT get char fct
- (i.e. rx51_kp_getc)
- CONFIG_VIDEO_LOGO display Linux logo in
- upper left corner
- CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of
- linux_logo.h for logo.
- Requires CONFIG_VIDEO_LOGO
- CONFIG_CONSOLE_EXTRA_INFO
- additional board info beside
- the logo
- CONFIG_HIDE_LOGO_VERSION
- do not display bootloader
- version string
-
- When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
- a limited number of ANSI escape sequences (cursor control,
- erase functions and limited graphics rendition control).
-
- When CONFIG_CFB_CONSOLE is defined, video console is
- default i/o. Serial console can be forced with
- environment 'console=serial'.
-
- When CONFIG_SILENT_CONSOLE is defined, all console
- messages (by U-Boot and Linux!) can be silenced with
- the "silent" environment variable. See
- doc/README.silent for more information.
-
- CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
- is 0x00.
- CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
- is 0xa0.
-
- Console Baudrate:
CONFIG_BAUDRATE - in bps
Select one of the baudrates listed in
@@ -877,23 +775,6 @@
must be defined, to setup the maximum idle timeout for
the SMC.
-- Pre-Console Buffer:
- Prior to the console being initialised (i.e. serial UART
- initialised etc) all console output is silently discarded.
- Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
- buffer any console messages prior to the console being
- initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
- bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
- a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
- bytes are output before the console is initialised, the
- earlier bytes are discarded.
-
- Note that when printing the buffer a copy is made on the
- stack so CONFIG_PRE_CON_BUF_SZ must fit on the stack.
-
- 'Sane' compilers will generate smaller code if
- CONFIG_PRE_CON_BUF_SZ is a power of 2
-
- Autoboot Command:
CONFIG_BOOTCOMMAND
Only needed when CONFIG_BOOTDELAY is enabled;
@@ -1343,10 +1224,6 @@
CONFIG_LAN91C96
Support for SMSC's LAN91C96 chips.
- CONFIG_LAN91C96_BASE
- Define this to hold the physical address
- of the LAN91C96's I/O space
-
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
@@ -1411,7 +1288,7 @@
- PWM Support:
CONFIG_PWM_IMX
- Support for PWM modul on the imx6.
+ Support for PWM module on the imx6.
- TPM Support:
CONFIG_TPM
@@ -1531,10 +1408,6 @@
Derive USB clock from external clock "blah"
- CONFIG_SYS_USB_EXTC_CLK 0x02
- CONFIG_SYS_USB_BRG_CLK 0xBLAH
- Derive USB clock from brgclk
- - CONFIG_SYS_USB_BRG_CLK 0x04
-
If you have a USB-IF assigned VendorID then you may wish to
define your own vendor specific values either in BoardName.h
or directly in usbd_vendor_info.h. If you don't define
@@ -1687,26 +1560,23 @@
to generate and write the Backup GUID Partition Table.)
This occurs when the specified "partition name" on the
"fastboot flash" command line matches this value.
- Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
+ The default is "gpt" if undefined.
+
+ CONFIG_FASTBOOT_MBR_NAME
+ The fastboot "flash" command supports writing the downloaded
+ image to DOS MBR.
+ This occurs when the "partition name" specified on the
+ "fastboot flash" command line matches this value.
+ If not defined the default value "mbr" is used.
- Journaling Flash filesystem support:
- CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
- CONFIG_JFFS2_NAND_DEV
+ CONFIG_JFFS2_NAND
Define these for a default partition on a NAND device
CONFIG_SYS_JFFS2_FIRST_SECTOR,
CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
Define these for a default partition on a NOR device
- CONFIG_SYS_JFFS_CUSTOM_PART
- Define this to create an own partition. You have to provide a
- function struct part_info* jffs2_part_info(int part_num)
-
- If you define only one JFFS2 partition you may also want to
- #define CONFIG_SYS_JFFS_SINGLE_PART 1
- to disable the command chpart. This is the default when you
- have not defined a custom partition
-
- FAT(File Allocation Table) filesystem write function support:
CONFIG_FAT_WRITE
@@ -1716,7 +1586,7 @@
This will also enable the command "fatwrite" enabling the
user to write files to FAT.
-CBFS (Coreboot Filesystem) support
+- CBFS (Coreboot Filesystem) support:
CONFIG_CMD_CBFS
Define this to enable support for reading from a Coreboot
@@ -1741,45 +1611,6 @@
instead.
- Video support:
- CONFIG_VIDEO
-
- Define this to enable video support (for output to
- video).
-
- CONFIG_VIDEO_CT69000
-
- Enable Chips & Technologies 69000 Video chip
-
- CONFIG_VIDEO_SMI_LYNXEM
- Enable Silicon Motion SMI 712/710/810 Video chip. The
- video output is selected via environment 'videoout'
- (1 = LCD and 2 = CRT). If videoout is undefined, CRT is
- assumed.
-
- For the CT69000 and SMI_LYNXEM drivers, videomode is
- selected via environment 'videomode'. Two different ways
- are possible:
- - "videomode=num" 'num' is a standard LiLo mode numbers.
- Following standard modes are supported (* is default):
-
- Colors 640x480 800x600 1024x768 1152x864 1280x1024
- -------------+---------------------------------------------
- 8 bits | 0x301* 0x303 0x305 0x161 0x307
- 15 bits | 0x310 0x313 0x316 0x162 0x319
- 16 bits | 0x311 0x314 0x317 0x163 0x31A
- 24 bits | 0x312 0x315 0x318 ? 0x31B
- -------------+---------------------------------------------
- (i.e. setenv videomode 317; saveenv; reset;)
-
- - "videomode=bootargs" all the video parameters are parsed
- from the bootargs. (See drivers/video/videomodes.c)
-
-
- CONFIG_VIDEO_SED13806
- Enable Epson SED13806 driver. This driver supports 8bpp
- and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
- or CONFIG_VIDEO_SED13806_16BPP
-
CONFIG_FSL_DIU_FB
Enable the Freescale DIU video driver. Reference boards for
SOCs that have a DIU should define this macro to enable DIU
@@ -1859,12 +1690,6 @@
here, since it is cheaper to change data cache settings on
a per-section basis.
- CONFIG_CONSOLE_SCROLL_LINES
-
- When the console need to be scrolled, this is the number of
- lines to scroll by. It defaults to 1. Increasing this makes
- the console jump but can help speed up operation when scrolling
- is slow.
CONFIG_LCD_ROTATION
@@ -2337,8 +2162,6 @@
- CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
- CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
- CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
- - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
- - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
- CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
- drivers/i2c/omap24xx_i2c.c
@@ -2392,10 +2215,7 @@
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
- Hold the number of i2c buses you want to use. If you
- don't use/have i2c muxes on your i2c bus, this
- is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
- omit this define.
+ Hold the number of i2c buses you want to use.
CONFIG_SYS_I2C_DIRECT_BUS
define this, if you don't use i2c muxes on your hardware.
@@ -2609,7 +2429,7 @@
will skip addresses 0x50 and 0x68 on a board with one I2C bus
#define CONFIG_I2C_MULTI_BUS
- #define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
+ #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
@@ -3515,26 +3335,6 @@
CONFIG_SPL_INIT_MINIMAL
Arch init code should be built for a very small image
- CONFIG_SPL_LIBCOMMON_SUPPORT
- Support for common/libcommon.o in SPL binary
-
- CONFIG_SPL_LIBDISK_SUPPORT
- Support for disk/libdisk.o in SPL binary
-
- CONFIG_SPL_I2C_SUPPORT
- Support for drivers/i2c/libi2c.o in SPL binary
-
- CONFIG_SPL_GPIO_SUPPORT
- Support for drivers/gpio/libgpio.o in SPL binary
-
- CONFIG_SPL_MMC_SUPPORT
- Support for drivers/mmc/libmmc.o in SPL binary
-
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
- CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
- Address and partition on the MMC to load U-Boot from
- when the MMC is being used in raw mode.
-
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
Partition on the MMC to load U-Boot from when the MMC is being
used in raw mode
@@ -3553,12 +3353,6 @@
Partition on the MMC to load U-Boot from when the MMC is being
used in fs mode
- CONFIG_SPL_FAT_SUPPORT
- Support for fs/fat/libfat.o in SPL binary
-
- CONFIG_SPL_EXT_SUPPORT
- Support for EXT filesystem in SPL binary
-
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
Filename to read to load U-Boot when reading from filesystem
@@ -3597,18 +3391,10 @@
Support for a lightweight UBI (fastmap) scanner and
loader
- CONFIG_SPL_MTD_SUPPORT
- Support for the MTD subsystem within SPL. Useful for
- environment on NAND support within SPL.
-
CONFIG_SPL_NAND_RAW_ONLY
Support to boot only raw u-boot.bin images. Use this only
if you need to save space.
- CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
- Set for the SPL on PPC mpc8xxx targets, support for
- drivers/ddr/fsl/libddr.o in SPL binary.
-
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in
SPL binary.
@@ -3644,29 +3430,9 @@
Support for an OMAP3-specific set of functions to return the
ID and MFR of the first attached NAND chip, if present.
- CONFIG_SPL_SERIAL_SUPPORT
- Support for drivers/serial/libserial.o in SPL binary
-
- CONFIG_SPL_SPI_FLASH_SUPPORT
- Support for drivers/mtd/spi/libspi_flash.o in SPL binary
-
- CONFIG_SPL_SPI_SUPPORT
- Support for drivers/spi/libspi.o in SPL binary
-
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
- CONFIG_SPL_LIBGENERIC_SUPPORT
- Support for lib/libgeneric.o in SPL binary
-
- CONFIG_SPL_ENV_SUPPORT
- Support for the environment operating in SPL binary
-
- CONFIG_SPL_NET_SUPPORT
- Support for the net/libnet.o in SPL binary.
- It conflicts with SPL env from storage medium specified by
- CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
-
CONFIG_SPL_PAD_TO
Image offset to which the SPL should be padded before appending
the SPL payload. By default, this is defined as
@@ -3753,21 +3519,6 @@
- CONFIG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
-- CONFIG_SYS_CONSOLE_INFO_QUIET
- Suppress display of console information at boot.
-
-- CONFIG_SYS_CONSOLE_IS_IN_ENV
- If the board specific function
- extern int overwrite_console (void);
- returns 1, the stdin, stderr and stdout are switched to the
- serial port, else the settings in the environment are used.
-
-- CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
- Enable the call to overwrite_console().
-
-- CONFIG_SYS_CONSOLE_ENV_OVERWRITE
- Enable overwrite of previous console environment settings.
-
- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
Begin and End addresses of the area used by the
simple memory test.
@@ -3815,10 +3566,6 @@
- CONFIG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
-- CONFIG_SYS_MBIO_BASE:
- Physical start address of Motherboard I/O (if using a
- Cogent motherboard)
-
- CONFIG_SYS_FLASH_BASE:
Physical start address of Flash memory.
@@ -4250,7 +3997,7 @@
This setting describes a second storage area of CONFIG_ENV_SIZE
size used to hold a redundant copy of the environment data, so
that there is a valid backup copy in case there is a power failure
- during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
+ during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
aligned to an erase sector boundary.
- CONFIG_ENV_SPI_BUS (optional):
@@ -4301,7 +4048,7 @@
This setting describes a second storage area of CONFIG_ENV_SIZE
size used to hold a redundant copy of the environment data, so
that there is a valid backup copy in case there is a power failure
- during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
+ during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
aligned to an erase block boundary.
- CONFIG_ENV_RANGE (optional):
@@ -4360,7 +4107,7 @@
Define this to a string that is the name of the block device.
- - FAT_ENV_DEV_AND_PART:
+ - FAT_ENV_DEVICE_AND_PART:
Define this to a string to specify the partition of the device. It can
be as following:
@@ -4602,7 +4349,7 @@
CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
data is located at the end of the available space
(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
- CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
+ GENERATED_GBL_DATA_SIZE), and the initial stack is just
below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_GBL_DATA_OFFSET) downward.
@@ -4661,11 +4408,6 @@
enable SPI microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [SCC4]
-- CONFIG_SYS_USE_OSCCLK:
- Use OSCM clock mode on MBX8xx board. Be careful,
- wrong setting might damage your board. Read
- doc/README.MBX before setting this variable!
-
- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
Offset of the bootmode word in DPRAM used by post
(Power On Self Tests). This definition overrides
@@ -4848,12 +4590,6 @@
addressable memory. This option causes some memory accesses
to be mapped through map_sysmem() / unmap_sysmem().
-- CONFIG_USE_ARCH_MEMCPY
- CONFIG_USE_ARCH_MEMSET
- If these options are used a optimized version of memcpy/memset will
- be used if available. These functions may be faster under some
- conditions but may increase the binary size.
-
- CONFIG_X86_RESET_VECTOR
If defined, the x86 reset vector code is included. This is not
needed when U-Boot is running from Coreboot.
@@ -4909,10 +4645,6 @@
Specifies that QE/FMAN firmware is located on the primary SD/MMC
device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
-- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
- Specifies that QE/FMAN firmware is located on the primary SPI
- device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
-
- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Specifies that QE/FMAN firmware is located in the remote (master)
memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
@@ -4931,34 +4663,12 @@
- CONFIG_FSL_MC_ENET
Enable the MC driver for Layerscape SoCs.
-- CONFIG_SYS_LS_MC_FW_ADDR
- The address in the storage device where the firmware is located. The
- meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro
- is also specified.
-
-- CONFIG_SYS_LS_MC_FW_LENGTH
- The maximum possible size of the firmware. The firmware binary format
- has a field that specifies the actual size of the firmware, but it
- might not be possible to read any part of the firmware unless some
- local storage is allocated to hold the entire firmware first.
-
-- CONFIG_SYS_LS_MC_FW_IN_NOR
- Specifies that MC firmware is located in NOR flash, mapped as
- normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the
- virtual address in NOR flash.
-
Freescale Layerscape Debug Server Support:
-------------------------------------------
The Freescale Layerscape Debug Server Support supports the loading of
"Debug Server firmware" and triggering SP boot-rom.
This firmware often needs to be loaded during U-Boot booting.
-- CONFIG_FSL_DEBUG_SERVER
- Enable the Debug Server for Layerscape SoCs.
-
-- CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
- Define minimum DDR size required for debug server image
-
- CONFIG_SYS_MC_RSV_MEM_ALIGN
Define alignment of reserved memory MC requires
diff --git a/README.version b/README.version
index 712376b..b737c0c 100644
--- a/README.version
+++ b/README.version
@@ -1,5 +1,5 @@
-URL: ftp://ftp.denx.de/pub/u-boot/u-boot-2016.09.tar.bz2
-Version: 2016.09
+URL: ftp://ftp.denx.de/pub/u-boot/u-boot-2017.01.tar.bz2
+Version: 2017.01
License: GPLv2
License File: Licenses/README
BugComponent: 164615
diff --git a/api/api_storage.c b/api/api_storage.c
index d425a9a..bd43144 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -37,11 +37,11 @@
int max_dev;
int enum_started;
int enum_ended;
- int type; /* "external" type: DT_STOR_{IDE,USB,etc} */
+ int type; /* "external" type: DT_STOR_{IDE,USB,etc} */
char *name;
};
-static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
+static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
void dev_stor_init(void)
@@ -105,6 +105,10 @@
struct blk_desc *dd;
+ /* Wasn't configured for this type, return 0 directly */
+ if (specs[type].name == NULL)
+ return 0;
+
if (first) {
di->cookie = (void *)blk_get_dev(specs[type].name, 0);
if (di->cookie == NULL)
@@ -112,8 +116,10 @@
else
found = 1;
- /* provide hint if there are more devices in
- * this group to enumerate */
+ /*
+ * provide hint if there are more devices in
+ * this group to enumerate
+ */
if (1 < specs[type].max_dev)
*more = 1;
@@ -121,8 +127,10 @@
for (i = 0; i < specs[type].max_dev; i++)
if (di->cookie ==
(void *)blk_get_dev(specs[type].name, i)) {
- /* previous cookie found -- advance to the
- * next device, if possible */
+ /*
+ * previous cookie found -- advance to the
+ * next device, if possible
+ */
if (++i >= specs[type].max_dev) {
/* out of range, no more to enum */
@@ -137,8 +145,10 @@
else
found = 1;
- /* provide hint if there are more devices in
- * this group to enumerate */
+ /*
+ * provide hint if there are more devices in
+ * this group to enumerate
+ */
if ((i + 1) < specs[type].max_dev)
*more = 1;
@@ -167,9 +177,8 @@
}
-/*
- * returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc
- */
+/* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */
+
static int dev_stor_type(struct blk_desc *dd)
{
int i, j;
@@ -183,9 +192,8 @@
}
-/*
- * returns: 0/1 whether cookie points to some device in this group
- */
+/* returns: 0/1 whether cookie points to some device in this group */
+
static int dev_is_stor(int type, struct device_info *di)
{
return (dev_stor_type(di->cookie) == type) ? 1 : 0;
@@ -216,7 +224,6 @@
*/
if (di->cookie == NULL) {
-
debugf("group%d - enum restart\n", type);
/*
@@ -227,7 +234,6 @@
specs[type].enum_started = 1;
} else if (dev_is_stor(type, di)) {
-
debugf("group%d - enum continued for the next device\n", type);
if (specs[type].enum_ended) {
@@ -239,7 +245,6 @@
found = dev_stor_get(type, 0, &more, di);
} else {
-
if (specs[type].enum_ended) {
debugf("group %d - already enumerated, skipping\n", type);
return 0;
@@ -251,7 +256,7 @@
/*
* 2b. If enumerating devices in this group did not
* happen before, it means the cookie pointed to a
- * device frome some other group (another storage
+ * device from some other group (another storage
* group, or network); in this case try to take the
* first available device from our group
*/
@@ -278,7 +283,7 @@
if (found)
debugf("device found, returning cookie 0x%08x\n",
- (u_int32_t)di->cookie);
+ (u_int32_t)di->cookie);
else
debugf("no device found\n");
@@ -299,9 +304,7 @@
{
int i;
- /*
- * check: ide, usb, scsi, mmc
- */
+ /* check: ide, usb, scsi, mmc */
for (i = ENUM_IDE; i < ENUM_MAX; i ++) {
if (dev_enum_stor(i, di))
return 1;
diff --git a/arch/Kconfig b/arch/Kconfig
index d718a68..ffc7b45 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -62,6 +62,7 @@
bool "Sandbox"
select SUPPORT_OF_CONTROL
select DM
+ select DM_KEYBOARD
select DM_SPI_FLASH
select DM_SERIAL
select DM_I2C
@@ -83,6 +84,7 @@
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
select DM
+ select DM_KEYBOARD
select DM_SERIAL
select DM_GPIO
select DM_SPI
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index 7c974f0..13676bd 100644
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -31,15 +31,15 @@
endif
ifdef CONFIG_CPU_ARC750D
-PLATFORM_CPPFLAGS += -marc700
+PLATFORM_CPPFLAGS += -mcpu=arc700
endif
ifdef CONFIG_CPU_ARC770D
-PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
+PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
endif
ifdef CONFIG_CPU_ARCEM6
-PLATFORM_CPPFLAGS += -marcem
+PLATFORM_CPPFLAGS += -mcpu=arcem
endif
ifdef CONFIG_CPU_ARCHS34
diff --git a/arch/arc/include/asm/errno.h b/arch/arc/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/arc/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
index 04d9d9c..5798149 100644
--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -37,6 +37,11 @@
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
}
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
static int cleanup_before_linux(void)
{
disable_interrupts();
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e63309a..0ed36cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -126,6 +126,35 @@
ARM_SOC_BOOT0_HOOK which contains the required assembler
preprocessor code.
+config USE_ARCH_MEMCPY
+ bool "Use an assembly optimized implementation of memcpy"
+ default y if CPU_V7
+ depends on !ARM64
+ help
+ Enable the generation of an optimized version of memcpy.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
+config USE_ARCH_MEMSET
+ bool "Use an assembly optimized implementation of memset"
+ default y if CPU_V7
+ depends on !ARM64
+ help
+ Enable the generation of an optimized version of memset.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
+config ARCH_OMAP2
+ bool
+ select CPU_V7
+ select SUPPORT_SPL
+
+config ARM64_SUPPORT_AARCH32
+ bool "ARM64 system support AArch32 execution state"
+ default y if ARM64 && !TARGET_THUNDERX_88XX
+ help
+ This ARM64 system supports AArch32 execution state.
+
choice
prompt "Target select"
default TARGET_HIKEY
@@ -137,14 +166,6 @@
bool "Support edb93xx"
select CPU_ARM920T
-config TARGET_VCMA9
- bool "Support VCMA9"
- select CPU_ARM920T
-
-config TARGET_SMDK2410
- bool "Support smdk2410"
- select CPU_ARM920T
-
config TARGET_ASPENITE
bool "Support aspenite"
select CPU_ARM926EJS
@@ -164,9 +185,7 @@
select CPU_ARM926EJS
config ARCH_MVEBU
- bool "Marvell MVEBU family (Armada XP/375/38x)"
- select CPU_V7
- select SUPPORT_SPL
+ bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
select OF_CONTROL
select OF_SEPARATE
select DM
@@ -174,10 +193,6 @@
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
- select SPL_DM
- select SPL_DM_SEQ_ALIAS
- select SPL_OF_CONTROL
- select SPL_SIMPLE_BUS
config TARGET_DEVKIT3250
bool "Support devkit3250"
@@ -316,6 +331,7 @@
select DM
select DM_SERIAL
select DM_GPIO
+ select OF_CONTROL
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
@@ -333,159 +349,61 @@
config TARGET_BRXRE1
bool "Support BRXRE1"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
config TARGET_BRPPT1
bool "Support BRPPT1"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_CM_T335
- bool "Support cm_t335"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_PEPPER
- bool "Support pepper"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_AM335X_IGEP0033
- bool "Support am335x_igep0033"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_PCM051
- bool "Support pcm051"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_GPIO
+ select ARCH_OMAP2
config TARGET_DRACO
bool "Support draco"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_THUBAN
bool "Support thuban"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_RASTABAN
bool "Support rastaban"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_ETAMIN
bool "Support etamin"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_PXM2
bool "Support pxm2"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_RUT
bool "Support rut"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
select DM
select DM_SERIAL
select DM_GPIO
-config TARGET_PENGWYN
- bool "Support pengwyn"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_AM335X_BALTOS
- bool "Support am335x_baltos"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_AM335X_EVM
- bool "Support am335x_evm"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_GPIO
- select TI_I2C_BOARD_DETECT
-
-config TARGET_AM335X_SHC
- bool "Support am335x based shc board from bosch"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_AM335X_SL50
- bool "Support am335x_sl50"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_GPIO
- select DM_SERIAL
-
-config TARGET_BAV335X
- bool "Support bav335x"
- select CPU_V7
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- help
- The BAV335x OEM Network Processor integrates all the functions of an
- embedded network computer in a small, easy to use SODIMM module which
- incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
- processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
- ethernet with simple connection to external connectors.
-
- For more information, visit: http://birdland.com/oem
-
config TARGET_TI814X_EVM
bool "Support ti814x_evm"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
config TARGET_TI816X_EVM
bool "Support ti816x_evm"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
config TARGET_BCM23550_W1D
bool "Support bcm23550_w1d"
@@ -506,6 +424,7 @@
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select DM
+ select DM_I2C
select DM_SPI_FLASH
select DM_SERIAL
select DM_SPI
@@ -518,6 +437,7 @@
select DM
select DM_SERIAL
select DM_GPIO
+ select DM_I2C
config ARCH_HIGHBANK
bool "Calxeda Highbank"
@@ -544,10 +464,16 @@
config ARCH_MX7
bool "Freescale MX7"
select CPU_V7
+ select SYS_FSL_HAS_SEC if SECURE_BOOT
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
config ARCH_MX6
bool "Freescale MX6"
select CPU_V7
+ select SYS_FSL_HAS_SEC if SECURE_BOOT
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
config ARCH_MX5
bool "Freescale MX5"
@@ -580,25 +506,21 @@
config OMAP34XX
bool "OMAP34XX SoC"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
select USE_TINY_PRINTF
config OMAP44XX
bool "OMAP44XX SoC"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
select USE_TINY_PRINTF
config OMAP54XX
bool "OMAP54XX SoC"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
config AM43XX
bool "AM43XX SoC"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
help
Support for AM43xx SOC from Texas Instruments.
The AM43xx high performance SOC features a Cortex-A9
@@ -606,6 +528,16 @@
protocols, dual camera support, optional 3D graphics
and an optional customer programmable secure boot.
+config AM33XX
+ bool "AM33XX SoC"
+ select ARCH_OMAP2
+ help
+ Support for AM335x SOC from Texas Instruments.
+ The AM335x high performance SOC features a Cortex-A8
+ ARM core, a dual core PRU-ICSS for industrial Ethernet
+ protocols, optional 3D graphics and an optional customer
+ programmable secure boot.
+
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
select DM
@@ -614,6 +546,7 @@
config TARGET_S32V234EVB
bool "Support s32v234evb"
select ARM64
+ select SYS_FSL_ERRATUM_ESDHC111
config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
@@ -634,49 +567,67 @@
select DM
select DM_SPI_FLASH
select DM_SPI
+ select ENABLE_ARM_SOC_BOOT0_HOOK
config TARGET_CM_T43
bool "Support cm_t43"
- select CPU_V7
- select SUPPORT_SPL
+ select ARCH_OMAP2
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
select CMD_GPIO
select CMD_MMC if MMC
- select CMD_USB
+ select CMD_USB if DISTRO_DEFAULTS
select DM
select DM_ETH
select DM_GPIO
select DM_KEYBOARD
select DM_SERIAL
- select DM_USB
+ select DM_USB if DISTRO_DEFAULTS
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
select SPL_STACK_R if SUPPORT_SPL
select SPL_SYS_MALLOC_SIMPLE if SUPPORT_SPL
select SYS_NS16550
- select USB
- select USB_STORAGE
- select USB_KEYBOARD
+ select USB if DISTRO_DEFAULTS
+ select USB_STORAGE if DISTRO_DEFAULTS
+ select USB_KEYBOARD if DISTRO_DEFAULTS
select USE_TINY_PRINTF
+config TARGET_TS4600
+ bool "Support TS4600"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC_A001
config TARGET_VF610TWR
bool "Support vf610twr"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_COLIBRI_VF
bool "Support Colibri VF50/61"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_PCM052
bool "Support pcm-052"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC135
+ select SYS_FSL_ERRATUM_ESDHC_A001
+
+config TARGET_BK4R1
+ bool "Support BK4r1"
+ select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC135
+ select SYS_FSL_ERRATUM_ESDHC_A001
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
@@ -735,6 +686,7 @@
config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
+ select ARCH_LS2080A
select ARM64
select ARMV8_MULTIENTRY
help
@@ -745,6 +697,7 @@
config TARGET_LS2080A_SIMU
bool "Support ls2080a_simu"
+ select ARCH_LS2080A
select ARM64
select ARMV8_MULTIENTRY
help
@@ -755,6 +708,7 @@
config TARGET_LS2080AQDS
bool "Support ls2080aqds"
+ select ARCH_LS2080A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
@@ -766,6 +720,7 @@
config TARGET_LS2080ARDB
bool "Support ls2080ardb"
+ select ARCH_LS2080A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
@@ -788,6 +743,7 @@
config TARGET_LS1012AQDS
bool "Support ls1012aqds"
+ select ARCH_LS1012A
select ARM64
help
Support for Freescale LS1012AQDS platform.
@@ -797,6 +753,7 @@
config TARGET_LS1012ARDB
bool "Support ls1012ardb"
+ select ARCH_LS1012A
select ARM64
help
Support for Freescale LS1012ARDB platform.
@@ -806,6 +763,7 @@
config TARGET_LS1012AFRDM
bool "Support ls1012afrdm"
+ select ARCH_LS1012A
select ARM64
help
Support for Freescale LS1012AFRDM platform.
@@ -816,17 +774,41 @@
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select SUPPORT_SPL
+ select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
+ select LS1_DEEP_SLEEP
+ select SYS_FSL_DDR
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select SUPPORT_SPL
+ select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
+ select LS1_DEEP_SLEEP
+
+config TARGET_LS1021AIOT
+ bool "Support ls1021aiot"
+ select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select SUPPORT_SPL
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ help
+ Support for Freescale LS1021AIOT platform.
+ The LS1021A Freescale board (IOT) is a high-performance
+ development platform that supports the QorIQ LS1021A
+ Layerscape Architecture processor.
config TARGET_LS1043AQDS
bool "Support ls1043aqds"
+ select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
@@ -835,12 +817,39 @@
config TARGET_LS1043ARDB
bool "Support ls1043ardb"
+ select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
Support for Freescale LS1043ARDB platform.
+config TARGET_LS1046AQDS
+ bool "Support ls1046aqds"
+ select ARCH_LS1046A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
+ select DM_SPI_FLASH if DM_SPI
+ help
+ Support for Freescale LS1046AQDS platform.
+ The LS1046A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
+config TARGET_LS1046ARDB
+ bool "Support ls1046ardb"
+ select ARCH_LS1046A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
+ select DM_SPI_FLASH if DM_SPI
+ help
+ Support for Freescale LS1046ARDB platform.
+ The LS1046A Reference Design Board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -856,17 +865,23 @@
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select CLK_UNIPHIER
- select SUPPORT_SPL
- select SPL
- select OF_CONTROL
- select SPL_OF_CONTROL
- select OF_LIBFDT
select DM
- select SPL_DM
select DM_GPIO
- select DM_SERIAL
select DM_I2C
select DM_MMC
+ select DM_RESET
+ select DM_SERIAL
+ select DM_USB
+ select OF_CONTROL
+ select OF_LIBFDT
+ select PINCTRL
+ select SPL
+ select SPL_DM
+ select SPL_LIBCOMMON_SUPPORT
+ select SPL_LIBGENERIC_SUPPORT
+ select SPL_OF_CONTROL
+ select SPL_PINCTRL
+ select SUPPORT_SPL
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
@@ -892,6 +907,9 @@
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select DM_USB if USB
+ select DM_PWM
+ select DM_REGULATOR
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
@@ -917,15 +935,21 @@
source "arch/arm/mach-kirkwood/Kconfig"
+source "arch/arm/mach-litesom/Kconfig"
+
source "arch/arm/mach-mvebu/Kconfig"
+source "arch/arm/cpu/armv7/ls102xa/Kconfig"
+
source "arch/arm/cpu/armv7/mx7/Kconfig"
source "arch/arm/cpu/armv7/mx6/Kconfig"
source "arch/arm/cpu/armv7/mx5/Kconfig"
-source "arch/arm/cpu/armv7/omap-common/Kconfig"
+source "arch/arm/mach-omap2/Kconfig"
+
+source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
@@ -984,7 +1008,10 @@
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1021aiot/Kconfig"
+source "board/freescale/ls1046aqds/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1046ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
@@ -1006,12 +1033,10 @@
source "board/hisilicon/hikey/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/phytec/pcm052/Kconfig"
source "board/ppcag/bg0900/Kconfig"
-source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/siemens/draco/Kconfig"
@@ -1035,6 +1060,7 @@
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
+source "board/technologic/ts4600/Kconfig"
source "board/technologic/ts4800/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 42093c2..4b8bf80 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -58,11 +58,13 @@
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
+machine-$(CONFIG_LITESOM) += litesom
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
+machine-$(CONFIG_ARCH_OMAP2) += omap2
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
@@ -93,7 +95,7 @@
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
libs-y += arch/arm/imx-common/
endif
else
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 8f85862..3a81f13 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -6,13 +6,16 @@
#
ifndef CONFIG_STANDALONE_LOAD_ADDR
-ifneq ($(CONFIG_OMAP_COMMON),)
+ifneq ($(CONFIG_ARCH_OMAP2),)
CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
else
CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
+CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
+CFLAGS_EFI := -fpic -fshort-wchar
+
LDFLAGS_FINAL += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-fno-common -ffixed-r9
@@ -118,7 +121,8 @@
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+ -j .u_boot_list -j .rela.dyn
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
@@ -144,4 +148,11 @@
ALL-y += u-boot.imx
endif
endif
+ifneq ($(CONFIG_VF610),)
+ALL-y += u-boot.vyb
endif
+endif
+
+EFI_LDS := elf_arm_efi.lds
+EFI_CRT0 := crt0_arm_efi.o
+EFI_RELOC := reloc_arm_efi.o
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index 068d93e..5297d62 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <div64.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
diff --git a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
index d358f5f..711ea76 100644
--- a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
+++ b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
@@ -5,7 +5,7 @@
*/
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <linux/types.h>
#include <asm/arch/sys_proto.h>
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index a602d4e..7c00201 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -16,6 +16,7 @@
#include <asm-offsets.h>
#include <config.h>
+#include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
@@ -37,6 +38,11 @@
.globl reset
reset:
+ /* Allow the board to save important registers */
+ b save_boot_params
+.globl save_boot_params_ret
+save_boot_params_ret:
+
/*
* set the cpu to SVC32 mode
*/
@@ -110,3 +116,7 @@
c_runtime_cpu_setup:
mov pc, lr
+
+WEAK(save_boot_params)
+ b save_boot_params_ret /* back to my caller */
+ENDPROC(save_boot_params)
diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c
index b62558f..178422a 100644
--- a/arch/arm/cpu/arm920t/imx/timer.c
+++ b/arch/arm/cpu/arm920t/imx/timer.c
@@ -78,11 +78,7 @@
*/
ulong get_tbclk (void)
{
- ulong tbclk;
-
- tbclk = CONFIG_SYS_HZ;
-
- return tbclk;
+ return CONFIG_SYS_HZ;
}
/*
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 9491096..b552e43 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -11,7 +11,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c
index 2e6be06..585fa8a 100644
--- a/arch/arm/cpu/arm926ejs/mxs/iomux.c
+++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 2298620..840dd9e 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -11,7 +11,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/imx-common/dma.h>
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index eb8669b..d9d1d73 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -40,17 +40,17 @@
;
}
+#if defined(CONFIG_MX23)
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
static const iomux_cfg_t iomux_boot[] = {
-#if defined(CONFIG_MX23)
MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-#endif
};
+#endif
static uint8_t mxs_get_bootmode_index(void)
{
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
index c88e962..89fd54f 100644
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -37,7 +37,7 @@
writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
synth = MISC_GPT3SYNTH;
#else
-# error Incorrect config. Can only be spear{600|300|310|320}
+# error Incorrect config. Can only be SPEAR{600|300|310|320}
#endif
writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 0d4bfbc..0e515a4 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@
obj-y += cpu.o cp15.o
obj-y += syslib.o
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
@@ -23,14 +23,12 @@
obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
-obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
endif
-obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
@@ -39,9 +37,6 @@
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
obj-$(CONFIG_MX7) += mx7/
-obj-$(CONFIG_OMAP34XX) += omap3/
-obj-$(CONFIG_OMAP44XX) += omap4/
-obj-$(CONFIG_OMAP54XX) += omap5/
obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig b/arch/arm/cpu/armv7/am33xx/Kconfig
deleted file mode 100644
index dc51e9b..0000000
--- a/arch/arm/cpu/armv7/am33xx/Kconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-if AM43XX
-config TARGET_AM43XX_EVM
- bool "Support am43xx_evm"
- select TI_I2C_BOARD_DETECT
- help
- This option specifies support for the AM43xx
- GP and HS EVM development platforms.The AM437x
- GP EVM is a standalone test, development, and
- evaluation module system that enables developers
- to write software and develop hardware around
- an AM43xx processor subsystem.
-
-config ISW_ENTRY_ADDR
- hex "Address in memory or XIP flash of bootloader entry point"
- help
- After any reset, the boot ROM on the AM43XX SOC
- searches the boot media for a valid boot image.
- For non-XIP devices, the ROM then copies the
- image into internal memory.
- For all boot modes, after the ROM processes the
- boot image it eventually computes the entry
- point address depending on the device type
- (secure/non-secure), boot media (xip/non-xip) and
- image headers.
- default 0x402F4000
-
-config PUB_ROM_DATA_SIZE
- hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
- help
- During the device boot, the public ROM uses the top of
- the public L3 OCMC RAM to store r/w data like stack,
- heap, globals etc. When the ROM is copying the boot
- image from the boot media into memory, the image must
- not spill over into this area. This value can be used
- during compile time to determine the maximum size of a
- boot image. Once the ROM transfers control to the boot
- image, this area is no longer used, and can be reclaimed
- for run time use by the boot image.
- default 0x8400
-endif
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
deleted file mode 100644
index a99cbf9..0000000
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * board.c
- *
- * Common board functions for AM33XX based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <ns16550.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <asm/errno.h>
-#include <linux/compiler.h>
-#include <linux/usb/ch9.h>
-#include <linux/usb/gadget.h>
-#include <linux/usb/musb.h>
-#include <asm/omap_musb.h>
-#include <asm/davinci_rtc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct ns16550_platdata am33xx_serial[] = {
- { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
-# ifdef CONFIG_SYS_NS16550_COM2
- { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
-# ifdef CONFIG_SYS_NS16550_COM3
- { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
- { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
- { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
- { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
-# endif
-# endif
-};
-
-U_BOOT_DEVICES(am33xx_uarts) = {
- { "ns16550_serial", &am33xx_serial[0] },
-# ifdef CONFIG_SYS_NS16550_COM2
- { "ns16550_serial", &am33xx_serial[1] },
-# ifdef CONFIG_SYS_NS16550_COM3
- { "ns16550_serial", &am33xx_serial[2] },
- { "ns16550_serial", &am33xx_serial[3] },
- { "ns16550_serial", &am33xx_serial[4] },
- { "ns16550_serial", &am33xx_serial[5] },
-# endif
-# endif
-};
-
-#ifdef CONFIG_DM_GPIO
-static const struct omap_gpio_platdata am33xx_gpio[] = {
- { 0, AM33XX_GPIO0_BASE },
- { 1, AM33XX_GPIO1_BASE },
- { 2, AM33XX_GPIO2_BASE },
- { 3, AM33XX_GPIO3_BASE },
-#ifdef CONFIG_AM43XX
- { 4, AM33XX_GPIO4_BASE },
- { 5, AM33XX_GPIO5_BASE },
-#endif
-};
-
-U_BOOT_DEVICES(am33xx_gpios) = {
- { "gpio_omap", &am33xx_gpio[0] },
- { "gpio_omap", &am33xx_gpio[1] },
- { "gpio_omap", &am33xx_gpio[2] },
- { "gpio_omap", &am33xx_gpio[3] },
-#ifdef CONFIG_AM43XX
- { "gpio_omap", &am33xx_gpio[4] },
- { "gpio_omap", &am33xx_gpio[5] },
-#endif
-};
-#endif
-#endif
-
-#ifndef CONFIG_DM_GPIO
-static const struct gpio_bank gpio_bank_am33xx[] = {
- { (void *)AM33XX_GPIO0_BASE },
- { (void *)AM33XX_GPIO1_BASE },
- { (void *)AM33XX_GPIO2_BASE },
- { (void *)AM33XX_GPIO3_BASE },
-#ifdef CONFIG_AM43XX
- { (void *)AM33XX_GPIO4_BASE },
- { (void *)AM33XX_GPIO5_BASE },
-#endif
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
-#endif
-
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int cpu_mmc_init(bd_t *bis)
-{
- int ret;
-
- ret = omap_mmc_init(0, 0, 0, -1, -1);
- if (ret)
- return ret;
-
- return omap_mmc_init(1, 0, 0, -1, -1);
-}
-#endif
-
-/* AM33XX has two MUSB controllers which can be host or gadget */
-#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
- (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/* USB 2.0 PHY Control */
-#define CM_PHY_PWRDN (1 << 0)
-#define CM_PHY_OTG_PWRDN (1 << 1)
-#define OTGVDET_EN (1 << 19)
-#define OTGSESSENDEN (1 << 20)
-
-static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
-{
- if (on) {
- clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
- OTGVDET_EN | OTGSESSENDEN);
- } else {
- clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
- }
-}
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12,
-};
-
-#ifdef CONFIG_AM335X_USB0
-static void am33xx_otg0_set_phy_power(u8 on)
-{
- am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
-}
-
-struct omap_musb_board_data otg0_board_data = {
- .set_phy_power = am33xx_otg0_set_phy_power,
-};
-
-static struct musb_hdrc_platform_data otg0_plat = {
- .mode = CONFIG_AM335X_USB0_MODE,
- .config = &musb_config,
- .power = 50,
- .platform_ops = &musb_dsps_ops,
- .board_data = &otg0_board_data,
-};
-#endif
-
-#ifdef CONFIG_AM335X_USB1
-static void am33xx_otg1_set_phy_power(u8 on)
-{
- am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
-}
-
-struct omap_musb_board_data otg1_board_data = {
- .set_phy_power = am33xx_otg1_set_phy_power,
-};
-
-static struct musb_hdrc_platform_data otg1_plat = {
- .mode = CONFIG_AM335X_USB1_MODE,
- .config = &musb_config,
- .power = 50,
- .platform_ops = &musb_dsps_ops,
- .board_data = &otg1_board_data,
-};
-#endif
-#endif
-
-int arch_misc_init(void)
-{
-#ifdef CONFIG_AM335X_USB0
- musb_register(&otg0_plat, &otg0_board_data,
- (void *)USB0_OTG_BASE);
-#endif
-#ifdef CONFIG_AM335X_USB1
- musb_register(&otg1_plat, &otg1_board_data,
- (void *)USB1_OTG_BASE);
-#endif
- return 0;
-}
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-/*
- * In the case of non-SPL based booting we'll want to call these
- * functions a tiny bit later as it will require gd to be set and cleared
- * and that's not true in s_init in this case so we cannot do it there.
- */
-int board_early_init_f(void)
-{
- prcm_init();
- set_mux_conf_regs();
-
- return 0;
-}
-
-/*
- * This function is the place to do per-board things such as ramp up the
- * MPU clock frequency.
- */
-__weak void am33xx_spl_board_init(void)
-{
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
-static void rtc32k_enable(void)
-{
- struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
-
- /*
- * Unlock the RTC's registers. For more details please see the
- * RTC_SS section of the TRM. In order to unlock we need to
- * write these specific values (keys) in this order.
- */
- writel(RTC_KICK0R_WE, &rtc->kick0r);
- writel(RTC_KICK1R_WE, &rtc->kick1r);
-
- /* Enable the RTC 32K OSC by setting bits 3 and 6. */
- writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-#endif
-
-static void uart_soft_reset(void)
-{
- struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
- u32 regval;
-
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_RESET;
- writel(regval, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
- ;
-
- /* Disable smart idle */
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_SMART_IDLE_EN;
- writel(regval, &uart_base->uartsyscfg);
-}
-
-static void watchdog_disable(void)
-{
- struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
-}
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
-{
- board_early_init_f();
- sdram_init();
-}
-#endif
-
-void s_init(void)
-{
- /*
- * The ROM will only have set up sufficient pinmux to allow for the
- * first 4KiB NOR to be read, we must finish doing what we know of
- * the NOR mux in this space in order to continue.
- */
-#ifdef CONFIG_NOR_BOOT
- enable_norboot_pin_mux();
-#endif
- watchdog_disable();
- set_uart_mux_conf();
- setup_clocks_for_console();
- uart_soft_reset();
-#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
- /* Enable RTC32K clock */
- rtc32k_enable();
-#endif
-}
-#endif
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
deleted file mode 100644
index 9b9b78e..0000000
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * clock.c
- *
- * Clock initialization for AM33XX boards.
- * Derived from OMAP4 boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-
-static void setup_post_dividers(const struct dpll_regs *dpll_regs,
- const struct dpll_params *params)
-{
- /* Setup post-dividers */
- if (params->m2 >= 0)
- writel(params->m2, dpll_regs->cm_div_m2_dpll);
- if (params->m3 >= 0)
- writel(params->m3, dpll_regs->cm_div_m3_dpll);
- if (params->m4 >= 0)
- writel(params->m4, dpll_regs->cm_div_m4_dpll);
- if (params->m5 >= 0)
- writel(params->m5, dpll_regs->cm_div_m5_dpll);
- if (params->m6 >= 0)
- writel(params->m6, dpll_regs->cm_div_m6_dpll);
-}
-
-static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
-{
- clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
-{
- if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
- (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
- printf("DPLL locking failed for 0x%x\n",
- dpll_regs->cm_clkmode_dpll);
- hang();
- }
-}
-
-static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
-{
- clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
-{
- if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
- (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
- printf("Bypassing DPLL failed 0x%x\n",
- dpll_regs->cm_clkmode_dpll);
- }
-}
-
-static void bypass_dpll(const struct dpll_regs *dpll_regs)
-{
- do_bypass_dpll(dpll_regs);
- wait_for_bypass(dpll_regs);
-}
-
-void do_setup_dpll(const struct dpll_regs *dpll_regs,
- const struct dpll_params *params)
-{
- u32 temp;
-
- if (!params)
- return;
-
- temp = readl(dpll_regs->cm_clksel_dpll);
-
- bypass_dpll(dpll_regs);
-
- /* Set M & N */
- temp &= ~CM_CLKSEL_DPLL_M_MASK;
- temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
-
- temp &= ~CM_CLKSEL_DPLL_N_MASK;
- temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
-
- writel(temp, dpll_regs->cm_clksel_dpll);
-
- setup_post_dividers(dpll_regs, params);
-
- /* Wait till the DPLL locks */
- do_lock_dpll(dpll_regs);
- wait_for_lock(dpll_regs);
-}
-
-static void setup_dplls(void)
-{
- const struct dpll_params *params;
-
- params = get_dpll_core_params();
- do_setup_dpll(&dpll_core_regs, params);
-
- params = get_dpll_mpu_params();
- do_setup_dpll(&dpll_mpu_regs, params);
-
- params = get_dpll_per_params();
- do_setup_dpll(&dpll_per_regs, params);
- writel(0x300, &cmwkup->clkdcoldodpllper);
-
- params = get_dpll_ddr_params();
- do_setup_dpll(&dpll_ddr_regs, params);
-}
-
-static inline void wait_for_clk_enable(u32 *clkctrl_addr)
-{
- u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
- u32 bound = LDELAY;
-
- while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
- (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
- clkctrl = readl(clkctrl_addr);
- idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
- MODULE_CLKCTRL_IDLEST_SHIFT;
- if (--bound == 0) {
- printf("Clock enable failed for 0x%p idlest 0x%x\n",
- clkctrl_addr, clkctrl);
- return;
- }
- }
-}
-
-static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
- u32 wait_for_enable)
-{
- clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
- enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - %p\n", clkctrl_addr);
- if (wait_for_enable)
- wait_for_clk_enable(clkctrl_addr);
-}
-
-static inline void wait_for_clk_disable(u32 *clkctrl_addr)
-{
- u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
- u32 bound = LDELAY;
-
- while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
- clkctrl = readl(clkctrl_addr);
- idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
- MODULE_CLKCTRL_IDLEST_SHIFT;
- if (--bound == 0) {
- printf("Clock disable failed for 0x%p idlest 0x%x\n",
- clkctrl_addr, clkctrl);
- return;
- }
- }
-}
-static inline void disable_clock_module(u32 *const clkctrl_addr,
- u32 wait_for_disable)
-{
- clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Disable clock module - %p\n", clkctrl_addr);
- if (wait_for_disable)
- wait_for_clk_disable(clkctrl_addr);
-}
-
-static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
-{
- clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
- enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - %p\n", clkctrl_reg);
-}
-
-static inline void disable_clock_domain(u32 *const clkctrl_reg)
-{
- clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Disable clock domain - %p\n", clkctrl_reg);
-}
-
-void do_enable_clocks(u32 *const *clk_domains,
- u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
-{
- u32 i, max = 100;
-
- /* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++) {
- enable_clock_domain(clk_domains[i],
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- }
-
- /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
- enable_clock_module(clk_modules_explicit_en[i],
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
- wait_for_enable);
- };
-}
-
-void do_disable_clocks(u32 *const *clk_domains,
- u32 *const *clk_modules_disable,
- u8 wait_for_disable)
-{
- u32 i, max = 100;
-
-
- /* Clock modules that need to be put in SW_DISABLE */
- for (i = 0; (i < max) && clk_modules_disable[i]; i++)
- disable_clock_module(clk_modules_disable[i],
- wait_for_disable);
-
- /* Put the clock domains in SW_SLEEP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++)
- disable_clock_domain(clk_domains[i]);
-}
-
-/*
- * Before scaling up the clocks we need to have the PMIC scale up the
- * voltages first. This will be dependent on which PMIC is in use
- * and in some cases we may not be scaling things up at all and thus not
- * need to do anything here.
- */
-__weak void scale_vcores(void)
-{
-}
-
-void prcm_init()
-{
- enable_basic_clocks();
- scale_vcores();
- setup_dplls();
- timer_init();
-}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
deleted file mode 100644
index 9b5a47b..0000000
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * clock_ti814x.c
- *
- * Clocks for TI814X based boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/* PRCM */
-#define PRCM_MOD_EN 0x2
-
-/* CLK_SRC */
-#define OSC_SRC0 0
-#define OSC_SRC1 1
-
-#define L3_OSC_SRC OSC_SRC0
-
-#define OSC_0_FREQ 20
-
-#define DCO_HS2_MIN 500
-#define DCO_HS2_MAX 1000
-#define DCO_HS1_MIN 1000
-#define DCO_HS1_MAX 2000
-
-#define SELFREQDCO_HS2 0x00000801
-#define SELFREQDCO_HS1 0x00001001
-
-#define MPU_N 0x1
-#define MPU_M 0x3C
-#define MPU_M2 1
-#define MPU_CLKCTRL 0x1
-
-#define L3_N 19
-#define L3_M 880
-#define L3_M2 4
-#define L3_CLKCTRL 0x801
-
-#define DDR_N 19
-#define DDR_M 666
-#define DDR_M2 2
-#define DDR_CLKCTRL 0x801
-
-/* ADPLLJ register values */
-#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
-#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
-#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
-#define ADPLLJ_CLKCTRL_IDLE (1 << 23)
-#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
-#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
-#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
-#define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
-#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
-#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
-#define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
-#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
- ADPLLJ_CLKCTRL_CLKOUTEN | \
- ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
- ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
-
-#define ADPLLJ_STATUS_PHASELOCK (1 << 10)
-#define ADPLLJ_STATUS_FREQLOCK (1 << 9)
-#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
- ADPLLJ_STATUS_FREQLOCK)
-#define ADPLLJ_STATUS_BYPASSACK (1 << 8)
-#define ADPLLJ_STATUS_BYPASS (1 << 0)
-#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
- ADPLLJ_STATUS_BYPASS)
-
-#define ADPLLJ_TENABLE_ENB (1 << 0)
-#define ADPLLJ_TENABLEDIV_ENB (1 << 0)
-
-#define ADPLLJ_M2NDIV_M2SHIFT 16
-
-#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
-#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
-#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
-
-struct ad_pll {
- unsigned int pwrctrl;
- unsigned int clkctrl;
- unsigned int tenable;
- unsigned int tenablediv;
- unsigned int m2ndiv;
- unsigned int mn2div;
- unsigned int fracdiv;
- unsigned int bwctrl;
- unsigned int fracctrl;
- unsigned int status;
- unsigned int m3div;
- unsigned int rampctrl;
-};
-
-#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
-
-#define ENET_CLKCTRL_CMPL 0x30000
-
-#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
-
-struct sata_pll {
- unsigned int pllcfg0;
- unsigned int pllcfg1;
- unsigned int pllcfg2;
- unsigned int pllcfg3;
- unsigned int pllcfg4;
- unsigned int pllstatus;
- unsigned int rxstatus;
- unsigned int txstatus;
- unsigned int testcfg;
-};
-
-#define SEL_IN_FREQ (0x1 << 31)
-#define DIGCLRZ (0x1 << 30)
-#define ENDIGLDO (0x1 << 4)
-#define APLL_CP_CURR (0x1 << 3)
-#define ENBGSC_REF (0x1 << 2)
-#define ENPLLLDO (0x1 << 1)
-#define ENPLL (0x1 << 0)
-
-#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
-#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
-#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
-#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
- ENPLLLDO | ENPLL)
-
-#define PLL_LOCK (0x1 << 0)
-
-#define ENSATAMODE (0x1 << 31)
-#define PLLREFSEL (0x1 << 30)
-#define MDIVINT (0x4b << 18)
-#define EN_CLKAUX (0x1 << 5)
-#define EN_CLK125M (0x1 << 4)
-#define EN_CLK100M (0x1 << 3)
-#define EN_CLK50M (0x1 << 2)
-
-#define SATA_PLLCFG1 (ENSATAMODE | \
- PLLREFSEL | \
- MDIVINT | \
- EN_CLKAUX | \
- EN_CLK125M | \
- EN_CLK100M | \
- EN_CLK50M)
-
-#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
-#define PLLDO_EN_LDO_STABLE (0x1 << 11)
-#define PLLDO_EN_BUF_CUR (0x1 << 7)
-#define PLLDO_EN_LP (0x1 << 6)
-#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
-
-#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
- PLLDO_EN_LDO_STABLE | \
- PLLDO_EN_BUF_CUR | \
- PLLDO_EN_LP | \
- PLLDO_CTRL_TRIM_1_4V)
-
-const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
-const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
-const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
-
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
-{
- /* HSMMC1 */
- writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
- while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
- ;
-
- /* Ethernet */
- writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
- while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
- ;
- writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
- while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
- ;
-
- /* RTC clocks */
- writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
- while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
- ;
-}
-
-/*
- * select the HS1 or HS2 for DCO Freq
- * return : CLKCTRL
- */
-static u32 pll_dco_freq_sel(u32 clkout_dco)
-{
- if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
- return SELFREQDCO_HS2;
- else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
- return SELFREQDCO_HS1;
- else
- return -1;
-}
-
-/*
- * select the sigma delta config
- * return: sigma delta val
- */
-static u32 pll_sigma_delta_val(u32 clkout_dco)
-{
- u32 sig_val = 0;
-
- sig_val = (clkout_dco + 225) / 250;
- sig_val = sig_val << 24;
-
- return sig_val;
-}
-
-/*
- * configure individual ADPLLJ
- */
-static void pll_config(u32 base, u32 n, u32 m, u32 m2,
- u32 clkctrl_val, int adpllj)
-{
- const struct ad_pll *adpll = (struct ad_pll *)base;
- u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
- u32 sig_val = 0, hs_mod = 0;
-
- m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
- mn2val = m;
-
- /* calculate clkout_dco */
- clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
-
- /* sigma delta & Hs mode selection skip for ADPLLS*/
- if (adpllj) {
- sig_val = pll_sigma_delta_val(clkout_dco);
- hs_mod = pll_dco_freq_sel(clkout_dco);
- }
-
- /* by-pass pll */
- read_clkctrl = readl(&adpll->clkctrl);
- writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
- while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
- != ADPLLJ_STATUS_BYPASSANDACK)
- ;
-
- /* clear TINITZ */
- read_clkctrl = readl(&adpll->clkctrl);
- writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
-
- /*
- * ref_clk = 20/(n + 1);
- * clkout_dco = ref_clk * m;
- * clk_out = clkout_dco/m2;
- */
- read_clkctrl = readl(&adpll->clkctrl) &
- ~(ADPLLJ_CLKCTRL_LPMODE |
- ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
- ADPLLJ_CLKCTRL_REGM4XEN);
- writel(m2nval, &adpll->m2ndiv);
- writel(mn2val, &adpll->mn2div);
-
- /* Skip for modena(ADPLLS) */
- if (adpllj) {
- writel(sig_val, &adpll->fracdiv);
- writel((read_clkctrl | hs_mod), &adpll->clkctrl);
- }
-
- /* Load M2, N2 dividers of ADPLL */
- writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
- writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
-
- /* Load M, N dividers of ADPLL */
- writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
- writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
-
- /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
- read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
- if (adpllj)
- writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
- &adpll->clkctrl);
-
- /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
- read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
- writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
-
- /* Wait for phase and freq lock */
- while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
- ADPLLJ_STATUS_PHSFRQLOCK)
- ;
-}
-
-static void unlock_pll_control_mmr(void)
-{
- /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
- writel(0x1EDA4C3D, 0x481C5040);
- writel(0x2FF1AC2B, 0x48140060);
- writel(0xF757FDC0, 0x48140064);
- writel(0xE2BC3A6D, 0x48140068);
- writel(0x1EBF131D, 0x4814006c);
- writel(0x6F361E05, 0x48140070);
-}
-
-static void mpu_pll_config(void)
-{
- pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
-}
-
-static void l3_pll_config(void)
-{
- u32 l3_osc_src, rd_osc_src = 0;
-
- l3_osc_src = L3_OSC_SRC;
- rd_osc_src = readl(OSC_SRC_CTRL);
-
- if (OSC_SRC0 == l3_osc_src)
- writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
- else
- writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
-
- pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
-}
-
-void ddr_pll_config(unsigned int ddrpll_m)
-{
- pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
-}
-
-void sata_pll_config(void)
-{
- /*
- * This sequence for configuring the SATA PLL
- * resident in the control module is documented
- * in TI8148 TRM section 21.3.1
- */
- writel(SATA_PLLCFG1, &spll->pllcfg1);
- udelay(50);
-
- writel(SATA_PLLCFG3, &spll->pllcfg3);
- udelay(50);
-
- writel(SATA_PLLCFG0_1, &spll->pllcfg0);
- udelay(50);
-
- writel(SATA_PLLCFG0_2, &spll->pllcfg0);
- udelay(50);
-
- writel(SATA_PLLCFG0_3, &spll->pllcfg0);
- udelay(50);
-
- writel(SATA_PLLCFG0_4, &spll->pllcfg0);
- udelay(50);
-
- while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
- ;
-}
-
-void enable_dmm_clocks(void)
-{
- writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
- writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
- writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
- while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
- while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
- ;
- while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
- ;
- writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
- while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
- while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
- ;
-}
-
-void setup_clocks_for_console(void)
-{
- unlock_pll_control_mmr();
- /* UART0 */
- writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
- while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
- ;
-}
-/*
- * Configure the PLL/PRCM for necessary peripherals
- */
-void prcm_init(void)
-{
- /* Enable the control module */
- writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
-
- /* Configure PLLs */
- mpu_pll_config();
- l3_pll_config();
- sata_pll_config();
-
- /* Enable the required peripherals */
- enable_per_clocks();
-}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
deleted file mode 100644
index ace4a5a..0000000
--- a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * clock_ti816x.c
- *
- * Clocks for TI816X based boards
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * Based on TI-PSP-04.00.02.14 :
- *
- * Copyright (C) 2009, Texas Instruments, Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#include <asm/emif.h>
-
-#define CM_PLL_BASE (CTRL_BASE + 0x0400)
-
-/* Main PLL */
-#define MAIN_N 64
-#define MAIN_P 0x1
-#define MAIN_INTFREQ1 0x8
-#define MAIN_FRACFREQ1 0x800000
-#define MAIN_MDIV1 0x2
-#define MAIN_INTFREQ2 0xE
-#define MAIN_FRACFREQ2 0x0
-#define MAIN_MDIV2 0x1
-#define MAIN_INTFREQ3 0x8
-#define MAIN_FRACFREQ3 0xAAAAB0
-#define MAIN_MDIV3 0x3
-#define MAIN_INTFREQ4 0x9
-#define MAIN_FRACFREQ4 0x55554F
-#define MAIN_MDIV4 0x3
-#define MAIN_INTFREQ5 0x9
-#define MAIN_FRACFREQ5 0x374BC6
-#define MAIN_MDIV5 0xC
-#define MAIN_MDIV6 0x48
-#define MAIN_MDIV7 0x4
-
-/* DDR PLL */
-#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */
-#define DDR_N 59
-#define DDR_P 0x1
-#define DDR_MDIV1 0x4
-#define DDR_INTFREQ2 0x8
-#define DDR_FRACFREQ2 0xD99999
-#define DDR_MDIV2 0x1E
-#define DDR_INTFREQ3 0x8
-#define DDR_FRACFREQ3 0x0
-#define DDR_MDIV3 0x4
-#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4 0x0
-#define DDR_MDIV4 0x4
-#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5 0x0
-#define DDR_MDIV5 0x4
-#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */
-#define DDR_N 59
-#define DDR_P 0x1
-#define DDR_MDIV1 0x3
-#define DDR_INTFREQ2 0x8
-#define DDR_FRACFREQ2 0xD99999
-#define DDR_MDIV2 0x1E
-#define DDR_INTFREQ3 0x8
-#define DDR_FRACFREQ3 0x0
-#define DDR_MDIV3 0x4
-#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4 0x0
-#define DDR_MDIV4 0x4
-#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5 0x0
-#define DDR_MDIV5 0x4
-#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */
-#define DDR_N 50
-#define DDR_P 0x1
-#define DDR_MDIV1 0x2
-#define DDR_INTFREQ2 0x9
-#define DDR_FRACFREQ2 0x0
-#define DDR_MDIV2 0x19
-#define DDR_INTFREQ3 0x13
-#define DDR_FRACFREQ3 0x800000
-#define DDR_MDIV3 0x2
-#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4 0x0
-#define DDR_MDIV4 0x4
-#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5 0x0
-#define DDR_MDIV5 0x4
-#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */
-#define DDR_N 59
-#define DDR_P 0x1
-#define DDR_MDIV1 0x2
-#define DDR_INTFREQ2 0x8
-#define DDR_FRACFREQ2 0xD99999
-#define DDR_MDIV2 0x1E
-#define DDR_INTFREQ3 0x8
-#define DDR_FRACFREQ3 0x0
-#define DDR_MDIV3 0x4
-#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ4 0x0
-#define DDR_MDIV4 0x4
-#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
-#define DDR_FRACFREQ5 0x0
-#define DDR_MDIV5 0x4
-#endif
-
-#define CONTROL_STATUS (CTRL_BASE + 0x40)
-#define DDR_RCD (CTRL_BASE + 0x070C)
-#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390)
-#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420)
-#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628)
-
-#define INTCPS_SYSCONFIG 0x48200010
-#define CM_SYSCLK10_CLKSEL 0x48180324
-
-struct cm_pll {
- unsigned int mainpll_ctrl; /* offset 0x400 */
- unsigned int mainpll_pwd;
- unsigned int mainpll_freq1;
- unsigned int mainpll_div1;
- unsigned int mainpll_freq2;
- unsigned int mainpll_div2;
- unsigned int mainpll_freq3;
- unsigned int mainpll_div3;
- unsigned int mainpll_freq4;
- unsigned int mainpll_div4;
- unsigned int mainpll_freq5;
- unsigned int mainpll_div5;
- unsigned int resv0[1];
- unsigned int mainpll_div6;
- unsigned int resv1[1];
- unsigned int mainpll_div7;
- unsigned int ddrpll_ctrl; /* offset 0x440 */
- unsigned int ddrpll_pwd;
- unsigned int resv2[1];
- unsigned int ddrpll_div1;
- unsigned int ddrpll_freq2;
- unsigned int ddrpll_div2;
- unsigned int ddrpll_freq3;
- unsigned int ddrpll_div3;
- unsigned int ddrpll_freq4;
- unsigned int ddrpll_div4;
- unsigned int ddrpll_freq5;
- unsigned int ddrpll_div5;
- unsigned int videopll_ctrl; /* offset 0x470 */
- unsigned int videopll_pwd;
- unsigned int videopll_freq1;
- unsigned int videopll_div1;
- unsigned int videopll_freq2;
- unsigned int videopll_div2;
- unsigned int videopll_freq3;
- unsigned int videopll_div3;
- unsigned int resv3[4];
- unsigned int audiopll_ctrl; /* offset 0x4A0 */
- unsigned int audiopll_pwd;
- unsigned int resv4[2];
- unsigned int audiopll_freq2;
- unsigned int audiopll_div2;
- unsigned int audiopll_freq3;
- unsigned int audiopll_div3;
- unsigned int audiopll_freq4;
- unsigned int audiopll_div4;
- unsigned int audiopll_freq5;
- unsigned int audiopll_div5;
-};
-
-const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
-const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
-const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
-const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
-void enable_dmm_clocks(void)
-{
- writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
- writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
- writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
-
- /* Wait for clocks to be active */
- while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
- ;
- /* Wait for emif0 to be fully functional, including OCP */
- while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
- ;
- /* Wait for emif1 to be fully functional, including OCP */
- while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
- ;
-
- writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
- /* Wait for dmm to be fully functional, including OCP */
- while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
- ;
-
- /* Enable Tiled Access */
- writel(0x80000000, DMM_PAT_BASE_ADDR);
-}
-
-/* assume delay is aprox at least 1us */
-static void ddr_delay(int d)
-{
- int i;
-
- /*
- * read a control register.
- * this is a bit more delay and cannot be optimized by the compiler
- * assuming one read takes 200 cycles and A8 is runing 1 GHz
- * somewhat conservative setting
- */
- for (i = 0; i < 50*d; i++)
- readl(CONTROL_STATUS);
-}
-
-static void main_pll_init_ti816x(void)
-{
- u32 main_pll_ctrl = 0;
-
- /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFFFFFFFB;
- main_pll_ctrl |= BIT(2);
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
- /* Enable PLL by setting BIT3 in its ctrl reg */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFFFFFFF7;
- main_pll_ctrl |= BIT(3);
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
- /* Write the values of N,P in the CTRL reg */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFF;
- main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-
- /* Power up clock1-7 */
- writel(0x0, &cmpll->mainpll_pwd);
-
- /* Program the freq and divider values for clock1-7 */
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
- &cmpll->mainpll_freq1);
- writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
- &cmpll->mainpll_freq2);
- writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
- &cmpll->mainpll_freq3);
- writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
- &cmpll->mainpll_freq4);
- writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
-
- writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
- &cmpll->mainpll_freq5);
- writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
-
- writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
-
- writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
-
- /* Wait for PLL to lock */
- while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
- ;
-
- /* Put the PLL in normal mode, disable bypass */
- main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
- main_pll_ctrl &= 0xFFFFFFFB;
- writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
-}
-
-static void ddr_pll_bypass_ti816x(void)
-{
- u32 ddr_pll_ctrl = 0;
-
- /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
- ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
- ddr_pll_ctrl &= 0xFFFFFFFB;
- ddr_pll_ctrl |= BIT(2);
- writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-}
-
-static void ddr_pll_init_ti816x(void)
-{
- u32 ddr_pll_ctrl = 0;
- /* Enable PLL by setting BIT3 in its ctrl reg */
- ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
- ddr_pll_ctrl &= 0xFFFFFFF7;
- ddr_pll_ctrl |= BIT(3);
- writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
- /* Write the values of N,P in the CTRL reg */
- ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
- ddr_pll_ctrl &= 0xFF;
- ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
- writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
-
- ddr_delay(10);
-
- /* Power up clock1-5 */
- writel(0x0, &cmpll->ddrpll_pwd);
-
- /* Program the freq and divider values for clock1-3 */
- writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
- ddr_delay(1);
- writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
- writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
- &cmpll->ddrpll_freq2);
- writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
- writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
- ddr_delay(1);
- writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
- ddr_delay(1);
- writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
- &cmpll->ddrpll_freq3);
- ddr_delay(1);
- writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
- &cmpll->ddrpll_freq3);
-
- ddr_delay(5);
-
- /* Wait for PLL to lock */
- while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
- ;
-
- /* Power up RCD */
- writel(BIT(0), DDR_RCD);
-}
-
-static void peripheral_enable(void)
-{
- /* Wake-up the l3_slow clock */
- writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
-
- /*
- * Note on Timers:
- * There are 8 timers(0-7) out of which timer 0 is a secure timer.
- * Timer 0 mux should not be changed
- *
- * To access the timer registers we need the to be
- * enabled which is what we do in the first step
- */
-
- /* Enable timer1 */
- writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
- /* Select timer1 clock to be CLKIN (27MHz) */
- writel(BIT(1), CM_TIMER1_CLKSEL);
-
- /* Wait for timer1 to be ON-ACTIVE */
- while (((readl(&cmalwon->l3slowclkstctrl)
- & (0x80000<<1))>>20) != 1)
- ;
- /* Wait for timer1 to be enabled */
- while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
- ;
- /* Active posted mode */
- writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
- while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
- ;
- /* Start timer1 */
- writel(BIT(0), (DM_TIMER1_BASE + 0x38));
-
- /* eFuse */
- writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
- while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
- ;
-
- /* Enable gpio0 */
- writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
- while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
- ;
- writel((BIT(8)), &cmalwon->gpio0clkctrl);
-
- /* Enable spi */
- writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
- while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
- ;
-
- /* Enable i2c0 */
- writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
- while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
- ;
-
- /* Enable ethernet0 */
- writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
-
- /* Enable hsmmc */
- writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
- while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
- ;
-}
-
-void setup_clocks_for_console(void)
-{
- /* Fix ROM code bug - from TI-PSP-04.00.02.14 */
- writel(0x0, CM_SYSCLK10_CLKSEL);
-
- ddr_pll_bypass_ti816x();
-
- /* Enable uart0-2 */
- writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
- while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
- while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
- while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
- ;
- while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
- ;
-}
-
-void prcm_init(void)
-{
- /* Enable the control */
- writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
-
- main_pll_init_ti816x();
- ddr_pll_init_ti816x();
-
- /*
- * With clk freqs setup to desired values,
- * enable the required peripherals
- */
- peripheral_enable();
-}
diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
deleted file mode 100644
index d4eb21c..0000000
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
-
-ifdef CONFIG_SPL_BUILD
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-#
-# For booting from SPI use
-# u-boot-spl_HS_SPI_X-LOADER to program flash
-#
-# For booting spl from all other media
-# use u-boot-spl_HS_ISSW
-#
-# Refer to README.ti-secure for more info
-#
-ALL-y += u-boot-spl_HS_ISSW
-ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
-else
-ALL-y += MLO
-ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
-endif
-else
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
-ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img
-endif
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
deleted file mode 100644
index 6acf30c..0000000
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * DDR Configuration for AM33xx devices.
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-
-/**
- * Base address for EMIF instances
- */
-static struct emif_reg_struct *emif_reg[2] = {
- (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
- (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
-
-/**
- * Base addresses for DDR PHY cmd/data regs
- */
-static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
- (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
- (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
-
-static struct ddr_data_regs *ddr_data_reg[2] = {
- (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
- (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
-
-/**
- * Base address for ddr io control instances
- */
-static struct ddr_cmdtctrl *ioctrl_reg = {
- (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
-
-static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
-{
- u32 mr;
-
- mr_addr |= cs << EMIF_REG_CS_SHIFT;
- writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
-
- mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
- debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
- if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
- ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
- ((mr & 0xff000000) >> 24) == (mr & 0xff))
- return mr & 0xff;
- else
- return mr;
-}
-
-static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
-{
- mr_addr |= cs << EMIF_REG_CS_SHIFT;
- writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
- writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
-}
-
-static void configure_mr(int nr, u32 cs)
-{
- u32 mr_addr;
-
- while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
- ;
- set_mr(nr, cs, LPDDR2_MR10, 0x56);
-
- set_mr(nr, cs, LPDDR2_MR1, 0x43);
- set_mr(nr, cs, LPDDR2_MR2, 0x2);
-
- mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(nr, cs, mr_addr, 0x2);
-}
-
-/*
- * Configure EMIF4D5 registers and MR registers For details about these magic
- * values please see the EMIF registers section of the TRM.
- */
-void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
-{
- writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
- writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
- writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
-
- writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
- writel(regs->emif_rd_wr_lvl_rmp_win,
- &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
- writel(regs->emif_rd_wr_lvl_rmp_ctl,
- &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
- writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
- writel(regs->emif_rd_wr_exec_thresh,
- &emif_reg[nr]->emif_rd_wr_exec_thresh);
-
- /*
- * for most SOCs these registers won't need to be changed so only
- * write to these registers if someone explicitly has set the
- * register's value.
- */
- if(regs->emif_cos_config) {
- writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
- writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
- writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
- writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
- }
-
- /*
- * Sequence to ensure that the PHY is in a known state prior to
- * startting hardware leveling. Also acts as to latch some state from
- * the EMIF into the PHY.
- */
- writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
- writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
- writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
-
- clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
- EMIF_REG_INITREF_DIS_MASK);
-
- writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
- writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
-
- /* Wait 1ms because of L3 timeout error */
- udelay(1000);
-
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
-
- /* Perform hardware leveling for DDR3 */
- if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
- writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
- 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
- writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
- 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
-
- writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
-
- /* Enable read leveling */
- writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
-
- /*
- * Enable full read and write leveling. Wait for read and write
- * leveling bit to clear RDWRLVLFULL_START bit 31
- */
- while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
- != 0)
- ;
-
- /* Check the timeout register to see if leveling is complete */
- if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
- puts("DDR3 H/W leveling incomplete with errors\n");
-
- } else {
- /* DDR2 */
- configure_mr(nr, 0);
- configure_mr(nr, 1);
- }
-}
-
-/**
- * Configure SDRAM
- */
-void config_sdram(const struct emif_regs *regs, int nr)
-{
- if (regs->zq_config) {
- writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
- writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
- writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
-
- /* Trigger initialization */
- writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
- /* Wait 1ms because of L3 timeout error */
- udelay(1000);
-
- /* Write proper sdram_ref_cref_ctrl value */
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
- }
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
- writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
-}
-
-/**
- * Set SDRAM timings
- */
-void set_sdram_timings(const struct emif_regs *regs, int nr)
-{
- writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
- writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
- writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
- writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
- writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
- writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
-}
-
-/*
- * Configure EXT PHY registers for software leveling
- */
-static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
-{
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- __maybe_unused const u32 *ext_phy_ctrl_const_regs;
- u32 i = 0;
- __maybe_unused u32 size;
-
- ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base =
- (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
-#ifdef CONFIG_AM43XX
- /*
- * External phy 6-24 registers do not change with ddr frequency.
- * These only need to be set on DDR2 on AM43xx.
- */
- emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
-
- if (!size)
- return;
-
- for (i = 0; i < size; i++) {
- writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
- }
-#endif
-}
-
-/*
- * Configure EXT PHY registers for hardware leveling
- */
-static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
-{
- /*
- * Enable hardware leveling on the EMIF. For details about these
- * magic values please see the EMIF registers section of the TRM.
- */
- writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
- writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
- writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
- writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
- writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
- writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
- writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
- writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
- writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
- writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
- writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
- writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
-
- /*
- * Sequence to ensure that the PHY is again in a known state after
- * hardware leveling.
- */
- writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
- writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
- writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
-}
-
-/**
- * Configure DDR PHY
- */
-void config_ddr_phy(const struct emif_regs *regs, int nr)
-{
- /*
- * Disable initialization and refreshes for now until we finish
- * programming EMIF regs and set time between rising edge of
- * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
- * We currently hardcode a value based on a max expected frequency
- * of 400MHz.
- */
- writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
- &emif_reg[nr]->emif_sdram_ref_ctrl);
-
- writel(regs->emif_ddr_phy_ctlr_1,
- &emif_reg[nr]->emif_ddr_phy_ctrl_1);
- writel(regs->emif_ddr_phy_ctlr_1,
- &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
-
- if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
- if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
- ext_phy_settings_hwlvl(regs, nr);
- else
- ext_phy_settings_swlvl(regs, nr);
- }
-}
-
-/**
- * Configure DDR CMD control registers
- */
-void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
-{
- if (!cmd)
- return;
-
- writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
- writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
-
- writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
- writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
-
- writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
- writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
-}
-
-/**
- * Configure DDR DATA registers
- */
-void config_ddr_data(const struct ddr_data *data, int nr)
-{
- int i;
-
- if (!data)
- return;
-
- for (i = 0; i < DDR_DATA_REGS_NR; i++) {
- writel(data->datardsratio0,
- &(ddr_data_reg[nr]+i)->dt0rdsratio0);
- writel(data->datawdsratio0,
- &(ddr_data_reg[nr]+i)->dt0wdsratio0);
- writel(data->datawiratio0,
- &(ddr_data_reg[nr]+i)->dt0wiratio0);
- writel(data->datagiratio0,
- &(ddr_data_reg[nr]+i)->dt0giratio0);
- writel(data->datafwsratio0,
- &(ddr_data_reg[nr]+i)->dt0fwsratio0);
- writel(data->datawrsratio0,
- &(ddr_data_reg[nr]+i)->dt0wrsratio0);
- }
-}
-
-void config_io_ctrl(const struct ctrl_ioregs *ioregs)
-{
- if (!ioregs)
- return;
-
- writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
- writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
- writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
- writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
- writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
-#ifdef CONFIG_AM43XX
- writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
- writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
- writel(ioregs->emif_sdram_config_ext,
- &ioctrl_reg->emif_sdram_config_ext);
-#endif
-}
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
deleted file mode 100644
index 52a6824..0000000
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * sys_info.c
- *
- * System information functions
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <power/tps65910.h>
-#include <linux/compiler.h>
-
-struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
-
-/**
- * get_cpu_rev(void) - extract rev info
- */
-u32 get_cpu_rev(void)
-{
- u32 id;
- u32 rev;
-
- id = readl(DEVICE_ID);
- rev = (id >> 28) & 0xff;
-
- return rev;
-}
-
-/**
- * get_cpu_type(void) - extract cpu info
- */
-u32 get_cpu_type(void)
-{
- u32 id = 0;
- u32 partnum;
-
- id = readl(DEVICE_ID);
- partnum = (id >> 12) & 0xffff;
-
- return partnum;
-}
-
-/**
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
- int mode;
- mode = readl(&cstat->statusreg) & (DEVICE_MASK);
- return mode >>= 8;
-}
-
-/**
- * get_sysboot_value(void) - return SYS_BOOT[4:0]
- */
-u32 get_sysboot_value(void)
-{
- int mode;
- mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
- return mode;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-static char *cpu_revs[] = {
- "1.0",
- "2.0",
- "2.1"};
-
-
-static char *dev_types[] = {
- "TST",
- "EMU",
- "HS",
- "GP"};
-
-/**
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
- char *cpu_s, *sec_s, *rev_s;
-
- switch (get_cpu_type()) {
- case AM335X:
- cpu_s = "AM335X";
- break;
- case TI81XX:
- cpu_s = "TI81XX";
- break;
- default:
- cpu_s = "Unknown CPU type";
- break;
- }
-
- if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
- rev_s = cpu_revs[get_cpu_rev()];
- else
- rev_s = "?";
-
- if (get_device_type() < ARRAY_SIZE(dev_types))
- sec_s = dev_types[get_device_type()];
- else
- sec_s = "?";
-
- printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_AM33XX
-int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
-{
- int sil_rev;
-
- sil_rev = readl(&cdev->deviceid) >> 28;
-
- if (sil_rev == 1)
- /* PG 2.0, efuse may not be set. */
- return MPUPLL_M_800;
- else if (sil_rev >= 2) {
- /* Check what the efuse says our max speed is. */
- int efuse_arm_mpu_max_freq;
- efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
- switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
- case AM335X_ZCZ_1000:
- return MPUPLL_M_1000;
- case AM335X_ZCZ_800:
- return MPUPLL_M_800;
- case AM335X_ZCZ_720:
- return MPUPLL_M_720;
- case AM335X_ZCZ_600:
- case AM335X_ZCE_600:
- return MPUPLL_M_600;
- case AM335X_ZCZ_300:
- case AM335X_ZCE_300:
- return MPUPLL_M_300;
- }
- }
-
- /* PG 1.0 or otherwise unknown, use the PG1.0 max */
- return MPUPLL_M_720;
-}
-
-int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
-{
- /* For PG2.1 and later, we have one set of values. */
- if (sil_rev >= 2) {
- switch (frequency) {
- case MPUPLL_M_1000:
- return TPS65910_OP_REG_SEL_1_3_2_5;
- case MPUPLL_M_800:
- return TPS65910_OP_REG_SEL_1_2_6;
- case MPUPLL_M_720:
- return TPS65910_OP_REG_SEL_1_2_0;
- case MPUPLL_M_600:
- case MPUPLL_M_300:
- return TPS65910_OP_REG_SEL_1_1_3;
- }
- }
-
- /* Default to PG1.0/PG2.0 values. */
- return TPS65910_OP_REG_SEL_1_1_3;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index 0588e2b..30915d2 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
#include <div64.h>
+#include <bootstage.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -17,7 +18,6 @@
gd->arch.tbu = 0;
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
-
return 0;
}
@@ -39,6 +39,11 @@
return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
}
+ulong timer_get_boot_us(void)
+{
+ return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
+}
+
void __udelay(unsigned long usec)
{
unsigned long long endtime;
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
index 80187e3..490bc4c 100644
--- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
@@ -12,7 +12,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
index d263068..4a1cc71 100644
--- a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
index a326dfe..79fafa0 100644
--- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
@@ -12,7 +12,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <bitfield.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
index b0b92b9..f188ef0 100644
--- a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
index b2ce6d6..456b767 100644
--- a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
index 1d7c5af..908502d 100644
--- a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
@@ -5,7 +5,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
index 7e25255..1c28551 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
@@ -12,7 +12,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
index ba55d0a..06a7ce8 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c
index d442583..cdc1264 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c
@@ -12,7 +12,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <bitfield.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c
index b0b92b9..f188ef0 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
index 49badcb..bf47672 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
index 1d7c5af..908502d 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
@@ -5,7 +5,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include "clk-core.h"
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index 1872c57..658934d 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -19,7 +19,11 @@
/*
* Setup a temporary stack. Global data is not available yet.
*/
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+ ldr sp, =CONFIG_SPL_STACK
+#else
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
+#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#ifdef CONFIG_SPL_DM
mov r9, #0
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
new file mode 100644
index 0000000..9ffb90e
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -0,0 +1,62 @@
+config ARCH_LS1021A
+ bool
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A008407
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+ select SYS_FSL_DDR_BE if SYS_FSL_DDR
+ select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+ select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
+ select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
+
+menu "LS102xA architecture"
+ depends on ARCH_LS1021A
+
+config LS1_DEEP_SLEEP
+ bool "Deep sleep"
+ depends on ARCH_LS1021A
+
+config MAX_CPUS
+ int "Maximum number of CPUs permitted for LS102xA"
+ depends on ARCH_LS1021A
+ default 2
+ help
+ Set this number to the maximum number of possible CPUs in the SoC.
+ SoCs may have multiple clusters with each cluster may have multiple
+ ports. If some ports are reserved but higher ports are used for
+ cores, count the reserved ports. This will allocate enough memory
+ in spin table to properly handle all cores.
+
+config SECURE_BOOT
+ bool "Secure Boot"
+ help
+ Enable Freescale Secure Boot feature. Normally selected
+ by defconfig. If unsure, do not change.
+
+config SYS_FSL_ERRATUM_A010315
+ bool "Workaround for PCIe erratum A010315"
+
+config SYS_FSL_SRDS_1
+ bool
+
+config SYS_FSL_SRDS_2
+ bool
+
+config SYS_HAS_SERDES
+ bool
+
+config SYS_FSL_IFC_BANK_COUNT
+ int "Maximum banks of Integrated flash controller"
+ depends on ARCH_LS1021A
+ default 8
+
+config SYS_FSL_ERRATUM_A008407
+ bool
+
+endmenu
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
index 0228300..f8300c7 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -16,5 +16,5 @@
obj-$(CONFIG_SPL) += spl.o
ifdef CONFIG_ARMV7_PSCI
-obj-y += psci.o
+obj-y += psci.o ls102xa_psci.o
endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
index 6212640..b4de523 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
@@ -9,6 +9,163 @@
#include "fsl_epu.h"
+struct fsm_reg_vals epu_default_val[] = {
+ /* EPGCR (Event Processor Global Control Register) */
+ {EPGCR, 0},
+ /* EPECR (Event Processor Event Control Registers) */
+ {EPECR0 + EPECR_STRIDE * 0, 0},
+ {EPECR0 + EPECR_STRIDE * 1, 0},
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+ {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
+ {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
+ {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
+ {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
+ {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
+ {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
+ {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
+ {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
+ {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
+ /*
+ * EPEVTCR (Event Processor EVT Pin Control Registers)
+ * SCU8 triger EVT2, and SCU11 triger EVT9
+ */
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
+ /* EPCMPR (Event Processor Counter Compare Registers) */
+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
+ /* EPCCR (Event Processor Counter Control Registers) */
+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
+ {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
+ {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
+ {EPCCR0 + EPCCR_STRIDE * 7, 0},
+ {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 13, 0},
+ {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
+ {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
+ /* EPSMCR (Event Processor SCU Mux Control Registers) */
+ {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
+ {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
+ {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
+ {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
+ {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
+ {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
+ {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
+ {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
+ {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
+ {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
+ {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
+ {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
+ /* EPACR (Event Processor Action Control Registers) */
+ {EPACR0 + EPACR_STRIDE * 0, 0},
+ {EPACR0 + EPACR_STRIDE * 1, 0},
+ {EPACR0 + EPACR_STRIDE * 2, 0},
+ {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
+ {EPACR0 + EPACR_STRIDE * 4, 0},
+ {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
+ {EPACR0 + EPACR_STRIDE * 6, 0},
+ {EPACR0 + EPACR_STRIDE * 7, 0},
+ {EPACR0 + EPACR_STRIDE * 8, 0},
+ {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
+ {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
+ {EPACR0 + EPACR_STRIDE * 11, 0},
+ {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
+ {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
+ {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
+ {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
+ /* EPIMCR (Event Processor Input Mux Control Registers) */
+ {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
+ {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
+ {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
+ /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+ {EPXTRIGCR, 0x0000FFDF},
+ /* end */
+ {FSM_END_FLAG, 0},
+};
+
+/**
+ * fsl_epu_setup - Setup EPU registers to default values
+ */
+void fsl_epu_setup(void *epu_base)
+{
+ struct fsm_reg_vals *data = epu_default_val;
+
+ if (!epu_base || !data)
+ return;
+
+ while (data->offset != FSM_END_FLAG) {
+ out_be32(epu_base + data->offset, data->value);
+ data++;
+ }
+}
+
/**
* fsl_epu_clean - Clear EPU registers
*/
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
index d658aad..d6f7310 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
@@ -63,6 +63,14 @@
#define EPCTR31 0xA7C
#define EPCTR_STRIDE FSL_STRIDE_4B
+#define FSM_END_FLAG 0xFFFFFFFFUL
+
+struct fsm_reg_vals {
+ u32 offset;
+ u32 value;
+};
+
+void fsl_epu_setup(void *epu_base);
void fsl_epu_clean(void *epu_base);
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
index 9b78acb..8e247ee 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/immap_ls102xa.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include "fsl_ls1_serdes.h"
@@ -23,9 +23,15 @@
u64 ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
+ if (!(serdes1_prtcl_map & (1ULL << NONE)))
+ fsl_serdes_init();
+
ret |= (1ULL << device) & serdes1_prtcl_map;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
+ if (!(serdes2_prtcl_map & (1ULL << NONE)))
+ fsl_serdes_init();
+
ret |= (1ULL << device) & serdes2_prtcl_map;
#endif
@@ -87,19 +93,24 @@
serdes_prtcl_map |= (1ULL << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes_prtcl_map |= (1ULL << NONE);
+
return serdes_prtcl_map;
}
void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
- serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+ if (!(serdes1_prtcl_map & (1ULL << NONE)))
+ serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
- serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+ if (!(serdes2_prtcl_map & (1ULL << NONE)))
+ serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
new file mode 100644
index 0000000..1cbe93c
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <fsl_immap.h>
+#include "fsl_epu.h"
+
+#define __secure __attribute__((section("._secure.text")))
+
+#define CCSR_GICD_CTLR 0x1000
+#define CCSR_GICC_CTLR 0x2000
+#define DCSR_RCPM_CG1CR0 0x31c
+#define DCSR_RCPM_CSTTACR0 0xb00
+#define DCFG_CRSTSR_WDRFR 0x8
+#define DDR_RESV_LEN 128
+
+#ifdef CONFIG_LS1_DEEP_SLEEP
+/*
+ * DDR controller initialization training breaks the first 128 bytes of DDR,
+ * save them so that the bootloader can restore them while resuming.
+ */
+static void __secure ls1_save_ddr_head(void)
+{
+ const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+ char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ int i;
+
+ out_le32(&scfg->sparecr[2], dest);
+
+ for (i = 0; i < DDR_RESV_LEN; i++)
+ *dest++ = *src++;
+}
+
+static void __secure ls1_fsm_setup(void)
+{
+ void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
+
+ out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
+ out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
+
+ fsl_epu_setup((void *)dcsr_epu_base);
+
+ /* Pull MCKE signal low before enabling deep sleep signal in FPGA */
+ out_be32(dcsr_epu_base + EPECR0, 0x5);
+ out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
+}
+
+static void __secure ls1_deepsleep_irq_cfg(void)
+{
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
+
+ /* Mask interrupts from GIC */
+ out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
+ out_be32(&rcpm->nirqoutr, 0x0ffffffff);
+ /* Mask deep sleep wake-up interrupts while entering deep sleep */
+ out_be32(&rcpm->dsimskr, 0x0ffffffff);
+
+ ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
+ /*
+ * Workaround: There is bug of register ippdexpcr1, when read it always
+ * returns zero, so its value is saved to a scrachpad register to be
+ * read, that is why we don't read it from register ippdexpcr1 itself.
+ */
+ ippdexpcr1 = in_le32(&scfg->sparecr[7]);
+
+ if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
+ pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
+ SCFG_PMCINTECR_ETSECRXG1 |
+ SCFG_PMCINTECR_ETSECERRG0 |
+ SCFG_PMCINTECR_ETSECERRG1;
+
+ if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
+ pmcintecr |= SCFG_PMCINTECR_GPIO;
+
+ if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
+ pmcintecr |= SCFG_PMCINTECR_LPUART;
+
+ if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
+ pmcintecr |= SCFG_PMCINTECR_FTM;
+
+ /* Always set external IRQ pins as wakeup source */
+ pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
+
+ out_be32(&scfg->pmcintlecr, 0);
+ /* Clear PMC interrupt status */
+ out_be32(&scfg->pmcintsr, 0xffffffff);
+ /* Enable wakeup interrupt during deep sleep */
+ out_be32(&scfg->pmcintecr, pmcintecr);
+}
+
+static void __secure ls1_delay(unsigned int loop)
+{
+ while (loop--) {
+ int i = 1000;
+ while (i--)
+ ;
+ }
+}
+
+static void __secure ls1_start_fsm(void)
+{
+ void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ /* Set HRSTCR */
+ setbits_be32(&scfg->hrstcr, 0x80000000);
+
+ /* Place DDR controller in self refresh mode */
+ setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
+
+ ls1_delay(2000);
+
+ /* Set EVT4_B to lock the signal MCKE down */
+ out_be32(dcsr_epu_base + EPECR0, 0x0);
+
+ ls1_delay(2000);
+
+ out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
+ out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
+
+ /* Enable all EPU Counters */
+ setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
+
+ /* Enable SCU15 */
+ setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
+
+ /* Enter WFI mode, and EPU FSM will start */
+ __asm__ __volatile__ ("wfi" : : : "memory");
+
+ /* NEVER ENTER HERE */
+ while (1)
+ ;
+}
+
+static void __secure ls1_deep_sleep(u32 entry_point)
+{
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+#ifdef QIXIS_BASE
+ u32 tmp;
+ void *qixis_base = (void *)QIXIS_BASE;
+#endif
+
+ /* Enable cluster to enter the PCL10 state */
+ out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
+
+ /* Save the first 128 bytes of DDR data */
+ ls1_save_ddr_head();
+
+ /* Save the kernel resume entry */
+ out_le32(&scfg->sparecr[3], entry_point);
+
+ /* Request to put cluster 0 in PCL10 state */
+ setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
+
+ /* Setup the registers of the EPU FSM for deep sleep */
+ ls1_fsm_setup();
+
+#ifdef QIXIS_BASE
+ /* Connect the EVENT button to IRQ in FPGA */
+ tmp = in_8(qixis_base + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
+ out_8(qixis_base + QIXIS_CTL_SYS, tmp);
+
+ /* Enable deep sleep signals in FPGA */
+ tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
+ tmp |= QIXIS_PWR_CTL2_PCTL;
+ out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
+
+ /* Pull down PCIe RST# */
+ tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
+ tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
+ out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
+#endif
+
+ /* Enable Warm Device Reset */
+ setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
+ setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
+
+ ls1_deepsleep_irq_cfg();
+
+ psci_v7_flush_dcache_all();
+
+ ls1_start_fsm();
+}
+
+#else
+static void __secure ls1_sleep(void)
+{
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+
+#ifdef QIXIS_BASE
+ u32 tmp;
+ void *qixis_base = (void *)QIXIS_BASE;
+
+ /* Connect the EVENT button to IRQ in FPGA */
+ tmp = in_8(qixis_base + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
+ out_8(qixis_base + QIXIS_CTL_SYS, tmp);
+#endif
+
+ /* Enable cluster to enter the PCL10 state */
+ out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
+
+ setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
+
+ __asm__ __volatile__ ("wfi" : : : "memory");
+}
+#endif
+
+void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
+{
+#ifdef CONFIG_LS1_DEEP_SLEEP
+ ls1_deep_sleep(entry_point);
+#else
+ ls1_sleep();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 8f38680..3d41d37 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -29,6 +29,7 @@
#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK 0x0
.pushsection ._secure.text, "ax"
@@ -61,6 +62,8 @@
.word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
.word ARM_PSCI_0_2_FN_SYSTEM_RESET
.word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+ .word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
+ .word PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
.word 0
.word ARM_PSCI_RET_NI
@@ -243,4 +246,12 @@
1: wfi
b 1b
+.globl psci_system_suspend
+psci_system_suspend:
+ push {lr}
+
+ bl ls1_system_suspend
+
+ pop {pc}
+
.popsection
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b1b0c71..52fb6f8 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -7,9 +7,11 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_stream_id.h>
+#include <fsl_csu.h>
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
@@ -58,12 +60,33 @@
return major;
}
+void s_init(void)
+{
+}
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void)
+{
+ int i;
+
+ for (i = PCIE1; i <= PCIE2; i++)
+ if (!is_serdes_configured(i)) {
+ debug("PCIe%d: disabled all R/W permission!\n", i);
+ set_pcie_ns_access(i, 0);
+ }
+}
+#endif
+
int arch_soc_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
#ifdef CONFIG_FSL_QSPI
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
diff --git a/arch/arm/cpu/armv7/mx5/Kconfig b/arch/arm/cpu/armv7/mx5/Kconfig
index 9f250c6..5fb5513 100644
--- a/arch/arm/cpu/armv7/mx5/Kconfig
+++ b/arch/arm/cpu/armv7/mx5/Kconfig
@@ -18,11 +18,19 @@
bool "Support USB armory"
select CPU_V7
+config TARGET_MX53CX9020
+ bool "Support CX9020"
+ select CPU_V7
+ select MX53
+ select DM
+ select DM_SERIAL
+
endchoice
config SYS_SOC
default "mx5"
+source "board/beckhoff/mx53cx9020/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index bf52f0d..610098c 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 3753c14..e6cc7cb 100644
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -12,7 +12,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/imx-common/boot_mode.h>
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 4214ab5..c646966 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -26,11 +26,27 @@
select ROM_UNIFIED_SECTIONS
bool
+config MX6SLL
+ select ROM_UNIFIED_SECTIONS
+ bool
+
config MX6UL
select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
bool
+config MX6ULL
+ bool
+ select MX6UL
+
+config MX6_DDRCAL
+ bool "Include dynamic DDR calibration routines"
+ depends on SPL
+ default n
+ help
+ Say "Y" if your board uses dynamic (per-boot) DDR calibration.
+ If unsure, say N.
+
choice
prompt "MX6 board select"
optional
@@ -39,6 +55,13 @@
bool "Advantech dms-ba16"
select MX6Q
+config TARGET_APALIS_IMX6
+ bool "Toradex Apalis iMX6 board"
+ select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_THERMAL
+
config TARGET_ARISTAINETOS
bool "aristainetos"
@@ -61,6 +84,13 @@
select DM_SERIAL
select DM_GPIO
+config TARGET_COLIBRI_IMX6
+ bool "Toradex Colibri iMX6 board"
+ select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_THERMAL
+
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
@@ -91,6 +121,30 @@
config TARGET_MX6QARM2
bool "mx6qarm2"
+config TARGET_MX6Q_ICORE
+ bool "Support Engicam i.Core"
+ select MX6QDL
+ select OF_CONTROL
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+
+config TARGET_MX6Q_ICORE_RQS
+ bool "Support Engicam i.Core RQS"
+ select MX6QDL
+ select OF_CONTROL
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
select DM
@@ -106,6 +160,12 @@
bool "mx6slevk"
select SUPPORT_SPL
+config TARGET_MX6SLLEVK
+ bool "mx6sll evk"
+ select MX6SLL
+ select DM
+ select DM_THERMAL
+
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
select MX6SX
@@ -133,6 +193,24 @@
select DM_THERMAL
select SUPPORT_SPL
+config TARGET_MX6UL_GEAM
+ bool "Support Engicam GEAM6UL"
+ select MX6UL
+ select OF_CONTROL
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+
+config TARGET_MX6ULL_14X14_EVK
+ bool "Support mx6ull_14x14_evk"
+ select MX6ULL
+ select DM
+ select DM_THERMAL
+
config TARGET_NITROGEN6X
bool "nitrogen6x"
@@ -144,6 +222,10 @@
bool "PICO-IMX6UL-EMMC"
select MX6UL
+config TARGET_LITEBOARD
+ bool "Grinn liteBoard (i.MX6UL)"
+ select LITESOM
+
config TARGET_PLATINUM_PICON
bool "platinum-picon"
select SUPPORT_SPL
@@ -172,6 +254,19 @@
bool "udoo"
select SUPPORT_SPL
+config TARGET_UDOO_NEO
+ bool "UDOO Neo"
+ select SUPPORT_SPL
+ select MX6SX
+ select DM
+ select DM_THERMAL
+
+config TARGET_SAMTEC_VINING_2000
+ bool "samtec VIN|ING 2000"
+ select MX6SX
+ select DM
+ select DM_THERMAL
+
config TARGET_WANDBOARD
bool "wandboard"
select SUPPORT_SPL
@@ -215,22 +310,32 @@
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/el/el6x/Kconfig"
source "board/embest/mx6boards/Kconfig"
+source "board/engicam/geam6ul/Kconfig"
+source "board/engicam/icorem6/Kconfig"
+source "board/engicam/icorem6_rqs/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sllevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
+source "board/freescale/mx6ullevk/Kconfig"
+source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
+source "board/samtec/vining_2000/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/tqc/tqma6/Kconfig"
+source "board/toradex/apalis_imx6/Kconfig"
+source "board/toradex/colibri_imx6/Kconfig"
source "board/udoo/Kconfig"
+source "board/udoo/neo/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index b3c9dcc..fa54c95 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <div64.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
@@ -97,7 +97,10 @@
{
u32 mask, *addr;
- if (is_mx6ul()) {
+ if (is_mx6ull()) {
+ mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
+ addr = &imx_ccm->CCGR0;
+ } else if (is_mx6ul()) {
mask = MXC_CCM_CCGR3_ENET_MASK;
addr = &imx_ccm->CCGR3;
} else {
@@ -117,7 +120,7 @@
{
u32 mask;
- if (is_mx6ul())
+ if (is_mx6ul() || is_mx6ull())
mask = MXC_CCM_CCGR5_UART_MASK;
else
mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
@@ -168,7 +171,9 @@
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
} else {
- if (is_mx6sx() || is_mx6ul()) {
+ if (is_mx6sll())
+ return -EINVAL;
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = &imx_ccm->CCGR6;
} else {
@@ -279,7 +284,7 @@
switch (pll) {
case PLL_BUS:
- if (!is_mx6ul()) {
+ if (!is_mx6ul() && !is_mx6ull()) {
if (pfd_num == 3) {
/* No PFD3 on PLL2 */
return 0;
@@ -379,8 +384,8 @@
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
- if (is_mx6sl() || is_mx6sx() ||
- is_mx6dqp() || is_mx6ul()) {
+ if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
+ is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
}
@@ -396,7 +401,8 @@
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
- if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
+ if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
+ is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
@@ -415,7 +421,8 @@
cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
- if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
+ if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
+ is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
@@ -477,7 +484,8 @@
u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
- if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
+ is_mx6sll()) {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -509,6 +517,11 @@
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
+ if (is_mx6sl()) {
+ freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
+ break;
+ }
+
pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
switch (pmu_misc2_audio_div) {
case 0:
@@ -615,16 +628,19 @@
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
- if (!is_mx6sx() && !is_mx6ul()) {
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+ !is_mx6sll()) {
debug("This chip not support lcd!\n");
return;
}
- if (base_addr == LCDIF1_BASE_ADDR) {
- reg = readl(&imx_ccm->cscdr2);
- /* Can't change clocks when clock not from pre-mux */
- if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
- return;
+ if (!is_mx6sl()) {
+ if (base_addr == LCDIF1_BASE_ADDR) {
+ reg = readl(&imx_ccm->cscdr2);
+ /* Can't change clocks when clock not from pre-mux */
+ if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
+ return;
+ }
}
if (is_mx6sx()) {
@@ -695,24 +711,44 @@
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
- /* Select pre-lcd clock to PLL5 and set pre divider */
- clrsetbits_le32(&imx_ccm->cscdr2,
- MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
- MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
- (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
- ((pred - 1) <<
- MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+ enable_lcdif_clock(base_addr, 0);
+ if (!is_mx6sl()) {
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
- /* Set the post divider */
- clrsetbits_le32(&imx_ccm->cbcmr,
- MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
- ((postd - 1) <<
- MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cbcmr,
+ MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
+ ((postd - 1) <<
+ MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+ } else {
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cscmr1,
+ MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
+ (((postd - 1)^0x6) <<
+ MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
+ }
+
+ enable_lcdif_clock(base_addr, 1);
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
+ enable_lcdif_clock(base_addr, 0);
/* Select pre-lcd clock to PLL5 and set pre divider */
clrsetbits_le32(&imx_ccm->cscdr2,
MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
@@ -726,10 +762,12 @@
MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
((postd - 1) <<
MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
+
+ enable_lcdif_clock(base_addr, 1);
}
}
-int enable_lcdif_clock(u32 base_addr)
+int enable_lcdif_clock(u32 base_addr, bool enable)
{
u32 reg = 0;
u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
@@ -749,7 +787,7 @@
MXC_CCM_CCGR3_DISP_AXI_MASK) :
(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
MXC_CCM_CCGR3_DISP_AXI_MASK);
- } else if (is_mx6ul()) {
+ } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
@@ -757,23 +795,59 @@
/* Set to pre-mux clock at default */
lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
+ } else if (is_mx6sl()) {
+ if (base_addr != LCDIF1_BASE_ADDR) {
+ puts("Wrong LCD interface!\n");
+ return -EINVAL;
+ }
+
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+ MXC_CCM_CCGR3_LCDIF_PIX_MASK);
+ writel(reg, &imx_ccm->CCGR3);
+
+ if (enable) {
+ reg = readl(&imx_ccm->cscdr3);
+ reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
+ reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
+ writel(reg, &imx_ccm->cscdr3);
+
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+ MXC_CCM_CCGR3_LCDIF_PIX_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+ }
+
+ return 0;
} else {
return 0;
}
- reg = readl(&imx_ccm->cscdr2);
- reg &= ~lcdif_clk_sel_mask;
- writel(reg, &imx_ccm->cscdr2);
-
- /* Enable the LCDIF pix clock */
+ /* Gate LCDIF clock first */
reg = readl(&imx_ccm->CCGR3);
- reg |= lcdif_ccgr3_mask;
+ reg &= ~lcdif_ccgr3_mask;
writel(reg, &imx_ccm->CCGR3);
reg = readl(&imx_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_LCD_MASK;
+ reg &= ~MXC_CCM_CCGR2_LCD_MASK;
writel(reg, &imx_ccm->CCGR2);
+ if (enable) {
+ /* Select pre-mux */
+ reg = readl(&imx_ccm->cscdr2);
+ reg &= ~lcdif_clk_sel_mask;
+ writel(reg, &imx_ccm->cscdr2);
+
+ /* Enable the LCDIF pix clock */
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= lcdif_ccgr3_mask;
+ writel(reg, &imx_ccm->CCGR3);
+
+ reg = readl(&imx_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_LCD_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+ }
+
return 0;
}
#endif
@@ -847,7 +921,7 @@
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
} else if (fec_id == 1) {
/* Only i.MX6SX/UL support ENET2 */
- if (!(is_mx6sx() || is_mx6ul()))
+ if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
return -EINVAL;
reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
@@ -876,6 +950,11 @@
writel(reg, &anatop->pll_enet);
#ifdef CONFIG_MX6SX
+ /* Disable enet system clcok before switching clock parent */
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_ENET_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+
/*
* Set enet ahb clock to 200MHz
* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
@@ -906,6 +985,16 @@
u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+ if (is_mx6ul() || is_mx6ull()) {
+ if (port > 1)
+ return 0;
+ }
+
+ if (is_mx6sll()) {
+ if (port > 2)
+ return 0;
+ }
+
switch (port) {
case 0:
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
@@ -1069,17 +1158,27 @@
{
u32 reg;
- /* CG4 ~ CG6, CAAM clocks */
- reg = __raw_readl(&imx_ccm->CCGR0);
- if (enable)
- reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
- MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
- MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- else
- reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
- MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
- MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- __raw_writel(reg, &imx_ccm->CCGR0);
+ if (is_mx6ull() || is_mx6sll()) {
+ /* CG5, DCP clock */
+ reg = __raw_readl(&imx_ccm->CCGR0);
+ if (enable)
+ reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR0);
+ } else {
+ /* CG4 ~ CG6, CAAM clocks */
+ reg = __raw_readl(&imx_ccm->CCGR0);
+ if (enable)
+ reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ else
+ reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ __raw_writel(reg, &imx_ccm->CCGR0);
+ }
/* EMI slow clk */
reg = __raw_readl(&imx_ccm->CCGR6);
@@ -1364,6 +1463,20 @@
}
#endif
+#ifndef CONFIG_SYS_NO_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
/***************************************************/
U_BOOT_CMD(
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7beb7ea..0cf391e 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -14,8 +14,7 @@
#include <asm/types.h>
#include <wait_bit.h>
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-
+#if defined(CONFIG_MX6_DDRCAL)
static void reset_read_data_fifos(void)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
@@ -86,14 +85,15 @@
writel(val_ctrl, reg_ctrl);
}
-int mmdc_do_write_level_calibration(void)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
u32 esdmisc_val, zq_val;
u32 errors = 0;
- u32 ldectrl[4];
+ u32 ldectrl[4] = {0};
u32 ddr_mr1 = 0x4;
+ u32 rwalat_max;
/*
* Stash old values in case calibration fails,
@@ -101,8 +101,10 @@
*/
ldectrl[0] = readl(&mmdc0->mpwldectrl0);
ldectrl[1] = readl(&mmdc0->mpwldectrl1);
- ldectrl[2] = readl(&mmdc1->mpwldectrl0);
- ldectrl[3] = readl(&mmdc1->mpwldectrl1);
+ if (sysinfo->dsize == 2) {
+ ldectrl[2] = readl(&mmdc1->mpwldectrl0);
+ ldectrl[3] = readl(&mmdc1->mpwldectrl1);
+ }
/* disable DDR logic power down timer */
clrbits_le32(&mmdc0->mdpdc, 0xff00);
@@ -122,10 +124,10 @@
writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
/* 3. increase walat and ralat to maximum */
- setbits_le32(&mmdc0->mdmisc,
- (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
- setbits_le32(&mmdc1->mdmisc,
- (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+ rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
+ setbits_le32(&mmdc0->mdmisc, rwalat_max);
+ if (sysinfo->dsize == 2)
+ setbits_le32(&mmdc1->mdmisc, rwalat_max);
/*
* 4 & 5. Configure the external DDR device to enter write-leveling
* mode through Load Mode Register command.
@@ -152,21 +154,25 @@
*/
if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
errors |= 1;
- if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
- errors |= 2;
+ if (sysinfo->dsize == 2)
+ if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
+ errors |= 2;
debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
/* check to see if cal failed */
if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
(readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
- (readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
- (readl(&mmdc1->mpwldectrl1) == 0x001F001F)) {
+ ((sysinfo->dsize < 2) ||
+ ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
+ (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
writel(ldectrl[0], &mmdc0->mpwldectrl0);
writel(ldectrl[1], &mmdc0->mpwldectrl1);
- writel(ldectrl[2], &mmdc1->mpwldectrl0);
- writel(ldectrl[3], &mmdc1->mpwldectrl1);
+ if (sysinfo->dsize == 2) {
+ writel(ldectrl[2], &mmdc1->mpwldectrl0);
+ writel(ldectrl[3], &mmdc1->mpwldectrl1);
+ }
errors |= 4;
}
@@ -189,16 +195,20 @@
readl(&mmdc0->mpwldectrl0));
debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
readl(&mmdc0->mpwldectrl1));
- debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
- readl(&mmdc1->mpwldectrl0));
- debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
- readl(&mmdc1->mpwldectrl1));
+ if (sysinfo->dsize == 2) {
+ debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+ readl(&mmdc1->mpwldectrl0));
+ debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
+ readl(&mmdc1->mpwldectrl1));
+ }
/* We must force a readback of these values, to get them to stick */
readl(&mmdc0->mpwldectrl0);
readl(&mmdc0->mpwldectrl1);
- readl(&mmdc1->mpwldectrl0);
- readl(&mmdc1->mpwldectrl1);
+ if (sysinfo->dsize == 2) {
+ readl(&mmdc1->mpwldectrl0);
+ readl(&mmdc1->mpwldectrl1);
+ }
/* enable DDR logic power down timer: */
setbits_le32(&mmdc0->mdpdc, 0x00005500);
@@ -212,7 +222,7 @@
return errors;
}
-int mmdc_do_dqs_calibration(void)
+int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
@@ -223,7 +233,6 @@
bool cs0_enable_initial;
bool cs1_enable_initial;
u32 esdmisc_val;
- u32 bus_size;
u32 temp_ref;
u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
u32 errors = 0;
@@ -292,10 +301,6 @@
cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
- /* Check to see what the data bus size is */
- bus_size = (readl(&mmdc0->mdctl) & 0x30000) >> 16;
- debug("Data bus size: %d (%d bits)\n", bus_size, 1 << (bus_size + 4));
-
precharge_all(cs0_enable, cs1_enable);
/* Write the pre-defined value into MPPDCMPR1 */
@@ -314,11 +319,11 @@
* Both PHYs for x64 configuration, if x32, do only PHY0.
*/
writel(initdelay, &mmdc0->mprddlctl);
- if (bus_size == 0x2)
+ if (sysinfo->dsize == 0x2)
writel(initdelay, &mmdc1->mprddlctl);
/* Force a measurment, for previous delay setup to take effect. */
- force_delay_measurement(bus_size);
+ force_delay_measurement(sysinfo->dsize);
/*
* ***************************
@@ -347,6 +352,8 @@
* 16 before comparing read data.
*/
setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+ if (sysinfo->dsize == 2)
+ setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
/* Set bit 28 to start automatic read DQS gating calibration */
setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
@@ -362,9 +369,14 @@
if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
errors |= 1;
- if ((bus_size == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
+ if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
errors |= 2;
+ /* now disable mpdgctrl0[DG_CMP_CYC] */
+ clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+ if (sysinfo->dsize == 2)
+ clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
+
/*
* DQS gating absolute offset should be modified from
* reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
@@ -374,7 +386,7 @@
&mmdc0->mpdgctrl0);
modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
&mmdc0->mpdgctrl1);
- if (bus_size == 0x2) {
+ if (sysinfo->dsize == 0x2) {
modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
&mmdc1->mpdgctrl0);
modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
@@ -417,7 +429,8 @@
if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
errors |= 4;
- if ((bus_size == 0x2) && (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
+ if ((sysinfo->dsize == 0x2) &&
+ (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
errors |= 8;
debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
@@ -443,14 +456,14 @@
* Both PHYs for x64 configuration, if x32, do only PHY0.
*/
writel(initdelay, &mmdc0->mpwrdlctl);
- if (bus_size == 0x2)
+ if (sysinfo->dsize == 0x2)
writel(initdelay, &mmdc1->mpwrdlctl);
/*
* XXX This isn't in the manual. Force a measurement,
* for previous delay setup to effect.
*/
- force_delay_measurement(bus_size);
+ force_delay_measurement(sysinfo->dsize);
/*
* 9. 10. Start the automatic write calibration process
@@ -470,7 +483,8 @@
if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
errors |= 16;
- if ((bus_size == 0x2) && (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
+ if ((sysinfo->dsize == 0x2) &&
+ (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
errors |= 32;
debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
@@ -522,14 +536,18 @@
debug("Read DQS gating calibration:\n");
debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
- debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
- debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
+ if (sysinfo->dsize == 2) {
+ debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
+ debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
+ }
debug("Read calibration:\n");
debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
- debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
+ if (sysinfo->dsize == 2)
+ debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
debug("Write calibration:\n");
debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
- debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
+ if (sysinfo->dsize == 2)
+ debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
/*
* Registers below are for debugging purposes. These print out
@@ -541,10 +559,12 @@
debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
- debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
- debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
- debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
- debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
+ if (sysinfo->dsize == 2) {
+ debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
+ debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
+ debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
+ debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
+ }
debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
@@ -1480,6 +1500,29 @@
mdelay(1);
}
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+ struct mx6_mmdc_calibration *calib)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+ calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
+ calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
+ calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
+ calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
+ calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
+ calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
+
+ if (sysinfo->dsize == 2) {
+ calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
+ calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
+ calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
+ calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
+ calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
+ calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
+ }
+}
+
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const void *ddr_cfg)
diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c
index 9f034d6..e28018b 100644
--- a/arch/arm/cpu/armv7/mx6/mp.c
+++ b/arch/arm/cpu/armv7/mx6/mp.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/imx-regs.h>
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 88fcfdc..dd94797 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
@@ -126,7 +126,7 @@
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
- if (is_mx6ul()) {
+ if (is_mx6ul() || is_mx6ull()) {
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 528000000;
else if (val == OCOTP_CFG3_SPEED_696MHZ)
@@ -293,16 +293,24 @@
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
- if (is_mx6sx() || is_mx6ul() || is_mx6sl())
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
else
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
writel(reg, &mxc_ccm->ccdr);
}
+#define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
+
static void init_bandgap(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
/*
* Ensure the bandgap has stabilized.
*/
@@ -314,8 +322,27 @@
* be set.
*/
writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
-}
+ /*
+ * On i.MX6ULL,we need to set VBGADJ bits according to the
+ * REFTOP_TRIM[3:0] in fuse table
+ * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
+ * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
+ * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
+ * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
+ * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
+ * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
+ * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
+ * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
+ */
+ if (is_mx6ull()) {
+ val = readl(&fuse->mem0);
+ val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
+ val &= 0x7;
+ writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
+ &anatop->ana_misc0_set);
+ }
+}
#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
@@ -343,7 +370,7 @@
*/
init_bandgap();
- if (!IS_ENABLED(CONFIG_MX6UL)) {
+ if (!is_mx6ul() && !is_mx6ull()) {
/*
* When low freq boot is enabled, ROM will not set AHB
* freq, so we need to ensure AHB freq is 132MHz in such
@@ -356,14 +383,41 @@
set_ahb_rate(132000000);
}
- if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
+ if (is_mx6ul()) {
+ if (is_soc_rev(CHIP_REV_1_0) == 0) {
+ /*
+ * According to the design team's requirement on
+ * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
+ * as open drain 100K (0x0000b8a0).
+ * Only exists on TO1.0
+ */
+ writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
+ } else {
+ /*
+ * From TO1.1, SNVS adds internal pull up control
+ * for POR_B, the register filed is GPBIT[1:0],
+ * after system boot up, it can be set to 2b'01
+ * to disable internal pull up.It can save about
+ * 30uA power in SNVS mode.
+ */
+ writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
+ (~0x1400)) | 0x400,
+ MX6UL_SNVS_LP_BASE_ADDR + 0x10);
+ }
+ }
+
+ if (is_mx6ull()) {
/*
- * According to the design team's requirement on i.MX6UL,
- * the PMIC_STBY_REQ PAD should be configured as open
- * drain 100K (0x0000b8a0).
- * Only exists on TO1.0
+ * GPBIT[1:0] is suggested to set to 2'b11:
+ * 2'b00 : always PUP100K
+ * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
+ * 2'b10 : always disable PUP100K
+ * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
+ * register offset is different from i.MX6UL, since
+ * i.MX6UL is fixed by ECO.
*/
- writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
+ writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
+ 0x3, MX6UL_SNVS_LP_BASE_ADDR);
}
/* Set perclk to source from OSC 24MHz */
@@ -459,7 +513,7 @@
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
- if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
+ if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
u32 value = readl(&fuse->mac_addr2);
mac[0] = value >> 24 ;
mac[1] = value >> 16 ;
@@ -494,7 +548,7 @@
const struct boot_mode soc_boot_modes[] = {
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
/* reserved value should start rom usb */
- {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
+ {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
@@ -523,7 +577,7 @@
u32 mask528;
u32 reg, periph1, periph2;
- if (is_mx6sx() || is_mx6ul())
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull())
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c
index 4d68ad2..2cfde46 100644
--- a/arch/arm/cpu/armv7/mx7/clock.c
+++ b/arch/arm/cpu/armv7/mx7/clock.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <div64.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c
index 1665df9..68a7005 100644
--- a/arch/arm/cpu/armv7/mx7/clock_slice.c
+++ b/arch/arm/cpu/armv7/mx7/clock_slice.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <div64.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
diff --git a/arch/arm/cpu/armv7/omap-common/Kconfig b/arch/arm/cpu/armv7/omap-common/Kconfig
deleted file mode 100644
index 7b39506..0000000
--- a/arch/arm/cpu/armv7/omap-common/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-config TI_SECURE_DEVICE
- bool "HS Device Type Support"
- depends on OMAP54XX || AM43XX
- help
- If a high secure (HS) device type is being used, this config
- must be set. This option impacts various aspects of the
- build system (to create signed boot images that can be
- authenticated) and the code. See the doc/README.ti-secure
- file for further details.
-
-source "arch/arm/cpu/armv7/omap3/Kconfig"
-
-source "arch/arm/cpu/armv7/omap4/Kconfig"
-
-source "arch/arm/cpu/armv7/omap5/Kconfig"
-
-source "arch/arm/cpu/armv7/am33xx/Kconfig"
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
deleted file mode 100644
index 3172bae..0000000
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := reset.o
-ifeq ($(CONFIG_TIMER),)
-obj-y += timer.o
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += timer.o
-endif
-endif
-obj-y += utils.o
-
-ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
-obj-y += hwinit-common.o
-obj-y += clocks-common.o
-obj-y += emif-common.o
-obj-y += vc.o
-obj-y += abb.o
-endif
-
-ifneq ($(CONFIG_OMAP54XX),)
-obj-y += pipe3-phy.o
-obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
-endif
-
-ifeq ($(CONFIG_SYS_DCACHE_OFF),)
-obj-y += omap-cache.o
-endif
-
-obj-y += boot-common.o
-obj-y += lowlevel_init.o
-
-obj-y += mem-common.o
-
-obj-$(CONFIG_TI_SECURE_DEVICE) += sec-common.o
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
deleted file mode 100644
index 60c367a..0000000
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * boot-common.c
- *
- * Common bootmode functions for omap based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ahci.h>
-#include <spl.h>
-#include <asm/omap_common.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <watchdog.h>
-#include <scsi.h>
-#include <i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak u32 omap_sys_boot_device(void)
-{
- return BOOT_DEVICE_NONE;
-}
-
-void save_omap_boot_params(void)
-{
- u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
- struct omap_boot_parameters *omap_boot_params;
- int sys_boot_device = 0;
- u32 boot_device;
- u32 boot_mode;
-
- if ((boot_params < NON_SECURE_SRAM_START) ||
- (boot_params > NON_SECURE_SRAM_END))
- return;
-
- omap_boot_params = (struct omap_boot_parameters *)boot_params;
-
- boot_device = omap_boot_params->boot_device;
- boot_mode = MMCSD_MODE_UNDEFINED;
-
- /* Boot device */
-
-#ifdef BOOT_DEVICE_NAND_I2C
- /*
- * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
- * Otherwise the SPL boot IF can't handle this device correctly.
- * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
- * Draco leads to this boot-device passed to SPL from the BootROM.
- */
- if (boot_device == BOOT_DEVICE_NAND_I2C)
- boot_device = BOOT_DEVICE_NAND;
-#endif
-#ifdef BOOT_DEVICE_QSPI_4
- /*
- * We get different values for QSPI_1 and QSPI_4 being used, but
- * don't actually care about this difference. Rather than
- * mangle the later code, if we're coming in as QSPI_4 just
- * change to the QSPI_1 value.
- */
- if (boot_device == BOOT_DEVICE_QSPI_4)
- boot_device = BOOT_DEVICE_SPI;
-#endif
- /*
- * When booting from peripheral booting, the boot device is not usable
- * as-is (unless there is support for it), so the boot device is instead
- * figured out using the SYS_BOOT pins.
- */
- switch (boot_device) {
-#if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT)
- case BOOT_DEVICE_UART:
- sys_boot_device = 1;
- break;
-#endif
-#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT)
- case BOOT_DEVICE_USB:
- sys_boot_device = 1;
- break;
-#endif
-#if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USBETH_SUPPORT)
- case BOOT_DEVICE_USBETH:
- sys_boot_device = 1;
- break;
-#endif
-#if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH_SUPPORT)
- case BOOT_DEVICE_CPGMAC:
- sys_boot_device = 1;
- break;
-#endif
- }
-
- if (sys_boot_device) {
- boot_device = omap_sys_boot_device();
-
- /* MMC raw mode will fallback to FS mode. */
- if ((boot_device >= MMC_BOOT_DEVICES_START) &&
- (boot_device <= MMC_BOOT_DEVICES_END))
- boot_mode = MMCSD_MODE_RAW;
- }
-
- gd->arch.omap_boot_device = boot_device;
-
- /* Boot mode */
-
-#ifdef CONFIG_OMAP34XX
- if ((boot_device >= MMC_BOOT_DEVICES_START) &&
- (boot_device <= MMC_BOOT_DEVICES_END)) {
- switch (boot_device) {
- case BOOT_DEVICE_MMC1:
- boot_mode = MMCSD_MODE_FS;
- break;
- case BOOT_DEVICE_MMC2:
- boot_mode = MMCSD_MODE_RAW;
- break;
- }
- }
-#else
- /*
- * If the boot device was dynamically changed and doesn't match what
- * the bootrom initially booted, we cannot use the boot device
- * descriptor to figure out the boot mode.
- */
- if ((boot_device == omap_boot_params->boot_device) &&
- (boot_device >= MMC_BOOT_DEVICES_START) &&
- (boot_device <= MMC_BOOT_DEVICES_END)) {
- boot_params = omap_boot_params->boot_device_descriptor;
- if ((boot_params < NON_SECURE_SRAM_START) ||
- (boot_params > NON_SECURE_SRAM_END))
- return;
-
- boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET));
- if ((boot_params < NON_SECURE_SRAM_START) ||
- (boot_params > NON_SECURE_SRAM_END))
- return;
-
- boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET));
-
- if (boot_mode != MMCSD_MODE_FS &&
- boot_mode != MMCSD_MODE_RAW)
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
- boot_mode = MMCSD_MODE_EMMCBOOT;
-#else
- boot_mode = MMCSD_MODE_UNDEFINED;
-#endif
- }
-#endif
-
- gd->arch.omap_boot_mode = boot_mode;
-
-#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \
- !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
-
- /* CH flags */
-
- gd->arch.omap_ch_flags = omap_boot_params->ch_flags;
-#endif
-}
-
-#ifdef CONFIG_SPL_BUILD
-u32 spl_boot_device(void)
-{
- return gd->arch.omap_boot_device;
-}
-
-u32 spl_boot_mode(const u32 boot_device)
-{
- return gd->arch.omap_boot_mode;
-}
-
-void spl_board_init(void)
-{
- /*
- * Save the boot parameters passed from romcode.
- * We cannot delay the saving further than this,
- * to prevent overwrites.
- */
- save_omap_boot_params();
-
- /* Prepare console output */
- preloader_console_init();
-
-#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
- gpmc_init();
-#endif
-#ifdef CONFIG_SPL_I2C_SUPPORT
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
-#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
- arch_misc_init();
-#endif
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
-#ifdef CONFIG_AM33XX
- am33xx_spl_board_init();
-#endif
-}
-
-__weak int board_mmc_init(bd_t *bis)
-{
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC1:
- omap_mmc_init(0, 0, 0, -1, -1);
- break;
- case BOOT_DEVICE_MMC2:
- case BOOT_DEVICE_MMC2_2:
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- break;
- }
- return 0;
-}
-
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
-{
- typedef void __noreturn (*image_entry_noargs_t)(u32 *);
- image_entry_noargs_t image_entry =
- (image_entry_noargs_t) spl_image->entry_point;
-
- u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
-
- debug("image entry point: 0x%X\n", spl_image->entry_point);
- /* Pass the saved boot_params from rom code */
- image_entry((u32 *)boot_params);
-}
-#endif
-
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void arch_preboot_os(void)
-{
- ahci_reset((void __iomem *)DWC_AHSATA_BASE);
-}
-#endif
-
-#if defined(CONFIG_USB_FUNCTION_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE)
-int fb_set_reboot_flag(void)
-{
- printf("Setting reboot to fastboot flag ...\n");
- setenv("dofastboot", "1");
- saveenv();
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
deleted file mode 100644
index 9b97583..0000000
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ /dev/null
@@ -1,892 +0,0 @@
-/*
- *
- * Clock initialization for OMAP4
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * Based on previous work by:
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- * Rajendra Nayak <rnayak@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <i2c.h>
-#include <asm/omap_common.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-#include <asm/omap_gpio.h>
-#include <asm/emif.h>
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * printing to console doesn't work unless
- * this code is executed from SPL
- */
-#define printf(fmt, args...)
-#define puts(s)
-#endif
-
-const u32 sys_clk_array[8] = {
- 12000000, /* 12 MHz */
- 20000000, /* 20 MHz */
- 16800000, /* 16.8 MHz */
- 19200000, /* 19.2 MHz */
- 26000000, /* 26 MHz */
- 27000000, /* 27 MHz */
- 38400000, /* 38.4 MHz */
-};
-
-static inline u32 __get_sys_clk_index(void)
-{
- s8 ind;
- /*
- * For ES1 the ROM code calibration of sys clock is not reliable
- * due to hw issue. So, use hard-coded value. If this value is not
- * correct for any board over-ride this function in board file
- * From ES2.0 onwards you will get this information from
- * CM_SYS_CLKSEL
- */
- if (omap_revision() == OMAP4430_ES1_0)
- ind = OMAP_SYS_CLK_IND_38_4_MHZ;
- else {
- /* SYS_CLKSEL - 1 to match the dpll param array indices */
- ind = (readl((*prcm)->cm_sys_clksel) &
- CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
- }
- return ind;
-}
-
-u32 get_sys_clk_index(void)
- __attribute__ ((weak, alias("__get_sys_clk_index")));
-
-u32 get_sys_clk_freq(void)
-{
- u8 index = get_sys_clk_index();
- return sys_clk_array[index];
-}
-
-void setup_post_dividers(u32 const base, const struct dpll_params *params)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- /* Setup post-dividers */
- if (params->m2 >= 0)
- writel(params->m2, &dpll_regs->cm_div_m2_dpll);
- if (params->m3 >= 0)
- writel(params->m3, &dpll_regs->cm_div_m3_dpll);
- if (params->m4_h11 >= 0)
- writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
- if (params->m5_h12 >= 0)
- writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
- if (params->m6_h13 >= 0)
- writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
- if (params->m7_h14 >= 0)
- writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
- if (params->h21 >= 0)
- writel(params->h21, &dpll_regs->cm_div_h21_dpll);
- if (params->h22 >= 0)
- writel(params->h22, &dpll_regs->cm_div_h22_dpll);
- if (params->h23 >= 0)
- writel(params->h23, &dpll_regs->cm_div_h23_dpll);
- if (params->h24 >= 0)
- writel(params->h24, &dpll_regs->cm_div_h24_dpll);
-}
-
-static inline void do_bypass_dpll(u32 const base)
-{
- struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
-
- clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_FAST_RELOCK_BYPASS <<
- CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_bypass(u32 const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
- LDELAY)) {
- printf("Bypassing DPLL failed %x\n", base);
- }
-}
-
-static inline void do_lock_dpll(u32 const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_lock(u32 const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
- &dpll_regs->cm_idlest_dpll, LDELAY)) {
- printf("DPLL locking failed for %x\n", base);
- hang();
- }
-}
-
-inline u32 check_for_lock(u32 const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
- u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
-
- return lock;
-}
-
-const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->mpu[sysclk_ind];
-}
-
-const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->core[sysclk_ind];
-}
-
-const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->per[sysclk_ind];
-}
-
-const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->iva[sysclk_ind];
-}
-
-const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->usb[sysclk_ind];
-}
-
-const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
-{
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- u32 sysclk_ind = get_sys_clk_index();
- return &dpll_data->abe[sysclk_ind];
-#else
- return dpll_data->abe;
-#endif
-}
-
-static const struct dpll_params *get_ddr_dpll_params
- (struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
-
- if (!dpll_data->ddr)
- return NULL;
- return &dpll_data->ddr[sysclk_ind];
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static const struct dpll_params *get_gmac_dpll_params
- (struct dplls const *dpll_data)
-{
- u32 sysclk_ind = get_sys_clk_index();
-
- if (!dpll_data->gmac)
- return NULL;
- return &dpll_data->gmac[sysclk_ind];
-}
-#endif
-
-static void do_setup_dpll(u32 const base, const struct dpll_params *params,
- u8 lock, char *dpll)
-{
- u32 temp, M, N;
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- if (!params)
- return;
-
- temp = readl(&dpll_regs->cm_clksel_dpll);
-
- if (check_for_lock(base)) {
- /*
- * The Dpll has already been locked by rom code using CH.
- * Check if M,N are matching with Ideal nominal opp values.
- * If matches, skip the rest otherwise relock.
- */
- M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
- N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
- if ((M != (params->m)) || (N != (params->n))) {
- debug("\n %s Dpll locked, but not for ideal M = %d,"
- "N = %d values, current values are M = %d,"
- "N= %d" , dpll, params->m, params->n,
- M, N);
- } else {
- /* Dpll locked with ideal values for nominal opps. */
- debug("\n %s Dpll already locked with ideal"
- "nominal opp values", dpll);
-
- bypass_dpll(base);
- goto setup_post_dividers;
- }
- }
-
- bypass_dpll(base);
-
- /* Set M & N */
- temp &= ~CM_CLKSEL_DPLL_M_MASK;
- temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
-
- temp &= ~CM_CLKSEL_DPLL_N_MASK;
- temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
-
- writel(temp, &dpll_regs->cm_clksel_dpll);
-
-setup_post_dividers:
- setup_post_dividers(base, params);
-
- /* Lock */
- if (lock)
- do_lock_dpll(base);
-
- /* Wait till the DPLL locks */
- if (lock)
- wait_for_lock(base);
-}
-
-u32 omap_ddr_clk(void)
-{
- u32 ddr_clk, sys_clk_khz, omap_rev, divider;
- const struct dpll_params *core_dpll_params;
-
- omap_rev = omap_revision();
- sys_clk_khz = get_sys_clk_freq() / 1000;
-
- core_dpll_params = get_core_dpll_params(*dplls_data);
-
- debug("sys_clk %d\n ", sys_clk_khz * 1000);
-
- /* Find Core DPLL locked frequency first */
- ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
- (core_dpll_params->n + 1);
-
- if (omap_rev < OMAP5430_ES1_0) {
- /*
- * DDR frequency is PHY_ROOT_CLK/2
- * PHY_ROOT_CLK = Fdpll/2/M2
- */
- divider = 4;
- } else {
- /*
- * DDR frequency is PHY_ROOT_CLK
- * PHY_ROOT_CLK = Fdpll/2/M2
- */
- divider = 2;
- }
-
- ddr_clk = ddr_clk / divider / core_dpll_params->m2;
- ddr_clk *= 1000; /* convert to Hz */
- debug("ddr_clk %d\n ", ddr_clk);
-
- return ddr_clk;
-}
-
-/*
- * Lock MPU dpll
- *
- * Resulting MPU frequencies:
- * 4430 ES1.0 : 600 MHz
- * 4430 ES2.x : 792 MHz (OPP Turbo)
- * 4460 : 920 MHz (OPP Turbo) - DCC disabled
- */
-void configure_mpu_dpll(void)
-{
- const struct dpll_params *params;
- struct dpll_regs *mpu_dpll_regs;
- u32 omap_rev;
- omap_rev = omap_revision();
-
- /*
- * DCC and clock divider settings for 4460.
- * DCC is required, if more than a certain frequency is required.
- * For, 4460 > 1GHZ.
- * 5430 > 1.4GHZ.
- */
- if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
- mpu_dpll_regs =
- (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
- bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
- clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
- setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
- clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
- CM_CLKSEL_DCC_EN_MASK);
- }
-
- params = get_mpu_dpll_params(*dplls_data);
-
- do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
- debug("MPU DPLL locked\n");
-}
-
-#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
- defined(CONFIG_USB_MUSB_OMAP2PLUS)
-static void setup_usb_dpll(void)
-{
- const struct dpll_params *params;
- u32 sys_clk_khz, sd_div, num, den;
-
- sys_clk_khz = get_sys_clk_freq() / 1000;
- /*
- * USB:
- * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
- * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
- * - where CLKINP is sys_clk in MHz
- * Use CLKINP in KHz and adjust the denominator accordingly so
- * that we have enough accuracy and at the same time no overflow
- */
- params = get_usb_dpll_params(*dplls_data);
- num = params->m * sys_clk_khz;
- den = (params->n + 1) * 250 * 1000;
- num += den - 1;
- sd_div = num / den;
- clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
- CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
- sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
-
- /* Now setup the dpll with the regular function */
- do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
-}
-#endif
-
-static void setup_dplls(void)
-{
- u32 temp;
- const struct dpll_params *params;
- struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
- debug("setup_dplls\n");
-
- /* CORE dpll */
- params = get_core_dpll_params(*dplls_data); /* default - safest */
- /*
- * Do not lock the core DPLL now. Just set it up.
- * Core DPLL will be locked after setting up EMIF
- * using the FREQ_UPDATE method(freq_update_core())
- */
- if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
- EMIF_SDRAM_TYPE_LPDDR2)
- do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
- DPLL_NO_LOCK, "core");
- else
- do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
- DPLL_LOCK, "core");
- /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
- temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
- (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
- (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
- writel(temp, (*prcm)->cm_clksel_core);
- debug("Core DPLL configured\n");
-
- /* lock PER dpll */
- params = get_per_dpll_params(*dplls_data);
- do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
- params, DPLL_LOCK, "per");
- debug("PER DPLL locked\n");
-
- /* MPU dpll */
- configure_mpu_dpll();
-
-#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
- defined(CONFIG_USB_MUSB_OMAP2PLUS)
- setup_usb_dpll();
-#endif
- params = get_ddr_dpll_params(*dplls_data);
- do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
- params, DPLL_LOCK, "ddr");
-
-#ifdef CONFIG_DRIVER_TI_CPSW
- params = get_gmac_dpll_params(*dplls_data);
- do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
- DPLL_LOCK, "gmac");
-#endif
-}
-
-u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
-{
- u32 offset_code;
-
- volt_offset -= pmic->base_offset;
-
- offset_code = (volt_offset + pmic->step - 1) / pmic->step;
-
- /*
- * Offset codes 1-6 all give the base voltage in Palmas
- * Offset code 0 switches OFF the SMPS
- */
- return offset_code + pmic->start_code;
-}
-
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
-{
- u32 offset_code;
- u32 offset = volt_mv;
- int ret = 0;
-
- if (!volt_mv)
- return;
-
- pmic->pmic_bus_init();
- /* See if we can first get the GPIO if needed */
- if (pmic->gpio_en)
- ret = gpio_request(pmic->gpio, "PMIC_GPIO");
-
- if (ret < 0) {
- printf("%s: gpio %d request failed %d\n", __func__,
- pmic->gpio, ret);
- return;
- }
-
- /* Pull the GPIO low to select SET0 register, while we program SET1 */
- if (pmic->gpio_en)
- gpio_direction_output(pmic->gpio, 0);
-
- /* convert to uV for better accuracy in the calculations */
- offset *= 1000;
-
- offset_code = get_offset_code(offset, pmic);
-
- debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
- offset_code);
-
- if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
- printf("Scaling voltage failed for 0x%x\n", vcore_reg);
- if (pmic->gpio_en)
- gpio_direction_output(pmic->gpio, 1);
-}
-
-static u32 optimize_vcore_voltage(struct volts const *v)
-{
- u32 val;
- if (!v->value)
- return 0;
- if (!v->efuse.reg)
- return v->value;
-
- switch (v->efuse.reg_bits) {
- case 16:
- val = readw(v->efuse.reg);
- break;
- case 32:
- val = readl(v->efuse.reg);
- break;
- default:
- printf("Error: efuse 0x%08x bits=%d unknown\n",
- v->efuse.reg, v->efuse.reg_bits);
- return v->value;
- }
-
- if (!val) {
- printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
- v->efuse.reg, v->efuse.reg_bits, v->value);
- return v->value;
- }
-
- debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
- __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
- return val;
-}
-
-#ifdef CONFIG_IODELAY_RECALIBRATION
-void __weak recalibrate_iodelay(void)
-{
-}
-#endif
-
-/*
- * Setup the voltages for the main SoC core power domains.
- * We start with the maximum voltages allowed here, as set in the corresponding
- * vcores_data struct, and then scale (usually down) to the fused values that
- * are retrieved from the SoC. The scaling happens only if the efuse.reg fields
- * are initialised.
- * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
- * compiled conditionally. Note that the new code writes the scaled (or zeroed)
- * values back to the vcores_data struct for eventual reuse. Zero values mean
- * that the corresponding rails are not controlled separately, and are not sent
- * to the PMIC.
- */
-void scale_vcores(struct vcores_data const *vcores)
-{
- int i;
- struct volts *pv = (struct volts *)vcores;
- struct volts *px;
-
- for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
- debug("%d -> ", pv->value);
- if (pv->value) {
- /* Handle non-empty members only */
- pv->value = optimize_vcore_voltage(pv);
- px = (struct volts *)vcores;
- while (px < pv) {
- /*
- * Scan already handled non-empty members to see
- * if we have a group and find the max voltage,
- * which is set to the first occurance of the
- * particular SMPS; the other group voltages are
- * zeroed.
- */
- if (px->value) {
- if ((pv->pmic->i2c_slave_addr ==
- px->pmic->i2c_slave_addr) &&
- (pv->addr == px->addr)) {
- /* Same PMIC, same SMPS */
- if (pv->value > px->value)
- px->value = pv->value;
-
- pv->value = 0;
- }
- }
- px++;
- }
- }
- debug("%d\n", pv->value);
- pv++;
- }
-
- debug("cor: %d\n", vcores->core.value);
- do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
- /*
- * IO delay recalibration should be done immediately after
- * adjusting AVS voltages for VDD_CORE_L.
- * Respective boards should call __recalibrate_iodelay()
- * with proper mux, virtual and manual mode configurations.
- */
-#ifdef CONFIG_IODELAY_RECALIBRATION
- recalibrate_iodelay();
-#endif
-
- debug("mpu: %d\n", vcores->mpu.value);
- do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
- /* Configure MPU ABB LDO after scale */
- abb_setup(vcores->mpu.efuse.reg,
- (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
- (*prcm)->prm_abbldo_mpu_setup,
- (*prcm)->prm_abbldo_mpu_ctrl,
- (*prcm)->prm_irqstatus_mpu_2,
- vcores->mpu.abb_tx_done_mask,
- OMAP_ABB_FAST_OPP);
-
- debug("mm: %d\n", vcores->mm.value);
- do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic);
- /* Configure MM ABB LDO after scale */
- abb_setup(vcores->mm.efuse.reg,
- (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
- (*prcm)->prm_abbldo_mm_setup,
- (*prcm)->prm_abbldo_mm_ctrl,
- (*prcm)->prm_irqstatus_mpu,
- vcores->mm.abb_tx_done_mask,
- OMAP_ABB_FAST_OPP);
-
- debug("gpu: %d\n", vcores->gpu.value);
- do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
- /* Configure GPU ABB LDO after scale */
- abb_setup(vcores->gpu.efuse.reg,
- (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
- (*prcm)->prm_abbldo_gpu_setup,
- (*prcm)->prm_abbldo_gpu_ctrl,
- (*prcm)->prm_irqstatus_mpu,
- vcores->gpu.abb_tx_done_mask,
- OMAP_ABB_FAST_OPP);
- debug("eve: %d\n", vcores->eve.value);
- do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
- /* Configure EVE ABB LDO after scale */
- abb_setup(vcores->eve.efuse.reg,
- (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
- (*prcm)->prm_abbldo_eve_setup,
- (*prcm)->prm_abbldo_eve_ctrl,
- (*prcm)->prm_irqstatus_mpu,
- vcores->eve.abb_tx_done_mask,
- OMAP_ABB_FAST_OPP);
- debug("iva: %d\n", vcores->iva.value);
- do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
- /* Configure IVA ABB LDO after scale */
- abb_setup(vcores->iva.efuse.reg,
- (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
- (*prcm)->prm_abbldo_iva_setup,
- (*prcm)->prm_abbldo_iva_ctrl,
- (*prcm)->prm_irqstatus_mpu,
- vcores->iva.abb_tx_done_mask,
- OMAP_ABB_FAST_OPP);
-}
-
-static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
-{
- clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
- enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - %x\n", clkctrl_reg);
-}
-
-static inline void disable_clock_domain(u32 const clkctrl_reg)
-{
- clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Disable clock domain - %x\n", clkctrl_reg);
-}
-
-static inline void wait_for_clk_enable(u32 clkctrl_addr)
-{
- u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
- u32 bound = LDELAY;
-
- while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
- (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
-
- clkctrl = readl(clkctrl_addr);
- idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
- MODULE_CLKCTRL_IDLEST_SHIFT;
- if (--bound == 0) {
- printf("Clock enable failed for 0x%x idlest 0x%x\n",
- clkctrl_addr, clkctrl);
- return;
- }
- }
-}
-
-static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
- u32 wait_for_enable)
-{
- clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
- enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - %x\n", clkctrl_addr);
- if (wait_for_enable)
- wait_for_clk_enable(clkctrl_addr);
-}
-
-static inline void wait_for_clk_disable(u32 clkctrl_addr)
-{
- u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
- u32 bound = LDELAY;
-
- while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
- clkctrl = readl(clkctrl_addr);
- idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
- MODULE_CLKCTRL_IDLEST_SHIFT;
- if (--bound == 0) {
- printf("Clock disable failed for 0x%x idlest 0x%x\n",
- clkctrl_addr, clkctrl);
- return;
- }
- }
-}
-
-static inline void disable_clock_module(u32 const clkctrl_addr,
- u32 wait_for_disable)
-{
- clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Disable clock module - %x\n", clkctrl_addr);
- if (wait_for_disable)
- wait_for_clk_disable(clkctrl_addr);
-}
-
-void freq_update_core(void)
-{
- u32 freq_config1 = 0;
- const struct dpll_params *core_dpll_params;
- u32 omap_rev = omap_revision();
-
- core_dpll_params = get_core_dpll_params(*dplls_data);
- /* Put EMIF clock domain in sw wakeup mode */
- enable_clock_domain((*prcm)->cm_memif_clkstctrl,
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
-
- freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
- SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
-
- freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
- SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
-
- freq_config1 |= (core_dpll_params->m2 <<
- SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
- SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
-
- writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
- if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
- (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
- puts("FREQ UPDATE procedure failed!!");
- hang();
- }
-
- /*
- * Putting EMIF in HW_AUTO is seen to be causing issues with
- * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
- * in OMAP5430 ES1.0 silicon
- */
- if (omap_rev != OMAP5430_ES1_0) {
- /* Put EMIF clock domain back in hw auto mode */
- enable_clock_domain((*prcm)->cm_memif_clkstctrl,
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
- }
-}
-
-void bypass_dpll(u32 const base)
-{
- do_bypass_dpll(base);
- wait_for_bypass(base);
-}
-
-void lock_dpll(u32 const base)
-{
- do_lock_dpll(base);
- wait_for_lock(base);
-}
-
-static void setup_clocks_for_console(void)
-{
- /* Do not add any spl_debug prints in this function */
- clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
-
- /* Enable all UARTs - console will be on one of them */
- clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
-}
-
-void do_enable_clocks(u32 const *clk_domains,
- u32 const *clk_modules_hw_auto,
- u32 const *clk_modules_explicit_en,
- u8 wait_for_enable)
-{
- u32 i, max = 100;
-
- /* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++) {
- enable_clock_domain(clk_domains[i],
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- }
-
- /* Clock modules that need to be put in HW_AUTO */
- for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
- enable_clock_module(clk_modules_hw_auto[i],
- MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
- wait_for_enable);
- };
-
- /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
- enable_clock_module(clk_modules_explicit_en[i],
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
- wait_for_enable);
- };
-
- /* Put the clock domains in HW_AUTO mode now */
- for (i = 0; (i < max) && clk_domains[i]; i++) {
- enable_clock_domain(clk_domains[i],
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- }
-}
-
-void do_disable_clocks(u32 const *clk_domains,
- u32 const *clk_modules_disable,
- u8 wait_for_disable)
-{
- u32 i, max = 100;
-
-
- /* Clock modules that need to be put in SW_DISABLE */
- for (i = 0; (i < max) && clk_modules_disable[i]; i++)
- disable_clock_module(clk_modules_disable[i],
- wait_for_disable);
-
- /* Put the clock domains in SW_SLEEP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++)
- disable_clock_domain(clk_domains[i]);
-}
-
-/**
- * setup_early_clocks() - Setup early clocks needed for SoC
- *
- * Setup clocks for console, SPL basic initialization clocks and initialize
- * the timer. This is invoked prior prcm_init.
- */
-void setup_early_clocks(void)
-{
- switch (omap_hw_init_context()) {
- case OMAP_INIT_CONTEXT_SPL:
- case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
- case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
- setup_clocks_for_console();
- enable_basic_clocks();
- timer_init();
- /* Fall through */
- }
-}
-
-void prcm_init(void)
-{
- switch (omap_hw_init_context()) {
- case OMAP_INIT_CONTEXT_SPL:
- case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
- case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
- scale_vcores(*omap_vcores);
- setup_dplls();
- setup_warmreset_time();
- break;
- default:
- break;
- }
-
- if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
- enable_basic_uboot_clocks();
-}
-
-void gpi2c_init(void)
-{
- static int gpi2c = 1;
-
- if (gpi2c) {
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
- CONFIG_SYS_OMAP24_I2C_SLAVE);
- gpi2c = 0;
- }
-}
diff --git a/arch/arm/cpu/armv7/omap-common/config_secure.mk b/arch/arm/cpu/armv7/omap-common/config_secure.mk
deleted file mode 100644
index 1122439..0000000
--- a/arch/arm/cpu/armv7/omap-common/config_secure.mk
+++ /dev/null
@@ -1,113 +0,0 @@
-#
-# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-quiet_cmd_mkomapsecimg = MKIMAGE $@
-ifneq ($(TI_SECURE_DEV_PKG),)
-ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
-ifneq ($(CONFIG_SPL_BUILD),)
-cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
- $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-else
-cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
- $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-endif
-else
-cmd_mkomapsecimg = echo "WARNING:" \
- "$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \
- "$@ was NOT created!"
-endif
-else
-cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
- "variable must be defined for TI secure devices. $@ was NOT created!"
-endif
-
-ifdef CONFIG_SPL_LOAD_FIT
-quiet_cmd_omapsecureimg = SECURE $@
-ifneq ($(TI_SECURE_DEV_PKG),)
-ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),)
-cmd_omapsecureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \
- $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-else
-cmd_omapsecureimg = echo "WARNING:" \
- "$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \
- "$@ was NOT created!"; cp $< $@
-endif
-else
-cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
- "variable must be defined for TI secure devices." \
- "$@ was NOT created!"; cp $< $@
-endif
-endif
-
-
-# Standard X-LOADER target (QPSI, NOR flash)
-u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin
- $(call if_changed,mkomapsecimg)
-
-# For MLO targets (SD card boot) the final file name that is copied to the SD
-# card FAT partition must be MLO, so we make a copy of the output file to a new
-# file with that name
-u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin
- $(call if_changed,mkomapsecimg)
- @if [ -f $@ ]; then \
- cp -f $@ MLO; \
- fi
-
-# Standard 2ND target (certain peripheral boot modes)
-u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin
- $(call if_changed,mkomapsecimg)
-
-# Standard ULO target (certain peripheral boot modes)
-u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin
- $(call if_changed,mkomapsecimg)
-
-# Standard ISSW target (certain devices, various boot modes)
-u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin
- $(call if_changed,mkomapsecimg)
-
-# For SPI flash on AM335x and AM43xx, these require special byte swap handling
-# so we use the SPI_X-LOADER target instead of X-LOADER and let the
-# create-boot-image.sh script handle that
-u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin
- $(call if_changed,mkomapsecimg)
-
-# For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot
-# file, not an SPL. In this case the mkomapsecimg command looks for a
-# u-boot-HS_* prefix
-u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin
- $(call if_changed,mkomapsecimg)
-
-# For supporting the SPL loading and interpreting of FIT images whose
-# components are pre-processed before being integrated into the FIT image in
-# order to secure them in some way
-ifdef CONFIG_SPL_LOAD_FIT
-
-MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
- -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
- $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
-
-OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
-$(OF_LIST_TARGETS): dtbs
-
-%_HS.dtb: %.dtb
- $(call if_changed,omapsecureimg)
- $(Q)if [ -f $@ ]; then \
- cp -f $@ $<; \
- fi
-
-u-boot-nodtb_HS.bin: u-boot-nodtb.bin
- $(call if_changed,omapsecureimg)
-
-u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%_HS.dtb,$(OF_LIST_TARGETS))
- $(call if_changed,mkimage)
- $(Q)if [ -f $@ ]; then \
- cp -f $@ u-boot.img; \
- fi
-
-endif
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
deleted file mode 100644
index 2b79010..0000000
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ /dev/null
@@ -1,1489 +0,0 @@
-/*
- * EMIF programming
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/emif.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/utils.h>
-#include <linux/compiler.h>
-
-static int emif1_enabled = -1, emif2_enabled = -1;
-
-void set_lpmode_selfrefresh(u32 base)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 reg;
-
- reg = readl(&emif->emif_pwr_mgmt_ctrl);
- reg &= ~EMIF_REG_LP_MODE_MASK;
- reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
- reg &= ~EMIF_REG_SR_TIM_MASK;
- writel(reg, &emif->emif_pwr_mgmt_ctrl);
-
- /* dummy read for the new SR_TIM to be loaded */
- readl(&emif->emif_pwr_mgmt_ctrl);
-}
-
-void force_emif_self_refresh()
-{
- set_lpmode_selfrefresh(EMIF1_BASE);
- if (!is_dra72x())
- set_lpmode_selfrefresh(EMIF2_BASE);
-}
-
-inline u32 emif_num(u32 base)
-{
- if (base == EMIF1_BASE)
- return 1;
- else if (base == EMIF2_BASE)
- return 2;
- else
- return 0;
-}
-
-static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
-{
- u32 mr;
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- mr_addr |= cs << EMIF_REG_CS_SHIFT;
- writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
- if (omap_revision() == OMAP4430_ES2_0)
- mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
- else
- mr = readl(&emif->emif_lpddr2_mode_reg_data);
- debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
- cs, mr_addr, mr);
- if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
- ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
- ((mr & 0xff000000) >> 24) == (mr & 0xff))
- return mr & 0xff;
- else
- return mr;
-}
-
-static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- mr_addr |= cs << EMIF_REG_CS_SHIFT;
- writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
- writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
-}
-
-void emif_reset_phy(u32 base)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 iodft;
-
- iodft = readl(&emif->emif_iodft_tlgc);
- iodft |= EMIF_REG_RESET_PHY_MASK;
- writel(iodft, &emif->emif_iodft_tlgc);
-}
-
-static void do_lpddr2_init(u32 base, u32 cs)
-{
- u32 mr_addr;
- const struct lpddr2_mr_regs *mr_regs;
-
- get_lpddr2_mr_regs(&mr_regs);
- /* Wait till device auto initialization is complete */
- while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
- ;
- set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
- /*
- * tZQINIT = 1 us
- * Enough loops assuming a maximum of 2GHz
- */
-
- sdelay(2000);
-
- set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
- set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
-
- /*
- * Enable refresh along with writing MR2
- * Encoding of RL in MR2 is (RL - 2)
- */
- mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(base, cs, mr_addr, mr_regs->mr2);
-
- if (mr_regs->mr3 > 0)
- set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
-}
-
-static void lpddr2_init(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- /* Not NVM */
- clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
-
- /*
- * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
- * when EMIF_SDRAM_CONFIG register is written
- */
- setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
-
- /*
- * Set the SDRAM_CONFIG and PHY_CTRL for the
- * un-locked frequency & default RL
- */
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
- writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
-
- do_ext_phy_settings(base, regs);
-
- do_lpddr2_init(base, CS0);
- if (regs->sdram_config & EMIF_REG_EBANK_MASK)
- do_lpddr2_init(base, CS1);
-
- writel(regs->sdram_config, &emif->emif_sdram_config);
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-
- /* Enable refresh now */
- clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
-
- }
-
-__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
-{
-}
-
-void emif_update_timings(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- if (!is_dra7xx())
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
- else
- writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
-
- writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
- writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
- writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
- if (omap_revision() == OMAP4430_ES1_0) {
- /* ES1 bug EMIF should be in force idle during freq_update */
- writel(0, &emif->emif_pwr_mgmt_ctrl);
- } else {
- writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
- writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
- }
- writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
- writel(regs->zq_config, &emif->emif_zq_config);
- writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
-
- if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
- writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
- &emif->emif_l3_config);
- } else if (omap_revision() >= OMAP4460_ES1_0) {
- writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
- &emif->emif_l3_config);
- } else {
- writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
- &emif->emif_l3_config);
- }
-}
-
-#ifndef CONFIG_OMAP44XX
-static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- /* keep sdram in self-refresh */
- writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
- & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
- __udelay(130);
-
- /*
- * Set invert_clkout (if activated)--DDR_PHYCTRL_1
- * Invert clock adds an additional half cycle delay on the
- * command interface. The additional half cycle, is usually
- * meant to enable leveling in the situation that DQS is later
- * than CK on the board.It also helps provide some additional
- * margin for leveling.
- */
- writel(regs->emif_ddr_phy_ctlr_1,
- &emif->emif_ddr_phy_ctrl_1);
-
- writel(regs->emif_ddr_phy_ctlr_1,
- &emif->emif_ddr_phy_ctrl_1_shdw);
- __udelay(130);
-
- writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
- & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
-
- /* Launch Full leveling */
- writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
-
- /* Wait till full leveling is complete */
- readl(&emif->emif_rd_wr_lvl_ctl);
- __udelay(130);
-
- /* Read data eye leveling no of samples */
- config_data_eye_leveling_samples(base);
-
- /*
- * Launch 8 incremental WR_LVL- to compensate for
- * PHY limitation.
- */
- writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
- &emif->emif_rd_wr_lvl_ctl);
-
- __udelay(130);
-
- /* Launch Incremental leveling */
- writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
- __udelay(130);
-}
-
-static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
- u32 reg, i, phy;
-
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
- phy = readl(&emif->emif_ddr_phy_ctrl_1);
-
- /* Update PHY_REG_RDDQS_RATIO */
- emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
- if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
- for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
- reg = readl(emif_phy_status++);
- writel(reg, emif_ext_phy_ctrl_reg++);
- writel(reg, emif_ext_phy_ctrl_reg++);
- }
-
- /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
- emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
- if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
- for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
- reg = readl(emif_phy_status++);
- writel(reg, emif_ext_phy_ctrl_reg++);
- writel(reg, emif_ext_phy_ctrl_reg++);
- }
-
- /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
- emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
- if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
- for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
- reg = readl(emif_phy_status++);
- writel(reg, emif_ext_phy_ctrl_reg++);
- writel(reg, emif_ext_phy_ctrl_reg++);
- }
-
- /* Disable Leveling */
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
- writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
-}
-
-static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- /* Clear Error Status */
- clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
- EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
- EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
-
- clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
- EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
- EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
-
- /* Disable refreshed before leveling */
- clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
- EMIF_REG_INITREF_DIS_MASK);
-
- /* Start Full leveling */
- writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
-
- __udelay(300);
-
- /* Check for leveling timeout */
- if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
- printf("Leveling timeout on EMIF%d\n", emif_num(base));
- return;
- }
-
- /* Enable refreshes after leveling */
- clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
-
- debug("HW leveling success\n");
- /*
- * Update slave ratios in EXT_PHY_CTRLx registers
- * as per HW leveling output
- */
- update_hwleveling_output(base, regs);
-}
-
-static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- if (warm_reset()) {
- emif_reset_phy(base);
- writel(0x0, &emif->emif_pwr_mgmt_ctrl);
- }
- do_ext_phy_settings(base, regs);
-
- writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
- &emif->emif_sdram_ref_ctrl);
- /* Update timing registers */
- writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
- writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
- writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
-
- writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
- writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
- writel(regs->zq_config, &emif->emif_zq_config);
- writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
- writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
- writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
-
- writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
- writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
-
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
-
- writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
-
- __udelay(1000);
-
- writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
-
- if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
- dra7_ddr3_leveling(base, regs);
-}
-
-static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
- /*
- * Set SDRAM_CONFIG and PHY control registers to locked frequency
- * and RL =7. As the default values of the Mode Registers are not
- * defined, contents of mode Registers must be fully initialized.
- * H/W takes care of this initialization
- */
- writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
-
- /* Update timing registers */
- writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
- writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
- writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
-
- writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
-
- writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
- do_ext_phy_settings(base, regs);
-
- writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
- omap5_ddr3_leveling(base, regs);
-}
-
-static void ddr3_init(u32 base, const struct emif_regs *regs)
-{
- if (is_omap54xx())
- omap5_ddr3_init(base, regs);
- else
- dra7_ddr3_init(base, regs);
-}
-#endif
-
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-
-/*
- * Organization and refresh requirements for LPDDR2 devices of different
- * types and densities. Derived from JESD209-2 section 2.4
- */
-const struct lpddr2_addressing addressing_table[] = {
- /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
- {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
- {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
- {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
- {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
- {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
- {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
- {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
- {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
- {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
- {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
-};
-
-static const u32 lpddr2_density_2_size_in_mbytes[] = {
- 8, /* 64Mb */
- 16, /* 128Mb */
- 32, /* 256Mb */
- 64, /* 512Mb */
- 128, /* 1Gb */
- 256, /* 2Gb */
- 512, /* 4Gb */
- 1024, /* 8Gb */
- 2048, /* 16Gb */
- 4096 /* 32Gb */
-};
-
-/*
- * Calculate the period of DDR clock from frequency value and set the
- * denominator and numerator in global variables for easy access later
- */
-static void set_ddr_clk_period(u32 freq)
-{
- /*
- * period = 1/freq
- * period_in_ns = 10^9/freq
- */
- *T_num = 1000000000;
- *T_den = freq;
- cancel_out(T_num, T_den, 200);
-
-}
-
-/*
- * Convert time in nano seconds to number of cycles of DDR clock
- */
-static inline u32 ns_2_cycles(u32 ns)
-{
- return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
-}
-
-/*
- * ns_2_cycles with the difference that the time passed is 2 times the actual
- * value(to avoid fractions). The cycles returned is for the original value of
- * the timing parameter
- */
-static inline u32 ns_x2_2_cycles(u32 ns)
-{
- return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
-}
-
-/*
- * Find addressing table index based on the device's type(S2 or S4) and
- * density
- */
-s8 addressing_table_index(u8 type, u8 density, u8 width)
-{
- u8 index;
- if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
- return -1;
-
- /*
- * Look at the way ADDR_TABLE_INDEX* values have been defined
- * in emif.h compared to LPDDR2_DENSITY_* values
- * The table is layed out in the increasing order of density
- * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
- * at the end
- */
- if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
- index = ADDR_TABLE_INDEX1GS2;
- else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
- index = ADDR_TABLE_INDEX2GS2;
- else
- index = density;
-
- debug("emif: addressing table index %d\n", index);
-
- return index;
-}
-
-/*
- * Find the the right timing table from the array of timing
- * tables of the device using DDR clock frequency
- */
-static const struct lpddr2_ac_timings *get_timings_table(const struct
- lpddr2_ac_timings const *const *device_timings,
- u32 freq)
-{
- u32 i, temp, freq_nearest;
- const struct lpddr2_ac_timings *timings = 0;
-
- emif_assert(freq <= MAX_LPDDR2_FREQ);
- emif_assert(device_timings);
-
- /*
- * Start with the maximum allowed frequency - that is always safe
- */
- freq_nearest = MAX_LPDDR2_FREQ;
- /*
- * Find the timings table that has the max frequency value:
- * i. Above or equal to the DDR frequency - safe
- * ii. The lowest that satisfies condition (i) - optimal
- */
- for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
- temp = device_timings[i]->max_freq;
- if ((temp >= freq) && (temp <= freq_nearest)) {
- freq_nearest = temp;
- timings = device_timings[i];
- }
- }
- debug("emif: timings table: %d\n", freq_nearest);
- return timings;
-}
-
-/*
- * Finds the value of emif_sdram_config_reg
- * All parameters are programmed based on the device on CS0.
- * If there is a device on CS1, it will be same as that on CS0 or
- * it will be NVM. We don't support NVM yet.
- * If cs1_device pointer is NULL it is assumed that there is no device
- * on CS1
- */
-static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
- const struct lpddr2_device_details *cs1_device,
- const struct lpddr2_addressing *addressing,
- u8 RL)
-{
- u32 config_reg = 0;
-
- config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
- config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
- EMIF_REG_IBANK_POS_SHIFT;
-
- config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
-
- config_reg |= RL << EMIF_REG_CL_SHIFT;
-
- config_reg |= addressing->row_sz[cs0_device->io_width] <<
- EMIF_REG_ROWSIZE_SHIFT;
-
- config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
-
- config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
- EMIF_REG_EBANK_SHIFT;
-
- config_reg |= addressing->col_sz[cs0_device->io_width] <<
- EMIF_REG_PAGESIZE_SHIFT;
-
- return config_reg;
-}
-
-static u32 get_sdram_ref_ctrl(u32 freq,
- const struct lpddr2_addressing *addressing)
-{
- u32 ref_ctrl = 0, val = 0, freq_khz;
- freq_khz = freq / 1000;
- /*
- * refresh rate to be set is 'tREFI * freq in MHz
- * division by 10000 to account for khz and x10 in t_REFI_us_x10
- */
- val = addressing->t_REFI_us_x10 * freq_khz / 10000;
- ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
-
- return ref_ctrl;
-}
-
-static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
- const struct lpddr2_min_tck *min_tck,
- const struct lpddr2_addressing *addressing)
-{
- u32 tim1 = 0, val = 0;
- val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
- tim1 |= val << EMIF_REG_T_WTR_SHIFT;
-
- if (addressing->num_banks == BANKS8)
- val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
- (4 * (*T_num)) - 1;
- else
- val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
-
- tim1 |= val << EMIF_REG_T_RRD_SHIFT;
-
- val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
- tim1 |= val << EMIF_REG_T_RC_SHIFT;
-
- val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
- tim1 |= val << EMIF_REG_T_RAS_SHIFT;
-
- val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
- tim1 |= val << EMIF_REG_T_WR_SHIFT;
-
- val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
- tim1 |= val << EMIF_REG_T_RCD_SHIFT;
-
- val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
- tim1 |= val << EMIF_REG_T_RP_SHIFT;
-
- return tim1;
-}
-
-static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
- const struct lpddr2_min_tck *min_tck)
-{
- u32 tim2 = 0, val = 0;
- val = max(min_tck->tCKE, timings->tCKE) - 1;
- tim2 |= val << EMIF_REG_T_CKE_SHIFT;
-
- val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
- tim2 |= val << EMIF_REG_T_RTP_SHIFT;
-
- /*
- * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
- * same value
- */
- val = ns_2_cycles(timings->tXSR) - 1;
- tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
- tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
-
- val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
- tim2 |= val << EMIF_REG_T_XP_SHIFT;
-
- return tim2;
-}
-
-static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
- const struct lpddr2_min_tck *min_tck,
- const struct lpddr2_addressing *addressing)
-{
- u32 tim3 = 0, val = 0;
- val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
- tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
-
- val = ns_2_cycles(timings->tRFCab) - 1;
- tim3 |= val << EMIF_REG_T_RFC_SHIFT;
-
- val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
- tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
-
- val = ns_2_cycles(timings->tZQCS) - 1;
- tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
-
- val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
- tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
-
- return tim3;
-}
-
-static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
- const struct lpddr2_addressing *addressing,
- u8 volt_ramp)
-{
- u32 zq = 0, val = 0;
- if (volt_ramp)
- val =
- EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
- addressing->t_REFI_us_x10;
- else
- val =
- EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
- addressing->t_REFI_us_x10;
- zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
-
- zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
-
- zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
-
- zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
-
- /*
- * Assuming that two chipselects have a single calibration resistor
- * If there are indeed two calibration resistors, then this flag should
- * be enabled to take advantage of dual calibration feature.
- * This data should ideally come from board files. But considering
- * that none of the boards today have calibration resistors per CS,
- * it would be an unnecessary overhead.
- */
- zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
-
- zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
-
- zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
-
- return zq;
-}
-
-static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
- const struct lpddr2_addressing *addressing,
- u8 is_derated)
-{
- u32 alert = 0, interval;
- interval =
- TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
- if (is_derated)
- interval *= 4;
- alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
-
- alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
-
- alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
-
- alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
-
- alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
-
- alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
-
- return alert;
-}
-
-static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
-{
- u32 idle = 0, val = 0;
- if (volt_ramp)
- val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
- else
- /*Maximum value in normal conditions - suggested by hw team */
- val = 0x1FF;
- idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
-
- idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
-
- return idle;
-}
-
-static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
-{
- u32 phy = 0, val = 0;
-
- phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
-
- if (freq <= 100000000)
- val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
- else if (freq <= 200000000)
- val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
- else
- val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
- phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
-
- /* Other fields are constant magic values. Hardcode them together */
- phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
- EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
-
- return phy;
-}
-
-static u32 get_emif_mem_size(u32 base)
-{
- u32 size_mbytes = 0, temp;
- struct emif_device_details dev_details;
- struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
- u32 emif_nr = emif_num(base);
-
- emif_reset_phy(base);
- dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
- &cs0_dev_details);
- dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
- &cs1_dev_details);
- emif_reset_phy(base);
-
- if (dev_details.cs0_device_details) {
- temp = dev_details.cs0_device_details->density;
- size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
- }
-
- if (dev_details.cs1_device_details) {
- temp = dev_details.cs1_device_details->density;
- size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
- }
- /* convert to bytes */
- return size_mbytes << 20;
-}
-
-/* Gets the encoding corresponding to a given DMM section size */
-u32 get_dmm_section_size_map(u32 section_size)
-{
- /*
- * Section size mapping:
- * 0x0: 16-MiB section
- * 0x1: 32-MiB section
- * 0x2: 64-MiB section
- * 0x3: 128-MiB section
- * 0x4: 256-MiB section
- * 0x5: 512-MiB section
- * 0x6: 1-GiB section
- * 0x7: 2-GiB section
- */
- section_size >>= 24; /* divide by 16 MB */
- return log_2_n_round_down(section_size);
-}
-
-static void emif_calculate_regs(
- const struct emif_device_details *emif_dev_details,
- u32 freq, struct emif_regs *regs)
-{
- u32 temp, sys_freq;
- const struct lpddr2_addressing *addressing;
- const struct lpddr2_ac_timings *timings;
- const struct lpddr2_min_tck *min_tck;
- const struct lpddr2_device_details *cs0_dev_details =
- emif_dev_details->cs0_device_details;
- const struct lpddr2_device_details *cs1_dev_details =
- emif_dev_details->cs1_device_details;
- const struct lpddr2_device_timings *cs0_dev_timings =
- emif_dev_details->cs0_device_timings;
-
- emif_assert(emif_dev_details);
- emif_assert(regs);
- /*
- * You can not have a device on CS1 without one on CS0
- * So configuring EMIF without a device on CS0 doesn't
- * make sense
- */
- emif_assert(cs0_dev_details);
- emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
- /*
- * If there is a device on CS1 it should be same type as CS0
- * (or NVM. But NVM is not supported in this driver yet)
- */
- emif_assert((cs1_dev_details == NULL) ||
- (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
- (cs0_dev_details->type == cs1_dev_details->type));
- emif_assert(freq <= MAX_LPDDR2_FREQ);
-
- set_ddr_clk_period(freq);
-
- /*
- * The device on CS0 is used for all timing calculations
- * There is only one set of registers for timings per EMIF. So, if the
- * second CS(CS1) has a device, it should have the same timings as the
- * device on CS0
- */
- timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
- emif_assert(timings);
- min_tck = cs0_dev_timings->min_tck;
-
- temp = addressing_table_index(cs0_dev_details->type,
- cs0_dev_details->density,
- cs0_dev_details->io_width);
-
- emif_assert((temp >= 0));
- addressing = &(addressing_table[temp]);
- emif_assert(addressing);
-
- sys_freq = get_sys_clk_freq();
-
- regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
- cs1_dev_details,
- addressing, RL_BOOT);
-
- regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
- cs1_dev_details,
- addressing, RL_FINAL);
-
- regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
-
- regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
-
- regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
-
- regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
-
- regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
-
- regs->temp_alert_config =
- get_temp_alert_config(cs1_dev_details, addressing, 0);
-
- regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
- LPDDR2_VOLTAGE_STABLE);
-
- regs->emif_ddr_phy_ctlr_1_init =
- get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
-
- regs->emif_ddr_phy_ctlr_1 =
- get_ddr_phy_ctrl_1(freq, RL_FINAL);
-
- regs->freq = freq;
-
- print_timing_reg(regs->sdram_config_init);
- print_timing_reg(regs->sdram_config);
- print_timing_reg(regs->ref_ctrl);
- print_timing_reg(regs->sdram_tim1);
- print_timing_reg(regs->sdram_tim2);
- print_timing_reg(regs->sdram_tim3);
- print_timing_reg(regs->read_idle_ctrl);
- print_timing_reg(regs->temp_alert_config);
- print_timing_reg(regs->zq_config);
- print_timing_reg(regs->emif_ddr_phy_ctlr_1);
- print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
-}
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
-#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-const char *get_lpddr2_type(u8 type_id)
-{
- switch (type_id) {
- case LPDDR2_TYPE_S4:
- return "LPDDR2-S4";
- case LPDDR2_TYPE_S2:
- return "LPDDR2-S2";
- default:
- return NULL;
- }
-}
-
-const char *get_lpddr2_io_width(u8 width_id)
-{
- switch (width_id) {
- case LPDDR2_IO_WIDTH_8:
- return "x8";
- case LPDDR2_IO_WIDTH_16:
- return "x16";
- case LPDDR2_IO_WIDTH_32:
- return "x32";
- default:
- return NULL;
- }
-}
-
-const char *get_lpddr2_manufacturer(u32 manufacturer)
-{
- switch (manufacturer) {
- case LPDDR2_MANUFACTURER_SAMSUNG:
- return "Samsung";
- case LPDDR2_MANUFACTURER_QIMONDA:
- return "Qimonda";
- case LPDDR2_MANUFACTURER_ELPIDA:
- return "Elpida";
- case LPDDR2_MANUFACTURER_ETRON:
- return "Etron";
- case LPDDR2_MANUFACTURER_NANYA:
- return "Nanya";
- case LPDDR2_MANUFACTURER_HYNIX:
- return "Hynix";
- case LPDDR2_MANUFACTURER_MOSEL:
- return "Mosel";
- case LPDDR2_MANUFACTURER_WINBOND:
- return "Winbond";
- case LPDDR2_MANUFACTURER_ESMT:
- return "ESMT";
- case LPDDR2_MANUFACTURER_SPANSION:
- return "Spansion";
- case LPDDR2_MANUFACTURER_SST:
- return "SST";
- case LPDDR2_MANUFACTURER_ZMOS:
- return "ZMOS";
- case LPDDR2_MANUFACTURER_INTEL:
- return "Intel";
- case LPDDR2_MANUFACTURER_NUMONYX:
- return "Numonyx";
- case LPDDR2_MANUFACTURER_MICRON:
- return "Micron";
- default:
- return NULL;
- }
-}
-
-static void display_sdram_details(u32 emif_nr, u32 cs,
- struct lpddr2_device_details *device)
-{
- const char *mfg_str;
- const char *type_str;
- char density_str[10];
- u32 density;
-
- debug("EMIF%d CS%d\t", emif_nr, cs);
-
- if (!device) {
- debug("None\n");
- return;
- }
-
- mfg_str = get_lpddr2_manufacturer(device->manufacturer);
- type_str = get_lpddr2_type(device->type);
-
- density = lpddr2_density_2_size_in_mbytes[device->density];
- if ((density / 1024 * 1024) == density) {
- density /= 1024;
- sprintf(density_str, "%d GB", density);
- } else
- sprintf(density_str, "%d MB", density);
- if (mfg_str && type_str)
- debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
-}
-
-static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
- struct lpddr2_device_details *lpddr2_device)
-{
- u32 mr = 0, temp;
-
- mr = get_mr(base, cs, LPDDR2_MR0);
- if (mr > 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
- if (temp) {
- /* Not SDRAM */
- return 0;
- }
- temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
-
- if (temp) {
- /* DNV supported - But DNV is only supported for NVM */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR4);
- if (mr > 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR5);
- if (mr > 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- if (!get_lpddr2_manufacturer(mr)) {
- /* Manufacturer not identified */
- return 0;
- }
- lpddr2_device->manufacturer = mr;
-
- mr = get_mr(base, cs, LPDDR2_MR6);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR7);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR8);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
- if (!get_lpddr2_type(temp)) {
- /* Not SDRAM */
- return 0;
- }
- lpddr2_device->type = temp;
-
- temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
- if (temp > LPDDR2_DENSITY_32Gb) {
- /* Density not supported */
- return 0;
- }
- lpddr2_device->density = temp;
-
- temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
- if (!get_lpddr2_io_width(temp)) {
- /* IO width unsupported value */
- return 0;
- }
- lpddr2_device->io_width = temp;
-
- /*
- * If all the above tests pass we should
- * have a device on this chip-select
- */
- return 1;
-}
-
-struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
- struct lpddr2_device_details *lpddr2_dev_details)
-{
- u32 phy;
- u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
-
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- if (!lpddr2_dev_details)
- return NULL;
-
- /* Do the minimum init for mode register accesses */
- if (!(running_from_sdram() || warm_reset())) {
- phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
- writel(phy, &emif->emif_ddr_phy_ctrl_1);
- }
-
- if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
- return NULL;
-
- display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
-
- return lpddr2_dev_details;
-}
-#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
-
-static void do_sdram_init(u32 base)
-{
- const struct emif_regs *regs;
- u32 in_sdram, emif_nr;
-
- debug(">>do_sdram_init() %x\n", base);
-
- in_sdram = running_from_sdram();
- emif_nr = (base == EMIF1_BASE) ? 1 : 2;
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
- emif_get_reg_dump(emif_nr, ®s);
- if (!regs) {
- debug("EMIF: reg dump not provided\n");
- return;
- }
-#else
- /*
- * The user has not provided the register values. We need to
- * calculate it based on the timings and the DDR frequency
- */
- struct emif_device_details dev_details;
- struct emif_regs calculated_regs;
-
- /*
- * Get device details:
- * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
- * - Obtained from user otherwise
- */
- struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
- emif_reset_phy(base);
- dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
- &cs0_dev_details);
- dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
- &cs1_dev_details);
- emif_reset_phy(base);
-
- /* Return if no devices on this EMIF */
- if (!dev_details.cs0_device_details &&
- !dev_details.cs1_device_details) {
- return;
- }
-
- /*
- * Get device timings:
- * - Default timings specified by JESD209-2 if
- * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
- * - Obtained from user otherwise
- */
- emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
- &dev_details.cs1_device_timings);
-
- /* Calculate the register values */
- emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
- regs = &calculated_regs;
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
- /*
- * Initializing the DDR device can not happen from SDRAM.
- * Changing the timing registers in EMIF can happen(going from one
- * OPP to another)
- */
- if (!in_sdram && (!warm_reset() || is_dra7xx())) {
- if (emif_sdram_type(regs->sdram_config) ==
- EMIF_SDRAM_TYPE_LPDDR2)
- lpddr2_init(base, regs);
-#ifndef CONFIG_OMAP44XX
- else
- ddr3_init(base, regs);
-#endif
- }
-#ifdef CONFIG_OMAP54X
- if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
- EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
- set_lpmode_selfrefresh(base);
- emif_reset_phy(base);
- omap5_ddr3_leveling(base, regs);
- }
-#endif
-
- /* Write to the shadow registers */
- emif_update_timings(base, regs);
-
- debug("<<do_sdram_init() %x\n", base);
-}
-
-void emif_post_init_config(u32 base)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 omap_rev = omap_revision();
-
- /* reset phy on ES2.0 */
- if (omap_rev == OMAP4430_ES2_0)
- emif_reset_phy(base);
-
- /* Put EMIF back in smart idle on ES1.0 */
- if (omap_rev == OMAP4430_ES1_0)
- writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
-}
-
-void dmm_init(u32 base)
-{
- const struct dmm_lisa_map_regs *lisa_map_regs;
- u32 i, section, valid;
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
- emif_get_dmm_regs(&lisa_map_regs);
-#else
- u32 emif1_size, emif2_size, mapped_size, section_map = 0;
- u32 section_cnt, sys_addr;
- struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
-
- mapped_size = 0;
- section_cnt = 3;
- sys_addr = CONFIG_SYS_SDRAM_BASE;
- emif1_size = get_emif_mem_size(EMIF1_BASE);
- emif2_size = get_emif_mem_size(EMIF2_BASE);
- debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
-
- if (!emif1_size && !emif2_size)
- return;
-
- /* symmetric interleaved section */
- if (emif1_size && emif2_size) {
- mapped_size = min(emif1_size, emif2_size);
- section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
- section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
- /* only MSB */
- section_map |= (sys_addr >> 24) <<
- EMIF_SYS_ADDR_SHIFT;
- section_map |= get_dmm_section_size_map(mapped_size * 2)
- << EMIF_SYS_SIZE_SHIFT;
- lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
- emif1_size -= mapped_size;
- emif2_size -= mapped_size;
- sys_addr += (mapped_size * 2);
- section_cnt--;
- }
-
- /*
- * Single EMIF section(we can have a maximum of 1 single EMIF
- * section- either EMIF1 or EMIF2 or none, but not both)
- */
- if (emif1_size) {
- section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
- section_map |= get_dmm_section_size_map(emif1_size)
- << EMIF_SYS_SIZE_SHIFT;
- /* only MSB */
- section_map |= (mapped_size >> 24) <<
- EMIF_SDRC_ADDR_SHIFT;
- /* only MSB */
- section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
- section_cnt--;
- }
- if (emif2_size) {
- section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
- section_map |= get_dmm_section_size_map(emif2_size) <<
- EMIF_SYS_SIZE_SHIFT;
- /* only MSB */
- section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
- /* only MSB */
- section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
- section_cnt--;
- }
-
- if (section_cnt == 2) {
- /* Only 1 section - either symmetric or single EMIF */
- lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
- lis_map_regs_calculated.dmm_lisa_map_2 = 0;
- lis_map_regs_calculated.dmm_lisa_map_1 = 0;
- } else {
- /* 2 sections - 1 symmetric, 1 single EMIF */
- lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
- lis_map_regs_calculated.dmm_lisa_map_1 = 0;
- }
-
- /* TRAP for invalid TILER mappings in section 0 */
- lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
-
- if (omap_revision() >= OMAP4460_ES1_0)
- lis_map_regs_calculated.is_ma_present = 1;
-
- lisa_map_regs = &lis_map_regs_calculated;
-#endif
- struct dmm_lisa_map_regs *hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)base;
-
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
- writel(lisa_map_regs->dmm_lisa_map_3,
- &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(lisa_map_regs->dmm_lisa_map_2,
- &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(lisa_map_regs->dmm_lisa_map_1,
- &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(lisa_map_regs->dmm_lisa_map_0,
- &hw_lisa_map_regs->dmm_lisa_map_0);
-
- if (lisa_map_regs->is_ma_present) {
- hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)MA_BASE;
-
- writel(lisa_map_regs->dmm_lisa_map_3,
- &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(lisa_map_regs->dmm_lisa_map_2,
- &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(lisa_map_regs->dmm_lisa_map_1,
- &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(lisa_map_regs->dmm_lisa_map_0,
- &hw_lisa_map_regs->dmm_lisa_map_0);
-
- setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
- }
-
- /*
- * EMIF should be configured only when
- * memory is mapped on it. Using emif1_enabled
- * and emif2_enabled variables for this.
- */
- emif1_enabled = 0;
- emif2_enabled = 0;
- for (i = 0; i < 4; i++) {
- section = __raw_readl(DMM_BASE + i*4);
- valid = (section & EMIF_SDRC_MAP_MASK) >>
- (EMIF_SDRC_MAP_SHIFT);
- if (valid == 3) {
- emif1_enabled = 1;
- emif2_enabled = 1;
- break;
- }
-
- if (valid == 1)
- emif1_enabled = 1;
-
- if (valid == 2)
- emif2_enabled = 1;
- }
-}
-
-static void do_bug0039_workaround(u32 base)
-{
- u32 val, i, clkctrl;
- struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
- const struct read_write_regs *bug_00339_regs;
- u32 iterations;
- u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
- u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
-
- if (is_dra7xx())
- phy_status_base++;
-
- bug_00339_regs = get_bug_regs(&iterations);
-
- /* Put EMIF in to idle */
- clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
- __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
-
- /* Copy the phy status registers in to phy ctrl shadow registers */
- for (i = 0; i < iterations; i++) {
- val = __raw_readl(phy_status_base +
- bug_00339_regs[i].read_reg - 1);
-
- __raw_writel(val, phy_ctrl_base +
- ((bug_00339_regs[i].write_reg - 1) << 1));
-
- __raw_writel(val, phy_ctrl_base +
- (bug_00339_regs[i].write_reg << 1) - 1);
- }
-
- /* Disable leveling */
- writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
-
- __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
-}
-
-/*
- * SDRAM initialization:
- * SDRAM initialization has two parts:
- * 1. Configuring the SDRAM device
- * 2. Update the AC timings related parameters in the EMIF module
- * (1) should be done only once and should not be done while we are
- * running from SDRAM.
- * (2) can and should be done more than once if OPP changes.
- * Particularly, this may be needed when we boot without SPL and
- * and using Configuration Header(CH). ROM code supports only at 50% OPP
- * at boot (low power boot). So u-boot has to switch to OPP100 and update
- * the frequency. So,
- * Doing (1) and (2) makes sense - first time initialization
- * Doing (2) and not (1) makes sense - OPP change (when using CH)
- * Doing (1) and not (2) doen't make sense
- * See do_sdram_init() for the details
- */
-void sdram_init(void)
-{
- u32 in_sdram, size_prog, size_detect;
- struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
- u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
-
- debug(">>sdram_init()\n");
-
- if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
- return;
-
- in_sdram = running_from_sdram();
- debug("in_sdram = %d\n", in_sdram);
-
- if (!in_sdram) {
- if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
- bypass_dpll((*prcm)->cm_clkmode_dpll_core);
- else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
- writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
- }
-
- if (!in_sdram)
- dmm_init(DMM_BASE);
-
- if (emif1_enabled)
- do_sdram_init(EMIF1_BASE);
-
- if (emif2_enabled)
- do_sdram_init(EMIF2_BASE);
-
- if (!(in_sdram || warm_reset())) {
- if (emif1_enabled)
- emif_post_init_config(EMIF1_BASE);
- if (emif2_enabled)
- emif_post_init_config(EMIF2_BASE);
- }
-
- /* for the shadow registers to take effect */
- if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
- freq_update_core();
-
- /* Do some testing after the init */
- if (!in_sdram) {
- size_prog = omap_sdram_size();
- size_prog = log_2_n_round_down(size_prog);
- size_prog = (1 << size_prog);
-
- size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- size_prog);
- /* Compare with the size programmed */
- if (size_detect != size_prog) {
- printf("SDRAM: identified size not same as expected"
- " size identified: %x expected: %x\n",
- size_detect,
- size_prog);
- } else
- debug("get_ram_size() successful");
- }
-
- if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
- (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
- if (emif1_enabled)
- do_bug0039_workaround(EMIF1_BASE);
- if (emif2_enabled)
- do_bug0039_workaround(EMIF2_BASE);
- }
-
- debug("<<sdram_init()\n");
-}
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
deleted file mode 100644
index 66a3b3d..0000000
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/omap.h>
-#include <asm/omap_common.h>
-#include <asm/arch/spl.h>
-#include <linux/linkage.h>
-
-.arch_extension sec
-
-#ifdef CONFIG_SPL
-ENTRY(save_boot_params)
- ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
- str r0, [r1]
- b save_boot_params_ret
-ENDPROC(save_boot_params)
-#endif
-
-ENTRY(omap_smc1)
- push {r4-r12, lr} @ save registers - ROM code may pollute
- @ our registers
- mov r12, r0 @ Service
- mov r0, r1 @ Argument
-
- dsb
- dmb
- smc 0 @ SMC #0 to enter monitor mode
- @ call ROM Code API for the service requested
- pop {r4-r12, pc}
-ENDPROC(omap_smc1)
-
-ENTRY(omap_smc_sec)
- push {r4-r12, lr} @ save registers - ROM code may pollute
- @ our registers
- mov r6, #0xFF @ Indicate new Task call
- mov r12, #0x00 @ Secure Service ID in R12
-
- dsb
- dmb
- smc 0 @ SMC #0 to enter monitor mode
-
- b omap_smc_sec_end @ exit at end of the service execution
- nop
-
- @ In case of IRQ happening in Secure, then ARM will branch here.
- @ At that moment, IRQ will be pending and ARM will jump to Non Secure
- @ IRQ handler
- mov r12, #0xFE
-
- dsb
- dmb
- smc 0 @ SMC #0 to enter monitor mode
-
-omap_smc_sec_end:
- pop {r4-r12, pc}
-ENDPROC(omap_smc_sec)
diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c
deleted file mode 100644
index 579bebf..0000000
--- a/arch/arm/cpu/armv7/omap-common/omap-cache.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- *
- * Common functions for OMAP4/5 based boards
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/cache.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ARMV7_DCACHE_WRITEBACK 0xe
-#define ARMV7_DOMAIN_CLIENT 1
-#define ARMV7_DOMAIN_MASK (0x3 << 0)
-
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-
-void dram_bank_mmu_setup(int bank)
-{
- bd_t *bd = gd->bd;
- int i;
-
- u32 start = bd->bi_dram[bank].start >> 20;
- u32 size = bd->bi_dram[bank].size >> 20;
- u32 end = start + size;
-
- debug("%s: bank: %d\n", __func__, bank);
- for (i = start; i < end; i++)
- set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
-}
-
-void arm_init_domains(void)
-{
- u32 reg;
-
- reg = get_dacr();
- /*
- * Set DOMAIN to client access so that all permissions
- * set in pagetables are validated by the mmu.
- */
- reg &= ~ARMV7_DOMAIN_MASK;
- reg |= ARMV7_DOMAIN_CLIENT;
- set_dacr(reg);
-}
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
deleted file mode 100644
index b71d769..0000000
--- a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * TI PIPE3 PHY
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <sata.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include "pipe3-phy.h"
-
-/* PLLCTRL Registers */
-#define PLL_STATUS 0x00000004
-#define PLL_GO 0x00000008
-#define PLL_CONFIGURATION1 0x0000000C
-#define PLL_CONFIGURATION2 0x00000010
-#define PLL_CONFIGURATION3 0x00000014
-#define PLL_CONFIGURATION4 0x00000020
-
-#define PLL_REGM_MASK 0x001FFE00
-#define PLL_REGM_SHIFT 9
-#define PLL_REGM_F_MASK 0x0003FFFF
-#define PLL_REGM_F_SHIFT 0
-#define PLL_REGN_MASK 0x000001FE
-#define PLL_REGN_SHIFT 1
-#define PLL_SELFREQDCO_MASK 0x0000000E
-#define PLL_SELFREQDCO_SHIFT 1
-#define PLL_SD_MASK 0x0003FC00
-#define PLL_SD_SHIFT 10
-#define SET_PLL_GO 0x1
-#define PLL_TICOPWDN BIT(16)
-#define PLL_LDOPWDN BIT(15)
-#define PLL_LOCK 0x2
-#define PLL_IDLE 0x1
-
-/* PHY POWER CONTROL Register */
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
-
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
-
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
-
-
-#define PLL_IDLE_TIME 100 /* in milliseconds */
-#define PLL_LOCK_TIME 100 /* in milliseconds */
-
-static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
-{
- return __raw_readl(addr + offset);
-}
-
-static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
- u32 data)
-{
- __raw_writel(data, addr + offset);
-}
-
-static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
- *pipe3)
-{
- u32 rate;
- struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
-
- rate = get_sys_clk_freq();
-
- for (; dpll_map->rate; dpll_map++) {
- if (rate == dpll_map->rate)
- return &dpll_map->params;
- }
-
- printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
- __func__, rate);
- return NULL;
-}
-
-
-static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
-{
- u32 val;
- int timeout = PLL_LOCK_TIME;
-
- do {
- mdelay(1);
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if (val & PLL_LOCK)
- break;
- } while (--timeout);
-
- if (!(val & PLL_LOCK)) {
- printf("%s: DPLL failed to lock\n", __func__);
- return -EBUSY;
- }
-
- return 0;
-}
-
-static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
-{
- u32 val;
- struct pipe3_dpll_params *dpll_params;
-
- dpll_params = omap_pipe3_get_dpll_params(phy);
- if (!dpll_params) {
- printf("%s: Invalid DPLL parameters\n", __func__);
- return -EINVAL;
- }
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
- val &= ~PLL_REGN_MASK;
- val |= dpll_params->n << PLL_REGN_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- val &= ~PLL_SELFREQDCO_MASK;
- val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
- val &= ~PLL_REGM_MASK;
- val |= dpll_params->m << PLL_REGM_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
- val &= ~PLL_REGM_F_MASK;
- val |= dpll_params->mf << PLL_REGM_F_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
- val &= ~PLL_SD_MASK;
- val |= dpll_params->sd << PLL_SD_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
-
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
-
- return omap_pipe3_wait_lock(phy);
-}
-
-static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
-{
- u32 val, rate;
-
- val = readl(phy->power_reg);
-
- rate = get_sys_clk_freq();
- rate = rate/1000000;
-
- if (on) {
- val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- val |= rate <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
- } else {
- val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- }
-
- writel(val, phy->power_reg);
-}
-
-int phy_pipe3_power_on(struct omap_pipe3 *phy)
-{
- int ret;
- u32 val;
-
- /* Program the DPLL only if not locked */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if (!(val & PLL_LOCK)) {
- ret = omap_pipe3_dpll_program(phy);
- if (ret)
- return ret;
- } else {
- /* else just bring it out of IDLE mode */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- if (val & PLL_IDLE) {
- val &= ~PLL_IDLE;
- omap_pipe3_writel(phy->pll_ctrl_base,
- PLL_CONFIGURATION2, val);
- ret = omap_pipe3_wait_lock(phy);
- if (ret)
- return ret;
- }
- }
-
- /* Power up the PHY */
- omap_control_phy_power(phy, 1);
-
- return 0;
-}
-
-int phy_pipe3_power_off(struct omap_pipe3 *phy)
-{
- u32 val;
- int timeout = PLL_IDLE_TIME;
-
- /* Power down the PHY */
- omap_control_phy_power(phy, 0);
-
- /* Put DPLL in IDLE mode */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- val |= PLL_IDLE;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- /* wait for LDO and Oscillator to power down */
- do {
- mdelay(1);
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
- break;
- } while (--timeout);
-
- if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
- printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
- __func__, val);
- return -EBUSY;
- }
-
- return 0;
-}
-
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
deleted file mode 100644
index 99a25f9..0000000
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ /dev/null
@@ -1,121 +0,0 @@
-if OMAP34XX
-
-choice
- prompt "OMAP3 board select"
- optional
-
-config TARGET_AM3517_EVM
- bool "AM3517 EVM"
-
-config TARGET_MT_VENTOUX
- bool "TeeJet Mt.Ventoux"
-
-config TARGET_OMAP3_BEAGLE
- bool "TI OMAP3 BeagleBoard"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_CM_T35
- bool "CompuLab CM-T3530 and CM-T3730 boards"
-
-config TARGET_CM_T3517
- bool "CompuLab CM-T3517 boards"
-
-config TARGET_DEVKIT8000
- bool "TimLL OMAP3 Devkit8000"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_OMAP3_EVM
- bool "TI OMAP3 EVM"
-
-config TARGET_OMAP3_IGEP00X0
- bool "IGEP"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_OMAP3_OVERO
- bool "OMAP35xx Gumstix Overo"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_OMAP3_ZOOM1
- bool "TI Zoom1"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_AM3517_CRANE
- bool "am3517_crane"
-
-config TARGET_OMAP3_PANDORA
- bool "OMAP3 Pandora"
-
-config TARGET_ECO5PK
- bool "ECO5PK"
-
-config TARGET_TRICORDER
- bool "Tricorder"
-
-config TARGET_MCX
- bool "MCX"
-
-config TARGET_OMAP3_LOGIC
- bool "OMAP3 Logic"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_NOKIA_RX51
- bool "Nokia RX51"
-
-config TARGET_TAO3530
- bool "TAO3530"
-
-config TARGET_TWISTER
- bool "Twister"
-
-config TARGET_OMAP3_CAIRO
- bool "QUIPOS CAIRO"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_SNIPER
- bool "LG Optimus Black"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-endchoice
-
-config SYS_SOC
- default "omap3"
-
-source "board/logicpd/am3517evm/Kconfig"
-source "board/teejet/mt_ventoux/Kconfig"
-source "board/ti/beagle/Kconfig"
-source "board/compulab/cm_t35/Kconfig"
-source "board/compulab/cm_t3517/Kconfig"
-source "board/timll/devkit8000/Kconfig"
-source "board/ti/evm/Kconfig"
-source "board/isee/igep00x0/Kconfig"
-source "board/overo/Kconfig"
-source "board/logicpd/zoom1/Kconfig"
-source "board/ti/am3517crane/Kconfig"
-source "board/pandora/Kconfig"
-source "board/8dtech/eco5pk/Kconfig"
-source "board/corscience/tricorder/Kconfig"
-source "board/htkw/mcx/Kconfig"
-source "board/logicpd/omap3som/Kconfig"
-source "board/nokia/rx51/Kconfig"
-source "board/technexion/tao3530/Kconfig"
-source "board/technexion/twister/Kconfig"
-source "board/quipos/cairo/Kconfig"
-source "board/lg/sniper/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/omap3/am35x_musb.c b/arch/arm/cpu/armv7/omap3/am35x_musb.c
deleted file mode 100644
index 74dd105..0000000
--- a/arch/arm/cpu/armv7/omap3/am35x_musb.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file configures the internal USB PHY in AM35X.
- *
- * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
- *
- * Based on omap_phy_internal.c code from Linux by
- * Hema HK <hemahk@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/am35x_def.h>
-
-void am35x_musb_reset(void)
-{
- /* Reset the musb interface */
- clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
- 0, USBOTGSS_SW_RST);
- clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
- USBOTGSS_SW_RST, 0);
-}
-
-void am35x_musb_phy_power(u8 on)
-{
- unsigned long start = get_timer(0);
-
- if (on) {
- /*
- * Start the on-chip PHY and its PLL.
- */
- clrsetbits_le32(&am35x_scm_general_regs->devconf2,
- CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
- CONF2_PHY_PLLON);
-
- debug("Waiting for PHY clock good...\n");
- while (!(readl(&am35x_scm_general_regs->devconf2)
- & CONF2_PHYCLKGD)) {
-
- if (get_timer(start) > CONFIG_SYS_HZ / 10) {
- printf("musb PHY clock good timed out\n");
- break;
- }
- }
- } else {
- /*
- * Power down the on-chip PHY.
- */
- clrsetbits_le32(&am35x_scm_general_regs->devconf2,
- CONF2_PHY_PLLON,
- CONF2_PHYPWRDN | CONF2_OTGPWRDN);
- }
-}
-
-void am35x_musb_clear_irq(void)
-{
- clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
- 0, USBOTGSS_INT_CLR);
- readl(&am35x_scm_general_regs->lvl_intr_clr);
-}
diff --git a/arch/arm/cpu/armv7/omap3/config.mk b/arch/arm/cpu/armv7/omap3/config.mk
deleted file mode 100644
index ad44d63..0000000
--- a/arch/arm/cpu/armv7/omap3/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright 2011 Linaro Limited
-#
-# (C) Copyright 2010
-# Texas Instruments, <www.ti.com>
-#
-# Aneesh V <aneesh@ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifdef CONFIG_SPL_BUILD
-ALL-y += MLO
-else
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig
deleted file mode 100644
index 49adb8e..0000000
--- a/arch/arm/cpu/armv7/omap4/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-if OMAP44XX
-
-choice
- prompt "OMAP4 board select"
- optional
-
-config TARGET_DUOVERO
- bool "OMAP4430 Gumstix Duovero"
-
-config TARGET_OMAP4_PANDA
- bool "TI OMAP4 PandaBoard"
-
-config TARGET_OMAP4_SDP4430
- bool "TI OMAP4 SDP4430"
-
-config TARGET_KC1
- bool "Amazon Kindle Fire (first generation)"
-
-endchoice
-
-config SYS_SOC
- default "omap4"
-
-source "board/gumstix/duovero/Kconfig"
-source "board/ti/panda/Kconfig"
-source "board/ti/sdp4430/Kconfig"
-source "board/amazon/kc1/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk
deleted file mode 100644
index ad44d63..0000000
--- a/arch/arm/cpu/armv7/omap4/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright 2011 Linaro Limited
-#
-# (C) Copyright 2010
-# Texas Instruments, <www.ti.com>
-#
-# Aneesh V <aneesh@ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifdef CONFIG_SPL_BUILD
-ALL-y += MLO
-else
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
deleted file mode 100644
index 02c06c1..0000000
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- *
- * HW data initialization for OMAP4
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/arch/clock.h>
-#include <asm/omap_gpio.h>
-#include <asm/io.h>
-
-struct prcm_regs const **prcm =
- (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
-struct dplls const **dplls_data =
- (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
-struct vcores_data const **omap_vcores =
- (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
-struct omap_sys_ctrl_regs const **ctrl =
- (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
-
-/*
- * The M & N values in the following tables are created using the
- * following tool:
- * tools/omap/clocks_get_m_n.c
- * Please use this tool for creating the table for any new frequency.
- */
-
-/*
- * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
- * OMAP4460 OPP_NOM frequency
- */
-static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
- {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/*
- * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
- * OMAP4430 OPP_TURBO frequency
- * OMAP4470 OPP_NOM frequency
- */
-static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/*
- * dpll locked at 1200 MHz - MPU clk at 600 MHz
- * OMAP4430 OPP_NOM frequency
- */
-static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
- {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OMAP4460 OPP_NOM frequency */
-/* OMAP4470 OPP_NOM (Low Power) frequency */
-static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
- {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
- {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OMAP4430 ES1 OPP_NOM frequency */
-static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
- {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
- {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
- {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
- {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
- {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
- {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
- {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OMAP4430 ES2.X OPP_NOM frequency */
-static const struct dpll_params
- core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
- {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
- {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
- {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
- {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
- {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
- {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
- {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
- {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
- {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
- {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
- abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
-};
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-struct dplls omap4430_dplls_es1 = {
- .mpu = mpu_dpll_params_1200mhz,
- .core = core_dpll_params_es1_1524mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap4430_dplls_es20 = {
- .mpu = mpu_dpll_params_1200mhz,
- .core = core_dpll_params_es2_1600mhz_ddr200mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap4430_dplls = {
- .mpu = mpu_dpll_params_1200mhz,
- .core = core_dpll_params_1600mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap4460_dplls = {
- .mpu = mpu_dpll_params_1400mhz,
- .core = core_dpll_params_1600mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap4470_dplls = {
- .mpu = mpu_dpll_params_1600mhz,
- .core = core_dpll_params_1600mhz,
- .per = per_dpll_params_1536mhz,
- .iva = iva_dpll_params_1862mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct pmic_data twl6030_4430es1 = {
- .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
- .step = 12660, /* 12.66 mV represented in uV */
- /* The code starts at 1 not 0 */
- .start_code = 1,
- .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
- .pmic_bus_init = sri2c_init,
- .pmic_write = omap_vc_bypass_send_value,
-};
-
-/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
-struct pmic_data twl6030 = {
- .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
- .step = 12660, /* 12.66 mV represented in uV */
- /* The code starts at 1 not 0 */
- .start_code = 1,
- .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
- .pmic_bus_init = sri2c_init,
- .pmic_write = omap_vc_bypass_send_value,
-};
-
-struct pmic_data tps62361 = {
- .base_offset = TPS62361_BASE_VOLT_MV,
- .step = 10000, /* 10 mV represented in uV */
- .start_code = 0,
- .gpio = TPS62361_VSEL0_GPIO,
- .gpio_en = 1,
- .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
- .pmic_bus_init = sri2c_init,
- .pmic_write = omap_vc_bypass_send_value,
-};
-
-struct vcores_data omap4430_volts_es1 = {
- .mpu.value = 1325,
- .mpu.addr = SMPS_REG_ADDR_VCORE1,
- .mpu.pmic = &twl6030_4430es1,
-
- .core.value = 1200,
- .core.addr = SMPS_REG_ADDR_VCORE3,
- .core.pmic = &twl6030_4430es1,
-
- .mm.value = 1200,
- .mm.addr = SMPS_REG_ADDR_VCORE2,
- .mm.pmic = &twl6030_4430es1,
-};
-
-struct vcores_data omap4430_volts = {
- .mpu.value = 1325,
- .mpu.addr = SMPS_REG_ADDR_VCORE1,
- .mpu.pmic = &twl6030,
-
- .core.value = 1200,
- .core.addr = SMPS_REG_ADDR_VCORE3,
- .core.pmic = &twl6030,
-
- .mm.value = 1200,
- .mm.addr = SMPS_REG_ADDR_VCORE2,
- .mm.pmic = &twl6030,
-};
-
-struct vcores_data omap4460_volts = {
- .mpu.value = 1203,
- .mpu.addr = TPS62361_REG_ADDR_SET1,
- .mpu.pmic = &tps62361,
-
- .core.value = 1200,
- .core.addr = SMPS_REG_ADDR_VCORE1,
- .core.pmic = &twl6030,
-
- .mm.value = 1200,
- .mm.addr = SMPS_REG_ADDR_VCORE2,
- .mm.pmic = &twl6030,
-};
-
-/*
- * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
- * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
- */
-struct vcores_data omap4470_volts = {
- .mpu.value = 1202,
- .mpu.addr = SMPS_REG_ADDR_SMPS1,
- .mpu.pmic = &twl6030,
-
- .core.value = 1126,
- .core.addr = SMPS_REG_ADDR_SMPS2,
- .core.pmic = &twl6030,
-
- .mm.value = 1139,
- .mm.addr = SMPS_REG_ADDR_SMPS5,
- .mm.pmic = &twl6030,
-};
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_basic_clocks(void)
-{
- u32 const clk_domains_essential[] = {
- (*prcm)->cm_l4per_clkstctrl,
- (*prcm)->cm_l3init_clkstctrl,
- (*prcm)->cm_memif_clkstctrl,
- (*prcm)->cm_l4cfg_clkstctrl,
- 0
- };
-
- u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)->cm_l3_gpmc_clkctrl,
- (*prcm)->cm_memif_emif_1_clkctrl,
- (*prcm)->cm_memif_emif_2_clkctrl,
- (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
- (*prcm)->cm_wkup_gpio1_clkctrl,
- (*prcm)->cm_l4per_gpio2_clkctrl,
- (*prcm)->cm_l4per_gpio3_clkctrl,
- (*prcm)->cm_l4per_gpio4_clkctrl,
- (*prcm)->cm_l4per_gpio5_clkctrl,
- (*prcm)->cm_l4per_gpio6_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_essential[] = {
- (*prcm)->cm_wkup_gptimer1_clkctrl,
- (*prcm)->cm_l3init_hsmmc1_clkctrl,
- (*prcm)->cm_l3init_hsmmc2_clkctrl,
- (*prcm)->cm_l4per_gptimer2_clkctrl,
- (*prcm)->cm_wkup_wdtimer2_clkctrl,
- (*prcm)->cm_l4per_uart3_clkctrl,
- (*prcm)->cm_l4per_i2c1_clkctrl,
- (*prcm)->cm_l4per_i2c2_clkctrl,
- (*prcm)->cm_l4per_i2c3_clkctrl,
- (*prcm)->cm_l4per_i2c4_clkctrl,
- 0
- };
-
- /* Enable optional additional functional clock for GPIO4 */
- setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
- GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable 96 MHz clock for MMC1 & MMC2 */
- setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
- setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
-
- /* Select 32KHz clock as the source of GPTIMER1 */
- setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
- GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
- /* Enable optional 48M functional clock for USB PHY */
- setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
- USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
-
- /* Enable 32 KHz clock for USB PHY */
- setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-void enable_basic_uboot_clocks(void)
-{
- u32 const clk_domains_essential[] = {
- 0
- };
-
- u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)->cm_l3init_hsusbotg_clkctrl,
- (*prcm)->cm_l3init_usbphy_clkctrl,
- (*prcm)->cm_clksel_usb_60mhz,
- (*prcm)->cm_l3init_hsusbtll_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_essential[] = {
- (*prcm)->cm_l4per_mcspi1_clkctrl,
- (*prcm)->cm_l3init_hsusbhost_clkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-void hw_data_init(void)
-{
- u32 omap_rev = omap_revision();
-
- (*prcm) = &omap4_prcm;
-
- switch (omap_rev) {
-
- case OMAP4430_ES1_0:
- *dplls_data = &omap4430_dplls_es1;
- *omap_vcores = &omap4430_volts_es1;
- break;
-
- case OMAP4430_ES2_0:
- *dplls_data = &omap4430_dplls_es20;
- *omap_vcores = &omap4430_volts;
- break;
-
- case OMAP4430_ES2_1:
- case OMAP4430_ES2_2:
- case OMAP4430_ES2_3:
- *dplls_data = &omap4430_dplls;
- *omap_vcores = &omap4430_volts;
- break;
-
- case OMAP4460_ES1_0:
- case OMAP4460_ES1_1:
- *dplls_data = &omap4460_dplls;
- *omap_vcores = &omap4460_volts;
- break;
-
- case OMAP4470_ES1_0:
- *dplls_data = &omap4470_dplls;
- *omap_vcores = &omap4470_volts;
- break;
-
- default:
- printf("\n INVALID OMAP REVISION ");
- }
-
- *ctrl = &omap4_ctrl;
-}
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
deleted file mode 100644
index 7c6638c..0000000
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- *
- * Common functions for OMAP4 based boards
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/armv7.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/sizes.h>
-#include <asm/emif.h>
-#include <asm/arch/gpio.h>
-#include <asm/omap_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
-
-static const struct gpio_bank gpio_bank_44xx[6] = {
- { (void *)OMAP44XX_GPIO1_BASE },
- { (void *)OMAP44XX_GPIO2_BASE },
- { (void *)OMAP44XX_GPIO3_BASE },
- { (void *)OMAP44XX_GPIO4_BASE },
- { (void *)OMAP44XX_GPIO5_BASE },
- { (void *)OMAP44XX_GPIO6_BASE },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Some tuning of IOs for optimal power and performance
- */
-void do_io_settings(void)
-{
- u32 lpddr2io;
-
- u32 omap4_rev = omap_revision();
-
- if (omap4_rev == OMAP4430_ES1_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
- else if (omap4_rev == OMAP4430_ES2_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
- else
- lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
-
- /* EMIF1 */
- writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
- writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
- /* No pull for GR10 as per hw team's recommendation */
- writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- (*ctrl)->control_lpddr2io1_2);
- writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
-
- /* EMIF2 */
- writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
- writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
- /* No pull for GR10 as per hw team's recommendation */
- writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- (*ctrl)->control_lpddr2io2_2);
- writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
-
- /*
- * Some of these settings (TRIM values) come from eFuse and are
- * in turn programmed in the eFuse at manufacturing time after
- * calibration of the device. Do the software over-ride only if
- * the device is not correctly trimmed
- */
- if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
-
- writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- (*ctrl)->control_ldosram_iva_voltage_ctrl);
-
- writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- (*ctrl)->control_ldosram_mpu_voltage_ctrl);
-
- writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- (*ctrl)->control_ldosram_core_voltage_ctrl);
- }
-
- /*
- * Over-ride the register
- * i. unconditionally for all 4430
- * ii. only if un-trimmed for 4460
- */
- if (!readl((*ctrl)->control_efuse_1))
- writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
-
- if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
- writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
-}
-#endif /* CONFIG_SPL_BUILD */
-
-/* dummy fuction for omap4 */
-void config_data_eye_leveling_samples(u32 emif_base)
-{
-}
-
-void init_omap_revision(void)
-{
- /*
- * For some of the ES2/ES1 boards ID_CODE is not reliable:
- * Also, ES1 and ES2 have different ARM revisions
- * So use ARM revision for identification
- */
- unsigned int arm_rev = cortex_rev();
-
- switch (arm_rev) {
- case MIDR_CORTEX_A9_R0P1:
- *omap_si_rev = OMAP4430_ES1_0;
- break;
- case MIDR_CORTEX_A9_R1P2:
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP4_CONTROL_ID_CODE_ES2_0:
- *omap_si_rev = OMAP4430_ES2_0;
- break;
- case OMAP4_CONTROL_ID_CODE_ES2_1:
- *omap_si_rev = OMAP4430_ES2_1;
- break;
- case OMAP4_CONTROL_ID_CODE_ES2_2:
- *omap_si_rev = OMAP4430_ES2_2;
- break;
- default:
- *omap_si_rev = OMAP4430_ES2_0;
- break;
- }
- break;
- case MIDR_CORTEX_A9_R1P3:
- *omap_si_rev = OMAP4430_ES2_3;
- break;
- case MIDR_CORTEX_A9_R2P10:
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP4470_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = OMAP4470_ES1_0;
- break;
- case OMAP4460_CONTROL_ID_CODE_ES1_1:
- *omap_si_rev = OMAP4460_ES1_1;
- break;
- case OMAP4460_CONTROL_ID_CODE_ES1_0:
- default:
- *omap_si_rev = OMAP4460_ES1_0;
- break;
- }
- break;
- default:
- *omap_si_rev = OMAP4430_SILICON_ID_INVALID;
- break;
- }
-}
-
-void omap_die_id(unsigned int *die_id)
-{
- die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
- die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
- die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
- die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
-}
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-void v7_outer_cache_enable(void)
-{
- omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
-}
-
-void v7_outer_cache_disable(void)
-{
- omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
-}
-#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
deleted file mode 100644
index a8600b1..0000000
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-if OMAP54XX
-
-choice
- prompt "OMAP5 board select"
- optional
-
-config TARGET_CM_T54
- bool "CompuLab CM-T54"
-
-config TARGET_OMAP5_UEVM
- bool "TI OMAP5 uEVM board"
-
-config TARGET_DRA7XX_EVM
- bool "TI DRA7XX"
- select TI_I2C_BOARD_DETECT
- select PHYS_64BIT
-
-config TARGET_AM57XX_EVM
- bool "AM57XX"
- select TI_I2C_BOARD_DETECT
-
-endchoice
-
-config SYS_SOC
- default "omap5"
-
-source "board/compulab/cm_t54/Kconfig"
-source "board/ti/omap5_uevm/Kconfig"
-source "board/ti/dra7xx/Kconfig"
-source "board/ti/am57xx/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
deleted file mode 100644
index 3caba86..0000000
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2000-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += boot.o
-obj-y += hwinit.o
-obj-y += emif.o
-obj-y += sdram.o
-obj-y += prcm-regs.o
-obj-y += hw_data.o
-obj-y += abb.o
-obj-y += fdt.o
-obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
diff --git a/arch/arm/cpu/armv7/omap5/boot.c b/arch/arm/cpu/armv7/omap5/boot.c
deleted file mode 100644
index 583becc..0000000
--- a/arch/arm/cpu/armv7/omap5/boot.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * OMAP5 boot
- *
- * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/omap_common.h>
-#include <spl.h>
-
-static u32 boot_devices[] = {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_NAND,
- BOOT_DEVICE_MMC1,
- BOOT_DEVICE_SATA,
- BOOT_DEVICE_XIP,
- BOOT_DEVICE_XIP,
- BOOT_DEVICE_SPI,
- BOOT_DEVICE_SPI,
-#else
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_NAND,
- BOOT_DEVICE_MMC1,
- BOOT_DEVICE_SATA,
- BOOT_DEVICE_XIP,
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_XIPWAIT,
-#endif
-};
-
-u32 omap_sys_boot_device(void)
-{
- u32 sys_boot;
-
- /* Grab the first 4 bits of the status register for SYS_BOOT. */
- sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 4) - 1);
-
- if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
- return BOOT_DEVICE_NONE;
-
- return boot_devices[sys_boot];
-}
diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
deleted file mode 100644
index 286ca86..0000000
--- a/arch/arm/cpu/armv7/omap5/config.mk
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# Copyright 2011 Linaro Limited
-#
-# Aneesh V <annesh@ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
-
-ifdef CONFIG_SPL_BUILD
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ALL-y += u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER
-else
-ALL-y += MLO
-endif
-else
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img
-endif
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/omap5/fdt.c b/arch/arm/cpu/armv7/omap5/fdt.c
deleted file mode 100644
index 0493cd1..0000000
--- a/arch/arm/cpu/armv7/omap5/fdt.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright 2016 Texas Instruments, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <malloc.h>
-
-#include <asm/omap_common.h>
-#include <asm/arch-omap5/sys_proto.h>
-
-#ifdef CONFIG_TI_SECURE_DEVICE
-
-/* Give zero values if not already defined */
-#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
-#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
-#endif
-#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
-#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
-#endif
-
-static u32 hs_irq_skip[] = {
- 8, /* Secure violation reporting interrupt */
- 15, /* One interrupt for SDMA by secure world */
- 118 /* One interrupt for Crypto DMA by secure world */
-};
-
-static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
-{
- const char *path;
- int offs;
- int ret;
- int len, i, old_cnt, new_cnt;
- u32 *temp;
- const u32 *p_data;
-
- /*
- * Increase the size of the fdt
- * so we have some breathing room
- */
- ret = fdt_increase_size(fdt, 512);
- if (ret < 0) {
- printf("Could not increase size of device tree: %s\n",
- fdt_strerror(ret));
- return ret;
- }
-
- /* Reserve IRQs that are used/needed by secure world */
- path = "/ocp/crossbar";
- offs = fdt_path_offset(fdt, path);
- if (offs < 0) {
- debug("Node %s not found.\n", path);
- return 0;
- }
-
- /* Get current entries */
- p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
- if (p_data)
- old_cnt = len / sizeof(u32);
- else
- old_cnt = 0;
-
- new_cnt = sizeof(hs_irq_skip) /
- sizeof(hs_irq_skip[0]);
-
- /* Create new/updated skip list for HS parts */
- temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
- for (i = 0; i < new_cnt; i++)
- temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
- for (i = 0; i < old_cnt; i++)
- temp[i + new_cnt] = p_data[i];
-
- /* Blow away old data and set new data */
- fdt_delprop(fdt, offs, "ti,irqs-skip");
- ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
- temp,
- (old_cnt + new_cnt) * sizeof(u32));
- free(temp);
-
- /* Check if the update worked */
- if (ret < 0) {
- printf("Could not add ti,irqs-skip property to node %s: %s\n",
- path, fdt_strerror(ret));
- return ret;
- }
-
- return 0;
-}
-
-static int ft_hs_disable_rng(void *fdt, bd_t *bd)
-{
- const char *path;
- int offs;
- int ret;
-
- /* Make HW RNG reserved for secure world use */
- path = "/ocp/rng";
- offs = fdt_path_offset(fdt, path);
- if (offs < 0) {
- debug("Node %s not found.\n", path);
- return 0;
- }
- ret = fdt_setprop_string(fdt, offs,
- "status", "disabled");
- if (ret < 0) {
- printf("Could not add status property to node %s: %s\n",
- path, fdt_strerror(ret));
- return ret;
- }
- return 0;
-}
-
-#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
- (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
-static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
-{
- const char *path;
- int offs;
- int ret;
- u32 temp[2];
-
- /*
- * Update SRAM reservations on secure devices. The OCMC RAM
- * is always reserved for secure use from the start of that
- * memory region
- */
- path = "/ocp/ocmcram@40300000/sram-hs";
- offs = fdt_path_offset(fdt, path);
- if (offs < 0) {
- debug("Node %s not found.\n", path);
- return 0;
- }
-
- /* relative start offset */
- temp[0] = cpu_to_fdt32(0);
- /* reservation size */
- temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
- CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
- fdt_delprop(fdt, offs, "reg");
- ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
- if (ret < 0) {
- printf("Could not add reg property to node %s: %s\n",
- path, fdt_strerror(ret));
- return ret;
- }
-
- return 0;
-}
-#else
-static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
-#endif
-
-static void ft_hs_fixups(void *fdt, bd_t *bd)
-{
- /* Check we are running on an HS/EMU device type */
- if (GP_DEVICE != get_device_type()) {
- if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
- (ft_hs_disable_rng(fdt, bd) == 0) &&
- (ft_hs_fixup_sram(fdt, bd) == 0))
- return;
- } else {
- printf("ERROR: Incorrect device type (GP) detected!");
- }
- /* Fixup failed or wrong device type */
- hang();
-}
-#else
-static void ft_hs_fixups(void *fdt, bd_t *bd)
-{
-}
-#endif
-
-/*
- * Place for general cpu/SoC FDT fixups. Board specific
- * fixups should remain in the board files which is where
- * this function should be called from.
- */
-void ft_cpu_setup(void *fdt, bd_t *bd)
-{
- ft_hs_fixups(fdt, bd);
-}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
deleted file mode 100644
index fc99135..0000000
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/*
- *
- * HW data initialization for OMAP5
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <palmas.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/arch/clock.h>
-#include <asm/omap_gpio.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-
-struct prcm_regs const **prcm =
- (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
-struct dplls const **dplls_data =
- (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
-struct vcores_data const **omap_vcores =
- (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
-struct omap_sys_ctrl_regs const **ctrl =
- (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
-
-/* OPP HIGH FREQUENCY for ES2.0 */
-static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
- {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OPP NOM FREQUENCY for ES1.0 */
-static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OPP LOW FREQUENCY for ES1.0 */
-static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OPP LOW FREQUENCY for ES2.0 */
-static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
- {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
-static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
- {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
- {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
- {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
- {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
- {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
- {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
- {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
- {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
- {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
- {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
- {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
- {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
- {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
- {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
- {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
- {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
- {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
- {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
- {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
- {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
- {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
- {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
- {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
- {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
- {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
- abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
-};
-
-/* ABE M & N values with sysclk2(22.5792 MHz) as input */
-static const struct dpll_params
- abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
- {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
- {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
- {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
- {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
- {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
- {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
-};
-
-struct dplls omap5_dplls_es1 = {
- .mpu = mpu_dpll_params_800mhz,
- .core = core_dpll_params_2128mhz_ddr532,
- .per = per_dpll_params_768mhz,
- .iva = iva_dpll_params_2330mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls omap5_dplls_es2 = {
- .mpu = mpu_dpll_params_1ghz,
- .core = core_dpll_params_2128mhz_ddr532_es2,
- .per = per_dpll_params_768mhz_es2,
- .iva = iva_dpll_params_2330mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- .abe = abe_dpll_params_sysclk_196608khz,
-#else
- .abe = &abe_dpll_params_32k_196608khz,
-#endif
- .usb = usb_dpll_params_1920mhz,
- .ddr = NULL
-};
-
-struct dplls dra7xx_dplls = {
- .mpu = mpu_dpll_params_1ghz,
- .core = core_dpll_params_2128mhz_dra7xx,
- .per = per_dpll_params_768mhz_dra7xx,
- .abe = abe_dpll_params_sysclk2_361267khz,
- .iva = iva_dpll_params_2330mhz_dra7xx,
- .usb = usb_dpll_params_1920mhz,
- .ddr = ddr_dpll_params_2128mhz,
- .gmac = gmac_dpll_params_2000mhz,
-};
-
-struct dplls dra72x_dplls = {
- .mpu = mpu_dpll_params_1ghz,
- .core = core_dpll_params_2128mhz_dra7xx,
- .per = per_dpll_params_768mhz_dra7xx,
- .abe = abe_dpll_params_sysclk2_361267khz,
- .iva = iva_dpll_params_2330mhz_dra7xx,
- .usb = usb_dpll_params_1920mhz,
- .ddr = ddr_dpll_params_2664mhz,
- .gmac = gmac_dpll_params_2000mhz,
-};
-
-struct pmic_data palmas = {
- .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
- .step = 10000, /* 10 mV represented in uV */
- /*
- * Offset codes 1-6 all give the base voltage in Palmas
- * Offset code 0 switches OFF the SMPS
- */
- .start_code = 6,
- .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
- .pmic_bus_init = sri2c_init,
- .pmic_write = omap_vc_bypass_send_value,
- .gpio_en = 0,
-};
-
-/* The TPS659038 and TPS65917 are software-compatible, use common struct */
-struct pmic_data tps659038 = {
- .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
- .step = 10000, /* 10 mV represented in uV */
- /*
- * Offset codes 1-6 all give the base voltage in Palmas
- * Offset code 0 switches OFF the SMPS
- */
- .start_code = 6,
- .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
- .pmic_bus_init = gpi2c_init,
- .pmic_write = palmas_i2c_write_u8,
- .gpio_en = 0,
-};
-
-struct vcores_data omap5430_volts = {
- .mpu.value = VDD_MPU,
- .mpu.addr = SMPS_REG_ADDR_12_MPU,
- .mpu.pmic = &palmas,
-
- .core.value = VDD_CORE,
- .core.addr = SMPS_REG_ADDR_8_CORE,
- .core.pmic = &palmas,
-
- .mm.value = VDD_MM,
- .mm.addr = SMPS_REG_ADDR_45_IVA,
- .mm.pmic = &palmas,
-};
-
-struct vcores_data omap5430_volts_es2 = {
- .mpu.value = VDD_MPU_ES2,
- .mpu.addr = SMPS_REG_ADDR_12_MPU,
- .mpu.pmic = &palmas,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .core.value = VDD_CORE_ES2,
- .core.addr = SMPS_REG_ADDR_8_CORE,
- .core.pmic = &palmas,
-
- .mm.value = VDD_MM_ES2,
- .mm.addr = SMPS_REG_ADDR_45_IVA,
- .mm.pmic = &palmas,
- .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
-};
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_basic_clocks(void)
-{
- u32 const clk_domains_essential[] = {
- (*prcm)->cm_l4per_clkstctrl,
- (*prcm)->cm_l3init_clkstctrl,
- (*prcm)->cm_memif_clkstctrl,
- (*prcm)->cm_l4cfg_clkstctrl,
-#ifdef CONFIG_DRIVER_TI_CPSW
- (*prcm)->cm_gmac_clkstctrl,
-#endif
- 0
- };
-
- u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)->cm_l3_gpmc_clkctrl,
- (*prcm)->cm_memif_emif_1_clkctrl,
- (*prcm)->cm_memif_emif_2_clkctrl,
- (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
- (*prcm)->cm_wkup_gpio1_clkctrl,
- (*prcm)->cm_l4per_gpio2_clkctrl,
- (*prcm)->cm_l4per_gpio3_clkctrl,
- (*prcm)->cm_l4per_gpio4_clkctrl,
- (*prcm)->cm_l4per_gpio5_clkctrl,
- (*prcm)->cm_l4per_gpio6_clkctrl,
- (*prcm)->cm_l4per_gpio7_clkctrl,
- (*prcm)->cm_l4per_gpio8_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_essential[] = {
- (*prcm)->cm_wkup_gptimer1_clkctrl,
- (*prcm)->cm_l3init_hsmmc1_clkctrl,
- (*prcm)->cm_l3init_hsmmc2_clkctrl,
- (*prcm)->cm_l4per_gptimer2_clkctrl,
- (*prcm)->cm_wkup_wdtimer2_clkctrl,
- (*prcm)->cm_l4per_uart3_clkctrl,
- (*prcm)->cm_l4per_i2c1_clkctrl,
-#ifdef CONFIG_DRIVER_TI_CPSW
- (*prcm)->cm_gmac_gmac_clkctrl,
-#endif
-
-#ifdef CONFIG_TI_QSPI
- (*prcm)->cm_l4per_qspi_clkctrl,
-#endif
- 0
- };
-
- /* Enable optional additional functional clock for GPIO4 */
- setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
- GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable 96 MHz clock for MMC1 & MMC2 */
- setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
- setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
-
- /* Set the correct clock dividers for mmc */
- setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
- setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-
- /* Select 32KHz clock as the source of GPTIMER1 */
- setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
- GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-
-#ifdef CONFIG_TI_QSPI
- setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
-#endif
-
- /* Enable SCRM OPT clocks for PER and CORE dpll */
- setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
- OPTFCLKEN_SCRM_PER_MASK);
- setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
- OPTFCLKEN_SCRM_CORE_MASK);
-}
-
-void enable_basic_uboot_clocks(void)
-{
- u32 const clk_domains_essential[] = {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- (*prcm)->cm_ipu_clkstctrl,
-#endif
- 0
- };
-
- u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)->cm_l3init_hsusbtll_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_essential[] = {
- (*prcm)->cm_l4per_mcspi1_clkctrl,
- (*prcm)->cm_l4per_i2c2_clkctrl,
- (*prcm)->cm_l4per_i2c3_clkctrl,
- (*prcm)->cm_l4per_i2c4_clkctrl,
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- (*prcm)->cm_ipu_i2c5_clkctrl,
-#else
- (*prcm)->cm_l4per_i2c5_clkctrl,
-#endif
- (*prcm)->cm_l3init_hsusbhost_clkctrl,
- (*prcm)->cm_l3init_fsusb_clkctrl,
- 0
- };
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-#ifdef CONFIG_TI_EDMA3
-void enable_edma3_clocks(void)
-{
- u32 const clk_domains_edma3[] = {
- 0
- };
-
- u32 const clk_modules_hw_auto_edma3[] = {
- (*prcm)->cm_l3main1_tptc1_clkctrl,
- (*prcm)->cm_l3main1_tptc2_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_edma3[] = {
- 0
- };
-
- do_enable_clocks(clk_domains_edma3,
- clk_modules_hw_auto_edma3,
- clk_modules_explicit_en_edma3,
- 1);
-}
-
-void disable_edma3_clocks(void)
-{
- u32 const clk_domains_edma3[] = {
- 0
- };
-
- u32 const clk_modules_disable_edma3[] = {
- (*prcm)->cm_l3main1_tptc1_clkctrl,
- (*prcm)->cm_l3main1_tptc2_clkctrl,
- 0
- };
-
- do_disable_clocks(clk_domains_edma3,
- clk_modules_disable_edma3,
- 1);
-}
-#endif
-
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-void enable_usb_clocks(int index)
-{
- u32 cm_l3init_usb_otg_ss_clkctrl = 0;
-
- if (index == 0) {
- cm_l3init_usb_otg_ss_clkctrl =
- (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
- /* Enable 960 MHz clock for dwc3 */
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
- OPTFCLKEN_REFCLK960M);
-
- /* Enable 32 KHz clock for USB_PHY1 */
- setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
- /* Enable 32 KHz clock for USB_PHY3 */
- if (is_dra7xx())
- setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
- } else if (index == 1) {
- cm_l3init_usb_otg_ss_clkctrl =
- (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
- /* Enable 960 MHz clock for dwc3 */
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
- OPTFCLKEN_REFCLK960M);
-
- /* Enable 32 KHz clock for dwc3 */
- setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
- /* Enable 60 MHz clock for USB2PHY2 */
- setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
- L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
- }
-
- u32 const clk_domains_usb[] = {
- 0
- };
-
- u32 const clk_modules_hw_auto_usb[] = {
- (*prcm)->cm_l3init_ocp2scp1_clkctrl,
- cm_l3init_usb_otg_ss_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_usb[] = {
- 0
- };
-
- do_enable_clocks(clk_domains_usb,
- clk_modules_hw_auto_usb,
- clk_modules_explicit_en_usb,
- 1);
-}
-
-void disable_usb_clocks(int index)
-{
- u32 cm_l3init_usb_otg_ss_clkctrl = 0;
-
- if (index == 0) {
- cm_l3init_usb_otg_ss_clkctrl =
- (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
- /* Disable 960 MHz clock for dwc3 */
- clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
- OPTFCLKEN_REFCLK960M);
-
- /* Disable 32 KHz clock for USB_PHY1 */
- clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
- /* Disable 32 KHz clock for USB_PHY3 */
- if (is_dra7xx())
- clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
- } else if (index == 1) {
- cm_l3init_usb_otg_ss_clkctrl =
- (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
- /* Disable 960 MHz clock for dwc3 */
- clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
- OPTFCLKEN_REFCLK960M);
-
- /* Disable 32 KHz clock for dwc3 */
- clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
- /* Disable 60 MHz clock for USB2PHY2 */
- clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
- L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
- }
-
- u32 const clk_domains_usb[] = {
- 0
- };
-
- u32 const clk_modules_disable[] = {
- (*prcm)->cm_l3init_ocp2scp1_clkctrl,
- cm_l3init_usb_otg_ss_clkctrl,
- 0
- };
-
- do_disable_clocks(clk_domains_usb,
- clk_modules_disable,
- 1);
-}
-#endif
-
-const struct ctrl_ioregs ioregs_omap5430 = {
- .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
- .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
- .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
-};
-
-const struct ctrl_ioregs ioregs_omap5432_es1 = {
- .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- .ctrl_lpddr2ch = 0x0,
- .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
- .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
- .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
- .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
- .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-};
-
-const struct ctrl_ioregs ioregs_omap5432_es2 = {
- .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
- .ctrl_lpddr2ch = 0x0,
- .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
- .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
- .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
- .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
- .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-};
-
-const struct ctrl_ioregs ioregs_dra7xx_es1 = {
- .ctrl_ddrch = 0x40404040,
- .ctrl_lpddr2ch = 0x40404040,
- .ctrl_ddr3ch = 0x80808080,
- .ctrl_ddrio_0 = 0x00094A40,
- .ctrl_ddrio_1 = 0x04A52000,
- .ctrl_ddrio_2 = 0x84210000,
- .ctrl_emif_sdram_config_ext = 0x0001C1A7,
- .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
- .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
-};
-
-const struct ctrl_ioregs ioregs_dra72x_es1 = {
- .ctrl_ddrch = 0x40404040,
- .ctrl_lpddr2ch = 0x40404040,
- .ctrl_ddr3ch = 0x60606080,
- .ctrl_ddrio_0 = 0x00094A40,
- .ctrl_ddrio_1 = 0x04A52000,
- .ctrl_ddrio_2 = 0x84210000,
- .ctrl_emif_sdram_config_ext = 0x0001C1A7,
- .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
- .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
-};
-
-const struct ctrl_ioregs ioregs_dra72x_es2 = {
- .ctrl_ddrch = 0x40404040,
- .ctrl_lpddr2ch = 0x40404040,
- .ctrl_ddr3ch = 0x60606060,
- .ctrl_ddrio_0 = 0x00094A40,
- .ctrl_ddrio_1 = 0x00000000,
- .ctrl_ddrio_2 = 0x00000000,
- .ctrl_emif_sdram_config_ext = 0x0001C1A7,
- .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
- .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
-};
-
-void __weak hw_data_init(void)
-{
- u32 omap_rev = omap_revision();
-
- switch (omap_rev) {
-
- case OMAP5430_ES1_0:
- case OMAP5432_ES1_0:
- *prcm = &omap5_es1_prcm;
- *dplls_data = &omap5_dplls_es1;
- *omap_vcores = &omap5430_volts;
- *ctrl = &omap5_ctrl;
- break;
-
- case OMAP5430_ES2_0:
- case OMAP5432_ES2_0:
- *prcm = &omap5_es2_prcm;
- *dplls_data = &omap5_dplls_es2;
- *omap_vcores = &omap5430_volts_es2;
- *ctrl = &omap5_ctrl;
- break;
-
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- case DRA752_ES2_0:
- *prcm = &dra7xx_prcm;
- *dplls_data = &dra7xx_dplls;
- *ctrl = &dra7xx_ctrl;
- break;
-
- case DRA722_ES1_0:
- case DRA722_ES2_0:
- *prcm = &dra7xx_prcm;
- *dplls_data = &dra72x_dplls;
- *ctrl = &dra7xx_ctrl;
- break;
-
- default:
- printf("\n INVALID OMAP REVISION ");
- }
-}
-
-void get_ioregs(const struct ctrl_ioregs **regs)
-{
- u32 omap_rev = omap_revision();
-
- switch (omap_rev) {
- case OMAP5430_ES1_0:
- case OMAP5430_ES2_0:
- *regs = &ioregs_omap5430;
- break;
- case OMAP5432_ES1_0:
- *regs = &ioregs_omap5432_es1;
- break;
- case OMAP5432_ES2_0:
- *regs = &ioregs_omap5432_es2;
- break;
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- case DRA752_ES2_0:
- *regs = &ioregs_dra7xx_es1;
- break;
- case DRA722_ES1_0:
- *regs = &ioregs_dra72x_es1;
- break;
- case DRA722_ES2_0:
- *regs = &ioregs_dra72x_es2;
- break;
-
- default:
- printf("\n INVALID OMAP REVISION ");
- }
-}
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
deleted file mode 100644
index e3ac8bb..0000000
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- *
- * Functions for omap5 based boards.
- *
- * (C) Copyright 2011
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- * Sricharan <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/armv7.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clock.h>
-#include <linux/sizes.h>
-#include <asm/utils.h>
-#include <asm/arch/gpio.h>
-#include <asm/emif.h>
-#include <asm/omap_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
-
-#ifndef CONFIG_DM_GPIO
-static struct gpio_bank gpio_bank_54xx[8] = {
- { (void *)OMAP54XX_GPIO1_BASE },
- { (void *)OMAP54XX_GPIO2_BASE },
- { (void *)OMAP54XX_GPIO3_BASE },
- { (void *)OMAP54XX_GPIO4_BASE },
- { (void *)OMAP54XX_GPIO5_BASE },
- { (void *)OMAP54XX_GPIO6_BASE },
- { (void *)OMAP54XX_GPIO7_BASE },
- { (void *)OMAP54XX_GPIO8_BASE },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
-#endif
-
-void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
-{
- int i;
- struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
- for (i = 0; i < size; i++, pad++)
- writel(pad->val, base + pad->offset);
-}
-
-#ifdef CONFIG_SPL_BUILD
-/* LPDDR2 specific IO settings */
-static void io_settings_lpddr2(void)
-{
- const struct ctrl_ioregs *ioregs;
-
- get_ioregs(&ioregs);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
- writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
- writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
- writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
-}
-
-/* DDR3 specific IO settings */
-static void io_settings_ddr3(void)
-{
- u32 io_settings = 0;
- const struct ctrl_ioregs *ioregs;
-
- get_ioregs(&ioregs);
- writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
-
- writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
- writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
-
- writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
- writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
-
- if (!is_dra7xx()) {
- writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
- }
-
- /* omap5432 does not use lpddr2 */
- writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
-
- writel(ioregs->ctrl_emif_sdram_config_ext,
- (*ctrl)->control_emif1_sdram_config_ext);
- if (!is_dra72x())
- writel(ioregs->ctrl_emif_sdram_config_ext,
- (*ctrl)->control_emif2_sdram_config_ext);
-
- if (is_omap54xx()) {
- /* Disable DLL select */
- io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
- & 0xFFEFFFFF);
- writel(io_settings,
- (*ctrl)->control_port_emif1_sdram_config);
-
- io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
- & 0xFFEFFFFF);
- writel(io_settings,
- (*ctrl)->control_port_emif2_sdram_config);
- } else {
- writel(ioregs->ctrl_ddr_ctrl_ext_0,
- (*ctrl)->control_ddr_control_ext_0);
- }
-}
-
-/*
- * Some tuning of IOs for optimal power and performance
- */
-void do_io_settings(void)
-{
- u32 io_settings = 0, mask = 0;
- struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
- /* Impedance settings EMMC, C2C 1,2, hsi2 */
- mask = (ds_mask << 2) | (ds_mask << 8) |
- (ds_mask << 16) | (ds_mask << 18);
- io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
- (~mask);
- io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
- (ds_45_ohm << 18) | (ds_60_ohm << 2);
- writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
-
- /* Impedance settings Mcspi2 */
- mask = (ds_mask << 30);
- io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
- (~mask);
- io_settings |= (ds_60_ohm << 30);
- writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
-
- /* Impedance settings C2C 3,4 */
- mask = (ds_mask << 14) | (ds_mask << 16);
- io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
- (~mask);
- io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
- writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
-
- /* Slew rate settings EMMC, C2C 1,2 */
- mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
- io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
- (~mask);
- io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
- writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
-
- /* Slew rate settings hsi2, Mcspi2 */
- mask = (sc_mask << 24) | (sc_mask << 28);
- io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
- (~mask);
- io_settings |= (sc_fast << 28) | (sc_fast << 24);
- writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
-
- /* Slew rate settings C2C 3,4 */
- mask = (sc_mask << 16) | (sc_mask << 18);
- io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
- (~mask);
- io_settings |= (sc_na << 16) | (sc_na << 18);
- writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
-
- /* impedance and slew rate settings for usb */
- mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
- (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
- io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
- (~mask);
- io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
- (ds_60_ohm << 23) | (sc_fast << 20) |
- (sc_fast << 17) | (sc_fast << 14);
- writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
-
- if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
- io_settings_lpddr2();
- else
- io_settings_ddr3();
-}
-
-static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
- {0x45, 0x1}, /* 12 MHz */
- {-1, -1}, /* 13 MHz */
- {0x63, 0x2}, /* 16.8 MHz */
- {0x57, 0x2}, /* 19.2 MHz */
- {0x20, 0x1}, /* 26 MHz */
- {-1, -1}, /* 27 MHz */
- {0x41, 0x3} /* 38.4 MHz */
-};
-
-void srcomp_enable(void)
-{
- u32 srcomp_value, mul_factor, div_factor, clk_val, i;
- u32 sysclk_ind = get_sys_clk_index();
- u32 omap_rev = omap_revision();
-
- if (!is_omap54xx())
- return;
-
- mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
- div_factor = srcomp_parameters[sysclk_ind].divide_factor;
-
- for (i = 0; i < 4; i++) {
- srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &=
- ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
- srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
- (div_factor << DIVIDE_FACTOR_XS_SHIFT);
- writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
- }
-
- if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
- clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
- clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
- writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
-
- for (i = 0; i < 4; i++) {
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &= ~PWRDWN_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
-
- while (((readl((*ctrl)->control_srcomp_north_side + i*4)
- & SRCODE_READ_XS_MASK) >>
- SRCODE_READ_XS_SHIFT) == 0)
- ;
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &= ~OVERRIDE_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
- }
- } else {
- srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
- srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
- DIVIDE_FACTOR_XS_MASK);
- srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
- (div_factor << DIVIDE_FACTOR_XS_SHIFT);
- writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-
- for (i = 0; i < 4; i++) {
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &= ~OVERRIDE_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
- }
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_east_side_wkup);
- srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
- writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_east_side_wkup);
- srcomp_value &= ~OVERRIDE_XS_MASK;
- writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-
- clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
- clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
- writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
-
- clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
- clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
- writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
-
- for (i = 0; i < 4; i++) {
- while (((readl((*ctrl)->control_srcomp_north_side + i*4)
- & SRCODE_READ_XS_MASK) >>
- SRCODE_READ_XS_SHIFT) == 0)
- ;
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_north_side + i*4);
- srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
- writel(srcomp_value,
- (*ctrl)->control_srcomp_north_side + i*4);
- }
-
- while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
- SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
- ;
-
- srcomp_value =
- readl((*ctrl)->control_srcomp_east_side_wkup);
- srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
- writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
- }
-}
-#endif
-
-void config_data_eye_leveling_samples(u32 emif_base)
-{
- const struct ctrl_ioregs *ioregs;
-
- get_ioregs(&ioregs);
-
- /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
- if (emif_base == EMIF1_BASE)
- writel(ioregs->ctrl_emif_sdram_config_ext_final,
- (*ctrl)->control_emif1_sdram_config_ext);
- else if (emif_base == EMIF2_BASE)
- writel(ioregs->ctrl_emif_sdram_config_ext_final,
- (*ctrl)->control_emif2_sdram_config_ext);
-}
-
-void init_cpu_configuration(void)
-{
- u32 l2actlr;
-
- asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
- /*
- * L2ACTLR: Ensure to enable the following:
- * 3: Disable clean/evict push to external
- * 4: Disable WriteUnique and WriteLineUnique transactions from master
- * 8: Disable DVM/CMO message broadcast
- */
- l2actlr |= 0x118;
- omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
-}
-
-void init_omap_revision(void)
-{
- /*
- * For some of the ES2/ES1 boards ID_CODE is not reliable:
- * Also, ES1 and ES2 have different ARM revisions
- * So use ARM revision for identification
- */
- unsigned int rev = cortex_rev();
-
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP5430_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = OMAP5430_ES1_0;
- if (rev == MIDR_CORTEX_A15_R2P2)
- *omap_si_rev = OMAP5430_ES2_0;
- break;
- case OMAP5432_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = OMAP5432_ES1_0;
- if (rev == MIDR_CORTEX_A15_R2P2)
- *omap_si_rev = OMAP5432_ES2_0;
- break;
- case OMAP5430_CONTROL_ID_CODE_ES2_0:
- *omap_si_rev = OMAP5430_ES2_0;
- break;
- case OMAP5432_CONTROL_ID_CODE_ES2_0:
- *omap_si_rev = OMAP5432_ES2_0;
- break;
- case DRA752_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = DRA752_ES1_0;
- break;
- case DRA752_CONTROL_ID_CODE_ES1_1:
- *omap_si_rev = DRA752_ES1_1;
- break;
- case DRA752_CONTROL_ID_CODE_ES2_0:
- *omap_si_rev = DRA752_ES2_0;
- break;
- case DRA722_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = DRA722_ES1_0;
- break;
- case DRA722_CONTROL_ID_CODE_ES2_0:
- *omap_si_rev = DRA722_ES2_0;
- break;
- default:
- *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
- }
- init_cpu_configuration();
-}
-
-void omap_die_id(unsigned int *die_id)
-{
- die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
- die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
- die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
- die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
-}
-
-void reset_cpu(ulong ignored)
-{
- u32 omap_rev = omap_revision();
-
- /*
- * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
- * So use cold reset in case instead.
- */
- if (omap_rev == OMAP5430_ES1_0)
- writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
- else
- writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
-}
-
-u32 warm_reset(void)
-{
- return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
-}
-
-void setup_warmreset_time(void)
-{
- u32 rst_time, rst_val;
-
-#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
- rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
-#else
- rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
-#endif
- rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
-
- if (rst_time > RSTTIME1_MASK)
- rst_time = RSTTIME1_MASK;
-
- rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
- rst_val |= rst_time;
- writel(rst_val, (*prcm)->prm_rsttime);
-}
-
-void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
- u32 cpu_rev_comb, u32 cpu_variant,
- u32 cpu_rev)
-{
- omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
-}
-
-void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
- u32 cpu_variant, u32 cpu_rev)
-{
-
-#ifdef CONFIG_ARM_ERRATA_801819
- /*
- * DRA72x processors are uniprocessors and DONOT have
- * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
- * Extensions) Hence the erratum workaround is not applicable for
- * DRA72x processors.
- */
- if (is_dra72x())
- acr &= ~((0x3 << 23) | (0x3 << 25));
-#endif
- omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
-}
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index f80f6e2..95b962d 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -187,7 +187,7 @@
.weak psci_get_cpu_id
/* Imported from Linux kernel */
-LENTRY(v7_flush_dcache_all)
+ENTRY(psci_v7_flush_dcache_all)
stmfd sp!, {r4-r5, r7, r9-r11, lr}
dmb @ ensure ordering with previous memory accesses
mrc p15, 1, r0, c0, c0, 1 @ read clidr
@@ -234,7 +234,7 @@
isb
ldmfd sp!, {r4-r5, r7, r9-r11, lr}
bx lr
-ENDPROC(v7_flush_dcache_all)
+ENDPROC(psci_v7_flush_dcache_all)
ENTRY(psci_disable_smp)
mrc p15, 0, r0, c1, c0, 1 @ ACTLR
@@ -258,13 +258,17 @@
ENTRY(psci_cpu_off_common)
push {lr}
+ bl psci_v7_flush_dcache_all
+
+ clrex @ Why???
+
mrc p15, 0, r0, c1, c0, 0 @ SCTLR
bic r0, r0, #(1 << 2) @ Clear C bit
mcr p15, 0, r0, c1, c0, 0 @ SCTLR
isb
dsb
- bl v7_flush_dcache_all
+ bl psci_v7_flush_dcache_all
clrex @ Why???
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 691e5d3..7eee54b 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -17,6 +17,7 @@
#include <config.h>
#include <asm/system.h>
#include <linux/linkage.h>
+#include <asm/armv7.h>
/*************************************************************************
*
@@ -30,11 +31,24 @@
.globl reset
.globl save_boot_params_ret
+#ifdef CONFIG_ARMV7_LPAE
+ .global switch_to_hypervisor_ret
+#endif
reset:
/* Allow the board to save important registers */
b save_boot_params
save_boot_params_ret:
+#ifdef CONFIG_ARMV7_LPAE
+/*
+ * check for Hypervisor support
+ */
+ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
+ and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
+ cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
+ beq switch_to_hypervisor
+switch_to_hypervisor_ret:
+#endif
/*
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
* except if in HYP mode already
@@ -103,6 +117,13 @@
ENDPROC(save_boot_params)
.weak save_boot_params
+#ifdef CONFIG_ARMV7_LPAE
+ENTRY(switch_to_hypervisor)
+ b switch_to_hypervisor_ret
+ENDPROC(switch_to_hypervisor)
+ .weak switch_to_hypervisor
+#endif
+
/*************************************************************************
*
* cpu_init_cp15
diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile
index 68cb756..2945377 100644
--- a/arch/arm/cpu/armv7/vf610/Makefile
+++ b/arch/arm/cpu/armv7/vf610/Makefile
@@ -6,3 +6,8 @@
obj-y += generic.o
obj-y += timer.o
+
+MKIMAGEFLAGS_u-boot.vyb = -T vybridimage
+
+u-boot.vyb: u-boot.imx
+ $(call if_changed,mkimage)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 08b9ef4..50eb0c6 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -322,7 +322,7 @@
{
char soc[6];
- strcat(soc, "vf");
+ strcpy(soc, "vf");
strcat(soc, soc_type);
setenv("soc", soc);
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 7e1fc4c..22dce88 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -21,4 +21,64 @@
- Reserve the code for the spin-table and the release address
via a /memreserve/ region in the Device Tree.
+config PSCI_RESET
+ bool "Use PSCI for reset and shutdown"
+ default y
+ depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
+ !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
+ !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+ !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
+ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
+ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
+ !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
+ help
+ Most armv8 systems have PSCI support enabled in EL3, either through
+ ARM Trusted Firmware or other firmware.
+
+ On these systems, we do not need to implement system reset manually,
+ but can instead rely on higher level firmware to deal with it.
+
+ Select Y here to make use of PSCI calls for system reset
+
+config ARMV8_PSCI
+ bool "Enable PSCI support" if EXPERT
+ default n
+ help
+ PSCI is Power State Coordination Interface defined by ARM.
+ The PSCI in U-boot provides a general framework and each platform
+ can implement their own specific PSCI functions.
+ Say Y here to enable PSCI support on ARMv8 platform.
+
+config ARMV8_PSCI_NR_CPUS
+ int "Maximum supported CPUs for PSCI"
+ depends on ARMV8_PSCI
+ default 4
+ help
+ The maximum number of CPUs supported in the PSCI firmware.
+ It is no problem to set a larger value than the number of CPUs in
+ the actual hardware implementation.
+
+config ARMV8_PSCI_CPUS_PER_CLUSTER
+ int "Number of CPUs per cluster"
+ depends on ARMV8_PSCI
+ default 0
+ help
+ The number of CPUs per cluster, suppose each cluster has same number
+ of CPU cores, platforms with asymmetric clusters don't apply here.
+ A value 0 or no definition of it works for single cluster system.
+ System with multi-cluster should difine their own exact value.
+
+if SYS_HAS_ARMV8_SECURE_BASE
+
+config ARMV8_SECURE_BASE
+ hex "Secure address for PSCI image"
+ depends on ARMV8_PSCI
+ help
+ Address for placing the PSCI text, data and stack sections.
+ If not defined, the PSCI sections are placed together with the u-boot
+ but platform can choose to place PSCI code image separately in other
+ places such as some secure RAM built-in SOC etc.
+
+endif
+
endif
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dea1465..28ba786 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -25,3 +25,4 @@
obj-$(CONFIG_S32V234) += s32v234/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 46f25e6..f1deaa7 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -150,11 +150,23 @@
ret
ENDPROC(__asm_invalidate_icache_all)
-ENTRY(__asm_flush_l3_cache)
+ENTRY(__asm_invalidate_l3_dcache)
mov x0, #0 /* return status as success */
ret
-ENDPROC(__asm_flush_l3_cache)
- .weak __asm_flush_l3_cache
+ENDPROC(__asm_invalidate_l3_dcache)
+ .weak __asm_invalidate_l3_dcache
+
+ENTRY(__asm_flush_l3_dcache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_flush_l3_dcache)
+ .weak __asm_flush_l3_dcache
+
+ENTRY(__asm_invalidate_l3_icache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_invalidate_l3_icache)
+ .weak __asm_invalidate_l3_icache
/*
* void __asm_switch_ttbr(ulong new_ttbr)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index cd3f6c1..6c5630c 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -421,19 +421,20 @@
void invalidate_dcache_all(void)
{
__asm_invalidate_dcache_all();
+ __asm_invalidate_l3_dcache();
}
/*
* Performs a clean & invalidation of the entire data cache at all levels.
* This function needs to be inline to avoid using stack.
- * __asm_flush_l3_cache return status of timeout
+ * __asm_flush_l3_dcache return status of timeout
*/
inline void flush_dcache_all(void)
{
int ret;
__asm_flush_dcache_all();
- ret = __asm_flush_l3_cache();
+ ret = __asm_flush_l3_dcache();
if (ret)
debug("flushing dcache returns 0x%x\n", ret);
else
@@ -623,7 +624,7 @@
void icache_enable(void)
{
- __asm_invalidate_icache_all();
+ invalidate_icache_all();
set_sctlr(get_sctlr() | CR_I);
}
@@ -640,6 +641,7 @@
void invalidate_icache_all(void)
{
__asm_invalidate_icache_all();
+ __asm_invalidate_l3_icache();
}
#else /* CONFIG_SYS_ICACHE_OFF */
diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk
index 6850258..27b66d4 100644
--- a/arch/arm/cpu/armv8/config.mk
+++ b/arch/arm/cpu/armv8/config.mk
@@ -8,3 +8,7 @@
PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)
+
+EFI_LDS := elf_aarch64_efi.lds
+EFI_CRT0 := crt0_aarch64_efi.o
+EFI_RELOC := reloc_aarch64_efi.o
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 9ffb49c..3a5afe8 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/psci.h>
+#include <asm/system.h>
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
@@ -13,7 +14,8 @@
int psci_update_dt(void *fdt)
{
#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
+
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
* If the PSCI in SEC Firmware didn't work, avoid to update the
@@ -25,6 +27,13 @@
return 0;
#endif
fdt_psci(fdt);
+
+#if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE)
+ /* secure code lives in RAM, keep it alive */
+ fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+ __secure_end - __secure_start);
+#endif
+
#endif
#endif
return 0;
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index e06c3cc..5dcb5e2 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <command.h>
#include <asm/system.h>
+#include <asm/secure.h>
#include <linux/compiler.h>
int cleanup_before_linux(void)
@@ -41,3 +42,24 @@
return 0;
}
+
+#ifdef CONFIG_ARMV8_PSCI
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+ size_t sz = __secure_end - __secure_start;
+
+ memcpy((void *)CONFIG_ARMV8_SECURE_BASE, __secure_start, sz);
+ flush_dcache_range(CONFIG_ARMV8_SECURE_BASE,
+ CONFIG_ARMV8_SECURE_BASE + sz + 1);
+ invalidate_icache_all();
+#endif
+}
+
+void armv8_setup_psci(void)
+{
+ relocate_secure_section();
+ secure_ram_addr(psci_setup_vectors)();
+ secure_ram_addr(psci_arch_init)();
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
new file mode 100644
index 0000000..de0b580
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -0,0 +1,170 @@
+config ARCH_LS1012A
+ bool
+ select FSL_LSCH2
+ select SYS_FSL_DDR_BE
+ select SYS_FSL_MMDC
+ select SYS_FSL_ERRATUM_A010315
+
+config ARCH_LS1043A
+ bool
+ select FSL_LSCH2
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A009660
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009929
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+
+config ARCH_LS1046A
+ bool
+ select FSL_LSCH2
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008511
+ select SYS_FSL_ERRATUM_A009801
+ select SYS_FSL_ERRATUM_A009803
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_SRDS_2
+
+config ARCH_LS2080A
+ bool
+ select FSL_LSCH3
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_LE
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_HAS_DP_DDR
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
+ select SYS_FSL_SRDS_2
+ select SYS_FSL_ERRATUM_A008336
+ select SYS_FSL_ERRATUM_A008511
+ select SYS_FSL_ERRATUM_A008514
+ select SYS_FSL_ERRATUM_A008585
+ select SYS_FSL_ERRATUM_A009635
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009801
+ select SYS_FSL_ERRATUM_A009803
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010165
+
+config FSL_LSCH2
+ bool
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+
+config FSL_LSCH3
+ bool
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+
+menu "Layerscape architecture"
+ depends on FSL_LSCH2 || FSL_LSCH3
+
+menu "Layerscape PPA"
+config FSL_LS_PPA
+ bool "FSL Layerscape PPA firmware support"
+ depends on !ARMV8_PSCI
+ depends on ARCH_LS1043A || ARCH_LS1046A
+ select FSL_PPA_ARMV8_PSCI
+ help
+ The FSL Primary Protected Application (PPA) is a software component
+ which is loaded during boot stage, and then remains resident in RAM
+ and runs in the TrustZone after boot.
+ Say y to enable it.
+
+config FSL_PPA_ARMV8_PSCI
+ bool "PSCI implementation in PPA firmware"
+ depends on FSL_LS_PPA
+ help
+ This config enables the ARMv8 PSCI implementation in PPA firmware.
+ This is a private PSCI implementation and different from those
+ implemented under the common ARMv8 PSCI framework.
+endmenu
+
+config SYS_FSL_ERRATUM_A010315
+ bool "Workaround for PCIe erratum A010315"
+
+config SYS_FSL_ERRATUM_A010539
+ bool "Workaround for PIN MUX erratum A010539"
+
+config MAX_CPUS
+ int "Maximum number of CPUs permitted for Layerscape"
+ default 4 if ARCH_LS1043A
+ default 4 if ARCH_LS1046A
+ default 16 if ARCH_LS2080A
+ default 1
+ help
+ Set this number to the maximum number of possible CPUs in the SoC.
+ SoCs may have multiple clusters with each cluster may have multiple
+ ports. If some ports are reserved but higher ports are used for
+ cores, count the reserved ports. This will allocate enough memory
+ in spin table to properly handle all cores.
+
+config SECURE_BOOT
+ bool
+ help
+ Enable Freescale Secure Boot feature
+
+config QSPI_AHB_INIT
+ bool "Init the QSPI AHB bus"
+ help
+ The default setting for QSPI AHB bus just support 3bytes addressing.
+ But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
+ bus for those flashes to support the full QSPI flash size.
+
+config SYS_FSL_IFC_BANK_COUNT
+ int "Maximum banks of Integrated flash controller"
+ depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+ default 4 if ARCH_LS1043A
+ default 4 if ARCH_LS1046A
+ default 8 if ARCH_LS2080A
+
+config SYS_FSL_HAS_DP_DDR
+ bool
+
+config SYS_FSL_SRDS_1
+ bool
+
+config SYS_FSL_SRDS_2
+ bool
+
+config SYS_HAS_SERDES
+ bool
+
+endmenu
+
+config SYS_FSL_ERRATUM_A008336
+ bool
+
+config SYS_FSL_ERRATUM_A008514
+ bool
+
+config SYS_FSL_ERRATUM_A008585
+ bool
+
+config SYS_FSL_ERRATUM_A008850
+ bool
+
+config SYS_FSL_ERRATUM_A009635
+ bool
+
+config SYS_FSL_ERRATUM_A009660
+ bool
+
+config SYS_FSL_ERRATUM_A009929
+ bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 8c1317f..423b4b3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,12 +28,13 @@
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
endif
-ifneq ($(CONFIG_LS1012A),)
+ifneq ($(CONFIG_ARCH_LS1012A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
endif
-ifneq ($(CONFIG_LS1046A),)
+ifneq ($(CONFIG_ARCH_LS1046A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index e12b773..467d9af 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
@@ -17,8 +17,8 @@
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
+#include <efi_loader.h>
#include <fm_eth.h>
-#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
@@ -26,6 +26,9 @@
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
+#ifdef CONFIG_SYS_FSL_DDR
+#include <fsl_ddr.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -45,6 +48,9 @@
if (IS_E_PROCESSOR(svr))
strcat(name, "E");
+
+ sprintf(name + strlen(name), " Rev%d.%d",
+ SVR_MAJ(svr), SVR_MIN(svr));
break;
}
@@ -188,7 +194,7 @@
}
#endif
-static inline u32 initiator_type(u32 cluster, int init_id)
+u32 initiator_type(u32 cluster, int init_id)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
@@ -201,6 +207,27 @@
return 0;
}
+u32 cpu_pos_mask(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ int i = 0;
+ u32 cluster, type, mask = 0;
+
+ do {
+ int j;
+
+ cluster = gur_in32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = initiator_type(cluster, j);
+ if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
+ mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) == 0x0);
+
+ return mask;
+}
+
u32 cpu_mask(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -282,12 +309,14 @@
return -1; /* cannot identify the cluster */
}
+#ifndef CONFIG_FSL_LSCH3
uint get_svr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
return gur_in32(&gur->svr);
}
+#endif
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
@@ -377,9 +406,12 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
erratum_a009635();
#endif
-
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
+ erratum_a009942_check_cpo();
+#endif
#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
/* Check the psci version to determine if the psci is supported */
psci_ver = sec_firmware_support_psci_version();
#endif
@@ -407,6 +439,7 @@
#endif
#ifdef CONFIG_LS2080A
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+ u32 svr_dev_id;
#endif
#ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
@@ -429,6 +462,14 @@
* Register (PCTBENR), which allows the watchdog to operate.
*/
setbits_le32(pctbenr, 0xff);
+ /*
+ * For LS2080A SoC and its personalities, timer controller
+ * offset is different
+ */
+ svr_dev_id = get_svr() >> 16;
+ if (svr_dev_id == SVR_DEV_LS2080A)
+ cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
+
#endif
/* Enable clock for timer
@@ -439,9 +480,10 @@
return 0;
}
-void reset_cpu(ulong addr)
+__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+
+void __efi_runtime reset_cpu(ulong addr)
{
- u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
u32 val;
/* Raise RESET_REQ_B */
@@ -450,6 +492,33 @@
scfg_out32(rstcr, val);
}
+#ifdef CONFIG_EFI_LOADER
+
+void __efi_runtime EFIAPI efi_reset_system(
+ enum efi_reset_type reset_type,
+ efi_status_t reset_status,
+ unsigned long data_size, void *reset_data)
+{
+ switch (reset_type) {
+ case EFI_RESET_COLD:
+ case EFI_RESET_WARM:
+ reset_cpu(0);
+ break;
+ case EFI_RESET_SHUTDOWN:
+ /* Nothing we can do */
+ break;
+ }
+
+ while (1) { }
+}
+
+void efi_reset_system_init(void)
+{
+ efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
+}
+
+#endif
+
phys_size_t board_reserve_ram_top(phys_size_t ram_size)
{
phys_size_t ram_top = ram_size;
@@ -457,10 +526,6 @@
#ifdef CONFIG_SYS_MEM_TOP_HIDE
#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
#endif
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
- ram_top -= debug_server_get_dram_block_size();
-#endif
/* Carve the MC private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_MC_ENET
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
index 8072f3c..a05f8aa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
@@ -5,4 +5,5 @@
*/
int fsl_qoriq_core_to_cluster(unsigned int core);
+u32 initiator_type(u32 cluster, int init_id);
u32 cpu_mask(void);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi
new file mode 100644
index 0000000..de86f4b
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi
@@ -0,0 +1,42 @@
+QSPI Boot source support Overview
+-------------------
+ 1. LS1043A
+ LS1043AQDS
+ 2. LS2080A
+ LS2080AQDS
+ 3. LS1012A
+ LS1012AQDS
+ LS1012ARDB
+ 4. LS1046A
+ LS1046AQDS
+ LS1046ARDB
+
+Booting from QSPI
+-------------------
+Booting from QSPI requires two images, RCW and u-boot-dtb.bin.
+The difference between QSPI boot RCW image and NOR boot image is the PBI
+command sequence for setting the boot location pointer. It's should point
+to the address for u-boot in QSPI flash.
+
+RCW image should be written to the beginning of QSPI flash device.
+Example of using u-boot command
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
+=> sf erase 0 +<size of rcw image>
+SF: 65536 bytes @ 0x0 Erased: OK
+=> sf write <rcw image in memory> 0 <size of rcw image>
+SF: 164 bytes @ 0x0 Written: OK
+
+To get the QSPI image, build u-boot with QSPI config, for example,
+<board_name>_qspi_defconfig. The image needed is u-boot-dtb.bin.
+The u-boot image should be written to 0x10000(but 0x1000 for LS1043A, LS2080A).
+
+=> sf probe 0:0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
+=> sf erase 10000 +<size of u-boot image>
+SF: 589824 bytes @ 0x10000 Erased: OK
+=> sf write <u-boot image in memory> 10000 <size of u-boot image>
+SF: 580966 bytes @ 0x10000 Written: OK
+
+With these two images in QSPI flash device, the board can boot from QSPI.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index f7b949a..c7496c0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -4,6 +4,7 @@
2. LS2080A
3. LS1012A
4. LS1046A
+ 5. LS2088A
LS1043A
---------
@@ -169,3 +170,60 @@
- Two DUARTs
- Integrated flash controller (IFC) supporting NAND and NOR flash
- QorIQ platform's trust architecture 2.1
+
+LS2088A
+--------
+The LS2088A integrated multicore processor combines eight ARM Cortex-A72
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2088A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A72 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+ the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+ - Packet parsing, classification, and distribution (WRIOP)
+ - Queue and Hardware buffer management for scheduling, packet sequencing, and
+ congestion management, buffer allocation and de-allocation (QBMan)
+ - Cryptography acceleration (SEC) at up to 10 Gbps
+ - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+ - Decompression/compression acceleration (DCE) at up to 20 Gbps
+ - Accelerated I/O processing (AIOP) at up to 20 Gbps
+ - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+ - Up to eight 10 Gbps Ethernet MACs
+ - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 3.0) controllers
+ - Two high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Serial peripheral interface (SPI) controller
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+ capabilities
+
+LS2088A SoC has 3 more similar SoC personalities
+1)LS2048A, few difference w.r.t. LS2088A:
+ a) Four 64-bit ARM v8 Cortex-A72 CPUs
+
+2)LS2084A, few difference w.r.t. LS2088A:
+ a) No AIOP
+ b) No 32-bit DDR3 SDRAM memory
+ c) 5 * 1/10G + 5 *1G WRIOP
+ d) No L2 switch
+
+3)LS2044A, few difference w.r.t. LS2084A:
+ a) Four 64-bit ARM v8 Cortex-A72 CPUs
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 40d6a76..c10ccf9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <efi_loader.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <phy.h>
@@ -41,7 +42,8 @@
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
int node;
u32 psci_ver;
@@ -105,9 +107,32 @@
fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
*boot_code_size);
+#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+ efi_add_memory_map((uintptr_t)&secondary_boot_code,
+ ALIGN(*boot_code_size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
+ EFI_RESERVED_MEMORY_TYPE, false);
+#endif
}
#endif
+void fsl_fdt_disable_usb(void *blob)
+{
+ int off;
+ /*
+ * SYSCLK is used as a reference clock for USB. When the USB
+ * controller is used, SYSCLK must meet the additional requirement
+ * of 100 MHz.
+ */
+ if (CONFIG_SYS_CLK_FREQ != 100000000) {
+ off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
+ while (off != -FDT_ERR_NOTFOUND) {
+ fdt_status_disabled(blob, off);
+ off = fdt_node_offset_by_compatible(blob, off,
+ "snps,dwc3");
+ }
+ }
+}
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FSL_LSCH2
@@ -150,4 +175,6 @@
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
+ fsl_fdt_disable_usb(blob);
+
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index f73092a..e06b063 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
@@ -22,9 +22,15 @@
int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
+ if (!serdes1_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
+ if (!serdes2_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes2_prtcl_map[device];
#endif
@@ -98,6 +104,9 @@
u32 cfg;
int lane;
+ if (serdes_prtcl_map[NONE])
+ return;
+
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
@@ -115,6 +124,9 @@
else
serdes_prtcl_map[lane_prtcl] = 1;
}
+
+ /* Set the first element to indicate serdes has been initialized */
+ serdes_prtcl_map[NONE] = 1;
}
void fsl_serdes_init(void)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 8922197..55005f0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -60,7 +60,7 @@
sys_info->freq_ddrbus = sysclk;
#endif
-#ifdef CONFIG_LS1012A
+#ifdef CONFIG_ARCH_LS1012A
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
@@ -91,7 +91,7 @@
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
-#ifdef CONFIG_LS1012A
+#ifdef CONFIG_ARCH_LS1012A
sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
sys_info->freq_ddrbus *= 2;
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index be6acc6..7faa86c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <fsl-mc/ldpaa_wriop.h>
@@ -28,9 +28,15 @@
int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
+ if (!serdes1_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
+ if (!serdes2_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes2_prtcl_map[device];
#endif
@@ -79,6 +85,9 @@
u32 cfg;
int lane;
+ if (serdes_prtcl_map[NONE])
+ return;
+
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
@@ -136,6 +145,9 @@
#endif
}
}
+
+ /* Set the first element to indicate serdes has been initialized */
+ serdes_prtcl_map[NONE] = 1;
}
void fsl_serdes_init(void)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..72f2c11 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -13,6 +13,11 @@
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#endif
+#include <asm/u-boot.h>
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
@@ -137,6 +142,16 @@
#endif
#ifdef CONFIG_FSL_TZASC_400
+ /*
+ * LS2080 and its personalities does not support TZASC
+ * So skip TZASC related operations
+ */
+ bl get_svr
+ lsr w0, w0, #16
+ ldr w1, =SVR_DEV_LS2080A
+ cmp w0, w1
+ b.eq 1f
+
/* Set TZASC so that:
* a. We use only Region0 whose global secure write/read is EN
* b. We use only Region0 whose NSAID write/read is EN
@@ -145,26 +160,26 @@
* placeholders.
*/
ldr x1, =TZASC_GATE_KEEPER(0)
- ldr x0, [x1] /* Filter 0 Gate Keeper Register */
- orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
- str x0, [x1]
+ ldr w0, [x1] /* Filter 0 Gate Keeper Register */
+ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
+ str w0, [x1]
ldr x1, =TZASC_GATE_KEEPER(1)
- ldr x0, [x1] /* Filter 0 Gate Keeper Register */
- orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
- str x0, [x1]
+ ldr w0, [x1] /* Filter 0 Gate Keeper Register */
+ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
+ str w0, [x1]
ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
- ldr x0, [x1] /* Region-0 Attributes Register */
- orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
- orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
- str x0, [x1]
+ ldr w0, [x1] /* Region-0 Attributes Register */
+ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str w0, [x1]
ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
- ldr x0, [x1] /* Region-1 Attributes Register */
- orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
- orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
- str x0, [x1]
+ ldr w0, [x1] /* Region-1 Attributes Register */
+ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str w0, [x1]
ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
ldr w0, [x1] /* Region-0 Access Register */
@@ -179,11 +194,32 @@
isb
dsb sy
#endif
+1:
+#ifdef CONFIG_ARCH_LS1046A
+ /* Initialize the L2 RAM latency */
+ mrs x1, S3_1_c11_c0_2
+ mov x0, #0x1C7
+ /* Clear L2 Tag RAM latency and L2 Data RAM latency */
+ bic x1, x1, x0
+ /* Set L2 data ram latency bits [2:0] */
+ orr x1, x1, #0x2
+ /* set L2 tag ram latency bits [8:6] */
+ orr x1, x1, #0x80
+ msr S3_1_c11_c0_2, x1
+ isb
+#endif
+
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
#ifdef CONFIG_FSL_LSCH3
+ .globl get_svr
+get_svr:
+ ldr x1, =FSL_LSCH3_SVR
+ ldr w0, [x1]
+ ret
+
hnf_pstate_poll:
/* x0 has the desired status, return 0 for success, 1 for timeout
* clobber x1, x2, x3, x4, x6, x7
@@ -230,7 +266,7 @@
ret
-ENTRY(__asm_flush_l3_cache)
+ENTRY(__asm_flush_l3_dcache)
/*
* Return status in x0
* success 0
@@ -260,7 +296,7 @@
mov x0, x8
mov lr, x29
ret
-ENDPROC(__asm_flush_l3_cache)
+ENDPROC(__asm_flush_l3_dcache)
#endif
#ifdef CONFIG_MP
@@ -324,11 +360,6 @@
gic_wait_for_interrupt_m x0, w1
#endif
- bl secondary_switch_to_el2
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- bl secondary_switch_to_el1
-#endif
-
slave_cpu:
wfe
ldr x0, [x11]
@@ -341,19 +372,64 @@
tbz x1, #25, cpu_is_le
rev x0, x0 /* BE to LE conversion */
cpu_is_le:
- br x0 /* branch to the given address */
+ ldr x5, [x11, #24]
+ ldr x6, =IH_ARCH_DEFAULT
+ cmp x6, x5
+ b.eq 1f
+
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x3, secondary_switch_to_el1
+ ldr x4, =ES_TO_AARCH64
+#else
+ ldr x3, [x11]
+ ldr x4, =ES_TO_AARCH32
+#endif
+ bl secondary_switch_to_el2
+
+1:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x3, secondary_switch_to_el1
+#else
+ ldr x3, [x11]
+#endif
+ ldr x4, =ES_TO_AARCH64
+ bl secondary_switch_to_el2
+
ENDPROC(secondary_boot_func)
ENTRY(secondary_switch_to_el2)
- switch_el x0, 1f, 0f, 0f
+ switch_el x5, 1f, 0f, 0f
0: ret
-1: armv8_switch_to_el2_m x0
+1: armv8_switch_to_el2_m x3, x4, x5
ENDPROC(secondary_switch_to_el2)
ENTRY(secondary_switch_to_el1)
- switch_el x0, 0f, 1f, 0f
+ mrs x0, mpidr_el1
+ ubfm x1, x0, #8, #15
+ ubfm x2, x0, #0, #1
+ orr x10, x2, x1, lsl #2 /* x10 has LPID */
+
+ lsl x1, x10, #6
+ ldr x0, =__spin_table
+ /* physical address of this cpus spin table element */
+ add x11, x1, x0
+
+ ldr x3, [x11]
+
+ ldr x5, [x11, #24]
+ ldr x6, =IH_ARCH_DEFAULT
+ cmp x6, x5
+ b.eq 2f
+
+ ldr x4, =ES_TO_AARCH32
+ bl switch_to_el1
+
+2: ldr x4, =ES_TO_AARCH64
+
+switch_to_el1:
+ switch_el x5, 0f, 1f, 0f
0: ret
-1: armv8_switch_to_el1_m x0, x1
+1: armv8_switch_to_el1_m x3, x4, x5
ENDPROC(secondary_switch_to_el1)
/* Ensure that the literals used by the secondary boot code are
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
new file mode 100644
index 0000000..86045ac
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+ .pushsection ._secure.text, "ax"
+
+.globl psci_version
+psci_version:
+ ldr w0, =0x00010000 /* PSCI v1.0 */
+ ret
+
+ .popsection
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index eaa44a7..ab83e85 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
@@ -34,6 +34,12 @@
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
QSGMII_A} },
{0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {0x39, {SGMII8, SGMII7, SGMII6, PCIE2, SGMII4, SGMII3, SGMII2,
+ PCIE1 } },
+ {0x3B, {XFI8, XFI7, XFI6, PCIE2, XFI4, XFI3, XFI2, PCIE1 } },
+ {0x4B, {PCIE2, PCIE2, PCIE2, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {0x4C, {XFI8, XFI7, XFI6, XFI5, PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x4D, {SGMII8, SGMII7, PCIE2, PCIE2, SGMII4, SGMII3, PCIE1, PCIE1 } },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
@@ -64,6 +70,7 @@
SATA2 } },
{0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
SATA2 } },
+ {0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } },
{}
};
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index df7ffb8..80fe1ad 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -9,6 +9,8 @@
#include <asm/system.h>
#include <asm/arch/mp.h>
#include <asm/arch/soc.h>
+#include "cpu.h"
+#include <asm/arch-fsl-layerscape/soc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -22,11 +24,49 @@
return (phys_addr_t)&secondary_boot_code;
}
+void update_os_arch_secondary_cores(uint8_t os_arch)
+{
+ u64 *table = get_spin_tbl_addr();
+ int i;
+
+ for (i = 1; i < CONFIG_MAX_CPUS; i++)
+ table[i * WORDS_PER_SPIN_TABLE_ENTRY +
+ SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch;
+}
+
+#ifdef CONFIG_FSL_LSCH3
+void wake_secondary_core_n(int cluster, int core, int cluster_cores)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+ u32 mpidr = 0;
+
+ mpidr = ((cluster << 8) | core);
+ /*
+ * mpidr_el1 register value of core which needs to be released
+ * is written to scratchrw[6] register
+ */
+ gur_out32(&gur->scratchrw[6], mpidr);
+ asm volatile("dsb st" : : : "memory");
+ rst->brrl |= 1 << ((cluster * cluster_cores) + core);
+ asm volatile("dsb st" : : : "memory");
+ /*
+ * scratchrw[6] register value is polled
+ * when the value becomes zero, this means that this core is up
+ * and running, next core can be released now
+ */
+ while (gur_in32(&gur->scratchrw[6]) != 0)
+ ;
+}
+#endif
+
int fsl_layerscape_wake_seconday_cores(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_LSCH3
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+ u32 svr, ver, cluster, type;
+ int j = 0, cluster_cores = 0;
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
#endif
@@ -55,10 +95,40 @@
#ifdef CONFIG_FSL_LSCH3
gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
- gur_out32(&gur->scratchrw[6], 1);
- asm volatile("dsb st" : : : "memory");
- rst->brrl = cores;
- asm volatile("dsb st" : : : "memory");
+
+ svr = gur_in32(&gur->svr);
+ ver = SVR_SOC_VER(svr);
+ if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
+ gur_out32(&gur->scratchrw[6], 1);
+ asm volatile("dsb st" : : : "memory");
+ rst->brrl = cores;
+ asm volatile("dsb st" : : : "memory");
+ } else {
+ /*
+ * Release the cores out of reset one-at-a-time to avoid
+ * power spikes
+ */
+ i = 0;
+ cluster = in_le32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = initiator_type(cluster, j);
+ if (type &&
+ TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
+ cluster_cores++;
+ }
+
+ do {
+ cluster = in_le32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = initiator_type(cluster, j);
+ if (type &&
+ TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
+ wake_secondary_core_n(i, j,
+ cluster_cores);
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+ }
#elif defined(CONFIG_FSL_LSCH2)
scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
@@ -104,6 +174,11 @@
return !!((1 << core) & cpu_mask());
}
+static int is_pos_valid(unsigned int pos)
+{
+ return !!((1 << pos) & cpu_pos_mask());
+}
+
int is_core_online(u64 cpu_id)
{
u64 *table;
@@ -126,9 +201,9 @@
return 0;
}
-int core_to_pos(int nr)
+static int core_to_pos(int nr)
{
- u32 cores = cpu_mask();
+ u32 cores = cpu_pos_mask();
int i, count = 0;
if (nr == 0) {
@@ -139,14 +214,17 @@
}
for (i = 1; i < 32; i++) {
- if (is_core_valid(i)) {
+ if (is_pos_valid(i)) {
count++;
if (count == nr)
break;
}
}
- return count;
+ if (count != nr)
+ return -1;
+
+ return i;
}
int cpu_status(int nr)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index f54ac3f..b68e87d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -17,6 +17,9 @@
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include <fsl_validate.h>
+#endif
int ppa_init(void)
{
@@ -24,12 +27,30 @@
u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
int ret;
+#ifdef CONFIG_CHAIN_OF_TRUST
+ uintptr_t ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR;
+ uintptr_t ppa_img_addr = 0;
+#endif
+
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
#else
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ ppa_img_addr = (uintptr_t)ppa_fit_addr;
+ if (fsl_check_boot_mode_secure() != 0) {
+ ret = fsl_secboot_validate(ppa_esbc_hdr,
+ CONFIG_PPA_KEY_HASH,
+ &ppa_img_addr);
+ if (ret != 0)
+ printf("PPA validation failed\n");
+ else
+ printf("PPA validation Successful\n");
+ }
+#endif
+
#ifdef CONFIG_FSL_LSCH3
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..2f54625 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -8,10 +8,14 @@
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
+#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+#include <fsl_csu.h>
+#endif
#ifdef CONFIG_SYS_FSL_DDR
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
@@ -27,8 +31,10 @@
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
- /* LS2085A has DP_DDR */
- if (SVR_SOC_VER(svr) == SVR_LS2085A)
+ /* LS2085A, LS2088A, LS2048A has DP_DDR */
+ if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
+ (SVR_SOC_VER(svr) == SVR_LS2088A) ||
+ (SVR_SOC_VER(svr) == SVR_LS2048A))
return true;
return false;
@@ -46,23 +52,25 @@
return false;
}
-#ifdef CONFIG_LS2080A
+#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
* optimal the DDR performance.
*/
static void erratum_a008336(void)
{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
- out_le32(eddrtqcr1, 0x63b30002);
+ if (fsl_ddr_get_version(0) == 0x50200)
+ out_le32(eddrtqcr1, 0x63b30002);
#endif
#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
- out_le32(eddrtqcr1, 0x63b30002);
+ if (fsl_ddr_get_version(0) == 0x50200)
+ out_le32(eddrtqcr1, 0x63b30002);
#endif
#endif
}
@@ -73,9 +81,9 @@
*/
static void erratum_a008514(void)
{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b20002);
@@ -170,6 +178,7 @@
#endif
#endif
}
+
void bypass_smmu(void)
{
u32 val;
@@ -222,10 +231,13 @@
{
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
+#ifdef CONFIG_ARCH_LS1046A
+ /* Disable SATA ECC */
+ out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
+#endif
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+ out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA);
scsi_scan(0);
@@ -298,11 +310,41 @@
#endif
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void)
+{
+ int i;
+
+ for (i = PCIE1; i <= PCIE4; i++)
+ if (!is_serdes_configured(i)) {
+ debug("PCIe%d: disabled all R/W permission!\n", i);
+ set_pcie_ns_access(i, 0);
+ }
+}
+#endif
+
+static void erratum_a010539(void)
+{
+#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 porsr1;
+
+ porsr1 = in_be32(&gur->porsr1);
+ porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
+ out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+ porsr1);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs(); /* tighten IFC timing */
#endif
@@ -312,7 +354,9 @@
#endif
/* Make SEC reads and writes snoopable */
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
- SCFG_SNPCNFGCR_SECWRSNP);
+ SCFG_SNPCNFGCR_SECWRSNP |
+ SCFG_SNPCNFGCR_SATARDSNP |
+ SCFG_SNPCNFGCR_SATAWRSNP);
/*
* Enable snoop requests and DVM message requests for
@@ -325,6 +369,46 @@
erratum_a008850_early(); /* part 1 of 2 */
erratum_a009929();
erratum_a009660();
+ erratum_a010539();
+}
+#endif
+
+#ifdef CONFIG_QSPI_AHB_INIT
+/* Enable 4bytes address support and fast read */
+int qspi_ahb_init(void)
+{
+ u32 *qspi_lut, lut_key, *qspi_key;
+
+ qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
+ qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
+
+ lut_key = in_be32(qspi_key);
+
+ if (lut_key == 0x5af05af0) {
+ /* That means the register is BE */
+ out_be32(qspi_key, 0x5af05af0);
+ /* Unlock the lut table */
+ out_be32(qspi_key + 1, 0x00000002);
+ out_be32(qspi_lut, 0x0820040c);
+ out_be32(qspi_lut + 1, 0x1c080c08);
+ out_be32(qspi_lut + 2, 0x00002400);
+ /* Lock the lut table */
+ out_be32(qspi_key, 0x5af05af0);
+ out_be32(qspi_key + 1, 0x00000001);
+ } else {
+ /* That means the register is LE */
+ out_le32(qspi_key, 0x5af05af0);
+ /* Unlock the lut table */
+ out_le32(qspi_key + 1, 0x00000002);
+ out_le32(qspi_lut, 0x0820040c);
+ out_le32(qspi_lut + 1, 0x1c080c08);
+ out_le32(qspi_lut + 2, 0x00002400);
+ /* Lock the lut table */
+ out_le32(qspi_key, 0x5af05af0);
+ out_le32(qspi_key + 1, 0x00000001);
+ }
+
+ return 0;
}
#endif
@@ -337,6 +421,9 @@
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
+#ifdef CONFIG_QSPI_AHB_INIT
+ qspi_ahb_init();
+#endif
return 0;
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 19e34fa..1dabdbb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -8,7 +8,6 @@
#include <spl.h>
#include <asm/io.h>
#include <fsl_ifc.h>
-#include <fsl_csu.h>
#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -62,13 +61,5 @@
i2c_init_all();
#endif
dram_init();
-
- /* Clear the BSS */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
-#endif
- board_init_r(NULL, 0);
}
#endif
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index 079e250..7dfd270 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -6,6 +6,7 @@
#include <asm-offsets.h>
#include <config.h>
+#include <efi_loader.h>
#include <version.h>
#include <asm/macro.h>
#include <asm/psci.h>
@@ -17,7 +18,7 @@
* x0~x7: input arguments
* x0~x3: output arguments
*/
-void hvc_call(struct pt_regs *args)
+static void __efi_runtime hvc_call(struct pt_regs *args)
{
asm volatile(
"ldr x0, %0\n"
@@ -51,7 +52,7 @@
* x0~x3: output arguments
*/
-void smc_call(struct pt_regs *args)
+void __efi_runtime smc_call(struct pt_regs *args)
{
asm volatile(
"ldr x0, %0\n"
@@ -75,13 +76,21 @@
"x16", "x17");
}
-void __noreturn psci_system_reset(bool conduit_smc)
+/*
+ * For now, all systems we support run at least in EL2 and thus
+ * trigger PSCI calls to EL3 using SMC. If anyone ever wants to
+ * use PSCI on U-Boot running below a hypervisor, please detect
+ * this and set the flag accordingly.
+ */
+static const __efi_runtime_data bool use_smc_for_psci = true;
+
+void __noreturn __efi_runtime psci_system_reset(void)
{
struct pt_regs regs;
regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
- if (conduit_smc)
+ if (use_smc_for_psci)
smc_call(®s);
else
hvc_call(®s);
@@ -89,3 +98,45 @@
while (1)
;
}
+
+void __noreturn __efi_runtime psci_system_off(void)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_OFF;
+
+ if (use_smc_for_psci)
+ smc_call(®s);
+ else
+ hvc_call(®s);
+
+ while (1)
+ ;
+}
+
+#ifdef CONFIG_PSCI_RESET
+void reset_misc(void)
+{
+ psci_system_reset();
+}
+
+#ifdef CONFIG_EFI_LOADER
+void __efi_runtime EFIAPI efi_reset_system(
+ enum efi_reset_type reset_type,
+ efi_status_t reset_status,
+ unsigned long data_size, void *reset_data)
+{
+ switch (reset_type) {
+ case EFI_RESET_COLD:
+ case EFI_RESET_WARM:
+ psci_system_reset();
+ break;
+ case EFI_RESET_SHUTDOWN:
+ psci_system_off();
+ break;
+ }
+
+ while (1) { }
+}
+#endif /* CONFIG_EFI_LOADER */
+#endif /* CONFIG_PSCI_RESET */
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
index 8f47a82..cd92b2c 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -9,6 +9,8 @@
#include <command.h>
#include <asm/system.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Generic timer implementation of get_tbclk()
*/
@@ -41,6 +43,15 @@
return cntpct;
}
+unsigned long long get_ticks(void)
+{
+ unsigned long ticks = timer_read_counter();
+
+ gd->arch.tbl = ticks;
+
+ return ticks;
+}
+
unsigned long usec2ticks(unsigned long usec)
{
ulong ticks;
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
new file mode 100644
index 0000000..43d5d6b
--- /dev/null
+++ b/arch/arm/cpu/armv8/psci.S
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+/* Default PSCI function, return -1, Not Implemented */
+#define PSCI_DEFAULT(__fn) \
+ ENTRY(__fn); \
+ mov w0, #ARM_PSCI_RET_NI; \
+ ret; \
+ ENDPROC(__fn); \
+ .weak __fn
+
+/* PSCI function and ID table definition*/
+#define PSCI_TABLE(__id, __fn) \
+ .word __id; \
+ .word __fn
+
+.pushsection ._secure.text, "ax"
+
+/* 32 bits PSCI default functions */
+PSCI_DEFAULT(psci_version)
+PSCI_DEFAULT(psci_cpu_suspend)
+PSCI_DEFAULT(psci_cpu_off)
+PSCI_DEFAULT(psci_cpu_on)
+PSCI_DEFAULT(psci_affinity_info)
+PSCI_DEFAULT(psci_migrate)
+PSCI_DEFAULT(psci_migrate_info_type)
+PSCI_DEFAULT(psci_migrate_info_up_cpu)
+PSCI_DEFAULT(psci_system_off)
+PSCI_DEFAULT(psci_system_reset)
+PSCI_DEFAULT(psci_features)
+PSCI_DEFAULT(psci_cpu_freeze)
+PSCI_DEFAULT(psci_cpu_default_suspend)
+PSCI_DEFAULT(psci_node_hw_state)
+PSCI_DEFAULT(psci_system_suspend)
+PSCI_DEFAULT(psci_set_suspend_mode)
+PSCI_DEFAULT(psi_stat_residency)
+PSCI_DEFAULT(psci_stat_count)
+
+.align 3
+_psci_32_table:
+PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
+PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
+PSCI_TABLE(0, 0)
+
+/* 64 bits PSCI default functions */
+PSCI_DEFAULT(psci_cpu_suspend_64)
+PSCI_DEFAULT(psci_cpu_on_64)
+PSCI_DEFAULT(psci_affinity_info_64)
+PSCI_DEFAULT(psci_migrate_64)
+PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
+PSCI_DEFAULT(psci_cpu_default_suspend_64)
+PSCI_DEFAULT(psci_node_hw_state_64)
+PSCI_DEFAULT(psci_system_suspend_64)
+PSCI_DEFAULT(psci_stat_residency_64)
+PSCI_DEFAULT(psci_stat_count_64)
+
+.align 3
+_psci_64_table:
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_SUSPEND, psci_cpu_suspend_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_ON, psci_cpu_on_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_AFFINITY_INFO, psci_affinity_info_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE, psci_migrate_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64)
+PSCI_TABLE(0, 0)
+
+.macro psci_enter
+ /* PSCI call is Fast Call(atomic), so mask DAIF */
+ mrs x15, DAIF
+ stp x15, xzr, [sp, #-16]!
+ ldr x15, =0x3C0
+ msr DAIF, x15
+ /* SMC convention, x18 ~ x30 should be saved by callee */
+ stp x29, x30, [sp, #-16]!
+ stp x27, x28, [sp, #-16]!
+ stp x25, x26, [sp, #-16]!
+ stp x23, x24, [sp, #-16]!
+ stp x21, x22, [sp, #-16]!
+ stp x19, x20, [sp, #-16]!
+ mrs x15, elr_el3
+ stp x18, x15, [sp, #-16]!
+.endm
+
+.macro psci_return
+ /* restore registers */
+ ldp x18, x15, [sp], #16
+ msr elr_el3, x15
+ ldp x19, x20, [sp], #16
+ ldp x21, x22, [sp], #16
+ ldp x23, x24, [sp], #16
+ ldp x25, x26, [sp], #16
+ ldp x27, x28, [sp], #16
+ ldp x29, x30, [sp], #16
+ /* restore DAIF */
+ ldp x15, xzr, [sp], #16
+ msr DAIF, x15
+ eret
+.endm
+
+/* Caller must put PSCI function-ID table base in x9 */
+handle_psci:
+ psci_enter
+1: ldr x10, [x9] /* Load PSCI function table */
+ ubfx x11, x10, #32, #32
+ ubfx x10, x10, #0, #32
+ cbz x10, 3f /* If reach the end, bail out */
+ cmp x10, x0
+ b.eq 2f /* PSCI function found */
+ add x9, x9, #8 /* If not match, try next entry */
+ b 1b
+
+2: blr x11 /* Call PSCI function */
+ psci_return
+
+3: mov x0, #ARM_PSCI_RET_NI
+ psci_return
+
+unknown_smc_id:
+ ldr x0, =0xFFFFFFFF
+ eret
+
+handle_smc32:
+ /* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */
+ ldr w9, =0x8400001F
+ cmp w0, w9
+ b.gt unknown_smc_id
+ ldr w9, =0x84000000
+ cmp w0, w9
+ b.lt unknown_smc_id
+
+ adr x9, _psci_32_table
+ b handle_psci
+
+handle_smc64:
+ /* check SMC32 or SMC64 calls */
+ ubfx x9, x0, #30, #1
+ cbz x9, handle_smc32
+
+ /* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */
+ ldr x9, =0xC400001F
+ cmp x0, x9
+ b.gt unknown_smc_id
+ ldr x9, =0xC4000000
+ cmp x0, x9
+ b.lt unknown_smc_id
+
+ adr x9, _psci_64_table
+ b handle_psci
+
+/*
+ * Get CPU ID from MPIDR, suppose every cluster has same number of CPU cores,
+ * Platform with asymmetric clusters should implement their own interface.
+ * In case this function being called by other platform's C code, the ARM
+ * Architecture Procedure Call Standard is considered, e.g. register X0 is
+ * used for the return value, while in this PSCI environment, X0 usually holds
+ * the SMC function identifier, so X0 should be saved by caller function.
+ */
+ENTRY(psci_get_cpu_id)
+#ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
+ mrs x9, MPIDR_EL1
+ ubfx x9, x9, #8, #8
+ ldr x10, =CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
+ mul x9, x10, x9
+#else
+ mov x9, xzr
+#endif
+ mrs x10, MPIDR_EL1
+ ubfx x10, x10, #0, #8
+ add x0, x10, x9
+ ret
+ENDPROC(psci_get_cpu_id)
+.weak psci_get_cpu_id
+
+/* CPU ID input in x0, stack top output in x0*/
+LENTRY(psci_get_cpu_stack_top)
+ adr x9, __secure_stack_end
+ lsl x0, x0, #ARM_PSCI_STACK_SHIFT
+ sub x0, x9, x0
+ ret
+ENDPROC(psci_get_cpu_stack_top)
+
+unhandled_exception:
+ b unhandled_exception /* simply dead loop */
+
+handle_sync:
+ mov x15, x30
+ mov x14, x0
+
+ bl psci_get_cpu_id
+ bl psci_get_cpu_stack_top
+ mov x9, #1
+ msr spsel, x9
+ mov sp, x0
+
+ mov x0, x14
+ mov x30, x15
+
+ mrs x9, esr_el3
+ ubfx x9, x9, #26, #6
+ cmp x9, #0x13
+ b.eq handle_smc32
+ cmp x9, #0x17
+ b.eq handle_smc64
+
+ b unhandled_exception
+
+ .align 11
+ .globl el3_exception_vectors
+el3_exception_vectors:
+ b unhandled_exception /* Sync, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* IRQ, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* FIQ, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* SError, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* Sync, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* IRQ, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* FIQ, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* SError, Current EL using SPx */
+ .align 7
+ b handle_sync /* Sync, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* IRQ, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* FIQ, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* SError, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* Sync, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* IRQ, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* FIQ, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* SError, Lower EL using AArch32 */
+
+ENTRY(psci_setup_vectors)
+ adr x0, el3_exception_vectors
+ msr vbar_el3, x0
+ ret
+ENDPROC(psci_setup_vectors)
+
+ENTRY(psci_arch_init)
+ ret
+ENDPROC(psci_arch_init)
+.weak psci_arch_init
+
+.popsection
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index e21e199..0b973f0 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -19,12 +19,22 @@
#define SEC_FIRMWARE_LOADED 0x1
#define SEC_FIRMWARE_RUNNING 0x2
#define SEC_FIRMWARE_ADDR_MASK (~0x3)
- /*
- * Secure firmware load addr
- * Flags used: 0x1 secure firmware has been loaded to secure memory
- * 0x2 secure firmware is running
- */
- phys_addr_t sec_firmware_addr;
+/*
+ * Secure firmware load addr
+ * Flags used: 0x1 secure firmware has been loaded to secure memory
+ * 0x2 secure firmware is running
+ */
+phys_addr_t sec_firmware_addr;
+
+#ifndef SEC_FIRMWARE_FIT_IMAGE
+#define SEC_FIRMWARE_FIT_IMAGE "firmware"
+#endif
+#ifndef SEC_FIRMEWARE_FIT_CNF_NAME
+#define SEC_FIRMEWARE_FIT_CNF_NAME "config@1"
+#endif
+#ifndef SEC_FIRMWARE_TARGET_EL
+#define SEC_FIRMWARE_TARGET_EL 2
+#endif
static int sec_firmware_get_data(const void *sec_firmware_img,
const void **data, size_t *size)
@@ -199,7 +209,7 @@
return true;
}
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
/*
* The PSCI_VERSION function is added from PSCI v0.2. When the PSCI
* v0.1 received this function, the NOT_SUPPORTED (0xffff_ffff) error
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S
index 0c6a462..903195d 100644
--- a/arch/arm/cpu/armv8/sec_firmware_asm.S
+++ b/arch/arm/cpu/armv8/sec_firmware_asm.S
@@ -41,7 +41,7 @@
ret
ENDPROC(_sec_firmware_entry)
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
ENTRY(_sec_firmware_support_psci_version)
mov x0, 0x84000000
mov x1, 0x0
@@ -50,4 +50,27 @@
smc #0
ret
ENDPROC(_sec_firmware_support_psci_version)
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+ENTRY(armv8_el2_to_aarch32)
+ mov x0, x3
+ mov x3, x2
+ mov x2, x1
+ mov x1, x0
+ ldr x0, =0xc000ff04
+ smc #0
+ ret
+ENDPROC(armv8_el2_to_aarch32)
#endif
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 19c771d..4f5f6d8 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -251,9 +251,17 @@
/*
* All slaves will enter EL2 and optionally EL1.
*/
+ adr x3, lowlevel_in_el2
+ ldr x4, =ES_TO_AARCH64
bl armv8_switch_to_el2
+
+lowlevel_in_el2:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x3, lowlevel_in_el1
+ ldr x4, =ES_TO_AARCH64
bl armv8_switch_to_el1
+
+lowlevel_in_el1:
#endif
#endif /* CONFIG_ARMV8_MULTIENTRY */
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index 253a39b..adb9f35 100644
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -11,13 +11,36 @@
#include <asm/macro.h>
ENTRY(armv8_switch_to_el2)
- switch_el x0, 1f, 0f, 0f
-0: ret
-1: armv8_switch_to_el2_m x0
+ switch_el x5, 1f, 0f, 0f
+0:
+ cmp x4, #ES_TO_AARCH64
+ b.eq 2f
+ /*
+ * When loading 32-bit kernel, it will jump
+ * to secure firmware again, and never return.
+ */
+ bl armv8_el2_to_aarch32
+2:
+ /*
+ * x3 is kernel entry point or switch_to_el1
+ * if CONFIG_ARMV8_SWITCH_TO_EL1 is defined.
+ * When running in EL2 now, jump to the
+ * address saved in x3.
+ */
+ br x3
+1: armv8_switch_to_el2_m x3, x4, x5
ENDPROC(armv8_switch_to_el2)
ENTRY(armv8_switch_to_el1)
- switch_el x0, 0f, 1f, 0f
-0: ret
-1: armv8_switch_to_el1_m x0, x1
+ switch_el x5, 0f, 1f, 0f
+0:
+ /* x3 is kernel entry point. When running in EL1
+ * now, jump to the address saved in x3.
+ */
+ br x3
+1: armv8_switch_to_el1_m x3, x4, x5
ENDPROC(armv8_switch_to_el1)
+
+WEAK(armv8_el2_to_aarch32)
+ ret
+ENDPROC(armv8_el2_to_aarch32)
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fd15ad5..22195b8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -8,11 +8,17 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <config.h>
+#include <asm/psci.h>
+
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+ /DISCARD/ : { *(.rela._secure*) }
+#endif
. = 0x00000000;
. = ALIGN(8);
@@ -23,6 +29,57 @@
*(.text*)
}
+#ifdef CONFIG_ARMV8_PSCI
+ .__secure_start :
+#ifndef CONFIG_ARMV8_SECURE_BASE
+ ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+ {
+ KEEP(*(.__secure_start))
+ }
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_PSCI_STACK_IN_RAM
+#endif
+ .secure_text CONFIG_ARMV8_SECURE_BASE :
+ AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+ {
+ *(._secure.text)
+ }
+
+ .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+ {
+ *(._secure.data)
+ }
+
+ .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+ CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV8_PSCI_STACK_IN_RAM
+ AT(ADDR(.secure_stack))
+#else
+ AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+ {
+ KEEP(*(.__secure_stack_start))
+
+ . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+ . = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+ KEEP(*(.__secure_stack_end))
+ }
+
+#ifndef __ARMV8_PSCI_STACK_IN_RAM
+ . = LOADADDR(.secure_stack);
+#endif
+
+ .__secure_end : AT(ADDR(.__secure_end)) {
+ KEEP(*(.__secure_end))
+ LONG(0x1d1071c); /* Must output something to reset LMA */
+ }
+#endif
+
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index ed3305d..e175e6e 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -1,5 +1,29 @@
if ARCH_ZYNQMP
+config SPL_FAT_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+config SPL_SPI_FLASH_SUPPORT
+ default y if ZYNQ_QSPI
+
+config SPL_SPI_SUPPORT
+ default y if ZYNQ_QSPI
+
config SYS_BOARD
default "zynqmp"
@@ -17,11 +41,75 @@
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
+config BOOT_INIT_FILE
+ string "boot.bin init register filename"
+ depends on SPL
+ default ""
+ help
+ Add register writes to boot.bin format (max 256 pairs).
+ Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
+
config ZYNQMP_USB
bool "Configure ZynqMP USB"
config SYS_MALLOC_F_LEN
default 0x600
+config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
+ bool "Overwrite SPL bootmode"
+ depends on SPL
+ help
+ Overwrite bootmode selected via boot mode pins to tell SPL what should
+ be the next boot device.
+
+config SPL_ZYNQMP_ALT_BOOTMODE
+ hex
+ default 0x0 if JTAG_MODE
+ default 0x1 if QSPI_MODE_24BIT
+ default 0x2 if QSPI_MODE_32BIT
+ default 0x3 if SD_MODE
+ default 0x4 if NAND_MODE
+ default 0x5 if SD_MODE1
+ default 0x6 if EMMC_MODE
+ default 0x7 if USB_MODE
+ default 0xa if SW_USBHOST_MODE
+ default 0xb if SW_SATA_MODE
+
+choice
+ prompt "Boot mode"
+ depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
+ default JTAG
+
+config JTAG_MODE
+ bool "JTAG_MODE"
+
+config QSPI_MODE_24BIT
+ bool "QSPI_MODE_24BIT"
+
+config QSPI_MODE_32BIT
+ bool "QSPI_MODE_32BIT"
+
+config SD_MODE
+ bool "SD_MODE"
+
+config SD_MODE1
+ bool "SD_MODE1"
+
+config NAND_MODE
+ bool "NAND_MODE"
+
+config EMMC_MODE
+ bool "EMMC_MODE"
+
+config USB_MODE
+ bool "USB"
+
+config SW_USBHOST_MODE
+ bool "SW USBHOST_MODE"
+
+config SW_SATA_MODE
+ bool "SW SATA_MODE"
+
+endchoice
endif
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
index 867d2b2..f5f550f 100644
--- a/arch/arm/cpu/armv8/zynqmp/spl.c
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -35,10 +35,29 @@
board_init_r(NULL, 0);
}
+static void ps_mode_reset(ulong mode)
+{
+ writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
+ &crlapb_base->boot_pin_ctrl);
+ udelay(5);
+ writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
+ mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
+ &crlapb_base->boot_pin_ctrl);
+}
+
+/*
+ * Set default PS_MODE1 which is used for USB ULPI phy reset
+ * Also other resets can be connected to this certain pin
+ */
+#ifndef MODE_RESET
+# define MODE_RESET PS_MODE1
+#endif
+
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
preloader_console_init();
+ ps_mode_reset(MODE_RESET);
board_init();
}
#endif
@@ -48,7 +67,16 @@
u32 reg = 0;
u8 bootmode;
+#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
+ /* Change default boot mode at run-time */
+ writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
+ &crlapb_base->boot_mode);
+#endif
+
reg = readl(&crlapb_base->boot_mode);
+ if (reg >> BOOT_MODE_ALT_SHIFT)
+ reg >>= BOOT_MODE_ALT_SHIFT;
+
bootmode = reg & BOOT_MODES_MASK;
switch (bootmode) {
@@ -60,6 +88,14 @@
case SD_MODE1:
return BOOT_DEVICE_MMC1;
#endif
+#ifdef CONFIG_SPL_DFU_SUPPORT
+ case USB_MODE:
+ return BOOT_DEVICE_DFU;
+#endif
+#ifdef CONFIG_SPL_SATA_SUPPORT
+ case SW_SATA_MODE:
+ return BOOT_DEVICE_SATA;
+#endif
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c
index 0a0006b..90e2128 100644
--- a/arch/arm/cpu/sa1100/timer.c
+++ b/arch/arm/cpu/sa1100/timer.c
@@ -66,8 +66,5 @@
*/
ulong get_tbclk (void)
{
- ulong tbclk;
-
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
+ return CONFIG_SYS_HZ;
}
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 0a5fae6..37d4c60 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -74,6 +74,7 @@
*(._secure.data)
}
+#ifdef CONFIG_ARMV7_PSCI
.secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
#ifdef __ARMV7_PSCI_STACK_IN_RAM
@@ -83,10 +84,10 @@
#endif
{
KEEP(*(.__secure_stack_start))
-#ifdef CONFIG_ARMV7_PSCI
+
/* Skip addreses for stack */
. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
-#endif
+
/* Align end of stack section to page boundary */
. = ALIGN(CONSTANT(COMMONPAGESIZE));
@@ -109,6 +110,8 @@
. = LOADADDR(.secure_stack);
#endif
+#endif
+
.__secure_end : AT(ADDR(.__secure_end)) {
*(.__secure_end)
LONG(0x1d1071c); /* Must output something to reset LMA */
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a4ab069..3ee608b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -28,14 +28,16 @@
exynos5422-odroidxu3.dtb
dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk3036-sdk.dtb \
rk3288-firefly.dtb \
- rk3288-jerry.dtb \
+ rk3288-veyron-jerry.dtb \
+ rk3288-veyron-mickey.dtb \
+ rk3288-veyron-minnie.dtb \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
rk3288-miniarm.dtb \
rk3288-popmetal.dtb \
- rk3036-sdk.dtb \
rk3399-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-odroidc2.dtb
@@ -67,33 +69,39 @@
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_MVEBU) += \
+ armada-3720-db.dtb \
armada-375-db.dtb \
armada-388-clearfog.dtb \
armada-388-gp.dtb \
+ armada-385-amc.dtb \
+ armada-7040-db.dtb \
+ armada-8040-db.dtb \
armada-xp-gp.dtb \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
armada-xp-theadorable.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
- uniphier-ph1-ld11-ref.dtb \
- uniphier-ph1-ld20-ref.dtb \
- uniphier-ph1-ld4-ref.dtb \
- uniphier-ph1-ld6b-ref.dtb \
- uniphier-ph1-pro4-ace.dtb \
- uniphier-ph1-pro4-ref.dtb \
- uniphier-ph1-pro4-sanji.dtb \
- uniphier-ph1-pro5-4kbox.dtb \
- uniphier-ph1-sld3-ref.dtb \
- uniphier-ph1-sld8-ref.dtb \
- uniphier-proxstream2-gentil.dtb \
- uniphier-proxstream2-vodka.dtb
+ uniphier-ld11-ref.dtb \
+ uniphier-ld20-ref.dtb \
+ uniphier-ld4-ref.dtb \
+ uniphier-ld6b-ref.dtb \
+ uniphier-pro4-ace.dtb \
+ uniphier-pro4-ref.dtb \
+ uniphier-pro4-sanji.dtb \
+ uniphier-pro5-4kbox.dtb \
+ uniphier-pxs2-gentil.dtb \
+ uniphier-pxs2-vodka.dtb \
+ uniphier-sld3-ref.dtb \
+ uniphier-sld8-ref.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
zynq-zybo.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
+ zynq-topic-miami.dtb \
+ zynq-topic-miamiplus.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
@@ -125,24 +133,32 @@
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_de0_nano_soc.dtb \
+ socfpga_cyclone5_de1_soc.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb
-dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
+dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
+ dra72-evm-revc.dtb dra71-evm.dtb
dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
- am572x-idk.dtb
+ am57xx-beagle-x15-revb1.dtb \
+ am572x-idk.dtb \
+ am571x-idk.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \
- ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
+ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
+ ls1021a-iot-duart.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+ fsl-ls1046a-qds-duart.dtb \
+ fsl-ls1046a-qds-lpuart.dtb \
+ fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-frdm.dtb
@@ -248,6 +264,7 @@
sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
+ sun8i-r16-nintendo-nes-classic-edition.dtb \
sun8i-r16-parrot.dtb
dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
@@ -261,7 +278,8 @@
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
- sun8i-h3-orangepi-plus2e.dtb
+ sun8i-h3-orangepi-plus2e.dtb \
+ sun8i-h3-nanopi-neo.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
@@ -272,7 +290,20 @@
dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-colibri.dtb \
vf610-twr.dtb \
- pcm052.dtb
+ pcm052.dtb \
+ bk4r1.dtb
+
+dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
+
+dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
+ imx6sll-evk.dtb \
+ imx6dl-icore.dtb \
+ imx6dl-icore-rqs.dtb \
+ imx6q-icore.dtb \
+ imx6q-icore-rqs.dtb \
+ imx6ul-geam-kit.dtb
+
+dtb-$(CONFIG_MX7) += imx7-colibri.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
k2l-evm.dtb \
@@ -282,6 +313,15 @@
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
+dtb-$(CONFIG_ARCH_BCM283X) += \
+ bcm2835-rpi-a-plus.dtb \
+ bcm2835-rpi-a.dtb \
+ bcm2835-rpi-b-plus.dtb \
+ bcm2835-rpi-b-rev2.dtb \
+ bcm2835-rpi-b.dtb \
+ bcm2836-rpi-2-b.dtb \
+ bcm2837-rpi-3-b.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts
index 478f0a6..e454647 100644
--- a/arch/arm/dts/am437x-idk-evm.dts
+++ b/arch/arm/dts/am437x-idk-evm.dts
@@ -341,7 +341,7 @@
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "mx66l51235l";
+ compatible = "mx66l51235l", "spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-cpol;
diff --git a/arch/arm/dts/am571x-idk.dts b/arch/arm/dts/am571x-idk.dts
new file mode 100644
index 0000000..ac69bb0
--- /dev/null
+++ b/arch/arm/dts/am571x-idk.dts
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-idk-common.dtsi"
+
+/ {
+ model = "TI AM5718 IDK";
+ compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ cpu0-led {
+ label = "status0:red:cpu0";
+ gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu0";
+ };
+
+ usr0-led {
+ label = "status0:green:usr";
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ heartbeat-led {
+ label = "status0:blue:heartbeat";
+ gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ usr1-led {
+ label = "status1:red:usr";
+ gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ usr2-led {
+ label = "status1:green:usr";
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ mmc0-led {
+ label = "status1:blue:mmc0";
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts
index b340551..f9adc00 100644
--- a/arch/arm/dts/am572x-idk.dts
+++ b/arch/arm/dts/am572x-idk.dts
@@ -18,11 +18,7 @@
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
"ti,dra7";
- chosen {
- stdout-path = &uart3;
- };
-
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
diff --git a/arch/arm/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/dts/am57xx-beagle-x15-common.dtsi
new file mode 100644
index 0000000..01a9e56
--- /dev/null
+++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi
@@ -0,0 +1,600 @@
+/*
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra74x.dtsi"
+#include "am57xx-commercial-grade.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ rtc0 = &mcp_rtc;
+ rtc1 = &tps659038_rtc;
+ rtc2 = &rtc;
+ display0 = &hdmi0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ vdd_3v3: fixedregulator-vdd_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ vin-supply = <®en1>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aic_dvdd: fixedregulator-aic_dvdd {
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd_fixed";
+ vin-supply = <&vdd_3v3>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vtt_fixed: fixedregulator-vtt {
+ /* TPS51200 */
+ compatible = "regulator-fixed";
+ regulator-name = "vtt_fixed";
+ vin-supply = <&smps3_reg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "beagle-x15:usr0";
+ gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led1 {
+ label = "beagle-x15:usr1";
+ gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "beagle-x15:usr2";
+ gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "beagle-x15:usr3";
+ gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ default-state = "off";
+ };
+ };
+
+ gpio_fan: gpio_fan {
+ /* Based on 5v 500mA AFB02505HHB */
+ compatible = "gpio-fan";
+ gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <0 0>,
+ <13000 1>;
+ #cooling-cells = <2>;
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "BeagleBoard-X15";
+ simple-audio-card,widgets =
+ "Line", "Line Out",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC2L", "Line In",
+ "MIC2R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ };
+
+ sound0_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3104>;
+ clocks = <&clkout2_clk>;
+ };
+ };
+};
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+};
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps659038: tps659038@58 {
+ compatible = "ti,tps659038";
+ reg = <0x58>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+
+ regulators {
+ smps12_reg: smps12 {
+ /* VDD_MPU */
+ regulator-name = "smps12";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_DDR */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps45_reg: smps45 {
+ /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps6_reg: smps6 {
+ /* VDD_CORE */
+ regulator-name = "smps6";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* SMPS7 unused */
+
+ smps8_reg: smps8 {
+ /* VDD_1V8 */
+ regulator-name = "smps8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* SMPS9 unused */
+
+ ldo1_reg: ldo1 {
+ /* VDD_SD / VDDSHV8 */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: ldo2 {
+ /* VDD_SHV5 */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHYA */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_1V8_PHYB */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: ldo9 {
+ /* VDD_RTC */
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldoln_reg: ldoln {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ regen1: regen1 {
+ /* VDD_3V3_ON */
+ regulator-name = "regen1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps659038_rtc: tps659038_rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&tps659038>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+
+ tps659038_pwr_button: tps659038_pwr_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps659038>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <12>;
+ };
+
+ tps659038_gpio: tps659038_gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ extcon_usb2: tps659038_usb {
+ compatible = "ti,palmas-usb-vid";
+ ti,enable-vbus-detection;
+ vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ };
+
+ tmp102: tmp102@48 {
+ compatible = "ti,tmp102";
+ reg = <0x48>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tlv320aic3104: tlv320aic3104@18 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3104";
+ reg = <0x18>;
+ assigned-clocks = <&clkoutmux2_clk_mux>;
+ assigned-clock-parents = <&sys_clk2_dclk_div>;
+
+ status = "okay";
+ adc-settle-ms = <40>;
+
+ AVDD-supply = <&vdd_3v3>;
+ IOVDD-supply = <&vdd_3v3>;
+ DRVDD-supply = <&vdd_3v3>;
+ DVDD-supply = <&aic_dvdd>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "at,24c32";
+ reg = <0x50>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ mcp_rtc: rtc@6f {
+ compatible = "microchip,mcp7941x";
+ reg = <0x6f>;
+ interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
+ <&dra7_pmx_core 0x424>;
+ interrupt-names = "irq", "wakeup";
+
+ vcc-supply = <&vdd_3v3>;
+ wakeup-source;
+ };
+};
+
+&gpio7 {
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&cpu0 {
+ cpu0-supply = <&smps12_reg>;
+ voltage-tolerance = <1>;
+};
+
+&uart3 {
+ status = "okay";
+ interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <&dra7_pmx_core 0x3f8>;
+};
+
+&mac {
+ status = "okay";
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "rgmii";
+ dual_emac_res_vlan = <2>;
+};
+
+&mmc1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+};
+
+&mmc2 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_default>;
+
+ vmmc-supply = <&vdd_3v3>;
+ bus-width = <8>;
+ ti,non-removable;
+ cap-mmc-dual-data-rate;
+};
+
+&sata {
+ status = "okay";
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+ dr_mode = "host";
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
+
+&usb2 {
+ /*
+ * Stand alone usage is peripheral only.
+ * However, with some resistor modifications
+ * this port can be used via expansion connectors
+ * as "host" or "dual-role". If so, provide
+ * the necessary dr_mode override in the expansion
+ * board's DT.
+ */
+ dr_mode = "peripheral";
+};
+
+&cpu_trips {
+ cpu_alert1: cpu_alert1 {
+ temperature = <50000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+};
+
+&cpu_cooling_maps {
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+};
+
+&thermal_zones {
+ board_thermal: board_thermal {
+ polling-delay-passive = <1250>; /* milliseconds */
+ polling-delay = <1500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&tmp102 0>;
+
+ board_trips: trips {
+ board_alert0: board_alert {
+ temperature = <40000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+
+ board_crit: board_crit {
+ temperature = <105000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ board_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&board_alert0>;
+ cooling-device =
+ <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&dss {
+ status = "ok";
+
+ vdda_video-supply = <&ldoln_reg>;
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo4_reg>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
+
+&pcie1 {
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&sys_clkin2>;
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/dts/am57xx-beagle-x15-revb1.dts
new file mode 100644
index 0000000..ca85570
--- /dev/null
+++ b/arch/arm/dts/am57xx-beagle-x15-revb1.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am57xx-beagle-x15-common.dtsi"
+
+/ {
+ model = "TI AM5728 BeagleBoard-X15 rev B1";
+};
+
+&tpd12s015 {
+ gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
+ <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+};
+
+&mmc1 {
+ vmmc-supply = <&vdd_3v3>;
+ vmmc-aux-supply = <&ldo1_reg>;
+};
diff --git a/arch/arm/dts/am57xx-beagle-x15.dts b/arch/arm/dts/am57xx-beagle-x15.dts
index 38b266a..8c66f2e 100644
--- a/arch/arm/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/dts/am57xx-beagle-x15.dts
@@ -1,699 +1,24 @@
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-/dts-v1/;
-#include "dra74x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-beagle-x15-common.dtsi"
/ {
+ /* NOTE: This describes the "original" pre-production A2 revision */
model = "TI AM5728 BeagleBoard-X15";
- compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
-
- chosen {
- stdout-path = &uart3;
- };
-
- aliases {
- rtc0 = &mcp_rtc;
- rtc1 = &tps659038_rtc;
- rtc2 = &rtc;
- display0 = &hdmi0;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- vdd_3v3: fixedregulator-vdd_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_3v3";
- vin-supply = <®en1>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vtt_fixed: fixedregulator-vtt {
- /* TPS51200 */
- compatible = "regulator-fixed";
- regulator-name = "vtt_fixed";
- vin-supply = <&smps3_reg>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_pins_default>;
-
- led@0 {
- label = "beagle-x15:usr0";
- gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led@1 {
- label = "beagle-x15:usr1";
- gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "cpu0";
- default-state = "off";
- };
-
- led@2 {
- label = "beagle-x15:usr2";
- gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
-
- led@3 {
- label = "beagle-x15:usr3";
- gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ide-disk";
- default-state = "off";
- };
- };
-
- gpio_fan: gpio_fan {
- /* Based on 5v 500mA AFB02505HHB */
- compatible = "gpio-fan";
- gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0>,
- <13000 1>;
- #cooling-cells = <2>;
- };
-
- extcon_usb1: extcon_usb1 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&extcon_usb1_pins>;
- };
-
- extcon_usb2: extcon_usb2 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&extcon_usb2_pins>;
- };
-
- hdmi0: connector {
- compatible = "hdmi-connector";
- label = "hdmi";
-
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&tpd12s015_out>;
- };
- };
- };
-
- tpd12s015: encoder {
- compatible = "ti,tpd12s015";
-
- pinctrl-names = "default";
- pinctrl-0 = <&tpd12s015_pins>;
-
- gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
- <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */
- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tpd12s015_in: endpoint {
- remote-endpoint = <&hdmi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tpd12s015_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
};
-&dra7_pmx_core {
- leds_pins_default: leds_pins_default {
- pinctrl-single,pins = <
- 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
- 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
- 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
- 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
- >;
- };
-
- i2c1_pins_default: i2c1_pins_default {
- pinctrl-single,pins = <
- 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
- 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
- >;
- };
-
- hdmi_pins: pinmux_hdmi_pins {
- pinctrl-single,pins = <
- 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
- 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
- >;
- };
-
- i2c3_pins_default: i2c3_pins_default {
- pinctrl-single,pins = <
- 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
- 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
- >;
- };
-
- uart3_pins_default: uart3_pins_default {
- pinctrl-single,pins = <
- 0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
- 0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
- >;
- };
-
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-
- cpsw_pins_default: cpsw_pins_default {
- pinctrl-single,pins = <
- /* Slave 1 */
- 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
- 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
- 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
- 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
- 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
- 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
- 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
- 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
- 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
- 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
- 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
- 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
-
- /* Slave 2 */
- 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
- 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
- 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
- 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
- 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
- 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
- 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
- 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
- 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
- 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
- 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
- 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
- >;
-
- };
-
- cpsw_pins_sleep: cpsw_pins_sleep {
- pinctrl-single,pins = <
- /* Slave 1 */
- 0x250 (PIN_INPUT | MUX_MODE15)
- 0x254 (PIN_INPUT | MUX_MODE15)
- 0x258 (PIN_INPUT | MUX_MODE15)
- 0x25c (PIN_INPUT | MUX_MODE15)
- 0x260 (PIN_INPUT | MUX_MODE15)
- 0x264 (PIN_INPUT | MUX_MODE15)
- 0x268 (PIN_INPUT | MUX_MODE15)
- 0x26c (PIN_INPUT | MUX_MODE15)
- 0x270 (PIN_INPUT | MUX_MODE15)
- 0x274 (PIN_INPUT | MUX_MODE15)
- 0x278 (PIN_INPUT | MUX_MODE15)
- 0x27c (PIN_INPUT | MUX_MODE15)
-
- /* Slave 2 */
- 0x198 (PIN_INPUT | MUX_MODE15)
- 0x19c (PIN_INPUT | MUX_MODE15)
- 0x1a0 (PIN_INPUT | MUX_MODE15)
- 0x1a4 (PIN_INPUT | MUX_MODE15)
- 0x1a8 (PIN_INPUT | MUX_MODE15)
- 0x1ac (PIN_INPUT | MUX_MODE15)
- 0x1b0 (PIN_INPUT | MUX_MODE15)
- 0x1b4 (PIN_INPUT | MUX_MODE15)
- 0x1b8 (PIN_INPUT | MUX_MODE15)
- 0x1bc (PIN_INPUT | MUX_MODE15)
- 0x1c0 (PIN_INPUT | MUX_MODE15)
- 0x1c4 (PIN_INPUT | MUX_MODE15)
- >;
- };
-
- davinci_mdio_pins_default: davinci_mdio_pins_default {
- pinctrl-single,pins = <
- /* MDIO */
- 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */
- 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */
- >;
- };
-
- davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
- pinctrl-single,pins = <
- 0x23c (PIN_INPUT | MUX_MODE15)
- 0x240 (PIN_INPUT | MUX_MODE15)
- >;
- };
-
- tps659038_pins_default: tps659038_pins_default {
- pinctrl-single,pins = <
- 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
- >;
- };
-
- tmp102_pins_default: tmp102_pins_default {
- pinctrl-single,pins = <
- 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
- >;
- };
-
- mcp79410_pins_default: mcp79410_pins_default {
- pinctrl-single,pins = <
- 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
- >;
- };
-
- usb1_pins: pinmux_usb1_pins {
- pinctrl-single,pins = <
- 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
- >;
- };
-
- extcon_usb1_pins: extcon_usb1_pins {
- pinctrl-single,pins = <
- 0x3ec (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
- >;
- };
-
- extcon_usb2_pins: extcon_usb2_pins {
- pinctrl-single,pins = <
- 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */
- >;
- };
-
- tpd12s015_pins: pinmux_tpd12s015_pins {
- pinctrl-single,pins = <
- 0x3b0 (PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
- 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
- 0x370 (PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */
- >;
- };
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_default>;
- clock-frequency = <400000>;
-
- tps659038: tps659038@58 {
- compatible = "ti,tps659038";
- reg = <0x58>;
- interrupt-parent = <&gpio1>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&tps659038_pins_default>;
-
- #interrupt-cells = <2>;
- interrupt-controller;
-
- ti,system-power-controller;
-
- tps659038_pmic {
- compatible = "ti,tps659038-pmic";
-
- regulators {
- smps12_reg: smps12 {
- /* VDD_MPU */
- regulator-name = "smps12";
- regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps3_reg: smps3 {
- /* VDD_DDR */
- regulator-name = "smps3";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps45_reg: smps45 {
- /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
- regulator-name = "smps45";
- regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1150000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps6_reg: smps6 {
- /* VDD_CORE */
- regulator-name = "smps6";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1030000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* SMPS7 unused */
-
- smps8_reg: smps8 {
- /* VDD_1V8 */
- regulator-name = "smps8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* SMPS9 unused */
-
- ldo1_reg: ldo1 {
- /* VDD_SD */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
-
- ldo2_reg: ldo2 {
- /* VDD_SHV5 */
- regulator-name = "ldo2";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo3_reg: ldo3 {
- /* VDDA_1V8_PHY */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo9_reg: ldo9 {
- /* VDD_RTC */
- regulator-name = "ldo9";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldoln_reg: ldoln {
- /* VDDA_1V8_PLL */
- regulator-name = "ldoln";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldousb_reg: ldousb {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldousb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
-
- regen1: regen1 {
- /* VDD_3V3_ON */
- regulator-name = "regen1";
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- tps659038_rtc: tps659038_rtc {
- compatible = "ti,palmas-rtc";
- interrupt-parent = <&tps659038>;
- interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
- wakeup-source;
- };
-
- tps659038_pwr_button: tps659038_pwr_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&tps659038>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- wakeup-source;
- ti,palmas-long-press-seconds = <12>;
- };
-
- tps659038_gpio: tps659038_gpio {
- compatible = "ti,palmas-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-
- tmp102: tmp102@48 {
- compatible = "ti,tmp102";
- reg = <0x48>;
- pinctrl-names = "default";
- pinctrl-0 = <&tmp102_pins_default>;
- interrupt-parent = <&gpio7>;
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- #thermal-sensor-cells = <1>;
- };
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins_default>;
- clock-frequency = <400000>;
-
- mcp_rtc: rtc@6f {
- compatible = "microchip,mcp7941x";
- reg = <0x6f>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
-
- pinctrl-names = "default";
- pinctrl-0 = <&mcp79410_pins_default>;
-
- vcc-supply = <&vdd_3v3>;
- wakeup-source;
- };
-};
-
-&gpio7 {
- ti,no-reset-on-init;
- ti,no-idle-on-init;
-};
-
-&cpu0 {
- cpu0-supply = <&smps12_reg>;
- voltage-tolerance = <1>;
-};
-
-&uart3 {
- status = "okay";
- interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <&dra7_pmx_core 0x3f8>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_default>;
-};
-
-&mac {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cpsw_pins_default>;
- pinctrl-1 = <&cpsw_pins_sleep>;
- dual_emac;
-};
-
-&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <1>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <1>;
-};
-
-&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <2>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <2>;
-};
-
-&davinci_mdio {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&davinci_mdio_pins_default>;
- pinctrl-1 = <&davinci_mdio_pins_sleep>;
+&tpd12s015 {
+ gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
+ <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
};
&mmc1 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_default>;
-
vmmc-supply = <&ldo1_reg>;
- vmmc_aux-supply = <&vdd_3v3>;
- pbias-supply = <&pbias_mmc_reg>;
- bus-width = <4>;
- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
-};
-
-&mmc2 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_default>;
-
- vmmc-supply = <&vdd_3v3>;
- bus-width = <8>;
- ti,non-removable;
- cap-mmc-dual-data-rate;
-};
-
-&sata {
- status = "okay";
-};
-
-&usb2_phy1 {
- phy-supply = <&ldousb_reg>;
-};
-
-&usb2_phy2 {
- phy-supply = <&ldousb_reg>;
-};
-
-&usb1 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins>;
-};
-
-&omap_dwc3_1 {
- extcon = <&extcon_usb1>;
-};
-
-&omap_dwc3_2 {
- extcon = <&extcon_usb2>;
-};
-
-&usb2 {
- dr_mode = "peripheral";
-};
-
-&cpu_trips {
- cpu_alert1: cpu_alert1 {
- temperature = <50000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "active";
- };
-};
-
-&cpu_cooling_maps {
- map1 {
- trip = <&cpu_alert1>;
- cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-};
-
-&thermal_zones {
- board_thermal: board_thermal {
- polling-delay-passive = <1250>; /* milliseconds */
- polling-delay = <1500>; /* milliseconds */
-
- /* sensor ID */
- thermal-sensors = <&tmp102 0>;
-
- board_trips: trips {
- board_alert0: board_alert {
- temperature = <40000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "active";
- };
-
- board_crit: board_crit {
- temperature = <105000>; /* millicelsius */
- hysteresis = <0>; /* millicelsius */
- type = "critical";
- };
- };
-
- board_cooling_maps: cooling-maps {
- map0 {
- trip = <&board_alert0>;
- cooling-device =
- <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-};
-
-&dss {
- status = "ok";
-
- vdda_video-supply = <&ldoln_reg>;
-};
-
-&hdmi {
- status = "ok";
- vdda-supply = <&ldo3_reg>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pins>;
-
- port {
- hdmi_out: endpoint {
- remote-endpoint = <&tpd12s015_in>;
- };
- };
};
diff --git a/arch/arm/dts/am57xx-commercial-grade.dtsi b/arch/arm/dts/am57xx-commercial-grade.dtsi
new file mode 100644
index 0000000..c183654
--- /dev/null
+++ b/arch/arm/dts/am57xx-commercial-grade.dtsi
@@ -0,0 +1,23 @@
+&cpu_alert0 {
+ temperature = <80000>; /* milliCelsius */
+};
+
+&cpu_crit {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&gpu_crit {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&core_crit {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&dspeve_crit {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&iva_crit {
+ temperature = <90000>; /* milliCelsius */
+};
diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi
index a5bcd25..30118ed 100644
--- a/arch/arm/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/dts/am57xx-idk-common.dtsi
@@ -6,12 +6,18 @@
* published by the Free Software Foundation.
*/
+#include "am57xx-industrial-grade.dtsi"
+
/ {
aliases {
rtc0 = &tps659038_rtc;
rtc1 = &rtc;
};
+ chosen {
+ stdout-path = &uart3;
+ };
+
vmain: fixedregulator-vmain {
compatible = "regulator-fixed";
regulator-name = "VMAIN";
@@ -58,10 +64,26 @@
tps659038_pmic {
compatible = "ti,tps659038-pmic";
+
+ smps12-in-supply = <&vmain>;
+ smps3-in-supply = <&vmain>;
+ smps45-in-supply = <&vmain>;
+ smps6-in-supply = <&vmain>;
+ smps7-in-supply = <&vmain>;
+ smps8-in-supply = <&vmain>;
+ smps9-in-supply = <&vmain>;
+ ldo1-in-supply = <&vmain>;
+ ldo2-in-supply = <&vmain>;
+ ldo3-in-supply = <&vmain>;
+ ldo4-in-supply = <&vmain>;
+ ldo9-in-supply = <&vmain>;
+ ldoln-in-supply = <&vmain>;
+ ldousb-in-supply = <&vmain>;
+ ldortc-in-supply = <&vmain>;
+
regulators {
smps12_reg: smps12 {
/* VDD_MPU */
- vin-supply = <&vmain>;
regulator-name = "smps12";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
@@ -71,7 +93,6 @@
smps3_reg: smps3 {
/* VDD_DDR EMIF1 EMIF2 */
- vin-supply = <&vmain>;
regulator-name = "smps3";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
@@ -82,7 +103,6 @@
smps45_reg: smps45 {
/* VDD_DSPEVE on AM572 */
/* VDD_IVA + VDD_DSP on AM571 */
- vin-supply = <&vmain>;
regulator-name = "smps45";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
@@ -92,7 +112,6 @@
smps6_reg: smps6 {
/* VDD_GPU */
- vin-supply = <&vmain>;
regulator-name = "smps6";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
@@ -102,7 +121,6 @@
smps7_reg: smps7 {
/* VDD_CORE */
- vin-supply = <&vmain>;
regulator-name = "smps7";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
@@ -113,13 +131,11 @@
smps8_reg: smps8 {
/* 5728 - VDD_IVAHD */
/* 5718 - N.C. test point */
- vin-supply = <&vmain>;
regulator-name = "smps8";
};
smps9_reg: smps9 {
/* VDD_3_3D */
- vin-supply = <&vmain>;
regulator-name = "smps9";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -130,7 +146,6 @@
ldo1_reg: ldo1 {
/* VDDSHV8 - VSDMMC */
/* NOTE: on rev 1.3a, data supply */
- vin-supply = <&vmain>;
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@@ -140,7 +155,6 @@
ldo2_reg: ldo2 {
/* VDDSH18V */
- vin-supply = <&vmain>;
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -150,7 +164,6 @@
ldo3_reg: ldo3 {
/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
- vin-supply = <&vmain>;
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -160,7 +173,6 @@
ldo4_reg: ldo4 {
/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
- vin-supply = <&vmain>;
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -172,7 +184,6 @@
ldo9_reg: ldo9 {
/* VDD_RTC */
- vin-supply = <&vmain>;
regulator-name = "ldo9";
regulator-min-microvolt = <840000>;
regulator-max-microvolt = <1160000>;
@@ -182,7 +193,6 @@
ldoln_reg: ldoln {
/* VDDA_1V8_PLL */
- vin-supply = <&vmain>;
regulator-name = "ldoln";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -192,7 +202,6 @@
ldousb_reg: ldousb {
/* VDDA_3V_USB: VDDA_USBHS33 */
- vin-supply = <&vmain>;
regulator-name = "ldousb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -202,7 +211,6 @@
ldortc_reg: ldortc {
/* VDDA_RTC */
- vin-supply = <&vmain>;
regulator-name = "ldortc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -306,7 +314,7 @@
spi-max-frequency = <76800000>;
m25p80@0 {
- compatible = "s25fl256s1","spi-flash";
+ compatible = "s25fl256s1", "spi-flash", "jedec,spi-nor";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/am57xx-industrial-grade.dtsi b/arch/arm/dts/am57xx-industrial-grade.dtsi
new file mode 100644
index 0000000..70c8c4b
--- /dev/null
+++ b/arch/arm/dts/am57xx-industrial-grade.dtsi
@@ -0,0 +1,23 @@
+&cpu_alert0 {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&cpu_crit {
+ temperature = <105000>; /* milliCelsius */
+};
+
+&gpu_crit {
+ temperature = <105000>; /* milliCelsius */
+};
+
+&core_crit {
+ temperature = <105000>; /* milliCelsius */
+};
+
+&dspeve_crit {
+ temperature = <105000>; /* milliCelsius */
+};
+
+&iva_crit {
+ temperature = <105000>; /* milliCelsius */
+};
diff --git a/arch/arm/dts/armada-371x.dtsi b/arch/arm/dts/armada-371x.dtsi
new file mode 100644
index 0000000..c9e5325
--- /dev/null
+++ b/arch/arm/dts/armada-371x.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Device Tree Include file for Marvell Armada 371x family of SoCs
+ * (also named 88F3710)
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-37xx.dtsi"
+
+/ {
+ model = "Marvell Armada 3710 SoC";
+ compatible = "marvell,armada3710", "marvell,armada3700";
+};
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
new file mode 100644
index 0000000..83967ee
--- /dev/null
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -0,0 +1,123 @@
+/*
+ * Device Tree file for Marvell Armada 3720 development board
+ * (DB-88F3720-DDR3)
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "armada-372x.dtsi"
+
+/ {
+ model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
+ compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = ð0;
+ i2c0 = &i2c0;
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+ };
+};
+
+&comphy {
+ phy0 {
+ phy-type = <PHY_TYPE_PEX0>;
+ phy-speed = <PHY_SPEED_2_5G>;
+ };
+
+ phy1 {
+ phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ phy-mode = "rgmii";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* CON3 */
+&sata {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p128", "spi-flash";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+/* Exported on the micro USB connector CON32 through an FTDI */
+&uart0 {
+ status = "okay";
+};
+
+/* CON29 */
+&usb2 {
+ status = "okay";
+};
+
+/* CON31 */
+&usb3 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/armada-372x.dtsi b/arch/arm/dts/armada-372x.dtsi
new file mode 100644
index 0000000..5120296
--- /dev/null
+++ b/arch/arm/dts/armada-372x.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Device Tree Include file for Marvell Armada 372x family of SoCs
+ * (also named 88F3720)
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-37xx.dtsi"
+
+/ {
+ model = "Marvell Armada 3720 SoC";
+ compatible = "marvell,armada3720", "marvell,armada3710";
+
+ cpus {
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x1>;
+ enable-method = "psci";
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
new file mode 100644
index 0000000..e27eae0
--- /dev/null
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -0,0 +1,189 @@
+/*
+ * Device Tree Include file for Marvell Armada 37xx family of SoCs.
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/comphy/comphy_data.h>
+
+/ {
+ model = "Marvell Armada 37xx SoC";
+ compatible = "marvell,armada3700";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ internal-regs {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ /* 32M internal register @ 0xd000_0000 */
+ ranges = <0x0 0x0 0xd0000000 0x2000000>;
+
+ uart0: serial@12000 {
+ compatible = "marvell,armada-3700-uart";
+ reg = <0x12000 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb3: usb@58000 {
+ compatible = "marvell,armada3700-xhci",
+ "generic-xhci";
+ reg = <0x58000 0x4000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb2: usb@5e000 {
+ compatible = "marvell,armada3700-ehci";
+ reg = <0x5e000 0x450>;
+ status = "disabled";
+ };
+
+ xor@60900 {
+ compatible = "marvell,armada-3700-xor";
+ reg = <0x60900 0x100
+ 0x60b00 0x100>;
+
+ xor10 {
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ xor11 {
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ sata: sata@e0000 {
+ compatible = "marvell,armada-3700-ahci";
+ reg = <0xe0000 0x2000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@1d00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x1d00000 0x10000>, /* GICD */
+ <0x1d40000 0x40000>; /* GICR */
+ };
+
+ eth0: neta@30000 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x30000 0x20>;
+ status = "disabled";
+ };
+
+ eth1: neta@40000 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x40000 0x20>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@11000 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11000 0x100>;
+ status = "disabled";
+ };
+
+ spi0: spi@10600 {
+ compatible = "marvell,armada-3700-spi";
+ reg = <0x10600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <160000>;
+ spi-max-frequency = <40000>;
+ status = "disabled";
+ };
+
+ comphy: comphy@18300 {
+ compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
+ reg = <0x18300 0x28>,
+ <0x1f300 0x3d000>;
+ mux-bitcount = <1>;
+ max-lanes = <2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts
new file mode 100644
index 0000000..a5a8a7f
--- /dev/null
+++ b/arch/arm/dts/armada-385-amc.dts
@@ -0,0 +1,163 @@
+/*
+ * Device Tree file for Marvell Armada 385 development board
+ * (DB-88F6820-AMC)
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Marvell Armada 385 AMC";
+ compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ spi1 = &spi1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000>; /* 2 GB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+ internal-regs {
+ i2c@11000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+ };
+
+ serial@12000 {
+ /*
+ * Exported on the micro USB connector CON16
+ * through an FTDI
+ */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ ethernet@34000 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "sgmii";
+ };
+
+ usb@58000 {
+ status = "okay";
+ };
+
+ ethernet@70000 {
+ pinctrl-names = "default";
+ /*
+ * The Reference Clock 0 is used to provide a
+ * clock to the PHY
+ */
+ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+
+
+ mdio@72004 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ flash@d0000 {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ };
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p128", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+&refclk {
+ clock-frequency = <20000000>;
+};
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
new file mode 100644
index 0000000..466c6dc
--- /dev/null
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada 7040 Development board platform
+ */
+
+#include "armada-7040.dtsi"
+
+/ {
+ model = "Marvell Armada 7040 DB board";
+ compatible = "marvell,armada7040-db", "marvell,armada7040",
+ "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cpm_i2c0;
+ spi0 = &cpm_spi1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-5]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 0 0 0 0
+ 0 3 0 0 0 0 0 0 0 3 >;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+
+&cpm_pcie2 {
+ status = "okay";
+};
+
+&cpm_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cpm_pinctl {
+ /* MPP Bus:
+ * TDM [0-11]
+ * SPI [13-16]
+ * SATA1 [28]
+ * UART0 [29-30]
+ * SMI [32,34]
+ * XSMI [35-36]
+ * I2C [37-38]
+ * RGMII1[44-55]
+ * SD [56-62]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 4 4 4 4 4 4 4 4 4 4
+ 4 4 0 3 3 3 3 0 0 0
+ 0 0 0 0 0 0 0 0 9 0xA
+ 0xA 0 7 0 7 7 7 2 2 0
+ 0 0 0 0 1 1 1 1 1 1
+ 1 1 1 1 1 1 0xE 0xE 0xE 0xE
+ 0xE 0xE 0xE >;
+};
+
+&cpm_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_spi0_pins>;
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cpm_sata0 {
+ status = "okay";
+};
+
+&cpm_usb3_0 {
+ status = "okay";
+};
+
+&cpm_usb3_1 {
+ status = "okay";
+};
+
+&cpm_comphy {
+ phy0 {
+ phy-type = <PHY_TYPE_SGMII2>;
+ phy-speed = <PHY_SPEED_3_125G>;
+ };
+
+ phy1 {
+ phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+
+ phy2 {
+ phy-type = <PHY_TYPE_SGMII0>;
+ phy-speed = <PHY_SPEED_1_25G>;
+ };
+
+ phy3 {
+ phy-type = <PHY_TYPE_SATA1>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+
+ phy4 {
+ phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+
+ phy5 {
+ phy-type = <PHY_TYPE_PEX2>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+};
+
+&cpm_utmi0 {
+ status = "okay";
+};
+
+&cpm_utmi1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi
new file mode 100644
index 0000000..78d995d
--- /dev/null
+++ b/arch/arm/dts/armada-7040.dtsi
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
+ * one CP110.
+ */
+
+#include "armada-ap806-quad.dtsi"
+#include "armada-cp110-master.dtsi"
+
+/ {
+ model = "Marvell Armada 7040";
+ compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
diff --git a/arch/arm/dts/armada-8020.dtsi b/arch/arm/dts/armada-8020.dtsi
new file mode 100644
index 0000000..048e5cf
--- /dev/null
+++ b/arch/arm/dts/armada-8020.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
+ * two CP110.
+ */
+
+#include "armada-ap806-dual.dtsi"
+#include "armada-cp110-master.dtsi"
+#include "armada-cp110-slave.dtsi"
+
+/ {
+ model = "Marvell Armada 8020";
+ compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
+ "marvell,armada-ap806";
+};
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
new file mode 100644
index 0000000..40def9d
--- /dev/null
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada 8040 Development board platform
+ */
+
+#include "armada-8040.dtsi"
+
+/ {
+ model = "Marvell Armada 8040 DB board";
+ compatible = "marvell,armada8040-db", "marvell,armada8040",
+ "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cpm_i2c0;
+ spi0 = &cps_spi1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+/* Accessible over the mini-USB CON9 connector on the main board */
+&uart0 {
+ status = "okay";
+};
+
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-10]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 3 0 0 0 0 0 0 0 3 >;
+};
+
+&cpm_pinctl {
+ /* MPP Bus:
+ * [0-31] = 0xff: Keep default CP0_shared_pins:
+ * [11] CLKOUT_MPP_11 (out)
+ * [23] LINK_RD_IN_CP2CP (in)
+ * [25] CLKOUT_MPP_25 (out)
+ * [29] AVS_FB_IN_CP2CP (in)
+ * [32,34] SMI
+ * [31] GPIO: push button/Wake
+ * [35-36] GPIO
+ * [37-38] I2C
+ * [40-41] SATA[0/1]_PRESENT_ACTIVEn
+ * [42-43] XSMI
+ * [44-55] RGMII1
+ * [56-62] SD
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0 7 0 7 0 0 2 2 0
+ 0 0 8 8 1 1 1 1 1 1
+ 1 1 1 1 1 1 0xe 0xe 0xe 0xe
+ 0xe 0xe 0xe >;
+};
+
+/* CON5 on CP0 expansion */
+&cpm_pcie2 {
+ status = "okay";
+};
+
+&cpm_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+/* CON4 on CP0 expansion */
+&cpm_sata0 {
+ status = "okay";
+};
+
+/* CON9 on CP0 expansion */
+&cpm_usb3_0 {
+ status = "okay";
+};
+
+/* CON10 on CP0 expansion */
+&cpm_usb3_1 {
+ status = "okay";
+};
+
+&cps_pinctl {
+ /* MPP Bus:
+ * [0-11] RGMII0
+ * [13-16] SPI1
+ * [27,31] GE_MDIO/MDC
+ * [32-62] = 0xff: Keep default CP1_shared_pins:
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
+ 0x3 0x3 0xff 0x3 0x3 0x3 0x3 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
+ 0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff >;
+};
+
+/* CON5 on CP1 expansion */
+&cps_pcie2 {
+ status = "okay";
+};
+
+&cps_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cps_spi1_pins>;
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xce0000>;
+ };
+ };
+ };
+};
+
+/* CON4 on CP1 expansion */
+&cps_sata0 {
+ status = "okay";
+};
+
+/* CON9 on CP1 expansion */
+&cps_usb3_0 {
+ status = "okay";
+};
+
+/* CON10 on CP1 expansion */
+&cps_usb3_1 {
+ status = "okay";
+};
+
+&cpm_comphy {
+ /*
+ * Serdes Configuration:
+ * Lane 0: SGMII2
+ * Lane 1: USB3_HOST0
+ * Lane 2: KR (10G)
+ * Lane 3: SATA1
+ * Lane 4: USB3_HOST1
+ * Lane 5: PEX2x1
+ */
+ phy0 {
+ phy-type = <PHY_TYPE_SGMII2>;
+ phy-speed = <PHY_SPEED_3_125G>;
+ };
+
+ phy1 {
+ phy-type = <PHY_TYPE_USB3_HOST0>;
+ };
+
+ phy2 {
+ phy-type = <PHY_TYPE_KR>;
+ };
+
+ phy3 {
+ phy-type = <PHY_TYPE_SATA1>;
+ };
+
+ phy4 {
+ phy-type = <PHY_TYPE_USB3_HOST1>;
+ };
+
+ phy5 {
+ phy-type = <PHY_TYPE_PEX2>;
+ };
+};
+
+&cps_comphy {
+ /*
+ * Serdes Configuration:
+ * Lane 0: SGMII2
+ * Lane 1: USB3_HOST0
+ * Lane 2: KR (10G)
+ * Lane 3: SATA1
+ * Lane 4: Unconnected
+ * Lane 5: PEX2x1
+ */
+ phy0 {
+ phy-type = <PHY_TYPE_SGMII2>;
+ phy-speed = <PHY_SPEED_3_125G>;
+ };
+
+ phy1 {
+ phy-type = <PHY_TYPE_USB3_HOST0>;
+ };
+
+ phy2 {
+ phy-type = <PHY_TYPE_KR>;
+ };
+
+ phy3 {
+ phy-type = <PHY_TYPE_SATA1>;
+ };
+
+ phy4 {
+ phy-type = <PHY_TYPE_UNCONNECTED>;
+ };
+
+ phy5 {
+ phy-type = <PHY_TYPE_PEX2>;
+ };
+};
+
+&cpm_utmi0 {
+ status = "okay";
+};
+
+&cpm_utmi1 {
+ status = "okay";
+};
+
+&cps_utmi0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi
new file mode 100644
index 0000000..9c1b28c
--- /dev/null
+++ b/arch/arm/dts/armada-8040.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
+ * two CP110.
+ */
+
+#include "armada-ap806-quad.dtsi"
+#include "armada-cp110-master.dtsi"
+#include "armada-cp110-slave.dtsi"
+
+/ {
+ model = "Marvell Armada 8040";
+ compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
diff --git a/arch/arm/dts/armada-ap806-quad.dtsi b/arch/arm/dts/armada-ap806-quad.dtsi
new file mode 100644
index 0000000..ba43a43
--- /dev/null
+++ b/arch/arm/dts/armada-ap806-quad.dtsi
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#include "armada-ap806.dtsi"
+
+/ {
+ model = "Marvell Armada AP806 Quad";
+ compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+ cpu@001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi
new file mode 100644
index 0000000..efb383b
--- /dev/null
+++ b/arch/arm/dts/armada-ap806.dtsi
@@ -0,0 +1,248 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ model = "Marvell Armada AP806";
+ compatible = "marvell,armada-ap806";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ ap806 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+ gic: interrupt-controller@210000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x210000 0x10000>,
+ <0x220000 0x20000>,
+ <0x240000 0x20000>,
+ <0x260000 0x20000>;
+
+ gic_v2m0: v2m@280000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x280000 0x1000>;
+ arm,msi-base-spi = <160>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m1: v2m@290000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x290000 0x1000>;
+ arm,msi-base-spi = <192>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m2: v2m@2a0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2a0000 0x1000>;
+ arm,msi-base-spi = <224>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m3: v2m@2b0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2b0000 0x1000>;
+ arm,msi-base-spi = <256>;
+ arm,msi-num-spis = <32>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ };
+
+ odmi: odmi@300000 {
+ compatible = "marvell,odmi-controller";
+ interrupt-controller;
+ msi-controller;
+ marvell,odmi-frames = <4>;
+ reg = <0x300000 0x4000>,
+ <0x304000 0x4000>,
+ <0x308000 0x4000>,
+ <0x30C000 0x4000>;
+ marvell,spi-base = <128>, <136>, <144>, <152>;
+ };
+
+ ap_pinctl: ap-pinctl@6F4000 {
+ compatible = "marvell,armada-ap806-pinctrl";
+ bank-name ="apn-806";
+ reg = <0x6F4000 0x10>;
+ pin-count = <20>;
+ max-func = <3>;
+
+ ap_i2c0_pins: i2c-pins-0 {
+ marvell,pins = < 4 5 >;
+ marvell,function = <3>;
+ };
+ ap_emmc_pins: emmc-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7
+ 8 9 10 >;
+ marvell,function = <1>;
+ };
+ };
+
+ xor@400000 {
+ compatible = "marvell,mv-xor-v2";
+ reg = <0x400000 0x1000>,
+ <0x410000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ dma-coherent;
+ };
+
+ xor@420000 {
+ compatible = "marvell,mv-xor-v2";
+ reg = <0x420000 0x1000>,
+ <0x430000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ dma-coherent;
+ };
+
+ xor@440000 {
+ compatible = "marvell,mv-xor-v2";
+ reg = <0x440000 0x1000>,
+ <0x450000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ dma-coherent;
+ };
+
+ xor@460000 {
+ compatible = "marvell,mv-xor-v2";
+ reg = <0x460000 0x1000>,
+ <0x470000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ dma-coherent;
+ };
+
+ spi0: spi@510600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x510600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@511000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x511000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-ms = <1000>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+ };
+
+ uart0: serial@512000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512000 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+ clock-frequency = <200000000>;
+ };
+
+ uart1: serial@512100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512100 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+
+ };
+
+ ap_syscon: system-controller@6f4000 {
+ compatible = "marvell,ap806-system-controller",
+ "syscon";
+ #clock-cells = <1>;
+ clock-output-names = "ap-cpu-cluster-0",
+ "ap-cpu-cluster-1",
+ "ap-fixed", "ap-mss";
+ reg = <0x6f4000 0x1000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
new file mode 100644
index 0000000..d637867
--- /dev/null
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada CP110 Master.
+ */
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+/ {
+ cp110-master {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0x0 0xf2000000 0x2000000>;
+
+ cpm_syscon0: system-controller@440000 {
+ compatible = "marvell,cp110-system-controller0",
+ "syscon";
+ reg = <0x440000 0x1000>;
+ #clock-cells = <2>;
+ core-clock-output-names =
+ "cpm-apll", "cpm-ppv2-core", "cpm-eip",
+ "cpm-core", "cpm-nand-core";
+ gate-clock-output-names =
+ "cpm-audio", "cpm-communit", "cpm-nand",
+ "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
+ "cpm-mg-core", "cpm-xor1", "cpm-xor0",
+ "cpm-gop-dp", "none", "cpm-pcie_x10",
+ "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
+ "cpm-sata", "cpm-sata-usb", "cpm-main",
+ "cpm-sd-mmc", "none", "none",
+ "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
+ "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
+ };
+
+ cpm_pinctl: cpm-pinctl@440000 {
+ compatible = "marvell,mvebu-pinctrl",
+ "marvell,a70x0-pinctrl",
+ "marvell,a80x0-cp0-pinctrl";
+ bank-name ="cp0-110";
+ reg = <0x440000 0x20>;
+ pin-count = <63>;
+ max-func = <0xf>;
+
+ cpm_i2c0_pins: cpm-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
+ marvell,pins = < 44 45 46 47 48 49 50 51
+ 52 53 54 55 >;
+ marvell,function = <1>;
+ };
+ pca0_pins: cpm-pca0_pins {
+ marvell,pins = <62>;
+ marvell,function = <0>;
+ };
+ cpm_sdhci_pins: cpm-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cpm_spi0_pins: cpm-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+ };
+
+ cpm_sata0: sata@540000 {
+ compatible = "marvell,armada-8k-ahci";
+ reg = <0x540000 0x30000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_syscon0 1 15>;
+ status = "disabled";
+ };
+
+ cpm_usb3_0: usb3@500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_syscon0 1 22>;
+ status = "disabled";
+ };
+
+ cpm_usb3_1: usb3@510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_syscon0 1 23>;
+ status = "disabled";
+ };
+
+ cpm_spi0: spi@700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ cell-index = <1>;
+ clocks = <&cpm_syscon0 0 3>;
+ status = "disabled";
+ };
+
+ cpm_spi1: spi@700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+ clocks = <&cpm_syscon0 1 21>;
+ status = "disabled";
+ };
+
+ cpm_i2c0: i2c@701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_syscon0 1 21>;
+ status = "disabled";
+ };
+
+ cpm_i2c1: i2c@701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpm_syscon0 1 21>;
+ status = "disabled";
+ };
+
+ cpm_comphy: comphy@441000 {
+ compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
+ reg = <0x441000 0x8>,
+ <0x120000 0x8>;
+ mux-bitcount = <4>;
+ max-lanes = <6>;
+ };
+
+ cpm_utmi0: utmi@580000 {
+ compatible = "marvell,mvebu-utmi-2.6.0";
+ reg = <0x580000 0x1000>, /* utmi-unit */
+ <0x440420 0x4>, /* usb-cfg */
+ <0x440440 0x4>; /* utmi-cfg */
+ utmi-port = <UTMI_PHY_TO_USB_HOST0>;
+ status = "disabled";
+ };
+
+ cpm_utmi1: utmi@581000 {
+ compatible = "marvell,mvebu-utmi-2.6.0";
+ reg = <0x581000 0x1000>, /* utmi-unit */
+ <0x440420 0x4>, /* usb-cfg */
+ <0x440444 0x4>; /* utmi-cfg */
+ utmi-port = <UTMI_PHY_TO_USB_HOST1>;
+ status = "disabled";
+ };
+ };
+
+ cpm_pcie0: pcie@f2600000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 0xf2600000 0 0x10000>,
+ <0 0xf6f00000 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clocks = <&cpm_syscon0 1 13>;
+ status = "disabled";
+ };
+
+ cpm_pcie1: pcie@f2620000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 0xf2620000 0 0x10000>,
+ <0 0xf7f00000 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&cpm_syscon0 1 11>;
+ status = "disabled";
+ };
+
+ cpm_pcie2: pcie@f2640000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 0xf2640000 0 0x10000>,
+ <0 0xf8f00000 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&cpm_syscon0 1 12>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi
new file mode 100644
index 0000000..92ef55c
--- /dev/null
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada CP110 Slave.
+ */
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+/ {
+ cp110-slave {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0x0 0xf4000000 0x2000000>;
+
+ cps_syscon0: system-controller@440000 {
+ compatible = "marvell,cp110-system-controller0",
+ "syscon";
+ reg = <0x440000 0x1000>;
+ #clock-cells = <2>;
+ core-clock-output-names =
+ "cps-apll", "cps-ppv2-core", "cps-eip",
+ "cps-core", "cps-nand-core";
+ gate-clock-output-names =
+ "cps-audio", "cps-communit", "cps-nand",
+ "cps-ppv2", "cps-sdio", "cps-mg-domain",
+ "cps-mg-core", "cps-xor1", "cps-xor0",
+ "cps-gop-dp", "none", "cps-pcie_x10",
+ "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
+ "cps-sata", "cps-sata-usb", "cps-main",
+ "cps-sd-mmc", "none", "none",
+ "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
+ "cps-usb3dev", "cps-eip150", "cps-eip197";
+ };
+
+ cps_pinctl: cps-pinctl@440000 {
+ compatible = "marvell,mvebu-pinctrl",
+ "marvell,a80x0-cp1-pinctrl";
+ bank-name ="cp1-110";
+ reg = <0x440000 0x20>;
+ pin-count = <63>;
+ max-func = <0xf>;
+
+ cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7
+ 8 9 10 11 >;
+ marvell,function = <3>;
+ };
+ cps_spi1_pins: cps-spi-pins-1 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+ };
+
+ cps_sata0: sata@540000 {
+ compatible = "marvell,armada-8k-ahci";
+ reg = <0x540000 0x30000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_syscon0 1 15>;
+ status = "disabled";
+ };
+
+ cps_usb3_0: usb3@500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_syscon0 1 22>;
+ status = "disabled";
+ };
+
+ cps_usb3_1: usb3@510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_syscon0 1 23>;
+ status = "disabled";
+ };
+
+ cps_xor0: xor@6a0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6a0000 0x1000>,
+ <0x6b0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&cps_syscon0 1 8>;
+ };
+
+ cps_xor1: xor@6c0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6c0000 0x1000>,
+ <0x6d0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&cps_syscon0 1 7>;
+ };
+
+ cps_spi0: spi@700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ cell-index = <1>;
+ clocks = <&cps_syscon0 0 3>;
+ status = "disabled";
+ };
+
+ cps_spi1: spi@700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+ clocks = <&cps_syscon0 1 21>;
+ status = "disabled";
+ };
+
+ cps_i2c0: i2c@701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_syscon0 1 21>;
+ status = "disabled";
+ };
+
+ cps_i2c1: i2c@701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cps_syscon0 1 21>;
+ status = "disabled";
+ };
+
+ cps_comphy: comphy@441000 {
+ compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
+ reg = <0x441000 0x8>,
+ <0x120000 0x8>;
+ mux-bitcount = <4>;
+ max-lanes = <6>;
+ };
+
+ cps_utmi0: utmi@580000 {
+ compatible = "marvell,mvebu-utmi-2.6.0";
+ reg = <0x580000 0x1000>, /* utmi-unit */
+ <0x440420 0x4>, /* usb-cfg */
+ <0x440440 0x4>; /* utmi-cfg */
+ utmi-port = <UTMI_PHY_TO_USB_HOST0>;
+ status = "disabled";
+ };
+ };
+
+ cps_pcie0: pcie@f4600000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 0xf4600000 0 0x10000>,
+ <0 0xfaf00000 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clocks = <&cps_syscon0 1 13>;
+ status = "disabled";
+ };
+
+ cps_pcie1: pcie@f4620000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 0xf4620000 0 0x10000>,
+ <0 0xfbf00000 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&cps_syscon0 1 11>;
+ status = "disabled";
+ };
+
+ cps_pcie2: pcie@f4640000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 0xf4640000 0 0x10000>,
+ <0 0xfcf00000 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&cps_syscon0 1 12>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm2835-rpi-a-plus.dts b/arch/arm/dts/bcm2835-rpi-a-plus.dts
new file mode 100644
index 0000000..35ff4e7
--- /dev/null
+++ b/arch/arm/dts/bcm2835-rpi-a-plus.dts
@@ -0,0 +1,35 @@
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+
+/ {
+ compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
+ model = "Raspberry Pi Model A+";
+
+ leds {
+ act {
+ gpios = <&gpio 47 0>;
+ };
+
+ pwr {
+ label = "PWR";
+ gpios = <&gpio 35 0>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&gpio {
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+
+ /* I2S interface */
+ i2s_alt0: i2s_alt0 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/bcm2835-rpi-a.dts b/arch/arm/dts/bcm2835-rpi-a.dts
new file mode 100644
index 0000000..306a84e
--- /dev/null
+++ b/arch/arm/dts/bcm2835-rpi-a.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+
+/ {
+ compatible = "raspberrypi,model-a", "brcm,bcm2835";
+ model = "Raspberry Pi Model A";
+
+ leds {
+ act {
+ gpios = <&gpio 16 1>;
+ };
+ };
+};
+
+&gpio {
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+
+ /* I2S interface */
+ i2s_alt2: i2s_alt2 {
+ brcm,pins = <28 29 30 31>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/bcm2835-rpi-b-plus.dts b/arch/arm/dts/bcm2835-rpi-b-plus.dts
new file mode 100644
index 0000000..d5fdb8e
--- /dev/null
+++ b/arch/arm/dts/bcm2835-rpi-b-plus.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9514.dtsi"
+
+/ {
+ compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
+ model = "Raspberry Pi Model B+";
+
+ leds {
+ act {
+ gpios = <&gpio 47 0>;
+ };
+
+ pwr {
+ label = "PWR";
+ gpios = <&gpio 35 0>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&gpio {
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+
+ /* I2S interface */
+ i2s_alt0: i2s_alt0 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/dts/bcm2835-rpi-b-rev2.dts
new file mode 100644
index 0000000..bfc4bd9
--- /dev/null
+++ b/arch/arm/dts/bcm2835-rpi-b-rev2.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9512.dtsi"
+
+/ {
+ compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
+ model = "Raspberry Pi Model B rev2";
+
+ leds {
+ act {
+ gpios = <&gpio 16 1>;
+ };
+ };
+};
+
+&gpio {
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+
+ /* I2S interface */
+ i2s_alt2: i2s_alt2 {
+ brcm,pins = <28 29 30 31>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/bcm2835-rpi-b.dts b/arch/arm/dts/bcm2835-rpi-b.dts
new file mode 100644
index 0000000..0371bb7
--- /dev/null
+++ b/arch/arm/dts/bcm2835-rpi-b.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9512.dtsi"
+
+/ {
+ compatible = "raspberrypi,model-b", "brcm,bcm2835";
+ model = "Raspberry Pi Model B";
+
+ leds {
+ act {
+ gpios = <&gpio 16 1>;
+ };
+ };
+};
+
+&gpio {
+ pinctrl-0 = <&gpioout &alt0 &alt3>;
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/bcm2835-rpi.dtsi b/arch/arm/dts/bcm2835-rpi.dtsi
new file mode 100644
index 0000000..e9b47b2
--- /dev/null
+++ b/arch/arm/dts/bcm2835-rpi.dtsi
@@ -0,0 +1,86 @@
+#include <dt-bindings/power/raspberrypi-power.h>
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0 0x10000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ act {
+ label = "ACT";
+ default-state = "keep";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ soc {
+ firmware: firmware {
+ compatible = "raspberrypi,bcm2835-firmware";
+ mboxes = <&mailbox>;
+ };
+
+ power: power {
+ compatible = "raspberrypi,bcm2835-power";
+ firmware = <&firmware>;
+ #power-domain-cells = <1>;
+ };
+ };
+};
+
+&gpio {
+ pinctrl-names = "default";
+
+ gpioout: gpioout {
+ brcm,pins = <6>;
+ brcm,function = <BCM2835_FSEL_GPIO_OUT>;
+ };
+
+ alt0: alt0 {
+ brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ alt3: alt3 {
+ brcm,pins = <48 49 50 51 52 53>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&sdhci {
+ status = "okay";
+ bus-width = <4>;
+};
+
+&pwm {
+ status = "okay";
+};
+
+&usb {
+ power-domains = <&power RPI_POWER_DOMAIN_USB>;
+};
+
+&v3d {
+ power-domains = <&power RPI_POWER_DOMAIN_V3D>;
+};
+
+&hdmi {
+ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm2835.dtsi b/arch/arm/dts/bcm2835.dtsi
new file mode 100644
index 0000000..a78759e
--- /dev/null
+++ b/arch/arm/dts/bcm2835.dtsi
@@ -0,0 +1,25 @@
+#include "bcm283x.dtsi"
+
+/ {
+ compatible = "brcm,bcm2835";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,arm1176jzf-s";
+ reg = <0x0>;
+ };
+ };
+
+ soc {
+ ranges = <0x7e000000 0x20000000 0x02000000>;
+ dma-ranges = <0x40000000 0x00000000 0x20000000>;
+
+ arm-pmu {
+ compatible = "arm,arm1176-pmu";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm2836-rpi-2-b.dts b/arch/arm/dts/bcm2836-rpi-2-b.dts
new file mode 100644
index 0000000..29e1cfe
--- /dev/null
+++ b/arch/arm/dts/bcm2836-rpi-2-b.dts
@@ -0,0 +1,40 @@
+/dts-v1/;
+#include "bcm2836.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9514.dtsi"
+
+/ {
+ compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
+ model = "Raspberry Pi 2 Model B";
+
+ memory {
+ reg = <0 0x40000000>;
+ };
+
+ leds {
+ act {
+ gpios = <&gpio 47 0>;
+ };
+
+ pwr {
+ label = "PWR";
+ gpios = <&gpio 35 0>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&gpio {
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+
+ /* I2S interface */
+ i2s_alt0: i2s_alt0 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+};
+
+&hdmi {
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/bcm2836.dtsi b/arch/arm/dts/bcm2836.dtsi
new file mode 100644
index 0000000..9d0651d
--- /dev/null
+++ b/arch/arm/dts/bcm2836.dtsi
@@ -0,0 +1,78 @@
+#include "bcm283x.dtsi"
+
+/ {
+ compatible = "brcm,bcm2836";
+
+ soc {
+ ranges = <0x7e000000 0x3f000000 0x1000000>,
+ <0x40000000 0x40000000 0x00001000>;
+ dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
+
+ local_intc: local_intc {
+ compatible = "brcm,bcm2836-l1-intc";
+ reg = <0x40000000 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&local_intc>;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupt-parent = <&local_intc>;
+ interrupts = <9>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&local_intc>;
+ interrupts = <0>, // PHYS_SECURE_PPI
+ <1>, // PHYS_NONSECURE_PPI
+ <3>, // VIRT_PPI
+ <2>; // HYP_PPI
+ always-on;
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ v7_cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ clock-frequency = <800000000>;
+ };
+
+ v7_cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ clock-frequency = <800000000>;
+ };
+
+ v7_cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ clock-frequency = <800000000>;
+ };
+
+ v7_cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ clock-frequency = <800000000>;
+ };
+ };
+};
+
+/* Make the BCM2835-style global interrupt controller be a child of the
+ * CPU-local interrupt controller.
+ */
+&intc {
+ compatible = "brcm,bcm2836-armctrl-ic";
+ reg = <0x7e00b200 0x200>;
+ interrupt-parent = <&local_intc>;
+ interrupts = <8>;
+};
diff --git a/arch/arm/dts/bcm2837-rpi-3-b.dts b/arch/arm/dts/bcm2837-rpi-3-b.dts
new file mode 100644
index 0000000..7841b72
--- /dev/null
+++ b/arch/arm/dts/bcm2837-rpi-3-b.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+#include "bcm2837.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9514.dtsi"
+
+/ {
+ compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
+ model = "Raspberry Pi 3 Model B";
+
+ memory {
+ reg = <0 0x40000000>;
+ };
+
+ leds {
+ act {
+ gpios = <&gpio 47 0>;
+ };
+
+ pwr {
+ label = "PWR";
+ gpios = <&gpio 35 0>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm2837.dtsi b/arch/arm/dts/bcm2837.dtsi
new file mode 100644
index 0000000..8216bbb
--- /dev/null
+++ b/arch/arm/dts/bcm2837.dtsi
@@ -0,0 +1,76 @@
+#include "bcm283x.dtsi"
+
+/ {
+ compatible = "brcm,bcm2836";
+
+ soc {
+ ranges = <0x7e000000 0x3f000000 0x1000000>,
+ <0x40000000 0x40000000 0x00001000>;
+ dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
+
+ local_intc: local_intc {
+ compatible = "brcm,bcm2836-l1-intc";
+ reg = <0x40000000 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&local_intc>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&local_intc>;
+ interrupts = <0>, // PHYS_SECURE_PPI
+ <1>, // PHYS_NONSECURE_PPI
+ <3>, // VIRT_PPI
+ <2>; // HYP_PPI
+ always-on;
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000d8>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e8>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000f0>;
+ };
+ };
+};
+
+/* Make the BCM2835-style global interrupt controller be a child of the
+ * CPU-local interrupt controller.
+ */
+&intc {
+ compatible = "brcm,bcm2836-armctrl-ic";
+ reg = <0x7e00b200 0x200>;
+ interrupt-parent = <&local_intc>;
+ interrupts = <8>;
+};
diff --git a/arch/arm/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/dts/bcm283x-rpi-smsc9512.dtsi
new file mode 100644
index 0000000..12c981e
--- /dev/null
+++ b/arch/arm/dts/bcm283x-rpi-smsc9512.dtsi
@@ -0,0 +1,19 @@
+/ {
+ aliases {
+ ethernet = ðernet;
+ };
+};
+
+&usb {
+ usb1@1 {
+ compatible = "usb424,9512";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/dts/bcm283x-rpi-smsc9514.dtsi
new file mode 100644
index 0000000..3f0a56e
--- /dev/null
+++ b/arch/arm/dts/bcm283x-rpi-smsc9514.dtsi
@@ -0,0 +1,19 @@
+/ {
+ aliases {
+ ethernet = ðernet;
+ };
+};
+
+&usb {
+ usb1@1 {
+ compatible = "usb424,9514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm283x-uboot.dtsi b/arch/arm/dts/bcm283x-uboot.dtsi
new file mode 100644
index 0000000..8e4231a
--- /dev/null
+++ b/arch/arm/dts/bcm283x-uboot.dtsi
@@ -0,0 +1,22 @@
+/*
+ * U-Boot addition to keep baudrate set by firmware
+ * and also initialize before relocation.
+ *
+ * (C) Copyright 2016 Fabian Vogt <fvogt@suse.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&soc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ skip-init;
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ skip-init;
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/bcm283x.dtsi b/arch/arm/dts/bcm283x.dtsi
new file mode 100644
index 0000000..e5b4f20
--- /dev/null
+++ b/arch/arm/dts/bcm283x.dtsi
@@ -0,0 +1,323 @@
+#include <dt-bindings/pinctrl/bcm2835.h>
+#include <dt-bindings/clock/bcm2835.h>
+#include <dt-bindings/clock/bcm2835-aux.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/* This include file covers the common peripherals and configuration between
+ * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
+ * bcm2835.dtsi and bcm2836.dtsi.
+ */
+
+/ {
+ compatible = "brcm,bcm2835";
+ model = "BCM2835";
+ interrupt-parent = <&intc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs = "earlyprintk console=ttyAMA0";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ timer@7e003000 {
+ compatible = "brcm,bcm2835-system-timer";
+ reg = <0x7e003000 0x1000>;
+ interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
+ /* This could be a reference to BCM2835_CLOCK_TIMER,
+ * but we don't have the driver using the common clock
+ * support yet.
+ */
+ clock-frequency = <1000000>;
+ };
+
+ dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xf00>;
+ interrupts = <1 16>,
+ <1 17>,
+ <1 18>,
+ <1 19>,
+ <1 20>,
+ <1 21>,
+ <1 22>,
+ <1 23>,
+ <1 24>,
+ <1 25>,
+ <1 26>,
+ /* dma channel 11-14 share one irq */
+ <1 27>,
+ <1 27>,
+ <1 27>,
+ <1 27>,
+ /* unused shared irq for all channels */
+ <1 28>;
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10",
+ "dma11",
+ "dma12",
+ "dma13",
+ "dma14",
+ "dma-shared-all";
+ #dma-cells = <1>;
+ brcm,dma-channel-mask = <0x7f35>;
+ };
+
+ intc: interrupt-controller@7e00b200 {
+ compatible = "brcm,bcm2835-armctrl-ic";
+ reg = <0x7e00b200 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog@7e100000 {
+ compatible = "brcm,bcm2835-pm-wdt";
+ reg = <0x7e100000 0x28>;
+ };
+
+ clocks: cprman@7e101000 {
+ compatible = "brcm,bcm2835-cprman";
+ #clock-cells = <1>;
+ reg = <0x7e101000 0x2000>;
+
+ /* CPRMAN derives everything from the platform's
+ * oscillator.
+ */
+ clocks = <&clk_osc>;
+ };
+
+ rng@7e104000 {
+ compatible = "brcm,bcm2835-rng";
+ reg = <0x7e104000 0x10>;
+ };
+
+ mailbox: mailbox@7e00b800 {
+ compatible = "brcm,bcm2835-mbox";
+ reg = <0x7e00b880 0x40>;
+ interrupts = <0 1>;
+ #mbox-cells = <0>;
+ };
+
+ gpio: gpio@7e200000 {
+ compatible = "brcm,bcm2835-gpio";
+ reg = <0x7e200000 0xb4>;
+ /*
+ * The GPIO IP block is designed for 3 banks of GPIOs.
+ * Each bank has a GPIO interrupt for itself.
+ * There is an overall "any bank" interrupt.
+ * In order, these are GIC interrupts 17, 18, 19, 20.
+ * Since the BCM2835 only has 2 banks, the 2nd bank
+ * interrupt output appears to be mirrored onto the
+ * 3rd bank's interrupt signal.
+ * So, a bank0 interrupt shows up on 17, 20, and
+ * a bank1 interrupt shows up on 18, 19, 20!
+ */
+ interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart0: serial@7e201000 {
+ compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+ reg = <0x7e201000 0x1000>;
+ interrupts = <2 25>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ };
+
+ i2s: i2s@7e203000 {
+ compatible = "brcm,bcm2835-i2s";
+ reg = <0x7e203000 0x20>,
+ <0x7e101098 0x02>;
+
+ dmas = <&dma 2>,
+ <&dma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi: spi@7e204000 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204000 0x1000>;
+ interrupts = <2 22>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@7e205000 {
+ compatible = "brcm,bcm2835-i2c";
+ reg = <0x7e205000 0x1000>;
+ interrupts = <2 21>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pixelvalve@7e206000 {
+ compatible = "brcm,bcm2835-pixelvalve0";
+ reg = <0x7e206000 0x100>;
+ interrupts = <2 13>; /* pwa0 */
+ };
+
+ pixelvalve@7e207000 {
+ compatible = "brcm,bcm2835-pixelvalve1";
+ reg = <0x7e207000 0x100>;
+ interrupts = <2 14>; /* pwa1 */
+ };
+
+ aux: aux@0x7e215000 {
+ compatible = "brcm,bcm2835-aux";
+ #clock-cells = <1>;
+ reg = <0x7e215000 0x8>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ };
+
+ uart1: serial@7e215040 {
+ compatible = "brcm,bcm2835-aux-uart";
+ reg = <0x7e215040 0x40>;
+ interrupts = <1 29>;
+ clocks = <&aux BCM2835_AUX_CLOCK_UART>;
+ status = "disabled";
+ };
+
+ spi1: spi@7e215080 {
+ compatible = "brcm,bcm2835-aux-spi";
+ reg = <0x7e215080 0x40>;
+ interrupts = <1 29>;
+ clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@7e2150c0 {
+ compatible = "brcm,bcm2835-aux-spi";
+ reg = <0x7e2150c0 0x40>;
+ interrupts = <1 29>;
+ clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pwm: pwm@7e20c000 {
+ compatible = "brcm,bcm2835-pwm";
+ reg = <0x7e20c000 0x28>;
+ clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clock-rates = <10000000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ sdhci: sdhci@7e300000 {
+ compatible = "brcm,bcm2835-sdhci";
+ reg = <0x7e300000 0x100>;
+ interrupts = <2 30>;
+ clocks = <&clocks BCM2835_CLOCK_EMMC>;
+ status = "disabled";
+ };
+
+ hvs@7e400000 {
+ compatible = "brcm,bcm2835-hvs";
+ reg = <0x7e400000 0x6000>;
+ interrupts = <2 1>;
+ };
+
+ i2c1: i2c@7e804000 {
+ compatible = "brcm,bcm2835-i2c";
+ reg = <0x7e804000 0x1000>;
+ interrupts = <2 21>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@7e805000 {
+ compatible = "brcm,bcm2835-i2c";
+ reg = <0x7e805000 0x1000>;
+ interrupts = <2 21>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pixelvalve@7e807000 {
+ compatible = "brcm,bcm2835-pixelvalve2";
+ reg = <0x7e807000 0x100>;
+ interrupts = <2 10>; /* pixelvalve */
+ };
+
+ hdmi: hdmi@7e902000 {
+ compatible = "brcm,bcm2835-hdmi";
+ reg = <0x7e902000 0x600>,
+ <0x7e808000 0x100>;
+ interrupts = <2 8>, <2 9>;
+ ddc = <&i2c2>;
+ clocks = <&clocks BCM2835_PLLH_PIX>,
+ <&clocks BCM2835_CLOCK_HSM>;
+ clock-names = "pixel", "hdmi";
+ status = "disabled";
+ };
+
+ usb: usb@7e980000 {
+ compatible = "brcm,bcm2835-usb";
+ reg = <0x7e980000 0x10000>;
+ interrupts = <1 9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ v3d: v3d@7ec00000 {
+ compatible = "brcm,bcm2835-v3d";
+ reg = <0x7ec00000 0x1000>;
+ interrupts = <1 10>;
+ };
+
+ vc4: gpu {
+ compatible = "brcm,bcm2835-vc4";
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* The oscillator is the root of the clock tree. */
+ clk_osc: clock@3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ #clock-cells = <0>;
+ clock-output-names = "osc";
+ clock-frequency = <19200000>;
+ };
+
+ };
+};
+
+#include "bcm283x-uboot.dtsi"
diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts
new file mode 100644
index 0000000..197e5ab
--- /dev/null
+++ b/arch/arm/dts/bk4r1.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "vf.dtsi"
+
+/ {
+ model = "Phytec phyCORE-Vybrid";
+ compatible = "phytec,pcm052", "fsl,vf610";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ aliases {
+ spi0 = &qspi0;
+ };
+
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&qspi0 {
+ bus-num = <0>;
+ num-cs = <2>;
+ status = "okay";
+
+ qflash0: spi_flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <108000000>;
+ reg = <0>;
+ };
+
+ qflash1: spi_flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <66000000>;
+ reg = <1>;
+ };
+};
diff --git a/arch/arm/dts/dra7-dspeve-thermal.dtsi b/arch/arm/dts/dra7-dspeve-thermal.dtsi
new file mode 100644
index 0000000..1c39a84
--- /dev/null
+++ b/arch/arm/dts/dra7-dspeve-thermal.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for DRA7x SoC DSPEVE thermal
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+dspeve_thermal: dspeve_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 3>;
+
+ trips {
+ dspeve_crit: dspeve_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index fe755c0..4d882ab 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -9,6 +9,8 @@
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
+#include <dt-bindings/input/input.h>
/ {
model = "TI DRA742";
@@ -19,9 +21,9 @@
tick-timer = &timer2;
};
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x80000000 0x60000000>; /* 1536 MB */
+ reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
};
evm_3v3_sd: fixedregulator-sd {
@@ -33,13 +35,23 @@
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
- mmc2_3v3: fixedregulator-mmc2 {
+ evm_3v3_sw: fixedregulator-evm_3v3_sw {
compatible = "regulator-fixed";
- regulator-name = "mmc2_3v3";
+ regulator-name = "evm_3v3_sw";
+ vin-supply = <&sysen1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&evm_3v3_sw>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
@@ -58,8 +70,89 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
+ vin-supply = <&sysen2>;
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Out",
+ "Microphone", "Mic Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ sound0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ system-clock-frequency = <5644800>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&atl_clkin2_ck>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "dra7:usr1";
+ gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led1 {
+ label = "dra7:usr2";
+ gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led2 {
+ label = "dra7:usr3";
+ gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "dra7:usr4";
+ gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ USER1 {
+ label = "btnUser1";
+ linux,code = <BTN_0>;
+ gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
+ };
+
+ USER2 {
+ label = "btnUser2";
+ linux,code = <BTN_1>;
+ gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&dra7_pmx_core {
@@ -68,163 +161,149 @@
vtt_pin: pinmux_vtt_pin {
pinctrl-single,pins = <
- 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
+ DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
- 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
- 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
+ DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
+ DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
- 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
- 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
+ DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
+ DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
- 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
- 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
+ DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
+ DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
>;
};
mcspi1_pins: pinmux_mcspi1_pins {
pinctrl-single,pins = <
- 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
- 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
- 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
- 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
- 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
- 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
+ DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
+ DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
+ DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
+ DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
+ DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
+ DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
>;
};
mcspi2_pins: pinmux_mcspi2_pins {
pinctrl-single,pins = <
- 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
- 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
- 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
- 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
+ DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
+ DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
+ DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
+ DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
- 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
- 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
- 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
- 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
+ DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
+ DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
- 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
- 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
- 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
- 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
- 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
- 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
- >;
- };
-
- qspi1_pins: pinmux_qspi1_pins {
- pinctrl-single,pins = <
- 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
- 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
- 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
- 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
- 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
- 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
- 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
- 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
- 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
- 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
+ DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
+ DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
- 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+ DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
usb2_pins: pinmux_usb2_pins {
pinctrl-single,pins = <
- 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+ DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
>;
};
nand_flash_x16: nand_flash_x16 {
/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
* So NAND flash requires following switch settings:
- * SW5.9 (GPMC_WPN) = LOW
- * SW5.1 (NAND_BOOTn) = HIGH */
+ * SW5.1 (NAND_BOOTn) = ON (LOW)
+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
+ */
pinctrl-single,pins = <
- 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
- 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
- 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
- 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
- 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
- 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
- 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
- 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
- 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
- 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
- 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
- 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
- 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
- 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
- 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
- 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
- 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
- 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
- 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
- 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
- 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
- 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
+ DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
+ DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
+ DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
+ DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
+ DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
+ DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
+ DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
+ DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
+ DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
+ DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
+ DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
+ DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
+ DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
+ DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
+ DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
+ DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
+ DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
+ DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+ DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
+ DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+ DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+ DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
- 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
- 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
- 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
- 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
- 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
- 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
- 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
- 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
- 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
- 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
- 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
- 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
+ DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
+ DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
+ DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
+ DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
+ DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
+ DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
+ DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
+ DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
+ DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
+ DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
+ DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
+ DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
/* Slave 2 */
- 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
- 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
- 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
- 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
- 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
- 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
- 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
- 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
- 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
- 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
- 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
- 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
+ DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
+ DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
+ DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
+ DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
+ DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
+ DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
+ DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
+ DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
+ DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
+ DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
+ DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
+ DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
@@ -232,60 +311,85 @@
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 */
- 0x250 (MUX_MODE15)
- 0x254 (MUX_MODE15)
- 0x258 (MUX_MODE15)
- 0x25c (MUX_MODE15)
- 0x260 (MUX_MODE15)
- 0x264 (MUX_MODE15)
- 0x268 (MUX_MODE15)
- 0x26c (MUX_MODE15)
- 0x270 (MUX_MODE15)
- 0x274 (MUX_MODE15)
- 0x278 (MUX_MODE15)
- 0x27c (MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
/* Slave 2 */
- 0x198 (MUX_MODE15)
- 0x19c (MUX_MODE15)
- 0x1a0 (MUX_MODE15)
- 0x1a4 (MUX_MODE15)
- 0x1a8 (MUX_MODE15)
- 0x1ac (MUX_MODE15)
- 0x1b0 (MUX_MODE15)
- 0x1b4 (MUX_MODE15)
- 0x1b8 (MUX_MODE15)
- 0x1bc (MUX_MODE15)
- 0x1c0 (MUX_MODE15)
- 0x1c4 (MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
- 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
- 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
+ DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
- 0x23c (MUX_MODE15)
- 0x240 (MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
- 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
- 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+ DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
- 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
- 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ >;
+ };
+
+ atl_pins: pinmux_atl_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
+ DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
+ >;
+ };
+
+ mcasp3_pins: pinmux_mcasp3_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
+ DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
+ DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
+ DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
+ >;
+ };
+
+ mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
>;
};
};
@@ -317,7 +421,7 @@
/* VDD_DSPEVE */
regulator-name = "smps45";
regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1150000>;
+ regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
@@ -335,7 +439,7 @@
/* CORE_VDD */
regulator-name = "smps7";
regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1060000>;
+ regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
@@ -363,6 +467,7 @@
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
regulator-boot-on;
};
@@ -392,6 +497,7 @@
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
+ regulator-allow-bypass;
};
ldoln_reg: ldoln {
@@ -410,12 +516,48 @@
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
+
+ /* REGEN1 is unused */
+
+ regen2: regen2 {
+ /* Needed for PMIC internal resources */
+ regulator-name = "regen2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* REGEN3 is unused */
+
+ sysen1: sysen1 {
+ /* PMIC_REGEN_3V3 */
+ regulator-name = "sysen1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sysen2: sysen2 {
+ /* PMIC_REGEN_DDR */
+ regulator-name = "sysen2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
};
};
+ pcf_lcd: gpio@20 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
pcf_gpio_21: gpio@21 {
- compatible = "ti,pcf8575";
+ compatible = "ti,pcf8575", "nxp,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
@@ -427,6 +569,20 @@
u-boot,i2c-offset-len = <0>;
};
+ tlv320aic3106: tlv320aic3106@19 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x19>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&evm_3v3_sw>;
+ IOVDD-supply = <&evm_3v3_sw>;
+ DRVDD-supply = <&evm_3v3_sw>;
+ DVDD-supply = <&aic_dvdd>;
+ };
};
&i2c2 {
@@ -434,6 +590,20 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
+
+ pcf_hdmi: gpio@26 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ p1 {
+ /* vin6_sel_s0: high: VIN6, low: audio */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "vin6_sel_s0";
+ };
+ };
};
&i2c3 {
@@ -489,7 +659,7 @@
&mmc2 {
status = "okay";
- vmmc-supply = <&mmc2_3v3>;
+ vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
};
@@ -499,13 +669,11 @@
&qspi {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&qspi1_pins>;
spi-max-frequency = <76800000>;
m25p80@0 {
- compatible = "s25fl256s1","spi-flash";
- spi-max-frequency = <64000000>;
+ compatible = "s25fl256s1", "spi-flash";
+ spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
@@ -588,9 +756,14 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x16>;
- ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
+ ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
@@ -613,7 +786,6 @@
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
@@ -710,3 +882,64 @@
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
+
+&atl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&atl_pins>;
+
+ assigned-clocks = <&abe_dpll_sys_clk_mux>,
+ <&atl_gfclk_mux>,
+ <&dpll_abe_ck>,
+ <&dpll_abe_m2x2_ck>,
+ <&atl_clkin2_ck>;
+ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
+ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
+
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp3_pins>;
+ pinctrl-1 = <&mcasp3_sleep_pins>;
+
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&atl_clkin2_ck>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/dra7-iva-thermal.dtsi b/arch/arm/dts/dra7-iva-thermal.dtsi
new file mode 100644
index 0000000..dd74a53
--- /dev/null
+++ b/arch/arm/dts/dra7-iva-thermal.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for DRA7x SoC IVA thermal
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+iva_thermal: iva_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 4>;
+
+ trips {
+ iva_crit: iva_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index 0f242e6..5570e30 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -10,13 +10,11 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
-#include "skeleton.dtsi"
-
#define MAX_SOURCES 400
/ {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "ti,dra7xx";
interrupt-parent = <&crossbar_mpu>;
@@ -57,10 +55,10 @@
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
- reg = <0x48211000 0x1000>,
- <0x48212000 0x1000>,
- <0x48214000 0x2000>,
- <0x48216000 0x2000>;
+ reg = <0x0 0x48211000 0x0 0x1000>,
+ <0x0 0x48212000 0x0 0x1000>,
+ <0x0 0x48214000 0x0 0x2000>,
+ <0x0 0x48216000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
@@ -69,10 +67,37 @@
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
- reg = <0x48281000 0x1000>;
+ reg = <0x0 0x48281000 0x0 0x1000>;
interrupt-parent = <&gic>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+
+ operating-points = <
+ /* kHz uV */
+ 1000000 1060000
+ 1176000 1160000
+ >;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
@@ -96,10 +121,10 @@
compatible = "ti,dra7-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0x0 0x0 0x0 0xc0000000>;
ti,hwmods = "l3_main_1", "l3_main_2";
- reg = <0x44000000 0x1000000>,
- <0x45000000 0x1000>;
+ reg = <0x0 0x44000000 0x0 0x1000000>,
+ <0x0 0x45000000 0x0 0x1000>;
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -117,13 +142,14 @@
ranges = <0 0x2000 0x2000>;
scm_conf: scm_conf@0 {
- compatible = "syscon";
+ compatible = "syscon", "simple-bus";
reg = <0x0 0x1400>;
#address-cells = <1>;
#size-cells = <1>;
+ ranges = <0 0x0 0x1400>;
- pbias_regulator: pbias_regulator {
- compatible = "ti,pbias-omap";
+ pbias_regulator: pbias_regulator@e00 {
+ compatible = "ti,pbias-dra7", "ti,pbias-omap";
reg = <0xe00 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap5 {
@@ -142,7 +168,7 @@
dra7_pmx_core: pinmux@1400 {
compatible = "ti,dra7-padconf",
"pinctrl-single";
- reg = <0x1400 0x0464>;
+ reg = <0x1400 0x0468>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
@@ -150,6 +176,34 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
+
+ scm_conf1: scm_conf@1c04 {
+ compatible = "syscon";
+ reg = <0x1c04 0x0020>;
+ };
+
+ scm_conf_pcie: scm_conf@1c24 {
+ compatible = "syscon";
+ reg = <0x1c24 0x0024>;
+ };
+
+ sdma_xbar: dma-router@b78 {
+ compatible = "ti,dra7-dma-crossbar";
+ reg = <0xb78 0xfc>;
+ #dma-cells = <1>;
+ dma-requests = <205>;
+ ti,dma-safe-map = <0>;
+ dma-masters = <&sdma>;
+ };
+
+ edma_xbar: dma-router@c78 {
+ compatible = "ti,dra7-dma-crossbar";
+ reg = <0xc78 0x7c>;
+ #dma-cells = <2>;
+ dma-requests = <204>;
+ ti,dma-safe-map = <0>;
+ dma-masters = <&edma>;
+ };
};
cm_core_aon: cm_core_aon@5000 {
@@ -204,6 +258,11 @@
prm_clockdomains: clockdomains {
};
};
+
+ scm_wkup: scm_conf@c000 {
+ compatible = "syscon";
+ reg = <0xc000 0x1000>;
+ };
};
axi@0 {
@@ -212,7 +271,7 @@
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
- pcie@51000000 {
+ pcie1: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
@@ -224,6 +283,7 @@
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
+ linux,pci-domain = <0>;
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
@@ -247,7 +307,7 @@
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
status = "disabled";
- pcie@51000000 {
+ pcie@51800000 {
compatible = "ti,dra7-pcie";
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
@@ -259,6 +319,7 @@
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
+ linux,pci-domain = <1>;
ti,hwmods = "pcie2";
phys = <&pcie2_phy>;
phy-names = "pcie-phy0";
@@ -275,6 +336,53 @@
};
};
+ ocmcram1: ocmcram@40300000 {
+ compatible = "mmio-sram";
+ reg = <0x40300000 0x80000>;
+ ranges = <0x0 0x40300000 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * This is a placeholder for an optional reserved
+ * region for use by secure software. The size
+ * of this region is not known until runtime so it
+ * is set as zero to either be updated to reserve
+ * space or left unchanged to leave all SRAM for use.
+ * On HS parts that that require the reserved region
+ * either the bootloader can update the size to
+ * the required amount or the node can be overridden
+ * from the board dts file for the secure platform.
+ */
+ sram-hs@0 {
+ compatible = "ti,secure-ram";
+ reg = <0x0 0x0>;
+ };
+ };
+
+ /*
+ * NOTE: ocmcram2 and ocmcram3 are not available on all
+ * DRA7xx and AM57xx variants. Confirm availability in
+ * the data manual for the exact part number in use
+ * before enabling these nodes in the board dts file.
+ */
+ ocmcram2: ocmcram@40400000 {
+ status = "disabled";
+ compatible = "mmio-sram";
+ reg = <0x40400000 0x100000>;
+ ranges = <0x0 0x40400000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ ocmcram3: ocmcram@40500000 {
+ status = "disabled";
+ compatible = "mmio-sram";
+ reg = <0x40500000 0x100000>;
+ ranges = <0x0 0x40500000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
bandgap: bandgap@4a0021e0 {
reg = <0x4a0021e0 0xc
0x4a00232c 0xc
@@ -287,14 +395,9 @@
#thermal-sensor-cells = <1>;
};
- dra7_ctrl_core: ctrl_core@4a002000 {
+ dsp1_system: dsp_system@40d00000 {
compatible = "syscon";
- reg = <0x4a002000 0x6d0>;
- };
-
- dra7_ctrl_general: tisyscon@4a002e00 {
- compatible = "syscon";
- reg = <0x4a002e00 0x7c>;
+ reg = <0x40d00000 0x100>;
};
sdma: dma-controller@4a056000 {
@@ -309,6 +412,45 @@
dma-requests = <127>;
};
+ edma: edma@43300000 {
+ compatible = "ti,edma3-tpcc";
+ ti,hwmods = "tpcc";
+ reg = <0x43300000 0x100000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_ccint", "edma3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
+
+ /*
+ * memcpy is disabled, can be enabled with:
+ * ti,edma-memcpy-channels = <20 21>;
+ * for example. Note that these channels need to be
+ * masked in the xbar as well.
+ */
+ };
+
+ edma_tptc0: tptc@43400000 {
+ compatible = "ti,edma3-tptc";
+ ti,hwmods = "tptc0";
+ reg = <0x43400000 0x100000>;
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
+
+ edma_tptc1: tptc@43500000 {
+ compatible = "ti,edma3-tptc";
+ ti,hwmods = "tptc1";
+ reg = <0x43500000 0x100000>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
+
gpio1: gpio@4ae10000 {
compatible = "ti,omap4-gpio";
reg = <0x4ae10000 0x200>;
@@ -398,79 +540,79 @@
};
uart1: serial@4806a000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806a000 0x100>;
reg-shift = <2>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 49>, <&sdma 50>;
+ dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
dma-names = "tx", "rx";
};
uart2: serial@4806c000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806c000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 51>, <&sdma 52>;
+ dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
dma-names = "tx", "rx";
};
uart3: serial@48020000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48020000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 53>, <&sdma 54>;
+ dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
dma-names = "tx", "rx";
};
uart4: serial@4806e000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806e000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 55>, <&sdma 56>;
+ dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
dma-names = "tx", "rx";
};
uart5: serial@48066000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48066000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 63>, <&sdma 64>;
+ dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
dma-names = "tx", "rx";
};
uart6: serial@48068000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48068000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 79>, <&sdma 80>;
+ dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
dma-names = "tx", "rx";
};
uart7: serial@48420000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48420000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
@@ -480,7 +622,7 @@
};
uart8: serial@48422000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48422000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
@@ -490,7 +632,7 @@
};
uart9: serial@48424000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48424000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
@@ -500,7 +642,7 @@
};
uart10: serial@4ae2b000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4ae2b000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
@@ -768,12 +910,20 @@
ti,hwmods = "timer11";
};
+ timer12: timer@4ae20000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4ae20000 0x80>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer12";
+ ti,timer-alwon;
+ ti,timer-secure;
+ };
+
timer13: timer@48828000 {
compatible = "ti,omap5430-timer";
reg = <0x48828000 0x80>;
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer13";
- status = "disabled";
};
timer14: timer@4882a000 {
@@ -781,7 +931,6 @@
reg = <0x4882a000 0x80>;
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer14";
- status = "disabled";
};
timer15: timer@4882c000 {
@@ -789,7 +938,6 @@
reg = <0x4882c000 0x80>;
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer15";
- status = "disabled";
};
timer16: timer@4882e000 {
@@ -797,7 +945,6 @@
reg = <0x4882e000 0x80>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer16";
- status = "disabled";
};
wdt2: wdt@4ae14000 {
@@ -878,7 +1025,7 @@
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
- dmas = <&sdma 61>, <&sdma 62>;
+ dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
dma-names = "tx", "rx";
status = "disabled";
pbias-supply = <&pbias_mmc_reg>;
@@ -890,7 +1037,7 @@
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
- dmas = <&sdma 47>, <&sdma 48>;
+ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -901,7 +1048,7 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
- dmas = <&sdma 77>, <&sdma 78>;
+ dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -912,11 +1059,51 @@
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
- dmas = <&sdma 57>, <&sdma 58>;
+ dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
dma-names = "tx", "rx";
status = "disabled";
};
+ mmu0_dsp1: mmu@40d01000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x40d01000 0x100>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu0_dsp1";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x0>;
+ status = "disabled";
+ };
+
+ mmu1_dsp1: mmu@40d02000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x40d02000 0x100>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu1_dsp1";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x1>;
+ status = "disabled";
+ };
+
+ mmu_ipu1: mmu@58882000 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x58882000 0x100>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu_ipu1";
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ status = "disabled";
+ };
+
+ mmu_ipu2: mmu@55082000 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x55082000 0x100>;
+ interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu_ipu2";
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ status = "disabled";
+ };
+
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v3";
regulator-name = "abb_mpu";
@@ -1057,14 +1244,14 @@
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
- dmas = <&sdma 35>,
- <&sdma 36>,
- <&sdma 37>,
- <&sdma 38>,
- <&sdma 39>,
- <&sdma 40>,
- <&sdma 41>,
- <&sdma 42>;
+ dmas = <&sdma_xbar 35>,
+ <&sdma_xbar 36>,
+ <&sdma_xbar 37>,
+ <&sdma_xbar 38>,
+ <&sdma_xbar 39>,
+ <&sdma_xbar 40>,
+ <&sdma_xbar 41>,
+ <&sdma_xbar 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
status = "disabled";
@@ -1078,10 +1265,10 @@
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
- dmas = <&sdma 43>,
- <&sdma 44>,
- <&sdma 45>,
- <&sdma 46>;
+ dmas = <&sdma_xbar 43>,
+ <&sdma_xbar 44>,
+ <&sdma_xbar 45>,
+ <&sdma_xbar 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
@@ -1094,7 +1281,7 @@
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
- dmas = <&sdma 15>, <&sdma 16>;
+ dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
dma-names = "tx0", "rx0";
status = "disabled";
};
@@ -1107,7 +1294,7 @@
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
- dmas = <&sdma 70>, <&sdma 71>;
+ dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
dma-names = "tx0", "rx0";
status = "disabled";
};
@@ -1115,10 +1302,9 @@
qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi";
reg = <0x4b300000 0x100>,
- <0x5c000000 0x4000000>,
- <0x4a002558 0x4>;
- reg-names = "qspi_base", "qspi_mmap",
- "qspi_ctrlmod";
+ <0x5c000000 0x4000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ syscon-chipselects = <&scm_conf 0x558>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
@@ -1129,14 +1315,6 @@
status = "disabled";
};
- omap_control_sata: control-phy@4a002374 {
- compatible = "ti,control-phy-pipe3";
- reg = <0x4a002374 0x4>;
- reg-names = "power";
- clocks = <&sys_clkin1>;
- clock-names = "sysclk";
- };
-
/* OCP2SCP3 */
ocp2scp@4a090000 {
compatible = "ti,omap-ocp2scp";
@@ -1151,9 +1329,10 @@
<0x4A096400 0x64>, /* phy_tx */
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_sata>;
+ syscon-phy-power = <&scm_conf 0x374>;
clocks = <&sys_clkin1>, <&sata_ref_clk>;
clock-names = "sysclk", "refclk";
+ syscon-pllreset = <&scm_conf 0x3fc>;
#phy-cells = <0>;
};
@@ -1162,16 +1341,18 @@
reg = <0x4a094000 0x80>, /* phy_rx */
<0x4a094400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
- ctrl-module = <&omap_control_pcie1phy>;
+ syscon-phy-power = <&scm_conf_pcie 0x1c>;
+ syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy1_32khz>,
<&optfclk_pciephy1_clk>,
<&optfclk_pciephy1_div_clk>,
- <&optfclk_pciephy_div>;
+ <&optfclk_pciephy_div>,
+ <&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
- "div-clk", "phy-div";
+ "div-clk", "phy-div", "sysclk";
#phy-cells = <0>;
};
@@ -1180,16 +1361,18 @@
reg = <0x4a095000 0x80>, /* phy_rx */
<0x4a095400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
- ctrl-module = <&omap_control_pcie2phy>;
+ syscon-phy-power = <&scm_conf_pcie 0x20>;
+ syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy2_32khz>,
<&optfclk_pciephy2_clk>,
<&optfclk_pciephy2_div_clk>,
- <&optfclk_pciephy_div>;
+ <&optfclk_pciephy_div>,
+ <&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
- "div-clk", "phy-div";
+ "div-clk", "phy-div", "sysclk";
#phy-cells = <0>;
status = "disabled";
};
@@ -1205,23 +1388,6 @@
ti,hwmods = "sata";
};
- omap_control_pcie1phy: control-phy@0x4a003c40 {
- compatible = "ti,control-phy-pcie";
- reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
- reg-names = "power", "control_sma", "pcie_pcs";
- clocks = <&sys_clkin1>;
- clock-names = "sysclk";
- };
-
- omap_control_pcie2phy: control-pcie@0x4a003c44 {
- compatible = "ti,control-phy-pcie";
- reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
- reg-names = "power", "control_sma", "pcie_pcs";
- clocks = <&sys_clkin1>;
- clock-names = "sysclk";
- status = "disabled";
- };
-
rtc: rtc@48838000 {
compatible = "ti,am3352-rtc";
reg = <0x48838000 0x100>;
@@ -1231,24 +1397,6 @@
clocks = <&sys_32k_ck>;
};
- omap_control_usb2phy1: control-phy@4a002300 {
- compatible = "ti,control-phy-usb2";
- reg = <0x4a002300 0x4>;
- reg-names = "power";
- };
-
- omap_control_usb3phy1: control-phy@4a002370 {
- compatible = "ti,control-phy-pipe3";
- reg = <0x4a002370 0x4>;
- reg-names = "power";
- };
-
- omap_control_usb2phy2: control-phy@0x4a002e74 {
- compatible = "ti,control-phy-usb2-dra7";
- reg = <0x4a002e74 0x4>;
- reg-names = "power";
- };
-
/* OCP2SCP1 */
ocp2scp@4a080000 {
compatible = "ti,omap-ocp2scp";
@@ -1259,9 +1407,9 @@
ti,hwmods = "ocp2scp1";
usb2_phy1: phy@4a084000 {
- compatible = "ti,omap-usb2";
+ compatible = "ti,dra7x-usb2", "ti,omap-usb2";
reg = <0x4a084000 0x400>;
- ctrl-module = <&omap_control_usb2phy1>;
+ syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
clock-names = "wkupclk",
@@ -1270,9 +1418,10 @@
};
usb2_phy2: phy@4a085000 {
- compatible = "ti,omap-usb2";
+ compatible = "ti,dra7x-usb2-phy2",
+ "ti,omap-usb2";
reg = <0x4a085000 0x400>;
- ctrl-module = <&omap_control_usb2phy2>;
+ syscon-phy-power = <&scm_conf 0xe74>;
clocks = <&usb_phy2_always_on_clk32k>,
<&usb_otg_ss2_refclk960m>;
clock-names = "wkupclk",
@@ -1286,7 +1435,7 @@
<0x4a084800 0x64>,
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_usb3phy1>;
+ syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>,
<&usb_otg_ss1_refclk960m>;
@@ -1309,10 +1458,14 @@
usb1: usb@48890000 {
compatible = "snps,dwc3";
reg = <0x48890000 0x17000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
phys = <&usb2_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
- tx-fifo-resize;
maximum-speed = "super-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
@@ -1332,10 +1485,14 @@
usb2: usb@488d0000 {
compatible = "snps,dwc3";
reg = <0x488d0000 0x17000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
- tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
@@ -1357,8 +1514,12 @@
usb3: usb@48910000 {
compatible = "snps,dwc3";
reg = <0x48910000 0x17000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- tx-fifo-resize;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
maximum-speed = "high-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
@@ -1379,10 +1540,16 @@
ti,hwmods = "gpmc";
reg = <0x50000000 0x37c>; /* device IO registers */
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 4 0>;
+ dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
status = "disabled";
};
@@ -1397,6 +1564,136 @@
status = "disabled";
};
+ mcasp1: mcasp@48460000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp1";
+ reg = <0x48460000 0x2000>,
+ <0x45800000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
+ <&mcasp1_ahclkr_mux>;
+ clock-names = "fck", "ahclkx", "ahclkr";
+ status = "disabled";
+ };
+
+ mcasp2: mcasp@48464000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp2";
+ reg = <0x48464000 0x2000>,
+ <0x45c00000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
+ <&mcasp2_ahclkr_mux>;
+ clock-names = "fck", "ahclkx", "ahclkr";
+ status = "disabled";
+ };
+
+ mcasp3: mcasp@48468000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp3";
+ reg = <0x48468000 0x2000>,
+ <0x46000000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp4: mcasp@4846c000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp4";
+ reg = <0x4846c000 0x2000>,
+ <0x48436000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp5: mcasp@48470000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp5";
+ reg = <0x48470000 0x2000>,
+ <0x4843a000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp6: mcasp@48474000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp6";
+ reg = <0x48474000 0x2000>,
+ <0x4844c000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp7: mcasp@48478000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp7";
+ reg = <0x48478000 0x2000>,
+ <0x48450000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp8: mcasp@4847c000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp8";
+ reg = <0x4847c000 0x2000>,
+ <0x48454000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
@@ -1412,25 +1709,34 @@
};
mac: ethernet@48484000 {
- compatible = "ti,cpsw";
+ compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
- clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
+ clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
- rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
- cpts_clock_mult = <0x80000000>;
+ cpts_clock_mult = <0x784CFE14>;
cpts_clock_shift = <29>;
syscon = <&scm_conf>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
#size-cells = <1>;
+
+ /*
+ * Do not allow gating of cpsw clock as workaround
+ * for errata i877. Keeping internal clock disabled
+ * causes the device switching characteristics
+ * to degrade over time and eventually fail to meet
+ * the data manual delay time/skew specs.
+ */
+ ti,no-idle;
+
/*
* rx_thresh_pend
* rx_pend
@@ -1445,7 +1751,7 @@
status = "disabled";
davinci_mdio: mdio@48485000 {
- compatible = "ti,davinci_mdio";
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
@@ -1527,12 +1833,157 @@
clock-names = "fck", "sys_clk";
};
};
+
+ epwmss0: epwmss@4843e000 {
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm0: pwm@4843e200 {
+ compatible = "ti,dra746-ehrpwm",
+ "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x4843e200 0x80>;
+ clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap0: ecap@4843e100 {
+ compatible = "ti,dra746-ecap",
+ "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x4843e100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ epwmss1: epwmss@48440000 {
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48440000 0x30>;
+ ti,hwmods = "epwmss1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm1: pwm@48440200 {
+ compatible = "ti,dra746-ehrpwm",
+ "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap1: ecap@48440100 {
+ compatible = "ti,dra746-ecap",
+ "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48440100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ epwmss2: epwmss@48442000 {
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48442000 0x30>;
+ ti,hwmods = "epwmss2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm2: pwm@48442200 {
+ compatible = "ti,dra746-ehrpwm",
+ "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48442200 0x80>;
+ clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap2: ecap@48442100 {
+ compatible = "ti,dra746-ecap",
+ "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48442100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ aes1: aes@4b500000 {
+ compatible = "ti,omap4-aes";
+ ti,hwmods = "aes1";
+ reg = <0x4b500000 0xa0>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ aes2: aes@4b700000 {
+ compatible = "ti,omap4-aes";
+ ti,hwmods = "aes2";
+ reg = <0x4b700000 0xa0>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ des: des@480a5000 {
+ compatible = "ti,omap4-des";
+ ti,hwmods = "des";
+ reg = <0x480a5000 0xa0>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ sham: sham@53100000 {
+ compatible = "ti,omap5-sham";
+ ti,hwmods = "sham";
+ reg = <0x4b101000 0x300>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 119 0>;
+ dma-names = "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ rng: rng@48090000 {
+ compatible = "ti,omap4-rng";
+ ti,hwmods = "rng";
+ reg = <0x48090000 0x2000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
};
thermal_zones: thermal-zones {
#include "omap4-cpu-thermal.dtsi"
#include "omap5-gpu-thermal.dtsi"
#include "omap5-core-thermal.dtsi"
+ #include "dra7-dspeve-thermal.dtsi"
+ #include "dra7-iva-thermal.dtsi"
};
};
diff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts
new file mode 100644
index 0000000..875116c
--- /dev/null
+++ b/arch/arm/dts/dra71-evm.dts
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "dra72-evm-common.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
+ model = "TI DRA718 EVM";
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
+ };
+
+ vpo_sd_1v8_3v3: gpio-regulator-TPS74801 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "vddshv8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ vin-supply = <&evm_5v0>;
+
+ gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0
+ 3000000 0x1>;
+ };
+
+ poweroff: gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ lp8733: lp8733@60 {
+ compatible = "ti,lp8733";
+ reg = <0x60>;
+
+ buck0-in-supply =<&vsys_3v3>;
+ buck1-in-supply =<&vsys_3v3>;
+ ldo0-in-supply =<&evm_5v0>;
+ ldo1-in-supply =<&evm_5v0>;
+
+ lp8733_regulators: regulators {
+ lp8733_buck0_reg: buck0 {
+ /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
+ regulator-name = "lp8733-buck0";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8733_buck1_reg: buck1 {
+ /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
+ regulator-name = "lp8733-buck1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8733_ldo0_reg: ldo0 {
+ /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */
+ regulator-name = "lp8733-ldo0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ lp8733_ldo1_reg: ldo1 {
+ /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */
+ regulator-name = "lp8733-ldo1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ lp8732: lp8732@61 {
+ compatible = "ti,lp8732";
+ reg = <0x61>;
+
+ buck0-in-supply =<&vsys_3v3>;
+ buck1-in-supply =<&vsys_3v3>;
+ ldo0-in-supply =<&vsys_3v3>;
+ ldo1-in-supply =<&vsys_3v3>;
+
+ lp8732_regulators: regulators {
+ lp8732_buck0_reg: buck0 {
+ /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */
+ regulator-name = "lp8732-buck0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8732_buck1_reg: buck1 {
+ /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */
+ regulator-name = "lp8732-buck1";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8732_ldo0_reg: ldo0 {
+ /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */
+ regulator-name = "lp8732-ldo0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8732_ldo1_reg: ldo1 {
+ /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */
+ regulator-name = "lp8732-ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio7>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&pcf_hdmi {
+ p0 {
+ /*
+ * PM_OEn to High: Disable routing I2C3 to PM_I2C
+ * With this PM_SEL(p3) should not matter
+ */
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "pm_oe_n";
+ };
+};
+
+&mmc1 {
+ vmmc_aux-supply = <&vpo_sd_1v8_3v3>;
+};
+
+&mac {
+ mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
+ <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
+ <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy-handle = <&dp83867_0>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy-handle = <&dp83867_1>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ dp83867_0: ethernet-phy@2 {
+ reg = <2>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,impedance-control = <0x1f>;
+ };
+
+ dp83867_1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,impedance-control = <0x1f>;
+ };
+};
+
+/* No Sata on this device */
+&sata_phy {
+ status = "disabled";
+};
+
+&sata {
+ status = "disabled";
+};
+
+/* No RTC on this device */
+&rtc {
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ phy-supply = <&lp8733_ldo1_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&lp8733_ldo1_reg>;
+};
+
+&dss {
+ /* Supplied by VDA_1V8_PLL */
+ vdda_video-supply = <&lp8732_ldo0_reg>;
+};
+
+&hdmi {
+ /* Supplied by VDA_1V8_PHY */
+ vdda_video-supply = <&lp8732_ldo1_reg>;
+};
diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi
new file mode 100644
index 0000000..c83f87f
--- /dev/null
+++ b/arch/arm/dts/dra72-evm-common.dtsi
@@ -0,0 +1,554 @@
+/*
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
+
+/ {
+ compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
+
+ aliases {
+ display0 = &hdmi0;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ tick-timer = &timer2;
+ };
+
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ evm_5v0: fixedregulator-evm5v0 {
+ /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ evm_3v3_sw: fixedregulator-evm_3v3 {
+ /* TPS22965DSG */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&evm_3v3_sw>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ evm_3v3_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_3v3_sw>;
+ enable-active-high;
+ gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
+ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Out",
+ "Microphone", "Mic Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ sound0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ system-clock-frequency = <5644800>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&atl_clkin2_ck>;
+ };
+ };
+};
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ dcan1_pins_default: dcan1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+ >;
+ };
+
+ dcan1_pins_sleep: dcan1_pins_sleep {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pcf_gpio_21: gpio@21 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ u-boot,i2c-offset-len = <0>;
+ reg = <0x21>;
+ lines-initial-states = <0x1408>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ tlv320aic3106: tlv320aic3106@19 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x19>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&evm_3v3_sw>;
+ IOVDD-supply = <&evm_3v3_sw>;
+ DRVDD-supply = <&evm_3v3_sw>;
+ DVDD-supply = <&aic_dvdd>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pcf_hdmi: pcf8575@26 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ u-boot,i2c-offset-len = <0>;
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * initial state is used here to keep the mdio interface
+ * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
+ * VIN2_S0 driven high otherwise Ethernet stops working
+ * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
+ */
+ lines-initial-states = <0x0f2b>;
+
+ p1 {
+ /* vin6_sel_s0: high: VIN6, low: audio */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "vin6_sel_s0";
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+ interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <&dra7_pmx_core 0x3e0>;
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay";
+ ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
+ nand@0,0 {
+ /* To use NAND, DIP switch SW5 must be set like so:
+ * SW5.1 (NAND_SELn) = ON (LOW)
+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
+ */
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
+ ti,nand-ecc-opt = "bch8";
+ ti,elm-id = <&elm>;
+ nand-bus-width = <16>;
+ gpmc,device-width = <2>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <80>;
+ gpmc,cs-wr-off-ns = <80>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <60>;
+ gpmc,adv-wr-off-ns = <60>;
+ gpmc,we-on-ns = <10>;
+ gpmc,we-off-ns = <50>;
+ gpmc,oe-on-ns = <4>;
+ gpmc,oe-off-ns = <40>;
+ gpmc,access-ns = <40>;
+ gpmc,wr-access-ns = <80>;
+ gpmc,rd-cycle-ns = <80>;
+ gpmc,wr-cycle-ns = <80>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+ * which can be independently programmable. For
+ * NAND flash this is equal to size of erase-block */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "NAND.SPL";
+ reg = <0x00000000 0x000020000>;
+ };
+ partition@1 {
+ label = "NAND.SPL.backup1";
+ reg = <0x00020000 0x00020000>;
+ };
+ partition@2 {
+ label = "NAND.SPL.backup2";
+ reg = <0x00040000 0x00020000>;
+ };
+ partition@3 {
+ label = "NAND.SPL.backup3";
+ reg = <0x00060000 0x00020000>;
+ };
+ partition@4 {
+ label = "NAND.u-boot-spl-os";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition@5 {
+ label = "NAND.u-boot";
+ reg = <0x000c0000 0x00100000>;
+ };
+ partition@6 {
+ label = "NAND.u-boot-env";
+ reg = <0x001c0000 0x00020000>;
+ };
+ partition@7 {
+ label = "NAND.u-boot-env.backup1";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition@8 {
+ label = "NAND.kernel";
+ reg = <0x00200000 0x00800000>;
+ };
+ partition@9 {
+ label = "NAND.file-system";
+ reg = <0x00a00000 0x0f600000>;
+ };
+ };
+};
+
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
+
+&usb1 {
+ dr_mode = "peripheral";
+};
+
+&usb2 {
+ dr_mode = "host";
+};
+
+&mmc1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+ vmmc-supply = <&evm_3v3_sd>;
+ bus-width = <4>;
+ /*
+ * SDCD signal is not being used here - using the fact that GPIO mode
+ * is a viable alternative
+ */
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+ max-frequency = <192000000>;
+};
+
+&mmc2 {
+ /* SW5-3 in ON position */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_default>;
+
+ vmmc-supply = <&evm_3v3_sw>;
+ bus-width = <8>;
+ ti,non-removable;
+ max-frequency = <192000000>;
+};
+
+&mac {
+ status = "okay";
+};
+
+&dcan1 {
+ status = "ok";
+ pinctrl-names = "default", "sleep", "active";
+ pinctrl-0 = <&dcan1_pins_sleep>;
+ pinctrl-1 = <&dcan1_pins_sleep>;
+ pinctrl-2 = <&dcan1_pins_default>;
+};
+
+&qspi {
+ status = "okay";
+
+ spi-max-frequency = <76800000>;
+ m25p80@0 {
+ compatible = "s25fl256s1", "spi-flash";
+ spi-max-frequency = <76800000>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+ * The ROM checks the first four physical blocks
+ * for a valid file to boot and the flash here is
+ * 64KiB block size.
+ */
+ partition@0 {
+ label = "QSPI.SPL";
+ reg = <0x00000000 0x000010000>;
+ };
+ partition@1 {
+ label = "QSPI.SPL.backup1";
+ reg = <0x00010000 0x00010000>;
+ };
+ partition@2 {
+ label = "QSPI.SPL.backup2";
+ reg = <0x00020000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.SPL.backup3";
+ reg = <0x00030000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.u-boot";
+ reg = <0x00040000 0x00100000>;
+ };
+ partition@5 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x00140000 0x00080000>;
+ };
+ partition@6 {
+ label = "QSPI.u-boot-env";
+ reg = <0x001c0000 0x00010000>;
+ };
+ partition@7 {
+ label = "QSPI.u-boot-env.backup1";
+ reg = <0x001d0000 0x0010000>;
+ };
+ partition@8 {
+ label = "QSPI.kernel";
+ reg = <0x001e0000 0x0800000>;
+ };
+ partition@9 {
+ label = "QSPI.file-system";
+ reg = <0x009e0000 0x01620000>;
+ };
+ };
+};
+
+&dss {
+ status = "ok";
+};
+
+&hdmi {
+ status = "ok";
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
+
+&atl {
+ assigned-clocks = <&abe_dpll_sys_clk_mux>,
+ <&atl_gfclk_mux>,
+ <&dpll_abe_ck>,
+ <&dpll_abe_m2x2_ck>,
+ <&atl_clkin2_ck>;
+ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
+ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
+
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&atl_clkin2_ck>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts
new file mode 100644
index 0000000..5a1bb34
--- /dev/null
+++ b/arch/arm/dts/dra72-evm-revc.dts
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "dra72-evm-common.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "TI DRA722 Rev C EVM";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
+ };
+};
+
+&i2c1 {
+ tps65917: tps65917@58 {
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+ };
+};
+
+#include "dra72-evm-tps65917.dtsi"
+
+&ldo2_reg {
+ /* LDO2_OUT --> VDDA_1V8_PHY2 */
+ regulator-always-on;
+ regulator-boot-on;
+};
+
+&hdmi {
+ vdda-supply = <&ldo2_reg>;
+};
+
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&mac {
+ mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
+ <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
+ <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy-handle = <&dp83867_0>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy-handle = <&dp83867_1>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ dp83867_0: ethernet-phy@2 {
+ reg = <2>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,min-output-imepdance;
+ };
+
+ dp83867_1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,min-output-imepdance;
+ };
+};
diff --git a/arch/arm/dts/dra72-evm-tps65917.dtsi b/arch/arm/dts/dra72-evm-tps65917.dtsi
new file mode 100644
index 0000000..ee6dac4
--- /dev/null
+++ b/arch/arm/dts/dra72-evm-tps65917.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
+ */
+
+&tps65917 {
+ compatible = "ti,tps65917";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,system-power-controller;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ smps1-in-supply = <&vsys_3v3>;
+ smps2-in-supply = <&vsys_3v3>;
+ smps3-in-supply = <&vsys_3v3>;
+ smps4-in-supply = <&vsys_3v3>;
+ smps5-in-supply = <&vsys_3v3>;
+ ldo1-in-supply = <&vsys_3v3>;
+ ldo2-in-supply = <&vsys_3v3>;
+ ldo3-in-supply = <&vsys_3v3>;
+ ldo4-in-supply = <&evm_5v0>;
+ ldo5-in-supply = <&vsys_3v3>;
+
+ tps65917_regulators: regulators {
+ smps1_reg: smps1 {
+ /* VDD_MPU */
+ regulator-name = "smps1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps2_reg: smps2 {
+ /* VDD_CORE */
+ regulator-name = "smps2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_GPU IVA DSPEVE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDDS1V8 */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDD_DDR */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> SDIO */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-bypass;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-bypass;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHY */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+};
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index e7c5db2..cd9c4ff 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -1,593 +1,41 @@
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-/dts-v1/;
-
-#include "dra72x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
+#include "dra72-evm-common.dtsi"
/ {
model = "TI DRA722";
- compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
- chosen {
- stdout-path = &uart1;
- tick-timer = &timer2;
- };
-
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x80000000 0x40000000>; /* 1024 MB */
- };
-
- aliases {
- display0 = &hdmi0;
- };
-
- evm_3v3: fixedregulator-evm_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "evm_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- evm_3v3_sd: fixedregulator-sd {
- compatible = "regulator-fixed";
- regulator-name = "evm_3v3_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
- };
-
- extcon_usb1: extcon_usb1 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
- };
-
- extcon_usb2: extcon_usb2 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
- };
-
- hdmi0: connector {
- compatible = "hdmi-connector";
- label = "hdmi";
-
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&tpd12s015_out>;
- };
- };
- };
-
- tpd12s015: encoder {
- compatible = "ti,tpd12s015";
-
- pinctrl-names = "default";
- pinctrl-0 = <&tpd12s015_pins>;
-
- gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
- <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tpd12s015_in: endpoint {
- remote-endpoint = <&hdmi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tpd12s015_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&dra7_pmx_core {
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
- 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
- >;
- };
-
- i2c5_pins: pinmux_i2c5_pins {
- pinctrl-single,pins = <
- 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
- 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
- >;
- };
-
- nand_default: nand_default {
- pinctrl-single,pins = <
- 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
- 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
- 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
- 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
- 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
- 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
- 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
- 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
- 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
- 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
- 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
- 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
- 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
- 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
- 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
- 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
- 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
- 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
- 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
- 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
- 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
- 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
- >;
- };
-
- usb1_pins: pinmux_usb1_pins {
- pinctrl-single,pins = <
- 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
- >;
- };
-
- usb2_pins: pinmux_usb2_pins {
- pinctrl-single,pins = <
- 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
- >;
- };
-
- tps65917_pins_default: tps65917_pins_default {
- pinctrl-single,pins = <
- 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
- >;
- };
-
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-
- dcan1_pins_default: dcan1_pins_default {
- pinctrl-single,pins = <
- 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
- 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
- >;
- };
-
- dcan1_pins_sleep: dcan1_pins_sleep {
- pinctrl-single,pins = <
- 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
- 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
- >;
- };
-
- qspi1_pins: pinmux_qspi1_pins {
- pinctrl-single,pins = <
- 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
- 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
- 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
- 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
- 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
- 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
- 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
- >;
- };
-
- hdmi_pins: pinmux_hdmi_pins {
- pinctrl-single,pins = <
- 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
- 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
- >;
- };
-
- tpd12s015_pins: pinmux_tpd12s015_pins {
- pinctrl-single,pins = <
- 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
- >;
+ reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
};
&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clock-frequency = <400000>;
-
tps65917: tps65917@58 {
- compatible = "ti,tps65917";
reg = <0x58>;
- pinctrl-names = "default";
- pinctrl-0 = <&tps65917_pins_default>;
-
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
- interrupt-controller;
- #interrupt-cells = <2>;
-
- ti,system-power-controller;
-
- tps65917_pmic {
- compatible = "ti,tps65917-pmic";
-
- regulators {
- smps1_reg: smps1 {
- /* VDD_MPU */
- regulator-name = "smps1";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps2_reg: smps2 {
- /* VDD_CORE */
- regulator-name = "smps2";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1060000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps3_reg: smps3 {
- /* VDD_GPU IVA DSPEVE */
- regulator-name = "smps3";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps4_reg: smps4 {
- /* VDDS1V8 */
- regulator-name = "smps4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps5_reg: smps5 {
- /* VDD_DDR */
- regulator-name = "smps5";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- /* LDO1_OUT --> SDIO */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
-
- ldo2_reg: ldo2 {
- /* LDO2_OUT --> TP1017 (UNUSED) */
- regulator-name = "ldo2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo3_reg: ldo3 {
- /* VDDA_1V8_PHY */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5_reg: ldo5 {
- /* VDDA_1V8_PLL */
- regulator-name = "ldo5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo4_reg: ldo4 {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldo4";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
- };
- };
-
- tps65917_power_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&tps65917>;
- interrupts = <1 IRQ_TYPE_NONE>;
- wakeup-source;
- ti,palmas-long-press-seconds = <6>;
- };
- };
-
- pcf_gpio_21: gpio@21 {
- compatible = "ti,pcf8575";
- reg = <0x21>;
- lines-initial-states = <0x1408>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gpio6>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- u-boot,i2c-offset-len = <0>;
};
};
-&i2c5 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins>;
- clock-frequency = <400000>;
+#include "dra72-evm-tps65917.dtsi"
- pcf_hdmi: pcf8575@26 {
- compatible = "nxp,pcf8575";
- reg = <0x26>;
- gpio-controller;
- #gpio-cells = <2>;
- /*
- * initial state is used here to keep the mdio interface
- * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
- * VIN2_S0 driven high otherwise Ethernet stops working
- * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
- */
- lines-initial-states = <0x0f2b>;
- u-boot,i2c-offset-len = <0>;
- };
+&hdmi {
+ vdda-supply = <&ldo3_reg>;
};
-&uart1 {
- status = "okay";
-};
-
-&elm {
- status = "okay";
-};
-
-&gpmc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&nand_default>;
- ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
- nand@0,0 {
- /* To use NAND, DIP switch SW5 must be set like so:
- * SW5.1 (NAND_SELn) = ON (LOW)
- * SW5.9 (GPMC_WPN) = OFF (HIGH)
- */
- reg = <0 0 4>; /* device IO registers */
- ti,nand-ecc-opt = "bch8";
- ti,elm-id = <&elm>;
- nand-bus-width = <16>;
- gpmc,device-width = <2>;
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <80>;
- gpmc,cs-wr-off-ns = <80>;
- gpmc,adv-on-ns = <0>;
- gpmc,adv-rd-off-ns = <60>;
- gpmc,adv-wr-off-ns = <60>;
- gpmc,we-on-ns = <10>;
- gpmc,we-off-ns = <50>;
- gpmc,oe-on-ns = <4>;
- gpmc,oe-off-ns = <40>;
- gpmc,access-ns = <40>;
- gpmc,wr-access-ns = <80>;
- gpmc,rd-cycle-ns = <80>;
- gpmc,wr-cycle-ns = <80>;
- gpmc,bus-turnaround-ns = <0>;
- gpmc,cycle2cycle-delay-ns = <0>;
- gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
- gpmc,wr-data-mux-bus-ns = <0>;
- /* MTD partition table */
- /* All SPL-* partitions are sized to minimal length
- * which can be independently programmable. For
- * NAND flash this is equal to size of erase-block */
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "NAND.SPL";
- reg = <0x00000000 0x000020000>;
- };
- partition@1 {
- label = "NAND.SPL.backup1";
- reg = <0x00020000 0x00020000>;
- };
- partition@2 {
- label = "NAND.SPL.backup2";
- reg = <0x00040000 0x00020000>;
- };
- partition@3 {
- label = "NAND.SPL.backup3";
- reg = <0x00060000 0x00020000>;
- };
- partition@4 {
- label = "NAND.u-boot-spl-os";
- reg = <0x00080000 0x00040000>;
- };
- partition@5 {
- label = "NAND.u-boot";
- reg = <0x000c0000 0x00100000>;
- };
- partition@6 {
- label = "NAND.u-boot-env";
- reg = <0x001c0000 0x00020000>;
- };
- partition@7 {
- label = "NAND.u-boot-env.backup1";
- reg = <0x001e0000 0x00020000>;
- };
- partition@8 {
- label = "NAND.kernel";
- reg = <0x00200000 0x00800000>;
- };
- partition@9 {
- label = "NAND.file-system";
- reg = <0x00a00000 0x0f600000>;
- };
- };
-};
-
-&usb2_phy1 {
- phy-supply = <&ldo4_reg>;
-};
-
-&usb2_phy2 {
- phy-supply = <&ldo4_reg>;
-};
-
-&omap_dwc3_1 {
- extcon = <&extcon_usb1>;
-};
-
-&omap_dwc3_2 {
- extcon = <&extcon_usb2>;
-};
-
-&usb1 {
- dr_mode = "peripheral";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins>;
-};
-
-&usb2 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_pins>;
-};
-
-&mmc1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_default>;
-
- vmmc_aux-supply = <&ldo1_reg>;
- vmmc-supply = <&evm_3v3_sd>;
- bus-width = <4>;
- /*
- * SDCD signal is not being used here - using the fact that GPIO mode
- * is a viable alternative
- */
- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
-};
-
-&mmc2 {
- /* SW5-3 in ON position */
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_default>;
-
- vmmc-supply = <&evm_3v3>;
- bus-width = <8>;
- ti,non-removable;
-};
-
-&dra7_pmx_core {
- cpsw_default: cpsw_default {
- pinctrl-single,pins = <
- /* Slave 2 */
- 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
- 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
- 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
- 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
- 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
- 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
- 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
- 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
- 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
- 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
- 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
- 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
- >;
-
- };
-
- cpsw_sleep: cpsw_sleep {
- pinctrl-single,pins = <
- /* Slave 2 */
- 0x198 (MUX_MODE15)
- 0x19c (MUX_MODE15)
- 0x1a0 (MUX_MODE15)
- 0x1a4 (MUX_MODE15)
- 0x1a8 (MUX_MODE15)
- 0x1ac (MUX_MODE15)
- 0x1b0 (MUX_MODE15)
- 0x1b4 (MUX_MODE15)
- 0x1b8 (MUX_MODE15)
- 0x1bc (MUX_MODE15)
- 0x1c0 (MUX_MODE15)
- 0x1c4 (MUX_MODE15)
- >;
- };
-
- davinci_mdio_default: davinci_mdio_default {
- pinctrl-single,pins = <
- /* MDIO */
- 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
- 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
- >;
- };
-
- davinci_mdio_sleep: davinci_mdio_sleep {
- pinctrl-single,pins = <
- 0x23c (MUX_MODE15)
- 0x240 (MUX_MODE15)
- >;
- };
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
};
&mac {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cpsw_default>;
- pinctrl-1 = <&cpsw_sleep>;
+ slaves = <1>;
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
};
@@ -595,100 +43,3 @@
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
};
-
-&davinci_mdio {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&davinci_mdio_default>;
- pinctrl-1 = <&davinci_mdio_sleep>;
-};
-
-&dcan1 {
- status = "ok";
- pinctrl-names = "default", "sleep", "active";
- pinctrl-0 = <&dcan1_pins_sleep>;
- pinctrl-1 = <&dcan1_pins_sleep>;
- pinctrl-2 = <&dcan1_pins_default>;
-};
-
-&qspi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&qspi1_pins>;
-
- spi-max-frequency = <76800000>;
- m25p80@0 {
- compatible = "s25fl256s1","spi-flash";
- spi-max-frequency = <64000000>;
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* MTD partition table.
- * The ROM checks the first four physical blocks
- * for a valid file to boot and the flash here is
- * 64KiB block size.
- */
- partition@0 {
- label = "QSPI.SPL";
- reg = <0x00000000 0x000010000>;
- };
- partition@1 {
- label = "QSPI.SPL.backup1";
- reg = <0x00010000 0x00010000>;
- };
- partition@2 {
- label = "QSPI.SPL.backup2";
- reg = <0x00020000 0x00010000>;
- };
- partition@3 {
- label = "QSPI.SPL.backup3";
- reg = <0x00030000 0x00010000>;
- };
- partition@4 {
- label = "QSPI.u-boot";
- reg = <0x00040000 0x00100000>;
- };
- partition@5 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x00140000 0x00080000>;
- };
- partition@6 {
- label = "QSPI.u-boot-env";
- reg = <0x001c0000 0x00010000>;
- };
- partition@7 {
- label = "QSPI.u-boot-env.backup1";
- reg = <0x001d0000 0x0010000>;
- };
- partition@8 {
- label = "QSPI.kernel";
- reg = <0x001e0000 0x0800000>;
- };
- partition@9 {
- label = "QSPI.file-system";
- reg = <0x009e0000 0x01620000>;
- };
- };
-};
-
-&dss {
- status = "ok";
-
- vdda_video-supply = <&ldo5_reg>;
-};
-
-&hdmi {
- status = "ok";
- vdda-supply = <&ldo3_reg>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pins>;
-
- port {
- hdmi_out: endpoint {
- remote-endpoint = <&tpd12s015_in>;
- };
- };
-};
diff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi
index 357bede..3330738 100644
--- a/arch/arm/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/dts/dra7xx-clocks.dtsi
@@ -98,12 +98,20 @@
clock-frequency = <32768>;
};
- sys_32k_ck: sys_32k_ck {
+ sys_clk32_crystal_ck: sys_clk32_crystal_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
+ sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin1>;
+ clock-mult = <1>;
+ clock-div = <610>;
+ };
+
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -188,7 +196,7 @@
clock-frequency = <0>;
};
- dpll_abe_ck: dpll_abe_ck {
+ dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
@@ -201,7 +209,7 @@
clocks = <&dpll_abe_ck>;
};
- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
@@ -212,7 +220,7 @@
ti,invert-autoidle-bit;
};
- abe_clk: abe_clk {
+ abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
@@ -221,7 +229,7 @@
ti,index-power-of-two;
};
- dpll_abe_m2_ck: dpll_abe_m2_ck {
+ dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_ck>;
@@ -232,7 +240,7 @@
ti,invert-autoidle-bit;
};
- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
@@ -243,7 +251,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_byp_mux: dpll_core_byp_mux {
+ dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -251,7 +259,7 @@
reg = <0x012c>;
};
- dpll_core_ck: dpll_core_ck {
+ dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
@@ -264,7 +272,7 @@
clocks = <&dpll_core_ck>;
};
- dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+ dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -283,14 +291,14 @@
clock-div = <1>;
};
- dpll_mpu_ck: dpll_mpu_ck {
+ dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
@@ -317,7 +325,7 @@
clock-div = <1>;
};
- dpll_dsp_byp_mux: dpll_dsp_byp_mux {
+ dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
@@ -325,14 +333,14 @@
reg = <0x0240>;
};
- dpll_dsp_ck: dpll_dsp_ck {
+ dpll_dsp_ck: dpll_dsp_ck@234 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
};
- dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+ dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_ck>;
@@ -351,7 +359,7 @@
clock-div = <1>;
};
- dpll_iva_byp_mux: dpll_iva_byp_mux {
+ dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
@@ -359,14 +367,14 @@
reg = <0x01ac>;
};
- dpll_iva_ck: dpll_iva_ck {
+ dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
};
- dpll_iva_m2_ck: dpll_iva_m2_ck {
+ dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_ck>;
@@ -385,7 +393,7 @@
clock-div = <1>;
};
- dpll_gpu_byp_mux: dpll_gpu_byp_mux {
+ dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -393,14 +401,14 @@
reg = <0x02e4>;
};
- dpll_gpu_ck: dpll_gpu_ck {
+ dpll_gpu_ck: dpll_gpu_ck@2d8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
};
- dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+ dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_ck>;
@@ -411,7 +419,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_m2_ck: dpll_core_m2_ck {
+ dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_ck>;
@@ -430,7 +438,7 @@
clock-div = <1>;
};
- dpll_ddr_byp_mux: dpll_ddr_byp_mux {
+ dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -438,14 +446,14 @@
reg = <0x021c>;
};
- dpll_ddr_ck: dpll_ddr_ck {
+ dpll_ddr_ck: dpll_ddr_ck@210 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+ dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_ck>;
@@ -456,7 +464,7 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_byp_mux: dpll_gmac_byp_mux {
+ dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -464,14 +472,14 @@
reg = <0x02b4>;
};
- dpll_gmac_ck: dpll_gmac_ck {
+ dpll_gmac_ck: dpll_gmac_ck@2a8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
- dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+ dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_ck>;
@@ -530,7 +538,7 @@
clock-div = <1>;
};
- dpll_eve_byp_mux: dpll_eve_byp_mux {
+ dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
@@ -538,14 +546,14 @@
reg = <0x0290>;
};
- dpll_eve_ck: dpll_eve_ck {
+ dpll_eve_ck: dpll_eve_ck@284 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
- dpll_eve_m2_ck: dpll_eve_m2_ck {
+ dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_eve_ck>;
@@ -564,7 +572,7 @@
clock-div = <1>;
};
- dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+ dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -575,7 +583,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+ dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -586,7 +594,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+ dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -597,7 +605,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+ dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -608,7 +616,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+ dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -625,7 +633,7 @@
clocks = <&dpll_ddr_ck>;
};
- dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+ dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_x2_ck>;
@@ -642,7 +650,7 @@
clocks = <&dpll_dsp_ck>;
};
- dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+ dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_x2_ck>;
@@ -659,7 +667,7 @@
clocks = <&dpll_gmac_ck>;
};
- dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+ dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
@@ -670,7 +678,7 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+ dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
@@ -681,7 +689,7 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+ dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
@@ -692,7 +700,7 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+ dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
@@ -727,7 +735,7 @@
clock-div = <1>;
};
- l3_iclk_div: l3_iclk_div {
+ l3_iclk_div: l3_iclk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
ti,max-div = <2>;
@@ -777,7 +785,7 @@
clock-div = <1>;
};
- ipu1_gfclk_mux: ipu1_gfclk_mux {
+ ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
@@ -785,7 +793,7 @@
reg = <0x0520>;
};
- mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+ mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -793,7 +801,7 @@
reg = <0x0550>;
};
- mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+ mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -801,7 +809,7 @@
reg = <0x0550>;
};
- mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+ mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -809,7 +817,7 @@
reg = <0x0550>;
};
- timer5_gfclk_mux: timer5_gfclk_mux {
+ timer5_gfclk_mux: timer5_gfclk_mux@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -817,7 +825,7 @@
reg = <0x0558>;
};
- timer6_gfclk_mux: timer6_gfclk_mux {
+ timer6_gfclk_mux: timer6_gfclk_mux@560 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -825,7 +833,7 @@
reg = <0x0560>;
};
- timer7_gfclk_mux: timer7_gfclk_mux {
+ timer7_gfclk_mux: timer7_gfclk_mux@568 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -833,7 +841,7 @@
reg = <0x0568>;
};
- timer8_gfclk_mux: timer8_gfclk_mux {
+ timer8_gfclk_mux: timer8_gfclk_mux@570 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -841,7 +849,7 @@
reg = <0x0570>;
};
- uart6_gfclk_mux: uart6_gfclk_mux {
+ uart6_gfclk_mux: uart6_gfclk_mux@580 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -856,7 +864,7 @@
};
};
&prm_clocks {
- sys_clkin1: sys_clkin1 {
+ sys_clkin1: sys_clkin1@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -864,28 +872,28 @@
ti,index-starts-at-one;
};
- abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+ abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0118>;
};
- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x0114>;
};
- abe_dpll_clk_mux: abe_dpll_clk_mux {
+ abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x010c>;
};
- abe_24m_fclk: abe_24m_fclk {
+ abe_24m_fclk: abe_24m_fclk@11c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
@@ -893,7 +901,7 @@
ti,dividers = <8>, <16>;
};
- aess_fclk: aess_fclk {
+ aess_fclk: aess_fclk@178 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
@@ -901,7 +909,7 @@
ti,max-div = <2>;
};
- abe_giclk_div: abe_giclk_div {
+ abe_giclk_div: abe_giclk_div@174 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&aess_fclk>;
@@ -909,7 +917,7 @@
ti,max-div = <2>;
};
- abe_lp_clk_div: abe_lp_clk_div {
+ abe_lp_clk_div: abe_lp_clk_div@1d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
@@ -917,7 +925,7 @@
ti,dividers = <16>, <32>;
};
- abe_sys_clk_div: abe_sys_clk_div {
+ abe_sys_clk_div: abe_sys_clk_div@120 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -925,14 +933,14 @@
ti,max-div = <2>;
};
- adc_gfclk_mux: adc_gfclk_mux {
+ adc_gfclk_mux: adc_gfclk_mux@1dc {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
reg = <0x01dc>;
};
- sys_clk1_dclk_div: sys_clk1_dclk_div {
+ sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -941,7 +949,7 @@
ti,index-power-of-two;
};
- sys_clk2_dclk_div: sys_clk2_dclk_div {
+ sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin2>;
@@ -950,7 +958,7 @@
ti,index-power-of-two;
};
- per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+ per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
@@ -959,7 +967,7 @@
ti,index-power-of-two;
};
- dsp_gclk_div: dsp_gclk_div {
+ dsp_gclk_div: dsp_gclk_div@18c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_m2_ck>;
@@ -968,7 +976,7 @@
ti,index-power-of-two;
};
- gpu_dclk: gpu_dclk {
+ gpu_dclk: gpu_dclk@1a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_m2_ck>;
@@ -977,7 +985,7 @@
ti,index-power-of-two;
};
- emif_phy_dclk_div: emif_phy_dclk_div {
+ emif_phy_dclk_div: emif_phy_dclk_div@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_m2_ck>;
@@ -986,7 +994,7 @@
ti,index-power-of-two;
};
- gmac_250m_dclk_div: gmac_250m_dclk_div {
+ gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_m2_ck>;
@@ -995,7 +1003,15 @@
ti,index-power-of-two;
};
- l3init_480m_dclk_div: l3init_480m_dclk_div {
+ gmac_main_clk: gmac_main_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&gmac_250m_dclk_div>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
@@ -1004,7 +1020,7 @@
ti,index-power-of-two;
};
- usb_otg_dclk_div: usb_otg_dclk_div {
+ usb_otg_dclk_div: usb_otg_dclk_div@184 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&usb_otg_clkin_ck>;
@@ -1013,7 +1029,7 @@
ti,index-power-of-two;
};
- sata_dclk_div: sata_dclk_div {
+ sata_dclk_div: sata_dclk_div@1c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -1022,7 +1038,7 @@
ti,index-power-of-two;
};
- pcie2_dclk_div: pcie2_dclk_div {
+ pcie2_dclk_div: pcie2_dclk_div@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_m2_ck>;
@@ -1031,7 +1047,7 @@
ti,index-power-of-two;
};
- pcie_dclk_div: pcie_dclk_div {
+ pcie_dclk_div: pcie_dclk_div@1b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&apll_pcie_m2_ck>;
@@ -1040,7 +1056,7 @@
ti,index-power-of-two;
};
- emu_dclk_div: emu_dclk_div {
+ emu_dclk_div: emu_dclk_div@194 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -1049,7 +1065,7 @@
ti,index-power-of-two;
};
- secure_32k_dclk_div: secure_32k_dclk_div {
+ secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&secure_32k_clk_src_ck>;
@@ -1058,21 +1074,21 @@
ti,index-power-of-two;
};
- clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+ clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0158>;
};
- clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+ clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x015c>;
};
- clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+ clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
@@ -1087,21 +1103,21 @@
clock-div = <2>;
};
- eve_clk: eve_clk {
+ eve_clk: eve_clk@180 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
reg = <0x0180>;
};
- hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+ hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0164>;
};
- mlb_clk: mlb_clk {
+ mlb_clk: mlb_clk@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlb_clkin_ck>;
@@ -1110,7 +1126,7 @@
ti,index-power-of-two;
};
- mlbp_clk: mlbp_clk {
+ mlbp_clk: mlbp_clk@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlbp_clkin_ck>;
@@ -1119,7 +1135,7 @@
ti,index-power-of-two;
};
- per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+ per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
@@ -1128,7 +1144,7 @@
ti,index-power-of-two;
};
- timer_sys_clk_div: timer_sys_clk_div {
+ timer_sys_clk_div: timer_sys_clk_div@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -1136,28 +1152,28 @@
ti,max-div = <2>;
};
- video1_dpll_clk_mux: video1_dpll_clk_mux {
+ video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0168>;
};
- video2_dpll_clk_mux: video2_dpll_clk_mux {
+ video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x016c>;
};
- wkupaon_iclk_mux: wkupaon_iclk_mux {
+ wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
- gpio1_dbclk: gpio1_dbclk {
+ gpio1_dbclk: gpio1_dbclk@1838 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1165,7 +1181,7 @@
reg = <0x1838>;
};
- dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+ dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
@@ -1173,7 +1189,7 @@
reg = <0x1888>;
};
- timer1_gfclk_mux: timer1_gfclk_mux {
+ timer1_gfclk_mux: timer1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1181,7 +1197,7 @@
reg = <0x1840>;
};
- uart10_gfclk_mux: uart10_gfclk_mux {
+ uart10_gfclk_mux: uart10_gfclk_mux@1880 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1190,14 +1206,14 @@
};
};
&cm_core_clocks {
- dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+ dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&sys_clkin1>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
- dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
@@ -1216,7 +1232,7 @@
ti,bit-shift = <7>;
};
- apll_pcie_ck: apll_pcie_ck {
+ apll_pcie_ck: apll_pcie_ck@21c {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
@@ -1305,7 +1321,7 @@
clock-div = <1>;
};
- dpll_per_byp_mux: dpll_per_byp_mux {
+ dpll_per_byp_mux: dpll_per_byp_mux@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
@@ -1313,14 +1329,14 @@
reg = <0x014c>;
};
- dpll_per_ck: dpll_per_ck {
+ dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
- dpll_per_m2_ck: dpll_per_m2_ck {
+ dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
@@ -1339,7 +1355,7 @@
clock-div = <1>;
};
- dpll_usb_byp_mux: dpll_usb_byp_mux {
+ dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
@@ -1347,14 +1363,14 @@
reg = <0x018c>;
};
- dpll_usb_ck: dpll_usb_ck {
+ dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
- dpll_usb_m2_ck: dpll_usb_m2_ck {
+ dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
@@ -1365,7 +1381,7 @@
ti,invert-autoidle-bit;
};
- dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+ dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
@@ -1382,7 +1398,7 @@
clocks = <&dpll_per_ck>;
};
- dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+ dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1393,7 +1409,7 @@
ti,invert-autoidle-bit;
};
- dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+ dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1404,7 +1420,7 @@
ti,invert-autoidle-bit;
};
- dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+ dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1415,7 +1431,7 @@
ti,invert-autoidle-bit;
};
- dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+ dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1426,7 +1442,7 @@
ti,invert-autoidle-bit;
};
- dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1485,7 +1501,7 @@
clock-div = <2>;
};
- l3init_60m_fclk: l3init_60m_fclk {
+ l3init_60m_fclk: l3init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
@@ -1493,7 +1509,7 @@
ti,dividers = <1>, <8>;
};
- clkout2_clk: clkout2_clk {
+ clkout2_clk: clkout2_clk@6b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkoutmux2_clk_mux>;
@@ -1501,7 +1517,7 @@
reg = <0x06b0>;
};
- l3init_960m_gfclk: l3init_960m_gfclk {
+ l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
@@ -1509,7 +1525,7 @@
reg = <0x06c0>;
};
- dss_32khz_clk: dss_32khz_clk {
+ dss_32khz_clk: dss_32khz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1517,7 +1533,7 @@
reg = <0x1120>;
};
- dss_48mhz_clk: dss_48mhz_clk {
+ dss_48mhz_clk: dss_48mhz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
@@ -1525,7 +1541,7 @@
reg = <0x1120>;
};
- dss_dss_clk: dss_dss_clk {
+ dss_dss_clk: dss_dss_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_h12x2_ck>;
@@ -1534,7 +1550,7 @@
ti,set-rate-parent;
};
- dss_hdmi_clk: dss_hdmi_clk {
+ dss_hdmi_clk: dss_hdmi_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&hdmi_dpll_clk_mux>;
@@ -1542,7 +1558,7 @@
reg = <0x1120>;
};
- dss_video1_clk: dss_video1_clk {
+ dss_video1_clk: dss_video1_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video1_dpll_clk_mux>;
@@ -1550,7 +1566,7 @@
reg = <0x1120>;
};
- dss_video2_clk: dss_video2_clk {
+ dss_video2_clk: dss_video2_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video2_dpll_clk_mux>;
@@ -1558,7 +1574,7 @@
reg = <0x1120>;
};
- gpio2_dbclk: gpio2_dbclk {
+ gpio2_dbclk: gpio2_dbclk@1760 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1566,7 +1582,7 @@
reg = <0x1760>;
};
- gpio3_dbclk: gpio3_dbclk {
+ gpio3_dbclk: gpio3_dbclk@1768 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1574,7 +1590,7 @@
reg = <0x1768>;
};
- gpio4_dbclk: gpio4_dbclk {
+ gpio4_dbclk: gpio4_dbclk@1770 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1582,7 +1598,7 @@
reg = <0x1770>;
};
- gpio5_dbclk: gpio5_dbclk {
+ gpio5_dbclk: gpio5_dbclk@1778 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1590,7 +1606,7 @@
reg = <0x1778>;
};
- gpio6_dbclk: gpio6_dbclk {
+ gpio6_dbclk: gpio6_dbclk@1780 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1598,7 +1614,7 @@
reg = <0x1780>;
};
- gpio7_dbclk: gpio7_dbclk {
+ gpio7_dbclk: gpio7_dbclk@1810 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1606,7 +1622,7 @@
reg = <0x1810>;
};
- gpio8_dbclk: gpio8_dbclk {
+ gpio8_dbclk: gpio8_dbclk@1818 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1614,7 +1630,7 @@
reg = <0x1818>;
};
- mmc1_clk32k: mmc1_clk32k {
+ mmc1_clk32k: mmc1_clk32k@1328 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1622,7 +1638,7 @@
reg = <0x1328>;
};
- mmc2_clk32k: mmc2_clk32k {
+ mmc2_clk32k: mmc2_clk32k@1330 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1630,7 +1646,7 @@
reg = <0x1330>;
};
- mmc3_clk32k: mmc3_clk32k {
+ mmc3_clk32k: mmc3_clk32k@1820 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1638,7 +1654,7 @@
reg = <0x1820>;
};
- mmc4_clk32k: mmc4_clk32k {
+ mmc4_clk32k: mmc4_clk32k@1828 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1646,7 +1662,7 @@
reg = <0x1828>;
};
- sata_ref_clk: sata_ref_clk {
+ sata_ref_clk: sata_ref_clk@1388 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin1>;
@@ -1654,7 +1670,7 @@
reg = <0x1388>;
};
- usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+ usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
@@ -1662,7 +1678,7 @@
reg = <0x13f0>;
};
- usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+ usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
@@ -1670,7 +1686,7 @@
reg = <0x1340>;
};
- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1678,7 +1694,7 @@
reg = <0x0640>;
};
- usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+ usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1686,7 +1702,7 @@
reg = <0x0688>;
};
- usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+ usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1694,7 +1710,7 @@
reg = <0x0698>;
};
- atl_dpll_clk_mux: atl_dpll_clk_mux {
+ atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
@@ -1702,7 +1718,7 @@
reg = <0x0c00>;
};
- atl_gfclk_mux: atl_gfclk_mux {
+ atl_gfclk_mux: atl_gfclk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
@@ -1710,16 +1726,15 @@
reg = <0x0c00>;
};
- gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+ rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
#clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_gmac_m2_ck>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
ti,bit-shift = <24>;
reg = <0x13d0>;
- ti,dividers = <2>;
};
- gmac_rft_clk_mux: gmac_rft_clk_mux {
+ gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
@@ -1727,7 +1742,7 @@
reg = <0x13d0>;
};
- gpu_core_gclk_mux: gpu_core_gclk_mux {
+ gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1735,7 +1750,7 @@
reg = <0x1220>;
};
- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1743,7 +1758,7 @@
reg = <0x1220>;
};
- l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&wkupaon_iclk_mux>;
@@ -1752,7 +1767,7 @@
ti,dividers = <8>, <16>, <32>;
};
- mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+ mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1760,7 +1775,7 @@
reg = <0x1860>;
};
- mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+ mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1768,7 +1783,7 @@
reg = <0x1860>;
};
- mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+ mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1776,7 +1791,7 @@
reg = <0x1860>;
};
- mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+ mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1784,7 +1799,7 @@
reg = <0x1868>;
};
- mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+ mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1792,7 +1807,7 @@
reg = <0x1868>;
};
- mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+ mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1800,7 +1815,7 @@
reg = <0x1898>;
};
- mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+ mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1808,7 +1823,7 @@
reg = <0x1898>;
};
- mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+ mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1816,7 +1831,7 @@
reg = <0x1878>;
};
- mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+ mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1824,7 +1839,7 @@
reg = <0x1878>;
};
- mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+ mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1832,7 +1847,7 @@
reg = <0x1904>;
};
- mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+ mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1840,7 +1855,7 @@
reg = <0x1904>;
};
- mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+ mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1848,7 +1863,7 @@
reg = <0x1908>;
};
- mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+ mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1856,7 +1871,7 @@
reg = <0x1908>;
};
- mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+ mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1864,7 +1879,7 @@
reg = <0x1890>;
};
- mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+ mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1872,7 +1887,7 @@
reg = <0x1890>;
};
- mmc1_fclk_mux: mmc1_fclk_mux {
+ mmc1_fclk_mux: mmc1_fclk_mux@1328 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1880,7 +1895,7 @@
reg = <0x1328>;
};
- mmc1_fclk_div: mmc1_fclk_div {
+ mmc1_fclk_div: mmc1_fclk_div@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc1_fclk_mux>;
@@ -1890,7 +1905,7 @@
ti,index-power-of-two;
};
- mmc2_fclk_mux: mmc2_fclk_mux {
+ mmc2_fclk_mux: mmc2_fclk_mux@1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1898,7 +1913,7 @@
reg = <0x1330>;
};
- mmc2_fclk_div: mmc2_fclk_div {
+ mmc2_fclk_div: mmc2_fclk_div@1330 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc2_fclk_mux>;
@@ -1908,7 +1923,7 @@
ti,index-power-of-two;
};
- mmc3_gfclk_mux: mmc3_gfclk_mux {
+ mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1916,7 +1931,7 @@
reg = <0x1820>;
};
- mmc3_gfclk_div: mmc3_gfclk_div {
+ mmc3_gfclk_div: mmc3_gfclk_div@1820 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc3_gfclk_mux>;
@@ -1926,7 +1941,7 @@
ti,index-power-of-two;
};
- mmc4_gfclk_mux: mmc4_gfclk_mux {
+ mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1934,7 +1949,7 @@
reg = <0x1828>;
};
- mmc4_gfclk_div: mmc4_gfclk_div {
+ mmc4_gfclk_div: mmc4_gfclk_div@1828 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc4_gfclk_mux>;
@@ -1944,7 +1959,7 @@
ti,index-power-of-two;
};
- qspi_gfclk_mux: qspi_gfclk_mux {
+ qspi_gfclk_mux: qspi_gfclk_mux@1838 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
@@ -1952,7 +1967,7 @@
reg = <0x1838>;
};
- qspi_gfclk_div: qspi_gfclk_div {
+ qspi_gfclk_div: qspi_gfclk_div@1838 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&qspi_gfclk_mux>;
@@ -1962,7 +1977,7 @@
ti,index-power-of-two;
};
- timer10_gfclk_mux: timer10_gfclk_mux {
+ timer10_gfclk_mux: timer10_gfclk_mux@1728 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1970,7 +1985,7 @@
reg = <0x1728>;
};
- timer11_gfclk_mux: timer11_gfclk_mux {
+ timer11_gfclk_mux: timer11_gfclk_mux@1730 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1978,7 +1993,7 @@
reg = <0x1730>;
};
- timer13_gfclk_mux: timer13_gfclk_mux {
+ timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1986,7 +2001,7 @@
reg = <0x17c8>;
};
- timer14_gfclk_mux: timer14_gfclk_mux {
+ timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1994,7 +2009,7 @@
reg = <0x17d0>;
};
- timer15_gfclk_mux: timer15_gfclk_mux {
+ timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2002,7 +2017,7 @@
reg = <0x17d8>;
};
- timer16_gfclk_mux: timer16_gfclk_mux {
+ timer16_gfclk_mux: timer16_gfclk_mux@1830 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2010,7 +2025,7 @@
reg = <0x1830>;
};
- timer2_gfclk_mux: timer2_gfclk_mux {
+ timer2_gfclk_mux: timer2_gfclk_mux@1738 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2018,7 +2033,7 @@
reg = <0x1738>;
};
- timer3_gfclk_mux: timer3_gfclk_mux {
+ timer3_gfclk_mux: timer3_gfclk_mux@1740 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2026,7 +2041,7 @@
reg = <0x1740>;
};
- timer4_gfclk_mux: timer4_gfclk_mux {
+ timer4_gfclk_mux: timer4_gfclk_mux@1748 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2034,7 +2049,7 @@
reg = <0x1748>;
};
- timer9_gfclk_mux: timer9_gfclk_mux {
+ timer9_gfclk_mux: timer9_gfclk_mux@1750 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2042,7 +2057,7 @@
reg = <0x1750>;
};
- uart1_gfclk_mux: uart1_gfclk_mux {
+ uart1_gfclk_mux: uart1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2050,7 +2065,7 @@
reg = <0x1840>;
};
- uart2_gfclk_mux: uart2_gfclk_mux {
+ uart2_gfclk_mux: uart2_gfclk_mux@1848 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2058,7 +2073,7 @@
reg = <0x1848>;
};
- uart3_gfclk_mux: uart3_gfclk_mux {
+ uart3_gfclk_mux: uart3_gfclk_mux@1850 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2066,7 +2081,7 @@
reg = <0x1850>;
};
- uart4_gfclk_mux: uart4_gfclk_mux {
+ uart4_gfclk_mux: uart4_gfclk_mux@1858 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2074,7 +2089,7 @@
reg = <0x1858>;
};
- uart5_gfclk_mux: uart5_gfclk_mux {
+ uart5_gfclk_mux: uart5_gfclk_mux@1870 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2082,7 +2097,7 @@
reg = <0x1870>;
};
- uart7_gfclk_mux: uart7_gfclk_mux {
+ uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2090,7 +2105,7 @@
reg = <0x18d0>;
};
- uart8_gfclk_mux: uart8_gfclk_mux {
+ uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2098,7 +2113,7 @@
reg = <0x18e0>;
};
- uart9_gfclk_mux: uart9_gfclk_mux {
+ uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2106,7 +2121,7 @@
reg = <0x18e8>;
};
- vip1_gclk_mux: vip1_gclk_mux {
+ vip1_gclk_mux: vip1_gclk_mux@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2114,7 +2129,7 @@
reg = <0x1020>;
};
- vip2_gclk_mux: vip2_gclk_mux {
+ vip2_gclk_mux: vip2_gclk_mux@1028 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2122,7 +2137,7 @@
reg = <0x1028>;
};
- vip3_gclk_mux: vip3_gclk_mux {
+ vip3_gclk_mux: vip3_gclk_mux@1030 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2139,11 +2154,43 @@
};
&scm_conf_clocks {
- dss_deshdcp_clk: dss_deshdcp_clk {
+ dss_deshdcp_clk: dss_deshdcp_clk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_iclk_div>;
ti,bit-shift = <0>;
reg = <0x558>;
};
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <20>;
+ reg = <0x0558>;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <21>;
+ reg = <0x0558>;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <22>;
+ reg = <0x0558>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x6c4>;
+ };
};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 2e9f1f9..2101172 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -135,8 +135,8 @@
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
- 0x2 0x0 0x0 0x7e800000 0x00010000
- 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ 0x1 0x0 0x0 0x7e800000 0x00010000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
nor@0,0 {
@@ -148,21 +148,21 @@
device-width = <1>;
};
- nand@2,0 {
+ nand@1,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x10000>;
};
- fpga: board-control@3,0 {
+ fpga: board-control@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- reg = <0x3 0x0 0x0000100>;
+ reg = <0x2 0x0 0x0000100>;
bank-width = <1>;
device-width = <1>;
- ranges = <0 3 0 0x100>;
+ ranges = <0 2 0 0x100>;
};
};
diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
index 16c5c89..f271e71 100644
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -47,12 +47,12 @@
compatible = "adi,adt7461a";
reg = <0x4c>;
};
- eeprom@56 {
+ eeprom@52 {
compatible = "at24,24c512";
reg = <0x52>;
};
- eeprom@57 {
+ eeprom@53 {
compatible = "at24,24c512";
reg = <0x53>;
};
@@ -69,8 +69,8 @@
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
- 0x2 0x0 0x0 0x7e800000 0x00010000
- 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ 0x1 0x0 0x0 0x7e800000 0x00010000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
nor@0,0 {
compatible = "cfi-flash";
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index a8bffba..f038f96 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -215,5 +215,26 @@
big-endian;
status = "disabled";
};
+
+ usb0: usb3@2f00000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <0 60 0x4>;
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3000000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <0 61 0x4>;
+ dr_mode = "host";
+ };
+
+ usb2: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 63 0x4>;
+ dr_mode = "host";
+ };
};
};
diff --git a/arch/arm/dts/fsl-ls1046a-qds-duart.dts b/arch/arm/dts/fsl-ls1046a-qds-duart.dts
new file mode 100644
index 0000000..10a95ea
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1046a-qds.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
new file mode 100644
index 0000000..21243d0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1046a-qds.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &lpuart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi
new file mode 100644
index 0000000..a49ca08
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -0,0 +1,81 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@nxp.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1046a.dtsi"
+
+/ {
+ model = "LS1046A QDS Board";
+ aliases {
+ spi0 = &qspi;
+ spi1 = &dspi0;
+ };
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <1000000>; /* input clock */
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3500000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3500000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&lpuart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
new file mode 100644
index 0000000..4902454
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1046a.dtsi"
+
+/ {
+ model = "LS1046A RDB Board";
+
+ aliases {
+ spi0 = &qspi;
+ };
+
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fs512s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+
+ qflash1: s25fs512s@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
new file mode 100644
index 0000000..359a9d1
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -0,0 +1,220 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <mingkai.hu@nxp.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+ compatible = "fsl,ls1046a";
+ interrupt-parent = <&gic>;
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ gic: interrupt-controller@1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1410000 0 0x10000>, /* GICD */
+ <0x0 0x1420000 0 0x10000>, /* GICC */
+ <0x0 0x1440000 0 0x20000>, /* GICH */
+ <0x0 0x1460000 0 0x20000>; /* GICV */
+ interrupts = <1 9 0xf08>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clockgen: clocking@1ee1000 {
+ compatible = "fsl,ls1046a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 64 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <6>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi@2110000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <0 65 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <6>;
+ big-endian;
+ status = "disabled";
+ };
+
+ ifc: ifc@1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <0 43 0x4>;
+ };
+
+ i2c0: i2c@2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@21a0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <0 58 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@21b0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21b0000 0x0 0x10000>;
+ interrupts = <0 59 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart2: serial@21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart3: serial@21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ lpuart0: serial@2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <0 48 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial@2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <0 49 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <0 50 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial@2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <0 51 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial@2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <0 52 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial@29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <0 53 0x4>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ qspi: quadspi@1550000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1550000 0x0 0x10000>,
+ <0x0 0x40000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ num-cs = <4>;
+ big-endian;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index b308c8b..f76e981 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -75,4 +75,18 @@
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
};
+
+ usb0: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 80 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3110000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <0 81 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
};
diff --git a/arch/arm/dts/imx53-cx9020.dts b/arch/arm/dts/imx53-cx9020.dts
new file mode 100644
index 0000000..9610301
--- /dev/null
+++ b/arch/arm/dts/imx53-cx9020.dts
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2016 Beckhoff Automation
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "imx53.dtsi"
+
+#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
+#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
+#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
+#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
+
+/ {
+ model = "Beckhoff CX9020-0100 i.MX53";
+ compatible = "fsl,imx53-qsb", "fsl,imx53";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx53-qsb {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
+ MX53_PAD_GPIO_8__GPIO1_8 0x80000000
+ MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
+ MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
+ MX53_PAD_GPIO_1__GPIO1_1 0x80000000
+ MX53_PAD_GPIO_4__GPIO1_4 0x80000000
+ MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
+ MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
+ MX53_PAD_GPIO_16__GPIO7_11 0x80000000
+
+ MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
+ MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x80000000
+ MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x80000000
+ MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
+ MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x80000000
+ MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x80000000
+ MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x80000000
+ MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x80000000
+ MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x80000000
+ MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
+ MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x80000000
+ MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x80000000
+ MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x80000000
+ MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x80000000
+ MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x80000000
+ MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x80000000
+ MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x80000000
+ MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
+ MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
+ MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
+ MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
+ MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
+ MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
+ MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
+ MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
+ MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0xa4
+ MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0xa4
+ MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0xa4
+ MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0xa4
+ MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0xa4
+ MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0xa4
+ MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0xa4
+ MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0xa4
+ MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
+ MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
+ MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
+ MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
+ MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
+ MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
+ MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
+ MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
+ MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0xa4
+ MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0xa4
+ MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0xa4
+ MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0xa4
+ MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0xa4
+ MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0xa4
+ MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0xa4
+ MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0xa4
+ MX53_PAD_NANDF_CLE__GPIO6_7 0x00000001
+ MX53_PAD_NANDF_WP_B__GPIO6_9 0x00000001
+ MX53_PAD_NANDF_ALE__GPIO6_8 0x00000001
+
+ MX53_PAD_EIM_D23__GPIO3_23 0x80000000
+
+ MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
+ MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
+ MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
+ MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
+
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
+ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
+ MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
+
+ MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
+
+ MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
+ MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
+
+ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
+ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
+
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
+ MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
+ MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
+ MX53_PAD_EIM_D28__UART2_RTS 0x1e4
+ MX53_PAD_EIM_D29__UART2_CTS 0x1e4
+ >;
+ };
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ fsl,dte-mode;
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio7 6 0>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx53-pinfunc.h b/arch/arm/dts/imx53-pinfunc.h
new file mode 100644
index 0000000..aec406b
--- /dev/null
+++ b/arch/arm/dts/imx53-pinfunc.h
@@ -0,0 +1,1189 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX53_PINFUNC_H
+#define __DTS_IMX53_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
+#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
+#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
+#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
+#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
+#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0
+#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0
+#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0
+#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0
+#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0
+#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0
+#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0
+#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0
+#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0
+#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0
+#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0
+#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0
+#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0
+#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0
+#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3
+#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0
+#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3
+#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0
+#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0
+#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3
+#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0
+#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3
+#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0
+#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2
+#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0
+#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0
+#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1
+#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0
+#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0
+#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0
+#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1
+#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0
+#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0
+#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1
+#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0
+#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0
+#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1
+#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1
+#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0
+#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0
+#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1
+#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1
+#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1
+#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0
+#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0
+#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1
+#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0
+#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0
+#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0
+#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1
+#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1
+#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0
+#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0
+#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0
+#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0
+#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0
+#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0
+#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0
+#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0
+#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0
+#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0
+#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0
+#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0
+#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0
+#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0
+#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0
+#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0
+#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0
+#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0
+#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0
+#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0
+#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0
+#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0
+#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0
+#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0
+#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0
+#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0
+#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0
+#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0
+#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0
+#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0
+#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0
+#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0
+#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0
+#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0
+#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0
+#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1
+#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0
+#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0
+#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0
+#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0
+#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0
+#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0
+#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0
+#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0
+#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0
+#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0
+#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0
+#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0
+#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0
+#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0
+#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0
+#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0
+#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0
+#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0
+#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0
+#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0
+#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0
+#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0
+#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0
+#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0
+#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0
+#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0
+#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0
+#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0
+#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0
+#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0
+#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0
+#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0
+#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0
+#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0
+#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0
+#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0
+#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0
+#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0
+#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0
+#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0
+#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0
+#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0
+#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0
+#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0
+#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0
+#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0
+#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1
+#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0
+#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0
+#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1
+#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3
+#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1
+#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3
+#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1
+#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3
+#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1
+#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1
+#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0
+#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0
+#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0
+#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0
+#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1
+#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0
+#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0
+#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0
+#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0
+#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1
+#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0
+#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0
+#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0
+#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0
+#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1
+#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0
+#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0
+#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1
+#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2
+#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1
+#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2
+#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1
+#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0
+#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0
+#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0
+#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2
+#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1
+#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0
+#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0
+#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1
+#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0
+#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2
+#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0
+#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1
+#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0
+#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1
+#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0
+#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0
+#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5
+#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1
+#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0
+#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1
+#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2
+#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0
+#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1
+#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0
+#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0
+#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0
+#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1
+#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1
+#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0
+
+#endif /* __DTS_IMX53_PINFUNC_H */
diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
new file mode 100644
index 0000000..1bdf066
--- /dev/null
+++ b/arch/arm/dts/imx53.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2016 Beckhoff Automation
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include "imx53-pinfunc.h"
+#include <dt-bindings/clock/imx5-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ aliases {
+ serial1 = &uart2;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+
+ aips@50000000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x50000000 0x10000000>;
+ ranges;
+
+ iomuxc: iomuxc@53fa8000 {
+ compatible = "fsl,imx53-iomuxc";
+ reg = <0x53fa8000 0x4000>;
+ };
+
+ gpr: iomuxc-gpr@53fa8000 {
+ compatible = "fsl,imx53-iomuxc-gpr", "syscon";
+ reg = <0x53fa8000 0xc>;
+ };
+
+ uart2: serial@53fc0000 {
+ compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
+ reg = <0x53fc0000 0x4000>;
+ interrupts = <32>;
+ clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
+ <&clks IMX5_CLK_UART2_PER_GATE>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ clks: ccm@53fd4000{
+ compatible = "fsl,imx53-ccm";
+ reg = <0x53fd4000 0x4000>;
+ interrupts = <0 71 0x04 0 72 0x04>;
+ #clock-cells = <1>;
+ };
+
+ gpio7: gpio@53fe4000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+ reg = <0x53fe4000 0x4000>;
+ interrupts = <107 108>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ aips@60000000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x60000000 0x10000000>;
+ ranges;
+
+ sdma: sdma@63fb0000 {
+ compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
+ reg = <0x63fb0000 0x4000>;
+ interrupts = <6>;
+ clocks = <&clks IMX5_CLK_SDMA_GATE>,
+ <&clks IMX5_CLK_SDMA_GATE>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
+ };
+
+
+ fec: ethernet@63fec000 {
+ compatible = "fsl,imx53-fec", "fsl,imx25-fec";
+ reg = <0x63fec000 0x4000>;
+ interrupts = <87>;
+ clocks = <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>;
+ clock-names = "ipg", "ahb", "ptp";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx6dl-icore-rqs.dts b/arch/arm/dts/imx6dl-icore-rqs.dts
new file mode 100644
index 0000000..0f1de3f
--- /dev/null
+++ b/arch/arm/dts/imx6dl-icore-rqs.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015 Amarula Solutions B.V.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore-rqs.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 DualLite/Solo RQS Starter Kit";
+ compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
+};
diff --git a/arch/arm/dts/imx6dl-icore.dts b/arch/arm/dts/imx6dl-icore.dts
new file mode 100644
index 0000000..aec332c
--- /dev/null
+++ b/arch/arm/dts/imx6dl-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 DualLite/Solo Starter Kit";
+ compatible = "engicam,imx6-icore", "fsl,imx6dl";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6dl-pinfunc.h b/arch/arm/dts/imx6dl-pinfunc.h
new file mode 100644
index 0000000..0ead323
--- /dev/null
+++ b/arch/arm/dts/imx6dl-pinfunc.h
@@ -0,0 +1,1091 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6DL_PINFUNC_H
+#define __DTS_IMX6DL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1
+#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0
+#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0
+#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0
+#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0
+#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0
+#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0
+#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0
+#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0
+#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0
+#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0
+#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0
+#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2
+#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2
+#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2
+#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1
+#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0
+#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0
+#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2
+#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1
+#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0
+#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2
+#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1
+#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0
+#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1
+#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1
+#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0
+#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1
+#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1
+#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0
+#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0
+#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1
+#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0
+#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0
+#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0
+#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1
+#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1
+#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1
+#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1
+#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1
+#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1
+#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1
+#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1
+#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1
+#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0
+#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2
+#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0
+#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1
+#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0
+#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1
+#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1
+#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0
+#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1
+#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2
+#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1
+#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0
+#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0
+#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3
+#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1
+#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0
+#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1
+#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2
+#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2
+#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0
+#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0
+#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1
+#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0
+#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0
+#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0
+#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0
+#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0
+#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0
+#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0
+#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1
+#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0
+#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1
+#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1
+#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1
+#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1
+#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0
+#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2
+#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1
+#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0
+#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1
+#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1
+#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0
+#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0
+#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1
+#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1
+#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2
+#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1
+#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1
+#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1
+#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1
+#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1
+#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1
+#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1
+#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1
+#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1
+#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1
+#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1
+#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
+#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609
+#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
+#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1
+#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1
+#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2
+#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1
+#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1
+#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0
+#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3
+#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1
+#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1
+#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1
+#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1
+#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3
+#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0
+#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1
+#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2
+#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3
+#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1
+#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1
+#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2
+#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2
+#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0
+#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1
+#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1
+#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1
+#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3
+#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0
+#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1
+#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2
+#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3
+#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3
+#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3
+#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3
+#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1
+#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1
+#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2
+#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0
+#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3
+#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0
+#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0
+#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2
+#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2
+#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1
+#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1
+#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1
+#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1
+#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0
+#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1
+#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0
+#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0
+#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1
+#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3
+#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1
+#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2
+#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1
+#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2
+#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0
+#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2
+#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2
+#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2
+#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1
+#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2
+#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2
+#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3
+#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1
+#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5
+#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5
+#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1
+#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2
+#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0
+#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3
+#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6
+#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4
+#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5
+#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7
+#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0
+
+#endif /* __DTS_IMX6DL_PINFUNC_H */
diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
new file mode 100644
index 0000000..9a4c22c
--- /dev/null
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -0,0 +1,133 @@
+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl-pinfunc.h"
+#include "imx6qdl.dtsi"
+
+/ {
+ aliases {
+ i2c3 = &i2c4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 996000 1250000
+ 792000 1175000
+ 396000 1150000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 996000 1175000
+ 792000 1175000
+ 396000 1175000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks IMX6QDL_CLK_ARM>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+ <&clks IMX6QDL_CLK_STEP>,
+ <&clks IMX6QDL_CLK_PLL1_SW>,
+ <&clks IMX6QDL_CLK_PLL1_SYS>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+ arm-supply = <®_arm>;
+ pu-supply = <®_pu>;
+ soc-supply = <®_soc>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ soc {
+ ocram: sram@00900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+ aips1: aips-bus@02000000 {
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6dl-iomuxc";
+ };
+
+ pxp: pxp@020f0000 {
+ reg = <0x020f0000 0x4000>;
+ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epdc: epdc@020f4000 {
+ reg = <0x020f4000 0x4000>;
+ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ lcdif: lcdif@020f8000 {
+ reg = <0x020f8000 0x4000>;
+ interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ aips2: aips-bus@02100000 {
+ i2c4: i2c@021f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+ reg = <0x021f8000 0x4000>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6DL_CLK_I2C4>;
+ status = "disabled";
+ };
+ };
+ };
+
+ display-subsystem {
+ compatible = "fsl,imx-display-subsystem";
+ ports = <&ipu1_di0>, <&ipu1_di1>;
+ };
+
+ gpu-subsystem {
+ compatible = "fsl,imx-gpu-subsystem";
+ cores = <&gpu_2d>, <&gpu_3d>;
+ };
+};
+
+&gpt {
+ compatible = "fsl,imx6dl-gpt";
+};
+
+&hdmi {
+ compatible = "fsl,imx6dl-hdmi";
+};
+
+&ldb {
+ clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
+ clock-names = "di0_pll", "di1_pll",
+ "di0_sel", "di1_sel",
+ "di0", "di1";
+};
+
+&vpu {
+ compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/dts/imx6q-icore-rqs.dts b/arch/arm/dts/imx6q-icore-rqs.dts
new file mode 100644
index 0000000..9fa6ba0
--- /dev/null
+++ b/arch/arm/dts/imx6q-icore-rqs.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015 Amarula Solutions B.V.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore-rqs.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit";
+ compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
+};
diff --git a/arch/arm/dts/imx6q-icore.dts b/arch/arm/dts/imx6q-icore.dts
new file mode 100644
index 0000000..025f543
--- /dev/null
+++ b/arch/arm/dts/imx6q-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 Quad/Dual Starter Kit";
+ compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6q-pinfunc.h b/arch/arm/dts/imx6q-pinfunc.h
new file mode 100644
index 0000000..9fc6120
--- /dev/null
+++ b/arch/arm/dts/imx6q-pinfunc.h
@@ -0,0 +1,1047 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6Q_PINFUNC_H
+#define __DTS_IMX6Q_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0
+#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
+#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0
+#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0
+#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0
+#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0
+#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0
+#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0
+#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0
+#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0
+#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0
+#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0
+#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0
+#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0
+#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0
+#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0
+#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0
+#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0
+#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0
+#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0
+#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0
+#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0
+#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0
+#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1
+#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0
+#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0
+#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0
+#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0
+#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0
+#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0
+#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1
+#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0
+#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0
+#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1
+#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0
+#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0
+#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0
+#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1
+#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0
+#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2
+#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0
+#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3
+#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1
+#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1
+#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1
+#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1
+#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1
+#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1
+#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1
+#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1
+#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1
+#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0
+#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0
+#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0
+#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0
+#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
+#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1
+#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0
+#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1
+#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1
+#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1
+#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1
+#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0
+#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0
+#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100
+#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
+#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
+#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1
+#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1
+#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1
+#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1
+#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0
+#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0
+#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2
+#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1
+#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1
+#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0
+#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2
+#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2
+#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1
+#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1
+#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0
+#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2
+#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2
+#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1
+#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1
+#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0
+#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1
+#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1
+#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1
+#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1
+#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2
+#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0
+#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1
+#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0
+#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0
+#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0
+#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0
+#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1
+#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
+#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
+#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101
+#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1
+#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0
+#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1
+#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1
+#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1
+#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
+#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
+#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609
+#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
+#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1
+#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1
+#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
+#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1
+#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1
+#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1
+#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1
+#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1
+#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2
+#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1
+#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
+#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1
+#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1
+#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3
+#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1
+#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
+#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3
+#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
+#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0
+#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1
+#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1
+#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0
+#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1
+#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1
+#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
+#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1
+#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1
+#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1
+#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3
+#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3
+#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3
+#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5
+#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2
+#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3
+#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2
+#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1
+#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5
+#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0
+#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0
+#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0
+#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0
+#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0
+#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2
+#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3
+#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6
+#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4
+#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5
+#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7
+#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1
+#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1
+#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0
+#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0
+#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1
+#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
+#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
+#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1
+#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3
+#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1
+#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1
+#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2
+#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1
+#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2
+#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0
+
+#endif /* __DTS_IMX6Q_PINFUNC_H */
diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
new file mode 100644
index 0000000..c30c836
--- /dev/null
+++ b/arch/arm/dts/imx6q.dtsi
@@ -0,0 +1,300 @@
+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q-pinfunc.h"
+#include "imx6qdl.dtsi"
+
+/ {
+ aliases {
+ ipu1 = &ipu2;
+ spi4 = &ecspi5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1250000
+ 852000 1250000
+ 792000 1175000
+ 396000 975000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 1200000 1275000
+ 996000 1250000
+ 852000 1250000
+ 792000 1175000
+ 396000 1175000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks IMX6QDL_CLK_ARM>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+ <&clks IMX6QDL_CLK_STEP>,
+ <&clks IMX6QDL_CLK_PLL1_SW>,
+ <&clks IMX6QDL_CLK_PLL1_SYS>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+ arm-supply = <®_arm>;
+ pu-supply = <®_pu>;
+ soc-supply = <®_soc>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ soc {
+ ocram: sram@00900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x40000>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+ aips-bus@02000000 { /* AIPS1 */
+ spba-bus@02000000 {
+ ecspi5: ecspi@02018000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02018000 0x4000>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6Q_CLK_ECSPI5>,
+ <&clks IMX6Q_CLK_ECSPI5>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6q-iomuxc";
+ };
+ };
+
+ sata: sata@02200000 {
+ compatible = "fsl,imx6q-ahci";
+ reg = <0x02200000 0x4000>;
+ interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_SATA>,
+ <&clks IMX6QDL_CLK_SATA_REF_100M>,
+ <&clks IMX6QDL_CLK_AHB>;
+ clock-names = "sata", "sata_ref", "ahb";
+ status = "disabled";
+ };
+
+ gpu_vg: gpu@02204000 {
+ compatible = "vivante,gc";
+ reg = <0x02204000 0x4000>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
+ <&clks IMX6QDL_CLK_GPU2D_CORE>;
+ clock-names = "bus", "core";
+ power-domains = <&gpc 1>;
+ };
+
+ ipu2: ipu@02800000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ipu";
+ reg = <0x02800000 0x400000>;
+ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPU2>,
+ <&clks IMX6QDL_CLK_IPU2_DI0>,
+ <&clks IMX6QDL_CLK_IPU2_DI1>;
+ clock-names = "bus", "di0", "di1";
+ resets = <&src 4>;
+
+ ipu2_csi0: port@0 {
+ reg = <0>;
+ };
+
+ ipu2_csi1: port@1 {
+ reg = <1>;
+ };
+
+ ipu2_di0: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ ipu2_di0_disp0: disp0-endpoint {
+ };
+
+ ipu2_di0_hdmi: hdmi-endpoint {
+ remote-endpoint = <&hdmi_mux_2>;
+ };
+
+ ipu2_di0_mipi: mipi-endpoint {
+ remote-endpoint = <&mipi_mux_2>;
+ };
+
+ ipu2_di0_lvds0: lvds0-endpoint {
+ remote-endpoint = <&lvds0_mux_2>;
+ };
+
+ ipu2_di0_lvds1: lvds1-endpoint {
+ remote-endpoint = <&lvds1_mux_2>;
+ };
+ };
+
+ ipu2_di1: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ ipu2_di1_hdmi: hdmi-endpoint {
+ remote-endpoint = <&hdmi_mux_3>;
+ };
+
+ ipu2_di1_mipi: mipi-endpoint {
+ remote-endpoint = <&mipi_mux_3>;
+ };
+
+ ipu2_di1_lvds0: lvds0-endpoint {
+ remote-endpoint = <&lvds0_mux_3>;
+ };
+
+ ipu2_di1_lvds1: lvds1-endpoint {
+ remote-endpoint = <&lvds1_mux_3>;
+ };
+ };
+ };
+ };
+
+ display-subsystem {
+ compatible = "fsl,imx-display-subsystem";
+ ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
+ };
+
+ gpu-subsystem {
+ compatible = "fsl,imx-gpu-subsystem";
+ cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
+ };
+};
+
+&hdmi {
+ compatible = "fsl,imx6q-hdmi";
+
+ port@2 {
+ reg = <2>;
+
+ hdmi_mux_2: endpoint {
+ remote-endpoint = <&ipu2_di0_hdmi>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ hdmi_mux_3: endpoint {
+ remote-endpoint = <&ipu2_di1_hdmi>;
+ };
+ };
+};
+
+&ldb {
+ clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
+ clock-names = "di0_pll", "di1_pll",
+ "di0_sel", "di1_sel", "di2_sel", "di3_sel",
+ "di0", "di1";
+
+ lvds-channel@0 {
+ port@2 {
+ reg = <2>;
+
+ lvds0_mux_2: endpoint {
+ remote-endpoint = <&ipu2_di0_lvds0>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ lvds0_mux_3: endpoint {
+ remote-endpoint = <&ipu2_di1_lvds0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ port@2 {
+ reg = <2>;
+
+ lvds1_mux_2: endpoint {
+ remote-endpoint = <&ipu2_di0_lvds1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ lvds1_mux_3: endpoint {
+ remote-endpoint = <&ipu2_di1_lvds1>;
+ };
+ };
+ };
+};
+
+&mipi_dsi {
+ ports {
+ port@2 {
+ reg = <2>;
+
+ mipi_mux_2: endpoint {
+ remote-endpoint = <&ipu2_di0_mipi>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ mipi_mux_3: endpoint {
+ remote-endpoint = <&ipu2_di1_mipi>;
+ };
+ };
+ };
+};
+
+&vpu {
+ compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
new file mode 100644
index 0000000..750229b
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2015 Amarula Solutions B.V.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-handle = <ð_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+
+ mdio {
+ eth_phy: ethernet-phy {
+ rxc-skew-ps = <1140>;
+ txc-skew-ps = <1140>;
+ txen-skew-ps = <600>;
+ rxdv-skew-ps = <240>;
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <600>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <240>;
+ txd0-skew-ps = <60>;
+ txd1-skew-ps = <60>;
+ txd2-skew-ps = <60>;
+ txd3-skew-ps = <240>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
new file mode 100644
index 0000000..a485c3e
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_3p3v>;
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_3p3v>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpmi-nand {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
new file mode 100644
index 0000000..b13b0b2
--- /dev/null
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -0,0 +1,1281 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &fec;
+ can0 = &can1;
+ can1 = &can2;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ ipu0 = &ipu1;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ mmc3 = &usdhc4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
+ usbphy0 = &usbphy1;
+ usbphy1 = &usbphy2;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ ckih1 {
+ compatible = "fsl,imx-ckih1", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gpc>;
+ ranges;
+
+ dma_apbh: dma-apbh@00110000 {
+ compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x00110000 0x2000>;
+ interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
+ };
+
+ gpmi: gpmi-nand@00112000 {
+ compatible = "fsl,imx6q-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
+ <&clks IMX6QDL_CLK_GPMI_APB>,
+ <&clks IMX6QDL_CLK_GPMI_BCH>,
+ <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
+ <&clks IMX6QDL_CLK_PER1_BCH>;
+ clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ hdmi: hdmi@0120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00120000 0x9000>;
+ interrupts = <0 115 0x04>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
+ <&clks IMX6QDL_CLK_HDMI_ISFR>;
+ clock-names = "iahb", "isfr";
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_hdmi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_hdmi>;
+ };
+ };
+ };
+
+ gpu_3d: gpu@00130000 {
+ compatible = "vivante,gc";
+ reg = <0x00130000 0x4000>;
+ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
+ <&clks IMX6QDL_CLK_GPU3D_CORE>,
+ <&clks IMX6QDL_CLK_GPU3D_SHADER>;
+ clock-names = "bus", "core", "shader";
+ power-domains = <&gpc 1>;
+ };
+
+ gpu_2d: gpu@00134000 {
+ compatible = "vivante,gc";
+ reg = <0x00134000 0x4000>;
+ interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
+ <&clks IMX6QDL_CLK_GPU2D_CORE>;
+ clock-names = "bus", "core";
+ power-domains = <&gpc 1>;
+ };
+
+ timer@00a00600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x00a00600 0x20>;
+ interrupts = <1 13 0xf01>;
+ interrupt-parent = <&intc>;
+ clocks = <&clks IMX6QDL_CLK_TWD>;
+ };
+
+ intc: interrupt-controller@00a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
+ L2: l2-cache@00a02000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a02000 0x1000>;
+ interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <4 2 3>;
+ arm,data-latency = <4 2 3>;
+ arm,shared-override;
+ };
+
+ pcie: pcie@0x01000000 {
+ compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
+ reg = <0x01ffc000 0x04000>,
+ <0x01f00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
+ <&clks IMX6QDL_CLK_LVDS1_GATE>,
+ <&clks IMX6QDL_CLK_PCIE_REF_125M>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy";
+ status = "disabled";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ aips-bus@02000000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x100000>;
+ ranges;
+
+ spba-bus@02000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x40000>;
+ ranges;
+
+ spdif: spdif@02004000 {
+ compatible = "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 14 18 0>,
+ <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
+ <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
+ <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
+ <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
+ <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ status = "disabled";
+ };
+
+ ecspi1: ecspi@02008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02008000 0x4000>;
+ interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_ECSPI1>,
+ <&clks IMX6QDL_CLK_ECSPI1>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ecspi2: ecspi@0200c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0200c000 0x4000>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_ECSPI2>,
+ <&clks IMX6QDL_CLK_ECSPI2>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ecspi3: ecspi@02010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02010000 0x4000>;
+ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_ECSPI3>,
+ <&clks IMX6QDL_CLK_ECSPI3>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ecspi4: ecspi@02014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02014000 0x4000>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_ECSPI4>,
+ <&clks IMX6QDL_CLK_ECSPI4>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@02020000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ esai: esai@02024000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx35-esai";
+ reg = <0x02024000 0x4000>;
+ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
+ <&clks IMX6QDL_CLK_ESAI_MEM>,
+ <&clks IMX6QDL_CLK_ESAI_EXTAL>,
+ <&clks IMX6QDL_CLK_ESAI_IPG>,
+ <&clks IMX6QDL_CLK_SPBA>;
+ clock-names = "core", "mem", "extal", "fsys", "spba";
+ dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ssi1: ssi@02028000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6q-ssi",
+ "fsl,imx51-ssi";
+ reg = <0x02028000 0x4000>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
+ <&clks IMX6QDL_CLK_SSI1>;
+ clock-names = "ipg", "baud";
+ dmas = <&sdma 37 1 0>,
+ <&sdma 38 1 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@0202c000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6q-ssi",
+ "fsl,imx51-ssi";
+ reg = <0x0202c000 0x4000>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
+ <&clks IMX6QDL_CLK_SSI2>;
+ clock-names = "ipg", "baud";
+ dmas = <&sdma 41 1 0>,
+ <&sdma 42 1 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@02030000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6q-ssi",
+ "fsl,imx51-ssi";
+ reg = <0x02030000 0x4000>;
+ interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
+ <&clks IMX6QDL_CLK_SSI3>;
+ clock-names = "ipg", "baud";
+ dmas = <&sdma 45 1 0>,
+ <&sdma 46 1 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ status = "disabled";
+ };
+
+ asrc: asrc@02034000 {
+ compatible = "fsl,imx53-asrc";
+ reg = <0x02034000 0x4000>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
+ <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
+ <&clks IMX6QDL_CLK_SPBA>;
+ clock-names = "mem", "ipg", "asrck_0",
+ "asrck_1", "asrck_2", "asrck_3", "asrck_4",
+ "asrck_5", "asrck_6", "asrck_7", "asrck_8",
+ "asrck_9", "asrck_a", "asrck_b", "asrck_c",
+ "asrck_d", "asrck_e", "asrck_f", "spba";
+ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
+ <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
+ dma-names = "rxa", "rxb", "rxc",
+ "txa", "txb", "txc";
+ fsl,asrc-rate = <48000>;
+ fsl,asrc-width = <16>;
+ status = "okay";
+ };
+
+ spba@0203c000 {
+ reg = <0x0203c000 0x4000>;
+ };
+ };
+
+ vpu: vpu@02040000 {
+ compatible = "cnm,coda960";
+ reg = <0x02040000 0x3c000>;
+ interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bit", "jpeg";
+ clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
+ <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
+ clock-names = "per", "ahb";
+ power-domains = <&gpc 1>;
+ resets = <&src 1>;
+ iram = <&ocram>;
+ };
+
+ aipstz@0207c000 { /* AIPSTZ1 */
+ reg = <0x0207c000 0x4000>;
+ };
+
+ pwm1: pwm@02080000 {
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+ reg = <0x02080000 0x4000>;
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPG>,
+ <&clks IMX6QDL_CLK_PWM1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ pwm2: pwm@02084000 {
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+ reg = <0x02084000 0x4000>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPG>,
+ <&clks IMX6QDL_CLK_PWM2>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ pwm3: pwm@02088000 {
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+ reg = <0x02088000 0x4000>;
+ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPG>,
+ <&clks IMX6QDL_CLK_PWM3>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ pwm4: pwm@0208c000 {
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+ reg = <0x0208c000 0x4000>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPG>,
+ <&clks IMX6QDL_CLK_PWM4>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can1: flexcan@02090000 {
+ compatible = "fsl,imx6q-flexcan";
+ reg = <0x02090000 0x4000>;
+ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
+ <&clks IMX6QDL_CLK_CAN1_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can2: flexcan@02094000 {
+ compatible = "fsl,imx6q-flexcan";
+ reg = <0x02094000 0x4000>;
+ interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
+ <&clks IMX6QDL_CLK_CAN2_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ gpt: gpt@02098000 {
+ compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
+ <&clks IMX6QDL_CLK_GPT_IPG_PER>,
+ <&clks IMX6QDL_CLK_GPT_3M>;
+ clock-names = "ipg", "per", "osc_per";
+ };
+
+ gpio1: gpio@0209c000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
+ <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@020a0000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
+ <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@020a4000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
+ <0 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@020a8000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
+ <0 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@020ac000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+ interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
+ <0 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@020b0000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020b0000 0x4000>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
+ <0 77 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio7: gpio@020b4000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020b4000 0x4000>;
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
+ <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ kpp: kpp@020b8000 {
+ compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
+ reg = <0x020b8000 0x4000>;
+ interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPG>;
+ status = "disabled";
+ };
+
+ wdog1: wdog@020bc000 {
+ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_DUMMY>;
+ };
+
+ wdog2: wdog@020c0000 {
+ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+ reg = <0x020c0000 0x4000>;
+ interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_DUMMY>;
+ status = "disabled";
+ };
+
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6q-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
+ <0 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
+ reg = <0x020c8000 0x1000>;
+ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
+ <0 54 IRQ_TYPE_LEVEL_HIGH>,
+ <0 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ regulator-1p1 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd1p1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1375000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x110>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <4>;
+ anatop-min-voltage = <800000>;
+ anatop-max-voltage = <1375000>;
+ };
+
+ regulator-3p0 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3150000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
+ };
+
+ regulator-2p5 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd2p5";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2750000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x130>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2000000>;
+ anatop-max-voltage = <2750000>;
+ };
+
+ reg_arm: regulator-vddcore {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddarm";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <0>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <24>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+
+ reg_pu: regulator-vddpu {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-enable-ramp-delay = <150>;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <9>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <26>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+
+ reg_soc: regulator-vddsoc {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddsoc";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <18>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <28>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6q-tempmon";
+ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ fsl,tempmon-data = <&ocotp>;
+ clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ };
+
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy@020ca000 {
+ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USBPHY2>;
+ fsl,anatop = <&anatop>;
+ };
+
+ snvs: snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_rtc: snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&snvs>;
+ offset = <0x34>;
+ interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs_poweroff: snvs-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&snvs>;
+ offset = <0x38>;
+ mask = <0x60>;
+ status = "disabled";
+ };
+ };
+
+ epit1: epit@020d0000 { /* EPIT1 */
+ reg = <0x020d0000 0x4000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epit2: epit@020d4000 { /* EPIT2 */
+ reg = <0x020d4000 0x4000>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ src: src@020d8000 {
+ compatible = "fsl,imx6q-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
+ <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+ <0 90 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ pu-supply = <®_pu>;
+ clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+ <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+ <&clks IMX6QDL_CLK_GPU2D_CORE>,
+ <&clks IMX6QDL_CLK_GPU2D_AXI>,
+ <&clks IMX6QDL_CLK_OPENVG_AXI>,
+ <&clks IMX6QDL_CLK_VPU_AXI>;
+ #power-domain-cells = <1>;
+ };
+
+ gpr: iomuxc-gpr@020e0000 {
+ compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+ reg = <0x020e0000 0x38>;
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ };
+
+ ldb: ldb@020e0008 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+ gpr = <&gpr>;
+ status = "disabled";
+
+ lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lvds0_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_lvds0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds0_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_lvds0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lvds1_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_lvds1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds1_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_lvds1>;
+ };
+ };
+ };
+ };
+
+ dcic1: dcic@020e4000 {
+ reg = <0x020e4000 0x4000>;
+ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dcic2: dcic@020e8000 {
+ reg = <0x020e8000 0x4000>;
+ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sdma: sdma@020ec000 {
+ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_SDMA>,
+ <&clks IMX6QDL_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+ };
+
+ aips-bus@02100000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+ crypto: caam@2100000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2100000 0x10000>;
+ ranges = <0 0x2100000 0x10000>;
+ clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
+ <&clks IMX6QDL_CLK_CAAM_ACLK>,
+ <&clks IMX6QDL_CLK_CAAM_IPG>,
+ <&clks IMX6QDL_CLK_EIM_SLOW>;
+ clock-names = "mem", "aclk", "ipg", "emi_slow";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ aipstz@0217c000 { /* AIPSTZ2 */
+ reg = <0x0217c000 0x4000>;
+ };
+
+ usbotg: usb@02184000 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+ interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbh1: usb@02184200 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+ interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+ dr_mode = "host";
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbh2: usb@02184400 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184400 0x200>;
+ interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ fsl,usbmisc = <&usbmisc 2>;
+ dr_mode = "host";
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbh3: usb@02184600 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184600 0x200>;
+ interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ fsl,usbmisc = <&usbmisc 3>;
+ dr_mode = "host";
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc@02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ };
+
+ fec: ethernet@02188000 {
+ compatible = "fsl,imx6q-fec";
+ reg = <0x02188000 0x4000>;
+ interrupts-extended =
+ <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp";
+ status = "disabled";
+ };
+
+ mlb@0218c000 {
+ reg = <0x0218c000 0x4000>;
+ interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
+ <0 117 IRQ_TYPE_LEVEL_HIGH>,
+ <0 126 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ usdhc1: usdhc@02190000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x02190000 0x4000>;
+ interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USDHC1>,
+ <&clks IMX6QDL_CLK_USDHC1>,
+ <&clks IMX6QDL_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc@02194000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x02194000 0x4000>;
+ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USDHC2>,
+ <&clks IMX6QDL_CLK_USDHC2>,
+ <&clks IMX6QDL_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc3: usdhc@02198000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x02198000 0x4000>;
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USDHC3>,
+ <&clks IMX6QDL_CLK_USDHC3>,
+ <&clks IMX6QDL_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc4: usdhc@0219c000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x0219c000 0x4000>;
+ interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_USDHC4>,
+ <&clks IMX6QDL_CLK_USDHC4>,
+ <&clks IMX6QDL_CLK_USDHC4>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@021a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@021a4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@021a8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ romcp@021ac000 {
+ reg = <0x021ac000 0x4000>;
+ };
+
+ mmdc0: mmdc@021b0000 { /* MMDC0 */
+ compatible = "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+
+ mmdc1: mmdc@021b4000 { /* MMDC1 */
+ reg = <0x021b4000 0x4000>;
+ };
+
+ weim: weim@021b8000 {
+ compatible = "fsl,imx6q-weim";
+ reg = <0x021b8000 0x4000>;
+ interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+ };
+
+ ocotp: ocotp@021bc000 {
+ compatible = "fsl,imx6q-ocotp", "syscon";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6QDL_CLK_IIM>;
+ };
+
+ tzasc@021d0000 { /* TZASC1 */
+ reg = <0x021d0000 0x4000>;
+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ tzasc@021d4000 { /* TZASC2 */
+ reg = <0x021d4000 0x4000>;
+ interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ audmux: audmux@021d8000 {
+ compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
+ reg = <0x021d8000 0x4000>;
+ status = "disabled";
+ };
+
+ mipi_csi: mipi@021dc000 {
+ reg = <0x021dc000 0x4000>;
+ };
+
+ mipi_dsi: mipi@021e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x021e0000 0x4000>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_mipi>;
+ };
+ };
+ };
+ };
+
+ vdoa@021e4000 {
+ reg = <0x021e4000 0x4000>;
+ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart2: serial@021e8000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021e8000 0x4000>;
+ interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@021ec000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021ec000 0x4000>;
+ interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@021f0000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021f0000 0x4000>;
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@021f4000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021f4000 0x4000>;
+ interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
+ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ };
+
+ ipu1: ipu@02400000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ipu";
+ reg = <0x02400000 0x400000>;
+ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_IPU1>,
+ <&clks IMX6QDL_CLK_IPU1_DI0>,
+ <&clks IMX6QDL_CLK_IPU1_DI1>;
+ clock-names = "bus", "di0", "di1";
+ resets = <&src 2>;
+
+ ipu1_csi0: port@0 {
+ reg = <0>;
+ };
+
+ ipu1_csi1: port@1 {
+ reg = <1>;
+ };
+
+ ipu1_di0: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ ipu1_di0_disp0: disp0-endpoint {
+ };
+
+ ipu1_di0_hdmi: hdmi-endpoint {
+ remote-endpoint = <&hdmi_mux_0>;
+ };
+
+ ipu1_di0_mipi: mipi-endpoint {
+ remote-endpoint = <&mipi_mux_0>;
+ };
+
+ ipu1_di0_lvds0: lvds0-endpoint {
+ remote-endpoint = <&lvds0_mux_0>;
+ };
+
+ ipu1_di0_lvds1: lvds1-endpoint {
+ remote-endpoint = <&lvds1_mux_0>;
+ };
+ };
+
+ ipu1_di1: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ ipu1_di1_disp1: disp1-endpoint {
+ };
+
+ ipu1_di1_hdmi: hdmi-endpoint {
+ remote-endpoint = <&hdmi_mux_1>;
+ };
+
+ ipu1_di1_mipi: mipi-endpoint {
+ remote-endpoint = <&mipi_mux_1>;
+ };
+
+ ipu1_di1_lvds0: lvds0-endpoint {
+ remote-endpoint = <&lvds0_mux_1>;
+ };
+
+ ipu1_di1_lvds1: lvds1-endpoint {
+ remote-endpoint = <&lvds1_mux_1>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts
new file mode 100644
index 0000000..b4af007
--- /dev/null
+++ b/arch/arm/dts/imx6sll-evk.dts
@@ -0,0 +1,801 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sll.dtsi"
+
+/ {
+ model = "Freescale i.MX6SLL EVK Board";
+ compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
+ memory {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ battery: max8903@0 {
+ compatible = "fsl,max8903-charger";
+ pinctrl-names = "default";
+ dok_input = <&gpio4 13 1>;
+ uok_input = <&gpio4 13 1>;
+ chg_input = <&gpio4 15 1>;
+ flt_input = <&gpio4 14 1>;
+ fsl,dcm_always_high;
+ fsl,dc_valid;
+ fsl,adc_disable;
+ status = "okay";
+ };
+
+ pxp_v4l2_out {
+ compatible = "fsl,imx6sl-pxp-v4l2";
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg2_vbus: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_aud3v: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "wm8962-supply-3v15";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+ regulator-boot-on;
+ };
+
+ reg_aud4v: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "wm8962-supply-4v2";
+ regulator-min-microvolt = <4325000>;
+ regulator-max-microvolt = <4325000>;
+ regulator-boot-on;
+ };
+
+ reg_lcd: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "lcd-pwr";
+ gpio = <&gpio4 8 0>;
+ enable-active-high;
+ };
+
+ reg_sd1_vmmc: sd1_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_sd2_vmmc: sd2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "eMMC-VCCQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ reg_sd3_vmmc: sd3_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD3_WIFI";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ };
+
+ sound {
+ compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+ cpu-dai = <&ssi2>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "AMIC", "MICBIAS",
+ "IN3R", "AMIC";
+ mux-int-port = <2>;
+ mux-ext-port = <3>;
+ codec-master;
+ hp-det-gpios = <&gpio4 24 1>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux3>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <393216000>;
+};
+
+&cpu0 {
+ arm-supply = <&sw1a_reg>;
+ soc-supply = <&sw1c_reg>;
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pfuze100@08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ max17135: max17135@48 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max17135>;
+ compatible = "maxim,max17135";
+ reg = <0x48>;
+ status = "okay";
+
+ vneg_pwrup = <1>;
+ gvee_pwrup = <2>;
+ vpos_pwrup = <10>;
+ gvdd_pwrup = <12>;
+ gvdd_pwrdn = <1>;
+ vpos_pwrdn = <2>;
+ gvee_pwrdn = <8>;
+ vneg_pwrdn = <10>;
+ gpio_pmic_pwrgood = <&gpio2 13 0>;
+ gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
+ gpio_pmic_wakeup = <&gpio2 14 0>;
+ gpio_pmic_v3p3 = <&gpio2 7 0>;
+ gpio_pmic_intr = <&gpio2 12 0>;
+
+ regulators {
+ DISPLAY_reg: DISPLAY {
+ regulator-name = "DISPLAY";
+ };
+
+ GVDD_reg: GVDD {
+ /* 20v */
+ regulator-name = "GVDD";
+ };
+
+ GVEE_reg: GVEE {
+ /* -22v */
+ regulator-name = "GVEE";
+ };
+
+ HVINN_reg: HVINN {
+ /* -22v */
+ regulator-name = "HVINN";
+ };
+
+ HVINP_reg: HVINP {
+ /* 20v */
+ regulator-name = "HVINP";
+ };
+
+ VCOM_reg: VCOM {
+ regulator-name = "VCOM";
+ /* 2's-compliment, -4325000 */
+ regulator-min-microvolt = <0xffbe0178>;
+ /* 2's-compliment, -500000 */
+ regulator-max-microvolt = <0xfff85ee0>;
+ };
+
+ VNEG_reg: VNEG {
+ /* -15v */
+ regulator-name = "VNEG";
+ };
+
+ VPOS_reg: VPOS {
+ /* 15v */
+ regulator-name = "VPOS";
+ };
+
+ V3P3_reg: V3P3 {
+ regulator-name = "V3P3";
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ codec: wm8962@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
+ DCVDD-supply = <&vgen3_reg>;
+ DBVDD-supply = <®_aud3v>;
+ AVDD-supply = <&vgen3_reg>;
+ CPVDD-supply = <&vgen3_reg>;
+ MICVDD-supply = <®_aud3v>;
+ PLLVDD-supply = <&vgen3_reg>;
+ SPKVDD1-supply = <®_aud4v>;
+ SPKVDD2-supply = <®_aud4v>;
+ amic-mono;
+ };
+};
+
+&gpc {
+ fsl,ldo-bypass = <1>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6sll-evk {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
+ MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
+ MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
+ /*
+ * Must set the LVE of pad SD2_RESET, otherwise current
+ * leakage through eMMC chip will pull high the VCCQ to
+ * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch.
+ */
+ MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
+ MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
+ MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
+ MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
+ MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
+ MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
+ /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */
+ MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
+ MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
+ MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
+ >;
+ };
+
+ pinctrl_audmux3: audmux3grp {
+ fsl,pins = <
+ MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
+ MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
+ MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
+ MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
+ MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
+ >;
+ };
+
+ pinctrl_csi1: csi1grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088
+ MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088
+ MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088
+ MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088
+ MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088
+ MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088
+ MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088
+ MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088
+ MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088
+ MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088
+ MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088
+ MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088
+ MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
+ MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
+ >;
+ };
+
+ pinctrl_epdc0: epdcgrp0 {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1
+ MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1
+ MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1
+ MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1
+ MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1
+ MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1
+ MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1
+ MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1
+ MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1
+ MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1
+ MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1
+ MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1
+ MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1
+ MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1
+ MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1
+ MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1
+ MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1
+ MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1
+ MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1
+ MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1
+ MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1
+ MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1
+ MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1
+ MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1
+ MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1
+ >;
+ };
+
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79
+ MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79
+ MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79
+ MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79
+ MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79
+ MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79
+ MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79
+ MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79
+ MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79
+ MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79
+ MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79
+ MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79
+ MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79
+ MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79
+ MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79
+ MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79
+ MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79
+ MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79
+ MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79
+ MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79
+ MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79
+ MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79
+ MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79
+ MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79
+ MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79
+ MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79
+ MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79
+ MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79
+ MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79
+ >;
+ };
+
+ pinctrl_max17135: max17135grp-1 {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */
+ MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */
+ MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */
+ MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */
+ MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+ MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */
+ MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1
+ MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1
+ MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1
+ MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5dte: uart5dtegrp {
+ fsl,pins = <
+ MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1
+ MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1
+ MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1
+ MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
+ MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059
+ MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059
+ MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059
+ MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059
+ MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
+ MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9
+ MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9
+ MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9
+ MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9
+ MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
+ MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9
+ MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9
+ MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9
+ MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9
+ MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13059
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1
+ MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1
+ >;
+ };
+
+ pinctrl_pwm1: pmw1grp {
+ fsl,pins = <
+ MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0
+ >;
+ };
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+ &pinctrl_lcdif_ctrl>;
+ lcd-supply = <®_lcd>;
+ display = <&display>;
+ status = "okay";
+
+ display: display {
+ bits-per-pixel = <16>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <33500000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <89>;
+ hfront-porch = <164>;
+ vback-porch = <23>;
+ vfront-porch = <10>;
+ hsync-len = <10>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&pxp {
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ fsl,uart-has-rtscts;
+ /* for DTE mode, add below change */
+ /* fsl,dte-mode; */
+ /* pinctrl-0 = <&pinctrl_uart5dte>; */
+ status = "disabled";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ vmmc-supply = <®_sd1_vmmc>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vqmmc-supply = <®_sd2_vmmc>;
+ bus-width = <8>;
+ no-removable;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ vmmc-supply = <®_sd3_vmmc>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ disable-over-current;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usb_otg2_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&epdc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epdc0>;
+ V3P3-supply = <&V3P3_reg>;
+ VCOM-supply = <&VCOM_reg>;
+ DISPLAY-supply = <&DISPLAY_reg>;
+ status = "okay";
+};
+
+&ssi2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6sll-pinfunc.h b/arch/arm/dts/imx6sll-pinfunc.h
new file mode 100644
index 0000000..5a3700b
--- /dev/null
+++ b/arch/arm/dts/imx6sll-pinfunc.h
@@ -0,0 +1,882 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6SLL_PINFUNC_H
+#define __DTS_IMX6SLL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
+#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
+#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0
+#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0
+#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0
+#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0
+#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0
+#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0
+#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0
+#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0
+#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0
+#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1
+#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1
+#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0
+#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1
+#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0
+#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0
+#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0
+#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0
+#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1
+#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0
+#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1
+#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0
+#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1
+#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0
+#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0
+#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1
+#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0
+#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1
+#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1
+#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2
+#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1
+#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1
+#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1
+#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1
+#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2
+#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1
+#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1
+#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0
+#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3
+#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2
+#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2
+#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1
+#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3
+#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2
+#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2
+#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1
+#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3
+#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3
+#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3
+#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1
+#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1
+#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4
+#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5
+#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4
+#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5
+#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1
+#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2
+#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1
+#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1
+#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0
+#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2
+#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2
+#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1
+#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4
+#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1
+#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5
+#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2
+#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3
+#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4
+#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1
+#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3
+#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1
+#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2
+#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2
+#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0
+#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1
+#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0
+#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1
+#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1
+#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2
+#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3
+#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2
+#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0
+#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1
+#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0
+#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1
+#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0
+#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0
+#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1
+#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1
+#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1
+#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0
+#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0
+#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0
+#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0
+#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1
+#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0
+#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0
+#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0
+#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1
+#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0
+#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0
+#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1
+#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0
+#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0
+#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0
+#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4
+#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0
+#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6
+#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0
+#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0
+#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0
+#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1
+#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0
+#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0
+#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5
+#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0
+#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7
+#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0
+#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0
+#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0
+#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0
+#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0
+#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0
+#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0
+#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0
+#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0
+#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0
+#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0
+#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1
+#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0
+#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0
+#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0
+#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0
+#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3
+#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2
+#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2
+#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3
+#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0
+#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1
+#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3
+#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2
+#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0
+#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3
+#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2
+#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1
+#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3
+#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2
+#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3
+#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1
+#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2
+#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2
+#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1
+#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2
+#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1
+#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0
+#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3
+#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1
+#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1
+#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2
+#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0
+#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2
+#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2
+#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2
+#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6
+#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7
+#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4
+#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3
+#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5
+#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1
+#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1
+#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1
+#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1
+#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1
+#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1
+#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1
+#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4
+#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1
+#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5
+#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4
+#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5
+#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2
+#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3
+#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1
+#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2
+#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1
+#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3
+#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1
+#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0
+#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0
+#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0
+#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0
+#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0
+#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0
+#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1
+#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1
+#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0
+#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0
+#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0
+#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0
+#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0
+#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2
+#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1
+#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1
+#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1
+#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0
+
+#endif /* __DTS_IMX6SLL_PINFUNC_H */
diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi
new file mode 100644
index 0000000..349c47a
--- /dev/null
+++ b/arch/arm/dts/imx6sll.dtsi
@@ -0,0 +1,859 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx6sll-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx6sll-pinfunc.h"
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi3 = &ecspi3;
+ spi4 = &ecspi4;
+ usbphy0 = &usbphy1;
+ usbphy1 = &usbphy2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 996000 1225000
+ 792000 1175000
+ 396000 1075000
+ 198000 975000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 996000 1225000
+ 792000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ fsl,low-power-run;
+ clocks = <&clks IMX6SLL_CLK_ARM>,
+ <&clks IMX6SLL_CLK_PLL2_PFD2>,
+ <&clks IMX6SLL_CLK_STEP>,
+ <&clks IMX6SLL_CLK_PLL1_SW>,
+ <&clks IMX6SLL_CLK_PLL1_SYS>,
+ <&clks IMX6SLL_CLK_PLL1>,
+ <&clks IMX6SLL_PLL1_BYPASS>,
+ <&clks IMX6SLL_PLL1_BYPASS_SRC>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
+ "pll1_bypass_src";
+ };
+ };
+
+ intc: interrupt-controller@00a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckil: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
+ };
+
+ osc: clock@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc";
+ };
+
+ ipp_di0: clock@2 {
+ compatible = "fixed-clock";
+ reg = <2>;
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di0";
+ };
+
+ ipp_di1: clock@3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di1";
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gpc>;
+ ranges;
+
+ busfreq {
+ compatible = "fsl,imx_busfreq";
+ clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>,
+ <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,
+ <&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>,
+ <&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>,
+ <&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>,
+ <&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>,
+ <&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>,
+ <&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>,
+ <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>,
+ <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>,
+ <&clks IMX6SLL_CLK_PLL1>;
+ clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
+ "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
+ "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
+ "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
+ fsl,max_ddr_freq = <400000000>;
+ };
+
+ ocrams: sram@00900000 {
+ compatible = "fsl,lpm-sram";
+ reg = <0x00900000 0x4000>;
+ };
+
+ ocrams_ddr: sram@00904000 {
+ compatible = "fsl,ddr-lpm-sram";
+ reg = <0x00904000 0x1000>;
+ };
+
+ ocram: sram@00905000 {
+ compatible = "mmio-sram";
+ reg = <0x00905000 0x1B000>;
+ };
+
+ L2: l2-cache@00a02000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a02000 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <4 2 3>;
+ arm,data-latency = <4 2 3>;
+ };
+
+ aips1: aips-bus@02000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x100000>;
+ ranges;
+
+ spba: spba-bus@02000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x40000>;
+ ranges;
+
+ spdif: spdif@02004000 {
+ compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
+ <&clks IMX6SLL_CLK_OSC>,
+ <&clks IMX6SLL_CLK_SPDIF>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_IPG>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_SPBA>;
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "dma";
+ status = "disabled";
+ };
+
+ ecspi1: ecspi@02008000 {
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02008000 0x4000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_ECSPI1>,
+ <&clks IMX6SLL_CLK_ECSPI1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi2: ecspi@0200c000 {
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0200c000 0x4000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_ECSPI2>,
+ <&clks IMX6SLL_CLK_ECSPI2>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi3: ecspi@02010000 {
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02010000 0x4000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_ECSPI3>,
+ <&clks IMX6SLL_CLK_ECSPI3>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi4: ecspi@02014000 {
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02014000 0x4000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_ECSPI4>,
+ <&clks IMX6SLL_CLK_ECSPI4>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart4: serial@02018000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02018000 0x4000>;
+ interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
+ <&clks IMX6SLL_CLK_UART4_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart1: serial@02020000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
+ <&clks IMX6SLL_CLK_UART1_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial@02024000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02024000 0x4000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
+ <&clks IMX6SLL_CLK_UART2_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ssi1: ssi@02028000 {
+ compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+ reg = <0x02028000 0x4000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
+ <&clks IMX6SLL_CLK_SSI1>;
+ clock-names = "ipg", "baud";
+ status = "disabled";
+ };
+
+ ssi2: ssi2@0202c000 {
+ compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+ reg = <0x0202c000 0x4000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
+ <&clks IMX6SLL_CLK_SSI2>;
+ clock-names = "ipg", "baud";
+ status = "disabled";
+ };
+
+ ssi3: ssi@02030000 {
+ compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+ reg = <0x02030000 0x4000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
+ <&clks IMX6SLL_CLK_SSI3>;
+ clock-names = "ipg", "baud";
+ status = "disabled";
+ };
+
+ uart3: serial@02034000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02034000 0x4000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+ dma-name = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
+ <&clks IMX6SLL_CLK_UART3_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+
+ pwm1: pwm@02080000 {
+ compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
+ reg = <0x02080000 0x4000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PWM1>,
+ <&clks IMX6SLL_CLK_PWM1>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm2: pwm@02084000 {
+ compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
+ reg = <0x02084000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PWM2>,
+ <&clks IMX6SLL_CLK_PWM2>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm3: pwm@02088000 {
+ compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
+ reg = <0x02088000 0x4000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PWM3>,
+ <&clks IMX6SLL_CLK_PWM3>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm4: pwm@0208c000 {
+ compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
+ reg = <0x0208c000 0x4000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PWM4>,
+ <&clks IMX6SLL_CLK_PWM4>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ gpt1: gpt@02098000 {
+ compatible = "fsl,imx6sll-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
+ <&clks IMX6SLL_CLK_GPT_SERIAL>;
+ clock-names = "ipg", "per";
+ };
+
+ gpio1: gpio@0209c000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@020a0000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@020a4000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@020a8000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@020ac000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@020b0000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020b0000 0x4000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ kpp: kpp@020b8000 {
+ compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
+ reg = <0x020b8000 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_KPP>;
+ status = "disabled";
+ };
+
+ wdog1: wdog@020bc000 {
+ compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_WDOG1>;
+ };
+
+ wdog2: wdog@020c0000 {
+ compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
+ reg = <0x020c0000 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_WDOG2>;
+ status = "disabled";
+ };
+
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6sll-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+ };
+
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6sll-anatop",
+ "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x020c8000 0x4000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg_3p0: regulator-3p0@120 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+ regulator-min-microvolt = <2625000>;
+ regulator-max-microvolt = <3400000>;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
+ };
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ fsl,tempmon-data = <&ocotp>;
+ clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
+ status = "disabled";
+ };
+
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
+ "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USBPHY1>;
+ phy-3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy@020ca000 {
+ compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
+ "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USBPHY2>;
+ phy-reg_3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ snvs: snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_rtc: snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&snvs>;
+ offset = <0x34>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs_poweroff: snvs-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&snvs>;
+ offset = <0x38>;
+ mask = <0x61>;
+ };
+
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup;
+ };
+ };
+
+ epit1: epit@020d0000 {
+ reg = <0x020d0000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epit2: epit@020d4000 {
+ reg = <0x020d4000 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ src: src@020d8000 {
+ compatible = "fsl,imx6sll-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6sll-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ };
+
+ gpr: iomuxc-gpr@020e4000 {
+ compatible = "fsl,imx6sll-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ };
+
+ csi: csi@020e8000 {
+ compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
+ reg = <0x020e8000 0x4000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_CSI>,
+ <&clks IMX6SLL_CLK_DUMMY>;
+ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+ status = "disabled";
+ };
+
+ sdma: sdma@020ec000 {
+ compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_SDMA>,
+ <&clks IMX6SLL_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ iram = <&ocram>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+
+ pxp: pxp@020f0000 {
+ compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
+ reg = <0x020f0000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_PXP>;
+ clock-names = "pxp_ipg", "pxp_axi";
+ status = "disabled";
+ };
+
+ epdc: epdc@020f4000 {
+ compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc";
+ reg = <0x020f4000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>;
+ clock-names = "epdc_axi", "epdc_pix";
+ status = "disabled";
+ };
+
+ lcdif: lcdif@020f8000 {
+ compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
+ reg = <0x020f8000 0x4000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
+ <&clks IMX6SLL_CLK_LCDIF_APB>,
+ <&clks IMX6SLL_CLK_DUMMY>;
+ clock-names = "pix", "axi", "disp_axi";
+ status = "disabled";
+ };
+
+ dcp: dcp@020fc000 {
+ compatible = "fsl,imx6sl-dcp";
+ reg = <0x020fc000 0x4000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_DCP>;
+ clock-names = "dcp";
+ };
+ };
+
+ aips2: aips-bus@02100000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+ usbotg1: usb@02184000 {
+ compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
+ "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ fsl,anatop = <&anatop>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbotg2: usb@02184200 {
+ compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
+ "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc@02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
+ "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ };
+
+ usdhc1: usdhc@02190000 {
+ compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02190000 0x4000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USDHC1>,
+ <&clks IMX6SLL_CLK_USDHC1>,
+ <&clks IMX6SLL_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-step = <2>;
+ fsl,tuning-start-tap = <20>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc@02194000 {
+ compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02194000 0x4000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USDHC2>,
+ <&clks IMX6SLL_CLK_USDHC2>,
+ <&clks IMX6SLL_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-step = <2>;
+ fsl,tuning-start-tap = <20>;
+ status = "disabled";
+ };
+
+ usdhc3: usdhc@02198000 {
+ compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02198000 0x4000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USDHC3>,
+ <&clks IMX6SLL_CLK_USDHC3>,
+ <&clks IMX6SLL_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-step = <2>;
+ fsl,tuning-start-tap = <20>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@021a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@021a4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@021a8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ romcp@021ac000 {
+ compatible = "fsl,imx6sll-romcp", "syscon";
+ reg = <0x021ac000 0x4000>;
+ };
+
+ mmdc: mmdc@021b0000 {
+ compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+
+ rngb: rngb@021b4000 {
+ compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
+ reg = <0x021b4000 0x4000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_DUMMY>;
+ };
+
+ ocotp: ocotp-ctrl@021bc000 {
+ compatible = "fsl,imx6sll-ocotp", "syscon";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6SLL_CLK_OCOTP>;
+ };
+
+ csu: csu@021c0000 {
+ compatible = "fsl,imx6sll-csu";
+ reg = <0x021c0000 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ snvs_gpr: snvs-gpr@0x021c4000 {
+ compatible = "fsl, imx6sll-snvs-gpr";
+ reg = <0x021c4000 0x10000>;
+ };
+
+ iomuxc_snvs: iomuxc-snvs@021c8000 {
+ compatible = "fsl,imx6sll-iomuxc-snvs";
+ reg = <0x021c80000 0x10000>;
+ };
+
+ audmux: audmux@021d8000 {
+ compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
+ reg = <0x021d8000 0x4000>;
+ status = "disabled";
+ };
+
+ uart5: serial@021f4000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021f4000 0x4000>;
+ interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
+ <&clks IMX6SLL_CLK_UART5_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam-kit.dts
new file mode 100644
index 0000000..07c21cb
--- /dev/null
+++ b/arch/arm/dts/imx6ul-geam-kit.dts
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6ul.dtsi"
+
+/ {
+ model = "Engicam GEAM6UL";
+ compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
+
+ memory {
+ reg = <0x80000000 0x08000000>;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <4>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6ul-pinfunc.h b/arch/arm/dts/imx6ul-pinfunc.h
new file mode 100644
index 0000000..0034eeb
--- /dev/null
+++ b/arch/arm/dts/imx6ul-pinfunc.h
@@ -0,0 +1,938 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6UL_PINFUNC_H
+#define __DTS_IMX6UL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
+#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
+
+#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0
+
+#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0
+#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0
+#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0
+#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0
+#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0
+#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0
+#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0
+#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0
+#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0
+#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0
+#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0
+#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0
+#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0
+#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0
+#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0
+#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0
+#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0
+#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0
+#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0
+#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0
+#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0
+#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0
+#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0
+#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0
+#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0
+#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0
+#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0
+#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0
+#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0
+#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0
+#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0
+#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0
+#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0
+#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0
+#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0
+#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0
+#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0
+#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0
+#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0
+#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0
+#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0
+#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1
+#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0
+#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0
+#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0
+#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1
+#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0
+#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0
+#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0
+#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0
+#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0
+#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0
+#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1
+#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0
+#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0
+#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1
+#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1
+#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2
+#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1
+#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0
+#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0
+#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3
+#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0
+#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0
+#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0
+#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0
+#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0
+#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0
+#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0
+#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1
+#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1
+#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0
+#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1
+#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1
+#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1
+#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0
+#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0
+#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1
+#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2
+#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0
+#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2
+#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0
+#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0
+#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1
+#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0
+#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0
+#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0
+#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3
+#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0
+#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0
+#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0
+#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1
+#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0
+#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0
+#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1
+#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0
+#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2
+#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0
+#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1
+#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0
+#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0
+#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0
+#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1
+#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3
+#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0
+#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0
+#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1
+#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1
+#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0
+#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0
+#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2
+#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0
+#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0
+#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0
+#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0
+#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0
+#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1
+#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0
+#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0
+#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1
+#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0
+#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0
+#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0
+#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0
+#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0
+#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0
+#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0
+#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0
+#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0
+#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0
+#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0
+#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0
+#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0
+#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0
+#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0
+#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0
+#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0
+#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1
+#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0
+#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0
+#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0
+#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0
+#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0
+#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0
+#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0
+#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0
+#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0
+#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0
+#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0
+#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0
+#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2
+#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0
+#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0
+#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1
+#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1
+#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0
+#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0
+#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0
+#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0
+#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0
+#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0
+#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0
+#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0
+#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0
+#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0
+#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0
+#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0
+#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0
+#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0
+#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1
+#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0
+#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0
+#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0
+#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0
+#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0
+#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0
+#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0
+#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0
+#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0
+#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0
+#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1
+#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0
+#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0
+#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0
+#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1
+#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1
+#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0
+#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0
+#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2
+#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0
+#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0
+#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0
+#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0
+#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0
+#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4
+#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0
+#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2
+#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0
+#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0
+#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0
+#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2
+#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0
+#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0
+#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0
+#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1
+#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0
+#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0
+#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1
+#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1
+#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0
+#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0
+#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4
+#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1
+#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2
+#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1
+#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0
+#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0
+#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2
+#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1
+#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0
+#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1
+#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1
+#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2
+#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0
+#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1
+#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0
+#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1
+#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0
+#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0
+#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1
+#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1
+#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0
+#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0
+#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0
+#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0
+#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0
+#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1
+#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0
+#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0
+#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0
+#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2
+#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1
+#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0
+#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0
+#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0
+#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0
+#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0
+#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0
+#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2
+#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0
+#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0
+#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0
+#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0
+#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3
+#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0
+#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0
+#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0
+#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0
+#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0
+#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0
+#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2
+#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0
+#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0
+#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0
+#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1
+#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3
+#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0
+#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0
+#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0
+#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0
+#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0
+#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0
+#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0
+#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0
+#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0
+#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0
+#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0
+#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2
+#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2
+#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0
+#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2
+#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0
+#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2
+#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2
+#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3
+#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2
+#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3
+#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0
+#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2
+#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2
+#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2
+#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1
+#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1
+#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0
+#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0
+#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2
+#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0
+#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3
+#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0
+#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1
+#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1
+#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1
+#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2
+#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0
+#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3
+#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1
+#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0
+#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0
+#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0
+#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1
+#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0
+#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2
+#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0
+#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0
+#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0
+#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0
+#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0
+#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0
+#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2
+#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0
+#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0
+#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0
+#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0
+#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2
+#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2
+#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1
+#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2
+#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1
+#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1
+#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2
+#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1
+#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1
+#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3
+#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1
+#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1
+#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4
+#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1
+#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5
+#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0
+#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0
+#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0
+#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0
+#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0
+#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0
+#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0
+#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0
+#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0
+#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0
+#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0
+#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0
+#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0
+#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0
+#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0
+#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0
+#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0
+#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0
+#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0
+#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0
+#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0
+#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0
+#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2
+#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0
+#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0
+#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0
+#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1
+#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0
+#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0
+#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3
+#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0
+#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0
+#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0
+#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0
+#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1
+#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0
+#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0
+#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0
+#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2
+#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0
+#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0
+#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0
+#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1
+#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0
+#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0
+#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3
+#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0
+#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0
+#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1
+#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0
+#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0
+#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0
+#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0
+#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0
+#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1
+#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0
+#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0
+#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0
+#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0
+#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0
+#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0
+#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0
+#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0
+#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0
+#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0
+#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0
+#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3
+#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0
+#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0
+#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2
+#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0
+#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1
+#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0
+#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2
+#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1
+#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1
+#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3
+#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0
+#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1
+#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1
+#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0
+#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0
+#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2
+#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1
+#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0
+#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3
+#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0
+#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2
+#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0
+#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0
+#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0
+#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0
+#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0
+#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0
+#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0
+#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0
+#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0
+#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1
+#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2
+#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0
+#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2
+#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0
+#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0
+#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0
+#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3
+#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0
+#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0
+#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0
+#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0
+#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0
+#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0
+#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0
+#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0
+#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0
+#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0
+#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0
+#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0
+#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0
+#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0
+#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0
+#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0
+#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0
+#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0
+#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1
+#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0
+#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0
+#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0
+#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0
+#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0
+#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0
+#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1
+#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1
+#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2
+#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1
+#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5
+#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0
+#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0
+#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0
+#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0
+#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1
+#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2
+#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1
+#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1
+#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2
+#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1
+#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2
+#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1
+#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2
+#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1
+#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2
+#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1
+#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1
+#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2
+#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1
+#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0
+
+#endif /* __DTS_IMX6UL_PINFUNC_H */
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
new file mode 100644
index 0000000..c5c05fd
--- /dev/null
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -0,0 +1,942 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx6ul-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx6ul-pinfunc.h"
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ serial6 = &uart7;
+ serial7 = &uart8;
+ sai1 = &sai1;
+ sai2 = &sai2;
+ sai3 = &sai3;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
+ usbphy0 = &usbphy1;
+ usbphy1 = &usbphy2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ operating-points = <
+ /* kHz uV */
+ 528000 1175000
+ 396000 1025000
+ 198000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* KHz uV */
+ 528000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+ clocks = <&clks IMX6UL_CLK_ARM>,
+ <&clks IMX6UL_CLK_PLL2_BUS>,
+ <&clks IMX6UL_CLK_PLL2_PFD2>,
+ <&clks IMX6UL_CA7_SECONDARY_SEL>,
+ <&clks IMX6UL_CLK_STEP>,
+ <&clks IMX6UL_CLK_PLL1_SW>,
+ <&clks IMX6UL_CLK_PLL1_SYS>,
+ <&clks IMX6UL_PLL1_BYPASS>,
+ <&clks IMX6UL_CLK_PLL1>,
+ <&clks IMX6UL_PLL1_BYPASS_SRC>,
+ <&clks IMX6UL_CLK_OSC>;
+ clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
+ "secondary_sel", "step", "pll1_sw",
+ "pll1_sys", "pll1_bypass", "pll1",
+ "pll1_bypass_src", "osc";
+ arm-supply = <®_arm>;
+ soc-supply = <®_soc>;
+ };
+ };
+
+ intc: interrupt-controller@00a01000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a02000 0x1000>,
+ <0x00a04000 0x2000>,
+ <0x00a06000 0x2000>;
+ };
+
+ ckil: clock-cli {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
+ };
+
+ osc: clock-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc";
+ };
+
+ ipp_di0: clock-di0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di0";
+ };
+
+ ipp_di1: clock-di1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di1";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gpc>;
+ ranges;
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ocram: sram@00900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
+ };
+
+ dma_apbh: dma-apbh@01804000 {
+ compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x01804000 0x2000>;
+ interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clks IMX6UL_CLK_APBHDMA>;
+ };
+
+ gpmi: gpmi-nand@01806000 {
+ compatible = "fsl,imx6q-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clks IMX6UL_CLK_GPMI_IO>,
+ <&clks IMX6UL_CLK_GPMI_APB>,
+ <&clks IMX6UL_CLK_GPMI_BCH>,
+ <&clks IMX6UL_CLK_GPMI_BCH_APB>,
+ <&clks IMX6UL_CLK_PER_BCH>;
+ clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ aips1: aips-bus@02000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x100000>;
+ ranges;
+
+ spba-bus@02000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x40000>;
+ ranges;
+
+ ecspi1: ecspi@02008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02008000 0x4000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI1>,
+ <&clks IMX6UL_CLK_ECSPI1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi2: ecspi@0200c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0200c000 0x4000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI2>,
+ <&clks IMX6UL_CLK_ECSPI2>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi3: ecspi@02010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02010000 0x4000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI3>,
+ <&clks IMX6UL_CLK_ECSPI3>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi4: ecspi@02014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02014000 0x4000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI4>,
+ <&clks IMX6UL_CLK_ECSPI4>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart7: serial@02018000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x02018000 0x4000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART7_IPG>,
+ <&clks IMX6UL_CLK_UART7_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart1: serial@02020000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART1_IPG>,
+ <&clks IMX6UL_CLK_UART1_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart8: serial@02024000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x02024000 0x4000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART8_IPG>,
+ <&clks IMX6UL_CLK_UART8_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ sai1: sai@02028000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+ reg = <0x02028000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
+ <&clks IMX6UL_CLK_SAI1>,
+ <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma 35 24 0>,
+ <&sdma 36 24 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai2: sai@0202c000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+ reg = <0x0202c000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
+ <&clks IMX6UL_CLK_SAI2>,
+ <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma 37 24 0>,
+ <&sdma 38 24 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai3: sai@02030000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+ reg = <0x02030000 0x4000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
+ <&clks IMX6UL_CLK_SAI3>,
+ <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma 39 24 0>,
+ <&sdma 40 24 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ };
+
+ tsc: tsc@02040000 {
+ compatible = "fsl,imx6ul-tsc";
+ reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_IPG>,
+ <&clks IMX6UL_CLK_ADC2>;
+ clock-names = "tsc", "adc";
+ status = "disabled";
+ };
+
+ pwm1: pwm@02080000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x02080000 0x4000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM1>,
+ <&clks IMX6UL_CLK_PWM1>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@02084000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x02084000 0x4000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM2>,
+ <&clks IMX6UL_CLK_PWM2>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@02088000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x02088000 0x4000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM3>,
+ <&clks IMX6UL_CLK_PWM3>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@0208c000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x0208c000 0x4000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM4>,
+ <&clks IMX6UL_CLK_PWM4>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ can1: flexcan@02090000 {
+ compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x02090000 0x4000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
+ <&clks IMX6UL_CLK_CAN1_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can2: flexcan@02094000 {
+ compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x02094000 0x4000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
+ <&clks IMX6UL_CLK_CAN2_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ gpt1: gpt@02098000 {
+ compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
+ <&clks IMX6UL_CLK_GPT1_SERIAL>;
+ clock-names = "ipg", "per";
+ };
+
+ gpio1: gpio@0209c000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
+ <&iomuxc 16 33 16>;
+ };
+
+ gpio2: gpio@020a0000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
+ };
+
+ gpio3: gpio@020a4000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 65 29>;
+ };
+
+ gpio4: gpio@020a8000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
+ };
+
+ gpio5: gpio@020ac000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
+ };
+
+ fec2: ethernet@020b4000 {
+ compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
+ reg = <0x020b4000 0x4000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ENET>,
+ <&clks IMX6UL_CLK_ENET_AHB>,
+ <&clks IMX6UL_CLK_ENET_PTP>,
+ <&clks IMX6UL_CLK_ENET2_REF_125M>,
+ <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues=<1>;
+ fsl,num-rx-queues=<1>;
+ status = "disabled";
+ };
+
+ kpp: kpp@020b8000 {
+ compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
+ reg = <0x020b8000 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_KPP>;
+ status = "disabled";
+ };
+
+ wdog1: wdog@020bc000 {
+ compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_WDOG1>;
+ };
+
+ wdog2: wdog@020c0000 {
+ compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
+ reg = <0x020c0000 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_WDOG2>;
+ status = "disabled";
+ };
+
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6ul-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+ };
+
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x020c8000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg_3p0: regulator-3p0 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+ regulator-min-microvolt = <2625000>;
+ regulator-max-microvolt = <3400000>;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
+ };
+
+ reg_arm: regulator-vddcore {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "cpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <0>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <24>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+
+ reg_soc: regulator-vddsoc {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddsoc";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <18>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <28>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+ };
+
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBPHY1>;
+ phy-3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy@020ca000 {
+ compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBPHY2>;
+ phy-3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ snvs: snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_rtc: snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&snvs>;
+ offset = <0x34>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs_poweroff: snvs-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&snvs>;
+ offset = <0x38>;
+ mask = <0x60>;
+ status = "disabled";
+ };
+
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ epit1: epit@020d0000 {
+ reg = <0x020d0000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epit2: epit@020d4000 {
+ reg = <0x020d4000 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ src: src@020d8000 {
+ compatible = "fsl,imx6ul-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6ul-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ };
+
+ gpr: iomuxc-gpr@020e4000 {
+ compatible = "fsl,imx6ul-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ };
+
+ gpt2: gpt@020e8000 {
+ compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
+ reg = <0x020e8000 0x4000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
+ <&clks IMX6UL_CLK_GPT2_SERIAL>;
+ clock-names = "ipg", "per";
+ };
+
+ sdma: sdma@020ec000 {
+ compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
+ "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SDMA>,
+ <&clks IMX6UL_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+
+ pwm5: pwm@020f0000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020f0000 0x4000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM5>,
+ <&clks IMX6UL_CLK_PWM5>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@020f4000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020f4000 0x4000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM6>,
+ <&clks IMX6UL_CLK_PWM6>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm7: pwm@020f8000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020f8000 0x4000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM7>,
+ <&clks IMX6UL_CLK_PWM7>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm8: pwm@020fc000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020fc000 0x4000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM8>,
+ <&clks IMX6UL_CLK_PWM8>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ aips2: aips-bus@02100000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+ usbotg1: usb@02184000 {
+ compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ fsl,anatop = <&anatop>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbotg2: usb@02184200 {
+ compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc@02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ };
+
+ fec1: ethernet@02188000 {
+ compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
+ reg = <0x02188000 0x4000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ENET>,
+ <&clks IMX6UL_CLK_ENET_AHB>,
+ <&clks IMX6UL_CLK_ENET_PTP>,
+ <&clks IMX6UL_CLK_ENET_REF>,
+ <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues=<1>;
+ fsl,num-rx-queues=<1>;
+ status = "disabled";
+ };
+
+ usdhc1: usdhc@02190000 {
+ compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02190000 0x4000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USDHC1>,
+ <&clks IMX6UL_CLK_USDHC1>,
+ <&clks IMX6UL_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc@02194000 {
+ compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02194000 0x4000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USDHC2>,
+ <&clks IMX6UL_CLK_USDHC2>,
+ <&clks IMX6UL_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ adc1: adc@02198000 {
+ compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
+ reg = <0x02198000 0x4000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ADC1>;
+ num-channels = <2>;
+ clock-names = "adc";
+ fsl,adck-max-frequency = <30000000>, <40000000>,
+ <20000000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@021a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@021a4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@021a8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ mmdc: mmdc@021b0000 {
+ compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+
+ lcdif: lcdif@021c8000 {
+ compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
+ reg = <0x021c8000 0x4000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
+ <&clks IMX6UL_CLK_LCDIF_APB>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "pix", "axi", "disp_axi";
+ status = "disabled";
+ };
+
+ qspi: qspi@021e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
+ reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_QSPI>,
+ <&clks IMX6UL_CLK_QSPI>;
+ clock-names = "qspi_en", "qspi";
+ status = "disabled";
+ };
+
+ uart2: serial@021e8000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021e8000 0x4000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART2_IPG>,
+ <&clks IMX6UL_CLK_UART2_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart3: serial@021ec000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021ec000 0x4000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART3_IPG>,
+ <&clks IMX6UL_CLK_UART3_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart4: serial@021f0000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021f0000 0x4000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART4_IPG>,
+ <&clks IMX6UL_CLK_UART4_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart5: serial@021f4000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021f4000 0x4000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART5_IPG>,
+ <&clks IMX6UL_CLK_UART5_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c4: i2c@021f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021f8000 0x4000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C4>;
+ status = "disabled";
+ };
+
+ uart6: serial@021fc000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x021fc000 0x4000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART6_IPG>,
+ <&clks IMX6UL_CLK_UART6_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts
new file mode 100644
index 0000000..375bd4e
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-evk.dts
@@ -0,0 +1,527 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ull.dtsi"
+
+/ {
+ model = "Freescale i.MX6 ULL 14x14 EVK Board";
+ compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_can_3v3: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "can-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_sd1_vmmc: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_gpio_dvfs: regulator-gpio {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dvfs>;
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "gpio_dvfs";
+ regulator-type = "voltage";
+ gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+ states = <1300000 0x1 1400000 0x0>;
+ };
+ };
+
+ spi4 {
+ compatible = "spi-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi4>;
+ status = "okay";
+ gpio-sck = <&gpio5 11 0>;
+ gpio-mosi = <&gpio5 10 0>;
+ cs-gpios = <&gpio5 7 0>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio_spi: gpio_spi@0 {
+ compatible = "fairchild,74hc595";
+ gpio-controller;
+ oe-gpios = <&gpio5 8 0>;
+ #gpio-cells = <2>;
+ reg = <0>;
+ registers-number = <1>;
+ registers-default = /bits/ 8 <0x57>;
+ spi-max-frequency = <100000>;
+ };
+ };
+};
+
+&cpu0 {
+ arm-supply = <®_arm>;
+ soc-supply = <®_soc>;
+ dc-supply = <®_gpio_dvfs>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <786432000>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&gpc {
+ fsl,cpu_pupscr_sw2iso = <0x1>;
+ fsl,cpu_pupscr_sw = <0x0>;
+ fsl,cpu_pdnscr_iso2sw = <0x1>;
+ fsl,cpu_pdnscr_iso = <0x1>;
+ fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ mag3110@0e {
+ compatible = "fsl,mag3110";
+ reg = <0x0e>;
+ position = <2>;
+ };
+
+ fxls8471@1e {
+ compatible = "fsl,fxls8471";
+ reg = <0x1e>;
+ position = <0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <0 8>;
+ };
+};
+
+&i2c2 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_1>;
+ imx6ul-evk {
+ pinctrl_hog_1: hoggrp-1 {
+ fsl,pins = <
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
+ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
+ >;
+ };
+
+ pinctrl_csi1: csi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
+ MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
+ MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
+ MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
+ MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
+ MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
+ MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
+ MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
+ MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
+ MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
+ MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
+ MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp{
+ fsl,pins = <
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
+ MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
+ MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
+ MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
+ MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
+ MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
+ MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
+ MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2dte: uart2dtegrp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+ };
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default_snvs";
+ pinctrl-0 = <&pinctrl_hog_2>;
+ imx6ul-evk {
+ pinctrl_hog_2: hoggrp-2 {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
+ >;
+ };
+
+ pinctrl_dvfs: dvfsgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
+ >;
+ };
+
+ pinctrl_lcdif_reset: lcdifresetgrp {
+ fsl,pins = <
+ /* used for lcd reset */
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
+ >;
+ };
+
+ pinctrl_spi4: spi4grp {
+ fsl,pins = <
+ MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
+ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
+ >;
+ };
+
+ pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
+ >;
+ };
+ };
+};
+
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+ &pinctrl_lcdif_ctrl
+ &pinctrl_lcdif_reset>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display {
+ bits-per-pixel = <16>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <9200000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <8>;
+ hback-porch = <4>;
+ hsync-len = <41>;
+ vback-porch = <2>;
+ vfront-porch = <4>;
+ vsync-len = <10>;
+
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+ ddrsmp=<0>;
+
+ flash0: n25q256a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a";
+ spi-max-frequency = <29000000>;
+ spi-nor,ddr-quad-read-dummy = <6>;
+ reg = <0>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ fsl,uart-has-rtscts;
+ /* for DTE mode, add below change */
+ /* fsl,dte-mode; */
+ /* pinctrl-0 = <&pinctrl_uart2dte>; */
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbphy1 {
+ tx-d-cal = <0x5>;
+};
+
+&usbphy2 {
+ tx-d-cal = <0x5>;
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ vmmc-supply = <®_sd1_vmmc>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ no-1-8-v;
+ non-removable;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,wdog_b;
+};
diff --git a/arch/arm/dts/imx6ull-pinfunc-snvs.h b/arch/arm/dts/imx6ull-pinfunc-snvs.h
new file mode 100644
index 0000000..da3f412
--- /dev/null
+++ b/arch/arm/dts/imx6ull-pinfunc-snvs.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H
+#define __DTS_IMX6ULL_PINFUNC_SNVS_H
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
+#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */
+
diff --git a/arch/arm/dts/imx6ull-pinfunc.h b/arch/arm/dts/imx6ull-pinfunc.h
new file mode 100644
index 0000000..fca0036
--- /dev/null
+++ b/arch/arm/dts/imx6ull-pinfunc.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_H
+#define __DTS_IMX6ULL_PINFUNC_H
+
+#include "imx6ul-pinfunc.h"
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
+
+#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_H */
diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
new file mode 100644
index 0000000..65950e8
--- /dev/null
+++ b/arch/arm/dts/imx6ull.dtsi
@@ -0,0 +1,1161 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx6ul-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx6ull-pinfunc.h"
+#include "imx6ull-pinfunc-snvs.h"
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ can0 = &flexcan1;
+ can1 = &flexcan2;
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ serial6 = &uart7;
+ serial7 = &uart8;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
+ usbphy0 = &usbphy1;
+ usbphy1 = &usbphy2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ operating-points = <
+ /* kHz uV */
+ 528000 1175000
+ 99000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* KHz uV */
+ 528000 1175000
+ 99000 1175000
+ >;
+ clocks = <&clks IMX6UL_CLK_ARM>,
+ <&clks IMX6UL_CLK_PLL2_BUS>,
+ <&clks IMX6UL_CLK_PLL2_PFD2>,
+ <&clks IMX6UL_CA7_SECONDARY_SEL>,
+ <&clks IMX6UL_CLK_STEP>,
+ <&clks IMX6UL_CLK_PLL1_SW>,
+ <&clks IMX6UL_CLK_PLL1_SYS>,
+ <&clks IMX6UL_PLL1_BYPASS>,
+ <&clks IMX6UL_CLK_PLL1>,
+ <&clks IMX6UL_PLL1_BYPASS_SRC>,
+ <&clks IMX6UL_CLK_OSC>;
+ clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step",
+ "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc";
+ };
+ };
+
+ intc: interrupt-controller@00a01000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a02000 0x100>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckil: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
+ };
+
+ osc: clock@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc";
+ };
+
+ ipp_di0: clock@2 {
+ compatible = "fixed-clock";
+ reg = <2>;
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di0";
+ };
+
+ ipp_di1: clock@3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di1";
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gpc>;
+ ranges;
+
+ busfreq {
+ compatible = "fsl,imx_busfreq";
+ clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
+ <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
+ <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
+ <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
+ <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
+ <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
+ <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
+ <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
+ <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>,
+ <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>,
+ <&clks IMX6UL_CLK_PLL1>;
+ clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
+ "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
+ "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
+ "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
+ fsl,max_ddr_freq = <400000000>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ocrams: sram@00900000 {
+ compatible = "fsl,lpm-sram";
+ reg = <0x00900000 0x4000>;
+ };
+
+ ocrams_ddr: sram@00904000 {
+ compatible = "fsl,ddr-lpm-sram";
+ reg = <0x00904000 0x1000>;
+ };
+
+ ocram: sram@00905000 {
+ compatible = "mmio-sram";
+ reg = <0x00905000 0x1B000>;
+ };
+
+ dma_apbh: dma-apbh@01804000 {
+ compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x01804000 0x2000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clks IMX6UL_CLK_APBHDMA>;
+ };
+
+ gpmi: gpmi-nand@01806000{
+ compatible = "fsl,imx6ull-gpmi-nand", "fsl, imx6ul-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clks IMX6UL_CLK_GPMI_IO>,
+ <&clks IMX6UL_CLK_GPMI_APB>,
+ <&clks IMX6UL_CLK_GPMI_BCH>,
+ <&clks IMX6UL_CLK_GPMI_BCH_APB>,
+ <&clks IMX6UL_CLK_PER_BCH>;
+ clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ aips1: aips-bus@02000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x100000>;
+ ranges;
+
+ spba-bus@02000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x40000>;
+ ranges;
+
+ spdif: spdif@02004000 {
+ compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 41 18 0>,
+ <&sdma 42 18 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>,
+ <&clks IMX6UL_CLK_OSC>,
+ <&clks IMX6UL_CLK_SPDIF>,
+ <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_IPG>,
+ <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_SPBA>;
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "dma";
+ status = "disabled";
+ };
+
+ ecspi1: ecspi@02008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02008000 0x4000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI1>,
+ <&clks IMX6UL_CLK_ECSPI1>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ecspi2: ecspi@0200c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0200c000 0x4000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI2>,
+ <&clks IMX6UL_CLK_ECSPI2>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ecspi3: ecspi@02010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02010000 0x4000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI3>,
+ <&clks IMX6UL_CLK_ECSPI3>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ecspi4: ecspi@02014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02014000 0x4000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ECSPI4>,
+ <&clks IMX6UL_CLK_ECSPI4>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart7: serial@02018000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02018000 0x4000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART7_IPG>,
+ <&clks IMX6UL_CLK_UART7_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@02020000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART1_IPG>,
+ <&clks IMX6UL_CLK_UART1_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ esai: esai@02024000 {
+ compatible = "fsl,imx6ull-esai";
+ reg = <0x02024000 0x4000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ESAI_IPG>,
+ <&clks IMX6UL_CLK_ESAI_MEM>,
+ <&clks IMX6UL_CLK_ESAI_EXTAL>,
+ <&clks IMX6UL_CLK_ESAI_IPG>,
+ <&clks IMX6UL_CLK_SPBA>;
+ clock-names = "core", "mem", "extal",
+ "fsys", "dma";
+ dmas = <&sdma 0 21 0>, <&sdma 47 21 0>;
+ dma-names = "rx", "tx";
+ dma-source = <&gpr 0 14 0 15>;
+ status = "disabled";
+ };
+
+ sai1: sai@02028000 {
+ compatible = "fsl,imx6ul-sai",
+ "fsl,imx6sx-sai";
+ reg = <0x02028000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
+ <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_SAI1>,
+ <&clks 0>, <&clks 0>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
+ status = "disabled";
+ };
+
+ sai2: sai@0202c000 {
+ compatible = "fsl,imx6ul-sai",
+ "fsl,imx6sx-sai";
+ reg = <0x0202c000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
+ <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_SAI2>,
+ <&clks 0>, <&clks 0>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 37 24 0>, <&sdma 38 24 0>;
+ status = "disabled";
+ };
+
+ sai3: sai@02030000 {
+ compatible = "fsl,imx6ul-sai",
+ "fsl,imx6sx-sai";
+ reg = <0x02030000 0x4000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
+ <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_SAI3>,
+ <&clks 0>, <&clks 0>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 39 24 0>, <&sdma 40 24 0>;
+ status = "disabled";
+ };
+
+ asrc: asrc@02034000 {
+ compatible = "fsl,imx53-asrc";
+ reg = <0x02034000 0x4000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
+ <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
+ <&clks IMX6UL_CLK_SPBA>;
+ clock-names = "mem", "ipg", "asrck_0",
+ "asrck_1", "asrck_2", "asrck_3", "asrck_4",
+ "asrck_5", "asrck_6", "asrck_7", "asrck_8",
+ "asrck_9", "asrck_a", "asrck_b", "asrck_c",
+ "asrck_d", "asrck_e", "asrck_f", "dma";
+ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
+ <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
+ dma-names = "rxa", "rxb", "rxc",
+ "txa", "txb", "txc";
+ fsl,asrc-rate = <48000>;
+ fsl,asrc-width = <16>;
+ status = "okay";
+ };
+ };
+
+ tsc: tsc@02040000 {
+ compatible = "fsl,imx6ul-tsc";
+ reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_IPG>,
+ <&clks IMX6UL_CLK_ADC2>;
+ clock-names = "tsc", "adc";
+ status = "disabled";
+ };
+
+ pwm1: pwm@02080000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x02080000 0x4000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM1>,
+ <&clks IMX6UL_CLK_PWM1>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm2: pwm@02084000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x02084000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm3: pwm@02088000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x02088000 0x4000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PWM3>,
+ <&clks IMX6UL_CLK_PWM3>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm4: pwm@0208c000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x0208c000 0x4000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ flexcan1: can@02090000 {
+ compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x02090000 0x4000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
+ <&clks IMX6UL_CLK_CAN1_SERIAL>;
+ clock-names = "ipg", "per";
+ stop-mode = <&gpr 0x10 1 0x10 17>;
+ status = "disabled";
+ };
+
+ flexcan2: can@02094000 {
+ compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x02094000 0x4000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
+ <&clks IMX6UL_CLK_CAN2_SERIAL>;
+ clock-names = "ipg", "per";
+ stop-mode = <&gpr 0x10 2 0x10 18>;
+ status = "disabled";
+ };
+
+ gpt1: gpt@02098000 {
+ compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
+ <&clks IMX6UL_CLK_GPT1_SERIAL>;
+ clock-names = "ipg", "per";
+ };
+
+ gpio1: gpio@0209c000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@020a0000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@020a4000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@020a8000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@020ac000 {
+ compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ snvslp: snvs@020b0000 {
+ compatible = "fsl,imx6ul-snvs";
+ reg = <0x020b0000 0x4000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ fec2: ethernet@020b4000 {
+ compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
+ reg = <0x020b4000 0x4000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ENET>,
+ <&clks IMX6UL_CLK_ENET_AHB>,
+ <&clks IMX6UL_CLK_ENET_PTP>,
+ <&clks IMX6UL_CLK_ENET2_REF_125M>,
+ <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ stop-mode = <&gpr 0x10 4>;
+ fsl,num-tx-queues=<1>;
+ fsl,num-rx-queues=<1>;
+ fsl,magic-packet;
+ fsl,wakeup_irq = <0>;
+ status = "disabled";
+ };
+
+ kpp: kpp@020b8000 {
+ compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
+ reg = <0x020b8000 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>;
+ status = "disabled";
+ };
+
+ wdog1: wdog@020bc000 {
+ compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_WDOG1>;
+ };
+
+ wdog2: wdog@020c0000 {
+ compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
+ reg = <0x020c0000 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_WDOG2>;
+ status = "disabled";
+ };
+
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6ul-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+ };
+
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x020c8000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg_3p0: regulator-3p0@120 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+ regulator-min-microvolt = <2625000>;
+ regulator-max-microvolt = <3400000>;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
+ };
+
+ reg_arm: regulator-vddcore@140 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "cpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <0>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <24>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+
+ reg_soc: regulator-vddsoc@140 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddsoc";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <18>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <28>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+ };
+
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBPHY1>;
+ phy-3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy@020ca000 {
+ compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBPHY2>;
+ phy-3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ fsl,tempmon-data = <&ocotp>;
+ clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
+ };
+
+ snvs: snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_rtc: snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&snvs>;
+ offset = <0x34>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs_poweroff: snvs-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&snvs>;
+ offset = <0x38>;
+ mask = <0x61>;
+ };
+
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup;
+ };
+ };
+
+ epit1: epit@020d0000 {
+ reg = <0x020d0000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epit2: epit@020d4000 {
+ reg = <0x020d4000 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ src: src@020d8000 {
+ compatible = "fsl,imx6ul-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>;
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6ul-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ };
+
+ gpr: iomuxc-gpr@020e4000 {
+ compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ };
+
+ mqs: mqs {
+ compatible = "fsl,imx6sx-mqs";
+ gpr = <&gpr>;
+ status = "disabled";
+ };
+
+ gpt2: gpt@020e8000 {
+ compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
+ reg = <0x020e8000 0x4000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "ipg", "per";
+ };
+
+ sdma: sdma@020ec000 {
+ compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_SDMA>,
+ <&clks IMX6UL_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ iram = <&ocram>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+
+ pwm5: pwm@020f0000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020f0000 0x4000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm6: pwm@020f4000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020f4000 0x4000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm7: pwm@020f8000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020f8000 0x4000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm8: pwm@020fc000 {
+ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+ reg = <0x020fc000 0x4000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+ };
+
+ aips2: aips-bus@02100000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+ usbotg1: usb@02184000 {
+ compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ fsl,anatop = <&anatop>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbotg2: usb@02184200 {
+ compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc@02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ };
+
+ fec1: ethernet@02188000 {
+ compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
+ reg = <0x02188000 0x4000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ENET>,
+ <&clks IMX6UL_CLK_ENET_AHB>,
+ <&clks IMX6UL_CLK_ENET_PTP>,
+ <&clks IMX6UL_CLK_ENET_REF>,
+ <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ stop-mode = <&gpr 0x10 3>;
+ fsl,num-tx-queues=<1>;
+ fsl,num-rx-queues=<1>;
+ fsl,magic-packet;
+ fsl,wakeup_irq = <0>;
+ status = "disabled";
+ };
+
+ usdhc1: usdhc@02190000 {
+ compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02190000 0x4000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USDHC1>,
+ <&clks IMX6UL_CLK_USDHC1>,
+ <&clks IMX6UL_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc@02194000 {
+ compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02194000 0x4000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_USDHC2>,
+ <&clks IMX6UL_CLK_USDHC2>,
+ <&clks IMX6UL_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ adc1: adc@02198000 {
+ compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
+ reg = <0x02198000 0x4000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ADC1>;
+ num-channels = <2>;
+ clock-names = "adc";
+ status = "disabled";
+ };
+
+ i2c1: i2c@021a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@021a4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@021a8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ romcp@021ac000 {
+ compatible = "fsl,imx6ul-romcp", "syscon";
+ reg = <0x021ac000 0x4000>;
+ };
+
+ mmdc: mmdc@021b0000 {
+ compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+
+ weim: weim@021b8000 {
+ compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
+ reg = <0x021b8000 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>;
+ };
+
+ ocotp: ocotp-ctrl@021bc000 {
+ compatible = "fsl,imx6ull-ocotp", "syscon";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6UL_CLK_OCOTP>;
+ };
+
+ csu: csu@021c0000 {
+ compatible = "fsl,imx6ul-csu";
+ reg = <0x021c0000 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ csi: csi@021c4000 {
+ compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi";
+ reg = <0x021c4000 0x4000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>,
+ <&clks IMX6UL_CLK_CSI>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+ status = "disabled";
+ };
+
+ lcdif: lcdif@021c8000 {
+ compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
+ reg = <0x021c8000 0x4000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
+ <&clks IMX6UL_CLK_LCDIF_APB>,
+ <&clks IMX6UL_CLK_DUMMY>;
+ clock-names = "pix", "axi", "disp_axi";
+ status = "disabled";
+ };
+
+ pxp: pxp@021cc000 {
+ compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
+ reg = <0x021cc000 0x4000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>;
+ clock-names = "pxp_ipg", "pxp_axi";
+ status = "disabled";
+ };
+
+ qspi: qspi@021e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ull-qspi", "fsl,imx6ul-qspi";
+ reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_QSPI>,
+ <&clks IMX6UL_CLK_QSPI>;
+ clock-names = "qspi_en", "qspi";
+ status = "disabled";
+ };
+
+ uart2: serial@021e8000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021e8000 0x4000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART2_IPG>,
+ <&clks IMX6UL_CLK_UART2_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@021ec000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021ec000 0x4000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART3_IPG>,
+ <&clks IMX6UL_CLK_UART3_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@021f0000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021f0000 0x4000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART4_IPG>,
+ <&clks IMX6UL_CLK_UART4_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@021f4000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021f4000 0x4000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART5_IPG>,
+ <&clks IMX6UL_CLK_UART5_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c4: i2c@021f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+ reg = <0x021f8000 0x4000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_I2C4>;
+ status = "disabled";
+ };
+
+ uart6: serial@021fc000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021fc000 0x4000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART6_IPG>,
+ <&clks IMX6UL_CLK_UART6_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ };
+
+ aips3: aips-bus@02200000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02200000 0x100000>;
+ ranges;
+
+ dcp: dcp@02280000 {
+ reg = <0x02280000 0x4000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ /*clocks = <&clks IMX6UL_CLK_DCP>;*/
+ clock-names = "dcp";
+ status = "disabled";
+ };
+
+ rngb: rngb@02284000 {
+ reg = <0x02284000 0x4000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart8: serial@02288000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02288000 0x4000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART8_IPG>,
+ <&clks IMX6UL_CLK_UART8_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ epdc: epdc@0228c000 {
+ compatible = "fsl,imx7d-epdc";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0228c000 0x4000>;
+ clocks = <&clks IMX6UL_CLK_EPDC_ACLK>,
+ <&clks IMX6UL_CLK_EPDC_PIX>;
+ clock-names = "epdc_axi", "epdc_pix";
+ /* Need to fix epdc-ram */
+ /* epdc-ram = <&gpr 0x4 30>; */
+ status = "disabled";
+ };
+
+ iomuxc_snvs: iomuxc-snvs@02290000 {
+ compatible = "fsl,imx6ull-iomuxc-snvs";
+ reg = <0x02290000 0x10000>;
+ };
+
+ snvs_gpr: snvs-gpr@0x02294000 {
+ compatible = "fsl, imx6ull-snvs-gpr";
+ reg = <0x02294000 0x10000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts
new file mode 100644
index 0000000..cbef5d5
--- /dev/null
+++ b/arch/arm/dts/imx7-colibri.dts
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx7.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7S/D";
+ compatible = "toradex,imx7-colibri", "fsl,imx7";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ rn5t567@33 {
+ compatible = "ricoh,rn5t567";
+ reg = <0x33>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
+ uart-has-rtscts;
+ fsl,dte-mode;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c4: i2c4-grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
+ MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4-gpio-grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
+ MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
+ MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
+ MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
+ MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
+ >;
+ };
+
+ pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
+ MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f
+ MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx7.dtsi b/arch/arm/dts/imx7.dtsi
new file mode 100644
index 0000000..755cc46
--- /dev/null
+++ b/arch/arm/dts/imx7.dtsi
@@ -0,0 +1,194 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+#include "imx7d-pinfunc.h"
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ serial6 = &uart7;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+
+ aips1: aips-bus@30000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30000000 0x400000>;
+ ranges;
+
+ gpio1: gpio@30200000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30200000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio2: gpio@30210000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30210000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio3: gpio@30220000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30220000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio4: gpio@30230000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30230000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio5: gpio@30240000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30240000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio6: gpio@30250000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30250000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio7: gpio@30260000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30260000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ iomuxc_lpsr: iomuxc-lpsr@302c0000 {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c0000 0x10000>;
+ fsl,input-sel = <&iomuxc>;
+ };
+
+ iomuxc: iomuxc@30330000 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x30330000 0x10000>;
+ };
+ };
+
+ aips3: aips-bus@30800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30800000 0x400000>;
+ ranges;
+
+ uart1: serial@30860000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ status = "disabled";
+ };
+
+ uart2: serial@30890000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ status = "disabled";
+ };
+
+ uart3: serial@30880000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@30a20000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+ reg = <0x30a20000 0x10000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@30a30000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+ reg = <0x30a30000 0x10000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@30a40000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+ reg = <0x30a40000 0x10000>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@30a50000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+ reg = <0x30a50000 0x10000>;
+ status = "disabled";
+ };
+
+ uart4: serial@30a60000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a60000 0x10000>;
+ status = "disabled";
+ };
+
+ uart5: serial@30a70000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a70000 0x10000>;
+ status = "disabled";
+ };
+
+ uart6: serial@30a80000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a80000 0x10000>;
+ status = "disabled";
+ };
+
+ uart7: serial@30a90000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a90000 0x10000>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx7d-pinfunc.h b/arch/arm/dts/imx7d-pinfunc.h
new file mode 100644
index 0000000..32d2464
--- /dev/null
+++ b/arch/arm/dts/imx7d-pinfunc.h
@@ -0,0 +1,1151 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DTS_IMX7D_PINFUNC_H
+#define __DTS_IMX7D_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
+#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
+#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
+#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
+#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
+#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
+#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
+#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
+#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
+#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
+#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
+#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
+#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
+#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
+#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
+#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
+#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
+#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
+#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
+#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
+#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
+#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0
+#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1
+#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0
+#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0
+#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1
+#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0
+#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0
+#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0
+#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0
+#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0
+#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1
+#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0
+#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0
+#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0
+#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0
+#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0
+#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0
+#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0
+#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0
+#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0
+#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 0x0034 0x02A4 0x0620 0x3 0x0
+#define MX7D_PAD_EPDC_DATA00__EIM_AD0 0x0034 0x02A4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x0034 0x02A4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x0034 0x02A4 0x0638 0x6 0x0
+#define MX7D_PAD_EPDC_DATA00__LCD_CLK 0x0034 0x02A4 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x0038 0x02A8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK 0x0038 0x02A8 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA01__KPP_COL3 0x0038 0x02A8 0x0600 0x3 0x0
+#define MX7D_PAD_EPDC_DATA01__EIM_AD1 0x0038 0x02A8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x0038 0x02A8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x0038 0x02A8 0x063C 0x6 0x0
+#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE 0x0038 0x02A8 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x003C 0x02AC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B 0x003C 0x02AC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 0x003C 0x02AC 0x061C 0x3 0x0
+#define MX7D_PAD_EPDC_DATA02__EIM_AD2 0x003C 0x02AC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x003C 0x02AC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x003C 0x02AC 0x0640 0x6 0x0
+#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC 0x003C 0x02AC 0x0698 0x7 0x0
+#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x0040 0x02B0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN 0x0040 0x02B0 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA03__KPP_COL2 0x0040 0x02B0 0x05FC 0x3 0x0
+#define MX7D_PAD_EPDC_DATA03__EIM_AD3 0x0040 0x02B0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x0040 0x02B0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x0040 0x02B0 0x0644 0x6 0x0
+#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC 0x0040 0x02B0 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x0044 0x02B4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD 0x0044 0x02B4 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 0x0044 0x02B4 0x0618 0x3 0x0
+#define MX7D_PAD_EPDC_DATA04__EIM_AD4 0x0044 0x02B4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x0044 0x02B4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x0044 0x02B4 0x0648 0x6 0x0
+#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL 0x0044 0x02B4 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x0048 0x02B8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD 0x0048 0x02B8 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA05__KPP_COL1 0x0048 0x02B8 0x05F8 0x3 0x0
+#define MX7D_PAD_EPDC_DATA05__EIM_AD5 0x0048 0x02B8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x0048 0x02B8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x0048 0x02B8 0x064C 0x6 0x0
+#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE 0x0048 0x02B8 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x004C 0x02BC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK 0x004C 0x02BC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 0x004C 0x02BC 0x0614 0x3 0x0
+#define MX7D_PAD_EPDC_DATA06__EIM_AD6 0x004C 0x02BC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x004C 0x02BC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x004C 0x02BC 0x0650 0x6 0x0
+#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B 0x004C 0x02BC 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x0050 0x02C0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B 0x0050 0x02C0 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA07__KPP_COL0 0x0050 0x02C0 0x05F4 0x3 0x0
+#define MX7D_PAD_EPDC_DATA07__EIM_AD7 0x0050 0x02C0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x0050 0x02C0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x0050 0x02C0 0x0654 0x6 0x0
+#define MX7D_PAD_EPDC_DATA07__JTAG_DONE 0x0050 0x02C0 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x0054 0x02C4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x0054 0x02C4 0x06E4 0x1 0x0
+#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x0054 0x02C4 0x071C 0x3 0x0
+#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX 0x0054 0x02C4 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA08__EIM_OE 0x0054 0x02C4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x0054 0x02C4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x0054 0x02C4 0x0658 0x6 0x0
+#define MX7D_PAD_EPDC_DATA08__LCD_BUSY 0x0054 0x02C4 0x0634 0x7 0x0
+#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK 0x0054 0x02C4 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x0058 0x02C8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x0058 0x02C8 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x0058 0x02C8 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX 0x0058 0x02C8 0x071C 0x3 0x1
+#define MX7D_PAD_EPDC_DATA09__EIM_RW 0x0058 0x02C8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x0058 0x02C8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x0058 0x02C8 0x065C 0x6 0x0
+#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 0x0058 0x02C8 0x0638 0x7 0x1
+#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE 0x0058 0x02C8 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x005C 0x02CC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x005C 0x02CC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x005C 0x02CC 0x0718 0x3 0x0
+#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x005C 0x02CC 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x005C 0x02CC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x005C 0x02CC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x005C 0x02CC 0x0660 0x6 0x0
+#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 0x005C 0x02CC 0x065C 0x7 0x1
+#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE 0x005C 0x02CC 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x0060 0x02D0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x0060 0x02D0 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x0060 0x02D0 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x0060 0x02D0 0x0718 0x3 0x1
+#define MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x0060 0x02D0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x0060 0x02D0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x0060 0x02D0 0x0664 0x6 0x0
+#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 0x0060 0x02D0 0x063C 0x7 0x1
+#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 0x0060 0x02D0 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x0064 0x02D4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x0064 0x02D4 0x06E0 0x1 0x0
+#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x0064 0x02D4 0x0724 0x3 0x0
+#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX 0x0064 0x02D4 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x0064 0x02D4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x0064 0x02D4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x0064 0x02D4 0x0668 0x6 0x0
+#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 0x0064 0x02D4 0x068C 0x7 0x0
+#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK 0x0064 0x02D4 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x0068 0x02D8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD 0x0068 0x02D8 0x06EC 0x1 0x0
+#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x0068 0x02D8 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX 0x0068 0x02D8 0x0724 0x3 0x1
+#define MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x0068 0x02D8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x0068 0x02D8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x0068 0x02D8 0x066C 0x6 0x0
+#define MX7D_PAD_EPDC_DATA13__LCD_CS 0x0068 0x02D8 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE 0x0068 0x02D8 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x006C 0x02DC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK 0x006C 0x02DC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x006C 0x02DC 0x0720 0x3 0x0
+#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x006C 0x02DC 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 0x006C 0x02DC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x006C 0x02DC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x006C 0x02DC 0x0670 0x6 0x0
+#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 0x006C 0x02DC 0x0690 0x7 0x0
+#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP 0x006C 0x02DC 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x0070 0x02E0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B 0x0070 0x02E0 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x0070 0x02E0 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x0070 0x02E0 0x0720 0x3 0x1
+#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B 0x0070 0x02E0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x0070 0x02E0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x0070 0x02E0 0x0674 0x6 0x0
+#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN 0x0070 0x02E0 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM 0x0070 0x02E0 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x0074 0x02E4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN 0x0074 0x02E4 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 0x0074 0x02E4 0x0624 0x3 0x0
+#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x0074 0x02E4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0074 0x02E4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x0074 0x02E4 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 0x0074 0x02E4 0x0688 0x7 0x0
+#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x0078 0x02E8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD 0x0078 0x02E8 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDLE__KPP_COL4 0x0078 0x02E8 0x0604 0x3 0x0
+#define MX7D_PAD_EPDC_SDLE__EIM_AD11 0x0078 0x02E8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0078 0x02E8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x0078 0x02E8 0x0678 0x6 0x0
+#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 0x0078 0x02E8 0x0658 0x7 0x1
+#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x007C 0x02EC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 0x007C 0x02EC 0x0584 0x1 0x0
+#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDOE__KPP_COL5 0x007C 0x02EC 0x0608 0x3 0x1
+#define MX7D_PAD_EPDC_SDOE__EIM_AD12 0x007C 0x02EC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x007C 0x02EC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x007C 0x02EC 0x067C 0x6 0x0
+#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 0x007C 0x02EC 0x0694 0x7 0x0
+#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x0080 0x02F0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 0x0080 0x02F0 0x0588 0x1 0x0
+#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 0x0080 0x02F0 0x0628 0x3 0x1
+#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x0080 0x02F0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x0080 0x02F0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x0080 0x02F0 0x0680 0x6 0x0
+#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 0x0080 0x02F0 0x0660 0x7 0x1
+#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x0084 0x02F4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 0x0084 0x02F4 0x058C 0x1 0x0
+#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x0084 0x02F4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0084 0x02F4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x0084 0x02F4 0x0684 0x6 0x0
+#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 0x0084 0x02F4 0x064C 0x7 0x1
+#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x0088 0x02F8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 0x0088 0x02F8 0x0590 0x1 0x0
+#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0
+#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x0088 0x02F8 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x0088 0x02F8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0088 0x02F8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x0088 0x02F8 0x0688 0x6 0x1
+#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 0x0088 0x02F8 0x0648 0x7 0x1
+#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x008C 0x02FC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN 0x008C 0x02FC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 0x008C 0x02FC 0x060C 0x3 0x1
+#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x008C 0x02FC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x008C 0x02FC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x008C 0x02FC 0x068C 0x6 0x1
+#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 0x008C 0x02FC 0x0644 0x7 0x1
+#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x0090 0x0300 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD 0x0090 0x0300 0x06E8 0x1 0x0
+#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 0x0090 0x0300 0x062C 0x3 0x1
+#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x0090 0x0300 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0090 0x0300 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x0090 0x0300 0x0690 0x6 0x1
+#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 0x0090 0x0300 0x0640 0x7 0x1
+#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0094 0x0304 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 0x0094 0x0304 0x05AC 0x1 0x0
+#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 0x0094 0x0304 0x0610 0x3 0x0
+#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x0094 0x0304 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x0094 0x0304 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x0094 0x0304 0x0694 0x6 0x1
+#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 0x0094 0x0304 0x0678 0x7 0x1
+#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x0098 0x0308 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 0x0098 0x0308 0x05B0 0x1 0x0
+#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 0x0098 0x0308 0x0630 0x3 0x0
+#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x0098 0x0308 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x0098 0x0308 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x0098 0x0308 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 0x0098 0x0308 0x0680 0x7 0x1
+#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x009C 0x030C 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 0x009C 0x030C 0x05B4 0x1 0x0
+#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x009C 0x030C 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x009C 0x030C 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x009C 0x030C 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 0x009C 0x030C 0x0684 0x7 0x1
+#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x00A0 0x0310 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 0x00A0 0x0310 0x05B8 0x1 0x0
+#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER 0x00A0 0x0310 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x00A0 0x0310 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x00A0 0x0310 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_GDSP__LCD_BUSY 0x00A0 0x0310 0x0634 0x6 0x1
+#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 0x00A0 0x0310 0x067C 0x7 0x1
+#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x00A4 0x0314 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x00A4 0x0314 0x0570 0x3 0x1
+#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x00A4 0x0314 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x00A4 0x0314 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_BDR0__LCD_CS 0x00A4 0x0314 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 0x00A4 0x0314 0x0654 0x7 0x1
+#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x00A8 0x0318 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN 0x00A8 0x0318 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1
+#define MX7D_PAD_EPDC_BDR1__EIM_AD8 0x00A8 0x0318 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x00A8 0x0318 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x00A8 0x0318 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 0x00A8 0x0318 0x0650 0x7 0x1
+#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00AC 0x031C 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA 0x00AC 0x031C 0x05CC 0x1 0x0
+#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x00AC 0x031C 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00AC 0x031C 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x00AC 0x031C 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 0x00AC 0x031C 0x0664 0x7 0x1
+#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00B0 0x0320 0x0580 0x0 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB 0x00B0 0x0320 0x05D0 0x1 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 0x00B0 0x0320 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x00B0 0x0320 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x00B0 0x0320 0x0698 0x6 0x1
+#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 0x00B0 0x0320 0x0668 0x7 0x1
+#define MX7D_PAD_LCD_CLK__LCD_CLK 0x00B4 0x0324 0x0000 0x0 0x0
+#define MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x00B4 0x0324 0x0558 0x1 0x0
+#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_CLK__CSI_DATA16 0x00B4 0x0324 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x00B4 0x0324 0x06FC 0x4 0x0
+#define MX7D_PAD_LCD_CLK__UART2_DTE_TX 0x00B4 0x0324 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_CLK__GPIO3_IO0 0x00B4 0x0324 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x00B8 0x0328 0x0000 0x0 0x0
+#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x00B8 0x0328 0x055C 0x1 0x0
+#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 0x00B8 0x0328 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00B8 0x0328 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX 0x00B8 0x0328 0x06FC 0x4 0x1
+#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 0x00B8 0x0328 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x00BC 0x032C 0x0000 0x0 0x0
+#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x00BC 0x032C 0x0554 0x1 0x0
+#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 0x00BC 0x032C 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x00BC 0x032C 0x06F8 0x4 0x0
+#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS 0x00BC 0x032C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00BC 0x032C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2
+#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 0x00C0 0x0330 0x0560 0x1 0x0
+#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 0x00C0 0x0330 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00C0 0x0330 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS 0x00C0 0x0330 0x06F8 0x4 0x1
+#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00C0 0x0330 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_RESET__LCD_RESET 0x00C4 0x0334 0x0000 0x0 0x0
+#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 0x00C4 0x0334 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_RESET__CSI_FIELD 0x00C4 0x0334 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_RESET__EIM_DTACK_B 0x00C4 0x0334 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00C4 0x0334 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2
+#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 0x00C8 0x0338 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA00__CSI_DATA20 0x00C8 0x0338 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA00__EIM_DATA0 0x00C8 0x0338 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00C8 0x0338 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 0x00C8 0x0338 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2
+#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 0x00CC 0x033C 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA01__CSI_DATA21 0x00CC 0x033C 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA01__EIM_DATA1 0x00CC 0x033C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x00CC 0x033C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 0x00CC 0x033C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2
+#define MX7D_PAD_LCD_DATA02__GPT1_CLK 0x00D0 0x0340 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA02__CSI_DATA22 0x00D0 0x0340 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA02__EIM_DATA2 0x00D0 0x0340 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x00D0 0x0340 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 0x00D0 0x0340 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2
+#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 0x00D4 0x0344 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA03__CSI_DATA23 0x00D4 0x0344 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA03__EIM_DATA3 0x00D4 0x0344 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x00D4 0x0344 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 0x00D4 0x0344 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2
+#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 0x00D8 0x0348 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x00D8 0x0348 0x0520 0x3 0x0
+#define MX7D_PAD_LCD_DATA04__EIM_DATA4 0x00D8 0x0348 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 0x00D8 0x0348 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 0x00D8 0x0348 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2
+#define MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x00DC 0x034C 0x0518 0x3 0x0
+#define MX7D_PAD_LCD_DATA05__EIM_DATA5 0x00DC 0x034C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x00DC 0x034C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 0x00DC 0x034C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2
+#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x00E0 0x0350 0x051C 0x3 0x0
+#define MX7D_PAD_LCD_DATA06__EIM_DATA6 0x00E0 0x0350 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 0x00E0 0x0350 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 0x00E0 0x0350 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2
+#define MX7D_PAD_LCD_DATA07__CSI_MCLK 0x00E4 0x0354 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA07__EIM_DATA7 0x00E4 0x0354 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x00E4 0x0354 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 0x00E4 0x0354 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2
+#define MX7D_PAD_LCD_DATA08__CSI_DATA9 0x00E8 0x0358 0x0514 0x3 0x0
+#define MX7D_PAD_LCD_DATA08__EIM_DATA8 0x00E8 0x0358 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 0x00E8 0x0358 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 0x00E8 0x0358 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2
+#define MX7D_PAD_LCD_DATA09__CSI_DATA8 0x00EC 0x035C 0x0510 0x3 0x0
+#define MX7D_PAD_LCD_DATA09__EIM_DATA9 0x00EC 0x035C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x00EC 0x035C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 0x00EC 0x035C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2
+#define MX7D_PAD_LCD_DATA10__CSI_DATA7 0x00F0 0x0360 0x050C 0x3 0x0
+#define MX7D_PAD_LCD_DATA10__EIM_DATA10 0x00F0 0x0360 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 0x00F0 0x0360 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x00F0 0x0360 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2
+#define MX7D_PAD_LCD_DATA11__CSI_DATA6 0x00F4 0x0364 0x0508 0x3 0x0
+#define MX7D_PAD_LCD_DATA11__EIM_DATA11 0x00F4 0x0364 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 0x00F4 0x0364 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x00F4 0x0364 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2
+#define MX7D_PAD_LCD_DATA12__CSI_DATA5 0x00F8 0x0368 0x0504 0x3 0x0
+#define MX7D_PAD_LCD_DATA12__EIM_DATA12 0x00F8 0x0368 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x00F8 0x0368 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x00F8 0x0368 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA13__LCD_DATA13 0x00FC 0x036C 0x066C 0x0 0x1
+#define MX7D_PAD_LCD_DATA13__CSI_DATA4 0x00FC 0x036C 0x0500 0x3 0x0
+#define MX7D_PAD_LCD_DATA13__EIM_DATA13 0x00FC 0x036C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x00FC 0x036C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x00FC 0x036C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA14__LCD_DATA14 0x0100 0x0370 0x0670 0x0 0x1
+#define MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0100 0x0370 0x04FC 0x3 0x0
+#define MX7D_PAD_LCD_DATA14__EIM_DATA14 0x0100 0x0370 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 0x0100 0x0370 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0100 0x0370 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA15__LCD_DATA15 0x0104 0x0374 0x0674 0x0 0x1
+#define MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0104 0x0374 0x04F8 0x3 0x0
+#define MX7D_PAD_LCD_DATA15__EIM_DATA15 0x0104 0x0374 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0104 0x0374 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0104 0x0374 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2
+#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 0x0108 0x0378 0x0594 0x1 0x0
+#define MX7D_PAD_LCD_DATA16__CSI_DATA1 0x0108 0x0378 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA16__EIM_CRE 0x0108 0x0378 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 0x0108 0x0378 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 0x0108 0x0378 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2
+#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 0x010C 0x037C 0x0598 0x1 0x0
+#define MX7D_PAD_LCD_DATA17__CSI_DATA0 0x010C 0x037C 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN 0x010C 0x037C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x010C 0x037C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 0x010C 0x037C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2
+#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 0x0110 0x0380 0x059C 0x1 0x0
+#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA18__CSI_DATA15 0x0110 0x0380 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA18__EIM_CS2_B 0x0110 0x0380 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x0110 0x0380 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 0x0110 0x0380 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA19__EIM_CS3_B 0x0114 0x0384 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0114 0x0384 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 0x0114 0x0384 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2
+#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 0x0114 0x0384 0x05A0 0x1 0x0
+#define MX7D_PAD_LCD_DATA19__CSI_DATA14 0x0114 0x0384 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x0118 0x0388 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x0118 0x0388 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA20__I2C3_SCL 0x0118 0x0388 0x05E4 0x6 0x1
+#define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2
+#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 0x0118 0x0388 0x05BC 0x1 0x0
+#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA20__CSI_DATA13 0x0118 0x0388 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2
+#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 0x011C 0x038C 0x05C0 0x1 0x0
+#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA21__CSI_DATA12 0x011C 0x038C 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x011C 0x038C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x011C 0x038C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA21__I2C3_SDA 0x011C 0x038C 0x05E8 0x6 0x1
+#define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2
+#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 0x0120 0x0390 0x05C4 0x1 0x0
+#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA22__CSI_DATA11 0x0120 0x0390 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x0120 0x0390 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0120 0x0390 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA22__I2C4_SCL 0x0120 0x0390 0x05EC 0x6 0x1
+#define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2
+#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 0x0124 0x0394 0x05C8 0x1 0x0
+#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA23__CSI_DATA10 0x0124 0x0394 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1
+#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0
+#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0
+#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0
+#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0
+#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 0x0128 0x0398 0x0000 0x3 0x0
+#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN 0x0128 0x0398 0x0000 0x4 0x0
+#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x0128 0x0398 0x0000 0x5 0x0
+#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO 0x0128 0x0398 0x0000 0x6 0x0
+#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x012C 0x039C 0x0000 0x0 0x0
+#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x012C 0x039C 0x06F4 0x0 0x1
+#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x012C 0x039C 0x05D8 0x1 0x0
+#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0
+#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 0x012C 0x039C 0x0000 0x3 0x0
+#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0
+#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0
+#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0
+#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2
+#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0
+#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0
+#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0
+#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0
+#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0
+#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0
+#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0
+#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0
+#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3
+#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0
+#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0
+#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0
+#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT 0x0134 0x03A4 0x0000 0x4 0x0
+#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x0134 0x03A4 0x0000 0x5 0x0
+#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC 0x0134 0x03A4 0x0000 0x6 0x0
+#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2
+#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x0138 0x03A8 0x0000 0x0 0x0
+#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC 0x0138 0x03A8 0x072C 0x1 0x0
+#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0
+#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO 0x0138 0x03A8 0x0528 0x3 0x0
+#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN 0x0138 0x03A8 0x0000 0x4 0x0
+#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x0138 0x03A8 0x0000 0x5 0x0
+#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL 0x0138 0x03A8 0x0000 0x6 0x0
+#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x013C 0x03AC 0x0000 0x0 0x0
+#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x013C 0x03AC 0x0704 0x0 0x3
+#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR 0x013C 0x03AC 0x0000 0x1 0x0
+#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0
+#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI 0x013C 0x03AC 0x052C 0x3 0x0
+#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0
+#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0
+#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0
+#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2
+#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0
+#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0
+#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0
+#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK 0x0140 0x03B0 0x0000 0x3 0x0
+#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN 0x0140 0x03B0 0x0000 0x4 0x0
+#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x0140 0x03B0 0x0000 0x5 0x0
+#define MX7D_PAD_UART3_RTS_B__SD3_LCTL 0x0140 0x03B0 0x0000 0x6 0x0
+#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x0144 0x03B4 0x0000 0x0 0x0
+#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x0144 0x03B4 0x0700 0x0 0x3
+#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR 0x0144 0x03B4 0x0000 0x1 0x0
+#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0
+#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 0x0144 0x03B4 0x0530 0x3 0x0
+#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT 0x0144 0x03B4 0x0000 0x4 0x0
+#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x0144 0x03B4 0x0000 0x5 0x0
+#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT 0x0144 0x03B4 0x0000 0x6 0x0
+#define MX7D_PAD_I2C1_SCL__I2C1_SCL 0x0148 0x03B8 0x05D4 0x0 0x1
+#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x0148 0x03B8 0x0000 0x1 0x0
+#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS 0x0148 0x03B8 0x0708 0x1 0x0
+#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1
+#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x0148 0x03B8 0x0548 0x3 0x0
+#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x0148 0x03B8 0x0000 0x5 0x0
+#define MX7D_PAD_I2C1_SCL__SD2_VSELECT 0x0148 0x03B8 0x0000 0x6 0x0
+#define MX7D_PAD_I2C1_SDA__I2C1_SDA 0x014C 0x03BC 0x05D8 0x0 0x1
+#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x014C 0x03BC 0x0708 0x1 0x1
+#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS 0x014C 0x03BC 0x0000 0x1 0x0
+#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0
+#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x014C 0x03BC 0x054C 0x3 0x0
+#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 0x014C 0x03BC 0x0564 0x4 0x1
+#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x014C 0x03BC 0x0000 0x5 0x0
+#define MX7D_PAD_I2C1_SDA__SD3_VSELECT 0x014C 0x03BC 0x0000 0x6 0x0
+#define MX7D_PAD_I2C2_SCL__I2C2_SCL 0x0150 0x03C0 0x05DC 0x0 0x1
+#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x0150 0x03C0 0x070C 0x1 0x0
+#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX 0x0150 0x03C0 0x0000 0x1 0x0
+#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0
+#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x0150 0x03C0 0x0544 0x3 0x0
+#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2
+#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x0150 0x03C0 0x0000 0x5 0x0
+#define MX7D_PAD_I2C2_SCL__SD3_CD_B 0x0150 0x03C0 0x0738 0x6 0x1
+#define MX7D_PAD_I2C2_SDA__I2C2_SDA 0x0154 0x03C4 0x05E0 0x0 0x1
+#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x0154 0x03C4 0x0000 0x1 0x0
+#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX 0x0154 0x03C4 0x070C 0x1 0x1
+#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0
+#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 0x0154 0x03C4 0x0550 0x3 0x0
+#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 0x0154 0x03C4 0x0000 0x4 0x0
+#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x0154 0x03C4 0x0000 0x5 0x0
+#define MX7D_PAD_I2C2_SDA__SD3_WP 0x0154 0x03C4 0x073C 0x6 0x1
+#define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2
+#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x0158 0x03C8 0x0000 0x1 0x0
+#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS 0x0158 0x03C8 0x0710 0x1 0x0
+#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1
+#define MX7D_PAD_I2C3_SCL__CSI_VSYNC 0x0158 0x03C8 0x0520 0x3 0x1
+#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 0x0158 0x03C8 0x06D8 0x4 0x1
+#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x0158 0x03C8 0x0000 0x5 0x0
+#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 0x0158 0x03C8 0x0000 0x6 0x0
+#define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2
+#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x015C 0x03CC 0x0710 0x1 0x1
+#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS 0x015C 0x03CC 0x0000 0x1 0x0
+#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0
+#define MX7D_PAD_I2C3_SDA__CSI_HSYNC 0x015C 0x03CC 0x0518 0x3 0x1
+#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 0x015C 0x03CC 0x06DC 0x4 0x1
+#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x015C 0x03CC 0x0000 0x5 0x0
+#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 0x015C 0x03CC 0x0000 0x6 0x0
+#define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2
+#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x0160 0x03D0 0x0714 0x1 0x0
+#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX 0x0160 0x03D0 0x0000 0x1 0x0
+#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0
+#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK 0x0160 0x03D0 0x051C 0x3 0x1
+#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID 0x0160 0x03D0 0x0734 0x4 0x1
+#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x0160 0x03D0 0x0000 0x5 0x0
+#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 0x0160 0x03D0 0x0000 0x6 0x0
+#define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2
+#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x0164 0x03D4 0x0000 0x1 0x0
+#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX 0x0164 0x03D4 0x0714 0x1 0x1
+#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0
+#define MX7D_PAD_I2C4_SDA__CSI_MCLK 0x0164 0x03D4 0x0000 0x3 0x0
+#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID 0x0164 0x03D4 0x0730 0x4 0x1
+#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x0164 0x03D4 0x0000 0x5 0x0
+#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 0x0164 0x03D4 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0168 0x03D8 0x0524 0x0 0x1
+#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2
+#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x0168 0x03D8 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 0x0168 0x03D8 0x04F8 0x3 0x1
+#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x0168 0x03D8 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM 0x0168 0x03D8 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x016C 0x03DC 0x052C 0x0 0x1
+#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x016C 0x03DC 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x016C 0x03DC 0x071C 0x1 0x3
+#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 0x016C 0x03DC 0x04FC 0x3 0x1
+#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x016C 0x03DC 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT 0x016C 0x03DC 0x0580 0x6 0x1
+#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0170 0x03E0 0x0528 0x0 0x1
+#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2
+#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS 0x0170 0x03E0 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 0x0170 0x03E0 0x0500 0x3 0x1
+#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x0170 0x03E0 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ 0x0170 0x03E0 0x057C 0x6 0x0
+#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0174 0x03E4 0x0530 0x0 0x1
+#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x0174 0x03E4 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS 0x0174 0x03E4 0x0718 0x1 0x3
+#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 0x0174 0x03E4 0x0504 0x3 0x1
+#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x0174 0x03E4 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 0x0174 0x03E4 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0178 0x03E8 0x0534 0x0 0x0
+#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2
+#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x0178 0x03E8 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 0x0178 0x03E8 0x0508 0x3 0x1
+#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2
+#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x0178 0x03E8 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 0x0178 0x03E8 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x017C 0x03EC 0x053C 0x0 0x0
+#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x017C 0x03EC 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x017C 0x03EC 0x0724 0x1 0x3
+#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 0x017C 0x03EC 0x050C 0x3 0x1
+#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2
+#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x017C 0x03EC 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 0x017C 0x03EC 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x0180 0x03F0 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 0x0180 0x03F0 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0180 0x03F0 0x0538 0x0 0x0
+#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2
+#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x0180 0x03F0 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 0x0180 0x03F0 0x0510 0x3 0x1
+#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2
+#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0184 0x03F4 0x0540 0x0 0x0
+#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x0184 0x03F4 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x0184 0x03F4 0x0720 0x1 0x3
+#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 0x0184 0x03F4 0x0514 0x3 0x1
+#define MX7D_PAD_ECSPI2_SS0__LCD_RESET 0x0184 0x03F4 0x0000 0x4 0x0
+#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x0184 0x03F4 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE 0x0184 0x03F4 0x0000 0x6 0x0
+#define MX7D_PAD_SD1_CD_B__SD1_CD_B 0x0188 0x03F8 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4
+#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x0188 0x03F8 0x0558 0x3 0x1
+#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 0x0188 0x03F8 0x0584 0x4 0x1
+#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x0188 0x03F8 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 0x0188 0x03F8 0x0000 0x6 0x0
+#define MX7D_PAD_SD1_WP__SD1_WP 0x018C 0x03FC 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5
+#define MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x018C 0x03FC 0x055C 0x3 0x1
+#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 0x018C 0x03FC 0x0588 0x4 0x1
+#define MX7D_PAD_SD1_WP__GPIO5_IO1 0x018C 0x03FC 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_WP__CCM_CLKO2 0x018C 0x03FC 0x0000 0x6 0x0
+#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B 0x0190 0x0400 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK 0x0190 0x0400 0x0000 0x1 0x0
+#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4
+#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x0190 0x0400 0x0554 0x3 0x1
+#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 0x0190 0x0400 0x058C 0x4 0x1
+#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x0190 0x0400 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_CLK__SD1_CLK 0x0194 0x0404 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC 0x0194 0x0404 0x06CC 0x1 0x1
+#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5
+#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 0x0194 0x0404 0x0560 0x3 0x1
+#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 0x0194 0x0404 0x0590 0x4 0x1
+#define MX7D_PAD_SD1_CLK__GPIO5_IO3 0x0194 0x0404 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_CMD__SD1_CMD 0x0198 0x0408 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK 0x0198 0x0408 0x06C4 0x1 0x1
+#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 0x0198 0x0408 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 0x0198 0x0408 0x05AC 0x4 0x1
+#define MX7D_PAD_SD1_CMD__GPIO5_IO4 0x0198 0x0408 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA0__SD1_DATA0 0x019C 0x040C 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 0x019C 0x040C 0x06C8 0x1 0x1
+#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4
+#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 0x019C 0x040C 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 0x019C 0x040C 0x05B0 0x4 0x1
+#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x019C 0x040C 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 0x019C 0x040C 0x04E4 0x6 0x1
+#define MX7D_PAD_SD1_DATA1__SD1_DATA1 0x01A0 0x0410 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x01A0 0x0410 0x06D0 0x1 0x1
+#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5
+#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 0x01A0 0x0410 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 0x01A0 0x0410 0x05B4 0x4 0x1
+#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x01A0 0x0410 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 0x01A0 0x0410 0x04E8 0x6 0x1
+#define MX7D_PAD_SD1_DATA2__SD1_DATA2 0x01A4 0x0414 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x01A4 0x0414 0x06D4 0x1 0x1
+#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4
+#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY 0x01A4 0x0414 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 0x01A4 0x0414 0x05B8 0x4 0x1
+#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 0x01A4 0x0414 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 0x01A4 0x0414 0x04EC 0x6 0x1
+#define MX7D_PAD_SD1_DATA3__SD1_DATA3 0x01A8 0x0418 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x01A8 0x0418 0x0000 0x1 0x0
+#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5
+#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 0x01A8 0x0418 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA 0x01A8 0x0418 0x05A4 0x4 0x1
+#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 0x01A8 0x0418 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 0x01A8 0x0418 0x04F0 0x6 0x1
+#define MX7D_PAD_SD2_CD_B__SD2_CD_B 0x01AC 0x041C 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2
+#define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2
+#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 0x01AC 0x041C 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB 0x01AC 0x041C 0x05A8 0x4 0x1
+#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x01AC 0x041C 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2
+#define MX7D_PAD_SD2_WP__SD2_WP 0x01B0 0x0420 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_WP__ENET1_MDC 0x01B0 0x0420 0x0000 0x1 0x0
+#define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_WP__ECSPI3_SS3 0x01B0 0x0420 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2
+#define MX7D_PAD_SD2_WP__GPIO5_IO10 0x01B0 0x0420 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2
+#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B 0x01B4 0x0424 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK 0x01B4 0x0424 0x0000 0x1 0x0
+#define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY 0x01B4 0x0424 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2
+#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x01B4 0x0424 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_CLK__SD2_CLK 0x01B8 0x0428 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC 0x01B8 0x0428 0x06B8 0x1 0x0
+#define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_CLK__GPT4_CLK 0x01B8 0x0428 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_CLK__GPIO5_IO12 0x01B8 0x0428 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_CMD__SD2_CMD 0x01BC 0x042C 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK 0x01BC 0x042C 0x06B0 0x1 0x0
+#define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 0x01BC 0x042C 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD 0x01BC 0x042C 0x06EC 0x4 0x1
+#define MX7D_PAD_SD2_CMD__GPIO5_IO13 0x01BC 0x042C 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_DATA0__SD2_DATA0 0x01C0 0x0430 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 0x01C0 0x0430 0x06B4 0x1 0x0
+#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2
+#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 0x01C0 0x0430 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK 0x01C0 0x0430 0x0000 0x4 0x0
+#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x01C0 0x0430 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_DATA1__SD2_DATA1 0x01C4 0x0434 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x01C4 0x0434 0x06BC 0x1 0x0
+#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3
+#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 0x01C4 0x0434 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B 0x01C4 0x0434 0x0000 0x4 0x0
+#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x01C4 0x0434 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_DATA2__SD2_DATA2 0x01C8 0x0438 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x01C8 0x0438 0x06C0 0x1 0x0
+#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2
+#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 0x01C8 0x0438 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN 0x01C8 0x0438 0x0000 0x4 0x0
+#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x01C8 0x0438 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_DATA3__SD2_DATA3 0x01CC 0x043C 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 0x01CC 0x043C 0x0000 0x1 0x0
+#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3
+#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 0x01CC 0x043C 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD 0x01CC 0x043C 0x06E8 0x4 0x1
+#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x01CC 0x043C 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_CLK__SD3_CLK 0x01D0 0x0440 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_CLK__NAND_CLE 0x01D0 0x0440 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2
+#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2
+#define MX7D_PAD_SD3_CLK__GPT3_CLK 0x01D0 0x0440 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_CLK__GPIO6_IO0 0x01D0 0x0440 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_CMD__SD3_CMD 0x01D4 0x0444 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_CMD__NAND_ALE 0x01D4 0x0444 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2
+#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2
+#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 0x01D4 0x0444 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_CMD__GPIO6_IO1 0x01D4 0x0444 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA0__SD3_DATA0 0x01D8 0x0448 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA0__NAND_DATA00 0x01D8 0x0448 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2
+#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2
+#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 0x01D8 0x0448 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x01D8 0x0448 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA1__SD3_DATA1 0x01DC 0x044C 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA1__NAND_DATA01 0x01DC 0x044C 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2
+#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2
+#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 0x01DC 0x044C 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x01DC 0x044C 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA2__SD3_DATA2 0x01E0 0x0450 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA2__NAND_DATA02 0x01E0 0x0450 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3
+#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2
+#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 0x01E0 0x0450 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x01E0 0x0450 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA3__SD3_DATA3 0x01E4 0x0454 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA3__NAND_DATA03 0x01E4 0x0454 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3
+#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 0x01E4 0x0454 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 0x01E4 0x0454 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x01E4 0x0454 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA4__SD3_DATA4 0x01E8 0x0458 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA4__NAND_DATA04 0x01E8 0x0458 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x01E8 0x0458 0x0704 0x3 0x4
+#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX 0x01E8 0x0458 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2
+#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x01E8 0x0458 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA5__SD3_DATA5 0x01EC 0x045C 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA5__NAND_DATA05 0x01EC 0x045C 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x01EC 0x045C 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX 0x01EC 0x045C 0x0704 0x3 0x5
+#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x01EC 0x045C 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x01EC 0x045C 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA6__SD3_DATA6 0x01F0 0x0460 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA6__NAND_DATA06 0x01F0 0x0460 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2
+#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x01F0 0x0460 0x0700 0x3 0x4
+#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS 0x01F0 0x0460 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x01F0 0x0460 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x01F0 0x0460 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA7__SD3_DATA7 0x01F4 0x0464 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA7__NAND_DATA07 0x01F4 0x0464 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2
+#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x01F4 0x0464 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS 0x01F4 0x0464 0x0700 0x3 0x5
+#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2
+#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x01F4 0x0464 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_STROBE__SD3_STROBE 0x01F8 0x0468 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_STROBE__NAND_RE_B 0x01F8 0x0468 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x01F8 0x0468 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x01FC 0x046C 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x01FC 0x046C 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0
+#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK 0x01FC 0x046C 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x01FC 0x046C 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x0200 0x0470 0x06A0 0x0 0x0
+#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x0200 0x0470 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2
+#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x0200 0x0470 0x04DC 0x3 0x3
+#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x0200 0x0470 0x06E4 0x4 0x1
+#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x0200 0x0470 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET 0x0200 0x0470 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x0204 0x0474 0x06A8 0x0 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x0204 0x0474 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3
+#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x0204 0x0474 0x0000 0x3 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x0204 0x0474 0x0000 0x4 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x0204 0x0474 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET 0x0204 0x0474 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x0208 0x0478 0x06AC 0x0 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS 0x0208 0x0478 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2
+#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x0208 0x0478 0x04E0 0x3 0x3
+#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x0208 0x0478 0x0000 0x4 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x0208 0x0478 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT 0x0208 0x0478 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x020C 0x047C 0x0000 0x0 0x0
+#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x020C 0x047C 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3
+#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x020C 0x047C 0x0000 0x3 0x0
+#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x020C 0x047C 0x0000 0x4 0x0
+#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x020C 0x047C 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET 0x020C 0x047C 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x0210 0x0480 0x06A4 0x0 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B 0x0210 0x0480 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1
+#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x0210 0x0480 0x05EC 0x3 0x3
+#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x0210 0x0480 0x06E0 0x4 0x1
+#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x0210 0x0480 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0210 0x0480 0x0000 0x6 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 0x0210 0x0480 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x0214 0x0484 0x069C 0x0 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B 0x0214 0x0484 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1
+#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x0214 0x0484 0x05F0 0x3 0x3
+#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA 0x0214 0x0484 0x05CC 0x4 0x1
+#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x0214 0x0484 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0214 0x0484 0x0000 0x6 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 0x0214 0x0484 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x0218 0x0488 0x0000 0x0 0x0
+#define MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x0218 0x0488 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY 0x0218 0x0488 0x04F4 0x3 0x3
+#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB 0x0218 0x0488 0x05D0 0x4 0x1
+#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 0x0218 0x0488 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK 0x0218 0x0488 0x0000 0x7 0x0
+#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x021C 0x048C 0x06C0 0x0 0x1
+#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x021C 0x048C 0x0548 0x1 0x1
+#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4
+#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0
+#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS 0x021C 0x048C 0x0000 0x3 0x0
+#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x021C 0x048C 0x06F0 0x3 0x0
+#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 0x021C 0x048C 0x05BC 0x4 0x1
+#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x021C 0x048C 0x0000 0x5 0x0
+#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x0220 0x0490 0x06BC 0x0 0x1
+#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x0220 0x0490 0x054C 0x1 0x1
+#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0
+#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5
+#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS 0x0220 0x0490 0x06F0 0x3 0x1
+#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x0220 0x0490 0x0000 0x3 0x0
+#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 0x0220 0x0490 0x05C0 0x4 0x1
+#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x0220 0x0490 0x0000 0x5 0x0
+#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x0224 0x0494 0x06B4 0x0 0x1
+#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x0224 0x0494 0x0544 0x1 0x1
+#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0
+#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4
+#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS 0x0224 0x0494 0x0000 0x3 0x0
+#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2
+#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 0x0224 0x0494 0x05C4 0x4 0x1
+#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x0224 0x0494 0x0000 0x5 0x0
+#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 0x0224 0x0494 0x0610 0x6 0x1
+#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x0228 0x0498 0x0000 0x0 0x0
+#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 0x0228 0x0498 0x0550 0x1 0x1
+#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5
+#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0
+#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS 0x0228 0x0498 0x06F8 0x3 0x3
+#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x0228 0x0498 0x0000 0x3 0x0
+#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 0x0228 0x0498 0x05C8 0x4 0x1
+#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x0228 0x0498 0x0000 0x5 0x0
+#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 0x0228 0x0498 0x0630 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x022C 0x049C 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT 0x022C 0x049C 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4
+#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x022C 0x049C 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2
+#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 0x022C 0x049C 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x022C 0x049C 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 0x022C 0x049C 0x0620 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x0230 0x04A0 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT 0x0230 0x04A0 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4
+#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x0230 0x04A0 0x06F0 0x3 0x3
+#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS 0x0230 0x04A0 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 0x0230 0x04A0 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0230 0x04A0 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 0x0230 0x04A0 0x0600 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x0234 0x04A4 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x0234 0x04A4 0x04DC 0x1 0x4
+#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2
+#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX 0x0234 0x04A4 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 0x0234 0x04A4 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x0234 0x04A4 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 0x0234 0x04A4 0x061C 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x0238 0x04A8 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x0238 0x04A8 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x0238 0x04A8 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX 0x0238 0x04A8 0x06F4 0x3 0x3
+#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 0x0238 0x04A8 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x0238 0x04A8 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 0x0238 0x04A8 0x05FC 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x023C 0x04AC 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 0x023C 0x04AC 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x023C 0x04AC 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 0x023C 0x04AC 0x0618 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x0240 0x04B0 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x0240 0x04B0 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 0x0240 0x04B0 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0240 0x04B0 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 0x0240 0x04B0 0x0000 0x6 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x0244 0x04B4 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT 0x0244 0x04B4 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 0x0244 0x04B4 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0244 0x04B4 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 0x0244 0x04B4 0x0614 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x0248 0x04B8 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT 0x0248 0x04B8 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 0x0248 0x04B8 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0248 0x04B8 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 0x0248 0x04B8 0x05F4 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x024C 0x04BC 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX 0x024C 0x04BC 0x04E0 0x1 0x4
+#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x024C 0x04BC 0x05EC 0x3 0x4
+#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED 0x024C 0x04BC 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x024C 0x04BC 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x0250 0x04C0 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX 0x0250 0x04C0 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x0250 0x04C0 0x05F0 0x3 0x4
+#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ 0x0250 0x04C0 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x025C 0x04CC 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2
+#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1
+#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 0x025C 0x04CC 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ 0x025C 0x04CC 0x057C 0x4 0x1
+#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x025C 0x04CC 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2
+#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 0x025C 0x04CC 0x0000 0x7 0x0
+#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x0260 0x04D0 0x056C 0x0 0x0
+#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B 0x0260 0x04D0 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1
+#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK 0x0260 0x04D0 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE 0x0260 0x04D0 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x0260 0x04D0 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2
+#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 0x0260 0x04D0 0x0000 0x7 0x0
+#define MX7D_PAD_ENET1_CRS__ENET1_CRS 0x0264 0x04D4 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB 0x0264 0x04D4 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1
+#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 0x0264 0x04D4 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 0x0264 0x04D4 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0264 0x04D4 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2
+#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 0x0264 0x04D4 0x0000 0x7 0x0
+#define MX7D_PAD_ENET1_COL__ENET1_COL 0x0268 0x04D8 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x0268 0x04D8 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 0x0268 0x04D8 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 0x0268 0x04D8 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_COL__GPIO7_IO15 0x0268 0x04D8 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2
+#define MX7D_PAD_ENET1_COL__CSU_INT_DEB 0x0268 0x04D8 0x0000 0x7 0x0
+
+#endif /* __DTS_IMX7D_PINFUNC_H */
diff --git a/arch/arm/dts/ls1021a-iot-duart.dts b/arch/arm/dts/ls1021a-iot-duart.dts
new file mode 100644
index 0000000..62e4c67
--- /dev/null
+++ b/arch/arm/dts/ls1021a-iot-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Freescale ls1021a IOT board device tree source
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a-iot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart0;
+ };
+};
diff --git a/arch/arm/dts/ls1021a-iot.dtsi b/arch/arm/dts/ls1021a-iot.dtsi
new file mode 100644
index 0000000..1817c62
--- /dev/null
+++ b/arch/arm/dts/ls1021a-iot.dtsi
@@ -0,0 +1,103 @@
+/*
+ * Freescale ls1021a IOT board device tree source
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include "ls1021a.dtsi"
+
+/ {
+ model = "LS1021A IOT Board";
+
+ aliases {
+ enet2_rgmii_phy = &rgmii_phy1;
+ enet0_sgmii_phy = &sgmii_phy2;
+ enet1_sgmii_phy = &sgmii_phy0;
+ spi0 = &qspi;
+ spi1 = &dspi1;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: n25q128a13@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: at26df081a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR Flash on board */
+ ranges = <0x0 0x0 0x60000000 0x08000000>;
+ status = "okay";
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&mdio0 {
+ sgmii_phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ rgmii_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ sgmii_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ tbi1: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 119b1af..37be169 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -176,6 +176,7 @@
#size-cells = <0>;
reg = <0x1550000 0x10000>,
<0x40000000 0x4000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <2>;
big-endian;
status = "disabled";
diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts
index 1c9ddf9..bdc7b98 100644
--- a/arch/arm/dts/rk3036-sdk.dts
+++ b/arch/arm/dts/rk3036-sdk.dts
@@ -16,10 +16,25 @@
stdout-path = &uart2;
};
- usb_control {
- compatible = "rockchip,rk3036-usb-control";
- host_drv_gpio = <&gpio2 23 GPIO_ACTIVE_LOW>;
- otg_drv_gpio = <&gpio0 26 GPIO_ACTIVE_LOW>;
+ vcc5v0_otg: vcc5v0-otg-drv {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_otg";
+ gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_host: vcc5v0-host-drv {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
};
};
@@ -42,3 +57,17 @@
&usb_otg {
status = "okay";
};
+
+&pinctrl {
+ usb_otg {
+ otg_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb_host {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts
index 3e1ee58..3f03e13 100644
--- a/arch/arm/dts/rk3288-evb.dts
+++ b/arch/arm/dts/rk3288-evb.dts
@@ -17,7 +17,6 @@
};
&dmc {
- rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
@@ -25,8 +24,6 @@
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x2>;
- /* Add a dummy value to cause of-platdata think this is bytes */
- rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>;
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
};
diff --git a/arch/arm/dts/rk3288-fennec.dts b/arch/arm/dts/rk3288-fennec.dts
index 36e9f3d..66ddf8d 100644
--- a/arch/arm/dts/rk3288-fennec.dts
+++ b/arch/arm/dts/rk3288-fennec.dts
@@ -17,7 +17,6 @@
};
&dmc {
- rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
@@ -25,8 +24,6 @@
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x2>;
- /* Add a dummy value to cause of-platdata think this is bytes */
- rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>;
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
};
diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts
index 3176d50..97568a3 100644
--- a/arch/arm/dts/rk3288-firefly.dts
+++ b/arch/arm/dts/rk3288-firefly.dts
@@ -22,7 +22,6 @@
};
&dmc {
- rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -31,7 +30,6 @@
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
/* Add a dummy value to cause of-platdata think this is bytes */
- rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
diff --git a/arch/arm/dts/rk3288-jerry.dts b/arch/arm/dts/rk3288-jerry.dts
deleted file mode 100644
index 2aa3b9f..0000000
--- a/arch/arm/dts/rk3288-jerry.dts
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Google Veyron Jerry Rev 3+ board device tree source
- *
- * Copyright 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-/dts-v1/;
-#include "rk3288-veyron-chromebook.dtsi"
-#include "cros-ec-sbs.dtsi"
-
-/ {
- model = "Google Jerry";
- compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
- "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
- "google,veyron-jerry-rev3", "google,veyron-jerry",
- "google,veyron", "rockchip,rk3288";
-
- chosen {
- stdout-path = &uart2;
- };
-
- panel_regulator: panel-regualtor {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_enable_h>;
- regulator-name = "panel_regulator";
- vin-supply = <&vcc33_sys>;
- };
-
- vcc18_lcd: vcc18-lcd {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&avdd_1v8_disp_en>;
- regulator-name = "vcc18_lcd";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc18_wl>;
- };
-
- backlight_regulator: backlight-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bl_pwr_en>;
- regulator-name = "backlight_regulator";
- vin-supply = <&vcc33_sys>;
- startup-delay-us = <15000>;
- };
-};
-
-&gpio_keys {
- power {
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
- };
-};
-
-&backlight {
- power-supply = <&backlight_regulator>;
-};
-
-&panel {
- power-supply= <&panel_regulator>;
-};
-
-&rk808 {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
- dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
- <&gpio7 15 GPIO_ACTIVE_HIGH>;
-
- regulators {
- mic_vcc: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "mic_vcc";
- regulator-suspend-mem-disabled;
- };
- };
-};
-
-&sdmmc {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
- &sdmmc_bus4>;
- disable-wp;
-};
-
-&vcc_5v {
- enable-active-high;
- gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&drv_5v>;
-};
-
-&vcc50_hdmi {
- enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc50_hdmi_en>;
-};
-
-&vopb {
- /* Disable this so that we use vopl */
- status = "disabled";
-};
-
-&edp {
- pinctrl-names = "default";
- pinctrl-0 = <&edp_hpd>;
-};
-
-&pinctrl {
- backlight {
- bl_pwr_en: bl_pwr_en {
- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- buck-5v {
- drv_5v: drv-5v {
- rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- edp {
- edp_hpd: edp_hpd {
- rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
- };
- };
-
- emmc {
- /* Make sure eMMC is not in reset */
- emmc_deassert_reset: emmc-deassert-reset {
- rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hdmi {
- vcc50_hdmi_en: vcc50-hdmi-en {
- rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- lcd {
- lcd_enable_h: lcd-en {
- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- avdd_1v8_disp_en: avdd-1v8-disp-en {
- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- dvs_1: dvs-1 {
- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- dvs_2: dvs-2 {
- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-};
-
-&i2c4 {
- status = "okay";
-
- /*
- * Trackpad pin control is shared between Elan and Synaptics devices
- * so we have to pull it up to the bus level.
- */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_xfer &trackpad_int>;
-
- trackpad@15 {
- compatible = "elan,i2c_touchpad";
- interrupt-parent = <&gpio7>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- /*
- * Remove the inherited pinctrl settings to avoid clashing
- * with bus-wide ones.
- */
- /delete-property/pinctrl-names;
- /delete-property/pinctrl-0;
- reg = <0x15>;
- vcc-supply = <&vcc33_io>;
- wakeup-source;
- };
-
- trackpad@2c {
- compatible = "hid-over-i2c";
- interrupt-parent = <&gpio7>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- reg = <0x2c>;
- hid-descr-addr = <0x0020>;
- vcc-supply = <&vcc33_io>;
- wakeup-source;
- };
-};
diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts
index c741082..9083028 100644
--- a/arch/arm/dts/rk3288-miniarm.dts
+++ b/arch/arm/dts/rk3288-miniarm.dts
@@ -17,7 +17,6 @@
};
&dmc {
- rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -25,8 +24,6 @@
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
- /* Add a dummy value to cause of-platdata think this is bytes */
- rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi
index b889875..ceb4e2b 100644
--- a/arch/arm/dts/rk3288-miniarm.dtsi
+++ b/arch/arm/dts/rk3288-miniarm.dtsi
@@ -116,18 +116,6 @@
cpu0-supply = <&vdd_cpu>;
};
-&emmc {
- broken-cd;
- bus-width = <8>;
- cap-mmc-highspeed;
- disable-wp;
- non-removable;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
- status = "okay";
-};
-
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts
index 3f61a61..284d5ed 100644
--- a/arch/arm/dts/rk3288-popmetal.dts
+++ b/arch/arm/dts/rk3288-popmetal.dts
@@ -17,7 +17,6 @@
};
&dmc {
- rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -25,8 +24,6 @@
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
- /* Add a dummy value to cause of-platdata think this is bytes */
- rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts
index 2c30355..11c580a 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -184,7 +184,6 @@
};
&dmc {
- rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -192,7 +191,6 @@
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
- rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
index bbbc2f4..f88a868 100644
--- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
@@ -13,6 +13,8 @@
/ {
aliases {
i2c20 = &i2c_tunnel;
+ video0 = &vopl;
+ video1 = &vopb;
};
gpio_keys: gpio-keys {
diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts
new file mode 100644
index 0000000..8aab607
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-jerry.dts
@@ -0,0 +1,214 @@
+/*
+ * Google Veyron Jerry Rev 3+ board device tree source
+ *
+ * Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+#include "cros-ec-sbs.dtsi"
+
+/ {
+ model = "Google Jerry";
+ compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
+ "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
+ "google,veyron-jerry-rev3", "google,veyron-jerry",
+ "google,veyron", "rockchip,rk3288";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ panel_regulator: panel-regualtor {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_enable_h>;
+ regulator-name = "panel_regulator";
+ vin-supply = <&vcc33_sys>;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&avdd_1v8_disp_en>;
+ regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc18_wl>;
+ };
+
+ backlight_regulator: backlight-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_pwr_en>;
+ regulator-name = "backlight_regulator";
+ vin-supply = <&vcc33_sys>;
+ startup-delay-us = <15000>;
+ };
+};
+
+&dmc {
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
+&gpio_keys {
+ power {
+ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&backlight {
+ power-supply = <&backlight_regulator>;
+};
+
+&panel {
+ power-supply= <&panel_regulator>;
+};
+
+&rk808 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
+ dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
+ <&gpio7 15 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ mic_vcc: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "mic_vcc";
+ regulator-suspend-mem-disabled;
+ };
+ };
+};
+
+&sdmmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ &sdmmc_bus4>;
+ disable-wp;
+};
+
+&vcc_5v {
+ enable-active-high;
+ gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&drv_5v>;
+};
+
+&vcc50_hdmi {
+ enable-active-high;
+ gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc50_hdmi_en>;
+};
+
+&edp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+};
+
+&pinctrl {
+ backlight {
+ bl_pwr_en: bl_pwr_en {
+ rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buck-5v {
+ drv_5v: drv-5v {
+ rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ edp {
+ edp_hpd: edp_hpd {
+ rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
+ };
+ };
+
+ emmc {
+ /* Make sure eMMC is not in reset */
+ emmc_deassert_reset: emmc-deassert-reset {
+ rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hdmi {
+ vcc50_hdmi_en: vcc50-hdmi-en {
+ rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ lcd {
+ lcd_enable_h: lcd-en {
+ rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ avdd_1v8_disp_en: avdd-1v8-disp-en {
+ rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ dvs_1: dvs-1 {
+ rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ dvs_2: dvs-2 {
+ rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ /*
+ * Trackpad pin control is shared between Elan and Synaptics devices
+ * so we have to pull it up to the bus level.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_xfer &trackpad_int>;
+
+ trackpad@15 {
+ compatible = "elan,i2c_touchpad";
+ interrupt-parent = <&gpio7>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ /*
+ * Remove the inherited pinctrl settings to avoid clashing
+ * with bus-wide ones.
+ */
+ /delete-property/pinctrl-names;
+ /delete-property/pinctrl-0;
+ reg = <0x15>;
+ vcc-supply = <&vcc33_io>;
+ wakeup-source;
+ };
+
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ interrupt-parent = <&gpio7>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ reg = <0x2c>;
+ hid-descr-addr = <0x0020>;
+ vcc-supply = <&vcc33_io>;
+ wakeup-source;
+ };
+};
diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts
new file mode 100644
index 0000000..e0dc362
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-mickey.dts
@@ -0,0 +1,277 @@
+/*
+ * Google Veyron Mickey Rev 0 board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+
+/ {
+ model = "Google Mickey";
+ compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
+ "google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
+ "google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
+ "google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
+ "google,veyron-mickey-rev0", "google,veyron-mickey",
+ "google,veyron", "rockchip,rk3288";
+
+ vcc_5v: vcc-5v {
+ vin-supply = <&vcc33_sys>;
+ };
+
+ vcc33_io: vcc33_io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc33_io";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc33_sys>;
+ };
+};
+
+&cpu_thermal {
+ /delete-node/ trips;
+ /delete-node/ cooling-maps;
+
+ trips {
+ cpu_alert_almost_warm: cpu_alert_almost_warm {
+ temperature = <63000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert_warm: cpu_alert_warm {
+ temperature = <65000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert_almost_hot: cpu_alert_almost_hot {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert_hot: cpu_alert_hot {
+ temperature = <82000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert_hotter: cpu_alert_hotter {
+ temperature = <84000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert_very_hot: cpu_alert_very_hot {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ /*
+ * After 1st level, throttle the CPU down to as low as 1.4 GHz
+ * and don't let the GPU go faster than 400 MHz. Note that we
+ * won't throttle the GPU lower than 400 MHz due to CPU
+ * heat--we'll let the GPU do the rest itself.
+ */
+ cpu_warm_limit_cpu {
+ trip = <&cpu_alert_warm>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT 4>;
+ };
+
+ /*
+ * Add some discrete steps to help throttling system deal
+ * with the fact that there are two passive cooling devices:
+ * the CPU and the GPU.
+ *
+ * - 1.2 GHz - 1.0 GHz (almost hot)
+ * - 800 MHz (hot)
+ * - 800 MHz - 696 MHz (hotter)
+ * - 696 MHz - min (very hot)
+ *
+ * Note:
+ * - 800 MHz appears to be a "sweet spot" for me. I can run
+ * some pretty serious workload here and be happy.
+ * - After 696 MHz we stop lowering voltage, so throttling
+ * past there is less effective.
+ */
+ cpu_almost_hot_limit_cpu {
+ trip = <&cpu_alert_almost_hot>;
+ cooling-device =
+ <&cpu0 5 6>;
+ };
+ cpu_hot_limit_cpu {
+ trip = <&cpu_alert_hot>;
+ cooling-device =
+ <&cpu0 7 7>;
+ };
+ cpu_hotter_limit_cpu {
+ trip = <&cpu_alert_hotter>;
+ cooling-device =
+ <&cpu0 7 8>;
+ };
+ cpu_very_hot_limit_cpu {
+ trip = <&cpu_alert_very_hot>;
+ cooling-device =
+ <&cpu0 8 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&dmc {
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x2>;
+ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>;
+};
+
+&emmc {
+ /delete-property/mmc-hs200-1_8v;
+};
+
+&i2c2 {
+ status = "disabled";
+};
+
+&i2c4 {
+ status = "disabled";
+};
+
+&i2s {
+ status = "okay";
+ clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
+ clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
+};
+
+&rk808 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
+ dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
+ <&gpio7 15 GPIO_ACTIVE_HIGH>;
+
+ /delete-property/ vcc6-supply;
+ /delete-property/ vcc12-supply;
+
+ vcc11-supply = <&vcc33_sys>;
+
+ regulators {
+ /* vcc33_io is sourced directly from vcc33_sys */
+ /delete-node/ LDO_REG1;
+ /delete-node/ LDO_REG7;
+
+ /* This is not a pwren anymore, but the real power supply */
+ vdd10_lcd: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_lcd";
+ regulator-suspend-mem-disabled;
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ regulator-suspend-mem-disabled;
+ };
+ };
+};
+
+&pinctrl {
+ hdmi {
+ power_hdmi_on: power-hdmi-on {
+ rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ dvs_1: dvs-1 {
+ rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ dvs_2: dvs-2 {
+ rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&sdmmc {
+ status = "disabled";
+};
+
+&sdio0 {
+ status = "disabled";
+};
+
+&sdmmc {
+ status = "disabled";
+};
+
+&spi0 {
+ status = "disabled";
+};
+
+&usb_host0_ehci {
+ status = "disabled";
+};
+
+&usb_host1 {
+ status = "disabled";
+};
+
+&vcc50_hdmi {
+ enable-active-high;
+ gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_hdmi_on>;
+};
diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts
new file mode 100644
index 0000000..0a2915f
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-minnie.dts
@@ -0,0 +1,301 @@
+/*
+ * Google Veyron Minnie Rev 0+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+
+/ {
+ model = "Google Minnie";
+ compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
+ "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
+ "google,veyron-minnie-rev0", "google,veyron-minnie",
+ "google,veyron", "rockchip,rk3288";
+
+ backlight_regulator: backlight-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_pwr_en>;
+ regulator-name = "backlight_regulator";
+ vin-supply = <&vcc33_sys>;
+ startup-delay-us = <15000>;
+ };
+
+ panel_regulator: panel-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_enable_h>;
+ regulator-name = "panel_regulator";
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc33_sys>;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&avdd_1v8_disp_en>;
+ regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc18_wl>;
+ };
+};
+
+&backlight {
+ /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
+ brightness-levels = <
+ 0 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23
+ 24 25 26 27 28 29 30 31
+ 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63
+ 64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95
+ 96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ power-supply = <&backlight_regulator>;
+};
+
+&dmc {
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x1>;
+ rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>;
+};
+
+&emmc {
+ /delete-property/mmc-hs200-1_8v;
+};
+
+&gpio_keys {
+ pinctrl-0 = <&pwr_key_h &ap_lid_int_l &volum_down_l &volum_up_l>;
+
+ volum_down {
+ label = "Volum_down";
+ gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <100>;
+ };
+
+ volum_up {
+ label = "Volum_up";
+ gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <100>;
+ };
+};
+
+&i2c_tunnel {
+ battery: bq27500@55 {
+ compatible = "ti,bq27500";
+ reg = <0x55>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+ i2c-scl-falling-time-ns = <50>;
+ i2c-scl-rising-time-ns = <300>;
+
+ touchscreen@10 {
+ compatible = "elan,ekth3500";
+ reg = <0x10>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_int &touch_rst>;
+ reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ vcc33-supply = <&vcc33_touch>;
+ vccio-supply = <&vcc33_touch>;
+ };
+};
+
+&panel {
+ compatible = "auo,b101ean01", "simple-panel";
+ power-supply= <&panel_regulator>;
+};
+
+&rk808 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
+
+ regulators {
+ vcc33_touch: LDO_REG2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_touch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc5v_touch: SWITCH_REG2 {
+ regulator-name = "vcc5v_touch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+};
+
+&sdmmc {
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ &sdmmc_bus4>;
+};
+
+&vcc_5v {
+ enable-active-high;
+ gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&drv_5v>;
+};
+
+&vcc50_hdmi {
+ enable-active-high;
+ gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc50_hdmi_en>;
+};
+
+&pinctrl {
+ backlight {
+ bl_pwr_en: bl_pwr_en {
+ rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buck-5v {
+ drv_5v: drv-5v {
+ rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buttons {
+ volum_down_l: volum-down-l {
+ rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ volum_up_l: volum-up-l {
+ rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ hdmi {
+ vcc50_hdmi_en: vcc50-hdmi-en {
+ rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ lcd {
+ lcd_enable_h: lcd-en {
+ rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ avdd_1v8_disp_en: avdd-1v8-disp-en {
+ rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ dvs_1: dvs-1 {
+ rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ dvs_2: dvs-2 {
+ rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ prochot {
+ gpio_prochot: gpio-prochot {
+ rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ touchscreen {
+ touch_int: touch-int {
+ rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ touch_rst: touch-rst {
+ rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index d9d5187..a314058 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -245,16 +245,6 @@
533000 1150000
666000 1200000
>;
- rockchip,num-channels = <2>;
- rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
- 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
- 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
- 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
- 0x5 0x0>;
- rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
- 0xa60 0x40 0x10 0x0>;
- rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
- rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&efuse {
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index e92a492..fa60e19 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -23,6 +23,7 @@
regulator-name = "vdd_center";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
+ regulator-init-microvolt = <950000>;
regulator-always-on;
regulator-boot-on;
status = "okay";
@@ -43,6 +44,12 @@
regulator-always-on;
regulator-boot-on;
};
+
+ vcc5v0_host: vcc5v0-host-en {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+ };
};
&emmc_phy {
@@ -85,6 +92,10 @@
status = "okay";
};
+&dwc3_typec0 {
+ status = "okay";
+};
+
&usb_host1_ehci {
status = "okay";
};
@@ -93,6 +104,10 @@
status = "okay";
};
+&dwc3_typec1 {
+ status = "okay";
+};
+
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index a4c6e27..179860c 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#define USB_CLASS_HUB 9
/ {
compatible = "rockchip,rk3399";
@@ -175,6 +176,8 @@
clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk>;
fifo-depth = <0x100>;
status = "disabled";
};
@@ -228,6 +231,50 @@
status = "disabled";
};
+ dwc3_typec0: usb@fe800000 {
+ compatible = "rockchip,rk3399-xhci";
+ reg = <0x0 0xfe800000 0x0 0x100000>;
+ status = "disabled";
+ rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ snps,dis-enblslpm-quirk;
+ snps,phyif-utmi-bits = <16>;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-u2-susphy-quirk;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ hub {
+ compatible = "usb-hub";
+ usb,device-class = <USB_CLASS_HUB>;
+ };
+ typec_phy0 {
+ compatible = "rockchip,rk3399-usb3-phy";
+ reg = <0x0 0xff7c0000 0x0 0x40000>;
+ };
+ };
+
+ dwc3_typec1: usb@fe900000 {
+ compatible = "rockchip,rk3399-xhci";
+ reg = <0x0 0xfe900000 0x0 0x100000>;
+ status = "disabled";
+ rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ snps,dis-enblslpm-quirk;
+ snps,phyif-utmi-bits = <16>;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-u2-susphy-quirk;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ hub {
+ compatible = "usb-hub";
+ usb,device-class = <USB_CLASS_HUB>;
+ };
+ typec_phy1 {
+ compatible = "rockchip,rk3399-usb3-phy";
+ reg = <0x0 0xff800000 0x0 0x40000>;
+ };
+ };
+
gic: interrupt-controller@fee00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
@@ -771,6 +818,41 @@
};
};
+ sdmmc {
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins =
+ <4 8 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ <4 8 RK_FUNC_1 &pcfg_pull_up>,
+ <4 9 RK_FUNC_1 &pcfg_pull_up>,
+ <4 10 RK_FUNC_1 &pcfg_pull_up>,
+ <4 11 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins =
+ <4 12 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins =
+ <4 13 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_cd: sdmcc-cd {
+ rockchip,pins =
+ <0 7 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_wp: sdmmc-wp {
+ rockchip,pins =
+ <0 8 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
spdif {
spdif_bus: spdif-bus {
rockchip,pins =
diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts
index 7bbfe59..e80132d 100644
--- a/arch/arm/dts/s5pc1xx-goni.dts
+++ b/arch/arm/dts/s5pc1xx-goni.dts
@@ -19,6 +19,7 @@
serial2 = "/serial@e2900800";
console = "/serial@e2900800";
pinctrl0 = &pinctrl0;
+ i2c3 = &i2c_pmic;
};
pinctrl0: pinctrl@e0200000 {
@@ -32,4 +33,168 @@
id = <2>;
};
+ i2c_pmic: i2c-pmic {
+ compatible = "i2c-gpio";
+ gpios = <&gpj4 0 0>, /* sda */
+ <&gpj4 3 0>; /* scl */
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ pmic@66 {
+ compatible = "maxim,max8998";
+ reg = <0x66 0 0>;
+
+ voltage-regulators {
+ ldo2_reg: LDO2 {
+ regulator-compatible = "LDO2";
+ regulator-name = "VALIVE_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-compatible = "LDO3";
+ regulator-name = "VUSB+MIPI_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-compatible = "LDO4";
+ regulator-name = "VADC_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-compatible = "LDO5";
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-compatible = "LDO6";
+ regulator-name = "VCC_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-compatible = "LDO7";
+ regulator-name = "VLCD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-compatible = "LDO8";
+ regulator-name = "VUSB+VDAC_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-compatible = "LDO9";
+ regulator-name = "VCC+VCAM_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-compatible = "LDO10";
+ regulator-name = "VPLL_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-compatible = "LDO11";
+ regulator-name = "CAM_IO_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-compatible = "LDO12";
+ regulator-name = "CAM_ISP_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-compatible = "LDO13";
+ regulator-name = "CAM_A_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-compatible = "LDO14";
+ regulator-name = "CAM_CIF_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-compatible = "LDO15";
+ regulator-name = "CAM_AF_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-compatible = "LDO16";
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-compatible = "LDO17";
+ regulator-name = "CAM_8M_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-compatible = "BUCK1";
+ regulator-name = "VARM_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-compatible = "BUCK2";
+ regulator-name = "VINT_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-compatible = "BUCK3";
+ regulator-name = "VCC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-compatible = "BUCK4";
+ regulator-name = "CAM_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
};
diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi
index 19feb66..a881d9e 100644
--- a/arch/arm/dts/sama5d2.dtsi
+++ b/arch/arm/dts/sama5d2.dtsi
@@ -79,7 +79,7 @@
#clock-cells = <0>;
};
- plla: pllack {
+ plla: pllack@0 {
compatible = "atmel,sama5d3-clk-pll";
#clock-cells = <0>;
clocks = <&main>;
@@ -146,17 +146,17 @@
interrupt-parent = <&pmc>;
clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
- prog0: prog0 {
+ prog0: prog@0 {
#clock-cells = <0>;
reg = <0>;
};
- prog1: prog1 {
+ prog1: prog@1 {
#clock-cells = <0>;
reg = <1>;
};
- prog2: prog2 {
+ prog2: prog@2 {
#clock-cells = <0>;
reg = <2>;
};
@@ -167,49 +167,49 @@
#address-cells = <1>;
#size-cells = <0>;
- ddrck: ddrck {
+ ddrck: ddrck@2 {
#clock-cells = <0>;
reg = <2>;
clocks = <&mck>;
};
- lcdck: lcdck {
+ lcdck: lcdck@3 {
#clock-cells = <0>;
reg = <3>;
clocks = <&mck>;
};
- uhpck: uhpck {
+ uhpck: uhpck@6 {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
- udpck: udpck {
+ udpck: udpck@7 {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
- pck0: pck0 {
+ pck0: pck0@8 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
- pck1: pck1 {
+ pck1: pck1@9 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
- pck2: pck2 {
+ pck2: pck2@10 {
#clock-cells = <0>;
reg = <10>;
clocks = <&prog2>;
};
- iscck: iscck {
+ iscck: iscck@18 {
#clock-cells = <0>;
reg = <18>;
clocks = <&mck>;
@@ -222,203 +222,203 @@
#size-cells = <0>;
clocks = <&h32ck>;
- macb0_clk: macb0_clk {
+ macb0_clk: macb0_clk@5 {
#clock-cells = <0>;
reg = <5>;
atmel,clk-output-range = <0 83000000>;
};
- tdes_clk: tdes_clk {
+ tdes_clk: tdes_clk@11 {
#clock-cells = <0>;
reg = <11>;
atmel,clk-output-range = <0 83000000>;
};
- matrix1_clk: matrix1_clk {
+ matrix1_clk: matrix1_clk@14 {
#clock-cells = <0>;
reg = <14>;
};
- hsmc_clk: hsmc_clk {
+ hsmc_clk: hsmc_clk@17 {
#clock-cells = <0>;
reg = <17>;
};
- pioA_clk: pioA_clk {
+ pioA_clk: pioA_clk@18 {
#clock-cells = <0>;
reg = <18>;
atmel,clk-output-range = <0 83000000>;
};
- flx0_clk: flx0_clk {
+ flx0_clk: flx0_clk@19 {
#clock-cells = <0>;
reg = <19>;
atmel,clk-output-range = <0 83000000>;
};
- flx1_clk: flx1_clk {
+ flx1_clk: flx1_clk@20 {
#clock-cells = <0>;
reg = <20>;
atmel,clk-output-range = <0 83000000>;
};
- flx2_clk: flx2_clk {
+ flx2_clk: flx2_clk@21 {
#clock-cells = <0>;
reg = <21>;
atmel,clk-output-range = <0 83000000>;
};
- flx3_clk: flx3_clk {
+ flx3_clk: flx3_clk@22 {
#clock-cells = <0>;
reg = <22>;
atmel,clk-output-range = <0 83000000>;
};
- flx4_clk: flx4_clk {
+ flx4_clk: flx4_clk@23 {
#clock-cells = <0>;
reg = <23>;
atmel,clk-output-range = <0 83000000>;
};
- uart0_clk: uart0_clk {
+ uart0_clk: uart0_clk@24 {
#clock-cells = <0>;
reg = <24>;
atmel,clk-output-range = <0 83000000>;
};
- uart1_clk: uart1_clk {
+ uart1_clk: uart1_clk@25 {
#clock-cells = <0>;
reg = <25>;
atmel,clk-output-range = <0 83000000>;
};
- uart2_clk: uart2_clk {
+ uart2_clk: uart2_clk@26 {
#clock-cells = <0>;
reg = <26>;
atmel,clk-output-range = <0 83000000>;
};
- uart3_clk: uart3_clk {
+ uart3_clk: uart3_clk@27 {
#clock-cells = <0>;
reg = <27>;
atmel,clk-output-range = <0 83000000>;
};
- uart4_clk: uart4_clk {
+ uart4_clk: uart4_clk@28 {
#clock-cells = <0>;
reg = <28>;
atmel,clk-output-range = <0 83000000>;
};
- twi0_clk: twi0_clk {
+ twi0_clk: twi0_clk@29 {
reg = <29>;
#clock-cells = <0>;
atmel,clk-output-range = <0 83000000>;
};
- twi1_clk: twi1_clk {
+ twi1_clk: twi1_clk@30 {
#clock-cells = <0>;
reg = <30>;
atmel,clk-output-range = <0 83000000>;
};
- spi0_clk: spi0_clk {
+ spi0_clk: spi0_clk@33 {
#clock-cells = <0>;
reg = <33>;
atmel,clk-output-range = <0 83000000>;
};
- spi1_clk: spi1_clk {
+ spi1_clk: spi1_clk@34 {
#clock-cells = <0>;
reg = <34>;
atmel,clk-output-range = <0 83000000>;
};
- tcb0_clk: tcb0_clk {
+ tcb0_clk: tcb0_clk@35 {
#clock-cells = <0>;
reg = <35>;
atmel,clk-output-range = <0 83000000>;
};
- tcb1_clk: tcb1_clk {
+ tcb1_clk: tcb1_clk@36 {
#clock-cells = <0>;
reg = <36>;
atmel,clk-output-range = <0 83000000>;
};
- pwm_clk: pwm_clk {
+ pwm_clk: pwm_clk@38 {
#clock-cells = <0>;
reg = <38>;
atmel,clk-output-range = <0 83000000>;
};
- adc_clk: adc_clk {
+ adc_clk: adc_clk@40 {
#clock-cells = <0>;
reg = <40>;
atmel,clk-output-range = <0 83000000>;
};
- uhphs_clk: uhphs_clk {
+ uhphs_clk: uhphs_clk@41 {
#clock-cells = <0>;
reg = <41>;
atmel,clk-output-range = <0 83000000>;
};
- udphs_clk: udphs_clk {
+ udphs_clk: udphs_clk@42 {
#clock-cells = <0>;
reg = <42>;
atmel,clk-output-range = <0 83000000>;
};
- ssc0_clk: ssc0_clk {
+ ssc0_clk: ssc0_clk@43 {
#clock-cells = <0>;
reg = <43>;
atmel,clk-output-range = <0 83000000>;
};
- ssc1_clk: ssc1_clk {
+ ssc1_clk: ssc1_clk@44 {
#clock-cells = <0>;
reg = <44>;
atmel,clk-output-range = <0 83000000>;
};
- trng_clk: trng_clk {
+ trng_clk: trng_clk@47 {
#clock-cells = <0>;
reg = <47>;
atmel,clk-output-range = <0 83000000>;
};
- pdmic_clk: pdmic_clk {
+ pdmic_clk: pdmic_clk@48 {
#clock-cells = <0>;
reg = <48>;
atmel,clk-output-range = <0 83000000>;
};
- i2s0_clk: i2s0_clk {
+ i2s0_clk: i2s0_clk@54 {
#clock-cells = <0>;
reg = <54>;
atmel,clk-output-range = <0 83000000>;
};
- i2s1_clk: i2s1_clk {
+ i2s1_clk: i2s1_clk@55 {
#clock-cells = <0>;
reg = <55>;
atmel,clk-output-range = <0 83000000>;
};
- can0_clk: can0_clk {
+ can0_clk: can0_clk@56 {
#clock-cells = <0>;
reg = <56>;
atmel,clk-output-range = <0 83000000>;
};
- can1_clk: can1_clk {
+ can1_clk: can1_clk@57 {
#clock-cells = <0>;
reg = <57>;
atmel,clk-output-range = <0 83000000>;
};
- classd_clk: classd_clk {
+ classd_clk: classd_clk@59 {
#clock-cells = <0>;
reg = <59>;
atmel,clk-output-range = <0 83000000>;
@@ -431,67 +431,67 @@
#size-cells = <0>;
clocks = <&mck>;
- dma0_clk: dma0_clk {
+ dma0_clk: dma0_clk@6 {
#clock-cells = <0>;
reg = <6>;
};
- dma1_clk: dma1_clk {
+ dma1_clk: dma1_clk@7 {
#clock-cells = <0>;
reg = <7>;
};
- aes_clk: aes_clk {
+ aes_clk: aes_clk@9 {
#clock-cells = <0>;
reg = <9>;
};
- aesb_clk: aesb_clk {
+ aesb_clk: aesb_clk@10 {
#clock-cells = <0>;
reg = <10>;
};
- sha_clk: sha_clk {
+ sha_clk: sha_clk@12 {
#clock-cells = <0>;
reg = <12>;
};
- mpddr_clk: mpddr_clk {
+ mpddr_clk: mpddr_clk@13 {
#clock-cells = <0>;
reg = <13>;
};
- matrix0_clk: matrix0_clk {
+ matrix0_clk: matrix0_clk@15 {
#clock-cells = <0>;
reg = <15>;
};
- sdmmc0_hclk: sdmmc0_hclk {
+ sdmmc0_hclk: sdmmc0_hclk@31 {
#clock-cells = <0>;
reg = <31>;
};
- sdmmc1_hclk: sdmmc1_hclk {
+ sdmmc1_hclk: sdmmc1_hclk@32 {
#clock-cells = <0>;
reg = <32>;
};
- lcdc_clk: lcdc_clk {
+ lcdc_clk: lcdc_clk@45 {
#clock-cells = <0>;
reg = <45>;
};
- isc_clk: isc_clk {
+ isc_clk: isc_clk@46 {
#clock-cells = <0>;
reg = <46>;
};
- qspi0_clk: qspi0_clk {
+ qspi0_clk: qspi0_clk@52 {
#clock-cells = <0>;
reg = <52>;
};
- qspi1_clk: qspi1_clk {
+ qspi1_clk: qspi1_clk@53 {
#clock-cells = <0>;
reg = <53>;
};
@@ -504,62 +504,62 @@
interrupt-parent = <&pmc>;
clocks = <&main>, <&plla>, <&utmi>, <&mck>;
- sdmmc0_gclk: sdmmc0_gclk {
+ sdmmc0_gclk: sdmmc0_gclk@31 {
#clock-cells = <0>;
reg = <31>;
};
- sdmmc1_gclk: sdmmc1_gclk {
+ sdmmc1_gclk: sdmmc1_gclk@32 {
#clock-cells = <0>;
reg = <32>;
};
- tcb0_gclk: tcb0_gclk {
+ tcb0_gclk: tcb0_gclk@35 {
#clock-cells = <0>;
reg = <35>;
atmel,clk-output-range = <0 83000000>;
};
- tcb1_gclk: tcb1_gclk {
+ tcb1_gclk: tcb1_gclk@36 {
#clock-cells = <0>;
reg = <36>;
atmel,clk-output-range = <0 83000000>;
};
- pwm_gclk: pwm_gclk {
+ pwm_gclk: pwm_gclk@38 {
#clock-cells = <0>;
reg = <38>;
atmel,clk-output-range = <0 83000000>;
};
- pdmic_gclk: pdmic_gclk {
+ pdmic_gclk: pdmic_gclk@48 {
#clock-cells = <0>;
reg = <48>;
};
- i2s0_gclk: i2s0_gclk {
+ i2s0_gclk: i2s0_gclk@54 {
#clock-cells = <0>;
reg = <54>;
};
- i2s1_gclk: i2s1_gclk {
+ i2s1_gclk: i2s1_gclk@55 {
#clock-cells = <0>;
reg = <55>;
};
- can0_gclk: can0_gclk {
+ can0_gclk: can0_gclk@56 {
#clock-cells = <0>;
reg = <56>;
atmel,clk-output-range = <0 80000000>;
};
- can1_gclk: can1_gclk {
+ can1_gclk: can1_gclk@57 {
#clock-cells = <0>;
reg = <57>;
atmel,clk-output-range = <0 80000000>;
};
- classd_gclk: classd_gclk {
+ classd_gclk: classd_gclk@59 {
#clock-cells = <0>;
reg = <59>;
atmel,clk-output-range = <0 100000000>;
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
new file mode 100644
index 0000000..a583990
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -0,0 +1,66 @@
+/*
+ * Copyright Altera Corporation (C) 2015
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Terasic DE1-SoC";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ aliases {
+ ethernet0 = &gmac1;
+ udc0 = &usb1;
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <420>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <420>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <1860>;
+ rxdv-skew-ps = <420>;
+ rxc-skew-ps = <1680>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&mmc0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
index d5a7249..9ec81c6 100644
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -46,6 +46,7 @@
aliases {
serial0 = &uart0;
+ ethernet0 = &emac;
};
soc {
@@ -78,3 +79,15 @@
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
+
+&usbphy {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 7d0dc76..bef0d00 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -653,5 +653,34 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ usbphy: phy@1c1b810 {
+ compatible = "allwinner,sun50i-a64-usb-phy",
+ "allwinner,sun8i-a33-usb-phy";
+ reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>;
+ reg-names = "phy_ctrl", "pmu1";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb@01c1b000 {
+ compatible = "allwinner,sun50i-a64-ehci",
+ "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1b400 {
+ compatible = "allwinner,sun50i-a64-ohci",
+ "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "enabled";
+ };
};
};
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
new file mode 100644
index 0000000..3d64caf
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "FriendlyARM NanoPi NEO";
+ compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+ pwr {
+ label = "nanopi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ default-state = "on";
+ };
+
+ status {
+ label = "nanopi:blue:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+ };
+ };
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ leds_opc: led-pins {
+ allwinner,pins = "PA10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_pio {
+ leds_r_opc: led-pins {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
new file mode 100644
index 0000000..dce688e
--- /dev/null
+++ b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016 FUKAUMI Naoki <naobsd@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+
+/ {
+ model = "Nintendo NES Classic Edition";
+ compatible = "nintendo,nes-classic-edition", "allwinner,sun8i-a33";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
new file mode 100644
index 0000000..5adfd9b
--- /dev/null
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -0,0 +1,14 @@
+#include <config.h>
+
+/ {
+ binman {
+ filename = "u-boot-sunxi-with-spl.bin";
+ pad-byte = <0xff>;
+ blob {
+ filename = "spl/sunxi-spl.bin";
+ };
+ u-boot-img {
+ pos = <CONFIG_SPL_PAD_TO>;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts
index 49195c3..5f4df88 100644
--- a/arch/arm/dts/tegra114-dalmore.dts
+++ b/arch/arm/dts/tegra114-dalmore.dts
@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
- sdhci0 = "/sdhci@78000600";
- sdhci1 = "/sdhci@78000400";
+ mmc0 = "/sdhci@78000600";
+ mmc1 = "/sdhci@78000400";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d008000";
};
@@ -66,6 +66,7 @@
sdhci@78000600 {
bus-width = <8>;
status = "okay";
+ non-removable;
};
usb@7d000000 {
@@ -78,4 +79,17 @@
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
};
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 88bdc49..8932ea3 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -1,53 +1,222 @@
#include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/memory/tegra114-mc.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra114";
+ interrupt-parent = <&lic>;
- tegra_car: clock {
+ host1x@50000000 {
+ compatible = "nvidia,tegra114-host1x", "simple-bus";
+ reg = <0x50000000 0x00028000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
+ resets = <&tegra_car 28>;
+ reset-names = "host1x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x54000000 0x54000000 0x01000000>;
+
+ gr2d@54140000 {
+ compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
+ reg = <0x54140000 0x00040000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_GR2D>;
+ resets = <&tegra_car 21>;
+ reset-names = "2d";
+ };
+
+ gr3d@54180000 {
+ compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
+ reg = <0x54180000 0x00040000>;
+ clocks = <&tegra_car TEGRA114_CLK_GR3D>;
+ resets = <&tegra_car 24>;
+ reset-names = "3d";
+ };
+
+ dc@54200000 {
+ compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+ reg = <0x54200000 0x00040000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_DISP1>,
+ <&tegra_car TEGRA114_CLK_PLL_P>;
+ clock-names = "dc", "parent";
+ resets = <&tegra_car 27>;
+ reset-names = "dc";
+
+ iommus = <&mc TEGRA_SWGROUP_DC>;
+
+ nvidia,head = <0>;
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ dc@54240000 {
+ compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+ reg = <0x54240000 0x00040000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_DISP2>,
+ <&tegra_car TEGRA114_CLK_PLL_P>;
+ clock-names = "dc", "parent";
+ resets = <&tegra_car 26>;
+ reset-names = "dc";
+
+ iommus = <&mc TEGRA_SWGROUP_DCB>;
+
+ nvidia,head = <1>;
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ hdmi@54280000 {
+ compatible = "nvidia,tegra114-hdmi";
+ reg = <0x54280000 0x00040000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_HDMI>,
+ <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
+ clock-names = "hdmi", "parent";
+ resets = <&tegra_car 51>;
+ reset-names = "hdmi";
+ status = "disabled";
+ };
+
+ dsi@54300000 {
+ compatible = "nvidia,tegra114-dsi";
+ reg = <0x54300000 0x00040000>;
+ clocks = <&tegra_car TEGRA114_CLK_DSIA>,
+ <&tegra_car TEGRA114_CLK_DSIALP>,
+ <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "lp", "parent";
+ resets = <&tegra_car 48>;
+ reset-names = "dsi";
+ nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dsi@54400000 {
+ compatible = "nvidia,tegra114-dsi";
+ reg = <0x54400000 0x00040000>;
+ clocks = <&tegra_car TEGRA114_CLK_DSIB>,
+ <&tegra_car TEGRA114_CLK_DSIBLP>,
+ <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
+ clock-names = "dsi", "lp", "parent";
+ resets = <&tegra_car 82>;
+ reset-names = "dsi";
+ nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ gic: interrupt-controller@50041000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x50041000 0x1000>,
+ <0x50042000 0x1000>,
+ <0x50044000 0x2000>,
+ <0x50046000 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-parent = <&gic>;
+ };
+
+ lic: interrupt-controller@60004000 {
+ compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
+ reg = <0x60004000 0x100>,
+ <0x60004100 0x50>,
+ <0x60004200 0x50>,
+ <0x60004300 0x50>,
+ <0x60004400 0x50>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ };
+
+ timer@60005000 {
+ compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
+ reg = <0x60005000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_TIMER>;
+ };
+
+ tegra_car: clock@60006000 {
compatible = "nvidia,tegra114-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
- apbdma: dma {
- compatible = "nvidia,tegra114-apbdma", "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+ flow-controller@60007000 {
+ compatible = "nvidia,tegra114-flowctrl";
+ reg = <0x60007000 0x1000>;
+ };
+
+ apbdma: dma@6000a000 {
+ compatible = "nvidia,tegra114-apbdma";
reg = <0x6000a000 0x1400>;
- interrupts = <0 104 0x04
- 0 105 0x04
- 0 106 0x04
- 0 107 0x04
- 0 108 0x04
- 0 109 0x04
- 0 110 0x04
- 0 111 0x04
- 0 112 0x04
- 0 113 0x04
- 0 114 0x04
- 0 115 0x04
- 0 116 0x04
- 0 117 0x04
- 0 118 0x04
- 0 119 0x04
- 0 128 0x04
- 0 129 0x04
- 0 130 0x04
- 0 131 0x04
- 0 132 0x04
- 0 133 0x04
- 0 134 0x04
- 0 135 0x04
- 0 136 0x04
- 0 137 0x04
- 0 138 0x04
- 0 139 0x04
- 0 140 0x04
- 0 141 0x04
- 0 142 0x04
- 0 143 0x04>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
+ resets = <&tegra_car 34>;
+ reset-names = "dma";
+ #dma-cells = <1>;
+ };
+
+ ahb: ahb@6000c000 {
+ compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
+ reg = <0x6000c000 0x150>;
};
gpio: gpio@6000d000 {
@@ -65,58 +234,31 @@
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
+ /*
+ gpio-ranges = <&pinmux 0 0 246>;
+ */
};
- i2c@7000c000 {
- compatible = "nvidia,tegra114-i2c";
- reg = <0x7000c000 0x100>;
- interrupts = <0 38 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 12>;
- status = "disabled";
+ apbmisc@70000800 {
+ compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
+ reg = <0x70000800 0x64 /* Chip revision */
+ 0x70000008 0x04>; /* Strapping options */
};
- i2c@7000c400 {
- compatible = "nvidia,tegra114-i2c";
- reg = <0x7000c400 0x100>;
- interrupts = <0 84 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 54>;
- status = "disabled";
+ pinmux: pinmux@70000868 {
+ compatible = "nvidia,tegra114-pinmux";
+ reg = <0x70000868 0x148 /* Pad control registers */
+ 0x70003000 0x40c>; /* Mux registers */
};
- i2c@7000c500 {
- compatible = "nvidia,tegra114-i2c";
- reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 67>;
- status = "disabled";
- };
-
- i2c@7000c700 {
- compatible = "nvidia,tegra114-i2c";
- reg = <0x7000c700 0x100>;
- interrupts = <0 120 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 103>;
- status = "disabled";
- };
-
- i2c@7000d000 {
- compatible = "nvidia,tegra114-i2c";
- reg = <0x7000d000 0x100>;
- interrupts = <0 53 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 47>;
- status = "disabled";
- };
-
+ /*
+ * There are two serial driver i.e. 8250 based simple serial
+ * driver and APB DMA based serial driver for higher baudrate
+ * and performace. To enable the 8250 based driver, the compatible
+ * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
+ * the APB DMA based serial driver, the compatible is
+ * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
+ */
uarta: serial@70006000 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
@@ -169,134 +311,477 @@
status = "disabled";
};
+ pwm: pwm@7000a000 {
+ compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
+ reg = <0x7000a000 0x100>;
+ #pwm-cells = <2>;
+ clocks = <&tegra_car TEGRA114_CLK_PWM>;
+ resets = <&tegra_car 17>;
+ reset-names = "pwm";
+ status = "disabled";
+ };
+
+ i2c@7000c000 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000c000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C1>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 12>;
+ reset-names = "i2c";
+ dmas = <&apbdma 21>, <&apbdma 21>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000c400 0x100>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C2>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 54>;
+ reset-names = "i2c";
+ dmas = <&apbdma 22>, <&apbdma 22>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000c500 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C3>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 67>;
+ reset-names = "i2c";
+ dmas = <&apbdma 23>, <&apbdma 23>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000c700 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000c700 0x100>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C4>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 103>;
+ reset-names = "i2c";
+ dmas = <&apbdma 26>, <&apbdma 26>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000d000 0x100>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_I2C5>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 47>;
+ reset-names = "i2c";
+ dmas = <&apbdma 24>, <&apbdma 24>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spi@7000d400 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d400 0x200>;
- interrupts = <0 59 0x04>;
- nvidia,dma-request-selector = <&apbdma 15>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC1>;
+ clock-names = "spi";
+ resets = <&tegra_car 41>;
+ reset-names = "spi";
+ dmas = <&apbdma 15>, <&apbdma 15>;
+ dma-names = "rx", "tx";
status = "disabled";
- /* PERIPH_ID_SBC1, PLLP_OUT0 */
- clocks = <&tegra_car 41>;
};
spi@7000d600 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>;
- interrupts = <0 82 0x04>;
- nvidia,dma-request-selector = <&apbdma 16>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC2>;
+ clock-names = "spi";
+ resets = <&tegra_car 44>;
+ reset-names = "spi";
+ dmas = <&apbdma 16>, <&apbdma 16>;
+ dma-names = "rx", "tx";
status = "disabled";
- /* PERIPH_ID_SBC2, PLLP_OUT0 */
- clocks = <&tegra_car 44>;
};
spi@7000d800 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d800 0x200>;
- interrupts = <0 83 0x04>;
- nvidia,dma-request-selector = <&apbdma 17>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC3>;
+ clock-names = "spi";
+ resets = <&tegra_car 46>;
+ reset-names = "spi";
+ dmas = <&apbdma 17>, <&apbdma 17>;
+ dma-names = "rx", "tx";
status = "disabled";
- /* PERIPH_ID_SBC3, PLLP_OUT0 */
- clocks = <&tegra_car 46>;
};
spi@7000da00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000da00 0x200>;
- interrupts = <0 93 0x04>;
- nvidia,dma-request-selector = <&apbdma 18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC4>;
+ clock-names = "spi";
+ resets = <&tegra_car 68>;
+ reset-names = "spi";
+ dmas = <&apbdma 18>, <&apbdma 18>;
+ dma-names = "rx", "tx";
status = "disabled";
- /* PERIPH_ID_SBC4, PLLP_OUT0 */
- clocks = <&tegra_car 68>;
};
spi@7000dc00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000dc00 0x200>;
- interrupts = <0 94 0x04>;
- nvidia,dma-request-selector = <&apbdma 27>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC5>;
+ clock-names = "spi";
+ resets = <&tegra_car 104>;
+ reset-names = "spi";
+ dmas = <&apbdma 27>, <&apbdma 27>;
+ dma-names = "rx", "tx";
status = "disabled";
- /* PERIPH_ID_SBC5, PLLP_OUT0 */
- clocks = <&tegra_car 104>;
};
spi@7000de00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000de00 0x200>;
- interrupts = <0 79 0x04>;
- nvidia,dma-request-selector = <&apbdma 28>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&tegra_car TEGRA114_CLK_SBC6>;
+ clock-names = "spi";
+ resets = <&tegra_car 105>;
+ reset-names = "spi";
+ dmas = <&apbdma 28>, <&apbdma 28>;
+ dma-names = "rx", "tx";
status = "disabled";
- /* PERIPH_ID_SBC6, PLLP_OUT0 */
- clocks = <&tegra_car 105>;
+ };
+
+ rtc@7000e000 {
+ compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_RTC>;
+ };
+
+ kbc@7000e200 {
+ compatible = "nvidia,tegra114-kbc";
+ reg = <0x7000e200 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_KBC>;
+ resets = <&tegra_car 36>;
+ reset-names = "kbc";
+ status = "disabled";
+ };
+
+ pmc@7000e400 {
+ compatible = "nvidia,tegra114-pmc";
+ reg = <0x7000e400 0x400>;
+ clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
+ };
+
+ fuse@7000f800 {
+ compatible = "nvidia,tegra114-efuse";
+ reg = <0x7000f800 0x400>;
+ clocks = <&tegra_car TEGRA114_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
+
+ mc: memory-controller@70019000 {
+ compatible = "nvidia,tegra114-mc";
+ reg = <0x70019000 0x1000>;
+ clocks = <&tegra_car TEGRA114_CLK_MC>;
+ clock-names = "mc";
+
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <1>;
+ };
+
+ ahub@70080000 {
+ compatible = "nvidia,tegra114-ahub";
+ reg = <0x70080000 0x200>,
+ <0x70080200 0x100>,
+ <0x70081000 0x200>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
+ <&tegra_car TEGRA114_CLK_APBIF>;
+ clock-names = "d_audio", "apbif";
+ resets = <&tegra_car 106>, /* d_audio */
+ <&tegra_car 107>, /* apbif */
+ <&tegra_car 30>, /* i2s0 */
+ <&tegra_car 11>, /* i2s1 */
+ <&tegra_car 18>, /* i2s2 */
+ <&tegra_car 101>, /* i2s3 */
+ <&tegra_car 102>, /* i2s4 */
+ <&tegra_car 108>, /* dam0 */
+ <&tegra_car 109>, /* dam1 */
+ <&tegra_car 110>, /* dam2 */
+ <&tegra_car 10>, /* spdif */
+ <&tegra_car 153>, /* amx */
+ <&tegra_car 154>; /* adx */
+ reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+ "i2s3", "i2s4", "dam0", "dam1", "dam2",
+ "spdif", "amx", "adx";
+ dmas = <&apbdma 1>, <&apbdma 1>,
+ <&apbdma 2>, <&apbdma 2>,
+ <&apbdma 3>, <&apbdma 3>,
+ <&apbdma 4>, <&apbdma 4>,
+ <&apbdma 6>, <&apbdma 6>,
+ <&apbdma 7>, <&apbdma 7>,
+ <&apbdma 12>, <&apbdma 12>,
+ <&apbdma 13>, <&apbdma 13>,
+ <&apbdma 14>, <&apbdma 14>,
+ <&apbdma 29>, <&apbdma 29>;
+ dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+ "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
+ "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
+ "rx9", "tx9";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tegra_i2s0: i2s@70080300 {
+ compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+ reg = <0x70080300 0x100>;
+ nvidia,ahub-cif-ids = <4 4>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+ resets = <&tegra_car 30>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s1: i2s@70080400 {
+ compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+ reg = <0x70080400 0x100>;
+ nvidia,ahub-cif-ids = <5 5>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+ resets = <&tegra_car 11>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s2: i2s@70080500 {
+ compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+ reg = <0x70080500 0x100>;
+ nvidia,ahub-cif-ids = <6 6>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+ resets = <&tegra_car 18>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s3: i2s@70080600 {
+ compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+ reg = <0x70080600 0x100>;
+ nvidia,ahub-cif-ids = <7 7>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+ resets = <&tegra_car 101>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s4: i2s@70080700 {
+ compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+ reg = <0x70080700 0x100>;
+ nvidia,ahub-cif-ids = <8 8>;
+ clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+ resets = <&tegra_car 102>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+ };
+
+ mipi: mipi@700e3000 {
+ compatible = "nvidia,tegra114-mipi";
+ reg = <0x700e3000 0x100>;
+ clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
+ #nvidia,mipi-calibrate-cells = <1>;
};
sdhci@78000000 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000000 0x200>;
- interrupts = <0 14 0x04>;
- clocks = <&tegra_car 14>;
- status = "disable";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
+ resets = <&tegra_car 14>;
+ reset-names = "sdhci";
+ status = "disabled";
};
sdhci@78000200 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000200 0x200>;
- interrupts = <0 15 0x04>;
- clocks = <&tegra_car 9>;
- status = "disable";
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
+ resets = <&tegra_car 9>;
+ reset-names = "sdhci";
+ status = "disabled";
};
sdhci@78000400 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000400 0x200>;
- interrupts = <0 19 0x04>;
- clocks = <&tegra_car 69>;
- status = "disable";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
+ resets = <&tegra_car 69>;
+ reset-names = "sdhci";
+ status = "disabled";
};
sdhci@78000600 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000600 0x200>;
- interrupts = <0 31 0x04>;
- clocks = <&tegra_car 15>;
- status = "disable";
- };
-
- usb@7d000000 {
- compatible = "nvidia,tegra114-ehci";
- reg = <0x7d000000 0x4000>;
- interrupts = <52>;
- phy_type = "utmi";
- clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
+ resets = <&tegra_car 15>;
+ reset-names = "sdhci";
status = "disabled";
};
- usb@7d004000 {
- compatible = "nvidia,tegra114-ehci";
- reg = <0x7d004000 0x4000>;
- interrupts = <53>;
- phy_type = "hsic";
- clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
+ usb@7d000000 {
+ compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ reg = <0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA114_CLK_USBD>;
+ resets = <&tegra_car 22>;
+ reset-names = "usb";
+ nvidia,phy = <&phy1>;
+ status = "disabled";
+ };
+
+ phy1: usb-phy@7d000000 {
+ compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
+ reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA114_CLK_USBD>,
+ <&tegra_car TEGRA114_CLK_PLL_U>,
+ <&tegra_car TEGRA114_CLK_USBD>;
+ clock-names = "reg", "pll_u", "utmi-pads";
+ resets = <&tegra_car 22>, <&tegra_car 22>;
+ reset-names = "usb", "utmi-pads";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <9>;
+ nvidia,xcvr-lsfslew = <0>;
+ nvidia,xcvr-lsrslew = <3>;
+ nvidia,hssquelch-level = <2>;
+ nvidia,hsdiscon-level = <5>;
+ nvidia,xcvr-hsslew = <12>;
+ nvidia,has-utmi-pad-registers;
status = "disabled";
};
usb@7d008000 {
- compatible = "nvidia,tegra114-ehci";
+ compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x7d008000 0x4000>;
- interrupts = <129>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
- clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
+ clocks = <&tegra_car TEGRA114_CLK_USB3>;
+ resets = <&tegra_car 59>;
+ reset-names = "usb";
+ nvidia,phy = <&phy3>;
status = "disabled";
};
+
+ phy3: usb-phy@7d008000 {
+ compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
+ reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA114_CLK_USB3>,
+ <&tegra_car TEGRA114_CLK_PLL_U>,
+ <&tegra_car TEGRA114_CLK_USBD>;
+ clock-names = "reg", "pll_u", "utmi-pads";
+ resets = <&tegra_car 59>, <&tegra_car 22>;
+ reset-names = "usb", "utmi-pads";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <9>;
+ nvidia,xcvr-lsfslew = <0>;
+ nvidia,xcvr-lsrslew = <3>;
+ nvidia,hssquelch-level = <2>;
+ nvidia,hsdiscon-level = <5>;
+ nvidia,xcvr-hsslew = <12>;
+ status = "disabled";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts =
+ <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&gic>;
+ };
};
diff --git a/arch/arm/dts/tegra124-cei-tk1-som.dts b/arch/arm/dts/tegra124-cei-tk1-som.dts
index d22c0ca..c4d4f9d 100644
--- a/arch/arm/dts/tegra124-cei-tk1-som.dts
+++ b/arch/arm/dts/tegra124-cei-tk1-som.dts
@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
- sdhci0 = "/sdhci@700b0600";
- sdhci1 = "/sdhci@700b0400";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d000000";
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts
index 21ed1ae..f1db952 100644
--- a/arch/arm/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
- sdhci0 = "/sdhci@700b0600";
- sdhci1 = "/sdhci@700b0400";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d000000";
@@ -312,6 +312,7 @@
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
usb@7d000000 {
diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
new file mode 100644
index 0000000..fff1d78
--- /dev/null
+++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ host1x@50000000 {
+ u-boot,dm-pre-reloc;
+ dc@54200000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts
index 20e0be3..62f89d0 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -15,10 +15,10 @@
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
i2c5 = "/i2c@7000d100";
- rtc0 = "/i2c@0,7000d000/pmic@40";
- rtc1 = "/rtc@0,7000e000";
- sdhci0 = "/sdhci@700b0600";
- sdhci1 = "/sdhci@700b0400";
+ rtc0 = "/i2c@7000d000/pmic@40";
+ rtc1 = "/rtc@7000e000";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d000000";
@@ -27,9 +27,7 @@
};
host1x@50000000 {
- u-boot,dm-pre-reloc;
dc@54200000 {
- u-boot,dm-pre-reloc;
display-timings {
timing@0 {
clock-frequency = <69500000>;
@@ -58,7 +56,7 @@
ddc-i2c-bus = <&dpaux>;
};
- sdhci@0,700b0400 { /* SD Card on this bus */
+ sdhci@700b0400 { /* SD Card on this bus */
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
};
@@ -69,7 +67,7 @@
nvidia,model = "GoogleNyanBig";
};
- pinmux@0,70000868 {
+ pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi
index 1b6931f..51895e4 100644
--- a/arch/arm/dts/tegra124-nyan.dtsi
+++ b/arch/arm/dts/tegra124-nyan.dtsi
@@ -3,8 +3,8 @@
/ {
aliases {
- rtc0 = "/i2c@0,7000d000/pmic@40";
- rtc1 = "/rtc@0,7000e000";
+ rtc0 = "/i2c@7000d000/pmic@40";
+ rtc1 = "/rtc@7000e000";
serial0 = &uarta;
};
@@ -424,10 +424,12 @@
usb@7d004000 { /* Internal webcam. */
status = "okay";
+ phy_type = "hsic";
};
usb-phy@7d004000 {
status = "okay";
+ phy_type = "hsic";
vbus-supply = <&vdd_run_cam>;
};
diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts
index 9de86c0..add9244 100644
--- a/arch/arm/dts/tegra124-venice2.dts
+++ b/arch/arm/dts/tegra124-venice2.dts
@@ -17,8 +17,8 @@
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
i2c5 = "/i2c@7000d100";
- sdhci0 = "/sdhci@700b0600";
- sdhci1 = "/sdhci@700b0400";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d000000";
@@ -81,6 +81,7 @@
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
usb@7d000000 {
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index 275a509..83d6348 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -196,13 +196,18 @@
lic: interrupt-controller@60004000 {
compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
+ reg = <0x0 0x60004000 0x0 0x100>,
+ <0x0 0x60004100 0x0 0x100>,
+ <0x0 0x60004200 0x0 0x100>,
+ <0x0 0x60004300 0x0 0x100>,
+ <0x0 0x60004400 0x0 0x100>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
timer@60005000 {
- compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
+ compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@@ -316,7 +321,7 @@
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
- * the APB DMA based serial driver, the comptible is
+ * the APB DMA based serial driver, the compatible is
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
*/
uarta: serial@70006000 {
@@ -399,10 +404,15 @@
i2c@7000c400 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
- interrupts = <0 84 0x04>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 54>;
+ clocks = <&tegra_car TEGRA124_CLK_I2C2>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 54>;
+ reset-names = "i2c";
+ dmas = <&apbdma 22>, <&apbdma 22>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -631,6 +641,41 @@
status = "disabled";
};
+ usb@70090000 {
+ compatible = "nvidia,tegra124-xusb";
+ reg = <0x70090000 0x8000>,
+ <0x70098000 0x1000>,
+ <0x70099000 0x1000>;
+ reg-names = "hcd", "fpci", "ipfs";
+
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
+ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
+ <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
+ <&tegra_car TEGRA124_CLK_XUSB_SS>,
+ <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
+ <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
+ <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
+ <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
+ <&tegra_car TEGRA124_CLK_PLL_U_480M>,
+ <&tegra_car TEGRA124_CLK_CLK_M>,
+ <&tegra_car TEGRA124_CLK_PLL_E>;
+ clock-names = "xusb_host", "xusb_host_src",
+ "xusb_falcon_src", "xusb_ss",
+ "xusb_ss_div2", "xusb_ss_src",
+ "xusb_hs_src", "xusb_fs_src",
+ "pll_u_480m", "clk_m", "pll_e";
+ resets = <&tegra_car 89>, <&tegra_car 156>,
+ <&tegra_car 143>;
+ reset-names = "xusb_host", "xusb_ss", "xusb_src";
+
+ nvidia,xusb-padctl = <&padctl>;
+
+ status = "disabled";
+ };
+
padctl: padctl@7009f000 {
compatible = "nvidia,tegra124-xusb-padctl";
reg = <0x7009f000 0x1000>;
@@ -820,7 +865,7 @@
};
usb@7d000000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x7d000000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
@@ -857,10 +902,10 @@
};
usb@7d004000 {
- compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x7d004000 0x4000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- phy_type = "hsic";
+ phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB2>;
resets = <&tegra_car 58>;
reset-names = "usb";
diff --git a/arch/arm/dts/tegra186-p2771-0000.dtsi b/arch/arm/dts/tegra186-p2771-0000.dtsi
index d867674..54b2539 100644
--- a/arch/arm/dts/tegra186-p2771-0000.dtsi
+++ b/arch/arm/dts/tegra186-p2771-0000.dtsi
@@ -9,8 +9,8 @@
};
aliases {
- sdhci0 = "/sdhci@3460000";
- sdhci1 = "/sdhci@3400000";
+ mmc0 = "/sdhci@3460000";
+ mmc1 = "/sdhci@3400000";
i2c0 = "/bpmp/i2c";
i2c1 = "/i2c@3160000";
i2c2 = "/i2c@c240000";
@@ -25,6 +25,11 @@
reg = <0x0 0x80000000 0x0 0x60000000>;
};
+ ethernet@2490000 {
+ status = "okay";
+ phy-reset-gpios = <&gpio_main TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
+ };
+
i2c@3160000 {
status = "okay";
};
@@ -50,6 +55,7 @@
sdhci@3460000 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
i2c@c240000 {
diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
index f878b65..dd9e3b8 100644
--- a/arch/arm/dts/tegra186.dtsi
+++ b/arch/arm/dts/tegra186.dtsi
@@ -31,6 +31,26 @@
#interrupt-cells = <2>;
};
+ ethernet@2490000 {
+ compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10";
+ reg = <0x0 0x02490000 0x0 0x10000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
+ <&bpmp TEGRA186_CLK_EQOS_AXI>,
+ <&bpmp TEGRA186_CLK_EQOS_RX>,
+ <&bpmp TEGRA186_CLK_EQOS_PTP_REF>,
+ <&bpmp TEGRA186_CLK_EQOS_TX>;
+ clock-names = "slave_bus",
+ "master_bus",
+ "rx",
+ "ptp_ref",
+ "tx";
+ resets = <&bpmp TEGRA186_RESET_EQOS>;
+ reset-names = "eqos";
+ phy-mode = "rgmii";
+ status = "disabled";
+ };
+
uarta: serial@3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x10000>;
diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts
index 2cf24d3..3c10dd6 100644
--- a/arch/arm/dts/tegra20-colibri.dts
+++ b/arch/arm/dts/tegra20-colibri.dts
@@ -14,41 +14,35 @@
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
- usb0 = "/usb@c5008000";
- usb1 = "/usb@c5000000";
- usb2 = "/usb@c5004000";
- sdhci0 = "/sdhci@c8000600";
+ mmc0 = "/sdhci@c8000600";
+ usb0 = "/usb@c5000000";
+ usb1 = "/usb@c5004000"; /* On-module only, for ASIX */
+ usb2 = "/usb@c5008000";
};
host1x@50000000 {
- status = "okay";
dc@54200000 {
- status = "okay";
rgb {
status = "okay";
nvidia,panel = <&lcd_panel>;
+ display-timings {
+ timing@0 {
+ /* VESA VGA */
+ clock-frequency = <25175000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <48>;
+ hfront-porch = <16>;
+ hsync-len = <96>;
+ vback-porch = <31>;
+ vfront-porch = <11>;
+ vsync-len = <2>;
+ };
+ };
};
};
};
- usb@c5000000 {
- statuc = "okay";
- dr_mode = "otg";
- };
-
- usb@c5004000 {
- statuc = "okay";
- /* VBUS_LAN */
- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
- };
-
- usb@c5008000 {
- statuc = "okay";
- /* USBH_PEN */
- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
- };
-
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
@@ -60,6 +54,10 @@
};
};
+ pwm@7000a000 {
+ status = "okay";
+ };
+
/*
* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
* board)
@@ -85,12 +83,47 @@
clock-frequency = <100000>;
};
+ /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
+ usb@c5000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ /* EHCI instance 1: ULPI -> USB3340 -> AX88772B */
+ usb@c5004000 {
+ status = "okay";
+ /* ULPI_RESET */
+ nvidia,phy-reset-gpio =
+ <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+ /* VBUS_LAN */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
+ usb@c5008000 {
+ status = "okay";
+ /* USBH_PEN */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ };
+
sdhci@c8000600 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ brightness-levels = <255 128 64 32 16 8 4 0>;
+ default-brightness-level = <6>;
+ /* BL_ON */
+ enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <®_3v3>;
+ /* PWM<A> */
+ pwms = <&pwm 0 5000000>;
+ };
+
clocks {
compatible = "simple-bus";
#address-cells = <1>;
@@ -104,25 +137,28 @@
};
};
- pwm: pwm@7000a000 {
- status = "okay";
+ lcd_panel: panel {
+ /*
+ * edt,et057090dhu: EDT 5.7" LCD TFT
+ * edt,et070080dh6: EDT 7.0" LCD TFT
+ */
+ compatible = "edt,et057090dhu", "simple-panel";
+
+ backlight = <&backlight>;
};
- lcd_panel: panel {
- clock = <25175000>;
- xres = <640>;
- yres = <480>;
- left-margin = <48>; /* horizontal back porch */
- right-margin = <16>; /* horizontal front porch */
- hsync-len = <96>;
- lower-margin = <11>; /* vertical front porch */
- upper-margin = <31>; /* vertical back porch */
- vsync-len = <2>;
- hsync-active-high;
- vsync-active-high;
- nvidia,bits-per-pixel = <16>;
- nvidia,pwm = <&pwm 0 0>;
- nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
- nvidia,panel-timings = <0 0 0 0>;
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3v3: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
};
diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts
index 8e9fe5a..dcbde7c 100644
--- a/arch/arm/dts/tegra20-harmony.dts
+++ b/arch/arm/dts/tegra20-harmony.dts
@@ -15,10 +15,11 @@
rtc0 = "/i2c@7000d000/tps6586x@34";
rtc1 = "/rtc@7000e000";
serial0 = &uartd;
- usb0 = "/usb@c5008000";
+ usb0 = "/usb@c5000000";
usb1 = "/usb@c5004000";
- sdhci0 = "/sdhci@c8000600";
- sdhci1 = "/sdhci@c8000200";
+ usb2 = "/usb@c5008000";
+ mmc0 = "/sdhci@c8000600";
+ mmc1 = "/sdhci@c8000200";
};
memory {
@@ -626,7 +627,8 @@
usb@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+ GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
diff --git a/arch/arm/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts
index 3d37257..1c79d75 100644
--- a/arch/arm/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/dts/tegra20-medcom-wide.dts
@@ -12,7 +12,7 @@
aliases {
usb0 = "/usb@c5008000";
- sdhci0 = "/sdhci@c8000600";
+ mmc0 = "/sdhci@c8000600";
};
memory {
diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts
index 5c7e805..ecf9fbd 100644
--- a/arch/arm/dts/tegra20-paz00.dts
+++ b/arch/arm/dts/tegra20-paz00.dts
@@ -1,5 +1,6 @@
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
/ {
@@ -11,9 +12,15 @@
};
aliases {
- usb0 = "/usb@c5008000";
- sdhci0 = "/sdhci@c8000600";
- sdhci1 = "/sdhci@c8000000";
+ rtc0 = "/i2c@7000d000/tps6586x@34";
+ rtc1 = "/rtc@7000e000";
+ serial0 = &uarta;
+ serial1 = &uartc;
+ usb0 = "/usb@c5000000";
+ usb1 = "/usb@c5004000";
+ usb2 = "/usb@c5008000";
+ mmc0 = "/sdhci@c8000600";
+ mmc1 = "/sdhci@c8000000";
};
memory {
@@ -26,19 +33,475 @@
status = "okay";
rgb {
status = "okay";
- nvidia,panel = <&lcd_panel>;
+
+ nvidia,panel = <&panel>;
+
+ display-timings {
+ timing@0 {
+ /* PAZ00 has 1024x600 */
+ clock-frequency = <54030000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hback-porch = <160>;
+ hfront-porch = <24>;
+ hsync-len = <136>;
+ vback-porch = <3>;
+ vfront-porch = <61>;
+ vsync-len = <6>;
+ hsync-active = <1>;
+ };
+ };
+ };
+ };
+
+ hdmi@54280000 {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ pinmux@70000014 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata", "atc", "atd", "ate",
+ "dap2", "gmb", "gmc", "gmd", "spia",
+ "spib", "spic", "spid", "spie";
+ nvidia,function = "gmi";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "pllc_out1";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "rsvd1";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gpu {
+ nvidia,pins = "gpu", "sdb", "sdd";
+ nvidia,function = "pwm";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa", "slxk";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint", "pta";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uarta";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ kbcb {
+ nvidia,pins = "kbcb", "kbcd";
+ nvidia,function = "sdio2";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+ "lhs", "lm0", "lm1", "lpp", "lpw0",
+ "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+ "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc";
+ nvidia,function = "owr";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdc {
+ nvidia,pins = "sdc";
+ nvidia,function = "twc";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxc {
+ nvidia,pins = "slxc", "slxd";
+ nvidia,function = "spi4";
+ };
+ spdi {
+ nvidia,pins = "spdi", "spdo";
+ nvidia,function = "rsvd2";
+ };
+ spif {
+ nvidia,pins = "spif", "uac";
+ nvidia,function = "rsvd4";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "spdif";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+ "cdev1", "cdev2", "dap1", "dap2", "dtf",
+ "gma", "gmb", "gmc", "gmd", "gme",
+ "gpu", "gpu7", "gpv", "i2cp", "pta",
+ "rm", "sdio1", "slxk", "spdo", "uac",
+ "uda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "dap3", "dap4", "dtb",
+ "dtc", "dte", "slxa", "slxc", "slxd",
+ "spdi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_csus {
+ nvidia,pins = "csus", "spia", "spib", "spid",
+ "spif";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_ddc {
+ nvidia,pins = "ddc", "irrx", "irtx", "kbca",
+ "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+ "spic", "spig", "uaa", "uab";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_dta {
+ nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
+ "spie", "spih", "uad", "uca", "ucb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhs", "lsc0", "lspi",
+ "lvs", "pmc";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ };
+ conf_lcsn {
+ nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
+ "lm0", "lm1", "lpp", "lpw0", "lpw1",
+ "lpw2", "lsc1", "lsck", "lsda", "lsdi",
+ "lvp0", "lvp1", "sdb";
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
};
};
};
+ i2s@70002800 {
+ status = "okay";
+ };
+
serial@70006000 {
- clock-frequency = < 216000000 >;
+ status = "okay";
+ };
+
+ serial@70006200 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ lvds_ddc: i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ alc5632: alc5632@1e {
+ compatible = "realtek,alc5632";
+ reg = <0x1e>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ hdmi_ddc: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ nvec@7000c500 {
+ compatible = "nvidia,nvec";
+ reg = <0x7000c500 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <80000>;
+ request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ slave-addr = <138>;
+ clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+ <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+ clock-names = "div-clk", "fast-clk";
+ resets = <&tegra_car 67>;
+ reset-names = "i2c";
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&p5valw_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ sm0 {
+ regulator-name = "+1.2vs_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ sm1 {
+ regulator-name = "+1.0vs_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: sm2 {
+ regulator-name = "+3.7vs_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ ldo1 {
+ regulator-name = "+1.1vs_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "+1.2vs_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3 {
+ regulator-name = "+3.3vs_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "+2.85vs_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo6 {
+ /*
+ * Research indicates this should be
+ * 1.8v; other boards that use this
+ * rail for the same purpose need it
+ * set to 1.8v. The schematic signal
+ * name is incorrect; perhaps copied
+ * from an incorrect NVIDIA reference.
+ */
+ regulator-name = "+2.85vs_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ hdmi_vdd_reg: ldo7 {
+ regulator-name = "+3.3vs_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: ldo8 {
+ regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo9 {
+ regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo_rtc {
+ regulator-name = "+3.3vs_rtc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ adt7461@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ };
+
+ pmc@7000e400 {
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <1>;
+ nvidia,cpu-pwr-good-time = <2000>;
+ nvidia,cpu-pwr-off-time = <0>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <0>;
+ nvidia,sys-clock-req-active-high;
+ };
+
+ usb@c5000000 {
+ status = "okay";
+ };
+
+ usb-phy@c5000000 {
+ status = "okay";
+ };
+
+ usb@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_LOW>;
+ };
+
+ usb-phy@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_LOW>;
};
usb@c5008000 {
status = "okay";
};
+ usb-phy@c5008000 {
+ status = "okay";
+ };
+
sdhci@c8000000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
@@ -50,6 +513,20 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
+ non-removable;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_bl_reg>;
+ pwms = <&pwm 0 5000000>;
+
+ brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
+ default-brightness-level = <10>;
+
+ backlight-boot-off;
};
clocks {
@@ -59,38 +536,101 @@
clk32k_in: clock@0 {
compatible = "fixed-clock";
- reg=<0>;
+ reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
- pwm: pwm@7000a000 {
- status = "okay";
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
};
- lcd_panel: panel {
- /* PAZ00 has 1024x600 */
- clock = <54030000>;
- xres = <1024>;
- yres = <600>;
- right-margin = <160>;
- left-margin = <24>;
- hsync-len = <136>;
- upper-margin = <3>;
- lower-margin = <61>;
- vsync-len = <6>;
- hsync-active-high;
- nvidia,bits-per-pixel = <16>;
- nvidia,pwm = <&pwm 0 0>;
- nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
- GPIO_ACTIVE_HIGH>;
- nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
- GPIO_ACTIVE_HIGH>;
- nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
- GPIO_ACTIVE_HIGH>;
- nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
- GPIO_ACTIVE_HIGH>;
- nvidia,panel-timings = <400 4 203 17 15>;
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ wifi {
+ label = "wifi-led";
+ gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "rfkill0";
+ };
+ };
+
+ panel: panel {
+ compatible = "samsung,ltn101nt05", "simple-panel";
+
+ ddc-i2c-bus = <&lvds_ddc>;
+ power-supply = <&vdd_pnl_reg>;
+ enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ p5valw_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "+5valw";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_pnl_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "+3VS,vdd_pnl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_bl_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-alc5632-paz00",
+ "nvidia,tegra-audio-alc5632";
+
+ nvidia,model = "Compal PAZ00";
+
+ nvidia,audio-routing =
+ "Int Spk", "SPKOUT",
+ "Int Spk", "SPKOUTN",
+ "Headset Mic", "MICBIAS1",
+ "MIC1", "Headset Mic",
+ "Headset Stereophone", "HPR",
+ "Headset Stereophone", "HPL",
+ "DMICDAT", "Digital Mic";
+
+ nvidia,audio-codec = <&alc5632>;
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
+
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
diff --git a/arch/arm/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts
index 7f57f1d..1b642be 100644
--- a/arch/arm/dts/tegra20-plutux.dts
+++ b/arch/arm/dts/tegra20-plutux.dts
@@ -12,7 +12,7 @@
aliases {
usb0 = "/usb@c5008000";
- sdhci0 = "/sdhci@c8000600";
+ mmc0 = "/sdhci@c8000600";
};
memory {
diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts
index 0a454f9..341c7f3 100644
--- a/arch/arm/dts/tegra20-seaboard.dts
+++ b/arch/arm/dts/tegra20-seaboard.dts
@@ -9,8 +9,9 @@
aliases {
/* This defines the order of our ports */
- usb0 = "/usb@c5008000";
- usb1 = "/usb@c5000000";
+ usb0 = "/usb@c5000000";
+ usb1 = "/usb@c5004000";
+ usb2 = "/usb@c5008000";
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
@@ -18,8 +19,8 @@
rtc0 = "/i2c@7000d000/tps6586x@34";
rtc1 = "/rtc@7000e000";
serial0 = &uartd;
- sdhci0 = "/sdhci@c8000600";
- sdhci1 = "/sdhci@c8000400";
+ mmc0 = "/sdhci@c8000600";
+ mmc1 = "/sdhci@c8000400";
};
chosen {
@@ -783,7 +784,7 @@
};
usb@c5004000 {
- status = "disabled";
+ status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts
index 4f68077..4733c81 100644
--- a/arch/arm/dts/tegra20-tec.dts
+++ b/arch/arm/dts/tegra20-tec.dts
@@ -12,7 +12,7 @@
aliases {
usb0 = "/usb@c5008000";
- sdhci0 = "/sdhci@c8000600";
+ mmc0 = "/sdhci@c8000600";
};
memory {
diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts
index db13ff9..7fb7dd0 100644
--- a/arch/arm/dts/tegra20-trimslice.dts
+++ b/arch/arm/dts/tegra20-trimslice.dts
@@ -11,10 +11,9 @@
};
aliases {
- usb0 = "/usb@c5008000";
- usb1 = "/usb@c5000000";
- sdhci0 = "/sdhci@c8000600";
- sdhci1 = "/sdhci@c8000000";
+ usb0 = "/usb@c5000000";
+ mmc0 = "/sdhci@c8000600";
+ mmc1 = "/sdhci@c8000000";
spi0 = "/spi@7000c380";
};
diff --git a/arch/arm/dts/tegra20-u-boot.dtsi b/arch/arm/dts/tegra20-u-boot.dtsi
new file mode 100644
index 0000000..9b9835d
--- /dev/null
+++ b/arch/arm/dts/tegra20-u-boot.dtsi
@@ -0,0 +1,8 @@
+/ {
+ host1x@50000000 {
+ u-boot,dm-pre-reloc;
+ dc@54200000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts
index 143e964..85cd1e3 100644
--- a/arch/arm/dts/tegra20-ventana.dts
+++ b/arch/arm/dts/tegra20-ventana.dts
@@ -15,9 +15,11 @@
rtc0 = "/i2c@7000d000/tps6586x@34";
rtc1 = "/rtc@7000e000";
serial0 = &uartd;
- usb0 = "/usb@c5008000";
- sdhci0 = "/sdhci@c8000600";
- sdhci1 = "/sdhci@c8000400";
+ usb0 = "/usb@c5000000";
+ usb1 = "/usb@c5004000";
+ usb2 = "/usb@c5008000";
+ mmc0 = "/sdhci@c8000600";
+ mmc1 = "/sdhci@c8000400";
};
memory {
diff --git a/arch/arm/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts
index 358c582..4478746 100644
--- a/arch/arm/dts/tegra20-whistler.dts
+++ b/arch/arm/dts/tegra20-whistler.dts
@@ -13,8 +13,8 @@
aliases {
i2c0 = "/i2c@7000d000";
usb0 = "/usb@c5008000";
- sdhci0 = "/sdhci@c8000600";
- sdhci1 = "/sdhci@c8000400";
+ mmc0 = "/sdhci@c8000600";
+ mmc1 = "/sdhci@c8000400";
};
memory {
@@ -58,6 +58,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
clocks {
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 31223e4..e21ee25 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -10,7 +10,6 @@
interrupt-parent = <&lic>;
host1x@50000000 {
- u-boot,dm-pre-reloc;
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -78,7 +77,6 @@
};
dc@54200000 {
- u-boot,dm-pre-reloc;
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
@@ -147,7 +145,7 @@
interrupt-parent = <&intc>;
reg = <0x50040600 0x20>;
interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&tegra_car TEGRA20_CLK_TWD>;
};
@@ -311,7 +309,7 @@
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
- * driver, the comptible is "nvidia,tegra20-hsuart".
+ * driver, the compatible is "nvidia,tegra20-hsuart".
*/
uarta: serial@70006000 {
compatible = "nvidia,tegra20-uart";
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-e2220-1170.dts
index 75efbba..70cd72b 100644
--- a/arch/arm/dts/tegra210-e2220-1170.dts
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -11,34 +11,35 @@
};
aliases {
- i2c0 = "/i2c@0,7000d000";
- sdhci0 = "/sdhci@0,700b0600";
- sdhci1 = "/sdhci@0,700b0000";
- usb0 = "/usb@0,7d000000";
+ i2c0 = "/i2c@7000d000";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b0000";
+ usb0 = "/usb@7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
- sdhci@0,700b0000 {
+ sdhci@700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
- sdhci@0,700b0600 {
+ sdhci@700b0600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
- i2c@0,7000d000 {
+ i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
- usb@0,7d000000 {
+ usb@7d000000 {
status = "okay";
dr_mode = "peripheral";
};
diff --git a/arch/arm/dts/tegra210-p2371-0000.dts b/arch/arm/dts/tegra210-p2371-0000.dts
index 10172a2..d961296 100644
--- a/arch/arm/dts/tegra210-p2371-0000.dts
+++ b/arch/arm/dts/tegra210-p2371-0000.dts
@@ -11,34 +11,35 @@
};
aliases {
- i2c0 = "/i2c@0,7000d000";
- sdhci0 = "/sdhci@0,700b0600";
- sdhci1 = "/sdhci@0,700b0000";
- usb0 = "/usb@0,7d000000";
+ i2c0 = "/i2c@7000d000";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b0000";
+ usb0 = "/usb@7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
- sdhci@0,700b0000 {
+ sdhci@700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
- sdhci@0,700b0600 {
+ sdhci@700b0600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
- i2c@0,7000d000 {
+ i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
- usb@0,7d000000 {
+ usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts
index bf35497..0dc06a4 100644
--- a/arch/arm/dts/tegra210-p2371-2180.dts
+++ b/arch/arm/dts/tegra210-p2371-2180.dts
@@ -11,17 +11,17 @@
};
aliases {
- i2c0 = "/i2c@0,7000d000";
- sdhci0 = "/sdhci@0,700b0600";
- sdhci1 = "/sdhci@0,700b0000";
- usb0 = "/usb@0,7d000000";
+ i2c0 = "/i2c@7000d000";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b0000";
+ usb0 = "/usb@7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
- pcie-controller@0,01003000 {
+ pcie-controller@01003000 {
status = "okay";
pci@1,0 {
@@ -33,7 +33,7 @@
};
};
- padctl@0,7009f000 {
+ padctl@7009f000 {
pinctrl-0 = <&padctl_default>;
pinctrl-names = "default";
@@ -71,7 +71,7 @@
};
};
- sdhci@0,700b0000 {
+ sdhci@700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
@@ -79,17 +79,18 @@
bus-width = <4>;
};
- sdhci@0,700b0600 {
+ sdhci@700b0600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
- i2c@0,7000d000 {
+ i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
- usb@0,7d000000 {
+ usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts
index de35bba..2afcde5 100644
--- a/arch/arm/dts/tegra210-p2571.dts
+++ b/arch/arm/dts/tegra210-p2571.dts
@@ -11,82 +11,83 @@
};
aliases {
- i2c0 = "/i2c@0,7000d000";
- i2c1 = "/i2c@0,7000c000";
- i2c2 = "/i2c@0,7000c400";
- i2c3 = "/i2c@0,7000c500";
- i2c4 = "/i2c@0,7000c700";
- i2c5 = "/i2c@0,7000d100";
- sdhci0 = "/sdhci@0,700b0600";
- sdhci1 = "/sdhci@0,700b0000";
- spi0 = "/spi@0,7000d400";
- spi1 = "/spi@0,7000da00";
- spi2 = "/spi@0,70410000";
- usb0 = "/usb@0,7d000000";
+ i2c0 = "/i2c@7000d000";
+ i2c1 = "/i2c@7000c000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ i2c5 = "/i2c@7000d100";
+ mmc0 = "/sdhci@700b0600";
+ mmc1 = "/sdhci@700b0000";
+ spi0 = "/spi@7000d400";
+ spi1 = "/spi@7000da00";
+ spi2 = "/spi@70410000";
+ usb0 = "/usb@7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
- i2c@0,7000c000 {
+ i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
};
- i2c@0,7000c400 {
+ i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
};
- i2c@0,7000c500 {
+ i2c@7000c500 {
status = "okay";
clock-frequency = <100000>;
};
- i2c@0,7000c700 {
+ i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
};
- i2c@0,7000d000 {
+ i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
- i2c@0,7000d100 {
+ i2c@7000d100 {
status = "okay";
clock-frequency = <400000>;
};
- spi@0,7000d400 {
+ spi@7000d400 {
status = "okay";
spi-max-frequency = <25000000>;
};
- spi@0,7000da00 {
+ spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
};
- spi@0,70410000 {
+ spi@70410000 {
status = "okay";
spi-max-frequency = <24000000>;
};
- sdhci@0,700b0000 {
+ sdhci@700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
- sdhci@0,700b0600 {
+ sdhci@700b0600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
- usb@0,7d000000 {
+ usb@7d000000 {
status = "okay";
dr_mode = "otg";
};
diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi
index a8c2f19..229fed0 100644
--- a/arch/arm/dts/tegra210.dtsi
+++ b/arch/arm/dts/tegra210.dtsi
@@ -1,18 +1,17 @@
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/memory/tegra210-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
-#include "skeleton.dtsi"
-
/ {
compatible = "nvidia,tegra210";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&lic>;
#address-cells = <2>;
#size-cells = <2>;
- pcie-controller@0,01003000 {
+ pcie-controller@01003000 {
compatible = "nvidia,tegra210-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -78,7 +77,202 @@
};
};
- gic: interrupt-controller@0,50041000 {
+ host1x@50000000 {
+ compatible = "nvidia,tegra210-host1x", "simple-bus";
+ reg = <0x0 0x50000000 0x0 0x00034000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
+ clock-names = "host1x";
+ resets = <&tegra_car 28>;
+ reset-names = "host1x";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
+
+ dpaux1: dpaux@54040000 {
+ compatible = "nvidia,tegra210-dpaux";
+ reg = <0x0 0x54040000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
+ <&tegra_car TEGRA210_CLK_PLL_DP>;
+ clock-names = "dpaux", "parent";
+ resets = <&tegra_car 207>;
+ reset-names = "dpaux";
+ status = "disabled";
+ };
+
+ vi@54080000 {
+ compatible = "nvidia,tegra210-vi";
+ reg = <0x0 0x54080000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ tsec@54100000 {
+ compatible = "nvidia,tegra210-tsec";
+ reg = <0x0 0x54100000 0x0 0x00040000>;
+ };
+
+ dc@54200000 {
+ compatible = "nvidia,tegra210-dc";
+ reg = <0x0 0x54200000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_DISP1>,
+ <&tegra_car TEGRA210_CLK_PLL_P>;
+ clock-names = "dc", "parent";
+ resets = <&tegra_car 27>;
+ reset-names = "dc";
+
+ iommus = <&mc TEGRA_SWGROUP_DC>;
+
+ nvidia,head = <0>;
+ };
+
+ dc@54240000 {
+ compatible = "nvidia,tegra210-dc";
+ reg = <0x0 0x54240000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_DISP2>,
+ <&tegra_car TEGRA210_CLK_PLL_P>;
+ clock-names = "dc", "parent";
+ resets = <&tegra_car 26>;
+ reset-names = "dc";
+
+ iommus = <&mc TEGRA_SWGROUP_DCB>;
+
+ nvidia,head = <1>;
+ };
+
+ dsi@54300000 {
+ compatible = "nvidia,tegra210-dsi";
+ reg = <0x0 0x54300000 0x0 0x00040000>;
+ clocks = <&tegra_car TEGRA210_CLK_DSIA>,
+ <&tegra_car TEGRA210_CLK_DSIALP>,
+ <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "lp", "parent";
+ resets = <&tegra_car 48>;
+ reset-names = "dsi";
+ nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ vic@54340000 {
+ compatible = "nvidia,tegra210-vic";
+ reg = <0x0 0x54340000 0x0 0x00040000>;
+ status = "disabled";
+ };
+
+ nvjpg@54380000 {
+ compatible = "nvidia,tegra210-nvjpg";
+ reg = <0x0 0x54380000 0x0 0x00040000>;
+ status = "disabled";
+ };
+
+ dsi@54400000 {
+ compatible = "nvidia,tegra210-dsi";
+ reg = <0x0 0x54400000 0x0 0x00040000>;
+ clocks = <&tegra_car TEGRA210_CLK_DSIB>,
+ <&tegra_car TEGRA210_CLK_DSIBLP>,
+ <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "lp", "parent";
+ resets = <&tegra_car 82>;
+ reset-names = "dsi";
+ nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ nvdec@54480000 {
+ compatible = "nvidia,tegra210-nvdec";
+ reg = <0x0 0x54480000 0x0 0x00040000>;
+ status = "disabled";
+ };
+
+ nvenc@544c0000 {
+ compatible = "nvidia,tegra210-nvenc";
+ reg = <0x0 0x544c0000 0x0 0x00040000>;
+ status = "disabled";
+ };
+
+ tsec@54500000 {
+ compatible = "nvidia,tegra210-tsec";
+ reg = <0x0 0x54500000 0x0 0x00040000>;
+ status = "disabled";
+ };
+
+ sor@54540000 {
+ compatible = "nvidia,tegra210-sor";
+ reg = <0x0 0x54540000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_SOR0>,
+ <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
+ <&tegra_car TEGRA210_CLK_PLL_DP>,
+ <&tegra_car TEGRA210_CLK_SOR_SAFE>;
+ clock-names = "sor", "parent", "dp", "safe";
+ resets = <&tegra_car 182>;
+ reset-names = "sor";
+ status = "disabled";
+ };
+
+ sor@54580000 {
+ compatible = "nvidia,tegra210-sor1";
+ reg = <0x0 0x54580000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_SOR1>,
+ <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
+ <&tegra_car TEGRA210_CLK_PLL_DP>,
+ <&tegra_car TEGRA210_CLK_SOR_SAFE>;
+ clock-names = "sor", "parent", "dp", "safe";
+ resets = <&tegra_car 183>;
+ reset-names = "sor";
+ status = "disabled";
+ };
+
+ dpaux: dpaux@545c0000 {
+ compatible = "nvidia,tegra124-dpaux";
+ reg = <0x0 0x545c0000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
+ <&tegra_car TEGRA210_CLK_PLL_DP>;
+ clock-names = "dpaux", "parent";
+ resets = <&tegra_car 181>;
+ reset-names = "dpaux";
+ status = "disabled";
+ };
+
+ isp@54600000 {
+ compatible = "nvidia,tegra210-isp";
+ reg = <0x0 0x54600000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ isp@54680000 {
+ compatible = "nvidia,tegra210-isp";
+ reg = <0x0 0x54680000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c@546c0000 {
+ compatible = "nvidia,tegra210-i2c-vi";
+ reg = <0x0 0x546c0000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@50041000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
@@ -91,14 +285,64 @@
interrupt-parent = <&gic>;
};
- tegra_car: clock@0,60006000 {
+ gpu@57000000 {
+ compatible = "nvidia,gm20b";
+ reg = <0x0 0x57000000 0x0 0x01000000>,
+ <0x0 0x58000000 0x0 0x01000000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&tegra_car TEGRA210_CLK_GPU>,
+ <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
+ <&tegra_car TEGRA210_CLK_PLL_G_REF>;
+ clock-names = "gpu", "pwr", "ref";
+ resets = <&tegra_car 184>;
+ reset-names = "gpu";
+
+ iommus = <&mc TEGRA_SWGROUP_GPU>;
+
+ status = "disabled";
+ };
+
+ lic: interrupt-controller@60004000 {
+ compatible = "nvidia,tegra210-ictlr";
+ reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
+ <0x0 0x60004100 0x0 0x40>, /* secondary controller */
+ <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
+ <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
+ <0x0 0x60004400 0x0 0x40>, /* quinary controller */
+ <0x0 0x60004500 0x0 0x40>; /* senary controller */
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ };
+
+ timer@60005000 {
+ compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
+ reg = <0x0 0x60005000 0x0 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_TIMER>;
+ clock-names = "timer";
+ };
+
+ tegra_car: clock@60006000 {
compatible = "nvidia,tegra210-car";
reg = <0x0 0x60006000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- gpio: gpio@0,6000d000 {
+ flow-controller@60007000 {
+ compatible = "nvidia,tegra210-flowctrl";
+ reg = <0x0 0x60007000 0x0 0x1000>;
+ };
+
+ gpio: gpio@6000d000 {
compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
reg = <0x0 0x6000d000 0x0 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -115,169 +359,336 @@
interrupt-controller;
};
- i2c@0,7000c000 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
- reg = <0x0 0x7000c000 0x0 0x100>;
- interrupts = <0 38 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 12>;
- status = "disabled";
+ apbdma: dma@60020000 {
+ compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
+ reg = <0x0 0x60020000 0x0 0x1400>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
+ clock-names = "dma";
+ resets = <&tegra_car 34>;
+ reset-names = "dma";
+ #dma-cells = <1>;
};
- i2c@0,7000c400 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
- reg = <0x0 0x7000c400 0x0 0x100>;
- interrupts = <0 84 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 54>;
- status = "disabled";
+ apbmisc@70000800 {
+ compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
+ reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
+ <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
};
- i2c@0,7000c500 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
- reg = <0x0 0x7000c500 0x0 0x100>;
- interrupts = <0 92 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 67>;
- status = "disabled";
+ pinmux: pinmux@700008d4 {
+ compatible = "nvidia,tegra210-pinmux";
+ reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
+ <0x0 0x70003000 0x0 0x294>; /* Mux registers */
};
- i2c@0,7000c700 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
- reg = <0x0 0x7000c700 0x0 0x100>;
- interrupts = <0 120 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 103>;
- status = "disabled";
- };
-
- i2c@0,7000d000 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
- reg = <0x0 0x7000d000 0x0 0x100>;
- interrupts = <0 53 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 47>;
- status = "disabled";
- };
-
- i2c@0,7000d100 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
- reg = <0x0 0x7000d100 0x0 0x100>;
- interrupts = <0 53 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 47>;
- status = "disabled";
- };
-
- uarta: serial@0,70006000 {
+ /*
+ * There are two serial driver i.e. 8250 based simple serial
+ * driver and APB DMA based serial driver for higher baudrate
+ * and performance. To enable the 8250 based driver, the compatible
+ * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
+ * the APB DMA based serial driver, the compatible is
+ * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
+ */
+ uarta: serial@70006000 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTA>;
+ clock-names = "serial";
resets = <&tegra_car 6>;
reset-names = "serial";
+ dmas = <&apbdma 8>, <&apbdma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- uartb: serial@0,70006040 {
+ uartb: serial@70006040 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006040 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTB>;
+ clock-names = "serial";
resets = <&tegra_car 7>;
reset-names = "serial";
+ dmas = <&apbdma 9>, <&apbdma 9>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- uartc: serial@0,70006200 {
+ uartc: serial@70006200 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006200 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTC>;
+ clock-names = "serial";
resets = <&tegra_car 55>;
reset-names = "serial";
+ dmas = <&apbdma 10>, <&apbdma 10>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- uartd: serial@0,70006300 {
+ uartd: serial@70006300 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006300 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTD>;
+ clock-names = "serial";
resets = <&tegra_car 65>;
reset-names = "serial";
+ dmas = <&apbdma 19>, <&apbdma 19>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- spi@0,7000d400 {
+ pwm: pwm@7000a000 {
+ compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
+ reg = <0x0 0x7000a000 0x0 0x100>;
+ #pwm-cells = <2>;
+ clocks = <&tegra_car TEGRA210_CLK_PWM>;
+ clock-names = "pwm";
+ resets = <&tegra_car 17>;
+ reset-names = "pwm";
+ status = "disabled";
+ };
+
+ i2c@7000c000 {
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x7000c000 0x0 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_I2C1>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 12>;
+ reset-names = "i2c";
+ dmas = <&apbdma 21>, <&apbdma 21>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x7000c400 0x0 0x100>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_I2C2>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 54>;
+ reset-names = "i2c";
+ dmas = <&apbdma 22>, <&apbdma 22>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x7000c500 0x0 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_I2C3>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 67>;
+ reset-names = "i2c";
+ dmas = <&apbdma 23>, <&apbdma 23>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000c700 {
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x7000c700 0x0 0x100>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_I2C4>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 103>;
+ reset-names = "i2c";
+ dmas = <&apbdma 26>, <&apbdma 26>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x7000d000 0x0 0x100>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_I2C5>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 47>;
+ reset-names = "i2c";
+ dmas = <&apbdma 24>, <&apbdma 24>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000d100 {
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x7000d100 0x0 0x100>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_I2C6>;
+ clock-names = "div-clk";
+ resets = <&tegra_car 166>;
+ reset-names = "i2c";
+ dmas = <&apbdma 30>, <&apbdma 30>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi@7000d400 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d400 0x0 0x200>;
- interrupts = <0 59 0x04>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC1>;
+ clock-names = "spi";
resets = <&tegra_car 41>;
reset-names = "spi";
+ dmas = <&apbdma 15>, <&apbdma 15>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- spi@0,7000d600 {
+ spi@7000d600 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d600 0x0 0x200>;
- interrupts = <0 82 0x04>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC2>;
+ clock-names = "spi";
resets = <&tegra_car 44>;
reset-names = "spi";
+ dmas = <&apbdma 16>, <&apbdma 16>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- spi@0,7000d800 {
+ spi@7000d800 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d800 0x0 0x200>;
- interrupts = <0 83 0x04>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC3>;
+ clock-names = "spi";
resets = <&tegra_car 46>;
reset-names = "spi";
+ dmas = <&apbdma 17>, <&apbdma 17>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- spi@0,7000da00 {
+ spi@7000da00 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000da00 0x0 0x200>;
- interrupts = <0 93 0x04>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC4>;
+ clock-names = "spi";
resets = <&tegra_car 68>;
reset-names = "spi";
+ dmas = <&apbdma 18>, <&apbdma 18>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- spi@0,70410000 {
- compatible = "nvidia,tegra210-qspi";
- reg = <0x0 0x70410000 0x0 0x1000>;
- interrupts = <0 10 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 211>;
+ rtc@7000e000 {
+ compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
+ reg = <0x0 0x7000e000 0x0 0x100>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_RTC>;
+ clock-names = "rtc";
+ };
+
+ pmc: pmc@7000e400 {
+ compatible = "nvidia,tegra210-pmc";
+ reg = <0x0 0x7000e400 0x0 0x400>;
+ clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
+ };
+
+ fuse@7000f800 {
+ compatible = "nvidia,tegra210-efuse";
+ reg = <0x0 0x7000f800 0x0 0x400>;
+ clocks = <&tegra_car TEGRA210_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
+
+ mc: memory-controller@70019000 {
+ compatible = "nvidia,tegra210-mc";
+ reg = <0x0 0x70019000 0x0 0x1000>;
+ clocks = <&tegra_car TEGRA210_CLK_MC>;
+ clock-names = "mc";
+
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <1>;
+ };
+
+ hda@70030000 {
+ compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
+ reg = <0x0 0x70030000 0x0 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_HDA>,
+ <&tegra_car TEGRA210_CLK_HDA2HDMI>,
+ <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
+ clock-names = "hda", "hda2hdmi", "hda2codec_2x";
+ resets = <&tegra_car 125>, /* hda */
+ <&tegra_car 128>, /* hda2hdmi */
+ <&tegra_car 111>; /* hda2codec_2x */
+ reset-names = "hda", "hda2hdmi", "hda2codec_2x";
status = "disabled";
};
- padctl: padctl@0,7009f000 {
+ padctl: padctl@7009f000 {
compatible = "nvidia,tegra210-xusb-padctl";
reg = <0x0 0x7009f000 0x0 0x1000>;
resets = <&tegra_car 142>;
@@ -285,65 +696,187 @@
#phy-cells = <1>;
};
- sdhci@0,700b0000 {
- compatible = "nvidia,tegra210-sdhci";
+ sdhci@700b0000 {
+ compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
- interrupts = <0 14 0x04>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
+ clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@0,700b0200 {
- compatible = "nvidia,tegra210-sdhci";
+ sdhci@700b0200 {
+ compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
- interrupts = <0 15 0x04>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
+ clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@0,700b0400 {
- compatible = "nvidia,tegra210-sdhci";
+ sdhci@700b0400 {
+ compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
- interrupts = <0 19 0x04>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
+ clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@0,700b0600 {
- compatible = "nvidia,tegra210-sdhci";
+ sdhci@700b0600 {
+ compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
- interrupts = <0 31 0x04>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
+ clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
};
- usb@0,7d000000 {
- compatible = "nvidia,tegra210-ehci";
- reg = <0x0 0x7d000000 0x0 0x4000>;
- interrupts = <0 20 0x04>;
- phy_type = "utmi";
- clocks = <&tegra_car TEGRA210_CLK_USBD>;
- resets = <&tegra_car 22>;
- reset-names = "usb";
+ mipi: mipi@700e3000 {
+ compatible = "nvidia,tegra210-mipi";
+ reg = <0x0 0x700e3000 0x0 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
+ clock-names = "mipi-cal";
+ #nvidia,mipi-calibrate-cells = <1>;
+ };
+
+ spi@70410000 {
+ compatible = "nvidia,tegra210-qspi";
+ reg = <0x0 0x70410000 0x0 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_QSPI>;
+ clock-names = "qspi";
+ resets = <&tegra_car 211>;
+ reset-names = "qspi";
+ dmas = <&apbdma 5>, <&apbdma 5>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- usb@0,7d004000 {
- compatible = "nvidia,tegra210-ehci";
+ usb@7d000000 {
+ compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+ reg = <0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA210_CLK_USBD>;
+ clock-names = "usb";
+ resets = <&tegra_car 22>;
+ reset-names = "usb";
+ nvidia,phy = <&phy1>;
+ status = "disabled";
+ };
+
+ phy1: usb-phy@7d000000 {
+ compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
+ reg = <0x0 0x7d000000 0x0 0x4000>,
+ <0x0 0x7d000000 0x0 0x4000>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA210_CLK_USBD>,
+ <&tegra_car TEGRA210_CLK_PLL_U>,
+ <&tegra_car TEGRA210_CLK_USBD>;
+ clock-names = "reg", "pll_u", "utmi-pads";
+ resets = <&tegra_car 22>, <&tegra_car 22>;
+ reset-names = "usb", "utmi-pads";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <9>;
+ nvidia,xcvr-lsfslew = <0>;
+ nvidia,xcvr-lsrslew = <3>;
+ nvidia,hssquelch-level = <2>;
+ nvidia,hsdiscon-level = <5>;
+ nvidia,xcvr-hsslew = <12>;
+ nvidia,has-utmi-pad-registers;
+ status = "disabled";
+ };
+
+ usb@7d004000 {
+ compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x0 0x7d004000 0x0 0x4000>;
- interrupts = < 53 >;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA210_CLK_USB2>;
+ clock-names = "usb";
resets = <&tegra_car 58>;
reset-names = "usb";
+ nvidia,phy = <&phy2>;
status = "disabled";
};
+
+ phy2: usb-phy@7d004000 {
+ compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
+ reg = <0x0 0x7d004000 0x0 0x4000>,
+ <0x0 0x7d000000 0x0 0x4000>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA210_CLK_USB2>,
+ <&tegra_car TEGRA210_CLK_PLL_U>,
+ <&tegra_car TEGRA210_CLK_USBD>;
+ clock-names = "reg", "pll_u", "utmi-pads";
+ resets = <&tegra_car 58>, <&tegra_car 22>;
+ reset-names = "usb", "utmi-pads";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <9>;
+ nvidia,xcvr-lsfslew = <0>;
+ nvidia,xcvr-lsrslew = <3>;
+ nvidia,hssquelch-level = <2>;
+ nvidia,hsdiscon-level = <5>;
+ nvidia,xcvr-hsslew = <12>;
+ status = "disabled";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <3>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&gic>;
+ };
};
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 3e0545c..9e4ab8c 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -15,9 +15,9 @@
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c500";
i2c3 = "/i2c@7000c700";
- sdhci0 = "/sdhci@78000600";
- sdhci1 = "/sdhci@78000400";
- sdhci2 = "/sdhci@78000000";
+ mmc0 = "/sdhci@78000600";
+ mmc1 = "/sdhci@78000400";
+ mmc2 = "/sdhci@78000000";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000dc00";
spi2 = "/spi@7000de00";
@@ -44,10 +44,12 @@
hvdd-pex-supply = <&sys_3v3_reg>;
pci@1,0 {
+ /* TS_DIFF1/2/3/4 left disabled */
nvidia,num-lanes = <4>;
};
pci@2,0 {
+ /* PCIE1_RX/TX left disabled */
nvidia,num-lanes = <1>;
};
@@ -277,7 +279,6 @@
status = "okay";
/* USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
- phy_type = "utmi";
};
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
@@ -287,6 +288,26 @@
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clk@0 {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ clk16m: clk@1 {
+ compatible = "fixed-clock";
+ reg=<1>;
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "clk16m";
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index ae83636..4a32fcf 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
- sdhci0 = "/sdhci@78000600";
- sdhci1 = "/sdhci@78000000";
+ mmc0 = "/sdhci@78000600";
+ mmc1 = "/sdhci@78000000";
spi0 = "/spi@7000da00";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d008000";
@@ -205,6 +205,7 @@
sdhci@78000600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
usb@7d000000 {
@@ -218,6 +219,19 @@
status = "okay";
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts
index 23ca141..70fd916 100644
--- a/arch/arm/dts/tegra30-cardhu.dts
+++ b/arch/arm/dts/tegra30-cardhu.dts
@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
- sdhci0 = "/sdhci@78000600";
- sdhci1 = "/sdhci@78000000";
+ mmc0 = "/sdhci@78000600";
+ mmc1 = "/sdhci@78000000";
spi0 = "/spi@7000da00";
usb0 = "/usb@7d008000";
};
@@ -194,6 +194,7 @@
sdhci@78000600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
usb@7d008000 {
@@ -201,6 +202,19 @@
status = "okay";
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts
index 487e1f6..3cff2f6 100644
--- a/arch/arm/dts/tegra30-colibri.dts
+++ b/arch/arm/dts/tegra30-colibri.dts
@@ -14,8 +14,8 @@
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c700";
- sdhci0 = "/sdhci@78000600";
- sdhci1 = "/sdhci@78000200";
+ mmc0 = "/sdhci@78000600";
+ mmc1 = "/sdhci@78000200";
spi0 = "/spi@7000d400";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d004000"; /* on module only, for ASIX */
@@ -84,7 +84,6 @@
status = "okay";
/* VBUS_LAN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
- phy_type = "utmi";
};
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
@@ -93,4 +92,17 @@
/* USBH_PEN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clk@0 {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
};
diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi
index 8eff627..33da175 100644
--- a/arch/arm/dts/tegra30-tamonten.dtsi
+++ b/arch/arm/dts/tegra30-tamonten.dtsi
@@ -18,9 +18,9 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000d000";
- sdhci0 = "/sdhci@78000600";
- sdhci1 = "/sdhci@78000400";
- sdhci2 = "/sdhci@78000000";
+ mmc0 = "/sdhci@78000600";
+ mmc1 = "/sdhci@78000400";
+ mmc2 = "/sdhci@78000000";
usb0 = "/usb@7d008000";
};
@@ -64,10 +64,23 @@
sdhci@78000600 {
status = "okay";
bus-width = <8>;
+ non-removable;
};
usb@7d008000 {
status = "okay";
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clk@0 {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
};
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index 5ea7e34..5030065 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -1,20 +1,14 @@
#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/memory/tegra30-mc.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra30";
- interrupt-parent = <&intc>;
-
- intc: interrupt-controller@50041000 {
- compatible = "arm,cortex-a9-gic";
- reg = <0x50041000 0x1000
- 0x50040100 0x0100>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
+ interrupt-parent = <&lic>;
pcie-controller@00003000 {
compatible = "nvidia,tegra30-pcie";
@@ -24,7 +18,7 @@
0x10000000 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
- GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
@@ -39,15 +33,18 @@
0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */
- 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
+ 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
+ 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
clocks = <&tegra_car TEGRA30_CLK_PCIE>,
<&tegra_car TEGRA30_CLK_AFI>,
- <&tegra_car TEGRA30_CLK_PCIEX>,
<&tegra_car TEGRA30_CLK_PLL_E>,
<&tegra_car TEGRA30_CLK_CML0>;
- clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+ clock-names = "pex", "afi", "pll_e", "cml";
+ resets = <&tegra_car 70>,
+ <&tegra_car 72>,
+ <&tegra_car 74>;
+ reset-names = "pex", "afi", "pcie_x";
status = "disabled";
pci@1,0 {
@@ -90,48 +87,251 @@
};
};
- tegra_car: clock {
+ host1x@50000000 {
+ compatible = "nvidia,tegra30-host1x", "simple-bus";
+ reg = <0x50000000 0x00024000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
+ resets = <&tegra_car 28>;
+ reset-names = "host1x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x54000000 0x54000000 0x04000000>;
+
+ mpe@54040000 {
+ compatible = "nvidia,tegra30-mpe";
+ reg = <0x54040000 0x00040000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_MPE>;
+ resets = <&tegra_car 60>;
+ reset-names = "mpe";
+ };
+
+ vi@54080000 {
+ compatible = "nvidia,tegra30-vi";
+ reg = <0x54080000 0x00040000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_VI>;
+ resets = <&tegra_car 20>;
+ reset-names = "vi";
+ };
+
+ epp@540c0000 {
+ compatible = "nvidia,tegra30-epp";
+ reg = <0x540c0000 0x00040000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_EPP>;
+ resets = <&tegra_car 19>;
+ reset-names = "epp";
+ };
+
+ isp@54100000 {
+ compatible = "nvidia,tegra30-isp";
+ reg = <0x54100000 0x00040000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_ISP>;
+ resets = <&tegra_car 23>;
+ reset-names = "isp";
+ };
+
+ gr2d@54140000 {
+ compatible = "nvidia,tegra30-gr2d";
+ reg = <0x54140000 0x00040000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_GR2D>;
+ resets = <&tegra_car 21>;
+ reset-names = "2d";
+ };
+
+ gr3d@54180000 {
+ compatible = "nvidia,tegra30-gr3d";
+ reg = <0x54180000 0x00040000>;
+ clocks = <&tegra_car TEGRA30_CLK_GR3D
+ &tegra_car TEGRA30_CLK_GR3D2>;
+ clock-names = "3d", "3d2";
+ resets = <&tegra_car 24>,
+ <&tegra_car 98>;
+ reset-names = "3d", "3d2";
+ };
+
+ dc@54200000 {
+ compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
+ reg = <0x54200000 0x00040000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+ <&tegra_car TEGRA30_CLK_PLL_P>;
+ clock-names = "dc", "parent";
+ resets = <&tegra_car 27>;
+ reset-names = "dc";
+
+ iommus = <&mc TEGRA_SWGROUP_DC>;
+
+ nvidia,head = <0>;
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ dc@54240000 {
+ compatible = "nvidia,tegra30-dc";
+ reg = <0x54240000 0x00040000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_DISP2>,
+ <&tegra_car TEGRA30_CLK_PLL_P>;
+ clock-names = "dc", "parent";
+ resets = <&tegra_car 26>;
+ reset-names = "dc";
+
+ iommus = <&mc TEGRA_SWGROUP_DCB>;
+
+ nvidia,head = <1>;
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ hdmi@54280000 {
+ compatible = "nvidia,tegra30-hdmi";
+ reg = <0x54280000 0x00040000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_HDMI>,
+ <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
+ clock-names = "hdmi", "parent";
+ resets = <&tegra_car 51>;
+ reset-names = "hdmi";
+ status = "disabled";
+ };
+
+ tvo@542c0000 {
+ compatible = "nvidia,tegra30-tvo";
+ reg = <0x542c0000 0x00040000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_TVO>;
+ status = "disabled";
+ };
+
+ dsi@54300000 {
+ compatible = "nvidia,tegra30-dsi";
+ reg = <0x54300000 0x00040000>;
+ clocks = <&tegra_car TEGRA30_CLK_DSIA>;
+ resets = <&tegra_car 48>;
+ reset-names = "dsi";
+ status = "disabled";
+ };
+ };
+
+ timer@50040600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x50040600 0x20>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&tegra_car TEGRA30_CLK_TWD>;
+ };
+
+ intc: interrupt-controller@50041000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x50041000 0x1000
+ 0x50040100 0x0100>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&intc>;
+ };
+
+ cache-controller@50043000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x50043000 0x1000>;
+ arm,data-latency = <6 6 2>;
+ arm,tag-latency = <5 5 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ lic: interrupt-controller@60004000 {
+ compatible = "nvidia,tegra30-ictlr";
+ reg = <0x60004000 0x100>,
+ <0x60004100 0x50>,
+ <0x60004200 0x50>,
+ <0x60004300 0x50>,
+ <0x60004400 0x50>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&intc>;
+ };
+
+ timer@60005000 {
+ compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
+ reg = <0x60005000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_TIMER>;
+ };
+
+ tegra_car: clock@60006000 {
compatible = "nvidia,tegra30-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
- apbdma: dma {
+ flow-controller@60007000 {
+ compatible = "nvidia,tegra30-flowctrl";
+ reg = <0x60007000 0x1000>;
+ };
+
+ apbdma: dma@6000a000 {
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1400>;
- interrupts = <0 104 0x04
- 0 105 0x04
- 0 106 0x04
- 0 107 0x04
- 0 108 0x04
- 0 109 0x04
- 0 110 0x04
- 0 111 0x04
- 0 112 0x04
- 0 113 0x04
- 0 114 0x04
- 0 115 0x04
- 0 116 0x04
- 0 117 0x04
- 0 118 0x04
- 0 119 0x04
- 0 128 0x04
- 0 129 0x04
- 0 130 0x04
- 0 131 0x04
- 0 132 0x04
- 0 133 0x04
- 0 134 0x04
- 0 135 0x04
- 0 136 0x04
- 0 137 0x04
- 0 138 0x04
- 0 139 0x04
- 0 140 0x04
- 0 141 0x04
- 0 142 0x04
- 0 143 0x04>;
- clocks = <&tegra_car 34>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
+ resets = <&tegra_car 34>;
+ reset-names = "dma";
+ #dma-cells = <1>;
+ };
+
+ ahb: ahb@6000c000 {
+ compatible = "nvidia,tegra30-ahb";
+ reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
};
gpio: gpio@6000d000 {
@@ -149,63 +349,31 @@
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
+ /*
+ gpio-ranges = <&pinmux 0 0 248>;
+ */
};
- i2c@7000c000 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c000 0x100>;
- interrupts = <0 38 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 12>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
+ apbmisc@70000800 {
+ compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
+ reg = <0x70000800 0x64 /* Chip revision */
+ 0x70000008 0x04>; /* Strapping options */
};
- i2c@7000c400 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c400 0x100>;
- interrupts = <0 84 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 54>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
+ pinmux: pinmux@70000868 {
+ compatible = "nvidia,tegra30-pinmux";
+ reg = <0x70000868 0xd4 /* Pad control registers */
+ 0x70003000 0x3e4>; /* Mux registers */
};
- i2c@7000c500 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c500 0x100>;
- interrupts = <0 92 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 67>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- i2c@7000c700 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000c700 0x100>;
- interrupts = <0 120 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 103>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
- i2c@7000d000 {
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000d000 0x100>;
- interrupts = <0 53 0x04>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 47>, <&tegra_car 182>;
- clock-names = "div-clk", "fast-clk";
- status = "disabled";
- };
-
+ /*
+ * There are two serial driver i.e. 8250 based simple serial
+ * driver and APB DMA based serial driver for higher baudrate
+ * and performace. To enable the 8250 based driver, the compatible
+ * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
+ * the APB DMA based serial driver, the compatible is
+ * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
+ */
uarta: serial@70006000 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
@@ -271,128 +439,506 @@
status = "disabled";
};
+ pwm: pwm@7000a000 {
+ compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
+ reg = <0x7000a000 0x100>;
+ #pwm-cells = <2>;
+ clocks = <&tegra_car TEGRA30_CLK_PWM>;
+ resets = <&tegra_car 17>;
+ reset-names = "pwm";
+ status = "disabled";
+ };
+
+ rtc@7000e000 {
+ compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_RTC>;
+ };
+
+ i2c@7000c000 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C1>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+ clock-names = "div-clk", "fast-clk";
+ resets = <&tegra_car 12>;
+ reset-names = "i2c";
+ dmas = <&apbdma 21>, <&apbdma 21>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c400 0x100>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C2>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+ clock-names = "div-clk", "fast-clk";
+ resets = <&tegra_car 54>;
+ reset-names = "i2c";
+ dmas = <&apbdma 22>, <&apbdma 22>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c500 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C3>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+ clock-names = "div-clk", "fast-clk";
+ resets = <&tegra_car 67>;
+ reset-names = "i2c";
+ dmas = <&apbdma 23>, <&apbdma 23>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000c700 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c700 0x100>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C4>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+ resets = <&tegra_car 103>;
+ reset-names = "i2c";
+ clock-names = "div-clk", "fast-clk";
+ dmas = <&apbdma 26>, <&apbdma 26>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000d000 0x100>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA30_CLK_I2C5>,
+ <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+ clock-names = "div-clk", "fast-clk";
+ resets = <&tegra_car 47>;
+ reset-names = "i2c";
+ dmas = <&apbdma 24>, <&apbdma 24>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spi@7000d400 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
- interrupts = <0 59 0x04>;
- nvidia,dma-request-selector = <&apbdma 15>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 41>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC1>;
+ resets = <&tegra_car 41>;
+ reset-names = "spi";
+ dmas = <&apbdma 15>, <&apbdma 15>;
+ dma-names = "rx", "tx";
status = "disabled";
};
spi@7000d600 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
- interrupts = <0 82 0x04>;
- nvidia,dma-request-selector = <&apbdma 16>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 44>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC2>;
+ resets = <&tegra_car 44>;
+ reset-names = "spi";
+ dmas = <&apbdma 16>, <&apbdma 16>;
+ dma-names = "rx", "tx";
status = "disabled";
};
spi@7000d800 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
- reg = <0x7000d480 0x200>;
- interrupts = <0 83 0x04>;
- nvidia,dma-request-selector = <&apbdma 17>;
+ reg = <0x7000d800 0x200>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 46>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC3>;
+ resets = <&tegra_car 46>;
+ reset-names = "spi";
+ dmas = <&apbdma 17>, <&apbdma 17>;
+ dma-names = "rx", "tx";
status = "disabled";
};
spi@7000da00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
- interrupts = <0 93 0x04>;
- nvidia,dma-request-selector = <&apbdma 18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 68>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC4>;
+ resets = <&tegra_car 68>;
+ reset-names = "spi";
+ dmas = <&apbdma 18>, <&apbdma 18>;
+ dma-names = "rx", "tx";
status = "disabled";
};
spi@7000dc00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000dc00 0x200>;
- interrupts = <0 94 0x04>;
- nvidia,dma-request-selector = <&apbdma 27>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 104>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC5>;
+ resets = <&tegra_car 104>;
+ reset-names = "spi";
+ dmas = <&apbdma 27>, <&apbdma 27>;
+ dma-names = "rx", "tx";
status = "disabled";
};
spi@7000de00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000de00 0x200>;
- interrupts = <0 79 0x04>;
- nvidia,dma-request-selector = <&apbdma 28>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&tegra_car 105>;
+ clocks = <&tegra_car TEGRA30_CLK_SBC6>;
+ resets = <&tegra_car 106>;
+ reset-names = "spi";
+ dmas = <&apbdma 28>, <&apbdma 28>;
+ dma-names = "rx", "tx";
status = "disabled";
};
+ kbc@7000e200 {
+ compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
+ reg = <0x7000e200 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_KBC>;
+ resets = <&tegra_car 36>;
+ reset-names = "kbc";
+ status = "disabled";
+ };
+
+ pmc@7000e400 {
+ compatible = "nvidia,tegra30-pmc";
+ reg = <0x7000e400 0x400>;
+ clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
+ };
+
+ mc: memory-controller@7000f000 {
+ compatible = "nvidia,tegra30-mc";
+ reg = <0x7000f000 0x400>;
+ clocks = <&tegra_car TEGRA30_CLK_MC>;
+ clock-names = "mc";
+
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <1>;
+ };
+
+ fuse@7000f800 {
+ compatible = "nvidia,tegra30-efuse";
+ reg = <0x7000f800 0x400>;
+ clocks = <&tegra_car TEGRA30_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
+
+ hda@70030000 {
+ compatible = "nvidia,tegra30-hda";
+ reg = <0x70030000 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_HDA>,
+ <&tegra_car TEGRA30_CLK_HDA2HDMI>,
+ <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
+ clock-names = "hda", "hda2hdmi", "hda2codec_2x";
+ resets = <&tegra_car 125>, /* hda */
+ <&tegra_car 128>, /* hda2hdmi */
+ <&tegra_car 111>; /* hda2codec_2x */
+ reset-names = "hda", "hda2hdmi", "hda2codec_2x";
+ status = "disabled";
+ };
+
+ ahub@70080000 {
+ compatible = "nvidia,tegra30-ahub";
+ reg = <0x70080000 0x200
+ 0x70080200 0x100>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
+ <&tegra_car TEGRA30_CLK_APBIF>;
+ clock-names = "d_audio", "apbif";
+ resets = <&tegra_car 106>, /* d_audio */
+ <&tegra_car 107>, /* apbif */
+ <&tegra_car 30>, /* i2s0 */
+ <&tegra_car 11>, /* i2s1 */
+ <&tegra_car 18>, /* i2s2 */
+ <&tegra_car 101>, /* i2s3 */
+ <&tegra_car 102>, /* i2s4 */
+ <&tegra_car 108>, /* dam0 */
+ <&tegra_car 109>, /* dam1 */
+ <&tegra_car 110>, /* dam2 */
+ <&tegra_car 10>; /* spdif */
+ reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+ "i2s3", "i2s4", "dam0", "dam1", "dam2",
+ "spdif";
+ dmas = <&apbdma 1>, <&apbdma 1>,
+ <&apbdma 2>, <&apbdma 2>,
+ <&apbdma 3>, <&apbdma 3>,
+ <&apbdma 4>, <&apbdma 4>;
+ dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+ "rx3", "tx3";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tegra_i2s0: i2s@70080300 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080300 0x100>;
+ nvidia,ahub-cif-ids = <4 4>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S0>;
+ resets = <&tegra_car 30>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s1: i2s@70080400 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080400 0x100>;
+ nvidia,ahub-cif-ids = <5 5>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S1>;
+ resets = <&tegra_car 11>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s2: i2s@70080500 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080500 0x100>;
+ nvidia,ahub-cif-ids = <6 6>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S2>;
+ resets = <&tegra_car 18>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s3: i2s@70080600 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080600 0x100>;
+ nvidia,ahub-cif-ids = <7 7>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S3>;
+ resets = <&tegra_car 101>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+
+ tegra_i2s4: i2s@70080700 {
+ compatible = "nvidia,tegra30-i2s";
+ reg = <0x70080700 0x100>;
+ nvidia,ahub-cif-ids = <8 8>;
+ clocks = <&tegra_car TEGRA30_CLK_I2S4>;
+ resets = <&tegra_car 102>;
+ reset-names = "i2s";
+ status = "disabled";
+ };
+ };
+
sdhci@78000000 {
- compatible = "nvidia,tegra30-sdhci";
+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000000 0x200>;
- interrupts = <0 14 0x04>;
- clocks = <&tegra_car 14>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
+ resets = <&tegra_car 14>;
+ reset-names = "sdhci";
status = "disabled";
};
sdhci@78000200 {
- compatible = "nvidia,tegra30-sdhci";
+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000200 0x200>;
- interrupts = <0 15 0x04>;
- clocks = <&tegra_car 9>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
+ resets = <&tegra_car 9>;
+ reset-names = "sdhci";
status = "disabled";
};
sdhci@78000400 {
- compatible = "nvidia,tegra30-sdhci";
+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000400 0x200>;
- interrupts = <0 19 0x04>;
- clocks = <&tegra_car 69>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+ resets = <&tegra_car 69>;
+ reset-names = "sdhci";
status = "disabled";
};
sdhci@78000600 {
- compatible = "nvidia,tegra30-sdhci";
+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000600 0x200>;
- interrupts = <0 31 0x04>;
- clocks = <&tegra_car 15>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
+ resets = <&tegra_car 15>;
+ reset-names = "sdhci";
status = "disabled";
};
usb@7d000000 {
- compatible = "nvidia,tegra30-ehci";
+ compatible = "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x7d000000 0x4000>;
- interrupts = <52>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
- clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
+ clocks = <&tegra_car TEGRA30_CLK_USBD>;
+ resets = <&tegra_car 22>;
+ reset-names = "usb";
+ nvidia,needs-double-reset;
+ nvidia,phy = <&phy1>;
+ status = "disabled";
+ };
+
+ phy1: usb-phy@7d000000 {
+ compatible = "nvidia,tegra30-usb-phy";
+ reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA30_CLK_USBD>,
+ <&tegra_car TEGRA30_CLK_PLL_U>,
+ <&tegra_car TEGRA30_CLK_USBD>;
+ clock-names = "reg", "pll_u", "utmi-pads";
+ resets = <&tegra_car 22>, <&tegra_car 22>;
+ reset-names = "usb", "utmi-pads";
+ nvidia,hssync-start-delay = <9>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <51>;
+ nvidia.xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <1>;
+ nvidia,xcvr-lsrslew = <1>;
+ nvidia,xcvr-hsslew = <32>;
+ nvidia,hssquelch-level = <2>;
+ nvidia,hsdiscon-level = <5>;
+ nvidia,has-utmi-pad-registers;
status = "disabled";
};
usb@7d004000 {
- compatible = "nvidia,tegra30-ehci";
+ compatible = "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x7d004000 0x4000>;
- interrupts = <53>;
- phy_type = "hsic";
- clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA30_CLK_USB2>;
+ resets = <&tegra_car 58>;
+ reset-names = "usb";
+ nvidia,phy = <&phy2>;
+ status = "disabled";
+ };
+
+ phy2: usb-phy@7d004000 {
+ compatible = "nvidia,tegra30-usb-phy";
+ reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA30_CLK_USB2>,
+ <&tegra_car TEGRA30_CLK_PLL_U>,
+ <&tegra_car TEGRA30_CLK_USBD>;
+ clock-names = "reg", "pll_u", "utmi-pads";
+ resets = <&tegra_car 58>, <&tegra_car 22>;
+ reset-names = "usb", "utmi-pads";
+ nvidia,hssync-start-delay = <9>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <51>;
+ nvidia.xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ nvidia,xcvr-hsslew = <32>;
+ nvidia,hssquelch-level = <2>;
+ nvidia,hsdiscon-level = <5>;
status = "disabled";
};
usb@7d008000 {
- compatible = "nvidia,tegra30-ehci";
+ compatible = "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x7d008000 0x4000>;
- interrupts = <129>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
- clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
+ clocks = <&tegra_car TEGRA30_CLK_USB3>;
+ resets = <&tegra_car 59>;
+ reset-names = "usb";
+ nvidia,phy = <&phy3>;
status = "disabled";
};
+
+ phy3: usb-phy@7d008000 {
+ compatible = "nvidia,tegra30-usb-phy";
+ reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA30_CLK_USB3>,
+ <&tegra_car TEGRA30_CLK_PLL_U>,
+ <&tegra_car TEGRA30_CLK_USBD>;
+ clock-names = "reg", "pll_u", "utmi-pads";
+ resets = <&tegra_car 59>, <&tegra_car 22>;
+ reset-names = "usb", "utmi-pads";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <51>;
+ nvidia.xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ nvidia,xcvr-hsslew = <32>;
+ nvidia,hssquelch-level = <2>;
+ nvidia,hsdiscon-level = <5>;
+ status = "disabled";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
deleted file mode 100644
index b0b2b57..0000000
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Device Tree Source commonly used by UniPhier ARM SoCs
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
- clocks {
- refclk: ref {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
- u-boot,dm-pre-reloc;
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart_clk>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&uart_clk>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- clocks = <&uart_clk>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- clocks = <&uart_clk>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- status = "disabled";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_system_bus>;
- };
-
- smpctrl@59800000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- mio: mioctrl@59810000 {
- /* specify compatible in each SoC DTSI */
- reg = <0x59810000 0x800>;
- #clock-cells = <1>;
- };
-
- peri: perictrl@59820000 {
- /* specify compatible in each SoC DTSI */
- reg = <0x59820000 0x200>;
- #clock-cells = <1>;
- };
-
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
- clocks = <&arm_timer_clk>;
- };
-
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
- clocks = <&arm_timer_clk>;
- };
-
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- soc-glue@5f800000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
-
- pinctrl: pinctrl {
- /* specify compatible in each SoC DTSI */
- u-boot,dm-pre-reloc;
- };
- };
-
- sysctrl: sysctrl@61840000 {
- /* specify compatible in each SoC DTSI */
- reg = <0x61840000 0x4000>;
- #clock-cells = <1>;
- clock-names = "ref";
- clocks = <&refclk>;
- };
-
- nand: nand@68000000 {
- compatible = "denali,denali-nand-dt";
- status = "disabled";
- reg-names = "nand_data", "denali_reg";
- reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- interrupts = <0 65 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
- };
- };
-};
-
-/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts
new file mode 100644
index 0000000..ea11198
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld11-ref.dts
@@ -0,0 +1,77 @@
+/*
+ * Device Tree Source for UniPhier LD11 Reference Board
+ *
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld11.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier LD11 Reference Board";
+ compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ðsc {
+ interrupts = <0 48 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_system_bus {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
new file mode 100644
index 0000000..eef4dce
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -0,0 +1,394 @@
+/*
+ * Device Tree Source for UniPhier LD11 SoC
+ *
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/memreserve/ 0x80000000 0x00080000;
+
+/ {
+ compatible = "socionext,uniphier-ld11";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x000>;
+ clocks = <&sys_clk 33>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x001>;
+ clocks = <&sys_clk 33>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+ };
+
+ cluster0_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@245000000 {
+ opp-hz = /bits/ 64 <245000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@490000000 {
+ opp-hz = /bits/ 64 <490000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@653334000 {
+ opp-hz = /bits/ 64 <653334000>;
+ clock-latency-ns = <300>;
+ };
+ opp@666667000 {
+ opp-hz = /bits/ 64 <666667000>;
+ clock-latency-ns = <300>;
+ };
+ opp@980000000 {
+ opp-hz = /bits/ 64 <980000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 4>,
+ <1 14 4>,
+ <1 11 4>,
+ <1 10 4>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ u-boot,dm-pre-reloc;
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ clock-frequency = <58820000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ clock-frequency = <58820000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ clock-frequency = <58820000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ clock-frequency = <58820000>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clocks = <&peri_clk 8>;
+ clock-frequency = <100000>;
+ };
+
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&peri_clk 9>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ sdctrl@59810000 {
+ compatible = "socionext,uniphier-ld11-sdctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x400>;
+
+ sd_rst: reset {
+ compatible = "socionext,uniphier-ld11-sd-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-ld11-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-ld11-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-ld11-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ emmc: sdhc@5a000000 {
+ compatible = "cdns,sd4hc";
+ reg = <0x5a000000 0x400>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc_1v8>;
+ clocks = <&sys_clk 4>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ /* mmc-hs400-1_8v; support depends on board design */
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 243 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 244 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 245 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
+
+ mioctrl@5b3e0000 {
+ compatible = "socionext,uniphier-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x5b3e0000 0x800>;
+
+ mio_clk: clock {
+ compatible = "socionext,uniphier-ld11-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ mio_rst: reset {
+ compatible = "socionext,uniphier-ld11-mio-reset";
+ #reset-cells = <1>;
+ resets = <&sys_rst 7>;
+ };
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-ld11-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-ld11-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ gic: interrupt-controller@5fe00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x5fe00000 0x10000>, /* GICD */
+ <0x5fe40000 0x80000>; /* GICR */
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 4>;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-ld11-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-ld11-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-ld11-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ nand-ecc-strength = <8>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts
new file mode 100644
index 0000000..044e000
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld20-ref.dts
@@ -0,0 +1,65 @@
+/*
+ * Device Tree Source for UniPhier LD20 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld20.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier LD20 Reference Board";
+ compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0xc0000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ðsc {
+ interrupts = <0 48 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_system_bus {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
new file mode 100644
index 0000000..1b41945
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -0,0 +1,446 @@
+/*
+ * Device Tree Source for UniPhier LD20 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/memreserve/ 0x80000000 0x00080000;
+
+/ {
+ compatible = "socionext,uniphier-ld20";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ core1 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x000>;
+ clocks = <&sys_clk 32>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x001>;
+ clocks = <&sys_clk 32>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x100>;
+ clocks = <&sys_clk 33>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster1_opp>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x101>;
+ clocks = <&sys_clk 33>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster1_opp>;
+ };
+ };
+
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@666667000 {
+ opp-hz = /bits/ 64 <666667000>;
+ clock-latency-ns = <300>;
+ };
+ opp@733334000 {
+ opp-hz = /bits/ 64 <733334000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@666667000 {
+ opp-hz = /bits/ 64 <666667000>;
+ clock-latency-ns = <300>;
+ };
+ opp@733334000 {
+ opp-hz = /bits/ 64 <733334000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 4>,
+ <1 14 4>,
+ <1 11 4>,
+ <1 10 4>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ u-boot,dm-pre-reloc;
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ clock-frequency = <58820000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ clock-frequency = <58820000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ clock-frequency = <58820000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ clock-frequency = <58820000>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clocks = <&peri_clk 8>;
+ clock-frequency = <100000>;
+ };
+
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&peri_clk 9>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ sdctrl@59810000 {
+ compatible = "socionext,uniphier-ld20-sdctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ sd_clk: clock {
+ compatible = "socionext,uniphier-ld20-sd-clock";
+ #clock-cells = <1>;
+ };
+
+ sd_rst: reset {
+ compatible = "socionext,uniphier-ld20-sd-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-ld20-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-ld20-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-ld20-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ emmc: sdhc@5a000000 {
+ compatible = "cdns,sd4hc";
+ reg = <0x5a000000 0x400>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc_1v8>;
+ clocks = <&sys_clk 4>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ /* mmc-hs400-1_8v; support depends on board design */
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x800>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd>;
+ clocks = <&sd_clk 0>;
+ reset-names = "host";
+ resets = <&sd_rst 0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-ld20-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-ld20-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ gic: interrupt-controller@5fe00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x5fe00000 0x10000>, /* GICD */
+ <0x5fe80000 0x80000>; /* GICR */
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 4>;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-ld20-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-ld20-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-ld20-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ usb: usb@65b00000 {
+ compatible = "socionext,uniphier-ld20-dwc3";
+ reg = <0x65b00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
+ <&pinctrl_usb2>, <&pinctrl_usb3>;
+ dwc3@65a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65a00000 0x10000>;
+ interrupts = <0 134 4>;
+ tx-fifo-resize;
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ nand-ecc-strength = <8>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-ld4-ref.dts b/arch/arm/dts/uniphier-ld4-ref.dts
new file mode 100644
index 0000000..0f4bd9b
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld4-ref.dts
@@ -0,0 +1,79 @@
+/*
+ * Device Tree Source for UniPhier LD4 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld4.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier LD4 Reference Board";
+ compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+ðsc {
+ interrupts = <0 49 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&serial3 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
new file mode 100644
index 0000000..bbfa164
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -0,0 +1,462 @@
+/*
+ * Device Tree Source for UniPhier LD4 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-ld4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+ u-boot,dm-pre-reloc;
+
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(512 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ clock-frequency = <36864000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ clock-frequency = <36864000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ clock-frequency = <36864000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 29 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ clock-frequency = <36864000>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port16x: gpio@55000088 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000088 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
+
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-ld4-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ mio_clk: clock {
+ compatible = "socionext,uniphier-ld4-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ mio_rst: reset {
+ compatible = "socionext,uniphier-ld4-mio-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-ld4-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-ld4-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-ld4-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
+
+ emmc: sdhc@5a500000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a500000 0x200>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_emmc>;
+ pinctrl-1 = <&pinctrl_emmc_1v8>;
+ clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 1>, <&mio_rst 4>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-ld4-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-ld4-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ aidet@61830000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x61830000 0x200>;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-ld4-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-ld4-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-ld4-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,denali-nand-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ nand-ecc-strength = <8>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-ld6b-ref.dts b/arch/arm/dts/uniphier-ld6b-ref.dts
new file mode 100644
index 0000000..4da3c63
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld6b-ref.dts
@@ -0,0 +1,81 @@
+/*
+ * Device Tree Source for UniPhier LD6b Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld6b.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier LD6b Reference Board";
+ compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+ðsc {
+ interrupts = <0 52 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-ld6b.dtsi b/arch/arm/dts/uniphier-ld6b.dtsi
new file mode 100644
index 0000000..9870047
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld6b.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Device Tree Source for UniPhier LD6b SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/*
+ * LD6b consists of two silicon dies: D-chip and A-chip.
+ * The D-chip (digital chip) is the same as the PXs2 die.
+ * Reuse the PXs2 device tree with some properties overridden.
+ */
+/include/ "uniphier-pxs2.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-ld6b";
+};
+
+/* UART3 unavailable: the pads are not wired to the package balls */
+&serial3 {
+ status = "disabled";
+};
+
+/*
+ * LD6b and PXs2 have completely different packages,
+ * which makes the pinctrl driver unshareable.
+ */
+&pinctrl {
+ compatible = "socionext,uniphier-ld6b-pinctrl";
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
deleted file mode 100644
index 4eb7664..0000000
--- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-LD11 Reference Board
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-ld11.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-LD11 Reference Board";
- compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11";
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- };
-
- memory {
- device_type = "memory";
- reg = <0 0x80000000 0 0x40000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-ðsc {
- interrupts = <0 48 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi
deleted file mode 100644
index ffe04f5..0000000
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-LD11 SoC
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
-
-/ {
- compatible = "socionext,ph1-ld11";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&gic>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- };
- };
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0 0x000>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0 0x001>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
- };
-
- clocks {
- refclk: ref {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- uart_clk: uart_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <58820000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 13 0xf01>,
- <1 14 0xf01>,
- <1 11 0xf01>,
- <1 10 0xf01>;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0xffffffff>;
- u-boot,dm-pre-reloc;
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart_clk>;
- clock-frequency = <58820000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&uart_clk>;
- clock-frequency = <58820000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- clocks = <&uart_clk>;
- clock-frequency = <58820000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- clocks = <&uart_clk>;
- clock-frequency = <58820000>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- status = "disabled";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_system_bus>;
- };
-
- smpctrl@59800000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 243 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio 3>, <&mio 6>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 244 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio 4>, <&mio 6>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 245 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio 5>, <&mio 6>;
- };
-
- mio: mioctrl@5b3e0000 {
- compatible = "socionext,ph1-ld11-mioctrl";
- reg = <0x5b3e0000 0x800>;
- #clock-cells = <1>;
- };
-
- soc-glue@5f800000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
-
- pinctrl: pinctrl {
- compatible = "socionext,uniphier-ld11-pinctrl";
- u-boot,dm-pre-reloc;
- };
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- gic: interrupt-controller@5fe00000 {
- compatible = "arm,gic-v3";
- reg = <0x5fe00000 0x10000>, /* GICD */
- <0x5fe40000 0x80000>; /* GICR */
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <1 9 4>;
- };
- };
-};
-
-/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
deleted file mode 100644
index 90c8705..0000000
--- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-LD20 Reference Board
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-ld20.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-LD20 Reference Board";
- compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- };
-
- memory {
- device_type = "memory";
- reg = <0 0x80000000 0 0xc0000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-ðsc {
- interrupts = <0 48 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi
deleted file mode 100644
index 7497539..0000000
--- a/arch/arm/dts/uniphier-ph1-ld20.dtsi
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-LD20 SoC
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
-
-/ {
- compatible = "socionext,ph1-ld20";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&gic>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&cpu2>;
- };
- core1 {
- cpu = <&cpu3>;
- };
- };
- };
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0 0x000>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0 0x001>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
-
- cpu2: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0 0x100>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
-
- cpu3: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0 0x101>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x80000000>;
- };
- };
-
- clocks {
- refclk: ref {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- uart_clk: uart_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <58820000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 13 0xf01>,
- <1 14 0xf01>,
- <1 11 0xf01>,
- <1 10 0xf01>;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0xffffffff>;
- u-boot,dm-pre-reloc;
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart_clk>;
- clock-frequency = <58820000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&uart_clk>;
- clock-frequency = <58820000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- clocks = <&uart_clk>;
- clock-frequency = <58820000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- clocks = <&uart_clk>;
- clock-frequency = <58820000>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- status = "disabled";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_system_bus>;
- };
-
- smpctrl@59800000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- mio: mioctrl@59810000 {
- compatible = "socionext,ph1-ld20-mioctrl";
- reg = <0x59810000 0x800>;
- #clock-cells = <1>;
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sd>;
- clocks = <&mio 0>;
- bus-width = <4>;
- };
-
- soc-glue@5f800000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
-
- pinctrl: pinctrl {
- compatible = "socionext,uniphier-ld20-pinctrl";
- u-boot,dm-pre-reloc;
- };
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- gic: interrupt-controller@5fe00000 {
- compatible = "arm,gic-v3";
- reg = <0x5fe00000 0x10000>, /* GICD */
- <0x5fe80000 0x80000>; /* GICR */
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <1 9 4>;
- };
- };
-};
-
-/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
deleted file mode 100644
index 36de7e3..0000000
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-LD4 Reference Board
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-ld4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-LD4 Reference Board";
- compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- };
-};
-
-ðsc {
- interrupts = <0 49 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&serial3 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
deleted file mode 100644
index 07f315a..0000000
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-LD4 SoC
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,ph1-ld4";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- uart_clk: uart_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <36864000>;
- };
-
- iobus_clk: iobus_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(512 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
-
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio 0>;
- bus-width = <4>;
- };
-
- emmc: sdhc@5a500000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_emmc>;
- pinctrl-1 = <&pinctrl_emmc_1v8>;
- clocks = <&mio 1>;
- bus-width = <8>;
- non-removable;
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio 3>, <&mio 6>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio 4>, <&mio 6>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio 5>, <&mio 6>;
- };
-
- aidet@61830000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x61830000 0x200>;
- };
-};
-
-&refclk {
- clock-frequency = <24576000>;
-};
-
-&serial0 {
- clock-frequency = <36864000>;
-};
-
-&serial1 {
- clock-frequency = <36864000>;
-};
-
-&serial2 {
- clock-frequency = <36864000>;
-};
-
-&serial3 {
- interrupts = <0 29 4>;
- clock-frequency = <36864000>;
-};
-
-&mio {
- compatible = "socionext,ph1-ld4-mioctrl";
- clock-names = "stdmac", "ehci";
- clocks = <&sysctrl 10>, <&sysctrl 18>;
-};
-
-&peri {
- compatible = "socionext,ph1-ld4-perictrl";
- clock-names = "uart", "i2c";
- clocks = <&sysctrl 3>, <&sysctrl 4>;
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-ld4-pinctrl";
-};
-
-&sysctrl {
- compatible = "socionext,ph1-ld4-sysctrl";
-};
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
deleted file mode 100644
index e29a6ea..0000000
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-LD6b Reference Board
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-ld6b.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-LD6b Reference Board";
- compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-ðsc {
- interrupts = <0 52 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/dts/uniphier-ph1-ld6b.dtsi
deleted file mode 100644
index e8110ee..0000000
--- a/arch/arm/dts/uniphier-ph1-ld6b.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-LD6b SoC
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/*
- * PH1-LD6b consists of two silicon dies: D-chip and A-chip.
- * The D-chip (digital chip) is the same as the ProXstream2 die.
- * Reuse the ProXstream2 device tree with some properties overridden.
- */
-/include/ "uniphier-proxstream2.dtsi"
-
-/ {
- compatible = "socionext,ph1-ld6b";
-};
-
-/* UART3 unavailable: the pads are not wired to the package balls */
-&serial3 {
- status = "disabled";
-};
-
-/*
- * PH1-LD6b and ProXstream2 have completely different packages,
- * which makes the pinctrl driver unshareable.
- */
-&pinctrl {
- compatible = "socionext,uniphier-ld6b-pinctrl";
-};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/dts/uniphier-ph1-pro4-ace.dts
deleted file mode 100644
index d8740cc..0000000
--- a/arch/arm/dts/uniphier-ph1-pro4-ace.dts
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-Pro4 Ace Board
- *
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-pro4.dtsi"
-
-/ {
- model = "UniPhier PH1-Pro4 Ace Board";
- compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- eeprom {
- compatible = "24c64", "i2c-eeprom";
- reg = <0x54>;
- u-boot,i2c-offset-len = <2>;
- };
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
deleted file mode 100644
index 4a2de08..0000000
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-Pro4 Reference Board
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-pro4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-Pro4 Reference Board";
- compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- usb0 = &usb0;
- };
-};
-
-ðsc {
- interrupts = <0 50 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&sd1 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
deleted file mode 100644
index 965fe08..0000000
--- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-Pro4 Sanji Board
- *
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-pro4.dtsi"
-
-/ {
- model = "UniPhier PH1-Pro4 Sanji Board";
- compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- eeprom {
- compatible = "24c64", "i2c-eeprom";
- reg = <0x54>;
- u-boot,i2c-offset-len = <2>;
- };
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&mio {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
deleted file mode 100644
index e0b28b8..0000000
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ /dev/null
@@ -1,465 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-Pro4 SoC
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,ph1-pro4";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- uart_clk: uart_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <73728000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(768 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port17x: gpio@550000a0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port18x: gpio@550000a8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port19x: gpio@550000b0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port20x: gpio@550000b8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port21x: gpio@550000c0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port22x: gpio@550000c8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port23x: gpio@550000d0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port24x: gpio@550000d8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port25x: gpio@550000e0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port26x: gpio@550000e8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port27x: gpio@550000f0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port28x: gpio@550000f8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port29x: gpio@55000100 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000100 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port30x: gpio@55000108 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000108 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- /* i2c4 does not exist */
-
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio 0>;
- bus-width = <4>;
- };
-
- emmc: sdhc@5a500000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_emmc>;
- pinctrl-1 = <&pinctrl_emmc_1v8>;
- clocks = <&mio 1>;
- bus-width = <8>;
- non-removable;
- };
-
- sd1: sdhc@5a600000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a600000 0x200>;
- interrupts = <0 85 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd1>;
- pinctrl-1 = <&pinctrl_sd1_1v8>;
- clocks = <&mio 2>;
- bus-width = <4>;
- };
-
- usb2: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio 3>, <&mio 6>;
- };
-
- usb3: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- clocks = <&mio 4>, <&mio 6>;
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- interrupts = <0 134 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- };
-
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- interrupts = <0 137 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- };
-};
-
-&refclk {
- clock-frequency = <25000000>;
-};
-
-&serial0 {
- clock-frequency = <73728000>;
-};
-
-&serial1 {
- clock-frequency = <73728000>;
-};
-
-&serial2 {
- clock-frequency = <73728000>;
-};
-
-&serial3 {
- clock-frequency = <73728000>;
-};
-
-&mio {
- compatible = "socionext,ph1-pro4-mioctrl";
- clock-names = "stdmac", "ehci";
- clocks = <&sysctrl 10>, <&sysctrl 18>;
-};
-
-&peri {
- compatible = "socionext,ph1-pro4-perictrl";
- clock-names = "uart", "fi2c";
- clocks = <&sysctrl 3>, <&sysctrl 4>;
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-pro4-pinctrl";
-};
-
-&sysctrl {
- compatible = "socionext,ph1-pro4-sysctrl";
-};
diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
deleted file mode 100644
index 682b795..0000000
--- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-pro5.dtsi"
-
-/ {
- model = "UniPhier PH1-Pro5 4KBOX Board";
- compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- chosen {
- stdout-path = "serial1:115200n8";
- };
-
- aliases {
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial1 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
deleted file mode 100644
index 05f961f..0000000
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ /dev/null
@@ -1,444 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-Pro5 SoC
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,ph1-pro5";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- uart_clk: uart_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <73728000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
- interrupts = <0 190 4>, <0 191 4>;
- cache-unified;
- cache-size = <(2 * 1024 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <128>;
- cache-level = <2>;
- next-level-cache = <&l3>;
- };
-
- l3: l3-cache@500c8000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(2 * 1024 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <256>;
- cache-level = <3>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port17x: gpio@550000a0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port18x: gpio@550000a8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port19x: gpio@550000b0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port20x: gpio@550000b8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port21x: gpio@550000c0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port22x: gpio@550000c8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port23x: gpio@550000d0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port24x: gpio@550000d8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port25x: gpio@550000e0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port26x: gpio@550000e8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port27x: gpio@550000f0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port28x: gpio@550000f8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port29x: gpio@55000100 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000100 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port30x: gpio@55000108 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000108 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- /* i2c4 does not exist */
-
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- emmc: sdhc@68400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x68400000 0x800>;
- interrupts = <0 78 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_emmc>;
- clocks = <&mio 1>;
- bus-width = <8>;
- non-removable;
- };
-
- sd: sdhc@68800000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x68800000 0x800>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio 0>;
- bus-width = <4>;
- };
-
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- interrupts = <0 134 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- };
-
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- interrupts = <0 137 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
- };
-};
-
-&refclk {
- clock-frequency = <20000000>;
-};
-
-&serial0 {
- clock-frequency = <73728000>;
-};
-
-&serial1 {
- clock-frequency = <73728000>;
-};
-
-&serial2 {
- clock-frequency = <73728000>;
-};
-
-&serial3 {
- clock-frequency = <73728000>;
-};
-
-&mio {
- compatible = "socionext,ph1-pro5-mioctrl";
- clock-names = "stdmac";
- clocks = <&sysctrl 10>;
-};
-
-&peri {
- compatible = "socionext,ph1-pro5-perictrl";
- clock-names = "uart", "fi2c";
- clocks = <&sysctrl 3>, <&sysctrl 4>;
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-pro5-pinctrl";
-};
-
-&sysctrl {
- compatible = "socionext,ph1-pro5-sysctrl";
-};
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
deleted file mode 100644
index 0863588..0000000
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-sLD3 Reference Board
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-sld3.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-sLD3 Reference Board";
- compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000
- 0xc0000000 0x20000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- };
-};
-
-ðsc {
- interrupts = <0 49 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&mio {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
deleted file mode 100644
index 6a95541..0000000
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-sLD3 SoC
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
- compatible = "socionext,ph1-sld3";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- };
- };
-
- clocks {
- refclk: ref {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24576000>;
- };
-
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- uart_clk: uart_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <36864000>;
- };
-
- iobus_clk: iobus_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
- u-boot,dm-pre-reloc;
-
- timer@20000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x20000200 0x20>;
- interrupts = <1 11 0x304>;
- clocks = <&arm_timer_clk>;
- };
-
- timer@20000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x20000600 0x20>;
- interrupts = <1 13 0x304>;
- clocks = <&arm_timer_clk>;
- };
-
- intc: interrupt-controller@20001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x20001000 0x1000>,
- <0x20000100 0x100>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c4: i2c@58600000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58600000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- smpctrl@59800000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- mio: mioctrl@59810000 {
- compatible = "socionext,ph1-sld3-mioctrl";
- reg = <0x59810000 0x800>;
- #clock-cells = <1>;
- clock-names = "stdmac", "ehci";
- clocks = <&sysctrl 10>, <&sysctrl 18>;
- };
-
- emmc: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x200>;
- interrupts = <0 78 4>;
- clocks = <&mio 1>;
- bus-width = <8>;
- non-removable;
- };
-
- sd: sdhc@5a500000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a500000 0x200>;
- interrupts = <0 76 4>;
- clocks = <&mio 0>;
- bus-width = <4>;
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- clocks = <&mio 3>, <&mio 6>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- clocks = <&mio 4>, <&mio 6>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- clocks = <&mio 5>, <&mio 6>;
- };
-
- usb3: usb@5a830100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a830100 0x100>;
- interrupts = <0 83 4>;
- clocks = <&mio 7>, <&mio 6>;
- };
-
- aidet@f1830000 {
- compatible = "simple-mfd", "syscon";
- reg = <0xf1830000 0x200>;
- };
-
- sysctrl: sysctrl@f1840000 {
- compatible = "socionext,ph1-sld3-sysctrl";
- reg = <0xf1840000 0x4000>;
- #clock-cells = <1>;
- clock-names = "ref";
- clocks = <&refclk>;
- };
-
- nand: nand@f8000000 {
- compatible = "denali,denali-nand-dt";
- reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- };
- };
-};
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
deleted file mode 100644
index 9af012c..0000000
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-sLD8 Reference Board
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/dts-v1/;
-/include/ "uniphier-ph1-sld8.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier PH1-sLD8 Reference Board";
- compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- };
-};
-
-ðsc {
- interrupts = <0 48 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&serial3 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
deleted file mode 100644
index e0376a1..0000000
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-sLD8 SoC
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,ph1-sld8";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- uart_clk: uart_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <80000000>;
- };
-
- iobus_clk: iobus_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(256 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
-
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio 0>;
- bus-width = <4>;
- };
-
- emmc: sdhc@5a500000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- interrupts = <0 78 4>;
- reg = <0x5a500000 0x200>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_emmc>;
- pinctrl-1 = <&pinctrl_emmc_1v8>;
- clocks = <&mio 1>;
- bus-width = <8>;
- non-removable;
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio 3>, <&mio 6>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio 4>, <&mio 6>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio 5>, <&mio 6>;
- };
-
- aidet@61830000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x61830000 0x200>;
- };
-};
-
-&refclk {
- clock-frequency = <25000000>;
-};
-
-&serial0 {
- clock-frequency = <80000000>;
-};
-
-&serial1 {
- clock-frequency = <80000000>;
-};
-
-&serial2 {
- clock-frequency = <80000000>;
-};
-
-&serial3 {
- interrupts = <0 29 4>;
- clock-frequency = <80000000>;
-};
-
-&mio {
- compatible = "socionext,ph1-sld8-mioctrl";
- clock-names = "stdmac", "ehci";
- clocks = <&sysctrl 10>, <&sysctrl 18>;
-};
-
-&peri {
- compatible = "socionext,ph1-sld8-perictrl";
- clock-names = "uart", "i2c";
- clocks = <&sysctrl 3>, <&sysctrl 4>;
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-sld8-pinctrl";
-};
-
-&sysctrl {
- compatible = "socionext,ph1-sld8-sysctrl";
-};
diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts
new file mode 100644
index 0000000..f70bc82
--- /dev/null
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -0,0 +1,100 @@
+/*
+ * Device Tree Source for UniPhier Pro4 Ace Board
+ *
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-pro4.dtsi"
+
+/ {
+ model = "UniPhier Pro4 Ace Board";
+ compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "st,24c64", "i2c-eeprom";
+ reg = <0x54>;
+ u-boot,i2c-offset-len = <2>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts
new file mode 100644
index 0000000..9714fb0
--- /dev/null
+++ b/arch/arm/dts/uniphier-pro4-ref.dts
@@ -0,0 +1,94 @@
+/*
+ * Device Tree Source for UniPhier Pro4 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-pro4.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier Pro4 Reference Board";
+ compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ usb0 = &usb0;
+ };
+};
+
+ðsc {
+ interrupts = <0 50 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&sd1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts
new file mode 100644
index 0000000..d43f725
--- /dev/null
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -0,0 +1,107 @@
+/*
+ * Device Tree Source for UniPhier Pro4 Sanji Board
+ *
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-pro4.dtsi"
+
+/ {
+ model = "UniPhier Pro4 Sanji Board";
+ compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "st,24c64", "i2c-eeprom";
+ reg = <0x54>;
+ u-boot,i2c-offset-len = <2>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&mio_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_emmc {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
new file mode 100644
index 0000000..9b881f6
--- /dev/null
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -0,0 +1,625 @@
+/*
+ * Device Tree Source for UniPhier Pro4 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-pro4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+ u-boot,dm-pre-reloc;
+
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(768 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ clock-frequency = <73728000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ clock-frequency = <73728000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ clock-frequency = <73728000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ clock-frequency = <73728000>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port17x: gpio@550000a0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port18x: gpio@550000a8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port19x: gpio@550000b0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port20x: gpio@550000b8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port21x: gpio@550000c0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port22x: gpio@550000c8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port23x: gpio@550000d0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port24x: gpio@550000d8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port25x: gpio@550000e0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port26x: gpio@550000e8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port27x: gpio@550000f0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port28x: gpio@550000f8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port29x: gpio@55000100 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000100 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port30x: gpio@55000108 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000108 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
+
+ /* i2c4 does not exist */
+
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&peri_clk 9>;
+ clock-frequency = <400000>;
+ };
+
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&peri_clk 10>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-pro4-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+ u-boot,dm-pre-reloc;
+
+ mio_clk: clock {
+ compatible = "socionext,uniphier-pro4-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ mio_rst: reset {
+ compatible = "socionext,uniphier-pro4-mio-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-pro4-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-pro4-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-pro4-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
+
+ emmc: sdhc@5a500000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a500000 0x200>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_emmc>;
+ pinctrl-1 = <&pinctrl_emmc_1v8>;
+ clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 1>, <&mio_rst 4>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ };
+
+ sd1: sdhc@5a600000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a600000 0x200>;
+ interrupts = <0 85 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd1>;
+ pinctrl-1 = <&pinctrl_sd1_1v8>;
+ clocks = <&mio_clk 2>;
+ resets = <&mio_rst 2>, <&mio_rst 5>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
+
+ usb2: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb3: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pro4-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pro4-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-pro4-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-pro4-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-pro4-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ usb0: usb@65b00000 {
+ compatible = "socionext,uniphier-pro4-dwc3";
+ status = "disabled";
+ reg = <0x65b00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ dwc3@65a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65a00000 0x10000>;
+ interrupts = <0 134 4>;
+ tx-fifo-resize;
+ };
+ };
+
+ usb1: usb@65d00000 {
+ compatible = "socionext,uniphier-pro4-dwc3";
+ status = "disabled";
+ reg = <0x65d00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ dwc3@65c00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65c00000 0x10000>;
+ interrupts = <0 137 4>;
+ tx-fifo-resize;
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,denali-nand-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ nand-ecc-strength = <8>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-pro5-4kbox.dts b/arch/arm/dts/uniphier-pro5-4kbox.dts
new file mode 100644
index 0000000..ffc21a7
--- /dev/null
+++ b/arch/arm/dts/uniphier-pro5-4kbox.dts
@@ -0,0 +1,66 @@
+/*
+ * Device Tree Source for UniPhier Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-pro5.dtsi"
+
+/ {
+ model = "UniPhier Pro5 4KBOX Board";
+ compatible = "socionext,uniphier-pro5-4kbox", "socionext,uniphier-pro5";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ aliases {
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial1 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
new file mode 100644
index 0000000..68866e1
--- /dev/null
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -0,0 +1,671 @@
+/*
+ * Device Tree Source for UniPhier Pro5 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-pro5";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ clocks = <&sys_clk 32>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ clocks = <&sys_clk 32>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ };
+ };
+
+ cpu_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@116667000 {
+ opp-hz = /bits/ 64 <116667000>;
+ clock-latency-ns = <300>;
+ };
+ opp@150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@175000000 {
+ opp-hz = /bits/ 64 <175000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@233334000 {
+ opp-hz = /bits/ 64 <233334000>;
+ clock-latency-ns = <300>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@466667000 {
+ opp-hz = /bits/ 64 <466667000>;
+ clock-latency-ns = <300>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@933334000 {
+ opp-hz = /bits/ 64 <933334000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+ u-boot,dm-pre-reloc;
+
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+ <0x506c0000 0x400>;
+ interrupts = <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ next-level-cache = <&l3>;
+ };
+
+ l3: l3-cache@500c8000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
+ <0x506c8000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <256>;
+ cache-level = <3>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ clock-frequency = <73728000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ clock-frequency = <73728000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ clock-frequency = <73728000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ clock-frequency = <73728000>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port17x: gpio@550000a0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port18x: gpio@550000a8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port19x: gpio@550000b0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port20x: gpio@550000b8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port21x: gpio@550000c0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port22x: gpio@550000c8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port23x: gpio@550000d0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port24x: gpio@550000d8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port25x: gpio@550000e0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port26x: gpio@550000e8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port27x: gpio@550000f0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port28x: gpio@550000f8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port29x: gpio@55000100 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000100 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port30x: gpio@55000108 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000108 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
+
+ /* i2c4 does not exist */
+
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&peri_clk 9>;
+ clock-frequency = <400000>;
+ };
+
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&peri_clk 10>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ sdctrl@59810000 {
+ compatible = "socionext,uniphier-pro5-sdctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+ u-boot,dm-pre-reloc;
+
+ sd_clk: clock {
+ compatible = "socionext,uniphier-pro5-sd-clock";
+ #clock-cells = <1>;
+ };
+
+ sd_rst: reset {
+ compatible = "socionext,uniphier-pro5-sd-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-pro5-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-pro5-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-pro5-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pro5-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pro5-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-pro5-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-pro5-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-pro5-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ usb0: usb@65b00000 {
+ compatible = "socionext,uniphier-pro5-dwc3";
+ status = "disabled";
+ reg = <0x65b00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ dwc3@65a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65a00000 0x10000>;
+ interrupts = <0 134 4>;
+ tx-fifo-resize;
+ };
+ };
+
+ usb1: usb@65d00000 {
+ compatible = "socionext,uniphier-pro5-dwc3";
+ status = "disabled";
+ reg = <0x65d00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
+ dwc3@65c00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65c00000 0x10000>;
+ interrupts = <0 137 4>;
+ tx-fifo-resize;
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ nand-ecc-strength = <8>;
+ };
+
+ emmc: sdhc@68400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x68400000 0x800>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc>;
+ clocks = <&sd_clk 1>;
+ reset-names = "host";
+ resets = <&sd_rst 1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ no-3-3-v;
+ };
+
+ sd: sdhc@68800000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x68800000 0x800>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&sd_clk 0>;
+ reset-names = "host";
+ resets = <&sd_rst 0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
deleted file mode 100644
index 1175703..0000000
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Device Tree Source for UniPhier ProXstream2 Gentil Board
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-/include/ "uniphier-proxstream2.dtsi"
-
-/ {
- model = "UniPhier ProXstream2 Gentil Board";
- compatible = "socionext,proxstream2-gentil", "socionext,proxstream2";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial2;
- serial1 = &serial0;
- serial2 = &serial1;
- i2c0 = &i2c0;
- i2c2 = &i2c2;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- eeprom {
- compatible = "24c64", "i2c-eeprom";
- reg = <0x54>;
- u-boot,i2c-offset-len = <2>;
- };
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial2 {
- u-boot,dm-pre-reloc;
-};
-
-&mio {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts
deleted file mode 100644
index 928a092..0000000
--- a/arch/arm/dts/uniphier-proxstream2-vodka.dts
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Device Tree Source for UniPhier ProXstream2 Vodka Board
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-/include/ "uniphier-proxstream2.dtsi"
-
-/ {
- model = "UniPhier ProXstream2 Vodka Board";
- compatible = "socionext,proxstream2-vodka", "socionext,proxstream2";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial2;
- serial1 = &serial0;
- serial2 = &serial1;
- i2c0 = &i2c0;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- };
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial2 {
- u-boot,dm-pre-reloc;
-};
-
-&mio {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
deleted file mode 100644
index 23a6bfa..0000000
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ /dev/null
@@ -1,448 +0,0 @@
-/*
- * Device Tree Source for UniPhier ProXstream2 SoC
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/include/ "uniphier-common32.dtsi"
-
-/ {
- compatible = "socionext,proxstream2";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- next-level-cache = <&l2>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- next-level-cache = <&l2>;
- };
-
- cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <2>;
- next-level-cache = <&l2>;
- };
-
- cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <3>;
- next-level-cache = <&l2>;
- };
- };
-
- clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- uart_clk: uart_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <88900000>;
- };
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
- cache-unified;
- cache-size = <(1280 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port15x: gpio@55000080 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000080 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port17x: gpio@550000a0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port18x: gpio@550000a8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port19x: gpio@550000b0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port20x: gpio@550000b8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port21x: gpio@550000c0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port22x: gpio@550000c8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port23x: gpio@550000d0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port24x: gpio@550000d8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port25x: gpio@550000e0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port26x: gpio@550000e8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port27x: gpio@550000f0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port28x: gpio@550000f8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- /* chip-internal connection for STM */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
-
- emmc: sdhc@5a000000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a000000 0x800>;
- interrupts = <0 78 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_emmc>;
- clocks = <&mio 1>;
- bus-width = <8>;
- non-removable;
- };
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio 0>;
- bus-width = <4>;
- };
-
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
-
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- interrupts = <0 134 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
- };
-
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- interrupts = <0 137 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
- };
-};
-
-&refclk {
- clock-frequency = <25000000>;
-};
-
-&serial0 {
- clock-frequency = <88900000>;
-};
-
-&serial1 {
- clock-frequency = <88900000>;
-};
-
-&serial2 {
- clock-frequency = <88900000>;
-};
-
-&serial3 {
- clock-frequency = <88900000>;
-};
-
-&mio {
- compatible = "socionext,proxstream2-mioctrl";
- clock-names = "stdmac";
- clocks = <&sysctrl 10>;
-};
-
-&peri {
- compatible = "socionext,proxstream2-perictrl";
- clock-names = "uart", "fi2c";
- clocks = <&sysctrl 3>, <&sysctrl 4>;
-};
-
-&pinctrl {
- compatible = "socionext,uniphier-pxs2-pinctrl";
-};
-
-&sysctrl {
- compatible = "socionext,proxstream2-sysctrl";
-};
diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts
new file mode 100644
index 0000000..0a6d46c
--- /dev/null
+++ b/arch/arm/dts/uniphier-pxs2-gentil.dts
@@ -0,0 +1,88 @@
+/*
+ * Device Tree Source for UniPhier PXs2 Gentil Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-pxs2.dtsi"
+
+/ {
+ model = "UniPhier PXs2 Gentil Board";
+ compatible = "socionext,uniphier-pxs2-gentil",
+ "socionext,uniphier-pxs2";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial2;
+ serial1 = &serial0;
+ serial2 = &serial1;
+ i2c0 = &i2c0;
+ i2c2 = &i2c2;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "st,24c64", "i2c-eeprom";
+ reg = <0x54>;
+ u-boot,i2c-offset-len = <2>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial2 {
+ u-boot,dm-pre-reloc;
+};
+
+&sd_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_emmc {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-pxs2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts
new file mode 100644
index 0000000..770edca
--- /dev/null
+++ b/arch/arm/dts/uniphier-pxs2-vodka.dts
@@ -0,0 +1,72 @@
+/*
+ * Device Tree Source for UniPhier PXs2 Vodka Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-pxs2.dtsi"
+
+/ {
+ model = "UniPhier PXs2 Vodka Board";
+ compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial2;
+ serial1 = &serial0;
+ serial2 = &serial1;
+ i2c0 = &i2c0;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial2 {
+ u-boot,dm-pre-reloc;
+};
+
+&sd_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_emmc {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
new file mode 100644
index 0000000..da62070
--- /dev/null
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -0,0 +1,654 @@
+/*
+ * Device Tree Source for UniPhier PXs2 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-pxs2";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ clocks = <&sys_clk 32>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ clocks = <&sys_clk 32>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <2>;
+ clocks = <&sys_clk 32>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <3>;
+ clocks = <&sys_clk 32>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ };
+ };
+
+ cpu_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ clock-latency-ns = <300>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ i2c_clk: i2c_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+ u-boot,dm-pre-reloc;
+
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(1280 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ clock-frequency = <88900000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ clock-frequency = <88900000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ clock-frequency = <88900000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ clock-frequency = <88900000>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port15x: gpio@55000080 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000080 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port16x: gpio@55000088 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000088 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port17x: gpio@550000a0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port18x: gpio@550000a8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000a8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port19x: gpio@550000b0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port20x: gpio@550000b8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000b8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port21x: gpio@550000c0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port22x: gpio@550000c8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000c8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port23x: gpio@550000d0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port24x: gpio@550000d8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000d8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port25x: gpio@550000e0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port26x: gpio@550000e8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000e8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port27x: gpio@550000f0 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f0 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port28x: gpio@550000f8 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x550000f8 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ /* chip-internal connection for DMD */
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ /* chip-internal connection for STM */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ sdctrl@59810000 {
+ compatible = "socionext,uniphier-pxs2-sdctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+ u-boot,dm-pre-reloc;
+
+ sd_clk: clock {
+ compatible = "socionext,uniphier-pxs2-sd-clock";
+ #clock-cells = <1>;
+ };
+
+ sd_rst: reset {
+ compatible = "socionext,uniphier-pxs2-sd-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-pxs2-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-pxs2-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-pxs2-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ emmc: sdhc@5a000000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a000000 0x800>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc>;
+ clocks = <&sd_clk 1>;
+ reset-names = "host";
+ resets = <&sd_rst 1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ no-3-3-v;
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x800>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&sd_clk 0>;
+ reset-names = "host";
+ resets = <&sd_rst 0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pxs2-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pxs2-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ aidet@5fc20000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x5fc20000 0x200>;
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0xf04>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0xf04>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-pxs2-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x4000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-pxs2-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-pxs2-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ usb0: usb@65b00000 {
+ compatible = "socionext,uniphier-pxs2-dwc3";
+ status = "disabled";
+ reg = <0x65b00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+ dwc3@65a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65a00000 0x10000>;
+ interrupts = <0 134 4>;
+ tx-fifo-resize;
+ };
+ };
+
+ usb1: usb@65d00000 {
+ compatible = "socionext,uniphier-pxs2-dwc3";
+ status = "disabled";
+ reg = <0x65d00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+ dwc3@65c00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65c00000 0x10000>;
+ interrupts = <0 137 4>;
+ tx-fifo-resize;
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ nand-ecc-strength = <8>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-sld3-ref.dts b/arch/arm/dts/uniphier-sld3-ref.dts
new file mode 100644
index 0000000..f35500d
--- /dev/null
+++ b/arch/arm/dts/uniphier-sld3-ref.dts
@@ -0,0 +1,100 @@
+/*
+ * Device Tree Source for UniPhier sLD3 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-sld3.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier sLD3 Reference Board";
+ compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000
+ 0xc0000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+};
+
+ðsc {
+ interrupts = <0 49 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_emmc {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi
new file mode 100644
index 0000000..919cbff
--- /dev/null
+++ b/arch/arm/dts/uniphier-sld3.dtsi
@@ -0,0 +1,455 @@
+/*
+ * Device Tree Source for UniPhier sLD3 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-sld3";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24576000>;
+ };
+
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+ u-boot,dm-pre-reloc;
+
+ timer@20000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x20000200 0x20>;
+ interrupts = <1 11 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@20000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x20000600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@20001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x20001000 0x1000>,
+ <0x20000100 0x100>;
+ };
+
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(512 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clock-frequency = <36864000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clock-frequency = <36864000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clock-frequency = <36864000>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port16x: gpio@55000088 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000088 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&sys_clk 1>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ clocks = <&sys_clk 1>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ clocks = <&sys_clk 1>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ clocks = <&sys_clk 1>;
+ clock-frequency = <100000>;
+ };
+
+ /* chip-internal connection for DMD */
+ i2c4: i2c@58600000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58600000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 1>;
+ clocks = <&sys_clk 1>;
+ clock-frequency = <400000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+ u-boot,dm-pre-reloc;
+
+ mio_clk: clock {
+ compatible = "socionext,uniphier-sld3-mio-clock";
+ #clock-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ mio_rst: reset {
+ compatible = "socionext,uniphier-sld3-mio-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ emmc: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_emmc>;
+ pinctrl-1 = <&pinctrl_emmc_1v8>;
+ clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 1>, <&mio_rst 4>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ };
+
+ sd: sdhc@5a500000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a500000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
+
+ usb3: usb@5a830100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a830100 0x100>;
+ interrupts = <0 83 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
+ <&mio_rst 15>;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-sld3-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-sld3-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ aidet@f1830000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0xf1830000 0x200>;
+ };
+
+ sysctrl@f1840000 {
+ compatible = "socionext,uniphier-sld3-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0xf1840000 0x4000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-sld3-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-sld3-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ nand: nand@f8000000 {
+ compatible = "socionext,denali-nand-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+ interrupts = <0 65 4>;
+ clocks = <&sys_clk 2>;
+ nand-ecc-strength = <8>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-sld8-ref.dts b/arch/arm/dts/uniphier-sld8-ref.dts
new file mode 100644
index 0000000..6c0544b
--- /dev/null
+++ b/arch/arm/dts/uniphier-sld8-ref.dts
@@ -0,0 +1,83 @@
+/*
+ * Device Tree Source for UniPhier sLD8 Reference Board
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-sld8.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier sLD8 Reference Board";
+ compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+};
+
+ðsc {
+ interrupts = <0 48 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&serial3 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
new file mode 100644
index 0000000..5550bb8
--- /dev/null
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -0,0 +1,462 @@
+/*
+ * Device Tree Source for UniPhier sLD8 SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-sld8";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ clocks {
+ refclk: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ arm_timer_clk: arm_timer_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+ u-boot,dm-pre-reloc;
+
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(256 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ clock-frequency = <80000000>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ clock-frequency = <80000000>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ clock-frequency = <80000000>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 29 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ clock-frequency = <80000000>;
+ };
+
+ port0x: gpio@55000008 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000008 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port1x: gpio@55000010 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000010 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port2x: gpio@55000018 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000018 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port3x: gpio@55000020 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000020 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port4: gpio@55000028 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000028 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port5x: gpio@55000030 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000030 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port6x: gpio@55000038 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000038 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port7x: gpio@55000040 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000040 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port8x: gpio@55000048 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000048 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port9x: gpio@55000050 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000050 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port10x: gpio@55000058 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000058 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port11x: gpio@55000060 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000060 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port12x: gpio@55000068 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000068 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port13x: gpio@55000070 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000070 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port14x: gpio@55000078 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000078 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ port16x: gpio@55000088 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000088 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ clock-frequency = <100000>;
+ };
+
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ clock-frequency = <400000>;
+ };
+
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ clock-frequency = <100000>;
+ };
+
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
+
+ smpctrl@59800000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
+
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-sld8-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ mio_clk: clock {
+ compatible = "socionext,uniphier-sld8-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ mio_rst: reset {
+ compatible = "socionext,uniphier-sld8-mio-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-sld8-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ peri_clk: clock {
+ compatible = "socionext,uniphier-sld8-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ peri_rst: reset {
+ compatible = "socionext,uniphier-sld8-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_1v8>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
+
+ emmc: sdhc@5a500000 {
+ compatible = "socionext,uniphier-sdhc";
+ status = "disabled";
+ reg = <0x5a500000 0x200>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default", "1.8v";
+ pinctrl-0 = <&pinctrl_emmc>;
+ pinctrl-1 = <&pinctrl_emmc_1v8>;
+ clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 1>, <&mio_rst 4>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ };
+
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
+ };
+
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
+ };
+
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
+ };
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-sld8-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+ u-boot,dm-pre-reloc;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-sld8-pinctrl";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ aidet@61830000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x61830000 0x200>;
+ };
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-sld8-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-sld8-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-sld8-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ nand: nand@68000000 {
+ compatible = "socionext,denali-nand-v5a";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ clocks = <&sys_clk 2>;
+ nand-ecc-strength = <8>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi
index dc52748..c2f104a 100644
--- a/arch/arm/dts/vf-colibri.dtsi
+++ b/arch/arm/dts/vf-colibri.dtsi
@@ -21,6 +21,17 @@
};
};
+&ehci0 {
+ dr_mode = "otg";
+ fsl,cdet-gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&ehci1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index 1530d2f..477d8de 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
@@ -20,6 +21,8 @@
serial5 = &uart5;
spi0 = &dspi0;
spi1 = &dspi1;
+ ehci0 = &ehci0;
+ ehci1 = &ehci1;
};
soc {
@@ -32,6 +35,7 @@
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ reg = <0x40000000 0x00070000>;
ranges;
uart0: serial@40027000 {
@@ -80,7 +84,9 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
- reg = <0x40044000 0x1000>;
+ reg = <0x40044000 0x1000>,
+ <0x20000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
status = "disabled";
};
@@ -113,12 +119,19 @@
reg = <0x400ff100 0x40>;
#gpio-cells = <2>;
};
+
+ ehci0: ehci@40034000 {
+ compatible = "fsl,vf610-usb";
+ reg = <0x40034000 0x800>;
+ status = "disabled";
+ };
};
aips1: aips-bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ reg = <0x40080000 0x0007f000>;
ranges;
uart4: serial@400a9000 {
@@ -133,6 +146,11 @@
status = "disabled";
};
+ ehci1: ehci@400b4000 {
+ compatible = "fsl,vf610-usb";
+ reg = <0x400b4000 0x800>;
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index b618a3f..668f54e 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -6,16 +6,17 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-/include/ "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "xlnx,zynq-7000";
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
@@ -29,7 +30,7 @@
>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
@@ -37,14 +38,14 @@
};
};
- pmu {
+ pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
interrupt-parent = <&intc>;
reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
};
- regulator_vccpint: fixedregulator@0 {
+ regulator_vccpint: fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <1000000>;
diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts
index cb238cd..2d07b92 100644
--- a/arch/arm/dts/zynq-microzed.dts
+++ b/arch/arm/dts/zynq-microzed.dts
@@ -18,7 +18,7 @@
mmc0 = &sdhci0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x40000000>;
};
diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts
index 3408df8..e15667c 100644
--- a/arch/arm/dts/zynq-picozed.dts
+++ b/arch/arm/dts/zynq-picozed.dts
@@ -14,9 +14,11 @@
aliases {
serial0 = &uart1;
+ spi0 = &qspi;
+ mmc0 = &sdhci1;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0x40000000>;
};
@@ -26,3 +28,13 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&sdhci1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts
new file mode 100644
index 0000000..aa05c4d
--- /dev/null
+++ b/arch/arm/dts/zynq-topic-miami.dts
@@ -0,0 +1,97 @@
+/*
+ * Topic Miami board DTS
+ *
+ * Copyright (C) 2014-2016 Topic Embedded Products
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Topic Miami Zynq Board";
+ compatible = "topic,miami", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+ is-dual = <0>;
+ num-cs = <1>;
+ flash@0 {
+ compatible = "st,m25p80", "n25q256a";
+ m25p,fast-read;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@qspi-u-boot-spl {
+ label = "qspi-u-boot-spl";
+ reg = <0x00000 0x10000>;
+ };
+ partition@qspi-u-boot-img {
+ label = "qspi-u-boot-img";
+ reg = <0x10000 0x60000>;
+ };
+ partition@qspi-device-tree {
+ label = "qspi-device-tree";
+ reg = <0x70000 0x10000>;
+ };
+ partition@qspi-linux {
+ label = "qspi-linux";
+ reg = <0x80000 0x400000>;
+ };
+ partition@qspi-rootfs {
+ label = "qspi-rootfs";
+ reg = <0x480000 0x1b80000>;
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&sdhci0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-topic-miamiplus.dts b/arch/arm/dts/zynq-topic-miamiplus.dts
new file mode 100644
index 0000000..3036f6e
--- /dev/null
+++ b/arch/arm/dts/zynq-topic-miamiplus.dts
@@ -0,0 +1,17 @@
+/*
+ * Topic Miami Plus board DTS
+ *
+ * Copyright (C) 2016 Topic Embedded Products
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include "zynq-topic-miami.dts"
+
+/ {
+ model = "Topic Miami+ Zynq Board";
+ compatible = "topic,miamiplus", "xlnx,zynq-7000";
+};
+
+&qspi {
+ is-dual = <1>;
+};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 6585010..478e9fd 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -21,7 +21,7 @@
mmc0 = &sdhci0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index d04880a..8b0177b 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -21,7 +21,7 @@
mmc0 = &sdhci0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index 33524cb..42af313 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -25,7 +25,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index 463b14b..7f08961 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -23,7 +23,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 6cab832..699cd2c 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -24,7 +24,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index d5bb4ef..07e92b8 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -25,7 +25,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 4363a4f..0ac7532 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -20,7 +20,7 @@
mmc0 = &sdhci0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x20000000>;
};
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index f8dcf1d..d59a383 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -20,7 +20,7 @@
mmc0 = &sdhci0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x20000000>;
};
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
index 0918c68..aa848c8 100644
--- a/arch/arm/dts/zynqmp-clk.dtsi
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -114,6 +114,38 @@
clocks = <&clk600>, <&clk100>;
};
+&lpd_dma_chan1 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan2 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan3 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan4 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan5 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan6 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan7 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan8 {
+ clocks = <&clk600>, <&clk100>;
+};
+
&nand0 {
clocks = <&clk100 &clk100>;
};
diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi
index b3ce0de..1c2efe4 100644
--- a/arch/arm/dts/zynqmp-ep108-clk.dtsi
+++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi
@@ -35,6 +35,18 @@
clock-accuracy = <100>;
};
+ clk100: clk100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk600: clk600 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ };
+
dp_aud_clk: clock1 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -47,6 +59,42 @@
clocks = <&misc_clk &misc_clk>;
};
+&can1 {
+ clocks = <&misc_clk &misc_clk>;
+};
+
+&fpd_dma_chan1 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan2 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan3 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan4 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan5 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan6 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan7 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan8 {
+ clocks = <&clk600>, <&clk100>;
+};
+
&gem0 {
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
};
diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index 0bbf9a7..2483180d 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -31,7 +31,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
@@ -41,6 +41,10 @@
status = "okay";
};
+&can1 {
+ status = "okay";
+};
+
&gem0 {
status = "okay";
phy-handle = <&phy0>;
@@ -150,10 +154,12 @@
&sdhci0 {
status = "okay";
bus-width = <8>;
+ xlnx,mio_bank = <2>;
};
&sdhci1 {
status = "okay";
+ xlnx,mio_bank = <1>;
};
&spi0 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index c68a41b..b3f4297 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -34,7 +34,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
@@ -159,12 +159,14 @@
&sdhci0 {
status = "okay";
bus-width = <8>;
+ xlnx,mio_bank = <0>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v; /* for 1.0 silicon */
+ xlnx,mio_bank = <1>;
};
&uart0 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 3fdfcc8..09a114b 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -36,7 +36,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 03f1ad7..1f03a94 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -41,7 +41,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index d754f9f..698e72e 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -32,7 +32,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102.dts
index de99602..0e9150e 100644
--- a/arch/arm/dts/zynqmp-zcu102.dts
+++ b/arch/arm/dts/zynqmp-zcu102.dts
@@ -12,6 +12,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "ZynqMP ZCU102 RevA";
@@ -26,6 +27,7 @@
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
+ serial2 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
@@ -35,16 +37,43 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <108>; /* down */
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
};
&can1 {
status = "okay";
};
+&dcc {
+ status = "okay";
+};
+
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
@@ -365,7 +394,7 @@
/* Bus 3 is not connected */
};
- /* FIXME PL connection - u55 , PMOD - j160 */
+ /* FIXME PMOD - j160 */
/* FIXME MSP430F - u41 - not detected */
};
@@ -576,6 +605,7 @@
&sdhci1 {
status = "okay";
no-1-8-v; /* for 1.0 silicon */
+ xlnx,mio_bank = <1>;
};
&uart0 {
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 619450e..de1f160 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -7,6 +7,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
@@ -45,6 +46,12 @@
};
};
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
power-domains {
compatible = "xlnx,zynqmp-genpd";
@@ -184,34 +191,14 @@
pd-id = <0x30>;
};
- pd_ddr: pd-ddr {
+ pd_pcie: pd-pcie {
#power-domain-cells = <0x0>;
- pd-id = <0x37>;
+ pd-id = <0x3b>;
};
- pd_apll: pd-apll {
+ pd_gpu: pd-gpu {
#power-domain-cells = <0x0>;
- pd-id = <0x32>;
- };
-
- pd_vpll: pd-vpll {
- #power-domain-cells = <0x0>;
- pd-id = <0x33>;
- };
-
- pd_dpll: pd-dpll {
- #power-domain-cells = <0x0>;
- pd-id = <0x34>;
- };
-
- pd_rpll: pd-rpll {
- #power-domain-cells = <0x0>;
- pd-id = <0x35>;
- };
-
- pd_iopll: pd-iopll {
- #power-domain-cells = <0x0>;
- pd-id = <0x36>;
+ pd-id = <0x3a 0x14 0x15>;
};
};
@@ -243,7 +230,15 @@
<1 10 0xf01>;
};
- amba_apu: amba_apu {
+ edac {
+ compatible = "arm,cortex-a53-edac";
+ };
+
+ pcap {
+ compatible = "xlnx,zynqmp-pcap-fpga";
+ };
+
+ amba_apu: amba_apu@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
@@ -266,14 +261,14 @@
compatible = "simple-bus";
u-boot,dm-pre-reloc;
#address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0 0 0xffffffff>;
+ #size-cells = <2>;
+ ranges;
can0: can@ff060000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
- reg = <0x0 0xff060000 0x1000>;
+ reg = <0x0 0xff060000 0x0 0x1000>;
interrupts = <0 23 4>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
@@ -285,7 +280,7 @@
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
- reg = <0x0 0xff070000 0x1000>;
+ reg = <0x0 0xff070000 0x0 0x1000>;
interrupts = <0 24 4>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
@@ -295,7 +290,7 @@
cci: cci@fd6e0000 {
compatible = "arm,cci-400";
- reg = <0x0 0xfd6e0000 0x9000>;
+ reg = <0x0 0xfd6e0000 0x0 0x9000>;
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -316,200 +311,228 @@
fpd_dma_chan1: dma@fd500000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xfd500000 0x1000>;
+ reg = <0x0 0xfd500000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
- xlnx,id = <0>;
xlnx,bus-width = <128>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x14e8>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan2: dma@fd510000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xfd510000 0x1000>;
+ reg = <0x0 0xfd510000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
- xlnx,id = <1>;
xlnx,bus-width = <128>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x14e9>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan3: dma@fd520000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xfd520000 0x1000>;
+ reg = <0x0 0xfd520000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
- xlnx,id = <2>;
xlnx,bus-width = <128>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x14ea>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan4: dma@fd530000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xfd530000 0x1000>;
+ reg = <0x0 0xfd530000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
- xlnx,id = <3>;
xlnx,bus-width = <128>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x14eb>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan5: dma@fd540000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xfd540000 0x1000>;
+ reg = <0x0 0xfd540000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
- xlnx,id = <4>;
xlnx,bus-width = <128>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x14ec>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan6: dma@fd550000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xfd550000 0x1000>;
+ reg = <0x0 0xfd550000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
- xlnx,id = <5>;
xlnx,bus-width = <128>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x14ed>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan7: dma@fd560000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xfd560000 0x1000>;
+ reg = <0x0 0xfd560000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
- xlnx,id = <6>;
xlnx,bus-width = <128>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x14ee>;
power-domains = <&pd_gdma>;
};
fpd_dma_chan8: dma@fd570000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xfd570000 0x1000>;
+ reg = <0x0 0xfd570000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
- xlnx,id = <7>;
xlnx,bus-width = <128>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x14ef>;
power-domains = <&pd_gdma>;
};
gpu: gpu@fd4b0000 {
status = "disabled";
compatible = "arm,mali-400", "arm,mali-utgard";
- reg = <0x0 0xfd4b0000 0x30000>;
+ reg = <0x0 0xfd4b0000 0x0 0x30000>;
interrupt-parent = <&gic>;
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
+ power-domains = <&pd_gpu>;
};
- /* ADMA */
+ /* LPDDMA default allows only secured access. inorder to enable
+ * These dma channels, Users should ensure that these dma
+ * Channels are allowed for non secure access.
+ */
lpd_dma_chan1: dma@ffa80000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xffa80000 0x1000>;
+ clock-names = "clk_main", "clk_apb";
+ reg = <0x0 0xffa80000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 77 4>;
- xlnx,id = <0>;
xlnx,bus-width = <64>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x868>;
power-domains = <&pd_adma>;
};
lpd_dma_chan2: dma@ffa90000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xffa90000 0x1000>;
+ clock-names = "clk_main", "clk_apb";
+ reg = <0x0 0xffa90000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 78 4>;
- xlnx,id = <1>;
xlnx,bus-width = <64>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x869>;
power-domains = <&pd_adma>;
};
lpd_dma_chan3: dma@ffaa0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xffaa0000 0x1000>;
+ clock-names = "clk_main", "clk_apb";
+ reg = <0x0 0xffaa0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 79 4>;
- xlnx,id = <2>;
xlnx,bus-width = <64>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x86a>;
power-domains = <&pd_adma>;
};
lpd_dma_chan4: dma@ffab0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xffab0000 0x1000>;
+ clock-names = "clk_main", "clk_apb";
+ reg = <0x0 0xffab0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 80 4>;
- xlnx,id = <3>;
xlnx,bus-width = <64>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x86b>;
power-domains = <&pd_adma>;
};
lpd_dma_chan5: dma@ffac0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xffac0000 0x1000>;
+ clock-names = "clk_main", "clk_apb";
+ reg = <0x0 0xffac0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 81 4>;
- xlnx,id = <4>;
xlnx,bus-width = <64>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x86c>;
power-domains = <&pd_adma>;
};
lpd_dma_chan6: dma@ffad0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xffad0000 0x1000>;
+ clock-names = "clk_main", "clk_apb";
+ reg = <0x0 0xffad0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 82 4>;
- xlnx,id = <5>;
xlnx,bus-width = <64>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x86d>;
power-domains = <&pd_adma>;
};
lpd_dma_chan7: dma@ffae0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xffae0000 0x1000>;
+ clock-names = "clk_main", "clk_apb";
+ reg = <0x0 0xffae0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 83 4>;
- xlnx,id = <6>;
xlnx,bus-width = <64>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x86e>;
power-domains = <&pd_adma>;
};
lpd_dma_chan8: dma@ffaf0000 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
- reg = <0x0 0xffaf0000 0x1000>;
+ clock-names = "clk_main", "clk_apb";
+ reg = <0x0 0xffaf0000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 84 4>;
- xlnx,id = <7>;
xlnx,bus-width = <64>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x86f>;
power-domains = <&pd_adma>;
};
mc: memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
- reg = <0x0 0xfd070000 0x30000>;
+ reg = <0x0 0xfd070000 0x0 0x30000>;
interrupt-parent = <&gic>;
interrupts = <0 112 4>;
};
@@ -517,12 +540,14 @@
nand0: nand@ff100000 {
compatible = "arasan,nfc-v3p10";
status = "disabled";
- reg = <0x0 0xff100000 0x1000>;
+ reg = <0x0 0xff100000 0x0 0x1000>;
clock-names = "clk_sys", "clk_flash";
interrupt-parent = <&gic>;
interrupts = <0 14 4>;
#address-cells = <2>;
#size-cells = <1>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x872>;
power-domains = <&pd_nand>;
};
@@ -531,11 +556,12 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
- reg = <0x0 0xff0b0000 0x1000>;
+ reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
+ iommus = <&smmu 0x874>;
power-domains = <&pd_eth0>;
};
@@ -544,11 +570,12 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
- reg = <0x0 0xff0c0000 0x1000>;
+ reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
+ iommus = <&smmu 0x875>;
power-domains = <&pd_eth1>;
};
@@ -557,11 +584,12 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
- reg = <0x0 0xff0d0000 0x1000>;
+ reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
+ iommus = <&smmu 0x876>;
power-domains = <&pd_eth2>;
};
@@ -570,11 +598,12 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
- reg = <0x0 0xff0e0000 0x1000>;
+ reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
#stream-id-cells = <1>;
+ iommus = <&smmu 0x877>;
power-domains = <&pd_eth3>;
};
@@ -582,11 +611,11 @@
compatible = "xlnx,zynqmp-gpio-1.0";
status = "disabled";
#gpio-cells = <0x2>;
- #interrupt-cells = <2>;
- interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <0 16 4>;
- reg = <0x0 0xff0a0000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0xff0a0000 0x0 0x1000>;
power-domains = <&pd_gpio>;
};
@@ -595,7 +624,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
- reg = <0x0 0xff020000 0x1000>;
+ reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_i2c0>;
@@ -606,35 +635,47 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
- reg = <0x0 0xff030000 0x1000>;
+ reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_i2c1>;
};
+ ocm: memory-controller@ff960000 {
+ compatible = "xlnx,zynqmp-ocmc-1.0";
+ reg = <0x0 0xff960000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 10 4>;
+ };
+
pcie: pcie@fd0e0000 {
compatible = "xlnx,nwl-pcie-2.11";
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
+ msi-controller;
device_type = "pci";
interrupt-parent = <&gic>;
interrupts = <0 118 4>,
+ <0 117 4>,
<0 116 4>,
<0 115 4>, /* MSI_1 [63...32] */
<0 114 4>; /* MSI_0 [31...0] */
- interrupt-names = "misc", "intx", "msi_1", "msi_0";
- reg = <0x0 0xfd0e0000 0x1000>,
- <0x0 0xfd480000 0x1000>,
- <0x0 0xe0000000 0x1000000>;
+ interrupt-names = "misc","dummy","intx", "msi1", "msi0";
+ msi-parent = <&pcie>;
+ reg = <0x0 0xfd0e0000 0x0 0x1000>,
+ <0x0 0xfd480000 0x0 0x1000>,
+ <0x80 0x00000000 0x0 0x1000000>;
reg-names = "breg", "pcireg", "cfg";
- ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+ ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
+ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+ power-domains = <&pd_pcie>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
@@ -649,26 +690,51 @@
interrupts = <0 15 4>;
interrupt-parent = <&gic>;
num-cs = <1>;
- reg = <0x0 0xff0f0000 0x1000>,
- <0x0 0xc0000000 0x8000000>;
+ reg = <0x0 0xff0f0000 0x0 0x1000>,
+ <0x0 0xc0000000 0x0 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x873>;
power-domains = <&pd_qspi>;
};
rtc: rtc@ffa60000 {
compatible = "xlnx,zynqmp-rtc";
status = "disabled";
- reg = <0x0 0xffa60000 0x100>;
+ reg = <0x0 0xffa60000 0x0 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 26 4>, <0 27 4>;
interrupt-names = "alarm", "sec";
};
+ serdes: zynqmp_phy@fd400000 {
+ compatible = "xlnx,zynqmp-psgtr";
+ status = "disabled";
+ reg = <0x0 0xfd400000 0x0 0x40000>,
+ <0x0 0xfd3d0000 0x0 0x1000>,
+ <0x0 0xfd1a0000 0x0 0x1000>,
+ <0x0 0xff5e0000 0x0 0x1000>;
+ reg-names = "serdes", "siou", "fpd", "lpd";
+ xlnx,tx_termination_fix;
+ lane0: lane0 {
+ #phy-cells = <4>;
+ };
+ lane1: lane1 {
+ #phy-cells = <4>;
+ };
+ lane2: lane2 {
+ #phy-cells = <4>;
+ };
+ lane3: lane3 {
+ #phy-cells = <4>;
+ };
+ };
+
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";
- reg = <0x0 0xfd0c0000 0x2000>;
+ reg = <0x0 0xfd0c0000 0x0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
power-domains = <&pd_sata>;
@@ -676,31 +742,36 @@
sdhci0: sdhci@ff160000 {
u-boot,dm-pre-reloc;
- compatible = "arasan,sdhci-8.9a";
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 48 4>;
- reg = <0x0 0xff160000 0x1000>;
+ reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- broken-tuning;
+ xlnx,device_id = <0>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x870>;
power-domains = <&pd_sd0>;
};
sdhci1: sdhci@ff170000 {
u-boot,dm-pre-reloc;
- compatible = "arasan,sdhci-8.9a";
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 49 4>;
- reg = <0x0 0xff170000 0x1000>;
+ reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- broken-tuning;
+ xlnx,device_id = <1>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x871>;
power-domains = <&pd_sd1>;
};
smmu: smmu@fd800000 {
compatible = "arm,mmu-500";
- reg = <0x0 0xfd800000 0x20000>;
+ reg = <0x0 0xfd800000 0x0 0x20000>;
+ #iommu-cells = <1>;
#global-interrupts = <1>;
interrupt-parent = <&gic>;
interrupts = <0 155 4>,
@@ -711,7 +782,29 @@
mmu-masters = < &gem0 0x874
&gem1 0x875
&gem2 0x876
- &gem3 0x877 >;
+ &gem3 0x877
+ &usb0 0x860
+ &usb1 0x861
+ &qspi 0x873
+ &lpd_dma_chan1 0x868
+ &lpd_dma_chan2 0x869
+ &lpd_dma_chan3 0x86a
+ &lpd_dma_chan4 0x86b
+ &lpd_dma_chan5 0x86c
+ &lpd_dma_chan6 0x86d
+ &lpd_dma_chan7 0x86e
+ &lpd_dma_chan8 0x86f
+ &fpd_dma_chan1 0x14e8
+ &fpd_dma_chan2 0x14e9
+ &fpd_dma_chan3 0x14ea
+ &fpd_dma_chan4 0x14eb
+ &fpd_dma_chan5 0x14ec
+ &fpd_dma_chan6 0x14ed
+ &fpd_dma_chan7 0x14ee
+ &fpd_dma_chan8 0x14ef
+ &sdhci0 0x870
+ &sdhci1 0x871
+ &nand0 0x872>;
};
spi0: spi@ff040000 {
@@ -719,7 +812,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 19 4>;
- reg = <0x0 0xff040000 0x1000>;
+ reg = <0x0 0xff040000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
@@ -731,7 +824,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 20 4>;
- reg = <0x0 0xff050000 0x1000>;
+ reg = <0x0 0xff050000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
@@ -743,7 +836,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
- reg = <0x0 0xff110000 0x1000>;
+ reg = <0x0 0xff110000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc0>;
};
@@ -753,7 +846,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
- reg = <0x0 0xff120000 0x1000>;
+ reg = <0x0 0xff120000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc1>;
};
@@ -763,7 +856,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
- reg = <0x0 0xff130000 0x1000>;
+ reg = <0x0 0xff130000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc2>;
};
@@ -773,7 +866,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
- reg = <0x0 0xff140000 0x1000>;
+ reg = <0x0 0xff140000 0x0 0x1000>;
timer-width = <32>;
power-domains = <&pd_ttc3>;
};
@@ -784,7 +877,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
- reg = <0x0 0xff000000 0x1000>;
+ reg = <0x0 0xff000000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&pd_uart0>;
};
@@ -795,25 +888,27 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
- reg = <0x0 0xff010000 0x1000>;
+ reg = <0x0 0xff010000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
power-domains = <&pd_uart1>;
};
- usb0: usb@fe200000 {
+ usb0: usb0 {
#address-cells = <2>;
- #size-cells = <1>;
+ #size-cells = <2>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
clock-names = "bus_clk", "ref_clk";
clocks = <&clk125>, <&clk125>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x860>;
power-domains = <&pd_usb0>;
ranges;
dwc3_0: dwc3@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
- reg = <0x0 0xfe200000 0x40000>;
+ reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupts = <0 65 4>;
/* snps,quirk-frame-length-adjustment = <0x20>; */
@@ -821,20 +916,22 @@
};
};
- usb1: usb@fe300000 {
+ usb1: usb1 {
#address-cells = <2>;
- #size-cells = <1>;
+ #size-cells = <2>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
clock-names = "bus_clk", "ref_clk";
clocks = <&clk125>, <&clk125>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x861>;
power-domains = <&pd_usb1>;
ranges;
dwc3_1: dwc3@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
- reg = <0x0 0xfe300000 0x40000>;
+ reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupts = <0 70 4>;
/* snps,quirk-frame-length-adjustment = <0x20>; */
@@ -847,7 +944,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 113 1>;
- reg = <0x0 0xfd4d0000 0x1000>;
+ reg = <0x0 0xfd4d0000 0x0 0x1000>;
timeout-sec = <10>;
};
@@ -861,11 +958,13 @@
xlnx,pixel-format = "rgb565";
plane0 {
dmas = <&xlnx_dpdma 3>;
- dma-names = "dma";
+ dma-names = "dma0";
};
plane1 {
- dmas = <&xlnx_dpdma 0>;
- dma-names = "dma";
+ dmas = <&xlnx_dpdma 0>,
+ <&xlnx_dpdma 1>,
+ <&xlnx_dpdma 2>;
+ dma-names = "dma0", "dma1", "dma2";
};
};
};
@@ -873,8 +972,7 @@
xlnx_dp: dp@fd4a0000 {
compatible = "xlnx,v-dp";
status = "disabled";
- reg = <0x0 0xfd4a0000 0x1000>,
- <0x0 0xfd400000 0x20000>;
+ reg = <0x0 0xfd4a0000 0x0 0x1000>;
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "aclk", "aud_clk";
@@ -920,9 +1018,9 @@
xlnx_dp_sub: dp_sub@fd4aa000 {
compatible = "xlnx,dp-sub";
status = "disabled";
- reg = <0x0 0xfd4aa000 0x1000>,
- <0x0 0xfd4ab000 0x1000>,
- <0x0 0xfd4ac000 0x1000>;
+ reg = <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
reg-names = "blend", "av_buf", "aud";
xlnx,output-fmt = "rgb";
xlnx,vid-fmt = "yuyv";
@@ -932,28 +1030,28 @@
xlnx_dpdma: dma@fd4c0000 {
compatible = "xlnx,dpdma";
status = "disabled";
- reg = <0x0 0xfd4c0000 0x1000>;
+ reg = <0x0 0xfd4c0000 0x0 0x1000>;
interrupts = <0 122 4>;
interrupt-parent = <&gic>;
clock-names = "axi_clk";
dma-channels = <6>;
#dma-cells = <1>;
- dma-video0channel@fd4c0000 {
+ dma-video0channel {
compatible = "xlnx,video0";
};
- dma-video1channel@fd4c0000 {
+ dma-video1channel {
compatible = "xlnx,video1";
};
- dma-video2channel@fd4c0000 {
+ dma-video2channel {
compatible = "xlnx,video2";
};
- dma-graphicschannel@fd4c0000 {
+ dma-graphicschannel {
compatible = "xlnx,graphics";
};
- dma-audio0channel@fd4c0000 {
+ dma-audio0channel {
compatible = "xlnx,audio0";
};
- dma-audio1channel@fd4c0000 {
+ dma-audio1channel {
compatible = "xlnx,audio1";
};
};
diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
index 1b7da5a..a6b61ad 100644
--- a/arch/arm/imx-common/Kconfig
+++ b/arch/arm/imx-common/Kconfig
@@ -17,3 +17,17 @@
depends on ARCH_MX7 || ARCH_MX6
help
bootaux [addr] to boot auxiliary core.
+
+config USE_IMXIMG_PLUGIN
+ bool "Use imximage plugin code"
+ depends on ARCH_MX7 || ARCH_MX6
+ help
+ i.MX6/7 supports DCD and Plugin. Enable this configuration
+ to use Plugin, otherwise DCD will be used.
+
+config SECURE_BOOT
+ bool "Support i.MX HAB features"
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
+ help
+ This option enables the support for secure boot (HAB).
+ See doc/README.mxc_hab for more details.
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index d34a784..da53f62 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -34,9 +34,28 @@
ifeq ($(SOC),$(filter $(SOC),vf610))
obj-y += ddrmc-vf610.o
endif
+ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
+endif
+
+PLUGIN = board/$(BOARDDIR)/plugin
+
+ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
+
+$(PLUGIN).o: $(PLUGIN).S FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,as_o_S)
+
+$(PLUGIN).bin: $(PLUGIN).o FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(OBJCOPY) -O binary --gap-fill 0xff $< $@
+else
+
+$(PLUGIN).bin:
+
+endif
quiet_cmd_cpp_cfg = CFGS $@
cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
@@ -47,24 +66,28 @@
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cpp_cfg)
-MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
+MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE)
+u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log
-u-boot.imx: u-boot.bin $(IMX_CONFIG) FORCE
+u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
ifeq ($(CONFIG_OF_SEPARATE),y)
-MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
+MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE)
+u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log
-u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) FORCE
+u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
endif
-MKIMAGEFLAGS_SPL = -n $(filter-out $< $(PHONY),$^) -T imximage \
+MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE)
-SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE
+SPL: MKIMAGEOUTPUT = SPL.log
+
+SPL: spl/u-boot-spl.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index b775488..1c4a9a2 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -8,6 +8,7 @@
#include <asm/armv7.h>
#include <asm/pl310.h>
#include <asm/io.h>
+#include <asm/imx-common/sys_proto.h>
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
@@ -39,6 +40,7 @@
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned int val;
@@ -55,15 +57,14 @@
*/
setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
-#if defined CONFIG_MX6SL
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- val = readl(&iomux->gpr[11]);
- if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
- /* L2 cache configured as OCRAM, reset it */
- val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
- writel(val, &iomux->gpr[11]);
+ if (is_mx6sl() || is_mx6sll()) {
+ val = readl(&iomux->gpr[11]);
+ if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+ /* L2 cache configured as OCRAM, reset it */
+ val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+ writel(val, &iomux->gpr[11]);
+ }
}
-#endif
writel(0x132, &pl310->pl310_tag_latency_ctrl);
writel(0x132, &pl310->pl310_data_latency_ctrl);
diff --git a/arch/arm/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c
index 841b1d3..b0868aa 100644
--- a/arch/arm/imx-common/cmd_bmode.c
+++ b/arch/arm/imx-common/cmd_bmode.c
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/imx-common/boot_mode.h>
#include <malloc.h>
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 4223187..40fe813 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -10,7 +10,7 @@
#include <bootm.h>
#include <common.h>
#include <netdev.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
@@ -155,10 +155,14 @@
return "6SOLO"; /* Solo version of the mx6 */
case MXC_CPU_MX6SL:
return "6SL"; /* Solo-Lite version of the mx6 */
+ case MXC_CPU_MX6SLL:
+ return "6SLL"; /* SLL version of the mx6 */
case MXC_CPU_MX6SX:
return "6SX"; /* SoloX version of the mx6 */
case MXC_CPU_MX6UL:
return "6UL"; /* Ultra-Lite version of the mx6 */
+ case MXC_CPU_MX6ULL:
+ return "6ULL"; /* ULL version of the mx6 */
case MXC_CPU_MX51:
return "51";
case MXC_CPU_MX53:
diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index 6731825..7449487 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -110,6 +110,10 @@
* +------------+ + CSF_PAD_SIZE
*/
+static bool is_hab_enabled(void);
+
+#if !defined(CONFIG_SPL_BUILD)
+
#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
struct record {
@@ -257,22 +261,6 @@
-1
};
-bool is_hab_enabled(void)
-{
- struct imx_sec_config_fuse_t *fuse =
- (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
- uint32_t reg;
- int ret;
-
- ret = fuse_read(fuse->bank, fuse->word, ®);
- if (ret) {
- puts("\nSecure boot fuse read error\n");
- return ret;
- }
-
- return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
-}
-
static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
{
uint8_t idx = 0;
@@ -359,6 +347,68 @@
return 0;
}
+int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if ((argc != 1)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ get_hab_status();
+
+ return 0;
+}
+
+static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ ulong addr, ivt_offset;
+ int rcode = 0;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ ivt_offset = simple_strtoul(argv[2], NULL, 16);
+
+ rcode = authenticate_image(addr, ivt_offset);
+
+ return rcode;
+}
+
+U_BOOT_CMD(
+ hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
+ "display HAB status",
+ ""
+ );
+
+U_BOOT_CMD(
+ hab_auth_img, 3, 0, do_authenticate_image,
+ "authenticate image via HAB",
+ "addr ivt_offset\n"
+ "addr - image hex address\n"
+ "ivt_offset - hex offset of IVT in the image"
+ );
+
+
+#endif /* !defined(CONFIG_SPL_BUILD) */
+
+static bool is_hab_enabled(void)
+{
+ struct imx_sec_config_fuse_t *fuse =
+ (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
+ uint32_t reg;
+ int ret;
+
+ ret = fuse_read(fuse->bank, fuse->word, ®);
+ if (ret) {
+ puts("\nSecure boot fuse read error\n");
+ return ret;
+ }
+
+ return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
+}
+
uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
{
uint32_t load_addr = 0;
@@ -400,7 +450,9 @@
(void *)(ddr_start + ivt_offset+IVT_SIZE),
4, 0x10, 0);
+#if !defined(CONFIG_SPL_BUILD)
get_hab_status();
+#endif
puts("\nCalling authenticate_image in ROM\n");
printf("\tivt_offset = 0x%x\n", ivt_offset);
@@ -449,7 +501,9 @@
hab_caam_clock_enable(0);
+#if !defined(CONFIG_SPL_BUILD)
get_hab_status();
+#endif
} else {
puts("hab fuse not enabled\n");
}
@@ -459,46 +513,3 @@
return result;
}
-
-int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if ((argc != 1)) {
- cmd_usage(cmdtp);
- return 1;
- }
-
- get_hab_status();
-
- return 0;
-}
-
-static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- ulong addr, ivt_offset;
- int rcode = 0;
-
- if (argc < 3)
- return CMD_RET_USAGE;
-
- addr = simple_strtoul(argv[1], NULL, 16);
- ivt_offset = simple_strtoul(argv[2], NULL, 16);
-
- rcode = authenticate_image(addr, ivt_offset);
-
- return rcode;
-}
-
-U_BOOT_CMD(
- hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
- "display HAB status",
- ""
- );
-
-U_BOOT_CMD(
- hab_auth_img, 3, 0, do_authenticate_image,
- "authenticate image via HAB",
- "addr ivt_offset\n"
- "addr - image hex address\n"
- "ivt_offset - hex offset of IVT in the image"
- );
diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c
index ff72b1a..ae8809c 100644
--- a/arch/arm/imx-common/i2c-mxv7.c
+++ b/arch/arm/imx-common/i2c-mxv7.c
@@ -7,7 +7,7 @@
#include <malloc.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <watchdog.h>
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
index 3d2ce3a..e5dbd93 100644
--- a/arch/arm/imx-common/init.c
+++ b/arch/arm/imx-common/init.c
@@ -44,7 +44,7 @@
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
- if (is_mx6sx() || is_mx7()) {
+ if (is_mx6ull() || is_mx6sx() || is_mx7()) {
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 66137d1..c9a3bf2 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -31,7 +31,7 @@
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-#if defined CONFIG_MX6SL
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
/* Check whether LVE bit needs to be set */
if (pad_ctrl & PAD_CTL_LVE) {
pad_ctrl &= ~PAD_CTL_LVE;
@@ -42,6 +42,7 @@
#ifdef CONFIG_IOMUX_LPSR
u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
+#ifdef CONFIG_MX7
if (lpsr == IOMUX_CONFIG_LPSR) {
base = (void *)IOMUXC_LPSR_BASE_ADDR;
mux_mode &= ~IOMUX_CONFIG_LPSR;
@@ -49,9 +50,17 @@
if (sel_input_ofs)
sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
}
+#else
+ if (is_mx6ull() || is_mx6sll()) {
+ if (lpsr == IOMUX_CONFIG_LPSR) {
+ base = (void *)IOMUXC_SNVS_BASE_ADDR;
+ mux_mode &= ~IOMUX_CONFIG_LPSR;
+ }
+ }
+#endif
#endif
- if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
+ if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
if (sel_input_ofs)
@@ -64,6 +73,10 @@
#else
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#if defined(CONFIG_MX6SLL)
+ else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+ clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
+#endif
#endif
#ifdef CONFIG_IOMUX_LPSR
@@ -83,7 +96,7 @@
#if defined(CONFIG_MX6QDL)
stride = 2;
- if (!is_mx6dq())
+ if (!is_mx6dq() && !is_mx6dqp())
p += 1;
#else
stride = 1;
diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c
index 12256a3..1b0f18d 100644
--- a/arch/arm/imx-common/misc.c
+++ b/arch/arm/imx-common/misc.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/imx-common/regs-common.h>
diff --git a/arch/arm/imx-common/rdc-sema.c b/arch/arm/imx-common/rdc-sema.c
index dcb5c41..5df4e02 100644
--- a/arch/arm/imx-common/rdc-sema.c
+++ b/arch/arm/imx-common/rdc-sema.c
@@ -8,7 +8,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
/*
* Check if the RDC Semaphore is required for this peripheral.
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index bdcda7d..c86b6f8 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -12,6 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/spl.h>
#include <spl.h>
+#include <asm/imx-common/hab.h>
#if defined(CONFIG_MX6)
/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
@@ -90,3 +91,27 @@
}
}
#endif
+
+#if defined(CONFIG_SECURE_BOOT)
+
+__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ typedef void __noreturn (*image_entry_noargs_t)(void);
+
+ image_entry_noargs_t image_entry =
+ (image_entry_noargs_t)(unsigned long)spl_image->entry_point;
+
+ debug("image entry point: 0x%X\n", spl_image->entry_point);
+
+ /* HAB looks for the CSF at the end of the authenticated data therefore,
+ * we need to subtract the size of the CSF from the actual filesize */
+ if (authenticate_image(spl_image->load_addr,
+ spl_image->size - CONFIG_CSF_SIZE)) {
+ image_entry();
+ } else {
+ puts("spl: ERROR: image authentication unsuccessful\n");
+ hang();
+ }
+}
+
+#endif
diff --git a/arch/arm/imx-common/spl_sd.cfg b/arch/arm/imx-common/spl_sd.cfg
index 5fc3e8a..14c135c 100644
--- a/arch/arm/imx-common/spl_sd.cfg
+++ b/arch/arm/imx-common/spl_sd.cfg
@@ -4,5 +4,15 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#define __ASSEMBLY__
+#include <config.h>
+
IMAGE_VERSION 2
BOOT_FROM sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
\ No newline at end of file
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index a01590c..ee6eff2 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -44,7 +44,8 @@
{
#if defined(CONFIG_MX6)
if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
- is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
+ is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
+ is_mx6ull() || is_mx6sll())
return 1;
return 0;
@@ -83,8 +84,12 @@
if (gpt_has_clk_source_osc()) {
i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
- /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
- if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
+ /*
+ * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
+ * Enable bit and prescaler
+ */
+ if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
+ is_mx6sll()) {
i |= GPTCR_24MEN;
/* Produce 3Mhz clock */
@@ -119,3 +124,19 @@
{
return gpt_get_clk();
}
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long _usec)
+{
+ unsigned long long usec = _usec;
+
+ usec *= get_tbclk();
+ usec += 999999;
+ do_div(usec, 1000000);
+
+ return usec;
+}
diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c
index 46f8a1e..549bf9d 100644
--- a/arch/arm/imx-common/video.c
+++ b/arch/arm/imx-common/video.c
@@ -3,7 +3,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/imx-common/video.h>
int board_video_skip(void)
@@ -34,7 +34,7 @@
}
if (i < display_count) {
- ret = ipuv3_fb_init(&displays[i].mode, 0,
+ ret = ipuv3_fb_init(&displays[i].mode, displays[i].di ? 1 : 0,
displays[i].pixfmt);
if (!ret) {
if (displays[i].enable)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 62bca8c..dbed776 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -43,7 +43,8 @@
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
-/* cpu-id for AM33XX and TI81XX family */
+/* cpu-id for AM43XX AM33XX and TI81XX family */
+#define AM437X 0xB98C
#define AM335X 0xB944
#define TI81XX 0xB81E
#define DEVICE_ID (CTRL_BASE + 0x0600)
@@ -579,6 +580,8 @@
};
#define ECAP_CLK_EN BIT(0)
#define ECAP_CLK_STOP_REQ BIT(1)
+#define EPWM_CLK_EN BIT(8)
+#define EPWM_CLK_STOP_REQ BIT(9)
struct pwmss_ecap_regs {
unsigned int tsctr;
@@ -592,6 +595,40 @@
unsigned short ecctl2;
};
+struct pwmss_epwm_regs {
+ unsigned short tbctl;
+ unsigned short tbsts;
+ unsigned short tbphshr;
+ unsigned short tbphs;
+ unsigned short tbcnt;
+ unsigned short tbprd;
+ unsigned short res1;
+ unsigned short cmpctl;
+ unsigned short cmpahr;
+ unsigned short cmpa;
+ unsigned short cmpb;
+ unsigned short aqctla;
+ unsigned short aqctlb;
+ unsigned short aqsfrc;
+ unsigned short aqcsfrc;
+ unsigned short dbctl;
+ unsigned short dbred;
+ unsigned short dbfed;
+ unsigned short tzsel;
+ unsigned short tzctl;
+ unsigned short tzflg;
+ unsigned short tzclr;
+ unsigned short tzfrc;
+ unsigned short etsel;
+ unsigned short etps;
+ unsigned short etflg;
+ unsigned short etclr;
+ unsigned short etfrc;
+ unsigned short pcctl;
+ unsigned int res2[66];
+ unsigned short hrcnfg;
+};
+
/* Capture Control register 2 */
#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
#define ECTRL2_MDSL_ECAP BIT(9)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index d1aed58..fa9b84f 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -67,5 +67,6 @@
/* PWMSS */
#define PWMSS0_BASE 0x48300000
#define AM33XX_ECAP0_BASE 0x48300100
+#define AM33XX_EPWM_BASE 0x48300200
#endif /* __AM33XX_HARDWARE_AM33XX_H */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index ed1a46c..0c5792b 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -19,6 +19,7 @@
extern struct ctrl_stat *cstat;
u32 get_device_type(void);
void save_omap_boot_params(void);
+void setup_early_clocks(void);
void setup_clocks_for_console(void);
void mpu_pll_config_val(int mpull_m);
void ddr_pll_config(unsigned int ddrpll_M);
@@ -44,3 +45,4 @@
void enable_usb_clocks(int index);
void disable_usb_clocks(int index);
+void do_board_detect(void);
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h
index 4927abe..54e6ccf 100644
--- a/arch/arm/include/asm/arch-armada100/gpio.h
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h
index 9efa1bf..631acf3 100644
--- a/arch/arm/include/asm/arch-armada100/spi.h
+++ b/arch/arm/include/asm/arch-armada100/spi.h
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/arch/arm/include/asm/arch-armada100/utmi-armada100.h
index 953dd44..fca1827 100644
--- a/arch/arm/include/asm/arch-armada100/utmi-armada100.h
+++ b/arch/arm/include/asm/arch-armada100/utmi-armada100.h
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2012
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
diff --git a/arch/arm/include/asm/arch-armada8k/cache_llc.h b/arch/arm/include/asm/arch-armada8k/cache_llc.h
new file mode 100644
index 0000000..8f97e6d
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada8k/cache_llc.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#ifndef _CACHE_LLC_H_
+#define _CACHE_LLC_H_
+
+/* Armada-7K/8K last level cache */
+
+#define MVEBU_A8K_REGS_BASE_MSB 0xf000
+#define LLC_BASE_ADDR 0x8000
+#define LLC_CACHE_SYNC 0x700
+#define LLC_CACHE_SYNC_COMPLETE 0x730
+#define LLC_FLUSH_BY_WAY 0x7fc
+#define LLC_WAY_MASK 0xffffffff
+#define LLC_CACHE_SYNC_MASK 0x1
+
+#endif /* _CACHE_LLC_H_ */
diff --git a/arch/arm/include/asm/arch-armada8k/soc-info.h b/arch/arm/include/asm/arch-armada8k/soc-info.h
new file mode 100644
index 0000000..bae3995
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada8k/soc-info.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#ifndef _SOC_INFO_H_
+#define _SOC_INFO_H_
+
+/* Pin Ctrl driver definitions */
+#define BITS_PER_PIN 4
+#define PIN_FUNC_MASK ((1 << BITS_PER_PIN) - 1)
+#define PIN_REG_SHIFT 3
+#define PIN_FIELD_MASK ((1 << PIN_REG_SHIFT) - 1)
+
+#endif /* _SOC_INFO_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5279981..6073d44 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -7,18 +7,10 @@
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+#include <linux/kconfig.h>
#include <fsl_ddrc_version.h>
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
-#endif
-
-#ifndef CONFIG_LS1012A
-#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-#endif
+#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
/*
* Reserve secure memory
@@ -27,25 +19,19 @@
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#ifdef CONFIG_LS2080A
-#define CONFIG_MAX_CPUS 16
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_NUM_DDR_CONTROLLERS 3
-#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
+#define CONFIG_FSL_TZASC_400
#endif
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
/* DDR */
-#define CONFIG_SYS_FSL_DDR_LE
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
@@ -69,10 +55,6 @@
#define CONFIG_SYS_FSL_SFP_LE
#define CONFIG_SYS_FSL_SRK_LE
-/* SEC */
-#define CONFIG_SYS_FSL_SEC_LE
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
-
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
@@ -129,17 +111,7 @@
#define EPU_EPCTR5 0x700060a14ULL
#define EPU_EPGCR 0x700060000ULL
-#define CONFIG_SYS_FSL_ERRATUM_A008336
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A008514
-#define CONFIG_SYS_FSL_ERRATUM_A008585
#define CONFIG_SYS_FSL_ERRATUM_A008751
-#define CONFIG_SYS_FSL_ERRATUM_A009635
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009801
-#define CONFIG_SYS_FSL_ERRATUM_A009803
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A010165
/* ARM A57 CORE ERRATA */
#define CONFIG_ARM_ERRATA_826974
@@ -149,11 +121,8 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
#define CONFIG_SYS_FSL_ESDHC_BE
@@ -162,18 +131,13 @@
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
-#define CONFIG_SYS_FSL_SEC_BE
-#define CONFIG_SYS_FSL_SRDS_1
/* SoC related */
#ifdef CONFIG_LS1043A
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
-#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
@@ -195,30 +159,20 @@
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
-#define CONFIG_SYS_FSL_ERRATUM_A008850
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009929
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A009660
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-#elif defined(CONFIG_LS1012A)
-#define CONFIG_MAX_CPUS 1
-#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
+#elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
-#elif defined(CONFIG_LS1046A)
-#define CONFIG_MAX_CPUS 4
+
+#elif defined(CONFIG_ARCH_LS1046A)
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
-#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SNVS_LE
@@ -234,6 +188,7 @@
#define GICC_BASE 0x01420000
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index e2d96a1..a97be5c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -11,6 +11,10 @@
CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+ CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
+ CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
+ CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
+ CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index e1b3f44..9f94b45 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -11,6 +11,10 @@
#ifdef CONFIG_LS2080A
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,
@@ -57,6 +61,10 @@
};
#elif defined(CONFIG_FSL_LSCH2)
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 95a4293..b3cfd89 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
+#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
@@ -60,7 +61,7 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
/* LUT registers */
-#ifdef CONFIG_LS1012A
+#ifdef CONFIG_ARCH_LS1012A
#define PCIE_LUT_BASE 0xC0000
#else
#define PCIE_LUT_BASE 0x10000
@@ -120,7 +121,7 @@
#endif
#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR 0x01000000
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
@@ -128,7 +129,7 @@
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
@@ -168,6 +169,8 @@
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
/* Device Configuration and Pin Control */
+#define DCFG_DCSR_PORCR1 0x0
+
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
@@ -335,6 +338,8 @@
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
+#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
+#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
/* Supplemental Configuration Unit */
struct ccsr_scfg {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 93e26c1..e18dcbd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,29 +19,23 @@
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
+#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
+#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
+#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
-/* SP (Cortex-A5) related */
-#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
- (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
-#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
- (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
-
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
@@ -162,7 +156,7 @@
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
#define TP_INIT_PER_CLUSTER 4
/* This is chassis generation 3 */
-
+#ifndef __ASSEMBLY__
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
@@ -326,6 +320,5 @@
u32 ip_rev2; /* 0xbfc */
};
-uint get_svr(void);
-
+#endif /*__ASSEMBLY__*/
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
index e46e076..d0832b5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -13,6 +13,7 @@
* uint64_t entry_addr;
* uint64_t status;
* uint64_t lpid;
+* uint64_t os_arch;
* };
* we pad this struct to 64 bytes so each entry is in its own cacheline
* the actual spin table is an array of these structures
@@ -20,6 +21,7 @@
#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
#define SPIN_TABLE_ELEM_STATUS_IDX 1
#define SPIN_TABLE_ELEM_LPID_IDX 2
+#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3
#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
#define SPIN_TABLE_ELEM_SIZE 64
@@ -34,5 +36,10 @@
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
int is_core_online(u64 cpu_id);
+u32 cpu_pos_mask(void);
#endif
+
+#define IH_ARCH_ARM 2 /* ARM */
+#define IH_ARCH_ARM64 22 /* ARM64 */
+
#endif /* _FSL_LAYERSCAPE_MP_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index db76066..f46f1d8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -6,6 +6,7 @@
#ifndef __FSL_NS_ACCESS_H_
#define __FSL_NS_ACCESS_H_
+#include <fsl_csu.h>
enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 8d4a7ad..78363b6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -30,7 +30,7 @@
#define pex_lut_in32(a) in_be32(a)
#define pex_lut_out32(a, v) out_be32(a, v)
#endif
-
+#ifndef __ASSEMBLY__
struct cpu_type {
char name[15];
u32 soc_ver;
@@ -39,7 +39,7 @@
#define CPU_TYPE_ENTRY(n, v, nc) \
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
-
+#endif
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
@@ -50,6 +50,12 @@
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100
#define SVR_LS2040A 0x870130
+#define SVR_LS2088A 0x870900
+#define SVR_LS2084A 0x870910
+#define SVR_LS2048A 0x870920
+#define SVR_LS2044A 0x870930
+
+#define SVR_DEV_LS2080A 0x8701
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
@@ -60,10 +66,10 @@
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
-#define AHCI_PORT_PHY_2_CFG 0x28184d1f
-#define AHCI_PORT_PHY_3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029
+#define AHCI_PORT_AXICC_CFG 0x3fffffff
+#ifndef __ASSEMBLY__
/* AHCI (sata) register map */
struct ccsr_ahci {
u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
@@ -100,6 +106,11 @@
void erratum_a009635(void);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void);
+#endif
+
bool soc_has_dp_ddr(void);
bool soc_has_aiop(void);
+#endif
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 7c63c13..8bd1421 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -17,8 +17,10 @@
#define MXC_CPU_MX6SX 0x62
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6UL 0x64
-#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
-#define MXC_CPU_MX6D 0x67
+#define MXC_CPU_MX6ULL 0x65
+#define MXC_CPU_MX6SOLO 0x66 /* dummy */
+#define MXC_CPU_MX6SLL 0x67
+#define MXC_CPU_MX6D 0x6A
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
#define MXC_CPU_MX7S 0x71 /* dummy ID */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 56d8f32..fccd4ff 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -16,7 +16,9 @@
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
+#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
+#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
@@ -89,17 +91,9 @@
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_FSL_ERRATUM_A008407
#ifdef CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
-#endif
-#define CONFIG_SYS_FSL_DDR
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
#endif
@@ -111,24 +105,14 @@
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_DCU_BE
#define CONFIG_SYS_FSL_SEC_MON_LE
-#define CONFIG_SYS_FSL_SEC_LE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define DCU_LAYER_MAX_NUM 16
-#define CONFIG_SYS_FSL_SRDS_1
-
#ifdef CONFIG_LS102XA
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
index 3a92f5a..fafc44b 100644
--- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
@@ -10,6 +10,10 @@
#include <config.h>
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 0a80772..c34fd63 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -161,6 +161,17 @@
#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000
#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000
#define SCFG_ENDIANCR_LE 0x80000000
+#define SCFG_DPSLPCR_WDRR_EN 0x00000001
+#define SCFG_PMCINTECR_LPUART 0x40000000
+#define SCFG_PMCINTECR_FTM 0x20000000
+#define SCFG_PMCINTECR_GPIO 0x10000000
+#define SCFG_PMCINTECR_IRQ0 0x08000000
+#define SCFG_PMCINTECR_IRQ1 0x04000000
+#define SCFG_PMCINTECR_ETSECRXG0 0x00800000
+#define SCFG_PMCINTECR_ETSECRXG1 0x00400000
+#define SCFG_PMCINTECR_ETSECERRG0 0x00080000
+#define SCFG_PMCINTECR_ETSECERRG1 0x00040000
+#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
/* Supplemental Configuration Unit */
struct ccsr_scfg {
@@ -226,7 +237,7 @@
u32 debug_streamid;
u32 resv10[5];
u32 snpcnfgcr;
- u32 resv11[1];
+ u32 hrstcr;
u32 intpcr;
u32 resv12[20];
u32 scfgrevcr;
@@ -243,6 +254,9 @@
u32 sdhciovserlcr;
u32 resv14[61];
u32 sparecr[8];
+ u32 resv15[248];
+ u32 core0sftrstsr;
+ u32 clusterpmcr;
};
/* Clocking */
@@ -433,6 +447,42 @@
u32 cmds; /* port 0/1 CMD status error */
};
+#define RCPM_POWMGTCSR 0x130
+#define RCPM_POWMGTCSR_SERDES_PW 0x80000000
+#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
+#define RCPM_POWMGTCSR_LPM20_ST 0x00000200
+#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
+#define RCPM_IPPDEXPCR0 0x140
+#define RCPM_IPPDEXPCR0_ETSEC 0x80000000
+#define RCPM_IPPDEXPCR0_GPIO 0x00000040
+#define RCPM_IPPDEXPCR1 0x144
+#define RCPM_IPPDEXPCR1_LPUART 0x40000000
+#define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000
+#define RCPM_IPPDEXPCR1_OCRAM1 0x10000000
+#define RCPM_NFIQOUTR 0x15c
+#define RCPM_NIRQOUTR 0x16c
+#define RCPM_DSIMSKR 0x18c
+#define RCPM_CLPCL10SETR 0x1c4
+#define RCPM_CLPCL10SETR_C0 0x00000001
+
+struct ccsr_rcpm {
+ u8 rev1[0x4c];
+ u32 twaitsr;
+ u8 rev2[0xe0];
+ u32 powmgtcsr;
+ u8 rev3[0xc];
+ u32 ippdexpcr0;
+ u32 ippdexpcr1;
+ u8 rev4[0x14];
+ u32 nfiqoutr;
+ u8 rev5[0xc];
+ u32 nirqoutr;
+ u8 rev6[0x1c];
+ u32 dsimskr;
+ u8 rev7[0x34];
+ u32 clpcl10setr;
+};
+
uint get_svr(void);
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
index a354684..9c91354 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
@@ -11,4 +11,8 @@
int arch_soc_init(void);
int ls102xa_smmu_stream_id_init(void);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void);
+#endif
+
#endif /* __FSL_LS102XA_SOC_H */
diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h
index 78869a2..3545aed 100644
--- a/arch/arm/include/asm/arch-mvebu/spi.h
+++ b/arch/arm/include/asm/arch-mvebu/spi.h
@@ -52,6 +52,10 @@
#define KWSPI_ADRLEN_3BYTE (2 << 8)
#define KWSPI_ADRLEN_4BYTE (3 << 8)
#define KWSPI_ADRLEN_MASK (3 << 8)
+#define KWSPI_CPOL (1 << 11)
+#define KWSPI_CPHA (1 << 12)
+#define KWSPI_TXLSBF (1 << 13)
+#define KWSPI_RXLSBF (1 << 14)
#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */
#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 82f9f92..2d9c45e 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -74,9 +74,10 @@
void enable_ipu_clock(void);
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
-int enable_lcdif_clock(u32 base_addr);
+int enable_lcdif_clock(u32 base_addr, bool enable);
void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);
void mxs_set_lcdclk(u32 base_addr, u32 freq);
void select_ldb_di_clock_source(enum ldb_di_clock clk);
+void enable_eim_clk(unsigned char enable);
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 22212c2..74ed912 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -307,6 +307,9 @@
/* LCFIF2_PODF on i.MX6SX */
#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20)
#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20
+/* LCDIF_PIX_PODF on i.MX6SL */
+#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK (0x7 << 20)
+#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET 20
/* ACLK_EMI on i.MX6DQ/SDL/DQP */
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
@@ -379,6 +382,16 @@
#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
/* Define the bits in register CS1CDR */
+/* MX6UL, !MX6ULL */
+#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22
+#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16
+#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6
+#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0
+
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
@@ -460,7 +473,7 @@
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
/* Define the bits in register CHSCCDR */
-#ifdef CONFIG_MX6SX
+/* i.MX6SX */
#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
@@ -473,7 +486,7 @@
#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
-#else
+
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
@@ -486,7 +499,14 @@
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
-#endif
+
+/* i.MX6ULL */
+#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12
+#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9
#define CHSCCDR_CLK_SEL_LDB_DI0 3
#define CHSCCDR_PODF_DIVIDE_BY_3 2
@@ -512,6 +532,12 @@
#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0)
#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0
+/*LCD on i.MX6SL */
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 6
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET 3
+
/* All IPU2_DI1 are LCDIF1 on MX6SX */
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
@@ -537,6 +563,12 @@
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
+/* For i.MX6SL */
+#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16
+#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14
+
/* Define the bits in register CDHIPR */
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
@@ -626,6 +658,12 @@
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGR_CG_MASK 3
+/* i.MX 6ULL */
+#define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10
+#define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET)
+#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12
+#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET)
+
#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
@@ -702,13 +740,12 @@
#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
#endif
-#ifndef CONFIG_MX6SX
#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
-#else
+/* i.MX6SX/UL */
#define MXC_CCM_CCGR2_CSI_OFFSET 2
#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
-#endif
+
#ifndef CONFIG_MX6SX
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
@@ -744,14 +781,29 @@
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0
+#define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET)
+#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4
+#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET)
+
/* Exist on i.MX6SX */
#define MXC_CCM_CCGR3_M4_OFFSET 2
#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4
+#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR3_ENET_OFFSET 4
#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
#define MXC_CCM_CCGR3_QSPI_OFFSET 14
#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
+/* i.MX6SL */
+#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6
+#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8
+#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET)
+
#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
@@ -808,7 +860,7 @@
#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
-/* GPIO4 on i.MX6UL */
+/* GPIO4 on i.MX6UL/ULL */
#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
@@ -817,6 +869,10 @@
#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
#endif
+/* i.MX6ULL */
+#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30
+#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET)
+
#define MXC_CCM_CCGR4_PCIE_OFFSET 0
#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
/* QSPI2 on i.MX6SX */
@@ -883,6 +939,13 @@
#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6
+#define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET)
+#define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8
+#define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8
+#define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET)
/* GPMI/BCH on i.MX6UL */
#define MXC_CCM_CCGR6_BCH_OFFSET 6
#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
@@ -895,6 +958,9 @@
#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18
+#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET)
/* The following *CCGR6* exist only i.MX6SX */
#define MXC_CCM_CCGR6_PWM8_OFFSET 16
#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
@@ -1226,6 +1292,8 @@
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
#define BP_PMU_MISC2_AUDIO_DIV_MSB 23
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 53bf054..6727c56 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -26,7 +26,7 @@
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000
-#else
+#elif !defined(CONFIG_MX6SLL)
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF
#define APBH_DMA_ARB_BASE_ADDR 0x00110000
@@ -46,13 +46,9 @@
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
#define GPV2_BASE_ADDR 0x00D00000
-#else
-#define GPV2_BASE_ADDR 0x00200000
-#endif
-
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define GPV3_BASE_ADDR 0x00E00000
#define GPV4_BASE_ADDR 0x00F00000
#define GPV5_BASE_ADDR 0x01000000
@@ -61,6 +57,7 @@
#define PCIE_ARB_END_ADDR 0x08FFFFFF
#else
+#define GPV2_BASE_ADDR 0x00200000
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
#define PCIE_ARB_BASE_ADDR 0x01000000
@@ -96,7 +93,7 @@
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
-#else
+#elif !defined(CONFIG_MX6SLL)
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
@@ -111,7 +108,8 @@
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
#endif
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
@@ -141,19 +139,21 @@
#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
-#ifdef CONFIG_MX6SL
-#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
-#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
-#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
-#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
-#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
-#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
-#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
-#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
-#else
+
+#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
+
#ifndef CONFIG_MX6SX
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#endif
+#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
@@ -161,7 +161,6 @@
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
-#endif
#ifndef CONFIG_MX6SX
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
@@ -176,12 +175,15 @@
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
+/* QOSC on i.MX6SLL */
+#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
+#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
@@ -197,11 +199,18 @@
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
-#ifdef CONFIG_MX6SL
+#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#ifdef CONFIG_MX6SLL
+#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
+#elif defined(CONFIG_MX6SL)
#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
-#elif CONFIG_MX6SX
+#elif defined(CONFIG_MX6SX)
#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
@@ -214,6 +223,9 @@
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#endif
+#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
+
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
@@ -248,7 +260,7 @@
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
-/* i.MX6SL */
+/* i.MX6SL/SLL */
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#ifdef CONFIG_MX6UL
#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
@@ -262,9 +274,14 @@
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
+#ifdef CONFIG_MX6SLL
+#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#endif
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#ifdef CONFIG_MX6SX
#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#else
@@ -294,6 +311,8 @@
#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
+/* i.MX6SLL */
+#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#ifdef CONFIG_MX6SX
#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
@@ -318,13 +337,22 @@
#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#elif defined(CONFIG_MX6ULL)
+#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
+#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
+#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
+#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
+#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
#endif
/* Only for i.MX6SX */
#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
-#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
#define IRAM_SIZE 0x00040000
#else
#define IRAM_SIZE 0x00020000
@@ -336,10 +364,16 @@
#include <asm/types.h>
/* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \
+#define WDOG3_BASE_ADDR ((is_mx6ul() ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
-#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \
- MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)
+#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
+ MX6SLL_LCDIF_BASE_ADDR : \
+ (is_cpu_type(MXC_CPU_MX6SL)) ? \
+ MX6SL_LCDIF_BASE_ADDR : \
+ ((is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MX6UL_LCDIF1_BASE_ADDR : \
+ ((is_mx6ull()) ? \
+ MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
@@ -660,7 +694,8 @@
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
+#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 9922409..2a8d443 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -458,9 +458,11 @@
const struct mx6sl_iomux_ddr_regs *,
const struct mx6sl_iomux_grp_regs *);
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-int mmdc_do_write_level_calibration(void);
-int mmdc_do_dqs_calibration(void);
+#if defined(CONFIG_MX6_DDRCAL)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+ struct mx6_mmdc_calibration *calib);
#endif
/* configure mx6 mmdc registers */
@@ -495,6 +497,7 @@
#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
+#define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C
#define MX6_MMDC_P0_MPMUR0 0x021b08b8
#define MX6_MMDC_P1_MDCTL 0x021b4000
@@ -522,6 +525,7 @@
#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
+#define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C
#define MX6_MMDC_P1_MPMUR0 0x021b48b8
#endif /*__ASM_ARCH_MX6_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index 4b6bb18..2934b12 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -33,10 +33,14 @@
MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6dl_pins.h"
};
+#elif defined(CONFIG_MX6SLL)
+#include "mx6sll_pins.h"
#elif defined(CONFIG_MX6SL)
#include "mx6sl_pins.h"
#elif defined(CONFIG_MX6SX)
#include "mx6sx_pins.h"
+#elif defined(CONFIG_MX6ULL)
+#include "mx6ull_pins.h"
#elif defined(CONFIG_MX6UL)
#include "mx6ul_pins.h"
#else
diff --git a/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/arch/arm/include/asm/arch-mx6/mx6_plugin.S
new file mode 100644
index 0000000..b7d1b20
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6_plugin.S
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
+#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
+#define ROM_VERSION_OFFSET 0x80
+#else
+#define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0
+#define ROM_VERSION_OFFSET 0x48
+#endif
+#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4
+#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4
+#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
+#define ROM_VERSION_TO10 0x10
+#define ROM_VERSION_TO12 0x12
+#define ROM_VERSION_TO15 0x15
+
+plugin_start:
+
+ push {r0-r4, lr}
+
+ imx6_ddr_setting
+ imx6_clock_gating
+ imx6_qos_setting
+
+/*
+ * The following is to fill in those arguments for this ROM function
+ * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+ * This function is used to copy data from the storage media into DDR.
+ * start - Initial (possibly partial) image load address on entry.
+ * Final image load address on exit.
+ * bytes - Initial (possibly partial) image size on entry.
+ * Final image size on exit.
+ * boot_data - Initial @ref ivt Boot Data load address.
+ */
+ adr r0, boot_data2
+ adr r1, image_len2
+ adr r2, boot_data2
+
+#ifdef CONFIG_NOR_BOOT
+#ifdef CONFIG_MX6SX
+ ldr r3, =ROM_VERSION_OFFSET
+ ldr r4, [r3]
+ cmp r4, #ROM_VERSION_TO10
+ bgt before_calling_rom___pu_irom_hwcnfg_setup
+ ldr r3, =0x00900b00
+ ldr r4, =0x50000000
+ str r4, [r3, #0x5c]
+#else
+ ldr r3, =0x00900800
+ ldr r4, =0x08000000
+ str r4, [r3, #0xc0]
+#endif
+#endif
+
+/*
+ * check the _pu_irom_api_table for the address
+ */
+before_calling_rom___pu_irom_hwcnfg_setup:
+ ldr r3, =ROM_VERSION_OFFSET
+ ldr r4, [r3]
+#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
+ ldr r3, =ROM_VERSION_TO12
+ cmp r4, r3
+ ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
+ ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
+#elif defined(CONFIG_MX6Q)
+ ldr r3, =ROM_VERSION_TO15
+ cmp r4, r3
+ ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15
+ ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
+#else
+ ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
+#endif
+ ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
+ blx r4
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+/*
+ * ROM_API_HWCNFG_SETUP function enables MMU & Caches.
+ * Thus disable MMU & Caches.
+ */
+
+ mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0*/
+ ands r0, r0, #0x1 /* check if MMU is enabled */
+ beq mmu_disable_notreq /* exit if MMU is already disabled */
+
+ /* Disable caches, MMU */
+ mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */
+ bic r0, r0, #(1 << 2) /* disable D Cache */
+ bic r0, r0, #0x1 /* clear bit 0 ; MMU off */
+
+ bic r0, r0, #(0x1 << 11) /* disable Z, branch prediction */
+ bic r0, r0, #(0x1 << 1) /* disable A, Strict alignment */
+ /* check enabled. */
+ mcr p15, 0, r0, c1, c0, 0 /* write CP15 register 1 */
+ mov r0, r0
+ mov r0, r0
+ mov r0, r0
+ mov r0, r0
+
+mmu_disable_notreq:
+ NOP
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+ pop {r0-r4, lr}
+ push {r5}
+ ldr r5, boot_data2
+ str r5, [r0]
+ ldr r5, image_len2
+ str r5, [r1]
+ ldr r5, second_ivt_offset
+ str r5, [r2]
+ mov r0, #1
+ pop {r5}
+
+ /* return back to ROM code */
+ bx lr
+
+/* make the following data right in the end of the output*/
+.ltorg
+
+#if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT))
+#define FLASH_OFFSET 0x1000
+#else
+#define FLASH_OFFSET 0x400
+#endif
+
+/*
+ * second_ivt_offset is the offset from the "second_ivt_header" to
+ * "image_copy_start", which involves FLASH_OFFSET, plus the first
+ * ivt_header, the plugin code size itself recorded by "ivt2_header"
+ */
+
+second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET)
+
+/*
+ * The following is the second IVT header plus the second boot data
+ */
+ivt2_header: .long 0x0
+app2_code_jump_v: .long 0x0
+reserv3: .long 0x0
+dcd2_ptr: .long 0x0
+boot_data2_ptr: .long 0x0
+self_ptr2: .long 0x0
+app_code_csf2: .long 0x0
+reserv4: .long 0x0
+boot_data2: .long 0x0
+image_len2: .long 0x0
+plugin2: .long 0x0
diff --git a/arch/arm/include/asm/arch-mx6/mx6sll_pins.h b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h
new file mode 100644
index 0000000..1ecb7ce
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h
@@ -0,0 +1,1019 @@
+/*
+ * Copyright (C) 2014 - 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX6SLL_PINS_H__
+#define __ASM_ARCH_IMX6SLL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+ MX6_PAD_WDOG_B__WDOG1_B = IOMUX_PAD(0x02DC, 0x0014, 0, 0x0000, 0, 0),
+ MX6_PAD_WDOG_B__WDOG1_RESET_B_DEB = IOMUX_PAD(0x02DC, 0x0014, 1, 0x0000, 0, 0),
+ MX6_PAD_WDOG_B__UART5_RI_B = IOMUX_PAD(0x02DC, 0x0014, 2, 0x0000, 0, 0),
+ MX6_PAD_WDOG_B__GPIO3_IO18 = IOMUX_PAD(0x02DC, 0x0014, 5, 0x0000, 0, 0),
+
+ MX6_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x02E0, 0x0018, 0, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_24M__I2C3_SCL = IOMUX_PAD(0x02E0, 0x0018, IOMUX_CONFIG_SION | 1, 0x068C, 0, 0),
+ MX6_PAD_REF_CLK_24M__PWM3_OUT = IOMUX_PAD(0x02E0, 0x0018, 2, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_24M__USB_OTG2_ID = IOMUX_PAD(0x02E0, 0x0018, 3, 0x0560, 0, 0),
+ MX6_PAD_REF_CLK_24M__CCM_PMIC_READY = IOMUX_PAD(0x02E0, 0x0018, 4, 0x05AC, 0, 0),
+ MX6_PAD_REF_CLK_24M__GPIO3_IO21 = IOMUX_PAD(0x02E0, 0x0018, 5, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_24M__SD3_WP = IOMUX_PAD(0x02E0, 0x0018, 6, 0x0794, 0, 0),
+
+ MX6_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x02E4, 0x001C, 0, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__I2C3_SDA = IOMUX_PAD(0x02E4, 0x001C, IOMUX_CONFIG_SION | 1, 0x0690, 0, 0),
+ MX6_PAD_REF_CLK_32K__PWM4_OUT = IOMUX_PAD(0x02E4, 0x001C, 2, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__USB_OTG1_ID = IOMUX_PAD(0x02E4, 0x001C, 3, 0x055C, 0, 0),
+ MX6_PAD_REF_CLK_32K__SD1_LCTL = IOMUX_PAD(0x02E4, 0x001C, 4, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__GPIO3_IO22 = IOMUX_PAD(0x02E4, 0x001C, 5, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__SD3_CD_B = IOMUX_PAD(0x02E4, 0x001C, 6, 0x0780, 0, 0),
+
+ MX6_PAD_PWM1__PWM1_OUT = IOMUX_PAD(0x02E8, 0x0020, 0, 0x0000, 0, 0),
+ MX6_PAD_PWM1__CCM_CLKO = IOMUX_PAD(0x02E8, 0x0020, 1, 0x0000, 0, 0),
+ MX6_PAD_PWM1__AUDIO_CLK_OUT = IOMUX_PAD(0x02E8, 0x0020, 2, 0x0000, 0, 0),
+ MX6_PAD_PWM1__CSI_MCLK = IOMUX_PAD(0x02E8, 0x0020, 4, 0x0000, 0, 0),
+ MX6_PAD_PWM1__GPIO3_IO23 = IOMUX_PAD(0x02E8, 0x0020, 5, 0x0000, 0, 0),
+ MX6_PAD_PWM1__EPIT1_OUT = IOMUX_PAD(0x02E8, 0x0020, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x02EC, 0x0024, 0, 0x06A0, 0, 0),
+ MX6_PAD_KEY_COL0__I2C2_SCL = IOMUX_PAD(0x02EC, 0x0024, IOMUX_CONFIG_SION | 1, 0x0684, 0, 0),
+ MX6_PAD_KEY_COL0__LCD_DATA00 = IOMUX_PAD(0x02EC, 0x0024, 2, 0x06D8, 0, 0),
+ MX6_PAD_KEY_COL0__SD1_CD_B = IOMUX_PAD(0x02EC, 0x0024, 4, 0x0770, 1, 0),
+ MX6_PAD_KEY_COL0__GPIO3_IO24 = IOMUX_PAD(0x02EC, 0x0024, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x02F0, 0x0028, 0, 0x06C0, 0, 0),
+ MX6_PAD_KEY_ROW0__I2C2_SDA = IOMUX_PAD(0x02F0, 0x0028, IOMUX_CONFIG_SION | 1, 0x0688, 0, 0),
+ MX6_PAD_KEY_ROW0__LCD_DATA01 = IOMUX_PAD(0x02F0, 0x0028, 2, 0x06DC, 0, 0),
+ MX6_PAD_KEY_ROW0__SD1_WP = IOMUX_PAD(0x02F0, 0x0028, 4, 0x0774, 1, 0),
+ MX6_PAD_KEY_ROW0__GPIO3_IO25 = IOMUX_PAD(0x02F0, 0x0028, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x02F4, 0x002C, 0, 0x06A4, 0, 0),
+ MX6_PAD_KEY_COL1__ECSPI4_MOSI = IOMUX_PAD(0x02F4, 0x002C, 1, 0x0658, 1, 0),
+ MX6_PAD_KEY_COL1__LCD_DATA02 = IOMUX_PAD(0x02F4, 0x002C, 2, 0x06E0, 0, 0),
+ MX6_PAD_KEY_COL1__SD3_DATA4 = IOMUX_PAD(0x02F4, 0x002C, 4, 0x0784, 0, 0),
+ MX6_PAD_KEY_COL1__GPIO3_IO26 = IOMUX_PAD(0x02F4, 0x002C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x02F8, 0x0030, 0, 0x06C4, 0, 0),
+ MX6_PAD_KEY_ROW1__ECSPI4_MISO = IOMUX_PAD(0x02F8, 0x0030, 1, 0x0654, 1, 0),
+ MX6_PAD_KEY_ROW1__LCD_DATA03 = IOMUX_PAD(0x02F8, 0x0030, 2, 0x06E4, 0, 0),
+ MX6_PAD_KEY_ROW1__CSI_FIELD = IOMUX_PAD(0x02F8, 0x0030, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__SD3_DATA5 = IOMUX_PAD(0x02F8, 0x0030, 4, 0x0788, 0, 0),
+ MX6_PAD_KEY_ROW1__GPIO3_IO27 = IOMUX_PAD(0x02F8, 0x0030, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x02FC, 0x0034, 0, 0x06A8, 0, 0),
+ MX6_PAD_KEY_COL2__ECSPI4_SS0 = IOMUX_PAD(0x02FC, 0x0034, 1, 0x065C, 1, 0),
+ MX6_PAD_KEY_COL2__LCD_DATA04 = IOMUX_PAD(0x02FC, 0x0034, 2, 0x06E8, 0, 0),
+ MX6_PAD_KEY_COL2__CSI_DATA12 = IOMUX_PAD(0x02FC, 0x0034, 3, 0x05B8, 1, 0),
+ MX6_PAD_KEY_COL2__SD3_DATA6 = IOMUX_PAD(0x02FC, 0x0034, 4, 0x078C, 0, 0),
+ MX6_PAD_KEY_COL2__GPIO3_IO28 = IOMUX_PAD(0x02FC, 0x0034, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0300, 0x0038, 0, 0x06C8, 0, 0),
+ MX6_PAD_KEY_ROW2__ECSPI4_SCLK = IOMUX_PAD(0x0300, 0x0038, 1, 0x0650, 1, 0),
+ MX6_PAD_KEY_ROW2__LCD_DATA05 = IOMUX_PAD(0x0300, 0x0038, 2, 0x06EC, 0, 0),
+ MX6_PAD_KEY_ROW2__CSI_DATA13 = IOMUX_PAD(0x0300, 0x0038, 3, 0x05BC, 1, 0),
+ MX6_PAD_KEY_ROW2__SD3_DATA7 = IOMUX_PAD(0x0300, 0x0038, 4, 0x0790, 0, 0),
+ MX6_PAD_KEY_ROW2__GPIO3_IO29 = IOMUX_PAD(0x0300, 0x0038, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x0304, 0x003C, 0, 0x06AC, 0, 0),
+ MX6_PAD_KEY_COL3__AUD6_RXFS = IOMUX_PAD(0x0304, 0x003C, 1, 0x05A0, 1, 0),
+ MX6_PAD_KEY_COL3__LCD_DATA06 = IOMUX_PAD(0x0304, 0x003C, 2, 0x06F0, 0, 0),
+ MX6_PAD_KEY_COL3__CSI_DATA14 = IOMUX_PAD(0x0304, 0x003C, 3, 0x05C0, 1, 0),
+ MX6_PAD_KEY_COL3__GPIO3_IO30 = IOMUX_PAD(0x0304, 0x003C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__SD1_RESET = IOMUX_PAD(0x0304, 0x003C, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x0308, 0x0040, 0, 0x06CC, 1, 0),
+ MX6_PAD_KEY_ROW3__AUD6_RXC = IOMUX_PAD(0x0308, 0x0040, 1, 0x059C, 1, 0),
+ MX6_PAD_KEY_ROW3__LCD_DATA07 = IOMUX_PAD(0x0308, 0x0040, 2, 0x06F4, 1, 0),
+ MX6_PAD_KEY_ROW3__CSI_DATA15 = IOMUX_PAD(0x0308, 0x0040, 3, 0x05C4, 2, 0),
+ MX6_PAD_KEY_ROW3__GPIO3_IO31 = IOMUX_PAD(0x0308, 0x0040, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x0308, 0x0040, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x030C, 0x0044, 0, 0x06B0, 1, 0),
+ MX6_PAD_KEY_COL4__AUD6_RXD = IOMUX_PAD(0x030C, 0x0044, 1, 0x0594, 1, 0),
+ MX6_PAD_KEY_COL4__LCD_DATA08 = IOMUX_PAD(0x030C, 0x0044, 2, 0x06F8, 1, 0),
+ MX6_PAD_KEY_COL4__CSI_DATA16 = IOMUX_PAD(0x030C, 0x0044, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__GPIO4_IO00 = IOMUX_PAD(0x030C, 0x0044, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__USB_OTG1_PWR = IOMUX_PAD(0x030C, 0x0044, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0310, 0x0048, 0, 0x06D0, 1, 0),
+ MX6_PAD_KEY_ROW4__AUD6_TXC = IOMUX_PAD(0x0310, 0x0048, 1, 0x05A4, 1, 0),
+ MX6_PAD_KEY_ROW4__LCD_DATA09 = IOMUX_PAD(0x0310, 0x0048, 2, 0x06FC, 1, 0),
+ MX6_PAD_KEY_ROW4__CSI_DATA17 = IOMUX_PAD(0x0310, 0x0048, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__GPIO4_IO01 = IOMUX_PAD(0x0310, 0x0048, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__USB_OTG1_OC = IOMUX_PAD(0x0310, 0x0048, 6, 0x076C, 2, 0),
+
+ MX6_PAD_KEY_COL5__KEY_COL5 = IOMUX_PAD(0x0314, 0x004C, 0, 0x0694, 1, 0),
+ MX6_PAD_KEY_COL5__AUD6_TXFS = IOMUX_PAD(0x0314, 0x004C, 1, 0x05A8, 1, 0),
+ MX6_PAD_KEY_COL5__LCD_DATA10 = IOMUX_PAD(0x0314, 0x004C, 2, 0x0700, 0, 0),
+ MX6_PAD_KEY_COL5__CSI_DATA18 = IOMUX_PAD(0x0314, 0x004C, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL5__GPIO4_IO02 = IOMUX_PAD(0x0314, 0x004C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL5__USB_OTG2_PWR = IOMUX_PAD(0x0314, 0x004C, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW5__KEY_ROW5 = IOMUX_PAD(0x0318, 0x0050, 0, 0x06B4, 2, 0),
+ MX6_PAD_KEY_ROW5__AUD6_TXD = IOMUX_PAD(0x0318, 0x0050, 1, 0x0598, 1, 0),
+ MX6_PAD_KEY_ROW5__LCD_DATA11 = IOMUX_PAD(0x0318, 0x0050, 2, 0x0704, 1, 0),
+ MX6_PAD_KEY_ROW5__CSI_DATA19 = IOMUX_PAD(0x0318, 0x0050, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW5__GPIO4_IO03 = IOMUX_PAD(0x0318, 0x0050, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW5__USB_OTG2_OC = IOMUX_PAD(0x0318, 0x0050, 6, 0x0768, 3, 0),
+
+ MX6_PAD_KEY_COL6__KEY_COL6 = IOMUX_PAD(0x031C, 0x0054, 0, 0x0698, 2, 0),
+ MX6_PAD_KEY_COL6__UART4_DCE_RX = IOMUX_PAD(0x031C, 0x0054, 1, 0x075C, 2, 0),
+ MX6_PAD_KEY_COL6__UART4_DTE_TX = IOMUX_PAD(0x031C, 0x0054, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL6__LCD_DATA12 = IOMUX_PAD(0x031C, 0x0054, 2, 0x0708, 1, 0),
+ MX6_PAD_KEY_COL6__CSI_DATA20 = IOMUX_PAD(0x031C, 0x0054, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL6__GPIO4_IO04 = IOMUX_PAD(0x031C, 0x0054, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL6__SD3_RESET = IOMUX_PAD(0x031C, 0x0054, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW6__KEY_ROW6 = IOMUX_PAD(0x0320, 0x0058, 0, 0x06B8, 2, 0),
+ MX6_PAD_KEY_ROW6__UART4_DCE_TX = IOMUX_PAD(0x0320, 0x0058, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW6__UART4_DTE_RX = IOMUX_PAD(0x0320, 0x0058, 1, 0x075C, 3, 0),
+ MX6_PAD_KEY_ROW6__LCD_DATA13 = IOMUX_PAD(0x0320, 0x0058, 2, 0x070C, 1, 0),
+ MX6_PAD_KEY_ROW6__CSI_DATA21 = IOMUX_PAD(0x0320, 0x0058, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW6__GPIO4_IO05 = IOMUX_PAD(0x0320, 0x0058, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW6__SD3_VSELECT = IOMUX_PAD(0x0320, 0x0058, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL7__KEY_COL7 = IOMUX_PAD(0x0324, 0x005C, 0, 0x069C, 2, 0),
+ MX6_PAD_KEY_COL7__UART4_DCE_RTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0758, 2, 0),
+ MX6_PAD_KEY_COL7__UART4_DTE_CTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL7__LCD_DATA14 = IOMUX_PAD(0x0324, 0x005C, 2, 0x0710, 1, 0),
+ MX6_PAD_KEY_COL7__CSI_DATA22 = IOMUX_PAD(0x0324, 0x005C, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL7__GPIO4_IO06 = IOMUX_PAD(0x0324, 0x005C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL7__SD1_WP = IOMUX_PAD(0x0324, 0x005C, 6, 0x0774, 3, 0),
+
+ MX6_PAD_KEY_ROW7__KEY_ROW7 = IOMUX_PAD(0x0328, 0x0060, 0, 0x06BC, 2, 0),
+ MX6_PAD_KEY_ROW7__UART4_DCE_CTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__UART4_DTE_RTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0758, 3, 0),
+ MX6_PAD_KEY_ROW7__LCD_DATA15 = IOMUX_PAD(0x0328, 0x0060, 2, 0x0714, 1, 0),
+ MX6_PAD_KEY_ROW7__CSI_DATA23 = IOMUX_PAD(0x0328, 0x0060, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__GPIO4_IO07 = IOMUX_PAD(0x0328, 0x0060, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__SD1_CD_B = IOMUX_PAD(0x0328, 0x0060, 6, 0x0770, 3, 0),
+
+ MX6_PAD_EPDC_DATA00__EPDC_DATA00 = IOMUX_PAD(0x032C, 0x0064, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA00__ECSPI4_MOSI = IOMUX_PAD(0x032C, 0x0064, 1, 0x0658, 2, 0),
+ MX6_PAD_EPDC_DATA00__LCD_DATA24 = IOMUX_PAD(0x032C, 0x0064, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA00__CSI_DATA00 = IOMUX_PAD(0x032C, 0x0064, 3, 0x05C8, 2, 0),
+ MX6_PAD_EPDC_DATA00__GPIO1_IO07 = IOMUX_PAD(0x032C, 0x0064, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA01__EPDC_DATA01 = IOMUX_PAD(0x0330, 0x0068, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA01__ECSPI4_MISO = IOMUX_PAD(0x0330, 0x0068, 1, 0x0654, 2, 0),
+ MX6_PAD_EPDC_DATA01__LCD_DATA25 = IOMUX_PAD(0x0330, 0x0068, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA01__CSI_DATA01 = IOMUX_PAD(0x0330, 0x0068, 3, 0x05CC, 2, 0),
+ MX6_PAD_EPDC_DATA01__GPIO1_IO08 = IOMUX_PAD(0x0330, 0x0068, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA02__EPDC_DATA02 = IOMUX_PAD(0x0334, 0x006C, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA02__ECSPI4_SS0 = IOMUX_PAD(0x0334, 0x006C, 1, 0x065C, 2, 0),
+ MX6_PAD_EPDC_DATA02__LCD_DATA26 = IOMUX_PAD(0x0334, 0x006C, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA02__CSI_DATA02 = IOMUX_PAD(0x0334, 0x006C, 3, 0x05D0, 2, 0),
+ MX6_PAD_EPDC_DATA02__GPIO1_IO09 = IOMUX_PAD(0x0334, 0x006C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA03__EPDC_DATA03 = IOMUX_PAD(0x0338, 0x0070, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA03__ECSPI4_SCLK = IOMUX_PAD(0x0338, 0x0070, 1, 0x0650, 2, 0),
+ MX6_PAD_EPDC_DATA03__LCD_DATA27 = IOMUX_PAD(0x0338, 0x0070, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA03__CSI_DATA03 = IOMUX_PAD(0x0338, 0x0070, 3, 0x05D4, 2, 0),
+ MX6_PAD_EPDC_DATA03__GPIO1_IO10 = IOMUX_PAD(0x0338, 0x0070, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA04__EPDC_DATA04 = IOMUX_PAD(0x033C, 0x0074, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA04__ECSPI4_SS1 = IOMUX_PAD(0x033C, 0x0074, 1, 0x0660, 1, 0),
+ MX6_PAD_EPDC_DATA04__LCD_DATA28 = IOMUX_PAD(0x033C, 0x0074, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA04__CSI_DATA04 = IOMUX_PAD(0x033C, 0x0074, 3, 0x05D8, 2, 0),
+ MX6_PAD_EPDC_DATA04__GPIO1_IO11 = IOMUX_PAD(0x033C, 0x0074, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA05__EPDC_DATA05 = IOMUX_PAD(0x0340, 0x0078, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA05__ECSPI4_SS2 = IOMUX_PAD(0x0340, 0x0078, 1, 0x0664, 1, 0),
+ MX6_PAD_EPDC_DATA05__LCD_DATA29 = IOMUX_PAD(0x0340, 0x0078, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA05__CSI_DATA05 = IOMUX_PAD(0x0340, 0x0078, 3, 0x05DC, 2, 0),
+ MX6_PAD_EPDC_DATA05__GPIO1_IO12 = IOMUX_PAD(0x0340, 0x0078, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA06__EPDC_DATA06 = IOMUX_PAD(0x0344, 0x007C, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA06__ECSPI4_SS3 = IOMUX_PAD(0x0344, 0x007C, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA06__LCD_DATA30 = IOMUX_PAD(0x0344, 0x007C, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA06__CSI_DATA06 = IOMUX_PAD(0x0344, 0x007C, 3, 0x05E0, 2, 0),
+ MX6_PAD_EPDC_DATA06__GPIO1_IO13 = IOMUX_PAD(0x0344, 0x007C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA07__EPDC_DATA07 = IOMUX_PAD(0x0348, 0x0080, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA07__ECSPI4_RDY = IOMUX_PAD(0x0348, 0x0080, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA07__LCD_DATA31 = IOMUX_PAD(0x0348, 0x0080, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA07__CSI_DATA07 = IOMUX_PAD(0x0348, 0x0080, 3, 0x05E4, 2, 0),
+ MX6_PAD_EPDC_DATA07__GPIO1_IO14 = IOMUX_PAD(0x0348, 0x0080, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA08__EPDC_DATA08 = IOMUX_PAD(0x034C, 0x0084, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA08__ECSPI3_MOSI = IOMUX_PAD(0x034C, 0x0084, 1, 0x063C, 2, 0),
+ MX6_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 = IOMUX_PAD(0x034C, 0x0084, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA08__GPIO1_IO15 = IOMUX_PAD(0x034C, 0x0084, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA09__EPDC_DATA09 = IOMUX_PAD(0x0350, 0x0088, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA09__ECSPI3_MISO = IOMUX_PAD(0x0350, 0x0088, 1, 0x0638, 2, 0),
+ MX6_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 = IOMUX_PAD(0x0350, 0x0088, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA09__GPIO1_IO16 = IOMUX_PAD(0x0350, 0x0088, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x0354, 0x008C, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA10__ECSPI3_SS0 = IOMUX_PAD(0x0354, 0x008C, 1, 0x0648, 2, 0),
+ MX6_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 = IOMUX_PAD(0x0354, 0x008C, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA10__GPIO1_IO17 = IOMUX_PAD(0x0354, 0x008C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x0358, 0x0090, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA11__ECSPI3_SCLK = IOMUX_PAD(0x0358, 0x0090, 1, 0x0630, 2, 0),
+ MX6_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 = IOMUX_PAD(0x0358, 0x0090, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA11__GPIO1_IO18 = IOMUX_PAD(0x0358, 0x0090, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x035C, 0x0094, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA12__UART2_DCE_RX = IOMUX_PAD(0x035C, 0x0094, 1, 0x074C, 4, 0),
+ MX6_PAD_EPDC_DATA12__UART2_DTE_TX = IOMUX_PAD(0x035C, 0x0094, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA12__EPDC_PWR_COM = IOMUX_PAD(0x035C, 0x0094, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA12__GPIO1_IO19 = IOMUX_PAD(0x035C, 0x0094, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA12__ECSPI3_SS1 = IOMUX_PAD(0x035C, 0x0094, 6, 0x064C, 1, 0),
+
+ MX6_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x0360, 0x0098, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA13__UART2_DCE_TX = IOMUX_PAD(0x0360, 0x0098, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA13__UART2_DTE_RX = IOMUX_PAD(0x0360, 0x0098, 1, 0x074C, 5, 0),
+ MX6_PAD_EPDC_DATA13__EPDC_PWR_IRQ = IOMUX_PAD(0x0360, 0x0098, 2, 0x0668, 0, 0),
+ MX6_PAD_EPDC_DATA13__GPIO1_IO20 = IOMUX_PAD(0x0360, 0x0098, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA13__ECSPI3_SS2 = IOMUX_PAD(0x0360, 0x0098, 6, 0x0640, 1, 0),
+
+ MX6_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x0364, 0x009C, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA14__UART2_DCE_RTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0748, 4, 0),
+ MX6_PAD_EPDC_DATA14__UART2_DTE_CTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA14__EPDC_PWR_STAT = IOMUX_PAD(0x0364, 0x009C, 2, 0x066C, 0, 0),
+ MX6_PAD_EPDC_DATA14__GPIO1_IO21 = IOMUX_PAD(0x0364, 0x009C, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA14__ECSPI3_SS3 = IOMUX_PAD(0x0364, 0x009C, 6, 0x0644, 1, 0),
+
+ MX6_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x0368, 0x00A0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA15__UART2_DCE_CTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA15__UART2_DTE_RTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0748, 5, 0),
+ MX6_PAD_EPDC_DATA15__EPDC_PWR_WAKE = IOMUX_PAD(0x0368, 0x00A0, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA15__GPIO1_IO22 = IOMUX_PAD(0x0368, 0x00A0, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA15__ECSPI3_RDY = IOMUX_PAD(0x0368, 0x00A0, 6, 0x0634, 1, 0),
+
+ MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P = IOMUX_PAD(0x036C, 0x00A4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCLK__ECSPI2_MOSI = IOMUX_PAD(0x036C, 0x00A4, 1, 0x0624, 2, 0),
+ MX6_PAD_EPDC_SDCLK__I2C2_SCL = IOMUX_PAD(0x036C, 0x00A4, IOMUX_CONFIG_SION | 2, 0x0684, 2, 0),
+ MX6_PAD_EPDC_SDCLK__CSI_DATA08 = IOMUX_PAD(0x036C, 0x00A4, 3, 0x05E8, 2, 0),
+ MX6_PAD_EPDC_SDCLK__GPIO1_IO23 = IOMUX_PAD(0x036C, 0x00A4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0370, 0x00A8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDLE__ECSPI2_MISO = IOMUX_PAD(0x0370, 0x00A8, 1, 0x0620, 2, 0),
+ MX6_PAD_EPDC_SDLE__I2C2_SDA = IOMUX_PAD(0x0370, 0x00A8, IOMUX_CONFIG_SION | 2, 0x0688, 2, 0),
+ MX6_PAD_EPDC_SDLE__CSI_DATA09 = IOMUX_PAD(0x0370, 0x00A8, 3, 0x05EC, 2, 0),
+ MX6_PAD_EPDC_SDLE__GPIO1_IO24 = IOMUX_PAD(0x0370, 0x00A8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0374, 0x00AC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDOE__ECSPI2_SS0 = IOMUX_PAD(0x0374, 0x00AC, 1, 0x0628, 1, 0),
+ MX6_PAD_EPDC_SDOE__CSI_DATA10 = IOMUX_PAD(0x0374, 0x00AC, 3, 0x05B0, 2, 0),
+ MX6_PAD_EPDC_SDOE__GPIO1_IO25 = IOMUX_PAD(0x0374, 0x00AC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x0378, 0x00B0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDSHR__ECSPI2_SCLK = IOMUX_PAD(0x0378, 0x00B0, 1, 0x061C, 2, 0),
+ MX6_PAD_EPDC_SDSHR__EPDC_SDCE4 = IOMUX_PAD(0x0378, 0x00B0, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDSHR__CSI_DATA11 = IOMUX_PAD(0x0378, 0x00B0, 3, 0x05B4, 2, 0),
+ MX6_PAD_EPDC_SDSHR__GPIO1_IO26 = IOMUX_PAD(0x0378, 0x00B0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x037C, 0x00B4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE0__ECSPI2_SS1 = IOMUX_PAD(0x037C, 0x00B4, 1, 0x062C, 1, 0),
+ MX6_PAD_EPDC_SDCE0__PWM3_OUT = IOMUX_PAD(0x037C, 0x00B4, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE0__GPIO1_IO27 = IOMUX_PAD(0x037C, 0x00B4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x0380, 0x00B8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE1__WDOG2_B = IOMUX_PAD(0x0380, 0x00B8, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE1__PWM4_OUT = IOMUX_PAD(0x0380, 0x00B8, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE1__GPIO1_IO28 = IOMUX_PAD(0x0380, 0x00B8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x0384, 0x00BC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE2__I2C3_SCL = IOMUX_PAD(0x0384, 0x00BC, IOMUX_CONFIG_SION | 1, 0x068C, 2, 0),
+ MX6_PAD_EPDC_SDCE2__PWM1_OUT = IOMUX_PAD(0x0384, 0x00BC, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE2__GPIO1_IO29 = IOMUX_PAD(0x0384, 0x00BC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0388, 0x00C0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE3__I2C3_SDA = IOMUX_PAD(0x0388, 0x00C0, IOMUX_CONFIG_SION | 1, 0x0690, 2, 0),
+ MX6_PAD_EPDC_SDCE3__PWM2_OUT = IOMUX_PAD(0x0388, 0x00C0, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE3__GPIO1_IO30 = IOMUX_PAD(0x0388, 0x00C0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x038C, 0x00C4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDCLK__ECSPI2_SS2 = IOMUX_PAD(0x038C, 0x00C4, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDCLK__CSI_PIXCLK = IOMUX_PAD(0x038C, 0x00C4, 3, 0x05F4, 2, 0),
+ MX6_PAD_EPDC_GDCLK__GPIO1_IO31 = IOMUX_PAD(0x038C, 0x00C4, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDCLK__SD2_RESET = IOMUX_PAD(0x038C, 0x00C4, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0390, 0x00C8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDOE__ECSPI2_SS3 = IOMUX_PAD(0x0390, 0x00C8, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDOE__CSI_HSYNC = IOMUX_PAD(0x0390, 0x00C8, 3, 0x05F0, 2, 0),
+ MX6_PAD_EPDC_GDOE__GPIO2_IO00 = IOMUX_PAD(0x0390, 0x00C8, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDOE__SD2_VSELECT = IOMUX_PAD(0x0390, 0x00C8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x0394, 0x00CC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDRL__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x00CC, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDRL__CSI_MCLK = IOMUX_PAD(0x0394, 0x00CC, 3, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDRL__GPIO2_IO01 = IOMUX_PAD(0x0394, 0x00CC, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDRL__SD2_WP = IOMUX_PAD(0x0394, 0x00CC, 6, 0x077C, 2, 0),
+
+ MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0398, 0x00D0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDSP__PWM4_OUT = IOMUX_PAD(0x0398, 0x00D0, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDSP__CSI_VSYNC = IOMUX_PAD(0x0398, 0x00D0, 3, 0x05F8, 2, 0),
+ MX6_PAD_EPDC_GDSP__GPIO2_IO02 = IOMUX_PAD(0x0398, 0x00D0, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDSP__SD2_CD_B = IOMUX_PAD(0x0398, 0x00D0, 6, 0x0778, 2, 0),
+
+ MX6_PAD_EPDC_VCOM0__EPDC_VCOM0 = IOMUX_PAD(0x039C, 0x00D4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM0__AUD5_RXFS = IOMUX_PAD(0x039C, 0x00D4, 1, 0x0588, 1, 0),
+ MX6_PAD_EPDC_VCOM0__UART3_DCE_RX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0754, 4, 0),
+ MX6_PAD_EPDC_VCOM0__UART3_DTE_TX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM0__GPIO2_IO03 = IOMUX_PAD(0x039C, 0x00D4, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM0__EPDC_SDCE5 = IOMUX_PAD(0x039C, 0x00D4, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_VCOM1__EPDC_VCOM1 = IOMUX_PAD(0x03A0, 0x00D8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM1__AUD5_RXD = IOMUX_PAD(0x03A0, 0x00D8, 1, 0x057C, 1, 0),
+ MX6_PAD_EPDC_VCOM1__UART3_DCE_TX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM1__UART3_DTE_RX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0754, 5, 0),
+ MX6_PAD_EPDC_VCOM1__GPIO2_IO04 = IOMUX_PAD(0x03A0, 0x00D8, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM1__EPDC_SDCE6 = IOMUX_PAD(0x03A0, 0x00D8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x03A4, 0x00DC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR0__UART3_DCE_RTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0750, 2, 0),
+ MX6_PAD_EPDC_BDR0__UART3_DTE_CTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR0__GPIO2_IO05 = IOMUX_PAD(0x03A4, 0x00DC, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR0__EPDC_SDCE7 = IOMUX_PAD(0x03A4, 0x00DC, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x03A8, 0x00E0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR1__UART3_DCE_CTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR1__UART3_DTE_RTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0750, 3, 0),
+ MX6_PAD_EPDC_BDR1__GPIO2_IO06 = IOMUX_PAD(0x03A8, 0x00E0, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR1__EPDC_SDCE8 = IOMUX_PAD(0x03A8, 0x00E0, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03AC, 0x00E4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_CTRL0__AUD5_RXC = IOMUX_PAD(0x03AC, 0x00E4, 1, 0x0584, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL0__LCD_DATA16 = IOMUX_PAD(0x03AC, 0x00E4, 2, 0x0718, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 = IOMUX_PAD(0x03AC, 0x00E4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03B0, 0x00E8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_CTRL1__AUD5_TXFS = IOMUX_PAD(0x03B0, 0x00E8, 1, 0x0590, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL1__LCD_DATA17 = IOMUX_PAD(0x03B0, 0x00E8, 2, 0x071C, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 = IOMUX_PAD(0x03B0, 0x00E8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03B4, 0x00EC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_CTRL2__AUD5_TXD = IOMUX_PAD(0x03B4, 0x00EC, 1, 0x0580, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL2__LCD_DATA18 = IOMUX_PAD(0x03B4, 0x00EC, 2, 0x0720, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 = IOMUX_PAD(0x03B4, 0x00EC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03B8, 0x00F0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_CTRL3__AUD5_TXC = IOMUX_PAD(0x03B8, 0x00F0, 1, 0x058C, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL3__LCD_DATA19 = IOMUX_PAD(0x03B8, 0x00F0, 2, 0x0724, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 = IOMUX_PAD(0x03B8, 0x00F0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x03BC, 0x00F4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_COM__LCD_DATA20 = IOMUX_PAD(0x03BC, 0x00F4, 2, 0x0728, 1, 0),
+ MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID = IOMUX_PAD(0x03BC, 0x00F4, 4, 0x055C, 4, 0),
+ MX6_PAD_EPDC_PWR_COM__GPIO2_IO11 = IOMUX_PAD(0x03BC, 0x00F4, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_COM__SD3_RESET = IOMUX_PAD(0x03BC, 0x00F4, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ = IOMUX_PAD(0x03C0, 0x00F8, 0, 0x0668, 1, 0),
+ MX6_PAD_EPDC_PWR_IRQ__LCD_DATA21 = IOMUX_PAD(0x03C0, 0x00F8, 2, 0x072C, 1, 0),
+ MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID = IOMUX_PAD(0x03C0, 0x00F8, 4, 0x0560, 3, 0),
+ MX6_PAD_EPDC_PWR_IRQ__GPIO2_IO12 = IOMUX_PAD(0x03C0, 0x00F8, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_IRQ__SD3_VSELECT = IOMUX_PAD(0x03C0, 0x00F8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x03C4, 0x00FC, 0, 0x066C, 1, 0),
+ MX6_PAD_EPDC_PWR_STAT__LCD_DATA22 = IOMUX_PAD(0x03C4, 0x00FC, 2, 0x0730, 1, 0),
+ MX6_PAD_EPDC_PWR_STAT__ARM_EVENTI = IOMUX_PAD(0x03C4, 0x00FC, 4, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 = IOMUX_PAD(0x03C4, 0x00FC, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_STAT__SD3_WP = IOMUX_PAD(0x03C4, 0x00FC, 6, 0x0794, 2, 0),
+
+ MX6_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE = IOMUX_PAD(0x03C8, 0x0100, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_WAKE__LCD_DATA23 = IOMUX_PAD(0x03C8, 0x0100, 2, 0x0734, 1, 0),
+ MX6_PAD_EPDC_PWR_WAKE__ARM_EVENTO = IOMUX_PAD(0x03C8, 0x0100, 4, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 = IOMUX_PAD(0x03C8, 0x0100, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_WAKE__SD3_CD_B = IOMUX_PAD(0x03C8, 0x0100, 6, 0x0780, 2, 0),
+
+ MX6_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x03CC, 0x0104, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__LCD_WR_RWN = IOMUX_PAD(0x03CC, 0x0104, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__PWM4_OUT = IOMUX_PAD(0x03CC, 0x0104, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__GPIO2_IO15 = IOMUX_PAD(0x03CC, 0x0104, 5, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x03D0, 0x0108, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__LCD_RD_E = IOMUX_PAD(0x03D0, 0x0108, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__UART2_DCE_RX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__UART2_DTE_TX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__GPIO2_IO16 = IOMUX_PAD(0x03D0, 0x0108, 5, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x03D4, 0x010C, 0, 0x06D4, 0, 0),
+ MX6_PAD_LCD_HSYNC__LCD_CS = IOMUX_PAD(0x03D4, 0x010C, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__UART2_DCE_TX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__UART2_DTE_RX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x074C, 1, 0),
+ MX6_PAD_LCD_HSYNC__GPIO2_IO17 = IOMUX_PAD(0x03D4, 0x010C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__ARM_TRACE_CLK = IOMUX_PAD(0x03D4, 0x010C, 6, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x03D8, 0x0110, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__LCD_RS = IOMUX_PAD(0x03D8, 0x0110, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__UART2_DCE_RTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0748, 0, 0),
+ MX6_PAD_LCD_VSYNC__UART2_DTE_CTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__GPIO2_IO18 = IOMUX_PAD(0x03D8, 0x0110, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__ARM_TRACE_CTL = IOMUX_PAD(0x03D8, 0x0110, 6, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x03DC, 0x0114, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__LCD_BUSY = IOMUX_PAD(0x03DC, 0x0114, 2, 0x06D4, 1, 0),
+ MX6_PAD_LCD_RESET__UART2_DCE_CTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__UART2_DTE_RTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0748, 1, 0),
+ MX6_PAD_LCD_RESET__GPIO2_IO19 = IOMUX_PAD(0x03DC, 0x0114, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__CCM_PMIC_READY = IOMUX_PAD(0x03DC, 0x0114, 6, 0x05AC, 2, 0),
+
+ MX6_PAD_LCD_DATA00__LCD_DATA00 = IOMUX_PAD(0x03E0, 0x0118, 0, 0x06D8, 1, 0),
+ MX6_PAD_LCD_DATA00__ECSPI1_MOSI = IOMUX_PAD(0x03E0, 0x0118, 1, 0x0608, 0, 0),
+ MX6_PAD_LCD_DATA00__USB_OTG2_ID = IOMUX_PAD(0x03E0, 0x0118, 2, 0x0560, 2, 0),
+ MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03E0, 0x0118, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__UART5_DTR_B = IOMUX_PAD(0x03E0, 0x0118, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__GPIO2_IO20 = IOMUX_PAD(0x03E0, 0x0118, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__ARM_TRACE00 = IOMUX_PAD(0x03E0, 0x0118, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__SRC_BOOT_CFG00 = IOMUX_PAD(0x03E0, 0x0118, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA01__LCD_DATA01 = IOMUX_PAD(0x03E4, 0x011C, 0, 0x06DC, 1, 0),
+ MX6_PAD_LCD_DATA01__ECSPI1_MISO = IOMUX_PAD(0x03E4, 0x011C, 1, 0x0604, 0, 0),
+ MX6_PAD_LCD_DATA01__USB_OTG1_ID = IOMUX_PAD(0x03E4, 0x011C, 2, 0x055C, 3, 0),
+ MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03E4, 0x011C, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__AUD4_RXFS = IOMUX_PAD(0x03E4, 0x011C, 4, 0x0570, 0, 0),
+ MX6_PAD_LCD_DATA01__GPIO2_IO21 = IOMUX_PAD(0x03E4, 0x011C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__ARM_TRACE01 = IOMUX_PAD(0x03E4, 0x011C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__SRC_BOOT_CFG01 = IOMUX_PAD(0x03E4, 0x011C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA02__LCD_DATA02 = IOMUX_PAD(0x03E8, 0x0120, 0, 0x06E0, 1, 0),
+ MX6_PAD_LCD_DATA02__ECSPI1_SS0 = IOMUX_PAD(0x03E8, 0x0120, 1, 0x0614, 0, 0),
+ MX6_PAD_LCD_DATA02__EPIT2_OUT = IOMUX_PAD(0x03E8, 0x0120, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03E8, 0x0120, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__AUD4_RXC = IOMUX_PAD(0x03E8, 0x0120, 4, 0x056C, 0, 0),
+ MX6_PAD_LCD_DATA02__GPIO2_IO22 = IOMUX_PAD(0x03E8, 0x0120, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__ARM_TRACE02 = IOMUX_PAD(0x03E8, 0x0120, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__SRC_BOOT_CFG02 = IOMUX_PAD(0x03E8, 0x0120, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA03__LCD_DATA03 = IOMUX_PAD(0x03EC, 0x0124, 0, 0x06E4, 1, 0),
+ MX6_PAD_LCD_DATA03__ECSPI1_SCLK = IOMUX_PAD(0x03EC, 0x0124, 1, 0x05FC, 0, 0),
+ MX6_PAD_LCD_DATA03__UART5_DSR_B = IOMUX_PAD(0x03EC, 0x0124, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03EC, 0x0124, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__AUD4_RXD = IOMUX_PAD(0x03EC, 0x0124, 4, 0x0564, 0, 0),
+ MX6_PAD_LCD_DATA03__GPIO2_IO23 = IOMUX_PAD(0x03EC, 0x0124, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__ARM_TRACE03 = IOMUX_PAD(0x03EC, 0x0124, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__SRC_BOOT_CFG03 = IOMUX_PAD(0x03EC, 0x0124, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA04__LCD_DATA04 = IOMUX_PAD(0x03F0, 0x0128, 0, 0x06E8, 1, 0),
+ MX6_PAD_LCD_DATA04__ECSPI1_SS1 = IOMUX_PAD(0x03F0, 0x0128, 1, 0x060C, 1, 0),
+ MX6_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x03F0, 0x0128, 2, 0x05F8, 0, 0),
+ MX6_PAD_LCD_DATA04__WDOG2_RESET_B_DEB = IOMUX_PAD(0x03F0, 0x0128, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__AUD4_TXC = IOMUX_PAD(0x03F0, 0x0128, 4, 0x0574, 0, 0),
+ MX6_PAD_LCD_DATA04__GPIO2_IO24 = IOMUX_PAD(0x03F0, 0x0128, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__ARM_TRACE04 = IOMUX_PAD(0x03F0, 0x0128, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__SRC_BOOT_CFG04 = IOMUX_PAD(0x03F0, 0x0128, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA05__LCD_DATA05 = IOMUX_PAD(0x03F4, 0x012C, 0, 0x06EC, 1, 0),
+ MX6_PAD_LCD_DATA05__ECSPI1_SS2 = IOMUX_PAD(0x03F4, 0x012C, 1, 0x0610, 1, 0),
+ MX6_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x03F4, 0x012C, 2, 0x05F0, 0, 0),
+ MX6_PAD_LCD_DATA05__AUD4_TXFS = IOMUX_PAD(0x03F4, 0x012C, 4, 0x0578, 0, 0),
+ MX6_PAD_LCD_DATA05__GPIO2_IO25 = IOMUX_PAD(0x03F4, 0x012C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__ARM_TRACE05 = IOMUX_PAD(0x03F4, 0x012C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__SRC_BOOT_CFG05 = IOMUX_PAD(0x03F4, 0x012C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA06__LCD_DATA06 = IOMUX_PAD(0x03F8, 0x0130, 0, 0x06F0, 1, 0),
+ MX6_PAD_LCD_DATA06__ECSPI1_SS3 = IOMUX_PAD(0x03F8, 0x0130, 1, 0x0618, 0, 0),
+ MX6_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x03F8, 0x0130, 2, 0x05F4, 0, 0),
+ MX6_PAD_LCD_DATA06__AUD4_TXD = IOMUX_PAD(0x03F8, 0x0130, 4, 0x0568, 0, 0),
+ MX6_PAD_LCD_DATA06__GPIO2_IO26 = IOMUX_PAD(0x03F8, 0x0130, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__ARM_TRACE06 = IOMUX_PAD(0x03F8, 0x0130, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__SRC_BOOT_CFG06 = IOMUX_PAD(0x03F8, 0x0130, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA07__LCD_DATA07 = IOMUX_PAD(0x03FC, 0x0134, 0, 0x06F4, 0, 0),
+ MX6_PAD_LCD_DATA07__ECSPI1_RDY = IOMUX_PAD(0x03FC, 0x0134, 1, 0x0600, 0, 0),
+ MX6_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x03FC, 0x0134, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__AUDIO_CLK_OUT = IOMUX_PAD(0x03FC, 0x0134, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__GPIO2_IO27 = IOMUX_PAD(0x03FC, 0x0134, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__ARM_TRACE07 = IOMUX_PAD(0x03FC, 0x0134, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__SRC_BOOT_CFG07 = IOMUX_PAD(0x03FC, 0x0134, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA08__LCD_DATA08 = IOMUX_PAD(0x0400, 0x0138, 0, 0x06F8, 0, 0),
+ MX6_PAD_LCD_DATA08__KEY_COL0 = IOMUX_PAD(0x0400, 0x0138, 1, 0x06A0, 1, 0),
+ MX6_PAD_LCD_DATA08__CSI_DATA09 = IOMUX_PAD(0x0400, 0x0138, 2, 0x05EC, 0, 0),
+ MX6_PAD_LCD_DATA08__ECSPI2_SCLK = IOMUX_PAD(0x0400, 0x0138, 4, 0x061C, 0, 0),
+ MX6_PAD_LCD_DATA08__GPIO2_IO28 = IOMUX_PAD(0x0400, 0x0138, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__ARM_TRACE08 = IOMUX_PAD(0x0400, 0x0138, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__SRC_BOOT_CFG08 = IOMUX_PAD(0x0400, 0x0138, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA09__LCD_DATA09 = IOMUX_PAD(0x0404, 0x013C, 0, 0x06FC, 0, 0),
+ MX6_PAD_LCD_DATA09__KEY_ROW0 = IOMUX_PAD(0x0404, 0x013C, 1, 0x06C0, 1, 0),
+ MX6_PAD_LCD_DATA09__CSI_DATA08 = IOMUX_PAD(0x0404, 0x013C, 2, 0x05E8, 0, 0),
+ MX6_PAD_LCD_DATA09__ECSPI2_MOSI = IOMUX_PAD(0x0404, 0x013C, 4, 0x0624, 0, 0),
+ MX6_PAD_LCD_DATA09__GPIO2_IO29 = IOMUX_PAD(0x0404, 0x013C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__ARM_TRACE09 = IOMUX_PAD(0x0404, 0x013C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__SRC_BOOT_CFG09 = IOMUX_PAD(0x0404, 0x013C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0408, 0x0140, 0, 0x0700, 1, 0),
+ MX6_PAD_LCD_DATA10__KEY_COL1 = IOMUX_PAD(0x0408, 0x0140, 1, 0x06A4, 1, 0),
+ MX6_PAD_LCD_DATA10__CSI_DATA07 = IOMUX_PAD(0x0408, 0x0140, 2, 0x05E4, 0, 0),
+ MX6_PAD_LCD_DATA10__ECSPI2_MISO = IOMUX_PAD(0x0408, 0x0140, 4, 0x0620, 0, 0),
+ MX6_PAD_LCD_DATA10__GPIO2_IO30 = IOMUX_PAD(0x0408, 0x0140, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__ARM_TRACE10 = IOMUX_PAD(0x0408, 0x0140, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0408, 0x0140, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x040C, 0x0144, 0, 0x0704, 0, 0),
+ MX6_PAD_LCD_DATA11__KEY_ROW1 = IOMUX_PAD(0x040C, 0x0144, 1, 0x06C4, 1, 0),
+ MX6_PAD_LCD_DATA11__CSI_DATA06 = IOMUX_PAD(0x040C, 0x0144, 2, 0x05E0, 0, 0),
+ MX6_PAD_LCD_DATA11__ECSPI2_SS1 = IOMUX_PAD(0x040C, 0x0144, 4, 0x062C, 0, 0),
+ MX6_PAD_LCD_DATA11__GPIO2_IO31 = IOMUX_PAD(0x040C, 0x0144, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__ARM_TRACE11 = IOMUX_PAD(0x040C, 0x0144, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x040C, 0x0144, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0410, 0x0148, 0, 0x0708, 0, 0),
+ MX6_PAD_LCD_DATA12__KEY_COL2 = IOMUX_PAD(0x0410, 0x0148, 1, 0x06A8, 1, 0),
+ MX6_PAD_LCD_DATA12__CSI_DATA05 = IOMUX_PAD(0x0410, 0x0148, 2, 0x05DC, 0, 0),
+ MX6_PAD_LCD_DATA12__UART5_DCE_RTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0760, 0, 0),
+ MX6_PAD_LCD_DATA12__UART5_DTE_CTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__GPIO3_IO00 = IOMUX_PAD(0x0410, 0x0148, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__ARM_TRACE12 = IOMUX_PAD(0x0410, 0x0148, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0410, 0x0148, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x0414, 0x014C, 0, 0x070C, 0, 0),
+ MX6_PAD_LCD_DATA13__KEY_ROW2 = IOMUX_PAD(0x0414, 0x014C, 1, 0x06C8, 1, 0),
+ MX6_PAD_LCD_DATA13__CSI_DATA04 = IOMUX_PAD(0x0414, 0x014C, 2, 0x05D8, 0, 0),
+ MX6_PAD_LCD_DATA13__UART5_DCE_CTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__UART5_DTE_RTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0760, 1, 0),
+ MX6_PAD_LCD_DATA13__GPIO3_IO01 = IOMUX_PAD(0x0414, 0x014C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__ARM_TRACE13 = IOMUX_PAD(0x0414, 0x014C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0414, 0x014C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0418, 0x0150, 0, 0x0710, 0, 0),
+ MX6_PAD_LCD_DATA14__KEY_COL3 = IOMUX_PAD(0x0418, 0x0150, 1, 0x06AC, 1, 0),
+ MX6_PAD_LCD_DATA14__CSI_DATA03 = IOMUX_PAD(0x0418, 0x0150, 2, 0x05D4, 0, 0),
+ MX6_PAD_LCD_DATA14__UART5_DCE_RX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0764, 0, 0),
+ MX6_PAD_LCD_DATA14__UART5_DTE_TX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__GPIO3_IO02 = IOMUX_PAD(0x0418, 0x0150, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__ARM_TRACE14 = IOMUX_PAD(0x0418, 0x0150, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0418, 0x0150, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x041C, 0x0154, 0, 0x0714, 0, 0),
+ MX6_PAD_LCD_DATA15__KEY_ROW3 = IOMUX_PAD(0x041C, 0x0154, 1, 0x06CC, 0, 0),
+ MX6_PAD_LCD_DATA15__CSI_DATA02 = IOMUX_PAD(0x041C, 0x0154, 2, 0x05D0, 0, 0),
+ MX6_PAD_LCD_DATA15__UART5_DCE_TX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__UART5_DTE_RX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0764, 1, 0),
+ MX6_PAD_LCD_DATA15__GPIO3_IO03 = IOMUX_PAD(0x041C, 0x0154, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__ARM_TRACE15 = IOMUX_PAD(0x041C, 0x0154, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x041C, 0x0154, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0420, 0x0158, 0, 0x0718, 0, 0),
+ MX6_PAD_LCD_DATA16__KEY_COL4 = IOMUX_PAD(0x0420, 0x0158, 1, 0x06B0, 0, 0),
+ MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x0420, 0x0158, 2, 0x05CC, 0, 0),
+ MX6_PAD_LCD_DATA16__I2C2_SCL = IOMUX_PAD(0x0420, 0x0158, IOMUX_CONFIG_SION | 4, 0x0684, 1, 0),
+ MX6_PAD_LCD_DATA16__GPIO3_IO04 = IOMUX_PAD(0x0420, 0x0158, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__SRC_BOOT_CFG24 = IOMUX_PAD(0x0420, 0x0158, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x0424, 0x015C, 0, 0x071C, 0, 0),
+ MX6_PAD_LCD_DATA17__KEY_ROW4 = IOMUX_PAD(0x0424, 0x015C, 1, 0x06D0, 0, 0),
+ MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x0424, 0x015C, 2, 0x05C8, 0, 0),
+ MX6_PAD_LCD_DATA17__I2C2_SDA = IOMUX_PAD(0x0424, 0x015C, IOMUX_CONFIG_SION | 4, 0x0688, 1, 0),
+ MX6_PAD_LCD_DATA17__GPIO3_IO05 = IOMUX_PAD(0x0424, 0x015C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__SRC_BOOT_CFG25 = IOMUX_PAD(0x0424, 0x015C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0428, 0x0160, 0, 0x0720, 0, 0),
+ MX6_PAD_LCD_DATA18__KEY_COL5 = IOMUX_PAD(0x0428, 0x0160, 1, 0x0694, 2, 0),
+ MX6_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0428, 0x0160, 2, 0x05C4, 1, 0),
+ MX6_PAD_LCD_DATA18__GPT_CAPTURE1 = IOMUX_PAD(0x0428, 0x0160, 4, 0x0670, 1, 0),
+ MX6_PAD_LCD_DATA18__GPIO3_IO06 = IOMUX_PAD(0x0428, 0x0160, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__SRC_BOOT_CFG26 = IOMUX_PAD(0x0428, 0x0160, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x042C, 0x0164, 0, 0x0724, 0, 0),
+ MX6_PAD_LCD_DATA19__KEY_ROW5 = IOMUX_PAD(0x042C, 0x0164, 1, 0x06B4, 1, 0),
+ MX6_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x042C, 0x0164, 2, 0x05C0, 2, 0),
+ MX6_PAD_LCD_DATA19__GPT_CAPTURE2 = IOMUX_PAD(0x042C, 0x0164, 4, 0x0674, 1, 0),
+ MX6_PAD_LCD_DATA19__GPIO3_IO07 = IOMUX_PAD(0x042C, 0x0164, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__SRC_BOOT_CFG27 = IOMUX_PAD(0x042C, 0x0164, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0430, 0x0168, 0, 0x0728, 0, 0),
+ MX6_PAD_LCD_DATA20__KEY_COL6 = IOMUX_PAD(0x0430, 0x0168, 1, 0x0698, 1, 0),
+ MX6_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0430, 0x0168, 2, 0x05BC, 2, 0),
+ MX6_PAD_LCD_DATA20__GPT_COMPARE1 = IOMUX_PAD(0x0430, 0x0168, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__GPIO3_IO08 = IOMUX_PAD(0x0430, 0x0168, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__SRC_BOOT_CFG28 = IOMUX_PAD(0x0430, 0x0168, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x0434, 0x016C, 0, 0x072C, 0, 0),
+ MX6_PAD_LCD_DATA21__KEY_ROW6 = IOMUX_PAD(0x0434, 0x016C, 1, 0x06B8, 1, 0),
+ MX6_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x0434, 0x016C, 2, 0x05B8, 2, 0),
+ MX6_PAD_LCD_DATA21__GPT_COMPARE2 = IOMUX_PAD(0x0434, 0x016C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__GPIO3_IO09 = IOMUX_PAD(0x0434, 0x016C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__SRC_BOOT_CFG29 = IOMUX_PAD(0x0434, 0x016C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0438, 0x0170, 0, 0x0730, 0, 0),
+ MX6_PAD_LCD_DATA22__KEY_COL7 = IOMUX_PAD(0x0438, 0x0170, 1, 0x069C, 1, 0),
+ MX6_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0438, 0x0170, 2, 0x05B4, 1, 0),
+ MX6_PAD_LCD_DATA22__GPT_COMPARE3 = IOMUX_PAD(0x0438, 0x0170, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__GPIO3_IO10 = IOMUX_PAD(0x0438, 0x0170, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__SRC_BOOT_CFG30 = IOMUX_PAD(0x0438, 0x0170, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x043C, 0x0174, 0, 0x0734, 0, 0),
+ MX6_PAD_LCD_DATA23__KEY_ROW7 = IOMUX_PAD(0x043C, 0x0174, 1, 0x06BC, 1, 0),
+ MX6_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x043C, 0x0174, 2, 0x05B0, 1, 0),
+ MX6_PAD_LCD_DATA23__GPT_CLKIN = IOMUX_PAD(0x043C, 0x0174, 4, 0x0678, 1, 0),
+ MX6_PAD_LCD_DATA23__GPIO3_IO11 = IOMUX_PAD(0x043C, 0x0174, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__SRC_BOOT_CFG31 = IOMUX_PAD(0x043C, 0x0174, 7, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_RXFS__AUD3_RXFS = IOMUX_PAD(0x0440, 0x0178, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXFS__I2C1_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 1, 0x067C, 1, 0),
+ MX6_PAD_AUD_RXFS__UART3_DCE_RX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0754, 0, 0),
+ MX6_PAD_AUD_RXFS__UART3_DTE_TX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXFS__I2C3_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 4, 0x068C, 1, 0),
+ MX6_PAD_AUD_RXFS__GPIO1_IO00 = IOMUX_PAD(0x0440, 0x0178, 5, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXFS__ECSPI3_SS0 = IOMUX_PAD(0x0440, 0x0178, 6, 0x0648, 0, 0),
+ MX6_PAD_AUD_RXFS__MBIST_BEND = IOMUX_PAD(0x0440, 0x0178, 7, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_RXC__AUD3_RXC = IOMUX_PAD(0x0444, 0x017C, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXC__I2C1_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 1, 0x0680, 1, 0),
+ MX6_PAD_AUD_RXC__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXC__UART3_DTE_RX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0754, 1, 0),
+ MX6_PAD_AUD_RXC__I2C3_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 4, 0x0690, 1, 0),
+ MX6_PAD_AUD_RXC__GPIO1_IO01 = IOMUX_PAD(0x0444, 0x017C, 5, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXC__ECSPI3_SS1 = IOMUX_PAD(0x0444, 0x017C, 6, 0x064C, 0, 0),
+
+ MX6_PAD_AUD_RXD__AUD3_RXD = IOMUX_PAD(0x0448, 0x0180, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXD__ECSPI3_MOSI = IOMUX_PAD(0x0448, 0x0180, 1, 0x063C, 0, 0),
+ MX6_PAD_AUD_RXD__UART4_DCE_RX = IOMUX_PAD(0x0448, 0x0180, 2, 0x075C, 0, 0),
+ MX6_PAD_AUD_RXD__UART4_DTE_TX = IOMUX_PAD(0x0448, 0x0180, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXD__SD1_LCTL = IOMUX_PAD(0x0448, 0x0180, 4, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXD__GPIO1_IO02 = IOMUX_PAD(0x0448, 0x0180, 5, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_TXC__AUD3_TXC = IOMUX_PAD(0x044C, 0x0184, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXC__ECSPI3_MISO = IOMUX_PAD(0x044C, 0x0184, 1, 0x0638, 0, 0),
+ MX6_PAD_AUD_TXC__UART4_DCE_TX = IOMUX_PAD(0x044C, 0x0184, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXC__UART4_DTE_RX = IOMUX_PAD(0x044C, 0x0184, 2, 0x075C, 1, 0),
+ MX6_PAD_AUD_TXC__SD2_LCTL = IOMUX_PAD(0x044C, 0x0184, 4, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXC__GPIO1_IO03 = IOMUX_PAD(0x044C, 0x0184, 5, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_TXFS__AUD3_TXFS = IOMUX_PAD(0x0450, 0x0188, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXFS__PWM3_OUT = IOMUX_PAD(0x0450, 0x0188, 1, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXFS__UART4_DCE_RTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0758, 0, 0),
+ MX6_PAD_AUD_TXFS__UART4_DTE_CTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXFS__SD3_LCTL = IOMUX_PAD(0x0450, 0x0188, 4, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXFS__GPIO1_IO04 = IOMUX_PAD(0x0450, 0x0188, 5, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_TXD__AUD3_TXD = IOMUX_PAD(0x0454, 0x018C, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXD__ECSPI3_SCLK = IOMUX_PAD(0x0454, 0x018C, 1, 0x0630, 0, 0),
+ MX6_PAD_AUD_TXD__UART4_DCE_CTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXD__UART4_DTE_RTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0758, 1, 0),
+ MX6_PAD_AUD_TXD__GPIO1_IO05 = IOMUX_PAD(0x0454, 0x018C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_MCLK__AUDIO_CLK_OUT = IOMUX_PAD(0x0458, 0x0190, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_MCLK__PWM4_OUT = IOMUX_PAD(0x0458, 0x0190, 1, 0x0000, 0, 0),
+ MX6_PAD_AUD_MCLK__ECSPI3_RDY = IOMUX_PAD(0x0458, 0x0190, 2, 0x0634, 0, 0),
+ MX6_PAD_AUD_MCLK__WDOG2_RESET_B_DEB = IOMUX_PAD(0x0458, 0x0190, 4, 0x0000, 0, 0),
+ MX6_PAD_AUD_MCLK__GPIO1_IO06 = IOMUX_PAD(0x0458, 0x0190, 5, 0x0000, 0, 0),
+ MX6_PAD_AUD_MCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0458, 0x0190, 6, 0x073C, 1, 0),
+
+ MX6_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0744, 0, 0),
+
+ MX6_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__PWM1_OUT = IOMUX_PAD(0x045C, 0x0194, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__UART4_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 2, 0x075C, 4, 0),
+ MX6_PAD_UART1_RXD__UART4_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 2, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__UART5_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0764, 6, 0),
+ MX6_PAD_UART1_RXD__UART5_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__GPIO3_IO16 = IOMUX_PAD(0x045C, 0x0194, 5, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0744, 1, 0),
+ MX6_PAD_UART1_TXD__PWM2_OUT = IOMUX_PAD(0x0460, 0x0198, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_TXD__UART4_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 2, 0x0000, 0, 0),
+ MX6_PAD_UART1_TXD__UART4_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 2, 0x075C, 5, 0),
+ MX6_PAD_UART1_TXD__UART5_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_TXD__UART5_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0764, 7, 0),
+ MX6_PAD_UART1_TXD__GPIO3_IO17 = IOMUX_PAD(0x0460, 0x0198, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_TXD__UART5_DCD_B = IOMUX_PAD(0x0460, 0x0198, 7, 0x0000, 0, 0),
+
+ MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0464, 0x019C, IOMUX_CONFIG_SION | 0, 0x067C, 0, 0),
+ MX6_PAD_I2C1_SCL__UART1_DCE_RTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0740, 0, 0),
+ MX6_PAD_I2C1_SCL__UART1_DTE_CTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SCL__ECSPI3_SS2 = IOMUX_PAD(0x0464, 0x019C, 2, 0x0640, 0, 0),
+ MX6_PAD_I2C1_SCL__SD3_RESET = IOMUX_PAD(0x0464, 0x019C, 4, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SCL__GPIO3_IO12 = IOMUX_PAD(0x0464, 0x019C, 5, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SCL__ECSPI1_SS1 = IOMUX_PAD(0x0464, 0x019C, 6, 0x060C, 0, 0),
+
+ MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0468, 0x01A0, IOMUX_CONFIG_SION | 0, 0x0680, 0, 0),
+ MX6_PAD_I2C1_SDA__UART1_DCE_CTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SDA__UART1_DTE_RTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0740, 1, 0),
+ MX6_PAD_I2C1_SDA__ECSPI3_SS3 = IOMUX_PAD(0x0468, 0x01A0, 2, 0x0644, 0, 0),
+ MX6_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x0468, 0x01A0, 4, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SDA__GPIO3_IO13 = IOMUX_PAD(0x0468, 0x01A0, 5, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SDA__ECSPI1_SS2 = IOMUX_PAD(0x0468, 0x01A0, 6, 0x0610, 0, 0),
+
+ MX6_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x046C, 0x01A4, IOMUX_CONFIG_SION | 0, 0x0684, 3, 0),
+ MX6_PAD_I2C2_SCL__AUD4_RXFS = IOMUX_PAD(0x046C, 0x01A4, 1, 0x0570, 2, 0),
+ MX6_PAD_I2C2_SCL__SPDIF_IN = IOMUX_PAD(0x046C, 0x01A4, 2, 0x0738, 2, 0),
+ MX6_PAD_I2C2_SCL__SD3_WP = IOMUX_PAD(0x046C, 0x01A4, 4, 0x0794, 3, 0),
+ MX6_PAD_I2C2_SCL__GPIO3_IO14 = IOMUX_PAD(0x046C, 0x01A4, 5, 0x0000, 0, 0),
+ MX6_PAD_I2C2_SCL__ECSPI1_RDY = IOMUX_PAD(0x046C, 0x01A4, 6, 0x0600, 1, 0),
+
+ MX6_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0470, 0x01A8, IOMUX_CONFIG_SION | 0, 0x0688, 3, 0),
+ MX6_PAD_I2C2_SDA__AUD4_RXC = IOMUX_PAD(0x0470, 0x01A8, 1, 0x056C, 2, 0),
+ MX6_PAD_I2C2_SDA__SPDIF_OUT = IOMUX_PAD(0x0470, 0x01A8, 2, 0x0000, 0, 0),
+ MX6_PAD_I2C2_SDA__SD3_CD_B = IOMUX_PAD(0x0470, 0x01A8, 4, 0x0780, 3, 0),
+ MX6_PAD_I2C2_SDA__GPIO3_IO15 = IOMUX_PAD(0x0470, 0x01A8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0474, 0x01AC, 0, 0x05FC, 1, 0),
+ MX6_PAD_ECSPI1_SCLK__AUD4_TXD = IOMUX_PAD(0x0474, 0x01AC, 1, 0x0568, 1, 0),
+ MX6_PAD_ECSPI1_SCLK__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0764, 2, 0),
+ MX6_PAD_ECSPI1_SCLK__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SCLK__EPDC_VCOM0 = IOMUX_PAD(0x0474, 0x01AC, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SCLK__SD2_RESET = IOMUX_PAD(0x0474, 0x01AC, 4, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 = IOMUX_PAD(0x0474, 0x01AC, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0474, 0x01AC, 6, 0x0768, 1, 0),
+
+ MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0478, 0x01B0, 0, 0x0608, 1, 0),
+ MX6_PAD_ECSPI1_MOSI__AUD4_TXC = IOMUX_PAD(0x0478, 0x01B0, 1, 0x0574, 1, 0),
+ MX6_PAD_ECSPI1_MOSI__UART5_DCE_TX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MOSI__UART5_DTE_RX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0764, 3, 0),
+ MX6_PAD_ECSPI1_MOSI__EPDC_VCOM1 = IOMUX_PAD(0x0478, 0x01B0, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MOSI__SD2_VSELECT = IOMUX_PAD(0x0478, 0x01B0, 4, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MOSI__GPIO4_IO09 = IOMUX_PAD(0x0478, 0x01B0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x047C, 0x01B4, 0, 0x0604, 1, 0),
+ MX6_PAD_ECSPI1_MISO__AUD4_TXFS = IOMUX_PAD(0x047C, 0x01B4, 1, 0x0578, 1, 0),
+ MX6_PAD_ECSPI1_MISO__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0760, 2, 0),
+ MX6_PAD_ECSPI1_MISO__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MISO__EPDC_BDR0 = IOMUX_PAD(0x047C, 0x01B4, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MISO__SD2_WP = IOMUX_PAD(0x047C, 0x01B4, 4, 0x077C, 0, 0),
+ MX6_PAD_ECSPI1_MISO__GPIO4_IO10 = IOMUX_PAD(0x047C, 0x01B4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0480, 0x01B8, 0, 0x0614, 1, 0),
+ MX6_PAD_ECSPI1_SS0__AUD4_RXD = IOMUX_PAD(0x0480, 0x01B8, 1, 0x0564, 1, 0),
+ MX6_PAD_ECSPI1_SS0__UART5_DCE_CTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SS0__UART5_DTE_RTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0760, 3, 0),
+ MX6_PAD_ECSPI1_SS0__EPDC_BDR1 = IOMUX_PAD(0x0480, 0x01B8, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SS0__SD2_CD_B = IOMUX_PAD(0x0480, 0x01B8, 4, 0x0778, 0, 0),
+ MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0480, 0x01B8, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SS0__USB_OTG2_PWR = IOMUX_PAD(0x0480, 0x01B8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0484, 0x01BC, 0, 0x061C, 1, 0),
+ MX6_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0484, 0x01BC, 1, 0x073C, 2, 0),
+ MX6_PAD_ECSPI2_SCLK__UART3_DCE_RX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0754, 2, 0),
+ MX6_PAD_ECSPI2_SCLK__UART3_DTE_TX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SCLK__CSI_PIXCLK = IOMUX_PAD(0x0484, 0x01BC, 3, 0x05F4, 1, 0),
+ MX6_PAD_ECSPI2_SCLK__SD1_RESET = IOMUX_PAD(0x0484, 0x01BC, 4, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SCLK__GPIO4_IO12 = IOMUX_PAD(0x0484, 0x01BC, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0484, 0x01BC, 6, 0x0768, 2, 0),
+
+ MX6_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0488, 0x01C0, 0, 0x0624, 1, 0),
+ MX6_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0488, 0x01C0, 1, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0754, 3, 0),
+ MX6_PAD_ECSPI2_MOSI__CSI_HSYNC = IOMUX_PAD(0x0488, 0x01C0, 3, 0x05F0, 1, 0),
+ MX6_PAD_ECSPI2_MOSI__SD1_VSELECT = IOMUX_PAD(0x0488, 0x01C0, 4, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MOSI__GPIO4_IO13 = IOMUX_PAD(0x0488, 0x01C0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x048C, 0x01C4, 0, 0x0620, 1, 0),
+ MX6_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 = IOMUX_PAD(0x048C, 0x01C4, 1, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MISO__UART3_DCE_RTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0750, 0, 0),
+ MX6_PAD_ECSPI2_MISO__UART3_DTE_CTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MISO__CSI_MCLK = IOMUX_PAD(0x048C, 0x01C4, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MISO__SD1_WP = IOMUX_PAD(0x048C, 0x01C4, 4, 0x0774, 2, 0),
+ MX6_PAD_ECSPI2_MISO__GPIO4_IO14 = IOMUX_PAD(0x048C, 0x01C4, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MISO__USB_OTG1_OC = IOMUX_PAD(0x048C, 0x01C4, 6, 0x076C, 1, 0),
+
+ MX6_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0490, 0x01C8, 0, 0x0628, 0, 0),
+ MX6_PAD_ECSPI2_SS0__ECSPI1_SS3 = IOMUX_PAD(0x0490, 0x01C8, 1, 0x0618, 1, 0),
+ MX6_PAD_ECSPI2_SS0__UART3_DCE_CTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SS0__UART3_DTE_RTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0750, 1, 0),
+ MX6_PAD_ECSPI2_SS0__CSI_VSYNC = IOMUX_PAD(0x0490, 0x01C8, 3, 0x05F8, 1, 0),
+ MX6_PAD_ECSPI2_SS0__SD1_CD_B = IOMUX_PAD(0x0490, 0x01C8, 4, 0x0770, 2, 0),
+ MX6_PAD_ECSPI2_SS0__GPIO4_IO15 = IOMUX_PAD(0x0490, 0x01C8, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SS0__USB_OTG1_PWR = IOMUX_PAD(0x0490, 0x01C8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0494, 0x01CC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__KEY_COL0 = IOMUX_PAD(0x0494, 0x01CC, 2, 0x06A0, 2, 0),
+ MX6_PAD_SD1_CLK__EPDC_SDCE4 = IOMUX_PAD(0x0494, 0x01CC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPIO5_IO15 = IOMUX_PAD(0x0494, 0x01CC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0498, 0x01D0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__KEY_ROW0 = IOMUX_PAD(0x0498, 0x01D0, 2, 0x06C0, 2, 0),
+ MX6_PAD_SD1_CMD__EPDC_SDCE5 = IOMUX_PAD(0x0498, 0x01D0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPIO5_IO14 = IOMUX_PAD(0x0498, 0x01D0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x049C, 0x01D4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__KEY_COL1 = IOMUX_PAD(0x049C, 0x01D4, 2, 0x06A4, 2, 0),
+ MX6_PAD_SD1_DATA0__EPDC_SDCE6 = IOMUX_PAD(0x049C, 0x01D4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__GPIO5_IO11 = IOMUX_PAD(0x049C, 0x01D4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x04A0, 0x01D8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__KEY_ROW1 = IOMUX_PAD(0x04A0, 0x01D8, 2, 0x06C4, 2, 0),
+ MX6_PAD_SD1_DATA1__EPDC_SDCE7 = IOMUX_PAD(0x04A0, 0x01D8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__GPIO5_IO08 = IOMUX_PAD(0x04A0, 0x01D8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x04A4, 0x01DC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__KEY_COL2 = IOMUX_PAD(0x04A4, 0x01DC, 2, 0x06A8, 2, 0),
+ MX6_PAD_SD1_DATA2__EPDC_SDCE8 = IOMUX_PAD(0x04A4, 0x01DC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__GPIO5_IO13 = IOMUX_PAD(0x04A4, 0x01DC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x04A8, 0x01E0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__KEY_ROW2 = IOMUX_PAD(0x04A8, 0x01E0, 2, 0x06C8, 2, 0),
+ MX6_PAD_SD1_DATA3__EPDC_SDCE9 = IOMUX_PAD(0x04A8, 0x01E0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__GPIO5_IO06 = IOMUX_PAD(0x04A8, 0x01E0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA4__SD1_DATA4 = IOMUX_PAD(0x04AC, 0x01E4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA4__KEY_COL3 = IOMUX_PAD(0x04AC, 0x01E4, 2, 0x06AC, 2, 0),
+ MX6_PAD_SD1_DATA4__EPDC_SDCLK_N = IOMUX_PAD(0x04AC, 0x01E4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA4__UART4_DCE_RX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x075C, 6, 0),
+ MX6_PAD_SD1_DATA4__UART4_DTE_TX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA4__GPIO5_IO12 = IOMUX_PAD(0x04AC, 0x01E4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA5__SD1_DATA5 = IOMUX_PAD(0x04B0, 0x01E8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA5__KEY_ROW3 = IOMUX_PAD(0x04B0, 0x01E8, 2, 0x06CC, 2, 0),
+ MX6_PAD_SD1_DATA5__EPDC_SDOED = IOMUX_PAD(0x04B0, 0x01E8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA5__UART4_DCE_TX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA5__UART4_DTE_RX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x075C, 7, 0),
+ MX6_PAD_SD1_DATA5__GPIO5_IO09 = IOMUX_PAD(0x04B0, 0x01E8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA6__SD1_DATA6 = IOMUX_PAD(0x04B4, 0x01EC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA6__KEY_COL4 = IOMUX_PAD(0x04B4, 0x01EC, 2, 0x06B0, 2, 0),
+ MX6_PAD_SD1_DATA6__EPDC_SDOEZ = IOMUX_PAD(0x04B4, 0x01EC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA6__UART4_DCE_RTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0758, 4, 0),
+ MX6_PAD_SD1_DATA6__UART4_DTE_CTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA6__GPIO5_IO07 = IOMUX_PAD(0x04B4, 0x01EC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA7__SD1_DATA7 = IOMUX_PAD(0x04B8, 0x01F0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA7__KEY_ROW4 = IOMUX_PAD(0x04B8, 0x01F0, 2, 0x06D0, 2, 0),
+ MX6_PAD_SD1_DATA7__CCM_PMIC_READY = IOMUX_PAD(0x04B8, 0x01F0, 3, 0x05AC, 3, 0),
+ MX6_PAD_SD1_DATA7__UART4_DCE_CTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA7__UART4_DTE_RTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0758, 5, 0),
+ MX6_PAD_SD1_DATA7__GPIO5_IO10 = IOMUX_PAD(0x04B8, 0x01F0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_RESET__SD2_RESET = IOMUX_PAD(0x04BC, 0x01F4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_RESET__WDOG2_B = IOMUX_PAD(0x04BC, 0x01F4, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_RESET__SPDIF_OUT = IOMUX_PAD(0x04BC, 0x01F4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD2_RESET__CSI_MCLK = IOMUX_PAD(0x04BC, 0x01F4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_RESET__GPIO4_IO27 = IOMUX_PAD(0x04BC, 0x01F4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x04C0, 0x01F8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x04C0, 0x01F8, 1, 0x0570, 1, 0),
+ MX6_PAD_SD2_CLK__ECSPI3_SCLK = IOMUX_PAD(0x04C0, 0x01F8, 2, 0x0630, 1, 0),
+ MX6_PAD_SD2_CLK__CSI_DATA00 = IOMUX_PAD(0x04C0, 0x01F8, 3, 0x05C8, 1, 0),
+ MX6_PAD_SD2_CLK__GPIO5_IO05 = IOMUX_PAD(0x04C0, 0x01F8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x04C4, 0x01FC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x04C4, 0x01FC, 1, 0x056C, 1, 0),
+ MX6_PAD_SD2_CMD__ECSPI3_SS0 = IOMUX_PAD(0x04C4, 0x01FC, 2, 0x0648, 1, 0),
+ MX6_PAD_SD2_CMD__CSI_DATA01 = IOMUX_PAD(0x04C4, 0x01FC, 3, 0x05CC, 1, 0),
+ MX6_PAD_SD2_CMD__EPIT1_OUT = IOMUX_PAD(0x04C4, 0x01FC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__GPIO5_IO04 = IOMUX_PAD(0x04C4, 0x01FC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x04C8, 0x0200, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA0__AUD4_RXD = IOMUX_PAD(0x04C8, 0x0200, 1, 0x0564, 2, 0),
+ MX6_PAD_SD2_DATA0__ECSPI3_MOSI = IOMUX_PAD(0x04C8, 0x0200, 2, 0x063C, 1, 0),
+ MX6_PAD_SD2_DATA0__CSI_DATA02 = IOMUX_PAD(0x04C8, 0x0200, 3, 0x05D0, 1, 0),
+ MX6_PAD_SD2_DATA0__UART5_DCE_RTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0760, 4, 0),
+ MX6_PAD_SD2_DATA0__UART5_DTE_CTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA0__GPIO5_IO01 = IOMUX_PAD(0x04C8, 0x0200, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x04CC, 0x0204, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA1__AUD4_TXC = IOMUX_PAD(0x04CC, 0x0204, 1, 0x0574, 2, 0),
+ MX6_PAD_SD2_DATA1__ECSPI3_MISO = IOMUX_PAD(0x04CC, 0x0204, 2, 0x0638, 1, 0),
+ MX6_PAD_SD2_DATA1__CSI_DATA03 = IOMUX_PAD(0x04CC, 0x0204, 3, 0x05D4, 1, 0),
+ MX6_PAD_SD2_DATA1__UART5_DCE_CTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA1__UART5_DTE_RTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0760, 5, 0),
+ MX6_PAD_SD2_DATA1__GPIO4_IO30 = IOMUX_PAD(0x04CC, 0x0204, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x04D0, 0x0208, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA2__AUD4_TXFS = IOMUX_PAD(0x04D0, 0x0208, 1, 0x0578, 2, 0),
+ MX6_PAD_SD2_DATA2__CSI_DATA04 = IOMUX_PAD(0x04D0, 0x0208, 3, 0x05D8, 1, 0),
+ MX6_PAD_SD2_DATA2__UART5_DCE_RX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0764, 4, 0),
+ MX6_PAD_SD2_DATA2__UART5_DTE_TX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA2__GPIO5_IO03 = IOMUX_PAD(0x04D0, 0x0208, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x04D4, 0x020C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA3__AUD4_TXD = IOMUX_PAD(0x04D4, 0x020C, 1, 0x0568, 2, 0),
+ MX6_PAD_SD2_DATA3__CSI_DATA05 = IOMUX_PAD(0x04D4, 0x020C, 3, 0x05DC, 1, 0),
+ MX6_PAD_SD2_DATA3__UART5_DCE_TX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA3__UART5_DTE_RX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0764, 5, 0),
+ MX6_PAD_SD2_DATA3__GPIO4_IO28 = IOMUX_PAD(0x04D4, 0x020C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA4__SD2_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA4__SD3_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 1, 0x0784, 1, 0),
+ MX6_PAD_SD2_DATA4__UART2_DCE_RX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x074C, 2, 0),
+ MX6_PAD_SD2_DATA4__UART2_DTE_TX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA4__CSI_DATA06 = IOMUX_PAD(0x04D8, 0x0210, 3, 0x05E0, 1, 0),
+ MX6_PAD_SD2_DATA4__SPDIF_OUT = IOMUX_PAD(0x04D8, 0x0210, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA4__GPIO5_IO02 = IOMUX_PAD(0x04D8, 0x0210, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA5__SD2_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA5__SD3_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 1, 0x0788, 1, 0),
+ MX6_PAD_SD2_DATA5__UART2_DCE_TX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA5__UART2_DTE_RX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x074C, 3, 0),
+ MX6_PAD_SD2_DATA5__CSI_DATA07 = IOMUX_PAD(0x04DC, 0x0214, 3, 0x05E4, 1, 0),
+ MX6_PAD_SD2_DATA5__SPDIF_IN = IOMUX_PAD(0x04DC, 0x0214, 4, 0x0738, 1, 0),
+ MX6_PAD_SD2_DATA5__GPIO4_IO31 = IOMUX_PAD(0x04DC, 0x0214, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA6__SD2_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA6__SD3_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 1, 0x078C, 1, 0),
+ MX6_PAD_SD2_DATA6__UART2_DCE_RTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0748, 2, 0),
+ MX6_PAD_SD2_DATA6__UART2_DTE_CTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA6__CSI_DATA08 = IOMUX_PAD(0x04E0, 0x0218, 3, 0x05E8, 1, 0),
+ MX6_PAD_SD2_DATA6__SD2_WP = IOMUX_PAD(0x04E0, 0x0218, 4, 0x077C, 1, 0),
+ MX6_PAD_SD2_DATA6__GPIO4_IO29 = IOMUX_PAD(0x04E0, 0x0218, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA7__SD2_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA7__SD3_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 1, 0x0790, 1, 0),
+ MX6_PAD_SD2_DATA7__UART2_DCE_CTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA7__UART2_DTE_RTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0748, 3, 0),
+ MX6_PAD_SD2_DATA7__CSI_DATA09 = IOMUX_PAD(0x04E4, 0x021C, 3, 0x05EC, 1, 0),
+ MX6_PAD_SD2_DATA7__SD2_CD_B = IOMUX_PAD(0x04E4, 0x021C, 4, 0x0778, 1, 0),
+ MX6_PAD_SD2_DATA7__GPIO5_IO00 = IOMUX_PAD(0x04E4, 0x021C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x04E8, 0x0220, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__AUD5_RXFS = IOMUX_PAD(0x04E8, 0x0220, 1, 0x0588, 0, 0),
+ MX6_PAD_SD3_CLK__KEY_COL5 = IOMUX_PAD(0x04E8, 0x0220, 2, 0x0694, 0, 0),
+ MX6_PAD_SD3_CLK__CSI_DATA10 = IOMUX_PAD(0x04E8, 0x0220, 3, 0x05B0, 0, 0),
+ MX6_PAD_SD3_CLK__WDOG1_RESET_B_DEB = IOMUX_PAD(0x04E8, 0x0220, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__GPIO5_IO18 = IOMUX_PAD(0x04E8, 0x0220, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USB_OTG1_PWR = IOMUX_PAD(0x04E8, 0x0220, 6, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x04EC, 0x0224, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__AUD5_RXC = IOMUX_PAD(0x04EC, 0x0224, 1, 0x0584, 0, 0),
+ MX6_PAD_SD3_CMD__KEY_ROW5 = IOMUX_PAD(0x04EC, 0x0224, 2, 0x06B4, 0, 0),
+ MX6_PAD_SD3_CMD__CSI_DATA11 = IOMUX_PAD(0x04EC, 0x0224, 3, 0x05B4, 0, 0),
+ MX6_PAD_SD3_CMD__USB_OTG2_ID = IOMUX_PAD(0x04EC, 0x0224, 4, 0x0560, 1, 0),
+ MX6_PAD_SD3_CMD__GPIO5_IO21 = IOMUX_PAD(0x04EC, 0x0224, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USB_OTG2_PWR = IOMUX_PAD(0x04EC, 0x0224, 6, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x04F0, 0x0228, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA0__AUD5_RXD = IOMUX_PAD(0x04F0, 0x0228, 1, 0x057C, 0, 0),
+ MX6_PAD_SD3_DATA0__KEY_COL6 = IOMUX_PAD(0x04F0, 0x0228, 2, 0x0698, 0, 0),
+ MX6_PAD_SD3_DATA0__CSI_DATA12 = IOMUX_PAD(0x04F0, 0x0228, 3, 0x05B8, 0, 0),
+ MX6_PAD_SD3_DATA0__USB_OTG1_ID = IOMUX_PAD(0x04F0, 0x0228, 4, 0x055C, 1, 0),
+ MX6_PAD_SD3_DATA0__GPIO5_IO19 = IOMUX_PAD(0x04F0, 0x0228, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x04F4, 0x022C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA1__AUD5_TXC = IOMUX_PAD(0x04F4, 0x022C, 1, 0x058C, 0, 0),
+ MX6_PAD_SD3_DATA1__KEY_ROW6 = IOMUX_PAD(0x04F4, 0x022C, 2, 0x06B8, 0, 0),
+ MX6_PAD_SD3_DATA1__CSI_DATA13 = IOMUX_PAD(0x04F4, 0x022C, 3, 0x05BC, 0, 0),
+ MX6_PAD_SD3_DATA1__SD1_VSELECT = IOMUX_PAD(0x04F4, 0x022C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA1__GPIO5_IO20 = IOMUX_PAD(0x04F4, 0x022C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA1__JTAG_DE_B = IOMUX_PAD(0x04F4, 0x022C, 6, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x04F8, 0x0230, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA2__AUD5_TXFS = IOMUX_PAD(0x04F8, 0x0230, 1, 0x0590, 0, 0),
+ MX6_PAD_SD3_DATA2__KEY_COL7 = IOMUX_PAD(0x04F8, 0x0230, 2, 0x069C, 0, 0),
+ MX6_PAD_SD3_DATA2__CSI_DATA14 = IOMUX_PAD(0x04F8, 0x0230, 3, 0x05C0, 0, 0),
+ MX6_PAD_SD3_DATA2__EPIT1_OUT = IOMUX_PAD(0x04F8, 0x0230, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA2__GPIO5_IO16 = IOMUX_PAD(0x04F8, 0x0230, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA2__USB_OTG2_OC = IOMUX_PAD(0x04F8, 0x0230, 6, 0x0768, 0, 0),
+
+ MX6_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x04FC, 0x0234, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA3__AUD5_TXD = IOMUX_PAD(0x04FC, 0x0234, 1, 0x0580, 0, 0),
+ MX6_PAD_SD3_DATA3__KEY_ROW7 = IOMUX_PAD(0x04FC, 0x0234, 2, 0x06BC, 0, 0),
+ MX6_PAD_SD3_DATA3__CSI_DATA15 = IOMUX_PAD(0x04FC, 0x0234, 3, 0x05C4, 0, 0),
+ MX6_PAD_SD3_DATA3__EPIT2_OUT = IOMUX_PAD(0x04FC, 0x0234, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA3__GPIO5_IO17 = IOMUX_PAD(0x04FC, 0x0234, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA3__USB_OTG1_OC = IOMUX_PAD(0x04FC, 0x0234, 6, 0x076C, 0, 0),
+
+ MX6_PAD_GPIO4_IO20__SD1_STROBE = IOMUX_PAD(0x0500, 0x0238, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO20__AUD6_RXFS = IOMUX_PAD(0x0500, 0x0238, 2, 0x05A0, 0, 0),
+ MX6_PAD_GPIO4_IO20__ECSPI4_SS0 = IOMUX_PAD(0x0500, 0x0238, 3, 0x065C, 0, 0),
+ MX6_PAD_GPIO4_IO20__GPT_CAPTURE1 = IOMUX_PAD(0x0500, 0x0238, 4, 0x0670, 0, 0),
+ MX6_PAD_GPIO4_IO20__GPIO4_IO20 = IOMUX_PAD(0x0500, 0x0238, 5, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO4_IO21__SD2_STROBE = IOMUX_PAD(0x0504, 0x023C, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO21__AUD6_RXC = IOMUX_PAD(0x0504, 0x023C, 2, 0x059C, 0, 0),
+ MX6_PAD_GPIO4_IO21__ECSPI4_SCLK = IOMUX_PAD(0x0504, 0x023C, 3, 0x0650, 0, 0),
+ MX6_PAD_GPIO4_IO21__GPT_CAPTURE2 = IOMUX_PAD(0x0504, 0x023C, 4, 0x0674, 0, 0),
+ MX6_PAD_GPIO4_IO21__GPIO4_IO21 = IOMUX_PAD(0x0504, 0x023C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO4_IO19__SD3_STROBE = IOMUX_PAD(0x0508, 0x0240, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO19__AUD6_RXD = IOMUX_PAD(0x0508, 0x0240, 2, 0x0594, 0, 0),
+ MX6_PAD_GPIO4_IO19__ECSPI4_MOSI = IOMUX_PAD(0x0508, 0x0240, 3, 0x0658, 0, 0),
+ MX6_PAD_GPIO4_IO19__GPT_COMPARE1 = IOMUX_PAD(0x0508, 0x0240, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO19__GPIO4_IO19 = IOMUX_PAD(0x0508, 0x0240, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO25__AUD6_TXC = IOMUX_PAD(0x050C, 0x0244, 2, 0x05A4, 0, 0),
+ MX6_PAD_GPIO4_IO25__ECSPI4_MISO = IOMUX_PAD(0x050C, 0x0244, 3, 0x0654, 0, 0),
+ MX6_PAD_GPIO4_IO25__GPT_COMPARE2 = IOMUX_PAD(0x050C, 0x0244, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO25__GPIO4_IO25 = IOMUX_PAD(0x050C, 0x0244, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO18__AUD6_TXFS = IOMUX_PAD(0x0510, 0x0248, 2, 0x05A8, 0, 0),
+ MX6_PAD_GPIO4_IO18__ECSPI4_SS1 = IOMUX_PAD(0x0510, 0x0248, 3, 0x0660, 0, 0),
+ MX6_PAD_GPIO4_IO18__GPT_COMPARE3 = IOMUX_PAD(0x0510, 0x0248, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO18__GPIO4_IO18 = IOMUX_PAD(0x0510, 0x0248, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO24__AUD6_TXD = IOMUX_PAD(0x0514, 0x024C, 2, 0x0598, 0, 0),
+ MX6_PAD_GPIO4_IO24__ECSPI4_SS2 = IOMUX_PAD(0x0514, 0x024C, 3, 0x0664, 0, 0),
+ MX6_PAD_GPIO4_IO24__GPT_CLKIN = IOMUX_PAD(0x0514, 0x024C, 4, 0x0678, 0, 0),
+ MX6_PAD_GPIO4_IO24__GPIO4_IO24 = IOMUX_PAD(0x0514, 0x024C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO23__AUDIO_CLK_OUT = IOMUX_PAD(0x0518, 0x0250, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO23__SD1_RESET = IOMUX_PAD(0x0518, 0x0250, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO23__SD3_RESET = IOMUX_PAD(0x0518, 0x0250, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO23__GPIO4_IO23 = IOMUX_PAD(0x0518, 0x0250, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO17__USB_OTG1_ID = IOMUX_PAD(0x051C, 0x0254, 2, 0x055C, 2, 0),
+ MX6_PAD_GPIO4_IO17__SD1_VSELECT = IOMUX_PAD(0x051C, 0x0254, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO17__SD3_VSELECT = IOMUX_PAD(0x051C, 0x0254, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO17__GPIO4_IO17 = IOMUX_PAD(0x051C, 0x0254, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO22__SPDIF_IN = IOMUX_PAD(0x0520, 0x0258, 2, 0x0738, 0, 0),
+ MX6_PAD_GPIO4_IO22__SD1_WP = IOMUX_PAD(0x0520, 0x0258, 3, 0x0774, 0, 0),
+ MX6_PAD_GPIO4_IO22__SD3_WP = IOMUX_PAD(0x0520, 0x0258, 4, 0x0794, 1, 0),
+ MX6_PAD_GPIO4_IO22__GPIO4_IO22 = IOMUX_PAD(0x0520, 0x0258, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO16__SPDIF_OUT = IOMUX_PAD(0x0524, 0x025C, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO16__SD1_CD_B = IOMUX_PAD(0x0524, 0x025C, 3, 0x0770, 0, 0),
+ MX6_PAD_GPIO4_IO16__SD3_CD_B = IOMUX_PAD(0x0524, 0x025C, 4, 0x0780, 1, 0),
+ MX6_PAD_GPIO4_IO16__GPIO4_IO16 = IOMUX_PAD(0x0524, 0x025C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO26__WDOG1_B = IOMUX_PAD(0x0528, 0x0260, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO26__PWM4_OUT = IOMUX_PAD(0x0528, 0x0260, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO26__CCM_PMIC_READY = IOMUX_PAD(0x0528, 0x0260, 4, 0x05AC, 1, 0),
+ MX6_PAD_GPIO4_IO26__GPIO4_IO26 = IOMUX_PAD(0x0528, 0x0260, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO26__SPDIF_EXT_CLK = IOMUX_PAD(0x0528, 0x0260, 6, 0x073C, 0, 0),
+};
+#endif /* __ASM_ARCH_IMX6SLL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
new file mode 100644
index 0000000..682430e
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
@@ -0,0 +1,1065 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX6ULL_PINS_H__
+#define __ASM_ARCH_IMX6ULL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+ MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x0044, 0x0000, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x0048, 0x0004, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+
+ /*
+ * The TAMPER Pin can be used for GPIO, which depends on
+ * TAMPER_PIN_DISABLE[1:0] settings.
+ */
+ MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x004C, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x0050, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x0054, 0x0010, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x0058, 0x0014, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x005C, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x0060, 0x001C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x0064, 0x0020, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x0068, 0x0024, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x006C, 0x0028, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+ MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x0070, 0x002C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0),
+ MX6_PAD_JTAG_MOD__SPDIF_OUT = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__CCM_PMIC_RDY = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0),
+ MX6_PAD_JTAG_MOD__GPIO1_IO10 = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0),
+
+ MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__GPT2_CAPTURE1 = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0),
+ MX6_PAD_JTAG_TMS__SAI2_MCLK = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0),
+ MX6_PAD_JTAG_TMS__CCM_CLKO1 = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__CCM_WAIT = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__GPIO1_IO11 = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0),
+ MX6_PAD_JTAG_TMS__EPIT1_OUT = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__GPT2_CAPTURE2 = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0),
+ MX6_PAD_JTAG_TDO__SAI2_TX_SYNC = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0),
+ MX6_PAD_JTAG_TDO__CCM_CLKO2 = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__CCM_STOP = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__GPIO1_IO12 = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__MQS_RIGHT = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__EPIT2_OUT = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__GPT2_COMPARE1 = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__SAI2_TX_BCLK = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0),
+ MX6_PAD_JTAG_TDI__PWM6_OUT = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__GPIO1_IO13 = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__MQS_LEFT = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__GPT2_COMPARE2 = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0),
+ MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0),
+
+ MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3 = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0),
+ MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1 = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0),
+ MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0),
+ MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1 = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0),
+ MX6_PAD_GPIO1_IO00__MQS_RIGHT = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO01__I2C2_SDA = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0),
+ MX6_PAD_GPIO1_IO01__GPT1_COMPARE1 = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__USB_OTG1_OC = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0),
+ MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2 = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0),
+ MX6_PAD_GPIO1_IO01__MQS_LEFT = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO02__I2C1_SCL = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0),
+ MX6_PAD_GPIO1_IO02__GPT1_COMPARE2 = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__USB_OTG2_PWR = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__USDHC1_WP = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0),
+ MX6_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0),
+ MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__UART1_DCE_TX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO02__UART1_DTE_RX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0),
+
+ MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0),
+ MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0),
+ MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0),
+ MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO03__UART1_DCE_RX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0),
+ MX6_PAD_GPIO1_IO03__UART1_DTE_TX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0),
+ MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__UART5_DCE_TX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO04__UART5_DTE_RX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0),
+
+ MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2 = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0),
+ MX6_PAD_GPIO1_IO05__PWM4_OUT = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0),
+ MX6_PAD_GPIO1_IO05__CSI_FIELD = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0),
+ MX6_PAD_GPIO1_IO05__USDHC1_VSELECT = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO05__UART5_DCE_RX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0),
+ MX6_PAD_GPIO1_IO05__UART5_DTE_TX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO06__ENET1_MDIO = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0),
+ MX6_PAD_GPIO1_IO06__ENET2_MDIO = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0),
+ MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__CSI_MCLK = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__USDHC2_WP = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0),
+ MX6_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__CCM_REF_EN_B = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__UART1_DCE_CTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO06__UART1_DTE_RTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0),
+
+ MX6_PAD_GPIO1_IO07__ENET1_MDC = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__ENET2_MDC = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__CSI_PIXCLK = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0),
+ MX6_PAD_GPIO1_IO07__USDHC2_CD_B = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0),
+ MX6_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO07__UART1_DCE_RTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0),
+ MX6_PAD_GPIO1_IO07__UART1_DTE_CTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__SPDIF_OUT = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__CSI_VSYNC = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0),
+ MX6_PAD_GPIO1_IO08__USDHC2_VSELECT = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0),
+ MX6_PAD_GPIO1_IO08__UART5_DCE_RTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0),
+ MX6_PAD_GPIO1_IO08__UART5_DTE_CTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__SPDIF_IN = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0),
+ MX6_PAD_GPIO1_IO09__CSI_HSYNC = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0),
+ MX6_PAD_GPIO1_IO09__USDHC2_RESET_B = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__USDHC1_RESET_B = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__UART5_DCE_CTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0),
+ MX6_PAD_GPIO1_IO09__UART5_DTE_RTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0),
+
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0),
+ MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_TX_DATA__I2C3_SCL = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0),
+ MX6_PAD_UART1_TX_DATA__CSI_DATA02 = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0),
+ MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1 = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_TX_DATA__GPIO1_IO16 = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_TX_DATA__SPDIF_OUT = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0),
+
+ MX6_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0),
+ MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_RX_DATA__I2C3_SDA = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0),
+ MX6_PAD_UART1_RX_DATA__CSI_DATA03 = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0),
+ MX6_PAD_UART1_RX_DATA__GPT1_CLK = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0),
+ MX6_PAD_UART1_RX_DATA__GPIO1_IO17 = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_RX_DATA__SPDIF_IN = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0),
+
+ MX6_PAD_UART1_CTS_B__UART1_DCE_CTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_CTS_B__UART1_DTE_RTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0),
+ MX6_PAD_UART1_CTS_B__ENET1_RX_CLK = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_CTS_B__USDHC1_WP = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0),
+ MX6_PAD_UART1_CTS_B__CSI_DATA04 = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0),
+ MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_CTS_B__GPIO1_IO18 = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_CTS_B__USDHC2_WP = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0),
+
+ MX6_PAD_UART1_RTS_B__UART1_DCE_RTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0),
+
+ MX6_PAD_UART1_RTS_B__UART1_DTE_CTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0),
+ MX6_PAD_UART1_RTS_B__ENET1_TX_ER = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_RTS_B__USDHC1_CD_B = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0),
+ MX6_PAD_UART1_RTS_B__CSI_DATA05 = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0),
+ MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_RTS_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0),
+
+ MX6_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0),
+ MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0),
+ MX6_PAD_UART2_TX_DATA__I2C4_SCL = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0),
+ MX6_PAD_UART2_TX_DATA__CSI_DATA06 = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0),
+ MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1 = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0),
+ MX6_PAD_UART2_TX_DATA__GPIO1_IO20 = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0),
+ MX6_PAD_UART2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0),
+
+ MX6_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0),
+
+ MX6_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0),
+ MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0),
+ MX6_PAD_UART2_RX_DATA__I2C4_SDA = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0),
+ MX6_PAD_UART2_RX_DATA__CSI_DATA07 = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0),
+ MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2 = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0),
+ MX6_PAD_UART2_RX_DATA__GPIO1_IO21 = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0),
+ MX6_PAD_UART2_RX_DATA__SJC_DONE = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0),
+ MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0),
+
+ MX6_PAD_UART2_CTS_B__UART2_DCE_CTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART2_CTS_B__UART2_DTE_RTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0),
+ MX6_PAD_UART2_CTS_B__ENET1_CRS = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__FLEXCAN2_TX = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__CSI_DATA08 = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0),
+ MX6_PAD_UART2_CTS_B__GPT1_COMPARE2 = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__GPIO1_IO22 = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__SJC_DE_B = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0),
+ MX6_PAD_UART2_CTS_B__ECSPI3_MOSI = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0),
+
+ MX6_PAD_UART2_RTS_B__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0),
+
+ MX6_PAD_UART2_RTS_B__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__ENET1_COL = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__FLEXCAN2_RX = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0),
+ MX6_PAD_UART2_RTS_B__CSI_DATA09 = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0),
+ MX6_PAD_UART2_RTS_B__GPT1_COMPARE3 = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__GPIO1_IO23 = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__SJC_FAIL = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0),
+ MX6_PAD_UART2_RTS_B__ECSPI3_MISO = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0),
+
+ MX6_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0),
+ MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__CSI_DATA01 = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0),
+ MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0),
+ MX6_PAD_UART3_TX_DATA__GPIO1_IO24 = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0),
+ MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0),
+
+ MX6_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0),
+
+ MX6_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__CSI_DATA00 = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0),
+ MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0),
+ MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__GPIO1_IO25 = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0),
+ MX6_PAD_UART3_RX_DATA__EPIT1_OUT = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0),
+ MX6_PAD_UART3_CTS_B__ENET2_RX_CLK = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
+ MX6_PAD_UART3_CTS_B__FLEXCAN1_TX = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0),
+ MX6_PAD_UART3_CTS_B__CSI_DATA10 = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0),
+ MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0),
+ MX6_PAD_UART3_CTS_B__GPIO1_IO26 = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0),
+ MX6_PAD_UART3_CTS_B__EPIT2_OUT = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0),
+
+ MX6_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0),
+ MX6_PAD_UART3_RTS_B__ENET2_TX_ER = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0),
+ MX6_PAD_UART3_RTS_B__FLEXCAN1_RX = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0),
+ MX6_PAD_UART3_RTS_B__CSI_DATA11 = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0),
+ MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0),
+ MX6_PAD_UART3_RTS_B__GPIO1_IO27 = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0),
+ MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0),
+
+ MX6_PAD_UART4_TX_DATA__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART4_TX_DATA__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0),
+ MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0),
+ MX6_PAD_UART4_TX_DATA__I2C1_SCL = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0),
+ MX6_PAD_UART4_TX_DATA__CSI_DATA12 = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0),
+ MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0),
+ MX6_PAD_UART4_TX_DATA__GPIO1_IO28 = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0),
+ MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0),
+
+ MX6_PAD_UART4_RX_DATA__UART4_DCE_RX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0),
+
+ MX6_PAD_UART4_RX_DATA__UART4_DTE_TX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0),
+ MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0),
+ MX6_PAD_UART4_RX_DATA__I2C1_SDA = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0),
+ MX6_PAD_UART4_RX_DATA__CSI_DATA13 = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0),
+ MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0),
+ MX6_PAD_UART4_RX_DATA__GPIO1_IO29 = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0),
+ MX6_PAD_UART4_RX_DATA__ECSPI2_SS0 = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0),
+ MX6_PAD_UART5_TX_DATA__GPIO1_IO30 = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0),
+ MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0),
+
+ MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0),
+ MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0),
+ MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0),
+ MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0),
+ MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0),
+
+ MX6_PAD_UART5_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 5, 0),
+
+ MX6_PAD_UART5_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0),
+ MX6_PAD_UART5_RX_DATA__ENET2_COL = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0),
+ MX6_PAD_UART5_RX_DATA__I2C2_SDA = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0),
+ MX6_PAD_UART5_RX_DATA__CSI_DATA15 = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0),
+ MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0),
+ MX6_PAD_UART5_RX_DATA__GPIO1_IO31 = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0),
+ MX6_PAD_UART5_RX_DATA__ECSPI2_MISO = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0),
+
+ MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__PWM1_OUT = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__CSI_DATA16 = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__KPP_ROW00 = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0),
+ MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0),
+ MX6_PAD_ENET1_RX_DATA1__PWM2_OUT = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__CSI_DATA17 = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0),
+ MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__KPP_COL00 = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0),
+ MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0),
+ MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0),
+ MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_EN__KPP_ROW01 = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0),
+ MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0),
+ MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0),
+ MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__KPP_COL01 = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0),
+ MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0),
+ MX6_PAD_ENET1_TX_DATA1__PWM5_OUT = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__CSI_DATA20 = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0),
+ MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__KPP_ROW02 = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0),
+ MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_TX_EN__ENET1_TX_EN = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0),
+ MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__PWM6_OUT = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__CSI_DATA21 = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0),
+ MX6_PAD_ENET1_TX_EN__ENET2_MDC = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__GPIO2_IO05 = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_EN__KPP_COL02 = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0),
+ MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__PWM7_OUT = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__CSI_DATA22 = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0),
+ MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__KPP_ROW03 = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET1_TX_CLK__GPT1_CLK = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0),
+
+ MX6_PAD_ENET1_RX_ER__ENET1_RX_ER = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0),
+ MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__PWM8_OUT = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__CSI_DATA23 = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0),
+ MX6_PAD_ENET1_RX_ER__EIM_CRE = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__GPIO2_IO07 = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__KPP_COL03 = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2 = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0),
+
+ MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0),
+ MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__I2C3_SCL = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0),
+ MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0),
+ MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0),
+ MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__I2C3_SDA = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0),
+ MX6_PAD_ENET2_RX_DATA1__ENET1_MDC = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0),
+
+ MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__UART7_DTE_RX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0),
+ MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__I2C4_SCL = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0),
+ MX6_PAD_ENET2_RX_EN__EIM_ADDR26 = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0),
+ MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__I2C4_SDA = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0),
+ MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0),
+
+ MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03 = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0),
+ MX6_PAD_ENET2_TX_EN__UART8_DTE_TX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0),
+ MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0),
+
+ MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0),
+ MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0),
+
+ MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0),
+ MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__ECSPI4_SS0 = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0),
+ MX6_PAD_ENET2_RX_ER__EIM_ADDR25 = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__UART4_DCE_TX = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__UART4_DTE_RX = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0),
+ MX6_PAD_LCD_CLK__SAI3_MCLK = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0),
+ MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__UART4_DCE_RX = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0),
+ MX6_PAD_LCD_ENABLE__UART4_DTE_TX = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0),
+ MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0),
+ MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__UART4_DCE_CTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__UART4_DTE_RTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0),
+ MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0),
+ MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0),
+ MX6_PAD_LCD_VSYNC__UART4_DCE_RTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0),
+ MX6_PAD_LCD_VSYNC__UART4_DTE_CTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__SAI3_RX_DATA = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0),
+ MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__CA7_MX6ULL_EVENTI = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__SAI3_TX_DATA = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0),
+ MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0),
+
+ MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0),
+ MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0),
+
+ MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0),
+ MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0),
+
+ MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0),
+ MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0),
+
+ MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0),
+ MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0),
+ MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0),
+ MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0),
+ MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0),
+ MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0),
+ MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0),
+ MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__SRC_BT_CFG08 = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__FLEXCAN1_TX = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0),
+ MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0),
+ MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__SRC_BT_CFG09 = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__FLEXCAN1_RX = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0),
+
+ MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0),
+ MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__SRC_BT_CFG10 = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0),
+ MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__SRC_BT_CFG11 = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__FLEXCAN2_RX = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0),
+
+ MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0),
+ MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0),
+ MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__SRC_BT_CFG12 = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__ECSPI1_RDY = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0),
+ MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0),
+ MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__SRC_BT_CFG13 = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__USDHC2_RESET_B = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0),
+ MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0),
+ MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0),
+
+ MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0),
+ MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0),
+
+ MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0),
+ MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0),
+ MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0),
+
+ MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0),
+ MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0),
+ MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0),
+
+ MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__CA7_MX6ULL_EVENTO = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__CSI_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0),
+ MX6_PAD_LCD_DATA18__EIM_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__SRC_BT_CFG26 = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__USDHC2_CMD = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0),
+ MX6_PAD_LCD_DATA19__EIM_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__SRC_BT_CFG27 = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__USDHC2_CLK = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0),
+
+ MX6_PAD_LCD_DATA19__LCDIF_DATA19 = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__PWM6_OUT = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__CSI_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0),
+ MX6_PAD_LCD_DATA20__EIM_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__SRC_BT_CFG28 = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__USDHC2_DATA0 = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0),
+
+ MX6_PAD_LCD_DATA20__LCDIF_DATA20 = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__UART8_DCE_TX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__UART8_DTE_RX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0),
+ MX6_PAD_LCD_DATA20__ECSPI1_SCLK = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0),
+ MX6_PAD_LCD_DATA20__CSI_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0),
+
+ MX6_PAD_LCD_DATA21__LCDIF_DATA21 = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__UART8_DCE_RX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0),
+ MX6_PAD_LCD_DATA21__UART8_DTE_TX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__ECSPI1_SS0 = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0),
+ MX6_PAD_LCD_DATA21__CSI_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0),
+ MX6_PAD_LCD_DATA21__EIM_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0),
+
+ MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0),
+ MX6_PAD_LCD_DATA22__CSI_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0),
+ MX6_PAD_LCD_DATA22__EIM_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__SRC_BT_CFG30 = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__USDHC2_DATA2 = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0),
+
+ MX6_PAD_LCD_DATA23__LCDIF_DATA23 = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__MQS_LEFT = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0),
+ MX6_PAD_LCD_DATA23__CSI_DATA15 = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0),
+ MX6_PAD_LCD_DATA23__EIM_DATA15 = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__SRC_BT_CFG31 = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__USDHC2_DATA3 = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0),
+
+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_RE_B__USDHC2_CLK = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0),
+ MX6_PAD_NAND_RE_B__QSPI_B_SCLK = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_RE_B__KPP_ROW00 = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0),
+ MX6_PAD_NAND_RE_B__EIM_EB_B00 = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_RE_B__GPIO4_IO00 = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_RE_B__ECSPI3_SS2 = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0),
+ MX6_PAD_NAND_WE_B__QSPI_B_SS0_B = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_WE_B__KPP_COL00 = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0),
+ MX6_PAD_NAND_WE_B__EIM_EB_B01 = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_WE_B__GPIO4_IO01 = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_WE_B__ECSPI3_SS3 = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0),
+ MX6_PAD_NAND_DATA00__QSPI_B_SS1_B = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA00__KPP_ROW01 = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0),
+ MX6_PAD_NAND_DATA00__EIM_AD08 = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA00__GPIO4_IO02 = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA00__ECSPI4_RDY = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0),
+ MX6_PAD_NAND_DATA01__QSPI_B_DQS = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA01__KPP_COL01 = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0),
+ MX6_PAD_NAND_DATA01__EIM_AD09 = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA01__GPIO4_IO03 = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA01__ECSPI4_SS1 = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0),
+ MX6_PAD_NAND_DATA02__QSPI_B_DATA00 = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA02__KPP_ROW02 = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0),
+ MX6_PAD_NAND_DATA02__EIM_AD10 = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA02__GPIO4_IO04 = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA02__ECSPI4_SS2 = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0),
+ MX6_PAD_NAND_DATA03__QSPI_B_DATA01 = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA03__KPP_COL02 = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0),
+ MX6_PAD_NAND_DATA03__EIM_AD11 = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA03__GPIO4_IO05 = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA03__ECSPI4_SS3 = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0),
+ MX6_PAD_NAND_DATA04__QSPI_B_DATA02 = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__ECSPI4_SCLK = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0),
+ MX6_PAD_NAND_DATA04__EIM_AD12 = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__GPIO4_IO06 = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__UART2_DCE_TX = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA04__UART2_DTE_RX = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0),
+
+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0),
+ MX6_PAD_NAND_DATA05__QSPI_B_DATA03 = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA05__ECSPI4_MOSI = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0),
+ MX6_PAD_NAND_DATA05__EIM_AD13 = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA05__GPIO4_IO07 = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA05__UART2_DCE_RX = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0),
+ MX6_PAD_NAND_DATA05__UART2_DTE_TX = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0),
+ MX6_PAD_NAND_DATA06__SAI2_RX_BCLK = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__ECSPI4_MISO = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0),
+ MX6_PAD_NAND_DATA06__EIM_AD14 = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__GPIO4_IO08 = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__UART2_DCE_CTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA06__UART2_DTE_RTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0),
+
+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0),
+ MX6_PAD_NAND_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA07__ECSPI4_SS0 = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0),
+ MX6_PAD_NAND_DATA07__EIM_AD15 = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA07__GPIO4_IO09 = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DATA07__UART2_DCE_RTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0),
+ MX6_PAD_NAND_DATA07__UART2_DTE_CTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__USDHC2_RESET_B = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__QSPI_A_DQS = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__PWM3_OUT = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__EIM_ADDR17 = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__GPIO4_IO10 = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_ALE__ECSPI3_SS1 = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__QSPI_A_SCLK = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__PWM4_OUT = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__EIM_BCLK = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__GPIO4_IO11 = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_WP_B__ECSPI3_RDY = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__USDHC1_DATA4 = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__QSPI_A_DATA00 = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__ECSPI3_SS0 = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0),
+ MX6_PAD_NAND_READY_B__EIM_CS1_B = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__GPIO4_IO12 = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__UART3_DCE_TX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0),
+ MX6_PAD_NAND_READY_B__UART3_DTE_RX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0),
+
+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__USDHC1_DATA5 = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__ECSPI3_SCLK = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0),
+ MX6_PAD_NAND_CE0_B__EIM_DTACK_B = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__GPIO4_IO13 = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE0_B__UART3_DCE_RX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0),
+ MX6_PAD_NAND_CE0_B__UART3_DTE_TX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__USDHC1_DATA6 = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__ECSPI3_MOSI = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0),
+ MX6_PAD_NAND_CE1_B__EIM_ADDR18 = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__GPIO4_IO14 = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__UART3_DCE_CTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0),
+ MX6_PAD_NAND_CE1_B__UART3_DTE_RTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0),
+
+ MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__USDHC1_DATA7 = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__QSPI_A_DATA03 = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__ECSPI3_MISO = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0),
+ MX6_PAD_NAND_CLE__EIM_ADDR16 = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__GPIO4_IO15 = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_CLE__UART3_DCE_RTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0),
+ MX6_PAD_NAND_CLE__UART3_DTE_CTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0),
+
+ MX6_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__CSI_FIELD = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0),
+ MX6_PAD_NAND_DQS__QSPI_A_SS0_B = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__PWM5_OUT = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__EIM_WAIT = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__GPIO4_IO16 = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0),
+ MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0),
+ MX6_PAD_NAND_DQS__SPDIF_EXT_CLK = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0),
+
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPT2_COMPARE1 = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__SAI2_RX_SYNC = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__SPDIF_OUT = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__EIM_ADDR19 = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPIO2_IO16 = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0),
+ MX6_PAD_SD1_CMD__USB_OTG1_PWR = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPT2_COMPARE2 = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__SAI2_MCLK = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0),
+ MX6_PAD_SD1_CLK__SPDIF_IN = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0),
+ MX6_PAD_SD1_CLK__EIM_ADDR20 = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPIO2_IO17 = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USB_OTG1_OC = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0),
+
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__GPT2_COMPARE3 = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__SAI2_TX_SYNC = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0),
+ MX6_PAD_SD1_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__EIM_ADDR21 = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__GPIO2_IO18 = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0),
+
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__GPT2_CLK = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0),
+ MX6_PAD_SD1_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0),
+ MX6_PAD_SD1_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0),
+ MX6_PAD_SD1_DATA1__EIM_ADDR22 = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__GPIO2_IO19 = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__GPT2_CAPTURE1 = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0),
+ MX6_PAD_SD1_DATA2__SAI2_RX_DATA = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0),
+ MX6_PAD_SD1_DATA2__FLEXCAN2_TX = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__EIM_ADDR23 = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__GPIO2_IO20 = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__USB_OTG2_OC = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0),
+
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__GPT2_CAPTURE2 = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0),
+ MX6_PAD_SD1_DATA3__SAI2_TX_DATA = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__FLEXCAN2_RX = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0),
+ MX6_PAD_SD1_DATA3__EIM_ADDR24 = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__GPIO2_IO21 = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0),
+
+ MX6_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__USDHC2_CD_B = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0),
+ MX6_PAD_CSI_MCLK__RAWNAND_CE2_B = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__I2C1_SDA = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0),
+ MX6_PAD_CSI_MCLK__EIM_CS0_B = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__GPIO4_IO17 = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__UART6_DCE_TX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0),
+ MX6_PAD_CSI_MCLK__UART6_DTE_RX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0),
+
+ MX6_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0),
+ MX6_PAD_CSI_PIXCLK__USDHC2_WP = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0),
+ MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_PIXCLK__I2C1_SCL = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0),
+ MX6_PAD_CSI_PIXCLK__EIM_OE = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_PIXCLK__GPIO4_IO18 = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_PIXCLK__UART6_DCE_RX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0),
+ MX6_PAD_CSI_PIXCLK__UART6_DTE_TX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0),
+ MX6_PAD_CSI_VSYNC__USDHC2_CLK = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0),
+ MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_VSYNC__I2C2_SDA = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0),
+ MX6_PAD_CSI_VSYNC__EIM_RW = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_VSYNC__GPIO4_IO19 = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_VSYNC__PWM7_OUT = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_VSYNC__UART6_DCE_RTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0),
+ MX6_PAD_CSI_VSYNC__UART6_DTE_CTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0),
+ MX6_PAD_CSI_HSYNC__USDHC2_CMD = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0),
+ MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__I2C2_SCL = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0),
+ MX6_PAD_CSI_HSYNC__EIM_LBA_B = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__GPIO4_IO20 = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__PWM8_OUT = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__UART6_DCE_CTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0),
+ MX6_PAD_CSI_HSYNC__UART6_DTE_RTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0),
+
+ MX6_PAD_CSI_DATA00__CSI_DATA02 = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0),
+ MX6_PAD_CSI_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0),
+ MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0),
+ MX6_PAD_CSI_DATA00__EIM_AD00 = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__GPIO4_IO21 = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__SRC_INT_BOOT = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__UART5_DCE_TX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA00__UART5_DTE_RX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0),
+
+ MX6_PAD_CSI_DATA01__CSI_DATA03 = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0),
+ MX6_PAD_CSI_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0),
+ MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA01__ECSPI2_SS0 = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0),
+ MX6_PAD_CSI_DATA01__EIM_AD01 = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA01__GPIO4_IO22 = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA01__SAI1_MCLK = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0),
+ MX6_PAD_CSI_DATA01__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0),
+ MX6_PAD_CSI_DATA01__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_DATA02__CSI_DATA04 = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0),
+ MX6_PAD_CSI_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0),
+ MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA02__ECSPI2_MOSI = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0),
+ MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0),
+ MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0),
+ MX6_PAD_CSI_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0),
+ MX6_PAD_CSI_DATA03__SIM2_PORT1_PD = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__ECSPI2_MISO = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0),
+ MX6_PAD_CSI_DATA03__EIM_AD03 = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__GPIO4_IO24 = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__SAI1_RX_BCLK = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__UART5_DCE_CTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA03__UART5_DTE_RTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0),
+
+ MX6_PAD_CSI_DATA04__CSI_DATA06 = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0),
+ MX6_PAD_CSI_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0),
+ MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA04__ECSPI1_SCLK = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0),
+ MX6_PAD_CSI_DATA04__EIM_AD04 = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA04__GPIO4_IO25 = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA04__SAI1_TX_SYNC = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0),
+ MX6_PAD_CSI_DATA04__USDHC1_WP = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0),
+
+ MX6_PAD_CSI_DATA05__CSI_DATA07 = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0),
+ MX6_PAD_CSI_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0),
+ MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA05__ECSPI1_SS0 = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0),
+ MX6_PAD_CSI_DATA05__EIM_AD05 = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA05__GPIO4_IO26 = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA05__SAI1_TX_BCLK = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0),
+ MX6_PAD_CSI_DATA05__USDHC1_CD_B = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0),
+
+ MX6_PAD_CSI_DATA06__CSI_DATA08 = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0),
+ MX6_PAD_CSI_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0),
+ MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA06__ECSPI1_MOSI = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0),
+ MX6_PAD_CSI_DATA06__EIM_AD06 = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA06__GPIO4_IO27 = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA06__SAI1_RX_DATA = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0),
+ MX6_PAD_CSI_DATA06__USDHC1_RESET_B = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0),
+
+ MX6_PAD_CSI_DATA07__CSI_DATA09 = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0),
+ MX6_PAD_CSI_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0),
+ MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA07__ECSPI1_MISO = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0),
+ MX6_PAD_CSI_DATA07__EIM_AD07 = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA07__GPIO4_IO28 = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA07__SAI1_TX_DATA = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI_DATA07__USDHC1_VSELECT = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_IMX6ULL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx7/mx7_plugin.S b/arch/arm/include/asm/arch-mx7/mx7_plugin.S
new file mode 100644
index 0000000..41336b4
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/mx7_plugin.S
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
+#define ROM_VERSION_OFFSET 0x80
+#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
+
+plugin_start:
+
+ push {r0-r4, lr}
+
+ imx7_ddr_setting
+ imx7_clock_gating
+ imx7_qos_setting
+
+/*
+ * Check if we are in USB serial download mode and immediately return to ROM
+ * Need to check USB CTRL clock firstly, then check the USBx_nASYNCLISTADDR
+ */
+ ldr r0, =0x30384680
+ ldr r1, [r0]
+ cmp r1, #0
+ beq normal_boot
+
+ ldr r0, =0x30B10158
+ ldr r1, [r0]
+ cmp r1, #0
+ beq normal_boot
+
+ pop {r0-r4, lr}
+ bx lr
+
+normal_boot:
+
+/*
+ * The following is to fill in those arguments for this ROM function
+ * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+ * This function is used to copy data from the storage media into DDR.
+ * start - Initial (possibly partial) image load address on entry.
+ * Final image load address on exit.
+ * bytes - Initial (possibly partial) image size on entry.
+ * Final image size on exit.
+ * boot_data - Initial @ref ivt Boot Data load address.
+ */
+ adr r0, boot_data2
+ adr r1, image_len2
+ adr r2, boot_data2
+
+/*
+ * check the _pu_irom_api_table for the address
+ */
+before_calling_rom___pu_irom_hwcnfg_setup:
+ ldr r3, =ROM_VERSION_OFFSET
+ ldr r4, [r3]
+ ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
+ ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
+ blx r4
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+ pop {r0-r4, lr}
+ push {r5}
+ ldr r5, boot_data2
+ str r5, [r0]
+ ldr r5, image_len2
+ str r5, [r1]
+ ldr r5, second_ivt_offset
+ str r5, [r2]
+ mov r0, #1
+ pop {r5}
+
+ /* return back to ROM code */
+ bx lr
+
+/* make the following data right in the end of the output*/
+.ltorg
+
+#define FLASH_OFFSET 0x400
+
+/*
+ * second_ivt_offset is the offset from the "second_ivt_header" to
+ * "image_copy_start", which involves FLASH_OFFSET, plus the first
+ * ivt_header, the plugin code size itself recorded by "ivt2_header"
+ */
+
+second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET)
+
+/*
+ * The following is the second IVT header plus the second boot data
+ */
+ivt2_header: .long 0x0
+app2_code_jump_v: .long 0x0
+reserv3: .long 0x0
+dcd2_ptr: .long 0x0
+boot_data2_ptr: .long 0x0
+self_ptr2: .long 0x0
+app_code_csf2: .long 0x0
+reserv4: .long 0x0
+boot_data2: .long 0x0
+image_len2: .long 0x0
+plugin2: .long 0x0
diff --git a/arch/arm/include/asm/arch-omap3/musb.h b/arch/arm/include/asm/arch-omap3/musb.h
index cee4ed3..d06a758 100644
--- a/arch/arm/include/asm/arch-omap3/musb.h
+++ b/arch/arm/include/asm/arch-omap3/musb.h
@@ -7,7 +7,7 @@
#ifndef __ASM_ARCH_OMAP3_MUSB_H
#define __ASM_ARCH_OMAP3_MUSB_H
-extern void am35x_musb_reset(void);
-extern void am35x_musb_phy_power(u8 on);
-extern void am35x_musb_clear_irq(void);
+void am35x_musb_reset(struct udevice *dev);
+void am35x_musb_phy_power(struct udevice *dev, u8 on);
+void am35x_musb_clear_irq(struct udevice *dev);
#endif
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 551c927..7ea7199 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -286,23 +286,47 @@
/* STD_FUSE_OPP_VMIN_MPU_4 */
#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
-/* Common voltage and Efuse register macros */
-/* DRA74x/DRA75x/DRA72x */
-#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM
-#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM
-#define VDD_EVE_DRA7 VDD_EVE_DRA7_NOM
-#define VDD_GPU_DRA7 VDD_GPU_DRA7_NOM
-#define VDD_IVA_DRA7 VDD_IVA_DRA7_NOM
+#if defined(CONFIG_DRA7_MPU_OPP_HIGH)
+#define DRA7_MPU_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_MPU_OPP_OD)
+#define DRA7_MPU_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_MPU_OPP OPP_NOM
+#endif
-#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM
-#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM
-#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM
-#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_NOM
-#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_NOM
+/* OPP_NOM only available option for CORE */
+#define DRA7_CORE_OPP OPP_NOM
+
+#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
+#define DRA7_DSPEVE_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
+#define DRA7_DSPEVE_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_DSPEVE_OPP OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_IVA_OPP_HIGH)
+#define DRA7_IVA_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_IVA_OPP_OD)
+#define DRA7_IVA_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_IVA_OPP OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_GPU_OPP_HIGH)
+#define DRA7_GPU_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_GPU_OPP_OD)
+#define DRA7_GPU_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_GPU_OPP OPP_NOM
+#endif
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
+/* Offset is 0.73V for LP873x */
+#define LP873X_BUCK_BASE_VOLT_UV 730000
+
/* TPS659038 */
#define TPS659038_I2C_SLAVE_ADDR 0x58
#define TPS659038_REG_ADDR_SMPS12 0x23
@@ -317,6 +341,11 @@
#define TPS65917_REG_ADDR_SMPS2 0x27
#define TPS65917_REG_ADDR_SMPS3 0x2F
+/* LP873X */
+#define LP873X_I2C_SLAVE_ADDR 0x60
+#define LP873X_REG_ADDR_BUCK0 0x6
+#define LP873X_REG_ADDR_BUCK1 0x7
+#define LP873X_REG_ADDR_LDO1 0xA
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
@@ -348,7 +377,7 @@
*/
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define V_OSCK 20000000 /* Clock output from T2 */
#else
#define V_OSCK 19200000 /* Clock output from T2 */
diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h
index a5bd600..d24d645 100644
--- a/arch/arm/include/asm/arch-omap5/hardware.h
+++ b/arch/arm/include/asm/arch-omap5/hardware.h
@@ -24,7 +24,7 @@
#define GPMC_BASE 0x50000000
/* EDMA3 Base address for DRA7XX and AM57XX */
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define EDMA3_BASE 0x43300000
#endif
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
index 2115abb..5eed98c 100644
--- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
+++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
@@ -362,7 +362,7 @@
#define EMU3 0x454
#define EMU4 0x458
#define RESETN 0x45C
-#define NMIN 0x460
+#define NMIN_DSP 0x460
#define RSTOUTN 0x464
#endif /* _MUX_DRA7XX_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index ef8e975..b5e5519f 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -29,13 +29,13 @@
#define CONTROL_CORE_ID_CODE 0x4A002204
#define CONTROL_WKUP_ID_CODE 0x4AE0C204
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
#else
#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
#endif
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define DRA7_USB_OTG_SS1_BASE 0x48890000
#define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000
#define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00
@@ -185,7 +185,7 @@
* much larger) and do not, at this time, make use of the additional
* space.
*/
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
#define NON_SECURE_SRAM_IMG_END 0x4037E000
diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
index 468ff5a..3582880 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -20,7 +20,7 @@
#define BOOT_DEVICE_QSPI_1 0x0A
#define BOOT_DEVICE_QSPI_4 0x0B
#define BOOT_DEVICE_UART 0x43
-#define BOOT_DEVICE_USB 0x45
+#define BOOT_DEVICE_DFU 0x45
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/arch-rockchip/boot_mode.h b/arch/arm/include/asm/arch-rockchip/boot_mode.h
new file mode 100644
index 0000000..bd65f60
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/boot_mode.h
@@ -0,0 +1,19 @@
+#ifndef __REBOOT_MODE_H
+#define __REBOOT_MODE_H
+
+/* high 24 bits is tag, low 8 bits is type */
+#define REBOOT_FLAG 0x5242C300
+/* normal boot */
+#define BOOT_NORMAL (REBOOT_FLAG + 0)
+/* enter loader rockusb mode */
+#define BOOT_LOADER (REBOOT_FLAG + 1)
+/* enter recovery */
+#define BOOT_RECOVERY (REBOOT_FLAG + 3)
+/* enter fastboot mode */
+#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
+/* enter charging mode */
+#define BOOT_CHARGING (REBOOT_FLAG + 11)
+/* enter usb mass storage mode */
+#define BOOT_UMS (REBOOT_FLAG + 12)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 21edbc2..804c77b 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -16,6 +16,7 @@
ROCKCHIP_SYSCON_GRF,
ROCKCHIP_SYSCON_SGRF,
ROCKCHIP_SYSCON_PMU,
+ ROCKCHIP_SYSCON_PMUGRF,
};
/* Standard Rockchip clock numbers */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
index 7ecc8ee..aaef4b9 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
@@ -24,6 +24,12 @@
#define PERI_HCLK_HZ 148500000
#define PERI_PCLK_HZ 74250000
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3036_clk_priv {
+ struct rk3036_cru *cru;
+ ulong rate;
+};
+
struct rk3036_cru {
struct rk3036_pll {
unsigned int con0;
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index 8a8ca9c..d575f4a 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -25,6 +25,13 @@
#define PERI_HCLK_HZ 148500000
#define PERI_PCLK_HZ 74250000
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3288_clk_priv {
+ struct rk3288_grf *grf;
+ struct rk3288_cru *cru;
+ ulong rate;
+};
+
struct rk3288_cru {
struct rk3288_pll {
u32 con0;
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index c919f47..98fba2b 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -9,6 +9,12 @@
#include <common.h>
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3399_clk_priv {
+ struct rk3399_cru *cru;
+ ulong rate;
+};
+
struct rk3399_pmucru {
u32 ppll_con[6];
u32 reserved[0x1a];
@@ -64,9 +70,9 @@
#define APLL_HZ (600*MHz)
#define GPLL_HZ (594*MHz)
#define CPLL_HZ (384*MHz)
-#define PPLL_HZ (594*MHz)
+#define PPLL_HZ (676*MHz)
-#define PMU_PCLK_HZ (99*MHz)
+#define PMU_PCLK_HZ (48*MHz)
#define ACLKM_CORE_HZ (300*MHz)
#define ATCLK_CORE_HZ (300*MHz)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
new file mode 100644
index 0000000..d3d1467
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -0,0 +1,321 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
+#define __SOC_ROCKCHIP_RK3399_GRF_H__
+
+struct rk3399_grf_regs {
+ u32 reserved[0x800];
+ u32 usb3_perf_con0;
+ u32 usb3_perf_con1;
+ u32 usb3_perf_con2;
+ u32 usb3_perf_rd_max_latency_num;
+ u32 usb3_perf_rd_latency_samp_num;
+ u32 usb3_perf_rd_latency_acc_num;
+ u32 usb3_perf_rd_axi_total_byte;
+ u32 usb3_perf_wr_axi_total_byte;
+ u32 usb3_perf_working_cnt;
+ u32 reserved1[0x103];
+ u32 usb3otg0_con0;
+ u32 usb3otg0_con1;
+ u32 reserved2[2];
+ u32 usb3otg1_con0;
+ u32 usb3otg1_con1;
+ u32 reserved3[2];
+ u32 usb3otg0_status_lat0;
+ u32 usb3otg0_status_lat1;
+ u32 usb3otg0_status_cb;
+ u32 reserved4;
+ u32 usb3otg1_status_lat0;
+ u32 usb3otg1_status_lat1;
+ u32 usb3ogt1_status_cb;
+ u32 reserved5[0x6e5];
+ u32 pcie_perf_con0;
+ u32 pcie_perf_con1;
+ u32 pcie_perf_con2;
+ u32 pcie_perf_rd_max_latency_num;
+ u32 pcie_perf_rd_latency_samp_num;
+ u32 pcie_perf_rd_laterncy_acc_num;
+ u32 pcie_perf_rd_axi_total_byte;
+ u32 pcie_perf_wr_axi_total_byte;
+ u32 pcie_perf_working_cnt;
+ u32 reserved6[0x37];
+ u32 usb20_host0_con0;
+ u32 usb20_host0_con1;
+ u32 reserved7[2];
+ u32 usb20_host1_con0;
+ u32 usb20_host1_con1;
+ u32 reserved8[2];
+ u32 hsic_con0;
+ u32 hsic_con1;
+ u32 reserved9[6];
+ u32 grf_usbhost0_status;
+ u32 grf_usbhost1_Status;
+ u32 grf_hsic_status;
+ u32 reserved10[0xc9];
+ u32 hsicphy_con0;
+ u32 reserved11[3];
+ u32 usbphy0_ctrl[26];
+ u32 reserved12[6];
+ u32 usbphy1[26];
+ u32 reserved13[0x72f];
+ u32 soc_con9;
+ u32 reserved14[0x0a];
+ u32 soc_con20;
+ u32 soc_con21;
+ u32 soc_con22;
+ u32 soc_con23;
+ u32 soc_con24;
+ u32 soc_con25;
+ u32 soc_con26;
+ u32 reserved15[0xf65];
+ u32 cpu_con[4];
+ u32 reserved16[0x1c];
+ u32 cpu_status[6];
+ u32 reserved17[0x1a];
+ u32 a53_perf_con[4];
+ u32 a53_perf_rd_mon_st;
+ u32 a53_perf_rd_mon_end;
+ u32 a53_perf_wr_mon_st;
+ u32 a53_perf_wr_mon_end;
+ u32 a53_perf_rd_max_latency_num;
+ u32 a53_perf_rd_latency_samp_num;
+ u32 a53_perf_rd_laterncy_acc_num;
+ u32 a53_perf_rd_axi_total_byte;
+ u32 a53_perf_wr_axi_total_byte;
+ u32 a53_perf_working_cnt;
+ u32 a53_perf_int_status;
+ u32 reserved18[0x31];
+ u32 a72_perf_con[4];
+ u32 a72_perf_rd_mon_st;
+ u32 a72_perf_rd_mon_end;
+ u32 a72_perf_wr_mon_st;
+ u32 a72_perf_wr_mon_end;
+ u32 a72_perf_rd_max_latency_num;
+ u32 a72_perf_rd_latency_samp_num;
+ u32 a72_perf_rd_laterncy_acc_num;
+ u32 a72_perf_rd_axi_total_byte;
+ u32 a72_perf_wr_axi_total_byte;
+ u32 a72_perf_working_cnt;
+ u32 a72_perf_int_status;
+ u32 reserved19[0x7f6];
+ u32 soc_con5;
+ u32 soc_con6;
+ u32 reserved20[0x779];
+ u32 gpio2a_iomux;
+ union {
+ u32 iomux_spi2;
+ u32 gpio2b_iomux;
+ };
+ union {
+ u32 gpio2c_iomux;
+ u32 iomux_spi5;
+ };
+ u32 gpio2d_iomux;
+ union {
+ u32 gpio3a_iomux;
+ u32 iomux_spi0;
+ };
+ u32 gpio3b_iomux;
+ u32 gpio3c_iomux;
+ union {
+ u32 iomux_i2s0;
+ u32 gpio3d_iomux;
+ };
+ union {
+ u32 iomux_i2sclk;
+ u32 gpio4a_iomux;
+ };
+ union {
+ u32 iomux_sdmmc;
+ u32 iomux_uart2a;
+ u32 gpio4b_iomux;
+ };
+ union {
+ u32 iomux_pwm_0;
+ u32 iomux_pwm_1;
+ u32 iomux_uart2b;
+ u32 iomux_uart2c;
+ u32 iomux_edp_hotplug;
+ u32 gpio4c_iomux;
+ };
+ u32 gpio4d_iomux;
+ u32 reserved21[4];
+ u32 gpio2_p[3][4];
+ u32 reserved22[4];
+ u32 gpio2_sr[3][4];
+ u32 reserved23[4];
+ u32 gpio2_smt[3][4];
+ u32 reserved24[(0xe130 - 0xe0ec)/4 - 1];
+ u32 gpio4b_e01;
+ u32 gpio4b_e2;
+ u32 reserved24a[(0xe200 - 0xe134)/4 - 1];
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5_pcie;
+ u32 reserved25;
+ u32 soc_con7;
+ u32 soc_con8;
+ u32 soc_con9_pcie;
+ u32 reserved26[0x1e];
+ u32 soc_status[6];
+ u32 reserved27[0x32];
+ u32 ddrc0_con0;
+ u32 ddrc0_con1;
+ u32 ddrc1_con0;
+ u32 ddrc1_con1;
+ u32 reserved28[0xac];
+ u32 io_vsel;
+ u32 saradc_testbit;
+ u32 tsadc_testbit_l;
+ u32 tsadc_testbit_h;
+ u32 reserved29[0x6c];
+ u32 chip_id_addr;
+ u32 reserved30[0x1f];
+ u32 fast_boot_addr;
+ u32 reserved31[0x1df];
+ u32 emmccore_con[12];
+ u32 reserved32[4];
+ u32 emmccore_status[4];
+ u32 reserved33[0x1cc];
+ u32 emmcphy_con[7];
+ u32 reserved34;
+ u32 emmcphy_status;
+};
+check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
+
+struct rk3399_pmugrf_regs {
+ union {
+ u32 iomux_pwm_3a;
+ u32 gpio0a_iomux;
+ };
+ u32 gpio0b_iomux;
+ u32 reserved0[2];
+ union {
+ u32 spi1_rxd;
+ u32 tsadc_int;
+ u32 gpio1a_iomux;
+ };
+ union {
+ u32 spi1_csclktx;
+ u32 iomux_pwm_3b;
+ u32 iomux_i2c0_sda;
+ u32 gpio1b_iomux;
+ };
+ union {
+ u32 iomux_pwm_2;
+ u32 iomux_i2c0_scl;
+ u32 gpio1c_iomux;
+ };
+ u32 gpio1d_iomux;
+ u32 reserved1[8];
+ u32 gpio0_p[2][4];
+ u32 reserved3[8];
+ u32 gpio0a_e;
+ u32 reserved4;
+ u32 gpio0b_e;
+ u32 reserved5[5];
+ u32 gpio1a_e;
+ u32 reserved6;
+ u32 gpio1b_e;
+ u32 reserved7;
+ u32 gpio1c_e;
+ u32 reserved8;
+ u32 gpio1d_e;
+ u32 reserved9[0x11];
+ u32 gpio0l_sr;
+ u32 reserved10;
+ u32 gpio1l_sr;
+ u32 gpio1h_sr;
+ u32 reserved11[4];
+ u32 gpio0a_smt;
+ u32 gpio0b_smt;
+ u32 reserved12[2];
+ u32 gpio1a_smt;
+ u32 gpio1b_smt;
+ u32 gpio1c_smt;
+ u32 gpio1d_smt;
+ u32 reserved13[8];
+ u32 gpio0l_he;
+ u32 reserved14;
+ u32 gpio1l_he;
+ u32 gpio1h_he;
+ u32 reserved15[4];
+ u32 soc_con0;
+ u32 reserved16[9];
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 reserved17[0x24];
+ u32 pmupvtm_con0;
+ u32 pmupvtm_con1;
+ u32 pmupvtm_status0;
+ u32 pmupvtm_status1;
+ u32 grf_osc_e;
+ u32 reserved18[0x2b];
+ u32 os_reg0;
+ u32 os_reg1;
+ u32 os_reg2;
+ u32 os_reg3;
+};
+check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
+
+struct rk3399_pmusgrf_regs {
+ u32 ddr_rgn_con[35];
+ u32 reserved[0x1fe5];
+ u32 soc_con8;
+ u32 soc_con9;
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 soc_con12;
+ u32 soc_con13;
+ u32 soc_con14;
+ u32 soc_con15;
+ u32 reserved1[3];
+ u32 soc_con19;
+ u32 soc_con20;
+ u32 soc_con21;
+ u32 soc_con22;
+ u32 reserved2[0x29];
+ u32 perilp_con[9];
+ u32 reserved4[7];
+ u32 perilp_status;
+ u32 reserved5[0xfaf];
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 reserved6[0x3e];
+ u32 pmu_con[9];
+ u32 reserved7[0x17];
+ u32 fast_boot_addr;
+ u32 reserved8[0x1f];
+ u32 efuse_prg_mask;
+ u32 efuse_read_mask;
+ u32 reserved9[0x0e];
+ u32 pmu_slv_con0;
+ u32 pmu_slv_con1;
+ u32 reserved10[0x771];
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5;
+ u32 soc_con6;
+ u32 soc_con7;
+ u32 reserved11[8];
+ u32 soc_con16;
+ u32 soc_con17;
+ u32 soc_con18;
+ u32 reserved12[0xdd];
+ u32 slv_secure_con0;
+ u32 slv_secure_con1;
+ u32 reserved13;
+ u32 slv_secure_con2;
+ u32 slv_secure_con3;
+ u32 slv_secure_con4;
+};
+check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
+
+#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h
index 08ff945..5d9a178 100644
--- a/arch/arm/include/asm/arch-rockchip/pwm.h
+++ b/arch/arm/include/asm/arch-rockchip/pwm.h
@@ -10,8 +10,8 @@
struct rk3288_pwm {
u32 cnt;
- u32 period_hpr;
u32 duty_lpr;
+ u32 period_hpr;
u32 ctrl;
};
check_member(rk3288_pwm, ctrl, 0xc);
diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
index e08e28f..d7d67ba 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -16,6 +16,11 @@
};
struct rk3288_sdram_channel {
+ /*
+ * bit width in address, eg:
+ * 8 banks using 3 bit to address,
+ * 2 cs using 1 bit to address.
+ */
u8 rank;
u8 col;
u8 bk;
@@ -24,12 +29,16 @@
u8 row_3_4;
u8 cs0_row;
u8 cs1_row;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
/*
* For of-platdata, which would otherwise convert this into two
* byte-swapped integers. With a size of 9 bytes, this struct will
* appear in of-platdata as a byte array.
+ *
+ * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
*/
u8 dummy;
+#endif
};
struct rk3288_sdram_pctl_timing {
@@ -83,6 +92,16 @@
u32 ddrconfig;
u32 ddr_freq;
u32 dramtype;
+ /*
+ * DDR Stride is address mapping for DRAM space
+ * Stride Ch 0 range Ch1 range Total
+ * 0x00 0-256MB 256MB-512MB 512MB
+ * 0x05 0-1GB 0-1GB 1GB
+ * 0x09 0-2GB 0-2GB 2GB
+ * 0x0d 0-4GB 0-4GB 4GB
+ * 0x17 N/A 0-4GB 4GB
+ * 0x1a 0-4GB 4GB-8GB 8GB
+ */
u32 stride;
u32 odt;
};
diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
new file mode 100644
index 0000000..35423e1
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -0,0 +1,10 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co.,Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index a61934f..0aeb640 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -37,64 +37,65 @@
u8 reserved3[0x04]; /* 0x7c */
u32 ats_cfg; /* 0x80 ats clock configuration */
u32 trace_cfg; /* 0x84 trace clock configuration */
- u8 reserved4[0xf8]; /* 0x88 */
+ u8 reserved4[0x14]; /* 0x88 */
+ u32 pll_stable_status; /* 0x9c */
+ u8 reserved5[0xe0]; /* 0xa0 */
u32 clk_output_a; /* 0x180 clk_output_a */
u32 clk_output_b; /* 0x184 clk_output_a */
- u8 reserved5[0x278]; /* 0x188 */
+ u8 reserved6[0x278]; /* 0x188 */
u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */
u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
- u8 reserved6[0x08]; /* 0x408 */
+ u8 reserved7[0x08]; /* 0x408 */
u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */
u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */
u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */
u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */
- u8 reserved7[0x08]; /* 0x420 */
+ u8 reserved8[0x08]; /* 0x420 */
u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
u32 ss_clk_cfg; /* 0x42c security system clock cfg */
u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */
u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */
u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */
u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */
- u8 reserved8[0x50]; /* 0x440 */
+ u8 reserved9[0x44]; /* 0x440 */
+ u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock config */
+ u8 reserved10[0x8]; /* 0x488 */
u32 de_clk_cfg; /* 0x490 display engine clock configuration */
- u8 reserved9[0x04]; /* 0x494 */
+ u8 reserved11[0x04]; /* 0x494 */
u32 mp_clk_cfg; /* 0x498 mp clock configuration */
u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */
u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */
- u8 reserved10[0x1c]; /* 0x4a4 */
+ u8 reserved12[0x1c]; /* 0x4a4 */
u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */
u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */
u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */
u32 fd_clk_cfg; /* 0x4cc FD module clock */
u32 ve_clk_cfg; /* 0x4d0 VE module clock */
u32 avs_clk_cfg; /* 0x4d4 AVS module clock */
- u8 reserved11[0x18]; /* 0x4d8 */
+ u8 reserved13[0x18]; /* 0x4d8 */
u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */
u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */
u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */
- u8 reserved12[0x10]; /* 0x4fc */
+ u8 reserved14[0x10]; /* 0x4fc */
u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
- u8 reserved13[0x70]; /* 0x510 */
+ u8 reserved15[0x70]; /* 0x510 */
u32 ahb_gate0; /* 0x580 AHB0 Gating Register */
u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
- u8 reserved14[0x04]; /* 0x58c */
+ u8 reserved16[0x04]; /* 0x58c */
u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */
u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */
- u8 reserved15[0x08]; /* 0x598 */
+ u8 reserved17[0x08]; /* 0x598 */
u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */
u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */
u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */
- u8 reserved16[0x04]; /* 0x5ac */
+ u8 reserved18[0x04]; /* 0x5ac */
u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */
u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */
};
-/* pll4_periph0_cfg */
-#define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */
-
#define CCM_PLL4_CTRL_N_SHIFT 8
#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT)
#define CCM_PLL4_CTRL_P_SHIFT 16
@@ -102,6 +103,80 @@
#define CCM_PLL4_CTRL_M_SHIFT 18
#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT)
+/* pllx_cfg bits */
+#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16)
+#define CCM_PLL1_CTRL_EN (1 << 31)
+#define CCM_PLL1_CLOCK_TIME_2 (2 << 24)
+
+#define CCM_PLL2_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL2_CTRL_P(n) (((n) & 0x1) << 16)
+#define CCM_PLL2_CTRL_EN (1 << 31)
+#define CCM_PLL2_CLOCK_TIME_2 (2 << 24)
+
+#define CCM_PLL4_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL4_CTRL_EN (1 << 31)
+
+#define CCM_PLL6_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL6_CTRL_P(p) (((p) & 0x1) << 16)
+#define CCM_PLL6_CTRL_EN (1 << 31)
+#define CCM_PLL6_CFG_UPDATE (1 << 30)
+
+#define CCM_PLL12_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL12_CTRL_EN (1 << 31)
+
+#define PLL_C0CPUX_STATUS (1 << 0)
+#define PLL_C1CPUX_STATUS (1 << 1)
+#define PLL_DDR_STATUS (1 << 5)
+#define PLL_PERIPH1_STATUS (1 << 11)
+
+/* cpu_clk_source bits */
+#define C0_CPUX_CLK_SRC_SHIFT 0
+#define C1_CPUX_CLK_SRC_SHIFT 8
+#define C0_CPUX_CLK_SRC_MASK (1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_MASK (1 << C1_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_OSC24M (0 << C0_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_PLL1 (1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_OSC24M (0 << C1_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_PLL2 (1 << C1_CPUX_CLK_SRC_SHIFT)
+
+/* c0_cfg */
+#define C0_CFG_AXI0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0)
+#define C0_CFG_APB0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 8)
+
+/* ahbx_cfg */
+#define AHBx_SRC_CLK_SELECT_SHIFT 24
+#define AHBx_SRC_MASK (0x3 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB0_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB1_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB2_SRC_OSC24M (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH0 (0x1 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH1 (0x2 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0)
+
+/* apb0_cfg */
+#define APB0_SRC_CLK_SELECT_SHIFT 24
+#define APB0_SRC_MASK (0x1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_OSC24M (0x0 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_PLL_PERIPH0 (0x1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0)
+
+/* gtbus_clk_cfg */
+#define GTBUS_SRC_CLK_SELECT_SHIFT 24
+#define GTBUS_SRC_MASK (0x3 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_OSC24M (0x0 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH0 (0x1 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH1 (0x2 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0)
+
+/* cci400_clk_cfg */
+#define CCI400_SRC_CLK_SELECT_SHIFT 24
+#define CCI400_SRC_MASK (0x3 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_OSC24M (0x0 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH0 (0x1 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH1 (0x2 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0)
+
/* sd#_clk_cfg fields */
#define CCM_MMC_CTRL_M(x) ((x) - 1)
#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
@@ -112,6 +187,8 @@
#define CCM_MMC_CTRL_ENABLE (1 << 31)
/* ahb_gate0 fields */
+#define AHB_GATE_OFFSET_MCTL 14
+
/* On sun9i all sdc-s share their ahb gate, so ignore (x) */
#define AHB_GATE_OFFSET_NAND0 13
#define AHB_GATE_OFFSET_MMC(x) 8
@@ -126,6 +203,8 @@
#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
/* ahb_reset0_cfg fields */
+#define AHB_RESET_OFFSET_MCTL 14
+
/* On sun9i all sdc-s share their ahb reset, so ignore (x) */
#define AHB_RESET_OFFSET_MMC(x) 8
@@ -137,6 +216,11 @@
#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int clk);
+void clock_set_pll2(unsigned int clk);
+void clock_set_pll4(unsigned int clk);
+void clock_set_pll6(unsigned int clk);
+void clock_set_pll12(unsigned int clk);
unsigned int clock_get_pll4_periph0(void);
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 5f93830..3c85222 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -56,7 +56,7 @@
#define SUNXI_USB2_BASE 0x01c1c000
#endif
#ifdef CONFIG_SUNXI_GEN_SUN6I
-#ifdef CONFIG_MACH_SUN8I_H3
+#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
#define SUNXI_USBPHY_BASE 0x01c19000
#define SUNXI_USB0_BASE 0x01c1a000
#define SUNXI_USB1_BASE 0x01c1b000
@@ -97,6 +97,7 @@
#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) || \
defined(CONFIG_MACH_SUN50I)
/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
+#define SUNXI_SIDC_BASE 0x01c14000
#define SUNXI_SID_BASE 0x01c14200
#else
#define SUNXI_SID_BASE 0x01c23800
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index 04889c5..c775bcc 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -23,6 +23,10 @@
#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
+#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
+/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */
+#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200)
+
#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000)
#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000)
#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000)
@@ -38,6 +42,12 @@
#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000)
#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000)
+#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000)
+#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000)
+#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000)
+#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000)
+#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000)
+
/* AHB1 Module */
#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000)
#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000)
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 675876f..e0be744 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -26,6 +26,8 @@
#include <asm/arch/dram_sun8i_a83t.h>
#elif defined(CONFIG_MACH_SUN8I_H3)
#include <asm/arch/dram_sun8i_h3.h>
+#elif defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/dram_sun9i.h>
#else
#include <asm/arch/dram_sun4i.h>
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h
new file mode 100644
index 0000000..22be6bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h
@@ -0,0 +1,278 @@
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN9I_H
+#define _SUNXI_DRAM_SUN9I_H
+
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x00 */
+ u32 ccr; /* 0x04 controller configuration register */
+ u32 dbgcr; /* 0x08 */
+ u32 dbgcr1; /* 0x0c */
+ u32 rmcr; /* 0x10 */
+ u8 res1[0x1c]; /* 0x14 */
+ u32 mmcr; /* 0x30 */
+ u8 res2[0x3c]; /* 0x34 */
+ u32 mbagcr; /* 0x70 */
+ u32 mbacr; /* 0x74 */
+ u8 res3[0x10]; /* 0x78 */
+ u32 maer; /* 0x88 */
+ u8 res4[0x74]; /* 0x8c */
+ u32 mdfscr; /* 0x100 */
+ u32 mdfsmer; /* 0x104 */
+ u32 mdfsmrmr; /* 0x108 */
+ u32 mdfstr[4]; /* 0x10c */
+ u32 mdfsgcr; /* 0x11c */
+ u8 res5[0x1c]; /* 0x120 */
+ u32 mdfsivr; /* 0x13c */
+ u8 res6[0xc]; /* 0x140 */
+ u32 mdfstcr; /* 0x14c */
+};
+
+
+struct sunxi_mctl_ctl_reg {
+ u32 mstr; /* 0x00 master register */
+ u32 stat; /* 0x04 operating mode status register */
+ u8 res1[0x8]; /* 0x08 */
+ u32 mrctrl[2]; /* 0x10 mode register read/write control reg */
+ u32 mstat; /* 0x18 mode register read/write status reg */
+ u8 res2[0x4]; /* 0x1c */
+ u32 derateen; /* 0x20 temperature derate enable register */
+ u32 derateint; /* 0x24 temperature derate interval register */
+ u8 res3[0x8]; /* 0x28 */
+ u32 pwrctl; /* 0x30 low power control register */
+ u32 pwrtmg; /* 0x34 low power timing register */
+ u8 res4[0x18]; /* 0x38 */
+ u32 rfshctl0; /* 0x50 refresh control register 0 */
+ u32 rfshctl1; /* 0x54 refresh control register 1 */
+ u8 res5[0x8]; /* 0x58 */
+ u32 rfshctl3; /* 0x60 refresh control register 3 */
+ u32 rfshtmg; /* 0x64 refresh timing register */
+ u8 res6[0x68]; /* 0x68 */
+ u32 init[6]; /* 0xd0 SDRAM initialisation register */
+ u8 res7[0xc]; /* 0xe8 */
+ u32 rankctl; /* 0xf4 rank control register */
+ u8 res8[0x8]; /* 0xf8 */
+ u32 dramtmg[9]; /* 0x100 DRAM timing register */
+ u8 res9[0x5c]; /* 0x124 */
+ u32 zqctrl[3]; /* 0x180 ZQ control register */
+ u32 zqstat; /* 0x18c ZQ status register */
+ u32 dfitmg[2]; /* 0x190 DFI timing register */
+ u32 dfilpcfg; /* 0x198 DFI low power configuration register */
+ u8 res10[0x4]; /* 0x19c */
+ u32 dfiupd[4]; /* 0x1a0 DFI update register */
+ u32 dfimisc; /* 0x1b0 DFI miscellaneous control register */
+ u8 res11[0x1c]; /* 0x1b4 */
+ u32 trainctl[3]; /* 0x1d0 */
+ u32 trainstat; /* 0x1dc */
+ u8 res12[0x20]; /* 0x1e0 */
+ u32 addrmap[7]; /* 0x200 address map register */
+ u8 res13[0x24]; /* 0x21c */
+ u32 odtcfg; /* 0x240 ODT configuration register */
+ u32 odtmap; /* 0x244 ODT/rank map register */
+ u8 res14[0x8]; /* 0x248 */
+ u32 sched; /* 0x250 scheduler control register */
+ u8 res15[0x4]; /* 0x254 */
+ u32 perfhpr0; /* 0x258 high priority read CAM register 0 */
+ u32 perfhpr1; /* 0x25c high priority read CAM register 1 */
+ u32 perflpr0; /* 0x260 low priority read CAM register 0 */
+ u32 perflpr1; /* 0x264 low priority read CAM register 1 */
+ u32 perfwr0; /* 0x268 write CAM register 0 */
+ u32 perfwr1; /* 0x26c write CAM register 1 */
+};
+
+
+struct sunxi_mctl_phy_reg {
+ u8 res0[0x04]; /* 0x00 revision id ??? */
+ u32 pir; /* 0x04 PHY initialisation register */
+ u32 pgcr[4]; /* 0x08 PHY general configuration register */
+ u32 pgsr[2]; /* 0x18 PHY general status register */
+ u32 pllcr; /* 0x20 PLL control register */
+ u32 ptr[5]; /* 0x24 PHY timing register */
+ u32 acmdlr; /* 0x38 AC master delay line register */
+ u32 aclcdlr; /* 0x3c AC local calibrated delay line reg */
+ u32 acbdlr[10]; /* 0x40 AC bit delay line register */
+ u32 aciocr[6]; /* 0x68 AC IO configuration register */
+ u32 dxccr; /* 0x80 DATX8 common configuration register */
+ u32 dsgcr; /* 0x84 DRAM system general config register */
+ u32 dcr; /* 0x88 DRAM configuration register */
+ u32 dtpr[4]; /* 0x8c DRAM timing parameters register */
+ u32 mr0; /* 0x9c mode register 0 */
+ u32 mr1; /* 0xa0 mode register 1 */
+ u32 mr2; /* 0xa4 mode register 2 */
+ u32 mr3; /* 0xa8 mode register 3 */
+ u32 odtcr; /* 0xac ODT configuration register */
+ u32 dtcr; /* 0xb0 data training configuration register */
+ u32 dtar[4]; /* 0xb4 data training address register */
+ u32 dtdr[2]; /* 0xc4 data training data register */
+ u32 dtedr[2]; /* 0xcc data training eye data register */
+ u32 rdimmgcr[2]; /* 0xd4 RDIMM general configuration register */
+ u32 rdimmcr[2]; /* 0xdc RDIMM control register */
+ u32 gpr[2]; /* 0xe4 general purpose register */
+ u32 catr[2]; /* 0xec CA training register */
+ u32 dqdsr; /* 0xf4 DQS drift register */
+ u8 res1[0xc8]; /* 0xf8 */
+ u32 bistrr; /* 0x1c0 BIST run register */
+ u32 bistwcr; /* 0x1c4 BIST word count register */
+ u32 bistmskr[3]; /* 0x1c8 BIST mask register */
+ u32 bistlsr; /* 0x1d4 BIST LFSR seed register */
+ u32 bistar[3]; /* 0x1d8 BIST address register */
+ u32 bistupdr; /* 0x1e4 BIST user pattern data register */
+ u32 bistgsr; /* 0x1e8 BIST general status register */
+ u32 bistwer; /* 0x1dc BIST word error register */
+ u32 bistber[4]; /* 0x1f0 BIST bit error register */
+ u32 bistwcsr; /* 0x200 BIST word count status register */
+ u32 bistfwr[3]; /* 0x204 BIST fail word register */
+ u8 res2[0x28]; /* 0x210 */
+ u32 iovcr[2]; /* 0x238 IO VREF control register */
+ struct ddrphy_zq {
+ u32 cr; /* impedance control register */
+ u32 pr; /* impedance control data register */
+ u32 dr; /* impedance control data register */
+ u32 sr; /* impedance control status register */
+ } zq[4]; /* 0x240, 0x250, 0x260, 0x270 */
+ struct ddrphy_dx {
+ u32 gcr[4]; /* DATX8 general configuration register */
+ u32 gsr[3]; /* DATX8 general status register */
+ u32 bdlr[7]; /* DATX8 bit delay line register */
+ u32 lcdlr[3]; /* DATX8 local calibrated delay line reg */
+ u32 mdlr; /* DATX8 master delay line register */
+ u32 gtr; /* DATX8 general timing register */
+ u8 res[0x34];
+ } dx[4]; /* 0x280, 0x300, 0x380, 0x400 */
+};
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK (3 << 0)
+#define MCTL_CR_RANK(x) (((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK (3 << 2)
+#define MCTL_CR_BANK(x) ((x) << 2)
+#define MCTL_CR_ROW_MASK (0xf << 4)
+#define MCTL_CR_ROW(x) (((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK (3 << 12)
+#define MCTL_CR_BUSW16 (1 << 12)
+#define MCTL_CR_BUSW32 (3 << 12)
+#define MCTL_CR_DRAMTYPE_MASK (7 << 16)
+#define MCTL_CR_DRAMTYPE_DDR2 (2 << 16)
+#define MCTL_CR_DRAMTYPE_DDR3 (3 << 16)
+#define MCTL_CR_DRAMTYPE_LPDDR2 (6 << 16)
+
+#define MCTL_CR_CHANNEL_MASK ((1 << 22) | (1 << 20) | (1 << 19))
+#define MCTL_CR_CHANNEL_SINGLE (1 << 22)
+#define MCTL_CR_CHANNEL_DUAL ((1 << 22) | (1 << 20) | (1 << 19))
+
+#define MCTL_CCR_CH0_CLK_EN (1 << 15)
+#define MCTL_CCR_CH1_CLK_EN (1 << 31)
+
+/*
+ * post_cke_x1024 [bits 16..25]: Cycles to wait after driving CKE high
+ * to start the SDRAM initialization sequence (in 1024s of cycles).
+ */
+#define MCTL_INIT0_POST_CKE_x1024(n) ((n & 0x0fff) << 16)
+/*
+ * pre_cke_x1024 [bits 0..11] Cycles to wait after reset before driving
+ * CKE high to start the SDRAM initialization (in 1024s of cycles)
+ */
+#define MCTL_INIT0_PRE_CKE_x1024(n) ((n & 0x0fff) << 0)
+#define MCTL_INIT1_DRAM_RSTN_x1024(n) ((n & 0xff) << 16)
+#define MCTL_INIT1_FINAL_WAIT_x32(n) ((n & 0x3f) << 8)
+#define MCTL_INIT1_PRE_OCD_x32(n) ((n & 0x0f) << 0)
+#define MCTL_INIT2_IDLE_AFTER_RESET_x32(n) ((n & 0xff) << 8)
+#define MCTL_INIT2_MIN_STABLE_CLOCK_x1(n) ((n & 0x0f) << 0)
+#define MCTL_INIT3_MR(n) ((n & 0xffff) << 16)
+#define MCTL_INIT3_EMR(n) ((n & 0xffff) << 0)
+#define MCTL_INIT4_EMR2(n) ((n & 0xffff) << 16)
+#define MCTL_INIT4_EMR3(n) ((n & 0xffff) << 0)
+#define MCTL_INIT5_DEV_ZQINIT_x32(n) ((n & 0x00ff) << 16)
+#define MCTL_INIT5_MAX_AUTO_INIT_x1024(n) ((n & 0x03ff) << 0);
+
+#define MCTL_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0)
+#define MCTL_DFIUPD0_DIS_AUTO_CTRLUPD (1 << 31)
+
+#define MCTL_MSTR_DEVICETYPE_DDR3 1
+#define MCTL_MSTR_DEVICETYPE_LPDDR2 4
+#define MCTL_MSTR_DEVICETYPE_LPDDR3 8
+#define MCTL_MSTR_DEVICETYPE(type) \
+ ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_DEVICETYPE_DDR3 : \
+ ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_DEVICETYPE_LPDDR2 : \
+ MCTL_MSTR_DEVICETYPE_LPDDR3))
+#define MCTL_MSTR_BURSTLENGTH4 (2 << 16)
+#define MCTL_MSTR_BURSTLENGTH8 (4 << 16)
+#define MCTL_MSTR_BURSTLENGTH16 (8 << 16)
+#define MCTL_MSTR_BURSTLENGTH(type) \
+ ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_BURSTLENGTH8 : \
+ ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_BURSTLENGTH4 : \
+ MCTL_MSTR_BURSTLENGTH8))
+#define MCTL_MSTR_ACTIVERANKS(x) (((x == 2) ? 3 : 1) << 24)
+#define MCTL_MSTR_BUSWIDTH8 (2 << 12)
+#define MCTL_MSTR_BUSWIDTH16 (1 << 12)
+#define MCTL_MSTR_BUSWIDTH32 (0 << 12)
+#define MCTL_MSTR_2TMODE (1 << 10)
+
+#define MCTL_RFSHCTL3_DIS_AUTO_REFRESH (1 << 0)
+
+#define MCTL_ZQCTRL0_TZQCS(x) (x << 0)
+#define MCTL_ZQCTRL0_TZQCL(x) (x << 16)
+#define MCTL_ZQCTRL0_ZQCL_DIS (1 << 30)
+#define MCTL_ZQCTRL0_ZQCS_DIS (1 << 31)
+#define MCTL_ZQCTRL1_TZQRESET(x) (x << 20)
+#define MCTL_ZQCTRL1_TZQSI_x1024(x) (x << 0)
+#define MCTL_ZQCTRL2_TZRESET_TRIGGER (1 << 0)
+
+#define MCTL_PHY_DCR_BYTEMASK (1 << 10)
+#define MCTL_PHY_DCR_2TMODE (1 << 28)
+#define MCTL_PHY_DCR_DDR8BNK (1 << 3)
+#define MCTL_PHY_DRAMMODE_DDR3 3
+#define MCTL_PHY_DRAMMODE_LPDDR2 0
+#define MCTL_PHY_DRAMMODE_LPDDR3 1
+
+#define MCTL_DTCR_DEFAULT 0x00003007
+#define MCTL_DTCR_RANKEN(n) (((n == 2) ? 3 : 1) << 24)
+
+#define MCTL_PGCR1_ZCKSEL_MASK (3 << 23)
+#define MCTL_PGCR1_IODDRM_MASK (3 << 7)
+#define MCTL_PGCR1_IODDRM_DDR3 (1 << 7)
+#define MCTL_PGCR1_IODDRM_DDR3L (2 << 7)
+#define MCTL_PGCR1_INHVT_EN (1 << 26)
+
+#define MCTL_PLLGCR_PLL_BYPASS (1 << 31)
+#define MCTL_PLLGCR_PLL_POWERDOWN (1 << 29)
+
+#define MCTL_PIR_PLL_BYPASS (1 << 17)
+#define MCTL_PIR_MASK (~(1 << 17))
+#define MCTL_PIR_INIT (1 << 0)
+
+#define MCTL_PGSR0_ERRORS (0x1ff << 20)
+
+/* Constants for assembling MR0 */
+#define DDR3_MR0_PPD_FAST_EXIT (1 << 12)
+#define DDR3_MR0_WR(n) \
+ ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
+#define DDR3_MR0_CL(n) \
+ ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
+#define DDR3_MR0_BL8 (0 << 0)
+
+#define DDR3_MR1_RTT120OHM ((0 << 9) | (1 << 6) | (0 << 2))
+
+#define DDR3_MR2_TWL(n) \
+ (((n - 5) & 0x7) << 3)
+
+#define MCTL_NS2CYCLES_CEIL(ns) ((ns * (CONFIG_DRAM_CLK / 2) + 999) / 1000)
+
+#define DRAM_TYPE_DDR3 3
+#define DRAM_TYPE_LPDDR2 6
+#define DRAM_TYPE_LPDDR3 7
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h b/arch/arm/include/asm/arch-sunxi/gtbus.h
new file mode 100644
index 0000000..b8308d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus.h
@@ -0,0 +1,21 @@
+/*
+ * GTBUS initialisation
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_H
+#define _SUNXI_GTBUS_H
+
+#if defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/gtbus_sun9i.h>
+#endif
+
+#ifndef __ASSEMBLY__
+void gtbus_init(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
new file mode 100644
index 0000000..fd50826
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
@@ -0,0 +1,92 @@
+/*
+ * GTBUS initialisation for sun9i
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_SUN9I_H
+#define _SUNXI_GTBUS_SUN9I_H
+
+#include <linux/types.h>
+
+struct sunxi_gtbus_reg {
+ u32 mst_cfg[36]; /* 0x000 */
+ u8 reserved1[0x70]; /* 0x090 */
+ u32 bw_wdw_cfg; /* 0x100 */
+ u32 mst_read_prio_cfg[2]; /* 0x104 */
+ u32 lvl2_mst_cfg; /* 0x10c */
+ u32 sw_clk_on; /* 0x110 */
+ u32 sw_clk_off; /* 0x114 */
+ u32 pmu_mst_en; /* 0x118 */
+ u32 pmu_cfg; /* 0x11c */
+ u32 pmu_cnt[19]; /* 0x120 */
+ u32 reserved2[0x94]; /* 0x16c */
+ u32 cci400_config[3]; /* 0x200 */
+ u32 cci400_status[2]; /* 0x20c */
+};
+
+/* for register GT_MST_CFG_REG(n) */
+#define GT_ENABLE_REQ (1<<31) /* clock on */
+#define GT_DISABLE_REQ (1<<30) /* clock off */
+#define GT_QOS_SHIFT 28
+#define GT_THD1_SHIFT 16
+#define GT_REQN_MAX 0xf /* max no master requests in one cycle */
+#define GT_REQN_SHIFT 12
+#define GT_THD0_SHIFT 0
+
+#define GT_QOS_MAX 0x3
+#define GT_THD_MAX 0xfff
+#define GT_BW_WDW_MAX 0xffff
+
+/* mst_read_prio_cfg */
+#define GT_PRIO_LOW 0
+#define GT_PRIO_HIGH 1
+
+/* GTBUS port ids */
+#define GT_PORT_CPUM1 0
+#define GT_PORT_CPUM2 1
+#define GT_PORT_SATA 2
+#define GT_PORT_USB3 3
+#define GT_PORT_FE0 4
+#define GT_PORT_BE1 5
+#define GT_PORT_BE2 6
+#define GT_PORT_IEP0 7
+#define GT_PORT_FE1 8
+#define GT_PORT_BE0 9
+#define GT_PORT_FE2 10
+#define GT_PORT_IEP1 11
+#define GT_PORT_VED 12
+#define GT_PORT_VEE 13
+#define GT_PORT_FD 14
+#define GT_PORT_CSI 15
+#define GT_PORT_MP 16
+#define GT_PORT_HSI 17
+#define GT_PORT_SS 18
+#define GT_PORT_TS 19
+#define GT_PORT_DMA 20
+#define GT_PORT_NDFC0 21
+#define GT_PORT_NDFC1 22
+#define GT_PORT_CPUS 23
+#define GT_PORT_TH 24
+#define GT_PORT_GMAC 25
+#define GT_PORT_USB0 26
+#define GT_PORT_MSTG0 27
+#define GT_PORT_MSTG1 28
+#define GT_PORT_MSTG2 29
+#define GT_PORT_MSTG3 30
+#define GT_PORT_USB1 31
+#define GT_PORT_GPU0 32
+#define GT_PORT_GPU1 33
+#define GT_PORT_USB2 34
+#define GT_PORT_CPUM0 35
+
+#define GP_MST_CFG_DEFAULT \
+ ((GT_QOS_MAX << GT_QOS_SHIFT) | \
+ (GT_THD_MAX << GT_THD1_SHIFT) | \
+ (GT_REQN_MAX << GT_REQN_SHIFT) | \
+ (GT_THD_MAX << GT_THD0_SHIFT))
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h
index 6a14cad..cef6c98 100644
--- a/arch/arm/include/asm/arch-sunxi/usb_phy.h
+++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h
@@ -16,7 +16,6 @@
void sunxi_usb_phy_exit(int index);
void sunxi_usb_phy_power_on(int index);
void sunxi_usb_phy_power_off(int index);
-int sunxi_usb_phy_power_is_on(int index);
int sunxi_usb_phy_vbus_detect(int index);
int sunxi_usb_phy_id_detect(int index);
void sunxi_usb_phy_enable_squelch_detect(int index, int enable);
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 7daf8bc..388afcb 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -187,6 +187,16 @@
unsigned divisor);
/**
+ * Returns the current parent clock ID of a given peripheral. This can be
+ * useful in order to call clock_*_periph_*() from generic code that has no
+ * specific knowledge of system-level clock tree structure.
+ *
+ * @param periph_id peripheral to query
+ * @return clock ID of the peripheral's current parent clock
+ */
+enum clock_id clock_get_periph_parent(enum periph_id periph_id);
+
+/**
* Start a peripheral PLL clock at the given rate. This also resets the
* peripheral.
*
@@ -284,6 +294,36 @@
/* Returns a pointer to the given 'simple' PLL */
struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
+/*
+ * Given a peripheral ID, determine where the mux bits are in the peripheral
+ * clock's register, the number of divider bits the clock has, and the SoC-
+ * specific clock type.
+ *
+ * This is an internal API between the core Tegra clock code and the SoC-
+ * specific clock code.
+ *
+ * @param periph_id peripheral to query
+ * @param mux_bits Set to number of bits in mux register
+ * @param divider_bits Set to the relevant MASK_BITS_* value
+ * @param type Set to the SoC-specific clock type
+ * @return 0 on success, -1 on error
+ */
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+ int *divider_bits, int *type);
+
+/*
+ * Given a peripheral ID and clock source mux value, determine the clock_id
+ * of that peripheral's parent.
+ *
+ * This is an internal API between the core Tegra clock code and the SoC-
+ * specific clock code.
+ *
+ * @param periph_id peripheral to query
+ * @param source raw clock source mux value
+ * @return the CLOCK_ID_* value @source represents
+ */
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source);
+
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
@@ -362,6 +402,12 @@
};
extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
+struct periph_clk_init {
+ enum periph_id periph_id;
+ enum clock_id parent_clock_id;
+};
+extern struct periph_clk_init periph_clk_init_table[];
+
/**
* Enable output clock for external peripherals
*
diff --git a/arch/arm/include/asm/arch-tegra/mmc.h b/arch/arm/include/asm/arch-tegra/mmc.h
deleted file mode 100644
index c2d52b2..0000000
--- a/arch/arm/include/asm/arch-tegra/mmc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2011, Google Inc. All rights reserved.
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TEGRA_MMC_H_
-#define _TEGRA_MMC_H_
-
-void tegra_mmc_init(void);
-
-#endif /* _TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index 07ef4c0..64c848a 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -132,26 +132,5 @@
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
-struct mmc_host {
- struct tegra_mmc *reg;
- int id; /* device id/number, 0-3 */
- int enabled; /* 1 to enable, 0 to disable */
- int width; /* Bus Width, 1, 4 or 8 */
-#ifdef CONFIG_TEGRA186
- struct reset_ctl reset_ctl;
- struct clk clk;
-#else
- enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
-#endif
- struct gpio_desc cd_gpio; /* Change Detect GPIO */
- struct gpio_desc pwr_gpio; /* Power GPIO */
- struct gpio_desc wp_gpio; /* Write Protect GPIO */
- unsigned int version; /* SDHCI spec. version */
- unsigned int clock; /* Current clock (MHz) */
- struct mmc_config cfg; /* mmc configuration */
-};
-
-void pad_init_mmc(struct mmc_host *host);
-
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 35964d6..041b43c 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -18,13 +18,18 @@
#define ARASAN_NAND_BASEADDR 0xFF100000
-#define ZYNQMP_SATA_BASEADDR 0xFD0C0000
-
#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
+#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
+#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
+
+#define PS_MODE0 BIT(0)
+#define PS_MODE1 BIT(1)
+#define PS_MODE2 BIT(2)
+#define PS_MODE3 BIT(3)
struct crlapb_regs {
u32 reserved0[36];
@@ -35,7 +40,9 @@
u32 boot_mode; /* 0x200 */
u32 reserved3[14];
u32 rst_lpd_top; /* 0x23C */
- u32 reserved4[26];
+ u32 reserved4[4];
+ u32 boot_pin_ctrl; /* 0x250 */
+ u32 reserved5[21];
};
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
@@ -69,7 +76,14 @@
#define SD_MODE1 0x00000005 /* sd 1 */
#define NAND_MODE 0x00000004
#define EMMC_MODE 0x00000006
+#define USB_MODE 0x00000007
+#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
#define JTAG_MODE 0x00000000
+#define BOOT_MODE_USE_ALT 0x100
+#define BOOT_MODE_ALT_SHIFT 12
+/* SW secondary boot modes 0xa - 0xd */
+#define SW_USBHOST_MODE 0x0000000A
+#define SW_SATA_MODE 0x0000000B
#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h
index eb68185..a4e144b 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -14,7 +14,7 @@
int sec_firmware_init(const void *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
unsigned int sec_firmware_support_psci_version(void);
unsigned int _sec_firmware_support_psci_version(void);
#endif
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 9b79506..171f4d9 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -21,6 +21,11 @@
#endif
typedef struct { volatile int counter; } atomic_t;
+#if BITS_PER_LONG == 32
+typedef struct { volatile long long counter; } atomic64_t;
+#else /* BIT_PER_LONG == 32 */
+typedef struct { volatile long counter; } atomic64_t;
+#endif
#define ATOMIC_INIT(i) { (i) }
@@ -28,7 +33,9 @@
#include <asm/proc-armv/system.h>
#define atomic_read(v) ((v)->counter)
-#define atomic_set(v,i) (((v)->counter) = (i))
+#define atomic_set(v, i) (((v)->counter) = (i))
+#define atomic64_read(v) atomic_read(v)
+#define atomic64_set(v, i) atomic_set(v, i)
static inline void atomic_add(int i, volatile atomic_t *v)
{
@@ -101,6 +108,65 @@
local_irq_restore(flags);
}
+#if BITS_PER_LONG == 32
+
+static inline void atomic64_add(long long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+
+#else /* BIT_PER_LONG == 32 */
+
+static inline void atomic64_add(long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+#endif
+
+static inline void atomic64_inc(volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += 1;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_dec(volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= 1;
+ local_irq_restore(flags);
+}
+
/* Atomic operations are already serializing on ARM */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_dec() barrier()
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index b00dece..9a46340 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1171,6 +1171,7 @@
u32 sdram_tim1;
u32 sdram_tim2;
u32 sdram_tim3;
+ u32 ocp_config;
u32 read_idle_ctrl;
u32 zq_config;
u32 temp_alert_config;
diff --git a/arch/arm/include/asm/errno.h b/arch/arm/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/arm/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index b35c271..4525287 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -26,13 +26,8 @@
#define CONFIG_FSL_CAAM
#endif
-#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_DM 1
-#define CONFIG_SPL_CRYPTO_SUPPORT
-#define CONFIG_SPL_HASH_SUPPORT
-#define CONFIG_SPL_RSA
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#ifdef CONFIG_SPL_BUILD
/*
* Define the key hash for U-Boot here if public/private key pair used to
* sign U-boot are different from the SRK hash put in the fuse
@@ -126,6 +121,24 @@
/* BOOTSCRIPT_ADDR is not required */
#endif
+#ifdef CONFIG_FSL_LS_PPA
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
+#ifdef CONFIG_LS1043A
+#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000
+#endif
+#else
+#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
+#endif /* ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP */
+
+/* Define the key hash here if SRK used for signing PPA image is
+ * different from SRK hash put in SFP used for U-Boot.
+ * Example
+ * #define CONFIG_PPA_KEY_HASH \
+ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ */
+#define CONFIG_PPA_KEY_HASH NULL
+#endif /* ifdef CONFIG_FSL_LS_PPA */
+
#include <config_fsl_chain_trust.h>
#endif /* #ifndef CONFIG_SPL_BUILD */
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 1055017..aee87cd 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -60,7 +60,7 @@
unsigned long tlb_allocated;
#endif
-#ifdef CONFIG_OMAP_COMMON
+#ifdef CONFIG_ARCH_OMAP2
u32 omap_boot_device;
u32 omap_boot_mode;
u8 omap_ch_flags;
diff --git a/arch/arm/include/asm/imx-common/hab.h b/arch/arm/include/asm/imx-common/hab.h
index dab6789..e0ff459 100644
--- a/arch/arm/include/asm/imx-common/hab.h
+++ b/arch/arm/include/asm/imx-common/hab.h
@@ -145,4 +145,6 @@
/* ----------- end of HAB API updates ------------*/
+uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size);
+
#endif
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 2e49968..7587cbb 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -39,10 +39,9 @@
* MUX_CTRL_OFS: 0..11 (12)
* PAD_CTRL_OFS: 12..23 (12)
* SEL_INPUT_OFS: 24..35 (12)
- * MUX_MODE + SION: 36..40 (5)
- * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
- * SEL_INP: 59..62 (4)
- * reserved: 63 (1)
+ * MUX_MODE + SION + LPSR: 36..41 (6)
+ * PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
+ * SEL_INP: 60..63 (4)
*/
typedef u64 iomux_v3_cfg_t;
@@ -57,10 +56,10 @@
MUX_SEL_INPUT_OFS_SHIFT)
#define MUX_MODE_SHIFT 36
-#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
-#define MUX_PAD_CTRL_SHIFT 41
+#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL_SHIFT 42
#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
-#define MUX_SEL_INPUT_SHIFT 59
+#define MUX_SEL_INPUT_SHIFT 60
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
@@ -85,12 +84,12 @@
#define NO_PAD_CTRL (1 << 17)
+#define IOMUX_CONFIG_LPSR 0x20
+#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
+ MUX_MODE_SHIFT)
#ifdef CONFIG_MX7
#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
-#define IOMUX_CONFIG_LPSR 0x8
-#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
- MUX_MODE_SHIFT)
#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)
@@ -145,10 +144,12 @@
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
-#if defined CONFIG_MX6SL
+/* i.MX6SL/SLL */
#define PAD_CTL_LVE (1 << 1)
#define PAD_CTL_LVE_BIT (1 << 22)
-#endif
+
+/* i.MX6SLL */
+#define PAD_CTL_IPD_BIT (1 << 27)
#elif defined(CONFIG_VF610)
diff --git a/arch/arm/include/asm/imx-common/regs-lcdif.h b/arch/arm/include/asm/imx-common/regs-lcdif.h
index 5a4f61f..ab147b5 100644
--- a/arch/arm/include/asm/imx-common/regs-lcdif.h
+++ b/arch/arm/include/asm/imx-common/regs-lcdif.h
@@ -20,7 +20,7 @@
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7)
+ defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -56,7 +56,7 @@
mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7)
+ defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -64,7 +64,8 @@
mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)
diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 32f95b3..539d34b 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -30,9 +30,13 @@
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
+#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
+#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h
index cad5f86..941a031 100644
--- a/arch/arm/include/asm/imx-common/video.h
+++ b/arch/arm/include/asm/imx-common/video.h
@@ -12,6 +12,7 @@
int bus;
int addr;
int pixfmt;
+ int di;
int (*detect)(struct display_info_t const *dev);
void (*enable)(struct display_info_t const *dev);
struct fb_videomode mode;
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 9bb0efa..e1916f7 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -8,6 +8,11 @@
#ifndef __ASM_ARM_MACRO_H__
#define __ASM_ARM_MACRO_H__
+
+#ifdef CONFIG_ARM64
+#include <asm/system.h>
+#endif
+
#ifdef __ASSEMBLY__
/*
@@ -135,13 +140,21 @@
#endif
.endm
-.macro armv8_switch_to_el2_m, xreg1
- /* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
- mov \xreg1, #0x5b1
- msr scr_el3, \xreg1
+/*
+ * Switch from EL3 to EL2 for ARMv8
+ * @ep: kernel entry point
+ * @flag: The execution state flag for lower exception
+ * level, ES_TO_AARCH64 or ES_TO_AARCH32
+ * @tmp: temporary register
+ *
+ * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
+ * For loading 64-bit OS, x0 is physical address to the FDT blob.
+ * They will be passed to the guest.
+ */
+.macro armv8_switch_to_el2_m, ep, flag, tmp
msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
- mov \xreg1, #0x33ff
- msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
+ mov \tmp, #CPTR_EL2_RES1
+ msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
/* Initialize Generic Timers */
msr cntvoff_el2, xzr
@@ -152,45 +165,96 @@
* and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
* EE,WXN,I,SA,C,A,M to 0
*/
- mov \xreg1, #0x0830
- movk \xreg1, #0x30C5, lsl #16
- msr sctlr_el2, \xreg1
+ ldr \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\
+ SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\
+ SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\
+ SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS)
+ msr sctlr_el2, \tmp
+
+ mov \tmp, sp
+ msr sp_el2, \tmp /* Migrate SP */
+ mrs \tmp, vbar_el3
+ msr vbar_el2, \tmp /* Migrate VBAR */
+
+ /* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */
+ cmp \flag, #ES_TO_AARCH32
+ b.eq 1f
+
+ /*
+ * The next lower exception level is AArch64, 64bit EL2 | HCE |
+ * RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ * and the SMD depends on requirements.
+ */
+#ifdef CONFIG_ARMV8_PSCI
+ ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
+ SCR_EL3_RES1 | SCR_EL3_NS_EN)
+#else
+ ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
+ SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
+ SCR_EL3_NS_EN)
+#endif
+ msr scr_el3, \tmp
/* Return to the EL2_SP2 mode from EL3 */
- mov \xreg1, sp
- msr sp_el2, \xreg1 /* Migrate SP */
- mrs \xreg1, vbar_el3
- msr vbar_el2, \xreg1 /* Migrate VBAR */
- mov \xreg1, #0x3c9
- msr spsr_el3, \xreg1 /* EL2_SP2 | D | A | I | F */
- msr elr_el3, lr
+ ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
+ SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
+ SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H)
+ msr spsr_el3, \tmp
+ msr elr_el3, \ep
+ eret
+
+1:
+ /*
+ * The next lower exception level is AArch32, 32bit EL2 | HCE |
+ * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ */
+ ldr \tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\
+ SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
+ SCR_EL3_NS_EN)
+ msr scr_el3, \tmp
+
+ /* Return to AArch32 Hypervisor mode */
+ ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
+ SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
+ SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
+ SPSR_EL_M_HYP)
+ msr spsr_el3, \tmp
+ msr elr_el3, \ep
eret
.endm
-.macro armv8_switch_to_el1_m, xreg1, xreg2
+/*
+ * Switch from EL2 to EL1 for ARMv8
+ * @ep: kernel entry point
+ * @flag: The execution state flag for lower exception
+ * level, ES_TO_AARCH64 or ES_TO_AARCH32
+ * @tmp: temporary register
+ *
+ * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
+ * For loading 64-bit OS, x0 is physical address to the FDT blob.
+ * They will be passed to the guest.
+ */
+.macro armv8_switch_to_el1_m, ep, flag, tmp
/* Initialize Generic Timers */
- mrs \xreg1, cnthctl_el2
- orr \xreg1, \xreg1, #0x3 /* Enable EL1 access to timers */
- msr cnthctl_el2, \xreg1
+ mrs \tmp, cnthctl_el2
+ /* Enable EL1 access to timers */
+ orr \tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\
+ CNTHCTL_EL2_EL1PCTEN_EN)
+ msr cnthctl_el2, \tmp
msr cntvoff_el2, xzr
/* Initilize MPID/MPIDR registers */
- mrs \xreg1, midr_el1
- mrs \xreg2, mpidr_el1
- msr vpidr_el2, \xreg1
- msr vmpidr_el2, \xreg2
+ mrs \tmp, midr_el1
+ msr vpidr_el2, \tmp
+ mrs \tmp, mpidr_el1
+ msr vmpidr_el2, \tmp
/* Disable coprocessor traps */
- mov \xreg1, #0x33ff
- msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
+ mov \tmp, #CPTR_EL2_RES1
+ msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
- mov \xreg1, #3 << 20
- msr cpacr_el1, \xreg1 /* Enable FP/SIMD at EL1 */
-
- /* Initialize HCR_EL2 */
- mov \xreg1, #(1 << 31) /* 64bit EL1 */
- orr \xreg1, \xreg1, #(1 << 29) /* Disable HVC */
- msr hcr_el2, \xreg1
+ mov \tmp, #CPACR_EL1_FPEN_EN
+ msr cpacr_el1, \tmp /* Enable FP/SIMD at EL1 */
/* SCTLR_EL1 initialization
*
@@ -199,18 +263,50 @@
* UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
* CP15BEN,SA0,SA,C,A,M to 0
*/
- mov \xreg1, #0x0800
- movk \xreg1, #0x30d0, lsl #16
- msr sctlr_el1, \xreg1
+ ldr \tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\
+ SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\
+ SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\
+ SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\
+ SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\
+ SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\
+ SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\
+ SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\
+ SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS)
+ msr sctlr_el1, \tmp
+
+ mov \tmp, sp
+ msr sp_el1, \tmp /* Migrate SP */
+ mrs \tmp, vbar_el2
+ msr vbar_el1, \tmp /* Migrate VBAR */
+
+ /* Check switch to AArch64 EL1 or AArch32 Supervisor mode */
+ cmp \flag, #ES_TO_AARCH32
+ b.eq 1f
+
+ /* Initialize HCR_EL2 */
+ ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
+ msr hcr_el2, \tmp
/* Return to the EL1_SP1 mode from EL2 */
- mov \xreg1, sp
- msr sp_el1, \xreg1 /* Migrate SP */
- mrs \xreg1, vbar_el2
- msr vbar_el1, \xreg1 /* Migrate VBAR */
- mov \xreg1, #0x3c5
- msr spsr_el2, \xreg1 /* EL1_SP1 | D | A | I | F */
- msr elr_el2, lr
+ ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
+ SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
+ SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H)
+ msr spsr_el2, \tmp
+ msr elr_el2, \ep
+ eret
+
+1:
+ /* Initialize HCR_EL2 */
+ ldr \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS)
+ msr hcr_el2, \tmp
+
+ /* Return to AArch32 Supervisor mode from EL2 */
+ ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
+ SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
+ SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
+ SPSR_EL_M_SVC)
+ msr spsr_el2, \tmp
+ msr elr_el2, \ep
eret
.endm
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 1864ab9..6b46078 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -45,7 +45,7 @@
/*
* Virtual <-> DMA view memory address translations
* Again, these are *only* valid on the kernel direct mapped RAM
- * memory. Use of these is *depreciated*.
+ * memory. Use of these is *deprecated*.
*/
#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x)))
#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x))))
@@ -127,7 +127,7 @@
#endif
/*
- * We should really eliminate virt_to_bus() here - it's depreciated.
+ * We should really eliminate virt_to_bus() here - it's deprecated.
*/
#define page_to_bus(page) (virt_to_bus(page_address(page)))
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 605c549..2034a5e 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -539,18 +539,26 @@
int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
};
+enum {
+ OPP_LOW,
+ OPP_NOM,
+ OPP_OD,
+ OPP_HIGH,
+ NUM_OPPS,
+};
+
/**
* struct volts_efuse_data - efuse definition for voltage
* @reg: register address for efuse
* @reg_bits: Number of bits in a register address, mandatory.
*/
struct volts_efuse_data {
- u32 reg;
+ u32 reg[NUM_OPPS];
u8 reg_bits;
};
struct volts {
- u32 value;
+ u32 value[NUM_OPPS];
u32 addr;
struct volts_efuse_data efuse;
struct pmic_data *pmic;
@@ -558,6 +566,16 @@
u32 abb_tx_done_mask;
};
+enum {
+ VOLT_MPU,
+ VOLT_CORE,
+ VOLT_MM,
+ VOLT_GPU,
+ VOLT_EVE,
+ VOLT_IVA,
+ NUM_VOLT_RAILS,
+};
+
struct vcores_data {
struct volts mpu;
struct volts core;
@@ -582,6 +600,7 @@
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
extern struct pmic_data tps659038;
+extern struct pmic_data lp8733;
void hw_data_init(void);
@@ -612,6 +631,7 @@
void disable_usb_clocks(int index);
void scale_vcores(struct vcores_data const *);
+int get_voltrail_opp(int rail_offset);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
@@ -632,6 +652,7 @@
* security (HS) device variants by doing a specially-formed smc entry.
*/
u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
void enable_edma3_clocks(void);
void disable_edma3_clocks(void);
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index b69d073..f2bf645 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -167,5 +167,5 @@
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio);
-
+void vmmc_pbias_config(uint voltage);
#endif /* OMAP_MMC_H_ */
diff --git a/arch/arm/include/asm/omap_musb.h b/arch/arm/include/asm/omap_musb.h
index 8b9cb0e..7c5fb40 100644
--- a/arch/arm/include/asm/omap_musb.h
+++ b/arch/arm/include/asm/omap_musb.h
@@ -15,9 +15,10 @@
struct omap_musb_board_data {
u8 interface_type;
- void (*set_phy_power)(u8 on);
- void (*clear_irq)(void);
- void (*reset)(void);
+ struct udevice *dev;
+ void (*set_phy_power)(struct udevice *dev, u8 on);
+ void (*clear_irq)(struct udevice *dev);
+ void (*reset)(struct udevice *dev);
};
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
diff --git a/arch/arm/include/asm/omap_sec_common.h b/arch/arm/include/asm/omap_sec_common.h
index 842f2af..79f1fbd 100644
--- a/arch/arm/include/asm/omap_sec_common.h
+++ b/arch/arm/include/asm/omap_sec_common.h
@@ -27,4 +27,34 @@
*/
int secure_boot_verify_image(void **p_image, size_t *p_size);
+/*
+ * Invoke a secure HAL API that allows configuration of the external memory
+ * firewall regions.
+ */
+int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr,
+ uint32_t size, uint32_t access_perm,
+ uint32_t initiator_perm);
+
+/*
+ * Invoke a secure HAL API on high-secure (HS) device variants that reserves a
+ * region of external memory for secure world use, and protects it using memory
+ * firewalls that prevent public world access. This API is intended to setaside
+ * memory that will be used for a secure world OS/TEE.
+ */
+int secure_emif_reserve(void);
+
+/*
+ * Invoke a secure HAL API to lock the external memory firewall configurations.
+ * After this API is called, none of the HAL APIs for configuring the that
+ * firewall will be usable (calls to those APIs will return failure and have
+ * no effect).
+ */
+int secure_emif_firewall_lock(void);
+
+/*
+ * Invoke a secure HAL API to authenticate and install a Trusted Execution
+ * Environment (TEE) image.
+ */
+int secure_tee_install(u32 tee_image);
+
#endif /* _OMAP_SEC_COMMON_H_ */
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 5b8ce4d..ac8b00d 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -45,6 +45,9 @@
#define ARM_PSCI_0_2_FN_BASE 0x84000000
#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n))
+#define ARM_PSCI_0_2_FN64_BASE 0xC4000000
+#define ARM_PSCI_0_2_FN64(n) (ARM_PSCI_0_2_FN64_BASE + (n))
+
#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0)
#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1)
#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2)
@@ -56,6 +59,12 @@
#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+#define ARM_PSCI_0_2_FN64_CPU_SUSPEND ARM_PSCI_0_2_FN64(1)
+#define ARM_PSCI_0_2_FN64_CPU_ON ARM_PSCI_0_2_FN64(3)
+#define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4)
+#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5)
+#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7)
+
/* PSCI 1.0 interface */
#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11)
@@ -66,6 +75,12 @@
#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
+#define ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN64(12)
+#define ARM_PSCI_1_0_FN64_NODE_HW_STATE ARM_PSCI_0_2_FN64(13)
+#define ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND ARM_PSCI_0_2_FN64(14)
+#define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16)
+#define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17)
+
/* 1KB stack per core */
#define ARM_PSCI_STACK_SHIFT 10
#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)
@@ -89,6 +104,8 @@
int psci_update_dt(void *fdt);
void psci_board_init(void);
int fdt_psci(void *fdt);
+
+void psci_v7_flush_dcache_all(void);
#endif /* ! __ASSEMBLY__ */
#endif /* __ARM_PSCI_H__ */
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 5a403bc..d23044a 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,7 +6,7 @@
#define __secure __attribute__ ((section ("._secure.text")))
#define __secure_data __attribute__ ((section ("._secure.data")))
-#ifdef CONFIG_ARMV7_SECURE_BASE
+#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
/*
* Warning, horror ahead.
*
diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
index f7b97ef..df9934b 100644
--- a/arch/arm/include/asm/setjmp.h
+++ b/arch/arm/include/asm/setjmp.h
@@ -11,29 +11,26 @@
struct jmp_buf_data {
ulong target;
ulong regs[5];
+ int ret;
};
typedef struct jmp_buf_data jmp_buf[1];
static inline int setjmp(jmp_buf jmp)
{
- long r = 0;
+ jmp->ret = 0;
#ifdef CONFIG_ARM64
asm volatile(
"adr x1, jmp_target\n"
- "str x1, %1\n"
- "stp x26, x27, %2\n"
- "stp x28, x29, %3\n"
+ "str x1, %0\n"
+ "stp x26, x27, %1\n"
+ "stp x28, x29, %2\n"
"mov x1, sp\n"
- "str x1, %4\n"
- "b 2f\n"
+ "str x1, %3\n"
"jmp_target: "
- "mov %0, #1\n"
- "2:\n"
- : "+r" (r), "=m" (jmp->target),
- "=m" (jmp->regs[0]), "=m" (jmp->regs[2]),
- "=m" (jmp->regs[4])
+ : "=m" (jmp->target), "=m" (jmp->regs[0]),
+ "=m" (jmp->regs[2]), "=m" (jmp->regs[4])
:
: "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
@@ -49,26 +46,25 @@
#else
"adr r0, jmp_target\n"
#endif
- "mov r1, %1\n"
+ "mov r1, %0\n"
"mov r2, sp\n"
"stm r1!, {r0, r2, r4, r5, r6, r7}\n"
- "b 2f\n"
".align 2\n"
"jmp_target: \n"
- "mov %0, #1\n"
- "2:\n"
- : "+l" (r)
+ :
: "l" (&jmp->target)
: "r0", "r1", "r2", "r3", /* "r4", "r5", "r6", "r7", */
"r8", "r9", "r10", "r11", /* sp, */ "ip", "lr",
"cc", "memory");
#endif
- return r;
+ return jmp->ret;
}
-static inline __noreturn void longjmp(jmp_buf jmp)
+static inline __noreturn void longjmp(jmp_buf jmp, int ret)
{
+ jmp->ret = ret;
+
#ifdef CONFIG_ARM64
asm volatile(
"ldr x0, %0\n"
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 78a7fac..3a4e902 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -132,7 +132,7 @@
/* describes where the compressed ramdisk image lives (virtual address) */
/*
* this one accidentally used virtual addresses - as such,
- * its depreciated.
+ * it's deprecated.
*/
#define ATAG_INITRD 0x54410005
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 19c38f4..a0bda28 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -28,19 +28,11 @@
BOOT_DEVICE_SATA,
BOOT_DEVICE_I2C,
BOOT_DEVICE_BOARD,
+ BOOT_DEVICE_DFU,
BOOT_DEVICE_NONE
};
#endif
-/**
- * Board specific load method for boards that have a special way of loading
- * U-Boot, which does not fit with the existing SPL code.
- *
- * @return 0 on success, negative errno value on failure.
- */
-
-int spl_board_load_image(void);
-
/* Linker symbols. */
extern char __bss_start[], __bss_end[];
diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h
index c6dfb25..11eaa34 100644
--- a/arch/arm/include/asm/string.h
+++ b/arch/arm/include/asm/string.h
@@ -14,7 +14,7 @@
#undef __HAVE_ARCH_STRCHR
extern char * strchr(const char * s, int c);
-#ifdef CONFIG_USE_ARCH_MEMCPY
+#if CONFIG_IS_ENABLED(USE_ARCH_MEMCPY)
#define __HAVE_ARCH_MEMCPY
#endif
extern void * memcpy(void *, const void *, __kernel_size_t);
@@ -26,7 +26,7 @@
extern void * memchr(const void *, int, __kernel_size_t);
#undef __HAVE_ARCH_MEMZERO
-#ifdef CONFIG_USE_ARCH_MEMSET
+#if CONFIG_IS_ENABLED(USE_ARCH_MEMSET)
#define __HAVE_ARCH_MEMSET
#endif
extern void * memset(void *, int, __kernel_size_t);
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 7b7b867..dc4c991 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -18,6 +18,95 @@
#define CR_WXN (1 << 19) /* Write Permision Imply XN */
#define CR_EE (1 << 25) /* Exception (Big) Endian */
+#define ES_TO_AARCH64 1
+#define ES_TO_AARCH32 0
+
+/*
+ * SCR_EL3 bits definitions
+ */
+#define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */
+#define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */
+#define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */
+#define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */
+#define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */
+#define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */
+
+/*
+ * SPSR_EL3/SPSR_EL2 bits definitions
+ */
+#define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */
+#define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */
+#define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */
+#define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */
+#define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */
+#define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */
+#define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */
+#define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */
+#define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */
+#define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */
+#define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */
+#define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */
+#define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */
+
+/*
+ * CPTR_EL2 bits definitions
+ */
+#define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */
+
+/*
+ * SCTLR_EL2 bits definitions
+ */
+#define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\
+ 1 << 11 | 3 << 4) /* Reserved, RES1 */
+#define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */
+#define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */
+#define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
+#define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */
+#define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */
+#define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */
+#define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */
+
+/*
+ * CNTHCTL_EL2 bits definitions
+ */
+#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
+#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
+
+/*
+ * HCR_EL2 bits definitions
+ */
+#define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
+#define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
+#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
+
+/*
+ * CPACR_EL1 bits definitions
+ */
+#define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */
+
+/*
+ * SCTLR_EL1 bits definitions
+ */
+#define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\
+ 1 << 11) /* Reserved, RES1 */
+#define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */
+#define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */
+#define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */
+#define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */
+#define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */
+#define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */
+#define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */
+#define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
+#define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */
+#define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */
+#define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */
+#define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */
+#define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */
+#define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */
+#define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */
+#define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */
+#define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */
+
#ifndef __ASSEMBLY__
u64 get_page_table_size(void);
@@ -93,11 +182,41 @@
void __asm_flush_dcache_range(u64 start, u64 end);
void __asm_invalidate_tlb_all(void);
void __asm_invalidate_icache_all(void);
-int __asm_flush_l3_cache(void);
+int __asm_invalidate_l3_dcache(void);
+int __asm_flush_l3_dcache(void);
+int __asm_invalidate_l3_icache(void);
void __asm_switch_ttbr(u64 new_ttbr);
-void armv8_switch_to_el2(void);
-void armv8_switch_to_el1(void);
+/*
+ * Switch from EL3 to EL2 for ARMv8
+ *
+ * @args: For loading 64-bit OS, fdt address.
+ * For loading 32-bit OS, zero.
+ * @mach_nr: For loading 64-bit OS, zero.
+ * For loading 32-bit OS, machine nr
+ * @fdt_addr: For loading 64-bit OS, zero.
+ * For loading 32-bit OS, fdt address.
+ * @entry_point: kernel entry point
+ * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
+ */
+void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
+ u64 entry_point, u64 es_flag);
+/*
+ * Switch from EL2 to EL1 for ARMv8
+ *
+ * @args: For loading 64-bit OS, fdt address.
+ * For loading 32-bit OS, zero.
+ * @mach_nr: For loading 64-bit OS, zero.
+ * For loading 32-bit OS, machine nr
+ * @fdt_addr: For loading 64-bit OS, zero.
+ * For loading 32-bit OS, fdt address.
+ * @entry_point: kernel entry point
+ * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
+ */
+void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
+ u64 entry_point, u64 es_flag);
+void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
+ u64 entry_point);
void gic_init(void);
void gic_send_sgi(unsigned long sgino);
void wait_for_wakeup(void);
@@ -107,15 +226,6 @@
void flush_l3_cache(void);
/*
- *Issue a hypervisor call in accordance with ARM "SMC Calling convention",
- * DEN0028A
- *
- * @args: input and output arguments
- *
- */
-void hvc_call(struct pt_regs *args);
-
-/*
*Issue a secure monitor call in accordance with ARM "SMC Calling convention",
* DEN0028A
*
@@ -124,7 +234,19 @@
*/
void smc_call(struct pt_regs *args);
-void __noreturn psci_system_reset(bool smc);
+void __noreturn psci_system_reset(void);
+void __noreturn psci_system_off(void);
+
+#ifdef CONFIG_ARMV8_PSCI
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+void armv8_setup_psci(void);
+void psci_setup_vectors(void);
+void psci_arch_init(void);
+#endif
#endif /* __ASSEMBLY__ */
@@ -223,6 +345,10 @@
*/
void save_boot_params_ret(void);
+#ifdef CONFIG_ARMV7_LPAE
+void switch_to_hypervisor_ret(void);
+#endif
+
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
#ifdef __ARM_ARCH_7A__
@@ -333,7 +459,7 @@
/* options available for data cache on each page */
enum dcache_option {
- DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
+ DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h
index a0d0d9b..0627728 100644
--- a/arch/arm/include/asm/ti-common/keystone_net.h
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -51,9 +51,9 @@
/* MDIO module input frequency */
#ifdef CONFIG_SOC_K2G
-#define EMAC_MDIO_BUS_FREQ (clk_get_rate(sys_clk0_3_clk))
+#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(sys_clk0_3_clk))
#else
-#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
+#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(pass_pll_clk))
#endif
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h
index 2bdb71c..60d1160 100644
--- a/arch/arm/include/asm/ti-common/sys_proto.h
+++ b/arch/arm/include/asm/ti-common/sys_proto.h
@@ -9,7 +9,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_OMAP_COMMON
+#ifdef CONFIG_ARCH_OMAP2
#define TI_ARMV7_DRAM_ADDR_SPACE_START 0x80000000
#define TI_ARMV7_DRAM_ADDR_SPACE_END 0xFFFFFFFF
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index 414042d..305a302 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -37,6 +37,7 @@
/* board/.../... */
int board_init(void);
void dram_init_banksize (void);
+void board_quiesce_devices(void);
/* cpu/.../interrupt.c */
int arch_interrupt_init (void);
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index caa62c6..0051f76 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -92,3 +92,13 @@
AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
endif
endif
+
+# For building EFI apps
+CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
+CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI)
+
+CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI)
+CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
+
+extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
+extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index a517550..e261d4f 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -25,7 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_ARCH_FIXUP_FDT
int arch_fixup_fdt(void *blob)
{
bd_t *bd = gd->bd;
@@ -53,7 +52,8 @@
return ret;
#endif
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
ret = psci_update_dt(blob);
if (ret)
return ret;
@@ -61,4 +61,3 @@
return 0;
}
-#endif
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 53c3141..43cc83e 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -64,6 +64,10 @@
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
}
+__weak void board_quiesce_devices(void)
+{
+}
+
/**
* announce_and_cleanup() - Print message and prepare for kernel boot
*
@@ -84,6 +88,9 @@
#ifdef CONFIG_USB_DEVICE
udc_disconnect();
#endif
+
+ board_quiesce_devices();
+
cleanup_before_linux();
}
@@ -193,10 +200,6 @@
{
smp_kick_all_cpus();
dcache_disable(); /* flush cache before swtiching to EL2 */
- armv8_switch_to_el2();
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- armv8_switch_to_el1();
-#endif
}
#endif
@@ -273,6 +276,28 @@
}
#endif
+#ifdef CONFIG_ARM64
+__weak void update_os_arch_secondary_cores(uint8_t os_arch)
+{
+}
+
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+static void switch_to_el1(void)
+{
+ if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
+ (images.os.arch == IH_ARCH_ARM))
+ armv8_switch_to_el1(0, (u64)gd->bd->bi_arch_number,
+ (u64)images.ft_addr,
+ (u64)images.ep,
+ ES_TO_AARCH32);
+ else
+ armv8_switch_to_el1((u64)images.ft_addr, 0, 0,
+ images.ep,
+ ES_TO_AARCH64);
+}
+#endif
+#endif
+
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
@@ -291,8 +316,28 @@
announce_and_cleanup(fake);
if (!fake) {
+#ifdef CONFIG_ARMV8_PSCI
+ armv8_setup_psci();
+#endif
do_nonsec_virt_switch();
- kernel_entry(images->ft_addr, NULL, NULL, NULL);
+
+ update_os_arch_secondary_cores(images->os.arch);
+
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ armv8_switch_to_el2((u64)images->ft_addr, 0, 0,
+ (u64)switch_to_el1, ES_TO_AARCH64);
+#else
+ if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
+ (images->os.arch == IH_ARCH_ARM))
+ armv8_switch_to_el2(0, (u64)gd->bd->bi_arch_number,
+ (u64)images->ft_addr,
+ (u64)images->ep,
+ ES_TO_AARCH32);
+ else
+ armv8_switch_to_el2((u64)images->ft_addr, 0, 0,
+ images->ep,
+ ES_TO_AARCH64);
+#endif
}
#else
unsigned long machid = gd->bd->bi_arch_number;
@@ -372,10 +417,8 @@
if (images->ft_addr) {
off = fdt_path_offset(images->ft_addr, "/memory");
if (off < 0) {
-#ifdef CONFIG_ARCH_FIXUP_FDT
if (arch_fixup_fdt(images->ft_addr))
puts("## WARNING: fixup memory failed!\n");
-#endif
}
}
#endif
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 70e94f0..e9bbcf5 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -71,8 +71,13 @@
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
- debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
+#ifdef CONFIG_ARMV7_LPAE
+ debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
option);
+#else
+ debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
+ option);
+#endif
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S
new file mode 100644
index 0000000..5205646
--- /dev/null
+++ b/arch/arm/lib/crt0_aarch64_efi.S
@@ -0,0 +1,135 @@
+/*
+ * crt0-efi-aarch64.S - PE/COFF header for aarch64 EFI applications
+ *
+ * Copright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause
+ *
+ * This file is taken and modified from the gnu-efi project.
+ */
+
+ .section .text.head
+
+ /*
+ * Magic "MZ" signature for PE/COFF
+ */
+ .globl ImageBase
+ImageBase:
+ .ascii "MZ"
+ .skip 58 /* 'MZ' + pad + offset == 64 */
+ .long pe_header - ImageBase /* Offset to the PE header */
+pe_header:
+ .ascii "PE"
+ .short 0
+coff_header:
+ .short 0xaa64 /* AArch64 */
+ .short 2 /* nr_sections */
+ .long 0 /* TimeDateStamp */
+ .long 0 /* PointerToSymbolTable */
+ .long 1 /* NumberOfSymbols */
+ .short section_table - optional_header /* SizeOfOptionalHeader */
+ /*
+ * Characteristics: IMAGE_FILE_DEBUG_STRIPPED |
+ * IMAGE_FILE_EXECUTABLE_IMAGE | IMAGE_FILE_LINE_NUMS_STRIPPED
+ */
+ .short 0x206
+optional_header:
+ .short 0x20b /* PE32+ format */
+ .byte 0x02 /* MajorLinkerVersion */
+ .byte 0x14 /* MinorLinkerVersion */
+ .long _edata - _start /* SizeOfCode */
+ .long 0 /* SizeOfInitializedData */
+ .long 0 /* SizeOfUninitializedData */
+ .long _start - ImageBase /* AddressOfEntryPoint */
+ .long _start - ImageBase /* BaseOfCode */
+
+extra_header_fields:
+ .quad 0 /* ImageBase */
+ .long 0x20 /* SectionAlignment */
+ .long 0x8 /* FileAlignment */
+ .short 0 /* MajorOperatingSystemVersion */
+ .short 0 /* MinorOperatingSystemVersion */
+ .short 0 /* MajorImageVersion */
+ .short 0 /* MinorImageVersion */
+ .short 0 /* MajorSubsystemVersion */
+ .short 0 /* MinorSubsystemVersion */
+ .long 0 /* Win32VersionValue */
+
+ .long _edata - ImageBase /* SizeOfImage */
+
+ /*
+ * Everything before the kernel image is considered part of the header
+ */
+ .long _start - ImageBase /* SizeOfHeaders */
+ .long 0 /* CheckSum */
+ .short EFI_SUBSYSTEM /* Subsystem */
+ .short 0 /* DllCharacteristics */
+ .quad 0 /* SizeOfStackReserve */
+ .quad 0 /* SizeOfStackCommit */
+ .quad 0 /* SizeOfHeapReserve */
+ .quad 0 /* SizeOfHeapCommit */
+ .long 0 /* LoaderFlags */
+ .long 0x6 /* NumberOfRvaAndSizes */
+
+ .quad 0 /* ExportTable */
+ .quad 0 /* ImportTable */
+ .quad 0 /* ResourceTable */
+ .quad 0 /* ExceptionTable */
+ .quad 0 /* CertificationTable */
+ .quad 0 /* BaseRelocationTable */
+
+ /* Section table */
+section_table:
+
+ /*
+ * The EFI application loader requires a relocation section
+ * because EFI applications must be relocatable. This is a
+ * dummy section as far as we are concerned.
+ */
+ .ascii ".reloc"
+ .byte 0
+ .byte 0 /* end of 0 padding of section name */
+ .long 0
+ .long 0
+ .long 0 /* SizeOfRawData */
+ .long 0 /* PointerToRawData */
+ .long 0 /* PointerToRelocations */
+ .long 0 /* PointerToLineNumbers */
+ .short 0 /* NumberOfRelocations */
+ .short 0 /* NumberOfLineNumbers */
+ .long 0x42100040 /* Characteristics (section flags) */
+
+
+ .ascii ".text"
+ .byte 0
+ .byte 0
+ .byte 0 /* end of 0 padding of section name */
+ .long _edata - _start /* VirtualSize */
+ .long _start - ImageBase /* VirtualAddress */
+ .long _edata - _start /* SizeOfRawData */
+ .long _start - ImageBase /* PointerToRawData */
+
+ .long 0 /* PointerToRelocations (0 for executables) */
+ .long 0 /* PointerToLineNumbers (0 for executables) */
+ .short 0 /* NumberOfRelocations (0 for executables) */
+ .short 0 /* NumberOfLineNumbers (0 for executables) */
+ .long 0xe0500020 /* Characteristics (section flags) */
+
+_start:
+ stp x29, x30, [sp, #-32]!
+ mov x29, sp
+
+ stp x0, x1, [sp, #16]
+ mov x2, x0
+ mov x3, x1
+ adr x0, ImageBase
+ adrp x1, _DYNAMIC
+ add x1, x1, #:lo12:_DYNAMIC
+ bl _relocate
+ cbnz x0, 0f
+
+ ldp x0, x1, [sp, #16]
+ bl efi_main
+
+0: ldp x29, x30, [sp], #32
+ ret
diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S
new file mode 100644
index 0000000..967c885
--- /dev/null
+++ b/arch/arm/lib/crt0_arm_efi.S
@@ -0,0 +1,138 @@
+/*
+ * crt0-efi-arm.S - PE/COFF header for ARM EFI applications
+ *
+ * Copright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause
+ *
+ * This file is taken and modified from the gnu-efi project.
+ */
+
+ .section .text.head
+
+ /*
+ * Magic "MZ" signature for PE/COFF
+ */
+ .globl image_base
+image_base:
+ .ascii "MZ"
+ .skip 58 /* 'MZ' + pad + offset == 64 */
+ .long pe_header - image_base /* Offset to the PE header */
+pe_header:
+ .ascii "PE"
+ .short 0
+coff_header:
+ .short 0x1c2 /* Mixed ARM/Thumb */
+ .short 2 /* nr_sections */
+ .long 0 /* TimeDateStamp */
+ .long 0 /* PointerToSymbolTable */
+ .long 1 /* NumberOfSymbols */
+ .short section_table - optional_header /* SizeOfOptionalHeader */
+ /*
+ * Characteristics: IMAGE_FILE_32BIT_MACHINE |
+ * IMAGE_FILE_DEBUG_STRIPPED | IMAGE_FILE_EXECUTABLE_IMAGE |
+ * IMAGE_FILE_LINE_NUMS_STRIPPED
+ */
+ .short 0x306
+optional_header:
+ .short 0x10b /* PE32+ format */
+ .byte 0x02 /* MajorLinkerVersion */
+ .byte 0x14 /* MinorLinkerVersion */
+ .long _edata - _start /* SizeOfCode */
+ .long 0 /* SizeOfInitializedData */
+ .long 0 /* SizeOfUninitializedData */
+ .long _start - image_base /* AddressOfEntryPoint */
+ .long _start - image_base /* BaseOfCode */
+ .long 0 /* BaseOfData */
+
+extra_header_fields:
+ .long 0 /* image_base */
+ .long 0x20 /* SectionAlignment */
+ .long 0x8 /* FileAlignment */
+ .short 0 /* MajorOperatingSystemVersion */
+ .short 0 /* MinorOperatingSystemVersion */
+ .short 0 /* MajorImageVersion */
+ .short 0 /* MinorImageVersion */
+ .short 0 /* MajorSubsystemVersion */
+ .short 0 /* MinorSubsystemVersion */
+ .long 0 /* Win32VersionValue */
+
+ .long _edata - image_base /* SizeOfImage */
+
+ /*
+ * Everything before the kernel image is considered part of the header
+ */
+ .long _start - image_base /* SizeOfHeaders */
+ .long 0 /* CheckSum */
+ .short EFI_SUBSYSTEM /* Subsystem */
+ .short 0 /* DllCharacteristics */
+ .long 0 /* SizeOfStackReserve */
+ .long 0 /* SizeOfStackCommit */
+ .long 0 /* SizeOfHeapReserve */
+ .long 0 /* SizeOfHeapCommit */
+ .long 0 /* LoaderFlags */
+ .long 0x6 /* NumberOfRvaAndSizes */
+
+ .quad 0 /* ExportTable */
+ .quad 0 /* ImportTable */
+ .quad 0 /* ResourceTable */
+ .quad 0 /* ExceptionTable */
+ .quad 0 /* CertificationTable */
+ .quad 0 /* BaseRelocationTable */
+
+section_table:
+
+ /*
+ * The EFI application loader requires a relocation section
+ * because EFI applications must be relocatable. This is a
+ * dummy section as far as we are concerned.
+ */
+ .ascii ".reloc"
+ .byte 0
+ .byte 0 /* end of 0 padding of section name */
+ .long 0
+ .long 0
+ .long 0 /* SizeOfRawData */
+ .long 0 /* PointerToRawData */
+ .long 0 /* PointerToRelocations */
+ .long 0 /* PointerToLineNumbers */
+ .short 0 /* NumberOfRelocations */
+ .short 0 /* NumberOfLineNumbers */
+ .long 0x42100040 /* Characteristics (section flags) */
+
+ .ascii ".text"
+ .byte 0
+ .byte 0
+ .byte 0 /* end of 0 padding of section name */
+ .long _edata - _start /* VirtualSize */
+ .long _start - image_base /* VirtualAddress */
+ .long _edata - _start /* SizeOfRawData */
+ .long _start - image_base /* PointerToRawData */
+
+ .long 0 /* PointerToRelocations (0 for executables) */
+ .long 0 /* PointerToLineNumbers (0 for executables) */
+ .short 0 /* NumberOfRelocations (0 for executables) */
+ .short 0 /* NumberOfLineNumbers (0 for executables) */
+ .long 0xe0500020 /* Characteristics (section flags) */
+
+_start:
+ stmfd sp!, {r0-r2, lr}
+
+ mov r2, r0
+ mov r3, r1
+ adr r1, .L_DYNAMIC
+ ldr r0, [r1]
+ add r1, r0, r1
+ adr r0, image_base
+ bl _relocate
+ teq r0, #0
+ bne 0f
+
+ ldmfd sp, {r0-r1}
+ bl efi_main
+
+0: add sp, sp, #12
+ ldr pc, [sp], #4
+
+.L_DYNAMIC:
+ .word _DYNAMIC - .
diff --git a/arch/arm/lib/elf_aarch64_efi.lds b/arch/arm/lib/elf_aarch64_efi.lds
new file mode 100644
index 0000000..47cce1d
--- /dev/null
+++ b/arch/arm/lib/elf_aarch64_efi.lds
@@ -0,0 +1,70 @@
+/*
+ * U-Boot aarch64 EFI linker script
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Modified from elf_aarch64_efi.lds in gnu-efi
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+ .text 0x0 : {
+ _text = .;
+ *(.text.head)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ *(.srodata)
+ *(.rodata*)
+ . = ALIGN(16);
+ }
+ _etext = .;
+ _text_size = . - _text;
+ .dynamic : { *(.dynamic) }
+ .data : {
+ _data = .;
+ *(.sdata)
+ *(.data)
+ *(.data1)
+ *(.data.*)
+ *(.got.plt)
+ *(.got)
+
+ /*
+ * The EFI loader doesn't seem to like a .bss section, so we
+ * stick it all into .data:
+ */
+ . = ALIGN(16);
+ _bss = .;
+ *(.sbss)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(16);
+ _bss_end = .;
+ _edata = .;
+ }
+ .rela.dyn : { *(.rela.dyn) }
+ .rela.plt : { *(.rela.plt) }
+ .rela.got : { *(.rela.got) }
+ .rela.data : { *(.rela.data) *(.rela.data*) }
+ _data_size = . - _etext;
+
+ . = ALIGN(4096);
+ .dynsym : { *(.dynsym) }
+ . = ALIGN(4096);
+ .dynstr : { *(.dynstr) }
+ . = ALIGN(4096);
+ .note.gnu.build-id : { *(.note.gnu.build-id) }
+ /DISCARD/ : {
+ *(.rel.reloc)
+ *(.eh_frame)
+ *(.note.GNU-stack)
+ }
+ .comment 0 : { *(.comment) }
+}
diff --git a/arch/arm/lib/elf_arm_efi.lds b/arch/arm/lib/elf_arm_efi.lds
new file mode 100644
index 0000000..59f66a1
--- /dev/null
+++ b/arch/arm/lib/elf_arm_efi.lds
@@ -0,0 +1,70 @@
+/*
+ * U-Boot ARM EFI linker script
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Modified from elf_arm_efi.lds in gnu-efi
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text 0x0 : {
+ _text = .;
+ *(.text.head)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ *(.srodata)
+ *(.rodata*)
+ . = ALIGN(16);
+ }
+ _etext = .;
+ _text_size = . - _text;
+ .dynamic : { *(.dynamic) }
+ .data : {
+ _data = .;
+ *(.sdata)
+ *(.data)
+ *(.data1)
+ *(.data.*)
+ *(.got.plt)
+ *(.got)
+
+ /*
+ * The EFI loader doesn't seem to like a .bss section, so we
+ * stick it all into .data:
+ */
+ . = ALIGN(16);
+ _bss = .;
+ *(.sbss)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(16);
+ _bss_end = .;
+ _edata = .;
+ }
+ .rel.dyn : { *(.rel.dyn) }
+ .rel.plt : { *(.rel.plt) }
+ .rel.got : { *(.rel.got) }
+ .rel.data : { *(.rel.data) *(.rel.data*) }
+ _data_size = . - _etext;
+
+ . = ALIGN(4096);
+ .dynsym : { *(.dynsym) }
+ . = ALIGN(4096);
+ .dynstr : { *(.dynstr) }
+ . = ALIGN(4096);
+ .note.gnu.build-id : { *(.note.gnu.build-id) }
+ /DISCARD/ : {
+ *(.rel.reloc)
+ *(.eh_frame)
+ *(.note.GNU-stack)
+ }
+ .comment 0 : { *(.comment) }
+}
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index baf6d70..45af037 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -16,7 +16,8 @@
int fdt_psci(void *fdt)
{
-#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+#if defined(CONFIG_ARMV7_PSCI) || defined(CONFIG_ARMV8_PSCI) || \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
int tmp;
@@ -65,7 +66,7 @@
init_psci_node:
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
psci_ver = sec_firmware_support_psci_version();
-#elif defined(CONFIG_ARMV7_PSCI_1_0)
+#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
#endif
switch (psci_ver) {
diff --git a/arch/arm/lib/reloc_aarch64_efi.c b/arch/arm/lib/reloc_aarch64_efi.c
new file mode 100644
index 0000000..38c13d3
--- /dev/null
+++ b/arch/arm/lib/reloc_aarch64_efi.c
@@ -0,0 +1,87 @@
+/* reloc_aarch64.c - position independent x86 ELF shared object relocator
+ Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ Copyright (C) 1999 Hewlett-Packard Co.
+ Contributed by David Mosberger <davidm@hpl.hp.com>.
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials
+ provided with the distribution.
+ * Neither the name of Hewlett-Packard Co. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ SUCH DAMAGE.
+*/
+
+#include <efi.h>
+
+#include <elf.h>
+
+efi_status_t _relocate(long ldbase, Elf64_Dyn *dyn, efi_handle_t image,
+ struct efi_system_table *systab)
+{
+ long relsz = 0, relent = 0;
+ Elf64_Rela *rel = 0;
+ unsigned long *addr;
+ int i;
+
+ for (i = 0; dyn[i].d_tag != DT_NULL; ++i) {
+ switch (dyn[i].d_tag) {
+ case DT_RELA:
+ rel = (Elf64_Rela *)((ulong)dyn[i].d_un.d_ptr + ldbase);
+ break;
+ case DT_RELASZ:
+ relsz = dyn[i].d_un.d_val;
+ break;
+ case DT_RELAENT:
+ relent = dyn[i].d_un.d_val;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (!rel && relent == 0)
+ return EFI_SUCCESS;
+
+ if (!rel || relent == 0)
+ return EFI_LOAD_ERROR;
+
+ while (relsz > 0) {
+ /* apply the relocs */
+ switch (ELF64_R_TYPE(rel->r_info)) {
+ case R_AARCH64_NONE:
+ break;
+ case R_AARCH64_RELATIVE:
+ addr = (ulong *)(ldbase + rel->r_offset);
+ *addr = ldbase + rel->r_addend;
+ break;
+ default:
+ break;
+ }
+ rel = (Elf64_Rela *)((char *)rel + relent);
+ relsz -= relent;
+ }
+ return EFI_SUCCESS;
+}
diff --git a/arch/arm/lib/reloc_arm_efi.c b/arch/arm/lib/reloc_arm_efi.c
new file mode 100644
index 0000000..d2f96ee
--- /dev/null
+++ b/arch/arm/lib/reloc_arm_efi.c
@@ -0,0 +1,66 @@
+/*
+ * reloc_arm.c - position-independent ARM ELF shared object relocator
+ *
+ * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ * Copyright (C) 1999 Hewlett-Packard Co.
+ * Contributed by David Mosberger <davidm@hpl.hp.com>.
+ *
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is taken and modified from the gnu-efi project.
+ */
+
+#include <efi.h>
+#include <elf.h>
+
+efi_status_t _relocate(long ldbase, Elf32_Dyn *dyn, efi_handle_t image,
+ struct efi_system_table *systab)
+{
+ long relsz = 0, relent = 0;
+ Elf32_Rel *rel = 0;
+ ulong *addr;
+ int i;
+
+ for (i = 0; dyn[i].d_tag != DT_NULL; ++i) {
+ switch (dyn[i].d_tag) {
+ case DT_REL:
+ rel = (Elf32_Rel *)((ulong)dyn[i].d_un.d_ptr
+ + ldbase);
+ break;
+ case DT_RELSZ:
+ relsz = dyn[i].d_un.d_val;
+ break;
+ case DT_RELENT:
+ relent = dyn[i].d_un.d_val;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (!rel && relent == 0)
+ return EFI_SUCCESS;
+
+ if (!rel || relent == 0)
+ return EFI_LOAD_ERROR;
+
+ while (relsz > 0) {
+ /* apply the relocs */
+ switch (ELF32_R_TYPE(rel->r_info)) {
+ case R_ARM_NONE:
+ break;
+ case R_ARM_RELATIVE:
+ addr = (ulong *)(ldbase + rel->r_offset);
+ *addr += ldbase;
+ break;
+ default:
+ break;
+ }
+ rel = (Elf32_Rel *)((char *)rel + relent);
+ relsz -= relent;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 475d503..a6fb07c 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -8,6 +8,7 @@
#include <asm-offsets.h>
#include <config.h>
+#include <elf.h>
#include <linux/linkage.h>
#ifdef CONFIG_CPU_V7M
#include <asm/armv7m.h>
@@ -96,7 +97,7 @@
fixloop:
ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */
and r1, r1, #0xff
- cmp r1, #23 /* relative fixup? */
+ cmp r1, #R_ARM_RELATIVE
bne fixnext
/* relative fix: increase location by offset */
diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S
index 5c51cae..242e56e 100644
--- a/arch/arm/lib/relocate_64.S
+++ b/arch/arm/lib/relocate_64.S
@@ -10,6 +10,7 @@
#include <asm-offsets.h>
#include <config.h>
+#include <elf.h>
#include <linux/linkage.h>
#include <asm/macro.h>
@@ -47,7 +48,7 @@
ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
ldr x4, [x2], #8 /* x4 <- addend */
and x1, x1, #0xffffffff
- cmp x1, #1027 /* relative fixup? */
+ cmp x1, #R_AARCH64_RELATIVE
bne fixnext
/* relative fix: store addend plus offset at dest location */
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index 3587ad6..e606d47 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -47,7 +47,7 @@
* arg: Pointer to paramter image in RAM
*/
#ifdef CONFIG_SPL_OS_BOOT
-void __noreturn jump_to_image_linux(void *arg)
+void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg)
{
unsigned long machid = 0xffffffff;
#ifdef CONFIG_MACH_TYPE
@@ -58,7 +58,7 @@
typedef void (*image_entry_arg_t)(int, int, void *)
__attribute__ ((noreturn));
image_entry_arg_t image_entry =
- (image_entry_arg_t)(uintptr_t) spl_image.entry_point;
+ (image_entry_arg_t)(uintptr_t) spl_image->entry_point;
cleanup_before_linux();
image_entry(0, machid, arg);
}
diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile
index ddc323f..d36e15a 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -18,6 +18,7 @@
obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
obj-$(CONFIG_AT91_EFLASH) += eflash.o
obj-$(CONFIG_AT91_LED) += led.o
+obj-y += cache.o
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o
diff --git a/arch/arm/mach-at91/arm926ejs/cache.c b/arch/arm/mach-at91/arm926ejs/cache.c
new file mode 100644
index 0000000..8813706
--- /dev/null
+++ b/arch/arm/mach-at91/arm926ejs/cache.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <linux/types.h>
+#include <common.h>
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+}
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+/* Invalidate entire I-cache and branch predictor array */
+void invalidate_icache_all(void)
+{
+ unsigned long i = 0;
+
+ asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
+}
+#else
+void invalidate_icache_all(void)
+{
+}
+#endif
diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
index c8d24ae..e3181fa 100644
--- a/arch/arm/mach-at91/arm926ejs/clock.c
+++ b/arch/arm/mach-at91/arm926ejs/clock.c
@@ -162,7 +162,13 @@
gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = gd->arch.mck_rate_hz;
+#if defined(CONFIG_AT91SAM9X5)
+ /* different in prescale on at91sam9x5 */
+ freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4));
+#else
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
+#endif
+
#if defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index 76fcada..2e55953 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -11,7 +11,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index d37d908..f6bcecd 100644
--- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
@@ -147,6 +147,9 @@
#define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf
/* Bit field in Memory Device Register */
+#define ATMEL_MPDDRC_MD_SDR_SDRAM 0x0
+#define ATMEL_MPDDRC_MD_LP_SDR_SDRAM 0x1
+#define ATMEL_MPDDRC_MD_DDR_SDRAM 0x2
#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3
#define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4
#define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 6d2a7b7..5a32bdb 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -10,7 +10,7 @@
#define __ASM_ARCH_AT91_GPIO_H
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/hardware.h>
diff --git a/arch/arm/mach-bcm283x/include/mach/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h
index 7741d7b..b4caca1 100644
--- a/arch/arm/mach-bcm283x/include/mach/wdog.h
+++ b/arch/arm/mach-bcm283x/include/mach/wdog.h
@@ -16,7 +16,7 @@
struct bcm2835_wdog_regs {
u32 unknown0[7];
u32 rstc;
- u32 unknown1;
+ u32 rsts;
u32 wdog;
};
diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c
index 72cdc31..685815c 100644
--- a/arch/arm/mach-bcm283x/reset.c
+++ b/arch/arm/mach-bcm283x/reset.c
@@ -10,19 +10,66 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/wdog.h>
+#include <efi_loader.h>
#define RESET_TIMEOUT 10
-void reset_cpu(ulong addr)
+/*
+ * The Raspberry Pi firmware uses the RSTS register to know which partiton
+ * to boot from. The partiton value is spread into bits 0, 2, 4, 6, 8, 10.
+ * Partiton 63 is a special partition used by the firmware to indicate halt.
+ */
+#define BCM2835_WDOG_RSTS_RASPBERRYPI_HALT 0x555
+
+__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
+ (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
+
+void __efi_runtime reset_cpu(ulong addr)
{
- struct bcm2835_wdog_regs *regs =
- (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
uint32_t rstc;
- rstc = readl(®s->rstc);
+ rstc = readl(&wdog_regs->rstc);
rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;
- writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, ®s->wdog);
- writel(BCM2835_WDOG_PASSWORD | rstc, ®s->rstc);
+ writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, &wdog_regs->wdog);
+ writel(BCM2835_WDOG_PASSWORD | rstc, &wdog_regs->rstc);
}
+
+#ifdef CONFIG_EFI_LOADER
+
+void __efi_runtime EFIAPI efi_reset_system(
+ enum efi_reset_type reset_type,
+ efi_status_t reset_status,
+ unsigned long data_size, void *reset_data)
+{
+ u32 val;
+
+ switch (reset_type) {
+ case EFI_RESET_COLD:
+ case EFI_RESET_WARM:
+ reset_cpu(0);
+ break;
+ case EFI_RESET_SHUTDOWN:
+ /*
+ * We set the watchdog hard reset bit here to distinguish this reset
+ * from the normal (full) reset. bootcode.bin will not reboot after a
+ * hard reset.
+ */
+ val = readl(&wdog_regs->rsts);
+ val |= BCM2835_WDOG_PASSWORD;
+ val |= BCM2835_WDOG_RSTS_RASPBERRYPI_HALT;
+ writel(val, &wdog_regs->rsts);
+ reset_cpu(0);
+ break;
+ }
+
+ while (1) { }
+}
+
+void efi_reset_system_init(void)
+{
+ efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs));
+}
+
+#endif
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 5d1c5c5..c593dad 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -7,10 +7,14 @@
config TARGET_IPAM390
bool "IPAM390 board"
select SUPPORT_SPL
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
config TARGET_DA850EVM
bool "DA850 EVM board"
select SUPPORT_SPL
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
config TARGET_EA20
bool "EA20 board"
@@ -18,18 +22,30 @@
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SUPPORT_SPL
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
config TARGET_CALIMAIN
bool "Calimain board"
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
endchoice
config SYS_SOC
default "davinci"
+config SYS_DA850_PLL_INIT
+ bool
+
+config SYS_DA850_DDR_INIT
+ bool
+
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/davinci/ea20/Kconfig"
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index c25fcf3..07118fc 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,15 @@
if ARCH_EXYNOS5
+config SPL_GPIO_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
choice
prompt "EXYNOS5 board select"
@@ -117,6 +126,7 @@
config TARGET_ESPRESSO7420
bool "ESPRESSO7420 board"
select ARM64
+ select ARMV8_MULTIENTRY
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index 25a9df9..6a5d26c 100644
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c
@@ -618,7 +618,7 @@
/*
* Send NOP, MRS and ZQINIT commands
* Sending MRS command will reset the DRAM. We should not be
- * reseting the DRAM after resume, this will lead to memory
+ * resetting the DRAM after resume, this will lead to memory
* corruption as DRAM content is lost after DRAM reset
*/
dmc_config_mrs(mem, &drex0->directcmd);
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index f9c7468..cf149ad 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -9,6 +9,16 @@
#include <asm/io.h>
#include <asm/system.h>
+#ifdef CONFIG_TARGET_ESPRESSO7420
+/*
+ * Exynos7420 uses CPU0 of Cluster-1 as boot CPU. Due to this, branch_if_master
+ * fails to identify as the boot CPU as the master CPU. As temporary workaround,
+ * setup the slave CPU boot address as "_main".
+ */
+extern void _main(void);
+void *secondary_boot_addr = (void *)_main;
+#endif /* CONFIG_TARGET_ESPRESSO7420 */
+
void reset_cpu(ulong addr)
{
#ifdef CONFIG_CPU_V7
@@ -23,11 +33,3 @@
dcache_enable();
}
#endif
-
-#ifdef CONFIG_ARM64
-void lowlevel_init(void)
-{
- armv8_switch_to_el2();
- armv8_switch_to_el1();
-}
-#endif
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index b2ffe5b..8253a3b 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -18,5 +18,5 @@
obj-y += msmc.o
obj-y += ddr3.o
obj-y += keystone.o
-obj-$(CONFIG_K2E_EVM) += ddr3_spd.o
-obj-$(CONFIG_K2HK_EVM) += ddr3_spd.o
+obj-$(CONFIG_TARGET_K2E_EVM) += ddr3_spd.o
+obj-$(CONFIG_TARGET_K2HK_EVM) += ddr3_spd.o
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index b25db1e..68f8980 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -163,15 +163,15 @@
{
int pllod = data->pll_od - 1;
+ /* Enable Glitch free bypass for ARM PLL */
+ if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
+ clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
+
/* Enable Bypass mode */
setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
setbits_le32(keystone_pll_regs[data->pll].reg0,
CFG_PLLCTL0_BYPASS_MASK);
- /* Enable Glitch free bypass for ARM PLL */
- if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
- clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
-
configure_mult_div(data);
/* Program Output Divider */
@@ -189,10 +189,6 @@
if (data->pll == PASS_PLL && cpu_is_k2hk())
pll_pa_clk_sel();
- /* Select the Output of ARM PLL as input to ARM */
- if (data->pll == TETRIS_PLL)
- setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
-
clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
/* Wait for 500 * REFCLK cucles * (PLLD + 1) */
sdelay(105000);
@@ -200,6 +196,10 @@
/* Switch to PLL mode */
clrbits_le32(keystone_pll_regs[data->pll].reg0,
CFG_PLLCTL0_BYPASS_MASK);
+
+ /* Select the Output of ARM PLL as input to ARM */
+ if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
+ setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
}
void init_pll(const struct pll_init_data *data)
@@ -341,7 +341,7 @@
return ret;
}
-unsigned long clk_get_rate(unsigned int clk)
+unsigned long ks_clk_get_rate(unsigned int clk)
{
unsigned long freq = 0;
@@ -381,37 +381,37 @@
freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
break;
case sys_clk0_2_clk:
- freq = clk_get_rate(sys_clk0_clk) / 2;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 2;
break;
case sys_clk0_3_clk:
- freq = clk_get_rate(sys_clk0_clk) / 3;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 3;
break;
case sys_clk0_4_clk:
- freq = clk_get_rate(sys_clk0_clk) / 4;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 4;
break;
case sys_clk0_6_clk:
- freq = clk_get_rate(sys_clk0_clk) / 6;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 6;
break;
case sys_clk0_8_clk:
- freq = clk_get_rate(sys_clk0_clk) / 8;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 8;
break;
case sys_clk0_12_clk:
- freq = clk_get_rate(sys_clk0_clk) / 12;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 12;
break;
case sys_clk0_24_clk:
- freq = clk_get_rate(sys_clk0_clk) / 24;
+ freq = ks_clk_get_rate(sys_clk0_clk) / 24;
break;
case sys_clk1_3_clk:
- freq = clk_get_rate(sys_clk1_clk) / 3;
+ freq = ks_clk_get_rate(sys_clk1_clk) / 3;
break;
case sys_clk1_4_clk:
- freq = clk_get_rate(sys_clk1_clk) / 4;
+ freq = ks_clk_get_rate(sys_clk1_clk) / 4;
break;
case sys_clk1_6_clk:
- freq = clk_get_rate(sys_clk1_clk) / 6;
+ freq = ks_clk_get_rate(sys_clk1_clk) / 6;
break;
case sys_clk1_12_clk:
- freq = clk_get_rate(sys_clk1_clk) / 12;
+ freq = ks_clk_get_rate(sys_clk1_clk) / 12;
break;
default:
break;
diff --git a/arch/arm/mach-keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c
index 3d5cf3f..06afa72 100644
--- a/arch/arm/mach-keystone/cmd_clock.c
+++ b/arch/arm/mach-keystone/cmd_clock.c
@@ -74,7 +74,7 @@
clk = simple_strtoul(argv[1], NULL, 10);
- freq = clk_get_rate(clk);
+ freq = ks_clk_get_rate(clk);
if (freq)
printf("clock index [%d] - frequency %lu\n", clk, freq);
else
diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c
index 6a9bdc9..591e758 100644
--- a/arch/arm/mach-keystone/cmd_mon.c
+++ b/arch/arm/mach-keystone/cmd_mon.c
@@ -9,14 +9,16 @@
#include <common.h>
#include <command.h>
+#include <image.h>
#include <mach/mon.h>
asm(".arch_extension sec\n\t");
static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- u32 addr, dpsc_base = 0x1E80000, freq;
+ u32 addr, dpsc_base = 0x1E80000, freq, load_addr, size;
int rcode = 0;
+ struct image_header *header;
if (argc < 2)
return CMD_RET_USAGE;
@@ -25,9 +27,21 @@
addr = simple_strtoul(argv[1], NULL, 16);
- rcode = mon_install(addr, dpsc_base, freq);
- printf("## installed monitor, freq [%d], status %d\n",
- freq, rcode);
+ header = (struct image_header *)addr;
+
+ if (image_get_magic(header) != IH_MAGIC) {
+ printf("## Please update monitor image\n");
+ return -EFAULT;
+ }
+
+ load_addr = image_get_load(header);
+ size = image_get_data_size(header);
+ memcpy((void *)load_addr, (void *)(addr + sizeof(struct image_header)),
+ size);
+
+ rcode = mon_install(load_addr, dpsc_base, freq);
+ printf("## installed monitor @ 0x%x, freq [%d], status %d\n",
+ load_addr, freq, rcode);
return 0;
}
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 34606f4..ee8e12e 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -65,9 +65,8 @@
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
- /* Disable ECC for K2G */
if (cpu_is_k2g()) {
- clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
+ setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
@@ -139,7 +138,10 @@
puts("\nClear entire DDR3 memory to enable ECC\n");
/* save the SES MPAX regs */
- msmc_get_ses_mpax(8, 0, mpax);
+ if (cpu_is_k2g())
+ msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
+ else
+ msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
/* setup edma slot 1 configuration */
slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
@@ -170,8 +172,17 @@
for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
/* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
access slave interface so that edma driver can access */
- msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
- KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
+ if (cpu_is_k2g()) {
+ msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
+ base >> KS2_MSMC_SEG_SIZE_SHIFT,
+ KS2_MSMC_DST_SEG_BASE + seg,
+ MPAX_SEG_2G);
+ } else {
+ msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
+ base >> KS2_MSMC_SEG_SIZE_SHIFT,
+ KS2_MSMC_DST_SEG_BASE + seg,
+ MPAX_SEG_2G);
+ }
if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
edma_blks = KS2_MSMC_MAP_SEG_NUM <<
@@ -198,7 +209,10 @@
qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
/* restore the SES MPAX regs */
- msmc_set_ses_mpax(8, 0, mpax);
+ if (cpu_is_k2g())
+ msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
+ else
+ msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
}
static void ddr3_ecc_init_range(u32 base)
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 72724aa..0d8a944 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -125,9 +125,7 @@
void init_plls(void);
void init_pll(const struct pll_init_data *data);
struct pll_init_data *get_pll_init_data(int pll);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
+unsigned long ks_clk_get_rate(unsigned int clk);
int get_max_dev_speed(int *spds);
int get_max_arm_speed(int *spds);
void pll_pa_clk_sel(void);
diff --git a/arch/arm/mach-keystone/psc.c b/arch/arm/mach-keystone/psc.c
index ff042a6..bbea74a 100644
--- a/arch/arm/mach-keystone/psc.c
+++ b/arch/arm/mach-keystone/psc.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/psc_defs.h>
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 9205b1e..9c24921 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -10,6 +10,9 @@
config TARGET_DREAMPLUG
bool "DreamPlug Board"
+config TARGET_DS109
+ bool "Synology DS109"
+
config TARGET_GURUPLUG
bool "GuruPlug Board"
@@ -59,6 +62,7 @@
source "board/Marvell/openrd/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
+source "board/Synology/ds109/Kconfig"
source "board/Marvell/guruplug/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"
source "board/buffalo/lsxl/Kconfig"
diff --git a/arch/arm/mach-litesom/Kconfig b/arch/arm/mach-litesom/Kconfig
new file mode 100644
index 0000000..9b7f36d
--- /dev/null
+++ b/arch/arm/mach-litesom/Kconfig
@@ -0,0 +1,6 @@
+config LITESOM
+ bool
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
diff --git a/arch/arm/mach-litesom/Makefile b/arch/arm/mach-litesom/Makefile
new file mode 100644
index 0000000..b15eb64
--- /dev/null
+++ b/arch/arm/mach-litesom/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Grinn
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := litesom.o
diff --git a/arch/arm/mach-litesom/include/mach/litesom.h b/arch/arm/mach-litesom/include/mach/litesom.h
new file mode 100644
index 0000000..6833949
--- /dev/null
+++ b/arch/arm/mach-litesom/include/mach/litesom.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2016 Grinn
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_LITESOM_SOM_H__
+#define __ARCH_ARM_MACH_LITESOM_SOM_H__
+
+int litesom_mmc_init(bd_t *bis);
+
+#ifdef CONFIG_SPL_BUILD
+void litesom_init_f(void);
+#endif
+
+#endif
diff --git a/arch/arm/mach-litesom/litesom.c b/arch/arm/mach-litesom/litesom.c
new file mode 100644
index 0000000..ac2eccf
--- /dev/null
+++ b/arch/arm/mach-litesom/litesom.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const emmc_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* RST_B */
+ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
+
+#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
+
+int litesom_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* eMMC */
+ imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads));
+ gpio_direction_output(EMMC_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(EMMC_PWR_GPIO, 1);
+ emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ ret = fsl_esdhc_initialize(bis, &emmc_cfg);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev 1 (eMMC)\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x41570155,
+ .p0_mprddlctl = 0x4040474A,
+ .p0_mpwrdlctl = 0x40405550,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 0, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+ .refsel = 0, /* Refresh cycles at 64KHz */
+ .refr = 1, /* 2 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ unsigned long ram_size;
+
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+
+ /*
+ * Get actual RAM size, so we can adjust DDR row size for <512M
+ * memories
+ */
+ ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
+ if (ram_size < SZ_512M) {
+ mem_ddr.rowaddr = 14;
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ }
+}
+
+void litesom_init_f(void)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+ board_early_init_f();
+#endif
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
+#endif
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
index 1dd53e2..f159cbf 100644
--- a/arch/arm/mach-meson/board.c
+++ b/arch/arm/mach-meson/board.c
@@ -43,7 +43,7 @@
void reset_cpu(ulong addr)
{
- psci_system_reset(true);
+ psci_system_reset();
}
static struct mm_region gxbb_mem_map[] = {
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 220886a..40476dc 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,14 +1,48 @@
if ARCH_MVEBU
+config ARMADA_32BIT
+ bool
+ select CPU_V7
+ select SUPPORT_SPL
+ select SPL_DM
+ select SPL_DM_SEQ_ALIAS
+ select SPL_OF_CONTROL
+ select SPL_SIMPLE_BUS
+
+config ARMADA_64BIT
+ bool
+ select ARM64
+
+# ARMv7 SoCs...
config ARMADA_375
bool
+ select ARMADA_32BIT
config ARMADA_38X
bool
+ select ARMADA_32BIT
config ARMADA_XP
bool
+ select ARMADA_32BIT
+# ARMv8 SoCs...
+config ARMADA_3700
+ bool
+ select ARM64
+
+# Armada 7K and 8K are very similar - use only one Kconfig symbol for both
+config ARMADA_8K
+ bool
+ select ARM64
+
+# Armada PLL frequency (used for NAND clock generation)
+config SYS_MVEBU_PLL_CLOCK
+ int
+ default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
+ default "1000000000" if ARMADA_38X || ARMADA_375
+
+# Armada XP/38x SoC types...
config MV78230
bool
select ARMADA_XP
@@ -21,17 +55,21 @@
bool
select ARMADA_XP
-config DB_88F6820_GP
+config 88F6820
bool
select ARMADA_38X
choice
- prompt "Marvell MVEBU (Armada XP/375/38x) board select"
+ prompt "Armada XP/375/38x/3700/7K/8K board select"
optional
config TARGET_CLEARFOG
bool "Support ClearFog"
- select DB_88F6820_GP
+ select 88F6820
+
+config TARGET_MVEBU_DB_88F3720
+ bool "Support DB-88F3720 Armada 3720"
+ select ARMADA_3700
config TARGET_DB_88F6720
bool "Support DB-88F6720 Armada 375"
@@ -39,7 +77,15 @@
config TARGET_DB_88F6820_GP
bool "Support DB-88F6820-GP"
- select DB_88F6820_GP
+ select 88F6820
+
+config TARGET_DB_88F6820_AMC
+ bool "Support DB-88F6820-AMC"
+ select 88F6820
+
+config TARGET_MVEBU_ARMADA_8K
+ bool "Support Armada 7k/8k platforms"
+ select ARMADA_8K
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
@@ -61,8 +107,11 @@
config SYS_BOARD
default "clearfog" if TARGET_CLEARFOG
+ default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+ default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
+ default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
@@ -70,8 +119,11 @@
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
+ default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+ default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
+ default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
@@ -79,8 +131,11 @@
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
+ default "Marvell" if TARGET_MVEBU_DB_88F3720
default "Marvell" if TARGET_DB_88F6720
default "Marvell" if TARGET_DB_88F6820_GP
+ default "Marvell" if TARGET_DB_88F6820_AMC
+ default "Marvell" if TARGET_MVEBU_ARMADA_8K
default "solidrun" if TARGET_CLEARFOG
default "Synology" if TARGET_DS414
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index ac009a3..65e90c4 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,16 +1,25 @@
#
-# Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+# Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_ARM64
+
+obj-$(CONFIG_ARMADA_3700) += armada3700/
+obj-$(CONFIG_ARMADA_8K) += armada8k/
+obj-y += arm64-common.o
+obj-y += sata.o
+
+else # CONFIG_ARM64
+
ifdef CONFIG_KIRKWOOD
obj-y = dram.o
obj-y += gpio.o
obj-y += timer.o
-else
+else # CONFIG_KIRKWOOD
obj-y = cpu.o
obj-y += dram.o
@@ -18,7 +27,7 @@
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
-endif
+endif # CONFIG_SPL_BUILD
obj-y += gpio.o
obj-y += mbus.o
obj-y += timer.o
@@ -28,4 +37,5 @@
obj-$(CONFIG_ARMADA_38X) += serdes/a38x/
obj-$(CONFIG_ARMADA_XP) += serdes/axp/
-endif
+endif # CONFIG_KIRKWOOD
+endif # CONFIG_ARM64
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
new file mode 100644
index 0000000..8f02655
--- /dev/null
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Not all memory is mapped in the MMU. So we need to restrict the
+ * memory size so that U-Boot does not try to access it. Also, the
+ * internal registers are located at 0xf000.0000 - 0xffff.ffff.
+ * Currently only 2GiB are mapped for system memory. This is what
+ * we pass to the U-Boot subsystem here.
+ */
+#define USABLE_RAM_SIZE 0x80000000
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ if (gd->ram_size > USABLE_RAM_SIZE)
+ return USABLE_RAM_SIZE;
+
+ return gd->ram_size;
+}
+
+/*
+ * On ARMv8, MBus is not configured in U-Boot. To enable compilation
+ * of the already implemented drivers, lets add a dummy version of
+ * this function so that linking does not fail.
+ */
+const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
+{
+ return NULL;
+}
+
+/* DRAM init code ... */
+
+static const void *get_memory_reg_prop(const void *fdt, int *lenp)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/memory");
+ if (offset < 0)
+ return NULL;
+
+ return fdt_getprop(fdt, offset, "reg", lenp);
+}
+
+int dram_init(void)
+{
+ const void *fdt = gd->fdt_blob;
+ const fdt32_t *val;
+ int ac, sc, len;
+
+ ac = fdt_address_cells(fdt, 0);
+ sc = fdt_size_cells(fdt, 0);
+ if (ac < 0 || sc < 1 || sc > 2) {
+ printf("invalid address/size cells\n");
+ return -EINVAL;
+ }
+
+ val = get_memory_reg_prop(fdt, &len);
+ if (len / sizeof(*val) < ac + sc)
+ return -EINVAL;
+
+ val += ac;
+
+ gd->ram_size = fdtdec_get_number(val, sc);
+
+ debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ const void *fdt = gd->fdt_blob;
+ const fdt32_t *val;
+ int ac, sc, cells, len, i;
+
+ val = get_memory_reg_prop(fdt, &len);
+ if (len < 0)
+ return;
+
+ ac = fdt_address_cells(fdt, 0);
+ sc = fdt_size_cells(fdt, 0);
+ if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
+ printf("invalid address/size cells\n");
+ return;
+ }
+
+ cells = ac + sc;
+
+ len /= sizeof(*val);
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells;
+ i++, len -= cells) {
+ gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac);
+ val += ac;
+ gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc);
+ val += sc;
+
+ debug("DRAM bank %d: start = %08lx, size = %08lx\n",
+ i, (unsigned long)gd->bd->bi_dram[i].start,
+ (unsigned long)gd->bd->bi_dram[i].size);
+ }
+}
+
+int arch_cpu_init(void)
+{
+ /* Nothing to do (yet) */
+ return 0;
+}
+
+int arch_early_init_r(void)
+{
+ struct udevice *dev;
+ int ret;
+ int i;
+
+ /*
+ * Loop over all MISC uclass drivers to call the comphy code
+ * and init all CP110 devices enabled in the DT
+ */
+ i = 0;
+ while (1) {
+ /* Call the comphy code via the MISC uclass driver */
+ ret = uclass_get_device(UCLASS_MISC, i++, &dev);
+
+ /* We're done, once no further CP110 device is found */
+ if (ret)
+ break;
+ }
+
+ /* Cause the SATA device to do its early init */
+ uclass_first_device(UCLASS_AHCI, &dev);
+
+ return 0;
+}
diff --git a/arch/arm/mach-mvebu/armada3700/Makefile b/arch/arm/mach-mvebu/armada3700/Makefile
new file mode 100644
index 0000000..84c69d9
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada3700/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpu.o
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c
new file mode 100644
index 0000000..6499eec
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Armada 3700 */
+#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
+
+#define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
+#define MVEBU_XTAL_MODE_MASK BIT(9)
+#define MVEBU_XTAL_MODE_OFFS 9
+#define MVEBU_XTAL_CLOCK_25MHZ 0x0
+#define MVEBU_XTAL_CLOCK_40MHZ 0x1
+
+#define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
+#define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
+
+static struct mm_region mvebu_mem_map[] = {
+ {
+ /* RAM */
+ .phys = 0x0UL,
+ .virt = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SRAM, MMIO regions */
+ .phys = 0xd0000000UL,
+ .virt = 0xd0000000UL,
+ .size = 0x02000000UL, /* 32MiB internal registers */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mvebu_mem_map;
+
+void reset_cpu(ulong ignored)
+{
+ /*
+ * Write magic number of 0x1d1e to North Bridge Warm Reset register
+ * to trigger warm reset
+ */
+ writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
+}
+
+/*
+ * get_ref_clk
+ *
+ * return: reference clock in MHz (25 or 40)
+ */
+u32 get_ref_clk(void)
+{
+ u32 regval;
+
+ regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
+ MVEBU_XTAL_MODE_OFFS;
+
+ if (regval == MVEBU_XTAL_CLOCK_25MHZ)
+ return 25;
+ else
+ return 40;
+}
diff --git a/arch/arm/mach-mvebu/armada8k/Makefile b/arch/arm/mach-mvebu/armada8k/Makefile
new file mode 100644
index 0000000..0facf14
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada8k/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpu.o
+obj-y += cache_llc.o
diff --git a/arch/arm/mach-mvebu/armada8k/cache_llc.S b/arch/arm/mach-mvebu/armada8k/cache_llc.S
new file mode 100644
index 0000000..71aecb2
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada8k/cache_llc.S
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include <asm/arch-armada8k/cache_llc.h>
+#include <linux/linkage.h>
+
+/*
+ * int __asm_flush_l3_dcache
+ *
+ * flush Armada-8K last level cache.
+ *
+ */
+ENTRY(__asm_flush_l3_dcache)
+ /* flush cache */
+ mov x0, #LLC_BASE_ADDR
+ add x0, x0, #LLC_FLUSH_BY_WAY
+ movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
+ mov w1, #LLC_WAY_MASK
+ str w1, [x0]
+ /* sync cache */
+ mov x0, #LLC_BASE_ADDR
+ add x0, x0, #LLC_CACHE_SYNC
+ movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
+ str wzr, [x0]
+ /* check that cache sync completed */
+ mov x0, #LLC_BASE_ADDR
+ add x0, x0, #LLC_CACHE_SYNC_COMPLETE
+ movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
+1: ldr w1, [x0]
+ and w1, w1, #LLC_CACHE_SYNC_MASK
+ cbnz w1, 1b
+ /* return success */
+ mov x0, #0
+ ret
+ENDPROC(__asm_flush_l3_dcache)
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
new file mode 100644
index 0000000..2325e9a
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Armada 7k/8k */
+#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
+#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
+#define RFU_SW_RESET_OFFSET 0
+
+/*
+ * The following table includes all memory regions for Armada 7k and
+ * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
+ * define these regions at the beginning of the struct so that they
+ * can be easier removed later dynamically if an Armada 7k device is detected.
+ * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
+ */
+#define ARMADA_7K8K_COMMON_REGIONS_START 2
+static struct mm_region mvebu_mem_map[] = {
+ /* Armada 80x0 memory regions include the CP1 (slave) units */
+ {
+ /* SRAM, MMIO regions - CP110 slave region */
+ .phys = 0xf4000000UL,
+ .virt = 0xf4000000UL,
+ .size = 0x02000000UL, /* 32MiB internal registers */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ {
+ /* PCI CP1 regions */
+ .phys = 0xfa000000UL,
+ .virt = 0xfa000000UL,
+ .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ /* Armada 80x0 and 70x0 common memory regions start here */
+ {
+ /* RAM */
+ .phys = 0x0UL,
+ .virt = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SRAM, MMIO regions - AP806 region */
+ .phys = 0xf0000000UL,
+ .virt = 0xf0000000UL,
+ .size = 0x01000000UL, /* 16MiB internal registers */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ {
+ /* SRAM, MMIO regions - CP110 master region */
+ .phys = 0xf2000000UL,
+ .virt = 0xf2000000UL,
+ .size = 0x02000000UL, /* 32MiB internal registers */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ {
+ /* PCI CP0 regions */
+ .phys = 0xf6000000UL,
+ .virt = 0xf6000000UL,
+ .size = 0x04000000UL, /* 64MiB CP110 master PCI space */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mvebu_mem_map;
+
+void enable_caches(void)
+{
+ /*
+ * Armada 7k is not equipped with the CP110 slave CP. In case this
+ * code runs on an Armada 7k device, lets remove the CP110 slave
+ * entries from the memory mapping by moving the start to the
+ * common regions.
+ */
+ if (of_machine_is_compatible("marvell,armada7040"))
+ mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
+
+ icache_enable();
+ dcache_enable();
+}
+
+void reset_cpu(ulong ignored)
+{
+ u32 reg;
+
+ reg = readl(RFU_GLOBAL_SW_RST);
+ reg &= ~(1 << RFU_SW_RESET_OFFSET);
+ writel(reg, RFU_GLOBAL_SW_RST);
+}
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 5eb2a39..1445731 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -475,7 +475,7 @@
}
#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_MV_SDHCI
+#ifdef CONFIG_MMC_SDHCI_MV
int board_mmc_init(bd_t *bis)
{
mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index cbec876..66f7680 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -166,5 +166,12 @@
int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
+/*
+ * get_ref_clk
+ *
+ * return: reference clock in MHz (25 or 40)
+ */
+u32 get_ref_clk(void);
+
#endif /* __ASSEMBLY__ */
#endif /* _MVEBU_CPU_H */
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 6342cdc..0f69f33 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -31,13 +31,10 @@
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#endif
-/* Armada XP PLL frequency (used for NAND clock generation) */
-#define CONFIG_SYS_MVEBU_PLL_CLOCK 2000000000
-
/* SOC specific definations */
#define INTREG_BASE 0xd0000000
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700)
/*
* The SPL U-Boot version still runs with the default
* address for the internal registers, configured by
@@ -46,6 +43,8 @@
* required for the Linux kernel.
*/
#define SOC_REGS_PHY_BASE 0xd0000000
+#elif defined(CONFIG_ARMADA_8K)
+#define SOC_REGS_PHY_BASE 0xf0000000
#else
#define SOC_REGS_PHY_BASE 0xf1000000
#endif
diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c
index df263bc..c4128cd 100644
--- a/arch/arm/mach-mvebu/mbus.c
+++ b/arch/arm/mach-mvebu/mbus.c
@@ -48,7 +48,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
diff --git a/arch/arm/mach-mvebu/sata.c b/arch/arm/mach-mvebu/sata.c
new file mode 100644
index 0000000..140a295
--- /dev/null
+++ b/arch/arm/mach-mvebu/sata.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Dummy implementation that can be overwritten by a board
+ * specific function
+ */
+__weak int board_ahci_enable(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_ARMADA_8K
+/* CP110 has different AHCI port addresses */
+void __iomem *ahci_port_base(void __iomem *base, u32 port)
+{
+ return base + 0x10000 + (port * 0x10000);
+}
+#endif
+
+static int mvebu_ahci_probe(struct udevice *dev)
+{
+ /*
+ * Board specific SATA / AHCI enable code, e.g. enable the
+ * AHCI power or deassert reset
+ */
+ board_ahci_enable();
+
+ ahci_init(dev_get_addr_ptr(dev));
+
+ return 0;
+}
+
+static const struct udevice_id mvebu_ahci_ids[] = {
+ { .compatible = "marvell,armada-3700-ahci" },
+ { .compatible = "marvell,armada-8k-ahci" },
+ { }
+};
+
+U_BOOT_DRIVER(ahci_mvebu_drv) = {
+ .name = "ahci_mvebu",
+ .id = UCLASS_AHCI,
+ .of_match = mvebu_ahci_ids,
+ .probe = mvebu_ahci_probe,
+};
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
index 49d704a..cc3e5e2 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
@@ -45,7 +45,7 @@
u32 mv_board_id_get(void)
{
-#if defined(CONFIG_DB_88F6820_GP)
+#if defined(CONFIG_TARGET_DB_88F6820_GP)
return DB_GP_68XX_ID;
#else
/*
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
new file mode 100644
index 0000000..24bc485
--- /dev/null
+++ b/arch/arm/mach-omap2/Kconfig
@@ -0,0 +1,17 @@
+config TI_SECURE_DEVICE
+ bool "HS Device Type Support"
+ depends on OMAP54XX || AM43XX || AM33XX
+ help
+ If a high secure (HS) device type is being used, this config
+ must be set. This option impacts various aspects of the
+ build system (to create signed boot images that can be
+ authenticated) and the code. See the doc/README.ti-secure
+ file for further details.
+
+source "arch/arm/mach-omap2/omap3/Kconfig"
+
+source "arch/arm/mach-omap2/omap4/Kconfig"
+
+source "arch/arm/mach-omap2/omap5/Kconfig"
+
+source "arch/arm/mach-omap2/am33xx/Kconfig"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
new file mode 100644
index 0000000..e814eb0
--- /dev/null
+++ b/arch/arm/mach-omap2/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
+obj-$(CONFIG_OMAP34XX) += omap3/
+obj-$(CONFIG_OMAP44XX) += omap4/
+obj-$(CONFIG_OMAP54XX) += omap5/
+
+obj-y += reset.o
+ifeq ($(CONFIG_TIMER),)
+obj-y += timer.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += timer.o
+endif
+endif
+obj-y += utils.o
+
+ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+obj-y += hwinit-common.o
+obj-y += clocks-common.o
+obj-y += emif-common.o
+obj-y += vc.o
+obj-y += abb.o
+endif
+
+ifneq ($(CONFIG_OMAP54XX),)
+obj-y += pipe3-phy.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
+endif
+
+ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+obj-y += omap-cache.o
+endif
+
+obj-y += boot-common.o
+obj-y += lowlevel_init.o
+
+obj-y += mem-common.o
+
+obj-$(CONFIG_TI_SECURE_DEVICE) += sec-common.o
diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/mach-omap2/abb.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/abb.c
rename to arch/arm/mach-omap2/abb.c
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
new file mode 100644
index 0000000..56c4406
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -0,0 +1,138 @@
+if AM33XX
+
+choice
+ prompt "AM33xx board select"
+ optional
+
+config TARGET_AM335X_EVM
+ bool "Support am335x_evm"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+ select TI_I2C_BOARD_DETECT
+ help
+ This option specifies support for the AM335x
+ GP and HS EVM development platforms. The AM335x
+ GP EVM is a standalone test, development, and
+ evaluation module system that enables developers
+ to write software and develop hardware around
+ an AM335x processor subsystem.
+
+config TARGET_AM335X_BALTOS
+ bool "Support am335x_baltos"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_AM335X_IGEP0033
+ bool "Support am335x_igep0033"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_AM335X_SHC
+ bool "Support am335x based shc board from bosch"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_AM335X_SL50
+ bool "Support am335x_sl50"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_BAV335X
+ bool "Support bav335x"
+ select DM
+ select DM_SERIAL
+ help
+ The BAV335x OEM Network Processor integrates all the functions of an
+ embedded network computer in a small, easy to use SODIMM module which
+ incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
+ processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
+ ethernet with simple connection to external connectors.
+
+ For more information, visit: http://birdland.com/oem
+
+config TARGET_CM_T335
+ bool "Support cm_t335"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_PCM051
+ bool "Support pcm051"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_PENGWYN
+ bool "Support pengwyn"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_PEPPER
+ bool "Support pepper"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+endchoice
+
+endif
+
+if AM43XX
+
+config SPL_EXT_SUPPORT
+ default y
+
+config SPL_GPIO_SUPPORT
+ default y
+
+config SPL_I2C_SUPPORT
+ default y
+
+config TARGET_AM43XX_EVM
+ bool "Support am43xx_evm"
+ select TI_I2C_BOARD_DETECT
+ help
+ This option specifies support for the AM43xx
+ GP and HS EVM development platforms.The AM437x
+ GP EVM is a standalone test, development, and
+ evaluation module system that enables developers
+ to write software and develop hardware around
+ an AM43xx processor subsystem.
+endif
+
+if AM43XX || AM33XX
+config ISW_ENTRY_ADDR
+ hex "Address in memory or XIP flash of bootloader entry point"
+ help
+ After any reset, the boot ROM on the AM43XX SOC
+ searches the boot media for a valid boot image.
+ For non-XIP devices, the ROM then copies the
+ image into internal memory.
+ For all boot modes, after the ROM processes the
+ boot image it eventually computes the entry
+ point address depending on the device type
+ (secure/non-secure), boot media (xip/non-xip) and
+ image headers.
+ default 0x402F4000 if AM43XX
+ default 0x402F0400 if AM33XX
+
+config PUB_ROM_DATA_SIZE
+ hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+ help
+ During the device boot, the public ROM uses the top of
+ the public L3 OCMC RAM to store r/w data like stack,
+ heap, globals etc. When the ROM is copying the boot
+ image from the boot media into memory, the image must
+ not spill over into this area. This value can be used
+ during compile time to determine the maximum size of a
+ boot image. Once the ROM transfers control to the boot
+ image, this area is no longer used, and can be reclaimed
+ for run time use by the boot image.
+ default 0x8400
+endif
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
similarity index 100%
rename from arch/arm/cpu/armv7/am33xx/Makefile
rename to arch/arm/mach-omap2/am33xx/Makefile
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
new file mode 100644
index 0000000..581c0ab
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -0,0 +1,327 @@
+/*
+ * board.c
+ *
+ * Common board functions for AM33XX based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <ns16550.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <linux/errno.h>
+#include <linux/compiler.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/davinci_rtc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct ns16550_platdata am33xx_serial[] = {
+ { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+# ifdef CONFIG_SYS_NS16550_COM2
+ { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+# ifdef CONFIG_SYS_NS16550_COM3
+ { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+ { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+ { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+ { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+# endif
+# endif
+};
+
+U_BOOT_DEVICES(am33xx_uarts) = {
+ { "ns16550_serial", &am33xx_serial[0] },
+# ifdef CONFIG_SYS_NS16550_COM2
+ { "ns16550_serial", &am33xx_serial[1] },
+# ifdef CONFIG_SYS_NS16550_COM3
+ { "ns16550_serial", &am33xx_serial[2] },
+ { "ns16550_serial", &am33xx_serial[3] },
+ { "ns16550_serial", &am33xx_serial[4] },
+ { "ns16550_serial", &am33xx_serial[5] },
+# endif
+# endif
+};
+
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+ { 0, AM33XX_GPIO0_BASE },
+ { 1, AM33XX_GPIO1_BASE },
+ { 2, AM33XX_GPIO2_BASE },
+ { 3, AM33XX_GPIO3_BASE },
+#ifdef CONFIG_AM43XX
+ { 4, AM33XX_GPIO4_BASE },
+ { 5, AM33XX_GPIO5_BASE },
+#endif
+};
+
+U_BOOT_DEVICES(am33xx_gpios) = {
+ { "gpio_omap", &am33xx_gpio[0] },
+ { "gpio_omap", &am33xx_gpio[1] },
+ { "gpio_omap", &am33xx_gpio[2] },
+ { "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+ { "gpio_omap", &am33xx_gpio[4] },
+ { "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+#endif
+#endif
+
+#ifndef CONFIG_DM_GPIO
+static const struct gpio_bank gpio_bank_am33xx[] = {
+ { (void *)AM33XX_GPIO0_BASE },
+ { (void *)AM33XX_GPIO1_BASE },
+ { (void *)AM33XX_GPIO2_BASE },
+ { (void *)AM33XX_GPIO3_BASE },
+#ifdef CONFIG_AM43XX
+ { (void *)AM33XX_GPIO4_BASE },
+ { (void *)AM33XX_GPIO5_BASE },
+#endif
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+#endif
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int cpu_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ ret = omap_mmc_init(0, 0, 0, -1, -1);
+ if (ret)
+ return ret;
+
+ return omap_mmc_init(1, 0, 0, -1, -1);
+}
+#endif
+
+/* AM33XX has two MUSB controllers which can be host or gadget */
+#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
+ (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
+ (!defined(CONFIG_DM_USB))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN (1 << 0)
+#define CM_PHY_OTG_PWRDN (1 << 1)
+#define OTGVDET_EN (1 << 19)
+#define OTGSESSENDEN (1 << 20)
+
+static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
+{
+ if (on) {
+ clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+ OTGVDET_EN | OTGSESSENDEN);
+ } else {
+ clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+ }
+}
+
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+#ifdef CONFIG_AM335X_USB0
+static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
+{
+ am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
+}
+
+struct omap_musb_board_data otg0_board_data = {
+ .set_phy_power = am33xx_otg0_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg0_plat = {
+ .mode = CONFIG_AM335X_USB0_MODE,
+ .config = &musb_config,
+ .power = 50,
+ .platform_ops = &musb_dsps_ops,
+ .board_data = &otg0_board_data,
+};
+#endif
+
+#ifdef CONFIG_AM335X_USB1
+static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
+{
+ am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
+}
+
+struct omap_musb_board_data otg1_board_data = {
+ .set_phy_power = am33xx_otg1_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg1_plat = {
+ .mode = CONFIG_AM335X_USB1_MODE,
+ .config = &musb_config,
+ .power = 50,
+ .platform_ops = &musb_dsps_ops,
+ .board_data = &otg1_board_data,
+};
+#endif
+#endif
+
+int arch_misc_init(void)
+{
+#ifndef CONFIG_DM_USB
+#ifdef CONFIG_AM335X_USB0
+ musb_register(&otg0_plat, &otg0_board_data,
+ (void *)USB0_OTG_BASE);
+#endif
+#ifdef CONFIG_AM335X_USB1
+ musb_register(&otg1_plat, &otg1_board_data,
+ (void *)USB1_OTG_BASE);
+#endif
+#else
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_MISC, &dev);
+ if (ret || !dev)
+ return ret;
+#endif
+ return 0;
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * In the case of non-SPL based booting we'll want to call these
+ * functions a tiny bit later as it will require gd to be set and cleared
+ * and that's not true in s_init in this case so we cannot do it there.
+ */
+int board_early_init_f(void)
+{
+ prcm_init();
+ set_mux_conf_regs();
+
+ return 0;
+}
+
+/*
+ * This function is the place to do per-board things such as ramp up the
+ * MPU clock frequency.
+ */
+__weak void am33xx_spl_board_init(void)
+{
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+static void rtc32k_enable(void)
+{
+ struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
+
+ /*
+ * Unlock the RTC's registers. For more details please see the
+ * RTC_SS section of the TRM. In order to unlock we need to
+ * write these specific values (keys) in this order.
+ */
+ writel(RTC_KICK0R_WE, &rtc->kick0r);
+ writel(RTC_KICK1R_WE, &rtc->kick1r);
+
+ /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+ writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+#endif
+
+static void uart_soft_reset(void)
+{
+ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+ u32 regval;
+
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_RESET;
+ writel(regval, &uart_base->uartsyscfg);
+ while ((readl(&uart_base->uartsyssts) &
+ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+ ;
+
+ /* Disable smart idle */
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_SMART_IDLE_EN;
+ writel(regval, &uart_base->uartsyscfg);
+}
+
+static void watchdog_disable(void)
+{
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ writel(0xAAAA, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+}
+
+void s_init(void)
+{
+}
+
+void early_system_init(void)
+{
+ /*
+ * The ROM will only have set up sufficient pinmux to allow for the
+ * first 4KiB NOR to be read, we must finish doing what we know of
+ * the NOR mux in this space in order to continue.
+ */
+#ifdef CONFIG_NOR_BOOT
+ enable_norboot_pin_mux();
+#endif
+ watchdog_disable();
+ set_uart_mux_conf();
+ setup_early_clocks();
+ uart_soft_reset();
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+ do_board_detect();
+#endif
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+ /* Enable RTC32K clock */
+ rtc32k_enable();
+#endif
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ early_system_init();
+ board_early_init_f();
+ sdram_init();
+}
+#endif
+
+#endif
+
+int arch_cpu_init_dm(void)
+{
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ early_system_init();
+#endif
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c
similarity index 100%
rename from arch/arm/cpu/armv7/am33xx/clk_synthesizer.c
rename to arch/arm/mach-omap2/am33xx/clk_synthesizer.c
diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c
new file mode 100644
index 0000000..3d17698
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx/clock.c
@@ -0,0 +1,246 @@
+/*
+ * clock.c
+ *
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
+{
+ /* Setup post-dividers */
+ if (params->m2 >= 0)
+ writel(params->m2, dpll_regs->cm_div_m2_dpll);
+ if (params->m3 >= 0)
+ writel(params->m3, dpll_regs->cm_div_m3_dpll);
+ if (params->m4 >= 0)
+ writel(params->m4, dpll_regs->cm_div_m4_dpll);
+ if (params->m5 >= 0)
+ writel(params->m5, dpll_regs->cm_div_m5_dpll);
+ if (params->m6 >= 0)
+ writel(params->m6, dpll_regs->cm_div_m6_dpll);
+}
+
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
+{
+ clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
+{
+ if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+ (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+ printf("DPLL locking failed for 0x%x\n",
+ dpll_regs->cm_clkmode_dpll);
+ hang();
+ }
+}
+
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+ clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
+{
+ if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+ (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+ printf("Bypassing DPLL failed 0x%x\n",
+ dpll_regs->cm_clkmode_dpll);
+ }
+}
+
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+ do_bypass_dpll(dpll_regs);
+ wait_for_bypass(dpll_regs);
+}
+
+void do_setup_dpll(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
+{
+ u32 temp;
+
+ if (!params)
+ return;
+
+ temp = readl(dpll_regs->cm_clksel_dpll);
+
+ bypass_dpll(dpll_regs);
+
+ /* Set M & N */
+ temp &= ~CM_CLKSEL_DPLL_M_MASK;
+ temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+ temp &= ~CM_CLKSEL_DPLL_N_MASK;
+ temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+ writel(temp, dpll_regs->cm_clksel_dpll);
+
+ setup_post_dividers(dpll_regs, params);
+
+ /* Wait till the DPLL locks */
+ do_lock_dpll(dpll_regs);
+ wait_for_lock(dpll_regs);
+}
+
+static void setup_dplls(void)
+{
+ const struct dpll_params *params;
+
+ params = get_dpll_core_params();
+ do_setup_dpll(&dpll_core_regs, params);
+
+ params = get_dpll_mpu_params();
+ do_setup_dpll(&dpll_mpu_regs, params);
+
+ params = get_dpll_per_params();
+ do_setup_dpll(&dpll_per_regs, params);
+ writel(0x300, &cmwkup->clkdcoldodpllper);
+
+ params = get_dpll_ddr_params();
+ do_setup_dpll(&dpll_ddr_regs, params);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+ u32 bound = LDELAY;
+
+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+ MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf("Clock enable failed for 0x%p idlest 0x%x\n",
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+ u32 wait_for_enable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug("Enable clock module - %p\n", clkctrl_addr);
+ if (wait_for_enable)
+ wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void wait_for_clk_disable(u32 *clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+ u32 bound = LDELAY;
+
+ while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+ MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf("Clock disable failed for 0x%p idlest 0x%x\n",
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
+static inline void disable_clock_module(u32 *const clkctrl_addr,
+ u32 wait_for_disable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug("Disable clock module - %p\n", clkctrl_addr);
+ if (wait_for_disable)
+ wait_for_clk_disable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug("Enable clock domain - %p\n", clkctrl_reg);
+}
+
+static inline void disable_clock_domain(u32 *const clkctrl_reg)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug("Disable clock domain - %p\n", clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+ u32 i, max = 100;
+
+ /* Put the clock domains in SW_WKUP mode */
+ for (i = 0; (i < max) && clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ }
+
+ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+ for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+ enable_clock_module(clk_modules_explicit_en[i],
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+ wait_for_enable);
+ };
+}
+
+void do_disable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_disable,
+ u8 wait_for_disable)
+{
+ u32 i, max = 100;
+
+
+ /* Clock modules that need to be put in SW_DISABLE */
+ for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+ disable_clock_module(clk_modules_disable[i],
+ wait_for_disable);
+
+ /* Put the clock domains in SW_SLEEP mode */
+ for (i = 0; (i < max) && clk_domains[i]; i++)
+ disable_clock_domain(clk_domains[i]);
+}
+
+/*
+ * Before scaling up the clocks we need to have the PMIC scale up the
+ * voltages first. This will be dependent on which PMIC is in use
+ * and in some cases we may not be scaling things up at all and thus not
+ * need to do anything here.
+ */
+__weak void scale_vcores(void)
+{
+}
+
+void setup_early_clocks(void)
+{
+ setup_clocks_for_console();
+ enable_basic_clocks();
+ timer_init();
+}
+
+void prcm_init(void)
+{
+ scale_vcores();
+ setup_dplls();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
similarity index 100%
rename from arch/arm/cpu/armv7/am33xx/clock_am33xx.c
rename to arch/arm/mach-omap2/am33xx/clock_am33xx.c
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c
similarity index 100%
rename from arch/arm/cpu/armv7/am33xx/clock_am43xx.c
rename to arch/arm/mach-omap2/am33xx/clock_am43xx.c
diff --git a/arch/arm/mach-omap2/am33xx/clock_ti814x.c b/arch/arm/mach-omap2/am33xx/clock_ti814x.c
new file mode 100644
index 0000000..50bd631
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx/clock_ti814x.c
@@ -0,0 +1,410 @@
+/*
+ * clock_ti814x.c
+ *
+ * Clocks for TI814X based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/* PRCM */
+#define PRCM_MOD_EN 0x2
+
+/* CLK_SRC */
+#define OSC_SRC0 0
+#define OSC_SRC1 1
+
+#define L3_OSC_SRC OSC_SRC0
+
+#define OSC_0_FREQ 20
+
+#define DCO_HS2_MIN 500
+#define DCO_HS2_MAX 1000
+#define DCO_HS1_MIN 1000
+#define DCO_HS1_MAX 2000
+
+#define SELFREQDCO_HS2 0x00000801
+#define SELFREQDCO_HS1 0x00001001
+
+#define MPU_N 0x1
+#define MPU_M 0x3C
+#define MPU_M2 1
+#define MPU_CLKCTRL 0x1
+
+#define L3_N 19
+#define L3_M 880
+#define L3_M2 4
+#define L3_CLKCTRL 0x801
+
+#define DDR_N 19
+#define DDR_M 666
+#define DDR_M2 2
+#define DDR_CLKCTRL 0x801
+
+/* ADPLLJ register values */
+#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
+#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
+#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
+#define ADPLLJ_CLKCTRL_IDLE (1 << 23)
+#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
+#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
+#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
+#define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
+#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
+#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
+#define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
+#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
+ ADPLLJ_CLKCTRL_CLKOUTEN | \
+ ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
+ ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
+
+#define ADPLLJ_STATUS_PHASELOCK (1 << 10)
+#define ADPLLJ_STATUS_FREQLOCK (1 << 9)
+#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
+ ADPLLJ_STATUS_FREQLOCK)
+#define ADPLLJ_STATUS_BYPASSACK (1 << 8)
+#define ADPLLJ_STATUS_BYPASS (1 << 0)
+#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
+ ADPLLJ_STATUS_BYPASS)
+
+#define ADPLLJ_TENABLE_ENB (1 << 0)
+#define ADPLLJ_TENABLEDIV_ENB (1 << 0)
+
+#define ADPLLJ_M2NDIV_M2SHIFT 16
+
+#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
+#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
+#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
+
+struct ad_pll {
+ unsigned int pwrctrl;
+ unsigned int clkctrl;
+ unsigned int tenable;
+ unsigned int tenablediv;
+ unsigned int m2ndiv;
+ unsigned int mn2div;
+ unsigned int fracdiv;
+ unsigned int bwctrl;
+ unsigned int fracctrl;
+ unsigned int status;
+ unsigned int m3div;
+ unsigned int rampctrl;
+};
+
+#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
+
+#define ENET_CLKCTRL_CMPL 0x30000
+
+#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
+
+struct sata_pll {
+ unsigned int pllcfg0;
+ unsigned int pllcfg1;
+ unsigned int pllcfg2;
+ unsigned int pllcfg3;
+ unsigned int pllcfg4;
+ unsigned int pllstatus;
+ unsigned int rxstatus;
+ unsigned int txstatus;
+ unsigned int testcfg;
+};
+
+#define SEL_IN_FREQ (0x1 << 31)
+#define DIGCLRZ (0x1 << 30)
+#define ENDIGLDO (0x1 << 4)
+#define APLL_CP_CURR (0x1 << 3)
+#define ENBGSC_REF (0x1 << 2)
+#define ENPLLLDO (0x1 << 1)
+#define ENPLL (0x1 << 0)
+
+#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
+#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
+#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
+#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
+ ENPLLLDO | ENPLL)
+
+#define PLL_LOCK (0x1 << 0)
+
+#define ENSATAMODE (0x1 << 31)
+#define PLLREFSEL (0x1 << 30)
+#define MDIVINT (0x4b << 18)
+#define EN_CLKAUX (0x1 << 5)
+#define EN_CLK125M (0x1 << 4)
+#define EN_CLK100M (0x1 << 3)
+#define EN_CLK50M (0x1 << 2)
+
+#define SATA_PLLCFG1 (ENSATAMODE | \
+ PLLREFSEL | \
+ MDIVINT | \
+ EN_CLKAUX | \
+ EN_CLK125M | \
+ EN_CLK100M | \
+ EN_CLK50M)
+
+#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
+#define PLLDO_EN_LDO_STABLE (0x1 << 11)
+#define PLLDO_EN_BUF_CUR (0x1 << 7)
+#define PLLDO_EN_LP (0x1 << 6)
+#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
+
+#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
+ PLLDO_EN_LDO_STABLE | \
+ PLLDO_EN_BUF_CUR | \
+ PLLDO_EN_LP | \
+ PLLDO_CTRL_TRIM_1_4V)
+
+const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
+const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
+
+/*
+ * Enable the peripheral clock for required peripherals
+ */
+static void enable_per_clocks(void)
+{
+ /* HSMMC1 */
+ writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
+ while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* Ethernet */
+ writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+ writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+ while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+ ;
+ writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+ while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+ ;
+
+ /* RTC clocks */
+ writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
+ writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
+ while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
+ ;
+}
+
+/*
+ * select the HS1 or HS2 for DCO Freq
+ * return : CLKCTRL
+ */
+static u32 pll_dco_freq_sel(u32 clkout_dco)
+{
+ if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
+ return SELFREQDCO_HS2;
+ else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
+ return SELFREQDCO_HS1;
+ else
+ return -1;
+}
+
+/*
+ * select the sigma delta config
+ * return: sigma delta val
+ */
+static u32 pll_sigma_delta_val(u32 clkout_dco)
+{
+ u32 sig_val = 0;
+
+ sig_val = (clkout_dco + 225) / 250;
+ sig_val = sig_val << 24;
+
+ return sig_val;
+}
+
+/*
+ * configure individual ADPLLJ
+ */
+static void pll_config(u32 base, u32 n, u32 m, u32 m2,
+ u32 clkctrl_val, int adpllj)
+{
+ const struct ad_pll *adpll = (struct ad_pll *)base;
+ u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
+ u32 sig_val = 0, hs_mod = 0;
+
+ m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
+ mn2val = m;
+
+ /* calculate clkout_dco */
+ clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
+
+ /* sigma delta & Hs mode selection skip for ADPLLS*/
+ if (adpllj) {
+ sig_val = pll_sigma_delta_val(clkout_dco);
+ hs_mod = pll_dco_freq_sel(clkout_dco);
+ }
+
+ /* by-pass pll */
+ read_clkctrl = readl(&adpll->clkctrl);
+ writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
+ while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
+ != ADPLLJ_STATUS_BYPASSANDACK)
+ ;
+
+ /* clear TINITZ */
+ read_clkctrl = readl(&adpll->clkctrl);
+ writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
+
+ /*
+ * ref_clk = 20/(n + 1);
+ * clkout_dco = ref_clk * m;
+ * clk_out = clkout_dco/m2;
+ */
+ read_clkctrl = readl(&adpll->clkctrl) &
+ ~(ADPLLJ_CLKCTRL_LPMODE |
+ ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
+ ADPLLJ_CLKCTRL_REGM4XEN);
+ writel(m2nval, &adpll->m2ndiv);
+ writel(mn2val, &adpll->mn2div);
+
+ /* Skip for modena(ADPLLS) */
+ if (adpllj) {
+ writel(sig_val, &adpll->fracdiv);
+ writel((read_clkctrl | hs_mod), &adpll->clkctrl);
+ }
+
+ /* Load M2, N2 dividers of ADPLL */
+ writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
+ writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
+
+ /* Load M, N dividers of ADPLL */
+ writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
+ writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
+
+ /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
+ read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
+ if (adpllj)
+ writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
+ &adpll->clkctrl);
+
+ /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
+ read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
+ writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
+
+ /* Wait for phase and freq lock */
+ while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
+ ADPLLJ_STATUS_PHSFRQLOCK)
+ ;
+}
+
+static void unlock_pll_control_mmr(void)
+{
+ /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
+ writel(0x1EDA4C3D, 0x481C5040);
+ writel(0x2FF1AC2B, 0x48140060);
+ writel(0xF757FDC0, 0x48140064);
+ writel(0xE2BC3A6D, 0x48140068);
+ writel(0x1EBF131D, 0x4814006c);
+ writel(0x6F361E05, 0x48140070);
+}
+
+static void mpu_pll_config(void)
+{
+ pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
+}
+
+static void l3_pll_config(void)
+{
+ u32 l3_osc_src, rd_osc_src = 0;
+
+ l3_osc_src = L3_OSC_SRC;
+ rd_osc_src = readl(OSC_SRC_CTRL);
+
+ if (OSC_SRC0 == l3_osc_src)
+ writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
+ else
+ writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
+
+ pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
+}
+
+void ddr_pll_config(unsigned int ddrpll_m)
+{
+ pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
+}
+
+void sata_pll_config(void)
+{
+ /*
+ * This sequence for configuring the SATA PLL
+ * resident in the control module is documented
+ * in TI8148 TRM section 21.3.1
+ */
+ writel(SATA_PLLCFG1, &spll->pllcfg1);
+ udelay(50);
+
+ writel(SATA_PLLCFG3, &spll->pllcfg3);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_1, &spll->pllcfg0);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_2, &spll->pllcfg0);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_3, &spll->pllcfg0);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_4, &spll->pllcfg0);
+ udelay(50);
+
+ while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
+ ;
+}
+
+void enable_dmm_clocks(void)
+{
+ writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
+ writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
+ writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
+ while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
+ ;
+ writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
+ while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
+ ;
+ while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
+ ;
+ writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
+ while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
+ ;
+ writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
+ while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
+ ;
+}
+
+void setup_clocks_for_console(void)
+{
+ unlock_pll_control_mmr();
+ /* UART0 */
+ writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+ while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+ ;
+}
+
+void setup_early_clocks(void)
+{
+ setup_clocks_for_console();
+}
+
+/*
+ * Configure the PLL/PRCM for necessary peripherals
+ */
+void prcm_init(void)
+{
+ /* Enable the control module */
+ writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+
+ /* Configure PLLs */
+ mpu_pll_config();
+ l3_pll_config();
+ sata_pll_config();
+
+ /* Enable the required peripherals */
+ enable_per_clocks();
+}
diff --git a/arch/arm/mach-omap2/am33xx/clock_ti816x.c b/arch/arm/mach-omap2/am33xx/clock_ti816x.c
new file mode 100644
index 0000000..079ddd7
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx/clock_ti816x.c
@@ -0,0 +1,450 @@
+/*
+ * clock_ti816x.c
+ *
+ * Clocks for TI816X based boards
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * Copyright (C) 2009, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#include <asm/emif.h>
+
+#define CM_PLL_BASE (CTRL_BASE + 0x0400)
+
+/* Main PLL */
+#define MAIN_N 64
+#define MAIN_P 0x1
+#define MAIN_INTFREQ1 0x8
+#define MAIN_FRACFREQ1 0x800000
+#define MAIN_MDIV1 0x2
+#define MAIN_INTFREQ2 0xE
+#define MAIN_FRACFREQ2 0x0
+#define MAIN_MDIV2 0x1
+#define MAIN_INTFREQ3 0x8
+#define MAIN_FRACFREQ3 0xAAAAB0
+#define MAIN_MDIV3 0x3
+#define MAIN_INTFREQ4 0x9
+#define MAIN_FRACFREQ4 0x55554F
+#define MAIN_MDIV4 0x3
+#define MAIN_INTFREQ5 0x9
+#define MAIN_FRACFREQ5 0x374BC6
+#define MAIN_MDIV5 0xC
+#define MAIN_MDIV6 0x48
+#define MAIN_MDIV7 0x4
+
+/* DDR PLL */
+#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */
+#define DDR_N 59
+#define DDR_P 0x1
+#define DDR_MDIV1 0x4
+#define DDR_INTFREQ2 0x8
+#define DDR_FRACFREQ2 0xD99999
+#define DDR_MDIV2 0x1E
+#define DDR_INTFREQ3 0x8
+#define DDR_FRACFREQ3 0x0
+#define DDR_MDIV3 0x4
+#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4 0x0
+#define DDR_MDIV4 0x4
+#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5 0x0
+#define DDR_MDIV5 0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */
+#define DDR_N 59
+#define DDR_P 0x1
+#define DDR_MDIV1 0x3
+#define DDR_INTFREQ2 0x8
+#define DDR_FRACFREQ2 0xD99999
+#define DDR_MDIV2 0x1E
+#define DDR_INTFREQ3 0x8
+#define DDR_FRACFREQ3 0x0
+#define DDR_MDIV3 0x4
+#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4 0x0
+#define DDR_MDIV4 0x4
+#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5 0x0
+#define DDR_MDIV5 0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */
+#define DDR_N 50
+#define DDR_P 0x1
+#define DDR_MDIV1 0x2
+#define DDR_INTFREQ2 0x9
+#define DDR_FRACFREQ2 0x0
+#define DDR_MDIV2 0x19
+#define DDR_INTFREQ3 0x13
+#define DDR_FRACFREQ3 0x800000
+#define DDR_MDIV3 0x2
+#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4 0x0
+#define DDR_MDIV4 0x4
+#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5 0x0
+#define DDR_MDIV5 0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */
+#define DDR_N 59
+#define DDR_P 0x1
+#define DDR_MDIV1 0x2
+#define DDR_INTFREQ2 0x8
+#define DDR_FRACFREQ2 0xD99999
+#define DDR_MDIV2 0x1E
+#define DDR_INTFREQ3 0x8
+#define DDR_FRACFREQ3 0x0
+#define DDR_MDIV3 0x4
+#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4 0x0
+#define DDR_MDIV4 0x4
+#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5 0x0
+#define DDR_MDIV5 0x4
+#endif
+
+#define CONTROL_STATUS (CTRL_BASE + 0x40)
+#define DDR_RCD (CTRL_BASE + 0x070C)
+#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390)
+#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420)
+#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628)
+
+#define INTCPS_SYSCONFIG 0x48200010
+#define CM_SYSCLK10_CLKSEL 0x48180324
+
+struct cm_pll {
+ unsigned int mainpll_ctrl; /* offset 0x400 */
+ unsigned int mainpll_pwd;
+ unsigned int mainpll_freq1;
+ unsigned int mainpll_div1;
+ unsigned int mainpll_freq2;
+ unsigned int mainpll_div2;
+ unsigned int mainpll_freq3;
+ unsigned int mainpll_div3;
+ unsigned int mainpll_freq4;
+ unsigned int mainpll_div4;
+ unsigned int mainpll_freq5;
+ unsigned int mainpll_div5;
+ unsigned int resv0[1];
+ unsigned int mainpll_div6;
+ unsigned int resv1[1];
+ unsigned int mainpll_div7;
+ unsigned int ddrpll_ctrl; /* offset 0x440 */
+ unsigned int ddrpll_pwd;
+ unsigned int resv2[1];
+ unsigned int ddrpll_div1;
+ unsigned int ddrpll_freq2;
+ unsigned int ddrpll_div2;
+ unsigned int ddrpll_freq3;
+ unsigned int ddrpll_div3;
+ unsigned int ddrpll_freq4;
+ unsigned int ddrpll_div4;
+ unsigned int ddrpll_freq5;
+ unsigned int ddrpll_div5;
+ unsigned int videopll_ctrl; /* offset 0x470 */
+ unsigned int videopll_pwd;
+ unsigned int videopll_freq1;
+ unsigned int videopll_div1;
+ unsigned int videopll_freq2;
+ unsigned int videopll_div2;
+ unsigned int videopll_freq3;
+ unsigned int videopll_div3;
+ unsigned int resv3[4];
+ unsigned int audiopll_ctrl; /* offset 0x4A0 */
+ unsigned int audiopll_pwd;
+ unsigned int resv4[2];
+ unsigned int audiopll_freq2;
+ unsigned int audiopll_div2;
+ unsigned int audiopll_freq3;
+ unsigned int audiopll_div3;
+ unsigned int audiopll_freq4;
+ unsigned int audiopll_div4;
+ unsigned int audiopll_freq5;
+ unsigned int audiopll_div5;
+};
+
+const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
+const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
+const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+void enable_dmm_clocks(void)
+{
+ writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
+ writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
+ writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
+
+ /* Wait for clocks to be active */
+ while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
+ ;
+ /* Wait for emif0 to be fully functional, including OCP */
+ while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
+ ;
+ /* Wait for emif1 to be fully functional, including OCP */
+ while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
+ ;
+
+ writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
+ /* Wait for dmm to be fully functional, including OCP */
+ while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
+ ;
+
+ /* Enable Tiled Access */
+ writel(0x80000000, DMM_PAT_BASE_ADDR);
+}
+
+/* assume delay is aprox at least 1us */
+static void ddr_delay(int d)
+{
+ int i;
+
+ /*
+ * read a control register.
+ * this is a bit more delay and cannot be optimized by the compiler
+ * assuming one read takes 200 cycles and A8 is runing 1 GHz
+ * somewhat conservative setting
+ */
+ for (i = 0; i < 50*d; i++)
+ readl(CONTROL_STATUS);
+}
+
+static void main_pll_init_ti816x(void)
+{
+ u32 main_pll_ctrl = 0;
+
+ /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
+ main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+ main_pll_ctrl &= 0xFFFFFFFB;
+ main_pll_ctrl |= BIT(2);
+ writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+ /* Enable PLL by setting BIT3 in its ctrl reg */
+ main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+ main_pll_ctrl &= 0xFFFFFFF7;
+ main_pll_ctrl |= BIT(3);
+ writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+ /* Write the values of N,P in the CTRL reg */
+ main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+ main_pll_ctrl &= 0xFF;
+ main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
+ writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+ /* Power up clock1-7 */
+ writel(0x0, &cmpll->mainpll_pwd);
+
+ /* Program the freq and divider values for clock1-7 */
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
+ &cmpll->mainpll_freq1);
+ writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
+
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
+ &cmpll->mainpll_freq2);
+ writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
+
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
+ &cmpll->mainpll_freq3);
+ writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
+
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
+ &cmpll->mainpll_freq4);
+ writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
+
+ writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
+ &cmpll->mainpll_freq5);
+ writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
+
+ writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
+
+ writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
+
+ /* Wait for PLL to lock */
+ while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
+ ;
+
+ /* Put the PLL in normal mode, disable bypass */
+ main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+ main_pll_ctrl &= 0xFFFFFFFB;
+ writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+}
+
+static void ddr_pll_bypass_ti816x(void)
+{
+ u32 ddr_pll_ctrl = 0;
+
+ /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
+ ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+ ddr_pll_ctrl &= 0xFFFFFFFB;
+ ddr_pll_ctrl |= BIT(2);
+ writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+}
+
+static void ddr_pll_init_ti816x(void)
+{
+ u32 ddr_pll_ctrl = 0;
+ /* Enable PLL by setting BIT3 in its ctrl reg */
+ ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+ ddr_pll_ctrl &= 0xFFFFFFF7;
+ ddr_pll_ctrl |= BIT(3);
+ writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+ /* Write the values of N,P in the CTRL reg */
+ ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+ ddr_pll_ctrl &= 0xFF;
+ ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
+ writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+ ddr_delay(10);
+
+ /* Power up clock1-5 */
+ writel(0x0, &cmpll->ddrpll_pwd);
+
+ /* Program the freq and divider values for clock1-3 */
+ writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+ ddr_delay(1);
+ writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+ writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
+ &cmpll->ddrpll_freq2);
+ writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
+ writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+ ddr_delay(1);
+ writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+ ddr_delay(1);
+ writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+ &cmpll->ddrpll_freq3);
+ ddr_delay(1);
+ writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+ &cmpll->ddrpll_freq3);
+
+ ddr_delay(5);
+
+ /* Wait for PLL to lock */
+ while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
+ ;
+
+ /* Power up RCD */
+ writel(BIT(0), DDR_RCD);
+}
+
+static void peripheral_enable(void)
+{
+ /* Wake-up the l3_slow clock */
+ writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
+
+ /*
+ * Note on Timers:
+ * There are 8 timers(0-7) out of which timer 0 is a secure timer.
+ * Timer 0 mux should not be changed
+ *
+ * To access the timer registers we need the to be
+ * enabled which is what we do in the first step
+ */
+
+ /* Enable timer1 */
+ writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
+ /* Select timer1 clock to be CLKIN (27MHz) */
+ writel(BIT(1), CM_TIMER1_CLKSEL);
+
+ /* Wait for timer1 to be ON-ACTIVE */
+ while (((readl(&cmalwon->l3slowclkstctrl)
+ & (0x80000<<1))>>20) != 1)
+ ;
+ /* Wait for timer1 to be enabled */
+ while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
+ ;
+ /* Active posted mode */
+ writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
+ while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
+ ;
+ /* Start timer1 */
+ writel(BIT(0), (DM_TIMER1_BASE + 0x38));
+
+ /* eFuse */
+ writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
+ while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
+ ;
+
+ /* Enable gpio0 */
+ writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
+ while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
+ ;
+ writel((BIT(8)), &cmalwon->gpio0clkctrl);
+
+ /* Enable spi */
+ writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
+ while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* Enable i2c0 */
+ writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
+ while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* Enable ethernet0 */
+ writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+ writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+ writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+
+ /* Enable hsmmc */
+ writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
+ while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
+ ;
+}
+
+void setup_clocks_for_console(void)
+{
+ /* Fix ROM code bug - from TI-PSP-04.00.02.14 */
+ writel(0x0, CM_SYSCLK10_CLKSEL);
+
+ ddr_pll_bypass_ti816x();
+
+ /* Enable uart0-2 */
+ writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+ while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+ ;
+ writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
+ while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
+ ;
+ writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
+ while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
+ ;
+ while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
+ ;
+}
+
+void setup_early_clocks(void)
+{
+ setup_clocks_for_console();
+}
+
+void prcm_init(void)
+{
+ /* Enable the control */
+ writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+
+ main_pll_init_ti816x();
+ ddr_pll_init_ti816x();
+
+ /*
+ * With clk freqs setup to desired values,
+ * enable the required peripherals
+ */
+ peripheral_enable();
+}
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
new file mode 100644
index 0000000..690487e
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -0,0 +1,381 @@
+/*
+ * DDR Configuration for AM33xx devices.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+/**
+ * Base address for EMIF instances
+ */
+static struct emif_reg_struct *emif_reg[2] = {
+ (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+ (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
+
+/**
+ * Base addresses for DDR PHY cmd/data regs
+ */
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+ (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
+ (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+ (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
+ (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
+
+/**
+ * Base address for ddr io control instances
+ */
+static struct ddr_cmdtctrl *ioctrl_reg = {
+ (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
+{
+ u32 mr;
+
+ mr_addr |= cs << EMIF_REG_CS_SHIFT;
+ writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+
+ mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
+ debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
+ if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
+ ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+ ((mr & 0xff000000) >> 24) == (mr & 0xff))
+ return mr & 0xff;
+ else
+ return mr;
+}
+
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
+{
+ mr_addr |= cs << EMIF_REG_CS_SHIFT;
+ writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+ writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
+}
+
+static void configure_mr(int nr, u32 cs)
+{
+ u32 mr_addr;
+
+ while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+ ;
+ set_mr(nr, cs, LPDDR2_MR10, 0x56);
+
+ set_mr(nr, cs, LPDDR2_MR1, 0x43);
+ set_mr(nr, cs, LPDDR2_MR2, 0x2);
+
+ mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+ set_mr(nr, cs, mr_addr, 0x2);
+}
+
+/*
+ * Configure EMIF4D5 registers and MR registers For details about these magic
+ * values please see the EMIF registers section of the TRM.
+ */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
+{
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+ writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+
+ writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
+ writel(regs->emif_rd_wr_lvl_rmp_win,
+ &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
+ writel(regs->emif_rd_wr_lvl_rmp_ctl,
+ &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+ writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+ writel(regs->emif_rd_wr_exec_thresh,
+ &emif_reg[nr]->emif_rd_wr_exec_thresh);
+
+ /*
+ * for most SOCs these registers won't need to be changed so only
+ * write to these registers if someone explicitly has set the
+ * register's value.
+ */
+ if(regs->emif_cos_config) {
+ writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+ writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+ writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+ writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+ }
+
+ /*
+ * Sequence to ensure that the PHY is in a known state prior to
+ * startting hardware leveling. Also acts as to latch some state from
+ * the EMIF into the PHY.
+ */
+ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+ writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+
+ clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+ EMIF_REG_INITREF_DIS_MASK);
+
+ writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+ writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+
+ /* Wait 1ms because of L3 timeout error */
+ udelay(1000);
+
+ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+
+ /* Perform hardware leveling for DDR3 */
+ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
+ writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
+ 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+ writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
+ 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
+ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+
+ /* Enable read leveling */
+ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+
+ /*
+ * Enable full read and write leveling. Wait for read and write
+ * leveling bit to clear RDWRLVLFULL_START bit 31
+ */
+ while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
+ != 0)
+ ;
+
+ /* Check the timeout register to see if leveling is complete */
+ if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
+ puts("DDR3 H/W leveling incomplete with errors\n");
+
+ } else {
+ /* DDR2 */
+ configure_mr(nr, 0);
+ configure_mr(nr, 1);
+ }
+}
+
+/**
+ * Configure SDRAM
+ */
+void config_sdram(const struct emif_regs *regs, int nr)
+{
+ if (regs->zq_config) {
+ writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+ writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+ writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+ /* Trigger initialization */
+ writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ /* Wait 1ms because of L3 timeout error */
+ udelay(1000);
+
+ /* Write proper sdram_ref_cref_ctrl value */
+ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+ }
+ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+ writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+ /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
+ if (regs->ocp_config)
+ writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
+}
+
+/**
+ * Set SDRAM timings
+ */
+void set_sdram_timings(const struct emif_regs *regs, int nr)
+{
+ writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
+ writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
+ writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
+ writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
+ writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
+ writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
+}
+
+/*
+ * Configure EXT PHY registers for software leveling
+ */
+static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
+{
+ u32 *ext_phy_ctrl_base = 0;
+ u32 *emif_ext_phy_ctrl_base = 0;
+ __maybe_unused const u32 *ext_phy_ctrl_const_regs;
+ u32 i = 0;
+ __maybe_unused u32 size;
+
+ ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+ emif_ext_phy_ctrl_base =
+ (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+ /* Configure external phy control timing registers */
+ for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+ writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+ }
+
+#ifdef CONFIG_AM43XX
+ /*
+ * External phy 6-24 registers do not change with ddr frequency.
+ * These only need to be set on DDR2 on AM43xx.
+ */
+ emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+ if (!size)
+ return;
+
+ for (i = 0; i < size; i++) {
+ writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+ }
+#endif
+}
+
+/*
+ * Configure EXT PHY registers for hardware leveling
+ */
+static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
+{
+ /*
+ * Enable hardware leveling on the EMIF. For details about these
+ * magic values please see the EMIF registers section of the TRM.
+ */
+ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
+ writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
+ writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
+ writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
+ writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
+ writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
+ writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
+ writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+ writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
+ /*
+ * Sequence to ensure that the PHY is again in a known state after
+ * hardware leveling.
+ */
+ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+ writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+}
+
+/**
+ * Configure DDR PHY
+ */
+void config_ddr_phy(const struct emif_regs *regs, int nr)
+{
+ /*
+ * Disable initialization and refreshes for now until we finish
+ * programming EMIF regs and set time between rising edge of
+ * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
+ * We currently hardcode a value based on a max expected frequency
+ * of 400MHz.
+ */
+ writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
+ &emif_reg[nr]->emif_sdram_ref_ctrl);
+
+ writel(regs->emif_ddr_phy_ctlr_1,
+ &emif_reg[nr]->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1,
+ &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
+
+ if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
+ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
+ ext_phy_settings_hwlvl(regs, nr);
+ else
+ ext_phy_settings_swlvl(regs, nr);
+ }
+}
+
+/**
+ * Configure DDR CMD control registers
+ */
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
+{
+ if (!cmd)
+ return;
+
+ writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
+ writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
+
+ writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
+ writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
+
+ writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
+ writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
+}
+
+/**
+ * Configure DDR DATA registers
+ */
+void config_ddr_data(const struct ddr_data *data, int nr)
+{
+ int i;
+
+ if (!data)
+ return;
+
+ for (i = 0; i < DDR_DATA_REGS_NR; i++) {
+ writel(data->datardsratio0,
+ &(ddr_data_reg[nr]+i)->dt0rdsratio0);
+ writel(data->datawdsratio0,
+ &(ddr_data_reg[nr]+i)->dt0wdsratio0);
+ writel(data->datawiratio0,
+ &(ddr_data_reg[nr]+i)->dt0wiratio0);
+ writel(data->datagiratio0,
+ &(ddr_data_reg[nr]+i)->dt0giratio0);
+ writel(data->datafwsratio0,
+ &(ddr_data_reg[nr]+i)->dt0fwsratio0);
+ writel(data->datawrsratio0,
+ &(ddr_data_reg[nr]+i)->dt0wrsratio0);
+ }
+}
+
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
+{
+ if (!ioregs)
+ return;
+
+ writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
+ writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
+ writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
+ writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
+ writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
+#ifdef CONFIG_AM43XX
+ writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
+ writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
+ writel(ioregs->emif_sdram_config_ext,
+ &ioctrl_reg->emif_sdram_config_ext);
+#endif
+}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c
similarity index 100%
rename from arch/arm/cpu/armv7/am33xx/emif4.c
rename to arch/arm/mach-omap2/am33xx/emif4.c
diff --git a/arch/arm/cpu/armv7/am33xx/mux.c b/arch/arm/mach-omap2/am33xx/mux.c
similarity index 100%
rename from arch/arm/cpu/armv7/am33xx/mux.c
rename to arch/arm/mach-omap2/am33xx/mux.c
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c
new file mode 100644
index 0000000..f0f72fa
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -0,0 +1,176 @@
+/*
+ * sys_info.c
+ *
+ * System information functions
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <power/tps65910.h>
+#include <linux/compiler.h>
+
+struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
+
+/**
+ * get_cpu_rev(void) - extract rev info
+ */
+u32 get_cpu_rev(void)
+{
+ u32 id;
+ u32 rev;
+
+ id = readl(DEVICE_ID);
+ rev = (id >> 28) & 0xff;
+
+ return rev;
+}
+
+/**
+ * get_cpu_type(void) - extract cpu info
+ */
+u32 get_cpu_type(void)
+{
+ u32 id = 0;
+ u32 partnum;
+
+ id = readl(DEVICE_ID);
+ partnum = (id >> 12) & 0xffff;
+
+ return partnum;
+}
+
+/**
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+ int mode;
+ mode = readl(&cstat->statusreg) & (DEVICE_MASK);
+ return mode >>= 8;
+}
+
+/**
+ * get_sysboot_value(void) - return SYS_BOOT[4:0]
+ */
+u32 get_sysboot_value(void)
+{
+ return readl(&cstat->statusreg) & SYSBOOT_MASK;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static char *cpu_revs[] = {
+ "1.0",
+ "2.0",
+ "2.1"};
+
+
+static char *dev_types[] = {
+ "TST",
+ "EMU",
+ "HS",
+ "GP"};
+
+/**
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+ char *cpu_s, *sec_s, *rev_s;
+
+ switch (get_cpu_type()) {
+ case AM335X:
+ cpu_s = "AM335X";
+ break;
+ case TI81XX:
+ cpu_s = "TI81XX";
+ break;
+ case AM437X:
+ cpu_s = "AM437X";
+ break;
+ default:
+ cpu_s = "Unknown CPU type";
+ break;
+ }
+
+ if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
+ rev_s = cpu_revs[get_cpu_rev()];
+ else
+ rev_s = "?";
+
+ if (get_device_type() < ARRAY_SIZE(dev_types))
+ sec_s = dev_types[get_device_type()];
+ else
+ sec_s = "?";
+
+ printf("CPU : %s-%s rev %s\n", cpu_s, sec_s, rev_s);
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_AM33XX
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
+{
+ int sil_rev;
+
+ sil_rev = readl(&cdev->deviceid) >> 28;
+
+ if (sil_rev == 1)
+ /* PG 2.0, efuse may not be set. */
+ return MPUPLL_M_800;
+ else if (sil_rev >= 2) {
+ /* Check what the efuse says our max speed is. */
+ int efuse_arm_mpu_max_freq;
+ efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+ switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
+ case AM335X_ZCZ_1000:
+ return MPUPLL_M_1000;
+ case AM335X_ZCZ_800:
+ return MPUPLL_M_800;
+ case AM335X_ZCZ_720:
+ return MPUPLL_M_720;
+ case AM335X_ZCZ_600:
+ case AM335X_ZCE_600:
+ return MPUPLL_M_600;
+ case AM335X_ZCZ_300:
+ case AM335X_ZCE_300:
+ return MPUPLL_M_300;
+ }
+ }
+
+ /* PG 1.0 or otherwise unknown, use the PG1.0 max */
+ return MPUPLL_M_720;
+}
+
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
+{
+ /* For PG2.1 and later, we have one set of values. */
+ if (sil_rev >= 2) {
+ switch (frequency) {
+ case MPUPLL_M_1000:
+ return TPS65910_OP_REG_SEL_1_3_2_5;
+ case MPUPLL_M_800:
+ return TPS65910_OP_REG_SEL_1_2_6;
+ case MPUPLL_M_720:
+ return TPS65910_OP_REG_SEL_1_2_0;
+ case MPUPLL_M_600:
+ case MPUPLL_M_300:
+ return TPS65910_OP_REG_SEL_1_1_3;
+ }
+ }
+
+ /* Default to PG1.0/PG2.0 values. */
+ return TPS65910_OP_REG_SEL_1_1_3;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/mach-omap2/am33xx/u-boot-spl.lds
similarity index 100%
rename from arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
rename to arch/arm/mach-omap2/am33xx/u-boot-spl.lds
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
new file mode 100644
index 0000000..385310b
--- /dev/null
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -0,0 +1,252 @@
+/*
+ * boot-common.c
+ *
+ * Common bootmode functions for omap based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <spl.h>
+#include <asm/omap_common.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <watchdog.h>
+#include <scsi.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak u32 omap_sys_boot_device(void)
+{
+ return BOOT_DEVICE_NONE;
+}
+
+void save_omap_boot_params(void)
+{
+ u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+ struct omap_boot_parameters *omap_boot_params;
+ int sys_boot_device = 0;
+ u32 boot_device;
+ u32 boot_mode;
+
+ if ((boot_params < NON_SECURE_SRAM_START) ||
+ (boot_params > NON_SECURE_SRAM_END))
+ return;
+
+ omap_boot_params = (struct omap_boot_parameters *)boot_params;
+
+ boot_device = omap_boot_params->boot_device;
+ boot_mode = MMCSD_MODE_UNDEFINED;
+
+ /* Boot device */
+
+#ifdef BOOT_DEVICE_NAND_I2C
+ /*
+ * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
+ * Otherwise the SPL boot IF can't handle this device correctly.
+ * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
+ * Draco leads to this boot-device passed to SPL from the BootROM.
+ */
+ if (boot_device == BOOT_DEVICE_NAND_I2C)
+ boot_device = BOOT_DEVICE_NAND;
+#endif
+#ifdef BOOT_DEVICE_QSPI_4
+ /*
+ * We get different values for QSPI_1 and QSPI_4 being used, but
+ * don't actually care about this difference. Rather than
+ * mangle the later code, if we're coming in as QSPI_4 just
+ * change to the QSPI_1 value.
+ */
+ if (boot_device == BOOT_DEVICE_QSPI_4)
+ boot_device = BOOT_DEVICE_SPI;
+#endif
+ /*
+ * When booting from peripheral booting, the boot device is not usable
+ * as-is (unless there is support for it), so the boot device is instead
+ * figured out using the SYS_BOOT pins.
+ */
+ switch (boot_device) {
+#if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT)
+ case BOOT_DEVICE_UART:
+ sys_boot_device = 1;
+ break;
+#endif
+#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT)
+ case BOOT_DEVICE_USB:
+ sys_boot_device = 1;
+ break;
+#endif
+#if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USBETH_SUPPORT)
+ case BOOT_DEVICE_USBETH:
+ sys_boot_device = 1;
+ break;
+#endif
+#if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH_SUPPORT)
+ case BOOT_DEVICE_CPGMAC:
+ sys_boot_device = 1;
+ break;
+#endif
+#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU_SUPPORT)
+ case BOOT_DEVICE_DFU:
+ sys_boot_device = 1;
+ break;
+#endif
+ }
+
+ if (sys_boot_device) {
+ boot_device = omap_sys_boot_device();
+
+ /* MMC raw mode will fallback to FS mode. */
+ if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+ (boot_device <= MMC_BOOT_DEVICES_END))
+ boot_mode = MMCSD_MODE_RAW;
+ }
+
+ gd->arch.omap_boot_device = boot_device;
+
+ /* Boot mode */
+
+#ifdef CONFIG_OMAP34XX
+ if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+ (boot_device <= MMC_BOOT_DEVICES_END)) {
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ boot_mode = MMCSD_MODE_FS;
+ break;
+ case BOOT_DEVICE_MMC2:
+ boot_mode = MMCSD_MODE_RAW;
+ break;
+ }
+ }
+#else
+ /*
+ * If the boot device was dynamically changed and doesn't match what
+ * the bootrom initially booted, we cannot use the boot device
+ * descriptor to figure out the boot mode.
+ */
+ if ((boot_device == omap_boot_params->boot_device) &&
+ (boot_device >= MMC_BOOT_DEVICES_START) &&
+ (boot_device <= MMC_BOOT_DEVICES_END)) {
+ boot_params = omap_boot_params->boot_device_descriptor;
+ if ((boot_params < NON_SECURE_SRAM_START) ||
+ (boot_params > NON_SECURE_SRAM_END))
+ return;
+
+ boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET));
+ if ((boot_params < NON_SECURE_SRAM_START) ||
+ (boot_params > NON_SECURE_SRAM_END))
+ return;
+
+ boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET));
+
+ if (boot_mode != MMCSD_MODE_FS &&
+ boot_mode != MMCSD_MODE_RAW)
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ boot_mode = MMCSD_MODE_EMMCBOOT;
+#else
+ boot_mode = MMCSD_MODE_UNDEFINED;
+#endif
+ }
+#endif
+
+ gd->arch.omap_boot_mode = boot_mode;
+
+#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \
+ !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
+
+ /* CH flags */
+
+ gd->arch.omap_ch_flags = omap_boot_params->ch_flags;
+#endif
+}
+
+#ifdef CONFIG_SPL_BUILD
+u32 spl_boot_device(void)
+{
+ return gd->arch.omap_boot_device;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ return gd->arch.omap_boot_mode;
+}
+
+void spl_board_init(void)
+{
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+ save_omap_boot_params();
+
+ /* Prepare console output */
+ preloader_console_init();
+
+#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
+ gpmc_init();
+#endif
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+#endif
+#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
+ arch_misc_init();
+#endif
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+#ifdef CONFIG_AM33XX
+ am33xx_spl_board_init();
+#endif
+}
+
+__weak int board_mmc_init(bd_t *bis)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC1:
+ omap_mmc_init(0, 0, 0, -1, -1);
+ break;
+ case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC2_2:
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ break;
+ }
+ return 0;
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ typedef void __noreturn (*image_entry_noargs_t)(u32 *);
+ image_entry_noargs_t image_entry =
+ (image_entry_noargs_t) spl_image->entry_point;
+
+ u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+
+ debug("image entry point: 0x%X\n", spl_image->entry_point);
+ /* Pass the saved boot_params from rom code */
+ image_entry((u32 *)boot_params);
+}
+#endif
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void arch_preboot_os(void)
+{
+ ahci_reset((void __iomem *)DWC_AHSATA_BASE);
+}
+#endif
+
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE)
+int fb_set_reboot_flag(void)
+{
+ printf("Setting reboot to fastboot flag ...\n");
+ setenv("dofastboot", "1");
+ saveenv();
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c
new file mode 100644
index 0000000..84f93e7
--- /dev/null
+++ b/arch/arm/mach-omap2/clocks-common.c
@@ -0,0 +1,920 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+#include <asm/omap_common.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+#include <asm/omap_gpio.h>
+#include <asm/emif.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+const u32 sys_clk_array[8] = {
+ 12000000, /* 12 MHz */
+ 20000000, /* 20 MHz */
+ 16800000, /* 16.8 MHz */
+ 19200000, /* 19.2 MHz */
+ 26000000, /* 26 MHz */
+ 27000000, /* 27 MHz */
+ 38400000, /* 38.4 MHz */
+};
+
+static inline u32 __get_sys_clk_index(void)
+{
+ s8 ind;
+ /*
+ * For ES1 the ROM code calibration of sys clock is not reliable
+ * due to hw issue. So, use hard-coded value. If this value is not
+ * correct for any board over-ride this function in board file
+ * From ES2.0 onwards you will get this information from
+ * CM_SYS_CLKSEL
+ */
+ if (omap_revision() == OMAP4430_ES1_0)
+ ind = OMAP_SYS_CLK_IND_38_4_MHZ;
+ else {
+ /* SYS_CLKSEL - 1 to match the dpll param array indices */
+ ind = (readl((*prcm)->cm_sys_clksel) &
+ CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+ }
+ return ind;
+}
+
+u32 get_sys_clk_index(void)
+ __attribute__ ((weak, alias("__get_sys_clk_index")));
+
+u32 get_sys_clk_freq(void)
+{
+ u8 index = get_sys_clk_index();
+ return sys_clk_array[index];
+}
+
+void setup_post_dividers(u32 const base, const struct dpll_params *params)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ /* Setup post-dividers */
+ if (params->m2 >= 0)
+ writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+ if (params->m3 >= 0)
+ writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+ if (params->m4_h11 >= 0)
+ writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
+ if (params->m5_h12 >= 0)
+ writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
+ if (params->m6_h13 >= 0)
+ writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
+ if (params->m7_h14 >= 0)
+ writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
+ if (params->h21 >= 0)
+ writel(params->h21, &dpll_regs->cm_div_h21_dpll);
+ if (params->h22 >= 0)
+ writel(params->h22, &dpll_regs->cm_div_h22_dpll);
+ if (params->h23 >= 0)
+ writel(params->h23, &dpll_regs->cm_div_h23_dpll);
+ if (params->h24 >= 0)
+ writel(params->h24, &dpll_regs->cm_div_h24_dpll);
+}
+
+static inline void do_bypass_dpll(u32 const base)
+{
+ struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+ clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_FAST_RELOCK_BYPASS <<
+ CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(u32 const base)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
+ LDELAY)) {
+ printf("Bypassing DPLL failed %x\n", base);
+ }
+}
+
+static inline void do_lock_dpll(u32 const base)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(u32 const base)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+ &dpll_regs->cm_idlest_dpll, LDELAY)) {
+ printf("DPLL locking failed for %x\n", base);
+ hang();
+ }
+}
+
+inline u32 check_for_lock(u32 const base)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+ u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
+
+ return lock;
+}
+
+const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->mpu[sysclk_ind];
+}
+
+const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->core[sysclk_ind];
+}
+
+const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->per[sysclk_ind];
+}
+
+const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->iva[sysclk_ind];
+}
+
+const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->usb[sysclk_ind];
+}
+
+const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
+{
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->abe[sysclk_ind];
+#else
+ return dpll_data->abe;
+#endif
+}
+
+static const struct dpll_params *get_ddr_dpll_params
+ (struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+
+ if (!dpll_data->ddr)
+ return NULL;
+ return &dpll_data->ddr[sysclk_ind];
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static const struct dpll_params *get_gmac_dpll_params
+ (struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+
+ if (!dpll_data->gmac)
+ return NULL;
+ return &dpll_data->gmac[sysclk_ind];
+}
+#endif
+
+static void do_setup_dpll(u32 const base, const struct dpll_params *params,
+ u8 lock, char *dpll)
+{
+ u32 temp, M, N;
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ if (!params)
+ return;
+
+ temp = readl(&dpll_regs->cm_clksel_dpll);
+
+ if (check_for_lock(base)) {
+ /*
+ * The Dpll has already been locked by rom code using CH.
+ * Check if M,N are matching with Ideal nominal opp values.
+ * If matches, skip the rest otherwise relock.
+ */
+ M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
+ N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
+ if ((M != (params->m)) || (N != (params->n))) {
+ debug("\n %s Dpll locked, but not for ideal M = %d,"
+ "N = %d values, current values are M = %d,"
+ "N= %d" , dpll, params->m, params->n,
+ M, N);
+ } else {
+ /* Dpll locked with ideal values for nominal opps. */
+ debug("\n %s Dpll already locked with ideal"
+ "nominal opp values", dpll);
+
+ bypass_dpll(base);
+ goto setup_post_dividers;
+ }
+ }
+
+ bypass_dpll(base);
+
+ /* Set M & N */
+ temp &= ~CM_CLKSEL_DPLL_M_MASK;
+ temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+ temp &= ~CM_CLKSEL_DPLL_N_MASK;
+ temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+ writel(temp, &dpll_regs->cm_clksel_dpll);
+
+setup_post_dividers:
+ setup_post_dividers(base, params);
+
+ /* Lock */
+ if (lock)
+ do_lock_dpll(base);
+
+ /* Wait till the DPLL locks */
+ if (lock)
+ wait_for_lock(base);
+}
+
+u32 omap_ddr_clk(void)
+{
+ u32 ddr_clk, sys_clk_khz, omap_rev, divider;
+ const struct dpll_params *core_dpll_params;
+
+ omap_rev = omap_revision();
+ sys_clk_khz = get_sys_clk_freq() / 1000;
+
+ core_dpll_params = get_core_dpll_params(*dplls_data);
+
+ debug("sys_clk %d\n ", sys_clk_khz * 1000);
+
+ /* Find Core DPLL locked frequency first */
+ ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
+ (core_dpll_params->n + 1);
+
+ if (omap_rev < OMAP5430_ES1_0) {
+ /*
+ * DDR frequency is PHY_ROOT_CLK/2
+ * PHY_ROOT_CLK = Fdpll/2/M2
+ */
+ divider = 4;
+ } else {
+ /*
+ * DDR frequency is PHY_ROOT_CLK
+ * PHY_ROOT_CLK = Fdpll/2/M2
+ */
+ divider = 2;
+ }
+
+ ddr_clk = ddr_clk / divider / core_dpll_params->m2;
+ ddr_clk *= 1000; /* convert to Hz */
+ debug("ddr_clk %d\n ", ddr_clk);
+
+ return ddr_clk;
+}
+
+/*
+ * Lock MPU dpll
+ *
+ * Resulting MPU frequencies:
+ * 4430 ES1.0 : 600 MHz
+ * 4430 ES2.x : 792 MHz (OPP Turbo)
+ * 4460 : 920 MHz (OPP Turbo) - DCC disabled
+ */
+void configure_mpu_dpll(void)
+{
+ const struct dpll_params *params;
+ struct dpll_regs *mpu_dpll_regs;
+ u32 omap_rev;
+ omap_rev = omap_revision();
+
+ /*
+ * DCC and clock divider settings for 4460.
+ * DCC is required, if more than a certain frequency is required.
+ * For, 4460 > 1GHZ.
+ * 5430 > 1.4GHZ.
+ */
+ if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
+ mpu_dpll_regs =
+ (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
+ bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
+ clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
+ MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
+ setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
+ MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
+ clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
+ CM_CLKSEL_DCC_EN_MASK);
+ }
+
+ params = get_mpu_dpll_params(*dplls_data);
+
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
+ debug("MPU DPLL locked\n");
+}
+
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
+ defined(CONFIG_USB_MUSB_OMAP2PLUS)
+static void setup_usb_dpll(void)
+{
+ const struct dpll_params *params;
+ u32 sys_clk_khz, sd_div, num, den;
+
+ sys_clk_khz = get_sys_clk_freq() / 1000;
+ /*
+ * USB:
+ * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+ * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+ * - where CLKINP is sys_clk in MHz
+ * Use CLKINP in KHz and adjust the denominator accordingly so
+ * that we have enough accuracy and at the same time no overflow
+ */
+ params = get_usb_dpll_params(*dplls_data);
+ num = params->m * sys_clk_khz;
+ den = (params->n + 1) * 250 * 1000;
+ num += den - 1;
+ sd_div = num / den;
+ clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
+ CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
+ sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
+
+ /* Now setup the dpll with the regular function */
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
+}
+#endif
+
+static void setup_dplls(void)
+{
+ u32 temp;
+ const struct dpll_params *params;
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+ debug("setup_dplls\n");
+
+ /* CORE dpll */
+ params = get_core_dpll_params(*dplls_data); /* default - safest */
+ /*
+ * Do not lock the core DPLL now. Just set it up.
+ * Core DPLL will be locked after setting up EMIF
+ * using the FREQ_UPDATE method(freq_update_core())
+ */
+ if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
+ EMIF_SDRAM_TYPE_LPDDR2)
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
+ DPLL_NO_LOCK, "core");
+ else
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
+ DPLL_LOCK, "core");
+ /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
+ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
+ (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
+ (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
+ writel(temp, (*prcm)->cm_clksel_core);
+ debug("Core DPLL configured\n");
+
+ /* lock PER dpll */
+ params = get_per_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
+ params, DPLL_LOCK, "per");
+ debug("PER DPLL locked\n");
+
+ /* MPU dpll */
+ configure_mpu_dpll();
+
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
+ defined(CONFIG_USB_MUSB_OMAP2PLUS)
+ setup_usb_dpll();
+#endif
+ params = get_ddr_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
+ params, DPLL_LOCK, "ddr");
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+ params = get_gmac_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
+ DPLL_LOCK, "gmac");
+#endif
+}
+
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
+{
+ u32 offset_code;
+
+ volt_offset -= pmic->base_offset;
+
+ offset_code = (volt_offset + pmic->step - 1) / pmic->step;
+
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ return offset_code + pmic->start_code;
+}
+
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
+{
+ u32 offset_code;
+ u32 offset = volt_mv;
+ int ret = 0;
+
+ if (!volt_mv)
+ return;
+
+ pmic->pmic_bus_init();
+ /* See if we can first get the GPIO if needed */
+ if (pmic->gpio_en)
+ ret = gpio_request(pmic->gpio, "PMIC_GPIO");
+
+ if (ret < 0) {
+ printf("%s: gpio %d request failed %d\n", __func__,
+ pmic->gpio, ret);
+ return;
+ }
+
+ /* Pull the GPIO low to select SET0 register, while we program SET1 */
+ if (pmic->gpio_en)
+ gpio_direction_output(pmic->gpio, 0);
+
+ /* convert to uV for better accuracy in the calculations */
+ offset *= 1000;
+
+ offset_code = get_offset_code(offset, pmic);
+
+ debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
+ offset_code);
+
+ if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
+ printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+ if (pmic->gpio_en)
+ gpio_direction_output(pmic->gpio, 1);
+}
+
+int __weak get_voltrail_opp(int rail_offset)
+{
+ /*
+ * By default return OPP_NOM for all voltage rails.
+ */
+ return OPP_NOM;
+}
+
+static u32 optimize_vcore_voltage(struct volts const *v, int opp)
+{
+ u32 val;
+
+ if (!v->value[opp])
+ return 0;
+ if (!v->efuse.reg[opp])
+ return v->value[opp];
+
+ switch (v->efuse.reg_bits) {
+ case 16:
+ val = readw(v->efuse.reg[opp]);
+ break;
+ case 32:
+ val = readl(v->efuse.reg[opp]);
+ break;
+ default:
+ printf("Error: efuse 0x%08x bits=%d unknown\n",
+ v->efuse.reg[opp], v->efuse.reg_bits);
+ return v->value[opp];
+ }
+
+ if (!val) {
+ printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
+ v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp]);
+ return v->value[opp];
+ }
+
+ debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
+ __func__, v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp],
+ val);
+ return val;
+}
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void __weak recalibrate_iodelay(void)
+{
+}
+#endif
+
+/*
+ * Setup the voltages for the main SoC core power domains.
+ * We start with the maximum voltages allowed here, as set in the corresponding
+ * vcores_data struct, and then scale (usually down) to the fused values that
+ * are retrieved from the SoC. The scaling happens only if the efuse.reg fields
+ * are initialised.
+ * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
+ * compiled conditionally. Note that the new code writes the scaled (or zeroed)
+ * values back to the vcores_data struct for eventual reuse. Zero values mean
+ * that the corresponding rails are not controlled separately, and are not sent
+ * to the PMIC.
+ */
+void scale_vcores(struct vcores_data const *vcores)
+{
+ int i, opp, j, ol;
+ struct volts *pv = (struct volts *)vcores;
+ struct volts *px;
+
+ for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
+ opp = get_voltrail_opp(i);
+ debug("%d -> ", pv->value[opp]);
+
+ if (pv->value[opp]) {
+ /* Handle non-empty members only */
+ pv->value[opp] = optimize_vcore_voltage(pv, opp);
+ px = (struct volts *)vcores;
+ j = 0;
+ while (px < pv) {
+ /*
+ * Scan already handled non-empty members to see
+ * if we have a group and find the max voltage,
+ * which is set to the first occurance of the
+ * particular SMPS; the other group voltages are
+ * zeroed.
+ */
+ ol = get_voltrail_opp(j);
+ if (px->value[ol] &&
+ (pv->pmic->i2c_slave_addr ==
+ px->pmic->i2c_slave_addr) &&
+ (pv->addr == px->addr)) {
+ /* Same PMIC, same SMPS */
+ if (pv->value[opp] > px->value[ol])
+ px->value[ol] = pv->value[opp];
+
+ pv->value[opp] = 0;
+ }
+ px++;
+ j++;
+ }
+ }
+ debug("%d\n", pv->value[opp]);
+ pv++;
+ }
+
+ opp = get_voltrail_opp(VOLT_CORE);
+ debug("cor: %d\n", vcores->core.value[opp]);
+ do_scale_vcore(vcores->core.addr, vcores->core.value[opp],
+ vcores->core.pmic);
+ /*
+ * IO delay recalibration should be done immediately after
+ * adjusting AVS voltages for VDD_CORE_L.
+ * Respective boards should call __recalibrate_iodelay()
+ * with proper mux, virtual and manual mode configurations.
+ */
+#ifdef CONFIG_IODELAY_RECALIBRATION
+ recalibrate_iodelay();
+#endif
+
+ opp = get_voltrail_opp(VOLT_MPU);
+ debug("mpu: %d\n", vcores->mpu.value[opp]);
+ do_scale_vcore(vcores->mpu.addr, vcores->mpu.value[opp],
+ vcores->mpu.pmic);
+ /* Configure MPU ABB LDO after scale */
+ abb_setup(vcores->mpu.efuse.reg[opp],
+ (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
+ (*prcm)->prm_abbldo_mpu_setup,
+ (*prcm)->prm_abbldo_mpu_ctrl,
+ (*prcm)->prm_irqstatus_mpu_2,
+ vcores->mpu.abb_tx_done_mask,
+ OMAP_ABB_FAST_OPP);
+
+ opp = get_voltrail_opp(VOLT_MM);
+ debug("mm: %d\n", vcores->mm.value[opp]);
+ do_scale_vcore(vcores->mm.addr, vcores->mm.value[opp],
+ vcores->mm.pmic);
+ /* Configure MM ABB LDO after scale */
+ abb_setup(vcores->mm.efuse.reg[opp],
+ (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
+ (*prcm)->prm_abbldo_mm_setup,
+ (*prcm)->prm_abbldo_mm_ctrl,
+ (*prcm)->prm_irqstatus_mpu,
+ vcores->mm.abb_tx_done_mask,
+ OMAP_ABB_FAST_OPP);
+
+ opp = get_voltrail_opp(VOLT_GPU);
+ debug("gpu: %d\n", vcores->gpu.value[opp]);
+ do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp],
+ vcores->gpu.pmic);
+ /* Configure GPU ABB LDO after scale */
+ abb_setup(vcores->gpu.efuse.reg[opp],
+ (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
+ (*prcm)->prm_abbldo_gpu_setup,
+ (*prcm)->prm_abbldo_gpu_ctrl,
+ (*prcm)->prm_irqstatus_mpu,
+ vcores->gpu.abb_tx_done_mask,
+ OMAP_ABB_FAST_OPP);
+
+ opp = get_voltrail_opp(VOLT_EVE);
+ debug("eve: %d\n", vcores->eve.value[opp]);
+ do_scale_vcore(vcores->eve.addr, vcores->eve.value[opp],
+ vcores->eve.pmic);
+ /* Configure EVE ABB LDO after scale */
+ abb_setup(vcores->eve.efuse.reg[opp],
+ (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
+ (*prcm)->prm_abbldo_eve_setup,
+ (*prcm)->prm_abbldo_eve_ctrl,
+ (*prcm)->prm_irqstatus_mpu,
+ vcores->eve.abb_tx_done_mask,
+ OMAP_ABB_FAST_OPP);
+
+ opp = get_voltrail_opp(VOLT_IVA);
+ debug("iva: %d\n", vcores->iva.value[opp]);
+ do_scale_vcore(vcores->iva.addr, vcores->iva.value[opp],
+ vcores->iva.pmic);
+ /* Configure IVA ABB LDO after scale */
+ abb_setup(vcores->iva.efuse.reg[opp],
+ (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
+ (*prcm)->prm_abbldo_iva_setup,
+ (*prcm)->prm_abbldo_iva_ctrl,
+ (*prcm)->prm_irqstatus_mpu,
+ vcores->iva.abb_tx_done_mask,
+ OMAP_ABB_FAST_OPP);
+}
+
+static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug("Enable clock domain - %x\n", clkctrl_reg);
+}
+
+static inline void disable_clock_domain(u32 const clkctrl_reg)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug("Disable clock domain - %x\n", clkctrl_reg);
+}
+
+static inline void wait_for_clk_enable(u32 clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+ u32 bound = LDELAY;
+
+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+ MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf("Clock enable failed for 0x%x idlest 0x%x\n",
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
+
+static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
+ u32 wait_for_enable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug("Enable clock module - %x\n", clkctrl_addr);
+ if (wait_for_enable)
+ wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void wait_for_clk_disable(u32 clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
+ u32 bound = LDELAY;
+
+ while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+ MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf("Clock disable failed for 0x%x idlest 0x%x\n",
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
+
+static inline void disable_clock_module(u32 const clkctrl_addr,
+ u32 wait_for_disable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug("Disable clock module - %x\n", clkctrl_addr);
+ if (wait_for_disable)
+ wait_for_clk_disable(clkctrl_addr);
+}
+
+void freq_update_core(void)
+{
+ u32 freq_config1 = 0;
+ const struct dpll_params *core_dpll_params;
+ u32 omap_rev = omap_revision();
+
+ core_dpll_params = get_core_dpll_params(*dplls_data);
+ /* Put EMIF clock domain in sw wakeup mode */
+ enable_clock_domain((*prcm)->cm_memif_clkstctrl,
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
+
+ freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
+ SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
+
+ freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
+ SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
+
+ freq_config1 |= (core_dpll_params->m2 <<
+ SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
+ SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
+
+ writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
+ if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
+ (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
+ puts("FREQ UPDATE procedure failed!!");
+ hang();
+ }
+
+ /*
+ * Putting EMIF in HW_AUTO is seen to be causing issues with
+ * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
+ * in OMAP5430 ES1.0 silicon
+ */
+ if (omap_rev != OMAP5430_ES1_0) {
+ /* Put EMIF clock domain back in hw auto mode */
+ enable_clock_domain((*prcm)->cm_memif_clkstctrl,
+ CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
+ }
+}
+
+void bypass_dpll(u32 const base)
+{
+ do_bypass_dpll(base);
+ wait_for_bypass(base);
+}
+
+void lock_dpll(u32 const base)
+{
+ do_lock_dpll(base);
+ wait_for_lock(base);
+}
+
+static void setup_clocks_for_console(void)
+{
+ /* Do not add any spl_debug prints in this function */
+ clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+ /* Enable all UARTs - console will be on one of them */
+ clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+ clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+ clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+ clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+ clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+}
+
+void do_enable_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_hw_auto,
+ u32 const *clk_modules_explicit_en,
+ u8 wait_for_enable)
+{
+ u32 i, max = 100;
+
+ /* Put the clock domains in SW_WKUP mode */
+ for (i = 0; (i < max) && clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ }
+
+ /* Clock modules that need to be put in HW_AUTO */
+ for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
+ enable_clock_module(clk_modules_hw_auto[i],
+ MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+ wait_for_enable);
+ };
+
+ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+ for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+ enable_clock_module(clk_modules_explicit_en[i],
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+ wait_for_enable);
+ };
+
+ /* Put the clock domains in HW_AUTO mode now */
+ for (i = 0; (i < max) && clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+ }
+}
+
+void do_disable_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_disable,
+ u8 wait_for_disable)
+{
+ u32 i, max = 100;
+
+
+ /* Clock modules that need to be put in SW_DISABLE */
+ for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+ disable_clock_module(clk_modules_disable[i],
+ wait_for_disable);
+
+ /* Put the clock domains in SW_SLEEP mode */
+ for (i = 0; (i < max) && clk_domains[i]; i++)
+ disable_clock_domain(clk_domains[i]);
+}
+
+/**
+ * setup_early_clocks() - Setup early clocks needed for SoC
+ *
+ * Setup clocks for console, SPL basic initialization clocks and initialize
+ * the timer. This is invoked prior prcm_init.
+ */
+void setup_early_clocks(void)
+{
+ switch (omap_hw_init_context()) {
+ case OMAP_INIT_CONTEXT_SPL:
+ case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+ case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+ setup_clocks_for_console();
+ enable_basic_clocks();
+ timer_init();
+ /* Fall through */
+ }
+}
+
+void prcm_init(void)
+{
+ switch (omap_hw_init_context()) {
+ case OMAP_INIT_CONTEXT_SPL:
+ case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+ case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+ scale_vcores(*omap_vcores);
+ setup_dplls();
+ setup_warmreset_time();
+ break;
+ default:
+ break;
+ }
+
+ if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
+ enable_basic_uboot_clocks();
+}
+
+void gpi2c_init(void)
+{
+ static int gpi2c = 1;
+
+ if (gpi2c) {
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+ CONFIG_SYS_OMAP24_I2C_SLAVE);
+ gpi2c = 0;
+ }
+}
diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk
new file mode 100644
index 0000000..5368f6b
--- /dev/null
+++ b/arch/arm/mach-omap2/config.mk
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(srctree)/arch/arm/mach-omap2/config_secure.mk
+
+ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_AM33XX)$(CONFIG_TI_SECURE_DEVICE),yy)
+#
+# For booting from SPI use
+# u-boot-spl_HS_SPI_X-LOADER to program flash
+#
+# On AM43XX:
+#
+# For booting spl from all other media use
+# u-boot-spl_HS_ISSW
+#
+# On AM33XX:
+#
+# For booting spl from NAND flash use
+# u-boot-spl_HS_X-LOADER
+#
+# For booting spl from SD/MMC/eMMC media use
+# u-boot-spl_HS_MLO
+#
+# For booting spl over UART, USB, or Ethernet use
+# u-boot-spl_HS_2ND
+#
+# Refer to README.ti-secure for more info
+#
+ALL-y += u-boot-spl_HS_ISSW
+ALL-y += u-boot-spl_HS_SPI_X-LOADER
+ALL-y += u-boot-spl_HS_X-LOADER
+ALL-y += u-boot-spl_HS_MLO
+ALL-y += u-boot-spl_HS_2ND
+else
+ifeq ($(CONFIG_OMAP54XX)$(CONFIG_TI_SECURE_DEVICE),yy)
+ALL-y += u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER
+else
+ALL-y += MLO
+ifeq ($(CONFIG_AM33XX),y)
+ALL-y += MLO.byteswap
+endif
+endif
+endif
+else
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
+ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img
+endif
+ALL-y += u-boot.img
+endif
diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk
new file mode 100644
index 0000000..0c84333
--- /dev/null
+++ b/arch/arm/mach-omap2/config_secure.mk
@@ -0,0 +1,111 @@
+#
+# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+quiet_cmd_mkomapsecimg = SECURE $@
+ifneq ($(TI_SECURE_DEV_PKG),)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
+ifneq ($(CONFIG_SPL_BUILD),)
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+ $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+else
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+ $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+endif
+else
+cmd_mkomapsecimg = echo "WARNING:" \
+ "$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \
+ "$@ was NOT secured!"; cp $< $@
+endif
+else
+cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
+ "variable must be defined for TI secure devices. \
+ $@ was NOT secured!"; cp $< $@
+endif
+
+ifdef CONFIG_SPL_LOAD_FIT
+quiet_cmd_omapsecureimg = SECURE $@
+ifneq ($(TI_SECURE_DEV_PKG),)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),)
+cmd_omapsecureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \
+ $< $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+else
+cmd_omapsecureimg = echo "WARNING:" \
+ "$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \
+ "$@ was NOT secured!"; cp $< $@
+endif
+else
+cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
+ "variable must be defined for TI secure devices." \
+ "$@ was NOT secured!"; cp $< $@
+endif
+endif
+
+
+# Standard X-LOADER target (QPSI, NOR flash)
+u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkomapsecimg)
+
+# For MLO targets (SD card boot) the final file name that is copied to the SD
+# card FAT partition must be MLO, so we make a copy of the output file to a new
+# file with that name
+u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkomapsecimg)
+ @if [ -f $@ ]; then \
+ cp -f $@ MLO; \
+ fi
+
+# Standard 2ND target (certain peripheral boot modes)
+u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkomapsecimg)
+
+# Standard ULO target (certain peripheral boot modes)
+u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkomapsecimg)
+
+# Standard ISSW target (certain devices, various boot modes)
+u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkomapsecimg)
+
+# For SPI flash on AM335x and AM43xx, these require special byte swap handling
+# so we use the SPI_X-LOADER target instead of X-LOADER and let the
+# create-boot-image.sh script handle that
+u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkomapsecimg)
+
+# For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot
+# file, not an SPL. In this case the mkomapsecimg command looks for a
+# u-boot-HS_* prefix
+u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin FORCE
+ $(call if_changed,mkomapsecimg)
+
+# For supporting the SPL loading and interpreting of FIT images whose
+# components are pre-processed before being integrated into the FIT image in
+# order to secure them in some way
+ifdef CONFIG_SPL_LOAD_FIT
+
+MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
+ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
+
+OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+$(OF_LIST_TARGETS): dtbs
+
+%.dtb_HS: %.dtb FORCE
+ $(call if_changed,omapsecureimg)
+
+u-boot-nodtb_HS.bin: u-boot-nodtb.bin FORCE
+ $(call if_changed,omapsecureimg)
+
+u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%.dtb_HS,$(OF_LIST_TARGETS)) FORCE
+ $(call if_changed,mkimage)
+ $(Q)if [ -f $@ ]; then \
+ cp -f $@ u-boot.img; \
+ fi
+
+endif
diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c
new file mode 100644
index 0000000..b26984e
--- /dev/null
+++ b/arch/arm/mach-omap2/emif-common.c
@@ -0,0 +1,1504 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/emif.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
+#include <asm/utils.h>
+#include <linux/compiler.h>
+
+static int emif1_enabled = -1, emif2_enabled = -1;
+
+void set_lpmode_selfrefresh(u32 base)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 reg;
+
+ reg = readl(&emif->emif_pwr_mgmt_ctrl);
+ reg &= ~EMIF_REG_LP_MODE_MASK;
+ reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
+ reg &= ~EMIF_REG_SR_TIM_MASK;
+ writel(reg, &emif->emif_pwr_mgmt_ctrl);
+
+ /* dummy read for the new SR_TIM to be loaded */
+ readl(&emif->emif_pwr_mgmt_ctrl);
+}
+
+void force_emif_self_refresh()
+{
+ set_lpmode_selfrefresh(EMIF1_BASE);
+ if (!is_dra72x())
+ set_lpmode_selfrefresh(EMIF2_BASE);
+}
+
+inline u32 emif_num(u32 base)
+{
+ if (base == EMIF1_BASE)
+ return 1;
+ else if (base == EMIF2_BASE)
+ return 2;
+ else
+ return 0;
+}
+
+static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
+{
+ u32 mr;
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ mr_addr |= cs << EMIF_REG_CS_SHIFT;
+ writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+ if (omap_revision() == OMAP4430_ES2_0)
+ mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
+ else
+ mr = readl(&emif->emif_lpddr2_mode_reg_data);
+ debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+ cs, mr_addr, mr);
+ if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
+ ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+ ((mr & 0xff000000) >> 24) == (mr & 0xff))
+ return mr & 0xff;
+ else
+ return mr;
+}
+
+static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ mr_addr |= cs << EMIF_REG_CS_SHIFT;
+ writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+ writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
+}
+
+void emif_reset_phy(u32 base)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 iodft;
+
+ iodft = readl(&emif->emif_iodft_tlgc);
+ iodft |= EMIF_REG_RESET_PHY_MASK;
+ writel(iodft, &emif->emif_iodft_tlgc);
+}
+
+static void do_lpddr2_init(u32 base, u32 cs)
+{
+ u32 mr_addr;
+ const struct lpddr2_mr_regs *mr_regs;
+
+ get_lpddr2_mr_regs(&mr_regs);
+ /* Wait till device auto initialization is complete */
+ while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+ ;
+ set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
+ /*
+ * tZQINIT = 1 us
+ * Enough loops assuming a maximum of 2GHz
+ */
+
+ sdelay(2000);
+
+ set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
+ set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
+
+ /*
+ * Enable refresh along with writing MR2
+ * Encoding of RL in MR2 is (RL - 2)
+ */
+ mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+ set_mr(base, cs, mr_addr, mr_regs->mr2);
+
+ if (mr_regs->mr3 > 0)
+ set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
+}
+
+static void lpddr2_init(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ /* Not NVM */
+ clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
+
+ /*
+ * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
+ * when EMIF_SDRAM_CONFIG register is written
+ */
+ setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
+
+ /*
+ * Set the SDRAM_CONFIG and PHY_CTRL for the
+ * un-locked frequency & default RL
+ */
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+ writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+ do_ext_phy_settings(base, regs);
+
+ do_lpddr2_init(base, CS0);
+ if (regs->sdram_config & EMIF_REG_EBANK_MASK)
+ do_lpddr2_init(base, CS1);
+
+ writel(regs->sdram_config, &emif->emif_sdram_config);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+ /* Enable refresh now */
+ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
+
+ }
+
+__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+}
+
+void emif_update_timings(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ if (!is_dra7xx())
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+ else
+ writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
+
+ writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
+ writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
+ writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
+ if (omap_revision() == OMAP4430_ES1_0) {
+ /* ES1 bug EMIF should be in force idle during freq_update */
+ writel(0, &emif->emif_pwr_mgmt_ctrl);
+ } else {
+ writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
+ writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
+ }
+ writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
+ writel(regs->zq_config, &emif->emif_zq_config);
+ writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+
+ if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
+ &emif->emif_l3_config);
+ } else if (omap_revision() >= OMAP4460_ES1_0) {
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+ &emif->emif_l3_config);
+ } else {
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
+ &emif->emif_l3_config);
+ }
+}
+
+#ifndef CONFIG_OMAP44XX
+static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ /* keep sdram in self-refresh */
+ writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
+ & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+ __udelay(130);
+
+ /*
+ * Set invert_clkout (if activated)--DDR_PHYCTRL_1
+ * Invert clock adds an additional half cycle delay on the
+ * command interface. The additional half cycle, is usually
+ * meant to enable leveling in the situation that DQS is later
+ * than CK on the board.It also helps provide some additional
+ * margin for leveling.
+ */
+ writel(regs->emif_ddr_phy_ctlr_1,
+ &emif->emif_ddr_phy_ctrl_1);
+
+ writel(regs->emif_ddr_phy_ctlr_1,
+ &emif->emif_ddr_phy_ctrl_1_shdw);
+ __udelay(130);
+
+ writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
+ & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+
+ /* Launch Full leveling */
+ writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+ /* Wait till full leveling is complete */
+ readl(&emif->emif_rd_wr_lvl_ctl);
+ __udelay(130);
+
+ /* Read data eye leveling no of samples */
+ config_data_eye_leveling_samples(base);
+
+ /*
+ * Launch 8 incremental WR_LVL- to compensate for
+ * PHY limitation.
+ */
+ writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
+ &emif->emif_rd_wr_lvl_ctl);
+
+ __udelay(130);
+
+ /* Launch Incremental leveling */
+ writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
+ __udelay(130);
+}
+
+static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
+ u32 reg, i, phy;
+
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+ phy = readl(&emif->emif_ddr_phy_ctrl_1);
+
+ /* Update PHY_REG_RDDQS_RATIO */
+ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
+ if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
+ for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+ reg = readl(emif_phy_status++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ }
+
+ /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
+ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
+ if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
+ for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+ reg = readl(emif_phy_status++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ }
+
+ /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
+ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
+ emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
+ if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
+ for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+ reg = readl(emif_phy_status++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ writel(reg, emif_ext_phy_ctrl_reg++);
+ }
+
+ /* Disable Leveling */
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+ writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
+}
+
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ /* Clear Error Status */
+ clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+ clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
+ EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
+
+ /* Disable refreshed before leveling */
+ clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
+ EMIF_REG_INITREF_DIS_MASK);
+
+ /* Start Full leveling */
+ writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+ __udelay(300);
+
+ /* Check for leveling timeout */
+ if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
+ printf("Leveling timeout on EMIF%d\n", emif_num(base));
+ return;
+ }
+
+ /* Enable refreshes after leveling */
+ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
+
+ debug("HW leveling success\n");
+ /*
+ * Update slave ratios in EXT_PHY_CTRLx registers
+ * as per HW leveling output
+ */
+ update_hwleveling_output(base, regs);
+}
+
+static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ if (warm_reset()) {
+ emif_reset_phy(base);
+ writel(0x0, &emif->emif_pwr_mgmt_ctrl);
+ }
+ do_ext_phy_settings(base, regs);
+
+ writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
+ &emif->emif_sdram_ref_ctrl);
+ /* Update timing registers */
+ writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+ writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+ writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
+ writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+ writel(regs->zq_config, &emif->emif_zq_config);
+ writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+ writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
+
+ writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
+
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+
+ writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+
+ __udelay(1000);
+
+ writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
+
+ if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
+ dra7_ddr3_leveling(base, regs);
+}
+
+static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+ /*
+ * Set SDRAM_CONFIG and PHY control registers to locked frequency
+ * and RL =7. As the default values of the Mode Registers are not
+ * defined, contents of mode Registers must be fully initialized.
+ * H/W takes care of this initialization
+ */
+ writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+ /* Update timing registers */
+ writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+ writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+ writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+ writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+
+ writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+ do_ext_phy_settings(base, regs);
+
+ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+ omap5_ddr3_leveling(base, regs);
+}
+
+static void ddr3_init(u32 base, const struct emif_regs *regs)
+{
+ if (is_omap54xx())
+ omap5_ddr3_init(base, regs);
+ else
+ dra7_ddr3_init(base, regs);
+}
+#endif
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+
+/*
+ * Organization and refresh requirements for LPDDR2 devices of different
+ * types and densities. Derived from JESD209-2 section 2.4
+ */
+const struct lpddr2_addressing addressing_table[] = {
+ /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
+ {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
+ {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
+ {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
+ {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
+ {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
+ {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
+ {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
+ {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
+ {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
+ {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
+};
+
+static const u32 lpddr2_density_2_size_in_mbytes[] = {
+ 8, /* 64Mb */
+ 16, /* 128Mb */
+ 32, /* 256Mb */
+ 64, /* 512Mb */
+ 128, /* 1Gb */
+ 256, /* 2Gb */
+ 512, /* 4Gb */
+ 1024, /* 8Gb */
+ 2048, /* 16Gb */
+ 4096 /* 32Gb */
+};
+
+/*
+ * Calculate the period of DDR clock from frequency value and set the
+ * denominator and numerator in global variables for easy access later
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+ /*
+ * period = 1/freq
+ * period_in_ns = 10^9/freq
+ */
+ *T_num = 1000000000;
+ *T_den = freq;
+ cancel_out(T_num, T_den, 200);
+
+}
+
+/*
+ * Convert time in nano seconds to number of cycles of DDR clock
+ */
+static inline u32 ns_2_cycles(u32 ns)
+{
+ return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
+}
+
+/*
+ * ns_2_cycles with the difference that the time passed is 2 times the actual
+ * value(to avoid fractions). The cycles returned is for the original value of
+ * the timing parameter
+ */
+static inline u32 ns_x2_2_cycles(u32 ns)
+{
+ return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
+}
+
+/*
+ * Find addressing table index based on the device's type(S2 or S4) and
+ * density
+ */
+s8 addressing_table_index(u8 type, u8 density, u8 width)
+{
+ u8 index;
+ if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
+ return -1;
+
+ /*
+ * Look at the way ADDR_TABLE_INDEX* values have been defined
+ * in emif.h compared to LPDDR2_DENSITY_* values
+ * The table is layed out in the increasing order of density
+ * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
+ * at the end
+ */
+ if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
+ index = ADDR_TABLE_INDEX1GS2;
+ else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
+ index = ADDR_TABLE_INDEX2GS2;
+ else
+ index = density;
+
+ debug("emif: addressing table index %d\n", index);
+
+ return index;
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_ac_timings *get_timings_table(const struct
+ lpddr2_ac_timings const *const *device_timings,
+ u32 freq)
+{
+ u32 i, temp, freq_nearest;
+ const struct lpddr2_ac_timings *timings = 0;
+
+ emif_assert(freq <= MAX_LPDDR2_FREQ);
+ emif_assert(device_timings);
+
+ /*
+ * Start with the maximum allowed frequency - that is always safe
+ */
+ freq_nearest = MAX_LPDDR2_FREQ;
+ /*
+ * Find the timings table that has the max frequency value:
+ * i. Above or equal to the DDR frequency - safe
+ * ii. The lowest that satisfies condition (i) - optimal
+ */
+ for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
+ temp = device_timings[i]->max_freq;
+ if ((temp >= freq) && (temp <= freq_nearest)) {
+ freq_nearest = temp;
+ timings = device_timings[i];
+ }
+ }
+ debug("emif: timings table: %d\n", freq_nearest);
+ return timings;
+}
+
+/*
+ * Finds the value of emif_sdram_config_reg
+ * All parameters are programmed based on the device on CS0.
+ * If there is a device on CS1, it will be same as that on CS0 or
+ * it will be NVM. We don't support NVM yet.
+ * If cs1_device pointer is NULL it is assumed that there is no device
+ * on CS1
+ */
+static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
+ const struct lpddr2_device_details *cs1_device,
+ const struct lpddr2_addressing *addressing,
+ u8 RL)
+{
+ u32 config_reg = 0;
+
+ config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
+ config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
+ EMIF_REG_IBANK_POS_SHIFT;
+
+ config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
+
+ config_reg |= RL << EMIF_REG_CL_SHIFT;
+
+ config_reg |= addressing->row_sz[cs0_device->io_width] <<
+ EMIF_REG_ROWSIZE_SHIFT;
+
+ config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
+
+ config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
+ EMIF_REG_EBANK_SHIFT;
+
+ config_reg |= addressing->col_sz[cs0_device->io_width] <<
+ EMIF_REG_PAGESIZE_SHIFT;
+
+ return config_reg;
+}
+
+static u32 get_sdram_ref_ctrl(u32 freq,
+ const struct lpddr2_addressing *addressing)
+{
+ u32 ref_ctrl = 0, val = 0, freq_khz;
+ freq_khz = freq / 1000;
+ /*
+ * refresh rate to be set is 'tREFI * freq in MHz
+ * division by 10000 to account for khz and x10 in t_REFI_us_x10
+ */
+ val = addressing->t_REFI_us_x10 * freq_khz / 10000;
+ ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
+
+ return ref_ctrl;
+}
+
+static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
+ const struct lpddr2_min_tck *min_tck,
+ const struct lpddr2_addressing *addressing)
+{
+ u32 tim1 = 0, val = 0;
+ val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
+ tim1 |= val << EMIF_REG_T_WTR_SHIFT;
+
+ if (addressing->num_banks == BANKS8)
+ val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
+ (4 * (*T_num)) - 1;
+ else
+ val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
+
+ tim1 |= val << EMIF_REG_T_RRD_SHIFT;
+
+ val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
+ tim1 |= val << EMIF_REG_T_RC_SHIFT;
+
+ val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
+ tim1 |= val << EMIF_REG_T_RAS_SHIFT;
+
+ val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
+ tim1 |= val << EMIF_REG_T_WR_SHIFT;
+
+ val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
+ tim1 |= val << EMIF_REG_T_RCD_SHIFT;
+
+ val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
+ tim1 |= val << EMIF_REG_T_RP_SHIFT;
+
+ return tim1;
+}
+
+static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
+ const struct lpddr2_min_tck *min_tck)
+{
+ u32 tim2 = 0, val = 0;
+ val = max(min_tck->tCKE, timings->tCKE) - 1;
+ tim2 |= val << EMIF_REG_T_CKE_SHIFT;
+
+ val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
+ tim2 |= val << EMIF_REG_T_RTP_SHIFT;
+
+ /*
+ * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
+ * same value
+ */
+ val = ns_2_cycles(timings->tXSR) - 1;
+ tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
+ tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
+
+ val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
+ tim2 |= val << EMIF_REG_T_XP_SHIFT;
+
+ return tim2;
+}
+
+static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
+ const struct lpddr2_min_tck *min_tck,
+ const struct lpddr2_addressing *addressing)
+{
+ u32 tim3 = 0, val = 0;
+ val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
+ tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
+
+ val = ns_2_cycles(timings->tRFCab) - 1;
+ tim3 |= val << EMIF_REG_T_RFC_SHIFT;
+
+ val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
+ tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
+
+ val = ns_2_cycles(timings->tZQCS) - 1;
+ tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
+
+ val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
+ tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
+
+ return tim3;
+}
+
+static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
+ const struct lpddr2_addressing *addressing,
+ u8 volt_ramp)
+{
+ u32 zq = 0, val = 0;
+ if (volt_ramp)
+ val =
+ EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
+ addressing->t_REFI_us_x10;
+ else
+ val =
+ EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
+ addressing->t_REFI_us_x10;
+ zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
+
+ zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
+
+ zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
+
+ zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
+
+ /*
+ * Assuming that two chipselects have a single calibration resistor
+ * If there are indeed two calibration resistors, then this flag should
+ * be enabled to take advantage of dual calibration feature.
+ * This data should ideally come from board files. But considering
+ * that none of the boards today have calibration resistors per CS,
+ * it would be an unnecessary overhead.
+ */
+ zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
+
+ zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
+
+ zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
+
+ return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
+ const struct lpddr2_addressing *addressing,
+ u8 is_derated)
+{
+ u32 alert = 0, interval;
+ interval =
+ TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
+ if (is_derated)
+ interval *= 4;
+ alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
+
+ alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
+
+ alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
+
+ alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
+
+ alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
+
+ alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
+
+ return alert;
+}
+
+static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
+{
+ u32 idle = 0, val = 0;
+ if (volt_ramp)
+ val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
+ else
+ /*Maximum value in normal conditions - suggested by hw team */
+ val = 0x1FF;
+ idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
+
+ idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
+
+ return idle;
+}
+
+static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
+{
+ u32 phy = 0, val = 0;
+
+ phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
+
+ if (freq <= 100000000)
+ val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
+ else if (freq <= 200000000)
+ val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
+ else
+ val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
+ phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
+
+ /* Other fields are constant magic values. Hardcode them together */
+ phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
+ EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
+
+ return phy;
+}
+
+static u32 get_emif_mem_size(u32 base)
+{
+ u32 size_mbytes = 0, temp;
+ struct emif_device_details dev_details;
+ struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+ u32 emif_nr = emif_num(base);
+
+ emif_reset_phy(base);
+ dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
+ &cs0_dev_details);
+ dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
+ &cs1_dev_details);
+ emif_reset_phy(base);
+
+ if (dev_details.cs0_device_details) {
+ temp = dev_details.cs0_device_details->density;
+ size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+ }
+
+ if (dev_details.cs1_device_details) {
+ temp = dev_details.cs1_device_details->density;
+ size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+ }
+ /* convert to bytes */
+ return size_mbytes << 20;
+}
+
+/* Gets the encoding corresponding to a given DMM section size */
+u32 get_dmm_section_size_map(u32 section_size)
+{
+ /*
+ * Section size mapping:
+ * 0x0: 16-MiB section
+ * 0x1: 32-MiB section
+ * 0x2: 64-MiB section
+ * 0x3: 128-MiB section
+ * 0x4: 256-MiB section
+ * 0x5: 512-MiB section
+ * 0x6: 1-GiB section
+ * 0x7: 2-GiB section
+ */
+ section_size >>= 24; /* divide by 16 MB */
+ return log_2_n_round_down(section_size);
+}
+
+static void emif_calculate_regs(
+ const struct emif_device_details *emif_dev_details,
+ u32 freq, struct emif_regs *regs)
+{
+ u32 temp, sys_freq;
+ const struct lpddr2_addressing *addressing;
+ const struct lpddr2_ac_timings *timings;
+ const struct lpddr2_min_tck *min_tck;
+ const struct lpddr2_device_details *cs0_dev_details =
+ emif_dev_details->cs0_device_details;
+ const struct lpddr2_device_details *cs1_dev_details =
+ emif_dev_details->cs1_device_details;
+ const struct lpddr2_device_timings *cs0_dev_timings =
+ emif_dev_details->cs0_device_timings;
+
+ emif_assert(emif_dev_details);
+ emif_assert(regs);
+ /*
+ * You can not have a device on CS1 without one on CS0
+ * So configuring EMIF without a device on CS0 doesn't
+ * make sense
+ */
+ emif_assert(cs0_dev_details);
+ emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
+ /*
+ * If there is a device on CS1 it should be same type as CS0
+ * (or NVM. But NVM is not supported in this driver yet)
+ */
+ emif_assert((cs1_dev_details == NULL) ||
+ (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
+ (cs0_dev_details->type == cs1_dev_details->type));
+ emif_assert(freq <= MAX_LPDDR2_FREQ);
+
+ set_ddr_clk_period(freq);
+
+ /*
+ * The device on CS0 is used for all timing calculations
+ * There is only one set of registers for timings per EMIF. So, if the
+ * second CS(CS1) has a device, it should have the same timings as the
+ * device on CS0
+ */
+ timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
+ emif_assert(timings);
+ min_tck = cs0_dev_timings->min_tck;
+
+ temp = addressing_table_index(cs0_dev_details->type,
+ cs0_dev_details->density,
+ cs0_dev_details->io_width);
+
+ emif_assert((temp >= 0));
+ addressing = &(addressing_table[temp]);
+ emif_assert(addressing);
+
+ sys_freq = get_sys_clk_freq();
+
+ regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
+ cs1_dev_details,
+ addressing, RL_BOOT);
+
+ regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
+ cs1_dev_details,
+ addressing, RL_FINAL);
+
+ regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
+
+ regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
+
+ regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
+
+ regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
+
+ regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
+
+ regs->temp_alert_config =
+ get_temp_alert_config(cs1_dev_details, addressing, 0);
+
+ regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
+ LPDDR2_VOLTAGE_STABLE);
+
+ regs->emif_ddr_phy_ctlr_1_init =
+ get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
+
+ regs->emif_ddr_phy_ctlr_1 =
+ get_ddr_phy_ctrl_1(freq, RL_FINAL);
+
+ regs->freq = freq;
+
+ print_timing_reg(regs->sdram_config_init);
+ print_timing_reg(regs->sdram_config);
+ print_timing_reg(regs->ref_ctrl);
+ print_timing_reg(regs->sdram_tim1);
+ print_timing_reg(regs->sdram_tim2);
+ print_timing_reg(regs->sdram_tim3);
+ print_timing_reg(regs->read_idle_ctrl);
+ print_timing_reg(regs->temp_alert_config);
+ print_timing_reg(regs->zq_config);
+ print_timing_reg(regs->emif_ddr_phy_ctlr_1);
+ print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
+}
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+const char *get_lpddr2_type(u8 type_id)
+{
+ switch (type_id) {
+ case LPDDR2_TYPE_S4:
+ return "LPDDR2-S4";
+ case LPDDR2_TYPE_S2:
+ return "LPDDR2-S2";
+ default:
+ return NULL;
+ }
+}
+
+const char *get_lpddr2_io_width(u8 width_id)
+{
+ switch (width_id) {
+ case LPDDR2_IO_WIDTH_8:
+ return "x8";
+ case LPDDR2_IO_WIDTH_16:
+ return "x16";
+ case LPDDR2_IO_WIDTH_32:
+ return "x32";
+ default:
+ return NULL;
+ }
+}
+
+const char *get_lpddr2_manufacturer(u32 manufacturer)
+{
+ switch (manufacturer) {
+ case LPDDR2_MANUFACTURER_SAMSUNG:
+ return "Samsung";
+ case LPDDR2_MANUFACTURER_QIMONDA:
+ return "Qimonda";
+ case LPDDR2_MANUFACTURER_ELPIDA:
+ return "Elpida";
+ case LPDDR2_MANUFACTURER_ETRON:
+ return "Etron";
+ case LPDDR2_MANUFACTURER_NANYA:
+ return "Nanya";
+ case LPDDR2_MANUFACTURER_HYNIX:
+ return "Hynix";
+ case LPDDR2_MANUFACTURER_MOSEL:
+ return "Mosel";
+ case LPDDR2_MANUFACTURER_WINBOND:
+ return "Winbond";
+ case LPDDR2_MANUFACTURER_ESMT:
+ return "ESMT";
+ case LPDDR2_MANUFACTURER_SPANSION:
+ return "Spansion";
+ case LPDDR2_MANUFACTURER_SST:
+ return "SST";
+ case LPDDR2_MANUFACTURER_ZMOS:
+ return "ZMOS";
+ case LPDDR2_MANUFACTURER_INTEL:
+ return "Intel";
+ case LPDDR2_MANUFACTURER_NUMONYX:
+ return "Numonyx";
+ case LPDDR2_MANUFACTURER_MICRON:
+ return "Micron";
+ default:
+ return NULL;
+ }
+}
+
+static void display_sdram_details(u32 emif_nr, u32 cs,
+ struct lpddr2_device_details *device)
+{
+ const char *mfg_str;
+ const char *type_str;
+ char density_str[10];
+ u32 density;
+
+ debug("EMIF%d CS%d\t", emif_nr, cs);
+
+ if (!device) {
+ debug("None\n");
+ return;
+ }
+
+ mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+ type_str = get_lpddr2_type(device->type);
+
+ density = lpddr2_density_2_size_in_mbytes[device->density];
+ if ((density / 1024 * 1024) == density) {
+ density /= 1024;
+ sprintf(density_str, "%d GB", density);
+ } else
+ sprintf(density_str, "%d MB", density);
+ if (mfg_str && type_str)
+ debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+ struct lpddr2_device_details *lpddr2_device)
+{
+ u32 mr = 0, temp;
+
+ mr = get_mr(base, cs, LPDDR2_MR0);
+ if (mr > 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
+ if (temp) {
+ /* Not SDRAM */
+ return 0;
+ }
+ temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
+
+ if (temp) {
+ /* DNV supported - But DNV is only supported for NVM */
+ return 0;
+ }
+
+ mr = get_mr(base, cs, LPDDR2_MR4);
+ if (mr > 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ mr = get_mr(base, cs, LPDDR2_MR5);
+ if (mr > 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ if (!get_lpddr2_manufacturer(mr)) {
+ /* Manufacturer not identified */
+ return 0;
+ }
+ lpddr2_device->manufacturer = mr;
+
+ mr = get_mr(base, cs, LPDDR2_MR6);
+ if (mr >= 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ mr = get_mr(base, cs, LPDDR2_MR7);
+ if (mr >= 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ mr = get_mr(base, cs, LPDDR2_MR8);
+ if (mr >= 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
+ if (!get_lpddr2_type(temp)) {
+ /* Not SDRAM */
+ return 0;
+ }
+ lpddr2_device->type = temp;
+
+ temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
+ if (temp > LPDDR2_DENSITY_32Gb) {
+ /* Density not supported */
+ return 0;
+ }
+ lpddr2_device->density = temp;
+
+ temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
+ if (!get_lpddr2_io_width(temp)) {
+ /* IO width unsupported value */
+ return 0;
+ }
+ lpddr2_device->io_width = temp;
+
+ /*
+ * If all the above tests pass we should
+ * have a device on this chip-select
+ */
+ return 1;
+}
+
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details)
+{
+ u32 phy;
+ u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
+
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ if (!lpddr2_dev_details)
+ return NULL;
+
+ /* Do the minimum init for mode register accesses */
+ if (!(running_from_sdram() || warm_reset())) {
+ phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
+ writel(phy, &emif->emif_ddr_phy_ctrl_1);
+ }
+
+ if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+ return NULL;
+
+ display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+ return lpddr2_dev_details;
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
+static void do_sdram_init(u32 base)
+{
+ const struct emif_regs *regs;
+ u32 in_sdram, emif_nr;
+
+ debug(">>do_sdram_init() %x\n", base);
+
+ in_sdram = running_from_sdram();
+ emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+ emif_get_reg_dump(emif_nr, ®s);
+ if (!regs) {
+ debug("EMIF: reg dump not provided\n");
+ return;
+ }
+#else
+ /*
+ * The user has not provided the register values. We need to
+ * calculate it based on the timings and the DDR frequency
+ */
+ struct emif_device_details dev_details;
+ struct emif_regs calculated_regs;
+
+ /*
+ * Get device details:
+ * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
+ * - Obtained from user otherwise
+ */
+ struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+ emif_reset_phy(base);
+ dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
+ &cs0_dev_details);
+ dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
+ &cs1_dev_details);
+ emif_reset_phy(base);
+
+ /* Return if no devices on this EMIF */
+ if (!dev_details.cs0_device_details &&
+ !dev_details.cs1_device_details) {
+ return;
+ }
+
+ /*
+ * Get device timings:
+ * - Default timings specified by JESD209-2 if
+ * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
+ * - Obtained from user otherwise
+ */
+ emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
+ &dev_details.cs1_device_timings);
+
+ /* Calculate the register values */
+ emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
+ regs = &calculated_regs;
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+ /*
+ * Initializing the DDR device can not happen from SDRAM.
+ * Changing the timing registers in EMIF can happen(going from one
+ * OPP to another)
+ */
+ if (!in_sdram && (!warm_reset() || is_dra7xx())) {
+ if (emif_sdram_type(regs->sdram_config) ==
+ EMIF_SDRAM_TYPE_LPDDR2)
+ lpddr2_init(base, regs);
+#ifndef CONFIG_OMAP44XX
+ else
+ ddr3_init(base, regs);
+#endif
+ }
+#ifdef CONFIG_OMAP54X
+ if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
+ EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
+ set_lpmode_selfrefresh(base);
+ emif_reset_phy(base);
+ omap5_ddr3_leveling(base, regs);
+ }
+#endif
+
+ /* Write to the shadow registers */
+ emif_update_timings(base, regs);
+
+ debug("<<do_sdram_init() %x\n", base);
+}
+
+void emif_post_init_config(u32 base)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 omap_rev = omap_revision();
+
+ /* reset phy on ES2.0 */
+ if (omap_rev == OMAP4430_ES2_0)
+ emif_reset_phy(base);
+
+ /* Put EMIF back in smart idle on ES1.0 */
+ if (omap_rev == OMAP4430_ES1_0)
+ writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
+}
+
+void dmm_init(u32 base)
+{
+ const struct dmm_lisa_map_regs *lisa_map_regs;
+ u32 i, section, valid;
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+ emif_get_dmm_regs(&lisa_map_regs);
+#else
+ u32 emif1_size, emif2_size, mapped_size, section_map = 0;
+ u32 section_cnt, sys_addr;
+ struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
+
+ mapped_size = 0;
+ section_cnt = 3;
+ sys_addr = CONFIG_SYS_SDRAM_BASE;
+ emif1_size = get_emif_mem_size(EMIF1_BASE);
+ emif2_size = get_emif_mem_size(EMIF2_BASE);
+ debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
+
+ if (!emif1_size && !emif2_size)
+ return;
+
+ /* symmetric interleaved section */
+ if (emif1_size && emif2_size) {
+ mapped_size = min(emif1_size, emif2_size);
+ section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
+ section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
+ /* only MSB */
+ section_map |= (sys_addr >> 24) <<
+ EMIF_SYS_ADDR_SHIFT;
+ section_map |= get_dmm_section_size_map(mapped_size * 2)
+ << EMIF_SYS_SIZE_SHIFT;
+ lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+ emif1_size -= mapped_size;
+ emif2_size -= mapped_size;
+ sys_addr += (mapped_size * 2);
+ section_cnt--;
+ }
+
+ /*
+ * Single EMIF section(we can have a maximum of 1 single EMIF
+ * section- either EMIF1 or EMIF2 or none, but not both)
+ */
+ if (emif1_size) {
+ section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
+ section_map |= get_dmm_section_size_map(emif1_size)
+ << EMIF_SYS_SIZE_SHIFT;
+ /* only MSB */
+ section_map |= (mapped_size >> 24) <<
+ EMIF_SDRC_ADDR_SHIFT;
+ /* only MSB */
+ section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
+ section_cnt--;
+ }
+ if (emif2_size) {
+ section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
+ section_map |= get_dmm_section_size_map(emif2_size) <<
+ EMIF_SYS_SIZE_SHIFT;
+ /* only MSB */
+ section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
+ /* only MSB */
+ section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
+ section_cnt--;
+ }
+
+ if (section_cnt == 2) {
+ /* Only 1 section - either symmetric or single EMIF */
+ lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+ lis_map_regs_calculated.dmm_lisa_map_2 = 0;
+ lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+ } else {
+ /* 2 sections - 1 symmetric, 1 single EMIF */
+ lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
+ lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+ }
+
+ /* TRAP for invalid TILER mappings in section 0 */
+ lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
+
+ if (omap_revision() >= OMAP4460_ES1_0)
+ lis_map_regs_calculated.is_ma_present = 1;
+
+ lisa_map_regs = &lis_map_regs_calculated;
+#endif
+ struct dmm_lisa_map_regs *hw_lisa_map_regs =
+ (struct dmm_lisa_map_regs *)base;
+
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+ writel(lisa_map_regs->dmm_lisa_map_3,
+ &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(lisa_map_regs->dmm_lisa_map_2,
+ &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(lisa_map_regs->dmm_lisa_map_1,
+ &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(lisa_map_regs->dmm_lisa_map_0,
+ &hw_lisa_map_regs->dmm_lisa_map_0);
+
+ if (lisa_map_regs->is_ma_present) {
+ hw_lisa_map_regs =
+ (struct dmm_lisa_map_regs *)MA_BASE;
+
+ writel(lisa_map_regs->dmm_lisa_map_3,
+ &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(lisa_map_regs->dmm_lisa_map_2,
+ &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(lisa_map_regs->dmm_lisa_map_1,
+ &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(lisa_map_regs->dmm_lisa_map_0,
+ &hw_lisa_map_regs->dmm_lisa_map_0);
+
+ setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
+ }
+
+ /*
+ * EMIF should be configured only when
+ * memory is mapped on it. Using emif1_enabled
+ * and emif2_enabled variables for this.
+ */
+ emif1_enabled = 0;
+ emif2_enabled = 0;
+ for (i = 0; i < 4; i++) {
+ section = __raw_readl(DMM_BASE + i*4);
+ valid = (section & EMIF_SDRC_MAP_MASK) >>
+ (EMIF_SDRC_MAP_SHIFT);
+ if (valid == 3) {
+ emif1_enabled = 1;
+ emif2_enabled = 1;
+ break;
+ }
+
+ if (valid == 1)
+ emif1_enabled = 1;
+
+ if (valid == 2)
+ emif2_enabled = 1;
+ }
+}
+
+static void do_bug0039_workaround(u32 base)
+{
+ u32 val, i, clkctrl;
+ struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
+ const struct read_write_regs *bug_00339_regs;
+ u32 iterations;
+ u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
+ u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
+
+ if (is_dra7xx())
+ phy_status_base++;
+
+ bug_00339_regs = get_bug_regs(&iterations);
+
+ /* Put EMIF in to idle */
+ clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
+ __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
+
+ /* Copy the phy status registers in to phy ctrl shadow registers */
+ for (i = 0; i < iterations; i++) {
+ val = __raw_readl(phy_status_base +
+ bug_00339_regs[i].read_reg - 1);
+
+ __raw_writel(val, phy_ctrl_base +
+ ((bug_00339_regs[i].write_reg - 1) << 1));
+
+ __raw_writel(val, phy_ctrl_base +
+ (bug_00339_regs[i].write_reg << 1) - 1);
+ }
+
+ /* Disable leveling */
+ writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
+
+ __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
+}
+
+/*
+ * SDRAM initialization:
+ * SDRAM initialization has two parts:
+ * 1. Configuring the SDRAM device
+ * 2. Update the AC timings related parameters in the EMIF module
+ * (1) should be done only once and should not be done while we are
+ * running from SDRAM.
+ * (2) can and should be done more than once if OPP changes.
+ * Particularly, this may be needed when we boot without SPL and
+ * and using Configuration Header(CH). ROM code supports only at 50% OPP
+ * at boot (low power boot). So u-boot has to switch to OPP100 and update
+ * the frequency. So,
+ * Doing (1) and (2) makes sense - first time initialization
+ * Doing (2) and not (1) makes sense - OPP change (when using CH)
+ * Doing (1) and not (2) doen't make sense
+ * See do_sdram_init() for the details
+ */
+void sdram_init(void)
+{
+ u32 in_sdram, size_prog, size_detect;
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+ u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
+
+ debug(">>sdram_init()\n");
+
+ if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+ return;
+
+ in_sdram = running_from_sdram();
+ debug("in_sdram = %d\n", in_sdram);
+
+ if (!in_sdram) {
+ if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
+ bypass_dpll((*prcm)->cm_clkmode_dpll_core);
+ else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
+ writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
+ }
+
+ if (!in_sdram)
+ dmm_init(DMM_BASE);
+
+ if (emif1_enabled)
+ do_sdram_init(EMIF1_BASE);
+
+ if (emif2_enabled)
+ do_sdram_init(EMIF2_BASE);
+
+ if (!(in_sdram || warm_reset())) {
+ if (emif1_enabled)
+ emif_post_init_config(EMIF1_BASE);
+ if (emif2_enabled)
+ emif_post_init_config(EMIF2_BASE);
+ }
+
+ /* for the shadow registers to take effect */
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+ freq_update_core();
+
+ /* Do some testing after the init */
+ if (!in_sdram) {
+ size_prog = omap_sdram_size();
+ size_prog = log_2_n_round_down(size_prog);
+ size_prog = (1 << size_prog);
+
+ size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ size_prog);
+ /* Compare with the size programmed */
+ if (size_detect != size_prog) {
+ printf("SDRAM: identified size not same as expected"
+ " size identified: %x expected: %x\n",
+ size_detect,
+ size_prog);
+ } else
+ debug("get_ram_size() successful");
+ }
+
+#if defined(CONFIG_TI_SECURE_DEVICE)
+ /*
+ * On HS devices, do static EMIF firewall configuration
+ * but only do it if not already running in SDRAM
+ */
+ if (!in_sdram)
+ if (0 != secure_emif_reserve())
+ hang();
+
+ /* On HS devices, ensure static EMIF firewall APIs are locked */
+ if (0 != secure_emif_firewall_lock())
+ hang();
+#endif
+
+ if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
+ (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
+ if (emif1_enabled)
+ do_bug0039_workaround(EMIF1_BASE);
+ if (emif2_enabled)
+ do_bug0039_workaround(EMIF2_BASE);
+ }
+
+ debug("<<sdram_init()\n");
+}
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/hwinit-common.c
rename to arch/arm/mach-omap2/hwinit-common.c
diff --git a/arch/arm/mach-omap2/lowlevel_init.S b/arch/arm/mach-omap2/lowlevel_init.S
new file mode 100644
index 0000000..8ce12c8
--- /dev/null
+++ b/arch/arm/mach-omap2/lowlevel_init.S
@@ -0,0 +1,90 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+#include <asm/arch/spl.h>
+#include <linux/linkage.h>
+
+.arch_extension sec
+
+#ifdef CONFIG_SPL
+ENTRY(save_boot_params)
+ ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
+ str r0, [r1]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
+ENTRY(switch_to_hypervisor)
+
+/*
+ * Switch to hypervisor mode
+ */
+ adr r0, save_sp
+ str sp, [r0]
+ adr r1, restore_from_hyp
+ ldr r0, =0x102
+ b omap_smc1
+restore_from_hyp:
+ adr r0, save_sp
+ ldr sp, [r0]
+ MRC p15, 4, R0, c1, c0, 0
+ ldr r1, =0X1004 @Set cache enable bits for hypervisor mode
+ orr r0, r0, r1
+ MCR p15, 4, R0, c1, c0, 0
+ b switch_to_hypervisor_ret
+save_sp:
+ .word 0x0
+ENDPROC(switch_to_hypervisor)
+#endif
+#endif
+
+ENTRY(omap_smc1)
+ push {r4-r12, lr} @ save registers - ROM code may pollute
+ @ our registers
+ mov r12, r0 @ Service
+ mov r0, r1 @ Argument
+
+ dsb
+ dmb
+ smc 0 @ SMC #0 to enter monitor mode
+ @ call ROM Code API for the service requested
+ pop {r4-r12, pc}
+ENDPROC(omap_smc1)
+
+ENTRY(omap_smc_sec)
+ push {r4-r12, lr} @ save registers - ROM code may pollute
+ @ our registers
+ mov r6, #0xFF @ Indicate new Task call
+ mov r12, #0x00 @ Secure Service ID in R12
+
+ dsb
+ dmb
+ smc 0 @ SMC #0 to enter monitor mode
+
+ b omap_smc_sec_end @ exit at end of the service execution
+ nop
+
+ @ In case of IRQ happening in Secure, then ARM will branch here.
+ @ At that moment, IRQ will be pending and ARM will jump to Non Secure
+ @ IRQ handler
+ mov r12, #0xFE
+
+ dsb
+ dmb
+ smc 0 @ SMC #0 to enter monitor mode
+
+omap_smc_sec_end:
+ pop {r4-r12, pc}
+ENDPROC(omap_smc_sec)
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/mach-omap2/mem-common.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/mem-common.c
rename to arch/arm/mach-omap2/mem-common.c
diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c
new file mode 100644
index 0000000..b37163a
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-cache.c
@@ -0,0 +1,77 @@
+/*
+ *
+ * Common functions for OMAP4/5 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Without LPAE short descriptors are used
+ * Set C - Cache Bit3
+ * Set B - Buffer Bit2
+ * The last 2 bits set to 0b10
+ * Do Not set XN bit4
+ * So value is 0xe
+ *
+ * With LPAE cache configuration happens via MAIR0 register
+ * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
+ * 0xFF maps to Cache writeback with Read and Write Allocate set
+ * The bits[1:0] should have the value 0b01 for the first level
+ * descriptor.
+ * So the value is 0xd
+ */
+
+#ifdef CONFIG_ARMV7_LPAE
+#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
+#else
+#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
+#endif
+
+#define ARMV7_DOMAIN_CLIENT 1
+#define ARMV7_DOMAIN_MASK (0x3 << 0)
+
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+ bd_t *bd = gd->bd;
+ int i;
+
+ u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+ u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+ u32 end = start + size;
+
+ debug("%s: bank: %d\n", __func__, bank);
+ for (i = start; i < end; i++)
+ set_section_dcache(i, ARMV7_DCACHE_POLICY);
+}
+
+void arm_init_domains(void)
+{
+ u32 reg;
+
+ reg = get_dacr();
+ /*
+ * Set DOMAIN to client access so that all permissions
+ * set in pagetables are validated by the mmu.
+ */
+ reg &= ~ARMV7_DOMAIN_MASK;
+ reg |= ARMV7_DOMAIN_CLIENT;
+ set_dacr(reg);
+}
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
new file mode 100644
index 0000000..7d884a2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -0,0 +1,154 @@
+if OMAP34XX
+
+config SPL_EXT_SUPPORT
+ default y
+
+config SPL_FAT_SUPPORT
+ default y
+
+config SPL_GPIO_SUPPORT
+ default y
+
+config SPL_I2C_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ default y
+
+config SPL_NAND_SUPPORT
+ default y
+
+config SPL_POWER_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+choice
+ prompt "OMAP3 board select"
+ optional
+
+config TARGET_AM3517_EVM
+ bool "AM3517 EVM"
+
+config TARGET_MT_VENTOUX
+ bool "TeeJet Mt.Ventoux"
+
+config TARGET_OMAP3_BEAGLE
+ bool "TI OMAP3 BeagleBoard"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_CM_T35
+ bool "CompuLab CM-T3530 and CM-T3730 boards"
+
+config TARGET_CM_T3517
+ bool "CompuLab CM-T3517 boards"
+
+config TARGET_DEVKIT8000
+ bool "TimLL OMAP3 Devkit8000"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_OMAP3_EVM
+ bool "TI OMAP3 EVM"
+
+config TARGET_OMAP3_IGEP00X0
+ bool "IGEP"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_OMAP3_OVERO
+ bool "OMAP35xx Gumstix Overo"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_OMAP3_ZOOM1
+ bool "TI Zoom1"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_AM3517_CRANE
+ bool "am3517_crane"
+
+config TARGET_OMAP3_PANDORA
+ bool "OMAP3 Pandora"
+
+config TARGET_ECO5PK
+ bool "ECO5PK"
+
+config TARGET_TRICORDER
+ bool "Tricorder"
+
+config TARGET_MCX
+ bool "MCX"
+
+config TARGET_OMAP3_LOGIC
+ bool "OMAP3 Logic"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_NOKIA_RX51
+ bool "Nokia RX51"
+
+config TARGET_TAO3530
+ bool "TAO3530"
+
+config TARGET_TWISTER
+ bool "Twister"
+
+config TARGET_OMAP3_CAIRO
+ bool "QUIPOS CAIRO"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_SNIPER
+ bool "LG Optimus Black"
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+endchoice
+
+config SYS_SOC
+ default "omap3"
+
+source "board/logicpd/am3517evm/Kconfig"
+source "board/teejet/mt_ventoux/Kconfig"
+source "board/ti/beagle/Kconfig"
+source "board/compulab/cm_t35/Kconfig"
+source "board/compulab/cm_t3517/Kconfig"
+source "board/timll/devkit8000/Kconfig"
+source "board/ti/evm/Kconfig"
+source "board/isee/igep00x0/Kconfig"
+source "board/overo/Kconfig"
+source "board/logicpd/zoom1/Kconfig"
+source "board/ti/am3517crane/Kconfig"
+source "board/pandora/Kconfig"
+source "board/8dtech/eco5pk/Kconfig"
+source "board/corscience/tricorder/Kconfig"
+source "board/htkw/mcx/Kconfig"
+source "board/logicpd/omap3som/Kconfig"
+source "board/nokia/rx51/Kconfig"
+source "board/technexion/tao3530/Kconfig"
+source "board/technexion/twister/Kconfig"
+source "board/quipos/cairo/Kconfig"
+source "board/lg/sniper/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/mach-omap2/omap3/Makefile
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/Makefile
rename to arch/arm/mach-omap2/omap3/Makefile
diff --git a/arch/arm/mach-omap2/omap3/am35x_musb.c b/arch/arm/mach-omap2/omap3/am35x_musb.c
new file mode 100644
index 0000000..d542699
--- /dev/null
+++ b/arch/arm/mach-omap2/omap3/am35x_musb.c
@@ -0,0 +1,61 @@
+/*
+ * This file configures the internal USB PHY in AM35X.
+ *
+ * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
+ *
+ * Based on omap_phy_internal.c code from Linux by
+ * Hema HK <hemahk@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/am35x_def.h>
+
+void am35x_musb_reset(struct udevice *dev)
+{
+ /* Reset the musb interface */
+ clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
+ 0, USBOTGSS_SW_RST);
+ clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
+ USBOTGSS_SW_RST, 0);
+}
+
+void am35x_musb_phy_power(struct udevice *dev, u8 on)
+{
+ unsigned long start = get_timer(0);
+
+ if (on) {
+ /*
+ * Start the on-chip PHY and its PLL.
+ */
+ clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+ CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
+ CONF2_PHY_PLLON);
+
+ debug("Waiting for PHY clock good...\n");
+ while (!(readl(&am35x_scm_general_regs->devconf2)
+ & CONF2_PHYCLKGD)) {
+
+ if (get_timer(start) > CONFIG_SYS_HZ / 10) {
+ printf("musb PHY clock good timed out\n");
+ break;
+ }
+ }
+ } else {
+ /*
+ * Power down the on-chip PHY.
+ */
+ clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+ CONF2_PHY_PLLON,
+ CONF2_PHYPWRDN | CONF2_OTGPWRDN);
+ }
+}
+
+void am35x_musb_clear_irq(struct udevice *dev)
+{
+ clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
+ 0, USBOTGSS_INT_CLR);
+ readl(&am35x_scm_general_regs->lvl_intr_clr);
+}
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/board.c
rename to arch/arm/mach-omap2/omap3/board.c
diff --git a/arch/arm/cpu/armv7/omap3/boot.c b/arch/arm/mach-omap2/omap3/boot.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/boot.c
rename to arch/arm/mach-omap2/omap3/boot.c
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/clock.c
rename to arch/arm/mach-omap2/omap3/clock.c
diff --git a/arch/arm/cpu/armv7/omap3/emac.c b/arch/arm/mach-omap2/omap3/emac.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/emac.c
rename to arch/arm/mach-omap2/omap3/emac.c
diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/emif4.c
rename to arch/arm/mach-omap2/omap3/emif4.c
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/lowlevel_init.S
rename to arch/arm/mach-omap2/omap3/lowlevel_init.S
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/sdrc.c
rename to arch/arm/mach-omap2/omap3/sdrc.c
diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/mach-omap2/omap3/spl_id_nand.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/spl_id_nand.c
rename to arch/arm/mach-omap2/omap3/spl_id_nand.c
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/mach-omap2/omap3/sys_info.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap3/sys_info.c
rename to arch/arm/mach-omap2/omap3/sys_info.c
diff --git a/arch/arm/mach-omap2/omap4/Kconfig b/arch/arm/mach-omap2/omap4/Kconfig
new file mode 100644
index 0000000..2091dd7
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4/Kconfig
@@ -0,0 +1,65 @@
+if OMAP44XX
+
+config SPL_EXT_SUPPORT
+ default y
+
+config SPL_FAT_SUPPORT
+ default y
+
+config SPL_GPIO_SUPPORT
+ default y
+
+config SPL_I2C_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ default y
+
+config SPL_NAND_SUPPORT
+ default y
+
+config SPL_POWER_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+config SPL_DISPLAY_PRINT
+ default y
+
+choice
+ prompt "OMAP4 board select"
+ optional
+
+config TARGET_DUOVERO
+ bool "OMAP4430 Gumstix Duovero"
+
+config TARGET_OMAP4_PANDA
+ bool "TI OMAP4 PandaBoard"
+
+config TARGET_OMAP4_SDP4430
+ bool "TI OMAP4 SDP4430"
+
+config TARGET_KC1
+ bool "Amazon Kindle Fire (first generation)"
+
+endchoice
+
+config SYS_SOC
+ default "omap4"
+
+source "board/gumstix/duovero/Kconfig"
+source "board/ti/panda/Kconfig"
+source "board/ti/sdp4430/Kconfig"
+source "board/amazon/kc1/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/mach-omap2/omap4/Makefile
similarity index 100%
rename from arch/arm/cpu/armv7/omap4/Makefile
rename to arch/arm/mach-omap2/omap4/Makefile
diff --git a/arch/arm/cpu/armv7/omap4/boot.c b/arch/arm/mach-omap2/omap4/boot.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap4/boot.c
rename to arch/arm/mach-omap2/omap4/boot.c
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/mach-omap2/omap4/emif.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap4/emif.c
rename to arch/arm/mach-omap2/omap4/emif.c
diff --git a/arch/arm/mach-omap2/omap4/hw_data.c b/arch/arm/mach-omap2/omap4/hw_data.c
new file mode 100644
index 0000000..6a4b8b9
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4/hw_data.c
@@ -0,0 +1,460 @@
+/*
+ *
+ * HW data initialization for OMAP4
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clock.h>
+#include <asm/omap_gpio.h>
+#include <asm/io.h>
+
+struct prcm_regs const **prcm =
+ (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+struct dplls const **dplls_data =
+ (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct vcores_data const **omap_vcores =
+ (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
+
+/*
+ * The M & N values in the following tables are created using the
+ * following tool:
+ * tools/omap/clocks_get_m_n.c
+ * Please use this tool for creating the table for any new frequency.
+ */
+
+/*
+ * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
+ * OMAP4460 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
+ {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/*
+ * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
+ * OMAP4430 OPP_TURBO frequency
+ * OMAP4470 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/*
+ * dpll locked at 1200 MHz - MPU clk at 600 MHz
+ * OMAP4430 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
+ {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OMAP4460 OPP_NOM frequency */
+/* OMAP4470 OPP_NOM (Low Power) frequency */
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OMAP4430 ES1 OPP_NOM frequency */
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+ {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OMAP4430 ES2.X OPP_NOM frequency */
+static const struct dpll_params
+ core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+ {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+ {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+ {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+ abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+ {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+ 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+ {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+struct dplls omap4430_dplls_es1 = {
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_es1_1524mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap4430_dplls_es20 = {
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_es2_1600mhz_ddr200mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap4430_dplls = {
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_1600mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap4460_dplls = {
+ .mpu = mpu_dpll_params_1400mhz,
+ .core = core_dpll_params_1600mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap4470_dplls = {
+ .mpu = mpu_dpll_params_1600mhz,
+ .core = core_dpll_params_1600mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct pmic_data twl6030_4430es1 = {
+ .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
+ .step = 12660, /* 12.66 mV represented in uV */
+ /* The code starts at 1 not 0 */
+ .start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
+};
+
+/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
+struct pmic_data twl6030 = {
+ .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
+ .step = 12660, /* 12.66 mV represented in uV */
+ /* The code starts at 1 not 0 */
+ .start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
+};
+
+struct pmic_data tps62361 = {
+ .base_offset = TPS62361_BASE_VOLT_MV,
+ .step = 10000, /* 10 mV represented in uV */
+ .start_code = 0,
+ .gpio = TPS62361_VSEL0_GPIO,
+ .gpio_en = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
+};
+
+struct vcores_data omap4430_volts_es1 = {
+ .mpu.value[OPP_NOM] = 1325,
+ .mpu.addr = SMPS_REG_ADDR_VCORE1,
+ .mpu.pmic = &twl6030_4430es1,
+
+ .core.value[OPP_NOM] = 1200,
+ .core.addr = SMPS_REG_ADDR_VCORE3,
+ .core.pmic = &twl6030_4430es1,
+
+ .mm.value[OPP_NOM] = 1200,
+ .mm.addr = SMPS_REG_ADDR_VCORE2,
+ .mm.pmic = &twl6030_4430es1,
+};
+
+struct vcores_data omap4430_volts = {
+ .mpu.value[OPP_NOM] = 1325,
+ .mpu.addr = SMPS_REG_ADDR_VCORE1,
+ .mpu.pmic = &twl6030,
+
+ .core.value[OPP_NOM] = 1200,
+ .core.addr = SMPS_REG_ADDR_VCORE3,
+ .core.pmic = &twl6030,
+
+ .mm.value[OPP_NOM] = 1200,
+ .mm.addr = SMPS_REG_ADDR_VCORE2,
+ .mm.pmic = &twl6030,
+};
+
+struct vcores_data omap4460_volts = {
+ .mpu.value[OPP_NOM] = 1203,
+ .mpu.addr = TPS62361_REG_ADDR_SET1,
+ .mpu.pmic = &tps62361,
+
+ .core.value[OPP_NOM] = 1200,
+ .core.addr = SMPS_REG_ADDR_VCORE1,
+ .core.pmic = &twl6030,
+
+ .mm.value[OPP_NOM] = 1200,
+ .mm.addr = SMPS_REG_ADDR_VCORE2,
+ .mm.pmic = &twl6030,
+};
+
+/*
+ * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
+ * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
+ */
+struct vcores_data omap4470_volts = {
+ .mpu.value[OPP_NOM] = 1202,
+ .mpu.addr = SMPS_REG_ADDR_SMPS1,
+ .mpu.pmic = &twl6030,
+
+ .core.value[OPP_NOM] = 1126,
+ .core.addr = SMPS_REG_ADDR_SMPS2,
+ .core.pmic = &twl6030,
+
+ .mm.value[OPP_NOM] = 1139,
+ .mm.addr = SMPS_REG_ADDR_SMPS5,
+ .mm.pmic = &twl6030,
+};
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ (*prcm)->cm_l4per_clkstctrl,
+ (*prcm)->cm_l3init_clkstctrl,
+ (*prcm)->cm_memif_clkstctrl,
+ (*prcm)->cm_l4cfg_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3_gpmc_clkctrl,
+ (*prcm)->cm_memif_emif_1_clkctrl,
+ (*prcm)->cm_memif_emif_2_clkctrl,
+ (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+ (*prcm)->cm_wkup_gpio1_clkctrl,
+ (*prcm)->cm_l4per_gpio2_clkctrl,
+ (*prcm)->cm_l4per_gpio3_clkctrl,
+ (*prcm)->cm_l4per_gpio4_clkctrl,
+ (*prcm)->cm_l4per_gpio5_clkctrl,
+ (*prcm)->cm_l4per_gpio6_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_wkup_gptimer1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc2_clkctrl,
+ (*prcm)->cm_l4per_gptimer2_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_l4per_uart3_clkctrl,
+ (*prcm)->cm_l4per_i2c1_clkctrl,
+ (*prcm)->cm_l4per_i2c2_clkctrl,
+ (*prcm)->cm_l4per_i2c3_clkctrl,
+ (*prcm)->cm_l4per_i2c4_clkctrl,
+ 0
+ };
+
+ /* Enable optional additional functional clock for GPIO4 */
+ setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
+ GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable 96 MHz clock for MMC1 & MMC2 */
+ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+ setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+
+ /* Select 32KHz clock as the source of GPTIMER1 */
+ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
+ GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+ /* Enable optional 48M functional clock for USB PHY */
+ setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
+ USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+
+ /* Enable 32 KHz clock for USB PHY */
+ setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+void enable_basic_uboot_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3init_hsusbotg_clkctrl,
+ (*prcm)->cm_l3init_usbphy_clkctrl,
+ (*prcm)->cm_clksel_usb_60mhz,
+ (*prcm)->cm_l3init_hsusbtll_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_l4per_mcspi1_clkctrl,
+ (*prcm)->cm_l3init_hsusbhost_clkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+void hw_data_init(void)
+{
+ u32 omap_rev = omap_revision();
+
+ (*prcm) = &omap4_prcm;
+
+ switch (omap_rev) {
+
+ case OMAP4430_ES1_0:
+ *dplls_data = &omap4430_dplls_es1;
+ *omap_vcores = &omap4430_volts_es1;
+ break;
+
+ case OMAP4430_ES2_0:
+ *dplls_data = &omap4430_dplls_es20;
+ *omap_vcores = &omap4430_volts;
+ break;
+
+ case OMAP4430_ES2_1:
+ case OMAP4430_ES2_2:
+ case OMAP4430_ES2_3:
+ *dplls_data = &omap4430_dplls;
+ *omap_vcores = &omap4430_volts;
+ break;
+
+ case OMAP4460_ES1_0:
+ case OMAP4460_ES1_1:
+ *dplls_data = &omap4460_dplls;
+ *omap_vcores = &omap4460_volts;
+ break;
+
+ case OMAP4470_ES1_0:
+ *dplls_data = &omap4470_dplls;
+ *omap_vcores = &omap4470_volts;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+
+ *ctrl = &omap4_ctrl;
+}
diff --git a/arch/arm/mach-omap2/omap4/hwinit.c b/arch/arm/mach-omap2/omap4/hwinit.c
new file mode 100644
index 0000000..67ab1cc
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4/hwinit.c
@@ -0,0 +1,190 @@
+/*
+ *
+ * Common functions for OMAP4 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <palmas.h>
+#include <asm/armv7.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/sizes.h>
+#include <asm/emif.h>
+#include <asm/arch/gpio.h>
+#include <asm/omap_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
+
+static const struct gpio_bank gpio_bank_44xx[6] = {
+ { (void *)OMAP44XX_GPIO1_BASE },
+ { (void *)OMAP44XX_GPIO2_BASE },
+ { (void *)OMAP44XX_GPIO3_BASE },
+ { (void *)OMAP44XX_GPIO4_BASE },
+ { (void *)OMAP44XX_GPIO5_BASE },
+ { (void *)OMAP44XX_GPIO6_BASE },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+void do_io_settings(void)
+{
+ u32 lpddr2io;
+
+ u32 omap4_rev = omap_revision();
+
+ if (omap4_rev == OMAP4430_ES1_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+ else if (omap4_rev == OMAP4430_ES2_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+ else
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
+
+ /* EMIF1 */
+ writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ (*ctrl)->control_lpddr2io1_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
+
+ /* EMIF2 */
+ writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ (*ctrl)->control_lpddr2io2_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
+
+ /*
+ * Some of these settings (TRIM values) come from eFuse and are
+ * in turn programmed in the eFuse at manufacturing time after
+ * calibration of the device. Do the software over-ride only if
+ * the device is not correctly trimmed
+ */
+ if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ (*ctrl)->control_ldosram_iva_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ (*ctrl)->control_ldosram_mpu_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ (*ctrl)->control_ldosram_core_voltage_ctrl);
+ }
+
+ /*
+ * Over-ride the register
+ * i. unconditionally for all 4430
+ * ii. only if un-trimmed for 4460
+ */
+ if (!readl((*ctrl)->control_efuse_1))
+ writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
+
+ if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
+ writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/* dummy fuction for omap4 */
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+}
+
+void init_omap_revision(void)
+{
+ /*
+ * For some of the ES2/ES1 boards ID_CODE is not reliable:
+ * Also, ES1 and ES2 have different ARM revisions
+ * So use ARM revision for identification
+ */
+ unsigned int arm_rev = cortex_rev();
+
+ switch (arm_rev) {
+ case MIDR_CORTEX_A9_R0P1:
+ *omap_si_rev = OMAP4430_ES1_0;
+ break;
+ case MIDR_CORTEX_A9_R1P2:
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = OMAP4430_ES2_0;
+ break;
+ case OMAP4_CONTROL_ID_CODE_ES2_1:
+ *omap_si_rev = OMAP4430_ES2_1;
+ break;
+ case OMAP4_CONTROL_ID_CODE_ES2_2:
+ *omap_si_rev = OMAP4430_ES2_2;
+ break;
+ default:
+ *omap_si_rev = OMAP4430_ES2_0;
+ break;
+ }
+ break;
+ case MIDR_CORTEX_A9_R1P3:
+ *omap_si_rev = OMAP4430_ES2_3;
+ break;
+ case MIDR_CORTEX_A9_R2P10:
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4470_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP4470_ES1_0;
+ break;
+ case OMAP4460_CONTROL_ID_CODE_ES1_1:
+ *omap_si_rev = OMAP4460_ES1_1;
+ break;
+ case OMAP4460_CONTROL_ID_CODE_ES1_0:
+ default:
+ *omap_si_rev = OMAP4460_ES1_0;
+ break;
+ }
+ break;
+ default:
+ *omap_si_rev = OMAP4430_SILICON_ID_INVALID;
+ break;
+ }
+}
+
+void omap_die_id(unsigned int *die_id)
+{
+ die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
+ die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
+ die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
+ die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
+}
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+void v7_outer_cache_enable(void)
+{
+ omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
+}
+
+void v7_outer_cache_disable(void)
+{
+ omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
+}
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
+
+void vmmc_pbias_config(uint voltage)
+{
+ u32 value = 0;
+
+ value = readl((*ctrl)->control_pbiaslite);
+ value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
+ writel(value, (*ctrl)->control_pbiaslite);
+ value = readl((*ctrl)->control_pbiaslite);
+ value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
+ writel(value, (*ctrl)->control_pbiaslite);
+}
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/mach-omap2/omap4/prcm-regs.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap4/prcm-regs.c
rename to arch/arm/mach-omap2/omap4/prcm-regs.c
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/mach-omap2/omap4/sdram_elpida.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap4/sdram_elpida.c
rename to arch/arm/mach-omap2/omap4/sdram_elpida.c
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
new file mode 100644
index 0000000..242d1ee
--- /dev/null
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -0,0 +1,191 @@
+if OMAP54XX
+
+config SPL_EXT_SUPPORT
+ default y
+
+config SPL_FAT_SUPPORT
+ default y
+
+config SPL_GPIO_SUPPORT
+ default y
+
+config SPL_I2C_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ default y
+
+config SPL_NAND_SUPPORT
+ default y
+
+config SPL_POWER_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+config SPL_DISPLAY_PRINT
+ default y
+
+choice
+ prompt "OMAP5 board select"
+ optional
+
+config TARGET_CL_SOM_AM57X
+ bool "CompuLab CL-SOM-AM57x"
+
+config TARGET_CM_T54
+ bool "CompuLab CM-T54"
+
+config TARGET_OMAP5_UEVM
+ bool "TI OMAP5 uEVM board"
+
+config TARGET_DRA7XX_EVM
+ bool "TI DRA7XX"
+ select TI_I2C_BOARD_DETECT
+ select PHYS_64BIT
+
+config TARGET_AM57XX_EVM
+ bool "AM57XX"
+ select TI_I2C_BOARD_DETECT
+
+endchoice
+
+config SYS_SOC
+ default "omap5"
+
+config TI_SECURE_EMIF_REGION_START
+ hex "Reserved EMIF region start address"
+ depends on TI_SECURE_DEVICE
+ default 0x0
+ help
+ Reserved EMIF region start address. Set to "0" to auto-select
+ to be at the end of the external memory region.
+
+config TI_SECURE_EMIF_TOTAL_REGION_SIZE
+ hex "Reserved EMIF region size"
+ depends on TI_SECURE_DEVICE
+ default 0x0
+ help
+ Total reserved EMIF region size. Default is 0, which means no reserved EMIF
+ region on secure devices.
+
+config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
+ hex "Size of protected region within reserved EMIF region"
+ depends on TI_SECURE_DEVICE
+ default 0x0
+ help
+ This config option is used to specify the size of the portion of the total
+ reserved EMIF region set aside for secure OS needs that will be protected
+ using hardware memory firewalls. This value must be smaller than the
+ TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
+
+if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM
+menu "Voltage Domain OPP selections"
+
+choice
+ prompt "MPU Voltage Domain"
+ default DRA7_MPU_OPP_NOM
+ help
+ Select the Operating Performance Point(OPP) for the MPU voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_MPU_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for MPU. This is the safest
+ option for booting.
+
+endchoice
+
+choice
+ prompt "DSPEVE Voltage Domain"
+ help
+ Select the Operating Performance Point(OPP) for the DSPEVE voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_DSPEVE_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for DSPEVE. This is the safest
+ option for booting and choose this when unsure about other OPPs .
+
+config DRA7_DSPEVE_OPP_OD
+ bool "OPP OD"
+ help
+ This config option enables Over drive OPP for DSPEVE.
+
+config DRA7_DSPEVE_OPP_HIGH
+ bool "OPP HIGH"
+ help
+ This config option enables High OPP for DSPEVE.
+
+endchoice
+
+choice
+ prompt "IVA Voltage Domain"
+ help
+ Select the Operating Performance Point(OPP) for the IVA voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_IVA_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for IVA. This is the safest
+ option for booting and choose this when unsure about other OPPs .
+
+config DRA7_IVA_OPP_OD
+ bool "OPP OD"
+ help
+ This config option enables Over drive OPP for IVA.
+
+config DRA7_IVA_OPP_HIGH
+ bool "OPP HIGH"
+ help
+ This config option enables High OPP for IVA.
+
+endchoice
+
+choice
+ prompt "GPU Voltage Domain"
+ help
+ Select the Operating Performance Point(OPP) for the GPU voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_GPU_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for GPU. This is the safest
+ option for booting and choose this when unsure about other OPPs .
+
+config DRA7_GPU_OPP_OD
+ bool "OPP OD"
+ help
+ This config option enables Over drive OPP for GPU.
+
+config DRA7_GPU_OPP_HIGH
+ bool "OPP HIGH"
+ help
+ This config option enables High OPP for GPU.
+
+endchoice
+
+endmenu
+endif
+
+source "board/compulab/cl-som-am57x/Kconfig"
+source "board/compulab/cm_t54/Kconfig"
+source "board/ti/omap5_uevm/Kconfig"
+source "board/ti/dra7xx/Kconfig"
+source "board/ti/am57xx/Kconfig"
+
+endif
diff --git a/arch/arm/mach-omap2/omap5/Makefile b/arch/arm/mach-omap2/omap5/Makefile
new file mode 100644
index 0000000..af17a3d
--- /dev/null
+++ b/arch/arm/mach-omap2/omap5/Makefile
@@ -0,0 +1,18 @@
+#
+# (C) Copyright 2000-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += boot.o
+obj-y += hwinit.o
+obj-y += emif.o
+obj-y += sdram.o
+obj-y += prcm-regs.o
+obj-y += hw_data.o
+obj-y += abb.o
+obj-y += fdt.o
+obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
+obj-$(CONFIG_TI_SECURE_DEVICE) += sec-fxns.o
+obj-$(CONFIG_DRA7XX) += sec_entry_cpu1.o
diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/mach-omap2/omap5/abb.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap5/abb.c
rename to arch/arm/mach-omap2/omap5/abb.c
diff --git a/arch/arm/mach-omap2/omap5/boot.c b/arch/arm/mach-omap2/omap5/boot.c
new file mode 100644
index 0000000..18750b8
--- /dev/null
+++ b/arch/arm/mach-omap2/omap5/boot.c
@@ -0,0 +1,46 @@
+/*
+ * OMAP5 boot
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/omap_common.h>
+#include <spl.h>
+
+static u32 boot_devices[] = {
+#if defined(CONFIG_DRA7XX)
+ BOOT_DEVICE_MMC2,
+ BOOT_DEVICE_NAND,
+ BOOT_DEVICE_MMC1,
+ BOOT_DEVICE_SATA,
+ BOOT_DEVICE_XIP,
+ BOOT_DEVICE_XIP,
+ BOOT_DEVICE_SPI,
+ BOOT_DEVICE_SPI,
+#else
+ BOOT_DEVICE_MMC2,
+ BOOT_DEVICE_NAND,
+ BOOT_DEVICE_MMC1,
+ BOOT_DEVICE_SATA,
+ BOOT_DEVICE_XIP,
+ BOOT_DEVICE_MMC2,
+ BOOT_DEVICE_XIPWAIT,
+#endif
+};
+
+u32 omap_sys_boot_device(void)
+{
+ u32 sys_boot;
+
+ /* Grab the first 4 bits of the status register for SYS_BOOT. */
+ sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 4) - 1);
+
+ if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
+ return BOOT_DEVICE_NONE;
+
+ return boot_devices[sys_boot];
+}
diff --git a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c
rename to arch/arm/mach-omap2/omap5/dra7xx_iodelay.c
diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/mach-omap2/omap5/emif.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap5/emif.c
rename to arch/arm/mach-omap2/omap5/emif.c
diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c
new file mode 100644
index 0000000..900f001
--- /dev/null
+++ b/arch/arm/mach-omap2/omap5/fdt.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright 2016 Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <malloc.h>
+
+#include <asm/omap_common.h>
+#include <asm/arch-omap5/sys_proto.h>
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+
+/* Give zero values if not already defined */
+#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
+#endif
+#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#endif
+
+static u32 hs_irq_skip[] = {
+ 8, /* Secure violation reporting interrupt */
+ 15, /* One interrupt for SDMA by secure world */
+ 118 /* One interrupt for Crypto DMA by secure world */
+};
+
+static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+ int len, i, old_cnt, new_cnt;
+ u32 *temp;
+ const u32 *p_data;
+
+ /*
+ * Increase the size of the fdt
+ * so we have some breathing room
+ */
+ ret = fdt_increase_size(fdt, 512);
+ if (ret < 0) {
+ printf("Could not increase size of device tree: %s\n",
+ fdt_strerror(ret));
+ return ret;
+ }
+
+ /* Reserve IRQs that are used/needed by secure world */
+ path = "/ocp/crossbar";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+
+ /* Get current entries */
+ p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
+ if (p_data)
+ old_cnt = len / sizeof(u32);
+ else
+ old_cnt = 0;
+
+ new_cnt = sizeof(hs_irq_skip) /
+ sizeof(hs_irq_skip[0]);
+
+ /* Create new/updated skip list for HS parts */
+ temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
+ for (i = 0; i < new_cnt; i++)
+ temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
+ for (i = 0; i < old_cnt; i++)
+ temp[i + new_cnt] = p_data[i];
+
+ /* Blow away old data and set new data */
+ fdt_delprop(fdt, offs, "ti,irqs-skip");
+ ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
+ temp,
+ (old_cnt + new_cnt) * sizeof(u32));
+ free(temp);
+
+ /* Check if the update worked */
+ if (ret < 0) {
+ printf("Could not add ti,irqs-skip property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ft_hs_disable_rng(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+
+ /* Make HW RNG reserved for secure world use */
+ path = "/ocp/rng";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+ ret = fdt_setprop_string(fdt, offs,
+ "status", "disabled");
+ if (ret < 0) {
+ printf("Could not add status property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+ return 0;
+}
+
+#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
+ (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+ u32 temp[2];
+
+ /*
+ * Update SRAM reservations on secure devices. The OCMC RAM
+ * is always reserved for secure use from the start of that
+ * memory region
+ */
+ path = "/ocp/ocmcram@40300000/sram-hs";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+
+ /* relative start offset */
+ temp[0] = cpu_to_fdt32(0);
+ /* reservation size */
+ temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
+ CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
+ fdt_delprop(fdt, offs, "reg");
+ ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
+ if (ret < 0) {
+ printf("Could not add reg property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+
+ return 0;
+}
+#else
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
+#endif
+
+#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0)
+static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
+{
+ const char *path, *subpath;
+ int offs;
+ u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
+ u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
+ fdt64_t temp[2];
+
+ /* If start address is zero, place at end of DRAM */
+ if (0 == sec_mem_start)
+ sec_mem_start =
+ (CONFIG_SYS_SDRAM_BASE +
+ (omap_sdram_size() - sec_mem_size));
+
+ /* Delete any original secure_reserved node */
+ path = "/reserved-memory/secure_reserved";
+ offs = fdt_path_offset(fdt, path);
+ if (offs >= 0)
+ fdt_del_node(fdt, offs);
+
+ /* Add new secure_reserved node */
+ path = "/reserved-memory";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found\n", path);
+ path = "/";
+ subpath = "reserved-memory";
+ fdt_path_offset(fdt, path);
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s%s node.\n", path, subpath);
+ return 1;
+ }
+ path = "/reserved-memory";
+ offs = fdt_path_offset(fdt, path);
+ }
+
+ subpath = "secure_reserved";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s%s node.\n", path, subpath);
+ return 1;
+ }
+
+ temp[0] = cpu_to_fdt64(((u64)sec_mem_start));
+ temp[1] = cpu_to_fdt64(((u64)sec_mem_size));
+ fdt_setprop_string(fdt, offs, "compatible",
+ "ti,dra7-secure-memory");
+ fdt_setprop_string(fdt, offs, "status", "okay");
+ fdt_setprop(fdt, offs, "no-map", NULL, 0);
+ fdt_setprop(fdt, offs, "reg", temp, sizeof(temp));
+
+ return 0;
+}
+#else
+static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; }
+#endif
+
+static int ft_hs_add_tee(void *fdt, bd_t *bd)
+{
+ const char *path, *subpath;
+ int offs;
+
+ extern int tee_loaded;
+ if (!tee_loaded)
+ return 0;
+
+ path = "/";
+ offs = fdt_path_offset(fdt, path);
+
+ subpath = "firmware";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return 1;
+ }
+
+ subpath = "optee";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return 1;
+ }
+
+ fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
+ fdt_setprop_string(fdt, offs, "method", "smc");
+
+ return 0;
+}
+
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+ /* Check we are running on an HS/EMU device type */
+ if (GP_DEVICE != get_device_type()) {
+ if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
+ (ft_hs_disable_rng(fdt, bd) == 0) &&
+ (ft_hs_fixup_sram(fdt, bd) == 0) &&
+ (ft_hs_fixup_dram(fdt, bd) == 0) &&
+ (ft_hs_add_tee(fdt, bd) == 0))
+ return;
+ } else {
+ printf("ERROR: Incorrect device type (GP) detected!");
+ }
+ /* Fixup failed or wrong device type */
+ hang();
+}
+#else
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+}
+#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
+
+#if defined(CONFIG_TARGET_DRA7XX_EVM) || defined(CONFIG_TARGET_AM57XX_EVM)
+#define OPP_DSP_CLK_NUM 3
+#define OPP_IVA_CLK_NUM 2
+#define OPP_GPU_CLK_NUM 2
+
+const char *dra7_opp_dsp_clk_names[OPP_DSP_CLK_NUM] = {
+ "dpll_dsp_ck",
+ "dpll_dsp_m2_ck",
+ "dpll_dsp_m3x2_ck",
+};
+
+const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = {
+ "dpll_iva_ck",
+ "dpll_iva_m2_ck",
+};
+
+const char *dra7_opp_gpu_clk_names[OPP_GPU_CLK_NUM] = {
+ "dpll_gpu_ck",
+ "dpll_gpu_m2_ck",
+};
+
+/* DSPEVE voltage domain */
+u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
+ {}, /*OPP_LOW */
+ {600000000, 600000000, 400000000}, /* OPP_NOM */
+ {700000000, 700000000, 466666667}, /* OPP_OD */
+ {750000000, 750000000, 500000000}, /* OPP_HIGH */
+};
+
+/* IVA voltage domain */
+u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
+ {}, /* OPP_LOW */
+ {1165000000, 388333334}, /* OPP_NOM */
+ {860000000, 430000000}, /* OPP_OD */
+ {1064000000, 532000000}, /* OPP_HIGH */
+};
+
+/* GPU voltage domain */
+u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = {
+ {}, /* OPP_LOW */
+ {1277000000, 425666667}, /* OPP_NOM */
+ {1000000000, 500000000}, /* OPP_OD */
+ {1064000000, 532000000}, /* OPP_HIGH */
+};
+
+static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
+{
+ int offs, node_offs, ret, i;
+ uint32_t phandle;
+
+ offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
+ if (offs < 0) {
+ debug("Could not find cm_core_aon clocks node path offset : %s\n",
+ fdt_strerror(offs));
+ return offs;
+ }
+
+ for (i = 0; i < num; i++) {
+ node_offs = fdt_subnode_offset(fdt, offs, names[i]);
+ if (node_offs < 0) {
+ debug("Could not find clock sub-node %s: %s\n",
+ names[i], fdt_strerror(node_offs));
+ return offs;
+ }
+
+ phandle = fdt_get_phandle(fdt, node_offs);
+ if (!phandle) {
+ debug("Could not find phandle for clock %s\n",
+ names[i]);
+ return -1;
+ }
+
+ ret = fdt_setprop_u32(fdt, node_offs, "assigned-clocks",
+ phandle);
+ if (ret < 0) {
+ debug("Could not add assigned-clocks property to clock node %s: %s\n",
+ names[i], fdt_strerror(ret));
+ return ret;
+ }
+
+ ret = fdt_setprop_u32(fdt, node_offs, "assigned-clock-rates",
+ rates[i]);
+ if (ret < 0) {
+ debug("Could not add assigned-clock-rates property to clock node %s: %s\n",
+ names[i], fdt_strerror(ret));
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
+{
+ const char **clk_names;
+ u32 *clk_rates;
+ int ret;
+
+ if (!is_dra72x() && !is_dra7xx())
+ return;
+
+ /* fixup DSP clocks */
+ clk_names = dra7_opp_dsp_clk_names;
+ clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
+ if (ret) {
+ printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+
+ /* fixup IVA clocks */
+ clk_names = dra7_opp_iva_clk_names;
+ clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)];
+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM);
+ if (ret) {
+ printf("ft_fixup_clocks failed for IVA voltage domain: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+
+ /* fixup GPU clocks */
+ clk_names = dra7_opp_gpu_clk_names;
+ clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)];
+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM);
+ if (ret) {
+ printf("ft_fixup_clocks failed for GPU voltage domain: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+}
+#else
+static void ft_opp_clock_fixups(void *fdt, bd_t *bd) { }
+#endif /* CONFIG_TARGET_DRA7XX_EVM || CONFIG_TARGET_AM57XX_EVM */
+
+/*
+ * Place for general cpu/SoC FDT fixups. Board specific
+ * fixups should remain in the board files which is where
+ * this function should be called from.
+ */
+void ft_cpu_setup(void *fdt, bd_t *bd)
+{
+ ft_hs_fixups(fdt, bd);
+ ft_opp_clock_fixups(fdt, bd);
+}
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
new file mode 100644
index 0000000..58991d7
--- /dev/null
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -0,0 +1,792 @@
+/*
+ *
+ * HW data initialization for OMAP5
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <palmas.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clock.h>
+#include <asm/omap_gpio.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+struct prcm_regs const **prcm =
+ (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+struct dplls const **dplls_data =
+ (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct vcores_data const **omap_vcores =
+ (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
+
+/* OPP HIGH FREQUENCY for ES2.0 */
+static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
+ {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP NOM FREQUENCY for ES1.0 */
+static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP LOW FREQUENCY for ES1.0 */
+static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
+ {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP LOW FREQUENCY for ES2.0 */
+static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
+ {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
+static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
+ {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
+ {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
+ {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
+ {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
+ {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
+ {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
+ {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
+ {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
+ {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
+ {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
+ {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
+ {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
+ {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
+ {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
+ {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
+ {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
+ {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
+ {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
+ {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
+ {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
+ {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
+ {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
+ {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+ abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+ {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+ 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+/* ABE M & N values with sysclk2(22.5792 MHz) as input */
+static const struct dpll_params
+ abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+ {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
+static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
+ {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
+static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
+ {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
+static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
+ {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
+struct dplls omap5_dplls_es1 = {
+ .mpu = mpu_dpll_params_800mhz,
+ .core = core_dpll_params_2128mhz_ddr532,
+ .per = per_dpll_params_768mhz,
+ .iva = iva_dpll_params_2330mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap5_dplls_es2 = {
+ .mpu = mpu_dpll_params_1ghz,
+ .core = core_dpll_params_2128mhz_ddr532_es2,
+ .per = per_dpll_params_768mhz_es2,
+ .iva = iva_dpll_params_2330mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls dra7xx_dplls = {
+ .mpu = mpu_dpll_params_1ghz,
+ .core = core_dpll_params_2128mhz_dra7xx,
+ .per = per_dpll_params_768mhz_dra7xx,
+ .abe = abe_dpll_params_sysclk2_361267khz,
+ .iva = iva_dpll_params_2330mhz_dra7xx,
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = ddr_dpll_params_2128mhz,
+ .gmac = gmac_dpll_params_2000mhz,
+};
+
+struct dplls dra72x_dplls = {
+ .mpu = mpu_dpll_params_1ghz,
+ .core = core_dpll_params_2128mhz_dra7xx,
+ .per = per_dpll_params_768mhz_dra7xx,
+ .abe = abe_dpll_params_sysclk2_361267khz,
+ .iva = iva_dpll_params_2330mhz_dra7xx,
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = ddr_dpll_params_2664mhz,
+ .gmac = gmac_dpll_params_2000mhz,
+};
+
+struct pmic_data palmas = {
+ .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+ .step = 10000, /* 10 mV represented in uV */
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ .start_code = 6,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
+ .gpio_en = 0,
+};
+
+/* The TPS659038 and TPS65917 are software-compatible, use common struct */
+struct pmic_data tps659038 = {
+ .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+ .step = 10000, /* 10 mV represented in uV */
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ .start_code = 6,
+ .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
+ .pmic_bus_init = gpi2c_init,
+ .pmic_write = palmas_i2c_write_u8,
+ .gpio_en = 0,
+};
+
+/* The LP8732 and LP8733 are software-compatible, use common struct */
+struct pmic_data lp8733 = {
+ .base_offset = LP873X_BUCK_BASE_VOLT_UV,
+ .step = 5000, /* 5 mV represented in uV */
+ /*
+ * Offset codes 0 - 0x13 Invalid.
+ * Offset codes 0x14 0x17 give 10mV steps
+ * Offset codes 0x17 through 0x9D give 5mV steps
+ * So let us start with our operating range from .73V
+ */
+ .start_code = 0x17,
+ .i2c_slave_addr = 0x60,
+ .pmic_bus_init = gpi2c_init,
+ .pmic_write = palmas_i2c_write_u8,
+};
+
+struct vcores_data omap5430_volts = {
+ .mpu.value[OPP_NOM] = VDD_MPU,
+ .mpu.addr = SMPS_REG_ADDR_12_MPU,
+ .mpu.pmic = &palmas,
+
+ .core.value[OPP_NOM] = VDD_CORE,
+ .core.addr = SMPS_REG_ADDR_8_CORE,
+ .core.pmic = &palmas,
+
+ .mm.value[OPP_NOM] = VDD_MM,
+ .mm.addr = SMPS_REG_ADDR_45_IVA,
+ .mm.pmic = &palmas,
+};
+
+struct vcores_data omap5430_volts_es2 = {
+ .mpu.value[OPP_NOM] = VDD_MPU_ES2,
+ .mpu.addr = SMPS_REG_ADDR_12_MPU,
+ .mpu.pmic = &palmas,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .core.value[OPP_NOM] = VDD_CORE_ES2,
+ .core.addr = SMPS_REG_ADDR_8_CORE,
+ .core.pmic = &palmas,
+
+ .mm.value[OPP_NOM] = VDD_MM_ES2,
+ .mm.addr = SMPS_REG_ADDR_45_IVA,
+ .mm.pmic = &palmas,
+ .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
+};
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ (*prcm)->cm_l4per_clkstctrl,
+ (*prcm)->cm_l3init_clkstctrl,
+ (*prcm)->cm_memif_clkstctrl,
+ (*prcm)->cm_l4cfg_clkstctrl,
+#ifdef CONFIG_DRIVER_TI_CPSW
+ (*prcm)->cm_gmac_clkstctrl,
+#endif
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3_gpmc_clkctrl,
+ (*prcm)->cm_memif_emif_1_clkctrl,
+ (*prcm)->cm_memif_emif_2_clkctrl,
+ (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+ (*prcm)->cm_wkup_gpio1_clkctrl,
+ (*prcm)->cm_l4per_gpio2_clkctrl,
+ (*prcm)->cm_l4per_gpio3_clkctrl,
+ (*prcm)->cm_l4per_gpio4_clkctrl,
+ (*prcm)->cm_l4per_gpio5_clkctrl,
+ (*prcm)->cm_l4per_gpio6_clkctrl,
+ (*prcm)->cm_l4per_gpio7_clkctrl,
+ (*prcm)->cm_l4per_gpio8_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_wkup_gptimer1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc2_clkctrl,
+ (*prcm)->cm_l4per_gptimer2_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_l4per_uart3_clkctrl,
+ (*prcm)->cm_l4per_i2c1_clkctrl,
+#ifdef CONFIG_DRIVER_TI_CPSW
+ (*prcm)->cm_gmac_gmac_clkctrl,
+#endif
+
+#ifdef CONFIG_TI_QSPI
+ (*prcm)->cm_l4per_qspi_clkctrl,
+#endif
+ 0
+ };
+
+ /* Enable optional additional functional clock for GPIO4 */
+ setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
+ GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable 96 MHz clock for MMC1 & MMC2 */
+ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+ setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+
+ /* Set the correct clock dividers for mmc */
+ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+ setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+
+ /* Select 32KHz clock as the source of GPTIMER1 */
+ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
+ GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+
+#ifdef CONFIG_TI_QSPI
+ setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
+ /* Enable SCRM OPT clocks for PER and CORE dpll */
+ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
+ OPTFCLKEN_SCRM_PER_MASK);
+ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
+ OPTFCLKEN_SCRM_CORE_MASK);
+}
+
+void enable_basic_uboot_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+#if defined(CONFIG_DRA7XX)
+ (*prcm)->cm_ipu_clkstctrl,
+#endif
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3init_hsusbtll_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_l4per_mcspi1_clkctrl,
+ (*prcm)->cm_l4per_i2c2_clkctrl,
+ (*prcm)->cm_l4per_i2c3_clkctrl,
+ (*prcm)->cm_l4per_i2c4_clkctrl,
+#if defined(CONFIG_DRA7XX)
+ (*prcm)->cm_ipu_i2c5_clkctrl,
+#else
+ (*prcm)->cm_l4per_i2c5_clkctrl,
+#endif
+ (*prcm)->cm_l3init_hsusbhost_clkctrl,
+ (*prcm)->cm_l3init_fsusb_clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void)
+{
+ u32 const clk_domains_edma3[] = {
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_edma3[] = {
+ (*prcm)->cm_l3main1_tptc1_clkctrl,
+ (*prcm)->cm_l3main1_tptc2_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_edma3[] = {
+ 0
+ };
+
+ do_enable_clocks(clk_domains_edma3,
+ clk_modules_hw_auto_edma3,
+ clk_modules_explicit_en_edma3,
+ 1);
+}
+
+void disable_edma3_clocks(void)
+{
+ u32 const clk_domains_edma3[] = {
+ 0
+ };
+
+ u32 const clk_modules_disable_edma3[] = {
+ (*prcm)->cm_l3main1_tptc1_clkctrl,
+ (*prcm)->cm_l3main1_tptc2_clkctrl,
+ 0
+ };
+
+ do_disable_clocks(clk_domains_edma3,
+ clk_modules_disable_edma3,
+ 1);
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
+void enable_usb_clocks(int index)
+{
+ u32 cm_l3init_usb_otg_ss_clkctrl = 0;
+
+ if (index == 0) {
+ cm_l3init_usb_otg_ss_clkctrl =
+ (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
+ /* Enable 960 MHz clock for dwc3 */
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+ OPTFCLKEN_REFCLK960M);
+
+ /* Enable 32 KHz clock for USB_PHY1 */
+ setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ /* Enable 32 KHz clock for USB_PHY3 */
+ if (is_dra7xx())
+ setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+ } else if (index == 1) {
+ cm_l3init_usb_otg_ss_clkctrl =
+ (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
+ /* Enable 960 MHz clock for dwc3 */
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+ OPTFCLKEN_REFCLK960M);
+
+ /* Enable 32 KHz clock for dwc3 */
+ setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ /* Enable 60 MHz clock for USB2PHY2 */
+ setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
+ L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
+ }
+
+ u32 const clk_domains_usb[] = {
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_usb[] = {
+ (*prcm)->cm_l3init_ocp2scp1_clkctrl,
+ cm_l3init_usb_otg_ss_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_usb[] = {
+ 0
+ };
+
+ do_enable_clocks(clk_domains_usb,
+ clk_modules_hw_auto_usb,
+ clk_modules_explicit_en_usb,
+ 1);
+}
+
+void disable_usb_clocks(int index)
+{
+ u32 cm_l3init_usb_otg_ss_clkctrl = 0;
+
+ if (index == 0) {
+ cm_l3init_usb_otg_ss_clkctrl =
+ (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
+ /* Disable 960 MHz clock for dwc3 */
+ clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+ OPTFCLKEN_REFCLK960M);
+
+ /* Disable 32 KHz clock for USB_PHY1 */
+ clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ /* Disable 32 KHz clock for USB_PHY3 */
+ if (is_dra7xx())
+ clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+ } else if (index == 1) {
+ cm_l3init_usb_otg_ss_clkctrl =
+ (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
+ /* Disable 960 MHz clock for dwc3 */
+ clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+ OPTFCLKEN_REFCLK960M);
+
+ /* Disable 32 KHz clock for dwc3 */
+ clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ /* Disable 60 MHz clock for USB2PHY2 */
+ clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
+ L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
+ }
+
+ u32 const clk_domains_usb[] = {
+ 0
+ };
+
+ u32 const clk_modules_disable[] = {
+ (*prcm)->cm_l3init_ocp2scp1_clkctrl,
+ cm_l3init_usb_otg_ss_clkctrl,
+ 0
+ };
+
+ do_disable_clocks(clk_domains_usb,
+ clk_modules_disable,
+ 1);
+}
+#endif
+
+const struct ctrl_ioregs ioregs_omap5430 = {
+ .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+ .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+ .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es1 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+ .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es2 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+ .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+};
+
+const struct ctrl_ioregs ioregs_dra7xx_es1 = {
+ .ctrl_ddrch = 0x40404040,
+ .ctrl_lpddr2ch = 0x40404040,
+ .ctrl_ddr3ch = 0x80808080,
+ .ctrl_ddrio_0 = 0x00094A40,
+ .ctrl_ddrio_1 = 0x04A52000,
+ .ctrl_ddrio_2 = 0x84210000,
+ .ctrl_emif_sdram_config_ext = 0x0001C1A7,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
+ .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
+const struct ctrl_ioregs ioregs_dra72x_es1 = {
+ .ctrl_ddrch = 0x40404040,
+ .ctrl_lpddr2ch = 0x40404040,
+ .ctrl_ddr3ch = 0x60606080,
+ .ctrl_ddrio_0 = 0x00094A40,
+ .ctrl_ddrio_1 = 0x04A52000,
+ .ctrl_ddrio_2 = 0x84210000,
+ .ctrl_emif_sdram_config_ext = 0x0001C1A7,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
+ .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
+const struct ctrl_ioregs ioregs_dra72x_es2 = {
+ .ctrl_ddrch = 0x40404040,
+ .ctrl_lpddr2ch = 0x40404040,
+ .ctrl_ddr3ch = 0x60606060,
+ .ctrl_ddrio_0 = 0x00094A40,
+ .ctrl_ddrio_1 = 0x00000000,
+ .ctrl_ddrio_2 = 0x00000000,
+ .ctrl_emif_sdram_config_ext = 0x0001C1A7,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
+ .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
+void __weak hw_data_init(void)
+{
+ u32 omap_rev = omap_revision();
+
+ switch (omap_rev) {
+
+ case OMAP5430_ES1_0:
+ case OMAP5432_ES1_0:
+ *prcm = &omap5_es1_prcm;
+ *dplls_data = &omap5_dplls_es1;
+ *omap_vcores = &omap5430_volts;
+ *ctrl = &omap5_ctrl;
+ break;
+
+ case OMAP5430_ES2_0:
+ case OMAP5432_ES2_0:
+ *prcm = &omap5_es2_prcm;
+ *dplls_data = &omap5_dplls_es2;
+ *omap_vcores = &omap5430_volts_es2;
+ *ctrl = &omap5_ctrl;
+ break;
+
+ case DRA752_ES1_0:
+ case DRA752_ES1_1:
+ case DRA752_ES2_0:
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra7xx_dplls;
+ *ctrl = &dra7xx_ctrl;
+ break;
+
+ case DRA722_ES1_0:
+ case DRA722_ES2_0:
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra72x_dplls;
+ *ctrl = &dra7xx_ctrl;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+}
+
+void get_ioregs(const struct ctrl_ioregs **regs)
+{
+ u32 omap_rev = omap_revision();
+
+ switch (omap_rev) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ *regs = &ioregs_omap5430;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = &ioregs_omap5432_es1;
+ break;
+ case OMAP5432_ES2_0:
+ *regs = &ioregs_omap5432_es2;
+ break;
+ case DRA752_ES1_0:
+ case DRA752_ES1_1:
+ case DRA752_ES2_0:
+ *regs = &ioregs_dra7xx_es1;
+ break;
+ case DRA722_ES1_0:
+ *regs = &ioregs_dra72x_es1;
+ break;
+ case DRA722_ES2_0:
+ *regs = &ioregs_dra72x_es2;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+}
diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c
new file mode 100644
index 0000000..839d79d
--- /dev/null
+++ b/arch/arm/mach-omap2/omap5/hwinit.c
@@ -0,0 +1,487 @@
+/*
+ *
+ * Functions for omap5 based boards.
+ *
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ * Sricharan <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <palmas.h>
+#include <asm/armv7.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <linux/sizes.h>
+#include <asm/utils.h>
+#include <asm/arch/gpio.h>
+#include <asm/emif.h>
+#include <asm/omap_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
+
+#ifndef CONFIG_DM_GPIO
+static struct gpio_bank gpio_bank_54xx[8] = {
+ { (void *)OMAP54XX_GPIO1_BASE },
+ { (void *)OMAP54XX_GPIO2_BASE },
+ { (void *)OMAP54XX_GPIO3_BASE },
+ { (void *)OMAP54XX_GPIO4_BASE },
+ { (void *)OMAP54XX_GPIO5_BASE },
+ { (void *)OMAP54XX_GPIO6_BASE },
+ { (void *)OMAP54XX_GPIO7_BASE },
+ { (void *)OMAP54XX_GPIO8_BASE },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
+#endif
+
+void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+ for (i = 0; i < size; i++, pad++)
+ writel(pad->val, base + pad->offset);
+}
+
+#ifdef CONFIG_SPL_BUILD
+/* LPDDR2 specific IO settings */
+static void io_settings_lpddr2(void)
+{
+ const struct ctrl_ioregs *ioregs;
+
+ get_ioregs(&ioregs);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+ writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+ writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+}
+
+/* DDR3 specific IO settings */
+static void io_settings_ddr3(void)
+{
+ u32 io_settings = 0;
+ const struct ctrl_ioregs *ioregs;
+
+ get_ioregs(&ioregs);
+ writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+
+ writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+
+ writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+ writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+
+ if (!is_dra7xx()) {
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+ }
+
+ /* omap5432 does not use lpddr2 */
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif1_sdram_config_ext);
+ if (!is_dra72x())
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif2_sdram_config_ext);
+
+ if (is_omap54xx()) {
+ /* Disable DLL select */
+ io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
+ & 0xFFEFFFFF);
+ writel(io_settings,
+ (*ctrl)->control_port_emif1_sdram_config);
+
+ io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
+ & 0xFFEFFFFF);
+ writel(io_settings,
+ (*ctrl)->control_port_emif2_sdram_config);
+ } else {
+ writel(ioregs->ctrl_ddr_ctrl_ext_0,
+ (*ctrl)->control_ddr_control_ext_0);
+ }
+}
+
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+void do_io_settings(void)
+{
+ u32 io_settings = 0, mask = 0;
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+ /* Impedance settings EMMC, C2C 1,2, hsi2 */
+ mask = (ds_mask << 2) | (ds_mask << 8) |
+ (ds_mask << 16) | (ds_mask << 18);
+ io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
+ (~mask);
+ io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
+ (ds_45_ohm << 18) | (ds_60_ohm << 2);
+ writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
+
+ /* Impedance settings Mcspi2 */
+ mask = (ds_mask << 30);
+ io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
+ (~mask);
+ io_settings |= (ds_60_ohm << 30);
+ writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
+
+ /* Impedance settings C2C 3,4 */
+ mask = (ds_mask << 14) | (ds_mask << 16);
+ io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
+ (~mask);
+ io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
+ writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
+
+ /* Slew rate settings EMMC, C2C 1,2 */
+ mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
+ io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
+ (~mask);
+ io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
+ writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
+
+ /* Slew rate settings hsi2, Mcspi2 */
+ mask = (sc_mask << 24) | (sc_mask << 28);
+ io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
+ (~mask);
+ io_settings |= (sc_fast << 28) | (sc_fast << 24);
+ writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
+
+ /* Slew rate settings C2C 3,4 */
+ mask = (sc_mask << 16) | (sc_mask << 18);
+ io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
+ (~mask);
+ io_settings |= (sc_na << 16) | (sc_na << 18);
+ writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
+
+ /* impedance and slew rate settings for usb */
+ mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
+ (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
+ io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
+ (~mask);
+ io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
+ (ds_60_ohm << 23) | (sc_fast << 20) |
+ (sc_fast << 17) | (sc_fast << 14);
+ writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
+
+ if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
+ io_settings_lpddr2();
+ else
+ io_settings_ddr3();
+}
+
+static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
+ {0x45, 0x1}, /* 12 MHz */
+ {-1, -1}, /* 13 MHz */
+ {0x63, 0x2}, /* 16.8 MHz */
+ {0x57, 0x2}, /* 19.2 MHz */
+ {0x20, 0x1}, /* 26 MHz */
+ {-1, -1}, /* 27 MHz */
+ {0x41, 0x3} /* 38.4 MHz */
+};
+
+void srcomp_enable(void)
+{
+ u32 srcomp_value, mul_factor, div_factor, clk_val, i;
+ u32 sysclk_ind = get_sys_clk_index();
+ u32 omap_rev = omap_revision();
+
+ if (!is_omap54xx())
+ return;
+
+ mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
+ div_factor = srcomp_parameters[sysclk_ind].divide_factor;
+
+ for (i = 0; i < 4; i++) {
+ srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &=
+ ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
+ srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
+ (div_factor << DIVIDE_FACTOR_XS_SHIFT);
+ writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
+ }
+
+ if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
+ clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
+
+ for (i = 0; i < 4; i++) {
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~PWRDWN_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+
+ while (((readl((*ctrl)->control_srcomp_north_side + i*4)
+ & SRCODE_READ_XS_MASK) >>
+ SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~OVERRIDE_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+ }
+ } else {
+ srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
+ DIVIDE_FACTOR_XS_MASK);
+ srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
+ (div_factor << DIVIDE_FACTOR_XS_SHIFT);
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+ for (i = 0; i < 4; i++) {
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~OVERRIDE_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+ }
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value &= ~OVERRIDE_XS_MASK;
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+ clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
+
+ clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
+
+ for (i = 0; i < 4; i++) {
+ while (((readl((*ctrl)->control_srcomp_north_side + i*4)
+ & SRCODE_READ_XS_MASK) >>
+ SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+ }
+
+ while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
+ SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+ }
+}
+#endif
+
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+ const struct ctrl_ioregs *ioregs;
+
+ get_ioregs(&ioregs);
+
+ /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
+ if (emif_base == EMIF1_BASE)
+ writel(ioregs->ctrl_emif_sdram_config_ext_final,
+ (*ctrl)->control_emif1_sdram_config_ext);
+ else if (emif_base == EMIF2_BASE)
+ writel(ioregs->ctrl_emif_sdram_config_ext_final,
+ (*ctrl)->control_emif2_sdram_config_ext);
+}
+
+void init_cpu_configuration(void)
+{
+ u32 l2actlr;
+
+ asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
+ /*
+ * L2ACTLR: Ensure to enable the following:
+ * 3: Disable clean/evict push to external
+ * 4: Disable WriteUnique and WriteLineUnique transactions from master
+ * 8: Disable DVM/CMO message broadcast
+ */
+ l2actlr |= 0x118;
+ omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
+}
+
+void init_omap_revision(void)
+{
+ /*
+ * For some of the ES2/ES1 boards ID_CODE is not reliable:
+ * Also, ES1 and ES2 have different ARM revisions
+ * So use ARM revision for identification
+ */
+ unsigned int rev = cortex_rev();
+
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP5430_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP5430_ES1_0;
+ if (rev == MIDR_CORTEX_A15_R2P2)
+ *omap_si_rev = OMAP5430_ES2_0;
+ break;
+ case OMAP5432_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP5432_ES1_0;
+ if (rev == MIDR_CORTEX_A15_R2P2)
+ *omap_si_rev = OMAP5432_ES2_0;
+ break;
+ case OMAP5430_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = OMAP5430_ES2_0;
+ break;
+ case OMAP5432_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = OMAP5432_ES2_0;
+ break;
+ case DRA752_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = DRA752_ES1_0;
+ break;
+ case DRA752_CONTROL_ID_CODE_ES1_1:
+ *omap_si_rev = DRA752_ES1_1;
+ break;
+ case DRA752_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = DRA752_ES2_0;
+ break;
+ case DRA722_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = DRA722_ES1_0;
+ break;
+ case DRA722_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = DRA722_ES2_0;
+ break;
+ default:
+ *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
+ }
+ init_cpu_configuration();
+}
+
+void omap_die_id(unsigned int *die_id)
+{
+ die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
+ die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
+ die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
+ die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
+}
+
+void reset_cpu(ulong ignored)
+{
+ u32 omap_rev = omap_revision();
+
+ /*
+ * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
+ * So use cold reset in case instead.
+ */
+ if (omap_rev == OMAP5430_ES1_0)
+ writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
+ else
+ writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
+}
+
+u32 warm_reset(void)
+{
+ return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
+}
+
+void setup_warmreset_time(void)
+{
+ u32 rst_time, rst_val;
+
+#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+ rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
+#else
+ rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
+#endif
+ rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
+
+ if (rst_time > RSTTIME1_MASK)
+ rst_time = RSTTIME1_MASK;
+
+ rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
+ rst_val |= rst_time;
+ writel(rst_val, (*prcm)->prm_rsttime);
+}
+
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev)
+{
+ omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
+}
+
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
+{
+
+#ifdef CONFIG_ARM_ERRATA_801819
+ /*
+ * DRA72x processors are uniprocessors and DONOT have
+ * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
+ * Extensions) Hence the erratum workaround is not applicable for
+ * DRA72x processors.
+ */
+ if (is_dra72x())
+ acr &= ~((0x3 << 23) | (0x3 << 25));
+#endif
+ omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
+}
+
+#if defined(CONFIG_PALMAS_POWER)
+void vmmc_pbias_config(uint voltage)
+{
+ u32 value = 0;
+ struct vcores_data const *vcores = *omap_vcores;
+
+ value = readl((*ctrl)->control_pbias);
+ value &= ~SDCARD_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+ udelay(10); /* wait 10 us */
+ value &= ~SDCARD_BIAS_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+
+ if (vcores->core.pmic->i2c_slave_addr == 0x60) {
+ if (voltage == LDO_VOLT_3V0)
+ voltage = 0x19;
+ else if (voltage == LDO_VOLT_1V8)
+ voltage = 0xa;
+ lp873x_mmc1_poweron_ldo(voltage);
+ } else {
+ palmas_mmc1_poweron_ldo(voltage);
+ }
+
+ value = readl((*ctrl)->control_pbias);
+ value |= SDCARD_BIAS_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+ udelay(150); /* wait 150 us */
+ value |= SDCARD_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+ udelay(150); /* wait 150 us */
+}
+#endif
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/mach-omap2/omap5/prcm-regs.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap5/prcm-regs.c
rename to arch/arm/mach-omap2/omap5/prcm-regs.c
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap5/sdram.c
rename to arch/arm/mach-omap2/omap5/sdram.c
diff --git a/arch/arm/mach-omap2/omap5/sec-fxns.c b/arch/arm/mach-omap2/omap5/sec-fxns.c
new file mode 100644
index 0000000..7fab575
--- /dev/null
+++ b/arch/arm/mach-omap2/omap5/sec-fxns.c
@@ -0,0 +1,234 @@
+/*
+ *
+ * Security related functions for OMAP5 class devices
+ *
+ * (C) Copyright 2016
+ * Texas Instruments, <www.ti.com>
+ *
+ * Daniel Allred <d-allred@ti.com>
+ * Harinarayan Bhatta <harinarayan@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <stdarg.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
+#include <asm/spl.h>
+#include <spl.h>
+#include <asm/cache.h>
+#include <mapmem.h>
+#include <tee/optee.h>
+
+/* Index for signature PPA-based TI HAL APIs */
+#define PPA_HAL_SERVICES_START_INDEX (0x200)
+#define PPA_SERV_HAL_TEE_LOAD_MASTER (PPA_HAL_SERVICES_START_INDEX + 23)
+#define PPA_SERV_HAL_TEE_LOAD_SLAVE (PPA_HAL_SERVICES_START_INDEX + 24)
+#define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25)
+#define PPA_SERV_HAL_SETUP_EMIF_FW_REGION (PPA_HAL_SERVICES_START_INDEX + 26)
+#define PPA_SERV_HAL_LOCK_EMIF_FW (PPA_HAL_SERVICES_START_INDEX + 27)
+
+int tee_loaded = 0;
+
+/* Argument for PPA_SERV_HAL_TEE_LOAD_MASTER */
+struct ppa_tee_load_info {
+ u32 tee_sec_mem_start; /* Physical start address reserved for TEE */
+ u32 tee_sec_mem_size; /* Size of the memory reserved for TEE */
+ u32 tee_cert_start; /* Address where signed TEE binary is loaded */
+ u32 tee_cert_size; /* Size of TEE certificate (signed binary) */
+ u32 tee_jump_addr; /* Address to jump to start TEE execution */
+ u32 tee_arg0; /* argument to TEE jump function, in r0 */
+};
+
+static u32 get_sec_mem_start(void)
+{
+ u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
+ u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
+ /*
+ * Total reserved region is all contiguous with protected
+ * region coming first, followed by the non-secure region.
+ * If 0x0 start address is given, we simply put the reserved
+ * region at the end of the external DRAM.
+ */
+ if (sec_mem_start == 0)
+ sec_mem_start =
+ (CONFIG_SYS_SDRAM_BASE +
+ (omap_sdram_size() - sec_mem_size));
+ return sec_mem_start;
+}
+
+int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr,
+ uint32_t size, uint32_t access_perm,
+ uint32_t initiator_perm)
+{
+ int result = 1;
+
+ /*
+ * Call PPA HAL API to do any other general firewall
+ * configuration for regions 1-6 of the EMIF firewall.
+ */
+ debug("%s: regionNum = %x, startAddr = %x, size = %x", __func__,
+ region_num, start_addr, size);
+
+ result = secure_rom_call(
+ PPA_SERV_HAL_SETUP_EMIF_FW_REGION, 0, 0, 4,
+ (start_addr & 0xFFFFFFF0) | (region_num & 0x0F),
+ size, access_perm, initiator_perm);
+
+ if (result != 0) {
+ puts("Secure EMIF Firewall Setup failed!\n");
+ debug("Return Value = %x\n", result);
+ }
+
+ return result;
+}
+
+#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE < \
+ CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE)
+#error "TI Secure EMIF: Protected size cannot be larger than total size."
+#endif
+int secure_emif_reserve(void)
+{
+ int result = 1;
+ u32 sec_mem_start = get_sec_mem_start();
+ u32 sec_prot_size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
+
+ /* If there is no protected region, there is no reservation to make */
+ if (sec_prot_size == 0)
+ return 0;
+
+ /*
+ * Call PPA HAL API to reserve a chunk of EMIF SDRAM
+ * for secure world use. This region should be carved out
+ * from use by any public code. EMIF firewall region 7
+ * will be used to protect this block of memory.
+ */
+ result = secure_rom_call(
+ PPA_SERV_HAL_SETUP_SEC_RESVD_REGION,
+ 0, 0, 2, sec_mem_start, sec_prot_size);
+
+ if (result != 0) {
+ puts("SDRAM Firewall: Secure memory reservation failed!\n");
+ debug("Return Value = %x\n", result);
+ }
+
+ return result;
+}
+
+int secure_emif_firewall_lock(void)
+{
+ int result = 1;
+
+ /*
+ * Call PPA HAL API to lock the EMIF firewall configurations.
+ * After this API is called, none of the PPA HAL APIs for
+ * configuring the EMIF firewalls will be usable again (that
+ * is, calls to those APIs will return failure and have no
+ * effect).
+ */
+
+ result = secure_rom_call(
+ PPA_SERV_HAL_LOCK_EMIF_FW,
+ 0, 0, 0);
+
+ if (result != 0) {
+ puts("Secure EMIF Firewall Lock failed!\n");
+ debug("Return Value = %x\n", result);
+ }
+
+ return result;
+}
+
+static struct ppa_tee_load_info tee_info __aligned(ARCH_DMA_MINALIGN);
+
+int secure_tee_install(u32 addr)
+{
+ struct optee_header *hdr;
+ void *loadptr;
+ u32 tee_file_size;
+ u32 sec_mem_start = get_sec_mem_start();
+ const u32 size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
+ u32 *smc_cpu1_params;
+ u32 ret;
+
+ /* If there is no protected region, there is no place to put the TEE */
+ if (size == 0) {
+ printf("Error loading TEE, no protected memory region available\n");
+ return -ENOBUFS;
+ }
+
+ hdr = (struct optee_header *)map_sysmem(addr, sizeof(struct optee_header));
+ /* 280 bytes = size of signature */
+ tee_file_size = hdr->init_size + hdr->paged_size +
+ sizeof(struct optee_header) + 280;
+
+ if ((hdr->magic != OPTEE_MAGIC) ||
+ (hdr->version != OPTEE_VERSION) ||
+ (hdr->init_load_addr_hi != 0) ||
+ (hdr->init_load_addr_lo < (sec_mem_start + sizeof(struct optee_header))) ||
+ (tee_file_size > size) ||
+ ((hdr->init_load_addr_lo + tee_file_size - 1) >
+ (sec_mem_start + size - 1))) {
+ printf("Error in TEE header. Check load address and sizes\n");
+ unmap_sysmem(hdr);
+ return CMD_RET_FAILURE;
+ }
+
+ tee_info.tee_sec_mem_start = sec_mem_start;
+ tee_info.tee_sec_mem_size = size;
+ tee_info.tee_jump_addr = hdr->init_load_addr_lo;
+ tee_info.tee_cert_start = addr;
+ tee_info.tee_cert_size = tee_file_size;
+ tee_info.tee_arg0 = hdr->init_size + tee_info.tee_jump_addr;
+ unmap_sysmem(hdr);
+ loadptr = map_sysmem(addr, tee_file_size);
+
+ debug("tee_info.tee_sec_mem_start= %08X\n", tee_info.tee_sec_mem_start);
+ debug("tee_info.tee_sec_mem_size = %08X\n", tee_info.tee_sec_mem_size);
+ debug("tee_info.tee_jump_addr = %08X\n", tee_info.tee_jump_addr);
+ debug("tee_info.tee_cert_start = %08X\n", tee_info.tee_cert_start);
+ debug("tee_info.tee_cert_size = %08X\n", tee_info.tee_cert_size);
+ debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
+ debug("tee_file_size = %d\n", tee_file_size);
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ flush_dcache_range(
+ rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
+ roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
+
+ flush_dcache_range((u32)&tee_info, (u32)&tee_info +
+ roundup(sizeof(tee_info), ARCH_DMA_MINALIGN));
+#endif
+ unmap_sysmem(loadptr);
+
+ ret = secure_rom_call(PPA_SERV_HAL_TEE_LOAD_MASTER, 0, 0, 1, &tee_info);
+ if (ret) {
+ printf("TEE_LOAD_MASTER Failed\n");
+ return ret;
+ }
+ printf("TEE_LOAD_MASTER Done\n");
+
+ if (!is_dra72x()) {
+ /* Reuse the tee_info buffer for SMC params */
+ smc_cpu1_params = (u32 *)&tee_info;
+ smc_cpu1_params[0] = 0;
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
+ roundup(sizeof(u32), ARCH_DMA_MINALIGN));
+#endif
+ ret = omap_smc_sec_cpu1(PPA_SERV_HAL_TEE_LOAD_SLAVE, 0, 0,
+ smc_cpu1_params);
+ if (ret) {
+ printf("TEE_LOAD_SLAVE Failed\n");
+ return ret;
+ }
+ printf("TEE_LOAD_SLAVE Done\n");
+ }
+
+ tee_loaded = 1;
+
+ return 0;
+}
diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
new file mode 100644
index 0000000..c2a35ee
--- /dev/null
+++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
@@ -0,0 +1,123 @@
+/*
+ * Secure entry function for CPU Core #1
+ *
+ * (C) Copyright 2016
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Harinarayan Bhatta <harinarayan@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+#include <linux/linkage.h>
+
+.arch_extension sec
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+.global flush_dcache_range
+#endif
+
+#define AUX_CORE_BOOT_0 0x48281800
+#define AUX_CORE_BOOT_1 0x48281804
+
+#ifdef CONFIG_DRA7XX
+/* DRA7xx ROM code function "startup_BootSlave". This function is where CPU1
+ * waits on WFE, polling on AUX_CORE_BOOT_x registers.
+ * This address is same for J6 and J6 Eco.
+ */
+#define ROM_FXN_STARTUP_BOOTSLAVE 0x00038a64
+#endif
+
+/* Assembly core where CPU1 is woken up into
+ * No need to save-restore registers, does not use stack.
+ */
+LENTRY(cpu1_entry)
+ ldr r4, =omap_smc_sec_cpu1_args
+ ldm r4, {r0,r1,r2,r3} @ Retrieve args
+
+ mov r6, #0xFF @ Indicate new Task call
+ mov r12, #0x00 @ Secure Service ID in R12
+
+ dsb
+ dmb
+ smc 0 @ SMC #0 to enter monitor mode
+
+ b .Lend @ exit at end of the service execution
+ nop
+
+ @ In case of IRQ happening in Secure, then ARM will branch here.
+ @ At that moment, IRQ will be pending and ARM will jump to Non Secure
+ @ IRQ handler
+ mov r12, #0xFE
+
+ dsb
+ dmb
+ smc 0 @ SMC #0 to enter monitor mode
+
+.Lend:
+ ldr r4, =omap_smc_sec_cpu1_args
+ str r0, [r4, #0x10] @ save return value
+ ldr r4, =AUX_CORE_BOOT_0
+ mov r5, #0x0
+ str r5, [r4]
+ ldr r4, =ROM_FXN_STARTUP_BOOTSLAVE
+ sev @ Tell CPU0 we are done
+ bx r4 @ Jump back to ROM
+END(cpu1_entry)
+
+/*
+ * u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
+ *
+ * Makes a secure ROM/PPA call on CPU Core #1 on supported platforms.
+ * Assumes that CPU #1 is waiting in ROM code and not yet woken up or used by
+ * u-boot.
+ */
+ENTRY(omap_smc_sec_cpu1)
+ push {r4, r5, lr}
+ ldr r4, =omap_smc_sec_cpu1_args
+ stm r4, {r0,r1,r2,r3} @ Save args to memory
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ mov r0, r4
+ mov r1, #CONFIG_SYS_CACHELINE_SIZE
+ add r1, r0, r1 @ dcache is not enabled on CPU1, so
+ blx flush_dcache_range @ flush the cache on args buffer
+#endif
+ ldr r4, =AUX_CORE_BOOT_1
+ ldr r5, =cpu1_entry
+ str r5, [r4] @ Setup CPU1 entry function
+ ldr r4, =AUX_CORE_BOOT_0
+ mov r5, #0x10
+ str r5, [r4] @ Tell ROM to exit while loop
+ sev @ Wake up CPU1
+.Lwait:
+ wfe @ Wait for CPU1 to finish
+ nop
+ ldr r5, [r4] @ Check if CPU1 is done
+ cmp r5, #0
+ bne .Lwait
+
+ ldr r4, =omap_smc_sec_cpu1_args
+ ldr r0, [r4, #0x10] @ Retrieve return value
+ pop {r4, r5, pc}
+ENDPROC(omap_smc_sec_cpu1)
+
+/*
+ * Buffer to save function arguments and return value for omap_smc_sec_cpu1
+ */
+.section .data
+omap_smc_sec_cpu1_args:
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ .balign CONFIG_SYS_CACHELINE_SIZE
+ .rept CONFIG_SYS_CACHELINE_SIZE/4
+ .word 0
+ .endr
+#else
+ .rept 5
+ .word 0
+ .endr
+#endif
+END(omap_smc_sec_cpu1_args)
diff --git a/arch/arm/mach-omap2/pipe3-phy.c b/arch/arm/mach-omap2/pipe3-phy.c
new file mode 100644
index 0000000..e02e3ec
--- /dev/null
+++ b/arch/arm/mach-omap2/pipe3-phy.c
@@ -0,0 +1,231 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <sata.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include "pipe3-phy.h"
+
+/* PLLCTRL Registers */
+#define PLL_STATUS 0x00000004
+#define PLL_GO 0x00000008
+#define PLL_CONFIGURATION1 0x0000000C
+#define PLL_CONFIGURATION2 0x00000010
+#define PLL_CONFIGURATION3 0x00000014
+#define PLL_CONFIGURATION4 0x00000020
+
+#define PLL_REGM_MASK 0x001FFE00
+#define PLL_REGM_SHIFT 9
+#define PLL_REGM_F_MASK 0x0003FFFF
+#define PLL_REGM_F_SHIFT 0
+#define PLL_REGN_MASK 0x000001FE
+#define PLL_REGN_SHIFT 1
+#define PLL_SELFREQDCO_MASK 0x0000000E
+#define PLL_SELFREQDCO_SHIFT 1
+#define PLL_SD_MASK 0x0003FC00
+#define PLL_SD_SHIFT 10
+#define SET_PLL_GO 0x1
+#define PLL_TICOPWDN BIT(16)
+#define PLL_LDOPWDN BIT(15)
+#define PLL_LOCK 0x2
+#define PLL_IDLE 0x1
+
+/* PHY POWER CONTROL Register */
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
+
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
+
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
+
+
+#define PLL_IDLE_TIME 100 /* in milliseconds */
+#define PLL_LOCK_TIME 100 /* in milliseconds */
+
+static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+ return __raw_readl(addr + offset);
+}
+
+static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
+ u32 data)
+{
+ __raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
+ *pipe3)
+{
+ u32 rate;
+ struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
+
+ rate = get_sys_clk_freq();
+
+ for (; dpll_map->rate; dpll_map++) {
+ if (rate == dpll_map->rate)
+ return &dpll_map->params;
+ }
+
+ printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
+ __func__, rate);
+ return NULL;
+}
+
+
+static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
+{
+ u32 val;
+ int timeout = PLL_LOCK_TIME;
+
+ do {
+ mdelay(1);
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+ if (val & PLL_LOCK)
+ break;
+ } while (--timeout);
+
+ if (!(val & PLL_LOCK)) {
+ printf("%s: DPLL failed to lock\n", __func__);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
+{
+ u32 val;
+ struct pipe3_dpll_params *dpll_params;
+
+ dpll_params = omap_pipe3_get_dpll_params(phy);
+ if (!dpll_params) {
+ printf("%s: Invalid DPLL parameters\n", __func__);
+ return -EINVAL;
+ }
+
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+ val &= ~PLL_REGN_MASK;
+ val |= dpll_params->n << PLL_REGN_SHIFT;
+ omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+ val &= ~PLL_SELFREQDCO_MASK;
+ val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
+ omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+ val &= ~PLL_REGM_MASK;
+ val |= dpll_params->m << PLL_REGM_SHIFT;
+ omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
+ val &= ~PLL_REGM_F_MASK;
+ val |= dpll_params->mf << PLL_REGM_F_SHIFT;
+ omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
+
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
+ val &= ~PLL_SD_MASK;
+ val |= dpll_params->sd << PLL_SD_SHIFT;
+ omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
+
+ omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
+
+ return omap_pipe3_wait_lock(phy);
+}
+
+static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
+{
+ u32 val, rate;
+
+ val = readl(phy->power_reg);
+
+ rate = get_sys_clk_freq();
+ rate = rate/1000000;
+
+ if (on) {
+ val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
+ val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+ val |= rate <<
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+ } else {
+ val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
+ val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+ }
+
+ writel(val, phy->power_reg);
+}
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy)
+{
+ int ret;
+ u32 val;
+
+ /* Program the DPLL only if not locked */
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+ if (!(val & PLL_LOCK)) {
+ ret = omap_pipe3_dpll_program(phy);
+ if (ret)
+ return ret;
+ } else {
+ /* else just bring it out of IDLE mode */
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+ if (val & PLL_IDLE) {
+ val &= ~PLL_IDLE;
+ omap_pipe3_writel(phy->pll_ctrl_base,
+ PLL_CONFIGURATION2, val);
+ ret = omap_pipe3_wait_lock(phy);
+ if (ret)
+ return ret;
+ }
+ }
+
+ /* Power up the PHY */
+ omap_control_phy_power(phy, 1);
+
+ return 0;
+}
+
+int phy_pipe3_power_off(struct omap_pipe3 *phy)
+{
+ u32 val;
+ int timeout = PLL_IDLE_TIME;
+
+ /* Power down the PHY */
+ omap_control_phy_power(phy, 0);
+
+ /* Put DPLL in IDLE mode */
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+ val |= PLL_IDLE;
+ omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+ /* wait for LDO and Oscillator to power down */
+ do {
+ mdelay(1);
+ val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+ if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
+ break;
+ } while (--timeout);
+
+ if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
+ printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
+ __func__, val);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/mach-omap2/pipe3-phy.h
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/pipe3-phy.h
rename to arch/arm/mach-omap2/pipe3-phy.h
diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/mach-omap2/reset.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/reset.c
rename to arch/arm/mach-omap2/reset.c
diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/mach-omap2/sata.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/sata.c
rename to arch/arm/mach-omap2/sata.c
diff --git a/arch/arm/cpu/armv7/omap-common/sec-common.c b/arch/arm/mach-omap2/sec-common.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/sec-common.c
rename to arch/arm/mach-omap2/sec-common.c
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/mach-omap2/timer.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/timer.c
rename to arch/arm/mach-omap2/timer.c
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/mach-omap2/u-boot-spl.lds
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
rename to arch/arm/mach-omap2/u-boot-spl.lds
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/mach-omap2/utils.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/utils.c
rename to arch/arm/mach-omap2/utils.c
diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/mach-omap2/vc.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap-common/vc.c
rename to arch/arm/mach-omap2/vc.c
diff --git a/arch/arm/mach-rmobile/emac.c b/arch/arm/mach-rmobile/emac.c
index 0710cfd..e45244c 100644
--- a/arch/arm/mach-rmobile/emac.c
+++ b/arch/arm/mach-rmobile/emac.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <netdev.h>
int cpu_eth_init(bd_t *bis)
diff --git a/arch/arm/mach-rmobile/lowlevel_init_gen3.S b/arch/arm/mach-rmobile/lowlevel_init_gen3.S
index 88ff56e..11acce0 100644
--- a/arch/arm/mach-rmobile/lowlevel_init_gen3.S
+++ b/arch/arm/mach-rmobile/lowlevel_init_gen3.S
@@ -61,11 +61,18 @@
/*
* All slaves will enter EL2 and optionally EL1.
*/
+ adr x3, lowlevel_in_el2
+ ldr x4, =ES_TO_AARCH64
bl armv8_switch_to_el2
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- bl armv8_switch_to_el1
-#endif
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x3, lowlevel_in_el1
+ ldr x4, =ES_TO_AARCH64
+ bl armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
#endif /* CONFIG_ARMV8_MULTIENTRY */
bl s_init
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 1aac3c8..5c4a4c2 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -21,7 +21,7 @@
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
video interfaces supporting HDMI and eDP, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
- USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
+ USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
config ROCKCHIP_RK3399
bool "Support Rockchip RK3399"
@@ -42,6 +42,9 @@
SPL will return to the boot rom, which will then load the U-Boot
binary to keep going on.
+config SPL_MMC_SUPPORT
+ default y if !ROCKCHIP_SPL_BACK_TO_BROM
+
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 157d42f..6e79fed 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -9,7 +9,8 @@
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o
else
-obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
+obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
+obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
endif
ifndef CONFIG_ARM64
obj-y += rk_timer.o
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
deleted file mode 100644
index bec756d..0000000
--- a/arch/arm/mach-rockchip/board.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
-#include <asm/gpio.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
- struct udevice *pinctrl;
- int ret;
-
- /*
- * We need to implement sdcard iomux here for the further
- * initlization, otherwise, it'll hit sdcard command sending
- * timeout exception.
- */
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
-
- return 0;
-err:
- printf("board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
-
- return -1;
-#else
- return 0;
-#endif
-}
-
-int dram_init(void)
-{
- struct ram_info ram;
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return ret;
- }
- ret = ram_get_info(dev, &ram);
- if (ret) {
- debug("Cannot get DRAM size: %d\n", ret);
- return ret;
- }
- debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
- gd->ram_size = ram.size;
-
- return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-void lowlevel_init(void)
-{
-}
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3288_otg_data = {
- .rx_fifo_sz = 512,
- .np_tx_fifo_sz = 16,
- .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- int node, phy_node;
- const char *mode;
- bool matched = false;
- const void *blob = gd->fdt_blob;
- u32 grf_phy_offset;
-
- /* find the usb_otg node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3288-usb");
-
- while (node > 0) {
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode && strcmp(mode, "otg") == 0) {
- matched = true;
- break;
- }
-
- node = fdt_node_offset_by_compatible(blob, node,
- "rockchip,rk3288-usb");
- }
- if (!matched) {
- debug("Not found usb_otg device\n");
- return -ENODEV;
- }
- rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
- node = fdtdec_lookup_phandle(blob, node, "phys");
- if (node <= 0) {
- debug("Not found usb phy device\n");
- return -ENODEV;
- }
-
- phy_node = fdt_parent_offset(blob, node);
- if (phy_node <= 0) {
- debug("Not found usb phy device\n");
- return -ENODEV;
- }
-
- rk3288_otg_data.phy_of_node = phy_node;
- grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
-
- /* find the grf node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3288-grf");
- if (node <= 0) {
- debug("Not found grf device\n");
- return -ENODEV;
- }
- rk3288_otg_data.regs_phy = grf_phy_offset +
- fdtdec_get_addr(blob, node, "reg");
-
- return dwc2_udc_probe(&rk3288_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-#endif
-
-static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- static const struct {
- char *name;
- int id;
- } clks[] = {
- { "osc", CLK_OSC },
- { "apll", CLK_ARM },
- { "dpll", CLK_DDR },
- { "cpll", CLK_CODEC },
- { "gpll", CLK_GENERAL },
-#ifdef CONFIG_ROCKCHIP_RK3036
- { "mpll", CLK_NEW },
-#else
- { "npll", CLK_NEW },
-#endif
- };
- int ret, i;
- struct udevice *dev;
-
- ret = rockchip_get_clk(&dev);
- if (ret) {
- printf("clk-uclass not found\n");
- return 0;
- }
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- struct clk clk;
- ulong rate;
-
- clk.id = clks[i].id;
- ret = clk_request(dev, &clk);
- if (ret < 0)
- continue;
-
- rate = clk_get_rate(&clk);
- printf("%s: %lu\n", clks[i].name, rate);
-
- clk_free(&clk);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- clock, 2, 1, do_clock,
- "display information about clocks",
- ""
-);
diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c
new file mode 100644
index 0000000..bf2b268
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3036-board.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/grf_rk3036.h>
+#include <asm/arch/boot_mode.h>
+#include <asm/arch/sdram_rk3036.h>
+#include <asm/gpio.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GRF_BASE 0x20008000
+
+static void setup_boot_mode(void)
+{
+ struct rk3036_grf *const grf = (void *)GRF_BASE;
+ int boot_mode = readl(&grf->os_reg[4]);
+
+ debug("boot mode %x.\n", boot_mode);
+
+ /* Clear boot mode */
+ writel(BOOT_NORMAL, &grf->os_reg[4]);
+
+ switch (boot_mode) {
+ case BOOT_FASTBOOT:
+ printf("enter fastboot!\n");
+ setenv("preboot", "setenv preboot; fastboot usb0");
+ break;
+ case BOOT_UMS:
+ printf("enter UMS!\n");
+ setenv("preboot", "setenv preboot; ums mmc 0");
+ break;
+ }
+}
+
+__weak int rk_board_late_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_boot_mode();
+
+ return rk_board_late_init();
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = sdram_size();
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3036_otg_data = {
+ .rx_fifo_sz = 512,
+ .np_tx_fifo_sz = 16,
+ .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node;
+ const char *mode;
+ bool matched = false;
+ const void *blob = gd->fdt_blob;
+
+ /* find the usb_otg node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3288-usb");
+
+ while (node > 0) {
+ mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "rockchip,rk3288-usb");
+ }
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+ return dwc2_udc_probe(&rk3036_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig
index 0804714..9263608 100644
--- a/arch/arm/mach-rockchip/rk3036/Kconfig
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -12,6 +12,9 @@
config SYS_MALLOC_F_LEN
default 0x400
+config SPL_SERIAL_SUPPORT
+ default y
+
source "board/rockchip/evb_rk3036/Kconfig"
source "board/rockchip/kylin_rk3036/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile
index 916a7a4..20d28f7 100644
--- a/arch/arm/mach-rockchip/rk3036/Makefile
+++ b/arch/arm/mach-rockchip/rk3036/Makefile
@@ -4,6 +4,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += clk_rk3036.o
+
ifndef CONFIG_SPL_BUILD
obj-y += syscon_rk3036.o
endif
diff --git a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c
new file mode 100644
index 0000000..6a06afb
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3036.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3036_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3036_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index e0d92a6..930939a 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -64,6 +64,10 @@
}
fallback:
+#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
+ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
+ defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
+ return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_MMC1;
}
@@ -206,7 +210,7 @@
debug("DRAM init failed: %d\n", ret);
return;
}
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
#endif
}
@@ -273,6 +277,9 @@
}
preloader_console_init();
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+ back_to_bootrom();
+#endif
return;
err:
printf("spl_board_init: Error %d\n", ret);
@@ -280,7 +287,3 @@
/* No way to report error here */
hang();
}
-
-void lowlevel_init(void)
-{
-}
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
new file mode 100644
index 0000000..bca6075
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -0,0 +1,289 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch/boot_mode.h>
+#include <asm/gpio.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PMU_BASE 0xff730000
+
+static void setup_boot_mode(void)
+{
+ struct rk3288_pmu *const pmu = (void *)PMU_BASE;
+ int boot_mode = readl(&pmu->sys_reg[0]);
+
+ debug("boot mode %x.\n", boot_mode);
+
+ /* Clear boot mode */
+ writel(BOOT_NORMAL, &pmu->sys_reg[0]);
+
+ switch (boot_mode) {
+ case BOOT_FASTBOOT:
+ printf("enter fastboot!\n");
+ setenv("preboot", "setenv preboot; fastboot usb0");
+ break;
+ case BOOT_UMS:
+ printf("enter UMS!\n");
+ setenv("preboot", "setenv preboot; if mmc dev 0;"
+ "then ums mmc 0; else ums mmc 1;fi");
+ break;
+ }
+}
+
+__weak int rk_board_late_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_boot_mode();
+
+ return rk_board_late_init();
+}
+
+#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+static int veyron_init(void)
+{
+ struct udevice *dev;
+ struct clk clk;
+ int ret;
+
+ ret = regulator_get_by_platname("vdd_arm", &dev);
+ if (ret)
+ return ret;
+
+ /* Slowly raise to max CPU voltage to prevent overshoot */
+ ret = regulator_set_value(dev, 1200000);
+ if (ret)
+ return ret;
+ udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+ ret = regulator_set_value(dev, 1400000);
+ if (ret)
+ return ret;
+ udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+ ret = rockchip_get_clk(&clk.dev);
+ if (ret)
+ return ret;
+ clk.id = PLL_APLL;
+ ret = clk_set_rate(&clk, 1800000000);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+ struct udevice *pinctrl;
+ int ret;
+
+ /*
+ * We need to implement sdcard iomux here for the further
+ * initlization, otherwise, it'll hit sdcard command sending
+ * timeout exception.
+ */
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ goto err;
+ }
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+ if (ret) {
+ debug("%s: Failed to set up SD card\n", __func__);
+ goto err;
+ }
+
+ return 0;
+err:
+ printf("board_init: Error %d\n", ret);
+
+ /* No way to report error here */
+ hang();
+
+ return -1;
+#else
+ int ret;
+
+ /* We do some SoC one time setting here */
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+ ret = veyron_init();
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+#endif
+}
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("Cannot get DRAM size: %d\n", ret);
+ return ret;
+ }
+ debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
+ gd->ram_size = ram.size;
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3288_otg_data = {
+ .rx_fifo_sz = 512,
+ .np_tx_fifo_sz = 16,
+ .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node, phy_node;
+ const char *mode;
+ bool matched = false;
+ const void *blob = gd->fdt_blob;
+ u32 grf_phy_offset;
+
+ /* find the usb_otg node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3288-usb");
+
+ while (node > 0) {
+ mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "rockchip,rk3288-usb");
+ }
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+ node = fdtdec_lookup_phandle(blob, node, "phys");
+ if (node <= 0) {
+ debug("Not found usb phy device\n");
+ return -ENODEV;
+ }
+
+ phy_node = fdt_parent_offset(blob, node);
+ if (phy_node <= 0) {
+ debug("Not found usb phy device\n");
+ return -ENODEV;
+ }
+
+ rk3288_otg_data.phy_of_node = phy_node;
+ grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
+
+ /* find the grf node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3288-grf");
+ if (node <= 0) {
+ debug("Not found grf device\n");
+ return -ENODEV;
+ }
+ rk3288_otg_data.regs_phy = grf_phy_offset +
+ fdtdec_get_addr(blob, node, "reg");
+
+ return dwc2_udc_probe(&rk3288_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
+
+static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ static const struct {
+ char *name;
+ int id;
+ } clks[] = {
+ { "osc", CLK_OSC },
+ { "apll", CLK_ARM },
+ { "dpll", CLK_DDR },
+ { "cpll", CLK_CODEC },
+ { "gpll", CLK_GENERAL },
+#ifdef CONFIG_ROCKCHIP_RK3036
+ { "mpll", CLK_NEW },
+#else
+ { "npll", CLK_NEW },
+#endif
+ };
+ int ret, i;
+ struct udevice *dev;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret) {
+ printf("clk-uclass not found\n");
+ return 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ struct clk clk;
+ ulong rate;
+
+ clk.id = clks[i].id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ continue;
+
+ rate = clk_get_rate(&clk);
+ printf("%s: %lu\n", clks[i].name, rate);
+
+ clk_free(&clk);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clock, 2, 1, do_clock,
+ "display information about clocks",
+ ""
+);
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index b4113e0..223ae41 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -49,6 +49,25 @@
WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
+config TARGET_CHROMEBIT_MICKEY
+ bool "Google/Rockchip Veyron-Mickey Chromebit"
+ help
+ Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
+ and WiFi. It has a separate power port and is designed to connect
+ to the HDMI input of a monitor or TV. It has no internal battery.
+ Typically a USB hub or wireless keyboard/touchpad is used to get
+ keyboard and mouse access.
+
+config TARGET_CHROMEBOOK_MINNIE
+ bool "Google/Rockchip Veyron-Minnie Chromebook"
+ help
+ Jerry is a RK3288-based convertible clamshell device with 2 USB 3.0
+ ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
+ HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS
+ EC (Cortex-M3) to provide access to the keyboard and battery
+ functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
+ internal MMC. The product name is ASUS Chromebook Flip.
+
config TARGET_ROCK2
bool "Radxa Rock 2"
help
@@ -72,11 +91,23 @@
config SYS_MALLOC_F_LEN
default 0x0800
+config SPL_DRIVERS_MISC_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
+
source "board/chipspark/popmetal_rk3288/Kconfig"
source "board/firefly/firefly-rk3288/Kconfig"
-source "board/google/chromebook_jerry/Kconfig"
+source "board/google/veyron/Kconfig"
source "board/radxa/rock2/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3288/Makefile b/arch/arm/mach-rockchip/rk3288/Makefile
index 5ec3f0d..b5b28ef 100644
--- a/arch/arm/mach-rockchip/rk3288/Makefile
+++ b/arch/arm/mach-rockchip/rk3288/Makefile
@@ -5,5 +5,6 @@
#
obj-y += clk_rk3288.o
+obj-y += rk3288.o
obj-y += sdram_rk3288.o
obj-y += syscon_rk3288.o
diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
index 2099e34..a45b923 100644
--- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
@@ -9,9 +9,25 @@
#include <dm.h>
#include <syscon.h>
#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3288.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3288_cru), devp);
}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3288_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
new file mode 100644
index 0000000..acc3b79
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#define GRF_SOC_CON2 0xff77024c
+
+int arch_cpu_init(void)
+{
+ /* We do some SoC one time setting here. */
+
+ /* Use rkpwm by default */
+ rk_setreg(GRF_SOC_CON2, 1 << 0);
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index cf9ef2e..be3d713 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -57,6 +57,10 @@
struct regmap *map;
};
+#define TEST_PATTEN 0x5aa5f00f
+#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
+#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
+
#ifdef CONFIG_SPL_BUILD
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
@@ -214,7 +218,7 @@
}
static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
- const struct rk3288_sdram_params *sdram_params,
+ struct rk3288_sdram_params *sdram_params,
struct rk3288_grf *grf)
{
unsigned int burstlen;
@@ -264,7 +268,7 @@
}
static void phy_cfg(const struct chan_info *chan, u32 channel,
- const struct rk3288_sdram_params *sdram_params)
+ struct rk3288_sdram_params *sdram_params)
{
struct rk3288_ddr_publ *publ = chan->publ;
struct rk3288_msch *msch = chan->msch;
@@ -446,7 +450,7 @@
}
static int data_training(const struct chan_info *chan, u32 channel,
- const struct rk3288_sdram_params *sdram_params)
+ struct rk3288_sdram_params *sdram_params)
{
unsigned int j;
int ret = 0;
@@ -549,7 +553,7 @@
}
static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
- const struct rk3288_sdram_params *sdram_params)
+ struct rk3288_sdram_params *sdram_params)
{
struct rk3288_ddr_publ *publ = chan->publ;
@@ -563,7 +567,7 @@
}
static void dram_all_config(const struct dram_info *dram,
- const struct rk3288_sdram_params *sdram_params)
+ struct rk3288_sdram_params *sdram_params)
{
unsigned int chan;
u32 sys_reg = 0;
@@ -589,9 +593,191 @@
writel(sys_reg, &dram->pmu->sys_reg[2]);
rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
}
+const int ddrconf_table[] = {
+ /* row col,bw */
+ 0,
+ ((1 << 4) | 1),
+ ((2 << 4) | 1),
+ ((3 << 4) | 1),
+ ((4 << 4) | 1),
+ ((1 << 4) | 2),
+ ((2 << 4) | 2),
+ ((3 << 4) | 2),
+ ((1 << 4) | 0),
+ ((2 << 4) | 0),
+ ((3 << 4) | 0),
+ 0,
+ 0,
+ 0,
+ 0,
+ ((4 << 4) | 2),
+};
+
+static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
+ struct rk3288_sdram_params *sdram_params)
+{
+ int reg;
+ int need_trainig = 0;
+ const struct chan_info *chan = &dram->chan[channel];
+ struct rk3288_ddr_publ *publ = chan->publ;
+
+ if (-1 == data_training(chan, channel, sdram_params)) {
+ reg = readl(&publ->datx8[0].dxgsr[0]);
+ /* Check the result for rank 0 */
+ if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
+ debug("data training fail!\n");
+ return -EIO;
+ } else if ((channel == 1) &&
+ (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
+ sdram_params->num_channels = 1;
+ }
+
+ /* Check the result for rank 1 */
+ if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
+ sdram_params->ch[channel].rank = 1;
+ clrsetbits_le32(&publ->pgcr, 0xF << 18,
+ sdram_params->ch[channel].rank << 18);
+ need_trainig = 1;
+ }
+ reg = readl(&publ->datx8[2].dxgsr[0]);
+ if (reg & (1 << 4)) {
+ sdram_params->ch[channel].bw = 1;
+ set_bandwidth_ratio(chan, channel,
+ sdram_params->ch[channel].bw,
+ dram->grf);
+ need_trainig = 1;
+ }
+ }
+ /* Assume the Die bit width are the same with the chip bit width */
+ sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
+
+ if (need_trainig &&
+ (-1 == data_training(chan, channel, sdram_params))) {
+ if (sdram_params->base.dramtype == LPDDR3) {
+ ddr_phy_ctl_reset(dram->cru, channel, 1);
+ udelay(10);
+ ddr_phy_ctl_reset(dram->cru, channel, 0);
+ udelay(10);
+ }
+ debug("2nd data training failed!");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int sdram_col_row_detect(struct dram_info *dram, int channel,
+ struct rk3288_sdram_params *sdram_params)
+{
+ int row, col;
+ unsigned int addr;
+ const struct chan_info *chan = &dram->chan[channel];
+ struct rk3288_ddr_pctl *pctl = chan->pctl;
+ struct rk3288_ddr_publ *publ = chan->publ;
+ int ret = 0;
+
+ /* Detect col */
+ for (col = 11; col >= 9; col--) {
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ addr = CONFIG_SYS_SDRAM_BASE +
+ (1 << (col + sdram_params->ch[channel].bw - 1));
+ writel(TEST_PATTEN, addr);
+ if ((readl(addr) == TEST_PATTEN) &&
+ (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ break;
+ }
+ if (col == 8) {
+ printf("Col detect error\n");
+ ret = -EINVAL;
+ goto out;
+ } else {
+ sdram_params->ch[channel].col = col;
+ }
+
+ move_to_config_state(publ, pctl);
+ writel(4, &chan->msch->ddrconf);
+ move_to_access_state(chan);
+ /* Detect row*/
+ for (row = 16; row >= 12; row--) {
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(TEST_PATTEN, addr);
+ if ((readl(addr) == TEST_PATTEN) &&
+ (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ break;
+ }
+ if (row == 11) {
+ printf("Row detect error\n");
+ ret = -EINVAL;
+ } else {
+ sdram_params->ch[channel].cs1_row = row;
+ sdram_params->ch[channel].row_3_4 = 0;
+ debug("chn %d col %d, row %d\n", channel, col, row);
+ sdram_params->ch[channel].cs0_row = row;
+ }
+
+out:
+ return ret;
+}
+
+static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params)
+{
+ int i, tmp, size, ret = 0;
+
+ tmp = sdram_params->ch[0].col - 9;
+ tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
+ tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4);
+ size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
+ for (i = 0; i < size; i++)
+ if (tmp == ddrconf_table[i])
+ break;
+ if (i >= size) {
+ printf("niu config not found\n");
+ ret = -EINVAL;
+ } else {
+ sdram_params->base.ddrconfig = i;
+ }
+
+ return ret;
+}
+
+static int sdram_get_stride(struct rk3288_sdram_params *sdram_params)
+{
+ int stride = -1;
+ int ret = 0;
+ long cap = sdram_params->num_channels * (1u <<
+ (sdram_params->ch[0].cs0_row +
+ sdram_params->ch[0].col +
+ (sdram_params->ch[0].rank - 1) +
+ sdram_params->ch[0].bw +
+ 3 - 20));
+
+ switch (cap) {
+ case 512:
+ stride = 0;
+ break;
+ case 1024:
+ stride = 5;
+ break;
+ case 2048:
+ stride = 9;
+ break;
+ case 4096:
+ stride = 0xd;
+ break;
+ default:
+ stride = -1;
+ printf("could not find correct stride, cap error!\n");
+ ret = -EINVAL;
+ break;
+ }
+ sdram_params->base.stride = stride;
+
+ return ret;
+}
static int sdram_init(struct dram_info *dram,
- const struct rk3288_sdram_params *sdram_params)
+ struct rk3288_sdram_params *sdram_params)
{
int channel;
int zqcr;
@@ -619,12 +805,14 @@
struct rk3288_ddr_pctl *pctl = chan->pctl;
struct rk3288_ddr_publ *publ = chan->publ;
+ /* map all the 4GB space to the current channel */
+ if (channel)
+ rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17);
+ else
+ rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a);
phy_pctrl_reset(dram->cru, publ, channel);
phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
- if (channel >= sdram_params->num_channels)
- continue;
-
dfi_cfg(pctl, sdram_params->base.dramtype);
pctl_cfg(channel, pctl, sdram_params, dram->grf);
@@ -658,16 +846,20 @@
udelay(1);
}
+ /* Using 32bit bus width for detect */
+ sdram_params->ch[channel].bw = 2;
set_bandwidth_ratio(chan, channel,
sdram_params->ch[channel].bw, dram->grf);
/*
- * set cs
+ * set cs, using n=3 for detect
* CS0, n=1
* CS1, n=2
* CS0 & CS1, n = 3
*/
+ sdram_params->ch[channel].rank = 2,
clrsetbits_le32(&publ->pgcr, 0xF << 18,
(sdram_params->ch[channel].rank | 1) << 18);
+
/* DS=40ohm,ODT=155ohm */
zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
@@ -693,16 +885,8 @@
}
}
- if (-1 == data_training(chan, channel, sdram_params)) {
- if (sdram_params->base.dramtype == LPDDR3) {
- ddr_phy_ctl_reset(dram->cru, channel, 1);
- udelay(10);
- ddr_phy_ctl_reset(dram->cru, channel, 0);
- udelay(10);
- }
- debug("failed!");
- return -EIO;
- }
+ /* Detect the rank and bit-width with data-training */
+ sdram_rank_bw_detect(dram, channel, sdram_params);
if (sdram_params->base.dramtype == LPDDR3) {
u32 i;
@@ -710,12 +894,31 @@
for (i = 0; i < 17; i++)
send_command_op(pctl, 1, MRR_CMD, i, 0);
}
+ writel(15, &chan->msch->ddrconf);
move_to_access_state(chan);
+ /* DDR3 and LPDDR3 are always 8 bank, no need detect */
+ sdram_params->ch[channel].bk = 3;
+ /* Detect Col and Row number*/
+ ret = sdram_col_row_detect(dram, channel, sdram_params);
+ if (ret)
+ goto error;
}
+ /* Find NIU DDR configuration */
+ ret = sdram_get_niu_config(sdram_params);
+ if (ret)
+ goto error;
+ /* Find stride setting */
+ ret = sdram_get_stride(sdram_params);
+ if (ret)
+ goto error;
+
dram_all_config(dram, sdram_params);
debug("%s done\n", __func__);
return 0;
+error:
+ printf("DRAM init failed!\n");
+ hang();
}
#endif /* CONFIG_SPL_BUILD */
@@ -743,7 +946,6 @@
SYS_REG_BW_MASK));
row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
SYS_REG_ROW_3_4_MASK;
-
chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
if (rank > 1)
@@ -755,10 +957,11 @@
}
/*
- * we use the 0x00000000~0xfeffffff space since 0xff000000~0xffffffff
- * is SoC register space (i.e. reserved)
+ * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
+ * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
+ * inaccessible for some IP controller.
*/
- size_mb = min(size_mb, 0xff000000 >> 20);
+ size_mb = min(size_mb, 0xfe000000 >> 20);
return size_mb;
}
@@ -814,21 +1017,10 @@
struct rk3288_sdram_params *params = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
- int i, ret;
+ int ret;
- params->num_channels = fdtdec_get_int(blob, node,
- "rockchip,num-channels", 1);
- for (i = 0; i < params->num_channels; i++) {
- ret = fdtdec_get_byte_array(blob, node,
- "rockchip,sdram-channel",
- (u8 *)¶ms->ch[i],
- sizeof(params->ch[i]));
- if (ret) {
- debug("%s: Cannot read rockchip,sdram-channel\n",
- __func__);
- return -EINVAL;
- }
- }
+ /* Rk3288 supports dual-channel, set default channel num to 2 */
+ params->num_channels = 2;
ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
(u32 *)¶ms->pctl_timing,
sizeof(params->pctl_timing) / sizeof(u32));
@@ -869,18 +1061,15 @@
{
struct rk3288_sdram_params *plat = dev_get_platdata(dev);
struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
- int i, ret;
+ int ret;
- for (i = 0; i < 2; i++) {
- memcpy(&plat->ch[i], of_plat->rockchip_sdram_channel,
- sizeof(plat->ch[i]));
- }
memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
sizeof(plat->pctl_timing));
memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
sizeof(plat->phy_timing));
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
- plat->num_channels = of_plat->rockchip_num_channels;
+ /* Rk3288 supports dual-channel, set default channel num to 2 */
+ plat->num_channels = 2;
ret = regmap_init_mem_platdata(dev, of_plat->reg,
ARRAY_SIZE(of_plat->reg) / 2,
&plat->map);
diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile
index 607f9c9..98ebeac 100644
--- a/arch/arm/mach-rockchip/rk3399/Makefile
+++ b/arch/arm/mach-rockchip/rk3399/Makefile
@@ -4,5 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += clk_rk3399.o
obj-y += rk3399.o
obj-y += syscon_rk3399.o
diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
new file mode 100644
index 0000000..7663591
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3399.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3399_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index b9d7629..8bb950e 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -6,6 +6,10 @@
#include <common.h>
#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#define GRF_EMMCCORE_CON11 0xff77f02c
static struct mm_region rk3399_mem_map[] = {
{
@@ -28,3 +32,13 @@
};
struct mm_region *mem_map = rk3399_mem_map;
+
+int arch_cpu_init(void)
+{
+ /* We do some SoC one time setting here. */
+
+ /* Emmc clock generator: disable the clock multipilier */
+ rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
index 2d81c55..2cef68b 100644
--- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
@@ -11,6 +11,7 @@
static const struct udevice_id rk3399_syscon_ids[] = {
{ .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
};
U_BOOT_DRIVER(syscon_rk3399) = {
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 1a43c7b..6991af8 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,5 +1,32 @@
if ARCH_SOCFPGA
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ default y if DM_MMC
+
+config SPL_NAND_SUPPORT
+ default y if SPL_NAND_DENALI
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+config SPL_SPI_FLASH_SUPPORT
+ default y if SPL_SPI_SUPPORT
+
+config SPL_SPI_SUPPORT
+ default y if DM_SPI
+
+config SPL_WATCHDOG_SUPPORT
+ default y
+
config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
@@ -47,6 +74,10 @@
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_TERASIC_DE1_SOC
+ bool "Terasic DE1-SoC (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_TERASIC_SOCKIT
bool "Terasic SoCkit (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -57,6 +88,7 @@
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+ default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
@@ -71,6 +103,7 @@
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+ default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
config SYS_SOC
@@ -80,6 +113,7 @@
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+ default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c
index 43fd2fe..f909573 100644
--- a/arch/arm/mach-socfpga/fpga_manager.c
+++ b/arch/arm/mach-socfpga/fpga_manager.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c
index 2b16795..71d5d99 100644
--- a/arch/arm/mach-socfpga/freeze_controller.c
+++ b/arch/arm/mach-socfpga/freeze_controller.c
@@ -9,7 +9,7 @@
#include <asm/io.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/freeze_controller.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
new file mode 100644
index 0000000..aaada31
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -0,0 +1,28 @@
+/*
+ * Specialty padding for the Altera SoCFPGA preloader image
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+#ifdef CONFIG_SPL_BUILD
+#define ARM_SOC_BOOT0_HOOK \
+ .balignl 64,0xf33db33f; \
+ \
+ .word 0x1337c0d3; /* SoCFPGA preloader validation word */ \
+ .word 0xc01df00d; /* Version, flags, length */ \
+ .word 0xcafec0d3; /* Checksum, zero-pad */ \
+ nop; \
+ \
+ b reset; /* SoCFPGA jumps here */ \
+ nop; \
+ nop; \
+ nop;
+#else
+#define ARM_SOC_BOOT0_HOOK
+#endif
+
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index f12bb84..b11228f 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -30,7 +30,8 @@
u32 dram_timing4; /* 0x10 */
u32 lowpwr_timing;
u32 dram_odt;
- u32 __padding0[4];
+ u32 extratime1;
+ u32 __padding0[3];
u32 dram_addrw; /* 0x2c */
u32 dram_if_width; /* 0x30 */
u32 dram_dev_width;
@@ -88,6 +89,7 @@
u32 dram_timing4;
u32 lowpwr_timing;
u32 dram_odt;
+ u32 extratime1;
u32 dram_addrw;
u32 dram_if_width;
u32 dram_dev_width;
@@ -427,6 +429,10 @@
/* Field instance: sdr::ctrlgrp::dramsts */
#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
/* SDRAM width macro for configuration with ECC */
#define SDRAM_WIDTH_32BIT_WITH_ECC 40
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 5cbd8a4..dd6b53b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -362,7 +362,7 @@
* issuing warm reset. The ancient kernel code expects this
* value to be written into the register by the bootloader, so
* to support that old code, we write it here instead of in the
- * reset_cpu() function just before reseting the CPU.
+ * reset_cpu() function just before resetting the CPU.
*/
writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh
index 050d6ba..785a0d5 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -1,6 +1,14 @@
#!/bin/sh
#
+# helper function to convert from DOS to Unix, if necessary, and handle
+# lines ending in '\'.
+#
+fix_newlines_in_macros() {
+ sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
+}
+
+#
# Process iocsr_config_*.[ch]
# $1: SoC type
# $2: Input handoff directory
@@ -27,14 +35,16 @@
EOF
# Retrieve the scan chain lengths
- grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
- ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+ fix_newlines_in_macros \
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.h |
+ grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' | tr -d "()"
echo ""
# Retrieve the scan chain config and zap the ad-hoc length encoding
- sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
- ${in_bsp_dir}/generated/iocsr_config_${soc}.c
+ fix_newlines_in_macros \
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.c |
+ sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'
cat << EOF
@@ -69,8 +79,9 @@
EOF
# Retrieve the pinmux config and zap the ad-hoc length encoding
- sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \
- ${in_bsp_dir}/generated/pinmux_config_${soc}.c
+ fix_newlines_in_macros \
+ ${in_bsp_dir}/generated/pinmux_config_${soc}.c |
+ sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'
cat << EOF
@@ -105,8 +116,9 @@
EOF
# Retrieve the pll config and zap parenthesis
- sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \
- ${in_bsp_dir}/generated/pll_config.h
+ fix_newlines_in_macros \
+ ${in_bsp_dir}/generated/pll_config.h |
+ sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
cat << EOF
@@ -119,7 +131,7 @@
# Filter out only the macros which are actually used by the code
#
grep_sdram_config() {
- egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL)[[:space:]]"
+ egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
}
#
@@ -149,32 +161,37 @@
echo "/* SDRAM configuration */"
# Retrieve the sdram config, zap broken lines and zap parenthesis
- sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" \
+ fix_newlines_in_macros \
${in_bsp_dir}/generated/sdram/sdram_config.h |
+ sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer auto configuration */"
- sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
+ fix_newlines_in_macros \
${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
+ sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer defines configuration */"
- sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
+ fix_newlines_in_macros \
${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
+ sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer ac_rom_init configuration */"
- sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+ fix_newlines_in_macros \
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c |
+ sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
echo ""
echo "/* Sequencer inst_rom_init configuration */"
- sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+ fix_newlines_in_macros \
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c |
+ sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
cat << EOF
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 31cc7de..8fb808a 100644
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -81,6 +81,13 @@
SDR_CTRLGRP_DRAMODT_READ_LSB) |
(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
SDR_CTRLGRP_DRAMODT_WRITE_LSB),
+ .extratime1 =
+ (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+ SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+ SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
+(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+ SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
.dram_addrw =
(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 25367cf..e73114e 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -32,7 +32,7 @@
else
obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
endif
-obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
+obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
@@ -49,4 +49,5 @@
obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o
+obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o
endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 6d9518d..aa11493 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -133,13 +133,17 @@
return 0;
}
-int spl_board_load_image(void)
+#ifdef CONFIG_SPL_BUILD
+static int spl_board_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
return_to_fel(fel_stash.sp, fel_stash.lr);
return 0;
}
+SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+#endif
void s_init(void)
{
@@ -178,7 +182,8 @@
#if defined CONFIG_MACH_SUN6I || \
defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN8I
+ defined CONFIG_MACH_SUN8I || \
+ defined CONFIG_MACH_SUN9I
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
@@ -242,15 +247,6 @@
return -1; /* Never reached */
}
-/*
- * Properly announce BOOT_DEVICE_BOARD as "FEL".
- * Overrides weak function from common/spl/spl.c
- */
-void spl_board_announce_boot_device(void)
-{
- printf("FEL");
-}
-
/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(const u32 boot_device)
{
diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c
index 0b8fc94..e6f53f9 100644
--- a/arch/arm/mach-sunxi/clock.c
+++ b/arch/arm/mach-sunxi/clock.c
@@ -13,16 +13,22 @@
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/prcm.h>
+#include <asm/arch/gtbus.h>
#include <asm/arch/sys_proto.h>
__weak void clock_init_sec(void)
{
}
+__weak void gtbus_init(void)
+{
+}
+
int clock_init(void)
{
#ifdef CONFIG_SPL_BUILD
clock_init_safe();
+ gtbus_init();
#endif
clock_init_uart();
clock_init_sec();
diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c
index 180634c..69930cf 100644
--- a/arch/arm/mach-sunxi/clock_sun9i.c
+++ b/arch/arm/mach-sunxi/clock_sun9i.c
@@ -1,8 +1,12 @@
+
/*
* sun9i specific clock code
*
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -12,6 +16,57 @@
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+
+void clock_init_safe(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* Set up PLL12 (peripheral 1) */
+ clock_set_pll12(1200000000);
+
+ /* Set up PLL1 (cluster 0) and PLL2 (cluster 1) */
+ clock_set_pll1(408000000);
+ clock_set_pll2(408000000);
+
+ /* Set up PLL4 (peripheral 0) */
+ clock_set_pll4(960000000);
+
+ /* Set up dividers for AXI0 and APB0 on cluster 0: PLL1 / 2 = 204MHz */
+ writel(C0_CFG_AXI0_CLK_DIV_RATIO(2) |
+ C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg);
+
+ /* AHB0: 120 MHz (PLL_PERIPH0 / 8) */
+ writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8),
+ &ccm->ahb0_cfg);
+ /* AHB1: 240 MHz (PLL_PERIPH0 / 4) */
+ writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(4),
+ &ccm->ahb1_cfg);
+ /* AHB2: 120 MHz (PLL_PERIPH0 / 8) */
+ writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8),
+ &ccm->ahb2_cfg);
+ /* APB0: 120 MHz (PLL_PERIPH0 / 8) */
+ writel(APB0_SRC_PLL_PERIPH0 | APB0_CLK_DIV_RATIO(8),
+ &ccm->apb0_cfg);
+
+ /* GTBUS: 400MHz (PERIPH0 div 3) */
+ writel(GTBUS_SRC_PLL_PERIPH1 | GTBUS_CLK_DIV_RATIO(3),
+ &ccm->gtbus_cfg);
+ /* CCI400: 480MHz (PERIPH1 div 2) */
+ writel(CCI400_SRC_PLL_PERIPH0 | CCI400_CLK_DIV_RATIO(2),
+ &ccm->cci400_cfg);
+
+ /* Deassert DMA reset and open clock gating for DMA */
+ setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24));
+ setbits_le32(&ccm->apb1_gate, (1 << 24));
+
+ /* set enable-bit in TSTAMP_CTRL_REG */
+ writel(1, 0x01720000);
+}
+#endif
+
void clock_init_uart(void)
{
struct sunxi_ccm_reg *const ccm =
@@ -25,11 +80,98 @@
setbits_le32(&ccm->apb1_reset_cfg,
1 << (APB1_RESET_UART_SHIFT +
CONFIG_CONS_INDEX - 1));
-
- /* Dup with clock_init_safe(), drop once sun9i SPL support lands */
- writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg);
}
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int p = 0;
+
+ /* Switch cluster 0 to 24MHz clock while changing PLL1 */
+ clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,
+ C0_CPUX_CLK_SRC_OSC24M);
+
+ writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
+ CCM_PLL1_CLOCK_TIME_2 |
+ CCM_PLL1_CTRL_N(clk / 24000000),
+ &ccm->pll1_c0_cfg);
+ /*
+ * Don't bother with the stable-time registers, as it doesn't
+ * wait until the PLL is stable. Note, that even Allwinner
+ * just uses a delay loop (or rather the AVS timer) for this
+ * instead of the PLL_STABLE_STATUS register.
+ */
+ sdelay(2000);
+
+ /* Switch cluster 0 back to PLL1 */
+ clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,
+ C0_CPUX_CLK_SRC_PLL1);
+}
+
+void clock_set_pll2(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int p = 0;
+
+ /* Switch cluster 1 to 24MHz clock while changing PLL2 */
+ clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
+ C1_CPUX_CLK_SRC_OSC24M);
+
+ writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) |
+ CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000),
+ &ccm->pll2_c1_cfg);
+
+ sdelay(2000);
+
+ /* Switch cluster 1 back to PLL2 */
+ clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
+ C1_CPUX_CLK_SRC_PLL2);
+}
+
+void clock_set_pll6(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int p = 0;
+
+ writel(CCM_PLL6_CTRL_EN | CCM_PLL6_CFG_UPDATE | CCM_PLL6_CTRL_P(p)
+ | CCM_PLL6_CTRL_N(clk / 24000000),
+ &ccm->pll6_ddr_cfg);
+ do { } while (!(readl(&ccm->pll_stable_status) & PLL_DDR_STATUS));
+
+ sdelay(2000);
+}
+
+void clock_set_pll12(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN)
+ return;
+
+ writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000),
+ &ccm->pll12_periph1_cfg);
+
+ sdelay(2000);
+}
+
+
+void clock_set_pll4(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000),
+ &ccm->pll4_periph0_cfg);
+
+ sdelay(2000);
+}
+#endif
+
int clock_twi_onoff(int port, int state)
{
struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 76b6719..f1f6fd5 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -99,10 +99,54 @@
}
#endif
+#ifdef CONFIG_MACH_SUN8I_H3
+
+#define SIDC_PRCTL 0x40
+#define SIDC_RDKEY 0x60
+
+#define SIDC_OP_LOCK 0xAC
+
+uint32_t sun8i_efuse_read(uint32_t offset)
+{
+ uint32_t reg_val;
+
+ reg_val = readl(SUNXI_SIDC_BASE + SIDC_PRCTL);
+ reg_val &= ~(((0x1ff) << 16) | 0x3);
+ reg_val |= (offset << 16);
+ writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
+
+ reg_val &= ~(((0xff) << 8) | 0x3);
+ reg_val |= (SIDC_OP_LOCK << 8) | 0x2;
+ writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
+
+ while (readl(SUNXI_SIDC_BASE + SIDC_PRCTL) & 0x2);
+
+ reg_val &= ~(((0x1ff) << 16) | ((0xff) << 8) | 0x3);
+ writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
+
+ reg_val = readl(SUNXI_SIDC_BASE + SIDC_RDKEY);
+ return reg_val;
+}
+#endif
+
int sunxi_get_sid(unsigned int *sid)
{
#ifdef CONFIG_AXP221_POWER
return axp_get_sid(sid);
+#elif defined CONFIG_MACH_SUN8I_H3
+ /*
+ * H3 SID controller has a bug, which makes the initial value of
+ * SUNXI_SID_BASE at boot wrong.
+ * Read the value directly from SID controller, in order to get
+ * the correct value, and also refresh the wrong value at
+ * SUNXI_SID_BASE.
+ */
+ int i;
+
+ for (i = 0; i< 4; i++)
+ sid[i] = sun8i_efuse_read(i * 4);
+
+ return 0;
#elif defined SUNXI_SID_BASE
int i;
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 2020d75..b08b8e6 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -217,35 +217,57 @@
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- int i;
- u16 zq_val[6];
- u8 val;
+ if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
+ (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
+ u32 reg_val;
- writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
-
- for (i = 0; i < 6; i++) {
- u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
-
- writel((zq << 20) | (zq << 16) | (zq << 12) |
- (zq << 8) | (zq << 4) | (zq << 0),
- &mctl_ctl->zqcr);
+ clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
+ CONFIG_DRAM_ZQ & 0xffff);
writel(PIR_CLRSR, &mctl_ctl->pir);
mctl_phy_init(PIR_ZCAL);
- zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
- writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
+ reg_val = readl(&mctl_ctl->zqdr[0]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[0]);
- writel(PIR_CLRSR, &mctl_ctl->pir);
- mctl_phy_init(PIR_ZCAL);
+ reg_val = readl(&mctl_ctl->zqdr[1]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[1]);
+ writel(reg_val, &mctl_ctl->zqdr[2]);
+ } else {
+ int i;
+ u16 zq_val[6];
+ u8 val;
- val = readl(&mctl_ctl->zqdr[0]) >> 24;
- zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
+ writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
+
+ for (i = 0; i < 6; i++) {
+ u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
+
+ writel((zq << 20) | (zq << 16) | (zq << 12) |
+ (zq << 8) | (zq << 4) | (zq << 0),
+ &mctl_ctl->zqcr);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
+ writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ val = readl(&mctl_ctl->zqdr[0]) >> 24;
+ zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
+ }
+
+ writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
+ writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
+ writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
}
-
- writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
- writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
- writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
}
static void mctl_set_cr(struct dram_para *para)
diff --git a/arch/arm/mach-sunxi/dram_sun9i.c b/arch/arm/mach-sunxi/dram_sun9i.c
new file mode 100644
index 0000000..8c681f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_sun9i.c
@@ -0,0 +1,961 @@
+/*
+ * sun9i dram controller initialisation
+ *
+ * (C) Copyright 2007-2015
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Jerry Wang <wangflord@allwinnertech.com>
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
+
+/*
+ * The following amounts to an extensive rewrite of the code received from
+ * Allwinner as part of the open-source bootloader release (refer to
+ * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
+ * sources (which act as the primary reference point for the inner workings
+ * of the 'underdocumented' DRAM controller in the A80) using the following
+ * documentation for other memory controllers based on the (Synopsys)
+ * Designware IP (DDR memory protocol controller and DDR PHY)
+ * * TI Keystone II Architecture: DDR3 Memory Controller, User's Guide
+ * Document 'SPRUHN7C', Oct 2013 (revised March 2015)
+ * * Xilinx Zynq UltraScale+ MPSoC Register Reference
+ * document ug1087 (v1.0)
+ * Note that the Zynq-documentation provides a very close match for the DDR
+ * memory protocol controller (and provides a very good guide to the rounding
+ * rules for various timings), whereas the TI Keystone II document should be
+ * referred to for DDR PHY specifics only.
+ *
+ * The DRAM controller in the A80 runs at half the frequency of the DDR PHY
+ * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
+ *
+ * Known limitations
+ * =================
+ * In the current state, the following features are not fully supported and
+ * a number of simplifying assumptions have been made:
+ * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
+ * module) is designed to accomodate DDR3/DDR3L.
+ * 2) Only 2T-mode has been implemented and tested.
+ * 3) The controller supports two different clocking strategies (PLL6 can
+ * either be 2*CK or CK/2)... we only support the 2*CK clock at this
+ * time and haven't verified whether the alternative clocking strategy
+ * works. If you are interested in porting this over/testing this,
+ * please refer to cases where bit 0 of 'dram_tpr8' is tested in the
+ * original code from Allwinner.
+ * 4) Support for 2 ranks per controller is not implemented (as we don't
+ * the hardware to test it).
+ *
+ * Future directions
+ * =================
+ * The driver should be driven from a device-tree based configuration that
+ * can dynamically provide the necessary timing parameters (i.e. target
+ * frequency and speed-bin information)---the data structures used in the
+ * calculation of the timing parameters are already designed to capture
+ * similar information as the device tree would provide.
+ *
+ * To enable a device-tree based configuration of the sun9i platform, we
+ * will need to enable CONFIG_TPL and bootstrap in 3 stages: initially
+ * into SRAM A1 (40KB) and next into SRAM A2 (160KB)---which would be the
+ * stage to initialise the platform via the device-tree---before having
+ * the full U-Boot run from DDR.
+ */
+
+/*
+ * A number of DDR3 timings are given as "the greater of a fixed number of
+ * clock cycles (CK) or nanoseconds. We express these using a structure
+ * that holds a cycle count and a duration in picoseconds (so we can model
+ * sub-ns timings, such as 7.5ns without losing precision or resorting to
+ * rounding up early.
+ */
+struct dram_sun9i_timing {
+ u32 ck;
+ u32 ps;
+};
+
+/* */
+struct dram_sun9i_cl_cwl_timing {
+ u32 CL;
+ u32 CWL;
+ u32 tCKmin; /* in ps */
+ u32 tCKmax; /* in ps */
+};
+
+struct dram_sun9i_para {
+ u32 dram_type;
+
+ u8 bus_width;
+ u8 chan;
+ u8 rank;
+ u8 rows;
+ u16 page_size;
+
+ /* Timing information for each speed-bin */
+ struct dram_sun9i_cl_cwl_timing *cl_cwl_table;
+ u32 cl_cwl_numentries;
+
+ /*
+ * For the timings, we try to keep the order and grouping used in
+ * JEDEC Standard No. 79-3F
+ */
+
+ /* timings */
+ u32 tREFI; /* in ns */
+ u32 tRFC; /* in ns */
+
+ u32 tRAS; /* in ps */
+
+ /* command and address timing */
+ u32 tDLLK; /* in nCK */
+ struct dram_sun9i_timing tRTP;
+ struct dram_sun9i_timing tWTR;
+ u32 tWR; /* in nCK */
+ u32 tMRD; /* in nCK */
+ struct dram_sun9i_timing tMOD;
+ u32 tRCD; /* in ps */
+ u32 tRP; /* in ps */
+ u32 tRC; /* in ps */
+ u32 tCCD; /* in nCK */
+ struct dram_sun9i_timing tRRD;
+ u32 tFAW; /* in ps */
+
+ /* calibration timing */
+ /* struct dram_sun9i_timing tZQinit; */
+ struct dram_sun9i_timing tZQoper;
+ struct dram_sun9i_timing tZQCS;
+
+ /* reset timing */
+ /* struct dram_sun9i_timing tXPR; */
+
+ /* self-refresh timings */
+ struct dram_sun9i_timing tXS;
+ u32 tXSDLL; /* in nCK */
+ /* struct dram_sun9i_timing tCKESR; */
+ struct dram_sun9i_timing tCKSRE;
+ struct dram_sun9i_timing tCKSRX;
+
+ /* power-down timings */
+ struct dram_sun9i_timing tXP;
+ struct dram_sun9i_timing tXPDLL;
+ struct dram_sun9i_timing tCKE;
+
+ /* write leveling timings */
+ u32 tWLMRD; /* min, in nCK */
+ /* u32 tWLDQSEN; min, in nCK */
+ u32 tWLO; /* max, in ns */
+ /* u32 tWLOE; max, in ns */
+
+ /* u32 tCKDPX; in nCK */
+ /* u32 tCKCSX; in nCK */
+};
+
+static void mctl_sys_init(void);
+
+#define SCHED_RDWR_IDLE_GAP(n) ((n & 0xff) << 24)
+#define SCHED_GO2CRITICAL_HYSTERESIS(n) ((n & 0xff) << 16)
+#define SCHED_LPR_NUM_ENTRIES(n) ((n & 0xff) << 8)
+#define SCHED_PAGECLOSE (1 << 2)
+#define SCHED_PREFER_WRITE (1 << 1)
+#define SCHED_FORCE_LOW_PRI_N (1 << 0)
+
+#define SCHED_CONFIG (SCHED_RDWR_IDLE_GAP(0xf) | \
+ SCHED_GO2CRITICAL_HYSTERESIS(0x80) | \
+ SCHED_LPR_NUM_ENTRIES(0x20) | \
+ SCHED_FORCE_LOW_PRI_N)
+#define PERFHPR0_CONFIG 0x0000001f
+#define PERFHPR1_CONFIG 0x1f00001f
+#define PERFLPR0_CONFIG 0x000000ff
+#define PERFLPR1_CONFIG 0x0f0000ff
+#define PERFWR0_CONFIG 0x000000ff
+#define PERFWR1_CONFIG 0x0f0001ff
+
+static void mctl_ctl_sched_init(unsigned long base)
+{
+ struct sunxi_mctl_ctl_reg *mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)base;
+
+ /* Needs to be done before the global clk enable... */
+ writel(SCHED_CONFIG, &mctl_ctl->sched);
+ writel(PERFHPR0_CONFIG, &mctl_ctl->perfhpr0);
+ writel(PERFHPR1_CONFIG, &mctl_ctl->perfhpr1);
+ writel(PERFLPR0_CONFIG, &mctl_ctl->perflpr0);
+ writel(PERFLPR1_CONFIG, &mctl_ctl->perflpr1);
+ writel(PERFWR0_CONFIG, &mctl_ctl->perfwr0);
+ writel(PERFWR1_CONFIG, &mctl_ctl->perfwr1);
+}
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ debug("Setting PLL6 to %d\n", DRAM_CLK * 2);
+ clock_set_pll6(DRAM_CLK * 2);
+
+ /* Original dram init code which may come in handy later
+ ********************************************************
+ clock_set_pll6(use_2channelPLL ? (DRAM_CLK * 2) :
+ (DRAM_CLK / 2), false);
+
+ if ((para->dram_clk <= 400)|((para->dram_tpr8 & 0x1)==0)) {
+ * PLL6 should be 2*CK *
+ * ccm_setup_pll6_ddr_clk(PLL6_DDR_CLK); *
+ ccm_setup_pll6_ddr_clk((1000000 * (para->dram_clk) * 2), 0);
+ } else {
+ * PLL6 should be CK/2 *
+ ccm_setup_pll6_ddr_clk((1000000 * (para->dram_clk) / 2), 1);
+ }
+
+ if (para->dram_tpr13 & (0xf<<18)) {
+ *
+ * bit21:bit18=0001:pll swing 0.4
+ * bit21:bit18=0010:pll swing 0.3
+ * bit21:bit18=0100:pll swing 0.2
+ * bit21:bit18=1000:pll swing 0.1
+ *
+ dram_dbg("DRAM fre extend open !\n");
+ reg_val=mctl_read_w(CCM_PLL6_DDR_REG);
+ reg_val&=(0x1<<16);
+ reg_val=reg_val>>16;
+
+ if(para->dram_tpr13 & (0x1<<18))
+ {
+ mctl_write_w(CCM_PLL_BASE + 0x114,
+ (0x3333U|(0x3<<17)|(reg_val<<19)|(0x120U<<20)|
+ (0x2U<<29)|(0x1U<<31)));
+ }
+ else if(para->dram_tpr13 & (0x1<<19))
+ {
+ mctl_write_w(CCM_PLL_BASE + 0x114,
+ (0x6666U|(0x3U<<17)|(reg_val<<19)|(0xD8U<<20)|
+ (0x2U<<29)|(0x1U<<31)));
+ }
+ else if(para->dram_tpr13 & (0x1<<20))
+ {
+ mctl_write_w(CCM_PLL_BASE + 0x114,
+ (0x9999U|(0x3U<<17)|(reg_val<<19)|(0x90U<<20)|
+ (0x2U<<29)|(0x1U<<31)));
+ }
+ else if(para->dram_tpr13 & (0x1<<21))
+ {
+ mctl_write_w(CCM_PLL_BASE + 0x114,
+ (0xccccU|(0x3U<<17)|(reg_val<<19)|(0x48U<<20)|
+ (0x2U<<29)|(0x1U<<31)));
+ }
+
+ //frequency extend open
+ reg_val = mctl_read_w(CCM_PLL6_DDR_REG);
+ reg_val |= ((0x1<<24)|(0x1<<30));
+ mctl_write_w(CCM_PLL6_DDR_REG, reg_val);
+
+
+ while(mctl_read_w(CCM_PLL6_DDR_REG) & (0x1<<30));
+ }
+
+ aw_delay(0x20000); //make some delay
+ ********************************************************
+ */
+
+ /* assert mctl reset */
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ /* stop mctl clock */
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+
+ sdelay(2000);
+
+ /* deassert mctl reset */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ /* enable mctl clock */
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+
+ /* set up the transactions scheduling before enabling the global clk */
+ mctl_ctl_sched_init(SUNXI_DRAM_CTL0_BASE);
+ mctl_ctl_sched_init(SUNXI_DRAM_CTL1_BASE);
+ sdelay(1000);
+
+ debug("2\n");
+
+ /* (3 << 12): PLL_DDR */
+ writel((3 << 12) | (1 << 16), &ccm->dram_clk_cfg);
+ do {
+ debug("Waiting for DRAM_CLK_CFG\n");
+ sdelay(10000);
+ } while (readl(&ccm->dram_clk_cfg) & (1 << 16));
+ setbits_le32(&ccm->dram_clk_cfg, (1 << 31));
+
+ /* TODO: we only support the common case ... i.e. 2*CK */
+ setbits_le32(&mctl_com->ccr, (1 << 14) | (1 << 30));
+ writel(2, &mctl_com->rmcr); /* controller clock is PLL6/4 */
+
+ sdelay(2000);
+
+ /* Original dram init code which may come in handy later
+ ********************************************************
+ if ((para->dram_clk <= 400) | ((para->dram_tpr8 & 0x1) == 0)) {
+ * PLL6 should be 2*CK *
+ * gating 2 channel pll *
+ reg_val = mctl_read_w(MC_CCR);
+ reg_val |= ((0x1 << 14) | (0x1U << 30));
+ mctl_write_w(MC_CCR, reg_val);
+ mctl_write_w(MC_RMCR, 0x2); * controller clock use pll6/4 *
+ } else {
+ * enable 2 channel pll *
+ reg_val = mctl_read_w(MC_CCR);
+ reg_val &= ~((0x1 << 14) | (0x1U << 30));
+ mctl_write_w(MC_CCR, reg_val);
+ mctl_write_w(MC_RMCR, 0x0); * controller clock use pll6 *
+ }
+
+ reg_val = mctl_read_w(MC_CCR);
+ reg_val &= ~((0x1<<15)|(0x1U<<31));
+ mctl_write_w(MC_CCR, reg_val);
+ aw_delay(20);
+ //aw_delay(0x10);
+ ********************************************************
+ */
+
+ clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN | MCTL_CCR_CH1_CLK_EN);
+ sdelay(1000);
+
+ setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
+ /* TODO if (para->chan == 2) */
+ setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
+}
+
+static void mctl_com_init(struct dram_sun9i_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* TODO: hard-wired for DDR3 now */
+ writel(((para->chan == 2) ? MCTL_CR_CHANNEL_DUAL :
+ MCTL_CR_CHANNEL_SINGLE)
+ | MCTL_CR_DRAMTYPE_DDR3 | MCTL_CR_BANK(1)
+ | MCTL_CR_ROW(para->rows)
+ | ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16)
+ | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_RANK(para->rank),
+ &mctl_com->cr);
+
+ debug("CR: %d\n", readl(&mctl_com->cr));
+}
+
+static u32 mctl_channel_init(u32 ch_index, struct dram_sun9i_para *para)
+{
+ struct sunxi_mctl_ctl_reg *mctl_ctl;
+ struct sunxi_mctl_phy_reg *mctl_phy;
+
+ u32 CL = 0;
+ u32 CWL = 0;
+ u16 mr[4] = { 0, };
+
+#define PS2CYCLES_FLOOR(n) ((n * CONFIG_DRAM_CLK) / 1000000)
+#define PS2CYCLES_ROUNDUP(n) ((n * CONFIG_DRAM_CLK + 999999) / 1000000)
+#define NS2CYCLES_FLOOR(n) ((n * CONFIG_DRAM_CLK) / 1000)
+#define NS2CYCLES_ROUNDUP(n) ((n * CONFIG_DRAM_CLK + 999) / 1000)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+
+ /*
+ * Convert the values to cycle counts (nCK) from what is provided
+ * by the definition of each speed bin.
+ */
+ /* const u32 tREFI = NS2CYCLES_FLOOR(para->tREFI); */
+ const u32 tREFI = NS2CYCLES_FLOOR(para->tREFI);
+ const u32 tRFC = NS2CYCLES_ROUNDUP(para->tRFC);
+ const u32 tRCD = PS2CYCLES_ROUNDUP(para->tRCD);
+ const u32 tRP = PS2CYCLES_ROUNDUP(para->tRP);
+ const u32 tRC = PS2CYCLES_ROUNDUP(para->tRC);
+ const u32 tRAS = PS2CYCLES_ROUNDUP(para->tRAS);
+
+ /* command and address timing */
+ const u32 tDLLK = para->tDLLK;
+ const u32 tRTP = MAX(para->tRTP.ck, PS2CYCLES_ROUNDUP(para->tRTP.ps));
+ const u32 tWTR = MAX(para->tWTR.ck, PS2CYCLES_ROUNDUP(para->tWTR.ps));
+ const u32 tWR = NS2CYCLES_FLOOR(para->tWR);
+ const u32 tMRD = para->tMRD;
+ const u32 tMOD = MAX(para->tMOD.ck, PS2CYCLES_ROUNDUP(para->tMOD.ps));
+ const u32 tCCD = para->tCCD;
+ const u32 tRRD = MAX(para->tRRD.ck, PS2CYCLES_ROUNDUP(para->tRRD.ps));
+ const u32 tFAW = PS2CYCLES_ROUNDUP(para->tFAW);
+
+ /* calibration timings */
+ /* const u32 tZQinit = MAX(para->tZQinit.ck,
+ PS2CYCLES_ROUNDUP(para->tZQinit.ps)); */
+ const u32 tZQoper = MAX(para->tZQoper.ck,
+ PS2CYCLES_ROUNDUP(para->tZQoper.ps));
+ const u32 tZQCS = MAX(para->tZQCS.ck,
+ PS2CYCLES_ROUNDUP(para->tZQCS.ps));
+
+ /* reset timing */
+ /* const u32 tXPR = MAX(para->tXPR.ck,
+ PS2CYCLES_ROUNDUP(para->tXPR.ps)); */
+
+ /* power-down timings */
+ const u32 tXP = MAX(para->tXP.ck, PS2CYCLES_ROUNDUP(para->tXP.ps));
+ const u32 tXPDLL = MAX(para->tXPDLL.ck,
+ PS2CYCLES_ROUNDUP(para->tXPDLL.ps));
+ const u32 tCKE = MAX(para->tCKE.ck, PS2CYCLES_ROUNDUP(para->tCKE.ps));
+
+ /*
+ * self-refresh timings (keep below power-down timings, as tCKESR
+ * needs to be calculated based on the nCK value of tCKE)
+ */
+ const u32 tXS = MAX(para->tXS.ck, PS2CYCLES_ROUNDUP(para->tXS.ps));
+ const u32 tXSDLL = para->tXSDLL;
+ const u32 tCKSRE = MAX(para->tCKSRE.ck,
+ PS2CYCLES_ROUNDUP(para->tCKSRE.ps));
+ const u32 tCKESR = tCKE + 1;
+ const u32 tCKSRX = MAX(para->tCKSRX.ck,
+ PS2CYCLES_ROUNDUP(para->tCKSRX.ps));
+
+ /* write leveling timings */
+ const u32 tWLMRD = para->tWLMRD;
+ /* const u32 tWLDQSEN = para->tWLDQSEN; */
+ const u32 tWLO = PS2CYCLES_FLOOR(para->tWLO);
+ /* const u32 tWLOE = PS2CYCLES_FLOOR(para->tWLOE); */
+
+ const u32 tRASmax = tREFI * 9;
+ int i;
+
+ for (i = 0; i < para->cl_cwl_numentries; ++i) {
+ const u32 tCK = 1000000 / CONFIG_DRAM_CLK;
+
+ if ((para->cl_cwl_table[i].tCKmin <= tCK) &&
+ (tCK < para->cl_cwl_table[i].tCKmax)) {
+ CL = para->cl_cwl_table[i].CL;
+ CWL = para->cl_cwl_table[i].CWL;
+
+ debug("found CL/CWL: CL = %d, CWL = %d\n", CL, CWL);
+ break;
+ }
+ }
+
+ if ((CL == 0) && (CWL == 0)) {
+ printf("failed to find valid CL/CWL for operating point %d MHz\n",
+ CONFIG_DRAM_CLK);
+ return 0;
+ }
+
+ if (ch_index == 0) {
+ mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ } else {
+ mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+ }
+
+ if (para->dram_type == DRAM_TYPE_DDR3) {
+ mr[0] = DDR3_MR0_PPD_FAST_EXIT | DDR3_MR0_WR(tWR) |
+ DDR3_MR0_CL(CL);
+ mr[1] = DDR3_MR1_RTT120OHM;
+ mr[2] = DDR3_MR2_TWL(CWL);
+ mr[3] = 0;
+
+ /*
+ * DRAM3 initialisation requires holding CKE LOW for
+ * at least 500us prior to starting the initialisation
+ * sequence and at least 10ns after driving CKE HIGH
+ * before the initialisation sequence may be started).
+ *
+ * Refer to Micron document "TN-41-07: DDR3 Power-Up,
+ * Initialization, and Reset DDR3 Initialization
+ * Routine" for details).
+ */
+ writel(MCTL_INIT0_POST_CKE_x1024(1) |
+ MCTL_INIT0_PRE_CKE_x1024(
+ (500 * CONFIG_DRAM_CLK + 1023) / 1024), /* 500us */
+ &mctl_ctl->init[0]);
+ writel(MCTL_INIT1_DRAM_RSTN_x1024(1),
+ &mctl_ctl->init[1]);
+ /* INIT2 is not used for DDR3 */
+ writel(MCTL_INIT3_MR(mr[0]) | MCTL_INIT3_EMR(mr[1]),
+ &mctl_ctl->init[3]);
+ writel(MCTL_INIT4_EMR2(mr[2]) | MCTL_INIT4_EMR3(mr[3]),
+ &mctl_ctl->init[4]);
+ writel(MCTL_INIT5_DEV_ZQINIT_x32(512 / 32), /* 512 cycles */
+ &mctl_ctl->init[5]);
+ } else {
+ /* !!! UNTESTED !!! */
+ /*
+ * LPDDR2 and/or LPDDR3 require a 200us minimum delay
+ * after driving CKE HIGH in the initialisation sequence.
+ */
+ writel(MCTL_INIT0_POST_CKE_x1024(
+ (200 * CONFIG_DRAM_CLK + 1023) / 1024),
+ &mctl_ctl->init[0]);
+ writel(MCTL_INIT1_DRAM_RSTN_x1024(1),
+ &mctl_ctl->init[1]);
+ writel(MCTL_INIT2_IDLE_AFTER_RESET_x32(
+ (CONFIG_DRAM_CLK + 31) / 32) /* 1us */
+ | MCTL_INIT2_MIN_STABLE_CLOCK_x1(5), /* 5 cycles */
+ &mctl_ctl->init[2]);
+ writel(MCTL_INIT3_MR(mr[1]) | MCTL_INIT3_EMR(mr[2]),
+ &mctl_ctl->init[3]);
+ writel(MCTL_INIT4_EMR2(mr[3]),
+ &mctl_ctl->init[4]);
+ writel(MCTL_INIT5_DEV_ZQINIT_x32(
+ (CONFIG_DRAM_CLK + 31) / 32) /* 1us */
+ | MCTL_INIT5_MAX_AUTO_INIT_x1024(
+ (10 * CONFIG_DRAM_CLK + 1023) / 1024),
+ &mctl_ctl->init[5]);
+ }
+
+ /* (DDR3) We always use a burst-length of 8. */
+#define MCTL_BL 8
+ /* wr2pre: WL + BL/2 + tWR */
+#define WR2PRE (MCTL_BL/2 + CWL + tWTR)
+ /* wr2rd = CWL + BL/2 + tWTR */
+#define WR2RD (MCTL_BL/2 + CWL + tWTR)
+ /*
+ * rd2wr = RL + BL/2 + 2 - WL (for DDR3)
+ * rd2wr = RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL (for LPDDR2/LPDDR3)
+ */
+#define RD2WR (CL + MCTL_BL/2 + 2 - CWL)
+#define MCTL_PHY_TRTW 0
+#define MCTL_PHY_TRTODT 0
+
+#define MCTL_DIV2(n) ((n + 1)/2)
+#define MCTL_DIV32(n) (n/32)
+#define MCTL_DIV1024(n) (n/1024)
+
+ writel((MCTL_DIV2(WR2PRE) << 24) | (MCTL_DIV2(tFAW) << 16) |
+ (MCTL_DIV1024(tRASmax) << 8) | (MCTL_DIV2(tRAS) << 0),
+ &mctl_ctl->dramtmg[0]);
+ writel((MCTL_DIV2(tXP) << 16) | (MCTL_DIV2(tRTP) << 8) |
+ (MCTL_DIV2(tRC) << 0),
+ &mctl_ctl->dramtmg[1]);
+ writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) |
+ (MCTL_DIV2(RD2WR) << 8) | (MCTL_DIV2(WR2RD) << 0),
+ &mctl_ctl->dramtmg[2]);
+ /*
+ * Note: tMRW is located at bit 16 (and up) in DRAMTMG3...
+ * this is only relevant for LPDDR2/LPDDR3
+ */
+ writel((MCTL_DIV2(tMRD) << 12) | (MCTL_DIV2(tMOD) << 0),
+ &mctl_ctl->dramtmg[3]);
+ writel((MCTL_DIV2(tRCD) << 24) | (MCTL_DIV2(tCCD) << 16) |
+ (MCTL_DIV2(tRRD) << 8) | (MCTL_DIV2(tRP) << 0),
+ &mctl_ctl->dramtmg[4]);
+ writel((MCTL_DIV2(tCKSRX) << 24) | (MCTL_DIV2(tCKSRE) << 16) |
+ (MCTL_DIV2(tCKESR) << 8) | (MCTL_DIV2(tCKE) << 0),
+ &mctl_ctl->dramtmg[5]);
+
+ /* These timings are relevant for LPDDR2/LPDDR3 only */
+ /* writel((MCTL_TCKDPDE << 24) | (MCTL_TCKDPX << 16) |
+ (MCTL_TCKCSX << 0), &mctl_ctl->dramtmg[6]); */
+
+ /* printf("DRAMTMG7 reset value: 0x%x\n",
+ readl(&mctl_ctl->dramtmg[7])); */
+ /* DRAMTMG7 reset value: 0x202 */
+ /* DRAMTMG7 should contain t_ckpde and t_ckpdx: check reset values!!! */
+ /* printf("DRAMTMG8 reset value: 0x%x\n",
+ readl(&mctl_ctl->dramtmg[8])); */
+ /* DRAMTMG8 reset value: 0x44 */
+
+ writel((MCTL_DIV32(tXSDLL) << 0), &mctl_ctl->dramtmg[8]);
+
+ writel((MCTL_DIV32(tREFI) << 16) | (MCTL_DIV2(tRFC) << 0),
+ &mctl_ctl->rfshtmg);
+
+ if (para->dram_type == DRAM_TYPE_DDR3) {
+ writel((2 << 24) | ((MCTL_DIV2(CL) - 2) << 16) |
+ (1 << 8) | ((MCTL_DIV2(CWL) - 2) << 0),
+ &mctl_ctl->dfitmg[0]);
+ } else {
+ /* TODO */
+ }
+
+ /* TODO: handle the case of the write latency domain going to 0 ... */
+
+ /*
+ * Disable dfi_init_complete_en (the triggering of the SDRAM
+ * initialisation when the PHY initialisation completes).
+ */
+ clrbits_le32(&mctl_ctl->dfimisc, MCTL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ /* Disable the automatic generation of DLL calibration requests */
+ setbits_le32(&mctl_ctl->dfiupd[0], MCTL_DFIUPD0_DIS_AUTO_CTRLUPD);
+
+ /* A80-Q7: 2T, 1 rank, DDR3, full-32bit-DQ */
+ /* TODO: make 2T and BUSWIDTH configurable */
+ writel(MCTL_MSTR_DEVICETYPE(para->dram_type) |
+ MCTL_MSTR_BURSTLENGTH(para->dram_type) |
+ MCTL_MSTR_ACTIVERANKS(para->rank) |
+ MCTL_MSTR_2TMODE | MCTL_MSTR_BUSWIDTH32,
+ &mctl_ctl->mstr);
+
+ if (para->dram_type == DRAM_TYPE_DDR3) {
+ writel(MCTL_ZQCTRL0_TZQCL(MCTL_DIV2(tZQoper)) |
+ (MCTL_DIV2(tZQCS)), &mctl_ctl->zqctrl[0]);
+ /*
+ * TODO: is the following really necessary as the bottom
+ * half should already be 0x100 and the upper half should
+ * be ignored for a DDR3 device???
+ */
+ writel(MCTL_ZQCTRL1_TZQSI_x1024(0x100),
+ &mctl_ctl->zqctrl[1]);
+ } else {
+ writel(MCTL_ZQCTRL0_TZQCL(0x200) | MCTL_ZQCTRL0_TZQCS(0x40),
+ &mctl_ctl->zqctrl[0]);
+ writel(MCTL_ZQCTRL1_TZQRESET(0x28) |
+ MCTL_ZQCTRL1_TZQSI_x1024(0x100),
+ &mctl_ctl->zqctrl[1]);
+ }
+
+ /* Assert dfi_init_complete signal */
+ setbits_le32(&mctl_ctl->dfimisc, MCTL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ /* Disable auto-refresh */
+ setbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH);
+
+ /* PHY initialisation */
+
+ /* TODO: make 2T and 8-bank mode configurable */
+ writel(MCTL_PHY_DCR_BYTEMASK | MCTL_PHY_DCR_2TMODE |
+ MCTL_PHY_DCR_DDR8BNK | MCTL_PHY_DRAMMODE_DDR3,
+ &mctl_phy->dcr);
+
+ /* For LPDDR2 or LPDDR3, set DQSGX to 0 before training. */
+ if (para->dram_type != DRAM_TYPE_DDR3)
+ clrbits_le32(&mctl_phy->dsgcr, (3 << 6));
+
+ writel(mr[0], &mctl_phy->mr0);
+ writel(mr[1], &mctl_phy->mr1);
+ writel(mr[2], &mctl_phy->mr2);
+ writel(mr[3], &mctl_phy->mr3);
+
+ /*
+ * The DFI PHY is running at full rate. We thus use the actual
+ * timings in clock cycles here.
+ */
+ writel((tRC << 26) | (tRRD << 22) | (tRAS << 16) |
+ (tRCD << 12) | (tRP << 8) | (tWTR << 4) | (tRTP << 0),
+ &mctl_phy->dtpr[0]);
+ writel((tMRD << 0) | ((tMOD - 12) << 2) | (tFAW << 5) |
+ (tRFC << 11) | (tWLMRD << 20) | (tWLO << 26),
+ &mctl_phy->dtpr[1]);
+ writel((tXS << 0) | (MAX(tXP, tXPDLL) << 10) |
+ (tCKE << 15) | (tDLLK << 19) |
+ (MCTL_PHY_TRTODT << 29) | (MCTL_PHY_TRTW << 30) |
+ (((tCCD - 4) & 0x1) << 31),
+ &mctl_phy->dtpr[2]);
+
+ /* tDQSCK and tDQSCKmax are used LPDDR2/LPDDR3 */
+ /* writel((tDQSCK << 0) | (tDQSCKMAX << 3), &mctl_phy->dtpr[3]); */
+
+ /*
+ * We use the same values used by Allwinner's Boot0 for the PTR
+ * (PHY timing register) configuration that is tied to the PHY
+ * implementation.
+ */
+ writel(0x42C21590, &mctl_phy->ptr[0]);
+ writel(0xD05612C0, &mctl_phy->ptr[1]);
+ if (para->dram_type == DRAM_TYPE_DDR3) {
+ const unsigned int tdinit0 = 500 * CONFIG_DRAM_CLK; /* 500us */
+ const unsigned int tdinit1 = (360 * CONFIG_DRAM_CLK + 999) /
+ 1000; /* 360ns */
+ const unsigned int tdinit2 = 200 * CONFIG_DRAM_CLK; /* 200us */
+ const unsigned int tdinit3 = CONFIG_DRAM_CLK; /* 1us */
+
+ writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]);
+ writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]);
+ } else {
+ /* LPDDR2 or LPDDR3 */
+ const unsigned int tdinit0 = (100 * CONFIG_DRAM_CLK + 999) /
+ 1000; /* 100ns */
+ const unsigned int tdinit1 = 200 * CONFIG_DRAM_CLK; /* 200us */
+ const unsigned int tdinit2 = 22 * CONFIG_DRAM_CLK; /* 11us */
+ const unsigned int tdinit3 = 2 * CONFIG_DRAM_CLK; /* 2us */
+
+ writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]);
+ writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]);
+ }
+
+ /* TEST ME */
+ writel(0x00203131, &mctl_phy->acmdlr);
+
+ /* TODO: can we enable this for 2 ranks, even when we don't know yet */
+ writel(MCTL_DTCR_DEFAULT | MCTL_DTCR_RANKEN(para->rank),
+ &mctl_phy->dtcr);
+
+ /* TODO: half width */
+ debug("DX2GCR0 reset: 0x%x\n", readl(&mctl_phy->dx[2].gcr[0]));
+ writel(0x7C000285, &mctl_phy->dx[2].gcr[0]);
+ writel(0x7C000285, &mctl_phy->dx[3].gcr[0]);
+
+ clrsetbits_le32(&mctl_phy->zq[0].pr, 0xff,
+ (CONFIG_DRAM_ZQ >> 0) & 0xff); /* CK/CA */
+ clrsetbits_le32(&mctl_phy->zq[1].pr, 0xff,
+ (CONFIG_DRAM_ZQ >> 8) & 0xff); /* DX0/DX1 */
+ clrsetbits_le32(&mctl_phy->zq[2].pr, 0xff,
+ (CONFIG_DRAM_ZQ >> 16) & 0xff); /* DX2/DX3 */
+
+ /* TODO: make configurable & implement non-ODT path */
+ if (1) {
+ int lane;
+ for (lane = 0; lane < 4; ++lane) {
+ clrbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff);
+ clrbits_le32(&mctl_phy->dx[lane].gcr[3],
+ (0x3<<12) | (0x3<<4));
+ }
+ } else {
+ /* TODO: check */
+ int lane;
+ for (lane = 0; lane < 4; ++lane) {
+ clrsetbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff,
+ 0xaaaa);
+ if (para->dram_type == DRAM_TYPE_DDR3)
+ setbits_le32(&mctl_phy->dx[lane].gcr[3],
+ (0x3<<12) | (0x3<<4));
+ else
+ setbits_le32(&mctl_phy->dx[lane].gcr[3],
+ 0x00000012);
+ }
+ }
+
+ writel(0x04058D02, &mctl_phy->zq[0].cr); /* CK/CA */
+ writel(0x04058D02, &mctl_phy->zq[1].cr); /* DX0/DX1 */
+ writel(0x04058D02, &mctl_phy->zq[2].cr); /* DX2/DX3 */
+
+ /* Disable auto-refresh prior to data training */
+ setbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH);
+
+ setbits_le32(&mctl_phy->dsgcr, 0xf << 24); /* unclear what this is... */
+ /* TODO: IODDRM (IO DDR-MODE) for DDR3L */
+ clrsetbits_le32(&mctl_phy->pgcr[1],
+ MCTL_PGCR1_ZCKSEL_MASK,
+ MCTL_PGCR1_IODDRM_DDR3 | MCTL_PGCR1_INHVT_EN);
+
+ setbits_le32(&mctl_phy->pllcr, 0x3 << 19); /* PLL frequency select */
+ /* TODO: single-channel PLL mode??? missing */
+ setbits_le32(&mctl_phy->pllcr,
+ MCTL_PLLGCR_PLL_BYPASS | MCTL_PLLGCR_PLL_POWERDOWN);
+ /* setbits_le32(&mctl_phy->pir, MCTL_PIR_PLL_BYPASS); included below */
+
+ /* Disable VT compensation */
+ clrbits_le32(&mctl_phy->pgcr[0], 0x3f);
+
+ /* TODO: "other" PLL mode ... 0x20000 seems to be the PLL Bypass */
+ if (para->dram_type == DRAM_TYPE_DDR3)
+ clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x20df3);
+ else
+ clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x2c573);
+
+ sdelay(10000); /* XXX necessary? */
+
+ /* Wait for the INIT bit to clear itself... */
+ while ((readl(&mctl_phy->pir) & MCTL_PIR_INIT) != MCTL_PIR_INIT) {
+ /* not done yet -- keep spinning */
+ debug("MCTL_PIR_INIT not set\n");
+ sdelay(1000);
+ /* TODO: implement timeout */
+ }
+
+ /* TODO: not used --- there's a "2rank debug" section here */
+
+ /* Original dram init code which may come in handy later
+ ********************************************************
+ * LPDDR2 and LPDDR3 *
+ if ((para->dram_type) == 6 || (para->dram_type) == 7) {
+ reg_val = mctl_read_w(P0_DSGCR + ch_offset);
+ reg_val &= (~(0x3<<6)); * set DQSGX to 1 *
+ reg_val |= (0x1<<6); * dqs gate extend *
+ mctl_write_w(P0_DSGCR + ch_offset, reg_val);
+ dram_dbg("DQS Gate Extend Enable!\n", ch_index);
+ }
+
+ * Disable ZCAL after initial--for nand dma debug--20140330 by YSZ *
+ if (para->dram_tpr13 & (0x1<<31)) {
+ reg_val = mctl_read_w(P0_ZQ0CR + ch_offset);
+ reg_val |= (0x7<<11);
+ mctl_write_w(P0_ZQ0CR + ch_offset, reg_val);
+ }
+ ********************************************************
+ */
+
+ /*
+ * TODO: more 2-rank support
+ * (setting the "dqs gate delay to average between 2 rank")
+ */
+
+ /* check if any errors are set */
+ if (readl(&mctl_phy->pgsr[0]) & MCTL_PGSR0_ERRORS) {
+ debug("Channel %d unavailable!\n", ch_index);
+ return 0;
+ } else{
+ /* initial OK */
+ debug("Channel %d OK!\n", ch_index);
+ /* return 1; */
+ }
+
+ while ((readl(&mctl_ctl->stat) & 0x1) != 0x1) {
+ debug("Waiting for INIT to be done (controller to come up into 'normal operating' mode\n");
+ sdelay(100000);
+ /* init not done */
+ /* TODO: implement time-out */
+ }
+ debug("done\n");
+
+ /* "DDR is controller by contoller" */
+ clrbits_le32(&mctl_phy->pgcr[3], (1 << 25));
+
+ /* TODO: is the following necessary? */
+ debug("DFIMISC before writing 0: 0x%x\n", readl(&mctl_ctl->dfimisc));
+ writel(0, &mctl_ctl->dfimisc);
+
+ /* Enable auto-refresh */
+ clrbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH);
+
+ debug("channel_init complete\n");
+ return 1;
+}
+
+signed int DRAMC_get_dram_size(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ unsigned int reg_val;
+ unsigned int dram_size;
+ unsigned int temp;
+
+ reg_val = readl(&mctl_com->cr);
+
+ temp = (reg_val >> 8) & 0xf; /* page size code */
+ dram_size = (temp - 6); /* (1 << dram_size) * 512Bytes */
+
+ temp = (reg_val >> 4) & 0xf; /* row width code */
+ dram_size += (temp + 1); /* (1 << dram_size) * 512Bytes */
+
+ temp = (reg_val >> 2) & 0x3; /* bank number code */
+ dram_size += (temp + 2); /* (1 << dram_size) * 512Bytes */
+
+ temp = reg_val & 0x3; /* rank number code */
+ dram_size += temp; /* (1 << dram_size) * 512Bytes */
+
+ temp = (reg_val >> 19) & 0x1; /* channel number code */
+ dram_size += temp; /* (1 << dram_size) * 512Bytes */
+
+ dram_size = dram_size - 11; /* (1 << dram_size) MBytes */
+
+ return 1 << dram_size;
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ struct dram_sun9i_cl_cwl_timing cl_cwl[] = {
+ { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 },
+ { .CL = 6, .CWL = 5, .tCKmin = 2500, .tCKmax = 3300 },
+ { .CL = 8, .CWL = 6, .tCKmin = 1875, .tCKmax = 2500 },
+ { .CL = 10, .CWL = 7, .tCKmin = 1500, .tCKmax = 1875 },
+ { .CL = 11, .CWL = 8, .tCKmin = 1250, .tCKmax = 1500 }
+ };
+
+ /* Set initial parameters, these get modified by the autodetect code */
+ struct dram_sun9i_para para = {
+ .dram_type = DRAM_TYPE_DDR3,
+ .bus_width = 32,
+ .chan = 2,
+ .rank = 1,
+ /* .rank = 2, */
+ .page_size = 4096,
+ /* .rows = 16, */
+ .rows = 15,
+
+ /* CL/CWL table for the speed bin */
+ .cl_cwl_table = cl_cwl,
+ .cl_cwl_numentries = sizeof(cl_cwl) /
+ sizeof(struct dram_sun9i_cl_cwl_timing),
+
+ /* timings */
+ .tREFI = 7800, /* 7.8us (up to 85 degC) */
+ .tRFC = 260, /* 260ns for 4GBit devices */
+ /* 350ns @ 8GBit */
+
+ .tRCD = 13750,
+ .tRP = 13750,
+ .tRC = 48750,
+ .tRAS = 35000,
+
+ .tDLLK = 512,
+ .tRTP = { .ck = 4, .ps = 7500 },
+ .tWTR = { .ck = 4, .ps = 7500 },
+ .tWR = 15,
+ .tMRD = 4,
+ .tMOD = { .ck = 12, .ps = 15000 },
+ .tCCD = 4,
+ .tRRD = { .ck = 4, .ps = 7500 },
+ .tFAW = 40,
+
+ /* calibration timing */
+ /* .tZQinit = { .ck = 512, .ps = 640000 }, */
+ .tZQoper = { .ck = 256, .ps = 320000 },
+ .tZQCS = { .ck = 64, .ps = 80000 },
+
+ /* reset timing */
+ /* .tXPR = { .ck = 5, .ps = 10000 }, */
+
+ /* self-refresh timings */
+ .tXS = { .ck = 5, .ps = 10000 },
+ .tXSDLL = 512,
+ .tCKSRE = { .ck = 5, .ps = 10000 },
+ .tCKSRX = { .ck = 5, .ps = 10000 },
+
+ /* power-down timings */
+ .tXP = { .ck = 3, .ps = 6000 },
+ .tXPDLL = { .ck = 10, .ps = 24000 },
+ .tCKE = { .ck = 3, .ps = 5000 },
+
+ /* write leveling timings */
+ .tWLMRD = 40,
+ /* .tWLDQSEN = 25, */
+ .tWLO = 7500,
+ /* .tWLOE = 2000, */
+ };
+
+ /*
+ * Disable A80 internal 240 ohm resistor.
+ *
+ * This code sequence is adapated from Allwinner's Boot0 (see
+ * https://github.com/allwinner-zh/bootloader.git), as there
+ * is no documentation for these two registers in the R_PRCM
+ * block.
+ */
+ setbits_le32(SUNXI_PRCM_BASE + 0x1e0, (0x3 << 8));
+ writel(0, SUNXI_PRCM_BASE + 0x1e8);
+
+ mctl_sys_init();
+
+ if (!mctl_channel_init(0, ¶))
+ return 0;
+
+ /* dual-channel */
+ if (!mctl_channel_init(1, ¶)) {
+ /* disable channel 1 */
+ clrsetbits_le32(&mctl_com->cr, MCTL_CR_CHANNEL_MASK,
+ MCTL_CR_CHANNEL_SINGLE);
+ /* disable channel 1 global clock */
+ clrbits_le32(&mctl_com->cr, MCTL_CCR_CH1_CLK_EN);
+ }
+
+ mctl_com_init(¶);
+
+ /* return the proper RAM size */
+ return DRAMC_get_dram_size() << 20;
+}
diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c
new file mode 100644
index 0000000..c20d3c0
--- /dev/null
+++ b/arch/arm/mach-sunxi/gtbus_sun9i.c
@@ -0,0 +1,48 @@
+/*
+ * GTBUS initialisation for sun9i
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gtbus_sun9i.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+
+void gtbus_init(void)
+{
+ struct sunxi_gtbus_reg * const gtbus =
+ (struct sunxi_gtbus_reg *)SUNXI_GTBUS_BASE;
+
+ /*
+ * We use the same setting that Allwinner used in Boot0 for now.
+ * It may be advantageous to adjust these for various workloads
+ * (e.g. headless use cases that focus on IO throughput).
+ */
+ writel((GT_PRIO_HIGH << GT_PORT_FE0) |
+ (GT_PRIO_HIGH << GT_PORT_BE1) |
+ (GT_PRIO_HIGH << GT_PORT_BE2) |
+ (GT_PRIO_HIGH << GT_PORT_IEP0) |
+ (GT_PRIO_HIGH << GT_PORT_FE1) |
+ (GT_PRIO_HIGH << GT_PORT_BE0) |
+ (GT_PRIO_HIGH << GT_PORT_FE2) |
+ (GT_PRIO_HIGH << GT_PORT_IEP1),
+ >bus->mst_read_prio_cfg[0]);
+
+ writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]);
+ writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]);
+ writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE1]);
+ writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE2]);
+ writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP0]);
+ writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE1]);
+ writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE0]);
+ writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE2]);
+ writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP1]);
+}
+
+#endif
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index f9993d2..278587b 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -146,12 +146,13 @@
}
}
-#if defined CONFIG_MACH_SUN8I_H3
+#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
{
+#if defined CONFIG_MACH_SUN8I_H3
if (phy->id == 0)
clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
-
+#endif
clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
}
#elif defined CONFIG_MACH_SUN8I_A83T
@@ -296,13 +297,6 @@
gpio_set_value(phy->gpio_vbus, 0);
}
-int sunxi_usb_phy_power_is_on(int index)
-{
- struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
- return phy->power_on_count > 0;
-}
-
int sunxi_usb_phy_vbus_detect(int index)
{
struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 1eaf406..5bdbc70 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -1,5 +1,17 @@
if TEGRA
+config SPL_GPIO_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
+
config TEGRA_IVC
bool "Tegra IVC protocol"
help
@@ -10,20 +22,28 @@
config TEGRA_COMMON
bool "Tegra common options"
+ select CLK
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
- select DM_PCI
- select DM_PCI_COMPAT
+ select DM_MMC
select DM_PWM
+ select DM_RESET
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select MISC
select OF_CONTROL
select VIDCONSOLE_AS_LCD if DM_VIDEO
+config TEGRA_NO_BPMP
+ bool "Tegra common options for SoCs without BPMP"
+ select TEGRA_CAR
+ select TEGRA_CAR_CLOCK
+ select TEGRA_CAR_RESET
+
config TEGRA_ARMV7_COMMON
bool "Tegra 32-bit common options"
select CPU_V7
@@ -31,6 +51,7 @@
select SUPPORT_SPL
select TEGRA_COMMON
select TEGRA_GPIO
+ select TEGRA_NO_BPMP
config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
@@ -61,13 +82,11 @@
bool "Tegra210 family"
select TEGRA_GPIO
select TEGRA_ARMV8_COMMON
+ select TEGRA_NO_BPMP
config TEGRA186
bool "Tegra186 family"
- select CLK
select DM_MAILBOX
- select DM_RESET
- select MISC
select TEGRA186_BPMP
select TEGRA186_CLOCK
select TEGRA186_GPIO
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c
index 7b1d258..a79a519 100644
--- a/arch/arm/mach-tegra/arm64-mmu.c
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@@ -23,7 +23,7 @@
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
- .size = 0xff80000000UL,
+ .size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
index 1b9799f..691c3fd 100644
--- a/arch/arm/mach-tegra/board186.c
+++ b/arch/arm/mach-tegra/board186.c
@@ -6,8 +6,6 @@
#include <common.h>
#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/mmc.h>
-#include <asm/arch-tegra/tegra_mmc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -26,18 +24,12 @@
return tegra_board_init();
}
+__weak int tegra_soc_board_init_late(void)
+{
+ return 0;
+}
+
int board_late_init(void)
{
- return 0;
-}
-
-void pad_init_mmc(struct mmc_host *host)
-{
-}
-
-int board_mmc_init(bd_t *bd)
-{
- tegra_mmc_init();
-
- return 0;
+ return tegra_soc_board_init_late();
}
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 9158ace..cb9503f 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -32,10 +32,6 @@
#ifdef CONFIG_USB_EHCI_TEGRA
#include <usb.h>
#endif
-#ifdef CONFIG_TEGRA_MMC
-#include <asm/arch-tegra/tegra_mmc.h>
-#include <asm/arch-tegra/mmc.h>
-#endif
#include <asm/arch-tegra/xusb-padctl.h>
#include <power/as3722.h>
#include <i2c.h>
@@ -54,6 +50,7 @@
__weak void pinmux_init(void) {}
__weak void pin_mux_usb(void) {}
__weak void pin_mux_spi(void) {}
+__weak void pin_mux_mmc(void) {}
__weak void gpio_early_init_uart(void) {}
__weak void pin_mux_display(void) {}
__weak void start_cpu_fan(void) {}
@@ -128,6 +125,10 @@
pin_mux_spi();
#endif
+#ifdef CONFIG_TEGRA_MMC
+ pin_mux_mmc();
+#endif
+
/* Init is handled automatically in the driver-model case */
#if defined(CONFIG_DM_VIDEO)
pin_mux_display();
@@ -230,54 +231,6 @@
return 0;
}
-#if defined(CONFIG_TEGRA_MMC)
-__weak void pin_mux_mmc(void)
-{
-}
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
- debug("%s called\n", __func__);
-
- /* Enable muxes, etc. for SDMMC controllers */
- pin_mux_mmc();
-
- debug("%s: init MMC\n", __func__);
- tegra_mmc_init();
-
- return 0;
-}
-
-void pad_init_mmc(struct mmc_host *host)
-{
-#if defined(CONFIG_TEGRA30)
- enum periph_id id = host->mmc_id;
- u32 val;
-
- debug("%s: sdmmc address = %08x, id = %d\n", __func__,
- (unsigned int)host->reg, id);
-
- /* Set the pad drive strength for SDMMC1 or 3 only */
- if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
- debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
- __func__);
- return;
- }
-
- val = readl(&host->reg->sdmemcmppadctl);
- val &= 0xFFFFFFF0;
- val |= MEMCOMP_PADCTRL_VREF;
- writel(val, &host->reg->sdmemcmppadctl);
-
- val = readl(&host->reg->autocalcfg);
- val &= 0xFFFF0000;
- val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
- writel(val, &host->reg->autocalcfg);
-#endif /* T30 */
-}
-#endif /* MMC */
-
/*
* In some SW environments, a memory carve-out exists to house a secure
* monitor, a trusted OS, and/or various statically allocated media buffers.
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 36eabc8..3bb7233 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -206,6 +206,29 @@
return 0;
}
+static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
+{
+ u32 *reg = get_periph_source_reg(periph_id);
+ u32 val = readl(reg);
+
+ switch (mux_bits) {
+ case MASK_BITS_31_30:
+ val >>= OUT_CLK_SOURCE_31_30_SHIFT;
+ val &= OUT_CLK_SOURCE_31_30_MASK;
+ return val;
+ case MASK_BITS_31_29:
+ val >>= OUT_CLK_SOURCE_31_29_SHIFT;
+ val &= OUT_CLK_SOURCE_31_29_MASK;
+ return val;
+ case MASK_BITS_31_28:
+ val >>= OUT_CLK_SOURCE_31_28_SHIFT;
+ val &= OUT_CLK_SOURCE_31_28_MASK;
+ return val;
+ default:
+ return -1;
+ }
+}
+
void clock_ll_set_source(enum periph_id periph_id, unsigned source)
{
clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
@@ -288,9 +311,43 @@
enum clock_id parent)
{
u32 *reg = get_periph_source_reg(periph_id);
+ unsigned parent_rate = pll_rate[parent];
+ int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT;
- return get_rate_from_divider(pll_rate[parent],
- (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
+ switch (periph_id) {
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_UART4:
+ case PERIPH_ID_UART5:
+#ifdef CONFIG_TEGRA20
+ /* There's no divider for these clocks in this SoC. */
+ return parent_rate;
+#else
+ /*
+ * This undoes the +2 in get_rate_from_divider() which I
+ * believe is incorrect. Ideally we would fix
+ * get_rate_from_divider(), but... Removing the +2 from
+ * get_rate_from_divider() would probably require remove the -2
+ * from the tail of clk_get_divider() since I believe that's
+ * only there to invert get_rate_from_divider()'s +2. Observe
+ * how find_best_divider() uses those two functions together.
+ * However, doing so breaks other stuff, such as Seaboard's
+ * display, likely due to clock_set_pllout()'s call to
+ * clk_get_divider(). Attempting to fix that by making
+ * clock_set_pllout() subtract 2 from clk_get_divider()'s
+ * return value doesn't help. In summary this clock driver is
+ * quite broken but I'm afraid I have no idea how to fix it
+ * without completely replacing it.
+ */
+ div -= 2;
+ break;
+#endif
+ default:
+ break;
+ }
+
+ return get_rate_from_divider(parent_rate, div);
}
/**
@@ -363,6 +420,20 @@
return 0;
}
+enum clock_id clock_get_periph_parent(enum periph_id periph_id)
+{
+ int err, mux_bits, divider_bits, type;
+ int source;
+
+ err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type);
+ if (err)
+ return CLOCK_ID_NONE;
+
+ source = clock_ll_get_source_bits(periph_id, mux_bits);
+
+ return get_periph_clock_id(periph_id, source);
+}
+
unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
enum clock_id parent, unsigned rate, int *extra_div)
{
@@ -612,6 +683,8 @@
void clock_init(void)
{
+ int i;
+
pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
@@ -630,6 +703,19 @@
debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
+
+ for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
+ enum periph_id periph_id;
+ enum clock_id parent;
+ int source, mux_bits, divider_bits;
+
+ periph_id = periph_clk_init_table[i].periph_id;
+ parent = periph_clk_init_table[i].parent_clock_id;
+
+ source = get_periph_clock_source(periph_id, parent, &mux_bits,
+ ÷r_bits);
+ clock_ll_set_source_bits(periph_id, mux_bits, source);
+ }
}
static void set_avp_clock_source(u32 src)
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index e6ef873..177ab6b 100644
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -496,6 +496,51 @@
return &clkrst->crc_clk_src[internal_id];
}
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+ int *divider_bits, int *type)
+{
+ enum periphc_internal_id internal_id;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return -1;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return -1;
+
+ *type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(*type))
+ return -1;
+
+ *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
+
+ if (*type == CLOCK_TYPE_PCMT16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ return 0;
+}
+
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
+{
+ enum periphc_internal_id internal_id;
+ int type;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return CLOCK_ID_NONE;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return CLOCK_ID_NONE;
+
+ type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(type))
+ return CLOCK_ID_NONE;
+
+ return clock_source[type][source];
+}
+
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
@@ -512,23 +557,10 @@
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
+ int mux, err;
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = periph_id_to_internal_id[periph_id];
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- *mux_bits = clock_source[type][CLOCK_MAX_MUX];
-
- if (type == CLOCK_TYPE_PCMT16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
+ err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
+ assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
@@ -699,3 +731,26 @@
writel(val, &sysctr->cntcr);
debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
}
+
+struct periph_clk_init periph_clk_init_table[] = {
+ { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
+ { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
+ { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
+ { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+ { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
+ { -1, },
+};
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 1e71146..5e44061 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -642,6 +642,51 @@
}
}
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+ int *divider_bits, int *type)
+{
+ enum periphc_internal_id internal_id;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return -1;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return -1;
+
+ *type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(*type))
+ return -1;
+
+ *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
+
+ if (*type == CLOCK_TYPE_PC2CC3M_T16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ return 0;
+}
+
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
+{
+ enum periphc_internal_id internal_id;
+ int type;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return CLOCK_ID_NONE;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return CLOCK_ID_NONE;
+
+ type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(type))
+ return CLOCK_ID_NONE;
+
+ return clock_source[type][source];
+}
+
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
@@ -658,23 +703,10 @@
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
+ int mux, err;
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = periph_id_to_internal_id[periph_id];
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- *mux_bits = clock_source[type][CLOCK_MAX_MUX];
-
- if (type == CLOCK_TYPE_PC2CC3M_T16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
+ err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
+ assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
@@ -1107,3 +1139,26 @@
return NULL;
}
+
+struct periph_clk_init periph_clk_init_table[] = {
+ { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
+ { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
+ { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
+ { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+ { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
+ { -1, },
+};
diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile
index 033d600..56f3378 100644
--- a/arch/arm/mach-tegra/tegra186/Makefile
+++ b/arch/arm/mach-tegra/tegra186/Makefile
@@ -3,5 +3,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += ../board186.o
+obj-y += cache.o
+obj-y += nvtboot_board.o
obj-y += nvtboot_ll.o
obj-y += nvtboot_mem.o
diff --git a/arch/arm/mach-tegra/tegra186/cache.S b/arch/arm/mach-tegra/tegra186/cache.S
new file mode 100644
index 0000000..3061dc2
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/cache.S
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#define SMC_SIP_INVOKE_MCE 0x82FFFF00
+#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11)
+#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14)
+#define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15)
+
+ENTRY(__asm_tegra_cache_smc)
+ mov x1, #0
+ mov x2, #0
+ mov x3, #0
+ mov x4, #0
+ mov x5, #0
+ mov x6, #0
+ smc #0
+ mov x0, #0
+ ret
+ENDPROC(__asm_invalidate_l3_dcache)
+
+ENTRY(__asm_invalidate_l3_dcache)
+ mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff)
+ movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16
+ b __asm_tegra_cache_smc
+ENDPROC(__asm_invalidate_l3_dcache)
+
+ENTRY(__asm_flush_l3_dcache)
+ mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff)
+ movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16
+ b __asm_tegra_cache_smc
+ENDPROC(__asm_flush_l3_dcache)
+
+ENTRY(__asm_invalidate_l3_icache)
+ mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
+ movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
+ b __asm_tegra_cache_smc
+ENDPROC(__asm_invalidate_l3_icache)
diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_board.c b/arch/arm/mach-tegra/tegra186/nvtboot_board.c
new file mode 100644
index 0000000..feb935f
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/nvtboot_board.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <asm/arch/tegra.h>
+
+extern unsigned long nvtboot_boot_x0;
+
+static int set_fdt_addr(void)
+{
+ int ret;
+
+ ret = setenv_hex("fdt_addr", nvtboot_boot_x0);
+ if (ret) {
+ printf("Failed to set fdt_addr to point at DTB: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's
+ * ethaddr environment variable if possible.
+ */
+static int set_ethaddr_from_nvtboot(void)
+{
+ const void *nvtboot_blob = (void *)nvtboot_boot_x0;
+ int ret, node, len;
+ const u32 *prop;
+
+ /* Already a valid address in the environment? If so, keep it */
+ if (getenv("ethaddr"))
+ return 0;
+
+ node = fdt_path_offset(nvtboot_blob, "/chosen");
+ if (node < 0) {
+ printf("Can't find /chosen node in nvtboot DTB\n");
+ return node;
+ }
+ prop = fdt_getprop(nvtboot_blob, node, "nvidia,ether-mac", &len);
+ if (!prop) {
+ printf("Can't find nvidia,ether-mac property in nvtboot DTB\n");
+ return -ENOENT;
+ }
+
+ ret = setenv("ethaddr", (void *)prop);
+ if (ret) {
+ printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int tegra_soc_board_init_late(void)
+{
+ /*
+ * Ignore errors here; the value may not be used depending on
+ * extlinux.conf or boot script content.
+ */
+ set_fdt_addr();
+ /* Ignore errors here; not all cases care about Ethernet addresses */
+ set_ethaddr_from_nvtboot();
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S
index 1eab890..899c9cc 100644
--- a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S
+++ b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S
@@ -9,6 +9,7 @@
#include <config.h>
#include <linux/linkage.h>
+.align 8
.globl nvtboot_boot_x0
nvtboot_boot_x0:
.dword 0
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index cd9fb9a..ec04cf5 100644
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -413,6 +413,57 @@
return &clkrst->crc_clk_src[internal_id];
}
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+ int *divider_bits, int *type)
+{
+ enum periphc_internal_id internal_id;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return -1;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return -1;
+
+ *type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(*type))
+ return -1;
+
+ /*
+ * Special cases here for the clock with a 4-bit source mux and I2C
+ * with its 16-bit divisor
+ */
+ if (*type == CLOCK_TYPE_PCXTS)
+ *mux_bits = MASK_BITS_31_28;
+ else
+ *mux_bits = MASK_BITS_31_30;
+ if (*type == CLOCK_TYPE_PCMT16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ return 0;
+}
+
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
+{
+ enum periphc_internal_id internal_id;
+ int type;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return CLOCK_ID_NONE;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return CLOCK_ID_NONE;
+
+ type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(type))
+ return CLOCK_ID_NONE;
+
+ return clock_source[type][source];
+}
+
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
@@ -429,29 +480,10 @@
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
+ int mux, err;
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = periph_id_to_internal_id[periph_id];
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- /*
- * Special cases here for the clock with a 4-bit source mux and I2C
- * with its 16-bit divisor
- */
- if (type == CLOCK_TYPE_PCXTS)
- *mux_bits = MASK_BITS_31_28;
- else
- *mux_bits = MASK_BITS_31_30;
- if (type == CLOCK_TYPE_PCMT16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
+ err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
+ assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
@@ -717,3 +749,24 @@
return 0;
}
+
+struct periph_clk_init periph_clk_init_table[] = {
+ { PERIPH_ID_SPI1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
+ { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
+ { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+ { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
+ { -1, },
+};
diff --git a/arch/arm/mach-tegra/tegra20/crypto.c b/arch/arm/mach-tegra/tegra20/crypto.c
index ec95d7c..1b82fbb 100644
--- a/arch/arm/mach-tegra/tegra20/crypto.c
+++ b/arch/arm/mach-tegra/tegra20/crypto.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "crypto.h"
#include "aes.h"
diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c
index 5fdc4bb..6aef6d3 100644
--- a/arch/arm/mach-tegra/tegra20/warmboot.c
+++ b/arch/arm/mach-tegra/tegra20/warmboot.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
#include <asm/arch/gp_padctrl.h>
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index f0052e7..c8bb946 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -732,6 +732,51 @@
return &clkrst->crc_clk_src_y[internal_id];
}
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+ int *divider_bits, int *type)
+{
+ enum periphc_internal_id internal_id;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return -1;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return -1;
+
+ *type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(*type))
+ return -1;
+
+ *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
+
+ if (*type == CLOCK_TYPE_PC2CC3M_T16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ return 0;
+}
+
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
+{
+ enum periphc_internal_id internal_id;
+ int type;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return CLOCK_ID_NONE;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return CLOCK_ID_NONE;
+
+ type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(type))
+ return CLOCK_ID_NONE;
+
+ return clock_source[type][source];
+}
+
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
@@ -748,23 +793,10 @@
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
+ int mux, err;
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- *mux_bits = clock_source[type][CLOCK_MAX_MUX];
-
- if (type == CLOCK_TYPE_PC2CC3M_T16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
+ err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
+ assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
@@ -1225,3 +1257,26 @@
return 0;
}
+
+struct periph_clk_init periph_clk_init_table[] = {
+ { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
+ { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
+ { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
+ { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+ { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
+ { -1, },
+};
diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index 1f104f2..4fd8b8a 100644
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -476,6 +476,51 @@
return &clkrst->crc_clk_src[internal_id];
}
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+ int *divider_bits, int *type)
+{
+ enum periphc_internal_id internal_id;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return -1;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return -1;
+
+ *type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(*type))
+ return -1;
+
+ *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
+
+ if (*type == CLOCK_TYPE_PCMT16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ return 0;
+}
+
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
+{
+ enum periphc_internal_id internal_id;
+ int type;
+
+ if (!clock_periph_id_isvalid(periph_id))
+ return CLOCK_ID_NONE;
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ if (!periphc_internal_id_isvalid(internal_id))
+ return CLOCK_ID_NONE;
+
+ type = clock_periph_type[internal_id];
+ if (!clock_type_id_isvalid(type))
+ return CLOCK_ID_NONE;
+
+ return clock_source[type][source];
+}
+
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
@@ -492,23 +537,10 @@
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
+ int mux, err;
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = periph_id_to_internal_id[periph_id];
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- *mux_bits = clock_source[type][CLOCK_MAX_MUX];
-
- if (type == CLOCK_TYPE_PCMT16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
+ err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
+ assert(!err);
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
@@ -763,3 +795,26 @@
return 0;
}
+
+struct periph_clk_init periph_clk_init_table[] = {
+ { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
+ { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
+ { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
+ { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
+ { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+ { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
+ { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
+ { -1, },
+};
diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c
index 18ad7bf..43f5bb7 100644
--- a/arch/arm/mach-tegra/xusb-padctl-common.c
+++ b/arch/arm/mach-tegra/xusb-padctl-common.c
@@ -78,11 +78,11 @@
const void *fdt, int node)
{
unsigned int i;
- int len, err;
+ int len;
group->name = fdt_get_name(fdt, node, &len);
- len = fdt_count_strings(fdt, node, "nvidia,lanes");
+ len = fdt_stringlist_count(fdt, node, "nvidia,lanes");
if (len < 0) {
error("failed to parse \"nvidia,lanes\" property");
return -EINVAL;
@@ -91,9 +91,9 @@
group->num_pins = len;
for (i = 0; i < group->num_pins; i++) {
- err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
- &group->pins[i]);
- if (err < 0) {
+ group->pins[i] = fdt_stringlist_get(fdt, node, "nvidia,lanes",
+ i, NULL);
+ if (!group->pins[i]) {
error("failed to read string from \"nvidia,lanes\" property");
return -EINVAL;
}
@@ -101,8 +101,8 @@
group->num_pins = len;
- err = fdt_get_string(fdt, node, "nvidia,function", &group->func);
- if (err < 0) {
+ group->func = fdt_stringlist_get(fdt, node, "nvidia,function", 0, NULL);
+ if (!group->func) {
error("failed to parse \"nvidia,func\" property");
return -EINVAL;
}
@@ -223,7 +223,7 @@
config->name = fdt_get_name(fdt, node, NULL);
- fdt_for_each_subnode(fdt, subnode, node) {
+ fdt_for_each_subnode(subnode, fdt, node) {
struct tegra_xusb_padctl_group *group;
int err;
@@ -253,7 +253,7 @@
return err;
}
- fdt_for_each_subnode(fdt, subnode, node) {
+ fdt_for_each_subnode(subnode, fdt, node) {
struct tegra_xusb_padctl_config *config = &padctl->config;
err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 7bee6c7..aa3909a 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -99,7 +99,8 @@
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
- depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || ARCH_UNIPHIER_SLD8
+ depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || \
+ ARCH_UNIPHIER_SLD8 || ARCH_UNIPHIER_LD11
default y
help
The command "ddrphy" shows the resulting parameters of DDR PHY
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 774ea99..ae78548 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -4,28 +4,25 @@
ifdef CONFIG_SPL_BUILD
-obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/
+obj-y += init/ bcu/ memconf/
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
-obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
obj-y += dram_init.o
-obj-y += board_common.o
-obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
+obj-y += board_init.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-y += reset.o
-obj-y += pinctrl/ clk/
-
endif
obj-y += boards.o
obj-y += soc_info.o
obj-y += boot-mode/
+obj-y += clk/
obj-y += dram/
+obj-y += pinctrl-glue.o
obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c
deleted file mode 100644
index 330d690..0000000
--- a/arch/arm/mach-uniphier/board_common.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include "micro-support-card.h"
-
-void uniphier_smp_kick_all_cpus(void);
-
-int board_init(void)
-{
- led_puts("Uboo");
-#ifdef CONFIG_ARM64
- uniphier_smp_kick_all_cpus();
-#endif
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
deleted file mode 100644
index d35d38d..0000000
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <libfdt.h>
-#include <linux/io.h>
-
-#include "init.h"
-#include "micro-support-card.h"
-#include "soc-info.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void uniphier_setup_xirq(void)
-{
- const void *fdt = gd->fdt_blob;
- int soc_node, aidet_node;
- const u32 *val;
- unsigned long aidet_base;
- u32 tmp;
-
- soc_node = fdt_path_offset(fdt, "/soc");
- if (soc_node < 0)
- return;
-
- aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
- if (aidet_node < 0)
- return;
-
- val = fdt_getprop(fdt, aidet_node, "reg", NULL);
- if (!val)
- return;
-
- aidet_base = fdt32_to_cpu(*val);
-
- tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */
- tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */
- writel(tmp, aidet_base + 8);
-
- tmp = readl(0x55000090); /* IRQCTL */
- tmp |= 0x000000ff;
- writel(tmp, 0x55000090);
-}
-
-int board_early_init_f(void)
-{
- led_puts("U0");
-
- switch (uniphier_get_soc_type()) {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- case SOC_UNIPHIER_SLD3:
- uniphier_sld3_pin_init();
- led_puts("U1");
- uniphier_ld4_clk_init();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD4)
- case SOC_UNIPHIER_LD4:
- uniphier_ld4_pin_init();
- led_puts("U1");
- uniphier_ld4_clk_init();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
- case SOC_UNIPHIER_PRO4:
- uniphier_pro4_pin_init();
- led_puts("U1");
- uniphier_pro4_clk_init();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
- case SOC_UNIPHIER_SLD8:
- uniphier_sld8_pin_init();
- led_puts("U1");
- uniphier_ld4_clk_init();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
- case SOC_UNIPHIER_PRO5:
- uniphier_pro5_pin_init();
- led_puts("U1");
- uniphier_pro5_clk_init();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
- case SOC_UNIPHIER_PXS2:
- uniphier_pxs2_pin_init();
- led_puts("U1");
- uniphier_pxs2_clk_init();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
- case SOC_UNIPHIER_LD6B:
- uniphier_ld6b_pin_init();
- led_puts("U1");
- uniphier_pxs2_clk_init();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- case SOC_UNIPHIER_LD11:
- uniphier_ld20_pin_init();
- led_puts("U1");
- uniphier_ld11_clk_init();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- case SOC_UNIPHIER_LD20:
- uniphier_ld20_pin_init();
- led_puts("U1");
- uniphier_ld20_clk_init();
- cci500_init(2);
- break;
-#endif
- default:
- break;
- }
-
- uniphier_setup_xirq();
-
- led_puts("U2");
-
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/board_early_init_r.c b/arch/arm/mach-uniphier/board_early_init_r.c
deleted file mode 100644
index b26da36..0000000
--- a/arch/arm/mach-uniphier/board_early_init_r.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include "micro-support-card.h"
-
-int board_early_init_r(void)
-{
- support_card_late_init();
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c
new file mode 100644
index 0000000..8c7864c
--- /dev/null
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <linux/io.h>
+
+#include "init.h"
+#include "micro-support-card.h"
+#include "sg-regs.h"
+#include "soc-info.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void uniphier_setup_xirq(void)
+{
+ const void *fdt = gd->fdt_blob;
+ int soc_node, aidet_node;
+ const u32 *val;
+ unsigned long aidet_base;
+ u32 tmp;
+
+ soc_node = fdt_path_offset(fdt, "/soc");
+ if (soc_node < 0)
+ return;
+
+ aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
+ if (aidet_node < 0)
+ return;
+
+ val = fdt_getprop(fdt, aidet_node, "reg", NULL);
+ if (!val)
+ return;
+
+ aidet_base = fdt32_to_cpu(*val);
+
+ tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */
+ tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */
+ writel(tmp, aidet_base + 8);
+
+ tmp = readl(0x55000090); /* IRQCTL */
+ tmp |= 0x000000ff;
+ writel(tmp, 0x55000090);
+}
+
+static void uniphier_nand_pin_init(bool cs2)
+{
+#ifdef CONFIG_NAND_DENALI
+ if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp"))
+ pr_err("failed to init NAND pins\n");
+#endif
+}
+
+int board_init(void)
+{
+ const struct uniphier_board_data *bd;
+
+ led_puts("U0");
+
+ bd = uniphier_get_board_param();
+ if (!bd)
+ return -ENODEV;
+
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ case SOC_UNIPHIER_SLD3:
+ uniphier_nand_pin_init(true);
+ led_puts("U1");
+ uniphier_sld3_pll_init();
+ uniphier_ld4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+ case SOC_UNIPHIER_LD4:
+ uniphier_nand_pin_init(true);
+ led_puts("U1");
+ uniphier_ld4_pll_init();
+ uniphier_ld4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+ case SOC_UNIPHIER_PRO4:
+ uniphier_nand_pin_init(false);
+ led_puts("U1");
+ uniphier_pro4_pll_init();
+ uniphier_pro4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ case SOC_UNIPHIER_SLD8:
+ uniphier_nand_pin_init(true);
+ led_puts("U1");
+ uniphier_ld4_pll_init();
+ uniphier_ld4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ case SOC_UNIPHIER_PRO5:
+ uniphier_nand_pin_init(true);
+ led_puts("U1");
+ uniphier_pro5_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+ case SOC_UNIPHIER_PXS2:
+ uniphier_nand_pin_init(true);
+ led_puts("U1");
+ uniphier_pxs2_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ case SOC_UNIPHIER_LD6B:
+ uniphier_nand_pin_init(true);
+ led_puts("U1");
+ uniphier_pxs2_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ case SOC_UNIPHIER_LD11:
+ uniphier_nand_pin_init(false);
+ sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
+ sg_set_iectrl(149);
+ sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
+ sg_set_iectrl(153);
+ led_puts("U1");
+ uniphier_ld11_pll_init();
+ uniphier_ld11_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+ case SOC_UNIPHIER_LD20:
+ /* ES1 errata: increase VDD09 supply to suppress VBO noise */
+ if (uniphier_get_soc_revision() == 1) {
+ writel(0x00000003, 0x6184e004);
+ writel(0x00000100, 0x6184e040);
+ writel(0x0000b500, 0x6184e024);
+ writel(0x00000001, 0x6184e000);
+ }
+ uniphier_nand_pin_init(false);
+ sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
+ sg_set_iectrl(149);
+ sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
+ sg_set_iectrl(153);
+ led_puts("U1");
+ uniphier_ld20_pll_init(bd);
+ uniphier_ld20_clk_init();
+ cci500_init(2);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ uniphier_setup_xirq();
+
+ led_puts("U2");
+
+ support_card_late_init();
+
+ led_puts("U3");
+
+#ifdef CONFIG_ARM64
+ uniphier_smp_kick_all_cpus();
+#endif
+
+ led_puts("Uboo");
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index a454126..ece761f 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -28,33 +30,27 @@
#endif
}
-#define VENDOR_PREFIX "socionext,"
-#define DTB_FILE_PREFIX "uniphier-"
-
static int uniphier_set_fdt_file(void)
{
DECLARE_GLOBAL_DATA_PTR;
const char *compat;
char dtb_name[256];
- int buf_len = 256;
- int ret;
+ int buf_len = sizeof(dtb_name);
if (getenv("fdt_file"))
return 0; /* do nothing if it is already set */
- ret = fdt_get_string(gd->fdt_blob, 0, "compatible", &compat);
- if (ret)
+ compat = fdt_stringlist_get(gd->fdt_blob, 0, "compatible", 0, NULL);
+ if (!compat)
return -EINVAL;
- if (strncmp(compat, VENDOR_PREFIX, strlen(VENDOR_PREFIX)))
+ /* rip off the vendor prefix "socionext," */
+ compat = strchr(compat, ',');
+ if (!compat)
return -EINVAL;
+ compat++;
- compat += strlen(VENDOR_PREFIX);
-
- strncat(dtb_name, DTB_FILE_PREFIX, buf_len);
- buf_len -= strlen(DTB_FILE_PREFIX);
-
- strncat(dtb_name, compat, buf_len);
+ strncpy(dtb_name, compat, buf_len);
buf_len -= strlen(compat);
strncat(dtb_name, ".dtb", buf_len);
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 20093d8..0596451 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -184,6 +184,27 @@
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+static const struct uniphier_board_data uniphier_ld20_ref_data = {
+ .dram_freq = 1866,
+ .dram_nr_ch = 3,
+ .dram_ch[0] = {
+ .base = 0x80000000,
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .dram_ch[1] = {
+ .base = 0xc0000000,
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .dram_ch[2] = {
+ .base = 0x100000000UL,
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .flags = UNIPHIER_BD_BOARD_LD20_REF,
+};
+
static const struct uniphier_board_data uniphier_ld20_data = {
.dram_freq = 1866,
.dram_nr_ch = 3,
@@ -202,6 +223,7 @@
.size = 0x40000000,
.width = 32,
},
+ .flags = UNIPHIER_BD_BOARD_LD20_GLOBAL,
};
static const struct uniphier_board_data uniphier_ld21_data = {
@@ -209,7 +231,7 @@
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
- .size = 0x40000000,
+ .size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
@@ -217,7 +239,7 @@
.size = 0x40000000,
.width = 32,
},
- .flags = UNIPHIER_BD_PACKAGE_LD21,
+ .flags = UNIPHIER_BD_BOARD_LD21_GLOBAL,
};
#endif
@@ -228,34 +250,35 @@
static const struct uniphier_board_id uniphier_boards[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- { "socionext,ph1-sld3", &uniphier_sld3_data, },
+ { "socionext,uniphier-sld3", &uniphier_sld3_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
- { "socionext,ph1-ld4", &uniphier_ld4_data, },
+ { "socionext,uniphier-ld4", &uniphier_ld4_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
- { "socionext,ph1-pro4-ace", &uniphier_pro4_2g_data, },
- { "socionext,ph1-pro4-sanji", &uniphier_pro4_2g_data, },
- { "socionext,ph1-pro4", &uniphier_pro4_data, },
+ { "socionext,uniphier-pro4-ace", &uniphier_pro4_2g_data, },
+ { "socionext,uniphier-pro4-sanji", &uniphier_pro4_2g_data, },
+ { "socionext,uniphier-pro4", &uniphier_pro4_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
- { "socionext,ph1-sld8", &uniphier_sld8_data, },
+ { "socionext,uniphier-sld8", &uniphier_sld8_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
- { "socionext,ph1-pro5", &uniphier_pro5_data, },
+ { "socionext,uniphier-pro5", &uniphier_pro5_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
- { "socionext,proxstream2", &uniphier_pxs2_data, },
+ { "socionext,uniphier-pxs2", &uniphier_pxs2_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
- { "socionext,ph1-ld6b", &uniphier_ld6b_data, },
+ { "socionext,uniphier-ld6b", &uniphier_ld6b_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- { "socionext,ph1-ld11", &uniphier_ld11_data, },
+ { "socionext,uniphier-ld11", &uniphier_ld11_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- { "socionext,ph1-ld21", &uniphier_ld21_data, },
- { "socionext,ph1-ld20", &uniphier_ld20_data, },
+ { "socionext,uniphier-ld21", &uniphier_ld21_data, },
+ { "socionext,uniphier-ld20-ref", &uniphier_ld20_ref_data, },
+ { "socionext,uniphier-ld20", &uniphier_ld20_data, },
#endif
};
diff --git a/arch/arm/mach-uniphier/boot-mode/spl_board.c b/arch/arm/mach-uniphier/boot-mode/spl_board.c
index 86292b6..a6b6686 100644
--- a/arch/arm/mach-uniphier/boot-mode/spl_board.c
+++ b/arch/arm/mach-uniphier/boot-mode/spl_board.c
@@ -12,11 +12,6 @@
#include "../soc-info.h"
-void spl_board_announce_boot_device(void)
-{
- printf("eMMC");
-}
-
struct uniphier_romfunc_table {
void *mmc_send_cmd;
void *mmc_card_blockaddr;
@@ -65,7 +60,8 @@
return 0;
}
-int spl_board_load_image(void)
+static int spl_board_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
int (*send_cmd)(u32 cmd, u32 arg);
int (*card_blockaddr)(u32 rca);
@@ -113,12 +109,12 @@
return ret;
}
- ret = spl_parse_image_header((void *)CONFIG_SYS_TEXT_BASE);
+ ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE);
if (ret)
return ret;
- ret = (*load_image)(dev_addr, spl_image.load_addr,
- spl_image.size / 512);
+ ret = (*load_image)(dev_addr, spl_image->load_addr,
+ spl_image->size / 512);
if (ret) {
printf("failed to load image\n");
return ret;
@@ -126,3 +122,4 @@
return 0;
}
+SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 1428e0c..95f433e 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -2,12 +2,31 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o
+ifdef CONFIG_SPL_BUILD
+
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o dpll-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o dpll-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o dpll-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o dpll-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o dpll-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o dpll-ld20.o
+
+else
+
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
+
+endif
+
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
index 92a0733..58069cb 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld11.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -5,17 +5,20 @@
*/
#include <common.h>
+#include <spl.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include "../boot-mode/boot-device.h"
#include "../init.h"
+#include "../sc64-regs.h"
#include "../sg-regs.h"
void uniphier_ld11_clk_init(void)
{
- if (readl(SG_PINMON0) & BIT(27)) {
- /* if booted without stand-by MPU */
-
+ /* if booted from a device other than USB, without stand-by MPU */
+ if ((readl(SG_PINMON0) & BIT(27)) &&
+ spl_boot_device_raw() != BOOT_DEVICE_USB) {
writel(1, SG_ETPHYPSHUT);
writel(1, SG_ETPHYCNT);
@@ -25,4 +28,14 @@
writel(3, SG_ETPHYPSHUT);
writel(7, SG_ETPHYCNT);
}
+
+#ifdef CONFIG_USB_EHCI
+ {
+ /* FIXME: the current clk driver can not handle parents */
+ u32 tmp;
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
+ writel(tmp, SC_CLKCTRL4);
+ }
+#endif
}
diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c
index 8744d26..62b6927 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld4.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -18,9 +20,6 @@
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c
index 8746d7d..92b7338 100644
--- a/arch/arm/mach-uniphier/clk/clk-pro4.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro4.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -22,9 +24,6 @@
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld11.c b/arch/arm/mach-uniphier/clk/dpll-ld11.c
new file mode 100644
index 0000000..7f0677c
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-ld11.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd)
+{
+ uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld20.c b/arch/arm/mach-uniphier/clk/dpll-ld20.c
new file mode 100644
index 0000000..86e99c4
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-ld20.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
+{
+ uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c
new file mode 100644
index 0000000..a40b30d
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+#undef DPLL_SSC_RATE_1PER
+
+int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
+{
+ unsigned int dram_freq = bd->dram_freq;
+ u32 tmp;
+
+ /*
+ * Set Frequency
+ * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+ * to FOUT (DPLLCTRL.bit[29:20])
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~0x000f0000;
+ switch (dram_freq) {
+ case 1333:
+ tmp |= 0x000d0000;
+ break;
+ case 1600:
+ tmp |= 0x000c0000;
+ break;
+ default:
+ pr_err("Unsupported frequency");
+ return -EINVAL;
+ }
+
+#if defined(DPLL_SSC_RATE_1PER)
+ tmp &= ~SC_DPLLCTRL_SSC_RATE;
+#else
+ tmp |= SC_DPLLCTRL_SSC_RATE;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ tmp = readl(SC_DPLLCTRL2);
+ tmp |= SC_DPLLCTRL2_NRSTDS;
+ writel(tmp, SC_DPLLCTRL2);
+
+ /* Wait 500 usec until dpll gets stable */
+ udelay(500);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/dpll-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c
new file mode 100644
index 0000000..3ac48d6
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-pro4.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+#undef DPLL_SSC_RATE_1PER
+
+int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
+{
+ unsigned int dram_freq = bd->dram_freq;
+ u32 tmp;
+
+ /*
+ * Set Frequency
+ * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+ * to FOUT ( DPLLCTRL.bit[29:20] )
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~(0x000f0000);
+ switch (dram_freq) {
+ case 1333:
+ tmp |= 0x000d0000;
+ break;
+ case 1600:
+ tmp |= 0x000c0000;
+ break;
+ default:
+ pr_err("Unsupported frequency");
+ return -EINVAL;
+ }
+
+ /*
+ * Set Moduration rate
+ * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
+ */
+#if defined(DPLL_SSC_RATE_1PER)
+ tmp &= ~0x00008000;
+#else
+ tmp |= 0x00008000;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ tmp = readl(SC_DPLLCTRL2);
+ tmp |= SC_DPLLCTRL2_NRSTDS;
+ writel(tmp, SC_DPLLCTRL2);
+
+ /* Wait until dpll gets stable */
+ udelay(500);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/dpll-sld3.c b/arch/arm/mach-uniphier/clk/dpll-sld3.c
new file mode 100644
index 0000000..0eb310c
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-sld3.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+
+int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd)
+{
+ /* add pll init code here */
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/dpll-sld8.c b/arch/arm/mach-uniphier/clk/dpll-sld8.c
new file mode 100644
index 0000000..7faa5e8
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-sld8.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL3
+ * [23] DIVN_TEST 0x1
+ * [22:16] DIVN 0x50
+ * [10] FREFSEL_TEST 0x1
+ * [9:8] FREFSEL 0x2
+ * [4] ICPD_TEST 0x1
+ * [3:0] ICPD 0xb
+ */
+ tmp = readl(SC_DPLLCTRL3);
+ tmp &= ~0x00ff0717;
+ tmp |= 0x00d0061b;
+ writel(tmp, SC_DPLLCTRL3);
+
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL
+ * <-1%> <-2%>
+ * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
+ * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~0x3ff07fff;
+#ifdef DPLL_SSC_RATE_1PER
+ tmp |= 0x084018bf;
+#else
+ tmp |= 0x084031a6;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL2
+ * [31:29] SSC_STEP 0
+ * [27] SSC_REG_REF 1
+ * [26:20] SSC_M 79 (0x4f)
+ * [19:0] SSC_K 964689 (0xeb851)
+ */
+ tmp = readl(SC_DPLLCTRL2);
+ tmp &= ~0xefffffff;
+ tmp |= 0x0cfeb851;
+ writel(tmp, SC_DPLLCTRL2);
+
+ /* Wait 500 usec until dpll gets stable */
+ udelay(500);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/dpll-tail.c b/arch/arm/mach-uniphier/clk/dpll-tail.c
new file mode 100644
index 0000000..2b88490
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-tail.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../sc-regs.h"
+#include "pll.h"
+
+void uniphier_ld4_dpll_ssc_en(void)
+{
+ u32 tmp;
+
+ tmp = readl(SC_DPLLCTRL);
+ tmp |= SC_DPLLCTRL_SSC_EN;
+ writel(tmp, SC_DPLLCTRL);
+}
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c b/arch/arm/mach-uniphier/clk/early-clk-ld11.c
similarity index 100%
rename from arch/arm/mach-uniphier/early-clk/early-clk-ld11.c
rename to arch/arm/mach-uniphier/clk/early-clk-ld11.c
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/clk/early-clk-ld20.c
similarity index 100%
rename from arch/arm/mach-uniphier/early-clk/early-clk-ld20.c
rename to arch/arm/mach-uniphier/clk/early-clk-ld20.c
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld4.c b/arch/arm/mach-uniphier/clk/early-clk-ld4.c
similarity index 100%
rename from arch/arm/mach-uniphier/early-clk/early-clk-ld4.c
rename to arch/arm/mach-uniphier/clk/early-clk-ld4.c
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-pro5.c b/arch/arm/mach-uniphier/clk/early-clk-pro5.c
similarity index 100%
rename from arch/arm/mach-uniphier/early-clk/early-clk-pro5.c
rename to arch/arm/mach-uniphier/clk/early-clk-pro5.c
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c b/arch/arm/mach-uniphier/clk/early-clk-pxs2.c
similarity index 100%
rename from arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c
rename to arch/arm/mach-uniphier/clk/early-clk-pxs2.c
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
new file mode 100644
index 0000000..caa631d
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
+#define SC_PLLCTRL_SSC_EN BIT(31)
+#define SC_PLLCTRL2_NRSTDS BIT(28)
+#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27CTRL_WP BIT(0)
+#define SC_VPLL27CTRL3_K_LD BIT(28)
+
+/* PLL type: DSPLL */
+#define SC_DSPLLCTRL2_K_LD BIT(28)
+
+int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
+ unsigned int ssc_rate, unsigned int divn)
+{
+ void __iomem *base;
+ u32 tmp;
+
+ base = ioremap(reg_base, SZ_16);
+ if (!base)
+ return -ENOMEM;
+
+ if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
+ tmp = readl(base); /* SSCPLLCTRL */
+ tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
+ tmp |= (487 * freq * ssc_rate / divn / 512) &
+ SC_PLLCTRL_SSC_DK_MASK;
+ writel(tmp, base);
+
+ tmp = readl(base + 4);
+ tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
+ tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
+
+ udelay(50);
+ }
+
+ tmp = readl(base + 4); /* SSCPLLCTRL2 */
+ tmp |= SC_PLLCTRL2_NRSTDS;
+ writel(tmp, base + 4);
+
+ iounmap(base);
+
+ return 0;
+}
+
+int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
+{
+ void __iomem *base;
+ u32 tmp;
+
+ base = ioremap(reg_base, SZ_16);
+ if (!base)
+ return -ENOMEM;
+
+ tmp = readl(base); /* SSCPLLCTRL */
+ tmp |= SC_PLLCTRL_SSC_EN;
+ writel(tmp, base);
+
+ iounmap(base);
+
+ return 0;
+}
+
+int uniphier_ld20_vpll27_init(unsigned long reg_base)
+{
+ void __iomem *base;
+ u32 tmp;
+
+ base = ioremap(reg_base, SZ_16);
+ if (!base)
+ return -ENOMEM;
+
+ tmp = readl(base); /* VPLL27CTRL */
+ tmp |= SC_VPLL27CTRL_WP; /* write protect off */
+ writel(tmp, base);
+
+ tmp = readl(base + 8); /* VPLL27CTRL3 */
+ tmp |= SC_VPLL27CTRL3_K_LD;
+ writel(tmp, base + 8);
+
+ tmp = readl(base); /* VPLL27CTRL */
+ tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
+ writel(tmp, base);
+
+ iounmap(base);
+
+ return 0;
+}
+
+int uniphier_ld20_dspll_init(unsigned long reg_base)
+{
+ void __iomem *base;
+ u32 tmp;
+
+ base = ioremap(reg_base, SZ_16);
+ if (!base)
+ return -ENOMEM;
+
+ tmp = readl(base + 8); /* DSPLLCTRL2 */
+ tmp |= SC_DSPLLCTRL2_K_LD;
+ writel(tmp, base + 8);
+
+ iounmap(base);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
new file mode 100644
index 0000000..7746deb
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+void uniphier_ld11_pll_init(void)
+{
+ uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */
+ /* do nothing for SPLL */
+ uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */
+ uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+ mdelay(1);
+
+ uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLLCTRL);
+
+ uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+ uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+ writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */
+ writel(SC_CA_GEARUPD, SC_CA53_GEARUPD);
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c
new file mode 100644
index 0000000..8ad6883
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
+{
+ uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ /* do nothing for SPLL */
+ uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+ mdelay(1);
+
+ uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
+
+ uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+ uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+ uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
+ uniphier_ld20_dspll_init(SC_A2PLLCTRL);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c
new file mode 100644
index 0000000..13257e4
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-ld4.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "pll.h"
+
+static void upll_init(void)
+{
+ u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+ tmp = readl(SC_UPLLCTRL);
+ tmp &= ~0x18000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x0228f5c0;
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x02328000;
+ }
+ }
+
+ writel(tmp, SC_UPLLCTRL);
+
+ /* set 1 to K_LD(UPLLCTRL.bit[27]) */
+ tmp |= 0x08000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* set 1 to SNRT(UPLLCTRL.bit[28]) */
+ tmp |= 0x10000000;
+ writel(tmp, SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 1 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Set 0 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* Set 1 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* set 0 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+void uniphier_ld4_pll_init(void)
+{
+ upll_init();
+ vpll_init();
+ uniphier_ld4_dpll_ssc_en();
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c
new file mode 100644
index 0000000..cdd1fd4
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-pro4.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "pll.h"
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ /* Set VPLL27A & VPLL27B */
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
+ return;
+
+ /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Unset VPLA_K_LD and VPLB_K_LD bit */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set VPLA_M and VPLB_M to 0x20 */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
+ /* Set VPLA_K and VPLB_K for AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066666;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066666;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* wait 1 usec */
+ udelay(1);
+
+ /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Unset VPLA_SNRST and VPLB_SNRST bit */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+void uniphier_pro4_pll_init(void)
+{
+ vpll_init();
+ uniphier_ld4_dpll_ssc_en();
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-sld3.c b/arch/arm/mach-uniphier/clk/pll-sld3.c
new file mode 100644
index 0000000..37a7c12
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-sld3.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+#include "pll.h"
+
+void uniphier_sld3_pll_init(void)
+{
+ uniphier_ld4_dpll_ssc_en();
+}
diff --git a/arch/arm/mach-uniphier/clk/pll.h b/arch/arm/mach-uniphier/clk/pll.h
new file mode 100644
index 0000000..d7e9303
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef MACH_PLL_H
+#define MACH_PLL_H
+
+#define UNIPHIER_PLL_FREQ_DEFAULT (0)
+
+void uniphier_ld4_dpll_ssc_en(void);
+
+int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
+ unsigned int ssc_rate, unsigned int divn);
+int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
+int uniphier_ld20_vpll27_init(unsigned long reg_base);
+int uniphier_ld20_dspll_init(unsigned long reg_base);
+
+#endif /* MACH_PLL_H */
diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
index 6ac261d..9730330 100644
--- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
+++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
@@ -22,89 +22,107 @@
/* field separator */
#define FS " "
-static unsigned long uniphier_ld4_base[] = {
- 0x5bc01000,
- 0x5be01000,
- 0 /* sentinel */
+#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
+
+struct phy_param {
+ resource_size_t base;
+ unsigned int nr_dx;
};
-static unsigned long uniphier_pro4_base[] = {
- 0x5bc01000,
- 0x5be01000,
- 0 /* sentinel */
+static const struct phy_param uniphier_ld4_phy_param[] = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ { /* sentinel */ }
};
-static unsigned long uniphier_sld8_base[] = {
- 0x5bc01000,
- 0x5be01000,
- 0 /* sentinel */
+static const struct phy_param uniphier_pro4_phy_param[] = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5bc02000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ { .base = 0x5be02000, .nr_dx = 2, },
+ { /* sentinel */ }
};
-static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
+static const struct phy_param uniphier_sld8_phy_param[] = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ { /* sentinel */ }
+};
+
+static const struct phy_param uniphier_ld11_phy_param[] = {
+ { .base = 0x5bc01000, .nr_dx = 4, },
+ { /* sentinel */ }
+};
+
+static void print_bdl(void __iomem *reg, int n)
{
- return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
+ u32 val = readl(reg);
+ int i;
+
+ for (i = 0; i < n; i++)
+ printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
}
-static void dump_loop(unsigned long *base,
- void (*callback)(struct ddrphy_datx8 __iomem *))
+static void dump_loop(const struct phy_param *phy_param,
+ void (*callback)(void __iomem *))
{
- struct ddrphy __iomem *phy;
+ void __iomem *phy_base, *dx_base;
int p, dx;
- for (p = 0; *base; base++, p++) {
- phy = ioremap(*base, SZ_4K);
+ for (p = 0; phy_param->base; phy_param++, p++) {
+ phy_base = ioremap(phy_param->base, SZ_4K);
+ dx_base = phy_base + PHY_DX_BASE;
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ for (dx = 0; dx < phy_param->nr_dx; dx++) {
printf("PHY%dDX%d:", p, dx);
- (*callback)(&phy->dx[dx]);
+ (*callback)(dx_base);
+ dx_base += PHY_DX_STRIDE;
printf("\n");
}
- iounmap(phy);
+ iounmap(phy_base);
}
}
-static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
+static void __wbdl_dump(void __iomem *dx_base)
{
- int i;
+ print_bdl(dx_base + PHY_DX_BDLR0, 5);
+ print_bdl(dx_base + PHY_DX_BDLR1, 5);
- for (i = 0; i < 10; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
+ printf(FS "(+" PRINTF_FORMAT ")",
+ readl(dx_base + PHY_DX_LCDLR1) & 0xff);
}
-static void wbdl_dump(unsigned long *base)
+static void wbdl_dump(const struct phy_param *phy_param)
{
printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
- dump_loop(base, &__wbdl_dump);
+ dump_loop(phy_param, &__wbdl_dump);
}
-static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
+static void __rbdl_dump(void __iomem *dx_base)
{
- int i;
+ print_bdl(dx_base + PHY_DX_BDLR3, 5);
+ print_bdl(dx_base + PHY_DX_BDLR4, 4);
- for (i = 15; i < 24; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
}
-static void rbdl_dump(unsigned long *base)
+static void rbdl_dump(const struct phy_param *phy_param)
{
printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
- dump_loop(base, &__rbdl_dump);
+ dump_loop(phy_param, &__rbdl_dump);
}
-static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
+static void __wld_dump(void __iomem *dx_base)
{
int rank;
- u32 lcdlr0 = readl(&dx->lcdlr[0]);
- u32 gtr = readl(&dx->gtr);
+ u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
+ u32 gtr = readl(dx_base + PHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
@@ -115,19 +133,19 @@
}
}
-static void wld_dump(unsigned long *base)
+static void wld_dump(const struct phy_param *phy_param)
{
printf("\n--- Write Leveling Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(base, &__wld_dump);
+ dump_loop(phy_param, &__wld_dump);
}
-static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
+static void __dqsgd_dump(void __iomem *dx_base)
{
int rank;
- u32 lcdlr2 = readl(&dx->lcdlr[2]);
- u32 gtr = readl(&dx->gtr);
+ u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
+ u32 gtr = readl(dx_base + PHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
@@ -137,94 +155,108 @@
}
}
-static void dqsgd_dump(unsigned long *base)
+static void dqsgd_dump(const struct phy_param *phy_param)
{
printf("\n--- DQS Gating Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(base, &__dqsgd_dump);
+ dump_loop(phy_param, &__dqsgd_dump);
}
-static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
+static void __mdl_dump(void __iomem *dx_base)
{
int i;
- u32 mdl = readl(&dx->mdlr);
+ u32 mdl = readl(dx_base + PHY_DX_MDLR);
for (i = 0; i < 3; i++)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
-static void mdl_dump(unsigned long *base)
+static void mdl_dump(const struct phy_param *phy_param)
{
printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n");
- dump_loop(base, &__mdl_dump);
+ dump_loop(phy_param, &__mdl_dump);
}
-#define REG_DUMP(x) \
- { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
- p - (u32 *)phy, #x, p, readl(p)); }
+#define REG_DUMP(x) \
+ { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
+ printf("%3d: %-10s: %08x : %08x\n", \
+ ofst >> PHY_REG_SHIFT, #x, \
+ ptr_to_uint(reg), readl(reg)); }
-static void reg_dump(unsigned long *base)
+#define DX_REG_DUMP(dx, x) \
+ { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
+ PHY_DX_## x; \
+ void __iomem *reg = phy_base + ofst; \
+ printf("%3d: DX%d%-7s: %08x : %08x\n", \
+ ofst >> PHY_REG_SHIFT, (dx), #x, \
+ ptr_to_uint(reg), readl(reg)); }
+
+static void reg_dump(const struct phy_param *phy_param)
{
- struct ddrphy __iomem *phy;
- int p;
+ void __iomem *phy_base;
+ int p, dx;
printf("\n--- DDR PHY registers ---\n");
- for (p = 0; *base; base++, p++) {
- phy = ioremap(*base, SZ_4K);
+ for (p = 0; phy_param->base; phy_param++, p++) {
+ phy_base = ioremap(phy_param->base, SZ_4K);
- printf("== PHY%d (base: %p) ==\n", p, phy);
+ printf("== PHY%d (base: %08x) ==\n", p, ptr_to_uint(phy_base));
printf(" No: Name : Address : Data\n");
- REG_DUMP(ridr);
- REG_DUMP(pir);
- REG_DUMP(pgcr[0]);
- REG_DUMP(pgcr[1]);
- REG_DUMP(pgsr[0]);
- REG_DUMP(pgsr[1]);
- REG_DUMP(pllcr);
- REG_DUMP(ptr[0]);
- REG_DUMP(ptr[1]);
- REG_DUMP(ptr[2]);
- REG_DUMP(ptr[3]);
- REG_DUMP(ptr[4]);
- REG_DUMP(acmdlr);
- REG_DUMP(acbdlr);
- REG_DUMP(dxccr);
- REG_DUMP(dsgcr);
- REG_DUMP(dcr);
- REG_DUMP(dtpr[0]);
- REG_DUMP(dtpr[1]);
- REG_DUMP(dtpr[2]);
- REG_DUMP(mr0);
- REG_DUMP(mr1);
- REG_DUMP(mr2);
- REG_DUMP(mr3);
- REG_DUMP(dx[0].gcr);
- REG_DUMP(dx[0].gtr);
- REG_DUMP(dx[1].gcr);
- REG_DUMP(dx[1].gtr);
+ REG_DUMP(RIDR);
+ REG_DUMP(PIR);
+ REG_DUMP(PGCR0);
+ REG_DUMP(PGCR1);
+ REG_DUMP(PGSR0);
+ REG_DUMP(PGSR1);
+ REG_DUMP(PLLCR);
+ REG_DUMP(PTR0);
+ REG_DUMP(PTR1);
+ REG_DUMP(PTR2);
+ REG_DUMP(PTR3);
+ REG_DUMP(PTR4);
+ REG_DUMP(ACMDLR);
+ REG_DUMP(ACBDLR);
+ REG_DUMP(DXCCR);
+ REG_DUMP(DSGCR);
+ REG_DUMP(DCR);
+ REG_DUMP(DTPR0);
+ REG_DUMP(DTPR1);
+ REG_DUMP(DTPR2);
+ REG_DUMP(MR0);
+ REG_DUMP(MR1);
+ REG_DUMP(MR2);
+ REG_DUMP(MR3);
- iounmap(phy);
+ for (dx = 0; dx < phy_param->nr_dx; dx++) {
+ DX_REG_DUMP(dx, GCR);
+ DX_REG_DUMP(dx, GTR);
+ }
+
+ iounmap(phy_base);
}
}
static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *cmd = argv[1];
- unsigned long *base;
+ const struct phy_param *phy_param;
switch (uniphier_get_soc_type()) {
case SOC_UNIPHIER_LD4:
- base = uniphier_ld4_base;
+ phy_param = uniphier_ld4_phy_param;
break;
case SOC_UNIPHIER_PRO4:
- base = uniphier_pro4_base;
+ phy_param = uniphier_pro4_phy_param;
break;
case SOC_UNIPHIER_SLD8:
- base = uniphier_sld8_base;
+ phy_param = uniphier_sld8_phy_param;
+ break;
+ case SOC_UNIPHIER_LD11:
+ phy_param = uniphier_ld11_phy_param;
break;
default:
printf("unsupported SoC\n");
@@ -235,22 +267,22 @@
cmd = "all";
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
- wbdl_dump(base);
+ wbdl_dump(phy_param);
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
- rbdl_dump(base);
+ rbdl_dump(phy_param);
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
- wld_dump(base);
+ wld_dump(phy_param);
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
- dqsgd_dump(base);
+ dqsgd_dump(phy_param);
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
- mdl_dump(base);
+ mdl_dump(phy_param);
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
- reg_dump(base);
+ reg_dump(phy_param);
return CMD_RET_SUCCESS;
}
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-init.h b/arch/arm/mach-uniphier/dram/ddrphy-init.h
new file mode 100644
index 0000000..4216745
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/ddrphy-init.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_INIT_H
+#define ARCH_DDRPHY_INTT_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
+void ddrphy_prepare_training(void __iomem *phy_base, int rank);
+int ddrphy_training(void __iomem *phy_base);
+
+#endif /* ARCH_DDRPHY_INT_H */
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
deleted file mode 100644
index b1b4cb0..0000000
--- a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2016 Socionext Inc.
- */
-
-#ifndef _DDRPHY_LD20_REGS_H
-#define _DDRPHY_LD20_REGS_H
-
-#define PHY_SCL_DATA_0 0x00000104
-#define PHY_SCL_DATA_1 0x00000108
-#define PHY_SCL_LATENCY 0x0000010C
-#define PHY_SCL_START 0x00000100
-#define PHY_SCL_CONFIG_1 0x00000118
-#define PHY_SCL_CONFIG_2 0x0000011C
-#define PHY_PAD_CTRL 0x00000120
-#define PHY_DLL_RECALIB 0x00000124
-#define PHY_DLL_ADRCTRL 0x00000128
-#define PHY_LANE_SEL 0x0000012C
-#define PHY_DLL_TRIM_1 0x00000130
-#define PHY_DLL_TRIM_2 0x00000134
-#define PHY_DLL_TRIM_3 0x00000138
-#define PHY_SCL_MAIN_CLK_DELTA 0x00000140
-#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C
-#define PHY_WRLVL_DYN_ODT 0x00000150
-#define PHY_WRLVL_ON_OFF 0x00000154
-#define PHY_UNQ_ANALOG_DLL_1 0x0000015C
-#define PHY_DLL_INCR_TRIM_1 0x00000164
-#define PHY_DLL_INCR_TRIM_3 0x00000168
-#define PHY_SCL_CONFIG_3 0x0000016C
-#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170
-#define PHY_SCL_START_ADDR 0x00000188
-#define PHY_DSCL_CNT 0x0000019C
-#define PHY_DLL_TRIM_CLK 0x000001A4
-#define PHY_DYNAMIC_BIT_LVL 0x000001AC
-#define PHY_SCL_WINDOW_TRIM 0x000001B4
-#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8
-#define PHY_SCL_CONFIG_4 0x000001BC
-#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0
-#define PHY_VREF_TRAINING 0x000001C8
-#define PHY_SCL_GATE_TIMING 0x000001E0
-
-#endif /* _DDRPHY_LD20_REGS_H */
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
index c9e164f..620668e 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c
@@ -1,14 +1,15 @@
/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
-#include <linux/types.h>
#include <linux/io.h>
+#include "ddrphy-init.h"
#include "ddrphy-regs.h"
enum dram_freq {
@@ -27,8 +28,7 @@
static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
-int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
- bool ddr3plus)
+int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)
{
enum dram_freq freq_e;
u32 tmp;
@@ -45,34 +45,34 @@
return -EINVAL;
}
- writel(0x0300c473, &phy->pgcr[1]);
- writel(ddrphy_ptr0[freq_e], &phy->ptr[0]);
- writel(ddrphy_ptr1[freq_e], &phy->ptr[1]);
- writel(0x00083DEF, &phy->ptr[2]);
- writel(ddrphy_ptr3[freq_e], &phy->ptr[3]);
- writel(ddrphy_ptr4[freq_e], &phy->ptr[4]);
- writel(0xF004001A, &phy->dsgcr);
+ writel(0x0300c473, phy_base + PHY_PGCR1);
+ writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);
+ writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);
+ writel(0x00083DEF, phy_base + PHY_PTR2);
+ writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);
+ writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);
+ writel(0xF004001A, phy_base + PHY_DSGCR);
/* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
+ tmp = readl(phy_base + PHY_DXCCR);
tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
+ tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM;
+ writel(tmp, phy_base + PHY_DXCCR);
- writel(0x0000040B, &phy->dcr);
- writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]);
- writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]);
- writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]);
- writel(ddrphy_mr0[freq_e], &phy->mr0);
- writel(0x00000006, &phy->mr1);
- writel(ddrphy_mr2[freq_e], &phy->mr2);
- writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
+ writel(0x0000040B, phy_base + PHY_DCR);
+ writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);
+ writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);
+ writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);
+ writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);
+ writel(0x00000006, phy_base + PHY_MR1);
+ writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);
+ writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
;
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
+ writel(0x0300C473, phy_base + PHY_PGCR1);
+ writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);
return 0;
}
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
index a8fe6a0..6960ae8 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
@@ -1,7 +1,8 @@
/*
* UniPhier DDR PHY registers
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,160 +10,134 @@
#ifndef ARCH_DDRPHY_REGS_H
#define ARCH_DDRPHY_REGS_H
-#include <linux/bitops.h>
-#include <linux/compiler.h>
-#include <linux/types.h>
+#define PHY_REG_SHIFT 2
-#ifndef __ASSEMBLY__
-
-struct ddrphy {
- u32 ridr; /* Revision Identification Register */
- u32 pir; /* PHY Initialixation Register */
- u32 pgcr[2]; /* PHY General Configuration Register */
- u32 pgsr[2]; /* PHY General Status Register */
- u32 pllcr; /* PLL Control Register */
- u32 ptr[5]; /* PHY Timing Register */
- u32 acmdlr; /* AC Master Delay Line Register */
- u32 acbdlr; /* AC Bit Delay Line Register */
- u32 aciocr; /* AC I/O Configuration Register */
- u32 dxccr; /* DATX8 Common Configuration Register */
- u32 dsgcr; /* DDR System General Configuration Register */
- u32 dcr; /* DRAM Configuration Register */
- u32 dtpr[3]; /* DRAM Timing Parameters Register */
- u32 mr0; /* Mode Register 0 */
- u32 mr1; /* Mode Register 1 */
- u32 mr2; /* Mode Register 2 */
- u32 mr3; /* Mode Register 3 */
- u32 odtcr; /* ODT Configuration Register */
- u32 dtcr; /* Data Training Configuration Register */
- u32 dtar[4]; /* Data Training Address Register */
- u32 dtdr[2]; /* Data Training Data Register */
- u32 dtedr[2]; /* Data Training Eye Data Register */
- u32 pgcr2; /* PHY General Configuration Register 2 */
- u32 rsv0[8]; /* Reserved */
- u32 rdimmgcr[2]; /* RDIMM General Configuration Register */
- u32 rdimmcr0[2]; /* RDIMM Control Register */
- u32 dcuar; /* DCU Address Register */
- u32 dcudr; /* DCU Data Register */
- u32 dcurr; /* DCU Run Register */
- u32 dculr; /* DCU Loop Register */
- u32 dcugcr; /* DCU General Configuration Register */
- u32 dcutpr; /* DCU Timing Parameters Register */
- u32 dcusr[2]; /* DCU Status Register */
- u32 rsv1[8]; /* Reserved */
- u32 bistrr; /* BIST Run Register */
- u32 bistwcr; /* BIST Word Count Register */
- u32 bistmskr[3]; /* BIST Mask Register */
- u32 bistlsr; /* BIST LFSR Sed Register */
- u32 bistar[3]; /* BIST Address Register */
- u32 bistudpr; /* BIST User Data Pattern Register */
- u32 bistgsr; /* BIST General Status Register */
- u32 bistwer; /* BIST Word Error Register */
- u32 bistber[4]; /* BIST Bit Error Register */
- u32 bistwcsr; /* BIST Word Count Status Register */
- u32 bistfwr[3]; /* BIST Fail Word Register */
- u32 rsv2[10]; /* Reserved */
- u32 gpr[2]; /* General Purpose Register */
- struct ddrphy_zq { /* ZQ */
- u32 cr[2]; /* Impedance Control Register */
- u32 sr[2]; /* Impedance Status Register */
- } zq[4];
- struct ddrphy_datx8 { /* DATX8 */
- u32 gcr; /* General Configuration Register */
- u32 gsr[2]; /* General Status Register */
- u32 bdlr[5]; /* Bit Delay Line Register */
- u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
- u32 mdlr; /* Master Delay Line Register */
- u32 gtr; /* General Timing Register */
- u32 gsr2; /* General Status Register 2 */
- u32 rsv[2]; /* Reserved */
- } dx[9];
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define PIR_INIT BIT(0) /* Initialization Trigger */
-#define PIR_ZCAL BIT(1) /* Impedance Calibration */
-#define PIR_PLLINIT BIT(4) /* PLL Initialization */
-#define PIR_DCAL BIT(5) /* DDL Calibration */
-#define PIR_PHYRST BIT(6) /* PHY Reset */
-#define PIR_DRAMRST BIT(7) /* DRAM Reset */
-#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */
-#define PIR_WL BIT(9) /* Write Leveling */
-#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
-#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
-#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
-#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
-#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
-#define PIR_WREYE BIT(15) /* Write Data Eye Training */
-#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
-#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
-#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
-#define PIR_INITBYP BIT(31) /* Initialization Bypass */
-
-#define PGSR0_IDONE BIT(0) /* Initialization Done */
-#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */
-#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
-#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
-#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
-#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */
-#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
-#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
-#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
-#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
-#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */
-#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
-#define PGSR0_IERR BIT(16) /* Initialization Error */
-#define PGSR0_PLERR BIT(17) /* PLL Lock Error */
-#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */
-#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */
-#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
-#define PGSR0_WLERR BIT(21) /* Write Leveling Error */
-#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
-#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
-#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
-#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
-#define PGSR0_REERR BIT(26) /* Read Eye Training Error */
-#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */
-#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
-#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
-#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */
-
-#define DXCCR_DQSRES_OPEN (0 << 5)
-#define DXCCR_DQSRES_688_OHM (1 << 5)
-#define DXCCR_DQSRES_611_OHM (2 << 5)
-#define DXCCR_DQSRES_550_OHM (3 << 5)
-#define DXCCR_DQSRES_500_OHM (4 << 5)
-#define DXCCR_DQSRES_458_OHM (5 << 5)
-#define DXCCR_DQSRES_393_OHM (6 << 5)
-#define DXCCR_DQSRES_344_OHM (7 << 5)
-
-#define DXCCR_DQSNRES_OPEN (0 << 9)
-#define DXCCR_DQSNRES_688_OHM (1 << 9)
-#define DXCCR_DQSNRES_611_OHM (2 << 9)
-#define DXCCR_DQSNRES_550_OHM (3 << 9)
-#define DXCCR_DQSNRES_500_OHM (4 << 9)
-#define DXCCR_DQSNRES_458_OHM (5 << 9)
-#define DXCCR_DQSNRES_393_OHM (6 << 9)
-#define DXCCR_DQSNRES_344_OHM (7 << 9)
-
-#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
-#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
-#define DTCR_DTMPR BIT(6) /* Data Training using MPR */
-#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
-#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
-
-#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
-#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
-
-/* SoC-specific parameters */
-#define NR_DATX8_PER_DDRPHY 2
-
-#ifndef __ASSEMBLY__
-int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
- bool ddr3plus);
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
-int ddrphy_training(struct ddrphy __iomem *phy);
-#endif
+#define PHY_RIDR (0x000 << PHY_REG_SHIFT)
+#define PHY_PIR (0x001 << PHY_REG_SHIFT)
+#define PHY_PIR_INIT BIT(0) /* Initialization Trigger */
+#define PHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define PHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define PHY_PIR_DCAL BIT(5) /* DDL Calibration */
+#define PHY_PIR_PHYRST BIT(6) /* PHY Reset */
+#define PHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define PHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define PHY_PIR_WL BIT(9) /* Write Leveling */
+#define PHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define PHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define PHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define PHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define PHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define PHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define PHY_PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
+#define PHY_PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
+#define PHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define PHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
+#define PHY_PGCR0 (0x002 << PHY_REG_SHIFT)
+#define PHY_PGCR1 (0x003 << PHY_REG_SHIFT)
+#define PHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
+#define PHY_PGSR0 (0x004 << PHY_REG_SHIFT)
+#define PHY_PGSR0_IDONE BIT(0) /* Initialization Done */
+#define PHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define PHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define PHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define PHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define PHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define PHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define PHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define PHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define PHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define PHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define PHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define PHY_PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
+#define PHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define PHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define PHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define PHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define PHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define PHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define PHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define PHY_PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
+#define PHY_PGSR0_DTERR (7 << (PHY_PGSR0_DTERR_SHIFT))
+#define PHY_PGSR1 (0x005 << PHY_REG_SHIFT)
+#define PHY_PGSR1_VTSTOP BIT(30) /* VT Stop (v3-) */
+#define PHY_PLLCR (0x006 << PHY_REG_SHIFT)
+#define PHY_PTR0 (0x007 << PHY_REG_SHIFT)
+#define PHY_PTR1 (0x008 << PHY_REG_SHIFT)
+#define PHY_PTR2 (0x009 << PHY_REG_SHIFT)
+#define PHY_PTR3 (0x00A << PHY_REG_SHIFT)
+#define PHY_PTR4 (0x00B << PHY_REG_SHIFT)
+#define PHY_ACMDLR (0x00C << PHY_REG_SHIFT)
+#define PHY_ACBDLR (0x00D << PHY_REG_SHIFT)
+#define PHY_ACIOCR (0x00E << PHY_REG_SHIFT)
+#define PHY_DXCCR (0x00F << PHY_REG_SHIFT)
+#define PHY_DXCCR_DQSRES_OPEN (0 << 5)
+#define PHY_DXCCR_DQSRES_688_OHM (1 << 5)
+#define PHY_DXCCR_DQSRES_611_OHM (2 << 5)
+#define PHY_DXCCR_DQSRES_550_OHM (3 << 5)
+#define PHY_DXCCR_DQSRES_500_OHM (4 << 5)
+#define PHY_DXCCR_DQSRES_458_OHM (5 << 5)
+#define PHY_DXCCR_DQSRES_393_OHM (6 << 5)
+#define PHY_DXCCR_DQSRES_344_OHM (7 << 5)
+#define PHY_DXCCR_DQSNRES_OPEN (0 << 9)
+#define PHY_DXCCR_DQSNRES_688_OHM (1 << 9)
+#define PHY_DXCCR_DQSNRES_611_OHM (2 << 9)
+#define PHY_DXCCR_DQSNRES_550_OHM (3 << 9)
+#define PHY_DXCCR_DQSNRES_500_OHM (4 << 9)
+#define PHY_DXCCR_DQSNRES_458_OHM (5 << 9)
+#define PHY_DXCCR_DQSNRES_393_OHM (6 << 9)
+#define PHY_DXCCR_DQSNRES_344_OHM (7 << 9)
+#define PHY_DSGCR (0x010 << PHY_REG_SHIFT)
+#define PHY_DCR (0x011 << PHY_REG_SHIFT)
+#define PHY_DTPR0 (0x012 << PHY_REG_SHIFT)
+#define PHY_DTPR1 (0x013 << PHY_REG_SHIFT)
+#define PHY_DTPR2 (0x014 << PHY_REG_SHIFT)
+#define PHY_MR0 (0x015 << PHY_REG_SHIFT)
+#define PHY_MR1 (0x016 << PHY_REG_SHIFT)
+#define PHY_MR2 (0x017 << PHY_REG_SHIFT)
+#define PHY_MR3 (0x018 << PHY_REG_SHIFT)
+#define PHY_ODTCR (0x019 << PHY_REG_SHIFT)
+#define PHY_DTCR (0x01A << PHY_REG_SHIFT)
+#define PHY_DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
+#define PHY_DTCR_DTRANK_MASK (0x3 << (PHY_DTCR_DTRANK_SHIFT))
+#define PHY_DTCR_DTMPR BIT(6) /* Data Training using MPR */
+#define PHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define PHY_DTCR_RANKEN_MASK (0xf << (PHY_DTCR_RANKEN_SHIFT))
+#define PHY_DTAR0 (0x01B << PHY_REG_SHIFT)
+#define PHY_DTAR1 (0x01C << PHY_REG_SHIFT)
+#define PHY_DTAR2 (0x01D << PHY_REG_SHIFT)
+#define PHY_DTAR3 (0x01E << PHY_REG_SHIFT)
+#define PHY_DTDR0 (0x01F << PHY_REG_SHIFT)
+#define PHY_DTDR1 (0x020 << PHY_REG_SHIFT)
+#define PHY_DTEDR0 (0x021 << PHY_REG_SHIFT)
+#define PHY_DTEDR1 (0x022 << PHY_REG_SHIFT)
+#define PHY_PGCR2 (0x023 << PHY_REG_SHIFT)
+#define PHY_GPR0 (0x05E << PHY_REG_SHIFT)
+#define PHY_GPR1 (0x05F << PHY_REG_SHIFT)
+/* ZQ */
+#define PHY_ZQ_BASE (0x060 << PHY_REG_SHIFT)
+#define PHY_ZQ_STRIDE (0x004 << PHY_REG_SHIFT)
+#define PHY_ZQ_CR0 (0x000 << PHY_REG_SHIFT)
+#define PHY_ZQ_CR1 (0x001 << PHY_REG_SHIFT)
+#define PHY_ZQ_SR0 (0x002 << PHY_REG_SHIFT)
+#define PHY_ZQ_SR1 (0x003 << PHY_REG_SHIFT)
+/* DATX8 */
+#define PHY_DX_BASE (0x070 << PHY_REG_SHIFT)
+#define PHY_DX_STRIDE (0x010 << PHY_REG_SHIFT)
+#define PHY_DX_GCR (0x000 << PHY_REG_SHIFT)
+#define PHY_DX_GCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define PHY_DX_GCR_WLRKEN_MASK (0xf << (PHY_DX_GCR_WLRKEN_SHIFT))
+#define PHY_DX_GSR0 (0x001 << PHY_REG_SHIFT)
+#define PHY_DX_GSR1 (0x002 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR0 (0x003 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR1 (0x004 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR2 (0x005 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR3 (0x006 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR4 (0x007 << PHY_REG_SHIFT)
+#define PHY_DX_LCDLR0 (0x008 << PHY_REG_SHIFT)
+#define PHY_DX_LCDLR1 (0x009 << PHY_REG_SHIFT)
+#define PHY_DX_LCDLR2 (0x00A << PHY_REG_SHIFT)
+#define PHY_DX_MDLR (0x00B << PHY_REG_SHIFT)
+#define PHY_DX_GTR (0x00C << PHY_REG_SHIFT)
+#define PHY_DX_GSR2 (0x00D << PHY_REG_SHIFT)
#endif /* ARCH_DDRPHY_REGS_H */
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-training.c b/arch/arm/mach-uniphier/dram/ddrphy-training.c
index a348136..005ca18 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-training.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-training.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -8,35 +9,38 @@
#include <linux/err.h>
#include <linux/io.h>
+#include "ddrphy-init.h"
#include "ddrphy-regs.h"
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
+/* for LD4, Pro4, sLD8 */
+#define NR_DATX8_PER_DDRPHY 2
+
+void ddrphy_prepare_training(void __iomem *phy_base, int rank)
{
+ void __iomem *dx_base = phy_base + PHY_DX_BASE;
int dx;
- u32 __iomem tmp, *p;
+ u32 tmp;
for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- p = &phy->dx[dx].gcr;
-
- tmp = readl(p);
+ tmp = readl(dx_base + PHY_DX_GCR);
/* Specify the rank that should be write leveled */
- tmp &= ~DXGCR_WLRKEN_MASK;
- tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
- writel(tmp, p);
+ tmp &= ~PHY_DX_GCR_WLRKEN_MASK;
+ tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) &
+ PHY_DX_GCR_WLRKEN_MASK;
+ writel(tmp, dx_base + PHY_DX_GCR);
+ dx_base += PHY_DX_STRIDE;
}
- p = &phy->dtcr;
-
- tmp = readl(p);
+ tmp = readl(phy_base + PHY_DTCR);
/* Specify the rank used during data bit deskew and eye centering */
- tmp &= ~DTCR_DTRANK_MASK;
- tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
+ tmp &= ~PHY_DTCR_DTRANK_MASK;
+ tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK;
/* Use Multi-Purpose Register for DQS gate training */
- tmp |= DTCR_DTMPR;
+ tmp |= PHY_DTCR_DTMPR;
/* Specify the rank enabled for data-training */
- tmp &= ~DTCR_RANKEN_MASK;
- tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
- writel(tmp, p);
+ tmp &= ~PHY_DTCR_RANKEN_MASK;
+ tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK;
+ writel(tmp, phy_base + PHY_DTCR);
}
struct ddrphy_init_sequence {
@@ -49,60 +53,60 @@
static const struct ddrphy_init_sequence init_sequence[] = {
{
"DRAM Initialization",
- PIR_DRAMRST | PIR_DRAMINIT,
- PGSR0_DIDONE,
- PGSR0_DIERR
+ PHY_PIR_DRAMRST | PHY_PIR_DRAMINIT,
+ PHY_PGSR0_DIDONE,
+ PHY_PGSR0_DIERR
},
{
"Write Leveling",
- PIR_WL,
- PGSR0_WLDONE,
- PGSR0_WLERR
+ PHY_PIR_WL,
+ PHY_PGSR0_WLDONE,
+ PHY_PGSR0_WLERR
},
{
"Read DQS Gate Training",
- PIR_QSGATE,
- PGSR0_QSGDONE,
- PGSR0_QSGERR
+ PHY_PIR_QSGATE,
+ PHY_PGSR0_QSGDONE,
+ PHY_PGSR0_QSGERR
},
{
"Write Leveling Adjustment",
- PIR_WLADJ,
- PGSR0_WLADONE,
- PGSR0_WLAERR
+ PHY_PIR_WLADJ,
+ PHY_PGSR0_WLADONE,
+ PHY_PGSR0_WLAERR
},
{
"Read Bit Deskew",
- PIR_RDDSKW,
- PGSR0_RDDONE,
- PGSR0_RDERR
+ PHY_PIR_RDDSKW,
+ PHY_PGSR0_RDDONE,
+ PHY_PGSR0_RDERR
},
{
"Write Bit Deskew",
- PIR_WRDSKW,
- PGSR0_WDDONE,
- PGSR0_WDERR
+ PHY_PIR_WRDSKW,
+ PHY_PGSR0_WDDONE,
+ PHY_PGSR0_WDERR
},
{
"Read Eye Training",
- PIR_RDEYE,
- PGSR0_REDONE,
- PGSR0_REERR
+ PHY_PIR_RDEYE,
+ PHY_PGSR0_REDONE,
+ PHY_PGSR0_REERR
},
{
"Write Eye Training",
- PIR_WREYE,
- PGSR0_WEDONE,
- PGSR0_WEERR
+ PHY_PIR_WREYE,
+ PHY_PGSR0_WEDONE,
+ PHY_PGSR0_WEERR
}
};
-int ddrphy_training(struct ddrphy __iomem *phy)
+int ddrphy_training(void __iomem *phy_base)
{
int i;
u32 pgsr0;
- u32 init_flag = PIR_INIT;
- u32 done_flag = PGSR0_IDONE;
+ u32 init_flag = PHY_PIR_INIT;
+ u32 done_flag = PHY_PGSR0_IDONE;
int timeout = 50000; /* 50 msec is long enough */
#ifdef DISPLAY_ELAPSED_TIME
ulong start = get_timer(0);
@@ -113,7 +117,7 @@
done_flag |= init_sequence[i].done_flag;
}
- writel(init_flag, &phy->pir);
+ writel(init_flag, phy_base + PHY_PIR);
do {
if (--timeout < 0) {
@@ -122,7 +126,7 @@
return -ETIMEDOUT;
}
udelay(1);
- pgsr0 = readl(&phy->pgsr[0]);
+ pgsr0 = readl(phy_base + PHY_PGSR0);
} while ((pgsr0 & done_flag) != done_flag);
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
diff --git a/arch/arm/mach-uniphier/dram/ddruqphy-regs.h b/arch/arm/mach-uniphier/dram/ddruqphy-regs.h
new file mode 100644
index 0000000..e496af5
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/ddruqphy-regs.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DDRUQPHY_REGS_H
+#define _DDRUQPHY_REGS_H
+
+#include <linux/bitops.h>
+
+#define PHY_REG_SHIFT 2
+#define PHY_SLV_DLY_WIDTH 6
+#define PHY_BITLVL_DLY_WIDTH 6
+#define PHY_MAS_DLY_WIDTH 8
+
+#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT))
+#define PHY_SCL_START_GO_DONE BIT(28)
+#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
+#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT))
+#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT))
+#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT))
+#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT))
+#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
+#define PHY_DLL_RECALIB_INCR BIT(27)
+#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT))
+#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
+#define PHY_DLL_ADRCTRL_INCR BIT(9)
+#define PHY_DLL_ADRCTRL_MDL_SHIFT 24
+#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \
+ PHY_DLL_ADRCTRL_MDL_SHIFT)
+#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT))
+#define PHY_LANE_SEL_LANE_SHIFT 0
+#define PHY_LANE_SEL_LANE_WIDTH 8
+#define PHY_LANE_SEL_BIT_SHIFT 8
+#define PHY_LANE_SEL_BIT_WIDTH 4
+#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT))
+#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT))
+#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT))
+#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT))
+#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT))
+#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT))
+#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT))
+#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT))
+#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT))
+#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT))
+#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT))
+#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT))
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \
+ GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \
+ BIT(PHY_BITLVL_DLY_WIDTH)
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \
+ BIT(PHY_BITLVL_DLY_WIDTH + 1)
+#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT))
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT))
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \
+ GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \
+ BIT(PHY_BITLVL_DLY_WIDTH)
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \
+ BIT(PHY_BITLVL_DLY_WIDTH + 1)
+#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0)
+#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1)
+#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT))
+#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT))
+#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT))
+#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT))
+#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT))
+#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT))
+
+#endif /* _DDRUQPHY_REGS_H */
diff --git a/arch/arm/mach-uniphier/dram/umc-ld11.c b/arch/arm/mach-uniphier/dram/umc-ld11.c
index 1be18a8..7dab00c 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld11.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld11.c
@@ -8,11 +8,13 @@
#include <asm/processor.h>
#include "../init.h"
+#include "ddrphy-regs.h"
#include "umc64-regs.h"
-#define CONFIG_DDR_FREQ 1866
+#define DDR_FREQ 1600
#define DRAM_CH_NR 2
+#define RANK_BLOCKS_TR 2
enum dram_freq {
DRAM_FREQ_1600M,
@@ -25,26 +27,370 @@
DRAM_SZ_NR,
};
-/* umc */
-static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
-static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
-static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
-static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
-static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
-static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
+/* PHY */
+const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
+const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
+const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
+const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
+const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
-static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
-static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
-static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
-static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
-static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
-static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
+/* Register address */
+#define PHY_ZQ0CR1 0x00000184
+#define PHY_ZQ1CR1 0x00000194
+#define PHY_ZQ2CR1 0x000001A4
+#define PHY_DX0GCR 0x000001C0
+#define PHY_DX0GTR 0x000001F0
+#define PHY_DX1GCR 0x00000200
+#define PHY_DX1GTR 0x00000230
+#define PHY_DX2GCR 0x00000240
+#define PHY_DX2GTR 0x00000270
+#define PHY_DX3GCR 0x00000280
+#define PHY_DX3GTR 0x000002B0
+
+#define PHY_DXMDLR(dx) (0x000001EC + 0x40 * (dx))
+#define PHY_DXLCDLR0(dx) (0x000001E0 + 0x40 * (dx))
+#define PHY_DXLCDLR1(dx) (0x000001E4 + 0x40 * (dx))
+#define PHY_DXLCDLR2(dx) (0x000001E8 + 0x40 * (dx))
+#define PHY_DXBDLR1(dx) (0x000001D0 + 0x40 * (dx))
+#define PHY_DXBDLR2(dx) (0x000001D4 + 0x40 * (dx))
+
+/* MASK */
+#define PHY_ACBD_MASK 0x00FC0000
+#define PHY_CK0BD_MASK 0x0000003F
+#define PHY_CK1BD_MASK 0x00000FC0
+#define PHY_IPRD_MASK 0x000000FF
+#define PHY_WLD_MASK(rank) (0xFF << (8 * (rank)))
+#define PHY_DQSGD_MASK(rank) (0xFF << (8 * (rank)))
+#define PHY_DQSGX_MASK BIT(6)
+#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */
+#define PHY_DSDQOE_MASK 0x00000FFF
+
+static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
+{
+ u32 value;
+
+ value = (readl(addr) & ~(mask)) | (data & mask);
+ writel(value, addr);
+}
+
+static u32 ddrphy_maskreadl(u32 mask, void *addr)
+{
+ return readl(addr) & mask;
+}
+
+/* step of 0.5T for PUB-byte */
+static u8 ddrphy_get_mdl(int dx, void __iomem *phy_base)
+{
+ return ddrphy_maskreadl(PHY_IPRD_MASK, phy_base + PHY_DXMDLR(dx));
+}
+
+/* Calculating step for PUB-byte */
+static int ddrphy_hpstep(int delay, int dx, void __iomem *phy_base)
+{
+ return delay * ddrphy_get_mdl(dx, phy_base) * DDR_FREQ / 1000000;
+}
+
+static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + PHY_PGCR1);
+
+ if (enable)
+ tmp &= ~PHY_PGCR1_INHVT;
+ else
+ tmp |= PHY_PGCR1_INHVT;
+
+ writel(tmp, phy_base + PHY_PGCR1);
+
+ if (!enable) {
+ while (!(readl(phy_base + PHY_PGSR1) & PHY_PGSR1_VTSTOP))
+ cpu_relax();
+ }
+}
+
+static void ddrphy_set_ckoffset_qoffset(int delay_ckoffset0, int delay_ckoffset1,
+ int delay_qoffset, int enable,
+ void __iomem *phy_base)
+{
+ u8 ck_step0, ck_step1; /* ckoffset_step for clock */
+ u8 q_step; /* qoffset_step for clock */
+ int dx;
+
+ dx = 2; /* use dx2 in sLD11 */
+
+ ck_step0 = ddrphy_hpstep(delay_ckoffset0, dx, phy_base); /* CK-Offset */
+ ck_step1 = ddrphy_hpstep(delay_ckoffset1, dx, phy_base); /* CK-Offset */
+ q_step = ddrphy_hpstep(delay_qoffset, dx, phy_base); /* Q-Offset */
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ /* Q->[23:18], CK1->[11:6], CK0->bit[5:0] */
+ if (enable == 1)
+ ddrphy_maskwritel((q_step << 18) + (ck_step1 << 6) + ck_step0,
+ PHY_ACBD_MASK | PHY_CK1BD_MASK | PHY_CK0BD_MASK,
+ phy_base + PHY_ACBDLR);
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_set_wl_delay_dx(int dx, int r0_delay, int r1_delay,
+ int enable, void __iomem *phy_base)
+{
+ int rank;
+ int delay_wl[4];
+ u32 wl_mask = 0; /* WriteLeveling's Mask */
+ u32 wl_value = 0; /* WriteLeveling's Value */
+
+ delay_wl[0] = r0_delay & 0xfff;
+ delay_wl[1] = r1_delay & 0xfff;
+ delay_wl[2] = 0;
+ delay_wl[3] = 0;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (rank = 0; rank < 4; rank++) {
+ wl_mask |= PHY_WLD_MASK(rank);
+ /* WriteLeveling's delay */
+ wl_value |= ddrphy_hpstep(delay_wl[rank], dx, phy_base) << (8 * rank);
+ }
+
+ if (enable == 1)
+ ddrphy_maskwritel(wl_value, wl_mask, phy_base + PHY_DXLCDLR0(dx));
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_set_dqsg_delay_dx(int dx, int r0_delay, int r1_delay,
+ int enable, void __iomem *phy_base)
+{
+ int rank;
+ int delay_dqsg[4];
+ u32 dqsg_mask = 0; /* DQSGating_LCDL_delay's Mask */
+ u32 dqsg_value = 0; /* DQSGating_LCDL_delay's Value */
+
+ delay_dqsg[0] = r0_delay;
+ delay_dqsg[1] = r1_delay;
+ delay_dqsg[2] = 0;
+ delay_dqsg[3] = 0;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (rank = 0; rank < 4; rank++) {
+ dqsg_mask |= PHY_DQSGD_MASK(rank);
+ /* DQSGating's delay */
+ dqsg_value |= ddrphy_hpstep(delay_dqsg[rank], dx, phy_base) << (8 * rank);
+ }
+
+ if (enable == 1)
+ ddrphy_maskwritel(dqsg_value, dqsg_mask, phy_base + PHY_DXLCDLR2(dx));
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_set_dswb_delay_dx(int dx, int delay, int enable, void __iomem *phy_base)
+{
+ u8 dswb_step;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ dswb_step = ddrphy_hpstep(delay, dx, phy_base); /* DQS-BDL's delay */
+
+ if (enable == 1)
+ ddrphy_maskwritel(dswb_step << 24, PHY_DSWBD_MASK, phy_base + PHY_DXBDLR1(dx));
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_set_oe_delay_dx(int dx, int dqs_delay, int dq_delay,
+ int enable, void __iomem *phy_base)
+{
+ u8 dqs_oe_step, dq_oe_step;
+ u32 wdata;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ /* OE(DQS,DQ) */
+ dqs_oe_step = ddrphy_hpstep(dqs_delay, dx, phy_base); /* DQS-oe's delay */
+ dq_oe_step = ddrphy_hpstep(dq_delay, dx, phy_base); /* DQ-oe's delay */
+ wdata = ((dq_oe_step<<6) + dqs_oe_step) & 0xFFF;
+
+ if (enable == 1)
+ ddrphy_maskwritel(wdata, PHY_DSDQOE_MASK, phy_base + PHY_DXBDLR2(dx));
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_ext_dqsgt(void __iomem *phy_base)
+{
+ /* Extend DQSGating_window min:+1T max:+1T */
+ ddrphy_maskwritel(PHY_DQSGX_MASK, PHY_DQSGX_MASK, phy_base + PHY_DSGCR);
+}
+
+static void ddrphy_shift_tof_hws(void __iomem *phy_base, const int shift[][2])
+{
+ int dx, block, byte;
+ u32 lcdlr1, wdqd;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (block = 0; block < RANK_BLOCKS_TR; block++) {
+ for (byte = 0; byte < 2; byte++) {
+ dx = block * 2 + byte;
+ lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
+ wdqd = lcdlr1 & 0xff;
+ wdqd = clamp(wdqd + ddrphy_hpstep(shift[block][byte], dx, phy_base),
+ 0U, 0xffU);
+ lcdlr1 = (lcdlr1 & ~0xff) | wdqd;
+ writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
+ readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
+ }
+ }
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_shift_rof_hws(void __iomem *phy_base, const int pos_shift[][2],
+ const int neg_shift[][2])
+{
+ int dx, block, byte;
+ u32 lcdlr1, rdqsd, rdqnsd;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (block = 0; block < RANK_BLOCKS_TR; block++) {
+ for (byte = 0; byte < 2; byte++) {
+ dx = block * 2 + byte;
+ lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
+
+ /* DQS LCDL RDQNSD->[23:16] RDQSD->[15:8] */
+ rdqsd = (lcdlr1 >> 8) & 0xff;
+ rdqnsd = (lcdlr1 >> 16) & 0xff;
+ rdqsd = clamp(rdqsd + ddrphy_hpstep(pos_shift[block][byte], dx, phy_base),
+ 0U, 0xffU);
+ rdqnsd = clamp(rdqnsd + ddrphy_hpstep(neg_shift[block][byte], dx, phy_base),
+ 0U, 0xffU);
+ lcdlr1 = (lcdlr1 & ~(0xffff << 8)) | (rdqsd << 8) | (rdqnsd << 16);
+ readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
+ }
+ }
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_boot_run_hws(void __iomem *phy_base)
+{
+ /* Hard Training for DIO */
+ writel(0x0000f401, phy_base + PHY_PIR);
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+}
+
+static void ddrphy_training(void __iomem *phy_base)
+{
+ /* DIO roffset shift before hard training */
+ ddrphy_shift_rof_hws(phy_base, rof_pos_shift_pre, rof_neg_shift_pre);
+
+ /* Hard Training for each CH */
+ ddrphy_boot_run_hws(phy_base);
+
+ /* DIO toffset shift after training */
+ ddrphy_shift_tof_hws(phy_base, tof_shift);
+
+ /* DIO roffset shift after training */
+ ddrphy_shift_rof_hws(phy_base, rof_pos_shift, rof_neg_shift);
+
+ /* Extend DQSGating window min:+1T max:+1T */
+ ddrphy_ext_dqsgt(phy_base);
+}
+
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
+{
+ writel(0x40000000, phy_base + PHY_PIR);
+ writel(0x0300C4F1, phy_base + PHY_PGCR1);
+ writel(0x0C807D04, phy_base + PHY_PTR0);
+ writel(0x27100578, phy_base + PHY_PTR1);
+ writel(0x00083DEF, phy_base + PHY_PTR2);
+ writel(0x12061A80, phy_base + PHY_PTR3);
+ writel(0x08027100, phy_base + PHY_PTR4);
+ writel(0x9D9CBB66, phy_base + PHY_DTPR0);
+ writel(0x1a878400, phy_base + PHY_DTPR1);
+ writel(0x50025200, phy_base + PHY_DTPR2);
+ writel(0xF004641A, phy_base + PHY_DSGCR);
+ writel(0x0000040B, phy_base + PHY_DCR);
+ writel(0x00000d71, phy_base + PHY_MR0);
+ writel(0x00000006, phy_base + PHY_MR1);
+ writel(0x00000098, phy_base + PHY_MR2);
+ writel(0x00000000, phy_base + PHY_MR3);
+
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+
+ writel(0x00000059, phy_base + PHY_ZQ0CR1);
+ writel(0x00000019, phy_base + PHY_ZQ1CR1);
+ writel(0x00000019, phy_base + PHY_ZQ2CR1);
+ writel(0x30FC6C20, phy_base + PHY_PGCR2);
+
+ ddrphy_set_ckoffset_qoffset(119, 0, 0, 1, phy_base);
+ ddrphy_set_wl_delay_dx(0, 220, 220, 1, phy_base);
+ ddrphy_set_wl_delay_dx(1, 160, 160, 1, phy_base);
+ ddrphy_set_wl_delay_dx(2, 190, 190, 1, phy_base);
+ ddrphy_set_wl_delay_dx(3, 150, 150, 1, phy_base);
+ ddrphy_set_dqsg_delay_dx(0, 750, 750, 1, phy_base);
+ ddrphy_set_dqsg_delay_dx(1, 750, 750, 1, phy_base);
+ ddrphy_set_dqsg_delay_dx(2, 750, 750, 1, phy_base);
+ ddrphy_set_dqsg_delay_dx(3, 750, 750, 1, phy_base);
+ ddrphy_set_dswb_delay_dx(0, 0, 1, phy_base);
+ ddrphy_set_dswb_delay_dx(1, 0, 1, phy_base);
+ ddrphy_set_dswb_delay_dx(2, 0, 1, phy_base);
+ ddrphy_set_dswb_delay_dx(3, 0, 1, phy_base);
+ ddrphy_set_oe_delay_dx(0, 0, 0, 1, phy_base);
+ ddrphy_set_oe_delay_dx(1, 0, 0, 1, phy_base);
+ ddrphy_set_oe_delay_dx(2, 0, 0, 1, phy_base);
+ ddrphy_set_oe_delay_dx(3, 0, 0, 1, phy_base);
+
+ writel(0x44000E81, phy_base + PHY_DX0GCR);
+ writel(0x44000E81, phy_base + PHY_DX1GCR);
+ writel(0x44000E81, phy_base + PHY_DX2GCR);
+ writel(0x44000E81, phy_base + PHY_DX3GCR);
+ writel(0x00055002, phy_base + PHY_DX0GTR);
+ writel(0x00055002, phy_base + PHY_DX1GTR);
+ writel(0x00055010, phy_base + PHY_DX2GTR);
+ writel(0x00055010, phy_base + PHY_DX3GTR);
+ writel(0x930035C7, phy_base + PHY_DTCR);
+ writel(0x00000003, phy_base + PHY_PIR);
+ readl(phy_base + PHY_PIR);
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+
+ writel(0x00000181, phy_base + PHY_PIR);
+ readl(phy_base + PHY_PIR);
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+
+ writel(0x44181884, phy_base + PHY_DXCCR);
+ writel(0x00000001, phy_base + PHY_GPR1);
+}
+
+/* UMC */
+static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060B0B1C};
+static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x27201806};
+static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00120B04};
+static const u32 umc_cmdctle[DRAM_FREQ_NR] = {0x00680607};
+static const u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
+static const u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
+
+static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000810};
+static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000004};
+static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
+static const u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
+
+static const u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
unsigned long size, int ch)
{
+ /* Wait for PHY Init Complete */
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
@@ -52,14 +398,14 @@
writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
- writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
- writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+ writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D0);
+ writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D1);
- writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
- writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
+ writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D0);
+ writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D1);
- writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
- writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
+ writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D0);
+ writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D1);
writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
@@ -93,6 +439,7 @@
{
void __iomem *um_base = (void __iomem *)0x5B800000;
void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
+ void __iomem *phy_base = (void __iomem *)0x5BC01000;
enum dram_freq freq;
int ch, ret;
@@ -105,6 +452,24 @@
return -EINVAL;
}
+ writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+
+ writel(0x00000000, umc_ch_base + UMC_DIOCTLA);
+ writel(0x00000001, umc_ch_base + UMC_DEBUGC);
+ writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
+
+ writel(0x00000100, umc_ch_base + UMC_INITSET);
+ while (readl(umc_ch_base + UMC_INITSTAT) & BIT(8))
+ cpu_relax();
+
+ writel(0x00000100, umc_ch_base + 0x00200000 + UMC_INITSET);
+ while (readl(umc_ch_base + 0x00200000 + UMC_INITSTAT) & BIT(8))
+ cpu_relax();
+
+ ddrphy_init(phy_base, freq);
+
for (ch = 0; ch < bd->dram_nr_ch; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
@@ -117,6 +482,7 @@
umc_ch_base += 0x00200000;
}
+ ddrphy_training(phy_base);
um_init(um_base);
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c
index 186a398..ecbe101 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld20.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld20.c
@@ -1,7 +1,7 @@
/*
* Copyright (C) 2016 Socionext Inc.
*
- * based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag
+ * based on commit 5e1cb0f1caeabc6c99469dd997cb6b4f46834443 of Diag
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include "../init.h"
-#include "ddrphy-ld20-regs.h"
+#include "ddruqphy-regs.h"
#include "umc64-regs.h"
#define DRAM_CH_NR 3
@@ -30,99 +30,424 @@
DRAM_SZ_NR,
};
-/* umc */
-static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
-static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
-static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
-static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
-static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
-
-static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801};
-static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130};
-static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803};
-
-static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
-static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
-static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
-static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- {0x0049071D, 0x0078071D},
+enum dram_board { /* board type */
+ DRAM_BOARD_LD20_REF, /* LD20 reference */
+ DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */
+ DRAM_BOARD_LD20_C1, /* LD20 TV C1 */
+ DRAM_BOARD_LD21_REF, /* LD21 reference */
+ DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */
+ DRAM_BOARD_NR,
};
-static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
-static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
-static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
-static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
-static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
+/* PHY */
+static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
+ {268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */
+ {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */
+ {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV C1 */
+ {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */
+ {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */
+};
-static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
-static u32 umc_directbusctrla[DRAM_CH_NR] = {
- 0x00000000, 0x00000001, 0x00000001
+static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = {
+ {268, 268, 268}, /* LD20 reference */
+ {268, 268, 268}, /* LD20 TV */
+ {189, 189, 189}, /* LD20 TV C1 */
+ {268, 268 + 252, /* No CH2 */}, /* LD21 reference */
+ {268, 268 + 202, /* No CH2 */}, /* LD21 TV */
+};
+
+static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = {
+ {268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */
+ {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */
+ {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV C1 */
+ {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */
+ {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */
+};
+
+static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
+ {0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */
+ {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */
+ {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV C1 */
+ {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */
+ {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */
+};
+
+static const u32 ddrphy_scl_gate_timing[DRAM_CH_NR] = {
+ 0x00000140, 0x00000180, 0x00000140
+};
+
+static const int ddrphy_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
+ { /* LD20 reference */
+ {
+ 2, 1, 0, 1, 2, 1, 1, 1,
+ 2, 1, 1, 2, 1, 1, 1, 1,
+ 1, 2, 1, 1, 1, 2, 1, 1,
+ 2, 2, 0, 1, 1, 2, 2, 1,
+ },
+ {
+ 1, 1, 0, 1, 2, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 0, 0, 1, 1, 0, 0,
+ 0, 1, 1, 1, 2, 1, 2, 1,
+ },
+ {
+ 2, 2, 0, 2, 1, 1, 2, 1,
+ 1, 1, 0, 1, 1, -1, 1, 1,
+ 2, 2, 2, 2, 1, 1, 1, 1,
+ 1, 1, 1, 0, 2, 2, 1, 2,
+ },
+ },
+ { /* LD20 TV */
+ {
+ 2, 1, 0, 1, 2, 1, 1, 1,
+ 2, 1, 1, 2, 1, 1, 1, 1,
+ 1, 2, 1, 1, 1, 2, 1, 1,
+ 2, 2, 0, 1, 1, 2, 2, 1,
+ },
+ {
+ 1, 1, 0, 1, 2, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 0, 0, 1, 1, 0, 0,
+ 0, 1, 1, 1, 2, 1, 2, 1,
+ },
+ {
+ 2, 2, 0, 2, 1, 1, 2, 1,
+ 1, 1, 0, 1, 1, -1, 1, 1,
+ 2, 2, 2, 2, 1, 1, 1, 1,
+ 1, 1, 1, 0, 2, 2, 1, 2,
+ },
+ },
+ { /* LD20 TV C1 */
+ {
+ 2, 1, 0, 1, 2, 1, 1, 1,
+ 2, 1, 1, 2, 1, 1, 1, 1,
+ 1, 2, 1, 1, 1, 2, 1, 1,
+ 2, 2, 0, 1, 1, 2, 2, 1,
+ },
+ {
+ 1, 1, 0, 1, 2, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 0, 0, 1, 1, 0, 0,
+ 0, 1, 1, 1, 2, 1, 2, 1,
+ },
+ {
+ 2, 2, 0, 2, 1, 1, 2, 1,
+ 1, 1, 0, 1, 1, -1, 1, 1,
+ 2, 2, 2, 2, 1, 1, 1, 1,
+ 1, 1, 1, 0, 2, 2, 1, 2,
+ },
+ },
+ { /* LD21 reference */
+ {
+ 1, 1, 0, 1, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 1, 0, 2,
+ 1, 1, 0, 0, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 0, 0, 1,
+ },
+ { 1, 0, 2, 1, 1, 1, 1, 0,
+ 1, 0, 0, 1, 0, 1, 0, 0,
+ 1, 0, 1, 0, 1, 1, 1, 0,
+ 1, 1, 1, 1, 0, 1, 0, 0,
+ },
+ /* No CH2 */
+ },
+ { /* LD21 TV */
+ {
+ 1, 1, 0, 1, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 1, 0, 2,
+ 1, 1, 0, 0, 1, 1, 1, 1,
+ 1, 0, 0, 0, 1, 0, 0, 1,
+ },
+ { 1, 0, 2, 1, 1, 1, 1, 0,
+ 1, 0, 0, 1, 0, 1, 0, 0,
+ 1, 0, 1, 0, 1, 1, 1, 0,
+ 1, 1, 1, 1, 0, 1, 0, 0,
+ },
+ /* No CH2 */
+ },
+};
+
+static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
+ { /* LD20 reference */
+ {
+ 3, 3, 3, 2, 3, 2, 0, 2,
+ 2, 3, 3, 1, 2, 2, 2, 2,
+ 2, 2, 2, 2, 0, 1, 1, 1,
+ 2, 2, 2, 2, 3, 0, 2, 2,
+ },
+ {
+ 2, 2, 1, 1, -1, 1, 1, 1,
+ 2, 0, 2, 2, 2, 1, 0, 2,
+ 2, 1, 2, 1, 0, 1, 1, 1,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ },
+ {
+ 2, 2, 3, 2, 1, 2, 2, 2,
+ 2, 3, 4, 2, 3, 4, 3, 3,
+ 2, 2, 1, 2, 1, 1, 1, 1,
+ 2, 2, 2, 2, 1, 2, 2, 1,
+ },
+ },
+ { /* LD20 TV */
+ {
+ 3, 3, 3, 2, 3, 2, 0, 2,
+ 2, 3, 3, 1, 2, 2, 2, 2,
+ 2, 2, 2, 2, 0, 1, 1, 1,
+ 2, 2, 2, 2, 3, 0, 2, 2,
+ },
+ {
+ 2, 2, 1, 1, -1, 1, 1, 1,
+ 2, 0, 2, 2, 2, 1, 0, 2,
+ 2, 1, 2, 1, 0, 1, 1, 1,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ },
+ {
+ 2, 2, 3, 2, 1, 2, 2, 2,
+ 2, 3, 4, 2, 3, 4, 3, 3,
+ 2, 2, 1, 2, 1, 1, 1, 1,
+ 2, 2, 2, 2, 1, 2, 2, 1,
+ },
+ },
+ { /* LD20 TV C1 */
+ {
+ 3, 3, 3, 2, 3, 2, 0, 2,
+ 2, 3, 3, 1, 2, 2, 2, 2,
+ 2, 2, 2, 2, 0, 1, 1, 1,
+ 2, 2, 2, 2, 3, 0, 2, 2,
+ },
+ {
+ 2, 2, 1, 1, -1, 1, 1, 1,
+ 2, 0, 2, 2, 2, 1, 0, 2,
+ 2, 1, 2, 1, 0, 1, 1, 1,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ },
+ {
+ 2, 2, 3, 2, 1, 2, 2, 2,
+ 2, 3, 4, 2, 3, 4, 3, 3,
+ 2, 2, 1, 2, 1, 1, 1, 1,
+ 2, 2, 2, 2, 1, 2, 2, 1,
+ },
+ },
+ { /* LD21 reference */
+ {
+ 2, 2, 2, 2, 1, 2, 2, 2,
+ 2, 3, 3, 2, 2, 2, 2, 2,
+ 2, 1, 2, 2, 1, 1, 1, 1,
+ 2, 2, 2, 3, 1, 2, 2, 2,
+ },
+ {
+ 3, 4, 4, 1, 0, 1, 1, 1,
+ 1, 2, 1, 2, 2, 3, 3, 2,
+ 1, 0, 2, 1, 1, 0, 1, 0,
+ 0, 1, 0, 0, 1, 1, 0, 1,
+ },
+ /* No CH2 */
+ },
+ { /* LD21 TV */
+ {
+ 2, 2, 2, 2, 1, 2, 2, 2,
+ 2, 3, 3, 2, 2, 2, 2, 2,
+ 2, 1, 2, 2, 1, 1, 1, 1,
+ 2, 2, 2, 3, 1, 2, 2, 2,
+ },
+ {
+ 3, 4, 4, 1, 0, 1, 1, 1,
+ 1, 2, 1, 2, 2, 3, 3, 2,
+ 1, 0, 2, 1, 1, 0, 1, 0,
+ 0, 1, 0, 0, 1, 1, 0, 1,
+ },
+ /* No CH2 */
+ },
};
/* DDR PHY */
-static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
+static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
+ unsigned int bit)
{
- writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
- while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
+ WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH);
+ WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH);
+
+ writel((bit << PHY_LANE_SEL_BIT_SHIFT) |
+ (lane << PHY_LANE_SEL_LANE_SHIFT),
+ phy_base + PHY_LANE_SEL);
+}
+
+static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch)
+{
+ writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
+ while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
cpu_relax();
+ writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
- writel(0x00000000, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 0, 0);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- writel(0x00000006, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 6, 0);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- writel(0x0000000c, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 12, 0);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- writel(0x00000012, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 18, 0);
writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
- writel(0x50bb40b1, phy_base + PHY_PAD_CTRL);
+ writel(ddrphy_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL);
writel(0x00000070, phy_base + PHY_VREF_TRAINING);
writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
- writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING);
+ writel(ddrphy_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING);
writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
- writel(0x00000000, phy_base + PHY_LANE_SEL);
+ ddrphy_select_lane(phy_base, 0, 0);
writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
writel(0x00005076, phy_base + PHY_SCL_LATENCY);
}
-static int ddrphy_training(void __iomem *phy_base)
+static int ddrphy_to_dly_step(void __iomem *phy_base, unsigned int freq,
+ int delay)
+{
+ int mdl;
+
+ mdl = (readl(phy_base + PHY_DLL_ADRCTRL) & PHY_DLL_ADRCTRL_MDL_MASK) >>
+ PHY_DLL_ADRCTRL_MDL_SHIFT;
+
+ return DIV_ROUND_CLOSEST((long)freq * delay * mdl, 2 * 1000000L);
+}
+
+static void ddrphy_set_delay(void __iomem *phy_base, unsigned int reg,
+ u32 mask, u32 incr, int dly_step)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + reg);
+ tmp &= ~mask;
+ tmp |= min_t(u32, abs(dly_step), mask);
+
+ if (dly_step >= 0)
+ tmp |= incr;
+ else
+ tmp &= ~incr;
+
+ writel(tmp, phy_base + reg);
+}
+
+static void ddrphy_set_dll_recalib(void __iomem *phy_base, int dly_step)
+{
+ ddrphy_set_delay(phy_base, PHY_DLL_RECALIB,
+ PHY_DLL_RECALIB_TRIM_MASK, PHY_DLL_RECALIB_INCR,
+ dly_step);
+}
+
+static void ddrphy_set_dll_adrctrl(void __iomem *phy_base, int dly_step)
+{
+ ddrphy_set_delay(phy_base, PHY_DLL_ADRCTRL,
+ PHY_DLL_ADRCTRL_TRIM_MASK, PHY_DLL_ADRCTRL_INCR,
+ dly_step);
+}
+
+static void ddrphy_set_dll_trim_clk(void __iomem *phy_base, int dly_step)
+{
+ ddrphy_select_lane(phy_base, 0, 0);
+
+ ddrphy_set_delay(phy_base, PHY_DLL_TRIM_CLK,
+ PHY_DLL_TRIM_CLK_MASK, PHY_DLL_TRIM_CLK_INCR,
+ dly_step);
+}
+
+static void ddrphy_init_tail(void __iomem *phy_base, enum dram_board board,
+ unsigned int freq, int ch)
+{
+ int step;
+
+ step = ddrphy_to_dly_step(phy_base, freq, ddrphy_adrctrl[board][ch]);
+ ddrphy_set_dll_adrctrl(phy_base, step);
+
+ step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dlltrimclk[board][ch]);
+ ddrphy_set_dll_trim_clk(phy_base, step);
+
+ step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dllrecalib[board][ch]);
+ ddrphy_set_dll_recalib(phy_base, step);
+}
+
+static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg,
+ u32 mask, u32 incr, int shift_val)
+{
+ u32 tmp;
+ int val;
+
+ tmp = readl(phy_base + reg);
+
+ val = tmp & mask;
+ if (!(tmp & incr))
+ val = -val;
+
+ val += shift_val;
+
+ tmp &= ~(incr | mask);
+ tmp |= min_t(u32, abs(val), mask);
+ if (val >= 0)
+ tmp |= incr;
+
+ writel(tmp, phy_base + reg);
+}
+
+static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg,
+ u32 mask, u32 incr, u32 override,
+ const int *shift_val_array)
+{
+ u32 tmp;
+ int dx, bit;
+
+ tmp = readl(phy_base + reg);
+ tmp |= override;
+ writel(tmp, phy_base + reg);
+
+ for (dx = 0; dx < 4; dx++) {
+ for (bit = 0; bit < 8; bit++) {
+ ddrphy_select_lane(phy_base,
+ (PHY_BITLVL_DLY_WIDTH + 1) * dx,
+ bit);
+
+ ddrphy_shift_one_dq(phy_base, reg, mask, incr,
+ shift_val_array[dx * 8 + bit]);
+ }
+ }
+
+ ddrphy_select_lane(phy_base, 0, 0);
+}
+
+static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
+ int ch)
{
writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
writel(0x50000000, phy_base + PHY_SCL_START);
- while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
- writel(0x00080000, phy_base + PHY_SCL_START_ADDR);
+ writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR);
writel(0x11000000, phy_base + PHY_SCL_START);
- while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
- writel(0x00000000, phy_base + PHY_SCL_START_ADDR);
+ writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR);
writel(0x30500000, phy_base + PHY_SCL_START);
- while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
@@ -131,24 +456,101 @@
writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
writel(0x11000000, phy_base + PHY_SCL_START);
- while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x34000000, phy_base + PHY_SCL_START);
- while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+ writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
+ writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL);
+ writel(0x011BD0C4, phy_base + PHY_DSCL_CNT);
+
+ /* shift ip_dq trim */
+ ddrphy_shift_dq(phy_base,
+ PHY_IP_DQ_DQS_BITWISE_TRIM,
+ PHY_IP_DQ_DQS_BITWISE_TRIM_MASK,
+ PHY_IP_DQ_DQS_BITWISE_TRIM_INC,
+ PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE,
+ ddrphy_ip_dq_shift_val[board][ch]);
+
+ /* shift op_dq trim */
+ ddrphy_shift_dq(phy_base,
+ PHY_OP_DQ_DM_DQS_BITWISE_TRIM,
+ PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK,
+ PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC,
+ PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE,
+ ddrphy_op_dq_shift_val[board][ch]);
+
return 0;
}
-static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+/* UMC */
+static const u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
+static const u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
+static const u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
+static const u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
+static const u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
+
+static const u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ /* 256MB 512MB */
+ {0x00000601, 0x00000801}, /* 1866 MHz */
+};
+
+static const u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ /* 256MB 512MB */
+ {0x00000120, 0x00000130}, /* 1866 MHz */
+};
+
+static const u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ /* 256MB 512MB */
+ {0x00033603, 0x00033803}, /* 1866 MHz */
+};
+
+static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static const u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+ /* 256MB 512MB */
+ {0x0049071D, 0x0078071D}, /* 1866 MHz */
+};
+
+static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000610};
+static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000204};
+static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
+static const u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
+
+static const u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
+static const u32 umc_directbusctrla[DRAM_CH_NR] = {
+ 0x00000000, 0x00000001, 0x00000001
+};
+
+static void umc_poll_phy_init_complete(void __iomem *dc_base)
+{
+ /* Wait for PHY Init Complete */
+ while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
+ cpu_relax();
+}
+
+static int umc_dc_init(void __iomem *dc_base, unsigned int freq,
unsigned long size, int ch)
{
+ enum dram_freq freq_e;
enum dram_size size_e;
+ switch (freq) {
+ case 1866:
+ freq_e = DRAM_FREQ_1866M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %ud MHz\n", freq);
+ return -EINVAL;
+ }
+
switch (size) {
case 0:
return 0;
@@ -164,47 +566,43 @@
return -EINVAL;
}
- /* Wait for PHY Init Complete */
- while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
- cpu_relax();
-
writel(0x00000001, dc_base + UMC_DFICSOVRRD);
writel(0x00000000, dc_base + UMC_DFITURNOFF);
- writel(umc_initctla[freq], dc_base + UMC_INITCTLA);
- writel(umc_initctlb[freq], dc_base + UMC_INITCTLB);
- writel(umc_initctlc[freq], dc_base + UMC_INITCTLC);
+ writel(umc_initctla[freq_e], dc_base + UMC_INITCTLA);
+ writel(umc_initctlb[freq_e], dc_base + UMC_INITCTLB);
+ writel(umc_initctlc[freq_e], dc_base + UMC_INITCTLC);
- writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0);
+ writel(umc_drmmr0[freq_e], dc_base + UMC_DRMMR0);
writel(0x00000004, dc_base + UMC_DRMMR1);
- writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2);
+ writel(umc_drmmr2[freq_e], dc_base + UMC_DRMMR2);
writel(0x00000000, dc_base + UMC_DRMMR3);
- writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A);
- writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B);
- writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
+ writel(umc_memconf0a[freq_e][size_e], dc_base + UMC_MEMCONF0A);
+ writel(umc_memconf0b[freq_e][size_e], dc_base + UMC_MEMCONF0B);
+ writel(umc_memconfch[freq_e][size_e], dc_base + UMC_MEMCONFCH);
writel(0x00000008, dc_base + UMC_MEMMAPSET);
- writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
- writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
- writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
- writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE);
+ writel(umc_cmdctla[freq_e], dc_base + UMC_CMDCTLA);
+ writel(umc_cmdctlb[freq_e], dc_base + UMC_CMDCTLB);
+ writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC);
+ writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE);
- writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
- writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+ writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
+ writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D1);
- writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
- writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
- writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
- writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
- writel(umc_dataset[freq], dc_base + UMC_DATASET);
+ writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D0);
+ writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D1);
+ writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D0);
+ writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D1);
+ writel(umc_dataset[freq_e], dc_base + UMC_DATASET);
writel(0x00400020, dc_base + UMC_DCCGCTL);
writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
writel(0x00010200, dc_base + UMC_ACSSETB);
- writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
+ writel(umc_flowctla[freq_e], dc_base + UMC_FLOWCTLA);
writel(0x00004444, dc_base + UMC_FLOWCTLC);
writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
@@ -227,7 +625,8 @@
}
static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
- enum dram_freq freq, unsigned long size, int ch)
+ enum dram_board board, unsigned int freq,
+ unsigned long size, int ch)
{
void __iomem *dc_base = umc_ch_base + 0x00011000;
void __iomem *phy_base = phy_ch_base;
@@ -240,13 +639,17 @@
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
dc_base + UMC_DIOCTLA);
- ddrphy_init(phy_base, freq);
+ ddrphy_init(phy_base, board, ch);
+
+ umc_poll_phy_init_complete(dc_base);
+
+ ddrphy_init_tail(phy_base, board, freq, ch);
ret = umc_dc_init(dc_base, freq, size, ch);
if (ret)
return ret;
- ret = ddrphy_training(phy_base);
+ ret = ddrphy_training(phy_base, board, ch);
if (ret)
return ret;
@@ -273,15 +676,28 @@
void __iomem *um_base = (void __iomem *)0x5b600000;
void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
- enum dram_freq freq;
+ enum dram_board board;
int ch, ret;
- switch (bd->dram_freq) {
- case 1866:
- freq = DRAM_FREQ_1866M;
+ switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) {
+ case UNIPHIER_BD_BOARD_LD20_REF:
+ board = DRAM_BOARD_LD20_REF;
+ break;
+ case UNIPHIER_BD_BOARD_LD20_GLOBAL:
+ board = DRAM_BOARD_LD20_GLOBAL;
+ break;
+ case UNIPHIER_BD_BOARD_LD20_C1:
+ board = DRAM_BOARD_LD20_C1;
+ break;
+ case UNIPHIER_BD_BOARD_LD21_REF:
+ board = DRAM_BOARD_LD21_REF;
+ break;
+ case UNIPHIER_BD_BOARD_LD21_GLOBAL:
+ board = DRAM_BOARD_LD21_GLOBAL;
break;
default:
- pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+ pr_err("unsupported board type %d\n",
+ UNIPHIER_BD_BOARD_GET_TYPE(bd->flags));
return -EINVAL;
}
@@ -289,8 +705,8 @@
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
- ret = umc_ch_init(umc_ch_base, phy_ch_base, freq,
- size / (width / 16), ch);
+ ret = umc_ch_init(umc_ch_base, phy_ch_base, board,
+ bd->dram_freq, size / (width / 16), ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;
diff --git a/arch/arm/mach-uniphier/dram/umc-ld4.c b/arch/arm/mach-uniphier/dram/umc-ld4.c
index 1ea6193..90e7f2d 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld4.c
@@ -13,7 +13,7 @@
#include <asm/processor.h>
#include "../init.h"
-#include "ddrphy-regs.h"
+#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
@@ -149,7 +149,7 @@
int ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
writel(0x00000101, dc_base + UMC_DIOCTLA);
diff --git a/arch/arm/mach-uniphier/dram/umc-pro4.c b/arch/arm/mach-uniphier/dram/umc-pro4.c
index f6c2d7f..5447fa9 100644
--- a/arch/arm/mach-uniphier/dram/umc-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-pro4.c
@@ -13,7 +13,7 @@
#include <asm/processor.h>
#include "../init.h"
-#include "ddrphy-regs.h"
+#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
@@ -137,7 +137,7 @@
int phy, ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
for (phy = 0; phy < nr_phy; phy++) {
diff --git a/arch/arm/mach-uniphier/dram/umc-sld8.c b/arch/arm/mach-uniphier/dram/umc-sld8.c
index 61b1dc1..61369f1 100644
--- a/arch/arm/mach-uniphier/dram/umc-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-sld8.c
@@ -13,7 +13,7 @@
#include <asm/processor.h>
#include "../init.h"
-#include "ddrphy-regs.h"
+#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
@@ -152,7 +152,7 @@
int ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
writel(0x00000101, dc_base + UMC_DIOCTLA);
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
deleted file mode 100644
index 755a361..0000000
--- a/arch/arm/mach-uniphier/early-clk/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o
diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile
deleted file mode 100644
index 7177a8c..0000000
--- a/arch/arm/mach-uniphier/early-pinctrl/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c
deleted file mode 100644
index 537deaf..0000000
--- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd)
-{
- /* Comment format: PAD Name -> Function Name */
- sg_set_pinsel(0, 0, 8, 4); /* XECS1 -> XECS1 */
- sg_set_pinsel(1, 0, 8, 4); /* ERXW -> ERXW */
- sg_set_pinsel(2, 0, 8, 4); /* XERWE1 -> XERWE1 */
- sg_set_pinsel(6, 2, 8, 4); /* XNFRE -> XERWE0 */
- sg_set_pinsel(7, 2, 8, 4); /* XNFWE -> ES0 */
- sg_set_pinsel(8, 2, 8, 4); /* NFALE -> ES1 */
- sg_set_pinsel(9, 2, 8, 4); /* NFCLE -> ES2 */
- sg_set_pinsel(10, 2, 8, 4); /* NFD0 -> ED0 */
- sg_set_pinsel(11, 2, 8, 4); /* NFD1 -> ED1 */
- sg_set_pinsel(12, 2, 8, 4); /* NFD2 -> ED2 */
- sg_set_pinsel(13, 2, 8, 4); /* NFD3 -> ED3 */
- sg_set_pinsel(14, 2, 8, 4); /* NFD4 -> ED4 */
- sg_set_pinsel(15, 2, 8, 4); /* NFD5 -> ED5 */
- sg_set_pinsel(16, 2, 8, 4); /* NFD6 -> ED6 */
- sg_set_pinsel(17, 2, 8, 4); /* NFD7 -> ED7 */
- sg_set_iectrl_range(0, 2);
- sg_set_iectrl_range(6, 17);
-
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
deleted file mode 100644
index 6c5d58f..0000000
--- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(63, 0, 4, 4); /* RXD0 */
- sg_set_pinsel(64, 1, 4, 4); /* TXD0 */
-
- sg_set_pinsel(65, 0, 4, 4); /* RXD1 */
- sg_set_pinsel(66, 1, 4, 4); /* TXD1 */
-
- sg_set_pinsel(96, 2, 4, 4); /* RXD2 */
- sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
-#endif
-
- sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
-
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index db80074..f3f9e54 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -23,9 +23,15 @@
unsigned int dram_nr_ch;
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
unsigned int flags;
-#define UNIPHIER_BD_DDR3PLUS BIT(2)
-#define UNIPHIER_BD_PACKAGE_LD21 1
-#define UNIPHIER_BD_PACKAGE_TYPE(f) ((f) & 0x3)
+
+#define UNIPHIER_BD_DDR3PLUS BIT(2)
+
+#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x7)
+#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */
+#define UNIPHIER_BD_BOARD_LD20_GLOBAL 1 /* LD20 TV Set */
+#define UNIPHIER_BD_BOARD_LD20_C1 2 /* LD20 TV Set C1 */
+#define UNIPHIER_BD_BOARD_LD21_REF 3 /* LD21 reference */
+#define UNIPHIER_BD_BOARD_LD21_GLOBAL 4 /* LD21 TV Set */
};
const struct uniphier_board_data *uniphier_get_board_param(void);
@@ -75,13 +81,12 @@
int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd);
-int uniphier_sld3_pll_init(const struct uniphier_board_data *bd);
-int uniphier_ld4_pll_init(const struct uniphier_board_data *bd);
-int uniphier_pro4_pll_init(const struct uniphier_board_data *bd);
-int uniphier_sld8_pll_init(const struct uniphier_board_data *bd);
-
-int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
-int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
+int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd);
int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
@@ -89,9 +94,6 @@
int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
-int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
-int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd);
-
int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
@@ -99,14 +101,11 @@
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
-void uniphier_sld3_pin_init(void);
-void uniphier_ld4_pin_init(void);
-void uniphier_pro4_pin_init(void);
-void uniphier_sld8_pin_init(void);
-void uniphier_pro5_pin_init(void);
-void uniphier_pxs2_pin_init(void);
-void uniphier_ld6b_pin_init(void);
-void uniphier_ld20_pin_init(void);
+void uniphier_sld3_pll_init(void);
+void uniphier_ld4_pll_init(void);
+void uniphier_pro4_pll_init(void);
+void uniphier_ld11_pll_init(void);
+int uniphier_ld20_pll_init(const struct uniphier_board_data *bd);
void uniphier_ld4_clk_init(void);
void uniphier_pro4_clk_init(void);
@@ -115,6 +114,8 @@
void uniphier_ld11_clk_init(void);
void uniphier_ld20_clk_init(void);
+int uniphier_pin_init(const char *pinconfig_name);
+void uniphier_smp_kick_all_cpus(void);
void cci500_init(int nr_slaves);
#define pr_err(fmt, args...) printf(fmt, ##args)
diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c
index de2dc62..fdb2838 100644
--- a/arch/arm/mach-uniphier/init/init-ld11.c
+++ b/arch/arm/mach-uniphier/init/init-ld11.c
@@ -15,7 +15,9 @@
{
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
- uniphier_ld20_early_pin_init(bd);
+ /* pins for NAND and System Bus are multiplexed */
+ if (spl_boot_device() != BOOT_DEVICE_NAND)
+ uniphier_pin_init("system_bus_grp");
support_card_reset();
@@ -31,12 +33,14 @@
led_puts("L2");
- led_puts("L3");
-
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
+ led_puts("L3");
+
+ uniphier_ld11_dpll_init(bd);
+
led_puts("L4");
{
diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c
index 7f66053..37b860a 100644
--- a/arch/arm/mach-uniphier/init/init-ld20.c
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -14,7 +15,9 @@
{
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
- uniphier_ld20_early_pin_init(bd);
+ /* pins for NAND and System Bus are multiplexed */
+ if (spl_boot_device() != BOOT_DEVICE_NAND)
+ uniphier_pin_init("system_bus_grp");
support_card_reset();
@@ -31,12 +34,14 @@
led_puts("L2");
- led_puts("L3");
-
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
+ led_puts("L3");
+
+ uniphier_ld20_dpll_init(bd);
+
led_puts("L4");
{
diff --git a/arch/arm/mach-uniphier/init/init-ld4.c b/arch/arm/mach-uniphier/init/init-ld4.c
index b1c9b5d..2f4c60d 100644
--- a/arch/arm/mach-uniphier/init/init-ld4.c
+++ b/arch/arm/mach-uniphier/init/init-ld4.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2013-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -19,7 +21,7 @@
support_card_reset();
- uniphier_ld4_pll_init(bd);
+ uniphier_ld4_dpll_init(bd);
support_card_init();
@@ -53,9 +55,5 @@
led_puts("L5");
- uniphier_ld4_enable_dpll_ssc(bd);
-
- led_puts("L6");
-
return 0;
}
diff --git a/arch/arm/mach-uniphier/init/init-pro4.c b/arch/arm/mach-uniphier/init/init-pro4.c
index 3528d84..2825150 100644
--- a/arch/arm/mach-uniphier/init/init-pro4.c
+++ b/arch/arm/mach-uniphier/init/init-pro4.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2013-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -16,7 +18,7 @@
support_card_reset();
- uniphier_pro4_pll_init(bd);
+ uniphier_pro4_dpll_init(bd);
support_card_init();
@@ -50,9 +52,5 @@
led_puts("L5");
- uniphier_ld4_enable_dpll_ssc(bd);
-
- led_puts("L6");
-
return 0;
}
diff --git a/arch/arm/mach-uniphier/init/init-sld3.c b/arch/arm/mach-uniphier/init/init-sld3.c
index 50fcbb0..ee3245c 100644
--- a/arch/arm/mach-uniphier/init/init-sld3.c
+++ b/arch/arm/mach-uniphier/init/init-sld3.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2013-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -16,11 +18,9 @@
uniphier_sbc_init_admulti(bd);
- uniphier_sld3_early_pin_init(bd);
-
support_card_reset();
- uniphier_sld3_pll_init(bd);
+ uniphier_sld3_dpll_init(bd);
support_card_init();
@@ -45,9 +45,5 @@
led_puts("L5");
- uniphier_sld3_enable_dpll_ssc(bd);
-
- led_puts("L6");
-
return 0;
}
diff --git a/arch/arm/mach-uniphier/init/init-sld8.c b/arch/arm/mach-uniphier/init/init-sld8.c
index 07c6d60..82d036b 100644
--- a/arch/arm/mach-uniphier/init/init-sld8.c
+++ b/arch/arm/mach-uniphier/init/init-sld8.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2013-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -19,7 +21,7 @@
support_card_reset();
- uniphier_sld8_pll_init(bd);
+ uniphier_sld8_dpll_init(bd);
support_card_init();
@@ -53,9 +55,5 @@
led_puts("L5");
- uniphier_ld4_enable_dpll_ssc(bd);
-
- led_puts("L6");
-
return 0;
}
diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c
index 3d4b504..e607ac9 100644
--- a/arch/arm/mach-uniphier/memconf/memconf.c
+++ b/arch/arm/mach-uniphier/memconf/memconf.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -14,7 +16,7 @@
int memconf_init(const struct uniphier_board_data *bd)
{
- u32 tmp = 0;
+ u32 tmp;
unsigned long size_per_word;
tmp = readl(SG_MEMCONF);
diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c
index 6987d1e..e53bcdf 100644
--- a/arch/arm/mach-uniphier/micro-support-card.c
+++ b/arch/arm/mach-uniphier/micro-support-card.c
@@ -49,7 +49,7 @@
return 0;
}
-int check_support_card(void)
+int checkboard(void)
{
printf("SC: Micro Support Card ");
return support_card_show_revision();
@@ -60,9 +60,8 @@
/*
* After power on, we need to keep the LAN controller in reset state
* for a while. (200 usec)
- * Fortunately, enough wait time is already inserted in pll_init()
- * function. So we do not have to wait here.
*/
+ udelay(200);
support_card_reset_deassert();
}
diff --git a/arch/arm/mach-uniphier/micro-support-card.h b/arch/arm/mach-uniphier/micro-support-card.h
index 5da0ada..4dae603 100644
--- a/arch/arm/mach-uniphier/micro-support-card.h
+++ b/arch/arm/mach-uniphier/micro-support-card.h
@@ -1,17 +1,18 @@
/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef ARCH_BOARD_H
-#define ARCH_BOARD_H
+#ifndef MICRO_SUPPORT_CARD_H
+#define MICRO_SUPPORT_CARD_H
#if defined(CONFIG_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
void support_card_late_init(void);
-int check_support_card(void);
void led_puts(const char *s);
#else
static inline void support_card_reset(void)
@@ -26,14 +27,9 @@
{
}
-static inline int check_support_card(void)
-{
- return 0;
-}
-
static inline void led_puts(const char *s)
{
}
#endif
-#endif /* ARCH_BOARD_H */
+#endif /* MICRO_SUPPORT_CARD_H */
diff --git a/arch/arm/mach-uniphier/pinctrl-glue.c b/arch/arm/mach-uniphier/pinctrl-glue.c
new file mode 100644
index 0000000..48549e3
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl-glue.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/err.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass.h>
+
+#include "init.h"
+
+int uniphier_pin_init(const char *pinconfig_name)
+{
+ struct udevice *pctldev, *config, *next;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_PINCTRL, &pctldev);
+ if (ret)
+ return ret;
+
+ device_foreach_child_safe(config, next, pctldev) {
+ if (strcmp(config->name, pinconfig_name))
+ continue;
+
+ return pinctrl_generic_set_state(pctldev, config);
+ }
+
+ return -ENODEV;
+}
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
deleted file mode 100644
index 7f4d9f7..0000000
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pinctrl-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pinctrl-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pinctrl-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
deleted file mode 100644
index 645b901..0000000
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void uniphier_ld20_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(3, 0, 8, 4); /* XNFWP -> XNFWP */
- sg_set_pinsel(4, 0, 8, 4); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(5, 0, 8, 4); /* NFRYBY0 -> NFRYBY0 */
- sg_set_pinsel(6, 0, 8, 4); /* XNFRE -> XNFRE */
- sg_set_pinsel(7, 0, 8, 4); /* XNFWE -> XNFWE */
- sg_set_pinsel(8, 0, 8, 4); /* NFALE -> NFALE */
- sg_set_pinsel(9, 0, 8, 4); /* NFCLE -> NFCLE */
- sg_set_pinsel(10, 0, 8, 4); /* NFD0 -> NFD0 */
- sg_set_pinsel(11, 0, 8, 4); /* NFD1 -> NFD1 */
- sg_set_pinsel(12, 0, 8, 4); /* NFD2 -> NFD2 */
- sg_set_pinsel(13, 0, 8, 4); /* NFD3 -> NFD3 */
- sg_set_pinsel(14, 0, 8, 4); /* NFD4 -> NFD4 */
- sg_set_pinsel(15, 0, 8, 4); /* NFD5 -> NFD5 */
- sg_set_pinsel(16, 0, 8, 4); /* NFD6 -> NFD6 */
- sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */
- sg_set_iectrl_range(3, 17);
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(46, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(47, 0, 8, 4); /* USB0OD -> USB0OD */
- sg_set_pinsel(48, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(49, 0, 8, 4); /* USB1OD -> USB1OD */
- sg_set_pinsel(50, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(51, 0, 8, 4); /* USB2OD -> USB2OD */
- sg_set_pinsel(52, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */
- sg_set_iectrl_range(46, 53);
-#endif
-
- sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
- sg_set_iectrl(149);
- sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
- sg_set_iectrl(153);
-}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c
deleted file mode 100644
index 625d40c..0000000
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void uniphier_ld4_pin_init(void)
-{
- u32 tmp;
-
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */
- sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */
- sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */
- sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */
- sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */
- sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */
- sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */
- sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */
- sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */
- sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */
- sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */
- sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */
- sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */
- sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */
- sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
-#endif
-
- tmp = readl(SG_IECTRL);
- tmp |= 0x41;
- writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c
deleted file mode 100644
index 913722b..0000000
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void uniphier_ld6b_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(30, 0, 8, 4); /* XNFRE -> XNFRE */
- sg_set_pinsel(31, 0, 8, 4); /* XNFWE -> XNFWE */
- sg_set_pinsel(32, 0, 8, 4); /* NFALE -> NFALE */
- sg_set_pinsel(33, 0, 8, 4); /* NFCLE -> NFCLE */
- sg_set_pinsel(34, 0, 8, 4); /* XNFWP -> XNFWP */
- sg_set_pinsel(35, 0, 8, 4); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(36, 0, 8, 4); /* NRYBY0 -> NRYBY0 */
- sg_set_pinsel(37, 0, 8, 4); /* XNFCE1 -> NRYBY1 */
- sg_set_pinsel(38, 0, 8, 4); /* NRYBY1 -> XNFCE1 */
- sg_set_pinsel(39, 0, 8, 4); /* NFD0 -> NFD0 */
- sg_set_pinsel(40, 0, 8, 4); /* NFD1 -> NFD1 */
- sg_set_pinsel(41, 0, 8, 4); /* NFD2 -> NFD2 */
- sg_set_pinsel(42, 0, 8, 4); /* NFD3 -> NFD3 */
- sg_set_pinsel(43, 0, 8, 4); /* NFD4 -> NFD4 */
- sg_set_pinsel(44, 0, 8, 4); /* NFD5 -> NFD5 */
- sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */
- sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(57, 0, 8, 4); /* USB0OD -> USB0OD */
- sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(59, 0, 8, 4); /* USB1OD -> USB1OD */
- sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(61, 0, 8, 4); /* USB2OD -> USB2OD */
- sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(63, 0, 8, 4); /* USB3OD -> USB3OD */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c
deleted file mode 100644
index 3796491..0000000
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void uniphier_pro4_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */
- sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */
- sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */
- sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */
- sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */
- sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */
- sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */
- sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */
- sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */
- sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */
- sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */
- sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */
- sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */
- sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
- /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */
- /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */
- sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c
deleted file mode 100644
index 32ba923..0000000
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void uniphier_pro5_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */
- sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */
- sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */
- sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */
- sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */
- sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
- sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */
- sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */
- sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */
- sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */
- sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */
- sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */
- sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */
- sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */
- sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */
- sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */
- sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c
deleted file mode 100644
index 2d62ab3..0000000
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void uniphier_pxs2_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(30, 8, 8, 4); /* XNFRE -> XNFRE */
- sg_set_pinsel(31, 8, 8, 4); /* XNFWE -> XNFWE */
- sg_set_pinsel(32, 8, 8, 4); /* NFALE -> NFALE */
- sg_set_pinsel(33, 8, 8, 4); /* NFCLE -> NFCLE */
- sg_set_pinsel(34, 8, 8, 4); /* XNFWP -> XNFWP */
- sg_set_pinsel(35, 8, 8, 4); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(36, 8, 8, 4); /* NRYBY0 -> NRYBY0 */
- sg_set_pinsel(37, 8, 8, 4); /* XNFCE1 -> NRYBY1 */
- sg_set_pinsel(38, 8, 8, 4); /* NRYBY1 -> XNFCE1 */
- sg_set_pinsel(39, 8, 8, 4); /* NFD0 -> NFD0 */
- sg_set_pinsel(40, 8, 8, 4); /* NFD1 -> NFD1 */
- sg_set_pinsel(41, 8, 8, 4); /* NFD2 -> NFD2 */
- sg_set_pinsel(42, 8, 8, 4); /* NFD3 -> NFD3 */
- sg_set_pinsel(43, 8, 8, 4); /* NFD4 -> NFD4 */
- sg_set_pinsel(44, 8, 8, 4); /* NFD5 -> NFD5 */
- sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */
- sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(57, 8, 8, 4); /* USB0OD -> USB0OD */
- sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(59, 8, 8, 4); /* USB1OD -> USB1OD */
- sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(61, 8, 8, 4); /* USB2OD -> USB2OD */
- sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(63, 8, 8, 4); /* USB3OD -> USB3OD */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c
deleted file mode 100644
index 62edc49..0000000
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void uniphier_sld3_pin_init(void)
-{
-#ifdef CONFIG_USB_EHCI
- sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
- sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */
-
- sg_set_pinsel(15, 0, 4, 4); /* USB1OC */
- sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */
-
- sg_set_pinsel(17, 0, 4, 4); /* USB2OC */
- sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */
-
- sg_set_pinsel(19, 0, 4, 4); /* USB3OC */
- sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(38, 1, 4, 4); /* NFALE_GB, NFCLE_GB */
- sg_set_pinsel(39, 1, 4, 4); /* XNFRYBY0_GB */
- sg_set_pinsel(40, 1, 4, 4); /* XNFCE0_GB, XNFRE_GB, XNFWE_GB, XNFWP_GB */
- sg_set_pinsel(41, 1, 4, 4); /* XNFRYBY1_GB, XNFCE1_GB */
- sg_set_pinsel(58, 1, 4, 4); /* NFD[0-3]_GB */
- sg_set_pinsel(59, 1, 4, 4); /* NFD[4-7]_GB */
-#endif
-
-#ifdef CONFIG_MMC_UNIPHIER
- /* eMMC */
- sg_set_pinsel(55, 1, 4, 4); /* XERST */
- sg_set_pinsel(56, 1, 4, 4); /* MMCDAT[0-3] */
- sg_set_pinsel(57, 1, 4, 4); /* MMCDAT[4-7] */
- sg_set_pinsel(60, 1, 4, 4); /* MMCCLK, MMCCMD */
-
- /* SD card */
- sg_set_pinsel(42, 1, 4, 4); /* SD1CLK, SD1CMD, SD1DAT[0-3] */
- sg_set_pinsel(43, 1, 4, 4); /* SD1CD */
- sg_set_pinsel(44, 1, 4, 4); /* SD1WP */
- sg_set_pinsel(45, 1, 4, 4); /* SDVTCG */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c
deleted file mode 100644
index 1c97c8b..0000000
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void uniphier_sld8_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */
- sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */
- sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */
- sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */
- sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */
- sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */
- sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */
- sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */
- sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */
- sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */
- sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */
- sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */
- sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */
- sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
- sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile
deleted file mode 100644
index 63f169c..0000000
--- a/arch/arm/mach-uniphier/pll/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pll-init-sld3.o pll-spectrum-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-init-ld4.o pll-spectrum-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pll-init-pro4.o pll-spectrum-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-init-sld8.o pll-spectrum-ld4.o
diff --git a/arch/arm/mach-uniphier/pll/pll-init-ld4.c b/arch/arm/mach-uniphier/pll/pll-init-ld4.c
deleted file mode 100644
index 57c1d9f..0000000
--- a/arch/arm/mach-uniphier/pll/pll-init-ld4.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-#include "../sg-regs.h"
-
-#undef DPLL_SSC_RATE_1PER
-
-static int dpll_init(unsigned int dram_freq)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT (DPLLCTRL.bit[29:20])
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x000f0000;
- switch (dram_freq) {
- case 1333:
- tmp |= 0x000d0000;
- break;
- case 1600:
- tmp |= 0x000c0000;
- break;
- default:
- pr_err("Unsupported frequency");
- return -EINVAL;
- }
-
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~SC_DPLLCTRL_SSC_RATE;
-#else
- tmp |= SC_DPLLCTRL_SSC_RATE;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-
- return 0;
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-int uniphier_ld4_pll_init(const struct uniphier_board_data *bd)
-{
- int ret;
-
- ret = dpll_init(bd->dram_freq);
- if (ret)
- return ret;
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/pll/pll-init-pro4.c b/arch/arm/mach-uniphier/pll/pll-init-pro4.c
deleted file mode 100644
index a7e4e0e..0000000
--- a/arch/arm/mach-uniphier/pll/pll-init-pro4.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-#include "../sg-regs.h"
-
-#undef DPLL_SSC_RATE_1PER
-
-static int dpll_init(unsigned int dram_freq)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT ( DPLLCTRL.bit[29:20] )
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~(0x000f0000);
- switch (dram_freq) {
- case 1333:
- tmp |= 0x000d0000;
- break;
- case 1600:
- tmp |= 0x000c0000;
- break;
- default:
- pr_err("Unsupported frequency");
- return -EINVAL;
- }
-
- /*
- * Set Moduration rate
- * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
- */
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~0x00008000;
-#else
- tmp |= 0x00008000;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-
- return 0;
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- /* Set VPLL27A & VPLL27B */
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
- return;
-
- /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Unset VPLA_K_LD and VPLB_K_LD bit */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set VPLA_M and VPLB_M to 0x20 */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
- /* Set VPLA_K and VPLB_K for AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* wait 1 usec */
- udelay(1);
-
- /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Unset VPLA_SNRST and VPLB_SNRST bit */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-int uniphier_pro4_pll_init(const struct uniphier_board_data *bd)
-{
- int ret;
-
- ret = dpll_init(bd->dram_freq);
- if (ret)
- return ret;
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 1 usec in vpll_init() so 1 usec can be saved here.
- */
- udelay(499);
-
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld3.c b/arch/arm/mach-uniphier/pll/pll-init-sld3.c
deleted file mode 100644
index 5b4f2e3..0000000
--- a/arch/arm/mach-uniphier/pll/pll-init-sld3.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "../init.h"
-
-int uniphier_sld3_pll_init(const struct uniphier_board_data *bd)
-{
- /* add pll init code here */
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-sld8.c
deleted file mode 100644
index b26106e..0000000
--- a/arch/arm/mach-uniphier/pll/pll-init-sld8.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-#include "../sg-regs.h"
-
-static void dpll_init(void)
-{
- u32 tmp;
- /*
- * Set DPLL SSC parameters for DPLLCTRL3
- * [23] DIVN_TEST 0x1
- * [22:16] DIVN 0x50
- * [10] FREFSEL_TEST 0x1
- * [9:8] FREFSEL 0x2
- * [4] ICPD_TEST 0x1
- * [3:0] ICPD 0xb
- */
- tmp = readl(SC_DPLLCTRL3);
- tmp &= ~0x00ff0717;
- tmp |= 0x00d0061b;
- writel(tmp, SC_DPLLCTRL3);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL
- * <-1%> <-2%>
- * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
- * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x3ff07fff;
-#ifdef CONFIG_DPLL_SSC_RATE_1PER
- tmp |= 0x084018bf;
-#else
- tmp |= 0x084031a6;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL2
- * [31:29] SSC_STEP 0
- * [27] SSC_REG_REF 1
- * [26:20] SSC_M 79 (0x4f)
- * [19:0] SSC_K 964689 (0xeb851)
- */
- tmp = readl(SC_DPLLCTRL2);
- tmp &= ~0xefffffff;
- tmp |= 0x0cfeb851;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-int uniphier_sld8_pll_init(const struct uniphier_board_data *bd)
-{
- dpll_init();
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c
deleted file mode 100644
index dc97697..0000000
--- a/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
-{
- u32 tmp;
-
- tmp = readl(SC_DPLLCTRL);
- tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
-
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c b/arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c
deleted file mode 100644
index ff09a92..0000000
--- a/arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
-{
- u32 tmp;
-
- tmp = readl(SC_DPLLCTRL);
- tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
-
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/print_misc_info.c b/arch/arm/mach-uniphier/print_misc_info.c
deleted file mode 100644
index 695b7ae..0000000
--- a/arch/arm/mach-uniphier/print_misc_info.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "micro-support-card.h"
-
-int misc_init_f(void)
-{
- return check_support_card();
-}
diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index ef02830..d3aa185 100644
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -1,7 +1,8 @@
/*
* UniPhier SC (System Control) block registers for ARMv8 SoCs
*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -11,6 +12,27 @@
#define SC_BASE_ADDR 0x61840000
+/* PLL type: SSC */
+#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */
+#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */
+#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */
+#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */
+#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */
+#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */
+#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */
+#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */
+#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */
+#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */
+#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
+#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
+
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
@@ -30,6 +52,8 @@
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4_MIO (1 << 10)
+#define SC_CLKCTRL4_STDMAC (1 << 8)
#define SC_CLKCTRL4_PERI (1 << 7)
#define SC_CLKCTRL4_ETHER (1 << 6)
#define SC_CLKCTRL4_NAND (1 << 0)
@@ -41,4 +65,12 @@
#define SC_CLKCTRL7_UMC31 (1 << 1)
#define SC_CLKCTRL7_UMC30 (1 << 0)
+#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
+#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
+#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008)
+#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
+#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
+#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
+#define SC_CA_GEARUPD (1 << 0)
+
#endif /* SC64_REGS_H */
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index a982320..c465918 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,9 +1,34 @@
if ARCH_ZYNQ
+config SPL_FAT_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ default y if ZYNQ_SDHCI
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+config SPL_SPI_FLASH_SUPPORT
+ default y if ZYNQ_QSPI
+
+config SPL_SPI_SUPPORT
+ default y if ZYNQ_QSPI
+
config SYS_BOARD
default "zynq"
config SYS_VENDOR
+ string "Vendor name"
default "xilinx"
config SYS_SOC
@@ -20,4 +45,11 @@
config SYS_MALLOC_F_LEN
default 0x600
+config BOOT_INIT_FILE
+ string "boot.bin init register filename"
+ default ""
+ help
+ Add register writes to boot.bin format (max 256 pairs).
+ Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
+
endif
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index 914b1fe..ba9171e 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -43,12 +43,8 @@
unsigned int zynq_get_silicon_version(void)
{
- unsigned int ver;
-
- ver = (readl(&devcfg_base->mctrl) &
- ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
-
- return ver;
+ return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
+ >> ZYNQ_SILICON_VER_SHIFT;
}
void reset_cpu(ulong addr)
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 05f4099..2d3bf2a 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -14,6 +14,9 @@
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
+#define SLCR_NAND_L2_SEL 0x10
+#define SLCR_NAND_L2_SEL_MASK 0x1F
+
#define SLCR_USB_L1_SEL 0x04
#define SLCR_IDCODE_MASK 0x1F000
@@ -36,6 +39,14 @@
u32 check_val;
};
+static const int nand8_pins[] = {
+ 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
+};
+
+static const int nand16_pins[] = {
+ 16, 17, 18, 19, 20, 21, 22, 23
+};
+
static const int usb0_pins[] = {
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
};
@@ -46,6 +57,20 @@
static const struct zynq_slcr_mio_get_status mio_periphs[] = {
{
+ "nand8",
+ nand8_pins,
+ ARRAY_SIZE(nand8_pins),
+ SLCR_NAND_L2_SEL_MASK,
+ SLCR_NAND_L2_SEL,
+ },
+ {
+ "nand16",
+ nand16_pins,
+ ARRAY_SIZE(nand16_pins),
+ SLCR_NAND_L2_SEL_MASK,
+ SLCR_NAND_L2_SEL,
+ },
+ {
"usb0",
usb0_pins,
ARRAY_SIZE(usb0_pins),
diff --git a/arch/avr32/cpu/interrupts.c b/arch/avr32/cpu/interrupts.c
index 4a03e19..de20220 100644
--- a/arch/avr32/cpu/interrupts.c
+++ b/arch/avr32/cpu/interrupts.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <div64.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/sysreg.h>
diff --git a/arch/avr32/include/asm/errno.h b/arch/avr32/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/avr32/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/avr32/include/asm/linkage.h b/arch/avr32/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/avr32/include/asm/linkage.h
diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c
index 4b4cf93..81b7090 100644
--- a/arch/blackfin/cpu/gpio.c
+++ b/arch/blackfin/cpu/gpio.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
diff --git a/arch/blackfin/cpu/interrupts.c b/arch/blackfin/cpu/interrupts.c
index 45c92c3..abb7dc1 100644
--- a/arch/blackfin/cpu/interrupts.c
+++ b/arch/blackfin/cpu/interrupts.c
@@ -47,10 +47,7 @@
*/
ulong get_tbclk(void)
{
- ulong tbclk;
-
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
+ return CONFIG_SYS_HZ;
}
void enable_interrupts(void)
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index 3d98a00..de3c979 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -171,7 +171,6 @@
}
#endif
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_CPU CONFIG_BFIN_CPU
diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/blackfin/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S
index b5d51bd..1bd914e 100644
--- a/arch/m68k/cpu/mcf5227x/start.S
+++ b/arch/m68k/cpu/mcf5227x/start.S
@@ -10,10 +10,6 @@
#include "version.h"
#include <asm/cache.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#define _START _start
#define _FAULT _fault
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index c4f6082..8533108 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -10,10 +10,6 @@
#include "version.h"
#include <asm/cache.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#define _START _start
#define _FAULT _fault
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 9837c41..ab199b1 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -10,10 +10,6 @@
#include "version.h"
#include <asm/cache.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#define _START _start
#define _FAULT _fault
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index da41c9a..536daa4 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -10,10 +10,6 @@
#include "version.h"
#include <asm/cache.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#define _START _start
#define _FAULT _fault
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index 302fca5..4678643 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -13,10 +13,6 @@
#include "version.h"
#include <asm/cache.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#define _START _start
#define _FAULT _fault
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index bc48ca0..0487d84 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -15,10 +15,6 @@
#include "version.h"
#include <asm/cache.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#define _START _start
#define _FAULT _fault
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
index fecf253..2296f9a 100644
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ b/arch/m68k/cpu/mcf547x_8x/start.S
@@ -10,10 +10,6 @@
#include "version.h"
#include <asm/cache.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#define _START _start
#define _FAULT _fault
diff --git a/arch/m68k/include/asm/errno.h b/arch/m68k/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/m68k/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/m68k/include/asm/linkage.h b/arch/m68k/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/m68k/include/asm/linkage.h
diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index 3163354..cb90c83 100644
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -192,7 +192,5 @@
*/
ulong get_tbclk(void)
{
- ulong tbclk;
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
+ return CONFIG_SYS_HZ;
}
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index f4bb091..8e6d926 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -29,13 +29,13 @@
}
#ifdef CONFIG_SPL_OS_BOOT
-void __noreturn jump_to_image_linux(void *arg)
+void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg)
{
debug("Entering kernel arg pointer: 0x%p\n", arg);
typedef void (*image_entry_arg_t)(char *, ulong, ulong)
__attribute__ ((noreturn));
image_entry_arg_t image_entry =
- (image_entry_arg_t)spl_image.entry_point;
+ (image_entry_arg_t)spl_image->entry_point;
image_entry(NULL, 0, (ulong)arg);
}
diff --git a/arch/microblaze/include/asm/errno.h b/arch/microblaze/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/microblaze/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/microblaze/include/asm/linkage.h b/arch/microblaze/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/microblaze/include/asm/linkage.h
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 3eb3440..2732203 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -17,6 +17,11 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *images)
{
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 21066f0..d97930e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -20,12 +20,15 @@
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
+ select ROM_EXCEPTION_VECTORS
config TARGET_MALTA
bool "Support malta"
select DM
select DM_SERIAL
select DYNAMIC_IO_PORT_BASE
+ select MIPS_CM
+ select MIPS_L2_CACHE
select OF_CONTROL
select OF_ISA_BUS
select SUPPORTS_BIG_ENDIAN
@@ -38,6 +41,7 @@
select SUPPORTS_CPU_MIPS64_R6
select SWAP_IO_SPACE
select MIPS_L1_CACHE_SHIFT_6
+ select ROM_EXCEPTION_VECTORS
config TARGET_VCT
bool "Support vct"
@@ -45,6 +49,7 @@
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select ROM_EXCEPTION_VECTORS
config TARGET_DBAU1X00
bool "Support dbau1x00"
@@ -53,6 +58,7 @@
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select ROM_EXCEPTION_VECTORS
select MIPS_TUNE_4KC
config TARGET_PB1X00
@@ -61,6 +67,7 @@
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select ROM_EXCEPTION_VECTORS
select MIPS_TUNE_4KC
config ARCH_ATH79
@@ -73,10 +80,45 @@
select OF_CONTROL
select DM
+config TARGET_BOSTON
+ bool "Support Boston"
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+ select MIPS_CM
+ select MIPS_L1_CACHE_SHIFT_6
+ select MIPS_L2_CACHE
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_CPU_MIPS32_R6
+ select SUPPORTS_CPU_MIPS64_R1
+ select SUPPORTS_CPU_MIPS64_R2
+ select SUPPORTS_CPU_MIPS64_R6
+ select ROM_EXCEPTION_VECTORS
+
+config TARGET_XILFPGA
+ bool "Support Imagination Xilfpga"
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+ select DM_ETH
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select MIPS_L1_CACHE_SHIFT_4
+ select ROM_EXCEPTION_VECTORS
+ help
+ This supports IMGTEC MIPSfpga platform
+
endchoice
source "board/dbau1x00/Kconfig"
+source "board/imgtec/boston/Kconfig"
source "board/imgtec/malta/Kconfig"
+source "board/imgtec/xilfpga/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
@@ -157,6 +199,20 @@
endchoice
+menu "General setup"
+
+config ROM_EXCEPTION_VECTORS
+ bool "Build U-Boot image with exception vectors"
+ help
+ Enable this to include exception vectors in the U-Boot image. This is
+ required if the U-Boot entry point is equal to the address of the
+ CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
+ U-Boot booted from parallel NOR flash).
+ Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
+ In that case the image size will be reduced by 0x500 bytes.
+
+endmenu
+
menu "OS boot interface"
config MIPS_BOOT_CMDLINE_LEGACY
@@ -246,6 +302,17 @@
config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
+config MIPS_INIT_STACK_IN_SRAM
+ bool
+ default n
+ help
+ Select this if the initial stack frame could be setup in SRAM.
+ Normally the initial stack frame is set up in DRAM which is often
+ only available after lowlevel_init. With this option the initial
+ stack frame and the early C environment is set up before
+ lowlevel_init. Thus lowlevel_init does not need to be implemented
+ in assembler.
+
config SYS_DCACHE_SIZE
int
default 0
@@ -300,9 +367,31 @@
default "4" if MIPS_L1_CACHE_SHIFT_4
default "5"
+config MIPS_L2_CACHE
+ bool
+ help
+ Select this if your system includes an L2 cache and you want U-Boot
+ to initialise & maintain it.
+
config DYNAMIC_IO_PORT_BASE
bool
+config MIPS_CM
+ bool
+ help
+ Select this if your system contains a MIPS Coherence Manager and you
+ wish U-Boot to configure it or make use of it to retrieve system
+ information such as cache configuration.
+
+config MIPS_CM_BASE
+ hex
+ default 0x1fbf8000
+ help
+ The physical base address at which to map the MIPS Coherence Manager
+ Global Configuration Registers (GCRs). This should be set such that
+ the GCRs occupy a region of the physical address space which is
+ otherwise unused, or at minimum that software doesn't need to access.
+
endif
endmenu
diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/Makefile
index fc6b455..429fd3a 100644
--- a/arch/mips/cpu/Makefile
+++ b/arch/mips/cpu/Makefile
@@ -7,3 +7,5 @@
obj-y += time.o
obj-y += interrupts.o
obj-y += cpu.o
+
+obj-$(CONFIG_MIPS_CM) += cm_init.o
diff --git a/arch/mips/cpu/cm_init.S b/arch/mips/cpu/cm_init.S
new file mode 100644
index 0000000..ddcaa49
--- /dev/null
+++ b/arch/mips/cpu/cm_init.S
@@ -0,0 +1,45 @@
+/*
+ * MIPS Coherence Manager (CM) Initialisation
+ *
+ * Copyright (c) 2016 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/cm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+
+LEAF(mips_cm_map)
+ /* Config3 must exist for a CM to be present */
+ mfc0 t0, CP0_CONFIG, 1
+ bgez t0, 2f
+ mfc0 t0, CP0_CONFIG, 2
+ bgez t0, 2f
+
+ /* Check Config3.CMGCR to determine CM presence */
+ mfc0 t0, CP0_CONFIG, 3
+ and t0, t0, MIPS_CONF3_CMGCR
+ beqz t0, 2f
+
+ /* Find the current physical GCR base address */
+1: MFC0 t0, CP0_CMGCRBASE
+ PTR_SLL t0, t0, 4
+
+ /* If the GCRs are where we want, we're done */
+ PTR_LI t1, CONFIG_MIPS_CM_BASE
+ beq t0, t1, 2f
+
+ /* Move the GCRs to our configured base address */
+ PTR_LI t2, CKSEG1
+ PTR_ADDU t0, t0, t2
+ sw zero, GCR_BASE_UPPER(t0)
+ sw t1, GCR_BASE(t0)
+
+ /* Re-check the GCR base */
+ b 1b
+
+2: jr ra
+ END(mips_cm_map)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 391feb3..1b919ed 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <command.h>
#include <linux/compiler.h>
+#include <asm/cache.h>
#include <asm/mipsregs.h>
#include <asm/reboot.h>
@@ -35,3 +36,9 @@
write_c0_index(index);
tlb_write_indexed();
}
+
+int arch_cpu_init(void)
+{
+ mips_cache_probe();
+ return 0;
+}
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index fc6dd66..6740fdf 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -12,10 +12,6 @@
#include <asm/regdef.h>
#include <asm/mipsregs.h>
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-#endif
-
#ifndef CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_SP_OFFSET)
@@ -38,129 +34,25 @@
# define STATUS_SET ST0_KX
#endif
- /*
- * For the moment disable interrupts, mark the kernel mode and
- * set ST0_KX so that the CPU does not spit fire when using
- * 64-bit addresses.
- */
- .macro setup_c0_status set clr
- .set push
- mfc0 t0, CP0_STATUS
- or t0, ST0_CU0 | \set | 0x1f | \clr
- xor t0, 0x1f | \clr
- mtc0 t0, CP0_STATUS
- .set noreorder
- sll zero, 3 # ehb
- .set pop
- .endm
-
.set noreorder
-ENTRY(_start)
- /* U-Boot entry point */
- b reset
+ .macro init_wr sel
+ MTC0 zero, CP0_WATCHLO,\sel
+ mtc0 t1, CP0_WATCHHI,\sel
+ mfc0 t0, CP0_WATCHHI,\sel
+ bgez t0, wr_done
nop
+ .endm
- .org 0x10
-#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
- /*
- * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
- * access external NOR flashes. If the board boots from NOR flash the
- * internal BootROM does a blind read at address 0xB0000010 to read the
- * initial configuration for that EBU in order to access the flash
- * device with correct parameters. This config option is board-specific.
- */
- .word CONFIG_SYS_XWAY_EBU_BOOTCFG
- .word 0x0
-#elif defined(CONFIG_MALTA)
- /*
- * Linux expects the Board ID here.
- */
- .word 0x00000420 # 0x420 (Malta Board with CoreLV)
- .word 0x00000000
-#endif
+ .macro uhi_mips_exception
+ move k0, t9 # preserve t9 in k0
+ move k1, a0 # preserve a0 in k1
+ li t9, 15 # UHI exception operation
+ li a0, 0 # Use hard register context
+ sdbbp 1 # Invoke UHI operation
+ .endm
- .org 0x200
- /* TLB refill, 32 bit task */
-1: b 1b
- nop
-
- .org 0x280
- /* XTLB refill, 64 bit task */
-1: b 1b
- nop
-
- .org 0x300
- /* Cache error exception */
-1: b 1b
- nop
-
- .org 0x380
- /* General exception */
-1: b 1b
- nop
-
- .org 0x400
- /* Catch interrupt exceptions */
-1: b 1b
- nop
-
- .org 0x480
- /* EJTAG debug exception */
-1: b 1b
- nop
-
- .align 4
-reset:
-
- /* Clear watch registers */
- MTC0 zero, CP0_WATCHLO
- mtc0 zero, CP0_WATCHHI
-
- /* WP(Watch Pending), SW0/1 should be cleared */
- mtc0 zero, CP0_CAUSE
-
- setup_c0_status STATUS_SET 0
-
- /* Init Timer */
- mtc0 zero, CP0_COUNT
- mtc0 zero, CP0_COMPARE
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- /* CONFIG0 register */
- li t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
-#endif
-
- /*
- * Initialize $gp, force pointer sized alignment of bal instruction to
- * forbid the compiler to put nop's between bal and _gp. This is
- * required to keep _gp and ra aligned to 8 byte.
- */
- .align PTRLOG
- bal 1f
- nop
- PTR _gp
-1:
- PTR_L gp, 0(ra)
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- /* Initialize any external memory */
- PTR_LA t9, lowlevel_init
- jalr t9
- nop
-
- /* Initialize caches... */
- PTR_LA t9, mips_cache_reset
- jalr t9
- nop
-
- /* ... and enable them */
- li t0, CONFIG_SYS_MIPS_CACHE_MODE
- mtc0 t0, CP0_CONFIG
-#endif
-
- /* Set up temporary stack */
+ .macro setup_stack_gd
li t0, -16
PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0 # force 16 byte alignment
@@ -186,9 +78,196 @@
#ifdef CONFIG_SYS_MALLOC_F_LEN
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
+ .endm
+
+ENTRY(_start)
+ /* U-Boot entry point */
+ b reset
+ mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
+
+#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
+ /*
+ * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
+ * access external NOR flashes. If the board boots from NOR flash the
+ * internal BootROM does a blind read at address 0xB0000010 to read the
+ * initial configuration for that EBU in order to access the flash
+ * device with correct parameters. This config option is board-specific.
+ */
+ .org 0x10
+ .word CONFIG_SYS_XWAY_EBU_BOOTCFG
+ .word 0x0
+#endif
+#if defined(CONFIG_MALTA)
+ /*
+ * Linux expects the Board ID here.
+ */
+ .org 0x10
+ .word 0x00000420 # 0x420 (Malta Board with CoreLV)
+ .word 0x00000000
+#endif
+
+#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
+ /*
+ * Exception vector entry points. When running from ROM, an exception
+ * cannot be handled. Halt execution and transfer control to debugger,
+ * if one is attached.
+ */
+ .org 0x200
+ /* TLB refill, 32 bit task */
+ uhi_mips_exception
+
+ .org 0x280
+ /* XTLB refill, 64 bit task */
+ uhi_mips_exception
+
+ .org 0x300
+ /* Cache error exception */
+ uhi_mips_exception
+
+ .org 0x380
+ /* General exception */
+ uhi_mips_exception
+
+ .org 0x400
+ /* Catch interrupt exceptions */
+ uhi_mips_exception
+
+ .org 0x480
+ /* EJTAG debug exception */
+1: b 1b
+ nop
+
+ .org 0x500
+#endif
+
+reset:
+#if __mips_isa_rev >= 6
+ mfc0 t0, CP0_CONFIG, 5
+ and t0, t0, MIPS_CONF5_VP
+ beqz t0, 1f
+ nop
+
+ b 2f
+ mfc0 t0, CP0_GLOBALNUMBER
+#endif
+
+1: mfc0 t0, CP0_EBASE
+ and t0, t0, EBASE_CPUNUM
+
+ /* Hang if this isn't the first CPU in the system */
+2: beqz t0, 4f
+ nop
+3: wait
+ b 3b
+ nop
+
+ /* Init CP0 Status */
+4: mfc0 t0, CP0_STATUS
+ and t0, ST0_IMPL
+ or t0, ST0_BEV | ST0_ERL | STATUS_SET
+ mtc0 t0, CP0_STATUS
+
+ /*
+ * Check whether CP0 Config1 is implemented. If not continue
+ * with legacy Watch register initialization.
+ */
+ mfc0 t0, CP0_CONFIG
+ bgez t0, wr_legacy
+ nop
+
+ /*
+ * Check WR bit in CP0 Config1 to determine if Watch registers
+ * are implemented.
+ */
+ mfc0 t0, CP0_CONFIG, 1
+ andi t0, (1 << 3)
+ beqz t0, wr_done
+ nop
+
+ /* Clear Watch Status bits and disable watch exceptions */
+ li t1, 0x7 # Clear I, R and W conditions
+ init_wr 0
+ init_wr 1
+ init_wr 2
+ init_wr 3
+ init_wr 4
+ init_wr 5
+ init_wr 6
+ init_wr 7
+ b wr_done
+ nop
+
+wr_legacy:
+ MTC0 zero, CP0_WATCHLO
+ mtc0 zero, CP0_WATCHHI
+
+wr_done:
+ /* Clear WP, IV and SW interrupts */
+ mtc0 zero, CP0_CAUSE
+
+ /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
+ mtc0 zero, CP0_COMPARE
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ mfc0 t0, CP0_CONFIG
+ and t0, t0, MIPS_CONF_IMPL
+ or t0, t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+ ehb
+#endif
+
+ /*
+ * Initialize $gp, force pointer sized alignment of bal instruction to
+ * forbid the compiler to put nop's between bal and _gp. This is
+ * required to keep _gp and ra aligned to 8 byte.
+ */
+ .align PTRLOG
+ bal 1f
+ nop
+ PTR _gp
+1:
+ PTR_L gp, 0(ra)
+
+#ifdef CONFIG_MIPS_CM
+ PTR_LA t9, mips_cm_map
+ jalr t9
+ nop
+#endif
+
+#ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
+ /* Set up initial stack and global data */
+ setup_stack_gd
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+ /* Initialize any external memory */
+ PTR_LA t9, lowlevel_init
+ jalr t9
+ nop
+# endif
+
+ /* Initialize caches... */
+ PTR_LA t9, mips_cache_reset
+ jalr t9
+ nop
+
+# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+ /* Initialize any external memory */
+ PTR_LA t9, lowlevel_init
+ jalr t9
+ nop
+# endif
+#endif
+
+#ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
+ /* Set up initial stack and global data */
+ setup_stack_gd
+#endif
move a0, zero # a0 <-- boot_flags = 0
PTR_LA t9, board_init_f
+
jr t9
move ra, zero
@@ -214,12 +293,9 @@
PTR_LI t0, CONFIG_SYS_MONITOR_BASE
PTR_SUB s1, s2, t0 # s1 <-- relocation offset
- PTR_LA t3, in_ram
- PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end
+ PTR_LA t2, __image_copy_end
move t1, a2
- PTR_ADD gp, s1 # adjust gp
-
/*
* t0 = source address
* t1 = target address
@@ -232,32 +308,14 @@
blt t0, t2, 1b
PTR_ADDU t1, PTRSIZE
- /* If caches were enabled, we would have to flush them here. */
- PTR_SUB a1, t1, s2 # a1 <-- size
- PTR_LA t9, flush_cache
- jalr t9
- move a0, s2 # a0 <-- destination address
-
- /* Jump to where we've relocated ourselves */
- PTR_ADDIU t0, s2, in_ram - _start
- jr t0
- nop
-
- PTR __rel_dyn_end
- PTR __rel_dyn_start
- PTR __image_copy_end
- PTR _GLOBAL_OFFSET_TABLE_
- PTR num_got_entries
-
-in_ram:
/*
* Now we want to update GOT.
*
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/
- PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries
- PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ PTR_LA t3, num_got_entries
+ PTR_LA t8, _GLOBAL_OFFSET_TABLE_
PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
PTR_LI t2, 2
@@ -272,8 +330,8 @@
PTR_ADDIU t8, PTRSIZE
/* Update dynamic relocations */
- PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start
- PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
+ PTR_LA t1, __rel_dyn_start
+ PTR_LA t2, __rel_dyn_end
b 2f # skip first reserved entry
PTR_ADDIU t1, 2 * PTRSIZE
@@ -298,6 +356,20 @@
PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
/*
+ * Flush caches to ensure our newly modified instructions are visible
+ * to the instruction cache. We're still running with the old GOT, so
+ * apply the reloc offset to the start address.
+ */
+ PTR_LA a0, __text_start
+ PTR_LA a1, __text_end
+ PTR_SUB a1, a1, a0
+ PTR_LA t9, flush_cache
+ jalr t9
+ PTR_ADD a0, s1
+
+ PTR_ADD gp, s1 # adjust gp
+
+ /*
* Clear BSS
*
* GOT is now relocated. Thus __bss_start and __bss_end can be
diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds
index 7d71c11..0129c99 100644
--- a/arch/mips/cpu/u-boot.lds
+++ b/arch/mips/cpu/u-boot.lds
@@ -19,7 +19,9 @@
. = ALIGN(4);
.text : {
+ __text_start = .;
*(.text*)
+ __text_end = .;
}
. = ALIGN(4);
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 2f04d73..30fcc2b 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -4,8 +4,10 @@
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
+dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts
new file mode 100644
index 0000000..1d4eeda
--- /dev/null
+++ b/arch/mips/dts/img,boston.dts
@@ -0,0 +1,222 @@
+/dts-v1/;
+
+#include <dt-bindings/clock/boston-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "img,boston";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "img,mips";
+ reg = <0>;
+ clocks = <&clk_boston BOSTON_CLK_CPU>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ gic: interrupt-controller {
+ compatible = "mti,gic";
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&clk_boston BOSTON_CLK_CPU>;
+ };
+ };
+
+ pci0: pci@10000000 {
+ status = "disabled";
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ device_type = "pci";
+ reg = <0x10000000 0x2000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0 0x40000000
+ 0x40000000 0 0x40000000>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pci0_intc 0>,
+ <0 0 0 2 &pci0_intc 1>,
+ <0 0 0 3 &pci0_intc 2>,
+ <0 0 0 4 &pci0_intc 3>;
+
+ pci0_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pci1: pci@12000000 {
+ status = "disabled";
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ device_type = "pci";
+ reg = <0x12000000 0x2000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0 0x20000000
+ 0x20000000 0 0x20000000>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pci1_intc 0>,
+ <0 0 0 2 &pci1_intc 1>,
+ <0 0 0 3 &pci1_intc 2>,
+ <0 0 0 4 &pci1_intc 3>;
+
+ pci1_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pci2: pci@14000000 {
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ device_type = "pci";
+ reg = <0x14000000 0x2000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0 0x16000000
+ 0x16000000 0 0x100000>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pci2_intc 0>,
+ <0 0 0 2 &pci2_intc 1>,
+ <0 0 0 3 &pci2_intc 2>,
+ <0 0 0 4 &pci2_intc 3>;
+
+ pci2_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ pci2_root@0,0,0 {
+ compatible = "pci10ee,7021";
+ reg = <0x00000000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ eg20t_bridge@1,0,0 {
+ compatible = "pci8086,8800";
+ reg = <0x00010000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ eg20t_mac@2,0,1 {
+ compatible = "pci8086,8802";
+ reg = <0x00020100 0 0 0 0>;
+ phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>;
+ };
+
+ eg20t_gpio: eg20t_gpio@2,0,2 {
+ compatible = "pci8086,8803";
+ reg = <0x00020200 0 0 0 0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ eg20t_i2c@2,12,2 {
+ compatible = "pci8086,8817";
+ reg = <0x00026200 0 0 0 0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@0x68 {
+ compatible = "st,m41t81s";
+ reg = <0x68>;
+ };
+ };
+ };
+ };
+ };
+
+ plat_regs: system-controller@17ffd000 {
+ compatible = "img,boston-platform-regs", "syscon";
+ reg = <0x17ffd000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ clk_boston: clock {
+ compatible = "img,boston-clock";
+ #clock-cells = <1>;
+ regmap = <&plat_regs>;
+ u-boot,dm-pre-reloc;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&plat_regs>;
+ offset = <0x10>;
+ mask = <0x10>;
+ };
+
+ uart0: uart@17ffe000 {
+ compatible = "ns16550a";
+ reg = <0x17ffe000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&clk_boston BOSTON_CLK_SYS>;
+
+ u-boot,dm-pre-reloc;
+ };
+
+ lcd: lcd@17fff000 {
+ compatible = "img,boston-lcd";
+ reg = <0x17fff000 0x8>;
+ };
+
+ flash@18000000 {
+ compatible = "cfi-flash";
+ reg = <0x18000000 0x8000000>;
+ bank-width = <2>;
+ };
+};
diff --git a/arch/mips/dts/microAptiv.dtsi b/arch/mips/dts/microAptiv.dtsi
new file mode 100644
index 0000000..81d518e
--- /dev/null
+++ b/arch/mips/dts/microAptiv.dtsi
@@ -0,0 +1,21 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "img,xilfpga";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,m14Kc";
+ clocks = <&ext>;
+ reg = <0>;
+ };
+ };
+
+ ext: ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+};
diff --git a/arch/mips/dts/nexys4ddr.dts b/arch/mips/dts/nexys4ddr.dts
new file mode 100644
index 0000000..e254ab1
--- /dev/null
+++ b/arch/mips/dts/nexys4ddr.dts
@@ -0,0 +1,62 @@
+/dts-v1/;
+
+#include "microAptiv.dtsi"
+
+/ {
+ compatible = "digilent,nexys4ddr";
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ aliases {
+ console = &axi_uart16550;
+ };
+
+ axi_ethernetlite: ethernet@10e00000 {
+ compatible = "xlnx,xps-ethernetlite-1.00.a";
+ device_type = "network";
+ local-mac-address = [08 86 4C 0D F7 09];
+ phy-handle = <&phy0>;
+ reg = <0x10e00000 0x10000>;
+ xlnx,duplex = <0x1>;
+ xlnx,include-global-buffers = <0x1>;
+ xlnx,include-internal-loopback = <0x0>;
+ xlnx,include-mdio = <0x1>;
+ xlnx,instance = "axi_ethernetlite_inst";
+ xlnx,rx-ping-pong = <0x1>;
+ xlnx,s-axi-id-width = <0x1>;
+ xlnx,tx-ping-pong = <0x1>;
+ xlnx,use-internal = <0x0>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: phy@1 {
+ compatible = <0x0007c0f0 0xfffffff0>;
+ device_type = "ethernet-phy";
+ reg = <1>;
+ } ;
+ } ;
+ } ;
+
+
+ axi_uart16550: serial@10400000 {
+ compatible = "ns16550a";
+ reg = <0x10400000 0x10000>;
+
+ reg-shift = <2>;
+ reg-offset = <0x1000>;
+
+ clock-frequency = <50000000>;
+
+ };
+};
+
diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h
new file mode 100644
index 0000000..5352b1c
--- /dev/null
+++ b/arch/mips/include/asm/asm-offsets.h
@@ -0,0 +1,5 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <generated/asm-offsets.h>
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 0cea581..83165d5 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -19,4 +19,15 @@
*/
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+#ifndef __ASSEMBLY__
+/**
+ * mips_cache_probe() - Probe the properties of the caches
+ *
+ * Call this to probe the properties such as line sizes of the caches
+ * present in the system, if any. This must be done before cache maintenance
+ * functions such as flush_cache may be called.
+ */
+void mips_cache_probe(void);
+#endif
+
#endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
new file mode 100644
index 0000000..b9ab0c6
--- /dev/null
+++ b/arch/mips/include/asm/cm.h
@@ -0,0 +1,62 @@
+/*
+ * MIPS Coherence Manager (CM) Register Definitions
+ *
+ * Copyright (c) 2016 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __MIPS_ASM_CM_H__
+#define __MIPS_ASM_CM_H__
+
+/* Global Control Register (GCR) offsets */
+#define GCR_BASE 0x0008
+#define GCR_BASE_UPPER 0x000c
+#define GCR_REV 0x0030
+#define GCR_L2_CONFIG 0x0130
+#define GCR_L2_TAG_ADDR 0x0600
+#define GCR_L2_TAG_ADDR_UPPER 0x0604
+#define GCR_L2_TAG_STATE 0x0608
+#define GCR_L2_TAG_STATE_UPPER 0x060c
+#define GCR_L2_DATA 0x0610
+#define GCR_L2_DATA_UPPER 0x0614
+#define GCR_Cx_COHERENCE 0x2008
+
+/* GCR_REV CM versions */
+#define GCR_REV_CM3 0x0800
+
+/* GCR_L2_CONFIG fields */
+#define GCR_L2_CONFIG_ASSOC_SHIFT 0
+#define GCR_L2_CONFIG_ASSOC_BITS 8
+#define GCR_L2_CONFIG_LINESZ_SHIFT 8
+#define GCR_L2_CONFIG_LINESZ_BITS 4
+#define GCR_L2_CONFIG_SETSZ_SHIFT 12
+#define GCR_L2_CONFIG_SETSZ_BITS 4
+#define GCR_L2_CONFIG_BYPASS (1 << 20)
+
+/* GCR_Cx_COHERENCE */
+#define GCR_Cx_COHERENCE_DOM_EN (0xff << 0)
+#define GCR_Cx_COHERENCE_EN (0x1 << 0)
+
+#ifndef __ASSEMBLY__
+
+#include <asm/io.h>
+
+static inline void *mips_cm_base(void)
+{
+ return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
+}
+
+static inline unsigned long mips_cm_l2_line_size(void)
+{
+ unsigned long l2conf, line_sz;
+
+ l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG);
+
+ line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT;
+ line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
+ return line_sz ? (2 << line_sz) : 0;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __MIPS_ASM_CM_H__ */
diff --git a/arch/mips/include/asm/errno.h b/arch/mips/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/mips/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 37f8ed5..0078bbe 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -21,6 +21,13 @@
unsigned long rev;
unsigned long ver;
#endif
+#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
+ unsigned short l1i_line_size;
+ unsigned short l1d_line_size;
+#endif
+#ifdef CONFIG_MIPS_L2_CACHE
+ unsigned short l2_line_size;
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 5b86386..ee7a592 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -501,7 +501,7 @@
if (flags == MAP_NOCACHE)
return ioremap(paddr, len);
- return (void *)paddr;
+ return (void *)CKSEG0ADDR(paddr);
}
/*
diff --git a/arch/mips/include/asm/linkage.h b/arch/mips/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/mips/include/asm/linkage.h
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 3185dc7..7a9d222 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -39,6 +39,7 @@
#define CP0_ENTRYLO0 $2
#define CP0_ENTRYLO1 $3
#define CP0_CONF $3
+#define CP0_GLOBALNUMBER $3, 1
#define CP0_CONTEXT $4
#define CP0_PAGEMASK $5
#define CP0_WIRED $6
@@ -298,6 +299,7 @@
#define STATUSF_IP14 (_ULCAST_(1) << 6)
#define STATUSB_IP15 7
#define STATUSF_IP15 (_ULCAST_(1) << 7)
+#define ST0_IMPL (_ULCAST_(3) << 16)
#define ST0_CH 0x00040000
#define ST0_NMI 0x00080000
#define ST0_SR 0x00100000
@@ -361,6 +363,11 @@
#define CAUSEF_BD (_ULCAST_(1) << 31)
/*
+ * Bits in the coprocessor 0 EBase register.
+ */
+#define EBASE_CPUNUM 0x3ff
+
+/*
* Bits in the coprocessor 0 config register.
*/
/* Generic bits. */
@@ -450,6 +457,7 @@
#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
+#define MIPS_CONF_IMPL (_ULCAST_(0x1ff) << 16)
#define MIPS_CONF_M (_ULCAST_(1) << 31)
/*
@@ -484,9 +492,13 @@
#define MIPS_CONF1_TLBS_SIZE (6)
#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
+#define MIPS_CONF2_SA_SHF 0
#define MIPS_CONF2_SA (_ULCAST_(15) << 0)
+#define MIPS_CONF2_SL_SHF 4
#define MIPS_CONF2_SL (_ULCAST_(15) << 4)
+#define MIPS_CONF2_SS_SHF 8
#define MIPS_CONF2_SS (_ULCAST_(15) << 8)
+#define MIPS_CONF2_L2B (_ULCAST_(1) << 12)
#define MIPS_CONF2_SU (_ULCAST_(15) << 12)
#define MIPS_CONF2_TA (_ULCAST_(15) << 16)
#define MIPS_CONF2_TL (_ULCAST_(15) << 20)
@@ -548,8 +560,10 @@
#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
+#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
+#define MIPS_CONF5_L2C (_ULCAST_(1) << 10)
#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index e6435cc..c9c5961 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -262,4 +262,12 @@
#define die_if_kernel(msg, regs) \
__die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
+static inline void execution_hazard_barrier(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n"
+ "ehb\n"
+ ".set reorder");
+}
+
#endif /* _ASM_SYSTEM_H */
diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
index 1f527bb..71ff41d 100644
--- a/arch/mips/include/asm/u-boot-mips.h
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -5,4 +5,8 @@
#ifndef _U_BOOT_MIPS_H_
#define _U_BOOT_MIPS_H_
+void exc_handler(void);
+void except_vec3_generic(void);
+void except_vec_ejtag_debug(void);
+
#endif /* _U_BOOT_MIPS_H_ */
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index b7ce5df..659c6ad 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -7,6 +7,9 @@
obj-y += cache.o
obj-y += cache_init.o
+obj-y += genex.o
+obj-y += stack.o
+obj-y += traps.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/mips/lib/asm-offsets.c b/arch/mips/lib/asm-offsets.c
new file mode 100644
index 0000000..9ed295a
--- /dev/null
+++ b/arch/mips/lib/asm-offsets.c
@@ -0,0 +1,61 @@
+/*
+ * offset.c: Calculate pt_regs and task_struct offsets.
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/ptrace.h>
+#include <linux/stddef.h>
+#include <linux/kbuild.h>
+
+void output_ptreg_defines(void)
+{
+ COMMENT("MIPS pt_regs offsets.");
+ OFFSET(PT_R0, pt_regs, regs[0]);
+ OFFSET(PT_R1, pt_regs, regs[1]);
+ OFFSET(PT_R2, pt_regs, regs[2]);
+ OFFSET(PT_R3, pt_regs, regs[3]);
+ OFFSET(PT_R4, pt_regs, regs[4]);
+ OFFSET(PT_R5, pt_regs, regs[5]);
+ OFFSET(PT_R6, pt_regs, regs[6]);
+ OFFSET(PT_R7, pt_regs, regs[7]);
+ OFFSET(PT_R8, pt_regs, regs[8]);
+ OFFSET(PT_R9, pt_regs, regs[9]);
+ OFFSET(PT_R10, pt_regs, regs[10]);
+ OFFSET(PT_R11, pt_regs, regs[11]);
+ OFFSET(PT_R12, pt_regs, regs[12]);
+ OFFSET(PT_R13, pt_regs, regs[13]);
+ OFFSET(PT_R14, pt_regs, regs[14]);
+ OFFSET(PT_R15, pt_regs, regs[15]);
+ OFFSET(PT_R16, pt_regs, regs[16]);
+ OFFSET(PT_R17, pt_regs, regs[17]);
+ OFFSET(PT_R18, pt_regs, regs[18]);
+ OFFSET(PT_R19, pt_regs, regs[19]);
+ OFFSET(PT_R20, pt_regs, regs[20]);
+ OFFSET(PT_R21, pt_regs, regs[21]);
+ OFFSET(PT_R22, pt_regs, regs[22]);
+ OFFSET(PT_R23, pt_regs, regs[23]);
+ OFFSET(PT_R24, pt_regs, regs[24]);
+ OFFSET(PT_R25, pt_regs, regs[25]);
+ OFFSET(PT_R26, pt_regs, regs[26]);
+ OFFSET(PT_R27, pt_regs, regs[27]);
+ OFFSET(PT_R28, pt_regs, regs[28]);
+ OFFSET(PT_R29, pt_regs, regs[29]);
+ OFFSET(PT_R30, pt_regs, regs[30]);
+ OFFSET(PT_R31, pt_regs, regs[31]);
+ OFFSET(PT_LO, pt_regs, lo);
+ OFFSET(PT_HI, pt_regs, hi);
+ OFFSET(PT_EPC, pt_regs, cp0_epc);
+ OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
+ OFFSET(PT_STATUS, pt_regs, cp0_status);
+ OFFSET(PT_CAUSE, pt_regs, cp0_cause);
+ DEFINE(PT_SIZE, sizeof(struct pt_regs));
+ BLANK();
+}
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 0c6a4ab..be87762 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -42,7 +42,7 @@
/* adjust sp by 4K to be safe */
sp -= 4096;
- lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp);
+ lmb_reserve(lmb, sp, gd->ram_top - sp);
}
static void linux_cmdline_init(void)
@@ -253,7 +253,6 @@
#endif
}
-#ifdef CONFIG_ARCH_FIXUP_FDT
int arch_fixup_fdt(void *blob)
{
#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
@@ -265,7 +264,6 @@
return 0;
#endif
}
-#endif
static int boot_setup_fdt(bootm_headers_t *images)
{
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index db81953..bd14ba6 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -7,34 +7,85 @@
#include <common.h>
#include <asm/cacheops.h>
+#include <asm/cm.h>
#include <asm/mipsregs.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+static void probe_l2(void)
+{
+#ifdef CONFIG_MIPS_L2_CACHE
+ unsigned long conf2, sl;
+ bool l2c = false;
+
+ if (!(read_c0_config1() & MIPS_CONF_M))
+ return;
+
+ conf2 = read_c0_config2();
+
+ if (__mips_isa_rev >= 6) {
+ l2c = conf2 & MIPS_CONF_M;
+ if (l2c)
+ l2c = read_c0_config3() & MIPS_CONF_M;
+ if (l2c)
+ l2c = read_c0_config4() & MIPS_CONF_M;
+ if (l2c)
+ l2c = read_c0_config5() & MIPS_CONF5_L2C;
+ }
+
+ if (l2c && config_enabled(CONFIG_MIPS_CM)) {
+ gd->arch.l2_line_size = mips_cm_l2_line_size();
+ } else if (l2c) {
+ /* We don't know how to retrieve L2 config on this system */
+ BUG();
+ } else {
+ sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
+ gd->arch.l2_line_size = sl ? (2 << sl) : 0;
+ }
+#endif
+}
+
+void mips_cache_probe(void)
+{
+#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
+ unsigned long conf1, il, dl;
+
+ conf1 = read_c0_config1();
+
+ il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
+ dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
+
+ gd->arch.l1i_line_size = il ? (2 << il) : 0;
+ gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
+#endif
+ probe_l2();
+}
+
static inline unsigned long icache_line_size(void)
{
- unsigned long conf1, il;
-
- if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
- return CONFIG_SYS_ICACHE_LINE_SIZE;
-
- conf1 = read_c0_config1();
- il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
- if (!il)
- return 0;
- return 2 << il;
+#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
+ return gd->arch.l1i_line_size;
+#else
+ return CONFIG_SYS_ICACHE_LINE_SIZE;
+#endif
}
static inline unsigned long dcache_line_size(void)
{
- unsigned long conf1, dl;
+#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
+ return gd->arch.l1d_line_size;
+#else
+ return CONFIG_SYS_DCACHE_LINE_SIZE;
+#endif
+}
- if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
- return CONFIG_SYS_DCACHE_LINE_SIZE;
-
- conf1 = read_c0_config1();
- dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
- if (!dl)
- return 0;
- return 2 << dl;
+static inline unsigned long scache_line_size(void)
+{
+#ifdef CONFIG_MIPS_L2_CACHE
+ return gd->arch.l2_line_size;
+#else
+ return 0;
+#endif
}
#define cache_loop(start, end, lsize, ops...) do { \
@@ -53,12 +104,13 @@
{
unsigned long ilsize = icache_line_size();
unsigned long dlsize = dcache_line_size();
+ unsigned long slsize = scache_line_size();
/* aend will be miscalculated when size is zero, so we return here */
if (size == 0)
return;
- if (ilsize == dlsize) {
+ if ((ilsize == dlsize) && !slsize) {
/* flush I-cache & D-cache simultaneously */
cache_loop(start_addr, start_addr + size, ilsize,
HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
@@ -68,6 +120,11 @@
/* flush D-cache */
cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
+ /* flush L2 cache */
+ if (slsize)
+ cache_loop(start_addr, start_addr + size, slsize,
+ HIT_WRITEBACK_INV_SD);
+
/* flush I-cache */
cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
}
@@ -75,21 +132,31 @@
void flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
+ unsigned long slsize = scache_line_size();
/* aend will be miscalculated when size is zero, so we return here */
if (start_addr == stop)
return;
cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
+
+ /* flush L2 cache */
+ if (slsize)
+ cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
+ unsigned long slsize = scache_line_size();
/* aend will be miscalculated when size is zero, so we return here */
if (start_addr == stop)
return;
+ /* invalidate L2 cache */
+ if (slsize)
+ cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
+
cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
}
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index bc8ab27..698a5af 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -13,6 +13,7 @@
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
+#include <asm/cm.h>
#ifndef CONFIG_SYS_MIPS_CACHE_MODE
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
@@ -95,22 +96,147 @@
* with good parity is available. This routine will initialise an area of
* memory starting at location zero to be used as a source of parity.
*
+ * Note that this function does not follow the standard calling convention &
+ * may clobber typically callee-saved registers.
+ *
* RETURNS: N/A
*
*/
+#define R_RETURN s0
+#define R_IC_SIZE s1
+#define R_IC_LINE s2
+#define R_DC_SIZE s3
+#define R_DC_LINE s4
+#define R_L2_SIZE s5
+#define R_L2_LINE s6
+#define R_L2_BYPASSED s7
+#define R_L2_L2C t8
LEAF(mips_cache_reset)
-#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
- li t2, CONFIG_SYS_ICACHE_SIZE
- li t8, CONFIG_SYS_ICACHE_LINE_SIZE
-#else
- l1_info t2, t8, MIPS_CONF1_IA_SHF
+ move R_RETURN, ra
+
+#ifdef CONFIG_MIPS_L2_CACHE
+ /*
+ * For there to be an L2 present, Config2 must be present. If it isn't
+ * then we proceed knowing there's no L2 cache.
+ */
+ move R_L2_SIZE, zero
+ move R_L2_LINE, zero
+ move R_L2_BYPASSED, zero
+ move R_L2_L2C, zero
+ mfc0 t0, CP0_CONFIG, 1
+ bgez t0, l2_probe_done
+
+ /*
+ * From MIPSr6 onwards the L2 cache configuration might not be reported
+ * by Config2. The Config5.L2C bit indicates whether this is the case,
+ * and if it is then we need knowledge of where else to look. For cores
+ * from Imagination Technologies this is a CM GCR.
+ */
+# if __mips_isa_rev >= 6
+ /* Check that Config5 exists */
+ mfc0 t0, CP0_CONFIG, 2
+ bgez t0, l2_probe_cop0
+ mfc0 t0, CP0_CONFIG, 3
+ bgez t0, l2_probe_cop0
+ mfc0 t0, CP0_CONFIG, 4
+ bgez t0, l2_probe_cop0
+
+ /* Check Config5.L2C is set */
+ mfc0 t0, CP0_CONFIG, 5
+ and R_L2_L2C, t0, MIPS_CONF5_L2C
+ beqz R_L2_L2C, l2_probe_cop0
+
+ /* Config5.L2C is set */
+# ifdef CONFIG_MIPS_CM
+ /* The CM will provide L2 configuration */
+ PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
+ lw t1, GCR_L2_CONFIG(t0)
+ bgez t1, l2_probe_done
+
+ ext R_L2_LINE, t1, \
+ GCR_L2_CONFIG_LINESZ_SHIFT, GCR_L2_CONFIG_LINESZ_BITS
+ beqz R_L2_LINE, l2_probe_done
+ li t2, 2
+ sllv R_L2_LINE, t2, R_L2_LINE
+
+ ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS
+ addiu t2, t2, 1
+ mul R_L2_SIZE, R_L2_LINE, t2
+
+ ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS
+ sllv R_L2_SIZE, R_L2_SIZE, t2
+ li t2, 64
+ mul R_L2_SIZE, R_L2_SIZE, t2
+
+ /* Bypass the L2 cache so that we can init the L1s early */
+ or t1, t1, GCR_L2_CONFIG_BYPASS
+ sw t1, GCR_L2_CONFIG(t0)
+ sync
+ li R_L2_BYPASSED, 1
+
+ /* Zero the L2 tag registers */
+ sw zero, GCR_L2_TAG_ADDR(t0)
+ sw zero, GCR_L2_TAG_ADDR_UPPER(t0)
+ sw zero, GCR_L2_TAG_STATE(t0)
+ sw zero, GCR_L2_TAG_STATE_UPPER(t0)
+ sw zero, GCR_L2_DATA(t0)
+ sw zero, GCR_L2_DATA_UPPER(t0)
+ sync
+# else
+ /* We don't know how to retrieve L2 configuration on this system */
+# endif
+ b l2_probe_done
+# endif
+
+ /*
+ * For pre-r6 systems, or r6 systems with Config5.L2C==0, probe the L2
+ * cache configuration from the cop0 Config2 register.
+ */
+l2_probe_cop0:
+ mfc0 t0, CP0_CONFIG, 2
+
+ srl R_L2_LINE, t0, MIPS_CONF2_SL_SHF
+ andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
+ beqz R_L2_LINE, l2_probe_done
+ li t1, 2
+ sllv R_L2_LINE, t1, R_L2_LINE
+
+ srl t1, t0, MIPS_CONF2_SA_SHF
+ andi t1, t1, MIPS_CONF2_SA >> MIPS_CONF2_SA_SHF
+ addiu t1, t1, 1
+ mul R_L2_SIZE, R_L2_LINE, t1
+
+ srl t1, t0, MIPS_CONF2_SS_SHF
+ andi t1, t1, MIPS_CONF2_SS >> MIPS_CONF2_SS_SHF
+ sllv R_L2_SIZE, R_L2_SIZE, t1
+ li t1, 64
+ mul R_L2_SIZE, R_L2_SIZE, t1
+
+ /* Attempt to bypass the L2 so that we can init the L1s early */
+ or t0, t0, MIPS_CONF2_L2B
+ mtc0 t0, CP0_CONFIG, 2
+ ehb
+ mfc0 t0, CP0_CONFIG, 2
+ and R_L2_BYPASSED, t0, MIPS_CONF2_L2B
+
+ /* Zero the L2 tag registers */
+ mtc0 zero, CP0_TAGLO, 4
+ ehb
+l2_probe_done:
#endif
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
- li t3, CONFIG_SYS_DCACHE_SIZE
- li t9, CONFIG_SYS_DCACHE_LINE_SIZE
+ li R_IC_SIZE, CONFIG_SYS_ICACHE_SIZE
+ li R_IC_LINE, CONFIG_SYS_ICACHE_LINE_SIZE
#else
- l1_info t3, t9, MIPS_CONF1_DA_SHF
+ l1_info R_IC_SIZE, R_IC_LINE, MIPS_CONF1_IA_SHF
+#endif
+
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
+ li R_DC_SIZE, CONFIG_SYS_DCACHE_SIZE
+ li R_DC_LINE, CONFIG_SYS_DCACHE_LINE_SIZE
+#else
+ l1_info R_DC_SIZE, R_DC_LINE, MIPS_CONF1_DA_SHF
#endif
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
@@ -123,9 +249,9 @@
li v0, CONFIG_SYS_DCACHE_SIZE
#endif
#else
- move v0, t2
- sltu t1, t2, t3
- movn v0, t3, t1
+ move v0, R_IC_SIZE
+ sltu t1, R_IC_SIZE, R_DC_SIZE
+ movn v0, R_DC_SIZE, t1
#endif
/*
* Now clear that much memory starting from zero.
@@ -138,13 +264,36 @@
#endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
+#ifdef CONFIG_MIPS_L2_CACHE
+ /*
+ * If the L2 is bypassed, init the L1 first so that we can execute the
+ * rest of the cache initialisation using the L1 instruction cache.
+ */
+ bnez R_L2_BYPASSED, l1_init
+
+l2_init:
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, R_L2_SIZE
+1: cache INDEX_STORE_TAG_SD, 0(t0)
+ PTR_ADDU t0, t0, R_L2_LINE
+ bne t0, t1, 1b
+
+ /*
+ * If the L2 was bypassed then we already initialised the L1s before
+ * the L2, so we are now done.
+ */
+ bnez R_L2_BYPASSED, l2_unbypass
+#endif
+
/*
* The TagLo registers used depend upon the CPU implementation, but the
* architecture requires that it is safe for software to write to both
* TagLo selects 0 & 2 covering supported cases.
*/
+l1_init:
mtc0 zero, CP0_TAGLO
mtc0 zero, CP0_TAGLO, 2
+ ehb
/*
* The caches are probably in an indeterminate state, so we force good
@@ -158,40 +307,122 @@
/*
* Initialize the I-cache first,
*/
- blez t2, 1f
+ blez R_IC_SIZE, 1f
PTR_LI t0, INDEX_BASE
- PTR_ADDU t1, t0, t2
+ PTR_ADDU t1, t0, R_IC_SIZE
/* clear tag to invalidate */
- cache_loop t0, t1, t8, INDEX_STORE_TAG_I
+ cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
- cache_loop t0, t1, t8, FILL
+ cache_loop t0, t1, R_IC_LINE, FILL
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
- cache_loop t0, t1, t8, INDEX_STORE_TAG_I
+ cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
#endif
+ /* Enable use of the I-cache by setting Config.K0 */
+ sync
+ mfc0 t0, CP0_CONFIG
+ li t1, CONFIG_SYS_MIPS_CACHE_MODE
+#if __mips_isa_rev >= 2
+ ins t0, t1, 0, 3
+#else
+ ori t0, t0, CONF_CM_CMASK
+ xori t0, t0, CONF_CM_CMASK
+ or t0, t0, t1
+#endif
+ mtc0 t0, CP0_CONFIG
+
/*
* then initialize D-cache.
*/
-1: blez t3, 3f
+1: blez R_DC_SIZE, 3f
PTR_LI t0, INDEX_BASE
- PTR_ADDU t1, t0, t3
+ PTR_ADDU t1, t0, R_DC_SIZE
/* clear all tags */
- cache_loop t0, t1, t9, INDEX_STORE_TAG_D
+ cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* load from each line (in cached space) */
PTR_LI t0, INDEX_BASE
2: LONG_L zero, 0(t0)
- PTR_ADDU t0, t9
+ PTR_ADDU t0, R_DC_LINE
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
- cache_loop t0, t1, t9, INDEX_STORE_TAG_D
+ cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
+#endif
+3:
+
+#ifdef CONFIG_MIPS_L2_CACHE
+ /* If the L2 isn't bypassed then we're done */
+ beqz R_L2_BYPASSED, return
+
+ /* The L2 is bypassed - go initialise it */
+ b l2_init
+
+l2_unbypass:
+# if __mips_isa_rev >= 6
+ beqz R_L2_L2C, 1f
+
+ li t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
+ lw t1, GCR_L2_CONFIG(t0)
+ xor t1, t1, GCR_L2_CONFIG_BYPASS
+ sw t1, GCR_L2_CONFIG(t0)
+ sync
+ ehb
+ b 2f
+# endif
+1: mfc0 t0, CP0_CONFIG, 2
+ xor t0, t0, MIPS_CONF2_L2B
+ mtc0 t0, CP0_CONFIG, 2
+ ehb
+
+2:
+# ifdef CONFIG_MIPS_CM
+ /* Config3 must exist for a CM to be present */
+ mfc0 t0, CP0_CONFIG, 1
+ bgez t0, 2f
+ mfc0 t0, CP0_CONFIG, 2
+ bgez t0, 2f
+
+ /* Check Config3.CMGCR to determine CM presence */
+ mfc0 t0, CP0_CONFIG, 3
+ and t0, t0, MIPS_CONF3_CMGCR
+ beqz t0, 2f
+
+ /* Change Config.K0 to a coherent CCA */
+ mfc0 t0, CP0_CONFIG
+ li t1, CONF_CM_CACHABLE_COW
+#if __mips_isa_rev >= 2
+ ins t0, t1, 0, 3
+#else
+ ori t0, t0, CONF_CM_CMASK
+ xori t0, t0, CONF_CM_CMASK
+ or t0, t0, t1
+#endif
+ mtc0 t0, CP0_CONFIG
+
+ /*
+ * Join the coherent domain such that the caches of this core are kept
+ * coherent with those of other cores.
+ */
+ PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
+ lw t1, GCR_REV(t0)
+ li t2, GCR_REV_CM3
+ li t3, GCR_Cx_COHERENCE_EN
+ bge t1, t2, 1f
+ li t3, GCR_Cx_COHERENCE_DOM_EN
+1: sw t3, GCR_Cx_COHERENCE(t0)
+ ehb
+2:
+# endif
#endif
-3: jr ra
+return:
+ /* Ensure all cache operations complete before returning */
+ sync
+ jr ra
END(mips_cache_reset)
/*
diff --git a/arch/mips/lib/genex.S b/arch/mips/lib/genex.S
new file mode 100644
index 0000000..2d6d7b0
--- /dev/null
+++ b/arch/mips/lib/genex.S
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2002, 2007 Maciej W. Rozycki
+ * Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+
+#define STATMASK 0x1f
+
+ .set noreorder
+
+ /*
+ * Macros copied and adapted from Linux MIPS
+ */
+ .macro SAVE_AT
+ .set push
+ .set noat
+ LONG_S $1, PT_R1(sp)
+ .set pop
+ .endm
+
+ .macro SAVE_TEMP
+#if __mips_isa_rev < 6
+ mfhi v1
+#endif
+#ifdef CONFIG_32BIT
+ LONG_S $8, PT_R8(sp)
+ LONG_S $9, PT_R9(sp)
+#endif
+ LONG_S $10, PT_R10(sp)
+ LONG_S $11, PT_R11(sp)
+ LONG_S $12, PT_R12(sp)
+#if __mips_isa_rev < 6
+ LONG_S v1, PT_HI(sp)
+ mflo v1
+#endif
+ LONG_S $13, PT_R13(sp)
+ LONG_S $14, PT_R14(sp)
+ LONG_S $15, PT_R15(sp)
+ LONG_S $24, PT_R24(sp)
+#if __mips_isa_rev < 6
+ LONG_S v1, PT_LO(sp)
+#endif
+ .endm
+
+ .macro SAVE_STATIC
+ LONG_S $16, PT_R16(sp)
+ LONG_S $17, PT_R17(sp)
+ LONG_S $18, PT_R18(sp)
+ LONG_S $19, PT_R19(sp)
+ LONG_S $20, PT_R20(sp)
+ LONG_S $21, PT_R21(sp)
+ LONG_S $22, PT_R22(sp)
+ LONG_S $23, PT_R23(sp)
+ LONG_S $30, PT_R30(sp)
+ .endm
+
+ .macro SAVE_SOME
+ .set push
+ .set noat
+ PTR_SUBU k1, sp, PT_SIZE
+ LONG_S sp, PT_R29(k1)
+ move sp, k1
+
+ LONG_S $3, PT_R3(sp)
+ LONG_S $0, PT_R0(sp)
+ mfc0 v1, CP0_STATUS
+ LONG_S $2, PT_R2(sp)
+ LONG_S v1, PT_STATUS(sp)
+ LONG_S $4, PT_R4(sp)
+ mfc0 v1, CP0_CAUSE
+ LONG_S $5, PT_R5(sp)
+ LONG_S v1, PT_CAUSE(sp)
+ LONG_S $6, PT_R6(sp)
+ MFC0 v1, CP0_EPC
+ LONG_S $7, PT_R7(sp)
+#ifdef CONFIG_64BIT
+ LONG_S $8, PT_R8(sp)
+ LONG_S $9, PT_R9(sp)
+#endif
+ LONG_S v1, PT_EPC(sp)
+ LONG_S $25, PT_R25(sp)
+ LONG_S $28, PT_R28(sp)
+ LONG_S $31, PT_R31(sp)
+ .set pop
+ .endm
+
+ .macro RESTORE_AT
+ .set push
+ .set noat
+ LONG_L $1, PT_R1(sp)
+ .set pop
+ .endm
+
+ .macro RESTORE_TEMP
+#if __mips_isa_rev < 6
+ LONG_L $24, PT_LO(sp)
+ mtlo $24
+ LONG_L $24, PT_HI(sp)
+ mthi $24
+#endif
+#ifdef CONFIG_32BIT
+ LONG_L $8, PT_R8(sp)
+ LONG_L $9, PT_R9(sp)
+#endif
+ LONG_L $10, PT_R10(sp)
+ LONG_L $11, PT_R11(sp)
+ LONG_L $12, PT_R12(sp)
+ LONG_L $13, PT_R13(sp)
+ LONG_L $14, PT_R14(sp)
+ LONG_L $15, PT_R15(sp)
+ LONG_L $24, PT_R24(sp)
+ .endm
+
+ .macro RESTORE_STATIC
+ LONG_L $16, PT_R16(sp)
+ LONG_L $17, PT_R17(sp)
+ LONG_L $18, PT_R18(sp)
+ LONG_L $19, PT_R19(sp)
+ LONG_L $20, PT_R20(sp)
+ LONG_L $21, PT_R21(sp)
+ LONG_L $22, PT_R22(sp)
+ LONG_L $23, PT_R23(sp)
+ LONG_L $30, PT_R30(sp)
+ .endm
+
+ .macro RESTORE_SOME
+ .set push
+ .set reorder
+ .set noat
+ mfc0 a0, CP0_STATUS
+ ori a0, STATMASK
+ xori a0, STATMASK
+ mtc0 a0, CP0_STATUS
+ li v1, ST0_CU1 | ST0_FR | ST0_IM
+ and a0, v1
+ LONG_L v0, PT_STATUS(sp)
+ nor v1, $0, v1
+ and v0, v1
+ or v0, a0
+ mtc0 v0, CP0_STATUS
+ LONG_L v1, PT_EPC(sp)
+ MTC0 v1, CP0_EPC
+ LONG_L $31, PT_R31(sp)
+ LONG_L $28, PT_R28(sp)
+ LONG_L $25, PT_R25(sp)
+#ifdef CONFIG_64BIT
+ LONG_L $8, PT_R8(sp)
+ LONG_L $9, PT_R9(sp)
+#endif
+ LONG_L $7, PT_R7(sp)
+ LONG_L $6, PT_R6(sp)
+ LONG_L $5, PT_R5(sp)
+ LONG_L $4, PT_R4(sp)
+ LONG_L $3, PT_R3(sp)
+ LONG_L $2, PT_R2(sp)
+ .set pop
+ .endm
+
+ .macro RESTORE_SP
+ LONG_L sp, PT_R29(sp)
+ .endm
+
+NESTED(except_vec3_generic, 0, sp)
+ PTR_LA k1, handle_reserved
+ jr k1
+ nop
+ END(except_vec3_generic)
+
+NESTED(except_vec_ejtag_debug, 0, sp)
+ PTR_LA k1, handle_ejtag_debug
+ jr k1
+ nop
+ END(except_vec_ejtag_debug)
+
+NESTED(handle_reserved, PT_SIZE, sp)
+ SAVE_SOME
+ SAVE_AT
+ SAVE_TEMP
+ SAVE_STATIC
+
+ PTR_LA t9, do_reserved
+ jr t9
+ move a0, sp
+ END(handle_reserved)
+
+NESTED(handle_ejtag_debug, PT_SIZE, sp)
+ .set push
+ .set noat
+ MTC0 k1, CP0_DESAVE
+
+ /* Check for SDBBP */
+ MFC0 k1, CP0_DEBUG
+ sll k1, k1, 30
+ bgez k1, ejtag_return
+ nop
+
+ SAVE_SOME
+ SAVE_AT
+ SAVE_TEMP
+ SAVE_STATIC
+
+ PTR_LA t9, do_ejtag_debug
+ jalr t9
+ move a0, sp
+
+ RESTORE_TEMP
+ RESTORE_STATIC
+ RESTORE_AT
+ RESTORE_SOME
+ RESTORE_SP
+
+ejtag_return:
+ MFC0 k1, CP0_DESAVE
+ deret
+ .set pop
+ END(handle_ejtag_debug)
diff --git a/arch/mips/lib/stack.c b/arch/mips/lib/stack.c
new file mode 100644
index 0000000..c80f5fe
--- /dev/null
+++ b/arch/mips/lib/stack.c
@@ -0,0 +1,19 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_reserve_stacks(void)
+{
+ /* reserve space for exception vector table */
+ gd->start_addr_sp -= 0x500;
+ gd->start_addr_sp &= ~0xFFF;
+ gd->irq_sp = gd->start_addr_sp;
+ debug("Reserving %d Bytes for exception vector at: %08lx\n",
+ 0x500, gd->start_addr_sp);
+
+ return 0;
+}
diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
new file mode 100644
index 0000000..18622c2
--- /dev/null
+++ b/arch/mips/lib/traps.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
+ * Copyright (C) 1995, 1996 Paul M. Antoine
+ * Copyright (C) 1998 Ulf Carlsson
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
+ * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
+ * Copyright (C) 2014, Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void show_regs(const struct pt_regs *regs)
+{
+ const int field = 2 * sizeof(unsigned long);
+ unsigned int cause = regs->cp0_cause;
+ unsigned int exccode;
+ int i;
+
+ /*
+ * Saved main processor registers
+ */
+ for (i = 0; i < 32; ) {
+ if ((i % 4) == 0)
+ printf("$%2d :", i);
+ if (i == 0)
+ printf(" %0*lx", field, 0UL);
+ else if (i == 26 || i == 27)
+ printf(" %*s", field, "");
+ else
+ printf(" %0*lx", field, regs->regs[i]);
+
+ i++;
+ if ((i % 4) == 0)
+ puts("\n");
+ }
+
+ printf("Hi : %0*lx\n", field, regs->hi);
+ printf("Lo : %0*lx\n", field, regs->lo);
+
+ /*
+ * Saved cp0 registers
+ */
+ printf("epc : %0*lx (text %0*lx)\n", field, regs->cp0_epc,
+ field, regs->cp0_epc - gd->reloc_off);
+ printf("ra : %0*lx (text %0*lx)\n", field, regs->regs[31],
+ field, regs->regs[31] - gd->reloc_off);
+
+ printf("Status: %08x\n", (uint32_t) regs->cp0_status);
+
+ exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
+ printf("Cause : %08x (ExcCode %02x)\n", cause, exccode);
+
+ if (1 <= exccode && exccode <= 5)
+ printf("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
+
+ printf("PrId : %08x\n", read_c0_prid());
+}
+
+void do_reserved(const struct pt_regs *regs)
+{
+ puts("\nOoops:\n");
+ show_regs(regs);
+ hang();
+}
+
+void do_ejtag_debug(const struct pt_regs *regs)
+{
+ const int field = 2 * sizeof(unsigned long);
+ unsigned long depc;
+ unsigned int debug;
+
+ depc = read_c0_depc();
+ debug = read_c0_debug();
+
+ printf("SDBBP EJTAG debug exception: c0_depc = %0*lx, DEBUG = %08x\n",
+ field, depc, debug);
+}
+
+static void set_handler(unsigned long offset, void *addr, unsigned long size)
+{
+ unsigned long ebase = gd->irq_sp;
+
+ memcpy((void *)(ebase + offset), addr, size);
+ flush_cache(ebase + offset, size);
+}
+
+void trap_init(ulong reloc_addr)
+{
+ unsigned long ebase = gd->irq_sp;
+
+ set_handler(0x180, &except_vec3_generic, 0x80);
+ set_handler(0x280, &except_vec_ejtag_debug, 0x80);
+
+ write_c0_ebase(ebase);
+ clear_c0_status(ST0_BEV);
+ execution_hazard_barrier();
+}
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 7d483aa..d982b0f 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -9,6 +9,7 @@
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select ROM_EXCEPTION_VECTORS
select MIPS_TUNE_24KC
help
This supports QCA/Atheros ar933x family SOCs.
@@ -27,6 +28,7 @@
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select ROM_EXCEPTION_VECTORS
select MIPS_TUNE_24KC
help
This supports QCA/Atheros qca953x family SOCs.
diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
index 5756a06..4ef5092 100644
--- a/arch/mips/mach-ath79/cpu.c
+++ b/arch/mips/mach-ath79/cpu.c
@@ -46,7 +46,7 @@
{ATH79_SOC_QCA9561, "9561", REV_ID_MAJOR_QCA9561, 0},
};
-int arch_cpu_init(void)
+int mach_cpu_init(void)
{
void __iomem *base;
enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 073a179..0593ec4 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -5,7 +5,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
diff --git a/arch/mips/mach-au1x00/au1x00_usb_ohci.c b/arch/mips/mach-au1x00/au1x00_usb_ohci.c
index 42484e5..088e612 100644
--- a/arch/mips/mach-au1x00/au1x00_usb_ohci.c
+++ b/arch/mips/mach-au1x00/au1x00_usb_ohci.c
@@ -671,7 +671,8 @@
__u32 info = 0;
unsigned int toggle = 0;
- /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+ /* OHCI handles the DATA-toggles itself, we just use the
+ USB-toggle bits for resetting */
if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
toggle = TD_T_TOGGLE;
} else {
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
index 2e38bb7..8fad4cf 100644
--- a/arch/mips/mach-pic32/Kconfig
+++ b/arch/mips/mach-pic32/Kconfig
@@ -14,6 +14,7 @@
select SUPPORTS_CPU_MIPS32_R2
select MIPS_L1_CACHE_SHIFT_4
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select ROM_EXCEPTION_VECTORS
help
This supports Microchip PIC32MZ[DA] family of microcontrollers.
diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
index 5ac9f90..ca76641 100644
--- a/arch/nds32/config.mk
+++ b/arch/nds32/config.mk
@@ -19,4 +19,4 @@
PLATFORM_RELFLAGS += -gdwarf-2
PLATFORM_CPPFLAGS += -D__nds32__ -G0 -ffixed-10 -fpie
-LDFLAGS_u-boot = --gc-sections --relax
+LDFLAGS_u-boot = --gc-sections --relax -pie
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
index 1a94868..abdd340 100644
--- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -6,6 +6,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+.pic
+
.text
#include <common.h>
@@ -248,16 +250,11 @@
*/
li $r5, AHBC_BSR6_A
lwi $r8, [$r5]
- li $r4, 0xfff00000
+ li $r4, 0xfff00000 /* r4 = bank6 base */
and $r4, $r4, $r8
-
- li $r5, 0x0
- la $r1, relo_base /* get $pc or $lp */
- sub $r2, $r0, $r1
- sethi $r6, hi20(_end)
- ori $r6, $r6, lo12(_end)
- add $r6, $r6, $r2
+ la $r5, _start@GOTOFF
+ la $r6, _end@GOTOFF
1:
lwi.p $r7, [$r5], #4
swi.p $r7, [$r4], #4
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index 8b7f8f4..7b2b637 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+.pic
+
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
@@ -116,6 +118,18 @@
*/
reset:
+
+/*
+ * gp = ~0 for burn mode
+ * = ~load_address for load mode
+ */
+reset_gp:
+ .relax_hint 0
+ sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
+ .relax_hint 0
+ ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
+ add5.pc $gp
+
set_ivb:
li $r0, 0x0
@@ -124,20 +138,31 @@
/* set IVIC, vector size: 4 bytes, base: 0x0 */
mtsr $r0, $ivb
-load_lli:
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- jal load_lowlevel_init
- jral $p0
+ jal lowlevel_init
+/*
+ * gp = ~VMA for burn mode
+ * = ~load_address for load mode
+ */
+update_gp:
+ .relax_hint 0
+ sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
+ .relax_hint 0
+ ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
+ add5.pc $gp
#endif
/*
+ * do critical initializations first (shall be in short time)
+ * do self_relocation ASAP.
+ */
+
+/*
* Set the N1213 (Whitiger) core to superuser mode
* According to spec, it is already when reset
*/
-turnoff_wtdog:
#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
- jal load_turnoff_watchdog
- jral $p0
+ jal turnoff_watchdog
#endif
/*
@@ -145,7 +170,7 @@
* not when booting from ram
*/
#ifdef CONFIG_INIT_CRITICAL
- bal cpu_init_crit ! Do CPU critical regs init
+ jal cpu_init_crit ! Do CPU critical regs init
#endif
/*
@@ -174,6 +199,11 @@
* after relocating the monitor code.
*
*/
+
+/*
+ * gp = ~RAM_SIZE - TEXT_SIZE for burn/load mode
+ */
+
.globl relocate_code
relocate_code:
move $r4, $r0 /* save addr_sp */
@@ -184,49 +214,43 @@
stack_setup:
move $sp, $r4
- la $r0, _start
-
+ la $r0, _start@GOTOFF
beq $r0, $r6, clear_bss /* skip relocation */
- move $r1, $r6 /* r1 <- scratch for copy_loop */
- la $r3, __bss_start
- sub $r3, $r3, $r0 /* r3 <- __bss_start_ofs */
- add $r2, $r0, $r3 /* r2 <- source end address */
+ la $r1, _end@GOTOFF
+ move $r2, $r6 /* r2 <- scratch for copy_loop */
copy_loop:
lwi.p $r7, [$r0], #4
- swi.p $r7, [$r1], #4
- blt $r0, $r2, copy_loop
+ swi.p $r7, [$r2], #4
+ blt $r0, $r1, copy_loop
/*
* fix relocations related issues
*/
fix_relocations:
- l.w $r0, _TEXT_BASE /* r0 <- Text base */
- sub $r9, $r6, $r0 /* r9 <- relocation offset */
+ l.w $r0, _TEXT_BASE@GOTOFF /* r0 <- Text base */
+ sub $r9, $r6, $r0 /* r9 <- relocation offset */
-fix_got:
-/*
- * Now we want to update GOT.
- *
- * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
- * generated by GNU ld. Skip these reserved entries from relocation.
- */
- la $r2, __got_start /* r2 <- rel __got_start in FLASH */
- add $r2, $r2, $r9 /* r2 <- rel __got_start in RAM */
- la $r3, __got_end /* r3 <- rel __got_end in FLASH */
- add $r3, $r3, $r9 /* r3 <- rel __got_end in RAM */
- addi $r2, $r2, #8 /* skipping first two entries */
-fix_got_loop:
- lwi $r0, [$r2] /* r0 <- location in FLASH to fix up */
- add $r0, $r0, $r9 /* r0 <- location fix up to RAM */
- swi.p $r0, [$r2], #4 /* r0 <- store fix into .got in RAM */
- blt $r2, $r3, fix_got_loop
+ la $r7, __rel_dyn_start@GOTOFF
+ add $r7, $r7, $r9 /* r2 <- rel __got_start in RAM */
+ la $r8, __rel_dyn_end@GOTOFF
+ add $r8, $r8, $r9 /* r2 <- rel __got_start in RAM */
+ li $r3, #0x2a /* R_NDS32_RELATIVE */
+1:
+ lmw.bim $r0, [$r7], $r2 /* r0,r1,r2 <- adr,type,addend */
+ bne $r1, $r3, 2f
+
+ add $r0, $r0, $r9
+ add $r2, $r2, $r9
+ sw $r2, [$r0]
+2:
+ blt $r7, $r8, 1b
clear_bss:
- la $r0, __bss_start /* r0 <- rel __bss_start in FLASH */
+ la $r0, __bss_start@GOTOFF /* r0 <- rel __bss_start in FLASH */
add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
- la $r1, __bss_end /* r1 <- rel __bss_end in RAM */
+ la $r1, __bss_end@GOTOFF /* r1 <- rel __bss_end in RAM */
add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
li $r2, 0x00000000 /* clear */
@@ -240,7 +264,7 @@
* initialization, now running from RAM.
*/
call_board_init_r:
- la $r0, board_init_r
+ la $r0, board_init_r@GOTOFF
move $lp, $r0 /* offset of board_init_r() */
add $lp, $lp, $r9 /* real address of board_init_r() */
/* setup parameters for board_init_r */
@@ -275,8 +299,8 @@
/* Flush caches and TLB */
/* Invalidate caches */
- bal invalidate_icac
- bal invalidate_dcac
+ jal invalidate_icac
+ jal invalidate_dcac
/* Flush TLB */
mfsr $p0, $MMU_CFG
@@ -299,24 +323,6 @@
2:
ret
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-load_lowlevel_init:
- la $r6, lowlevel_init
- la $r7, load_lli + 4
- sub $p0, $r6, $r7
- add $p0, $p0, $lp
-ret
-#endif
-
-#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
-load_turnoff_watchdog:
- la $r6, turnoff_watchdog
- la $r7, turnoff_wtdog + 4
- sub $p0, $r6, $r7
- add $p0, $p0, $lp
-ret
-#endif
-
/*
* Invalidate I$
*/
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
index b88d742..40db0e6 100644
--- a/arch/nds32/cpu/n1213/u-boot.lds
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -31,25 +31,28 @@
.got : {
__got_start = .;
- *(.got.plt) *(.got)
+ *(.got.plt) *(.got)
__got_end = .;
}
- . = .;
-
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
-
+ /DISCARD/ : { *(.rela.plt*) }
+ .rela.dyn : {
+ __rel_dyn_start = .;
+ *(.rela*)
+ __rel_dyn_end = .;
+ }
_end = .;
.bss : {
__bss_start = .;
*(.bss)
- . = ALIGN(4);
+ . = ALIGN(4);
__bss_end = .;
}
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
index 3d1886e..054cc48 100644
--- a/arch/nds32/include/asm/config.h
+++ b/arch/nds32/include/asm/config.h
@@ -9,6 +9,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#define CONFIG_NEEDS_MANUAL_RELOC
-
#endif
diff --git a/arch/nds32/include/asm/errno.h b/arch/nds32/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/nds32/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/nios2/include/asm/errno.h b/arch/nios2/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/nios2/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/nios2/include/asm/linkage.h b/arch/nios2/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/nios2/include/asm/linkage.h
diff --git a/arch/openrisc/include/asm/errno.h b/arch/openrisc/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/openrisc/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/openrisc/include/asm/linkage.h b/arch/openrisc/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/openrisc/include/asm/linkage.h
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 18451d3..0033c35 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -23,13 +23,20 @@
config MPC83xx
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config MPC85xx
bool "MPC85xx"
select CREATE_ARCH_SYMLINK
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
config MPC86xx
bool "MPC86xx"
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
config 8xx
bool "MPC8xx"
diff --git a/arch/powerpc/cpu/mpc512x/cpu.c b/arch/powerpc/cpu/mpc512x/cpu.c
index 8508e8d..4ee91e1 100644
--- a/arch/powerpc/cpu/mpc512x/cpu.c
+++ b/arch/powerpc/cpu/mpc512x/cpu.c
@@ -95,11 +95,7 @@
*/
unsigned long get_tbclk (void)
{
- ulong tbclk;
-
- tbclk = (gd->bus_clk + 3L) / 4L;
-
- return tbclk;
+ return (gd->bus_clk + 3L) / 4L;
}
diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S
index 6c331d1..dd3066e 100644
--- a/arch/powerpc/cpu/mpc512x/start.S
+++ b/arch/powerpc/cpu/mpc512x/start.S
@@ -15,9 +15,6 @@
#include <asm-offsets.h>
#include <config.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING "MPC512X"
-#endif
#include <version.h>
#define CONFIG_521X 1 /* needed for Linux kernel header files*/
@@ -446,6 +443,11 @@
mfspr r3, PVR
blr
+ .globl get_svr
+get_svr:
+ mfspr r3, SVR
+ blr
+
/*-------------------------------------------------------------------*/
/*
diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
index b7c1b55..cf36954 100644
--- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
+++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
@@ -670,7 +670,8 @@
__u32 info = 0;
unsigned int toggle = 0;
- /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+ /* OHCI handles the DATA-toggles itself, we just use the
+ USB-toggle bits for resetting */
if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
toggle = TD_T_TOGGLE;
} else {
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 3ea62ca..184063c 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -22,6 +22,7 @@
config TARGET_MPC8308RDB
bool "Support MPC8308RDB"
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
@@ -38,6 +39,9 @@
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
+ select SYS_FSL_DDR
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_DDR_BE
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
@@ -66,9 +70,11 @@
config TARGET_HRCON
bool "Support hrcon"
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER
bool "Support strider"
+ select SYS_FSL_ERRATUM_ESDHC111
endchoice
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 3809309..c87f0fd 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -173,11 +173,7 @@
unsigned long get_tbclk(void)
{
- ulong tbclk;
-
- tbclk = (gd->bus_clk + 3L) / 4L;
-
- return tbclk;
+ return (gd->bus_clk + 3L) / 4L;
}
diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c
index 106704d..14406af 100644
--- a/arch/powerpc/cpu/mpc83xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc83xx/qe_io.c
@@ -7,10 +7,10 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "common.h"
-#include "asm/errno.h"
-#include "asm/io.h"
-#include "asm/immap_83xx.h"
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/immap_83xx.h>
#define NUM_OF_PINS 32
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 9bd86d8..0001687 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -14,9 +14,6 @@
#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING "MPC83XX"
-#endif
#include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 9bcbda0..704f65b 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -10,25 +10,37 @@
config TARGET_SBC8548
bool "Support sbc8548"
+ select ARCH_MPC8548
config TARGET_SOCRATES
bool "Support socrates"
+ select ARCH_MPC8544
+
+config TARGET_B4420QDS
+ bool "Support B4420QDS"
+ select ARCH_B4420
+ select SUPPORT_SPL
+ select PHYS_64BIT
config TARGET_B4860QDS
bool "Support B4860QDS"
+ select ARCH_B4860
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_BSC9131RDB
bool "Support BSC9131RDB"
+ select ARCH_BSC9131
select SUPPORT_SPL
config TARGET_BSC9132QDS
bool "Support BSC9132QDS"
+ select ARCH_BSC9132
select SUPPORT_SPL
config TARGET_C29XPCIE
bool "Support C29XPCIE"
+ select ARCH_C29X
select SUPPORT_SPL
select SUPPORT_TPL
select PHYS_64BIT
@@ -36,142 +48,1206 @@
config TARGET_P3041DS
bool "Support P3041DS"
select PHYS_64BIT
+ select ARCH_P3041
config TARGET_P4080DS
bool "Support P4080DS"
select PHYS_64BIT
+ select ARCH_P4080
config TARGET_P5020DS
bool "Support P5020DS"
select PHYS_64BIT
+ select ARCH_P5020
config TARGET_P5040DS
bool "Support P5040DS"
select PHYS_64BIT
+ select ARCH_P5040
config TARGET_MPC8536DS
bool "Support MPC8536DS"
+ select ARCH_MPC8536
+# Use DDR3 controller with DDR2 DIMMs on this board
+ select SYS_FSL_DDRC_GEN3
config TARGET_MPC8540ADS
bool "Support MPC8540ADS"
+ select ARCH_MPC8540
config TARGET_MPC8541CDS
bool "Support MPC8541CDS"
+ select ARCH_MPC8541
config TARGET_MPC8544DS
bool "Support MPC8544DS"
+ select ARCH_MPC8544
config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
+ select ARCH_MPC8548
config TARGET_MPC8555CDS
bool "Support MPC8555CDS"
+ select ARCH_MPC8555
config TARGET_MPC8560ADS
bool "Support MPC8560ADS"
+ select ARCH_MPC8560
config TARGET_MPC8568MDS
bool "Support MPC8568MDS"
+ select ARCH_MPC8568
config TARGET_MPC8569MDS
bool "Support MPC8569MDS"
+ select ARCH_MPC8569
config TARGET_MPC8572DS
bool "Support MPC8572DS"
+ select ARCH_MPC8572
+# Use DDR3 controller with DDR2 DIMMs on this board
+ select SYS_FSL_DDRC_GEN3
-config TARGET_P1010RDB
- bool "Support P1010RDB"
+config TARGET_P1010RDB_PA
+ bool "Support P1010RDB_PA"
+ select ARCH_P1010
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+
+config TARGET_P1010RDB_PB
+ bool "Support P1010RDB_PB"
+ select ARCH_P1010
select SUPPORT_SPL
select SUPPORT_TPL
config TARGET_P1022DS
bool "Support P1022DS"
+ select ARCH_P1022
select SUPPORT_SPL
select SUPPORT_TPL
config TARGET_P1023RDB
bool "Support P1023RDB"
+ select ARCH_P1023
-config TARGET_P1_P2_RDB_PC
- bool "Support p1_p2_rdb_pc"
+config TARGET_P1020MBG
+ bool "Support P1020MBG-PC"
select SUPPORT_SPL
select SUPPORT_TPL
+ select ARCH_P1020
+
+config TARGET_P1020RDB_PC
+ bool "Support P1020RDB-PC"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1020
+
+config TARGET_P1020RDB_PD
+ bool "Support P1020RDB-PD"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1020
+
+config TARGET_P1020UTM
+ bool "Support P1020UTM"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1020
+
+config TARGET_P1021RDB
+ bool "Support P1021RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1021
+
+config TARGET_P1024RDB
+ bool "Support P1024RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1024
+
+config TARGET_P1025RDB
+ bool "Support P1025RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1025
+
+config TARGET_P2020RDB
+ bool "Support P2020RDB-PC"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P2020
config TARGET_P1_TWR
bool "Support p1_twr"
+ select ARCH_P1025
config TARGET_P2041RDB
bool "Support P2041RDB"
+ select ARCH_P2041
select PHYS_64BIT
config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
+ select ARCH_QEMU_E500
select PHYS_64BIT
-config TARGET_T102XQDS
- bool "Support T102xQDS"
+config TARGET_T1024QDS
+ bool "Support T1024QDS"
+ select ARCH_T1024
select SUPPORT_SPL
select PHYS_64BIT
-config TARGET_T102XRDB
- bool "Support T102xRDB"
+config TARGET_T1023RDB
+ bool "Support T1023RDB"
+ select ARCH_T1023
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T1024RDB
+ bool "Support T1024RDB"
+ select ARCH_T1024
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T1040QDS
bool "Support T1040QDS"
+ select ARCH_T1040
select PHYS_64BIT
-config TARGET_T104XRDB
- bool "Support T104xRDB"
+config TARGET_T1040RDB
+ bool "Support T1040RDB"
+ select ARCH_T1040
select SUPPORT_SPL
select PHYS_64BIT
-config TARGET_T208XQDS
- bool "Support T208xQDS"
+config TARGET_T1040D4RDB
+ bool "Support T1040D4RDB"
+ select ARCH_T1040
select SUPPORT_SPL
select PHYS_64BIT
-config TARGET_T208XRDB
- bool "Support T208xRDB"
+config TARGET_T1042RDB
+ bool "Support T1042RDB"
+ select ARCH_T1042
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T1042D4RDB
+ bool "Support T1042D4RDB"
+ select ARCH_T1042
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T1042RDB_PI
+ bool "Support T1042RDB_PI"
+ select ARCH_T1042
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T2080QDS
+ bool "Support T2080QDS"
+ select ARCH_T2080
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T2080RDB
+ bool "Support T2080RDB"
+ select ARCH_T2080
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T2081QDS
+ bool "Support T2081QDS"
+ select ARCH_T2081
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T4160QDS
+ bool "Support T4160QDS"
+ select ARCH_T4160
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T4160RDB
+ bool "Support T4160RDB"
+ select ARCH_T4160
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T4240QDS
bool "Support T4240QDS"
+ select ARCH_T4240
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T4240RDB
bool "Support T4240RDB"
+ select ARCH_T4240
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_CONTROLCENTERD
bool "Support controlcenterd"
+ select ARCH_P1022
config TARGET_KMP204X
bool "Support kmp204x"
+ select ARCH_P2041
select PHYS_64BIT
config TARGET_XPEDITE520X
bool "Support xpedite520x"
+ select ARCH_MPC8548
config TARGET_XPEDITE537X
bool "Support xpedite537x"
+ select ARCH_MPC8572
+# Use DDR3 controller with DDR2 DIMMs on this board
+ select SYS_FSL_DDRC_GEN3
config TARGET_XPEDITE550X
bool "Support xpedite550x"
+ select ARCH_P2020
config TARGET_UCP1020
bool "Support uCP1020"
+ select ARCH_P1020
-config TARGET_CYRUS
- bool "Support Varisys Cyrus"
+config TARGET_CYRUS_P5020
+ bool "Support Varisys Cyrus P5020"
+ select ARCH_P5020
+ select PHYS_64BIT
+
+config TARGET_CYRUS_P5040
+ bool "Support Varisys Cyrus P5040"
+ select ARCH_P5040
select PHYS_64BIT
endchoice
+config ARCH_B4420
+ bool
+ select E500MC
+ select E6500
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006384
+ select SYS_FSL_ERRATUM_A006475
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config ARCH_B4860
+ bool
+ select E500MC
+ select E6500
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006384
+ select SYS_FSL_ERRATUM_A006475
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config ARCH_BSC9131
+ bool
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+
+config ARCH_BSC9132
+ bool
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_46
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_A005434
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_IFC_A002769
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_C29X
+ bool
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_46
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_6
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_MPC8536
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_MPC8540
+ bool
+ select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+
+config ARCH_MPC8541
+ bool
+ select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+
+config ARCH_MPC8544
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_MPC8548
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_NMG_DDR120
+ select SYS_FSL_ERRATUM_NMG_LBC103
+ select SYS_FSL_ERRATUM_NMG_ETSEC129
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_MPC8555
+ bool
+ select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+
+config ARCH_MPC8560
+ bool
+ select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+
+config ARCH_MPC8568
+ bool
+ select FSL_LAW
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+
+config ARCH_MPC8569
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+
+config ARCH_MPC8572
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_DDR_115
+ select SYS_FSL_ERRATUM_DDR111_DDR134
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_P1010
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_IFC_A002769
+ select SYS_FSL_ERRATUM_P1010_A003549
+ select SYS_FSL_ERRATUM_SEC_A003571
+ select SYS_FSL_ERRATUM_IFC_A003399
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_P1011
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_P1020
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_P1021
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_P1022
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_SATA_A001
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_P1023
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+
+config ARCH_P1024
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_P1025
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_P2020
+ bool
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC_A001
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
+
+config ARCH_P2041
+ bool
+ select E500MC
+ select FSL_LAW
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_CPU_A003999
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_NMG_CPU_A011
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+
+config ARCH_P3041
+ bool
+ select E500MC
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A005812
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_CPU_A003999
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_NMG_CPU_A011
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+
+config ARCH_P4080
+ bool
+ select E500MC
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004580
+ select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A005812
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_CPC_A002
+ select SYS_FSL_ERRATUM_CPC_A003
+ select SYS_FSL_ERRATUM_CPU_A003999
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC13
+ select SYS_FSL_ERRATUM_ESDHC135
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_NMG_CPU_A011
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_P4080_ERRATUM_CPU22
+ select SYS_P4080_ERRATUM_PCIE_A003
+ select SYS_P4080_ERRATUM_SERDES8
+ select SYS_P4080_ERRATUM_SERDES9
+ select SYS_P4080_ERRATUM_SERDES_A001
+ select SYS_P4080_ERRATUM_SERDES_A005
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+
+config ARCH_P5020
+ bool
+ select E500MC
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config ARCH_P5040
+ bool
+ select E500MC
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004699
+ select SYS_FSL_ERRATUM_A005812
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config ARCH_QEMU_E500
+ bool
+
+config ARCH_T1023
+ bool
+ select E500MC
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
+
+config ARCH_T1024
+ bool
+ select E500MC
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
+
+config ARCH_T1040
+ bool
+ select E500MC
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008044
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
+
+config ARCH_T1042
+ bool
+ select E500MC
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008044
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
+
+config ARCH_T2080
+ bool
+ select E500MC
+ select E6500
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config ARCH_T2081
+ bool
+ select E500MC
+ select E6500
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config ARCH_T4160
+ bool
+ select E500MC
+ select E6500
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004468
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007798
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config ARCH_T4240
+ bool
+ select E500MC
+ select E6500
+ select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004468
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007798
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config BOOKE
+ bool
+ default y
+
+config E500
+ bool
+ default y
+ help
+ Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
+
+config E500MC
+ bool
+ help
+ Enble PowerPC E500MC core
+
+config E6500
+ bool
+ help
+ Enable PowerPC E6500 core
+
+config FSL_LAW
+ bool
+ help
+ Use Freescale common code for Local Access Window
+
+config SECURE_BOOT
+ bool "Secure Boot"
+ help
+ Enable Freescale Secure Boot feature. Normally selected
+ by defconfig. If unsure, do not change.
+
+config MAX_CPUS
+ int "Maximum number of CPUs permitted for MPC85xx"
+ default 12 if ARCH_T4240
+ default 8 if ARCH_P4080 || \
+ ARCH_T4160
+ default 4 if ARCH_B4860 || \
+ ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P5040 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T2080 || \
+ ARCH_T2081
+ default 2 if ARCH_B4420 || \
+ ARCH_BSC9132 || \
+ ARCH_MPC8572 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1023 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020 || \
+ ARCH_P5020 || \
+ ARCH_T1023 || \
+ ARCH_T1024
+ default 1
+ help
+ Set this number to the maximum number of possible CPUs in the SoC.
+ SoCs may have multiple clusters with each cluster may have multiple
+ ports. If some ports are reserved but higher ports are used for
+ cores, count the reserved ports. This will allocate enough memory
+ in spin table to properly handle all cores.
+
+config SYS_CCSRBAR_DEFAULT
+ hex "Default CCSRBAR address"
+ default 0xff700000 if ARCH_BSC9131 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X || \
+ ARCH_MPC8536 || \
+ ARCH_MPC8540 || \
+ ARCH_MPC8541 || \
+ ARCH_MPC8544 || \
+ ARCH_MPC8548 || \
+ ARCH_MPC8555 || \
+ ARCH_MPC8560 || \
+ ARCH_MPC8568 || \
+ ARCH_MPC8569 || \
+ ARCH_MPC8572 || \
+ ARCH_P1010 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 0xff600000 if ARCH_P1023
+ default 0xfe000000 if ARCH_B4420 || \
+ ARCH_B4860 || \
+ ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4160 || \
+ ARCH_T4240
+ default 0xe0000000 if ARCH_QEMU_E500
+ help
+ Default value of CCSRBAR comes from power-on-reset. It
+ is fixed on each SoC. Some SoCs can have different value
+ if changed by pre-boot regime. The value here must match
+ the current value in SoC. If not sure, do not change.
+
+config SYS_FSL_ERRATUM_A004468
+ bool
+
+config SYS_FSL_ERRATUM_A004477
+ bool
+
+config SYS_FSL_ERRATUM_A004508
+ bool
+
+config SYS_FSL_ERRATUM_A004580
+ bool
+
+config SYS_FSL_ERRATUM_A004699
+ bool
+
+config SYS_FSL_ERRATUM_A004849
+ bool
+
+config SYS_FSL_ERRATUM_A004510
+ bool
+
+config SYS_FSL_ERRATUM_A004510_SVR_REV
+ hex
+ depends on SYS_FSL_ERRATUM_A004510
+ default 0x20 if ARCH_P4080
+ default 0x10
+
+config SYS_FSL_ERRATUM_A004510_SVR_REV2
+ hex
+ depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
+ default 0x11
+
+config SYS_FSL_ERRATUM_A005125
+ bool
+
+config SYS_FSL_ERRATUM_A005434
+ bool
+
+config SYS_FSL_ERRATUM_A005812
+ bool
+
+config SYS_FSL_ERRATUM_A005871
+ bool
+
+config SYS_FSL_ERRATUM_A006261
+ bool
+
+config SYS_FSL_ERRATUM_A006379
+ bool
+
+config SYS_FSL_ERRATUM_A006384
+ bool
+
+config SYS_FSL_ERRATUM_A006475
+ bool
+
+config SYS_FSL_ERRATUM_A006593
+ bool
+
+config SYS_FSL_ERRATUM_A007075
+ bool
+
+config SYS_FSL_ERRATUM_A007186
+ bool
+
+config SYS_FSL_ERRATUM_A007212
+ bool
+
+config SYS_FSL_ERRATUM_A007798
+ bool
+
+config SYS_FSL_ERRATUM_A008044
+ bool
+
+config SYS_FSL_ERRATUM_CPC_A002
+ bool
+
+config SYS_FSL_ERRATUM_CPC_A003
+ bool
+
+config SYS_FSL_ERRATUM_CPU_A003999
+ bool
+
+config SYS_FSL_ERRATUM_ELBC_A001
+ bool
+
+config SYS_FSL_ERRATUM_I2C_A004447
+ bool
+
+config SYS_FSL_A004447_SVR_REV
+ hex
+ depends on SYS_FSL_ERRATUM_I2C_A004447
+ default 0x00 if ARCH_MPC8548
+ default 0x10 if ARCH_P1010
+ default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
+ default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
+
+config SYS_FSL_ERRATUM_IFC_A002769
+ bool
+
+config SYS_FSL_ERRATUM_IFC_A003399
+ bool
+
+config SYS_FSL_ERRATUM_NMG_CPU_A011
+ bool
+
+config SYS_FSL_ERRATUM_NMG_ETSEC129
+ bool
+
+config SYS_FSL_ERRATUM_NMG_LBC103
+ bool
+
+config SYS_FSL_ERRATUM_P1010_A003549
+ bool
+
+config SYS_FSL_ERRATUM_SATA_A001
+ bool
+
+config SYS_FSL_ERRATUM_SEC_A003571
+ bool
+
+config SYS_FSL_ERRATUM_SRIO_A004034
+ bool
+
+config SYS_FSL_ERRATUM_USB14
+ bool
+
+config SYS_P4080_ERRATUM_CPU22
+ bool
+
+config SYS_P4080_ERRATUM_PCIE_A003
+ bool
+
+config SYS_P4080_ERRATUM_SERDES8
+ bool
+
+config SYS_P4080_ERRATUM_SERDES9
+ bool
+
+config SYS_P4080_ERRATUM_SERDES_A001
+ bool
+
+config SYS_P4080_ERRATUM_SERDES_A005
+ bool
+
+config SYS_FSL_QORIQ_CHASSIS1
+ bool
+
+config SYS_FSL_QORIQ_CHASSIS2
+ bool
+
+config SYS_FSL_NUM_LAWS
+ int "Number of local access windows"
+ depends on FSL_LAW
+ default 32 if ARCH_B4420 || \
+ ARCH_B4860 || \
+ ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4160 || \
+ ARCH_T4240
+ default 16 if ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042
+ default 12 if ARCH_BSC9131 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X || \
+ ARCH_MPC8536 || \
+ ARCH_MPC8572 || \
+ ARCH_P1010 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1023 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 10 if ARCH_MPC8544 || \
+ ARCH_MPC8548 || \
+ ARCH_MPC8568 || \
+ ARCH_MPC8569
+ default 8 if ARCH_MPC8540 || \
+ ARCH_MPC8541 || \
+ ARCH_MPC8555 || \
+ ARCH_MPC8560
+ help
+ Number of local access windows. This is fixed per SoC.
+ If not sure, do not change.
+
+config SYS_FSL_THREADS_PER_CORE
+ int
+ default 2 if E6500
+ default 1
+
+config SYS_NUM_TLBCAMS
+ int "Number of TLB CAM entries"
+ default 64 if E500MC
+ default 16
+ help
+ Number of TLB CAM entries for Book-E chips. 64 for E500MC,
+ 16 for other E500 SoCs.
+
+config SYS_PPC64
+ bool
+
+config SYS_PPC_E500_USE_DEBUG_TLB
+ bool
+
+config SYS_PPC_E500_DEBUG_TLB
+ int "Temporary TLB entry for external debugger"
+ depends on SYS_PPC_E500_USE_DEBUG_TLB
+ default 0 if ARCH_MPC8544 || ARCH_MPC8548
+ default 1 if ARCH_MPC8536
+ default 2 if ARCH_MPC8572 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 3 if ARCH_P1010 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X
+ help
+ Select a temporary TLB entry to be used during boot to work
+ around limitations in e500v1 and e500v2 external debugger
+ support. This reduces the portions of the boot code where
+ breakpoints and single stepping do not work. The value of this
+ symbol should be set to the TLB1 entry to be used for this
+ purpose. If unsure, do not change.
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index f4c4fe2..04585d0 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -39,24 +39,21 @@
obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
-obj-$(CONFIG_PPC_P2041) += p2041_ids.o
-obj-$(CONFIG_PPC_P3041) += p3041_ids.o
-obj-$(CONFIG_PPC_P4080) += p4080_ids.o
-obj-$(CONFIG_PPC_P5020) += p5020_ids.o
-obj-$(CONFIG_PPC_P5040) += p5040_ids.o
-obj-$(CONFIG_PPC_T4240) += t4240_ids.o
-obj-$(CONFIG_PPC_T4160) += t4240_ids.o
-obj-$(CONFIG_PPC_T4080) += t4240_ids.o
-obj-$(CONFIG_PPC_B4420) += b4860_ids.o
-obj-$(CONFIG_PPC_B4860) += b4860_ids.o
-obj-$(CONFIG_PPC_T1040) += t1040_ids.o
-obj-$(CONFIG_PPC_T1042) += t1040_ids.o
-obj-$(CONFIG_PPC_T1020) += t1040_ids.o
-obj-$(CONFIG_PPC_T1022) += t1040_ids.o
-obj-$(CONFIG_PPC_T1023) += t1024_ids.o
-obj-$(CONFIG_PPC_T1024) += t1024_ids.o
-obj-$(CONFIG_PPC_T2080) += t2080_ids.o
-obj-$(CONFIG_PPC_T2081) += t2080_ids.o
+obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
+obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
+obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
+obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
+obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
+obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
+obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
+obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
+obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
+obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
+obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
+obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
+obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
+obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
+obj-$(CONFIG_ARCH_T2081) += t2080_ids.o
obj-$(CONFIG_QE) += qe_io.o
@@ -65,52 +62,44 @@
obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support
-obj-$(CONFIG_PPC_C29X) += c29x_serdes.o
-obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
-obj-$(CONFIG_MPC8544) += mpc8544_serdes.o
-obj-$(CONFIG_MPC8548) += mpc8548_serdes.o
-obj-$(CONFIG_MPC8568) += mpc8568_serdes.o
-obj-$(CONFIG_MPC8569) += mpc8569_serdes.o
-obj-$(CONFIG_MPC8572) += mpc8572_serdes.o
-obj-$(CONFIG_P1010) += p1010_serdes.o
-obj-$(CONFIG_P1011) += p1021_serdes.o
-obj-$(CONFIG_P1012) += p1021_serdes.o
-obj-$(CONFIG_P1013) += p1022_serdes.o
-obj-$(CONFIG_P1014) += p1010_serdes.o
-obj-$(CONFIG_P1017) += p1023_serdes.o
-obj-$(CONFIG_P1020) += p1021_serdes.o
-obj-$(CONFIG_P1021) += p1021_serdes.o
-obj-$(CONFIG_P1022) += p1022_serdes.o
-obj-$(CONFIG_P1023) += p1023_serdes.o
-obj-$(CONFIG_P1024) += p1021_serdes.o
-obj-$(CONFIG_P1025) += p1021_serdes.o
-obj-$(CONFIG_P2010) += p2020_serdes.o
-obj-$(CONFIG_P2020) += p2020_serdes.o
-obj-$(CONFIG_PPC_P2041) += p2041_serdes.o
-obj-$(CONFIG_PPC_P3041) += p3041_serdes.o
-obj-$(CONFIG_PPC_P4080) += p4080_serdes.o
-obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
-obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
-obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
-obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
-obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
-obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
-obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
-obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
-obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1023) += t1024_serdes.o
-obj-$(CONFIG_PPC_T1024) += t1024_serdes.o
-obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
-obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
+obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
+obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
+obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
+obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
+obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
+obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
+obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
+obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
+obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o
+obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o
+obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
+obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
+obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
+obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
+obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
+obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
+obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
+obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
+obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
+obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
+obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
+obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
+obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
+obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
+obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
+obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
+obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o
obj-y += cpu.o
obj-y += cpu_init.o
obj-y += cpu_init_early.o
obj-y += interrupts.o
-ifneq ($(CONFIG_QEMU_E500),y)
+ifneq ($(CONFIG_ARCH_QEMU_E500),y)
obj-y += speed.o
endif
obj-y += tlb.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 85eba0b..4ceb6f5 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -62,7 +62,7 @@
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
-#ifndef CONFIG_PPC_B4420
+#ifndef CONFIG_ARCH_B4420
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
@@ -81,7 +81,7 @@
SET_FMAN_RX_1G_LIODN(1, 3, 91),
SET_FMAN_RX_1G_LIODN(1, 4, 92),
SET_FMAN_RX_1G_LIODN(1, 5, 93),
-#ifndef CONFIG_PPC_B4420
+#ifndef CONFIG_ARCH_B4420
SET_FMAN_RX_10G_LIODN(1, 0, 94),
SET_FMAN_RX_10G_LIODN(1, 1, 95),
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index 63172de..a5709dd 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -15,7 +15,7 @@
u8 lanes[SRDS_MAX_LANES];
};
-#ifdef CONFIG_PPC_B4860
+#ifdef CONFIG_ARCH_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x01, {AURORA, AURORA, CPRI6, CPRI5,
@@ -180,7 +180,7 @@
};
#endif
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
static struct serdes_config serdes1_cfg_tbl[] = {
{0x0D, {NONE, NONE, CPRI6, CPRI5,
CPRI4, CPRI3, NONE, NONE} },
diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
index 399b208..4b5cd99 100644
--- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
@@ -68,6 +68,9 @@
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
@@ -79,6 +82,9 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -90,4 +96,7 @@
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
index 51972cb..74d27b9 100644
--- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
@@ -32,6 +32,9 @@
int is_serdes_configured(enum srds_prtcl device)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes1_prtcl_map;
}
@@ -44,6 +47,9 @@
const struct serdes_config *ptr;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -59,4 +65,7 @@
enum srds_prtcl lane_prtcl = ptr->lanes[lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3b06ae4..54b5b33 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -26,12 +26,12 @@
void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
unsigned int i;
-#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
+#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
static const uint8_t offsets[] = {
0x50, 0x54, 0x58, 0x90, 0x94, 0x98
};
#endif
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
static const uint8_t offsets[] = {
0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
};
@@ -45,11 +45,11 @@
}
}
-#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
+#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
x108 = 0x12;
#endif
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
/*
* For P4080, the erratum document says that the value at offset 0x108
* should be 0x12 on rev2, or 0x1c on rev3.
@@ -136,7 +136,7 @@
#endif
__maybe_unused u32 svr = get_svr();
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
if (IS_SVR_REV(svr, 1, 0)) {
switch (SVR_SOC_VER(svr)) {
case SVR_P1013:
@@ -323,7 +323,8 @@
if (IS_SVR_REV(svr, 1, 0))
puts("Work-around for Erratum A-008044 enabled\n");
#endif
-#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS)
+#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \
+ (defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS))
puts("Work-around for Erratum XFI on B4860QDS enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index ef08489..cc30fa6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -293,8 +293,8 @@
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
+ defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
unsigned long val, msr;
/*
@@ -404,7 +404,7 @@
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
- defined(CONFIG_QEMU_E500)
+ defined(CONFIG_ARCH_QEMU_E500)
return fsl_ddr_sdram_size();
#else
return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
@@ -482,17 +482,17 @@
int i, j, k, m;
u8 *p_8;
u32 *p_32;
- struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+ struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
generic_spd_eeprom_t
- spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+ spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
- puts("SPD data of all dimms (zero vaule is omitted)...\n");
+ puts("SPD data of all dimms (zero value is omitted)...\n");
puts("Byte (hex) ");
k = 1;
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
printf("Dimm%d ", k++);
}
@@ -500,7 +500,7 @@
for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
m = 0;
printf("%3d (0x%02x) ", k, k);
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
p_8 = (u8 *) &spd[i][j];
if (p_8[k]) {
@@ -516,22 +516,22 @@
puts("\r");
}
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
@@ -543,15 +543,15 @@
}
}
printf("DDR registers dump for all controllers "
- "(zero vaule is omitted)...\n");
+ "(zero value is omitted)...\n");
puts("Offset (hex) ");
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
p_32 = (u32 *) ddr[i];
if (p_32[k]) {
printf(" 0x%08x", p_32[k]);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index ace4279..822844d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -45,7 +45,9 @@
#include <nand.h>
#include <errno.h>
#endif
-
+#ifndef CONFIG_ARCH_QEMU_E500
+#include <fsl_ddr.h>
+#endif
#include "../../../../drivers/block/fsl_sata.h"
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
@@ -114,10 +116,10 @@
setbits_be32(&usb_phy->config2,
CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
- temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+ temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
- temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+ temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
#endif
}
@@ -376,10 +378,10 @@
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
#endif
@@ -407,25 +409,25 @@
ddr_pll_ratio >>= 1;
setbits_be32(plldadcr1, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
setbits_be32(plldadcr2, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
setbits_be32(plldadcr3, 0x02000001);
#endif
#endif
setbits_be32(dpdovrcr4, 0xe0000000);
out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
#endif
#endif
udelay(100);
clrbits_be32(plldadcr1, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
clrbits_be32(plldadcr2, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
clrbits_be32(plldadcr3, 0x02000001);
#endif
#endif
@@ -442,7 +444,7 @@
#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
struct law_entry law;
#endif
-#ifdef CONFIG_MPC8548
+#ifdef CONFIG_ARCH_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
@@ -947,6 +949,10 @@
#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+ erratum_a009942_check_cpo();
+#endif
+
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif
@@ -959,7 +965,7 @@
#ifdef CONFIG_FSL_CAAM
sec_init();
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
sec_init_idx(1);
@@ -969,7 +975,7 @@
#endif
#endif
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
* controller is configured in legacy mode instead of the
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index aa519b0..345d693 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -97,7 +97,7 @@
/* gd area was zeroed during startup */
-#ifdef CONFIG_QEMU_E500
+#ifdef CONFIG_ARCH_QEMU_E500
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index ced216c..67140ba 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -180,6 +180,39 @@
#define ft_fixup_l3cache(x, y)
#endif
+#if defined(CONFIG_L2_CACHE) || \
+ defined(CONFIG_BACKSIDE_L2_CACHE) || \
+ defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+static inline void ft_fixup_l2cache_compatible(void *blob, int off)
+{
+ int len;
+ struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
+
+ if (cpu) {
+ char buf[40];
+
+ if (isdigit(cpu->name[0])) {
+ /* MPCxxxx, where xxxx == 4-digit number */
+ len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
+ cpu->name) + 1;
+ } else {
+ /* Pxxxx or Txxxx, where xxxx == 4-digit number */
+ len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
+ tolower(cpu->name[0]), cpu->name + 1) + 1;
+ }
+
+ /*
+ * append "cache" after the NULL character that the previous
+ * sprintf wrote. This is how a device tree stores multiple
+ * strings in a property.
+ */
+ len += sprintf(buf + len, "cache") + 1;
+
+ fdt_setprop(blob, off, "compatible", buf, len);
+ }
+}
+#endif
+
#if defined(CONFIG_L2_CACHE)
/* return size in kilobytes */
static inline u32 l2cache_size(void)
@@ -215,9 +248,8 @@
static inline void ft_fixup_l2cache(void *blob)
{
- int len, off;
+ int off;
u32 *ph;
- struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
const u32 line_size = 32;
const u32 num_ways = 8;
@@ -243,28 +275,7 @@
return ;
}
- if (cpu) {
- char buf[40];
-
- if (isdigit(cpu->name[0])) {
- /* MPCxxxx, where xxxx == 4-digit number */
- len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
- cpu->name) + 1;
- } else {
- /* Pxxxx or Txxxx, where xxxx == 4-digit number */
- len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
- tolower(cpu->name[0]), cpu->name + 1) + 1;
- }
-
- /*
- * append "cache" after the NULL character that the previous
- * sprintf wrote. This is how a device tree stores multiple
- * strings in a property.
- */
- len += sprintf(buf + len, "cache") + 1;
-
- fdt_setprop(blob, off, "compatible", buf, len);
- }
+ ft_fixup_l2cache_compatible(blob, off);
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
@@ -337,7 +348,7 @@
fdt_setprop_cell(blob, l2_off, "cache-size", size);
fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
fdt_setprop_cell(blob, l2_off, "cache-level", 2);
- fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ ft_fixup_l2cache_compatible(blob, l2_off);
}
if (l3_off < 0) {
@@ -490,7 +501,7 @@
}
#endif
-#if defined(CONFIG_PPC_P4080)
+#if defined(CONFIG_ARCH_P4080)
static void fdt_fixup_usb(void *fdt)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -511,8 +522,8 @@
#define fdt_fixup_usb(x)
#endif
-#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \
- defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
+ defined(CONFIG_ARCH_T4160)
void fdt_fixup_dma3(void *blob)
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
@@ -520,7 +531,7 @@
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
@@ -529,8 +540,7 @@
case 0x29:
case 0x2d:
case 0x2e:
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080)
+#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
@@ -556,7 +566,7 @@
#define fdt_fixup_dma3(x)
#endif
-#if defined(CONFIG_PPC_T1040)
+#if defined(CONFIG_ARCH_T1040)
static void fdt_fixup_l2_switch(void *blob)
{
uchar l2swaddr[6];
@@ -626,10 +636,6 @@
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
- "bus-frequency", gd->arch.lbc_clk, 1);
- do_fixup_by_compat_u32(blob, "fsl,elbc",
- "bus-frequency", gd->arch.lbc_clk, 1);
#ifdef CONFIG_QE
ft_qe_setup(blob);
ft_fixup_qe_snum(blob);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 9920839..677b062 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -10,7 +10,7 @@
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/fsl_law.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <fsl_errata.h>
#include "fsl_corenet2_serdes.h"
@@ -92,15 +92,27 @@
int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
+ if (!serdes1_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
+ if (!serdes2_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes2_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
+ if (!serdes3_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes3_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
+ if (!serdes4_prtcl_map[NONE])
+ fsl_serdes_init();
+
ret |= serdes4_prtcl_map[device];
#endif
@@ -184,6 +196,9 @@
u32 cfg;
int lane;
+ if (serdes_prtcl_map[NONE])
+ return;
+
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
struct ccsr_sfp_regs __iomem *sfp_regs =
@@ -325,6 +340,9 @@
else
serdes_prtcl_map[lane_prtcl] = 1;
}
+
+ /* Set the first element to indicate serdes has been initialized */
+ serdes_prtcl_map[NONE] = 1;
}
void fsl_serdes_init(void)
@@ -373,7 +391,7 @@
case SRDS_PLLCR0_RFCK_SEL_161_13:
return "161.1328123";
default:
-#if defined(CONFIG_T4240QDS)
+#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS)
return "???";
#else
return "122.88";
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index ba22f90..1bc0c64 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -13,7 +13,7 @@
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/fsl_law.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "fsl_corenet_serdes.h"
/*
@@ -76,7 +76,7 @@
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
@@ -136,6 +136,9 @@
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return 0;
+ if (!(serdes_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes_prtcl_map;
}
@@ -488,7 +491,7 @@
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
serdes_corenet_t *srds2_regs;
#endif
int lane, bank, idx;
@@ -514,6 +517,8 @@
if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
#endif
+ if (serdes_prtcl_map & (1 << NONE))
+ return;
/* Is serdes enabled at all? */
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -572,7 +577,7 @@
}
}
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
/*
* Lanes on bank 4 on P5040 are commented-out, but for some SERDES
* protocols, these lanes are routed to SATA. We use serdes_prtcl_map
@@ -602,6 +607,9 @@
soc_serdes_init();
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes_prtcl_map |= (1 << NONE);
+
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
/*
* Bank two uses the clock from bank three, so if bank two is enabled,
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index baf52d5..8c075f1 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -71,11 +71,19 @@
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
@@ -88,6 +96,10 @@
u32 tmp;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
@@ -221,6 +233,9 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
return;
@@ -230,4 +245,7 @@
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
index ed78a66..b27763e 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
@@ -34,11 +34,19 @@
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
@@ -50,6 +58,10 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -61,6 +73,9 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
@@ -76,4 +91,7 @@
if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
index d146955..f1042d5 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -24,6 +24,9 @@
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
@@ -35,6 +38,9 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -46,4 +52,7 @@
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
index 9199f01..7c287a0 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
@@ -24,6 +24,9 @@
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
@@ -35,6 +38,9 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -46,4 +52,7 @@
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
index 6c80b5e..cc8ddb2 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
@@ -33,6 +33,9 @@
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
@@ -44,6 +47,9 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -55,4 +61,7 @@
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
index 3632eb5..1f0f474 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
@@ -28,6 +28,9 @@
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
@@ -39,6 +42,9 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -62,4 +68,7 @@
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
serdes1_prtcl_map |= (1 << SGMII_TSEC4);
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
index 4b965f7..d8c0b62 100644
--- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
@@ -33,11 +33,19 @@
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
@@ -49,6 +57,10 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -60,6 +72,9 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
@@ -69,4 +84,7 @@
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
index 99a77bd..77b9439 100644
--- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
@@ -41,6 +41,9 @@
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
@@ -55,6 +58,9 @@
int lane;
u32 mask, val;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -67,6 +73,9 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
/* Init SERDES Receiver electrical idle detection control for PCIe */
/* Lane 0 is always PCIe 1 */
diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
index 14d17eb..88013d4 100644
--- a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
@@ -72,11 +72,19 @@
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
@@ -88,6 +96,10 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -99,6 +111,9 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
@@ -108,4 +123,7 @@
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
index e83b0a3..b2b9f95 100644
--- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -24,7 +24,12 @@
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
return ret;
}
@@ -36,6 +41,9 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -47,4 +55,6 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
index 59d402c..0890eaa 100644
--- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
@@ -32,6 +32,9 @@
int is_serdes_configured(enum srds_prtcl prtcl)
{
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << prtcl) & serdes1_prtcl_map;
}
@@ -43,6 +46,9 @@
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -54,4 +60,7 @@
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
index c6d2fda..538729f 100644
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ b/arch/powerpc/cpu/mpc85xx/pci.c
@@ -120,7 +120,7 @@
pci_register_hose(hose);
-#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
+#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
/*
* This is a SW workaround for an apparent HW problem
* in the PCI controller on the MPC85555/41 CDS boards.
diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c
index d2825ec..49e82a2 100644
--- a/arch/powerpc/cpu/mpc85xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc85xx/qe_io.c
@@ -7,10 +7,10 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "common.h"
-#include "asm/errno.h"
-#include "asm/io.h"
-#include "asm/immap_85xx.h"
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
#define NUM_OF_PINS 32
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e732969..fcf5d92 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -130,9 +130,8 @@
* it uses 6.
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
- defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
+ defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
@@ -202,11 +201,11 @@
}
#endif
-#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
- defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
+ defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
-#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#define FM1_CLK_SEL 0x00000007
#define FM1_CLK_SHIFT 0
#else
@@ -216,7 +215,7 @@
#define FM1_CLK_SHIFT 26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
-#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
#else
rcw_tmp = in_be32(&gur->rcwsr[7]);
@@ -456,7 +455,7 @@
#endif
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
#define ESDHC_CLK_SEL 0x00000007
#define ESDHC_CLK_SHIFT 0
#define ESDHC_CLK_RCWSR 15
@@ -480,7 +479,7 @@
case 4:
sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
break;
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
case 5:
sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
break;
@@ -596,7 +595,7 @@
#endif
#ifdef CONFIG_QE
-#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
sys_info->freq_qe = sys_info->freq_systembus;
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
@@ -625,8 +624,8 @@
* for four times the clock divider values.
*/
lcrr_div *= 4;
-#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
- !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
+#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
+ !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider values.
@@ -652,7 +651,7 @@
int get_clocks (void)
{
sys_info_t sys_info;
-#ifdef CONFIG_MPC8544
+#ifdef CONFIG_ARCH_MPC8544
volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
@@ -681,11 +680,11 @@
* for that SOC. This information is taken from application note
* AN2919.
*/
-#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
- defined(CONFIG_P1022)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
+ defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
+ defined(CONFIG_ARCH_P1022)
gd->arch.i2c1_clk = sys_info.freq_systembus;
-#elif defined(CONFIG_MPC8544)
+#elif defined(CONFIG_ARCH_MPC8544)
/*
* On the 8544, the I2C clock is the same as the SEC clock. This can be
* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
@@ -707,8 +706,7 @@
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
#else
-#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
- defined(CONFIG_P1014)
+#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
gd->arch.sdhc_clk = gd->bus_clk;
#else
gd->arch.sdhc_clk = gd->bus_clk / 2;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index c3e1234..932216c 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -311,7 +311,7 @@
#endif
mtspr HID0,r0
-#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
+#if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
@@ -345,7 +345,7 @@
mtspr DBCR0,r0
#endif
-#ifdef CONFIG_MPC8569
+#ifdef CONFIG_ARCH_MPC8569
#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
@@ -376,7 +376,7 @@
tlbivax 0,r4
isync
-#endif /* CONFIG_MPC8569 */
+#endif /* CONFIG_ARCH_MPC8569 */
/*
* Search for the TLB that covers the code we're executing, and shrink it
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
index c65f41d..fc63fe3 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -161,7 +161,7 @@
{}
};
-#ifndef CONFIG_PPC_T2081
+#ifndef CONFIG_ARCH_T2081
static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
@@ -181,7 +181,7 @@
static const struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
-#ifndef CONFIG_PPC_T2081
+#ifndef CONFIG_ARCH_T2081
serdes2_cfg_tbl,
#endif
};
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 7b43b28..3fc527d 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -15,7 +15,7 @@
u8 lanes[SRDS_MAX_LANES];
};
-#ifdef CONFIG_PPC_T4240
+#ifdef CONFIG_ARCH_T4240
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
@@ -263,7 +263,7 @@
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
+#elif defined(CONFIG_ARCH_T4160)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {NONE, NONE, NONE, NONE,
diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index fe1859d..ff21c48 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -10,18 +10,54 @@
config TARGET_SBC8641D
bool "Support sbc8641d"
+ select ARCH_MPC8641
config TARGET_MPC8610HPCD
bool "Support MPC8610HPCD"
+ select ARCH_MPC8610
config TARGET_MPC8641HPCN
bool "Support MPC8641HPCN"
+ select ARCH_MPC8641
config TARGET_XPEDITE517X
bool "Support xpedite517x"
+ select ARCH_MPC8641
endchoice
+config ARCH_MPC8610
+ bool
+ select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_DDR2
+
+config ARCH_MPC8641
+ bool
+ select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_DDR2
+
+config FSL_LAW
+ bool
+ help
+ Use Freescale common code for Local Access Window
+
+config SYS_CCSRBAR_DEFAULT
+ hex "Default CCSRBAR address"
+ default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641
+ help
+ Default value of CCSRBAR comes from power-on-reset. It
+ is fixed on each SoC. Some SoCs can have different value
+ if changed by pre-boot regime. The value here must match
+ the current value in SoC. If not sure, do not change.
+config SYS_FSL_NUM_LAWS
+ int "Number of local access windows"
+ default 10 if ARCH_MPC8610 || ARCH_MPC8641
+ help
+ Number of local access windows. This is fixed per SoC.
+ If not sure, do not change.
+
source "board/freescale/mpc8610hpcd/Kconfig"
source "board/freescale/mpc8641hpcn/Kconfig"
source "board/sbc8641d/Kconfig"
diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile
index 0f790b0..88c23fc 100644
--- a/arch/powerpc/cpu/mpc86xx/Makefile
+++ b/arch/powerpc/cpu/mpc86xx/Makefile
@@ -19,6 +19,6 @@
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-y += interrupts.o
obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_MPC8610) += mpc8610_serdes.o
-obj-$(CONFIG_MPC8641) += mpc8641_serdes.o
+obj-$(CONFIG_ARCH_MPC8610) += mpc8610_serdes.o
+obj-$(CONFIG_ARCH_MPC8641) += mpc8641_serdes.o
obj-y += speed.o
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
index 3051854..7a9570c 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu.c
@@ -90,9 +90,9 @@
puts("L2: ");
if (get_l2cr() & 0x80000000) {
-#if defined(CONFIG_MPC8610)
+#if defined(CONFIG_ARCH_MPC8610)
puts("256");
-#elif defined(CONFIG_MPC8641)
+#elif defined(CONFIG_ARCH_MPC8641)
puts("512");
#endif
puts(" KiB enabled\n");
@@ -139,7 +139,7 @@
void
watchdog_reset(void)
{
-#if defined(CONFIG_MPC8610)
+#if defined(CONFIG_ARCH_MPC8610)
/*
* This actually feed the hard enabled watchdog.
*/
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index dd99155..5f9ad6b 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c
@@ -30,13 +30,6 @@
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
-#if defined(CONFIG_MPC8641)
- do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus",
- "bus-frequency", gd->arch.lbc_clk, 1);
-#endif
- do_fixup_by_compat_u32(blob, "fsl,elbc",
- "bus-frequency", gd->arch.lbc_clk, 1);
-
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \
diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
index 2a7e3bf..ea4f4c8 100644
--- a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
+++ b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
@@ -29,11 +29,19 @@
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
@@ -46,6 +54,10 @@
MPC8610_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -57,6 +69,9 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
@@ -66,4 +81,7 @@
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
index cc0f8e9..5b12cbd 100644
--- a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
+++ b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
@@ -38,11 +38,19 @@
int is_serdes_configured(enum srds_prtcl device)
{
- int ret = (1 << device) & serdes1_prtcl_map;
+ int ret;
+
+ if (!(serdes1_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
+ ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes2_prtcl_map;
}
@@ -55,6 +63,10 @@
MPC8641_PORDEVSR_IO_SEL_SHIFT;
int lane;
+ if (serdes1_prtcl_map & (1 << NONE) &&
+ serdes2_prtcl_map & (1 << NONE))
+ return;
+
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -66,6 +78,9 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes1_prtcl_map |= (1 << NONE);
+
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
@@ -75,4 +90,7 @@
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
+
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes2_prtcl_map |= (1 << NONE);
}
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index 5abe6f0..05f23db 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -115,7 +115,7 @@
* for that SOC. This information is taken from application note
* AN2919.
*/
-#ifdef CONFIG_MPC8610
+#ifdef CONFIG_ARCH_MPC8610
gd->arch.i2c1_clk = sys_info.freq_systembus;
#else
gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 0ab9aac..e17e201 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -9,7 +9,7 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
#define SRIO_PORT_ACCEPT_ALL 0x10000001
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
index 30e6c65..bfe48a2 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
@@ -118,7 +118,8 @@
#endif
unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
-#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
+#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
+ || defined(CONFIG_TARGET_MIP405T)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
@@ -408,7 +409,8 @@
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
-#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
+#if !(defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
+ || defined(CONFIG_TARGET_MIP405T))
/*
*As is these functs get called out of flash Not a horrible
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
index f0f3462..a616365 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
@@ -18,7 +18,7 @@
#include <asm/ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 92a330d..a6066ef 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -104,6 +104,9 @@
config TARGET_MIP405
bool "Support MIP405"
+config TARGET_MIP405T
+ bool "Support MIP405T"
+
config TARGET_PIP405
bool "Support PIP405"
diff --git a/arch/powerpc/cpu/ppc4xx/resetvec.S b/arch/powerpc/cpu/ppc4xx/resetvec.S
index b3308bd..a42d91f 100644
--- a/arch/powerpc/cpu/ppc4xx/resetvec.S
+++ b/arch/powerpc/cpu/ppc4xx/resetvec.S
@@ -4,7 +4,8 @@
#if defined(CONFIG_440)
b _start_440
#else
-#if defined(CONFIG_BOOT_PCI) && defined(CONFIG_MIP405)
+#if defined(CONFIG_BOOT_PCI) && (defined(CONFIG_TARGET_MIP405) \
+ || defined(CONFIG_TARGET_MIP405T))
b _start_pci
#else
b _start
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
index 65a0675..27423e3 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c
+++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
@@ -673,7 +673,8 @@
__u32 info = 0;
unsigned int toggle = 0;
- /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+ /* OHCI handles the DATA-toggles itself, we just use the
+ USB-toggle bits for resetting */
if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
toggle = TD_T_TOGGLE;
} else {
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index bb23756..55686a1 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -9,16 +9,13 @@
#ifdef CONFIG_MPC85xx
#include <asm/config_mpc85xx.h>
-#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC86xx
#include <asm/config_mpc86xx.h>
-#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC83xx
-#define CONFIG_SYS_FSL_DDR
#endif
#ifndef HWCONFIG_BUFFER_SIZE
@@ -57,10 +54,6 @@
#endif
#endif
-#ifndef CONFIG_MAX_CPUS
-#define CONFIG_MAX_CPUS 1
-#endif
-
/*
* Provide a default boot page translation virtual address that lines up with
* Freescale's default e500 reset page.
@@ -71,14 +64,6 @@
#endif
#endif
-/*
- * SEC (crypto unit) major compatible version determination
- */
-#if defined(CONFIG_MPC83xx)
-#define CONFIG_SYS_FSL_SEC_BE
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#endif
-
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 505d355..6fd218a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -9,10 +9,6 @@
/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
-#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
-#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
-#endif
-
/*
* This macro should be removed when we no longer care about backwards
* compatibility with older operating systems.
@@ -20,651 +16,247 @@
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
#include <fsl_ddrc_version.h>
-#define CONFIG_SYS_FSL_DDR_BE
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SEC_MON_BE
-/* Number of TLB CAM entries we have on FSL Book-E chips */
-#if defined(CONFIG_E500MC)
-#define CONFIG_SYS_NUM_TLBCAMS 64
-#elif defined(CONFIG_E500)
-#define CONFIG_SYS_NUM_TLBCAMS 16
-#endif
-
-#if defined(CONFIG_MPC8536)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_MPC8540)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 8
-#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-
-#elif defined(CONFIG_MPC8541)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 8
-#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-
-#elif defined(CONFIG_MPC8544)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 10
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_MPC8548)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 10
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
-#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
-#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+#if defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
-#elif defined(CONFIG_MPC8555)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 8
-#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-
-#elif defined(CONFIG_MPC8560)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 8
-#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-
-#elif defined(CONFIG_MPC8568)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 10
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#elif defined(CONFIG_ARCH_MPC8568)
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#elif defined(CONFIG_MPC8569)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 10
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#elif defined(CONFIG_ARCH_MPC8569)
#define QE_MURAM_SIZE 0x20000UL
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#elif defined(CONFIG_MPC8572)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_DDR_115
-#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P1010)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
-#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A007075
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_ESDHC_HC_BLK_ADDR
/* P1011 is single core version of P1020 */
-#elif defined(CONFIG_P1011)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
+#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-/* P1012 is single core version of P1021 */
-#elif defined(CONFIG_P1012)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
+#elif defined(CONFIG_ARCH_P1020)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define QE_MURAM_SIZE 0x6000UL
-#define MAX_QE_RISC 1
-#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-/* P1013 is single core version of P1022 */
-#elif defined(CONFIG_P1013)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_FSL_SATA_ERRATUM_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P1014)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
-#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
-#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-
-/* P1017 is single core version of P1023 */
-#elif defined(CONFIG_P1017)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_NUM_FM1_DTSEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_QMAN_NUM_PORTALS 3
-#define CONFIG_SYS_BMAN_NUM_PORTALS 3
-#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P1020)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
-#elif defined(CONFIG_P1021)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
+#elif defined(CONFIG_ARCH_P1021)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#elif defined(CONFIG_P1022)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
+#elif defined(CONFIG_ARCH_P1022)
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_FSL_SATA_ERRATUM_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#elif defined(CONFIG_P1023)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
/* P1024 is lower end variant of P1020 */
-#elif defined(CONFIG_P1024)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
+#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */
-#elif defined(CONFIG_P1025)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 12
+#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-/* P2010 is single core version of P2020 */
-#elif defined(CONFIG_P2010)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P2020)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#elif defined(CONFIG_ARCH_P2020)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_A004849
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
-#elif defined(CONFIG_PPC_P3041)
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#elif defined(CONFIG_ARCH_P3041)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_A004849
-#define CONFIG_SYS_FSL_ERRATUM_A005812
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
-#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
-#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
-#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
-#define CONFIG_SYS_P4080_ERRATUM_CPU22
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_P4080_ERRATUM_SERDES8
-#define CONFIG_SYS_P4080_ERRATUM_SERDES9
-#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
-#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_A004849
-#define CONFIG_SYS_FSL_ERRATUM_A004580
-#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
-#define CONFIG_SYS_FSL_ERRATUM_A005812
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A007075
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
-#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
-#define CONFIG_SYS_PPC64 /* 64-bit core */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
-#elif defined(CONFIG_PPC_P5040)
-#define CONFIG_SYS_PPC64
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_ERRATUM_A004699
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
-#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#define CONFIG_SYS_FSL_ERRATUM_A005812
-#elif defined(CONFIG_BSC9131)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_BSC9132)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
+#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A005434
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080)
-#define CONFIG_E6500
-#define CONFIG_SYS_PPC64 /* 64-bit core */
+#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
-#ifdef CONFIG_PPC_T4240
-#define CONFIG_MAX_CPUS 12
+#ifdef CONFIG_ARCH_T4240
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 3
#else
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#if defined(CONFIG_PPC_T4160)
-#define CONFIG_MAX_CPUS 8
+#if defined(CONFIG_ARCH_T4160)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#elif defined(CONFIG_PPC_T4080)
-#define CONFIG_MAX_CPUS 4
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRDS_3
#define CONFIG_SYS_FSL_SRDS_4
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_PME_CLK 0
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM1_CLK 3
@@ -678,115 +270,70 @@
#define CONFIG_SYS_FSL_SRIO_LIODN
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_A004468
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
-#define CONFIG_SYS_FSL_ERRATUM_A005871
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_ERRATUM_A006379
-#define CONFIG_SYS_FSL_ERRATUM_A007186
-#define CONFIG_SYS_FSL_ERRATUM_A006593
-#define CONFIG_SYS_FSL_ERRATUM_A007798
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
-#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
-#define CONFIG_E6500
-#define CONFIG_SYS_PPC64 /* 64-bit core */
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_MAPLE
#define CONFIG_SYS_CPRI
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_CPRI_CLK 3
#define CONFIG_SYS_ULB_CLK 4
#define CONFIG_SYS_ETVPE_CLK 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A_004934
-#define CONFIG_SYS_FSL_ERRATUM_A005871
-#define CONFIG_SYS_FSL_ERRATUM_A006379
-#define CONFIG_SYS_FSL_ERRATUM_A007186
-#define CONFIG_SYS_FSL_ERRATUM_A006593
-#define CONFIG_SYS_FSL_ERRATUM_A007075
-#define CONFIG_SYS_FSL_ERRATUM_A006475
-#define CONFIG_SYS_FSL_ERRATUM_A006384
-#define CONFIG_SYS_FSL_ERRATUM_A007212
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#ifdef CONFIG_PPC_B4860
+#ifdef CONFIG_ARCH_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
-#define CONFIG_MAX_CPUS 4
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_SRIO_LIODN
#else
-#define CONFIG_MAX_CPUS 2
#define CONFIG_MAX_DSP_CPUS 2
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#endif
-#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
-defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#endif
-#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
-#define CONFIG_MAX_CPUS 4
-#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
-#define CONFIG_MAX_CPUS 2
-#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FSL_ERRATUM_A008044
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
@@ -799,45 +346,26 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
-defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#define CONFIG_SYS_FMAN_V3
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#endif
-#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
-#define CONFIG_MAX_CPUS 2
-#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
-#define CONFIG_MAX_CPUS 1
-#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
@@ -849,32 +377,22 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
-#define CONFIG_E6500
-#define CONFIG_SYS_PPC64 /* 64-bit core */
+#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_QMAN_V3
-#define CONFIG_MAX_CPUS 4
-#define CONFIG_SYS_FSL_NUM_LAWS 32
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCI_VER_3_X
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
@@ -882,19 +400,17 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#elif defined(CONFIG_PPC_T2081)
+#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
per rcw field value */
#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
@@ -902,61 +418,22 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_A007212
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_ERRATUM_A006593
-#define CONFIG_SYS_FSL_ERRATUM_A007186
-#define CONFIG_SYS_FSL_ERRATUM_A006379
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#elif defined(CONFIG_PPC_C29X)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 6
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
-#elif defined(CONFIG_QEMU_E500)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
-
-#else
-#error Processor type not defined for this platform
#endif
-#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
-#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
-#endif
-
-#ifdef CONFIG_E6500
-#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
-#else
-#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
-#endif
-
-#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN4)
-#define CONFIG_SYS_FSL_DDRC_GEN3
-#endif
-
-#if !defined(CONFIG_PPC_C29X)
+#if !defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#endif
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
index 4f9b225..5eabe6d 100644
--- a/arch/powerpc/include/asm/config_mpc86xx.h
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -7,20 +7,4 @@
#ifndef _ASM_MPC86xx_CONFIG_H_
#define _ASM_MPC86xx_CONFIG_H_
-#define CONFIG_SYS_FSL_DDR_86XX
-
-/* SoC specific defines for Freescale MPC86xx processors */
-
-#if defined(CONFIG_MPC8610)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 10
-
-#elif defined(CONFIG_MPC8641)
-#define CONFIG_MAX_CPUS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 10
-
-#else
-#error Processor type not defined for this platform
-#endif
-
#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
index b137a71..b46e20e 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -77,7 +77,7 @@
*/
#define CPM_DATAONLY_BASE ((uint)128)
#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
-#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
#else /* MPC8540, MPC8560 */
diff --git a/arch/powerpc/include/asm/errno.h b/arch/powerpc/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/powerpc/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 2a759c8..b348cc1 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -79,13 +79,13 @@
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
-#ifndef CONFIG_MPC8641
+#ifndef CONFIG_ARCH_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_OCN_DSP = 0x03,
#else
-#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
+#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
#endif
@@ -95,7 +95,7 @@
LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
-#if defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_CLASS_DSP = 0x0d,
#else
LAW_TRGT_IF_RIO_2 = 0x0d,
@@ -117,11 +117,11 @@
#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
-#ifdef CONFIG_MPC8641
+#ifdef CONFIG_ARCH_MPC8641
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
#endif
-#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
+#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
#endif /* CONFIG_FSL_CORENET */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 402edd7..b8270c5 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -325,9 +325,9 @@
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
-#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
- defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
- defined(CONFIG_MPC8560)
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
+ defined(CONFIG_ARCH_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 2e937f0..10e26d6 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -16,25 +16,29 @@
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
-#elif defined(CONFIG_BSC9132QDS)
+#elif defined(CONFIG_TARGET_BSC9132QDS)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
-#elif defined(CONFIG_C29XPCIE)
+#elif defined(CONFIG_TARGET_C29XPCIE)
#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
#else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif
#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
-#if defined(CONFIG_B4860QDS) || \
- defined(CONFIG_T4240QDS) || \
- defined(CONFIG_T2080QDS) || \
- defined(CONFIG_T2080RDB) || \
- defined(CONFIG_T1040QDS) || \
- defined(CONFIG_T104xD4QDS) || \
- defined(CONFIG_T104xRDB) || \
- defined(CONFIG_T104xD4RDB) || \
- defined(CONFIG_PPC_T1023) || \
- defined(CONFIG_PPC_T1024)
+#if defined(CONFIG_TARGET_B4860QDS) || \
+ defined(CONFIG_TARGET_B4420QDS) || \
+ defined(CONFIG_TARGET_T4160QDS) || \
+ defined(CONFIG_TARGET_T4240QDS) || \
+ defined(CONFIG_TARGET_T2080QDS) || \
+ defined(CONFIG_TARGET_T2080RDB) || \
+ defined(CONFIG_TARGET_T1040QDS) || \
+ defined(CONFIG_TARGET_T1040RDB) || \
+ defined(CONFIG_TARGET_T1040D4RDB) || \
+ defined(CONFIG_TARGET_T1042RDB) || \
+ defined(CONFIG_TARGET_T1042D4RDB) || \
+ defined(CONFIG_TARGET_T1042RDB_PI) || \
+ defined(CONFIG_ARCH_T1023) || \
+ defined(CONFIG_ARCH_T1024)
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CPC_REINIT_F
#endif
@@ -54,15 +58,15 @@
#endif
#endif
-#if defined(CONFIG_C29XPCIE)
+#if defined(CONFIG_TARGET_C29XPCIE)
#define CONFIG_KEY_REVOCATION
#endif
-#if defined(CONFIG_PPC_P3041) || \
- defined(CONFIG_PPC_P4080) || \
- defined(CONFIG_PPC_P5020) || \
- defined(CONFIG_PPC_P5040) || \
- defined(CONFIG_PPC_P2041)
+#if defined(CONFIG_ARCH_P3041) || \
+ defined(CONFIG_ARCH_P4080) || \
+ defined(CONFIG_ARCH_P5020) || \
+ defined(CONFIG_ARCH_P5040) || \
+ defined(CONFIG_ARCH_P2041)
#define CONFIG_FSL_TRUST_ARCH_v1
#endif
@@ -79,13 +83,7 @@
#endif /* #ifdef CONFIG_SECURE_BOOT */
#ifdef CONFIG_CHAIN_OF_TRUST
-
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_DM 1
-#define CONFIG_SPL_CRYPTO_SUPPORT
-#define CONFIG_SPL_HASH_SUPPORT
-#define CONFIG_SPL_RSA
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
/*
* PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
* due to space crunch on CPC and thus malloc will not work.
@@ -140,13 +138,13 @@
/* The bootscript header address is different for B4860 because the NOR
* mapping is different on B4 due to reduced NOR size.
*/
-#if defined(CONFIG_B4860QDS)
+#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
#elif defined(CONFIG_FSL_CORENET)
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
-#elif defined(CONFIG_BSC9132QDS)
+#elif defined(CONFIG_TARGET_BSC9132QDS)
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
-#elif defined(CONFIG_C29XPCIE)
+#elif defined(CONFIG_TARGET_C29XPCIE)
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
#else
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 45e248e..cb259cc 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -10,6 +10,10 @@
#include <config.h>
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7a878be..762b174 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -124,10 +124,10 @@
u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
} ccsr_i2c_t;
-#if defined(CONFIG_MPC8540) \
- || defined(CONFIG_MPC8541) \
- || defined(CONFIG_MPC8548) \
- || defined(CONFIG_MPC8555)
+#if defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8541) || \
+ defined(CONFIG_ARCH_MPC8548) || \
+ defined(CONFIG_ARCH_MPC8555)
/* DUART Registers */
typedef struct ccsr_duart {
u8 res1[1280];
@@ -1759,8 +1759,7 @@
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
@@ -1770,14 +1769,13 @@
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
-#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
-#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
-defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
@@ -1797,8 +1795,7 @@
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
-#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \
- defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
@@ -1812,7 +1809,7 @@
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
-#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
@@ -1848,7 +1845,7 @@
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
@@ -1856,8 +1853,8 @@
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
#endif
-#if defined(CONFIG_PPC_P2041) \
- || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
+#if defined(CONFIG_ARCH_P2041) || \
+ defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
@@ -1866,7 +1863,7 @@
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_P5040)
+#if defined(CONFIG_ARCH_P5040)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
@@ -1875,8 +1872,7 @@
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
@@ -1885,7 +1881,7 @@
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#endif
-#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
@@ -2120,16 +2116,16 @@
#else
typedef struct ccsr_gur {
u32 porpllsr; /* POR PLL ratio status */
-#ifdef CONFIG_MPC8536
+#ifdef CONFIG_ARCH_MPC8536
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
& MPC85xx_PORDEVSR2_DDR_SPD_0) \
>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
#else
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#else
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
@@ -2150,7 +2146,7 @@
#define PORBMSR_ROMLOC_NOR 0xf
u32 porimpscr; /* POR I/O impedance status & control */
u32 pordevsr; /* POR I/O device status regsiter */
-#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#if defined(CONFIG_ARCH_P1023)
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
@@ -2162,26 +2158,26 @@
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#define MPC85xx_PORDEVSR_PCI1 0x00800000
-#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
-#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#elif defined(CONFIG_ARCH_P1023)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
-#if defined(CONFIG_P1010)
+#if defined(CONFIG_ARCH_P1010)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
-#elif defined(CONFIG_BSC9132)
+#elif defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
-#endif /* if defined(CONFIG_P1010) */
+#endif /* if defined(CONFIG_ARCH_P1010) */
#endif
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
@@ -2193,7 +2189,7 @@
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
u32 pordbgmsr; /* POR debug mode status */
u32 pordevsr2; /* POR I/O device status 2 */
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
#endif
@@ -2203,14 +2199,14 @@
u8 res1[8];
u32 gpporcr; /* General-purpose POR configuration */
u8 res2[12];
-#if defined(CONFIG_MPC8536)
+#if defined(CONFIG_ARCH_MPC8536)
u32 gencfgr; /* General Configuration Register */
#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
#else
u32 gpiocr; /* GPIO control */
#endif
u8 res3[12];
-#if defined(CONFIG_MPC8569)
+#if defined(CONFIG_ARCH_MPC8569)
u32 plppar1; /* Platform port pin assignment 1 */
u32 plppar2; /* Platform port pin assignment 2 */
u32 plpdir1; /* Platform port pin direction 1 */
@@ -2222,7 +2218,7 @@
u32 gpindr; /* General-purpose input data */
u8 res5[12];
u32 pmuxcr; /* Alt. function signal multiplex control */
-#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#if defined(CONFIG_ARCH_P1010)
#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
@@ -2268,7 +2264,7 @@
#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
#endif
-#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#if defined(CONFIG_ARCH_P1023)
#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
#else
#define MPC85xx_PMUXCR_SD_DATA 0x80000000
@@ -2290,13 +2286,13 @@
#define MPC85xx_PMUXCR_QE11 0x00000010
#define MPC85xx_PMUXCR_QE12 0x00000008
#endif
-#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
#define MPC85xx_PMUXCR_TDM 0x00014800
#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
#define MPC85xx_PMUXCR_SPI 0x00000000
#endif
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
@@ -2340,17 +2336,17 @@
#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
#endif
-#ifdef CONFIG_BSC9132
+#ifdef CONFIG_ARCH_BSC9132
#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
#endif
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
#define MPC85xx_PMUXCR_SPI 0x00000000
#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
-#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#if defined(CONFIG_ARCH_P1010)
#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
@@ -2375,12 +2371,12 @@
#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
#endif
-#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
#define MPC85xx_PMUXCR2_USB 0x00150000
#endif
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
@@ -2425,7 +2421,7 @@
#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
#endif
u32 pmuxcr3;
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
@@ -2441,7 +2437,7 @@
#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
#endif
-#ifdef CONFIG_BSC9132
+#ifdef CONFIG_ARCH_BSC9132
#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
@@ -2484,11 +2480,11 @@
u32 svr; /* System version */
u8 res10[8];
u32 rstcr; /* Reset control */
-#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
+#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
u8 res11a[76];
par_io_t qe_par_io[7];
u8 res11b[1600];
-#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
u8 res11a[12];
u32 iovselsr;
u8 res11b[60];
@@ -2504,7 +2500,7 @@
u32 ddrdllcr; /* DDR DLL control */
u8 res14[12];
u32 lbcdllcr; /* LBC DLL control */
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
u8 res15[12];
u32 halt_req_mask;
#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
@@ -2883,8 +2879,8 @@
#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
-#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
- && !defined(CONFIG_PPC_B4420)
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
+ !defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
@@ -2940,7 +2936,7 @@
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
-#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
+#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
#else
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
@@ -2953,6 +2949,8 @@
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
+#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
+#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
#ifdef CONFIG_TSECV2
#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
#elif defined(CONFIG_TSECV2_1)
@@ -2962,7 +2960,7 @@
#endif
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
#else
@@ -2986,7 +2984,7 @@
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
-#if defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
(CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index b078569..1fbc63a 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -1195,7 +1195,7 @@
#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
-#ifdef CONFIG_MPC8610
+#ifdef CONFIG_ARCH_MPC8610
#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
#else
#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fdfca90..fbf72bb 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1048,7 +1048,7 @@
#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
-#ifdef CONFIG_MPC8536
+#ifdef CONFIG_ARCH_MPC8536
#define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/
#else
#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index ef15e7a..17c5ed1 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -38,6 +38,11 @@
#define CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024)
#endif
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
static void boot_jump_linux(bootm_headers_t *images)
{
void (*kernel)(bd_t *, ulong r4, ulong r5, ulong r6,
diff --git a/arch/powerpc/lib/ppcstring.S b/arch/powerpc/lib/ppcstring.S
index 56bb3b8..4f60108 100644
--- a/arch/powerpc/lib/ppcstring.S
+++ b/arch/powerpc/lib/ppcstring.S
@@ -6,7 +6,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <ppc_asm.tmpl>
-#include <asm/errno.h>
+#include <linux/errno.h>
.globl strcpy
strcpy:
diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c
index 0e486cc..080b978 100644
--- a/arch/powerpc/lib/spl.c
+++ b/arch/powerpc/lib/spl.c
@@ -17,14 +17,14 @@
* arg: Pointer to paramter image in RAM
*/
#ifdef CONFIG_SPL_OS_BOOT
-void __noreturn jump_to_image_linux(void *arg)
+void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg)
{
debug("Entering kernel arg pointer: 0x%p\n", arg);
typedef void (*image_entry_arg_t)(void *, ulong r4, ulong r5, ulong r6,
ulong r7, ulong r8, ulong r9)
__attribute__ ((noreturn));
image_entry_arg_t image_entry =
- (image_entry_arg_t)spl_image.entry_point;
+ (image_entry_arg_t)spl_image->entry_point;
image_entry(arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0);
}
diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index d4c1ee0..f7a6e1a 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -18,14 +18,4 @@
default "sandbox_spl" if SANDBOX_SPL
default "sandbox" if !SANDBOX_SPL
-config PCI
- bool "PCI support"
- help
- Enable support for PCI (Peripheral Interconnect Bus), a type of bus
- used on some devices to allow the CPU to communicate with its
- peripherals.
-
-config DM_KEYBOARD
- default y
-
endmenu
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 2d63dd8..35ea00ce 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -313,21 +313,23 @@
int os_dirent_ls(const char *dirname, struct os_dirent_node **headp)
{
- struct dirent entry, *result;
+ struct dirent *entry;
struct os_dirent_node *head, *node, *next;
struct stat buf;
DIR *dir;
int ret;
char *fname;
int len;
+ int dirlen;
*headp = NULL;
dir = opendir(dirname);
if (!dir)
return -1;
- /* Create a buffer for the maximum filename length */
- len = sizeof(entry.d_name) + strlen(dirname) + 2;
+ /* Create a buffer upfront, with typically sufficient size */
+ dirlen = strlen(dirname) + 2;
+ len = dirlen + 256;
fname = malloc(len);
if (!fname) {
ret = -ENOMEM;
@@ -335,18 +337,26 @@
}
for (node = head = NULL;; node = next) {
- ret = readdir_r(dir, &entry, &result);
- if (ret || !result)
+ errno = 0;
+ entry = readdir(dir);
+ if (!entry) {
+ ret = errno;
break;
- next = malloc(sizeof(*node) + strlen(entry.d_name) + 1);
- if (!next) {
+ }
+ next = malloc(sizeof(*node) + strlen(entry->d_name) + 1);
+ if (dirlen + strlen(entry->d_name) > len) {
+ len = dirlen + strlen(entry->d_name);
+ fname = realloc(fname, len);
+ }
+ if (!next || !fname) {
+ free(next);
os_dirent_free(head);
ret = -ENOMEM;
goto done;
}
next->next = NULL;
- strcpy(next->name, entry.d_name);
- switch (entry.d_type) {
+ strcpy(next->name, entry->d_name);
+ switch (entry->d_type) {
case DT_REG:
next->type = OS_FILET_REG;
break;
@@ -356,6 +366,8 @@
case DT_LNK:
next->type = OS_FILET_LNK;
break;
+ default:
+ next->type = OS_FILET_UNKNOWN;
}
next->size = 0;
snprintf(fname, len, "%s/%s", dirname, next->name);
@@ -363,8 +375,8 @@
next->size = buf.st_size;
if (node)
node->next = next;
- if (!head)
- head = node;
+ else
+ head = next;
}
*headp = head;
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index e8349c0..7cc76d4 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -25,7 +25,8 @@
return BOOT_DEVICE_BOARD;
}
-void spl_board_announce_boot_device(void)
+static int spl_board_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
char fname[256];
int ret;
@@ -33,23 +34,13 @@
ret = os_find_u_boot(fname, sizeof(fname));
if (ret) {
printf("(%s not found, error %d)\n", fname, ret);
- return;
- }
- printf("%s\n", fname);
-}
-
-int spl_board_load_image(void)
-{
- char fname[256];
- int ret;
-
- ret = os_find_u_boot(fname, sizeof(fname));
- if (ret)
return ret;
+ }
/* Hopefully this will not return */
return os_spl_to_uboot(fname);
}
+SPL_LOAD_IMAGE_METHOD("sandbox", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
void spl_board_init(void)
{
diff --git a/arch/sandbox/include/asm/errno.h b/arch/sandbox/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/sandbox/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 6919632..a685635 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -40,12 +40,12 @@
phys_addr_t map_to_sysmem(const void *ptr);
/* Define nops for sandbox I/O access */
-#define readb(addr) 0
-#define readw(addr) 0
-#define readl(addr) 0
-#define writeb(v, addr)
-#define writew(v, addr)
-#define writel(v, addr)
+#define readb(addr) ((void)addr, 0)
+#define readw(addr) ((void)addr, 0)
+#define readl(addr) ((void)addr, 0)
+#define writeb(v, addr) ((void)addr)
+#define writew(v, addr) ((void)addr)
+#define writel(v, addr) ((void)addr)
/* I/O access functions */
int inl(unsigned int addr);
diff --git a/arch/sandbox/include/asm/linkage.h b/arch/sandbox/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/sandbox/include/asm/linkage.h
diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h
index 59f2401..eb3cb56 100644
--- a/arch/sandbox/include/asm/spl.h
+++ b/arch/sandbox/include/asm/spl.h
@@ -8,14 +8,6 @@
#define CONFIG_SPL_BOARD_LOAD_IMAGE
-/**
- * Board-specific load method for boards that have a special way of loading
- * U-Boot, which does not fit with the existing SPL code.
- *
- * @return 0 on success, negative errno value on failure.
- */
-int spl_board_load_image(void);
-
enum {
BOOT_DEVICE_BOARD,
};
diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c
index 0c9a797..4cdd18f 100644
--- a/arch/sandbox/lib/bootm.c
+++ b/arch/sandbox/lib/bootm.c
@@ -50,6 +50,11 @@
return ret;
}
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index ca55fac..14e0b66 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -2,7 +2,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-head-y := arch/sh/cpu/$(CPU)/start.o
+head-y := arch/sh/lib/start.o
libs-y += arch/sh/cpu/$(CPU)/
libs-y += arch/sh/lib/
diff --git a/arch/sh/config.mk b/arch/sh/config.mk
index 0578fa3..71540c8 100644
--- a/arch/sh/config.mk
+++ b/arch/sh/config.mk
@@ -15,6 +15,6 @@
endif
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
-PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
+PLATFORM_RELFLAGS += -fpic
LDFLAGS_FINAL = --gc-sections
PLATFORM_RELFLAGS += -ffixed-r13
diff --git a/arch/sh/cpu/sh2/Makefile b/arch/sh/cpu/sh2/Makefile
index a19ed5e..80fff49 100644
--- a/arch/sh/cpu/sh2/Makefile
+++ b/arch/sh/cpu/sh2/Makefile
@@ -8,5 +8,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-extra-y = start.o
obj-y = cpu.o interrupts.o watchdog.o
diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
index 9a93cf5..a2f856f 100644
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -83,9 +83,3 @@
{
return 0;
}
-
-void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
-{
- /* TODO(sh maintainer): Implement this */
- while (1);
-}
diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S
deleted file mode 100644
index 6171edc..0000000
--- a/arch/sh/cpu/sh2/start.S
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Renesas Solutions Corp.
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-
- .text
- .align 2
-
- .global _start
-_sh_start:
- .long 0x00000010 /* Ppower ON reset PC*/
- .long 0x00000000
- .long 0x00000010 /* Manual reset PC */
- .long 0x00000000
-_init:
- mov.l ._lowlevel_init, r0
-100: bsrf r0
- nop
- bsr 1f
- nop
-1: sts pr, r5
- mov.l ._reloc_dst, r4
- add #(_sh_start-1b), r5
- mov.l ._reloc_dst_end, r6
-
-2: mov.l @r5+, r1
- mov.l r1, @r4
- add #4, r4
- cmp/hs r6, r4
- bf 2b
-
- mov.l ._bss_start, r4
- mov.l ._bss_end, r5
- mov #0, r1
-
-3: mov.l r1, @r4 /* bss clear */
- add #4, r4
- cmp/hs r5, r4
- bf 3b
-
- mov.l ._gd_init, r13 /* global data */
- mov.l ._stack_init, r15 /* stack */
-
- #TODO(sh maintainer): Fix this up to call the correct code
- #mov.l ._sh_generic_init, r0
- #jsr @r0
- nop
-
-loop:
- bra loop
-
- .align 2
-
-._lowlevel_init: .long (lowlevel_init - (100b + 4))
-._reloc_dst: .long reloc_dst
-._reloc_dst_end: .long reloc_dst_end
-._bss_start: .long bss_start
-._bss_end: .long bss_end
-._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
-._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-#._sh_generic_init: .long sh_generic_init
diff --git a/arch/sh/cpu/sh3/Makefile b/arch/sh/cpu/sh3/Makefile
index 1dccaf9..cddc15b 100644
--- a/arch/sh/cpu/sh3/Makefile
+++ b/arch/sh/cpu/sh3/Makefile
@@ -11,5 +11,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-extra-y = start.o
-obj-y = cpu.o interrupts.o watchdog.o cache.o
+obj-y = cpu.o interrupts.o watchdog.o
diff --git a/arch/sh/cpu/sh3/cache.c b/arch/sh/cpu/sh3/cache.c
deleted file mode 100644
index 34cbbff..0000000
--- a/arch/sh/cpu/sh3/cache.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-/*
- * Jump to P2 area.
- * When handling TLB or caches, we need to do it from P2 area.
- */
-#define jump_to_P2() \
- do { \
- unsigned long __dummy; \
- __asm__ __volatile__( \
- "mov.l 1f, %0\n\t" \
- "or %1, %0\n\t" \
- "jmp @%0\n\t" \
- " nop\n\t" \
- ".balign 4\n" \
- "1: .long 2f\n" \
- "2:" \
- : "=&r" (__dummy) \
- : "r" (0x20000000)); \
- } while (0)
-
-/*
- * Back to P1 area.
- */
-#define back_to_P1() \
- do { \
- unsigned long __dummy; \
- __asm__ __volatile__( \
- "nop;nop;nop;nop;nop;nop;nop\n\t" \
- "mov.l 1f, %0\n\t" \
- "jmp @%0\n\t" \
- " nop\n\t" \
- ".balign 4\n" \
- "1: .long 2f\n" \
- "2:" \
- : "=&r" (__dummy)); \
- } while (0)
-
-#define CACHE_VALID 1
-#define CACHE_UPDATED 2
-
-static inline void cache_wback_all(void)
-{
- unsigned long addr, data, i, j;
-
- jump_to_P2();
- for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
- for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
- addr = CACHE_OC_ADDRESS_ARRAY
- | (j << CACHE_OC_WAY_SHIFT)
- | (i << CACHE_OC_ENTRY_SHIFT);
- data = inl(addr);
- if (data & CACHE_UPDATED) {
- data &= ~CACHE_UPDATED;
- outl(data, addr);
- }
- }
- }
- back_to_P1();
-}
-
-
-#define CACHE_ENABLE 0
-#define CACHE_DISABLE 1
-
-int cache_control(unsigned int cmd)
-{
- unsigned long ccr;
-
- jump_to_P2();
- ccr = inl(CCR);
-
- if (ccr & CCR_CACHE_ENABLE)
- cache_wback_all();
-
- if (cmd == CACHE_DISABLE)
- outl(CCR_CACHE_STOP, CCR);
- else
- outl(CCR_CACHE_INIT, CCR);
- back_to_P1();
-
- return 0;
-}
diff --git a/arch/sh/cpu/sh3/cpu.c b/arch/sh/cpu/sh3/cpu.c
index 494f908..ea0006a 100644
--- a/arch/sh/cpu/sh3/cpu.c
+++ b/arch/sh/cpu/sh3/cpu.c
@@ -66,9 +66,3 @@
{
return 0;
}
-
-void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
-{
- /* TODO(sh maintainer): Implement this */
- while (1);
-}
diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S
deleted file mode 100644
index 9ed7198..0000000
--- a/arch/sh/cpu/sh3/start.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-
- .text
- .align 2
-
- .global _start
-_sh_start:
- mov.l ._lowlevel_init, r0
-100: bsrf r0
- nop
-
- bsr 1f
- nop
-1: sts pr, r5
- mov.l ._reloc_dst, r4
- add #(_sh_start-1b), r5
- mov.l ._reloc_dst_end, r6
-
-2: mov.l @r5+, r1
- mov.l r1, @r4
- add #4, r4
- cmp/hs r6, r4
- bf 2b
-
- mov.l ._bss_start, r4
- mov.l ._bss_end, r5
- mov #0, r1
-
-3: mov.l r1, @r4 /* bss clear */
- add #4, r4
- cmp/hs r5, r4
- bf 3b
-
- mov.l ._gd_init, r13 /* global data */
- mov.l ._stack_init, r15 /* stack */
-
- #TODO(sh maintainer): Fix this up to call the correct code
- #mov.l ._sh_generic_init, r0
- #jsr @r0
- nop
-
-loop:
- bra loop
-
- .align 2
-
-._lowlevel_init: .long (lowlevel_init - (100b + 4))
-._reloc_dst: .long reloc_dst
-._reloc_dst_end: .long reloc_dst_end
-._bss_start: .long bss_start
-._bss_end: .long bss_end
-._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
-._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-#._sh_generic_init: .long sh_generic_init
diff --git a/arch/sh/cpu/sh4/Makefile b/arch/sh/cpu/sh4/Makefile
index 38c6188..976994b 100644
--- a/arch/sh/cpu/sh4/Makefile
+++ b/arch/sh/cpu/sh4/Makefile
@@ -8,5 +8,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-extra-y = start.o
obj-y = cpu.o interrupts.o watchdog.o cache.o
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c
index e1ee970..6175c67 100644
--- a/arch/sh/cpu/sh4/cache.c
+++ b/arch/sh/cpu/sh4/cache.c
@@ -1,50 +1,15 @@
/*
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com>
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
-#include <asm/processor.h>
#include <asm/io.h>
-
-/*
- * Jump to P2 area.
- * When handling TLB or caches, we need to do it from P2 area.
- */
-#define jump_to_P2() \
- do { \
- unsigned long __dummy; \
- __asm__ __volatile__( \
- "mov.l 1f, %0\n\t" \
- "or %1, %0\n\t" \
- "jmp @%0\n\t" \
- " nop\n\t" \
- ".balign 4\n" \
- "1: .long 2f\n" \
- "2:" \
- : "=&r" (__dummy) \
- : "r" (0x20000000)); \
- } while (0)
-
-/*
- * Back to P1 area.
- */
-#define back_to_P1() \
- do { \
- unsigned long __dummy; \
- __asm__ __volatile__( \
- "nop;nop;nop;nop;nop;nop;nop\n\t" \
- "mov.l 1f, %0\n\t" \
- "jmp @%0\n\t" \
- " nop\n\t" \
- ".balign 4\n" \
- "1: .long 2f\n" \
- "2:" \
- : "=&r" (__dummy)); \
- } while (0)
+#include <asm/processor.h>
+#include <asm/system.h>
#define CACHE_VALID 1
#define CACHE_UPDATED 2
@@ -53,10 +18,10 @@
{
unsigned long addr, data, i, j;
- jump_to_P2();
- for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){
+ for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
- addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT)
+ addr = CACHE_OC_ADDRESS_ARRAY
+ | (j << CACHE_OC_WAY_SHIFT)
| (i << CACHE_OC_ENTRY_SHIFT);
data = inl(addr);
if (data & CACHE_UPDATED) {
@@ -65,14 +30,12 @@
}
}
}
- back_to_P1();
}
-
#define CACHE_ENABLE 0
#define CACHE_DISABLE 1
-int cache_control(unsigned int cmd)
+static int cache_control(unsigned int cmd)
{
unsigned long ccr;
@@ -97,7 +60,7 @@
start &= ~(L1_CACHE_BYTES - 1);
for (v = start; v < end; v += L1_CACHE_BYTES) {
- asm volatile ("ocbwb %0" : /* no output */
+ asm volatile ("ocbp %0" : /* no output */
: "m" (__m(v)));
}
}
@@ -112,3 +75,36 @@
: "m" (__m(v)));
}
}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ flush_dcache_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+ cache_control(CACHE_ENABLE);
+}
+
+void icache_disable(void)
+{
+ cache_control(CACHE_DISABLE);
+}
+
+int icache_status(void)
+{
+ return 0;
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+ return 0;
+}
diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c
index de90ca7..aa8d4df 100644
--- a/arch/sh/cpu/sh4/cpu.c
+++ b/arch/sh/cpu/sh4/cpu.c
@@ -9,7 +9,6 @@
#include <command.h>
#include <netdev.h>
#include <asm/processor.h>
-#include <asm/cache.h>
int checkcpu(void)
{
@@ -35,39 +34,6 @@
return 0;
}
-void flush_cache (unsigned long addr, unsigned long size)
-{
- invalidate_dcache_range(addr , addr + size);
-}
-
-void icache_enable (void)
-{
- cache_control(0);
-}
-
-void icache_disable (void)
-{
- cache_control(1);
-}
-
-int icache_status (void)
-{
- return 0;
-}
-
-void dcache_enable (void)
-{
-}
-
-void dcache_disable (void)
-{
-}
-
-int dcache_status (void)
-{
- return 0;
-}
-
int cpu_eth_init(bd_t *bis)
{
#ifdef CONFIG_SH_ETHER
@@ -75,9 +41,3 @@
#endif
return 0;
}
-
-void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
-{
- /* TODO(sh maintainer): Implement this */
- while (1);
-}
diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S
deleted file mode 100644
index 77fc221..0000000
--- a/arch/sh/cpu/sh4/start.S
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * (C) Copyright 2007, 2010
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-
- .text
- .align 2
-
- .global _start
-_sh_start:
- mov.l ._lowlevel_init, r0
-100: bsrf r0
- nop
-
- bsr 1f
- nop
-1: sts pr, r5
- mov.l ._reloc_dst, r4
- add #(_sh_start-1b), r5
- mov.l ._reloc_dst_end, r6
-
-2: mov.l @r5+, r1
- mov.l r1, @r4
- add #4, r4
- cmp/hs r6, r4
- bf 2b
-
- mov.l ._bss_start, r4
- mov.l ._bss_end, r5
- mov #0, r1
-
-3: mov.l r1, @r4 /* bss clear */
- add #4, r4
- cmp/hs r5, r4
- bf 3b
-
- mov.l ._gd_init, r13 /* global data */
- mov.l ._stack_init, r15 /* stack */
-
- #TODO(sh maintainer): Fix this up to call the correct code
- #mov.l ._sh_generic_init, r0
- #jsr @r0
- nop
-
-loop:
- bra loop
-
- .align 2
-
-._lowlevel_init: .long (lowlevel_init - (100b + 4))
-._reloc_dst: .long reloc_dst
-._reloc_dst_end: .long reloc_dst_end
-._bss_start: .long bss_start
-._bss_end: .long bss_end
-._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
-._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-#._sh_generic_init: .long sh_generic_init
diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds
index 78611c2..bbf9ff4 100644
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@@ -1,26 +1,27 @@
/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2008-2009
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyright (C) 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
+ * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ * Copyright (C) 2008 Mark Jonas <mark.jonas@de.bosch.com>
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include "config.h"
+
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE
+}
+
ENTRY(_start)
SECTIONS
{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
+ reloc_dst = .;
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
@@ -29,6 +30,8 @@
.text :
{
KEEP(*/start.o (.text))
+ KEEP(CONFIG_BOARDDIR/lowlevel_init.o (.text .spiboot1.text))
+ KEEP(*(.spiboot2.text))
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
@@ -36,13 +39,13 @@
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
- } =0xFF
+ } >ram =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
. = ALIGN(4);
- }
+ } >ram
PROVIDE (_etext = .);
@@ -51,25 +54,23 @@
{
*(.data)
. = ALIGN(4);
- }
+ } >ram
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
- *(.got)
+ *(.got.plt) *(.got)
. = ALIGN(4);
- }
+ } >ram
PROVIDE (_egot = .);
-
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
- }
+ } >ram
PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
@@ -77,8 +78,7 @@
{
*(.bss)
. = ALIGN(4);
- }
+ } >ram
PROVIDE (bss_end = .);
-
PROVIDE (__bss_end = .);
}
diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
index abaf405..b548a35 100644
--- a/arch/sh/include/asm/cache.h
+++ b/arch/sh/include/asm/cache.h
@@ -3,8 +3,6 @@
#if defined(CONFIG_CPU_SH4)
-int cache_control(unsigned int cmd);
-
#define L1_CACHE_BYTES 32
struct __large_struct { unsigned long buf[100]; };
diff --git a/arch/sh/include/asm/errno.h b/arch/sh/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/sh/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 5dc27be..5cb000c 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -68,13 +68,6 @@
#define __raw_base_readl(base, off) __arch_base_getl(base, off)
/*
- * Now, pick up the machine-defined IO definitions
- */
-#if 0 /* XXX###XXX */
-#include <asm/arch/io.h>
-#endif /* XXX###XXX */
-
-/*
* IO port access primitives
* -------------------------
*
@@ -82,9 +75,6 @@
* mapped. Note that these are defined to perform little endian accesses
* only. Their primary purpose is to access PCI and ISA peripherals.
*
- * The machine specific io.h include defines __io to translate an "IO"
- * address to a memory address.
- *
* Note that we prevent GCC re-ordering or caching values in expressions
* by introducing sequence points into the in*() definitions. Note that
* __raw_* do not guarantee this behaviour.
diff --git a/arch/sh/include/asm/linkage.h b/arch/sh/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/sh/include/asm/linkage.h
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index c5cf89f..473cf0d 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -5,7 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
+extra-y += start.o
+obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
ifeq ($(CONFIG_CPU_SH2),y)
obj-y += time_sh2.o
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
new file mode 100644
index 0000000..aa967c0
--- /dev/null
+++ b/arch/sh/lib/board.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr)
+{
+ void (*reloc_board_init_r)(gd_t *gd, ulong dest) = board_init_r;
+
+ if (new_gd->reloc_off) {
+ memcpy((void *)new_gd->relocaddr,
+ (void *)(new_gd->relocaddr - new_gd->reloc_off),
+ new_gd->mon_len);
+
+ reloc_board_init_r += new_gd->reloc_off;
+ }
+
+ __asm__ __volatile__("mov.l %0, r15\n" : : "m" (new_gd->start_addr_sp));
+
+ while (1)
+ reloc_board_init_r(new_gd, 0x0);
+}
diff --git a/arch/sh/lib/start.S b/arch/sh/lib/start.S
new file mode 100644
index 0000000..37d38d5
--- /dev/null
+++ b/arch/sh/lib/start.S
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2007, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+
+ .text
+ .align 2
+
+ .global _start
+_start:
+#ifdef CONFIG_CPU_SH2
+ .long 0x00000010 /* Ppower ON reset PC*/
+ .long 0x00000000
+ .long 0x00000010 /* Manual reset PC */
+ .long 0x00000000
+#endif
+ mov.l ._lowlevel_init, r0
+100: bsrf r0
+ nop
+
+ bsr 1f
+ nop
+1: sts pr, r5
+ mov.l ._reloc_dst, r4
+ add #(_start-1b), r5
+ mov.l ._reloc_dst_end, r6
+
+2: mov.l @r5+, r1
+ mov.l r1, @r4
+ add #4, r4
+ cmp/hs r6, r4
+ bf 2b
+
+ mov.l ._bss_start, r4
+ mov.l ._bss_end, r5
+ mov #0, r1
+
+3: mov.l r1, @r4 /* bss clear */
+ add #4, r4
+ cmp/hs r5, r4
+ bf 3b
+
+ mov.l ._gd_init, r13 /* global data */
+ mov.l ._stack_init, r15 /* stack */
+
+ mov.l ._sh_generic_init, r0
+ jsr @r0
+ mov #0, r4
+
+loop:
+ bra loop
+
+ .align 2
+
+._lowlevel_init: .long (lowlevel_init - (100b + 4))
+._reloc_dst: .long _start
+._reloc_dst_end: .long reloc_dst_end
+._bss_start: .long bss_start
+._bss_end: .long bss_end
+._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
+._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
+._sh_generic_init: .long board_init_f
diff --git a/arch/sparc/include/asm/errno.h b/arch/sparc/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/sparc/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/sparc/include/asm/linkage.h b/arch/sparc/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/sparc/include/asm/linkage.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5193ee7..0884af2 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -461,33 +461,6 @@
by the operating system. It defines platform-independent interfaces
for configuration and power management monitoring.
-config GENERATE_SMBIOS_TABLE
- bool "Generate an SMBIOS (System Management BIOS) table"
- default y
- help
- The System Management BIOS (SMBIOS) specification addresses how
- motherboard and system vendors present management information about
- their products in a standard format by extending the BIOS interface
- on Intel architecture systems.
-
- Check http://www.dmtf.org/standards/smbios for details.
-
-config SMBIOS_MANUFACTURER
- string "SMBIOS Manufacturer"
- depends on GENERATE_SMBIOS_TABLE
- default SYS_VENDOR
- help
- The board manufacturer to store in SMBIOS structures.
- Change this to override the default one (CONFIG_SYS_VENDOR).
-
-config SMBIOS_PRODUCT_NAME
- string "SMBIOS Product Name"
- depends on GENERATE_SMBIOS_TABLE
- default SYS_BOARD
- help
- The product name to store in SMBIOS structures.
- Change this to override the default one (CONFIG_SYS_BOARD).
-
endmenu
config MAX_PIRQ_LINKS
@@ -546,12 +519,6 @@
Intel 8254 timer contains three counters which have fixed uses.
Include this to have U-Boot set up the timer correctly.
-config I8042_KEYB
- default y
-
-config DM_KEYBOARD
- default y
-
config SEABIOS
bool "Support booting SeaBIOS"
help
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index d7addd8..1697dca 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -45,8 +45,8 @@
EFIPAYLOAD_BFDARCH = i386
-LDSCRIPT_EFI := $(srctree)/$(CPUDIR)/efi/elf_$(EFIARCH)_efi.lds
-EFISTUB := crt0-efi-$(EFIARCH).o reloc_$(EFIARCH).o
+LDSCRIPT_EFI := $(srctree)/arch/x86/lib/elf_$(EFIARCH)_efi.lds
+EFISTUB := crt0_$(EFIARCH)_efi.o reloc_$(EFIARCH)_efi.o
OBJCOPYFLAGS_EFI += --target=efi-app-$(EFIARCH)
CPPFLAGS_REMOVE_crt0-efi-$(EFIARCH).o += $(CFLAGS_NON_EFI)
@@ -65,3 +65,19 @@
LDFLAGS_FINAL += --gc-sections -pie
endif
+
+ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
+
+ifneq ($(CONFIG_EFI_STUB_64BIT),)
+EFI_LDS := elf_x86_64_efi.lds
+EFI_CRT0 := crt0_x86_64_efi.o
+EFI_RELOC := reloc_x86_64_efi.o
+EFI_TARGET := --target=efi-app-ia32
+else
+EFI_LDS := elf_ia32_efi.lds
+EFI_CRT0 := crt0_ia32_efi.o
+EFI_RELOC := reloc_ia32_efi.o
+EFI_TARGET := --target=efi-app-x86_64
+endif
+
+endif
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 2667e0b..f5b8c9e 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -10,7 +10,7 @@
extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y += interrupts.o cpu.o cpu_x86.o call64.o
+obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o
AFLAGS_REMOVE_call32.o := -mregparm=3 \
$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 2837709..0bb0852 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -189,6 +189,7 @@
.get_desc = cpu_x86_get_desc,
.get_info = baytrail_get_info,
.get_count = baytrail_get_count,
+ .get_vendor = cpu_x86_get_vendor,
};
static const struct udevice_id cpu_x86_baytrail_ids[] = {
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index b31f24e..87ba849 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -12,8 +12,9 @@
#include <asm/post.h>
static struct pci_device_id mmc_supported[] = {
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 },
{},
};
@@ -25,15 +26,9 @@
#ifndef CONFIG_EFI_APP
int arch_cpu_init(void)
{
- int ret;
-
post_code(POST_CPU_INIT);
- ret = x86_cpu_init_f();
- if (ret)
- return ret;
-
- return 0;
+ return x86_cpu_init_f();
}
int arch_misc_init(void)
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index 3ba21aa..6977e86 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -743,6 +743,7 @@
.get_desc = cpu_x86_get_desc,
.get_info = broadwell_get_info,
.get_count = broadwell_get_count,
+ .get_vendor = cpu_x86_get_vendor,
};
static const struct udevice_id cpu_x86_broadwell_ids[] = {
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index e7befde..74736cd 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -291,7 +291,6 @@
static const struct udevice_id broadwell_syscon_ids[] = {
{ .compatible = "intel,me", .data = X86_SYSCON_ME },
- { .compatible = "intel,gma", .data = X86_SYSCON_GMA },
{ }
};
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index e0e3c64..4b3601f 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -8,8 +8,4 @@
bool
default y
-config VIDEO_COREBOOT
- bool
- default y
-
endif
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 269043d..7c1d6de 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -135,7 +135,7 @@
struct gdt_ptr gdt;
gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
- gdt.ptr = (u32)boot_gdt;
+ gdt.ptr = (ulong)boot_gdt;
asm volatile("lgdtl %0\n" : : "m" (gdt));
}
@@ -630,13 +630,11 @@
memset(pgtable, '\0', PAGETABLE_SIZE);
/* Level 4 needs a single entry */
- pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+ pgtable[0] = (ulong)&pgtable[1024] + 7;
/* Level 3 has one 64-bit entry for each GiB of memory */
- for (i = 0; i < 4; i++) {
- pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
- 0x1000 * i + 7;
- }
+ for (i = 0; i < 4; i++)
+ pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
for (i = 0; i < 2048; i++)
diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c
index 0941041..157f3de 100644
--- a/arch/x86/cpu/cpu_x86.c
+++ b/arch/x86/cpu/cpu_x86.c
@@ -15,9 +15,26 @@
int cpu_x86_bind(struct udevice *dev)
{
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpuid_result res;
plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"intel,apic-id", -1);
+ plat->family = gd->arch.x86;
+ res = cpuid(1);
+ plat->id[0] = res.eax;
+ plat->id[1] = res.edx;
+
+ return 0;
+}
+
+int cpu_x86_get_vendor(struct udevice *dev, char *buf, int size)
+{
+ const char *vendor = cpu_vendor_name(gd->arch.x86_vendor);
+
+ if (size < (strlen(vendor) + 1))
+ return -ENOSPC;
+
+ strcpy(buf, vendor);
return 0;
}
@@ -60,6 +77,7 @@
static const struct cpu_ops cpu_x86_ops = {
.get_desc = cpu_x86_get_desc,
.get_count = cpu_x86_get_count,
+ .get_vendor = cpu_x86_get_vendor,
};
static const struct udevice_id cpu_x86_ids[] = {
diff --git a/arch/x86/cpu/efi/elf_ia32_efi.lds b/arch/x86/cpu/efi/elf_ia32_efi.lds
deleted file mode 100644
index cd3b0a9..0000000
--- a/arch/x86/cpu/efi/elf_ia32_efi.lds
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * U-Boot EFI linker script
- *
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Modified from usr/lib32/elf_ia32_efi.lds in gnu-efi
- */
-
-#include <config.h>
-
-OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
-OUTPUT_ARCH(i386)
-ENTRY(_start)
-SECTIONS
-{
- image_base = .;
- .hash : { *(.hash) } /* this MUST come first, EFI expects it */
- . = ALIGN(4096);
- .text :
- {
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t.*)
- }
- . = ALIGN(4096);
- .sdata :
- {
- *(.got.plt)
- *(.got)
- *(.srodata)
- *(.sdata)
- *(.sbss)
- *(.scommon)
- }
- . = ALIGN(4096);
- .data :
- {
- *(.rodata*)
- *(.data)
- *(.data1)
- *(.data.*)
- *(.sdata)
- *(.got.plt)
- *(.got)
- /*
- * the EFI loader doesn't seem to like a .bss section, so we
- * stick it all into .data:
- */
- *(.sbss)
- *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
-
- /* U-Boot lists and device tree */
- . = ALIGN(8);
- *(SORT(.u_boot_list*));
- . = ALIGN(8);
- *(.dtb*);
- }
-
- . = ALIGN(4096);
- .dynamic : { *(.dynamic) }
- . = ALIGN(4096);
- .rel :
- {
- *(.rel.data)
- *(.rel.data.*)
- *(.rel.got)
- *(.rel.stab)
- *(.data.rel.ro.local)
- *(.data.rel.local)
- *(.data.rel.ro)
- *(.data.rel*)
- *(.rel.u_boot_list*)
- }
- . = ALIGN(4096);
- .reloc : /* This is the PECOFF .reloc section! */
- {
- *(.reloc)
- }
- . = ALIGN(4096);
- .dynsym : { *(.dynsym) }
- . = ALIGN(4096);
- .dynstr : { *(.dynstr) }
- . = ALIGN(4096);
- /DISCARD/ :
- {
- *(.rel.reloc)
- *(.eh_frame)
- *(.note.GNU-stack)
- }
- .comment 0 : { *(.comment) }
-}
diff --git a/arch/x86/cpu/efi/elf_x86_64_efi.lds b/arch/x86/cpu/efi/elf_x86_64_efi.lds
deleted file mode 100644
index 9d9f057..0000000
--- a/arch/x86/cpu/efi/elf_x86_64_efi.lds
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * U-Boot EFI linker script
- *
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Modified from usr/lib32/elf_x86_64_efi.lds in gnu-efi
- */
-
-#include <config.h>
-
-OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64")
-OUTPUT_ARCH(i386:x86-64)
-ENTRY(_start)
-SECTIONS
-{
- image_base = .;
- .hash : { *(.hash) } /* this MUST come first, EFI expects it */
- . = ALIGN(4096);
- .eh_frame : {
- *(.eh_frame)
- }
-
- . = ALIGN(4096);
-
- .text : {
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t.*)
- }
-
- . = ALIGN(4096);
-
- .reloc : {
- *(.reloc)
- }
-
- . = ALIGN(4096);
-
- .data : {
- *(.rodata*)
- *(.got.plt)
- *(.got)
- *(.data*)
- *(.sdata)
- /* the EFI loader doesn't seem to like a .bss section, so we stick
- * it all into .data: */
- *(.sbss)
- *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- *(.rel.local)
-
- /* U-Boot lists and device tree */
- . = ALIGN(8);
- *(SORT(.u_boot_list*));
- . = ALIGN(8);
- *(.dtb*);
- }
-
- . = ALIGN(4096);
- .dynamic : { *(.dynamic) }
- . = ALIGN(4096);
-
- .rela : {
- *(.rela.data*)
- *(.rela.got)
- *(.rela.stab)
- }
-
- . = ALIGN(4096);
- .dynsym : { *(.dynsym) }
- . = ALIGN(4096);
- .dynstr : { *(.dynstr) }
- . = ALIGN(4096);
- .ignored.reloc : {
- *(.rela.reloc)
- *(.eh_frame)
- *(.note.GNU-stack)
- }
-
- .comment 0 : { *(.comment) }
-}
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index dd2819a..5f6cdd3 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -182,8 +182,8 @@
void set_vector(u8 intnum, void *routine)
{
- idt[intnum].base_high = (u16)((u32)(routine) >> 16);
- idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
+ idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
+ idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
}
/*
@@ -238,8 +238,11 @@
{
long flags;
+#ifdef CONFIG_X86_64
+ asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
+#else
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
-
+#endif
return flags & X86_EFLAGS_IF;
}
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index df3cd0a..9364410 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -103,11 +103,12 @@
/* extract the bdf from fdt_pci_addr */
priv->bdf = dm_pci_get_bdf(dev->parent);
- ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
+ ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
if (!ret) {
priv->config = PIRQ_VIA_PCI;
} else {
- ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
+ ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
+ "ibase");
if (!ret)
priv->config = PIRQ_VIA_IBASE;
else
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 9cdb07b..498e71a 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -9,7 +9,6 @@
else
obj-y += cpu.o
obj-y += early_me.o
-obj-y += gma.o
obj-y += lpc.o
obj-y += model_206ax.o
obj-y += northbridge.o
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 5b58d6c..e63ea6b 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -9,14 +9,12 @@
#include <fdtdec.h>
#include <malloc.h>
#include <pch.h>
-#include <syscon.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/lpc_common.h>
#include <asm/pci.h>
-#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
@@ -155,22 +153,12 @@
static int bd82x6x_probe(struct udevice *dev)
{
- struct udevice *gma_dev;
- int ret;
-
if (!(gd->flags & GD_FLG_RELOC))
return 0;
/* Cause the SATA device to do its init */
uclass_first_device(UCLASS_AHCI, &dev);
- ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev);
- if (ret)
- return ret;
- ret = gma_func0_init(gma_dev);
- if (ret)
- return ret;
-
return 0;
}
#endif /* CONFIG_HAVE_FSP */
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index cda96ab..5435a92 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -162,7 +162,6 @@
static const struct udevice_id ivybridge_syscon_ids[] = {
{ .compatible = "intel,me", .data = X86_SYSCON_ME },
- { .compatible = "intel,gma", .data = X86_SYSCON_GMA },
{ }
};
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
deleted file mode 100644
index 37e2e6e..0000000
--- a/arch/x86/cpu/ivybridge/gma.c
+++ /dev/null
@@ -1,850 +0,0 @@
-/*
- * From Coreboot file of the same name
- *
- * Copyright (C) 2011 Chromium OS Authors
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <bios_emul.h>
-#include <dm.h>
-#include <errno.h>
-#include <fdtdec.h>
-#include <pci_rom.h>
-#include <asm/intel_regs.h>
-#include <asm/io.h>
-#include <asm/mtrr.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-#include <asm/arch/sandybridge.h>
-
-struct gt_powermeter {
- u16 reg;
- u32 value;
-};
-
-static const struct gt_powermeter snb_pm_gt1[] = {
- { 0xa200, 0xcc000000 },
- { 0xa204, 0x07000040 },
- { 0xa208, 0x0000fe00 },
- { 0xa20c, 0x00000000 },
- { 0xa210, 0x17000000 },
- { 0xa214, 0x00000021 },
- { 0xa218, 0x0817fe19 },
- { 0xa21c, 0x00000000 },
- { 0xa220, 0x00000000 },
- { 0xa224, 0xcc000000 },
- { 0xa228, 0x07000040 },
- { 0xa22c, 0x0000fe00 },
- { 0xa230, 0x00000000 },
- { 0xa234, 0x17000000 },
- { 0xa238, 0x00000021 },
- { 0xa23c, 0x0817fe19 },
- { 0xa240, 0x00000000 },
- { 0xa244, 0x00000000 },
- { 0xa248, 0x8000421e },
- { 0 }
-};
-
-static const struct gt_powermeter snb_pm_gt2[] = {
- { 0xa200, 0x330000a6 },
- { 0xa204, 0x402d0031 },
- { 0xa208, 0x00165f83 },
- { 0xa20c, 0xf1000000 },
- { 0xa210, 0x00000000 },
- { 0xa214, 0x00160016 },
- { 0xa218, 0x002a002b },
- { 0xa21c, 0x00000000 },
- { 0xa220, 0x00000000 },
- { 0xa224, 0x330000a6 },
- { 0xa228, 0x402d0031 },
- { 0xa22c, 0x00165f83 },
- { 0xa230, 0xf1000000 },
- { 0xa234, 0x00000000 },
- { 0xa238, 0x00160016 },
- { 0xa23c, 0x002a002b },
- { 0xa240, 0x00000000 },
- { 0xa244, 0x00000000 },
- { 0xa248, 0x8000421e },
- { 0 }
-};
-
-static const struct gt_powermeter ivb_pm_gt1[] = {
- { 0xa800, 0x00000000 },
- { 0xa804, 0x00021c00 },
- { 0xa808, 0x00000403 },
- { 0xa80c, 0x02001700 },
- { 0xa810, 0x05000200 },
- { 0xa814, 0x00000000 },
- { 0xa818, 0x00690500 },
- { 0xa81c, 0x0000007f },
- { 0xa820, 0x01002501 },
- { 0xa824, 0x00000300 },
- { 0xa828, 0x01000331 },
- { 0xa82c, 0x0000000c },
- { 0xa830, 0x00010016 },
- { 0xa834, 0x01100101 },
- { 0xa838, 0x00010103 },
- { 0xa83c, 0x00041300 },
- { 0xa840, 0x00000b30 },
- { 0xa844, 0x00000000 },
- { 0xa848, 0x7f000000 },
- { 0xa84c, 0x05000008 },
- { 0xa850, 0x00000001 },
- { 0xa854, 0x00000004 },
- { 0xa858, 0x00000007 },
- { 0xa85c, 0x00000000 },
- { 0xa860, 0x00010000 },
- { 0xa248, 0x0000221e },
- { 0xa900, 0x00000000 },
- { 0xa904, 0x00001c00 },
- { 0xa908, 0x00000000 },
- { 0xa90c, 0x06000000 },
- { 0xa910, 0x09000200 },
- { 0xa914, 0x00000000 },
- { 0xa918, 0x00590000 },
- { 0xa91c, 0x00000000 },
- { 0xa920, 0x04002501 },
- { 0xa924, 0x00000100 },
- { 0xa928, 0x03000410 },
- { 0xa92c, 0x00000000 },
- { 0xa930, 0x00020000 },
- { 0xa934, 0x02070106 },
- { 0xa938, 0x00010100 },
- { 0xa93c, 0x00401c00 },
- { 0xa940, 0x00000000 },
- { 0xa944, 0x00000000 },
- { 0xa948, 0x10000e00 },
- { 0xa94c, 0x02000004 },
- { 0xa950, 0x00000001 },
- { 0xa954, 0x00000004 },
- { 0xa960, 0x00060000 },
- { 0xaa3c, 0x00001c00 },
- { 0xaa54, 0x00000004 },
- { 0xaa60, 0x00060000 },
- { 0 }
-};
-
-static const struct gt_powermeter ivb_pm_gt2[] = {
- { 0xa800, 0x10000000 },
- { 0xa804, 0x00033800 },
- { 0xa808, 0x00000902 },
- { 0xa80c, 0x0c002f00 },
- { 0xa810, 0x12000400 },
- { 0xa814, 0x00000000 },
- { 0xa818, 0x00d20800 },
- { 0xa81c, 0x00000002 },
- { 0xa820, 0x03004b02 },
- { 0xa824, 0x00000600 },
- { 0xa828, 0x07000773 },
- { 0xa82c, 0x00000000 },
- { 0xa830, 0x00010032 },
- { 0xa834, 0x1520040d },
- { 0xa838, 0x00020105 },
- { 0xa83c, 0x00083700 },
- { 0xa840, 0x0000151d },
- { 0xa844, 0x00000000 },
- { 0xa848, 0x20001b00 },
- { 0xa84c, 0x0a000010 },
- { 0xa850, 0x00000000 },
- { 0xa854, 0x00000008 },
- { 0xa858, 0x00000008 },
- { 0xa85c, 0x00000000 },
- { 0xa860, 0x00020000 },
- { 0xa248, 0x0000221e },
- { 0xa900, 0x00000000 },
- { 0xa904, 0x00003500 },
- { 0xa908, 0x00000000 },
- { 0xa90c, 0x0c000000 },
- { 0xa910, 0x12000500 },
- { 0xa914, 0x00000000 },
- { 0xa918, 0x00b20000 },
- { 0xa91c, 0x00000000 },
- { 0xa920, 0x08004b02 },
- { 0xa924, 0x00000200 },
- { 0xa928, 0x07000820 },
- { 0xa92c, 0x00000000 },
- { 0xa930, 0x00030000 },
- { 0xa934, 0x050f020d },
- { 0xa938, 0x00020300 },
- { 0xa93c, 0x00903900 },
- { 0xa940, 0x00000000 },
- { 0xa944, 0x00000000 },
- { 0xa948, 0x20001b00 },
- { 0xa94c, 0x0a000010 },
- { 0xa950, 0x00000000 },
- { 0xa954, 0x00000008 },
- { 0xa960, 0x00110000 },
- { 0xaa3c, 0x00003900 },
- { 0xaa54, 0x00000008 },
- { 0xaa60, 0x00110000 },
- { 0 }
-};
-
-static const struct gt_powermeter ivb_pm_gt2_17w[] = {
- { 0xa800, 0x20000000 },
- { 0xa804, 0x000e3800 },
- { 0xa808, 0x00000806 },
- { 0xa80c, 0x0c002f00 },
- { 0xa810, 0x0c000800 },
- { 0xa814, 0x00000000 },
- { 0xa818, 0x00d20d00 },
- { 0xa81c, 0x000000ff },
- { 0xa820, 0x03004b02 },
- { 0xa824, 0x00000600 },
- { 0xa828, 0x07000773 },
- { 0xa82c, 0x00000000 },
- { 0xa830, 0x00020032 },
- { 0xa834, 0x1520040d },
- { 0xa838, 0x00020105 },
- { 0xa83c, 0x00083700 },
- { 0xa840, 0x000016ff },
- { 0xa844, 0x00000000 },
- { 0xa848, 0xff000000 },
- { 0xa84c, 0x0a000010 },
- { 0xa850, 0x00000002 },
- { 0xa854, 0x00000008 },
- { 0xa858, 0x0000000f },
- { 0xa85c, 0x00000000 },
- { 0xa860, 0x00020000 },
- { 0xa248, 0x0000221e },
- { 0xa900, 0x00000000 },
- { 0xa904, 0x00003800 },
- { 0xa908, 0x00000000 },
- { 0xa90c, 0x0c000000 },
- { 0xa910, 0x12000800 },
- { 0xa914, 0x00000000 },
- { 0xa918, 0x00b20000 },
- { 0xa91c, 0x00000000 },
- { 0xa920, 0x08004b02 },
- { 0xa924, 0x00000300 },
- { 0xa928, 0x01000820 },
- { 0xa92c, 0x00000000 },
- { 0xa930, 0x00030000 },
- { 0xa934, 0x15150406 },
- { 0xa938, 0x00020300 },
- { 0xa93c, 0x00903900 },
- { 0xa940, 0x00000000 },
- { 0xa944, 0x00000000 },
- { 0xa948, 0x20001b00 },
- { 0xa94c, 0x0a000010 },
- { 0xa950, 0x00000000 },
- { 0xa954, 0x00000008 },
- { 0xa960, 0x00110000 },
- { 0xaa3c, 0x00003900 },
- { 0xaa54, 0x00000008 },
- { 0xaa60, 0x00110000 },
- { 0 }
-};
-
-static const struct gt_powermeter ivb_pm_gt2_35w[] = {
- { 0xa800, 0x00000000 },
- { 0xa804, 0x00030400 },
- { 0xa808, 0x00000806 },
- { 0xa80c, 0x0c002f00 },
- { 0xa810, 0x0c000300 },
- { 0xa814, 0x00000000 },
- { 0xa818, 0x00d20d00 },
- { 0xa81c, 0x000000ff },
- { 0xa820, 0x03004b02 },
- { 0xa824, 0x00000600 },
- { 0xa828, 0x07000773 },
- { 0xa82c, 0x00000000 },
- { 0xa830, 0x00020032 },
- { 0xa834, 0x1520040d },
- { 0xa838, 0x00020105 },
- { 0xa83c, 0x00083700 },
- { 0xa840, 0x000016ff },
- { 0xa844, 0x00000000 },
- { 0xa848, 0xff000000 },
- { 0xa84c, 0x0a000010 },
- { 0xa850, 0x00000001 },
- { 0xa854, 0x00000008 },
- { 0xa858, 0x00000008 },
- { 0xa85c, 0x00000000 },
- { 0xa860, 0x00020000 },
- { 0xa248, 0x0000221e },
- { 0xa900, 0x00000000 },
- { 0xa904, 0x00003800 },
- { 0xa908, 0x00000000 },
- { 0xa90c, 0x0c000000 },
- { 0xa910, 0x12000800 },
- { 0xa914, 0x00000000 },
- { 0xa918, 0x00b20000 },
- { 0xa91c, 0x00000000 },
- { 0xa920, 0x08004b02 },
- { 0xa924, 0x00000300 },
- { 0xa928, 0x01000820 },
- { 0xa92c, 0x00000000 },
- { 0xa930, 0x00030000 },
- { 0xa934, 0x15150406 },
- { 0xa938, 0x00020300 },
- { 0xa93c, 0x00903900 },
- { 0xa940, 0x00000000 },
- { 0xa944, 0x00000000 },
- { 0xa948, 0x20001b00 },
- { 0xa94c, 0x0a000010 },
- { 0xa950, 0x00000000 },
- { 0xa954, 0x00000008 },
- { 0xa960, 0x00110000 },
- { 0xaa3c, 0x00003900 },
- { 0xaa54, 0x00000008 },
- { 0xaa60, 0x00110000 },
- { 0 }
-};
-
-/*
- * Some vga option roms are used for several chipsets but they only have one
- * PCI ID in their header. If we encounter such an option rom, we need to do
- * the mapping ourselves.
- */
-
-u32 map_oprom_vendev(u32 vendev)
-{
- u32 new_vendev = vendev;
-
- switch (vendev) {
- case 0x80860102: /* GT1 Desktop */
- case 0x8086010a: /* GT1 Server */
- case 0x80860112: /* GT2 Desktop */
- case 0x80860116: /* GT2 Mobile */
- case 0x80860122: /* GT2 Desktop >=1.3GHz */
- case 0x80860126: /* GT2 Mobile >=1.3GHz */
- case 0x80860156: /* IVB */
- case 0x80860166: /* IVB */
- /* Set to GT1 Mobile */
- new_vendev = 0x80860106;
- break;
- }
-
- return new_vendev;
-}
-
-static inline u32 gtt_read(void *bar, u32 reg)
-{
- return readl(bar + reg);
-}
-
-static inline void gtt_write(void *bar, u32 reg, u32 data)
-{
- writel(data, bar + reg);
-}
-
-static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
-{
- for (; pm && pm->reg; pm++)
- gtt_write(bar, pm->reg, pm->value);
-}
-
-#define GTT_RETRY 1000
-static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
-{
- unsigned try = GTT_RETRY;
- u32 data;
-
- while (try--) {
- data = gtt_read(bar, reg);
- if ((data & mask) == value)
- return 1;
- udelay(10);
- }
-
- printf("GT init timeout\n");
- return 0;
-}
-
-static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
-{
- u32 reg32;
-
- debug("GT Power Management Init, silicon = %#x\n", rev);
-
- if (rev < IVB_STEP_C0) {
- /* 1: Enable force wake */
- gtt_write(gtt_bar, 0xa18c, 0x00000001);
- gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
- } else {
- gtt_write(gtt_bar, 0xa180, 1 << 5);
- gtt_write(gtt_bar, 0xa188, 0xffff0001);
- gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
- }
-
- if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
- /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
- reg32 = gtt_read(gtt_bar, 0x42004);
- reg32 |= (1 << 14) | (1 << 15);
- gtt_write(gtt_bar, 0x42004, reg32);
- }
-
- if (rev >= IVB_STEP_A0) {
- /* Display Reset Acknowledge Settings */
- reg32 = gtt_read(gtt_bar, 0x45010);
- reg32 |= (1 << 1) | (1 << 0);
- gtt_write(gtt_bar, 0x45010, reg32);
- }
-
- /* 2: Get GT SKU from GTT+0x911c[13] */
- reg32 = gtt_read(gtt_bar, 0x911c);
- if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
- if (reg32 & (1 << 13)) {
- debug("SNB GT1 Power Meter Weights\n");
- gtt_write_powermeter(gtt_bar, snb_pm_gt1);
- } else {
- debug("SNB GT2 Power Meter Weights\n");
- gtt_write_powermeter(gtt_bar, snb_pm_gt2);
- }
- } else {
- u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
-
- if (reg32 & (1 << 13)) {
- /* GT1 SKU */
- debug("IVB GT1 Power Meter Weights\n");
- gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
- } else {
- /* GT2 SKU */
- u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
- tdp /= (1 << unit);
-
- if (tdp <= 17) {
- /* <=17W ULV */
- debug("IVB GT2 17W Power Meter Weights\n");
- gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
- } else if ((tdp >= 25) && (tdp <= 35)) {
- /* 25W-35W */
- debug("IVB GT2 25W-35W Power Meter Weights\n");
- gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
- } else {
- /* All others */
- debug("IVB GT2 35W Power Meter Weights\n");
- gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
- }
- }
- }
-
- /* 3: Gear ratio map */
- gtt_write(gtt_bar, 0xa004, 0x00000010);
-
- /* 4: GFXPAUSE */
- gtt_write(gtt_bar, 0xa000, 0x00070020);
-
- /* 5: Dynamic EU trip control */
- gtt_write(gtt_bar, 0xa080, 0x00000004);
-
- /* 6: ECO bits */
- reg32 = gtt_read(gtt_bar, 0xa180);
- reg32 |= (1 << 26) | (1 << 31);
- /* (bit 20=1 for SNB step D1+ / IVB A0+) */
- if (rev >= SNB_STEP_D1)
- reg32 |= (1 << 20);
- gtt_write(gtt_bar, 0xa180, reg32);
-
- /* 6a: for SnB step D2+ only */
- if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
- (rev >= SNB_STEP_D2)) {
- reg32 = gtt_read(gtt_bar, 0x9400);
- reg32 |= (1 << 7);
- gtt_write(gtt_bar, 0x9400, reg32);
-
- reg32 = gtt_read(gtt_bar, 0x941c);
- reg32 &= 0xf;
- reg32 |= (1 << 1);
- gtt_write(gtt_bar, 0x941c, reg32);
- gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
- }
-
- if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
- reg32 = gtt_read(gtt_bar, 0x907c);
- reg32 |= (1 << 16);
- gtt_write(gtt_bar, 0x907c, reg32);
-
- /* 6b: Clocking reset controls */
- gtt_write(gtt_bar, 0x9424, 0x00000001);
- } else {
- /* 6b: Clocking reset controls */
- gtt_write(gtt_bar, 0x9424, 0x00000000);
- }
-
- /* 7 */
- if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
- gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
- /* Mailbox Cmd for RC6 VID */
- gtt_write(gtt_bar, 0x138124, 0x80000004);
- if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
- gtt_write(gtt_bar, 0x138124, 0x8000000a);
- gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
- }
-
- /* 8 */
- gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
- gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
- gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
- gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
- gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
- gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
-
- /* 9 */
- gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
- gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
- gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
-
- /* 10 */
- gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
- gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
- gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
- gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
- gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
-
- /* 11 */
- gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
- gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
- gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
- gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
- gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
- gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
- gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
-
- /* 11a: Enable Render Standby (RC6) */
- if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
- /*
- * IvyBridge should also support DeepRenderStandby.
- *
- * Unfortunately it does not work reliably on all SKUs so
- * disable it here and it can be enabled by the kernel.
- */
- gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
- } else {
- gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
- }
-
- /* 12: Normal Frequency Request */
- /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
- reg32 = readl(MCHBAR_REG(0x5998));
- reg32 >>= 16;
- reg32 &= 0xef;
- reg32 <<= 25;
- gtt_write(gtt_bar, 0xa008, reg32);
-
- /* 13: RP Control */
- gtt_write(gtt_bar, 0xa024, 0x00000592);
-
- /* 14: Enable PM Interrupts */
- gtt_write(gtt_bar, 0x4402c, 0x03000076);
-
- /* Clear 0x6c024 [8:6] */
- reg32 = gtt_read(gtt_bar, 0x6c024);
- reg32 &= ~0x000001c0;
- gtt_write(gtt_bar, 0x6c024, reg32);
-
- return 0;
-}
-
-int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
-{
- const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
- u32 reg32, cycle_delay;
-
- debug("GT Power Management Init (post VBIOS)\n");
-
- /* 15: Deassert Force Wake */
- if (rev < IVB_STEP_C0) {
- gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
- gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
- } else {
- gtt_write(gtt_bar, 0xa188, 0x1fffe);
- if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
- gtt_write(gtt_bar, 0xa188,
- gtt_read(gtt_bar, 0xa188) | 1);
- }
- }
-
- /* 16: SW RC Control */
- gtt_write(gtt_bar, 0xa094, 0x00060000);
-
- /* Setup Digital Port Hotplug */
- reg32 = gtt_read(gtt_bar, 0xc4030);
- if (!reg32) {
- u32 dp_hotplug[3];
-
- if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
- dp_hotplug, ARRAY_SIZE(dp_hotplug)))
- return -EINVAL;
-
- reg32 = (dp_hotplug[0] & 0x7) << 2;
- reg32 |= (dp_hotplug[0] & 0x7) << 10;
- reg32 |= (dp_hotplug[0] & 0x7) << 18;
- gtt_write(gtt_bar, 0xc4030, reg32);
- }
-
- /* Setup Panel Power On Delays */
- reg32 = gtt_read(gtt_bar, 0xc7208);
- if (!reg32) {
- reg32 = (unsigned)fdtdec_get_int(blob, node,
- "panel-port-select", 0) << 30;
- reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
- << 16;
- reg32 |= fdtdec_get_int(blob, node,
- "panel-power-backlight-on-delay", 0);
- gtt_write(gtt_bar, 0xc7208, reg32);
- }
-
- /* Setup Panel Power Off Delays */
- reg32 = gtt_read(gtt_bar, 0xc720c);
- if (!reg32) {
- reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
- << 16;
- reg32 |= fdtdec_get_int(blob, node,
- "panel-power-backlight-off-delay", 0);
- gtt_write(gtt_bar, 0xc720c, reg32);
- }
-
- /* Setup Panel Power Cycle Delay */
- cycle_delay = fdtdec_get_int(blob, node,
- "intel,panel-power-cycle-delay", 0);
- if (cycle_delay) {
- reg32 = gtt_read(gtt_bar, 0xc7210);
- reg32 &= ~0xff;
- reg32 |= cycle_delay;
- gtt_write(gtt_bar, 0xc7210, reg32);
- }
-
- /* Enable Backlight if needed */
- reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
- if (reg32) {
- gtt_write(gtt_bar, 0x48250, (1 << 31));
- gtt_write(gtt_bar, 0x48254, reg32);
- }
- reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
- if (reg32) {
- gtt_write(gtt_bar, 0xc8250, (1 << 31));
- gtt_write(gtt_bar, 0xc8254, reg32);
- }
-
- return 0;
-}
-
-/*
- * Some vga option roms are used for several chipsets but they only have one
- * PCI ID in their header. If we encounter such an option rom, we need to do
- * the mapping ourselves.
- */
-
-uint32_t board_map_oprom_vendev(uint32_t vendev)
-{
- switch (vendev) {
- case 0x80860102: /* GT1 Desktop */
- case 0x8086010a: /* GT1 Server */
- case 0x80860112: /* GT2 Desktop */
- case 0x80860116: /* GT2 Mobile */
- case 0x80860122: /* GT2 Desktop >=1.3GHz */
- case 0x80860126: /* GT2 Mobile >=1.3GHz */
- case 0x80860156: /* IVB */
- case 0x80860166: /* IVB */
- return 0x80860106; /* GT1 Mobile */
- }
-
- return vendev;
-}
-
-static int int15_handler(void)
-{
- int res = 0;
-
- debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
-
- switch (M.x86.R_AX) {
- case 0x5f34:
- /*
- * Set Panel Fitting Hook:
- * bit 2 = Graphics Stretching
- * bit 1 = Text Stretching
- * bit 0 = Centering (do not set with bit1 or bit2)
- * 0 = video bios default
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CL = 0x00; /* Use video bios default */
- res = 1;
- break;
- case 0x5f35:
- /*
- * Boot Display Device Hook:
- * bit 0 = CRT
- * bit 1 = TV (eDP)
- * bit 2 = EFP
- * bit 3 = LFP
- * bit 4 = CRT2
- * bit 5 = TV2 (eDP)
- * bit 6 = EFP2
- * bit 7 = LFP2
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0000; /* Use video bios default */
- res = 1;
- break;
- case 0x5f51:
- /*
- * Hook to select active LFP configuration:
- * 00h = No LVDS, VBIOS does not enable LVDS
- * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
- * 02h = SVDO-LVDS, LFP driven by SVDO decoder
- * 03h = eDP, LFP Driven by Int-DisplayPort encoder
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0003; /* eDP */
- res = 1;
- break;
- case 0x5f70:
- switch (M.x86.R_CH) {
- case 0:
- /* Get Mux */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0000;
- res = 1;
- break;
- case 1:
- /* Set Mux */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0000;
- res = 1;
- break;
- case 2:
- /* Get SG/Non-SG mode */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0000;
- res = 1;
- break;
- default:
- /* Interrupt was not handled */
- debug("Unknown INT15 5f70 function: 0x%02x\n",
- M.x86.R_CH);
- break;
- }
- break;
- case 0x5fac:
- res = 1;
- break;
- default:
- debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
- break;
- }
- return res;
-}
-
-void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev)
-{
- u32 reg32;
- u16 reg16;
- u8 reg8;
-
- dm_pci_read_config16(video_dev, PCI_DEVICE_ID, ®16);
- switch (reg16) {
- case 0x0102: /* GT1 Desktop */
- case 0x0106: /* GT1 Mobile */
- case 0x010a: /* GT1 Server */
- case 0x0112: /* GT2 Desktop */
- case 0x0116: /* GT2 Mobile */
- case 0x0122: /* GT2 Desktop >=1.3GHz */
- case 0x0126: /* GT2 Mobile >=1.3GHz */
- case 0x0156: /* IvyBridge */
- case 0x0166: /* IvyBridge */
- break;
- default:
- debug("Graphics not supported by this CPU/chipset\n");
- return;
- }
-
- debug("Initialising Graphics\n");
-
- /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
- dm_pci_read_config16(dev, GGC, ®16);
- reg16 &= ~0x00f8;
- reg16 |= 1 << 3;
- /* Program GTT memory by setting GGC[9:8] = 2MB */
- reg16 &= ~0x0300;
- reg16 |= 2 << 8;
- /* Enable VGA decode */
- reg16 &= ~0x0002;
- dm_pci_write_config16(dev, GGC, reg16);
-
- /* Enable 256MB aperture */
- dm_pci_read_config8(video_dev, MSAC, ®8);
- reg8 &= ~0x06;
- reg8 |= 0x02;
- dm_pci_write_config8(video_dev, MSAC, reg8);
-
- /* Erratum workarounds */
- reg32 = readl(MCHBAR_REG(0x5f00));
- reg32 |= (1 << 9) | (1 << 10);
- writel(reg32, MCHBAR_REG(0x5f00));
-
- /* Enable SA Clock Gating */
- reg32 = readl(MCHBAR_REG(0x5f00));
- writel(reg32 | 1, MCHBAR_REG(0x5f00));
-
- /* GPU RC6 workaround for sighting 366252 */
- reg32 = readl(MCHBAR_REG(0x5d14));
- reg32 |= (1 << 31);
- writel(reg32, MCHBAR_REG(0x5d14));
-
- /* VLW */
- reg32 = readl(MCHBAR_REG(0x6120));
- reg32 &= ~(1 << 0);
- writel(reg32, MCHBAR_REG(0x6120));
-
- reg32 = readl(MCHBAR_REG(0x5418));
- reg32 |= (1 << 4) | (1 << 5);
- writel(reg32, MCHBAR_REG(0x5418));
-}
-
-int gma_func0_init(struct udevice *dev)
-{
-#ifdef CONFIG_VIDEO
- ulong start;
-#endif
- struct udevice *nbridge;
- void *gtt_bar;
- ulong base;
- u32 reg32;
- int ret;
- int rev;
-
- /* Enable PCH Display Port */
- writew(0x0010, RCB_REG(DISPBDF));
- setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
-
- ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
- if (ret)
- return ret;
- rev = bridge_silicon_revision(nbridge);
- sandybridge_setup_graphics(nbridge, dev);
-
- /* IGD needs to be Bus Master */
- dm_pci_read_config32(dev, PCI_COMMAND, ®32);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- dm_pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* Use write-combining for the graphics memory, 256MB */
- base = dm_pci_read_bar32(dev, 2);
- mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
- mtrr_commit(true);
-
- gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
- debug("GT bar %p\n", gtt_bar);
- ret = gma_pm_init_pre_vbios(gtt_bar, rev);
- if (ret)
- return ret;
-
-#ifdef CONFIG_VIDEO
- start = get_timer(0);
- ret = dm_pci_run_vga_bios(dev, int15_handler,
- PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK);
- debug("BIOS ran in %lums\n", get_timer(start));
-#endif
- /* Post VBIOS init */
- ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
- if (ret)
- return ret;
-
- return 0;
-}
diff --git a/arch/x86/cpu/ivybridge/gma.h b/arch/x86/cpu/ivybridge/gma.h
deleted file mode 100644
index e7ec649..0000000
--- a/arch/x86/cpu/ivybridge/gma.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * From Coreboot file of the same name
- *
- * Copyright (C) 2012 Chromium OS Authors
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-/* mailbox 0: header */
-__packed struct opregion_header {
- u8 signature[16];
- u32 size;
- u32 version;
- u8 sbios_version[32];
- u8 vbios_version[16];
- u8 driver_version[16];
- u32 mailboxes;
- u8 reserved[164];
-};
-
-#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
-#define IGD_OPREGION_VERSION 2
-
-#define IGD_MBOX1 (1 << 0)
-#define IGD_MBOX2 (1 << 1)
-#define IGD_MBOX3 (1 << 2)
-#define IGD_MBOX4 (1 << 3)
-#define IGD_MBOX5 (1 << 4)
-
-#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
- IGD_MBOX4 | IGD_MBOX5)
-#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
-
-#define SBIOS_VERSION_SIZE 32
-
-/* mailbox 1: public acpi methods */
-__packed struct opregion_mailbox1 {
- u32 drdy;
- u32 csts;
- u32 cevt;
- u8 reserved1[20];
- u32 didl[8];
- u32 cpdl[8];
- u32 cadl[8];
- u32 nadl[8];
- u32 aslp;
- u32 tidx;
- u32 chpd;
- u32 clid;
- u32 cdck;
- u32 sxsw;
- u32 evts;
- u32 cnot;
- u32 nrdy;
- u8 reserved2[60];
-};
-
-/* mailbox 2: software sci interface */
-__packed struct opregion_mailbox2 {
- u32 scic;
- u32 parm;
- u32 dslp;
- u8 reserved[244];
-};
-
-/* mailbox 3: power conservation */
-__packed struct opregion_mailbox3 {
- u32 ardy;
- u32 aslc;
- u32 tche;
- u32 alsi;
- u32 bclp;
- u32 pfit;
- u32 cblv;
- u16 bclm[20];
- u32 cpfm;
- u32 epfm;
- u8 plut[74];
- u32 pfmb;
- u32 ccdv;
- u32 pcft;
- u8 reserved[94];
-};
-
-#define IGD_BACKLIGHT_BRIGHTNESS 0xff
-#define IGD_INITIAL_BRIGHTNESS 0x64
-
-#define IGD_FIELD_VALID (1 << 31)
-#define IGD_WORD_FIELD_VALID (1 << 15)
-#define IGD_PFIT_STRETCH 6
-
-/* mailbox 4: vbt */
-__packed struct {
- u8 gvd1[7168];
-} opregion_vbt_t;
-
-/* IGD OpRegion */
-__packed struct igd_opregion {
- opregion_header_t header;
- opregion_mailbox1_t mailbox1;
- opregion_mailbox2_t mailbox2;
- opregion_mailbox3_t mailbox3;
- opregion_vbt_t vbt;
-};
-
-/* Intel Video BIOS (Option ROM) */
-__packed struct optionrom_header {
- u16 signature;
- u8 size;
- u8 reserved[21];
- u16 pcir_offset;
- u16 vbt_offset;
-};
-
-#define OPROM_SIGNATURE 0xaa55
-
-__packed struct optionrom_pcir {
- u32 signature;
- u16 vendor;
- u16 device;
- u16 reserved1;
- u16 length;
- u8 revision;
- u8 classcode[3];
- u16 imagelength;
- u16 coderevision;
- u8 codetype;
- u8 indicator;
- u16 reserved2;
-};
-
-__packed struct optionrom_vbt {
- u8 hdr_signature[20];
- u16 hdr_version;
- u16 hdr_size;
- u16 hdr_vbt_size;
- u8 hdr_vbt_checksum;
- u8 hdr_reserved;
- u32 hdr_vbt_datablock;
- u32 hdr_aim[4];
- u8 datahdr_signature[16];
- u16 datahdr_version;
- u16 datahdr_size;
- u16 datahdr_datablocksize;
- u8 coreblock_id;
- u16 coreblock_size;
- u16 coreblock_biossize;
- u8 coreblock_biostype;
- u8 coreblock_releasestatus;
- u8 coreblock_hwsupported;
- u8 coreblock_integratedhw;
- u8 coreblock_biosbuild[4];
- u8 coreblock_biossignon[155];
-};
-
-#define VBT_SIGNATURE 0x54425624
diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c
index c770b53..e817eb9 100644
--- a/arch/x86/cpu/ivybridge/ivybridge.c
+++ b/arch/x86/cpu/ivybridge/ivybridge.c
@@ -10,13 +10,7 @@
int arch_cpu_init(void)
{
- int ret;
-
post_code(POST_CPU_INIT);
- ret = x86_cpu_init_f();
- if (ret)
- return ret;
-
- return 0;
+ return x86_cpu_init_f();
}
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 4e0be2a..4af89b3 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -213,10 +213,10 @@
dm_pci_read_config16(pch, 0x40, &pmbase);
pmbase &= 0xfffe;
- writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
- "intel,gpe0-enable", 0));
- writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
- "intel,alt-gp-smi-enable", 0));
+ writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0),
+ (ulong)pmbase + GPE0_EN);
+ writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0),
+ (ulong)pmbase + ALT_GP_SMI_EN);
/* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + 0x04); /* PM1_CNT */
@@ -355,10 +355,10 @@
reg16 |= (1 << 2) | (1 << 11);
dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
- pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
- pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
- pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
- pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
+ pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31);
+ pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7);
+ pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31);
+ pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7);
reg32 = readl(RCB_REG(CG));
reg32 |= (1 << 31);
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 38e244b..09b5342 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -20,7 +20,6 @@
#include <asm/processor.h>
#include <asm/speedstep.h>
#include <asm/turbo.h>
-#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
static void enable_vmx(void)
@@ -478,6 +477,7 @@
.get_desc = cpu_x86_get_desc,
.get_info = model_206ax_get_info,
.get_count = model_206ax_get_count,
+ .get_vendor = cpu_x86_get_vendor,
};
static const struct udevice_id cpu_x86_model_206ax_ids[] = {
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index 1ce8195..87ff872 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -12,7 +12,6 @@
#include <asm/pch_common.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
-#include <asm/arch/bd82x6x.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 680e558..c3092f2 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -139,15 +139,9 @@
int arch_cpu_init(void)
{
- int ret;
-
post_code(POST_CPU_INIT);
- ret = x86_cpu_init_f();
- if (ret)
- return ret;
-
- return 0;
+ return x86_cpu_init_f();
}
#ifndef CONFIG_EFI_STUB
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index b226e4c..f307c62 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -94,15 +94,9 @@
int arch_cpu_init(void)
{
- int ret;
-
post_code(POST_CPU_INIT);
- ret = x86_cpu_init_f();
- if (ret)
- return ret;
-
- return 0;
+ return x86_cpu_init_f();
}
int arch_early_init_r(void)
diff --git a/arch/x86/cpu/setjmp.S b/arch/x86/cpu/setjmp.S
new file mode 100644
index 0000000..2ea1c6c
--- /dev/null
+++ b/arch/x86/cpu/setjmp.S
@@ -0,0 +1,61 @@
+/*
+ * Written by H. Peter Anvin <hpa@zytor.com>
+ * Brought in from Linux v4.4 and modified for U-Boot
+ * From Linux arch/um/sys-i386/setjmp.S
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#define _REGPARM
+
+/*
+ * The jmp_buf is assumed to contain the following, in order:
+ * %ebx
+ * %esp
+ * %ebp
+ * %esi
+ * %edi
+ * <return address>
+ */
+
+ .text
+ .align 4
+ .globl setjmp
+ .type setjmp, @function
+setjmp:
+#ifdef _REGPARM
+ movl %eax, %edx
+#else
+ movl 4(%esp), %edx
+#endif
+ popl %ecx /* Return address, and adjust the stack */
+ xorl %eax, %eax /* Return value */
+ movl %ebx, (%edx)
+ movl %esp, 4(%edx) /* Post-return %esp! */
+ pushl %ecx /* Make the call/return stack happy */
+ movl %ebp, 8(%edx)
+ movl %esi, 12(%edx)
+ movl %edi, 16(%edx)
+ movl %ecx, 20(%edx) /* Return address */
+ ret
+
+ /* Provide function size if needed */
+ .size setjmp, .-setjmp
+
+ .align 4
+ .globl longjmp
+ .type longjmp, @function
+longjmp:
+#ifdef _REGPARM
+ xchgl %eax, %edx
+#else
+ movl 4(%esp), %edx /* jmp_ptr address */
+#endif
+ movl (%edx), %ebx
+ movl 4(%edx), %esp
+ movl 8(%edx), %ebp
+ movl 12(%edx), %esi
+ movl 16(%edx), %edi
+ jmp *20(%edx)
+
+ .size longjmp, .-longjmp
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index 36f59ea..cca536b 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -28,7 +28,10 @@
}
. = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ KEEP(*(.rodata.efi.init));
+ }
. = ALIGN(4);
.data : { *(.data*) }
@@ -40,6 +43,37 @@
.got : { *(.got*) }
. = ALIGN(4);
+
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(efi_runtime_text)
+ *(efi_runtime_data)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
+ .efi_runtime_rel_start :
+ {
+ *(.__efi_runtime_rel_start)
+ }
+
+ .efi_runtime_rel : {
+ *(.relefi_runtime_text)
+ *(.relefi_runtime_data)
+ }
+
+ .efi_runtime_rel_stop :
+ {
+ *(.__efi_runtime_rel_stop)
+ }
+
+ . = ALIGN(4);
+
__data_end = .;
__init_end = .;
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index c8907ce..18b310d 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -14,6 +14,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Bayley Bay";
diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
index 4bb0a34..3966199 100644
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ b/arch/x86/dts/broadwell_som-6896.dts
@@ -4,6 +4,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Advantech SOM-6896";
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index fb1b31d..b932340 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -7,6 +7,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Google Link";
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 5dd3e57..52a9ea6 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -7,6 +7,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Google Samus";
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 480b366..b25c919 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -4,6 +4,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Google Panther";
diff --git a/arch/x86/dts/coreboot_fb.dtsi b/arch/x86/dts/coreboot_fb.dtsi
new file mode 100644
index 0000000..7d72f18
--- /dev/null
+++ b/arch/x86/dts/coreboot_fb.dtsi
@@ -0,0 +1,5 @@
+/ {
+ coreboot-fb {
+ compatible = "coreboot-fb";
+ };
+};
diff --git a/arch/x86/dts/emulation-u-boot.dtsi b/arch/x86/dts/emulation-u-boot.dtsi
new file mode 100644
index 0000000..56d34af
--- /dev/null
+++ b/arch/x86/dts/emulation-u-boot.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <u-boot.dtsi>
+
+#ifdef CONFIG_ROM_SIZE
+/ {
+ binman {
+ u-boot-with-ucode-ptr {
+ optional-ucode;
+ };
+ };
+};
+#endif
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 1a8a8cc..d51318b 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -13,6 +13,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Minnowboard Max";
diff --git a/arch/x86/dts/quark-u-boot.dtsi b/arch/x86/dts/quark-u-boot.dtsi
new file mode 100644
index 0000000..04eb985
--- /dev/null
+++ b/arch/x86/dts/quark-u-boot.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <u-boot.dtsi>
+
+#ifdef CONFIG_ROM_SIZE
+/ {
+ binman {
+ u-boot-with-ucode-ptr {
+ optional-ucode;
+ };
+ };
+};
+#endif
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
new file mode 100644
index 0000000..31f0b1a
--- /dev/null
+++ b/arch/x86/dts/u-boot.dtsi
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_ROM_SIZE
+/ {
+ binman {
+ filename = "u-boot.rom";
+ end-at-4gb;
+ sort-by-pos;
+ pad-byte = <0xff>;
+ size = <CONFIG_ROM_SIZE>;
+#ifdef CONFIG_HAVE_INTEL_ME
+ intel-descriptor {
+ };
+ intel-me {
+ };
+#endif
+ u-boot-with-ucode-ptr {
+ pos = <CONFIG_SYS_TEXT_BASE>;
+ };
+ u-boot-dtb-with-ucode {
+ };
+ u-boot-ucode {
+ align = <16>;
+ };
+#ifdef CONFIG_HAVE_MRC
+ intel-mrc {
+ pos = <CONFIG_X86_MRC_ADDR>;
+ };
+#endif
+#ifdef CONFIG_HAVE_FSP
+ intel-fsp {
+ filename = CONFIG_FSP_FILE;
+ pos = <CONFIG_FSP_ADDR>;
+ };
+#endif
+#ifdef CONFIG_HAVE_CMC
+ intel-cmc {
+ filename = CONFIG_CMC_FILE;
+ pos = <CONFIG_CMC_ADDR>;
+ };
+#endif
+#ifdef CONFIG_HAVE_VGA_BIOS
+ intel-vga {
+ filename = CONFIG_VGA_BIOS_FILE;
+ pos = <CONFIG_VGA_BIOS_ADDR>;
+ };
+#endif
+#ifdef CONFIG_HAVE_REFCODE
+ intel-refcode {
+ pos = <CONFIG_X86_REFCODE_ADDR>;
+ };
+#endif
+ x86-start16 {
+ pos = <CONFIG_SYS_X86_START16>;
+ };
+ };
+};
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
deleted file mode 100644
index e866580..0000000
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_BD82X6X_H
-#define _ASM_ARCH_BD82X6X_H
-
-int gma_func0_init(struct udevice *dev);
-
-#endif
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index 1400951..a373a79 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -63,6 +63,9 @@
__u32 payload_offset;
__u32 payload_length;
__u64 setup_data;
+ __u64 pref_address;
+ __u32 init_size;
+ __u32 handover_offset;
} __attribute__((packed));
struct sys_desc_table {
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 7892757..540024a 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -53,7 +53,6 @@
enum {
X86_NONE,
X86_SYSCON_ME, /* Intel Management Engine */
- X86_SYSCON_GMA, /* Intel Graphics Media Accelerator */
X86_SYSCON_PINCONF, /* Intel x86 pin configuration */
};
diff --git a/arch/x86/include/asm/cpu_x86.h b/arch/x86/include/asm/cpu_x86.h
index 1940480..74b82ed 100644
--- a/arch/x86/include/asm/cpu_x86.h
+++ b/arch/x86/include/asm/cpu_x86.h
@@ -31,4 +31,17 @@
*/
int cpu_x86_get_desc(struct udevice *dev, char *buf, int size);
+/**
+ * cpu_x86_get_vendor() - Get a vendor string for an x86 CPU
+ *
+ * This uses cpu_vendor_name() and is suitable to use as the get_vendor()
+ * method for the CPU uclass.
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @buf: Buffer to place string
+ * @size: Size of string space
+ * @return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int cpu_x86_get_vendor(struct udevice *dev, char *buf, int size);
+
#endif /* _ASM_CPU_X86_H */
diff --git a/arch/x86/include/asm/errno.h b/arch/x86/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/x86/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/x86/include/asm/init_helpers.h b/arch/x86/include/asm/init_helpers.h
index c689a63..ef05ac4 100644
--- a/arch/x86/include/asm/init_helpers.h
+++ b/arch/x86/include/asm/init_helpers.h
@@ -9,7 +9,5 @@
#define _INIT_HELPERS_H_
int init_cache_f_r(void);
-int init_bd_struct_r(void);
-int init_func_spi(void);
#endif /* !_INIT_HELPERS_H_ */
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index c480920..8e8d443 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -22,7 +22,7 @@
#ifdef __KERNEL__
-#include <asm/errno.h>
+#include <linux/errno.h>
struct msr {
union {
diff --git a/arch/x86/include/asm/setjmp.h b/arch/x86/include/asm/setjmp.h
new file mode 100644
index 0000000..1feaa89
--- /dev/null
+++ b/arch/x86/include/asm/setjmp.h
@@ -0,0 +1,24 @@
+/*
+ * Written by H. Peter Anvin <hpa@zytor.com>
+ * Brought in from Linux v4.4 and modified for U-Boot
+ * From Linux arch/um/sys-i386/setjmp.S
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __setjmp_h
+#define __setjmp_h
+
+struct jmp_buf_data {
+ unsigned int __ebx;
+ unsigned int __esp;
+ unsigned int __ebp;
+ unsigned int __esi;
+ unsigned int __edi;
+ unsigned int __eip;
+};
+
+int setjmp(struct jmp_buf_data *jmp_buf);
+void longjmp(struct jmp_buf_data *jmp_buf, int val);
+
+#endif
diff --git a/arch/x86/include/asm/smbios.h b/arch/x86/include/asm/smbios.h
deleted file mode 100644
index 623a703..0000000
--- a/arch/x86/include/asm/smbios.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * Adapted from coreboot src/include/smbios.h
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SMBIOS_H_
-#define _SMBIOS_H_
-
-/* SMBIOS spec version implemented */
-#define SMBIOS_MAJOR_VER 3
-#define SMBIOS_MINOR_VER 0
-
-/* SMBIOS structure types */
-enum {
- SMBIOS_BIOS_INFORMATION = 0,
- SMBIOS_SYSTEM_INFORMATION = 1,
- SMBIOS_BOARD_INFORMATION = 2,
- SMBIOS_SYSTEM_ENCLOSURE = 3,
- SMBIOS_PROCESSOR_INFORMATION = 4,
- SMBIOS_CACHE_INFORMATION = 7,
- SMBIOS_SYSTEM_SLOTS = 9,
- SMBIOS_PHYS_MEMORY_ARRAY = 16,
- SMBIOS_MEMORY_DEVICE = 17,
- SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19,
- SMBIOS_SYSTEM_BOOT_INFORMATION = 32,
- SMBIOS_END_OF_TABLE = 127
-};
-
-#define SMBIOS_INTERMEDIATE_OFFSET 16
-#define SMBIOS_STRUCT_EOS_BYTES 2
-
-struct __packed smbios_entry {
- u8 anchor[4];
- u8 checksum;
- u8 length;
- u8 major_ver;
- u8 minor_ver;
- u16 max_struct_size;
- u8 entry_point_rev;
- u8 formatted_area[5];
- u8 intermediate_anchor[5];
- u8 intermediate_checksum;
- u16 struct_table_length;
- u32 struct_table_address;
- u16 struct_count;
- u8 bcd_rev;
-};
-
-/* BIOS characteristics */
-#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7)
-#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11)
-#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16)
-
-#define BIOS_CHARACTERISTICS_EXT1_ACPI (1 << 0)
-#define BIOS_CHARACTERISTICS_EXT2_TARGET (1 << 2)
-
-struct __packed smbios_type0 {
- u8 type;
- u8 length;
- u16 handle;
- u8 vendor;
- u8 bios_ver;
- u16 bios_start_segment;
- u8 bios_release_date;
- u8 bios_rom_size;
- u64 bios_characteristics;
- u8 bios_characteristics_ext1;
- u8 bios_characteristics_ext2;
- u8 bios_major_release;
- u8 bios_minor_release;
- u8 ec_major_release;
- u8 ec_minor_release;
- char eos[SMBIOS_STRUCT_EOS_BYTES];
-};
-
-struct __packed smbios_type1 {
- u8 type;
- u8 length;
- u16 handle;
- u8 manufacturer;
- u8 product_name;
- u8 version;
- u8 serial_number;
- u8 uuid[16];
- u8 wakeup_type;
- u8 sku_number;
- u8 family;
- char eos[SMBIOS_STRUCT_EOS_BYTES];
-};
-
-#define SMBIOS_BOARD_FEATURE_HOSTING (1 << 0)
-#define SMBIOS_BOARD_MOTHERBOARD 10
-
-struct __packed smbios_type2 {
- u8 type;
- u8 length;
- u16 handle;
- u8 manufacturer;
- u8 product_name;
- u8 version;
- u8 serial_number;
- u8 asset_tag_number;
- u8 feature_flags;
- u8 chassis_location;
- u16 chassis_handle;
- u8 board_type;
- char eos[SMBIOS_STRUCT_EOS_BYTES];
-};
-
-#define SMBIOS_ENCLOSURE_DESKTOP 3
-#define SMBIOS_STATE_SAFE 3
-#define SMBIOS_SECURITY_NONE 3
-
-struct __packed smbios_type3 {
- u8 type;
- u8 length;
- u16 handle;
- u8 manufacturer;
- u8 chassis_type;
- u8 version;
- u8 serial_number;
- u8 asset_tag_number;
- u8 bootup_state;
- u8 power_supply_state;
- u8 thermal_state;
- u8 security_status;
- u32 oem_defined;
- u8 height;
- u8 number_of_power_cords;
- u8 element_count;
- u8 element_record_length;
- char eos[SMBIOS_STRUCT_EOS_BYTES];
-};
-
-#define SMBIOS_PROCESSOR_TYPE_CENTRAL 3
-#define SMBIOS_PROCESSOR_STATUS_ENABLED 1
-#define SMBIOS_PROCESSOR_UPGRADE_NONE 6
-
-struct __packed smbios_type4 {
- u8 type;
- u8 length;
- u16 handle;
- u8 socket_designation;
- u8 processor_type;
- u8 processor_family;
- u8 processor_manufacturer;
- u32 processor_id[2];
- u8 processor_version;
- u8 voltage;
- u16 external_clock;
- u16 max_speed;
- u16 current_speed;
- u8 status;
- u8 processor_upgrade;
- u16 l1_cache_handle;
- u16 l2_cache_handle;
- u16 l3_cache_handle;
- u8 serial_number;
- u8 asset_tag;
- u8 part_number;
- u8 core_count;
- u8 core_enabled;
- u8 thread_count;
- u16 processor_characteristics;
- u16 processor_family2;
- u16 core_count2;
- u16 core_enabled2;
- u16 thread_count2;
- char eos[SMBIOS_STRUCT_EOS_BYTES];
-};
-
-struct __packed smbios_type32 {
- u8 type;
- u8 length;
- u16 handle;
- u8 reserved[6];
- u8 boot_status;
- u8 eos[SMBIOS_STRUCT_EOS_BYTES];
-};
-
-struct __packed smbios_type127 {
- u8 type;
- u8 length;
- u16 handle;
- u8 eos[SMBIOS_STRUCT_EOS_BYTES];
-};
-
-struct __packed smbios_header {
- u8 type;
- u8 length;
- u16 handle;
-};
-
-/**
- * fill_smbios_header() - Fill the header of an SMBIOS table
- *
- * This fills the header of an SMBIOS table structure.
- *
- * @table: start address of the structure
- * @type: the type of structure
- * @length: the length of the formatted area of the structure
- * @handle: the structure's handle, a unique 16-bit number
- */
-static inline void fill_smbios_header(void *table, int type,
- int length, int handle)
-{
- struct smbios_header *header = table;
-
- header->type = type;
- header->length = length - SMBIOS_STRUCT_EOS_BYTES;
- header->handle = handle;
-}
-
-/**
- * Function prototype to write a specific type of SMBIOS structure
- *
- * @addr: start address to write the structure
- * @handle: the structure's handle, a unique 16-bit number
- * @return: size of the structure
- */
-typedef int (*smbios_write_type)(u32 *addr, int handle);
-
-/**
- * write_smbios_table() - Write SMBIOS table
- *
- * This writes SMBIOS table at a given address.
- *
- * @addr: start address to write SMBIOS table
- * @return: end address of SMBIOS table
- */
-u32 write_smbios_table(u32 addr);
-
-#endif /* _SMBIOS_H_ */
diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h
index 0ad612f..38afd23 100644
--- a/arch/x86/include/asm/string.h
+++ b/arch/x86/include/asm/string.h
@@ -17,7 +17,7 @@
#define __HAVE_ARCH_MEMCPY
extern void * memcpy(void *, const void *, __kernel_size_t);
-#undef __HAVE_ARCH_MEMMOVE
+#define __HAVE_ARCH_MEMMOVE
extern void * memmove(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMCHR
diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h
index ae9f0d0..81f98f2 100644
--- a/arch/x86/include/asm/tables.h
+++ b/arch/x86/include/asm/tables.h
@@ -7,6 +7,8 @@
#ifndef _X86_TABLES_H_
#define _X86_TABLES_H_
+#include <tables_csum.h>
+
/*
* All x86 tables happen to like the address range from 0xf0000 to 0x100000.
* We use 0xf0000 as the starting address to store those tables, including
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 031740b..4f901f9 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -74,6 +74,7 @@
/* board/... */
void timer_set_tsc_base(uint64_t new_base);
uint64_t timer_get_tsc(void);
+void board_quiesce_devices(void);
void quick_ram_check(void);
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index e17f0bb..723288f 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -28,8 +28,8 @@
obj-y += relocate.o
obj-y += physmem.o
obj-$(CONFIG_X86_RAMTEST) += ramtest.o
+obj-y += sections.o
obj-y += sfi.o
-obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
obj-y += string.o
ifndef CONFIG_QEMU
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
@@ -44,3 +44,26 @@
OBJCOPYFLAGS := --prefix-symbols=__normal_
$(obj)/lib.a: $(NORMAL_LIBGCC) FORCE
$(call if_changed,objcopy)
+
+obj-$(CONFIG_EFI_APP) += crt0_ia32_efi.o reloc_ia32_efi.o
+
+ifneq ($(CONFIG_EFI_STUB),)
+
+CFLAGS_REMOVE_reloc_ia32_efi.o += -mregparm=3
+CFLAGS_reloc_ia32_efi.o += -fpic -fshort-wchar
+
+# When building for 64-bit we must remove the i386-specific flags
+CFLAGS_REMOVE_reloc_x86_64_efi.o += -mregparm=3 -march=i386 -m32
+CFLAGS_reloc_x86_64_efi.o += -fpic -fshort-wchar
+
+AFLAGS_REMOVE_crt0_x86_64_efi.o += -mregparm=3 -march=i386 -m32
+AFLAGS_crt0_x86_64_efi.o += -fpic -fshort-wchar
+
+extra-$(CONFIG_EFI_STUB_32BIT) += crt0_ia32_efi.o reloc_ia32_efi.o
+extra-$(CONFIG_EFI_STUB_64BIT) += crt0_x86_64_efi.o reloc_x86_64_efi.o
+
+endif
+
+ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
+extra-y += $(EFI_CRT0) $(EFI_RELOC)
+endif
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 7cf9de4..e5e63f6 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -26,6 +26,15 @@
#define COMMAND_LINE_OFFSET 0x9000
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
+__weak void board_quiesce_devices(void)
+{
+}
+
void bootm_announce_and_cleanup(void)
{
printf("\nStarting kernel ...\n\n");
diff --git a/arch/x86/lib/efi/crt0-efi-ia32.S b/arch/x86/lib/crt0_ia32_efi.S
similarity index 100%
rename from arch/x86/lib/efi/crt0-efi-ia32.S
rename to arch/x86/lib/crt0_ia32_efi.S
diff --git a/arch/x86/lib/efi/crt0-efi-x86_64.S b/arch/x86/lib/crt0_x86_64_efi.S
similarity index 100%
rename from arch/x86/lib/efi/crt0-efi-x86_64.S
rename to arch/x86/lib/crt0_x86_64_efi.S
diff --git a/arch/x86/lib/efi/Makefile b/arch/x86/lib/efi/Makefile
index af4503e..43aadfc 100644
--- a/arch/x86/lib/efi/Makefile
+++ b/arch/x86/lib/efi/Makefile
@@ -7,21 +7,3 @@
obj-$(CONFIG_EFI_STUB) += car.o
obj-$(CONFIG_EFI_STUB) += efi.o
-
-obj-$(CONFIG_EFI_APP) += crt0-efi-ia32.o reloc_ia32.o
-
-ifneq ($(CONFIG_EFI_STUB),)
-
-CFLAGS_REMOVE_reloc_ia32.o += -mregparm=3
-CFLAGS_reloc_ia32.o += -fpic -fshort-wchar
-
-# When building for 64-bit we must remove the i386-specific flags
-CFLAGS_REMOVE_reloc_x86_64.o += -mregparm=3 -march=i386 -m32
-CFLAGS_reloc_x86_64.o += -fpic -fshort-wchar
-
-AFLAGS_REMOVE_crt0-efi-x86_64.o += -mregparm=3 -march=i386 -m32
-AFLAGS_crt0-efi-x86_64.o += -fpic -fshort-wchar
-
-extra-$(CONFIG_EFI_STUB_32BIT) += crt0-efi-ia32.o reloc_ia32.o
-extra-$(CONFIG_EFI_STUB_64BIT) += crt0-efi-x86_64.o reloc_x86_64.o
-endif
diff --git a/arch/x86/lib/elf_ia32_efi.lds b/arch/x86/lib/elf_ia32_efi.lds
new file mode 100644
index 0000000..174d36f
--- /dev/null
+++ b/arch/x86/lib/elf_ia32_efi.lds
@@ -0,0 +1,92 @@
+/*
+ * U-Boot EFI linker script
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Modified from usr/lib32/elf_ia32_efi.lds in gnu-efi
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+SECTIONS
+{
+ image_base = .;
+ .hash : { *(.hash) } /* this MUST come first, EFI expects it */
+ . = ALIGN(4096);
+ .text :
+ {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ }
+ . = ALIGN(4096);
+ .sdata :
+ {
+ *(.got.plt)
+ *(.got)
+ *(.srodata)
+ *(.sdata)
+ *(.sbss)
+ *(.scommon)
+ }
+ . = ALIGN(4096);
+ .data :
+ {
+ *(.rodata*)
+ *(.data)
+ *(.data1)
+ *(.data.*)
+ *(.sdata)
+ *(.got.plt)
+ *(.got)
+ /*
+ * the EFI loader doesn't seem to like a .bss section, so we
+ * stick it all into .data:
+ */
+ *(.sbss)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+
+ /* U-Boot lists and device tree */
+ . = ALIGN(8);
+ *(SORT(.u_boot_list*));
+ . = ALIGN(8);
+ *(.dtb*);
+ }
+
+ . = ALIGN(4096);
+ .dynamic : { *(.dynamic) }
+ . = ALIGN(4096);
+ .rel :
+ {
+ *(.rel.data)
+ *(.rel.data.*)
+ *(.rel.got)
+ *(.rel.stab)
+ *(.data.rel.ro.local)
+ *(.data.rel.local)
+ *(.data.rel.ro)
+ *(.data.rel*)
+ *(.rel.u_boot_list*)
+ }
+ . = ALIGN(4096);
+ .reloc : /* This is the PECOFF .reloc section! */
+ {
+ *(.reloc)
+ }
+ . = ALIGN(4096);
+ .dynsym : { *(.dynsym) }
+ . = ALIGN(4096);
+ .dynstr : { *(.dynstr) }
+ . = ALIGN(4096);
+ /DISCARD/ :
+ {
+ *(.rel.reloc)
+ *(.eh_frame)
+ *(.note.GNU-stack)
+ }
+ .comment 0 : { *(.comment) }
+}
diff --git a/arch/x86/lib/elf_x86_64_efi.lds b/arch/x86/lib/elf_x86_64_efi.lds
new file mode 100644
index 0000000..70c7c52
--- /dev/null
+++ b/arch/x86/lib/elf_x86_64_efi.lds
@@ -0,0 +1,81 @@
+/*
+ * U-Boot EFI linker script
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Modified from usr/lib32/elf_x86_64_efi.lds in gnu-efi
+ */
+
+OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64")
+OUTPUT_ARCH(i386:x86-64)
+ENTRY(_start)
+SECTIONS
+{
+ image_base = .;
+ .hash : { *(.hash) } /* this MUST come first, EFI expects it */
+ . = ALIGN(4096);
+ .eh_frame : {
+ *(.eh_frame)
+ }
+
+ . = ALIGN(4096);
+
+ .text : {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ }
+
+ . = ALIGN(4096);
+
+ .reloc : {
+ *(.reloc)
+ }
+
+ . = ALIGN(4096);
+
+ .data : {
+ *(.rodata*)
+ *(.got.plt)
+ *(.got)
+ *(.data*)
+ *(.sdata)
+ /* the EFI loader doesn't seem to like a .bss section, so we stick
+ * it all into .data: */
+ *(.sbss)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ *(.rel.local)
+
+ /* U-Boot lists and device tree */
+ . = ALIGN(8);
+ *(SORT(.u_boot_list*));
+ . = ALIGN(8);
+ *(.dtb*);
+ }
+
+ . = ALIGN(4096);
+ .dynamic : { *(.dynamic) }
+ . = ALIGN(4096);
+
+ .rela : {
+ *(.rela.data*)
+ *(.rela.got)
+ *(.rela.stab)
+ }
+
+ . = ALIGN(4096);
+ .dynsym : { *(.dynsym) }
+ . = ALIGN(4096);
+ .dynstr : { *(.dynstr) }
+ . = ALIGN(4096);
+ .ignored.reloc : {
+ *(.rela.reloc)
+ *(.eh_frame)
+ *(.note.GNU-stack)
+ }
+
+ .comment 0 : { *(.comment) }
+}
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 82fd5c3..2a186fc 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/mtrr.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -30,13 +30,3 @@
/* Initialise the CPU cache(s) */
return init_cache();
}
-
-bd_t bd_data;
-
-int init_bd_struct_r(void)
-{
- gd->bd = &bd_data;
- memset(gd->bd, 0, sizeof(bd_t));
-
- return 0;
-}
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 67bace4..eca88ac 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -198,11 +198,13 @@
/* Find the flash chip within the SPI controller node */
node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
- if (node < 0)
+ if (node < 0) {
+ debug("%s: Cannot find SPI flash\n", __func__);
return -ENOENT;
+ }
if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2))
- return -FDT_ERR_NOTFOUND;
+ return -EINVAL;
entry->base = reg[0];
/* Find the place where we put the MRC cache */
@@ -211,7 +213,7 @@
return -EPERM;
if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2))
- return -FDT_ERR_NOTFOUND;
+ return -EINVAL;
entry->offset = reg[0];
entry->length = reg[1];
diff --git a/arch/x86/lib/efi/reloc_ia32.c b/arch/x86/lib/reloc_ia32_efi.c
similarity index 100%
rename from arch/x86/lib/efi/reloc_ia32.c
rename to arch/x86/lib/reloc_ia32_efi.c
diff --git a/arch/x86/lib/efi/reloc_x86_64.c b/arch/x86/lib/reloc_x86_64_efi.c
similarity index 100%
rename from arch/x86/lib/efi/reloc_x86_64.c
rename to arch/x86/lib/reloc_x86_64_efi.c
diff --git a/arch/x86/lib/sections.c b/arch/x86/lib/sections.c
new file mode 100644
index 0000000..6455e0f
--- /dev/null
+++ b/arch/x86/lib/sections.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+char __efi_runtime_start[0] __attribute__((section(".__efi_runtime_start")));
+char __efi_runtime_stop[0] __attribute__((section(".__efi_runtime_stop")));
+char __efi_runtime_rel_start[0]
+ __attribute__((section(".__efi_runtime_rel_start")));
+char __efi_runtime_rel_stop[0]
+ __attribute__((section(".__efi_runtime_rel_stop")));
diff --git a/arch/x86/lib/smbios.c b/arch/x86/lib/smbios.c
deleted file mode 100644
index 9f30550..0000000
--- a/arch/x86/lib/smbios.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * Adapted from coreboot src/arch/x86/smbios.c
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <version.h>
-#include <asm/cpu.h>
-#include <asm/smbios.h>
-#include <asm/tables.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/**
- * smbios_add_string() - add a string to the string area
- *
- * This adds a string to the string area which is appended directly after
- * the formatted portion of an SMBIOS structure.
- *
- * @start: string area start address
- * @str: string to add
- * @return: string number in the string area
- */
-static int smbios_add_string(char *start, const char *str)
-{
- int i = 1;
- char *p = start;
-
- for (;;) {
- if (!*p) {
- strcpy(p, str);
- p += strlen(str);
- *p++ = '\0';
- *p++ = '\0';
-
- return i;
- }
-
- if (!strcmp(p, str))
- return i;
-
- p += strlen(p) + 1;
- i++;
- }
-}
-
-/**
- * smbios_string_table_len() - compute the string area size
- *
- * This computes the size of the string area including the string terminator.
- *
- * @start: string area start address
- * @return: string area size
- */
-static int smbios_string_table_len(char *start)
-{
- char *p = start;
- int i, len = 0;
-
- while (*p) {
- i = strlen(p) + 1;
- p += i;
- len += i;
- }
-
- return len + 1;
-}
-
-static int smbios_write_type0(u32 *current, int handle)
-{
- struct smbios_type0 *t = (struct smbios_type0 *)*current;
- int len = sizeof(struct smbios_type0);
-
- memset(t, 0, sizeof(struct smbios_type0));
- fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, handle);
- t->vendor = smbios_add_string(t->eos, "U-Boot");
- t->bios_ver = smbios_add_string(t->eos, PLAIN_VERSION);
- t->bios_release_date = smbios_add_string(t->eos, U_BOOT_DMI_DATE);
- t->bios_rom_size = (CONFIG_ROM_SIZE / 65536) - 1;
- t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED |
- BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
- BIOS_CHARACTERISTICS_UPGRADEABLE;
-#ifdef CONFIG_GENERATE_ACPI_TABLE
- t->bios_characteristics_ext1 = BIOS_CHARACTERISTICS_EXT1_ACPI;
-#endif
- t->bios_characteristics_ext2 = BIOS_CHARACTERISTICS_EXT2_TARGET;
- t->bios_major_release = 0xff;
- t->bios_minor_release = 0xff;
- t->ec_major_release = 0xff;
- t->ec_minor_release = 0xff;
-
- len = t->length + smbios_string_table_len(t->eos);
- *current += len;
-
- return len;
-}
-
-static int smbios_write_type1(u32 *current, int handle)
-{
- struct smbios_type1 *t = (struct smbios_type1 *)*current;
- int len = sizeof(struct smbios_type1);
-
- memset(t, 0, sizeof(struct smbios_type1));
- fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
- t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
- t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
-
- len = t->length + smbios_string_table_len(t->eos);
- *current += len;
-
- return len;
-}
-
-static int smbios_write_type2(u32 *current, int handle)
-{
- struct smbios_type2 *t = (struct smbios_type2 *)*current;
- int len = sizeof(struct smbios_type2);
-
- memset(t, 0, sizeof(struct smbios_type2));
- fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
- t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
- t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
- t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
- t->board_type = SMBIOS_BOARD_MOTHERBOARD;
-
- len = t->length + smbios_string_table_len(t->eos);
- *current += len;
-
- return len;
-}
-
-static int smbios_write_type3(u32 *current, int handle)
-{
- struct smbios_type3 *t = (struct smbios_type3 *)*current;
- int len = sizeof(struct smbios_type3);
-
- memset(t, 0, sizeof(struct smbios_type3));
- fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle);
- t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
- t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP;
- t->bootup_state = SMBIOS_STATE_SAFE;
- t->power_supply_state = SMBIOS_STATE_SAFE;
- t->thermal_state = SMBIOS_STATE_SAFE;
- t->security_status = SMBIOS_SECURITY_NONE;
-
- len = t->length + smbios_string_table_len(t->eos);
- *current += len;
-
- return len;
-}
-
-static int smbios_write_type4(u32 *current, int handle)
-{
- struct smbios_type4 *t = (struct smbios_type4 *)*current;
- int len = sizeof(struct smbios_type4);
- const char *vendor;
- char *name;
- char processor_name[CPU_MAX_NAME_LEN];
- struct cpuid_result res;
-
- memset(t, 0, sizeof(struct smbios_type4));
- fill_smbios_header(t, SMBIOS_PROCESSOR_INFORMATION, len, handle);
- t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
- t->processor_family = gd->arch.x86;
- vendor = cpu_vendor_name(gd->arch.x86_vendor);
- t->processor_manufacturer = smbios_add_string(t->eos, vendor);
- res = cpuid(1);
- t->processor_id[0] = res.eax;
- t->processor_id[1] = res.edx;
- name = cpu_get_name(processor_name);
- t->processor_version = smbios_add_string(t->eos, name);
- t->status = SMBIOS_PROCESSOR_STATUS_ENABLED;
- t->processor_upgrade = SMBIOS_PROCESSOR_UPGRADE_NONE;
- t->l1_cache_handle = 0xffff;
- t->l2_cache_handle = 0xffff;
- t->l3_cache_handle = 0xffff;
- t->processor_family2 = t->processor_family;
-
- len = t->length + smbios_string_table_len(t->eos);
- *current += len;
-
- return len;
-}
-
-static int smbios_write_type32(u32 *current, int handle)
-{
- struct smbios_type32 *t = (struct smbios_type32 *)*current;
- int len = sizeof(struct smbios_type32);
-
- memset(t, 0, sizeof(struct smbios_type32));
- fill_smbios_header(t, SMBIOS_SYSTEM_BOOT_INFORMATION, len, handle);
-
- *current += len;
-
- return len;
-}
-
-static int smbios_write_type127(u32 *current, int handle)
-{
- struct smbios_type127 *t = (struct smbios_type127 *)*current;
- int len = sizeof(struct smbios_type127);
-
- memset(t, 0, sizeof(struct smbios_type127));
- fill_smbios_header(t, SMBIOS_END_OF_TABLE, len, handle);
-
- *current += len;
-
- return len;
-}
-
-static smbios_write_type smbios_write_funcs[] = {
- smbios_write_type0,
- smbios_write_type1,
- smbios_write_type2,
- smbios_write_type3,
- smbios_write_type4,
- smbios_write_type32,
- smbios_write_type127
-};
-
-u32 write_smbios_table(u32 addr)
-{
- struct smbios_entry *se;
- u32 tables;
- int len = 0;
- int max_struct_size = 0;
- int handle = 0;
- char *istart;
- int isize;
- int i;
-
- /* 16 byte align the table address */
- addr = ALIGN(addr, 16);
-
- se = (struct smbios_entry *)addr;
- memset(se, 0, sizeof(struct smbios_entry));
-
- addr += sizeof(struct smbios_entry);
- addr = ALIGN(addr, 16);
- tables = addr;
-
- /* populate minimum required tables */
- for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) {
- int tmp = smbios_write_funcs[i](&addr, handle++);
- max_struct_size = max(max_struct_size, tmp);
- len += tmp;
- }
-
- memcpy(se->anchor, "_SM_", 4);
- se->length = sizeof(struct smbios_entry);
- se->major_ver = SMBIOS_MAJOR_VER;
- se->minor_ver = SMBIOS_MINOR_VER;
- se->max_struct_size = max_struct_size;
- memcpy(se->intermediate_anchor, "_DMI_", 5);
- se->struct_table_length = len;
- se->struct_table_address = tables;
- se->struct_count = handle;
-
- /* calculate checksums */
- istart = (char *)se + SMBIOS_INTERMEDIATE_OFFSET;
- isize = sizeof(struct smbios_entry) - SMBIOS_INTERMEDIATE_OFFSET;
- se->intermediate_checksum = table_compute_checksum(istart, isize);
- se->checksum = table_compute_checksum(se, sizeof(struct smbios_entry));
-
- return addr;
-}
diff --git a/arch/x86/lib/string.c b/arch/x86/lib/string.c
index 6c66431..5343c2b 100644
--- a/arch/x86/lib/string.c
+++ b/arch/x86/lib/string.c
@@ -130,3 +130,164 @@
return dstpp;
}
+
+void *memmove(void *dest, const void *src, size_t n)
+{
+ int d0, d1, d2, d3, d4, d5;
+ char *ret = dest;
+
+ __asm__ __volatile__(
+ /* Handle more 16 bytes in loop */
+ "cmp $0x10, %0\n\t"
+ "jb 1f\n\t"
+
+ /* Decide forward/backward copy mode */
+ "cmp %2, %1\n\t"
+ "jb 2f\n\t"
+
+ /*
+ * movs instruction have many startup latency
+ * so we handle small size by general register.
+ */
+ "cmp $680, %0\n\t"
+ "jb 3f\n\t"
+ /* movs instruction is only good for aligned case */
+ "mov %1, %3\n\t"
+ "xor %2, %3\n\t"
+ "and $0xff, %3\n\t"
+ "jz 4f\n\t"
+ "3:\n\t"
+ "sub $0x10, %0\n\t"
+
+ /* We gobble 16 bytes forward in each loop */
+ "3:\n\t"
+ "sub $0x10, %0\n\t"
+ "mov 0*4(%1), %3\n\t"
+ "mov 1*4(%1), %4\n\t"
+ "mov %3, 0*4(%2)\n\t"
+ "mov %4, 1*4(%2)\n\t"
+ "mov 2*4(%1), %3\n\t"
+ "mov 3*4(%1), %4\n\t"
+ "mov %3, 2*4(%2)\n\t"
+ "mov %4, 3*4(%2)\n\t"
+ "lea 0x10(%1), %1\n\t"
+ "lea 0x10(%2), %2\n\t"
+ "jae 3b\n\t"
+ "add $0x10, %0\n\t"
+ "jmp 1f\n\t"
+
+ /* Handle data forward by movs */
+ ".p2align 4\n\t"
+ "4:\n\t"
+ "mov -4(%1, %0), %3\n\t"
+ "lea -4(%2, %0), %4\n\t"
+ "shr $2, %0\n\t"
+ "rep movsl\n\t"
+ "mov %3, (%4)\n\t"
+ "jmp 11f\n\t"
+ /* Handle data backward by movs */
+ ".p2align 4\n\t"
+ "6:\n\t"
+ "mov (%1), %3\n\t"
+ "mov %2, %4\n\t"
+ "lea -4(%1, %0), %1\n\t"
+ "lea -4(%2, %0), %2\n\t"
+ "shr $2, %0\n\t"
+ "std\n\t"
+ "rep movsl\n\t"
+ "mov %3,(%4)\n\t"
+ "cld\n\t"
+ "jmp 11f\n\t"
+
+ /* Start to prepare for backward copy */
+ ".p2align 4\n\t"
+ "2:\n\t"
+ "cmp $680, %0\n\t"
+ "jb 5f\n\t"
+ "mov %1, %3\n\t"
+ "xor %2, %3\n\t"
+ "and $0xff, %3\n\t"
+ "jz 6b\n\t"
+
+ /* Calculate copy position to tail */
+ "5:\n\t"
+ "add %0, %1\n\t"
+ "add %0, %2\n\t"
+ "sub $0x10, %0\n\t"
+
+ /* We gobble 16 bytes backward in each loop */
+ "7:\n\t"
+ "sub $0x10, %0\n\t"
+
+ "mov -1*4(%1), %3\n\t"
+ "mov -2*4(%1), %4\n\t"
+ "mov %3, -1*4(%2)\n\t"
+ "mov %4, -2*4(%2)\n\t"
+ "mov -3*4(%1), %3\n\t"
+ "mov -4*4(%1), %4\n\t"
+ "mov %3, -3*4(%2)\n\t"
+ "mov %4, -4*4(%2)\n\t"
+ "lea -0x10(%1), %1\n\t"
+ "lea -0x10(%2), %2\n\t"
+ "jae 7b\n\t"
+ /* Calculate copy position to head */
+ "add $0x10, %0\n\t"
+ "sub %0, %1\n\t"
+ "sub %0, %2\n\t"
+
+ /* Move data from 8 bytes to 15 bytes */
+ ".p2align 4\n\t"
+ "1:\n\t"
+ "cmp $8, %0\n\t"
+ "jb 8f\n\t"
+ "mov 0*4(%1), %3\n\t"
+ "mov 1*4(%1), %4\n\t"
+ "mov -2*4(%1, %0), %5\n\t"
+ "mov -1*4(%1, %0), %1\n\t"
+
+ "mov %3, 0*4(%2)\n\t"
+ "mov %4, 1*4(%2)\n\t"
+ "mov %5, -2*4(%2, %0)\n\t"
+ "mov %1, -1*4(%2, %0)\n\t"
+ "jmp 11f\n\t"
+
+ /* Move data from 4 bytes to 7 bytes */
+ ".p2align 4\n\t"
+ "8:\n\t"
+ "cmp $4, %0\n\t"
+ "jb 9f\n\t"
+ "mov 0*4(%1), %3\n\t"
+ "mov -1*4(%1, %0), %4\n\t"
+ "mov %3, 0*4(%2)\n\t"
+ "mov %4, -1*4(%2, %0)\n\t"
+ "jmp 11f\n\t"
+
+ /* Move data from 2 bytes to 3 bytes */
+ ".p2align 4\n\t"
+ "9:\n\t"
+ "cmp $2, %0\n\t"
+ "jb 10f\n\t"
+ "movw 0*2(%1), %%dx\n\t"
+ "movw -1*2(%1, %0), %%bx\n\t"
+ "movw %%dx, 0*2(%2)\n\t"
+ "movw %%bx, -1*2(%2, %0)\n\t"
+ "jmp 11f\n\t"
+
+ /* Move data for 1 byte */
+ ".p2align 4\n\t"
+ "10:\n\t"
+ "cmp $1, %0\n\t"
+ "jb 11f\n\t"
+ "movb (%1), %%cl\n\t"
+ "movb %%cl, (%2)\n\t"
+ ".p2align 4\n\t"
+ "11:"
+ : "=&c" (d0), "=&S" (d1), "=&D" (d2),
+ "=r" (d3), "=r" (d4), "=r"(d5)
+ : "0" (n),
+ "1" (src),
+ "2" (dest)
+ : "memory");
+
+ return ret;
+}
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index f92111e..5966e58 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -5,13 +5,20 @@
*/
#include <common.h>
+#include <smbios.h>
#include <asm/sfi.h>
#include <asm/mpspec.h>
-#include <asm/smbios.h>
#include <asm/tables.h>
#include <asm/acpi_table.h>
#include <asm/coreboot_tables.h>
+#ifdef CONFIG_GENERATE_SMBIOS_TABLE
+static u32 write_smbios_table_wrapper(u32 addr)
+{
+ return write_smbios_table(addr);
+}
+#endif
+
/**
* Function prototype to write a specific configuration table
*
@@ -34,22 +41,10 @@
write_acpi_tables,
#endif
#ifdef CONFIG_GENERATE_SMBIOS_TABLE
- write_smbios_table,
+ write_smbios_table_wrapper,
#endif
};
-u8 table_compute_checksum(void *v, int len)
-{
- u8 *bytes = v;
- u8 checksum = 0;
- int i;
-
- for (i = 0; i < len; i++)
- checksum -= bytes[i];
-
- return checksum;
-}
-
void table_fill_string(char *dest, const char *src, size_t n, char pad)
{
int start, len;
diff --git a/arch/xtensa/include/asm/errno.h b/arch/xtensa/include/asm/errno.h
deleted file mode 100644
index 4c82b50..0000000
--- a/arch/xtensa/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c
index 1332072..915eb51 100644
--- a/arch/xtensa/lib/time.c
+++ b/arch/xtensa/lib/time.c
@@ -104,10 +104,7 @@
*/
ulong get_tbclk(void)
{
- ulong tbclk;
-
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
+ return CONFIG_SYS_HZ;
}
#if XCHAL_HAVE_CCOUNT
diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
index 9315bb7..9c19c87 100644
--- a/board/Arcturus/ucp1020/spl.c
+++ b/board/Arcturus/ucp1020/spl.c
@@ -119,8 +119,6 @@
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c
index 0fc2bac..0d086e8 100644
--- a/board/Arcturus/ucp1020/ucp1020.c
+++ b/board/Arcturus/ucp1020/ucp1020.c
@@ -315,7 +315,7 @@
FT_FSL_PCI_SETUP;
#if defined(CONFIG_HAS_FSL_DR_USB)
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c
index 6ce8960..9747f32 100644
--- a/board/Barix/ipam390/ipam390.c
+++ b/board/Barix/ipam390/ipam390.c
@@ -25,7 +25,7 @@
#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <hwconfig.h>
#include <bootstage.h>
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
index 7f5cfc8..3cd4dc9 100644
--- a/board/CarMediaLab/flea3/flea3.c
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux-mx35.h>
@@ -19,6 +19,9 @@
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <netdev.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
#ifndef CONFIG_BOARD_EARLY_INIT_F
#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
@@ -27,18 +30,6 @@
#define CCM_CCMR_CONFIG 0x003F4208
#define ESDCTL_DDR2_CONFIG 0x007FFC3F
-#define ESDCTL_0x92220000 0x92220000
-#define ESDCTL_0xA2220000 0xA2220000
-#define ESDCTL_0xB2220000 0xB2220000
-#define ESDCTL_0x82228080 0x82228080
-#define ESDCTL_DDR2_EMR2 0x04000000
-#define ESDCTL_DDR2_EMR3 0x06000000
-#define ESDCTL_PRECHARGE 0x00000400
-#define ESDCTL_DDR2_EN_DLL 0x02000400
-#define ESDCTL_DDR2_RESET_DLL 0x00000333
-#define ESDCTL_DDR2_MR 0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-#define ESDCTL_DELAY_LINE5 0x00F49F00
static inline void dram_wait(unsigned int count)
{
@@ -58,83 +49,6 @@
return 0;
}
-static void board_setup_sdram_bank(u32 start_address)
-
-{
- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
- u32 *cfg_reg, *ctl_reg;
- u32 val;
-
- switch (start_address) {
- case CSD0_BASE_ADDR:
- cfg_reg = &esdc->esdcfg0;
- ctl_reg = &esdc->esdctl0;
- break;
- case CSD1_BASE_ADDR:
- cfg_reg = &esdc->esdcfg1;
- ctl_reg = &esdc->esdctl1;
- break;
- default:
- return;
- }
-
- /* Initialize MISC register for DDR2 */
- val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
- ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
- writel(val, &esdc->esdmisc);
- val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
- writel(val, &esdc->esdmisc);
-
- /*
- * according to DDR2 specs, wait a while before
- * the PRECHARGE_ALL command
- */
- dram_wait(0x20000);
-
- /* Load DDR2 config and timing */
- writel(ESDCTL_DDR2_CONFIG, cfg_reg);
-
- /* Precharge ALL */
- writel(ESDCTL_0x92220000,
- ctl_reg);
- writel(0xda, start_address + ESDCTL_PRECHARGE);
-
- /* Load mode */
- writel(ESDCTL_0xB2220000,
- ctl_reg);
- writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
- writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
- writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
- /* Precharge ALL */
- writel(ESDCTL_0x92220000,
- ctl_reg);
- writel(0xda, start_address + ESDCTL_PRECHARGE);
-
- /* Set mode auto refresh : at least two refresh are required */
- writel(ESDCTL_0xA2220000,
- ctl_reg);
- writel(0xda, start_address);
- writel(0xda, start_address);
-
- writel(ESDCTL_0xB2220000,
- ctl_reg);
- writeb(0xda, start_address + ESDCTL_DDR2_MR);
- writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
- /* OCD mode exit */
- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
- /* Set normal mode */
- writel(ESDCTL_0x82228080,
- ctl_reg);
-
- dram_wait(0x20000);
-
- /* Do not set delay lines, only for MDDR */
-}
-
static void board_setup_sdram(void)
{
struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
@@ -143,7 +57,9 @@
writel(0x2000, &esdc->esdctl0);
writel(0x2000, &esdc->esdctl1);
- board_setup_sdram_bank(CSD0_BASE_ADDR);
+
+ mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+ 13, 10, 2, 0x8080);
}
static void setup_iomux_uart3(void)
@@ -206,6 +122,8 @@
MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ /* GPIO used to power off ethernet */
+ MX35_PAD_STXFS4__GPIO2_31,
};
/* setup pins for FEC */
@@ -267,6 +185,11 @@
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ /* Enable power for ethernet */
+ gpio_direction_output(63, 0);
+
+ udelay(2000);
+
return 0;
}
@@ -276,3 +199,24 @@
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ struct node_info nodes[] = {
+ { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */
+ { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+ };
+
+ if (getenv("fdt_noauto")) {
+ puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
+ return 0;
+ }
+
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+ return 0;
+}
diff --git a/board/Marvell/db-88f6820-amc/MAINTAINERS b/board/Marvell/db-88f6820-amc/MAINTAINERS
new file mode 100644
index 0000000..abf5b7e
--- /dev/null
+++ b/board/Marvell/db-88f6820-amc/MAINTAINERS
@@ -0,0 +1,6 @@
+DB_88F6820_AMC BOARD
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: board/Marvell/db-88f6820-amc/
+F: include/configs/db-88f6820-amc.h
+F: configs/db-88f6820-amc_defconfig
diff --git a/board/Marvell/db-88f6820-amc/Makefile b/board/Marvell/db-88f6820-amc/Makefile
new file mode 100644
index 0000000..79e1a75
--- /dev/null
+++ b/board/Marvell/db-88f6820-amc/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := db-88f6820-amc.o
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
new file mode 100644
index 0000000..cade99c
--- /dev/null
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ETH_PHY_CTRL_REG 0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v10"
+ */
+#define DB_AMC_88F68XX_GPP_OUT_ENA_LOW \
+ (~(BIT(29)))
+#define DB_AMC_88F68XX_GPP_OUT_ENA_MID \
+ (~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
+#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT(29))
+#define DB_AMC_88F68XX_GPP_OUT_VAL_MID 0x0
+#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0
+#define DB_AMC_88F68XX_GPP_POL_LOW 0x0
+#define DB_AMC_88F68XX_GPP_POL_MID 0x0
+
+static struct serdes_map board_serdes_map[] = {
+ {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+ *serdes_map_array = board_serdes_map;
+ *count = ARRAY_SIZE(board_serdes_map);
+ return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1866L, /* speed_bin */
+ BUS_WIDTH_8, /* memory_width */
+ MEM_4G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_LOW} }, /* temperature */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+ /* Return the board topology as defined in the board code */
+ return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+ writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+ writel(0x55066011, MVEBU_MPP_BASE + 0x08);
+ writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
+ writel(0x05055555, MVEBU_MPP_BASE + 0x10);
+ writel(0x01106565, MVEBU_MPP_BASE + 0x14);
+ writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+ writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+ /* Set GPP Out value */
+ writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Marvell DB-88F6820-AMC\n");
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in controller(s) come first */
+ return pci_eth_init(bis);
+}
diff --git a/board/Marvell/db-88f6820-amc/kwbimage.cfg b/board/Marvell/db-88f6820-amc/kwbimage.cfg
new file mode 100644
index 0000000..1f748db
--- /dev/null
+++ b/board/Marvell/db-88f6820-amc/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/Marvell/gplugd/MAINTAINERS b/board/Marvell/gplugd/MAINTAINERS
index 320bc09..197c6a0 100644
--- a/board/Marvell/gplugd/MAINTAINERS
+++ b/board/Marvell/gplugd/MAINTAINERS
@@ -1,5 +1,5 @@
GPLUGD BOARD
-M: Ajay Bhargav <ajay.bhargav@einfochips.com>
+M: Ajay Bhargav <contact@8051projects.net>
S: Maintained
F: board/Marvell/gplugd/
F: include/configs/gplugd.h
diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile
index b384578..8929da5 100644
--- a/board/Marvell/gplugd/Makefile
+++ b/board/Marvell/gplugd/Makefile
@@ -1,7 +1,7 @@
#
# (C) Copyright 2011
# eInfochips Ltd. <www.einfochips.com>
-# Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+# Written-by: Ajay Bhargav <contact@8051projects.net>
#
# Based on Aspenite:
# (C) Copyright 2010
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index 0e8ebcc..c8c4ad2 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* Based on Aspenite:
* (C) Copyright 2010
diff --git a/board/Marvell/mvebu_armada-8k/MAINTAINERS b/board/Marvell/mvebu_armada-8k/MAINTAINERS
new file mode 100644
index 0000000..e0b965d
--- /dev/null
+++ b/board/Marvell/mvebu_armada-8k/MAINTAINERS
@@ -0,0 +1,7 @@
+MVEBU_ARMADA_8K BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/Marvell/mvebu_armada-8k/
+F: include/configs/mvebu_armada-8k.h
+F: configs/mvebu_db-88f7040_defconfig
+F: configs/mvebu_db-88f8040_defconfig
diff --git a/board/Marvell/mvebu_armada-8k/Makefile b/board/Marvell/mvebu_armada-8k/Makefile
new file mode 100644
index 0000000..ed39738
--- /dev/null
+++ b/board/Marvell/mvebu_armada-8k/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c
new file mode 100644
index 0000000..7d1b5d9
--- /dev/null
+++ b/board/Marvell/mvebu_armada-8k/board.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Information specific to the DB-88F7040 eval board. We strive to use
+ * DT for such platform specfic configurations. At some point, this
+ * might be removed here and implemented via DT.
+ */
+/* IO expander I2C device */
+#define I2C_IO_EXP_ADDR 0x21
+#define I2C_IO_CFG_REG_0 0x6
+#define I2C_IO_DATA_OUT_REG_0 0x2
+/* VBus enable */
+#define I2C_IO_REG_0_USB_H0_OFF 0
+#define I2C_IO_REG_0_USB_H1_OFF 1
+#define I2C_IO_REG_VBUS ((1 << I2C_IO_REG_0_USB_H0_OFF) | \
+ (1 << I2C_IO_REG_0_USB_H1_OFF))
+/* Current limit */
+#define I2C_IO_REG_0_USB_H0_CL 4
+#define I2C_IO_REG_0_USB_H1_CL 5
+#define I2C_IO_REG_CL ((1 << I2C_IO_REG_0_USB_H0_CL) | \
+ (1 << I2C_IO_REG_0_USB_H1_CL))
+
+static int usb_enabled = 0;
+
+/* Board specific xHCI dis-/enable code */
+
+/*
+ * Set USB VBUS signals (via I2C IO expander/GPIO) as output and set
+ * output value as disabled
+ *
+ * Set USB Current Limit signals (via I2C IO expander/GPIO) as output
+ * and set output value as enabled
+ */
+int board_xhci_config(void)
+{
+ struct udevice *dev;
+ int ret;
+ u8 buf[8];
+
+ if (of_machine_is_compatible("marvell,armada7040-db")) {
+ /* Configure IO exander PCA9555: 7bit address 0x21 */
+ ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+ if (ret) {
+ printf("Cannot find PCA9555: %d\n", ret);
+ return 0;
+ }
+
+ /*
+ * Read configuration (direction) and set VBUS pin as output
+ * (reset pin = output)
+ */
+ ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to read IO expander value via I2C\n");
+ return -EIO;
+ }
+ buf[0] &= ~I2C_IO_REG_VBUS;
+ buf[0] &= ~I2C_IO_REG_CL;
+ ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to set IO expander via I2C\n");
+ return -EIO;
+ }
+
+ /* Read output value and configure it */
+ ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to read IO expander value via I2C\n");
+ return -EIO;
+ }
+ buf[0] &= ~I2C_IO_REG_VBUS;
+ buf[0] |= I2C_IO_REG_CL;
+ ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to set IO expander via I2C\n");
+ return -EIO;
+ }
+
+ mdelay(500); /* required delay to let output value settle */
+ }
+
+ return 0;
+}
+
+int board_xhci_enable(void)
+{
+ struct udevice *dev;
+ int ret;
+ u8 buf[8];
+
+ if (of_machine_is_compatible("marvell,armada7040-db")) {
+ /*
+ * This function enables all USB ports simultaniously,
+ * it only needs to get called once
+ */
+ if (usb_enabled)
+ return 0;
+
+ /* Configure IO exander PCA9555: 7bit address 0x21 */
+ ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+ if (ret) {
+ printf("Cannot find PCA9555: %d\n", ret);
+ return 0;
+ }
+
+ /* Read VBUS output value */
+ ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to read IO expander value via I2C\n");
+ return -EIO;
+ }
+
+ /* Enable VBUS power: Set output value of VBUS pin as enabled */
+ buf[0] |= I2C_IO_REG_VBUS;
+ ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to set IO expander via I2C\n");
+ return -EIO;
+ }
+
+ mdelay(500); /* required delay to let output value settle */
+ usb_enabled = 1;
+ }
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /* Nothing to do (yet), perhaps later some pin-muxing etc */
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ /* Pre-configure the USB ports (overcurrent, VBus) */
+ board_xhci_config();
+
+ return 0;
+}
diff --git a/board/Marvell/mvebu_db-88f3720/MAINTAINERS b/board/Marvell/mvebu_db-88f3720/MAINTAINERS
new file mode 100644
index 0000000..4e80917
--- /dev/null
+++ b/board/Marvell/mvebu_db-88f3720/MAINTAINERS
@@ -0,0 +1,6 @@
+MVEBU_DB_88F3720 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/Marvell/mvebu_db-88f3720/
+F: include/configs/mvebu_db-88f3720.h
+F: configs/mvebu_db-88f3720_defconfig
diff --git a/board/Marvell/mvebu_db-88f3720/Makefile b/board/Marvell/mvebu_db-88f3720/Makefile
new file mode 100644
index 0000000..ed39738
--- /dev/null
+++ b/board/Marvell/mvebu_db-88f3720/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/Marvell/mvebu_db-88f3720/board.c b/board/Marvell/mvebu_db-88f3720/board.c
new file mode 100644
index 0000000..edf88c7
--- /dev/null
+++ b/board/Marvell/mvebu_db-88f3720/board.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO expander I2C device */
+#define I2C_IO_EXP_ADDR 0x22
+#define I2C_IO_CFG_REG_0 0x6
+#define I2C_IO_DATA_OUT_REG_0 0x2
+#define I2C_IO_REG_0_SATA_OFF 2
+#define I2C_IO_REG_0_USB_H_OFF 1
+
+int board_early_init_f(void)
+{
+ /* Nothing to do (yet), perhaps later some pin-muxing etc */
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/* Board specific AHCI / SATA enable code */
+int board_ahci_enable(void)
+{
+ struct udevice *dev;
+ int ret;
+ u8 buf[8];
+
+ /* Configure IO exander PCA9555: 7bit address 0x22 */
+ ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+ if (ret) {
+ printf("Cannot find PCA9555: %d\n", ret);
+ return 0;
+ }
+
+ ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to read IO expander value via I2C\n");
+ return -EIO;
+ }
+
+ /*
+ * Enable SATA power via IO expander connected via I2C by setting
+ * the corresponding bit to output mode to enable power for SATA
+ */
+ buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
+ ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to set IO expander via I2C\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/* Board specific xHCI enable code */
+int board_xhci_enable(void)
+{
+ struct udevice *dev;
+ int ret;
+ u8 buf[8];
+
+ /* Configure IO exander PCA9555: 7bit address 0x22 */
+ ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+ if (ret) {
+ printf("Cannot find PCA9555: %d\n", ret);
+ return 0;
+ }
+
+ printf("Enable USB VBUS\n");
+
+ /*
+ * Read configuration (direction) and set VBUS pin as output
+ * (reset pin = output)
+ */
+ ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to read IO expander value via I2C\n");
+ return -EIO;
+ }
+ buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
+ ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to set IO expander via I2C\n");
+ return -EIO;
+ }
+
+ /* Read VBUS output value and disable it */
+ ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to read IO expander value via I2C\n");
+ return -EIO;
+ }
+ buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
+ ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to set IO expander via I2C\n");
+ return -EIO;
+ }
+
+ /*
+ * Required delay for configuration to settle - must wait for
+ * power on port is disabled in case VBUS signal was high,
+ * required 3 seconds delay to let VBUS signal fully settle down
+ */
+ mdelay(3000);
+
+ /* Enable VBUS power: Set output value of VBUS pin as enabled */
+ buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
+ ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+ if (ret) {
+ printf("Failed to set IO expander via I2C\n");
+ return -EIO;
+ }
+
+ mdelay(500); /* required delay to let output value settle */
+
+ return 0;
+}
diff --git a/board/Synology/ds109/Kconfig b/board/Synology/ds109/Kconfig
new file mode 100644
index 0000000..a7c75ae
--- /dev/null
+++ b/board/Synology/ds109/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DS109
+
+config SYS_BOARD
+ default "ds109"
+
+config SYS_VENDOR
+ default "Synology"
+
+config SYS_CONFIG_NAME
+ default "ds109"
+
+endif
diff --git a/board/Synology/ds109/MAINTAINERS b/board/Synology/ds109/MAINTAINERS
new file mode 100644
index 0000000..8783fdb
--- /dev/null
+++ b/board/Synology/ds109/MAINTAINERS
@@ -0,0 +1,6 @@
+DS109 BOARD
+M: Walter Schweizer <swwa@users.sourceforge.net>
+S: Maintained
+F: board/Synology/ds109
+F: configs/ds109_defconfig
+F: include/configs/ds109.h
diff --git a/board/Synology/ds109/Makefile b/board/Synology/ds109/Makefile
new file mode 100644
index 0000000..eeeb64d
--- /dev/null
+++ b/board/Synology/ds109/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ds109.o
diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c
new file mode 100644
index 0000000..b46c09d
--- /dev/null
+++ b/board/Synology/ds109/ds109.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "ds109.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(DS109_OE_VAL_LOW,
+ DS109_OE_VAL_HIGH,
+ DS109_OE_LOW, DS109_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn, /* SPI Flash */
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_GPIO,
+ MPP5_GPO,
+ MPP6_SYSRST_OUTn, /* Reset signal */
+ MPP7_GPO,
+ MPP8_TW_SDA, /* I2C */
+ MPP9_TW_SCK, /* I2C */
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_UART1_TXD,
+ MPP14_UART1_RXD,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_GPO,
+ MPP19_GPO,
+ MPP20_SATA1_ACTn,
+ MPP21_SATA0_ACTn,
+ MPP22_GPIO, /* HDD2 FAIL LED */
+ MPP23_GPIO, /* HDD1 FAIL LED */
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO, /* HDD2 */
+ MPP32_GPIO, /* FAN A */
+ MPP33_GPIO, /* FAN B */
+ MPP34_GPIO, /* FAN C */
+ MPP35_GPIO, /* FAN SENSE */
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+/* Synology reset uses UART */
+#include <ns16550.h>
+#define SOFTWARE_SHUTDOWN 0x31
+#define SOFTWARE_REBOOT 0x43
+#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
+void reset_misc(void)
+{
+ int b_d;
+ printf("Synology reset...");
+ udelay(50000);
+
+ b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
+ CONFIG_SYS_NS16550_CLK, 9600);
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
+}
+
+/* Support old kernels */
+void setup_board_tags(struct tag **in_params)
+{
+ unsigned int boardId;
+ struct tag *params;
+ struct tag_mv_uboot *t;
+ int i;
+
+ printf("Synology board tags...");
+ params = *in_params;
+ t = (struct tag_mv_uboot *)¶ms->u;
+
+ t->uboot_version = VER_NUM;
+
+ boardId = SYNO_DS109_ID;
+ t->uboot_version |= boardId;
+
+ t->tclk = CONFIG_SYS_TCLK;
+ t->sysclk = CONFIG_SYS_TCLK*2;
+
+ t->isusbhost = 1;
+ for (i = 0; i < 4; i++) {
+ memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
+ t->mtu[i] = 0;
+ }
+
+ params->hdr.tag = ATAG_MV_UBOOT;
+ params->hdr.size = tag_size(tag_mv_uboot);
+ params = tag_next(params);
+ *in_params = params;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+ printf("Error: 88E1116 could not read PHY dev address\n");
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Synology/ds109/ds109.h b/board/Synology/ds109/ds109.h
new file mode 100644
index 0000000..a57cda7
--- /dev/null
+++ b/board/Synology/ds109/ds109.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DS109_H
+#define __DS109_H
+
+#define DS109_OE_LOW (0)
+#define DS109_OE_HIGH (0)
+#define DS109_OE_VAL_LOW ((1 << 22)|(1 << 23))
+#define DS109_OE_VAL_HIGH ((1 << 1)|1)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_MAC_CTRL2_REG 21
+
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+/* Marvell uboot parameters */
+#define ATAG_MV_UBOOT 0x41000403
+#define VER_NUM 0x03040400 /* 3.4.4 */
+#define BOARD_ID_BASE 0x0
+#define SYNO_DS109_ID (BOARD_ID_BASE+0x15)
+
+struct tag_mv_uboot {
+ u32 uboot_version;
+ u32 tclk;
+ u32 sysclk;
+ u32 isusbhost;
+ char macaddr[4][6];
+ u16 mtu[4];
+ u32 fw_image_base;
+ u32 fw_image_size;
+};
+
+#endif /* __DS109_H */
diff --git a/board/Synology/ds109/kwbimage.cfg b/board/Synology/ds109/kwbimage.cfg
new file mode 100644
index 0000000..d544af5
--- /dev/null
+++ b/board/Synology/ds109/kwbimage.cfg
@@ -0,0 +1,152 @@
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD20134 0xbbbbbbbb
+DATA 0xFFD20138 0x00bbbbbb
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d # DDR Address Control
+# bit1-0: 01, Cs0width=x8
+# bit3-2: 10, Cs0size=1Gb
+# bit5-4: 01, Cs1width=x8
+# bit7-6: 10, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Synology/ds109/openocd.cfg b/board/Synology/ds109/openocd.cfg
new file mode 100644
index 0000000..baa512a
--- /dev/null
+++ b/board/Synology/ds109/openocd.cfg
@@ -0,0 +1,115 @@
+# Synology DS109
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x000b
+ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
+
+adapter_khz 2000
+
+# length of reset signal: [ms]
+adapter_nsrst_assert_width 1000
+
+# don't talk to JTAG after reset for: [ms]
+adapter_nsrst_delay 200
+
+source [find target/feroceon.cfg]
+
+reset_config trst_and_srst srst_nogate
+
+proc ds109_init { } {
+
+ # We need to assert DBGRQ while holding nSRST down.
+ # However DBGACK will be set only when nSRST is released.
+ # Furthermore, the JTAG interface doesn't respond at all when
+ # the CPU is in the WFI (wait for interrupts) state, so it is
+ # possible that initial tap examination failed. So let's
+ # re-examine the target again here when nSRST is asserted which
+ # should then succeed.
+ jtag_reset 0 1
+ feroceon.cpu arp_examine
+ halt 0
+ jtag_reset 0 0
+ wait_halt
+ #reset run
+ #soft_reset_halt
+
+ arm mcr 15 0 0 1 0 0x00052078
+
+ mww 0xD00100e0 0x1b1b1b9b ;#
+ mww 0xD0020134 0xbbbbbbbb ;#
+ mww 0xD0020138 0x00bbbbbb ;#
+ mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
+ mww 0xD0001404 0x39743000 ;# Dunit Control Low Register
+ mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
+ mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
+ mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
+ mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
+ mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
+ mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
+ mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
+ mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register
+ mww 0xD0001428 0x00085520 ;# Dunit Control High Register
+ mww 0xD000147c 0x00008552 ;# Dunit Control High Register
+ mww 0xD0001500 0x00000000 ;#
+ mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register
+ mww 0xD0001508 0x10000000 ;# CS1n Base Register
+ mww 0xD000150C 0x00000000 ;# CS1n Size Register
+ mww 0xD0001510 0x20000000 ;#
+ mww 0xD0001514 0x00000000 ;# CS2n Size Register
+ mww 0xD000151C 0x00000000 ;# CS3n Size Register
+ mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
+ mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
+ mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
+ mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
+ mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+
+ mww 0xD0010000 0x01111111 ;# MPP 0 to 7
+ mww 0xD0010004 0x11113322 ;# MPP 8 to 15
+ mww 0xD0010008 0x00001111 ;# MPP 16 to 23
+}
+
+proc ds109_load { } {
+ # load u-Boot into RAM and execute it
+ ds109_init
+ load_image u-boot.bin 0x00600000 bin
+ resume 0x00600000
+}
diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c
index f0f1976..20750fb 100644
--- a/board/advantech/dms-ba16/dms-ba16.c
+++ b/board/advantech/dms-ba16/dms-ba16.c
@@ -10,7 +10,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
diff --git a/board/alphaproject/ap_sh4a_4a/Makefile b/board/alphaproject/ap_sh4a_4a/Makefile
index 486d0ac..df76466 100644
--- a/board/alphaproject/ap_sh4a_4a/Makefile
+++ b/board/alphaproject/ap_sh4a_4a/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := ap_sh4a_4a.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
index e65befc..31418a1 100644
--- a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
+++ b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
@@ -11,8 +11,6 @@
#include <netdev.h>
#include <i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODEMR (0xFFCC0020)
#define MODEMR_MASK (0x6)
#define MODEMR_533MHZ (0x2)
@@ -172,12 +170,3 @@
return 0;
}
-
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
- return 0;
-}
diff --git a/board/altera/arria5-socdk/MAINTAINERS b/board/altera/arria5-socdk/MAINTAINERS
index ba35b36..873ec2b 100644
--- a/board/altera/arria5-socdk/MAINTAINERS
+++ b/board/altera/arria5-socdk/MAINTAINERS
@@ -1,5 +1,5 @@
SOCFPGA BOARD
-M: Dinh Nguyen <dinguyen@opensource.altera.com>
+M: Dinh Nguyen <dinguyen@kernel.org>
M: Chin-Liang See <clsee@altera.com>
S: Maintained
F: board/altera/arria5-socdk/
diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h
index e9fe60f..2589f3f 100644
--- a/board/altera/arria5-socdk/qts/sdram_config.h
+++ b/board/altera/arria5-socdk/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
diff --git a/board/altera/cyclone5-socdk/MAINTAINERS b/board/altera/cyclone5-socdk/MAINTAINERS
index 6374d59..ecf1d04 100644
--- a/board/altera/cyclone5-socdk/MAINTAINERS
+++ b/board/altera/cyclone5-socdk/MAINTAINERS
@@ -1,5 +1,5 @@
SOCFPGA BOARD
-M: Dinh Nguyen <dinguyen@opensource.altera.com>
+M: Dinh Nguyen <dinguyen@kernel.org>
M: Chin-Liang See <clsee@altera.com>
S: Maintained
F: board/altera/cyclone5-socdk/
diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h
index 37c1476..8f3ddce 100644
--- a/board/altera/cyclone5-socdk/qts/sdram_config.h
+++ b/board/altera/cyclone5-socdk/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
diff --git a/board/amcc/acadia/Kconfig b/board/amcc/acadia/Kconfig
index 7c0ef53..033deaf 100644
--- a/board/amcc/acadia/Kconfig
+++ b/board/amcc/acadia/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "acadia"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig
index d44a36a..c0bd40a 100644
--- a/board/amcc/bamboo/Kconfig
+++ b/board/amcc/bamboo/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "bamboo"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index c8d0963..2838f9a 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -438,11 +438,7 @@
phys_size_t initdram (int board_type)
{
- long dram_size;
-
- dram_size = spd_sdram();
-
- return dram_size;
+ return spd_sdram();
}
/*----------------------------------------------------------------------------+
diff --git a/board/amcc/bubinga/Kconfig b/board/amcc/bubinga/Kconfig
index fc40f6e..540d9b6 100644
--- a/board/amcc/bubinga/Kconfig
+++ b/board/amcc/bubinga/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "bubinga"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
index 5c1e071..9043de6 100644
--- a/board/amcc/bubinga/bubinga.c
+++ b/board/amcc/bubinga/bubinga.c
@@ -57,8 +57,5 @@
------------------------------------------------------------------------- */
phys_size_t initdram(int board_type)
{
- long int ret;
-
- ret = spd_sdram();
- return ret;
+ return spd_sdram();
}
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig
index a655dbc..cea6009 100644
--- a/board/amcc/canyonlands/Kconfig
+++ b/board/amcc/canyonlands/Kconfig
@@ -30,8 +30,4 @@
endchoice
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index dc2e3ba..6ea004c 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -15,7 +15,7 @@
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
#include <asm/ppc4xx-gpio.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <usb.h>
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
@@ -63,11 +63,7 @@
*/
static inline int board_fpga_read(int offset)
{
- int data;
-
- data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
-
- return data;
+ return in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
}
static inline void board_fpga_write(int offset, int data)
diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig
index 59d3ef5..fc606cf 100644
--- a/board/amcc/katmai/Kconfig
+++ b/board/amcc/katmai/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "katmai"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 6ae340b..7582d40 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -15,7 +15,7 @@
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/4xx_pcie.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/amcc/kilauea/Kconfig b/board/amcc/kilauea/Kconfig
index 5dfd9eb..3f2f434 100644
--- a/board/amcc/kilauea/Kconfig
+++ b/board/amcc/kilauea/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "kilauea"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index abfaa1e..2937217 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -12,7 +12,7 @@
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
diff --git a/board/amcc/luan/Kconfig b/board/amcc/luan/Kconfig
index 36b44ff..3df90af 100644
--- a/board/amcc/luan/Kconfig
+++ b/board/amcc/luan/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "luan"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig
index 7f8498a..31ce5f1 100644
--- a/board/amcc/makalu/Kconfig
+++ b/board/amcc/makalu/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "makalu"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index a6ad2a1..2194942 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -13,7 +13,7 @@
#include <asm/ppc4xx-gpio.h>
#include <asm/io.h>
#include <fdt_support.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
diff --git a/board/amcc/redwood/Kconfig b/board/amcc/redwood/Kconfig
index fee6441..d710590 100644
--- a/board/amcc/redwood/Kconfig
+++ b/board/amcc/redwood/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "redwood"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig
index 6e6e408..67ee3ca 100644
--- a/board/amcc/sequoia/Kconfig
+++ b/board/amcc/sequoia/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "sequoia"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/walnut/Kconfig b/board/amcc/walnut/Kconfig
index d4c451d..94e3dc9 100644
--- a/board/amcc/walnut/Kconfig
+++ b/board/amcc/walnut/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "walnut"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/yosemite/Kconfig b/board/amcc/yosemite/Kconfig
index ec51236..dfa1068 100644
--- a/board/amcc/yosemite/Kconfig
+++ b/board/amcc/yosemite/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "yosemite"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/yucca/Kconfig b/board/amcc/yucca/Kconfig
index 338b6a9..61d9589 100644
--- a/board/amcc/yucca/Kconfig
+++ b/board/amcc/yucca/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "yucca"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index c0445ef..8ee3851 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -16,7 +16,7 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/4xx_pcie.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "yucca.h"
diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
index b8fed2e..94e2b8a 100644
--- a/board/aristainetos/aristainetos-v1.c
+++ b/board/aristainetos/aristainetos-v1.c
@@ -14,7 +14,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c
index fa4b4d2..4cd184e 100644
--- a/board/aristainetos/aristainetos-v2.c
+++ b/board/aristainetos/aristainetos-v2.c
@@ -14,7 +14,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index d1e6850..b7c65ca 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -14,7 +14,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
index 30e720d..29995ea 100644
--- a/board/armadeus/apf27/apf27.c
+++ b/board/armadeus/apf27/apf27.c
@@ -16,7 +16,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "apf27.h"
#include "crc.h"
#include "fpga.h"
diff --git a/board/armltd/vexpress/vexpress_tc2.c b/board/armltd/vexpress/vexpress_tc2.c
index ebb41a8..c7adf95 100644
--- a/board/armltd/vexpress/vexpress_tc2.c
+++ b/board/armltd/vexpress/vexpress_tc2.c
@@ -7,7 +7,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <asm/armv7.h>
#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <common.h>
+#include <libfdt.h>
#define SCC_BASE 0x7fff0000
@@ -31,3 +35,51 @@
return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0;
#endif
}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ int offset, tmp, len;
+ const struct fdt_property *prop;
+ const char *cci_compatible = "arm,cci-400-ctrl-if";
+
+#ifdef CONFIG_ARMV7_NONSEC
+ if (!armv7_boot_nonsec())
+ return 0;
+#else
+ return 0;
+#endif
+ /* Booting in nonsec mode, disable CCI access */
+ offset = fdt_path_offset(fdt, "/cpus");
+ if (offset < 0) {
+ printf("couldn't find /cpus\n");
+ return offset;
+ }
+
+ /* delete cci-control-port in each cpu node */
+ for (tmp = fdt_first_subnode(fdt, offset); tmp >= 0;
+ tmp = fdt_next_subnode(fdt, tmp))
+ fdt_delprop(fdt, tmp, "cci-control-port");
+
+ /* disable all ace cci slave ports */
+ offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible",
+ cci_compatible, 20);
+ while (offset > 0) {
+ prop = fdt_get_property(fdt, offset, "interface-type",
+ &len);
+ if (!prop)
+ continue;
+ if (len < 4)
+ continue;
+ if (strcmp(prop->data, "ace"))
+ continue;
+
+ fdt_setprop_string(fdt, offset, "status", "disabled");
+
+ offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible",
+ cci_compatible, 20);
+ }
+
+ return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
index b3fb09c..0608a5a 100644
--- a/board/armltd/vexpress64/pcie.c
+++ b/board/armltd/vexpress64/pcie.c
@@ -123,7 +123,7 @@
base += XR3PCI_ATR_TABLE_SIZE;
/* setup IO space translation */
- xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, XR3_PCI_IOSPACE_START,
+ xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
base += XR3PCI_ATR_TABLE_SIZE;
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 93df7ba..c5337af 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -7,6 +7,9 @@
#include <common.h>
#include <atmel_hlcdc.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <i2c.h>
#include <lcd.h>
#include <mmc.h>
#include <net.h>
@@ -25,32 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
-}
-
-static void board_spi0_hw_init(void)
-{
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
-
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
-
- at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-
static void board_usb_hw_init(void)
{
atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
@@ -157,55 +134,6 @@
at91_periph_clk_enable(ATMEL_ID_GMAC);
}
-static void board_sdhci0_hw_init(void)
-{
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SDMMC0_CK */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SDMMC0_CMD */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SDMMC0_DAT0 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* SDMMC0_DAT1 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* SDMMC0_DAT2 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* SDMMC0_DAT3 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0); /* SDMMC0_DAT4 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0); /* SDMMC0_DAT5 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0); /* SDMMC0_DAT6 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SDMMC0_CD */
-
- at91_periph_clk_enable(ATMEL_ID_SDMMC0);
- at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
- GCK_CSS_UPLL_CLK, 1);
-}
-
-static void board_sdhci1_hw_init(void)
-{
- atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */
- atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0); /* SDMMC1_DAT1 */
- atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0); /* SDMMC1_DAT2 */
- atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0); /* SDMMC1_DAT3 */
- atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0); /* SDMMC1_CK */
- atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0); /* SDMMC1_RSTN */
- atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0); /* SDMMC1_CMD */
- atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0); /* SDMMC1_CD */
-
- at91_periph_clk_enable(ATMEL_ID_SDMMC1);
- at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
- GCK_CSS_UPLL_CLK, 1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_ATMEL_SDHCI0
- atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0);
-#endif
-#ifdef CONFIG_ATMEL_SDHCI1
- atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1);
-#endif
-
- return 0;
-}
-
static void board_uart1_hw_init(void)
{
atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */
@@ -214,34 +142,31 @@
at91_periph_clk_enable(ATMEL_ID_UART1);
}
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ board_uart1_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
- at91_periph_clk_enable(ATMEL_ID_PIOD);
-
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#else
board_uart1_hw_init();
+#endif
return 0;
}
+#endif
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#ifdef CONFIG_ATMEL_SPI
- board_spi0_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SDHCI
-#ifdef CONFIG_ATMEL_SDHCI0
- board_sdhci0_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SDHCI1
- board_sdhci1_hw_init();
-#endif
-#endif
#ifdef CONFIG_MACB
board_gmac_hw_init();
#endif
@@ -283,21 +208,59 @@
return rc;
}
+#ifdef CONFIG_CMD_I2C
+static int set_ethaddr_from_eeprom(void)
+{
+ const int ETH_ADDR_LEN = 6;
+ unsigned char ethaddr[ETH_ADDR_LEN];
+ const char *ETHADDR_NAME = "ethaddr";
+ struct udevice *bus, *dev;
+
+ if (getenv(ETHADDR_NAME))
+ return 0;
+
+ if (uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)) {
+ printf("Cannot find I2C bus 1\n");
+ return -1;
+ }
+
+ if (dm_i2c_probe(bus, AT24MAC_ADDR, 0, &dev)) {
+ printf("Failed to probe I2C chip\n");
+ return -1;
+ }
+
+ if (dm_i2c_read(dev, AT24MAC_REG, ethaddr, ETH_ADDR_LEN)) {
+ printf("Failed to read ethernet address from EEPROM\n");
+ return -1;
+ }
+
+ if (!is_valid_ethaddr(ethaddr)) {
+ printf("The ethernet address read from EEPROM is not valid!\n");
+ return -1;
+ }
+
+ return eth_setenv_enetaddr(ETHADDR_NAME, ethaddr);
+}
+#else
+static int set_ethaddr_from_eeprom(void)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ set_ethaddr_from_eeprom();
+
+ return 0;
+}
+#endif
+
/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
-#ifdef CONFIG_SYS_USE_SERIALFLASH
- board_spi0_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SDHCI
-#ifdef CONFIG_ATMEL_SDHCI0
- board_sdhci0_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SDHCI1
- board_sdhci1_hw_init();
-#endif
-#endif
}
static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
diff --git a/board/barco/titanium/imximage.cfg b/board/barco/titanium/imximage.cfg
index 7219256..4fb6982 100644
--- a/board/barco/titanium/imximage.cfg
+++ b/board/barco/titanium/imximage.cfg
@@ -7,7 +7,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/beckhoff/mx53cx9020/Kconfig b/board/beckhoff/mx53cx9020/Kconfig
new file mode 100644
index 0000000..dcdafb6
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX53CX9020
+
+config SYS_BOARD
+ default "mx53cx9020"
+
+config SYS_VENDOR
+ default "beckhoff"
+
+config SYS_CONFIG_NAME
+ default "mx53cx9020"
+
+endif
diff --git a/board/beckhoff/mx53cx9020/MAINTAINERS b/board/beckhoff/mx53cx9020/MAINTAINERS
new file mode 100644
index 0000000..f84413e
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/MAINTAINERS
@@ -0,0 +1,6 @@
+MX53 CX9020
+M: Patrick Bruenn <p.bruenn@beckhoff.com>
+S: Maintained
+F: board/beckhoff/mx53cx9020/
+F: include/configs/mx53cx9020.h
+F: configs/mx53cx9020_defconfig
diff --git a/board/beckhoff/mx53cx9020/Makefile b/board/beckhoff/mx53cx9020/Makefile
new file mode 100644
index 0000000..a01c0f1
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
+# Patrick Bruenn <p.bruenn@beckhoff.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mx53cx9020.o
+obj-$(CONFIG_VIDEO) += mx53cx9020_video.o
diff --git a/board/beckhoff/mx53cx9020/imximage.cfg b/board/beckhoff/mx53cx9020/imximage.cfg
new file mode 100644
index 0000000..a11d04c
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/imximage.cfg
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2015 Beckhoff Automation GmbH
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Based on <u-boot>/board/freescale/mx53loco/imximage.cfg
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x00000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0x83190000
+DATA 4 0x63fd900c 0x40425333
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c
new file mode 100644
index 0000000..9b3ac22
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/mx53cx9020.c
@@ -0,0 +1,367 @@
+/*
+ * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/imx-common/mx5_video.h>
+#include <ACEX1K.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <fs.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_mxc.h>
+
+enum LED_GPIOS {
+ GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
+ GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
+ GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
+ GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
+ GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
+ GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
+ GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
+ GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
+ GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
+ GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
+ GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
+ GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
+ GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
+ GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
+ GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
+};
+
+#define CCAT_BASE_ADDR ((void *)0xf0000000)
+#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
+#define CCAT_SIZE 1191788
+#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
+static const char CCAT_SIGNATURE[] = "CCAT";
+
+static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
+static const u32 CCAT_MODE_RUN = 0x0033DC8F;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
+{
+ /*
+ * WARNING: We must override get_effective_memsize() function here
+ * to report only the size of the first DRAM bank. This is to make
+ * U-Boot relocator place U-Boot into valid memory, that is, at the
+ * end of the first DRAM bank. If we did not override this function
+ * like so, U-Boot would be placed at the address of the first DRAM
+ * bank + total DRAM size - sizeof(uboot), which in the setup where
+ * each DRAM bank contains 512MiB of DRAM would result in placing
+ * U-Boot into invalid memory area close to the end of the first
+ * DRAM bank.
+ */
+ return mx53_dram_size[0];
+}
+
+int dram_init(void)
+{
+ mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+ mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+ gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = mx53_dram_size[1];
+}
+
+u32 get_board_rev(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ int rev = readl(&fuse->gp[6]);
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+/*
+ * Set CCAT mode
+ * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
+ */
+void weim_cs0_settings(u32 mode)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ writel(0x0, &weim_regs->cs0gcr1);
+ writel(mode, &weim_regs->cs0gcr1);
+ writel(0x00001002, &weim_regs->cs0gcr2);
+
+ writel(0x04000000, &weim_regs->cs0rcr1);
+ writel(0x00000000, &weim_regs->cs0rcr2);
+
+ writel(0x04000000, &weim_regs->cs0wcr1);
+ writel(0x00000000, &weim_regs->cs0wcr2);
+}
+
+static void setup_gpio_eim(void)
+{
+ gpio_direction_input(GPIO_C3_STATUS);
+ gpio_direction_input(GPIO_C3_DONE);
+ gpio_direction_output(GPIO_C3_CONFIG, 1);
+
+ weim_cs0_settings(CCAT_MODE_RUN);
+}
+
+static void setup_gpio_sups(void)
+{
+ gpio_direction_input(GPIO_SUPS_INT);
+
+ static const int BLINK_INTERVALL = 50000;
+ int status = 1;
+ while (gpio_get_value(GPIO_SUPS_INT)) {
+ /* signal "CX SUPS power fail" */
+ gpio_set_value(GPIO_LED_PWR_R,
+ (++status / BLINK_INTERVALL) % 2);
+ }
+
+ /* signal "CX power up" */
+ gpio_set_value(GPIO_LED_PWR_R, 1);
+}
+
+static void setup_gpio_leds(void)
+{
+ gpio_direction_output(GPIO_LED_SD2_R, 0);
+ gpio_direction_output(GPIO_LED_SD2_B, 0);
+ gpio_direction_output(GPIO_LED_SD2_G, 0);
+ gpio_direction_output(GPIO_LED_SD1_R, 0);
+ gpio_direction_output(GPIO_LED_SD1_B, 0);
+ gpio_direction_output(GPIO_LED_SD1_G, 0);
+ gpio_direction_output(GPIO_LED_PWR_R, 0);
+ gpio_direction_output(GPIO_LED_PWR_B, 0);
+ gpio_direction_output(GPIO_LED_PWR_G, 0);
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+ /* request VBUS power enable pin, GPIO7_8 */
+ gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ gpio_direction_input(GPIO_SD1_CD);
+ gpio_direction_input(GPIO_SD2_CD);
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ ret = !gpio_get_value(GPIO_SD1_CD);
+ else
+ ret = !gpio_get_value(GPIO_SD2_CD);
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ u32 index;
+ int ret;
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ break;
+ case 1:
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return -EINVAL;
+ }
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+static int power_init(void)
+{
+ /* nothing to do on CX9020 */
+ return 0;
+}
+
+static void clock_1GHz(void)
+{
+ int ret;
+ u32 ref_clk = MXC_HCLK;
+ /*
+ * After increasing voltage to 1.25V, we can switch
+ * CPU clock to 1GHz and DDR to 400MHz safely
+ */
+ ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+ if (ret)
+ printf("CPU: Switch CPU clock to 1GHZ failed\n");
+
+ ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+ ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+ if (ret)
+ printf("CPU: Switch DDR clock to 400MHz failed\n");
+}
+
+int board_early_init_f(void)
+{
+ setup_gpio_leds();
+ setup_gpio_sups();
+ setup_gpio_eim();
+ setup_iomux_lcd();
+
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ mxc_set_sata_internal_clock();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Beckhoff CX9020\n");
+
+ return 0;
+}
+
+static int ccat_config_fn(int assert_config, int flush, int cookie)
+{
+ /* prepare FPGA for programming */
+ weim_cs0_settings(CCAT_MODE_CONFIG);
+ gpio_set_value(GPIO_C3_CONFIG, 0);
+ udelay(1);
+ gpio_set_value(GPIO_C3_CONFIG, 1);
+ udelay(230);
+
+ return FPGA_SUCCESS;
+}
+
+static int ccat_status_fn(int cookie)
+{
+ return FPGA_FAIL;
+}
+
+static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
+{
+ const uint8_t *const buffer = buf;
+
+ /* program CCAT */
+ int i;
+ for (i = 0; i < buf_len; ++i)
+ writeb(buffer[i], CCAT_BASE_ADDR);
+
+ writeb(0xff, CCAT_BASE_ADDR);
+ writeb(0xff, CCAT_BASE_ADDR);
+
+ return FPGA_SUCCESS;
+}
+
+static int ccat_done_fn(int cookie)
+{
+ /* programming complete? */
+ return gpio_get_value(GPIO_C3_DONE);
+}
+
+static int ccat_post_fn(int cookie)
+{
+ /* switch to FPGA run mode */
+ weim_cs0_settings(CCAT_MODE_RUN);
+ invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
+
+ if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
+ printf("Verifing CCAT firmware failed, signature not found\n");
+ return FPGA_FAIL;
+ }
+
+ /* signal "CX booting OS" */
+ gpio_set_value(GPIO_LED_PWR_R, 1);
+ gpio_set_value(GPIO_LED_PWR_G, 1);
+ gpio_set_value(GPIO_LED_PWR_B, 0);
+ return FPGA_SUCCESS;
+}
+
+static Altera_CYC2_Passive_Serial_fns ccat_fns = {
+ .config = ccat_config_fn,
+ .status = ccat_status_fn,
+ .done = ccat_done_fn,
+ .write = ccat_write_fn,
+ .abort = ccat_post_fn,
+ .post = ccat_post_fn,
+};
+
+static Altera_desc ccat_fpga = {
+ .family = Altera_CYC2,
+ .iface = passive_serial,
+ .size = CCAT_SIZE,
+ .iface_fns = &ccat_fns,
+ .base = CCAT_BASE_ADDR,
+};
+
+int board_late_init(void)
+{
+ if (!power_init())
+ clock_1GHz();
+
+ fpga_init();
+ fpga_add(fpga_altera, &ccat_fpga);
+
+ return 0;
+}
diff --git a/board/beckhoff/mx53cx9020/mx53cx9020_video.c b/board/beckhoff/mx53cx9020/mx53cx9020_video.c
new file mode 100644
index 0000000..4da83da
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/mx53cx9020_video.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Based on <u-boot>/board/freescale/mx53loco/mx53loco_video.c
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/list.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx53.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+#define CX9020_DVI_PWD IMX_GPIO_NR(6, 1)
+
+static struct fb_videomode const vga_640x480 = {
+ .name = "VESA_VGA_640x480",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 39721, /* picosecond (25.175 MHz) */
+ .left_margin = 40,
+ .right_margin = 60,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 20,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+void setup_iomux_lcd(void)
+{
+ /* Turn on DVI_PWD */
+ imx_iomux_v3_setup_pad(MX53_PAD_CSI0_DAT15__GPIO6_1);
+ gpio_direction_output(CX9020_DVI_PWD, 1);
+}
+
+int board_video_skip(void)
+{
+ const int ret = ipuv3_fb_init(&vga_640x480, 0, IPU_PIX_FMT_RGB24);
+ if (ret)
+ printf("VESA VG 640x480 cannot be configured: %d\n", ret);
+ return ret;
+}
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
index 2a36d29..08b1401 100644
--- a/board/bluewater/gurnard/gurnard.c
+++ b/board/bluewater/gurnard/gurnard.c
@@ -414,12 +414,6 @@
{
}
-/* This breaks the Ethernet MAC at present */
-void enable_caches(void)
-{
- dcache_enable();
-}
-
/* SPI chip select control - only used for FPGA programming */
#ifdef CONFIG_ATMEL_SPI
diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg
index 1cdccad..5c3e961 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg
@@ -20,6 +20,9 @@
#define __ASSEMBLY__
#include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
index 516d67e..fe19ed0 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
@@ -20,6 +20,9 @@
#define __ASSEMBLY__
#include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg
index b6642e6..60e1885 100644
--- a/board/boundary/nitrogen6x/nitrogen6q.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q.cfg
@@ -20,6 +20,9 @@
#define __ASSEMBLY__
#include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
index fe6dfc1..7a3ee94 100644
--- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
@@ -20,6 +20,9 @@
#define __ASSEMBLY__
#include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg
index ca30cd6..2540b7b 100644
--- a/board/boundary/nitrogen6x/nitrogen6s.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s.cfg
@@ -20,6 +20,9 @@
#define __ASSEMBLY__
#include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
index b1489fb..946af7b 100644
--- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
@@ -20,6 +20,9 @@
#define __ASSEMBLY__
#include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index a3a56ca..ab8b2be 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -13,7 +13,7 @@
#include <asm/arch/sys_proto.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
diff --git a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
index 0cb059f..533e99e 100644
--- a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
+++ b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
@@ -68,7 +68,7 @@
gd->bd->bi_dram[0].size = gd->ram_size;
}
-#ifdef CONFIG_KONA_SDHCI
+#ifdef CONFIG_MMC_SDHCI_KONA
/*
* mmc_init - Initializes mmc
*/
diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c
index b3a4a41..b868812 100644
--- a/board/broadcom/bcm28155_ap/bcm28155_ap.c
+++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
@@ -75,7 +75,7 @@
gd->bd->bi_dram[0].size = gd->ram_size;
}
-#ifdef CONFIG_KONA_SDHCI
+#ifdef CONFIG_MMC_SDHCI_KONA
/*
* mmc_init - Initializes mmc
*/
diff --git a/board/ccv/xpress/imximage.cfg b/board/ccv/xpress/imximage.cfg
index 92167c9..d98bc36 100644
--- a/board/ccv/xpress/imximage.cfg
+++ b/board/ccv/xpress/imximage.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/compulab/cl-som-am57x/Kconfig b/board/compulab/cl-som-am57x/Kconfig
new file mode 100644
index 0000000..85fc9a1
--- /dev/null
+++ b/board/compulab/cl-som-am57x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CL_SOM_AM57X
+
+config SYS_BOARD
+ default "cl-som-am57x"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_CONFIG_NAME
+ default "cl-som-am57x"
+
+endif
diff --git a/board/compulab/cl-som-am57x/MAINTAINERS b/board/compulab/cl-som-am57x/MAINTAINERS
new file mode 100644
index 0000000..e0195f4
--- /dev/null
+++ b/board/compulab/cl-som-am57x/MAINTAINERS
@@ -0,0 +1,6 @@
+CL-SOM-AM57x BOARD
+M: Uri Mashiach <uri.mashiach@compulab.co.il>
+S: Maintained
+F: board/compulab/cl-som-am57x/
+F: include/configs/cl-som-am57x.h
+F: configs/cl-som-am57x_defconfig
diff --git a/board/compulab/cl-som-am57x/Makefile b/board/compulab/cl-som-am57x/Makefile
new file mode 100644
index 0000000..566366b
--- /dev/null
+++ b/board/compulab/cl-som-am57x/Makefile
@@ -0,0 +1,17 @@
+#
+# Makefile
+#
+# (C) Copyright 2016 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o mux.o
+else
+obj-y += cl-som-am57x.o mux.o
+endif
+
+obj-$(CONFIG_DRIVER_TI_CPSW) += eth.o
diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c b/board/compulab/cl-som-am57x/cl-som-am57x.c
new file mode 100644
index 0000000..bdd0a2b
--- /dev/null
+++ b/board/compulab/cl-som-am57x/cl-som-am57x.c
@@ -0,0 +1,76 @@
+/*
+ * Board functions for CompuLab cl_som_am57x board
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <palmas.h>
+#include <usb.h>
+#include <asm/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include "../common/common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: CL-SOM-AM57x\n"
+};
+
+int board_init(void)
+{
+ /* Disable PMIC Powerhold feature, DEV_CTRL.DEV_ON = 1 */
+ palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+#define SB_SOM_CD_GPIO 187
+#define SB_SOM_WP_GPIO 188
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret0, ret1;
+
+ ret0 = omap_mmc_init(0, 0, 0, SB_SOM_CD_GPIO, SB_SOM_WP_GPIO);
+ if (ret0)
+ printf("cl-som-am57x: failed to initialize mmc0\n");
+
+ ret1 = omap_mmc_init(1, 0, 0, -1, -1);
+ if (ret1)
+ printf("cl-som-am57x: failed to initialize mmc1\n");
+
+ return ret0 && ret1;
+}
+#endif /* CONFIG_GENERIC_MMC */
+
+#ifdef CONFIG_USB_XHCI_OMAP
+int board_usb_init(int index, enum usb_init_type init)
+{
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+ OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
+
+ return 0;
+}
+#endif /* CONFIG_USB_XHCI_OMAP */
+
+int misc_init_r(void)
+{
+ cl_print_pcb_info();
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
+}
diff --git a/board/compulab/cl-som-am57x/eth.c b/board/compulab/cl-som-am57x/eth.c
new file mode 100644
index 0000000..0c4bf91
--- /dev/null
+++ b/board/compulab/cl-som-am57x/eth.c
@@ -0,0 +1,198 @@
+/*
+ * Ethernet specific code for CompuLab CL-SOM-AM57x module
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpsw.h>
+#include <miiphy.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include "../common/eeprom.h"
+
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+}
+
+static struct cpsw_slave_data cl_som_am57x_cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+
+ },
+};
+
+static struct cpsw_platform_data cl_som_am57_cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 2,
+ .slave_data = cl_som_am57x_cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+/*
+ * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address.
+ * The information is retrieved from the SOC's registers.
+ * @buff: read buffer.
+ * @port_num: port number.
+ */
+static void cl_som_am57x_efuse_read_mac_addr(uchar *buff, uint port_num)
+{
+ uint32_t mac_hi, mac_lo;
+
+ if (port_num) {
+ mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+ } else {
+ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+ }
+
+ buff[0] = (mac_hi & 0xFF0000) >> 16;
+ buff[1] = (mac_hi & 0xFF00) >> 8;
+ buff[2] = mac_hi & 0xFF;
+ buff[3] = (mac_lo & 0xFF0000) >> 16;
+ buff[4] = (mac_lo & 0xFF00) >> 8;
+ buff[5] = mac_lo & 0xFF;
+}
+
+/*
+ * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot
+ * environment.
+ * The address is retrieved retrieved from an EEPROM field or from the
+ * SOC's registers.
+ * @env_name: U-Boot environment name.
+ * @field_name: EEPROM field name.
+ * @port_num: SOC's port number.
+ */
+static int cl_som_am57x_handle_mac_address(char *env_name, uint port_num)
+{
+ int ret;
+ uint8_t enetaddr[6];
+
+ ret = eth_getenv_enetaddr(env_name, enetaddr);
+ if (ret)
+ return 0;
+
+ ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
+
+ if (ret || !is_valid_ethaddr(enetaddr))
+ cl_som_am57x_efuse_read_mac_addr(enetaddr, port_num);
+
+ if (!is_valid_ethaddr(enetaddr))
+ return -1;
+
+ ret = eth_setenv_enetaddr(env_name, enetaddr);
+ if (ret)
+ printf("cl-som-am57x: Failed to set Eth port %d MAC address\n",
+ port_num);
+
+ return ret;
+}
+
+#define CL_SOM_AM57X_PHY_ADDR2 0x01
+#define AR8033_PHY_DEBUG_ADDR_REG 0x1d
+#define AR8033_PHY_DEBUG_DATA_REG 0x1e
+#define AR8033_DEBUG_RGMII_RX_CLK_DLY_REG 0x00
+#define AR8033_DEBUG_RGMII_TX_CLK_DLY_REG 0x05
+#define AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK (1 << 15)
+#define AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK (1 << 8)
+
+/*
+ * cl_som_am57x_rgmii_clk_delay() - Set RGMII clock delay.
+ * Enable RX delay, disable TX delay.
+ */
+static void cl_som_am57x_rgmii_clk_delay(void)
+{
+ uint16_t mii_reg_val;
+ const char *devname;
+
+ devname = miiphy_get_current_dev();
+ /* PHY 2 */
+ miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG,
+ AR8033_DEBUG_RGMII_RX_CLK_DLY_REG);
+ miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
+ &mii_reg_val);
+ mii_reg_val |= AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK;
+ miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
+ mii_reg_val);
+
+ miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG,
+ AR8033_DEBUG_RGMII_TX_CLK_DLY_REG);
+ miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
+ &mii_reg_val);
+ mii_reg_val &= ~AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK;
+ miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
+ mii_reg_val);
+}
+
+#define CL_SOM_AM57X_GPIO_PHY1_RST 92 /* GPIO3_28 */
+#define CL_SOM_AM57X_RGMII_PORT1 1
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ uint32_t ctrl_val;
+ char *cpsw_phy_envval;
+ int cpsw_act_phy = 1;
+
+ /* SB-SOM-AM57x primary Eth (P21) is routed to RGMII1 */
+ ret = cl_som_am57x_handle_mac_address("ethaddr",
+ CL_SOM_AM57X_RGMII_PORT1);
+
+ if (ret)
+ return -1;
+
+ /* Select RGMII for GMII1_SEL */
+ ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+ ctrl_val |= 0x22;
+ writel(ctrl_val, (*ctrl)->control_core_control_io1);
+ mdelay(10);
+
+ gpio_request(CL_SOM_AM57X_GPIO_PHY1_RST, "phy1_rst");
+ gpio_direction_output(CL_SOM_AM57X_GPIO_PHY1_RST, 0);
+ mdelay(20);
+
+ gpio_set_value(CL_SOM_AM57X_GPIO_PHY1_RST, 1);
+ mdelay(20);
+
+ cpsw_phy_envval = getenv("cpsw_phy");
+ if (cpsw_phy_envval != NULL)
+ cpsw_act_phy = simple_strtoul(cpsw_phy_envval, NULL, 0);
+
+ cl_som_am57_cpsw_data.active_slave = cpsw_act_phy;
+
+ ret = cpsw_register(&cl_som_am57_cpsw_data);
+ if (ret < 0)
+ printf("Error %d registering CPSW switch\n", ret);
+
+ /* Set RGMII clock delay */
+ cl_som_am57x_rgmii_clk_delay();
+
+ return ret;
+}
diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c
new file mode 100644
index 0000000..5b71975
--- /dev/null
+++ b/board/compulab/cl-som-am57x/mux.c
@@ -0,0 +1,123 @@
+/*
+ * Pinmux configuration for CompuLab CL-SOM-AM57x board
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux_dra7xx.h>
+
+/* Serial console */
+static const struct pad_conf_entry cl_som_am57x_padconf_console[] = {
+ {UART3_RXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_RXD */
+ {UART3_TXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_TXD */
+};
+
+/* PMIC I2C */
+static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = {
+ {MCASP1_ACLKR, (IEN | PEN | M10)}, /* MCASP1_ACLKR.I2C4_SDA */
+ {MCASP1_FSR, (IEN | PEN | M10)}, /* MCASP1_FSR.I2C4_SCL */
+};
+
+/* Green GPIO led */
+static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = {
+ {GPMC_A15, (IDIS | PDIS | PTD | M14)}, /* GPMC_A15.GPIO2_5 */
+};
+
+/* MMC/SD Card */
+static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = {
+ {MMC1_CLK, (IEN | PDIS | PTU | M0) }, /* MMC1_CLK */
+ {MMC1_CMD, (IEN | PDIS | PTU | M0) }, /* MMC1_CMD */
+ {MMC1_DAT0, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT0 */
+ {MMC1_DAT1, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT1 */
+ {MMC1_DAT2, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT2 */
+ {MMC1_DAT3, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT3 */
+ {MMC1_SDCD, (IEN | PEN | M14)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (IEN | PEN | M14)}, /* MMC1_SDWP */
+};
+
+/* WiFi - must be in the safe mode on boot */
+static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = {
+ {UART1_CTSN, (IEN | M15)}, /* UART1_CTSN */
+ {UART1_RTSN, (IEN | M15)}, /* UART1_RTSN */
+ {UART2_RXD, (IEN | M15)}, /* UART2_RXD */
+ {UART2_TXD, (IEN | M15)}, /* UART2_TXD */
+ {UART2_CTSN, (IEN | M15)}, /* UART2_CTSN */
+ {UART2_RTSN, (IEN | M15)}, /* UART2_RTSN */
+};
+
+/* QSPI */
+static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = {
+ {GPMC_A13, (IEN | PEN | M1)}, /* GPMC_A13.QSPI1_RTCLK */
+ {GPMC_A18, (IEN | PEN | M1)}, /* GPMC_A18.QSPI1_SCLK */
+ {GPMC_A16, (IEN | PEN | M1)}, /* GPMC_A16.QSPI1_D0 */
+ {GPMC_A17, (IEN | PEN | M1)}, /* GPMC_A17.QSPI1_D1 */
+ {GPMC_CS2, (IEN | PDIS | PTU | M1)}, /* GPMC_CS2.QSPI1_CS0 */
+};
+
+/* GPIO Expander I2C */
+static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = {
+ {MCASP1_AXR0, (IEN | PEN | M10)}, /* MCASP1_AXR0.I2C5_SDA */
+ {MCASP1_AXR1, (IEN | PEN | M10)}, /* MCASP1_AXR1.I2C5_SCL */
+};
+
+/* eMMC internal storage */
+static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = {
+ {GPMC_A19, (IEN | PDIS | PTU | M1)}, /* GPMC_A19.MMC2_DAT4 */
+ {GPMC_A20, (IEN | PDIS | PTU | M1)}, /* GPMC_A20.MMC2_DAT5 */
+ {GPMC_A21, (IEN | PDIS | PTU | M1)}, /* GPMC_A21.MMC2_DAT6 */
+ {GPMC_A22, (IEN | PDIS | PTU | M1)}, /* GPMC_A22.MMC2_DAT7 */
+ {GPMC_A23, (IEN | PDIS | PTU | M1)}, /* GPMC_A23.MMC2_CLK */
+ {GPMC_A24, (IEN | PDIS | PTU | M1)}, /* GPMC_A24.MMC2_DAT0 */
+ {GPMC_A25, (IEN | PDIS | PTU | M1)}, /* GPMC_A25.MMC2_DAT1 */
+ {GPMC_A26, (IEN | PDIS | PTU | M1)}, /* GPMC_A26.MMC2_DAT2 */
+ {GPMC_A27, (IEN | PDIS | PTU | M1)}, /* GPMC_A27.MMC2_DAT3 */
+ {GPMC_CS1, (IEN | PDIS | PTU | M1)}, /* GPMC_CS1.MMC2_CMD */
+};
+
+/* usb1_drvvbus */
+static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = {
+ {USB1_DRVVBUS, (M0 | FSC) }, /* USB1_DRVVBUS.USB1_DRVVBUS */
+};
+
+/* Ethernet */
+static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = {
+ /* MDIO bus */
+ {VIN2A_D10, (PDIS | PTU | M3) }, /* VIN2A_D10.MDIO_MCLK */
+ {VIN2A_D11, (IEN | PDIS | PTU | M3) }, /* VIN2A_D11.MDIO_D */
+ /* EMAC Slave 1 at addr 0x1 - Default interface */
+ {VIN2A_D12, (IDIS | PEN | M3) }, /* VIN2A_D12.RGMII1_TXC */
+ {VIN2A_D13, (IDIS | PEN | M3) }, /* VIN2A_D13.RGMII1_TXCTL */
+ {VIN2A_D14, (IDIS | PEN | M3) }, /* VIN2A_D14.RGMII1_TXD3 */
+ {VIN2A_D15, (IDIS | PEN | M3) }, /* VIN2A_D15.RGMII1_TXD2 */
+ {VIN2A_D16, (IDIS | PEN | M3) }, /* VIN2A_D16.RGMII1_TXD1 */
+ {VIN2A_D17, (IDIS | PEN | M3) }, /* VIN2A_D17.RGMII1_TXD0 */
+ {VIN2A_D18, (IEN | PDIS | PTD | M3) }, /* VIN2A_D18.RGMII1_RXC */
+ {VIN2A_D19, (IEN | PDIS | PTD | M3) }, /* VIN2A_D19.RGMII1_RXCTL */
+ {VIN2A_D20, (IEN | PDIS | PTD | M3) }, /* VIN2A_D20.RGMII1_RXD3 */
+ {VIN2A_D21, (IEN | PDIS | PTD | M3) }, /* VIN2A_D21.RGMII1_RXD2 */
+ {VIN2A_D22, (IEN | PDIS | PTD | M3) }, /* VIN2A_D22.RGMII1_RXD1 */
+ {VIN2A_D23, (IEN | PDIS | PTD | M3) }, /* VIN2A_D23.RGMII1_RXD0 */
+ /* Eth PHY1 reset GPIOs*/
+ {VIN1B_CLK1, (IDIS | PDIS | PTD | M14)}, /* VIN1B_CLK1.GPIO2_31 */
+};
+
+#define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \
+ mux_array, ARRAY_SIZE(mux_array))
+
+void set_muxconf_regs(void)
+{
+ SET_MUX(cl_som_am57x_padconf_console);
+ SET_MUX(cl_som_am57x_padconf_pmic);
+ SET_MUX(cl_som_am57x_padconf_green_led);
+ SET_MUX(cl_som_am57x_padconf_sd_card);
+ SET_MUX(cl_som_am57x_padconf_wifi);
+ SET_MUX(cl_som_am57x_padconf_qspi);
+ SET_MUX(cl_som_am57x_padconf_i2c_gpio);
+ SET_MUX(cl_som_am57x_padconf_emmc);
+ SET_MUX(cl_som_am57x_padconf_usb);
+ SET_MUX(cl_som_am57x_padconf_ethernet);
+}
diff --git a/board/compulab/cl-som-am57x/spl.c b/board/compulab/cl-som-am57x/spl.c
new file mode 100644
index 0000000..855678f
--- /dev/null
+++ b/board/compulab/cl-som-am57x/spl.c
@@ -0,0 +1,234 @@
+/*
+ * SPL data and initialization for CompuLab CL-SOM-AM57x board
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/emif.h>
+#include <asm/omap_common.h>
+#include <asm/arch/sys_proto.h>
+
+static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = {
+ .dmm_lisa_map_3 = 0x80740300,
+ .is_ma_present = 0x1
+};
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+ *dmm_lisa_regs = &cl_som_am57x_lisa_regs;
+}
+
+static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61852332,
+ .sdram_config = 0x61852332,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x000040f1,
+ .ref_ctrl_final = 0x00001040,
+ .sdram_tim1 = 0xeeef36f3,
+ .sdram_tim2 = 0x348f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x1007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0034400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e34400b,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
+ .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+/* Ext phy ctrl regs 1-35 */
+static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = {
+ 0x10040100,
+ 0x00740074,
+ 0x00780078,
+ 0x007c007c,
+ 0x007b007b,
+ 0x00800080,
+ 0x00360036,
+ 0x00340034,
+ 0x00360036,
+ 0x00350035,
+ 0x00350035,
+
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+
+ 0x00430043,
+ 0x003e003e,
+ 0x004a004a,
+ 0x00470047,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40011080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
+};
+
+static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61852332,
+ .sdram_config = 0x61852332,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x000040f1,
+ .ref_ctrl_final = 0x00001040,
+ .sdram_tim1 = 0xeeef36f3,
+ .sdram_tim2 = 0x348f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x1007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0034400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e34400b,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
+ .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = {
+ 0x10040100,
+ 0x00820082,
+ 0x008b008b,
+ 0x00800080,
+ 0x007e007e,
+ 0x00800080,
+ 0x00370037,
+ 0x00390039,
+ 0x00360036,
+ 0x00370037,
+ 0x00350035,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x00540054,
+ 0x00540054,
+ 0x004e004e,
+ 0x004c004c,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40011080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
+};
+
+static struct vcores_data cl_som_am57x_volts = {
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6,
+ .gpu.pmic = &tps659038,
+
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS7,
+ .core.pmic = &tps659038,
+
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8,
+ .iva.pmic = &tps659038,
+};
+
+void hw_data_init(void)
+{
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra7xx_dplls;
+ *omap_vcores = &cl_som_am57x_volts;
+ *ctrl = &dra7xx_ctrl;
+}
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs;
+ break;
+ case 2:
+ *regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs;
+ break;
+ }
+}
+
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs;
+ *size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs);
+ break;
+ case 2:
+ *regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs;
+ *size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs);
+ break;
+ }
+}
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 28e9a8f..5b88bcc 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -602,7 +602,7 @@
char baseboard_name[16];
int err;
- fdt_shrink_to_minimum(blob); /* Make room for new properties */
+ fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
/* MAC addr */
if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 189d903..484651b 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -24,7 +24,7 @@
#include <linux/compiler.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/mmc_host_def.h>
diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h
index 8f38b79..759ec31 100644
--- a/board/compulab/common/common.h
+++ b/board/compulab/common/common.h
@@ -9,7 +9,7 @@
#ifndef _CL_COMMON_
#define _CL_COMMON_
-#include <asm/errno.h>
+#include <linux/errno.h>
void cl_print_pcb_info(void);
diff --git a/board/compulab/common/omap3_smc911x.c b/board/compulab/common/omap3_smc911x.c
index 4561661..858ced8 100644
--- a/board/compulab/common/omap3_smc911x.c
+++ b/board/compulab/common/omap3_smc911x.c
@@ -10,7 +10,7 @@
#include <netdev.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/congatec/conga-qeval20-qa3-e3845/README b/board/congatec/conga-qeval20-qa3-e3845/README
new file mode 100644
index 0000000..98ff992
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/README
@@ -0,0 +1,23 @@
+------------------------------
+U-Boot console UART selection:
+------------------------------
+
+The U-Boot port for this congatec board currently supports two different
+configurations (defconfig files). The only difference is the UART that
+is used as the U-Boot console UART. The default defconfig file:
+
+conga-qeval20-qa3-e3845_defconfig
+
+provides this console on the UART0 which is provided via a Winbond
+Super-IO chip connected on the congatec Qseven 2.0 evaluation carrier
+board (conga-QEVAL). This UART is the one provided with a SubD9
+connector on the mainboard (the low one). The 2nd defconfig file:
+
+conga-qeval20-qa3-e3845-internal-uart_defconfig
+
+provides the U-Boot console on the BayTrail internal legacy UART,
+which is routed from the QSeven SoM to the X300 connector on the
+baseboard. Here is called COM2. The baseboard already provides the
+RS232 level shifters. So a TTL-USB UART adapter does not work in
+this case. The signals need to get connected directly to the
+RS232 level signals of the PC UART via some adapter cable.
diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c
index 340a009..aeacd6a 100644
--- a/board/corscience/tricorder/tricorder-eeprom.c
+++ b/board/corscience/tricorder/tricorder-eeprom.c
@@ -190,13 +190,8 @@
if (argc == 3) {
ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
- if (strcmp(argv[1], "read") == 0) {
- int rcode;
-
- rcode = tricorder_eeprom_read(dev_addr);
-
- return rcode;
- }
+ if (strcmp(argv[1], "read") == 0)
+ return tricorder_eeprom_read(dev_addr);
} else if (argc == 6 || argc == 7) {
ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
char *name = argv[3];
@@ -207,14 +202,9 @@
if (argc == 7)
interface = argv[6];
- if (strcmp(argv[1], "write") == 0) {
- int rcode;
-
- rcode = tricorder_eeprom_write(dev_addr, name, version,
- serial, interface);
-
- return rcode;
- }
+ if (strcmp(argv[1], "write") == 0)
+ return tricorder_eeprom_write(dev_addr, name, version,
+ serial, interface);
}
return CMD_RET_USAGE;
diff --git a/board/davinci/da8xxevm/README.omapl138-lcdk b/board/davinci/da8xxevm/README.omapl138-lcdk
deleted file mode 100644
index ea0c53d..0000000
--- a/board/davinci/da8xxevm/README.omapl138-lcdk
+++ /dev/null
@@ -1,28 +0,0 @@
-Summary
-=======
-This README assumes you have read README.da850. It contains some additional
-information specific to building the omapl138-lcdk. The AIS file as generated
-by the build is, currently, not useable due to differences in the flash
-available on this board, as compared to the da850evm boards.
-
-Flash Differences
-=================
-Refer to the discussion in [1] for more detail - basically the da850evm uses
-SPI flash whereas the lcdk uses NAND flash to store the bootloader, and
-the support isn't there in the SPL code.
-
-It should be possible to add the support in the SPL code should someone be
-sufficiently motivated.
-
-Using the built image
-=====================
-The output image to use is u-boot.bin. This needs to be converted to an
-AIS file as described in [1] and then flashed using the utitilty linked to
-there and also described in README.da850. You _may_ be able to write using
-u-boot itself, but the commands in README.da850 won't work as they write to
-SPI rather than NAND.
-
-Links
-=====
-[1]
- http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/386829
\ No newline at end of file
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index b82385a..52f914d 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -21,7 +21,7 @@
#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <hwconfig.h>
#ifdef CONFIG_DAVINCI_MMC
@@ -164,7 +164,7 @@
memcmp(env_enetaddr, buff, 6))
printf("Warning: MAC address in SPI flash don't match "
"with the MAC address in the environment\n");
- printf("Default using MAC address from environment\n");
+ printf("Default using MAC address from environment\n");
}
#endif
uint8_t enetaddr[8];
@@ -190,7 +190,7 @@
if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
printf("Warning: MAC address in EEPROM don't match "
"with the MAC address in the environment\n");
- printf("Default using MAC address from environment\n");
+ printf("Default using MAC address from environment\n");
}
#endif
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index f69aeb6..9c1a483 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -18,7 +18,7 @@
#include <asm/arch/hardware.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/davinci_misc.h>
#ifdef CONFIG_DAVINCI_MMC
#include <mmc.h>
@@ -333,15 +333,17 @@
get_mac_addr(addr);
}
- if (is_multicast_ethaddr(addr) || is_zero_ethaddr(addr)) {
- printf("Invalid MAC address read.\n");
- return -EINVAL;
- }
- sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", addr[0],
- addr[1], addr[2], addr[3], addr[4], addr[5]);
+ if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
+ sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
+ addr[0], addr[1], addr[2], addr[3], addr[4],
+ addr[5]);
- setenv("ethaddr", (char *)tmp);
+ setenv("ethaddr", (char *)tmp);
+ } else {
+ printf("Invalid MAC address read.\n");
+ }
}
+
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
/* Select RMII fucntion through the expander */
if (rmii_hw_init())
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index ab4f50c..85a6be9 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -34,6 +34,9 @@
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram
+
+ . = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg
index 4cd002c..c0e2602 100644
--- a/board/denx/m53evk/imximage.cfg
+++ b/board/denx/m53evk/imximage.cfg
@@ -4,7 +4,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c
index 934f009..ef63bbd 100644
--- a/board/denx/m53evk/m53evk.c
+++ b/board/denx/m53evk/m53evk.c
@@ -15,7 +15,7 @@
#include <asm/arch/iomux-mx53.h>
#include <asm/imx-common/mx5_video.h>
#include <asm/spl.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h
index 30c4d7d..ff64f55 100644
--- a/board/denx/mcvevk/qts/sdram_config.h
+++ b/board/denx/mcvevk/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h
index cf9d1d3..b4872c2 100644
--- a/board/ebv/socrates/qts/sdram_config.h
+++ b/board/ebv/socrates/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c
index 7856b84..5b60654 100644
--- a/board/el/el6x/el6x.c
+++ b/board/el/el6x/el6x.c
@@ -10,7 +10,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
index ad7a8cf..95cdaeb 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -18,7 +18,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
diff --git a/board/engicam/geam6ul/Kconfig b/board/engicam/geam6ul/Kconfig
new file mode 100644
index 0000000..8753d15
--- /dev/null
+++ b/board/engicam/geam6ul/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6UL_GEAM
+
+config SYS_BOARD
+ default "geam6ul"
+
+config SYS_VENDOR
+ default "engicam"
+
+config SYS_CONFIG_NAME
+ default "imx6ul_geam"
+
+endif
diff --git a/board/engicam/geam6ul/MAINTAINERS b/board/engicam/geam6ul/MAINTAINERS
new file mode 100644
index 0000000..079370c
--- /dev/null
+++ b/board/engicam/geam6ul/MAINTAINERS
@@ -0,0 +1,7 @@
+GEAM6UL BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: board/engicam/geam6ul
+F: include/configs/imx6ul_geam.h
+F: configs/imx6ul_geam_mmc_defconfig
+F: configs/imx6ul_geam_nand_defconfig
diff --git a/board/engicam/geam6ul/Makefile b/board/engicam/geam6ul/Makefile
new file mode 100644
index 0000000..0e367e2
--- /dev/null
+++ b/board/engicam/geam6ul/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := geam6ul.o
diff --git a/board/engicam/geam6ul/README b/board/engicam/geam6ul/README
new file mode 100644
index 0000000..0df6ae4
--- /dev/null
+++ b/board/engicam/geam6ul/README
@@ -0,0 +1,28 @@
+How to use U-Boot on Engicam GEAM6UL Starter Kit:
+-------------------------------------------------
+
+- Configure U-Boot for Engicam GEAM6UL:
+
+$ make mrproper
+$ make imx6ul_geam_mmc_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c
new file mode 100644
index 0000000..40f20a9
--- /dev/null
+++ b/board/engicam/geam6ul/geam6ul.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+
+ return 0;
+}
+
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+static iomux_v3_cfg_t const nand_pads[] = {
+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+
+ clrbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+ /*
+ * config gpmi and bch clock to 100 MHz
+ * bch/gpmi select PLL2 PFD2 400M
+ * 100M = 400M / 4
+ */
+ clrbits_le32(&mxc_ccm->cscmr1,
+ MXC_CCM_CSCMR1_BCH_CLK_SEL |
+ MXC_CCM_CSCMR1_GPMI_CLK_SEL);
+ clrsetbits_le32(&mxc_ccm->cscdr1,
+ MXC_CCM_CSCDR1_BCH_PODF_MASK |
+ MXC_CCM_CSCDR1_GPMI_PODF_MASK,
+ (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+ (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif /* CONFIG_NAND_MXS */
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* VSELECT */
+ MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* CD */
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* RST_B */
+ MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ default:
+ printf("Warning - USDHC%d controller not supporting\n",
+ i + 1);
+ return 0;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000008,
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00070007,
+ .p0_mpdgctrl0 = 0x41490145,
+ .p0_mprddlctl = 0x40404546,
+ .p0_mpwrdlctl = 0x4040524D,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 13,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/engicam/icorem6/Kconfig b/board/engicam/icorem6/Kconfig
new file mode 100644
index 0000000..6d62f0e
--- /dev/null
+++ b/board/engicam/icorem6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6Q_ICORE
+
+config SYS_BOARD
+ default "icorem6"
+
+config SYS_VENDOR
+ default "engicam"
+
+config SYS_CONFIG_NAME
+ default "imx6qdl_icore"
+
+endif
diff --git a/board/engicam/icorem6/MAINTAINERS b/board/engicam/icorem6/MAINTAINERS
new file mode 100644
index 0000000..0ef3a2c
--- /dev/null
+++ b/board/engicam/icorem6/MAINTAINERS
@@ -0,0 +1,9 @@
+ICOREM6QDL BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: board/engicam/icorem6
+F: include/configs/imx6qdl_icore.h
+F: configs/imx6q_icore_mmc_defconfig
+F: configs/imx6q_icore_nand_defconfig
+F: configs/imx6dl_icore_mmc_defconfig
+F: configs/imx6dl_icore_nand_defconfig
diff --git a/board/engicam/icorem6/Makefile b/board/engicam/icorem6/Makefile
new file mode 100644
index 0000000..9ec9ecd
--- /dev/null
+++ b/board/engicam/icorem6/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := icorem6.o
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
new file mode 100644
index 0000000..6461c0a
--- /dev/null
+++ b/board/engicam/icorem6/README
@@ -0,0 +1,33 @@
+How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit:
+-----------------------------------------------------------------------------
+
+$ make mrproper
+
+- Configure U-Boot for Engicam i.CoreM6 Quad/Dual:
+$ make imx6q_icore_mmc_defconfig
+
+- Configure U-Boot for Engicam i.CoreM6 Solo/DualLite:
+$ make imx6dl_icore_mmc_defconfig
+
+- Build U-Boot
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
new file mode 100644
index 0000000..171ec45
--- /dev/null
+++ b/board/engicam/icorem6/icorem6.c
@@ -0,0 +1,579 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+iomux_v3_cfg_t gpmi_pads[] = {
+ IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+ IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ SETUP_IOMUX_PADS(gpmi_pads);
+
+ /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable ENFC_CLK_ROOT clock */
+ setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const rgb_pads[] = {
+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+ IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
+ IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+ IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+ IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+ IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+ IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+ IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+ IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+ IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+ IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+ IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+ IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+ IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+ IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+ IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+ IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+ IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+ IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+ IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ SETUP_IOMUX_PADS(rgb_pads);
+}
+
+struct display_info_t const displays[] = {
+ {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "Amp-WD",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 30000,
+ .left_margin = 30,
+ .right_margin = 30,
+ .upper_margin = 5,
+ .lower_margin = 5,
+ .hsync_len = 64,
+ .vsync_len = 20,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+ },
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+ IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_early_init_f(void)
+{
+ SETUP_IOMUX_PADS(uart4_pads);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc1_pads);
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ default:
+ printf("Warning - USDHC%d controller not supporting\n",
+ i + 1);
+ return 0;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+/*
+ * Driving strength:
+ * 0x30 == 40 Ohm
+ * 0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH 0x30
+#define IMX6SDL_DRIVE_STRENGTH 0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ .dram_sdqs0 = 0x28,
+ .dram_sdqs1 = 0x28,
+ .dram_sdqs2 = 0x28,
+ .dram_sdqs3 = 0x28,
+ .dram_sdqs4 = 0x28,
+ .dram_sdqs5 = 0x28,
+ .dram_sdqs6 = 0x28,
+ .dram_sdqs7 = 0x28,
+ .dram_dqm0 = 0x28,
+ .dram_dqm1 = 0x28,
+ .dram_dqm2 = 0x28,
+ .dram_dqm3 = 0x28,
+ .dram_dqm4 = 0x28,
+ .dram_dqm5 = 0x28,
+ .dram_dqm6 = 0x28,
+ .dram_dqm7 = 0x28,
+ .dram_cas = 0x30,
+ .dram_ras = 0x30,
+ .dram_sdclk_0 = 0x30,
+ .dram_sdclk_1 = 0x30,
+ .dram_reset = 0x30,
+ .dram_sdcke0 = 0x3000,
+ .dram_sdcke1 = 0x3000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x30,
+ .dram_sdodt1 = 0x30,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ .grp_b0ds = 0x30,
+ .grp_b1ds = 0x30,
+ .grp_b2ds = 0x30,
+ .grp_b3ds = 0x30,
+ .grp_b4ds = 0x30,
+ .grp_b5ds = 0x30,
+ .grp_b6ds = 0x30,
+ .grp_b7ds = 0x30,
+ .grp_addds = 0x30,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ctlds = 0x30,
+ .grp_ddr_type = 0x000c0000,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = 0x30,
+ .dram_sdclk_1 = 0x30,
+ .dram_cas = 0x30,
+ .dram_ras = 0x30,
+ .dram_reset = 0x30,
+ .dram_sdcke0 = 0x30,
+ .dram_sdcke1 = 0x30,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x30,
+ .dram_sdodt1 = 0x30,
+ .dram_sdqs0 = 0x28,
+ .dram_sdqs1 = 0x28,
+ .dram_sdqs2 = 0x28,
+ .dram_sdqs3 = 0x28,
+ .dram_sdqs4 = 0x28,
+ .dram_sdqs5 = 0x28,
+ .dram_sdqs6 = 0x28,
+ .dram_sdqs7 = 0x28,
+ .dram_dqm0 = 0x28,
+ .dram_dqm1 = 0x28,
+ .dram_dqm2 = 0x28,
+ .dram_dqm3 = 0x28,
+ .dram_dqm4 = 0x28,
+ .dram_dqm5 = 0x28,
+ .dram_dqm6 = 0x28,
+ .dram_dqm7 = 0x28,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x30,
+ .grp_ctlds = 0x30,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x28,
+ .grp_b1ds = 0x28,
+ .grp_b2ds = 0x28,
+ .grp_b3ds = 0x28,
+ .grp_b4ds = 0x28,
+ .grp_b5ds = 0x28,
+ .grp_b6ds = 0x28,
+ .grp_b7ds = 0x28,
+};
+
+/* mt41j256 */
+static struct mx6_ddr3_cfg mt41j256 = {
+ .mem_speed = 1066,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 13,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+ .SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x000E0009,
+ .p0_mpwldectrl1 = 0x0018000E,
+ .p1_mpwldectrl0 = 0x00000007,
+ .p1_mpwldectrl1 = 0x00000000,
+ .p0_mpdgctrl0 = 0x43280334,
+ .p0_mpdgctrl1 = 0x031C0314,
+ .p1_mpdgctrl0 = 0x4318031C,
+ .p1_mpdgctrl1 = 0x030C0258,
+ .p0_mprddlctl = 0x3E343A40,
+ .p1_mprddlctl = 0x383C3844,
+ .p0_mpwrdlctl = 0x40404440,
+ .p1_mpwrdlctl = 0x4C3E4446,
+};
+
+/* DDR 64bit */
+static struct mx6_ddr_sysinfo mem_q = {
+ .ddr_type = DDR_TYPE_DDR3,
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 2,
+ .rtt_wr = 2,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001F0024,
+ .p0_mpwldectrl1 = 0x00110018,
+ .p1_mpwldectrl0 = 0x001F0024,
+ .p1_mpwldectrl1 = 0x00110018,
+ .p0_mpdgctrl0 = 0x4230022C,
+ .p0_mpdgctrl1 = 0x02180220,
+ .p1_mpdgctrl0 = 0x42440248,
+ .p1_mpdgctrl1 = 0x02300238,
+ .p0_mprddlctl = 0x44444A48,
+ .p1_mprddlctl = 0x46484A42,
+ .p0_mpwrdlctl = 0x38383234,
+ .p1_mpwrdlctl = 0x3C34362E,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 1,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+ .dsize = 1,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 1,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00003F3F, &ccm->CCGR0);
+ writel(0x0030FC00, &ccm->CCGR1);
+ writel(0x000FC000, &ccm->CCGR2);
+ writel(0x3F300000, &ccm->CCGR3);
+ writel(0xFF00F300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003CC, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_mx6solo()) {
+ mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
+ } else if (is_mx6dl()) {
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
+ } else if (is_mx6dq()) {
+ mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+ mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
+ }
+
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
diff --git a/board/engicam/icorem6_rqs/Kconfig b/board/engicam/icorem6_rqs/Kconfig
new file mode 100644
index 0000000..1352c68
--- /dev/null
+++ b/board/engicam/icorem6_rqs/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6Q_ICORE_RQS
+
+config SYS_BOARD
+ default "icorem6_rqs"
+
+config SYS_VENDOR
+ default "engicam"
+
+config SYS_CONFIG_NAME
+ default "imx6qdl_icore_rqs"
+
+endif
diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS
new file mode 100644
index 0000000..0556211
--- /dev/null
+++ b/board/engicam/icorem6_rqs/MAINTAINERS
@@ -0,0 +1,7 @@
+ICOREM6QDL_RQS BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: board/engicam/icorem6_rqs
+F: include/configs/imx6qdl_icore_rqs.h
+F: configs/imx6q_icore_rqs_mmc_defconfig
+F: configs/imx6dl_icore_rqs_mmc_defconfig
diff --git a/board/engicam/icorem6_rqs/Makefile b/board/engicam/icorem6_rqs/Makefile
new file mode 100644
index 0000000..2e3933c
--- /dev/null
+++ b/board/engicam/icorem6_rqs/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := icorem6_rqs.o
diff --git a/board/engicam/icorem6_rqs/README b/board/engicam/icorem6_rqs/README
new file mode 100644
index 0000000..ccce622
--- /dev/null
+++ b/board/engicam/icorem6_rqs/README
@@ -0,0 +1,33 @@
+How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter Kit:
+----------------------------------------------------------------------------------
+
+$ make mrproper
+
+- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual:
+$ make imx6q_icore_rqs_mmc_defconfig
+
+- Configure U-Boot for Engicam i.CoreM6 RQS Solo/DualLite:
+$ make imx6dl_icore_rqs_mmc_defconfig
+
+- Build U-Boot
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c
new file mode 100644
index 0000000..2769177
--- /dev/null
+++ b/board/engicam/icorem6_rqs/icorem6_rqs.c
@@ -0,0 +1,399 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+int board_early_init_f(void)
+{
+ SETUP_IOMUX_PADS(uart4_pads);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR, 1, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC3
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning - USDHC%d controller not supporting\n",
+ i + 1);
+ return 0;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+/*
+ * Driving strength:
+ * 0x30 == 40 Ohm
+ * 0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH 0x30
+#define IMX6SDL_DRIVE_STRENGTH 0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ .dram_sdqs0 = 0x28,
+ .dram_sdqs1 = 0x28,
+ .dram_sdqs2 = 0x28,
+ .dram_sdqs3 = 0x28,
+ .dram_sdqs4 = 0x28,
+ .dram_sdqs5 = 0x28,
+ .dram_sdqs6 = 0x28,
+ .dram_sdqs7 = 0x28,
+ .dram_dqm0 = 0x28,
+ .dram_dqm1 = 0x28,
+ .dram_dqm2 = 0x28,
+ .dram_dqm3 = 0x28,
+ .dram_dqm4 = 0x28,
+ .dram_dqm5 = 0x28,
+ .dram_dqm6 = 0x28,
+ .dram_dqm7 = 0x28,
+ .dram_cas = 0x30,
+ .dram_ras = 0x30,
+ .dram_sdclk_0 = 0x30,
+ .dram_sdclk_1 = 0x30,
+ .dram_reset = 0x30,
+ .dram_sdcke0 = 0x3000,
+ .dram_sdcke1 = 0x3000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x30,
+ .dram_sdodt1 = 0x30,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ .grp_b0ds = 0x30,
+ .grp_b1ds = 0x30,
+ .grp_b2ds = 0x30,
+ .grp_b3ds = 0x30,
+ .grp_b4ds = 0x30,
+ .grp_b5ds = 0x30,
+ .grp_b6ds = 0x30,
+ .grp_b7ds = 0x30,
+ .grp_addds = 0x30,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ctlds = 0x30,
+ .grp_ddr_type = 0x000c0000,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = 0x30,
+ .dram_sdclk_1 = 0x30,
+ .dram_cas = 0x30,
+ .dram_ras = 0x30,
+ .dram_reset = 0x30,
+ .dram_sdcke0 = 0x30,
+ .dram_sdcke1 = 0x30,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x30,
+ .dram_sdodt1 = 0x30,
+ .dram_sdqs0 = 0x28,
+ .dram_sdqs1 = 0x28,
+ .dram_sdqs2 = 0x28,
+ .dram_sdqs3 = 0x28,
+ .dram_sdqs4 = 0x28,
+ .dram_sdqs5 = 0x28,
+ .dram_sdqs6 = 0x28,
+ .dram_sdqs7 = 0x28,
+ .dram_dqm0 = 0x28,
+ .dram_dqm1 = 0x28,
+ .dram_dqm2 = 0x28,
+ .dram_dqm3 = 0x28,
+ .dram_dqm4 = 0x28,
+ .dram_dqm5 = 0x28,
+ .dram_dqm6 = 0x28,
+ .dram_dqm7 = 0x28,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x30,
+ .grp_ctlds = 0x30,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x28,
+ .grp_b1ds = 0x28,
+ .grp_b2ds = 0x28,
+ .grp_b3ds = 0x28,
+ .grp_b4ds = 0x28,
+ .grp_b5ds = 0x28,
+ .grp_b6ds = 0x28,
+ .grp_b7ds = 0x28,
+};
+
+/* mt41j256 */
+static struct mx6_ddr3_cfg mt41j256 = {
+ .mem_speed = 1066,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 13,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+ .SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x000E0009,
+ .p0_mpwldectrl1 = 0x0018000E,
+ .p1_mpwldectrl0 = 0x00000007,
+ .p1_mpwldectrl1 = 0x00000000,
+ .p0_mpdgctrl0 = 0x43280334,
+ .p0_mpdgctrl1 = 0x031C0314,
+ .p1_mpdgctrl0 = 0x4318031C,
+ .p1_mpdgctrl1 = 0x030C0258,
+ .p0_mprddlctl = 0x3E343A40,
+ .p1_mprddlctl = 0x383C3844,
+ .p0_mpwrdlctl = 0x40404440,
+ .p1_mpwrdlctl = 0x4C3E4446,
+};
+
+/* DDR 64bit */
+static struct mx6_ddr_sysinfo mem_q = {
+ .ddr_type = DDR_TYPE_DDR3,
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 2,
+ .rtt_wr = 2,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001F0024,
+ .p0_mpwldectrl1 = 0x00110018,
+ .p1_mpwldectrl0 = 0x001F0024,
+ .p1_mpwldectrl1 = 0x00110018,
+ .p0_mpdgctrl0 = 0x4230022C,
+ .p0_mpdgctrl1 = 0x02180220,
+ .p1_mpdgctrl0 = 0x42440248,
+ .p1_mpdgctrl1 = 0x02300238,
+ .p0_mprddlctl = 0x44444A48,
+ .p1_mprddlctl = 0x46484A42,
+ .p0_mpwrdlctl = 0x38383234,
+ .p1_mpwrdlctl = 0x3C34362E,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 1,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+ .dsize = 1,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 1,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00003F3F, &ccm->CCGR0);
+ writel(0x0030FC00, &ccm->CCGR1);
+ writel(0x000FC000, &ccm->CCGR2);
+ writel(0x3F300000, &ccm->CCGR3);
+ writel(0xFF00F300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003CC, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_mx6solo()) {
+ mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
+ } else if (is_mx6dl()) {
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
+ } else if (is_mx6dq()) {
+ mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+ mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
+ }
+
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
index 22a59e4..29421fc 100644
--- a/board/esd/common/lcd.c
+++ b/board/esd/common/lcd.c
@@ -8,7 +8,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "asm/io.h"
+#include <asm/io.h>
#include "lcd.h"
diff --git a/board/espt/Makefile b/board/espt/Makefile
index 8a8a2c9..f24e9cf 100644
--- a/board/espt/Makefile
+++ b/board/espt/Makefile
@@ -8,4 +8,4 @@
#
obj-y := espt.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/espt/espt.c b/board/espt/espt.c
index ee6e538..9ab71fe 100644
--- a/board/espt/espt.c
+++ b/board/espt/espt.c
@@ -11,8 +11,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: ESPT-GIGA\n");
@@ -24,14 +22,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig
index c7aab75..01d68e1 100644
--- a/board/freescale/b4860qds/Kconfig
+++ b/board/freescale/b4860qds/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_B4860QDS
+if TARGET_B4860QDS || TARGET_B4420QDS
config SYS_BOARD
default "b4860qds"
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
index 673d2ea..c032242 100644
--- a/board/freescale/b4860qds/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -8,7 +8,8 @@
obj-y += spl.o
else
obj-y += b4860qds.o
-obj-$(CONFIG_B4860QDS) += eth_b4860qds.o
+obj-$(CONFIG_TARGET_B4860QDS) += eth_b4860qds.o
+obj-$(CONFIG_TARGET_B4420QDS) += eth_b4860qds.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index e582abb..83a7015 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -11,7 +11,7 @@
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
@@ -437,7 +437,7 @@
}
break;
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
case 0x17:
case 0x18:
/*
@@ -496,7 +496,7 @@
/* Configure VSC3308 crossbar switch */
ret = select_i2c_ch_pca(I2C_CH_VSC3308);
switch (serdes2_prtcl) {
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
case 0x9d:
#endif
case 0x9E:
@@ -929,7 +929,7 @@
* For this SerDes2's Refclk1 need to be set to 100MHz
*/
switch (serdes2_prtcl) {
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
case 0x9d:
#endif
case 0x9E:
@@ -1209,7 +1209,7 @@
fdt_fixup_liodn(blob);
#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index fcccb8f..901f8b0 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -28,7 +28,7 @@
{7, 8}, {9, 0}, {5, 14},
{4, 15}, {2, 12}, {12, 13} };
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
@@ -54,7 +54,7 @@
{7, 8}, {1, 9}, {14, 11},
{15, 10}, {13, 3}, {12, 12} };
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index 31b186e..99cd884 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -171,6 +171,9 @@
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x3e;
}
phys_size_t initdram(int board_type)
@@ -210,7 +213,7 @@
debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
rank_density, ctlr_density);
- for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+ for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
@@ -234,7 +237,7 @@
* Simple linear assignment if memory
* controllers are not interleaved.
*/
- for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+ for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
total_ctlr_mem = 0;
pinfo->common_timing_params[i].base_address =
current_mem_base;
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 164ec0a..89a1883 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -213,7 +213,7 @@
fm_info_set_phy_address(FM1_DTSEC6,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
index 75e1142..fb8bb39 100644
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -73,7 +73,7 @@
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
return 0;
}
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index 71a7bb5..2c836da 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -394,7 +394,7 @@
/* remove dts usb node */
fdt_del_node_compat(blob, "fsl-usb2-dr");
} else {
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
fdt_del_node_and_alias(blob, "serial2");
}
}
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index be114ce..e941949 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -45,18 +45,18 @@
obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
-obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
-obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
-obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8541CDS) += cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o
-obj-$(CONFIG_MPC8536DS) += ics307_clk.o
-obj-$(CONFIG_MPC8572DS) += ics307_clk.o
-obj-$(CONFIG_P1022DS) += ics307_clk.o
+obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o
+obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o
+obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o
obj-$(CONFIG_P2020DS) += ics307_clk.o
-obj-$(CONFIG_P3041DS) += ics307_clk.o
-obj-$(CONFIG_P4080DS) += ics307_clk.o
-obj-$(CONFIG_P5020DS) += ics307_clk.o
-obj-$(CONFIG_P5040DS) += ics307_clk.o
+obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
+obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o
+obj-$(CONFIG_TARGET_P5020DS) += ics307_clk.o
+obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
@@ -65,11 +65,11 @@
obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
# deal with common files for P-series corenet based devices
-obj-$(CONFIG_P2041RDB) += p_corenet/
-obj-$(CONFIG_P3041DS) += p_corenet/
-obj-$(CONFIG_P4080DS) += p_corenet/
-obj-$(CONFIG_P5020DS) += p_corenet/
-obj-$(CONFIG_P5040DS) += p_corenet/
+obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
+obj-$(CONFIG_TARGET_P3041DS) += p_corenet/
+obj-$(CONFIG_TARGET_P4080DS) += p_corenet/
+obj-$(CONFIG_TARGET_P5020DS) += p_corenet/
+obj-$(CONFIG_TARGET_P5040DS) += p_corenet/
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index 71ed15e..16fd445 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -66,6 +66,36 @@
*dst++ = *src++;
}
+#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA)
+void ls1_psci_resume_fixup(void)
+{
+ u32 tmp;
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef QIXIS_BASE
+ void *qixis_base = (void *)QIXIS_BASE;
+
+ /* Pull on PCIe RST# */
+ out_8(qixis_base + QIXIS_RST_FORCE_3, 0);
+
+ /* disable deep sleep signals in FPGA */
+ tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
+ tmp &= ~QIXIS_PWR_CTL2_PCTL;
+ out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
+#endif
+
+ /* Disable wakeup interrupt during deep sleep */
+ out_be32(&scfg->pmcintecr, 0);
+ /* Clear PMC interrupt status */
+ out_be32(&scfg->pmcintsr, 0xffffffff);
+
+ /* Disable Warm Device Reset */
+ tmp = in_be32(&scfg->dpslpcr);
+ tmp &= ~SCFG_DPSLPCR_WDRR_EN;
+ out_be32(&scfg->dpslpcr, tmp);
+}
+#endif
+
static void dp_resume_prepare(void)
{
dp_ddr_restore();
@@ -74,6 +104,9 @@
#ifdef CONFIG_U_QE
u_qe_resume();
#endif
+#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA)
+ ls1_psci_resume_fixup();
+#endif
}
int fsl_dp_resume(void)
@@ -88,7 +121,7 @@
dp_resume_prepare();
/* Get the entry address and jump to kernel */
- start_addr = in_le32(&scfg->sparecr[1]);
+ start_addr = in_le32(&scfg->sparecr[3]);
debug("Entry address is 0x%08x\n", start_addr);
kernel_resume = (void (*)(void))start_addr;
secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 8c171b1..2b723a4 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -301,27 +301,15 @@
*/
static void fsl_secboot_header_verification_failure(void)
{
- struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
- u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
/* 29th bit of OSPR is ITS */
u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
- /*
- * Read the SEC_MON status register
- * Read SSM_ST field
- */
- sts = sec_mon_in32(&sec_mon_regs->hp_stat);
- if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
- if (its == 1)
- change_sec_mon_state(HPSR_SSM_ST_TRUST,
- HPSR_SSM_ST_SOFT_FAIL);
- else
- change_sec_mon_state(HPSR_SSM_ST_TRUST,
- HPSR_SSM_ST_NON_SECURE);
- }
+ if (its == 1)
+ set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
+ else
+ set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
printf("Generating reset request\n");
do_reset(NULL, 0, 0, NULL);
@@ -338,32 +326,20 @@
*/
static void fsl_secboot_image_verification_failure(void)
{
- struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
- u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
- /*
- * Read the SEC_MON status register
- * Read SSM_ST field
- */
- sts = sec_mon_in32(&sec_mon_regs->hp_stat);
- if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
- if (its == 1) {
- change_sec_mon_state(HPSR_SSM_ST_TRUST,
- HPSR_SSM_ST_SOFT_FAIL);
+ if (its == 1) {
+ set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
- printf("Generating reset request\n");
- do_reset(NULL, 0, 0, NULL);
- /* If reset doesn't coocur, halt execution */
- do_esbc_halt(NULL, 0, 0, NULL);
+ printf("Generating reset request\n");
+ do_reset(NULL, 0, 0, NULL);
+ /* If reset doesn't coocur, halt execution */
+ do_esbc_halt(NULL, 0, 0, NULL);
- } else {
- change_sec_mon_state(HPSR_SSM_ST_TRUST,
- HPSR_SSM_ST_NON_SECURE);
- }
+ } else {
+ set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
}
}
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index d8d16c5..81c9211 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -8,29 +8,63 @@
#include <asm/io.h>
#include <fsl_csu.h>
#include <asm/arch/ns_access.h>
+#include <asm/arch/fsl_serdes.h>
-static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
{
u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
u32 *reg;
- uint32_t val;
+ uint32_t tmp;
+
+ reg = base + ns_dev->ind / 2;
+ tmp = in_be32(reg);
+ if (ns_dev->ind % 2 == 0) {
+ tmp &= 0x0000ffff;
+ tmp |= val << 16;
+ } else {
+ tmp &= 0xffff0000;
+ tmp |= val;
+ }
+
+ out_be32(reg, tmp);
+}
+
+static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
int i;
- for (i = 0; i < num; i++) {
- reg = base + ns_dev[i].ind / 2;
- val = in_be32(reg);
- if (ns_dev[i].ind % 2 == 0) {
- val &= 0x0000ffff;
- val |= ns_dev[i].val << 16;
- } else {
- val &= 0xffff0000;
- val |= ns_dev[i].val;
- }
- out_be32(reg, val);
- }
+ for (i = 0; i < num; i++)
+ set_devices_ns_access(ns_dev + i, ns_dev[i].val);
}
void enable_layerscape_ns_access(void)
{
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
}
+
+void set_pcie_ns_access(int pcie, u16 val)
+{
+ switch (pcie) {
+#ifdef CONFIG_PCIE1
+ case PCIE1:
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
+ return;
+#endif
+#ifdef CONFIG_PCIE2
+ case PCIE2:
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
+ return;
+#endif
+#ifdef CONFIG_PCIE3
+ case PCIE3:
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
+ return;
+#endif
+ default:
+ debug("The PCIE%d doesn't exist!\n", pcie);
+ return;
+ }
+}
diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h
index 9328404..e6e0f66 100644
--- a/board/freescale/common/pixis.h
+++ b/board/freescale/common/pixis.h
@@ -7,7 +7,7 @@
#define __PIXIS_H_ 1
/* PIXIS register set. */
-#if defined(CONFIG_MPC8536DS)
+#if defined(CONFIG_TARGET_MPC8536DS)
typedef struct pixis {
u8 id;
u8 ver;
@@ -46,7 +46,7 @@
u8 res2[4];
} __attribute__ ((packed)) pixis_t;
-#elif defined(CONFIG_MPC8544DS)
+#elif defined(CONFIG_TARGET_MPC8544DS)
typedef struct pixis {
u8 id;
u8 ver;
@@ -73,7 +73,7 @@
u8 res2[34];
} __attribute__ ((packed)) pixis_t;
-#elif defined(CONFIG_MPC8572DS)
+#elif defined(CONFIG_TARGET_MPC8572DS)
typedef struct pixis {
u8 id;
u8 ver;
@@ -102,7 +102,7 @@
u8 res4[25];
} __attribute__ ((packed)) pixis_t;
-#elif defined(CONFIG_MPC8610HPCD)
+#elif defined(CONFIG_TARGET_MPC8610HPCD)
typedef struct pixis {
u8 id;
u8 ver; /* also called arch */
@@ -132,7 +132,7 @@
u8 res4[33];
} __attribute__ ((packed)) pixis_t;
-#elif defined(CONFIG_MPC8641HPCN)
+#elif defined(CONFIG_TARGET_MPC8641HPCN)
typedef struct pixis {
u8 id;
u8 ver;
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index 1eb3786..d152a78 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -63,7 +63,7 @@
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_MPC8569MDS)
+#if defined(CONFIG_TARGET_MPC8569MDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, &val8, 1);
i2c_write(0x20, 0x7, 1, &val8, 1);
diff --git a/board/freescale/common/spl.h b/board/freescale/common/spl.h
new file mode 100644
index 0000000..88c987e
--- /dev/null
+++ b/board/freescale/common/spl.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FREESCALE_BOARD_SPL_H
+#define __FREESCALE_BOARD_SPL_H
+
+void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+void fsl_spi_boot(void) __noreturn;
+
+#endif
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 2f29795..1a50304 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -8,7 +8,7 @@
#include <command.h>
#include <i2c.h>
#include <asm/io.h>
-#ifdef CONFIG_LS1043A
+#ifdef CONFIG_FSL_LSCH2
#include <asm/arch/immap_lsch2.h>
#elif defined(CONFIG_FSL_LSCH3)
#include <asm/arch/immap_lsch3.h>
@@ -247,7 +247,7 @@
* SoC before converting into an IR VID value
*/
vdd += board_vdd_drop_compensation();
-#ifdef CONFIG_LS1043A
+#ifdef CONFIG_FSL_LSCH2
vid = DIV_ROUND_UP(vdd - 265, 5);
#else
vid = DIV_ROUND_UP(vdd - 245, 5);
@@ -287,7 +287,7 @@
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
-#if defined(CONFIG_LS1043A) || defined(CONFIG_FSL_LSCH3)
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
@@ -386,7 +386,7 @@
* | T | | | | |
* ------------------------------------------------------
*/
-#ifdef CONFIG_LS1043A
+#ifdef CONFIG_FSL_LSCH2
vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c
index be5953a..a6c3e69 100644
--- a/board/freescale/common/zm7300.c
+++ b/board/freescale/common/zm7300.c
@@ -140,9 +140,7 @@
/* Uses the DPM command RRP */
u8 zm_read(uchar reg)
{
- u8 d;
- d = dpm_rrp(reg);
- return d;
+ return dpm_rrp(reg);
}
/* ZM_write --
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
index 9ade947..100ba92 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -8,11 +8,11 @@
obj-y += corenet_ds.o
obj-y += ddr.o
-obj-$(CONFIG_P3041DS) += eth_hydra.o
-obj-$(CONFIG_P4080DS) += eth_p4080.o
-obj-$(CONFIG_P5020DS) += eth_hydra.o
-obj-$(CONFIG_P5040DS) += eth_superhydra.o
-obj-$(CONFIG_P3041DS) += p3041ds_ddr.o
-obj-$(CONFIG_P4080DS) += p4080ds_ddr.o
-obj-$(CONFIG_P5020DS) += p5020ds_ddr.o
-obj-$(CONFIG_P5040DS) += p5040ds_ddr.o
+obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o
+obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o
+obj-$(CONFIG_TARGET_P5020DS) += eth_hydra.o
+obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o
+obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o
+obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o
+obj-$(CONFIG_TARGET_P5020DS) += p5020ds_ddr.o
+obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index f41985d..93e1258 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -26,8 +26,8 @@
{
u8 sw;
struct cpu_type *cpu = gd->arch.cpu;
-#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \
- defined(CONFIG_P5040DS)
+#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
+ defined(CONFIG_TARGET_P5040DS)
unsigned int i;
#endif
static const char * const freq[] = {"100", "125", "156.25", "212.5" };
@@ -56,15 +56,15 @@
* don't match.
*/
puts("SERDES Reference Clocks: ");
-#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
- || defined(CONFIG_P5040DS)
+#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
+ defined(CONFIG_TARGET_P5040DS)
sw = in_8(&PIXIS_SW(5));
for (i = 0; i < 3; i++) {
unsigned int clock = (sw >> (6 - (2 * i))) & 3;
printf("Bank%u=%sMhz ", i+1, freq[clock]);
}
-#ifdef CONFIG_P5040DS
+#ifdef CONFIG_TARGET_P5040DS
/* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
sw = in_8(&PIXIS_SW(9));
printf("Bank4=%sMhz ", freq[sw & 3]);
@@ -136,8 +136,8 @@
unsigned int i;
u8 sw;
-#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
- || defined(CONFIG_P5040DS)
+#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
+ defined(CONFIG_TARGET_P5040DS)
sw = in_8(&PIXIS_SW(5));
for (i = 0; i < 3; i++) {
unsigned int clock = (sw >> (6 - (2 * i))) & 3;
@@ -201,7 +201,7 @@
#endif
fdt_fixup_liodn(blob);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index f3ba41a..9c1a4c2 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -19,7 +19,7 @@
* Fixed sdram init -- doesn't use serial presence detect.
*/
extern fixed_ddr_parm_t fixed_ddr_parm_0[];
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
extern fixed_ddr_parm_t fixed_ddr_parm_1[];
#endif
@@ -56,7 +56,7 @@
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_1[i].ddr_settings,
sizeof(ddr_cfg_regs));
@@ -76,7 +76,7 @@
return 0;
}
} else {
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
/* We require both controllers have identical DIMMs */
lawbar1_target_id = LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index a94a458..b03bdb8 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -11,27 +11,12 @@
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
-#include <fsl_csu.h>
#include <environment.h>
#include <fsl_mmdc.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
- int timeout = 1000;
-
- out_be32(ptr, value);
-
- while (in_be32(ptr) & bits) {
- udelay(100);
- timeout--;
- }
- if (timeout <= 0)
- puts("Error: wait for clear timeout.\n");
-}
-
int checkboard(void)
{
puts("Board: LS1012AFRDM ");
@@ -39,111 +24,25 @@
return 0;
}
-void mmdc_init(void)
-{
- struct mmdc_p_regs *mmdc =
- (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- /* configure timing parms */
- out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
- out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
- out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
- out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
- /* other parms */
- out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
- out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
- out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
- out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
- /* out of reset delays */
- out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
- /* physical parms */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
- out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
- /* Enable MMDC */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
- /* dram init sequence: update MRs */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
- CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
- /* dram init sequence: ZQCL */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
- set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
- CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
- FORCE_ZQ_AUTO_CALIBRATION);
-
- /* Calibrations now: wr lvl */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
- CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
- set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
- mdelay(1);
-
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- mdelay(1);
-
- /* Calibrations now: Read DQS gating calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
- set_wait_for_bits_clear(&mmdc->mpdgctrl0,
- AUTO_RD_DQS_GATING_CALIBRATION_EN,
- AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* Calibrations now: Read calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- set_wait_for_bits_clear(&mmdc->mprddlhwctl,
- AUTO_RD_CALIBRATION_EN,
- AUTO_RD_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* PD, SR */
- out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
- out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
-
- /* refresh scheme */
- set_wait_for_bits_clear(&mmdc->mdref,
- CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
- START_REFRESH);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
-}
-
int dram_init(void)
{
- mmdc_init();
+ static const struct fsl_mmdc_info mparam = {
+ 0x04180000, /* mdctl */
+ 0x00030035, /* mdpdc */
+ 0x12554000, /* mdotc */
+ 0xbabf7954, /* mdcfg0 */
+ 0xdb328f64, /* mdcfg1 */
+ 0x01ff00db, /* mdcfg2 */
+ 0x00001680, /* mdmisc */
+ 0x0f3c8000, /* mdref */
+ 0x00002000, /* mdrwd */
+ 0x00bf1023, /* mdor */
+ 0x0000003f, /* mdasp */
+ 0x0000022a, /* mpodtctrl */
+ 0xa1390003, /* mpzqhwctrl */
+ };
+
+ mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
@@ -175,10 +74,6 @@
gd->env_addr = (ulong)&default_environment[0];
#endif
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
-#endif
-
return 0;
}
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 71eea82..94440b3 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -17,7 +17,6 @@
#include <mmc.h>
#include <scsi.h>
#include <fm_eth.h>
-#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_mmdc.h>
#include <spl.h>
@@ -28,20 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
- int timeout = 1000;
-
- out_be32(ptr, value);
-
- while (in_be32(ptr) & bits) {
- udelay(100);
- timeout--;
- }
- if (timeout <= 0)
- puts("Error: wait for clear timeout.\n");
-}
-
int checkboard(void)
{
char buf[64];
@@ -67,111 +52,25 @@
return 0;
}
-void mmdc_init(void)
-{
- struct mmdc_p_regs *mmdc =
- (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- /* configure timing parms */
- out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
- out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
- out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
- out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
- /* other parms */
- out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
- out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
- out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
- out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
- /* out of reset delays */
- out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
- /* physical parms */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
- out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
- /* Enable MMDC */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
- /* dram init sequence: update MRs */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
- CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
- /* dram init sequence: ZQCL */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
- set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
- CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
- FORCE_ZQ_AUTO_CALIBRATION);
-
- /* Calibrations now: wr lvl */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
- CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
- set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
- mdelay(1);
-
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- mdelay(1);
-
- /* Calibrations now: Read DQS gating calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
- set_wait_for_bits_clear(&mmdc->mpdgctrl0,
- AUTO_RD_DQS_GATING_CALIBRATION_EN,
- AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* Calibrations now: Read calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- set_wait_for_bits_clear(&mmdc->mprddlhwctl,
- AUTO_RD_CALIBRATION_EN,
- AUTO_RD_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* PD, SR */
- out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
- out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
-
- /* refresh scheme */
- set_wait_for_bits_clear(&mmdc->mdref,
- CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
- START_REFRESH);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
-}
-
int dram_init(void)
{
- mmdc_init();
+ static const struct fsl_mmdc_info mparam = {
+ 0x05180000, /* mdctl */
+ 0x00030035, /* mdpdc */
+ 0x12554000, /* mdotc */
+ 0xbabf7954, /* mdcfg0 */
+ 0xdb328f64, /* mdcfg1 */
+ 0x01ff00db, /* mdcfg2 */
+ 0x00001680, /* mdmisc */
+ 0x0f3c8000, /* mdref */
+ 0x00002000, /* mdrwd */
+ 0x00bf1023, /* mdor */
+ 0x0000003f, /* mdasp */
+ 0x0000022a, /* mpodtctrl */
+ 0xa1390003, /* mpzqhwctrl */
+ };
+
+ mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
@@ -207,8 +106,8 @@
out_le32(&cci->ctrl_ord,
CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+ erratum_a010315();
#endif
#ifdef CONFIG_ENV_IS_NOWHERE
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index f69768d..778434d 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -14,7 +14,6 @@
#include <ahci.h>
#include <mmc.h>
#include <scsi.h>
-#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <environment.h>
#include <fsl_mmdc.h>
@@ -22,20 +21,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
- int timeout = 1000;
-
- out_be32(ptr, value);
-
- while (in_be32(ptr) & bits) {
- udelay(100);
- timeout--;
- }
- if (timeout <= 0)
- puts("Error: wait for clear timeout.\n");
-}
-
int checkboard(void)
{
u8 in1;
@@ -71,111 +56,25 @@
return 0;
}
-void mmdc_init(void)
-{
- struct mmdc_p_regs *mmdc =
- (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- /* configure timing parms */
- out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
- out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
- out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
- out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
- /* other parms */
- out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
- out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
- out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
- out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
- /* out of reset delays */
- out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
- /* physical parms */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
- out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
- /* Enable MMDC */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
- /* dram init sequence: update MRs */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
- CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
- /* dram init sequence: ZQCL */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
- set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
- CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
- FORCE_ZQ_AUTO_CALIBRATION);
-
- /* Calibrations now: wr lvl */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
- CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
- set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
- mdelay(1);
-
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- mdelay(1);
-
- /* Calibrations now: Read DQS gating calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
- set_wait_for_bits_clear(&mmdc->mpdgctrl0,
- AUTO_RD_DQS_GATING_CALIBRATION_EN,
- AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* Calibrations now: Read calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- set_wait_for_bits_clear(&mmdc->mprddlhwctl,
- AUTO_RD_CALIBRATION_EN,
- AUTO_RD_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* PD, SR */
- out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
- out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
-
- /* refresh scheme */
- set_wait_for_bits_clear(&mmdc->mdref,
- CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
- START_REFRESH);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
-}
-
int dram_init(void)
{
- mmdc_init();
+ static const struct fsl_mmdc_info mparam = {
+ 0x05180000, /* mdctl */
+ 0x00030035, /* mdpdc */
+ 0x12554000, /* mdotc */
+ 0xbabf7954, /* mdcfg0 */
+ 0xdb328f64, /* mdcfg1 */
+ 0x01ff00db, /* mdcfg2 */
+ 0x00001680, /* mdmisc */
+ 0x0f3c8000, /* mdref */
+ 0x00002000, /* mdrwd */
+ 0x00bf1023, /* mdor */
+ 0x0000003f, /* mdasp */
+ 0x0000022a, /* mpodtctrl */
+ 0xa1390003, /* mpzqhwctrl */
+ };
+
+ mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
@@ -203,12 +102,12 @@
*/
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+ erratum_a010315();
#endif
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
#endif
return 0;
diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig
new file mode 100644
index 0000000..4a12c16
--- /dev/null
+++ b/board/freescale/ls1021aiot/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1021AIOT
+
+config SYS_BOARD
+ default "ls1021aiot"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "ls102xa"
+
+config SYS_CONFIG_NAME
+ default "ls1021aiot"
+
+endif
diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS
new file mode 100644
index 0000000..2dab798
--- /dev/null
+++ b/board/freescale/ls1021aiot/MAINTAINERS
@@ -0,0 +1,7 @@
+LS1021AIOT BOARD
+M: Feng Li <feng.li_2@nxp.com>
+S: Maintained
+F: board/freescale/ls1021aiot/
+F: include/configs/ls1021aiot.h
+F: configs/ls1021aiot_sdcard_defconfig
+F: configs/ls1021aiot_qspi_defconfig
diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile
new file mode 100644
index 0000000..05709e6
--- /dev/null
+++ b/board/freescale/ls1021aiot/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1021aiot.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aiot/README b/board/freescale/ls1021aiot/README
new file mode 100644
index 0000000..08b0268
--- /dev/null
+++ b/board/freescale/ls1021aiot/README
@@ -0,0 +1,58 @@
+Overview
+--------
+The LS1021A-IOT is a Freescale reference board that hosts
+the LS1021A SoC.
+
+LS1021AIOT board Overview
+-------------------------
+ - DDR Controller
+ - Supports 1GB un-buffered DDR3L SDRAM discrete
+ devices(32-bit bus) with 4 bit ECC
+ - DDR power supplies 1.35V to all devices with
+ automatic tracking of VTT
+ - Soldered DDR chip
+ - Supprot one fixed speed
+ - Ethernet
+ - Two on-board SGMII 10/100/1G ethernet ports
+ - One Gbit Etherent RGMII interface to 4-ports switch
+ with 4x 10/100/1000 RJ145 ports
+ - CPLD
+ - 8-bit registers in CPLD for system configuration
+ - connected to IFC_AD[0:7]
+ - Power Supplies
+ - 12V@5A DC
+ - SDHC
+ - SDHC port connects directly to a full 8-bit SD/MMC slot
+ - Support for SDIO devices
+ - USB
+ - Two on-board USB 3.0
+ - One on-board USB k22
+ - PCIe
+ - Two MiniPCIe Solts
+ - SATA
+ - Support SATA Connector
+ - AUDIO
+ - AUDIO in and out
+ - I/O Expansion
+ - Arduino Shield Connector
+ - Port0 - CAN/GPIO/Flextimer
+ - Port1 - GPIO/CPLD Expansion
+ - Port2 - SPI/I2C/UART
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address End Address Description Size
+0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_4000_0000 0x00_43FF_FFFF QSPI(Chip select 0) 64MB
+0x00_4400_0000 0x00_47FF_FFFF QSPI(Chip select 1) 64MB
+0x00_6000_0000 0x00_6000_FFFF CPLD 64K
+0x00_8000_0000 0x00_BFFF_FFFF DDR 1GB
+
+Boot description
+-----------------
+LS1021A-IOT support two ways of boot:
+Qspi boot and SD boot
+The board doesn't support boot from another
+source without changing any switch/jumper.
diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c
new file mode 100644
index 0000000..e27647f
--- /dev/null
+++ b/board/freescale/ls1021aiot/dcu.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+#include "../common/dcu_sii9022a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long long div;
+
+ div = (unsigned long long)(gd->bus_clk / 1000);
+ div *= (unsigned long long)pixclock;
+ do_div(div, 1000000000);
+
+ return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
+{
+ const char *name;
+ unsigned int pixel_format;
+
+ if (strncmp(port, "twr_lcd", 4) == 0) {
+ name = "TWR_LCD_RGB card";
+ } else {
+ name = "HDMI";
+ dcu_set_dvi_encoder(dcu_fb_videomode);
+ }
+
+ printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+ pixel_format = 32;
+ fsl_dcu_init(xres, yres, pixel_format);
+
+ return 0;
+}
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
new file mode 100644
index 0000000..3340e4d
--- /dev/null
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/ls102xa_sata.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <spl.h>
+
+#include <fsl_validate.h>
+#include "../common/sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_SIZE 0x40000000
+
+
+int checkboard(void)
+{
+ puts("Board: LS1021AIOT\n");
+
+#ifndef CONFIG_QSPI_BOOT
+ struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 cpldrev;
+
+ cpldrev = in_be32(&dcfg->gpporcr1);
+
+ printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
+ 0xf));
+#endif
+ return 0;
+}
+
+void ddrmc_init(void)
+{
+ struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ u32 temp_sdram_cfg, tmp;
+
+ out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
+
+ out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
+ out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
+
+ out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
+ out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
+ out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
+ out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
+ out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
+ out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
+
+ out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+ out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+
+ out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
+ out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
+
+ out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
+
+ out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
+
+ out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
+ out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
+
+ out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
+
+ out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
+ out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
+
+ out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+ /* DDR erratum A-009942 */
+ tmp = in_be32(&ddr->debug[28]);
+ out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
+ udelay(500);
+
+ temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+ out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+}
+
+int dram_init(void)
+{
+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+ ddrmc_init();
+#endif
+
+ gd->ram_size = DDR_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {CONFIG_SYS_FSL_ESDHC_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+
+#endif
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ if (is_serdes_configured(SGMII_TSEC1)) {
+ puts("eTSEC1 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (is_serdes_configured(SGMII_TSEC2)) {
+ puts("eTSEC2 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+ /* clear BD & FR bits for BE BD's and frame data */
+ clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+
+#endif
+
+ arch_soc_init();
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ get_clocks();
+
+ preloader_console_init();
+
+ dram_init();
+
+ /* Allow OCRAM access permission as R/W */
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ board_init_r(NULL, 0);
+}
+#endif
+
+int board_init(void)
+{
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+ fsl_serdes_init();
+#endif
+
+ ls102xa_smmu_stream_id_init();
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ ls1021a_sata_init();
+#endif
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+ device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+ return sec_init();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
+
+void flash_write16(u16 val, void *addr)
+{
+ u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+ __raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 val = __raw_readw(addr);
+
+ return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/board/freescale/ls1021aiot/ls102xa_pbi.cfg b/board/freescale/ls1021aiot/ls102xa_pbi.cfg
new file mode 100644
index 0000000..b5ac5e2
--- /dev/null
+++ b/board/freescale/ls1021aiot/ls102xa_pbi.cfg
@@ -0,0 +1,14 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
+
+09ea085c 00502880
diff --git a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
new file mode 100644
index 0000000..a1984c7
--- /dev/null
+++ b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
@@ -0,0 +1,27 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+
+#Default with 2 x SGMII (no SATA)
+0608000a 00000000 00000000 00000000
+20000000 08407900 60025a00 21046000
+00000000 00000000 00000000 20038000
+20024800 881b1340 00000000 00000000
+
+#SATA set-up
+#0608000a 00000000 00000000 00000000
+#70000000 08007900 60025a00 21046000
+#00000000 00000000 00000000 20038000
+#20024800 881b1340 00000000 00000000
+
+#HDMI set-up
+#0608000a 00000000 00000000 00000000
+#20000000 08407900 60025a00 21046000
+#00000000 00000000 00000000 20038000
+#00000000 881b1340 00000000 00000000
+
+#QE testing
+#0608000a 00000000 00000000 00000000
+#20000000 08407900 60025a00 21046000
+#00000000 00000000 00000000 00038000
+#20094800 881b1340 00000000 00000000
diff --git a/board/freescale/ls1021aiot/psci.S b/board/freescale/ls1021aiot/psci.S
new file mode 100644
index 0000000..564145c
--- /dev/null
+++ b/board/freescale/ls1021aiot/psci.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Feng Li <feng.li_2@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+ .pushsection ._secure.text, "ax"
+
+ .arch_extension sec
+
+ .align 5
+
+.globl psci_system_off
+psci_system_off:
+1: wfi
+ b 1b
+
+.globl psci_text_end
+psci_text_end:
+ nop
+ .popsection
diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README
index c561776..6cf7146 100644
--- a/board/freescale/ls1021aqds/README
+++ b/board/freescale/ls1021aqds/README
@@ -110,3 +110,9 @@
0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+--------------------------------------------
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021aqds.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index dbea0bf..79078d2 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -22,7 +22,7 @@
#include <spl.h>
#include <fsl_devdis.h>
#include <fsl_validate.h>
-
+#include <fsl_ddr.h>
#include "../common/sleep.h"
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
@@ -430,6 +430,12 @@
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+ erratum_a010315();
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+ erratum_a009942_check_cpo();
+#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to
@@ -446,10 +452,6 @@
ls102xa_smmu_stream_id_init();
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
-#endif
-
#ifdef CONFIG_U_QE
u_qe_init();
#endif
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
index 222c71d..d76e913 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# serdes protocol
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
60000000 00407900 e0106a00 21046000
00000000 00000000 00000000 00038000
00000000 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
index 9d99bd8..f0cf9c2 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
@@ -2,13 +2,13 @@
aa55aa55 01ee0100
#enable IFC, disable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
60000000 00407900 60040a00 21046000
00000000 00000000 00000000 00038000
00000000 001b7200 00000000 00000000
#disable IFC, enable QSPI and DSPI
-#0608000a 00000000 00000000 00000000
+#0608000c 00000000 00000000 00000000
#60000000 00407900 60040a00 21046000
#00000000 00000000 00000000 00038000
#20024800 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
index 2bd398c..10cc4a9 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
@@ -2,13 +2,13 @@
aa55aa55 01ee0100
#enable IFC, disable QSPI and DSPI
-#0608000a 00000000 00000000 00000000
+#0608000c 00000000 00000000 00000000
#60000000 00407900 60040a00 21046000
#00000000 00000000 00000000 00038000
#00000000 001b7200 00000000 00000000
#disable IFC, enable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
60000000 00407900 60040a00 21046000
00000000 00000000 00000000 00038000
20024800 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README
index d2821cb..896a659 100644
--- a/board/freescale/ls1021atwr/README
+++ b/board/freescale/ls1021atwr/README
@@ -107,3 +107,9 @@
0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+--------------------------------------------
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021atwr.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 77482a9..d96fd77 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -142,7 +142,7 @@
void ddrmc_init(void)
{
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
- u32 temp_sdram_cfg;
+ u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@@ -189,6 +189,11 @@
out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+ /* DDR erratum A-009942 */
+ tmp = in_be32(&ddr->debug[28]);
+ out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
udelay(1);
#ifdef CONFIG_DEEP_SLEEP
@@ -480,6 +485,10 @@
int board_init(void)
{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+ erratum_a010315();
+#endif
+
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
@@ -489,10 +498,6 @@
ls102xa_smmu_stream_id_init();
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
-#endif
-
#ifdef CONFIG_U_QE
u_qe_init();
#endif
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
index 205606f..f94997d 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
@@ -2,7 +2,7 @@
aa55aa55 01ee0100
#enable IFC, disable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
30000000 00007900 60040a00 21046000
00000000 00000000 00000000 20000000
00080000 881b7340 00000000 00000000
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
index 6767e09..541b604 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
@@ -2,7 +2,7 @@
aa55aa55 01ee0100
#disable IFC, enable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
30000000 00007900 60040a00 21046000
00000000 00000000 00000000 20000000
20024800 881b7340 00000000 00000000
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index d4540d0..7882a9a 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -96,6 +96,9 @@
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x59;
#else
popts->cswl_override = DDR_CSWL_CS0;
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 941dfbc..8835a49 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -17,7 +17,6 @@
#include <mmc.h>
#include <scsi.h>
#include <fm_eth.h>
-#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <spl.h>
@@ -309,6 +308,10 @@
int board_init(void)
{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+ erratum_a010315();
+#endif
+
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
@@ -316,9 +319,6 @@
config_serdes_mux();
#endif
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
-#endif
return 0;
}
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
index 51818ec..80203a4 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -13,4 +13,13 @@
config SYS_CONFIG_NAME
default "ls1043ardb"
+config SYS_HAS_ARMV8_SECURE_BASE
+ bool "Enable secure address for PSCI image"
+ depends on ARMV8_PSCI
+ default n
+ help
+ PSCI image can be re-located to secure RAM.
+ If enabled, please also define the value for ARMV8_SECURE_BASE,
+ for LS1043ARDB, it could be some address in OCRAM.
+
endif
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 61b1cc4..849f1d1 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -91,6 +91,9 @@
/* Enable ZQ calibration */
popts->zq_en = 1;
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x46;
+
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index d3e37b4..e213128 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -16,7 +16,6 @@
#include <mmc.h>
#include <scsi.h>
#include <fm_eth.h>
-#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
@@ -86,12 +85,29 @@
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+ erratum_a010315();
+#endif
+
#ifdef CONFIG_FSL_IFC
init_final_memctl_regs();
#endif
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
+#ifdef CONFIG_SECURE_BOOT
+ /* In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
@@ -137,21 +153,6 @@
int misc_init_r(void)
{
config_board_mux();
-#ifdef CONFIG_SECURE_BOOT
- /* In case of Secure Boot, the IBR configures the SMMU
- * to allow only Secure transactions.
- * SMMU must be reset in bypass mode.
- * Set the ClientPD bit and Clear the USFCFG Bit
- */
- u32 val;
- val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_SCR0, val);
- val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_NSCR0, val);
-#endif
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
return 0;
}
#endif
diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig
new file mode 100644
index 0000000..723f4ba
--- /dev/null
+++ b/board/freescale/ls1046aqds/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1046AQDS
+
+config SYS_BOARD
+ default "ls1046aqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1046aqds"
+
+endif
diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS
new file mode 100644
index 0000000..b4549ae
--- /dev/null
+++ b/board/freescale/ls1046aqds/MAINTAINERS
@@ -0,0 +1,10 @@
+LS1046AQDS BOARD
+M: Mingkai Hu <Mingkai.Hu@nxp.com>
+S: Maintained
+F: board/freescale/ls1046aqds/
+F: include/configs/ls1046aqds.h
+F: configs/ls1046aqds_defconfig
+F: configs/ls1046aqds_nand_defconfig
+F: configs/ls1046aqds_sdcard_ifc_defconfig
+F: configs/ls1046aqds_sdcard_qspi_defconfig
+F: configs/ls1046aqds_qspi_defconfig
diff --git a/board/freescale/ls1046aqds/Makefile b/board/freescale/ls1046aqds/Makefile
new file mode 100644
index 0000000..df6e546
--- /dev/null
+++ b/board/freescale/ls1046aqds/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ddr.o
+obj-y += eth.o
+obj-y += ls1046aqds.o
diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README
new file mode 100644
index 0000000..b8fa326
--- /dev/null
+++ b/board/freescale/ls1046aqds/README
@@ -0,0 +1,70 @@
+Overview
+--------
+The LS1046A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1046A
+LayerScape Architecture processor. The LS1046AQDS provides SW development
+platform for the Freescale LS1046A processor series, with a complete
+debugging environment.
+
+LS1046A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
+SoC overview.
+
+ LS1046AQDS board Overview
+ -----------------------
+ - SERDES Connections, 8 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - QSGMII
+ - SATA 3.0
+ - XFI
+ - DDR Controller
+ - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
+ -IFC/Local Bus
+ - One in-socket 128 MB NOR flash 16-bit data bus
+ - One 512 MB NAND flash with ECC support
+ - PromJet Port
+ - FPGA connection
+ - USB 3.0
+ - Three high speed USB 3.0 ports
+ - First USB 3.0 port configured as Host with Type-A connector
+ - The other two USB 3.0 ports configured as OTG with micro-AB connector
+ - SDHC port connects directly to an adapter card slot, featuring:
+ - Optional clock feedback paths, and optional high-speed voltage translation assistance
+ - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
+ - eMMC memory devices
+ - DSPI: Onboard support for three SPI flash memory devices
+ - 4 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - Two 4-pin serial ports at up to 115.2 Kbit/s
+ - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address End Address Description Size
+0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
+0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
+0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
+0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB
+0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
+0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - FPGA 4KB
+0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
+0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
+0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
+0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
+0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
+0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
+0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
+e) QSPI boot
diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c
new file mode 100644
index 0000000..4ea8b23
--- /dev/null
+++ b/board/freescale/ls1046aqds/ddr.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 3) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for %lu MT/s\n",
+ ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+ popts->data_bus_width = 0; /* 64b data bus */
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->bstopre = 0; /* enable auto precharge */
+
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x70;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ return fsl_ddr_sdram_size();
+#else
+ puts("Initializing DDR....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+#endif
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+ fsl_dp_ddr_restore();
+#endif
+
+ erratum_a008850_post();
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+ /*
+ * gd->arch.secure_ram tracks the location of secure memory.
+ * It was set as if the memory starts from 0.
+ * The address needs to add the offset of its bank.
+ */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+ gd->arch.secure_ram -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+ gd->arch.secure_ram;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+ }
+}
diff --git a/board/freescale/ls1046aqds/ddr.h b/board/freescale/ls1046aqds/ddr.h
new file mode 100644
index 0000000..b594032
--- /dev/null
+++ b/board/freescale/ls1046aqds/ddr.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+void erratum_a008850_post(void);
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2300, 0, 8, 9, 0x0A0C0D11, 0x1214150E,},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+#endif
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
new file mode 100644
index 0000000..046db11
--- /dev/null
+++ b/board/freescale/ls1046aqds/eth.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fdt_support.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <fsl_dtsec.h>
+#include <malloc.h>
+#include <asm/arch/fsl_serdes.h>
+
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "ls1046aqds_qixis.h"
+
+#define EMI_NONE 0xFF
+#define EMI1_RGMII1 0
+#define EMI1_RGMII2 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+#define EMI1_SLOT4 4
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+ "LS1046AQDS_MDIO_RGMII1",
+ "LS1046AQDS_MDIO_RGMII2",
+ "LS1046AQDS_MDIO_SLOT1",
+ "LS1046AQDS_MDIO_SLOT2",
+ "LS1046AQDS_MDIO_SLOT4",
+ "NULL",
+};
+
+/* Map SerDes 1 & 2 lanes to default slot. */
+static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
+
+static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name;
+
+ if (muxval > EMI1_SLOT4)
+ return NULL;
+
+ name = ls1046aqds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct ls1046aqds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void ls1046aqds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval < 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct ls1046aqds_mdio *priv = bus->priv;
+
+ ls1046aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls1046aqds_mdio *priv = bus->priv;
+
+ ls1046aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad,
+ regnum, value);
+}
+
+static int ls1046aqds_mdio_reset(struct mii_dev *bus)
+{
+ struct ls1046aqds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct ls1046aqds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate ls1046aqds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate ls1046aqds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = ls1046aqds_mdio_read;
+ bus->write = ls1046aqds_mdio_write;
+ bus->reset = ls1046aqds_mdio_reset;
+ sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ struct fixed_link f_link;
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ switch (port) {
+ case FM1_DTSEC9:
+ fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1");
+ break;
+ case FM1_DTSEC10:
+ fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2");
+ break;
+ case FM1_DTSEC5:
+ fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3");
+ break;
+ case FM1_DTSEC6:
+ fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4");
+ break;
+ case FM1_DTSEC2:
+ fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1");
+ break;
+ default:
+ break;
+ }
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+ /* 2.5G SGMII interface */
+ f_link.phy_id = cpu_to_fdt32(port);
+ f_link.duplex = cpu_to_fdt32(1);
+ f_link.link_speed = cpu_to_fdt32(1000);
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for 2.5G SGMII on QDS */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "sgmii-2500");
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+ switch (port) {
+ case FM1_DTSEC1:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4");
+ break;
+ case FM1_DTSEC5:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2");
+ break;
+ case FM1_DTSEC6:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1");
+ break;
+ case FM1_DTSEC10:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3");
+ break;
+ default:
+ break;
+ }
+ fdt_delprop(fdt, offset, "phy-connection-type");
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "qsgmii");
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
+ (port == FM1_10GEC1 || port == FM1_10GEC2)) {
+ /* XFI interface */
+ f_link.phy_id = cpu_to_fdt32(port);
+ f_link.duplex = cpu_to_fdt32(1);
+ f_link.link_speed = cpu_to_fdt32(10000);
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for XFI */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+ fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i;
+
+ for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT1:
+ fdt_status_okay_by_alias(fdt, "emi1_slot1");
+ break;
+ case EMI1_SLOT2:
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ break;
+ case EMI1_SLOT4:
+ fdt_status_okay_by_alias(fdt, "emi1_slot4");
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ int i, idx, lane, slot, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1, srds_s2;
+ u8 brdcfg12;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ srds_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
+ srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+ switch (srds_s1) {
+ case 0x3333:
+ /* SGMII on slot 1, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ case 0x1333:
+ case 0x2333:
+ /* SGMII on slot 1, MAC 10 */
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ case 0x1133:
+ case 0x2233:
+ /* SGMII on slot 1, MAC 5/6 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0x1040:
+ case 0x2040:
+ /* QSGMII on lane B, MAC 6/5/10/1 */
+ fm_info_set_phy_address(FM1_DTSEC6,
+ QSGMII_CARD_PORT1_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ QSGMII_CARD_PORT2_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC10,
+ QSGMII_CARD_PORT3_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC1,
+ QSGMII_CARD_PORT4_PHY_ADDR_S2);
+ break;
+ case 0x3363:
+ /* SGMII on slot 1, MAC 9/10 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ case 0x1163:
+ case 0x2263:
+ case 0x2223:
+ /* SGMII on slot 1, MAC 6 */
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ default:
+ printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
+ srds_s1);
+ break;
+ }
+
+ if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
+ /* SGMII on slot 4, MAC 2 */
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ if (i == FM1_DTSEC5) {
+ /* route lane 2 to slot1 so to have
+ * one sgmii riser card supports
+ * MAC5 and MAC6.
+ */
+ brdcfg12 = QIXIS_READ(brdcfg[12]);
+ QIXIS_WRITE(brdcfg[12],
+ brdcfg12 | 0x80);
+ }
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ } else {
+ /* clear the bit 7 to route lane B on slot2. */
+ brdcfg12 = QIXIS_READ(brdcfg[12]);
+ QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
+
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ QSGMII_FM1_A);
+ lane_to_slot[lane] = 2;
+ }
+
+ if (i == FM1_DTSEC2)
+ lane = 5;
+
+ if (lane < 0)
+ break;
+
+ slot = lane_to_slot[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC3)
+ mdio_mux[i] = EMI1_RGMII1;
+ else if (i == FM1_DTSEC4)
+ mdio_mux[i] = EMI1_RGMII2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
new file mode 100644
index 0000000..552365b
--- /dev/null
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <spl.h>
+
+#include "../common/vid.h"
+#include "../common/qixis.h"
+#include "ls1046aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ MUX_TYPE_GPIO,
+};
+
+int checkboard(void)
+{
+ char buf[64];
+#ifndef CONFIG_SD_BOOT
+ u8 sw;
+#endif
+
+ puts("Board: LS1046AQDS, boot from ");
+
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#else
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("PromJet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else if (sw == 0xF)
+ printf("QSPI\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
+ QIXIS_READ(id), QIXIS_READ(arch));
+
+ printf("FPGA: v%d (%s), build %d\n",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+
+ return 0;
+}
+
+bool if_board_diff_clk(void)
+{
+ u8 diff_conf = QIXIS_READ(brdcfg[11]);
+
+ return diff_conf & 0x40;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0f) {
+ case QIXIS_SYSCLK_64:
+ return 64000000;
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ if (if_board_diff_clk())
+ return get_board_sys_clk();
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+
+ return 66666666;
+}
+
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+ return gd->bus_clk;
+}
+#endif
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * When resuming from deep sleep, the I2C channel may not be
+ * in the default channel. So, switch to the default channel
+ * before accessing DDR SPD.
+ */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 usb_pwrfault;
+#endif
+#ifdef CONFIG_LPUART
+ u8 uart;
+#endif
+
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+ i2c_early_init_f();
+#endif
+ fsl_lsch2_early_init_f();
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+ out_be32(&scfg->rcwpmuxcr0, 0x3333);
+ out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+ usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED <<
+ SCFG_USBPWRFAULT_USB1_SHIFT);
+ out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+
+#ifdef CONFIG_LPUART
+ /* We use lpuart0 as system console */
+ uart = QIXIS_READ(brdcfg[14]);
+ uart &= ~CFG_UART_MUX_MASK;
+ uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+ QIXIS_WRITE(brdcfg[14], uart);
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+ return 1;
+
+ return 0;
+}
+#endif
+
+int config_board_mux(int ctrl_type)
+{
+ u8 reg14;
+
+ reg14 = QIXIS_READ(brdcfg[14]);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_GPIO:
+ reg14 = (reg14 & (~0x6)) | 0x2;
+ break;
+ default:
+ puts("Unsupported mux interface type\n");
+ return -1;
+ }
+
+ QIXIS_WRITE(brdcfg[14], reg14);
+
+ return 0;
+}
+
+int config_serdes_mux(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ if (hwconfig("gpio"))
+ config_board_mux(MUX_TYPE_GPIO);
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#ifdef CONFIG_SYS_FSL_SERDES
+ config_serdes_mux();
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+ u8 reg;
+
+ /* fixup DT for the two DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ reg = QIXIS_READ(brdcfg[0]);
+ reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ /* Disable IFC if QSPI is enabled */
+ if (reg == 0xF)
+ do_fixup_by_compat(blob, "fsl,ifc",
+ "status", "disabled", 8 + 1, 1);
+
+ return 0;
+}
+#endif
+
+u8 flash_read8(void *addr)
+{
+ return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+ u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+ __raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 val = __raw_readw(addr);
+
+ return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg b/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
new file mode 100644
index 0000000..5a6b7b8
--- /dev/null
+++ b/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
@@ -0,0 +1,17 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#Serdes SATA
+09eb1300 80104e20
+09eb08dc 00502880
+#flush PBI data
+096100c0 000fffff
diff --git a/board/freescale/ls1046aqds/ls1046aqds_qixis.h b/board/freescale/ls1046aqds/ls1046aqds_qixis.h
new file mode 100644
index 0000000..58ab132
--- /dev/null
+++ b/board/freescale/ls1046aqds/ls1046aqds_qixis.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1046AQDS_QIXIS_H__
+#define __LS1046AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1046AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xe0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+#define QIXIS_SYSCLK_64 0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100 0x0
+#define QIXIS_SDCLK1_125 0x1
+#define QIXIS_SDCLK1_165 0x2
+#define QIXIS_SDCLK1_100_SP 0x3
+
+#endif
diff --git a/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg b/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
new file mode 100644
index 0000000..b5fc08c
--- /dev/null
+++ b/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0c150010 0e000000 00000000 00000000
+11335559 40005012 e0116000 c1000000
+00000000 00000000 00000000 00038800
+00000000 01001101 00000096 00000001
diff --git a/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
new file mode 100644
index 0000000..59d24d6
--- /dev/null
+++ b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable IFC; disable QSPI
+0c150010 0e000000 00000000 00000000
+11335559 40005012 60040000 c1000000
+00000000 00000000 00000000 00038800
+00000000 01001101 00000096 00000001
diff --git a/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
new file mode 100644
index 0000000..9401a6f
--- /dev/null
+++ b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable QSPI; disable IFC
+0c150010 0e000000 00000000 00000000
+11335559 40005012 60040000 c1000000
+00000000 00000000 00000000 00038800
+20124000 01001101 00000096 00000001
diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig
new file mode 100644
index 0000000..a62255c
--- /dev/null
+++ b/board/freescale/ls1046ardb/Kconfig
@@ -0,0 +1,16 @@
+
+if TARGET_LS1046ARDB
+
+config SYS_BOARD
+ default "ls1046ardb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1046ardb"
+
+endif
diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS
new file mode 100644
index 0000000..ff42bef
--- /dev/null
+++ b/board/freescale/ls1046ardb/MAINTAINERS
@@ -0,0 +1,9 @@
+LS1046A BOARD
+M: Mingkai Hu <mingkai.hu@nxp.com>
+S: Maintained
+F: board/freescale/ls1046ardb/
+F: board/freescale/ls1046ardb/ls1046ardb.c
+F: include/configs/ls1046ardb.h
+F: configs/ls1046ardb_qspi_defconfig
+F: configs/ls1046ardb_sdcard_defconfig
+F: configs/ls1046ardb_emmc_defconfig
diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile
new file mode 100644
index 0000000..348eb76
--- /dev/null
+++ b/board/freescale/ls1046ardb/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2016 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpld.o
+obj-y += ddr.o
+obj-y += ls1046ardb.o
+obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
new file mode 100644
index 0000000..1ef7d47
--- /dev/null
+++ b/board/freescale/ls1046ardb/README
@@ -0,0 +1,76 @@
+Overview
+--------
+The LS1046A Reference Design Board (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1046A
+LayerScape Architecture processor. The LS1046ARDB provides SW development
+platform for the Freescale LS1046A processor series, with a complete
+debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
+
+LS1046A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
+SoC overview.
+
+ LS1046ARDB board Overview
+ -----------------------
+ - SERDES1 Connections, 4 lanes supporting:
+ - Lane0: XFI with x1 RJ45 connector
+ - Lane1: XFI Cage
+ - Lane2: SGMII.5
+ - Lane3: SGMII.6
+ - SERDES2 Connections, 4 lanes supporting:
+ - Lane0: PCIe1 with miniPCIe slot
+ - Lane1: PCIe2 with PCIe x2 slot
+ - Lane2: PCIe3 with PCIe x4 slot
+ - Lane3: SATA
+ - DDR Controller
+ - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
+ -IFC/Local Bus
+ - One 512 MB NAND flash with ECC support
+ - CPLD connection
+ - USB 3.0
+ - one Type A port, one Micro-AB port
+ - SDHC: connects directly to a full SD/MMC slot
+ - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+ - 4 I2C controllers
+ - UART
+ - Two 4-pin serial ports at up to 115.2 Kbit/s
+ - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address End Address Description Size
+0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
+0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
+0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
+0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
+0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
+0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
+0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
+0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
+0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
+0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
+0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
+0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
+
+QSPI flash map:
+Start Address End Address Description Size
+0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
+0x00_4010_0000 - 0x00_401F_FFFF U-Boot 1MB
+0x00_4020_0000 - 0x00_402F_FFFF U-Boot Env 1MB
+0x00_4030_0000 - 0x00_403F_FFFF FMan ucode 1MB
+0x00_4040_0000 - 0x00_404F_FFFF UEFI 1MB
+0x00_4050_0000 - 0x00_406F_FFFF PPA 2MB
+0x00_4070_0000 - 0x00_408F_FFFF Secure boot header
+ + bootscript 2MB
+0x00_4090_0000 - 0x00_40FF_FFFF Reserved 7MB
+0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
+
+Booting Options
+---------------
+a) QSPI boot
+b) SD boot
+c) eMMC boot
diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c
new file mode 100644
index 0000000..81a646e
--- /dev/null
+++ b/board/freescale/ls1046ardb/cpld.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Freescale LS1046ARDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+ u16 reg = CPLD_CFG_RCW_SRC_QSPI;
+ u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+ u8 reg7 = CPLD_READ(vbank);
+
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
+ CPLD_WRITE(vbank, reg7);
+
+ CPLD_WRITE(system_rst, 1);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+ u16 reg = CPLD_CFG_RCW_SRC_QSPI;
+ u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(vbank, 0);
+
+ CPLD_WRITE(system_rst, 1);
+}
+
+void cpld_set_sd(void)
+{
+ u16 reg = CPLD_CFG_RCW_SRC_SD;
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(system_rst, 1);
+}
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
+ printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
+ printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
+ printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
+ printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
+ printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
+ printf("vbank = %x\n", CPLD_READ(vbank));
+ printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
+ printf("uart_sel = %x\n", CPLD_READ(uart_sel));
+ printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
+ printf("rgmii_1588_sel = %x\n", CPLD_READ(rgmii_1588_sel));
+ printf("1588_clk_sel = %x\n", CPLD_READ(reg_1588_clk_sel));
+ printf("status_led = %x\n", CPLD_READ(status_led));
+ printf("sd_emmc = %x\n", CPLD_READ(sd_emmc));
+ printf("vdd_en = %x\n", CPLD_READ(vdd_en));
+ printf("vdd_sel = %x\n", CPLD_READ(vdd_sel));
+ putc('\n');
+}
+#endif
+
+void cpld_rev_bit(unsigned char *value)
+{
+ u8 rev_val, val;
+ int i;
+
+ val = *value;
+ rev_val = val & 1;
+ for (i = 1; i <= 7; i++) {
+ val >>= 1;
+ rev_val <<= 1;
+ rev_val |= val & 1;
+ }
+
+ *value = rev_val;
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else if (strcmp(argv[2], "sd") == 0)
+ cpld_set_sd();
+ else
+ cpld_set_defbank();
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else {
+ rc = cmd_usage(cmdtp);
+ }
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset: reset to default bank\n"
+ "cpld reset altbank: reset to alternate bank\n"
+ "cpld reset sd: reset to boot from SD card\n"
+#ifdef DEBUG
+ "cpld dump - display the CPLD registers\n"
+#endif
+);
diff --git a/board/freescale/ls1046ardb/cpld.h b/board/freescale/ls1046ardb/cpld.h
new file mode 100644
index 0000000..458da7e
--- /dev/null
+++ b/board/freescale/ls1046ardb/cpld.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CPLD_H__
+#define __CPLD_H__
+
+/*
+ * CPLD register set of LS1046ARDB board-specific.
+ * CPLD Revision: V2.1
+ */
+struct cpld_data {
+ u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
+ u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
+ u8 pcba_ver; /* 0x2 - PCBA Revision Register */
+ u8 system_rst; /* 0x3 - system reset register */
+ u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
+ u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */
+ u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */
+ u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */
+ u8 sysclk_sel; /* 0x8 - System clock POR Register */
+ u8 uart_sel; /* 0x9 - UART1 Connection Control Register */
+ u8 sd1refclk_sel; /* 0xA - */
+ u8 rgmii_1588_sel; /* 0xB - */
+ u8 reg_1588_clk_sel; /* 0xC - */
+ u8 status_led; /* 0xD - */
+ u8 global_rst; /* 0xE - */
+ u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */
+ u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */
+ u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */
+};
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+void cpld_rev_bit(unsigned char *value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value) \
+ cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_SW_MUX_BANK_SEL 0x40
+#define CPLD_BANK_SEL_MASK 0x07
+#define CPLD_BANK_SEL_ALTBANK 0x04
+#define CPLD_CFG_RCW_SRC_QSPI 0x044
+#define CPLD_CFG_RCW_SRC_SD 0x040
+#endif
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
new file mode 100644
index 0000000..dd3b5d0
--- /dev/null
+++ b/board/freescale/ls1046ardb/ddr.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for %lu MT/s\n",
+ ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+ popts->data_bus_width = 0; /* 64-bit data bus */
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->bstopre = 0; /* enable auto precharge */
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x70;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ return fsl_ddr_sdram_size();
+#else
+ puts("Initializing DDR....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+#endif
+
+ erratum_a008850_post();
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+ /*
+ * gd->arch.secure_ram tracks the location of secure memory.
+ * It was set as if the memory starts from 0.
+ * The address needs to add the offset of its bank.
+ */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+ gd->arch.secure_ram -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+ gd->arch.secure_ram;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+ }
+}
diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h
new file mode 100644
index 0000000..9e440f6
--- /dev/null
+++ b/board/freescale/ls1046ardb/ddr.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+void erratum_a008850_post(void);
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+#endif
diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
new file mode 100644
index 0000000..ac8bbec
--- /dev/null
+++ b/board/freescale/ls1046ardb/eth.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_dtsec.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ int i;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ u32 srds_s1;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+ /* Set the two on-board SGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
+
+ /* Set the on-board AQ PHY address */
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+
+ switch (srds_s1) {
+ case 0x1133:
+ break;
+ default:
+ printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
+ srds_s1);
+ break;
+ }
+
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
+ fm_info_set_mdio(i, dev);
+
+ /* XFI on lane A, MAC 9 */
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(FM1_10GEC1, dev);
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
new file mode 100644
index 0000000..585c807
--- /dev/null
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
+ u8 cfg_rcw_src1, cfg_rcw_src2;
+ u16 cfg_rcw_src;
+ u8 sd1refclk_sel;
+
+ puts("Board: LS1046ARDB, boot from ");
+
+ cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
+ cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
+ cpld_rev_bit(&cfg_rcw_src1);
+ cfg_rcw_src = cfg_rcw_src1;
+ cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
+
+ if (cfg_rcw_src == 0x44)
+ printf("QSPI vBank %d\n", CPLD_READ(vbank));
+ else if (cfg_rcw_src == 0x40)
+ puts("SD\n");
+ else
+ puts("Invalid setting of SW5\n");
+
+ printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
+ CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
+
+ puts("SERDES Reference Clocks:\n");
+ sd1refclk_sel = CPLD_READ(sd1refclk_sel);
+ printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+ ppa_init();
+#endif
+
+ /* invert AQR105 IRQ pins polarity */
+ out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
+
+ return 0;
+}
+
+void config_board_mux(void)
+{
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 usb_pwrfault;
+
+ /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
+ out_be32(&scfg->rcwpmuxcr0, 0x3300);
+ out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+ usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED <<
+ SCFG_USBPWRFAULT_USB1_SHIFT);
+ out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ config_board_mux();
+ return 0;
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ /* fixup DT for the two DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg b/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
new file mode 100644
index 0000000..5478217
--- /dev/null
+++ b/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
@@ -0,0 +1,22 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#Serdes SATA
+09eb1300 80104e20
+09eb08dc 00502880
+#PEX gen3 link
+09570158 00000300
+89400890 01048000
+89500890 01048000
+89600890 01048000
+#Alt base register
+09570158 00001000
+#flush PBI data
+096100c0 000fffff
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
new file mode 100644
index 0000000..6a5076e
--- /dev/null
+++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0c150010 0e000000 00000000 00000000
+11335559 40000012 60040000 c1000000
+00000000 00000000 00000000 00238800
+20124000 00003000 00000096 00000001
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
new file mode 100644
index 0000000..d5265b8
--- /dev/null
+++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0c150010 0e000000 00000000 00000000
+11335559 40005012 60040000 c1000000
+00000000 00000000 00000000 00238800
+20124000 00003101 00000096 00000001
diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
index c8dac99..de137ef 100644
--- a/board/freescale/ls2080a/MAINTAINERS
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: York Sun <york.sun@nxp.com>
+M: York Sun <york.sun@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/ls2080a/
F: include/configs/ls2080a_emu.h
diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
index 00337d7..4f9b9c8 100644
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -12,7 +12,6 @@
#include <asm/io.h>
#include <fdt_support.h>
#include <libfdt.h>
-#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <asm/arch/soc.h>
@@ -60,10 +59,6 @@
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_DEBUG_SERVER
- debug_server_init();
-#endif
-
return 0;
}
#endif
@@ -107,6 +102,11 @@
else
fdt_status_fail(fdt, offset);
}
+
+void board_quiesce_devices(void)
+{
+ fsl_mc_ldpaa_exit(gd->bd);
+}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
@@ -127,7 +127,6 @@
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
- fsl_mc_ldpaa_exit(bd);
#endif
return 0;
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 8f78b67..79877d7 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/ls2080aqds/
F: board/freescale/ls2080a/ls2080aqds.c
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index f288750..2808bd5 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -2,14 +2,14 @@
--------
The LS2080A Development System (QDS) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS2080A
-Layerscape Architecture processor. The LS2080AQDS provides validation and
-SW development platform for the Freescale LS2080A processor series, with
-a complete debugging environment.
+and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
+validation and SW development platform for the Freescale LS2080A, LS2088A
+processor series, with a complete debugging environment.
-LS2080A SoC Overview
+LS2080A, LS2088A SoC Overview
--------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
LS2080AQDS board Overview
-----------------------
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 95ff68b..59361e9 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -64,7 +64,7 @@
};
/* Slot2 does not have EMI connections */
-#define EMI_NONE 0xFFFFFFFF
+#define EMI_NONE 0xFF
#define EMI1_SLOT1 0
#define EMI1_SLOT2 1
#define EMI1_SLOT3 2
@@ -144,8 +144,10 @@
mdelay(10);
- if ((value & 0xfff) == 0x40f) {
+ if ((value & 0xfff) == 0x401) {
printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
+ miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
+ 0x1f, 0);
continue;
}
@@ -181,28 +183,29 @@
if (ret > 0)
goto error;
- mdelay(1);
+ mdelay(100);
ret = miiphy_read(dev[mii_bus],
riser_phy_addr[dpmac],
0x11, &value);
if (ret > 0)
goto error;
- mdelay(10);
- if ((value & 0xfff) == 0x40f) {
+ if ((value & 0xfff) == 0x401) {
printf("DPMAC %d :PHY is configured ",
dpmac_id);
printf("after setting repeater 0x%x\n",
value);
i = 5;
j = 5;
- } else
+ } else {
printf("DPMAC %d :PHY is failed to ",
dpmac_id);
printf("configure the repeater 0x%x\n",
value);
}
+ }
}
+ miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
}
error:
if (ret)
@@ -470,7 +473,49 @@
}
break;
+ case 0x39:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm1[0] = EMI1_SLOT3;
+ lane_to_slot_fsm1[1] = EMI1_SLOT3;
+ lane_to_slot_fsm1[2] = EMI1_SLOT3;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ } else {
+ lane_to_slot_fsm1[0] = EMI_NONE;
+ lane_to_slot_fsm1[1] = EMI_NONE;
+ lane_to_slot_fsm1[2] = EMI_NONE;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ }
+ lane_to_slot_fsm1[4] = EMI1_SLOT3;
+ lane_to_slot_fsm1[5] = EMI1_SLOT3;
+ lane_to_slot_fsm1[6] = EMI1_SLOT3;
+ lane_to_slot_fsm1[7] = EMI_NONE;
+ break;
+
+ case 0x4D:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm1[0] = EMI1_SLOT3;
+ lane_to_slot_fsm1[1] = EMI1_SLOT3;
+ lane_to_slot_fsm1[2] = EMI_NONE;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ } else {
+ lane_to_slot_fsm1[0] = EMI_NONE;
+ lane_to_slot_fsm1[1] = EMI_NONE;
+ lane_to_slot_fsm1[2] = EMI_NONE;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ }
+ lane_to_slot_fsm1[4] = EMI1_SLOT3;
+ lane_to_slot_fsm1[5] = EMI1_SLOT3;
+ lane_to_slot_fsm1[6] = EMI_NONE;
+ lane_to_slot_fsm1[7] = EMI_NONE;
+ break;
+
case 0x2A:
+ case 0x4B:
+ case 0x4C:
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
break;
@@ -505,6 +550,38 @@
lane_to_slot_fsm2[7] = EMI1_SLOT6;
}
break;
+
+ case 0x47:
+ printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ lane_to_slot_fsm2[0] = EMI_NONE;
+ lane_to_slot_fsm2[1] = EMI1_SLOT5;
+ lane_to_slot_fsm2[2] = EMI1_SLOT5;
+ lane_to_slot_fsm2[3] = EMI1_SLOT5;
+
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm2[4] = EMI_NONE;
+ lane_to_slot_fsm2[5] = EMI1_SLOT5;
+ lane_to_slot_fsm2[6] = EMI1_SLOT5;
+ lane_to_slot_fsm2[7] = EMI1_SLOT5;
+ }
+ break;
+
+ case 0x57:
+ printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm2[0] = EMI_NONE;
+ lane_to_slot_fsm2[1] = EMI_NONE;
+ lane_to_slot_fsm2[2] = EMI_NONE;
+ lane_to_slot_fsm2[3] = EMI_NONE;
+ }
+ lane_to_slot_fsm2[4] = EMI_NONE;
+ lane_to_slot_fsm2[5] = EMI_NONE;
+ lane_to_slot_fsm2[6] = EMI1_SLOT5;
+ lane_to_slot_fsm2[7] = EMI1_SLOT5;
+ break;
+
default:
printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
__func__ , serdes2_prtcl);
@@ -537,8 +614,10 @@
switch (serdes1_prtcl) {
case 0x07:
+ case 0x39:
+ case 0x4D:
+ lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
- lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
slot = lane_to_slot_fsm1[lane];
switch (++slot) {
@@ -559,6 +638,26 @@
wriop_set_mdio(dpmac_id, bus);
break;
case 3:
+ if (slot == EMI_NONE)
+ return;
+ if (serdes1_prtcl == 0x39) {
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 2]);
+ if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
+ env_hwconfig))
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 3]);
+ } else {
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 2]);
+ if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
+ env_hwconfig))
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 3]);
+ }
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
+ bus = mii_dev_for_muxval(EMI1_SLOT3);
+ wriop_set_mdio(dpmac_id, bus);
break;
case 4:
break;
@@ -579,6 +678,8 @@
case 0x07:
case 0x08:
case 0x49:
+ case 0x47:
+ case 0x57:
lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
(dpmac_id - 9));
slot = lane_to_slot_fsm2[lane];
@@ -597,7 +698,23 @@
wriop_set_mdio(dpmac_id, bus);
break;
case 5:
- break;
+ if (slot == EMI_NONE)
+ return;
+ if (serdes2_prtcl == 0x47) {
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 10]);
+ if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
+ env_hwconfig))
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 11]);
+ } else {
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 11]);
+ }
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
+ bus = mii_dev_for_muxval(EMI1_SLOT5);
+ wriop_set_mdio(dpmac_id, bus);
+ break;
case 6:
/* Slot housing a SGMII riser card? */
wriop_set_phy_address(dpmac_id,
@@ -691,6 +808,8 @@
switch (serdes1_prtcl) {
case 0x2A:
+ case 0x4B:
+ case 0x4C:
/*
* XFI does not need a PHY to work, but to avoid U-Boot use
* default PHY address which is zero to a MAC when it found
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 7d95deb..73a61fd 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -12,7 +12,6 @@
#include <asm/io.h>
#include <fdt_support.h>
#include <libfdt.h>
-#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <i2c.h>
@@ -265,9 +264,6 @@
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_DEBUG_SERVER
- debug_server_init();
-#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
@@ -296,14 +292,16 @@
else
fdt_status_fail(fdt, offset);
}
+
+void board_quiesce_devices(void)
+{
+ fsl_mc_ldpaa_exit(gd->bd);
+}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
-#ifdef CONFIG_FSL_MC_ENET
- int err;
-#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
@@ -317,13 +315,10 @@
fdt_fixup_memory_banks(blob, base, size, 2);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
- err = fsl_mc_ldpaa_exit(bd);
- if (err)
- return err;
#endif
return 0;
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index a20c003..759a146 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/ls2080ardb/
F: board/freescale/ls2080a/ls2080ardb.c
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index b1613ba..0c9c574 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -1,13 +1,13 @@
Overview
--------
The LS2080A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2080A
+evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
Layerscape Architecture processor.
-LS2080A SoC Overview
+LS2080A, LS2088A SoC Overview
--------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
LS2080ARDB board Overview
-----------------------
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index ecd1e71..959dfeb 100644
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -134,6 +134,9 @@
/* Enable ZQ calibration */
popts->zq_en = 1;
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x6e;
+
if (ddr_freq < 2350) {
if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
/* four chip-selects */
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index a65cd4ab..02954ef 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -13,9 +13,9 @@
#include <hwconfig.h>
#include <fdt_support.h>
#include <libfdt.h>
-#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
+#include <efi_loader.h>
#include <i2c.h>
#include <asm/arch/soc.h>
#include <fsl_sec.h>
@@ -202,6 +202,14 @@
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
+#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+ if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
+ efi_add_memory_map(gd->bd->bi_dram[2].start,
+ gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT,
+ EFI_RESERVED_MEMORY_TYPE, false);
+ }
+#endif
+
return 0;
}
@@ -229,9 +237,6 @@
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_DEBUG_SERVER
- debug_server_init();
-#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
@@ -260,14 +265,16 @@
else
fdt_status_fail(fdt, offset);
}
+
+void board_quiesce_devices(void)
+{
+ fsl_mc_ldpaa_exit(gd->bd);
+}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
-#ifdef CONFIG_FSL_MC_ENET
- int err;
-#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
@@ -281,13 +288,10 @@
fdt_fixup_memory_banks(blob, base, size, 2);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
- err = fsl_mc_ldpaa_exit(bd);
- if (err)
- return err;
#endif
return 0;
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
index 93e1c50..b4a0dd5 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -164,7 +164,7 @@
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
return 0;
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index ed611c5..3cec09b 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -194,7 +194,7 @@
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
fdt_tsec1_fixup(blob, bd);
return 0;
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 572913c..045841d 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -332,7 +332,7 @@
{
ft_cpu_setup(blob, bd);
ft_tsec_fixup(blob, bd);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 565f815..07c0599 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -210,7 +210,7 @@
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
return 0;
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 7b0f461..cede1da 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -282,7 +282,7 @@
#endif
#ifdef CONFIG_HAS_FSL_MPH_USB
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
return 0;
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index 12467a9..fb0ab77 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 2ea5346..df25be8 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -9,7 +9,7 @@
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx51.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index 8ba2728..a6e46b9 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -11,7 +11,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <netdev.h>
#include <mmc.h>
#include <fsl_esdhc.h>
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index 6ee6d73..db28942 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -11,7 +11,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/imx-common/boot_mode.h>
#include <netdev.h>
#include <i2c.h>
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index 1298788..9e1072f 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -13,7 +13,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/imx-common/mx5_video.h>
#include <netdev.h>
#include <i2c.h>
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index 0963fd7..938c611 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -11,7 +11,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <netdev.h>
#include <mmc.h>
#include <fsl_esdhc.h>
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index 5aae721..7f8eca3 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/clock.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <mmc.h>
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index a3ed4cd..51bbbc4 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -12,7 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
@@ -231,6 +231,33 @@
set_chipselect_size(CS0_128);
}
+static void eim_clk_setup(void)
+{
+ struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int cscmr1, ccgr6;
+
+
+ /* Turn off EIM clock */
+ ccgr6 = readl(&imx_ccm->CCGR6);
+ ccgr6 &= ~(0x3 << 10);
+ writel(ccgr6, &imx_ccm->CCGR6);
+
+ /*
+ * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
+ * and aclk_eim_slow_podf = 01 --> divide by 2
+ * so that we can have EIM at the maximum clock of 132MHz
+ */
+ cscmr1 = readl(&imx_ccm->cscmr1);
+ cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
+ MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
+ cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
+ writel(cscmr1, &imx_ccm->cscmr1);
+
+ /* Turn on EIM clock */
+ ccgr6 |= (0x3 << 10);
+ writel(ccgr6, &imx_ccm->CCGR6);
+}
+
static void setup_iomux_eimnor(void)
{
imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
@@ -519,6 +546,7 @@
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
+ eim_clk_setup();
return 0;
}
diff --git a/board/freescale/mx6sabresd/README b/board/freescale/mx6sabresd/README
new file mode 100644
index 0000000..5814b9d
--- /dev/null
+++ b/board/freescale/mx6sabresd/README
@@ -0,0 +1,103 @@
+How to use and build U-Boot on mx6sabresd:
+----------------------------------
+
+Currently there are three methods for booting mx6sabresd boards:
+
+1. Booting via Normal U-Boot (u-boot.imx)
+
+2. Booting via SPL (SPL and u-boot.img)
+
+3. Booting via Falcon mode (SPL launches the kernel directly)
+
+
+1. Booting via Normal U-Boot
+----------------------------
+
+$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd)
+
+or
+
+$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd)
+
+$ make
+
+This will generate the image called u-boot.imx.
+
+- Flash the u-boot.imx binary into the SD card:
+
+$ sudo dd if=u-boot.imx of=/dev/sdb bs=1K seek=1 && sync
+
+
+2. Booting via SPL
+------------------
+
+Other method for building U-Boot on mx6qsabresd and mx6qpsabresd is
+through SPL. In order to do so:
+
+$ make mx6sabresd_spl_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
+
+- Flash the u-boot.img image into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 && sync
+
+
+3. Booting via Falcon mode
+--------------------------
+
+$ make mx6sabresd_spl_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 oflag=sync status=none && sync
+
+- Flash the u-boot.img image into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 oflag=sync status=none && sync
+
+Create a partition for root file system and extract it there:
+
+$ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Setup the IP server:
+
+# setenv serverip <server_ip_address>
+
+- Download dtb file:
+
+# dhcp ${fdt_addr} imx6q-sabresd.dtb
+
+- Download kernel image:
+
+# dhcp ${loadaddr} uImage
+
+- Write kernel at 2MB offset:
+
+# mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs:
+
+# setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args:
+
+# spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
+
+# mmc write 18000000 0x800 0x800
+
+- Press KEY_VOL_UP key, power up the board and then SPL binary will
+launch the kernel directly.
diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
index f35f22e..be9f87f 100644
--- a/board/freescale/mx6sabresd/mx6dlsabresd.cfg
+++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index f836ecb..80a7789 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -10,7 +10,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
@@ -57,6 +57,8 @@
#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
+#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
+
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -360,6 +362,39 @@
}
#endif
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ ar8031_phy_fixup(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
#if defined(CONFIG_VIDEO_IPUV3)
static void disable_lvds(struct display_info_t const *dev)
{
@@ -682,124 +717,15 @@
#include <spl.h>
#include <libfdt.h>
-const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_sdclk_0 = 0x00020030,
- .dram_sdclk_1 = 0x00020030,
- .dram_cas = 0x00020030,
- .dram_ras = 0x00020030,
- .dram_reset = 0x00020030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
- .dram_dqm0 = 0x00020030,
- .dram_dqm1 = 0x00020030,
- .dram_dqm2 = 0x00020030,
- .dram_dqm3 = 0x00020030,
- .dram_dqm4 = 0x00020030,
- .dram_dqm5 = 0x00020030,
- .dram_dqm6 = 0x00020030,
- .dram_dqm7 = 0x00020030,
-};
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ gpio_direction_input(KEY_VOL_UP);
-const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {
- .dram_sdclk_0 = 0x00000030,
- .dram_sdclk_1 = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_reset = 0x00000030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
- .dram_dqm0 = 0x00000030,
- .dram_dqm1 = 0x00000030,
- .dram_dqm2 = 0x00000030,
- .dram_dqm3 = 0x00000030,
- .dram_dqm4 = 0x00000030,
- .dram_dqm5 = 0x00000030,
- .dram_dqm6 = 0x00000030,
- .dram_dqm7 = 0x00000030,
-};
-
-const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
- .grp_ddr_type = 0x000C0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_b2ds = 0x00000030,
- .grp_b3ds = 0x00000030,
- .grp_b4ds = 0x00000030,
- .grp_b5ds = 0x00000030,
- .grp_b6ds = 0x00000030,
- .grp_b7ds = 0x00000030,
-};
-
-const struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x001F001F,
- .p0_mpwldectrl1 = 0x001F001F,
- .p1_mpwldectrl0 = 0x00440044,
- .p1_mpwldectrl1 = 0x00440044,
- .p0_mpdgctrl0 = 0x434B0350,
- .p0_mpdgctrl1 = 0x034C0359,
- .p1_mpdgctrl0 = 0x434B0350,
- .p1_mpdgctrl1 = 0x03650348,
- .p0_mprddlctl = 0x4436383B,
- .p1_mprddlctl = 0x39393341,
- .p0_mpwrdlctl = 0x35373933,
- .p1_mpwrdlctl = 0x48254A36,
-};
-
-const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {
- .p0_mpwldectrl0 = 0x001B001E,
- .p0_mpwldectrl1 = 0x002E0029,
- .p1_mpwldectrl0 = 0x001B002A,
- .p1_mpwldectrl1 = 0x0019002C,
- .p0_mpdgctrl0 = 0x43240334,
- .p0_mpdgctrl1 = 0x0324031A,
- .p1_mpdgctrl0 = 0x43340344,
- .p1_mpdgctrl1 = 0x03280276,
- .p0_mprddlctl = 0x44383A3E,
- .p1_mprddlctl = 0x3C3C3846,
- .p0_mpwrdlctl = 0x2E303230,
- .p1_mpwrdlctl = 0x38283E34,
-};
-
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 1600,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
+ /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
+ return gpio_get_value(KEY_VOL_UP);
+}
+#endif
static void ccgr_init(void)
{
@@ -831,44 +757,209 @@
}
}
-/*
- * This section requires the differentiation between iMX6 Sabre boards, but
- * for now, it will configure only for the mx6q variant.
- */
+static int mx6q_dcd_table[] = {
+ 0x020e0798, 0x000C0000,
+ 0x020e0758, 0x00000000,
+ 0x020e0588, 0x00000030,
+ 0x020e0594, 0x00000030,
+ 0x020e056c, 0x00000030,
+ 0x020e0578, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e057c, 0x00000030,
+ 0x020e058c, 0x00000000,
+ 0x020e059c, 0x00000030,
+ 0x020e05a0, 0x00000030,
+ 0x020e078c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e05a8, 0x00000030,
+ 0x020e05b0, 0x00000030,
+ 0x020e0524, 0x00000030,
+ 0x020e051c, 0x00000030,
+ 0x020e0518, 0x00000030,
+ 0x020e050c, 0x00000030,
+ 0x020e05b8, 0x00000030,
+ 0x020e05c0, 0x00000030,
+ 0x020e0774, 0x00020000,
+ 0x020e0784, 0x00000030,
+ 0x020e0788, 0x00000030,
+ 0x020e0794, 0x00000030,
+ 0x020e079c, 0x00000030,
+ 0x020e07a0, 0x00000030,
+ 0x020e07a4, 0x00000030,
+ 0x020e07a8, 0x00000030,
+ 0x020e0748, 0x00000030,
+ 0x020e05ac, 0x00000030,
+ 0x020e05b4, 0x00000030,
+ 0x020e0528, 0x00000030,
+ 0x020e0520, 0x00000030,
+ 0x020e0514, 0x00000030,
+ 0x020e0510, 0x00000030,
+ 0x020e05bc, 0x00000030,
+ 0x020e05c4, 0x00000030,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001F001F,
+ 0x021b0810, 0x001F001F,
+ 0x021b480c, 0x001F001F,
+ 0x021b4810, 0x001F001F,
+ 0x021b083c, 0x43270338,
+ 0x021b0840, 0x03200314,
+ 0x021b483c, 0x431A032F,
+ 0x021b4840, 0x03200263,
+ 0x021b0848, 0x4B434748,
+ 0x021b4848, 0x4445404C,
+ 0x021b0850, 0x38444542,
+ 0x021b4850, 0x4935493A,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020036,
+ 0x021b0008, 0x09444040,
+ 0x021b000c, 0x555A7975,
+ 0x021b0010, 0xFF538F64,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x005A1023,
+ 0x021b0040, 0x00000027,
+ 0x021b0000, 0x831A0000,
+ 0x021b001c, 0x04088032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x09408030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025576,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+};
+
+static int mx6qp_dcd_table[] = {
+ 0x020e0798, 0x000c0000,
+ 0x020e0758, 0x00000000,
+ 0x020e0588, 0x00000030,
+ 0x020e0594, 0x00000030,
+ 0x020e056c, 0x00000030,
+ 0x020e0578, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e057c, 0x00000030,
+ 0x020e058c, 0x00000000,
+ 0x020e059c, 0x00000030,
+ 0x020e05a0, 0x00000030,
+ 0x020e078c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e05a8, 0x00000030,
+ 0x020e05b0, 0x00000030,
+ 0x020e0524, 0x00000030,
+ 0x020e051c, 0x00000030,
+ 0x020e0518, 0x00000030,
+ 0x020e050c, 0x00000030,
+ 0x020e05b8, 0x00000030,
+ 0x020e05c0, 0x00000030,
+ 0x020e0774, 0x00020000,
+ 0x020e0784, 0x00000030,
+ 0x020e0788, 0x00000030,
+ 0x020e0794, 0x00000030,
+ 0x020e079c, 0x00000030,
+ 0x020e07a0, 0x00000030,
+ 0x020e07a4, 0x00000030,
+ 0x020e07a8, 0x00000030,
+ 0x020e0748, 0x00000030,
+ 0x020e05ac, 0x00000030,
+ 0x020e05b4, 0x00000030,
+ 0x020e0528, 0x00000030,
+ 0x020e0520, 0x00000030,
+ 0x020e0514, 0x00000030,
+ 0x020e0510, 0x00000030,
+ 0x020e05bc, 0x00000030,
+ 0x020e05c4, 0x00000030,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001b001e,
+ 0x021b0810, 0x002e0029,
+ 0x021b480c, 0x001b002a,
+ 0x021b4810, 0x0019002c,
+ 0x021b083c, 0x43240334,
+ 0x021b0840, 0x0324031a,
+ 0x021b483c, 0x43340344,
+ 0x021b4840, 0x03280276,
+ 0x021b0848, 0x44383A3E,
+ 0x021b4848, 0x3C3C3846,
+ 0x021b0850, 0x2e303230,
+ 0x021b4850, 0x38283E34,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08c0, 0x24912249,
+ 0x021b48c0, 0x24914289,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020036,
+ 0x021b0008, 0x24444040,
+ 0x021b000c, 0x555A7955,
+ 0x021b0010, 0xFF320F64,
+ 0x021b0014, 0x01ff00db,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x005A1023,
+ 0x021b0040, 0x00000027,
+ 0x021b0400, 0x14420000,
+ 0x021b0000, 0x831A0000,
+ 0x021b0890, 0x00400C58,
+ 0x00bb0008, 0x00000000,
+ 0x00bb000c, 0x2891E41A,
+ 0x00bb0038, 0x00000564,
+ 0x00bb0014, 0x00000040,
+ 0x00bb0028, 0x00000020,
+ 0x00bb002c, 0x00000020,
+ 0x021b001c, 0x04088032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x09408030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025576,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+};
+
+static void ddr_init(int *table, int size)
+{
+ int i;
+
+ for (i = 0; i < size / 2 ; i++)
+ writel(table[2 * i + 1], table[2 * i]);
+}
+
static void spl_dram_init(void)
{
- struct mx6_ddr_sysinfo sysinfo = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = 2,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
- /* single chip select */
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
- .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
- };
-
- if (is_mx6dqp()) {
- mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
- } else {
- mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
- }
+ if (is_mx6dq())
+ ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+ else if (is_mx6dqp())
+ ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
}
void board_init_f(ulong dummy)
{
+ /* DDR initialization */
+ spl_dram_init();
+
/* setup AIPS and disable watchdog */
arch_cpu_init();
@@ -884,9 +975,6 @@
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
- /* DDR initialization */
- spl_dram_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg
index c77bbde..024de9c 100644
--- a/board/freescale/mx6slevk/imximage.cfg
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig
new file mode 100644
index 0000000..4ba9bbf
--- /dev/null
+++ b/board/freescale/mx6sllevk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SLLEVK
+
+config SYS_BOARD
+ default "mx6sllevk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx6sllevk"
+
+endif
diff --git a/board/freescale/mx6sllevk/MAINTAINERS b/board/freescale/mx6sllevk/MAINTAINERS
new file mode 100644
index 0000000..b82273c
--- /dev/null
+++ b/board/freescale/mx6sllevk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6SLLEVK BOARD
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/mx6sllevk/
+F: include/configs/mx6sllevk.h
+F: configs/mx6sllevk_defconfig
+F: configs/mx6sllevk_plugin_defconfig
diff --git a/board/freescale/mx6sllevk/Makefile b/board/freescale/mx6sllevk/Makefile
new file mode 100644
index 0000000..667fcb0
--- /dev/null
+++ b/board/freescale/mx6sllevk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6sllevk.o
diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg
new file mode 100644
index 0000000..7d8b323
--- /dev/null
+++ b/board/freescale/mx6sllevk/imximage.cfg
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sllevk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E052C 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x3F393B3C
+DATA 4 0x021B0850 0x262C3826
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100B22
+DATA 4 0x021B0038 0x00170778
+DATA 4 0x021B0014 0x00C700DB
+DATA 4 0x021B0018 0x00201718
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0xC4190000
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B001C 0x00008050
+DATA 4 0x021B001C 0x00008058
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x83018030
+DATA 4 0x021B001C 0x83018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c
new file mode 100644
index 0000000..74a27a3
--- /dev/null
+++ b/board/freescale/mx6sllevk/mx6sllevk.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_DM_PMIC_PFUZE100
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+ u32 dev_id, rev_id, i;
+ u32 switch_num = 6;
+ u32 offset = PFUZE100_SW1CMODE;
+
+ ret = pmic_get("pfuze100", &dev);
+ if (ret == -ENODEV)
+ return 0;
+
+ if (ret != 0)
+ return ret;
+
+ dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+ printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+
+ /* Init mode to APS_PFM */
+ pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+ for (i = 0; i < switch_num - 1; i++)
+ pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+ /* set SW1AB staby volatage 0.975V */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+ /* set SW1C staby volatage 0.975V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6SLL EVK\n");
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+ return devno;
+}
diff --git a/board/freescale/mx6sllevk/plugin.S b/board/freescale/mx6sllevk/plugin.S
new file mode 100644
index 0000000..f9ef35a
--- /dev/null
+++ b/board/freescale/mx6sllevk/plugin.S
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sll_evk_ddr_setting
+ ldr r0, =IOMUXC_BASE_ADDR
+ ldr r1, =0x00080000
+ str r1, [r0, #0x550]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x534]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x2AC]
+ str r1, [r0, #0x548]
+ str r1, [r0, #0x52C]
+ ldr r1, =0x00020000
+ str r1, [r0, #0x530]
+ ldr r1, =0x00003030
+ str r1, [r0, #0x2B0]
+ str r1, [r0, #0x2B4]
+ str r1, [r0, #0x2B8]
+ str r1, [r0, #0x2BC]
+
+ ldr r1, =0x00020000
+ str r1, [r0, #0x540]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x544]
+ str r1, [r0, #0x54C]
+ str r1, [r0, #0x554]
+ str r1, [r0, #0x558]
+ str r1, [r0, #0x294]
+ str r1, [r0, #0x298]
+ str r1, [r0, #0x29C]
+ str r1, [r0, #0x2A0]
+
+ ldr r1, =0x00082030
+ str r1, [r0, #0x2C0]
+
+ ldr r0, =MMDC_P0_BASE_ADDR
+ ldr r1, =0x00008000
+ str r1, [r0, #0x1C]
+ ldr r1, =0xA1390003
+ str r1, [r0, #0x800]
+ ldr r1, =0x084700C7
+ str r1, [r0, #0x85C]
+ ldr r1, =0x00400000
+ str r1, [r0, #0x890]
+
+ ldr r1, =0x3F393B3C
+ str r1, [r0, #0x848]
+ ldr r1, =0x262C3826
+ str r1, [r0, #0x850]
+
+ ldr r1, =0x33333333
+ str r1, [r0, #0x81C]
+ str r1, [r0, #0x820]
+ str r1, [r0, #0x824]
+ str r1, [r0, #0x828]
+
+ ldr r1, =0xf3333333
+ str r1, [r0, #0x82C]
+ str r1, [r0, #0x830]
+ str r1, [r0, #0x834]
+ str r1, [r0, #0x838]
+
+ ldr r1, =0x24922492
+ str r1, [r0, #0x8C0]
+ ldr r1, =0x00000800
+ str r1, [r0, #0x8B8]
+
+ ldr r1, =0x00020052
+ str r1, [r0, #0x004]
+ ldr r1, =0x53574333
+ str r1, [r0, #0x00C]
+ ldr r1, =0x00100B22
+ str r1, [r0, #0x010]
+ ldr r1, =0x00170778
+ str r1, [r0, #0x038]
+ ldr r1, =0x00C700DB
+ str r1, [r0, #0x014]
+ ldr r1, =0x00201718
+ str r1, [r0, #0x018]
+ ldr r1, =0x0F9F26D2
+ str r1, [r0, #0x02C]
+ ldr r1, =0x009F0E10
+ str r1, [r0, #0x030]
+ ldr r1, =0x0000005F
+ str r1, [r0, #0x040]
+ ldr r1, =0xC4190000
+ str r1, [r0, #0x000]
+ ldr r1, =0x20000000
+ str r1, [r0, #0x83C]
+
+ ldr r1, =0x00008050
+ str r1, [r0, #0x01C]
+ ldr r1, =0x00008058
+ str r1, [r0, #0x01C]
+ ldr r1, =0x003F8030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x003F8038
+ str r1, [r0, #0x01C]
+ ldr r1, =0xFF0A8030
+ str r1, [r0, #0x01C]
+ ldr r1, =0xFF0A8038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x04028030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x04028038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x83018030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x83018038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x01038030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x01038038
+ str r1, [r0, #0x01C]
+
+ ldr r1, =0x00001800
+ str r1, [r0, #0x020]
+ ldr r1, =0xA1390003
+ str r1, [r0, #0x800]
+ ldr r1, =0x00020052
+ str r1, [r0, #0x004]
+ ldr r1, =0x00011006
+ str r1, [r0, #0x404]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0xffffffff
+ str r1, [r0, #0x068]
+ str r1, [r0, #0x06c]
+ str r1, [r0, #0x070]
+ str r1, [r0, #0x074]
+ str r1, [r0, #0x078]
+ str r1, [r0, #0x07c]
+ str r1, [r0, #0x080]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+ imx6sll_evk_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 965e511..0460cd9 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -504,7 +504,7 @@
static int setup_lcd(void)
{
- enable_lcdif_clock(LCDIF1_BASE_ADDR);
+ enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 399bad2..b28ce10 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -600,7 +600,7 @@
static int setup_lcd(void)
{
- enable_lcdif_clock(LCDIF1_BASE_ADDR);
+ enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig
new file mode 100644
index 0000000..7eec497
--- /dev/null
+++ b/board/freescale/mx6ullevk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6ULL_14X14_EVK
+
+config SYS_BOARD
+ default "mx6ullevk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx6ullevk"
+
+endif
diff --git a/board/freescale/mx6ullevk/MAINTAINERS b/board/freescale/mx6ullevk/MAINTAINERS
new file mode 100644
index 0000000..73031cd
--- /dev/null
+++ b/board/freescale/mx6ullevk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6ULLEVK BOARD
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/mx6ullevk/
+F: include/configs/mx6ullevk.h
+F: configs/mx6ull_14x14_evk_defconfig
+F: configs/mx6ull_14x14_evk_plugin_defconfig
diff --git a/board/freescale/mx6ullevk/Makefile b/board/freescale/mx6ullevk/Makefile
new file mode 100644
index 0000000..c64fba4
--- /dev/null
+++ b/board/freescale/mx6ullevk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6ullevk.o
diff --git a/board/freescale/mx6ullevk/README b/board/freescale/mx6ullevk/README
new file mode 100644
index 0000000..d5c8770
--- /dev/null
+++ b/board/freescale/mx6ullevk/README
@@ -0,0 +1,36 @@
+How to use U-Boot on Freescale MX6ULL 14x14 EVK
+----------------------------------------------
+
+- First make sure you have installed the dtc package (device tree compiler):
+
+$ sudo apt-get install device-tree-compiler
+
+- Build U-Boot for MX6ULL 14x14 EVK:
+
+$ make mrproper
+$ make mx6ull_14x14_evk_defconfig
+$ make
+
+This generates the u-boot-dtb.imx image in the current directory.
+
+- Flash the u-boot-dtb.imx image into the micro SD card:
+
+$ sudo dd if=u-boot-dtb.imx of=/dev/sdb bs=1K seek=1 && sync
+
+- Jumper settings:
+
+SW601: 0 0 1 0
+Sw602: 1 0
+
+Where 0 means bottom position and 1 means top position (from the switch label
+numbers reference).
+
+Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the push buttons)
+
+Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
+
+The link for the board: http://www.nxp.com/products/microcontrollers-and- \
+processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/ \
+i.mx6qp/evaluation-kit-for-the-i.mx-6ull-applications-processor:MCIMX6ULL-EVK
diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg
new file mode 100644
index 0000000..80cb038
--- /dev/null
+++ b/board/freescale/mx6ullevk/imximage.cfg
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM nor
+#else
+BOOT_FROM sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x000C0030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000004
+DATA 4 0x021B083C 0x41640158
+DATA 4 0x021B0848 0x40403237
+DATA 4 0x021B0850 0x40403C33
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00944009
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
new file mode 100644
index 0000000..489bf21
--- /dev/null
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+ return devno;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "EVK");
+ setenv("board_rev", "14X14");
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6ULL 14x14 EVK\n");
+
+ return 0;
+}
diff --git a/board/freescale/mx6ullevk/plugin.S b/board/freescale/mx6ullevk/plugin.S
new file mode 100644
index 0000000..65a3c45
--- /dev/null
+++ b/board/freescale/mx6ullevk/plugin.S
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6ull_ddr3_evk_setting
+ ldr r0, =IOMUXC_BASE_ADDR
+ ldr r1, =0x000C0000
+ str r1, [r0, #0x4B4]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x4AC]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x27C]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x250]
+ str r1, [r0, #0x24C]
+ str r1, [r0, #0x490]
+ ldr r1, =0x000C0030
+ str r1, [r0, #0x288]
+
+ ldr r1, =0x00000000
+ str r1, [r0, #0x270]
+
+ ldr r1, =0x00000030
+ str r1, [r0, #0x260]
+ str r1, [r0, #0x264]
+ str r1, [r0, #0x4A0]
+
+ ldr r1, =0x00020000
+ str r1, [r0, #0x494]
+
+ ldr r1, =0x00000030
+ str r1, [r0, #0x280]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x284]
+
+ ldr r1, =0x00020000
+ str r1, [r0, #0x4B0]
+
+ ldr r1, =0x00000030
+ str r1, [r0, #0x498]
+ str r1, [r0, #0x4A4]
+ str r1, [r0, #0x244]
+ str r1, [r0, #0x248]
+
+ ldr r0, =MMDC_P0_BASE_ADDR
+ ldr r1, =0x00008000
+ str r1, [r0, #0x1C]
+ ldr r1, =0xA1390003
+ str r1, [r0, #0x800]
+ ldr r1, =0x00000004
+ str r1, [r0, #0x80C]
+ ldr r1, =0x41640158
+ str r1, [r0, #0x83C]
+ ldr r1, =0x40403237
+ str r1, [r0, #0x848]
+ ldr r1, =0x40403C33
+ str r1, [r0, #0x850]
+ ldr r1, =0x33333333
+ str r1, [r0, #0x81C]
+ str r1, [r0, #0x820]
+ ldr r1, =0xF3333333
+ str r1, [r0, #0x82C]
+ str r1, [r0, #0x830]
+ ldr r1, =0x00944009
+ str r1, [r0, #0x8C0]
+ ldr r1, =0x00000800
+ str r1, [r0, #0x8B8]
+ ldr r1, =0x0002002D
+ str r1, [r0, #0x004]
+ ldr r1, =0x1B333030
+ str r1, [r0, #0x008]
+ ldr r1, =0x676B52F3
+ str r1, [r0, #0x00C]
+ ldr r1, =0xB66D0B63
+ str r1, [r0, #0x010]
+ ldr r1, =0x01FF00DB
+ str r1, [r0, #0x014]
+ ldr r1, =0x00201740
+ str r1, [r0, #0x018]
+ ldr r1, =0x00008000
+ str r1, [r0, #0x01C]
+ ldr r1, =0x000026D2
+ str r1, [r0, #0x02C]
+ ldr r1, =0x006B1023
+ str r1, [r0, #0x030]
+ ldr r1, =0x0000004F
+ str r1, [r0, #0x040]
+ ldr r1, =0x84180000
+ str r1, [r0, #0x000]
+ ldr r1, =0x00400000
+ str r1, [r0, #0x890]
+ ldr r1, =0x02008032
+ str r1, [r0, #0x01C]
+ ldr r1, =0x00008033
+ str r1, [r0, #0x01C]
+ ldr r1, =0x00048031
+ str r1, [r0, #0x01C]
+ ldr r1, =0x15208030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x04008040
+ str r1, [r0, #0x01C]
+ ldr r1, =0x00000800
+ str r1, [r0, #0x020]
+ ldr r1, =0x00000227
+ str r1, [r0, #0x818]
+ ldr r1, =0x0002552D
+ str r1, [r0, #0x004]
+ ldr r1, =0x00011006
+ str r1, [r0, #0x404]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #0x68]
+ str r1, [r0, #0x6C]
+ str r1, [r0, #0x70]
+ str r1, [r0, #0x74]
+ str r1, [r0, #0x78]
+ str r1, [r0, #0x7C]
+ str r1, [r0, #0x80]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+ imx6ull_ddr3_evk_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg
index 76574ff..c2b3a8c 100644
--- a/board/freescale/mx7dsabresd/imximage.cfg
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index b936544..6ccdd4b 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -50,6 +50,9 @@
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+#define SPI_PAD_CTRL \
+ (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
+
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
@@ -68,6 +71,23 @@
};
#endif
+static iomux_v3_cfg_t const ecspi3_pads[] = {
+ MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
+}
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+}
+
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
@@ -553,6 +573,10 @@
board_qspi_init();
#endif
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+
return 0;
}
diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig
index b0a7a8d..159bcc4 100644
--- a/board/freescale/p1010rdb/Kconfig
+++ b/board/freescale/p1010rdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_P1010RDB
+if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB
config SYS_BOARD
default "p1010rdb"
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 1ae1540..65bb575 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -54,7 +54,7 @@
struct cpld_data {
u8 cpld_ver; /* cpld revision */
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
u8 pcba_ver; /* pcb revision number */
u8 twindie_ddr3;
u8 res1[6];
@@ -69,7 +69,7 @@
u8 por1; /* POR Options */
u8 por2; /* POR Options */
u8 por3; /* POR Options */
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
u8 rom_loc;
#endif
};
@@ -135,7 +135,7 @@
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u8 tmp;
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
switch (ctrl_type) {
@@ -171,7 +171,7 @@
default:
break;
}
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
uint orig_bus = i2c_get_bus_num();
i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
@@ -245,7 +245,7 @@
return 0;
}
-#ifdef CONFIG_P1010RDB_PB
+#ifdef CONFIG_TARGET_P1010RDB_PB
int i2c_pca9557_read(int type)
{
u8 val;
@@ -275,9 +275,9 @@
u8 val;
cpu = gd->arch.cpu;
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
printf("Board: %sRDB-PA, ", cpu->name);
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
printf("Board: %sRDB-PB, ", cpu->name);
i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
@@ -290,10 +290,10 @@
config_board_mux(MUX_TYPE_IFC);
#endif
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
val = (in_8(&cpld_data->pcba_ver) & 0xf);
printf("PCB: v%x.0\n", val);
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
val = in_8(&cpld_data->cpld_ver);
printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
@@ -463,7 +463,7 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB)
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
/* P1014 and it's derivatives don't support CAN and eTSEC3 */
@@ -544,7 +544,7 @@
else if (hwconfig("ifc"))
config_board_mux(MUX_TYPE_IFC);
-#ifdef CONFIG_P1010RDB_PB
+#ifdef CONFIG_TARGET_P1010RDB_PB
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
#endif
return 0;
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index f858408..c22e215 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -12,6 +12,7 @@
#include <i2c.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -31,7 +32,7 @@
/* Clock configuration to access CPLD using IFC(GPCM) */
setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-#ifdef CONFIG_P1010RDB_PB
+#ifdef CONFIG_TARGET_P1010RDB_PB
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
#endif
@@ -103,7 +104,7 @@
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
+ fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index d7dd478..345feac 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -345,7 +345,7 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
FT_FSL_PCI_SETUP;
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 04db767..6a5fe74 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -14,6 +14,7 @@
#include "../common/ngpixis.h"
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -120,7 +121,7 @@
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
+ fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index 074b713..0451722 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -143,7 +143,7 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
index d3352d2..2f9640b 100644
--- a/board/freescale/p1_p2_rdb_pc/Kconfig
+++ b/board/freescale/p1_p2_rdb_pc/Kconfig
@@ -1,4 +1,11 @@
-if TARGET_P1_P2_RDB_PC
+if TARGET_P1020MBG || \
+ TARGET_P1020RDB_PC || \
+ TARGET_P1020RDB_PD || \
+ TARGET_P1020UTM || \
+ TARGET_P1021RDB || \
+ TARGET_P1024RDB || \
+ TARGET_P1025RDB || \
+ TARGET_P2020RDB
config SYS_BOARD
default "p1_p2_rdb_pc"
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 1f3793b..fc38326 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -15,8 +15,8 @@
#ifdef CONFIG_SYS_DDR_RAW_TIMING
#if defined(CONFIG_P1020RDB_PROTO) || \
- defined(CONFIG_P1021RDB) || \
- defined(CONFIG_P1020UTM)
+ defined(CONFIG_TARGET_P1021RDB) || \
+ defined(CONFIG_TARGET_P1020UTM)
/* Micron MT41J256M8_187E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
@@ -47,7 +47,7 @@
.refresh_rate_ps = 7800000,
.tfaw_ps = 37500,
};
-#elif defined(CONFIG_P2020RDB)
+#elif defined(CONFIG_TARGET_P2020RDB)
/* Micron MT41J128M16_15E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
@@ -78,7 +78,7 @@
.refresh_rate_ps = 7800000,
.tfaw_ps = 30000,
};
-#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
/* Micron MT41J512M8_187E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 2,
@@ -109,7 +109,7 @@
.refresh_rate_ps = 7800000,
.tfaw_ps = 37500,
};
-#elif defined(CONFIG_P1020RDB_PC)
+#elif defined(CONFIG_TARGET_P1020RDB_PC)
/*
* Samsung K4B2G0846C-HCF8
* The following timing are for "downshift"
@@ -146,8 +146,8 @@
.refresh_rate_ps = 7800000,
.tfaw_ps = 37500,
};
-#elif defined(CONFIG_P1024RDB) || \
- defined(CONFIG_P1025RDB)
+#elif defined(CONFIG_TARGET_P1024RDB) || \
+ defined(CONFIG_TARGET_P1025RDB)
/*
* Samsung K4B2G0846C-HCH9
* The following timing are for "downshift"
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 61b7a91..51217c5 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -39,7 +39,7 @@
#define GPIO_SLIC_PIN 30
#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
-#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
#define GPIO_DDR_RST_PORT 1
#define GPIO_DDR_RST_PIN 8
#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
@@ -47,7 +47,7 @@
#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
#endif
-#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
+#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
#define PCA_IOPORT_I2C_ADDR 0x23
#define PCA_IOPORT_OUTPUT_CMD 0x2
#define PCA_IOPORT_CFG_CMD 0x6
@@ -58,14 +58,14 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GPIO */
{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
-#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
{1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
#endif
{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
-#ifdef CONFIG_P1025RDB
+#ifdef CONFIG_TARGET_P1025RDB
/* QE_MUX_MDC */
{1, 19, 1, 0, 1}, /* QE_MUX_MDC */
@@ -150,7 +150,7 @@
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
-#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
/* reset DDR3 */
setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
udelay(1000);
@@ -379,7 +379,7 @@
}
#if defined(CONFIG_QE) && \
- (defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB))
+ (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
static void fdt_board_fixup_qe_pins(void *blob)
{
unsigned int oldbus;
@@ -428,7 +428,7 @@
{
phys_addr_t base;
phys_size_t size;
-#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
const char *soc_usb_compat = "fsl-usb2-dr";
int usb_err, usb1_off, usb2_off;
#endif
@@ -448,13 +448,13 @@
#ifdef CONFIG_QE
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
sizeof("okay"), 0);
-#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
+#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
fdt_board_fixup_qe_pins(blob);
#endif
#endif
#if defined(CONFIG_HAS_FSL_DR_USB)
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
@@ -478,7 +478,7 @@
}
#endif
-#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 76a3cf4..9e8f359 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -13,6 +13,7 @@
#include <i2c.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -117,7 +118,7 @@
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
+ fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 1c0008b..7cba411 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -85,13 +85,13 @@
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
-#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
/* 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_1G, 1),
-#endif /* P1020MBG */
+#endif /* TARGET_P1020MBG */
#endif /* RAMBOOT/SPL */
#ifdef CONFIG_SYS_INIT_L2_ADDR
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index a40bea3..f54a6ff 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -282,7 +282,7 @@
#if defined(CONFIG_TWR_P1025)
fdt_board_fixup_qe_pins(blob);
#endif
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
return 0;
}
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index c6a7242..21fb66f 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -225,7 +225,7 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_PCI
diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg
index 6017a40..6449ef2 100644
--- a/board/freescale/s32v234evb/s32v234evb.cfg
+++ b/board/freescale/s32v234evb/s32v234evb.cfg
@@ -5,7 +5,7 @@
*/
/*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig
index 4d17798..6ee7468 100644
--- a/board/freescale/t102xqds/Kconfig
+++ b/board/freescale/t102xqds/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T102XQDS
+if TARGET_T1024QDS
config SYS_BOARD
default "t102xqds"
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index c26f350..b6b1191 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -139,6 +139,9 @@
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x5f;
#endif
/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
index d59d343..c9239b8 100644
--- a/board/freescale/t102xqds/spl.c
+++ b/board/freescale/t102xqds/spl.c
@@ -14,6 +14,7 @@
#include <spi_flash.h>
#include "../common/qixis.h"
#include "t102xqds_qixis.h"
+#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -65,7 +66,7 @@
u32 plat_ratio, sys_clk, ccb_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT)
+#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
/*
* There is T1040 SoC issue where NOR, FPGA are inaccessible during
* NAND boot because IFC signals > IFC_AD7 are not enabled.
@@ -132,8 +133,8 @@
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
- spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
+ fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
@@ -146,7 +147,7 @@
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
+ fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
diff --git a/board/freescale/t102xqds/t1024_rcw.cfg b/board/freescale/t102xqds/t1024_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t102xqds/t1024_rcw.cfg
rename to board/freescale/t102xqds/t1024_nand_rcw.cfg
diff --git a/board/freescale/t102xqds/t1024_sd_rcw.cfg b/board/freescale/t102xqds/t1024_sd_rcw.cfg
new file mode 100644
index 0000000..3eca275
--- /dev/null
+++ b/board/freescale/t102xqds/t1024_sd_rcw.cfg
@@ -0,0 +1,10 @@
+# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
+# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
+
+# PBL preamble and RCW header for T1024QDS
+aa55aa55 010e0100
+# Serdes protocol 0x6F
+0810000e 00000000 00000000 00000000
+37800001 00000012 68104000 21000000
+00000000 00000000 00000000 00030810
+00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t1024_spi_rcw.cfg b/board/freescale/t102xqds/t1024_spi_rcw.cfg
new file mode 100644
index 0000000..1601e35
--- /dev/null
+++ b/board/freescale/t102xqds/t1024_spi_rcw.cfg
@@ -0,0 +1,10 @@
+# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
+# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
+
+# PBL preamble and RCW header for T1024QDS
+aa55aa55 010e0100
+# Serdes protocol 0x6F
+0810000e 00000000 00000000 00000000
+37800001 00000012 58104000 21000000
+00000000 00000000 00000000 00030810
+00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
index 76793a1..1b2f6b2 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -152,7 +152,7 @@
return 0;
}
-#ifdef CONFIG_PPC_T1024
+#ifdef CONFIG_ARCH_T1024
static void board_mux_setup(void)
{
u8 brdcfg15;
@@ -332,7 +332,7 @@
#define NUM_SRDS_PLL 2
int misc_init_r(void)
{
-#ifdef CONFIG_PPC_T1024
+#ifdef CONFIG_ARCH_T1024
board_mux_setup();
#endif
return 0;
@@ -375,7 +375,7 @@
fdt_fixup_liodn(blob);
#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig
index 10d49f5..d538386 100644
--- a/board/freescale/t102xrdb/Kconfig
+++ b/board/freescale/t102xrdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T102XRDB
+if TARGET_T1023RDB || TARGET_T1024RDB
config SYS_BOARD
default "t102xrdb"
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index 6452865..ddeb44f 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -8,7 +8,7 @@
obj-y += spl.o
else
obj-y += t102xrdb.o
-obj-$(CONFIG_T1024RDB) += cpld.o
+obj-$(CONFIG_TARGET_T1024RDB) += cpld.o
obj-y += eth_t102xrdb.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index edfbdbf..e666578 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -136,9 +136,13 @@
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#endif
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
popts->wrlvl_ctl_2 = 0x07070606;
popts->half_strength_driver_enable = 1;
+ popts->cpo_sample = 0x43;
+#elif defined(CONFIG_TARGET_T1024RDB)
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x52;
#endif
}
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 02b283d..c06d1b8 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -58,7 +58,7 @@
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
case 0x95:
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
@@ -73,7 +73,7 @@
case 0x135:
/* set the on-board 2.5G SGMII AQR105 PHY */
fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
/* set the on-board 1G SGMII RTL8211F PHY */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
#endif
@@ -92,9 +92,9 @@
fm_info_set_mdio(i, dev);
break;
case PHY_INTERFACE_MODE_SGMII:
-#if defined(CONFIG_T1023RDB)
+#if defined(CONFIG_TARGET_T1023RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
#endif
fm_info_set_mdio(i, dev);
@@ -128,7 +128,7 @@
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
(port == FM1_DTSEC3)) {
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index bd3cbbf..6d8866e 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -13,6 +13,7 @@
#include <fsl_esdhc.h>
#include <spi_flash.h>
#include "../common/sleep.h"
+#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -119,8 +120,8 @@
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
- spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
+ fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
@@ -133,7 +134,7 @@
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
+ fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t102xrdb/t1023_rcw.cfg
rename to board/freescale/t102xrdb/t1023_nand_rcw.cfg
diff --git a/board/freescale/t102xrdb/t1023_sd_rcw.cfg b/board/freescale/t102xrdb/t1023_sd_rcw.cfg
new file mode 100644
index 0000000..dbf8fba
--- /dev/null
+++ b/board/freescale/t102xrdb/t1023_sd_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Default Core=1200MHz, DDR=1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+3b800003 00000012 68104000 21000000
+00000000 00000000 00000000 00022800
+00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1023_spi_rcw.cfg b/board/freescale/t102xrdb/t1023_spi_rcw.cfg
new file mode 100644
index 0000000..5edcdb5
--- /dev/null
+++ b/board/freescale/t102xrdb/t1023_spi_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Default Core=1200MHz, DDR=1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+3b800003 00000012 58104000 21000000
+00000000 00000000 00000000 00022800
+00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1024_rcw.cfg b/board/freescale/t102xrdb/t1024_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t102xrdb/t1024_rcw.cfg
rename to board/freescale/t102xrdb/t1024_nand_rcw.cfg
diff --git a/board/freescale/t102xrdb/t1024_sd_rcw.cfg b/board/freescale/t102xrdb/t1024_sd_rcw.cfg
new file mode 100644
index 0000000..05b3f37
--- /dev/null
+++ b/board/freescale/t102xrdb/t1024_sd_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1024RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x95
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+4a800003 80000012 6c027000 21000000
+00000000 00000000 00000000 00030810
+00000000 0b005a08 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1024_spi_rcw.cfg b/board/freescale/t102xrdb/t1024_spi_rcw.cfg
new file mode 100644
index 0000000..8b695b4
--- /dev/null
+++ b/board/freescale/t102xrdb/t1024_spi_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1024RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x95
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+4a800003 80000012 5c027000 21000000
+00000000 00000000 00000000 00030810
+00000000 0b005a08 00000000 00000006
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index 01dbf38..56f7c1a 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -17,9 +17,9 @@
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t102xrdb.h"
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
#include "cpld.h"
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#include <i2c.h>
#include <mmc.h>
#endif
@@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
enum {
GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
GPIO1_EMMC_SEL,
@@ -51,10 +51,10 @@
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name);
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
#endif
printf("boot from ");
@@ -63,7 +63,7 @@
puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
puts("SPI\n");
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
u8 reg;
reg = CPLD_READ(flash_csr);
@@ -74,7 +74,7 @@
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
printf("NOR vBank%d\n", reg);
}
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#ifdef CONFIG_NAND
puts("NAND\n");
#else
@@ -91,7 +91,7 @@
return 0;
}
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
static void board_mux_lane(void)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -150,7 +150,7 @@
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
board_mux_lane();
#endif
@@ -189,14 +189,14 @@
#endif
fdt_fixup_liodn(blob);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
fdt_enable_nor(blob);
#endif
@@ -204,7 +204,7 @@
return 0;
}
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
/* Enable NOR flash for RevC */
static void fdt_enable_nor(void *blob)
{
diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h
index ae5c60f..6634e7a 100644
--- a/board/freescale/t102xrdb/t102xrdb.h
+++ b/board/freescale/t102xrdb/t102xrdb.h
@@ -9,7 +9,7 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
static u32 t1023rdb_ctrl(u32 ctrl_type);
static void fdt_enable_nor(void *blob);
#endif
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 8240240..cb58d1e 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -95,6 +95,9 @@
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x69;
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index d7d56b4..5466fbf 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -257,7 +257,7 @@
fdt_fixup_liodn(blob);
#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig
index f28728d..e33d317 100644
--- a/board/freescale/t104xrdb/Kconfig
+++ b/board/freescale/t104xrdb/Kconfig
@@ -1,4 +1,6 @@
-if TARGET_T104XRDB
+if TARGET_T1040RDB || TARGET_T1040D4RDB || \
+ TARGET_T1042RDB || TARGET_T1042D4RDB || \
+ TARGET_T1042RDB_PI
config SYS_BOARD
default "t104xrdb"
diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c
index 0ce4e47..95ff6a7 100644
--- a/board/freescale/t104xrdb/cpld.c
+++ b/board/freescale/t104xrdb/cpld.c
@@ -69,7 +69,7 @@
printf("int_status = 0x%02x\n", CPLD_READ(int_status));
printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
-#if defined(CONFIG_T104XD4RDB)
+#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
printf("int_mask = 0x%02x\n", CPLD_READ(int_mask));
#else
printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h
index 86de26c..7adf5e4 100644
--- a/board/freescale/t104xrdb/cpld.h
+++ b/board/freescale/t104xrdb/cpld.h
@@ -21,7 +21,7 @@
u8 int_status; /* 0x12 - Interrupt status Register */
u8 flash_ctl_status; /* 0x13 - Flash control and status register */
u8 fan_ctl_status; /* 0x14 - Fan control and status register */
-#if defined(CONFIG_T104XD4RDB)
+#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
u8 int_mask; /* 0x15 - Interrupt mask Register */
#else
u8 led_ctl_status; /* 0x15 - LED control and status register */
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 22d6a5f..302f19b 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -77,6 +77,8 @@
*/
#ifdef CONFIG_SYS_FSL_DDR4
popts->half_strength_driver_enable = 1;
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x59;
#else
popts->half_strength_driver_enable = 0;
#endif
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 52cd112..ab8c8bb 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -43,7 +43,7 @@
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
+#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
case PHY_INTERFACE_MODE_SGMII:
/* T1040RDB & T1040D4RDB only supports SGMII on
* DTSEC3
@@ -52,7 +52,7 @@
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
#endif
-#ifdef CONFIG_T1042RDB
+#ifdef CONFIG_TARGET_T1042RDB
case PHY_INTERFACE_MODE_SGMII:
/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
@@ -62,7 +62,7 @@
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
#endif
-#ifdef CONFIG_T1042D4RDB
+#ifdef CONFIG_TARGET_T1042D4RDB
case PHY_INTERFACE_MODE_SGMII:
/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
* & DTSEC3
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 4b35af6..1c2023b 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -13,6 +13,7 @@
#include <fsl_esdhc.h>
#include <spi_flash.h>
#include "../common/sleep.h"
+#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -114,8 +115,8 @@
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
- spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
+ fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
@@ -129,7 +130,7 @@
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
+ fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
diff --git a/board/freescale/t104xrdb/t1040_rcw.cfg b/board/freescale/t104xrdb/t1040_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t104xrdb/t1040_rcw.cfg
rename to board/freescale/t104xrdb/t1040_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1040_sd_rcw.cfg b/board/freescale/t104xrdb/t1040_sd_rcw.cfg
new file mode 100644
index 0000000..fd3e8c5
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 80000002 68106000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040_spi_rcw.cfg b/board/freescale/t104xrdb/t1040_spi_rcw.cfg
new file mode 100644
index 0000000..fccde5e
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 80000002 58106000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040d4_rcw.cfg b/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t104xrdb/t1040d4_rcw.cfg
rename to board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg b/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
new file mode 100644
index 0000000..e6f7585
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 6c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg b/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
new file mode 100644
index 0000000..cde862d
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 5c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_rcw.cfg b/board/freescale/t104xrdb/t1042_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t104xrdb/t1042_rcw.cfg
rename to board/freescale/t104xrdb/t1042_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1042_pi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t104xrdb/t1042_pi_rcw.cfg
rename to board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
new file mode 100644
index 0000000..bbce9a3
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 68106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
new file mode 100644
index 0000000..b1d8b4c
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 58106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_sd_rcw.cfg b/board/freescale/t104xrdb/t1042_sd_rcw.cfg
new file mode 100644
index 0000000..d77bf18
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 80000002 6c027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_spi_rcw.cfg b/board/freescale/t104xrdb/t1042_spi_rcw.cfg
new file mode 100644
index 0000000..e8a3ad1
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 80000002 5c027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042d4_rcw.cfg b/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t104xrdb/t1042d4_rcw.cfg
rename to board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg b/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
new file mode 100644
index 0000000..9d9046d
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 6c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg b/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
new file mode 100644
index 0000000..f1ec989
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 5c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index ec97677..d4c3d4d 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -29,7 +29,7 @@
struct cpu_type *cpu = gd->arch.cpu;
u8 sw;
-#ifdef CONFIG_T104XD4RDB
+#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
printf("Board: %sD4RDB\n", cpu->name);
#else
printf("Board: %sRDB\n", cpu->name);
@@ -105,7 +105,7 @@
CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
-#if defined(CONFIG_T1040D4RDB)
+#if defined(CONFIG_TARGET_T1040D4RDB)
if (hwconfig("qe-tdm")) {
CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
MISC_MUX_QE_TDM);
@@ -144,7 +144,7 @@
fdt_fixup_liodn(blob);
#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig
index 4e329dd..26ef530 100644
--- a/board/freescale/t208xqds/Kconfig
+++ b/board/freescale/t208xqds/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T208XQDS
+if TARGET_T2080QDS || TARGET_T2081QDS
config SYS_BOARD
default "t208xqds"
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
index ef04a26..587903a 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -7,8 +7,8 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
index f96470f..d6e4554 100644
--- a/board/freescale/t208xqds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
@@ -99,6 +99,9 @@
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x64;
}
phys_size_t initdram(int board_type)
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index e92b5d3..c880294 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -32,13 +32,13 @@
#define EMI1_RGMII1 0
#define EMI1_RGMII2 1
#define EMI1_SLOT1 2
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
#define EMI1_SLOT2 6
#define EMI1_SLOT3 3
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
#define EMI2 7
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
#define EMI1_SLOT2 3
#define EMI1_SLOT3 4
#define EMI1_SLOT5 5
@@ -59,7 +59,7 @@
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
"T2080QDS_MDIO_RGMII1",
"T2080QDS_MDIO_RGMII2",
"T2080QDS_MDIO_SLOT1",
@@ -68,7 +68,7 @@
"T2080QDS_MDIO_SLOT5",
"T2080QDS_MDIO_SLOT2",
"T2080QDS_MDIO_10GC",
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
"T2081QDS_MDIO_RGMII1",
"T2081QDS_MDIO_RGMII2",
"T2081QDS_MDIO_SLOT1",
@@ -82,9 +82,9 @@
};
/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
#endif
@@ -204,7 +204,7 @@
int off;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_T2080QDS
+#ifdef CONFIG_TARGET_T2080QDS
serdes_corenet_t *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
@@ -217,7 +217,7 @@
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
switch (port) {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case FM1_DTSEC1:
if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
media_type = 1;
@@ -311,7 +311,7 @@
fdt_status_okay_by_alias(fdt, "emi1_slot2");
}
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC5:
@@ -454,7 +454,7 @@
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_s1) {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case 0x51:
case 0x5f:
case 0x65:
@@ -481,7 +481,7 @@
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case 0x6b:
lane_to_slot[4] = 1;
lane_to_slot[5] = 3;
@@ -552,11 +552,11 @@
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
#endif
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-#if defined(CONFIG_T2081QDS)
+#if defined(CONFIG_TARGET_T2081QDS)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
#endif
@@ -663,7 +663,7 @@
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case 0xd9:
case 0xd3:
case 0xcb:
@@ -675,7 +675,7 @@
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case 0xca:
case 0xcb:
/* SGMII in Slot3 */
@@ -731,7 +731,7 @@
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
-#if defined(CONFIG_T2081QDS)
+#if defined(CONFIG_TARGET_T2081QDS)
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i, mii_dev_for_muxval(
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index bb02dab..b1e1cf1 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -14,6 +14,7 @@
#include <spi_flash.h>
#include "../common/qixis.h"
#include "t208xqds_qixis.h"
+#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -118,8 +119,8 @@
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
- spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
+ fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
@@ -132,7 +133,7 @@
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
+ fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t208xqds/t2080_rcw.cfg
rename to board/freescale/t208xqds/t2080_nand_rcw.cfg
diff --git a/board/freescale/t208xqds/t2080_sd_rcw.cfg b/board/freescale/t208xqds/t2080_sd_rcw.cfg
new file mode 100644
index 0000000..73f53fa
--- /dev/null
+++ b/board/freescale/t208xqds/t2080_sd_rcw.cfg
@@ -0,0 +1,16 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
+#12100017 15000000 00000000 00000000
+#66150002 00008400 e8104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 68104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2080_spi_rcw.cfg b/board/freescale/t208xqds/t2080_spi_rcw.cfg
new file mode 100644
index 0000000..8474c8e
--- /dev/null
+++ b/board/freescale/t208xqds/t2080_spi_rcw.cfg
@@ -0,0 +1,16 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
+#12100017 15000000 00000000 00000000
+#66150002 00008400 e8104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 58104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t208xqds/t2081_rcw.cfg
rename to board/freescale/t208xqds/t2081_nand_rcw.cfg
diff --git a/board/freescale/t208xqds/t2081_sd_rcw.cfg b/board/freescale/t208xqds/t2081_sd_rcw.cfg
new file mode 100644
index 0000000..daced67
--- /dev/null
+++ b/board/freescale/t208xqds/t2081_sd_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 68104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_spi_rcw.cfg b/board/freescale/t208xqds/t2081_spi_rcw.cfg
new file mode 100644
index 0000000..79ba1f1
--- /dev/null
+++ b/board/freescale/t208xqds/t2081_spi_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 58104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg
index e200d92..43be8a8 100644
--- a/board/freescale/t208xqds/t208x_pbi.cfg
+++ b/board/freescale/t208xqds/t208x_pbi.cfg
@@ -37,5 +37,4 @@
09000014 ff000000
09000018 81000000
#Flush PBL data
-09138000 00000000
-091380c0 00000000
+091380c0 00100000
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index bfea3a1..26093ea 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -99,7 +99,7 @@
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
@@ -109,7 +109,7 @@
case 0:
/* SerDes1 is not enabled */
break;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case 0x1b:
case 0x1c:
case 0xa2:
@@ -191,7 +191,7 @@
*/
QIXIS_WRITE(brdcfg[12], 0x1a);
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case 0x50:
case 0x51:
/* SD1(A:D) => SLOT2 XAUI
@@ -268,7 +268,7 @@
return -1;
}
-#ifdef CONFIG_T2080QDS
+#ifdef CONFIG_TARGET_T2080QDS
switch (srds_prtcl_s2) {
case 0:
/* SerDes2 is not enabled */
@@ -461,7 +461,7 @@
#endif
fdt_fixup_liodn(blob);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig
index 845af3d..71e1130 100644
--- a/board/freescale/t208xrdb/Kconfig
+++ b/board/freescale/t208xrdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T208XRDB
+if TARGET_T2080RDB
config SYS_BOARD
default "t208xrdb"
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
index cd8fe09..25ea66a 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -7,7 +7,7 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
+obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index f6c8ca3..3487261 100644
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -92,6 +92,9 @@
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x54;
}
phys_size_t initdram(int board_type)
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 2ff05a2..bb23865 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -12,6 +12,7 @@
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -88,8 +89,8 @@
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
- spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
+ fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
@@ -102,7 +103,7 @@
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
+ fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_nand_rcw.cfg
similarity index 100%
rename from board/freescale/t208xrdb/t2080_rcw.cfg
rename to board/freescale/t208xrdb/t2080_nand_rcw.cfg
diff --git a/board/freescale/t208xrdb/t2080_pbi.cfg b/board/freescale/t208xrdb/t2080_pbi.cfg
index e200d92..43be8a8 100644
--- a/board/freescale/t208xrdb/t2080_pbi.cfg
+++ b/board/freescale/t208xrdb/t2080_pbi.cfg
@@ -37,5 +37,4 @@
09000014 ff000000
09000018 81000000
#Flush PBL data
-09138000 00000000
-091380c0 00000000
+091380c0 00100000
diff --git a/board/freescale/t208xrdb/t2080_sd_rcw.cfg b/board/freescale/t208xrdb/t2080_sd_rcw.cfg
new file mode 100644
index 0000000..6309b1d
--- /dev/null
+++ b/board/freescale/t208xrdb/t2080_sd_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 68104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t2080_spi_rcw.cfg b/board/freescale/t208xrdb/t2080_spi_rcw.cfg
new file mode 100644
index 0000000..f167495
--- /dev/null
+++ b/board/freescale/t208xrdb/t2080_spi_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 58104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 0cb05aa..1ab05ec 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -128,7 +128,7 @@
#endif
fdt_fixup_liodn(blob);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig
index 27a64b6..563a87c 100644
--- a/board/freescale/t4qds/Kconfig
+++ b/board/freescale/t4qds/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T4240QDS
+if TARGET_T4160QDS || TARGET_T4240QDS
config SYS_BOARD
default "t4qds"
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index 731ccb0..1eacbcc 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -7,7 +7,8 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_T4240QDS) += t4240qds.o eth.o
+obj-$(CONFIG_TARGET_T4160QDS) += t4240qds.o eth.o
+obj-$(CONFIG_TARGET_T4240QDS) += t4240qds.o eth.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index d533924..842073b 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -107,6 +107,9 @@
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x63;
}
phys_size_t initdram(int board_type)
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
index f1393f2..35ad19e 100644
--- a/board/freescale/t4qds/t4240emu.c
+++ b/board/freescale/t4qds/t4240emu.c
@@ -76,7 +76,7 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
fdt_fixup_liodn(blob);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
return 0;
}
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index d6df144..8f9e7e8 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -694,7 +694,7 @@
#endif
fdt_fixup_liodn(blob);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/t4qds/t4_nand_rcw.cfg b/board/freescale/t4qds/t4_nand_rcw.cfg
new file mode 100644
index 0000000..9386be0
--- /dev/null
+++ b/board/freescale/t4qds/t4_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol 1_27_5_11
+1607001b 18101b16 00000000 00000000
+04362858 30548c00 e8020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
index 6126266..8d46003 100644
--- a/board/freescale/t4qds/t4_pbi.cfg
+++ b/board/freescale/t4qds/t4_pbi.cfg
@@ -18,5 +18,4 @@
09000014 ff000000
09000018 81000000
#Flush PBL data
-09138000 00000000
-091380c0 00000000
+091380c0 00100000
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
deleted file mode 100644
index 267494c..0000000
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol 1_27_5_11
-1607001b 18101b16 00000000 00000000
-04362858 30548c00 ec020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4qds/t4_sd_rcw.cfg b/board/freescale/t4qds/t4_sd_rcw.cfg
new file mode 100644
index 0000000..54beb67
--- /dev/null
+++ b/board/freescale/t4qds/t4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol 1_27_5_11
+1607001b 18101b16 00000000 00000000
+04362858 30548c00 68020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
index d93e453..67832da 100644
--- a/board/freescale/t4rdb/Kconfig
+++ b/board/freescale/t4rdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T4240RDB
+if TARGET_T4160RDB || TARGET_T4240RDB
config SYS_BOARD
default "t4rdb"
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 4f29eea..209983a 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -7,7 +7,8 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-$(CONFIG_TARGET_T4160RDB) += t4240rdb.o
+obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o
obj-y += cpld.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 230f031..7b05821 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -100,6 +100,9 @@
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x64;
}
phys_size_t initdram(int board_type)
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 406fb13..bdd6f4e 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -107,7 +107,7 @@
#endif
fdt_fixup_liodn(blob);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg
index e7bb673..0b326fa 100644
--- a/board/freescale/t4rdb/t4_pbi.cfg
+++ b/board/freescale/t4rdb/t4_pbi.cfg
@@ -24,5 +24,4 @@
09000014 ff000000
09000018 81000000
#Flush PBL data
-09138000 00000000
-091380c0 00000000
+091380c0 00100000
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
deleted file mode 100644
index 282fea48..0000000
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol 27_55_1_9
-16070019 18101916 00000000 00000000
-6c6e0848 00448c00 ec020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/t4_sd_rcw.cfg b/board/freescale/t4rdb/t4_sd_rcw.cfg
new file mode 100644
index 0000000..cc2bff6
--- /dev/null
+++ b/board/freescale/t4rdb/t4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol 27_55_1_9
+16070019 18101916 00000000 00000000
+6c6e0848 00448c00 6c020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg
index 9c823c4..09125cf 100644
--- a/board/freescale/vf610twr/imximage.cfg
+++ b/board/freescale/vf610twr/imximage.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 2ca6d5c..613a275 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -6,7 +6,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <common.h>
#include <i2c.h>
#include <linux/ctype.h>
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index 848cdde..0a7baaa 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -15,7 +15,7 @@
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/ppc4xx-gpio.h>
#include <flash.h>
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
index f55893f..c6566e9 100644
--- a/board/gdsys/mpc8308/hrcon.c
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -358,7 +358,7 @@
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
return 0;
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
index b8dde5f..34e9d19 100644
--- a/board/gdsys/mpc8308/strider.c
+++ b/board/gdsys/mpc8308/strider.c
@@ -413,7 +413,7 @@
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
return 0;
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 2f98e47..01064dc 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -341,7 +341,7 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
FT_FSL_PCI_SETUP;
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index e9729f8..2fc1144 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -10,7 +10,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
@@ -596,6 +596,57 @@
};
#endif
+void pmic_init(void)
+{
+#define I2C_PMIC 0x2
+#define DA9063_I2C_ADDR 0x58
+#define DA9063_REG_BCORE2_CFG 0x9D
+#define DA9063_REG_BCORE1_CFG 0x9E
+#define DA9063_REG_BPRO_CFG 0x9F
+#define DA9063_REG_BIO_CFG 0xA0
+#define DA9063_REG_BMEM_CFG 0xA1
+#define DA9063_REG_BPERI_CFG 0xA2
+#define DA9063_BUCK_MODE_MASK 0xC0
+#define DA9063_BUCK_MODE_MANUAL 0x00
+#define DA9063_BUCK_MODE_SLEEP 0x40
+#define DA9063_BUCK_MODE_SYNC 0x80
+#define DA9063_BUCK_MODE_AUTO 0xC0
+
+ uchar val;
+
+ i2c_set_bus_num(I2C_PMIC);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+}
+
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
@@ -619,6 +670,9 @@
pwm_enable(0);
#endif
+ /* board specific pmic init */
+ pmic_init();
+
return 0;
}
diff --git a/board/google/chromebook_jerry/Kconfig b/board/google/chromebook_jerry/Kconfig
deleted file mode 100644
index 3640513..0000000
--- a/board/google/chromebook_jerry/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_CHROMEBOOK_JERRY
-
-config SYS_BOARD
- default "chromebook_jerry"
-
-config SYS_VENDOR
- default "google"
-
-config SYS_CONFIG_NAME
- default "chromebook_jerry"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
-endif
diff --git a/board/google/chromebook_jerry/MAINTAINERS b/board/google/chromebook_jerry/MAINTAINERS
deleted file mode 100644
index b01b6cd..0000000
--- a/board/google/chromebook_jerry/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CHROMEBOOK JERRY BOARD
-M: Simon Glass <sjg@chromium.org>
-S: Maintained
-F: board/google/chromebook_jerry/
-F: include/configs/chromebook_jerry.h
-F: configs/chromebook_jerry_defconfig
diff --git a/board/google/chromebook_jerry/Makefile b/board/google/chromebook_jerry/Makefile
deleted file mode 100644
index d29a063..0000000
--- a/board/google/chromebook_jerry/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2015 Google, Inc
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += jerry.o
diff --git a/board/google/chromebook_jerry/jerry.c b/board/google/chromebook_jerry/jerry.c
deleted file mode 100644
index 5119e95..0000000
--- a/board/google/chromebook_jerry/jerry.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig
new file mode 100644
index 0000000..770e9aa
--- /dev/null
+++ b/board/google/veyron/Kconfig
@@ -0,0 +1,47 @@
+if TARGET_CHROMEBOOK_JERRY
+
+config SYS_BOARD
+ default "veyron"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_CONFIG_NAME
+ default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
+
+if TARGET_CHROMEBIT_MICKEY
+
+config SYS_BOARD
+ default "veyron"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_CONFIG_NAME
+ default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
+
+if TARGET_CHROMEBOOK_MINNIE
+
+config SYS_BOARD
+ default "veyron"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_CONFIG_NAME
+ default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS
new file mode 100644
index 0000000..d582cb0
--- /dev/null
+++ b/board/google/veyron/MAINTAINERS
@@ -0,0 +1,20 @@
+CHROMEBOOK JERRY BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/veyron/
+F: include/configs/veyron.h
+F: configs/chromebook_jerry_defconfig
+
+CHROMEBIT MICKEY BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/veyron/
+F: include/configs/veyron.h
+F: configs/chromebit_mickey_defconfig
+
+CHROMEBIT MINNIE BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/veyron/
+F: include/configs/veyron.h
+F: configs/chromebit_minnie_defconfig
diff --git a/board/google/veyron/Makefile b/board/google/veyron/Makefile
new file mode 100644
index 0000000..9868357
--- /dev/null
+++ b/board/google/veyron/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += veyron.o
diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
new file mode 100644
index 0000000..20297e1
--- /dev/null
+++ b/board/google/veyron/veyron.c
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * We should increase the DDR voltage to 1.2V using the PWM regulator.
+ * There is a U-Boot driver for this but it may need to add support for the
+ * 'voltage-table' property.
+ */
diff --git a/board/grinn/liteboard/Kconfig b/board/grinn/liteboard/Kconfig
new file mode 100644
index 0000000..e035872
--- /dev/null
+++ b/board/grinn/liteboard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LITEBOARD
+
+config SYS_BOARD
+ default "liteboard"
+
+config SYS_VENDOR
+ default "grinn"
+
+config SYS_CONFIG_NAME
+ default "liteboard"
+
+endif
diff --git a/board/grinn/liteboard/MAINTAINERS b/board/grinn/liteboard/MAINTAINERS
new file mode 100644
index 0000000..b4474f1
--- /dev/null
+++ b/board/grinn/liteboard/MAINTAINERS
@@ -0,0 +1,6 @@
+LITEBOARD
+M: Marcin Niestroj <m.niestroj@grinn-global.com>
+S: Maintained
+F: board/grinn/liteboard/
+F: include/configs/liteboard.h
+F: configs/liteboard_defconfig
diff --git a/board/grinn/liteboard/Makefile b/board/grinn/liteboard/Makefile
new file mode 100644
index 0000000..e2492d6
--- /dev/null
+++ b/board/grinn/liteboard/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Grinn
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/grinn/liteboard/README b/board/grinn/liteboard/README
new file mode 100644
index 0000000..bee0394
--- /dev/null
+++ b/board/grinn/liteboard/README
@@ -0,0 +1,31 @@
+How to use U-Boot on Grinn's liteBoard
+--------------------------------------
+
+- Build U-Boot for liteBoard:
+
+$ make mrproper
+$ make liteboard_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+S1: 0 1 0 1 1 1
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Insert the micro SD card in the board.
+
+- Connect USB cable between liteBoard and the PC for the power and console.
+
+- U-Boot messages should come up.
diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c
new file mode 100644
index 0000000..13dd0a6
--- /dev/null
+++ b/board/grinn/liteboard/board.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <linux/sizes.h>
+#include <linux/fb.h>
+#include <mach/litesom.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <spl.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const sd_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD */
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
+
+#define SD_CD_GPIO IMX_GPIO_NR(1, 19)
+
+static int mmc_get_env_devno(void)
+{
+ u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+ int dev_no;
+ u32 bootsel;
+
+ bootsel = (soc_sbmr & 0x000000FF) >> 6;
+
+ /* If not boot from sd/mmc, use default value */
+ if (bootsel != 1)
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ /* BOOT_CFG2[3] and BOOT_CFG2[4] */
+ dev_no = (soc_sbmr & 0x00001800) >> 11;
+
+ return dev_no;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(SD_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* SD */
+ imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
+ gpio_direction_input(SD_CD_GPIO);
+ sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ ret = fsl_esdhc_initialize(bis, &sd_cfg);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev 0 (SD)\n");
+ return ret;
+ }
+
+ return litesom_mmc_init(bis);
+}
+
+static int check_mmc_autodetect(void)
+{
+ char *autodetect_str = getenv("mmcautodetect");
+
+ if ((autodetect_str != NULL) &&
+ (strcmp(autodetect_str, "yes") == 0)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+void board_late_mmc_init(void)
+{
+ char cmd[32];
+ char mmcblk[32];
+ u32 dev_no = mmc_get_env_devno();
+
+ if (!check_mmc_autodetect())
+ return;
+
+ setenv_ulong("mmcdev", dev_no);
+
+ /* Set mmcblk env */
+ sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+ dev_no);
+ setenv("mmcroot", mmcblk);
+
+ sprintf(cmd, "mmc dev %d", dev_no);
+ run_command(cmd, 0);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_fec();
+
+ return fecmxc_initialize(bis);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
+ set gpr1[17]*/
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ enable_enet_clk(1);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_usb_phy_mode(int port)
+{
+ return USB_INIT_HOST;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+ {"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_init();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Grinn liteBoard\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_boot_order(u32 *spl_boot_list)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
+ unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
+ unsigned port = (reg >> 11) & 0x1;
+
+ if (port == 0) {
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ spl_boot_list[1] = BOOT_DEVICE_MMC2;
+ } else {
+ spl_boot_list[0] = BOOT_DEVICE_MMC2;
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+ }
+}
+
+void board_init_f(ulong dummy)
+{
+ litesom_init_f();
+}
+#endif
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index 4330cf0..5ef383d 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -17,7 +17,7 @@
#include <asm/omap_gpio.h>
#include <asm/arch/dss.h>
#include <asm/arch/clock.h>
-#include "errno.h"
+#include <errno.h>
#include <i2c.h>
#ifdef CONFIG_USB_EHCI
#include <usb.h>
diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig
new file mode 100644
index 0000000..ab76a3c
--- /dev/null
+++ b/board/imgtec/boston/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_BOSTON
+
+config SYS_BOARD
+ default "boston"
+
+config SYS_VENDOR
+ default "imgtec"
+
+config SYS_CONFIG_NAME
+ default "boston"
+
+config SYS_TEXT_BASE
+ default 0x9fc00000 if 32BIT
+ default 0xffffffff9fc00000 if 64BIT
+
+endif
diff --git a/board/imgtec/boston/MAINTAINERS b/board/imgtec/boston/MAINTAINERS
new file mode 100644
index 0000000..ec850d2
--- /dev/null
+++ b/board/imgtec/boston/MAINTAINERS
@@ -0,0 +1,9 @@
+BOSTON BOARD
+M: Paul Burton <paul.burton@imgtec.com>
+S: Maintained
+F: board/imgtec/boston/
+F: include/configs/boston.h
+F: configs/boston32r2_defconfig
+F: configs/boston32r2el_defconfig
+F: configs/boston64r2_defconfig
+F: configs/boston64r2el_defconfig
diff --git a/board/imgtec/boston/Makefile b/board/imgtec/boston/Makefile
new file mode 100644
index 0000000..deda457
--- /dev/null
+++ b/board/imgtec/boston/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Imagination Technologies
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y += checkboard.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
diff --git a/board/imgtec/boston/boston-lcd.h b/board/imgtec/boston/boston-lcd.h
new file mode 100644
index 0000000..9f5c1b9
--- /dev/null
+++ b/board/imgtec/boston/boston-lcd.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __BOARD_BOSTON_LCD_H__
+#define __BOARD_BOSTON_LCD_H__
+
+/**
+ * lowlevel_display() - Display a message on Boston's LCD
+ * @msg: The string to display
+ *
+ * Display the string @msg on the 7 character LCD display of the Boston board.
+ * This is typically used for debug or to present some form of status
+ * indication to the user, allowing faults to be identified when things go
+ * wrong early enough that the UART isn't up.
+ */
+void lowlevel_display(const char msg[static 8]);
+
+#endif /* __BOARD_BOSTON_LCD_H__ */
diff --git a/board/imgtec/boston/boston-regs.h b/board/imgtec/boston/boston-regs.h
new file mode 100644
index 0000000..b9dfbb4
--- /dev/null
+++ b/board/imgtec/boston/boston-regs.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __BOARD_BOSTON_REGS_H__
+#define __BOARD_BOSTON_REGS_H__
+
+#include <asm/addrspace.h>
+
+#define BOSTON_PLAT_BASE CKSEG1ADDR(0x17ffd000)
+#define BOSTON_LCD_BASE CKSEG1ADDR(0x17fff000)
+
+/*
+ * Platform Register Definitions
+ */
+#define BOSTON_PLAT_CORE_CL (BOSTON_PLAT_BASE + 0x04)
+
+#define BOSTON_PLAT_DDR3STAT (BOSTON_PLAT_BASE + 0x14)
+# define BOSTON_PLAT_DDR3STAT_CALIB (1 << 2)
+
+#define BOSTON_PLAT_DDRCONF0 (BOSTON_PLAT_BASE + 0x38)
+# define BOSTON_PLAT_DDRCONF0_SIZE (0xf << 0)
+
+#endif /* __BOARD_BOSTON_REGS_H__ */
diff --git a/board/imgtec/boston/checkboard.c b/board/imgtec/boston/checkboard.c
new file mode 100644
index 0000000..93eae7f
--- /dev/null
+++ b/board/imgtec/boston/checkboard.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+
+#include "boston-lcd.h"
+#include "boston-regs.h"
+
+int checkboard(void)
+{
+ u32 changelist;
+
+ lowlevel_display("U-boot ");
+
+ printf("Board: MIPS Boston\n");
+
+ printf("CPU: 0x%08x", read_c0_prid());
+ changelist = __raw_readl((uint32_t *)BOSTON_PLAT_CORE_CL);
+ if (changelist > 1)
+ printf(" cl%x", changelist);
+ putc('\n');
+
+ return 0;
+}
diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
new file mode 100644
index 0000000..ceffef6
--- /dev/null
+++ b/board/imgtec/boston/ddr.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+
+#include "boston-regs.h"
+
+phys_size_t initdram(int board_type)
+{
+ u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
+
+ return (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) << 30;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
+ /* 2GB wrapped around to 0 */
+ return CKSEG0ADDR(256 << 20);
+ }
+
+ return min_t(unsigned long, gd->ram_top, CKSEG0ADDR(256 << 20));
+}
diff --git a/board/imgtec/boston/lowlevel_init.S b/board/imgtec/boston/lowlevel_init.S
new file mode 100644
index 0000000..0c01aa9
--- /dev/null
+++ b/board/imgtec/boston/lowlevel_init.S
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+
+#include "boston-regs.h"
+
+.data
+
+msg_ddr_cal: .ascii "DDR Cal "
+msg_ddr_ok: .ascii "DDR OK "
+
+.text
+
+LEAF(lowlevel_init)
+ move s0, ra
+
+ PTR_LA a0, msg_ddr_cal
+ bal lowlevel_display
+
+ PTR_LI t0, BOSTON_PLAT_DDR3STAT
+1: lw t1, 0(t0)
+ andi t1, t1, BOSTON_PLAT_DDR3STAT_CALIB
+ beqz t1, 1b
+
+ PTR_LA a0, msg_ddr_ok
+ bal lowlevel_display
+
+ move v0, zero
+ jr s0
+ END(lowlevel_init)
+
+LEAF(lowlevel_display)
+ .set push
+ .set noat
+ PTR_LI AT, BOSTON_LCD_BASE
+#ifdef CONFIG_64BIT
+ ld k1, 0(a0)
+ sd k1, 0(AT)
+#else
+ lw k1, 0(a0)
+ sw k1, 0(AT)
+ lw k1, 4(a0)
+ sw k1, 4(AT)
+#endif
+ .set pop
+1: jr ra
+ END(lowlevel_display)
diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS
index a0b3284..052ec67 100644
--- a/board/imgtec/malta/MAINTAINERS
+++ b/board/imgtec/malta/MAINTAINERS
@@ -3,5 +3,7 @@
S: Maintained
F: board/imgtec/malta/
F: include/configs/malta.h
+F: configs/malta64_defconfig
+F: configs/malta64el_defconfig
F: configs/malta_defconfig
F: configs/maltael_defconfig
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index 3d48cdc..6df4d9f 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -28,12 +28,6 @@
.globl lowlevel_init
lowlevel_init:
- /* disable any L2 cache for now */
- sync
- mfc0 t0, CP0_CONFIG, 2
- ori t0, t0, 0x1 << 12
- mtc0 t0, CP0_CONFIG, 2
-
/* detect the core card */
PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
lw t0, 0(t0)
diff --git a/board/imgtec/xilfpga/Kconfig b/board/imgtec/xilfpga/Kconfig
new file mode 100644
index 0000000..b078278
--- /dev/null
+++ b/board/imgtec/xilfpga/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_XILFPGA
+
+config SYS_BOARD
+ default "xilfpga"
+
+config SYS_VENDOR
+ default "imgtec"
+
+config SYS_CONFIG_NAME
+ default "imgtec_xilfpga"
+
+config SYS_TEXT_BASE
+ default 0x80C00000
+
+endif
diff --git a/board/imgtec/xilfpga/MAINTAINERS b/board/imgtec/xilfpga/MAINTAINERS
new file mode 100644
index 0000000..aa04532
--- /dev/null
+++ b/board/imgtec/xilfpga/MAINTAINERS
@@ -0,0 +1,6 @@
+XILFPGA BOARD
+M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+S: Maintained
+F: board/imgtec/xilfpga
+F: include/configs/xilfpga.h
+F: configs/imgtec_xilfpga_defconfig
diff --git a/board/imgtec/xilfpga/Makefile b/board/imgtec/xilfpga/Makefile
new file mode 100644
index 0000000..9aaf9ce
--- /dev/null
+++ b/board/imgtec/xilfpga/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016, Imagination Technologies Ltd.
+# Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-y := xilfpga.o
diff --git a/board/imgtec/xilfpga/README b/board/imgtec/xilfpga/README
new file mode 100644
index 0000000..ac19d48
--- /dev/null
+++ b/board/imgtec/xilfpga/README
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com
+ */
+
+MIPSfpga
+=======================================
+
+MIPSfpga is an FPGA based development platform by Imagination Technologies
+As we are dealing with a MIPS core instantiated on an FPGA, specifications
+are fluid and can be varied in RTL.
+
+The example project provided by IMGTEC runs on the Nexys4DDR board by
+Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
+the example project and the Nexys4DDR board:
+
+- microAptiv UP core m14Kc
+- 50MHz clock speed
+- 128Mbyte DDR RAM at 0x0000_0000
+- 8Kbyte RAM at 0x1000_0000
+- axi_intc at 0x1020_0000
+- axi_uart16550 at 0x1040_0000
+- axi_gpio at 0x1060_0000
+- axi_i2c at 0x10A0_0000
+- custom_gpio at 0x10C0_0000
+- axi_ethernetlite at 0x10E0_0000
+- 8Kbyte BootRAM at 0x1FC0_0000
+- 16Mbyte QPI at 0x1D00_0000
+
+Boot protocol:
+--------------
+
+The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
+This is for easy reprogrammibility via JTAG.
+
+DDR initialization is already handled by a HW IP block.
+
+When the example project bitstream is loaded, the cpu_reset button
+needs to be pressed.
+
+The bootram initializes the cache and axi_uart
+Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000
+
+If there is, then that is considered as u-boot. u-boot is copied from
+0x1D40_0000 to memory and the bootram jumps into u-boot code.
+
+At this point, the board is ready to load the Linux kernel + buildroot initramfs
+
+This can be done in multiple ways:
+
+1- JTAG load the binary and jump into it.
+2- Load kernel stored in the QSPI flash at 0x1D80_0000
+3- Load uImage via tftp. Ethernet works in u-boot.
+ e.g. env set server ip 192.168.154.45; dhcp uImage; bootm
diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c
new file mode 100644
index 0000000..77a1952
--- /dev/null
+++ b/board/imgtec/xilfpga/xilfpga.c
@@ -0,0 +1,20 @@
+/*
+ * Imagination Technologies MIPSfpga platform code
+ *
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+
+/* initialize the DDR Controller and PHY */
+phys_size_t initdram(int board_type)
+{
+ /* MIG IP block is smart and doesn't need SW
+ * to do any init */
+ return CONFIG_SYS_SDRAM_SIZE; /* in bytes */
+}
diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile
index fd0c2f9..4d13ead 100644
--- a/board/intercontrol/digsy_mtc/Makefile
+++ b/board/intercontrol/digsy_mtc/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := digsy_mtc.o cmd_mtc.o
+obj-y := digsy_mtc.o
obj-$(CONFIG_VIDEO) += cmd_disp.o
diff --git a/board/intercontrol/digsy_mtc/cmd_mtc.c b/board/intercontrol/digsy_mtc/cmd_mtc.c
deleted file mode 100644
index f17ec55..0000000
--- a/board/intercontrol/digsy_mtc/cmd_mtc.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2009
- * Werner Pfister <Pfister_Werner@intercontrol.de>
- *
- * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <mpc5xxx.h>
-#include "spi.h"
-#include "cmd_mtc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static uchar user_out;
-
-static const char *led_names[] = {
- "diag",
- "can1",
- "can2",
- "can3",
- "can4",
- "usbpwr",
- "usbbusy",
- "user1",
- "user2",
- ""
-};
-
-static int msp430_xfer(const void *dout, void *din)
-{
- int err;
-
- err = spi_xfer(NULL, MTC_TRANSFER_SIZE, dout, din,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- /* The MSP chip needs time to ready itself for the next command */
- udelay(1000);
-
- return err;
-}
-
-static void mtc_calculate_checksum(tx_msp_cmd *packet)
-{
- int i;
- uchar *buff;
-
- buff = (uchar *) packet;
-
- for (i = 0; i < 6; i++)
- packet->cks += buff[i];
-}
-
-static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- tx_msp_cmd pcmd;
- rx_msp_cmd prx;
- int err;
- int i;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- memset(&pcmd, 0, sizeof(pcmd));
- memset(&prx, 0, sizeof(prx));
-
- pcmd.cmd = CMD_SET_LED;
-
- pcmd.cmd_val0 = 0xff;
- for (i = 0; strlen(led_names[i]) != 0; i++) {
- if (strncmp(argv[1], led_names[i], strlen(led_names[i])) == 0) {
- pcmd.cmd_val0 = i;
- break;
- }
- }
-
- if (pcmd.cmd_val0 == 0xff) {
- printf("Usage:\n%s\n", cmdtp->help);
- return -1;
- }
-
- if (argc >= 3) {
- if (strncmp(argv[2], "red", 3) == 0)
- pcmd.cmd_val1 = 1;
- else if (strncmp(argv[2], "green", 5) == 0)
- pcmd.cmd_val1 = 2;
- else if (strncmp(argv[2], "orange", 6) == 0)
- pcmd.cmd_val1 = 3;
- else
- pcmd.cmd_val1 = 0;
- }
-
- if (argc >= 4)
- pcmd.cmd_val2 = simple_strtol(argv[3], NULL, 10);
- else
- pcmd.cmd_val2 = 0;
-
- pcmd.user_out = user_out;
-
- mtc_calculate_checksum(&pcmd);
- err = msp430_xfer(&pcmd, &prx);
-
- return err;
-}
-
-static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- tx_msp_cmd pcmd;
- rx_msp_cmd prx;
- int err;
-
- memset(&pcmd, 0, sizeof(pcmd));
- memset(&prx, 0, sizeof(prx));
-
- pcmd.cmd = CMD_GET_VIM;
- pcmd.user_out = user_out;
-
- mtc_calculate_checksum(&pcmd);
- err = msp430_xfer(&pcmd, &prx);
-
- if (!err) {
- /* function returns '0' if key is pressed */
- err = (prx.input & 0x80) ? 0 : 1;
- }
-
- return err;
-}
-
-static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- tx_msp_cmd pcmd;
- rx_msp_cmd prx;
- int err;
- uchar channel_mask = 0;
-
- if (argc < 3)
- return cmd_usage(cmdtp);
-
- if (strncmp(argv[1], "on", 2) == 0)
- channel_mask |= 1;
- if (strncmp(argv[2], "on", 2) == 0)
- channel_mask |= 2;
-
- memset(&pcmd, 0, sizeof(pcmd));
- memset(&prx, 0, sizeof(prx));
-
- pcmd.cmd = CMD_GET_VIM;
- pcmd.user_out = channel_mask;
- user_out = channel_mask;
-
- mtc_calculate_checksum(&pcmd);
- err = msp430_xfer(&pcmd, &prx);
-
- return err;
-}
-
-static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- tx_msp_cmd pcmd;
- rx_msp_cmd prx;
- int err;
- uchar channel_num = 0;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- channel_num = simple_strtol(argv[1], NULL, 10);
- if ((channel_num != 1) && (channel_num != 2)) {
- printf("mtc digin: invalid parameter - must be '1' or '2'\n");
- return -1;
- }
-
- memset(&pcmd, 0, sizeof(pcmd));
- memset(&prx, 0, sizeof(prx));
-
- pcmd.cmd = CMD_GET_VIM;
- pcmd.user_out = user_out;
-
- mtc_calculate_checksum(&pcmd);
- err = msp430_xfer(&pcmd, &prx);
-
- if (!err) {
- /* function returns '0' when digin is on */
- err = (prx.input & channel_num) ? 0 : 1;
- }
-
- return err;
-}
-
-static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- tx_msp_cmd pcmd;
- rx_msp_cmd prx;
- int err;
- char buf[5];
- uchar appreg;
-
- /* read appreg */
- memset(&pcmd, 0, sizeof(pcmd));
- memset(&prx, 0, sizeof(prx));
-
- pcmd.cmd = CMD_WD_PARA;
- pcmd.cmd_val0 = 5; /* max. Count */
- pcmd.cmd_val1 = 5; /* max. Time */
- pcmd.cmd_val2 = 0; /* =0 means read appreg */
- pcmd.user_out = user_out;
-
- mtc_calculate_checksum(&pcmd);
- err = msp430_xfer(&pcmd, &prx);
-
- /* on success decide between read or write */
- if (!err) {
- if (argc == 2) {
- appreg = simple_strtol(argv[1], NULL, 10);
- if (appreg == 0) {
- printf("mtc appreg: invalid parameter - "
- "must be between 1 and 255\n");
- return -1;
- }
- memset(&pcmd, 0, sizeof(pcmd));
- pcmd.cmd = CMD_WD_PARA;
- pcmd.cmd_val0 = prx.ack3; /* max. Count */
- pcmd.cmd_val1 = prx.ack0; /* max. Time */
- pcmd.cmd_val2 = appreg; /* !=0 means write appreg */
- pcmd.user_out = user_out;
- memset(&prx, 0, sizeof(prx));
-
- mtc_calculate_checksum(&pcmd);
- err = msp430_xfer(&pcmd, &prx);
- } else {
- sprintf(buf, "%d", prx.ack2);
- setenv("appreg", buf);
- }
- }
-
- return err;
-}
-
-static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- tx_msp_cmd pcmd;
- rx_msp_cmd prx;
- int err;
-
- memset(&pcmd, 0, sizeof(pcmd));
- memset(&prx, 0, sizeof(prx));
-
- pcmd.cmd = CMD_FW_VERSION;
- pcmd.user_out = user_out;
-
- mtc_calculate_checksum(&pcmd);
- err = msp430_xfer(&pcmd, &prx);
-
- if (!err) {
- printf("FW V%d.%d.%d / HW %d\n",
- prx.ack0, prx.ack1, prx.ack3, prx.ack2);
- }
-
- return err;
-}
-
-static int do_mtc_state(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- tx_msp_cmd pcmd;
- rx_msp_cmd prx;
- int err;
-
- memset(&pcmd, 0, sizeof(pcmd));
- memset(&prx, 0, sizeof(prx));
-
- pcmd.cmd = CMD_WD_WDSTATE;
- pcmd.cmd_val2 = 1;
- pcmd.user_out = user_out;
-
- mtc_calculate_checksum(&pcmd);
- err = msp430_xfer(&pcmd, &prx);
-
- if (!err) {
- printf("State %02Xh\n", prx.state);
- printf("Input %02Xh\n", prx.input);
- printf("UserWD %02Xh\n", prx.ack2);
- printf("Sys WD %02Xh\n", prx.ack3);
- printf("WD Timout %02Xh\n", prx.ack0);
- printf("eSysState %02Xh\n", prx.ack1);
- }
-
- return err;
-}
-
-static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-cmd_tbl_t cmd_mtc_sub[] = {
- U_BOOT_CMD_MKENT(led, 3, 1, do_mtc_led,
- "set state of leds",
- "[ledname] [state] [blink]\n"
- " - lednames: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
- " - state: off red green orange\n"
- " - blink: blink interval in 100ms steps (1 - 10; 0 = static)\n"),
- U_BOOT_CMD_MKENT(key, 0, 1, do_mtc_key,
- "returns state of user key", ""),
- U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version,
- "returns firmware version of supervisor uC", ""),
- U_BOOT_CMD_MKENT(appreg, 1, 1, do_mtc_appreg,
- "reads or writes appreg value and stores in environment "
- "variable 'appreg'",
- "[value] - value (1 - 255) to write to appreg"),
- U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin,
- "returns state of digital input",
- "<channel_num> - get state of digital input (1 or 2)\n"),
- U_BOOT_CMD_MKENT(digout, 2, 1, do_mtc_digout,
- "sets digital outputs",
- "<on|off> <on|off>- set state of digital output 1 and 2\n"),
- U_BOOT_CMD_MKENT(state, 0, 1, do_mtc_state,
- "displays state", ""),
- U_BOOT_CMD_MKENT(help, 4, 1, do_mtc_help, "get help",
- "[command] - get help for command\n"),
-};
-
-static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- extern int _do_help(cmd_tbl_t *cmd_start, int cmd_items,
- cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[]);
-#ifdef CONFIG_SYS_LONGHELP
- puts("mtc ");
-#endif
- return _do_help(&cmd_mtc_sub[0],
- ARRAY_SIZE(cmd_mtc_sub), cmdtp, flag, argc, argv);
-}
-
-int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- cmd_tbl_t *c;
- int err = 0;
-
- c = find_cmd_tbl(argv[1], &cmd_mtc_sub[0], ARRAY_SIZE(cmd_mtc_sub));
- if (c) {
- argc--;
- argv++;
- return c->cmd(c, flag, argc, argv);
- } else {
- /* Unrecognized command */
- return cmd_usage(cmdtp);
- }
-
- return err;
-}
-
-U_BOOT_CMD(mtc, 5, 1, cmd_mtc,
- "special commands for digsyMTC",
- "[subcommand] [args...]\n"
- "Subcommands list:\n"
- "led [ledname] [state] [blink] - set state of leds\n"
- " [ledname]: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
- " [state]: off red green orange\n"
- " [blink]: blink interval in 100ms steps (1 - 10; 0 = static)\n"
- "key - returns state of user key\n"
- "version - returns firmware version of supervisor uC\n"
- "appreg [value] - reads (in environment variable 'appreg') or writes"
- " appreg value\n"
- " [value]: value (1 - 255) to write to appreg\n"
- "digin [channel] - returns state of digital input (1 or 2)\n"
- "digout <on|off> <on|off> - sets state of two digital outputs\n"
- "state - displays state\n"
- "help [subcommand] - get help for subcommand\n"
-);
diff --git a/board/intercontrol/digsy_mtc/cmd_mtc.h b/board/intercontrol/digsy_mtc/cmd_mtc.h
deleted file mode 100644
index 4493433..0000000
--- a/board/intercontrol/digsy_mtc/cmd_mtc.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * (C) Copyright 2009
- * Werner Pfister <Pfister_Werner@intercontrol.de>
- *
- * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef CMD_MTC_H
-#define CMD_MTC_H
-
-#define CMD_WD_PARA 0x02
-#define CMD_WD_WDSTATE 0x04
-#define CMD_FW_VERSION 0x10
-#define CMD_GET_VIM 0x30
-#define CMD_SET_LED 0x40
-
-typedef struct {
- u8 cmd;
- u8 sys_in;
- u8 cmd_val0;
- u8 cmd_val1;
- u8 cmd_val2;
- u8 user_out;
- u8 cks;
- u8 dummy1;
- u8 dummy2;
-} tx_msp_cmd;
-
-typedef struct {
- u8 input;
- u8 state;
- u8 ack2;
- u8 ack3;
- u8 ack0;
- u8 ack1;
- u8 ack;
- u8 dummy;
- u8 cks;
-} rx_msp_cmd;
-
-#define MTC_TRANSFER_SIZE (sizeof(tx_msp_cmd) * 8)
-
-#endif
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
index 2e52d51..05d673d 100644
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -41,7 +41,7 @@
#if defined(CONFIG_DIGSY_REV5)
/*
- * The M29W128GH needs a specail reset command function,
+ * The M29W128GH needs a special reset command function,
* details see the doc/README.cfi file
*/
void flash_cmd_reset(flash_info_t *info)
@@ -76,7 +76,7 @@
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ * CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
*/
phys_size_t initdram(int board_type)
@@ -250,9 +250,6 @@
int board_early_init_r(void)
{
-#ifdef CONFIG_MPC52XX_SPI
- struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
-#endif
/*
* Now, when we are in RAM, enable flash write access for detection
* process. Note that CS_BOOT cannot be cleared when executing in
@@ -269,12 +266,6 @@
/* Low level USB init, required for proper kernel operation */
usb_cpu_init();
#endif
-#ifdef CONFIG_MPC52XX_SPI
- /* GPT 6 Output Enable */
- out_be32(&gpt[6].emsr, 0x00000034);
- /* GPT 7 Output Enable */
- out_be32(&gpt[7].emsr, 0x00000034);
-#endif
return (0);
}
diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c
index c875e78..2f6bc3a 100644
--- a/board/inversepath/usbarmory/usbarmory.c
+++ b/board/inversepath/usbarmory/usbarmory.c
@@ -15,7 +15,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
index 67ea1ec..8ce3c70 100644
--- a/board/is1/qts/sdram_config.h
+++ b/board/is1/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 808955e..669f3dd 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -27,24 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
- "IGEPv2",
-#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
- "IGEP COM MODULE/ELECTRON",
-#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
- "IGEP COM PROTON",
-#endif
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "ONENAND",
-#else
- "NAND",
-#endif
-};
-
static const struct ns16550_platdata igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
@@ -102,10 +84,22 @@
int mfr, id, err = identify_nand_chip(&mfr, &id);
timings->mr = MICRON_V_MR_165;
- if (!err && mfr == NAND_MFR_MICRON) {
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
+ if (!err) {
+ switch (mfr) {
+ case NAND_MFR_HYNIX:
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ break;
+ case NAND_MFR_MICRON:
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ break;
+ default:
+ /* Should not happen... */
+ break;
+ }
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
} else {
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index 51a3cfe..6f8d696 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
#define KM_XLX_PROGRAM_B_PIN 39
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index eebb47f..abb2019 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -277,7 +277,7 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_PCI
diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c
index 2b0b054..b827e43 100644
--- a/board/keymile/kmp204x/pci.c
+++ b/board/keymile/kmp204x/pci.c
@@ -14,7 +14,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "kmp204x.h"
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
index b3159d3..f6972c2 100644
--- a/board/kosagi/novena/novena.c
+++ b/board/kosagi/novena/novena.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index 92c61ae..b934d36 100644
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -605,8 +605,8 @@
/* Perform DDR DRAM calibration */
udelay(100);
- mmdc_do_write_level_calibration();
- mmdc_do_dqs_calibration();
+ mmdc_do_write_level_calibration(&novena_ddr_info);
+ mmdc_do_dqs_calibration(&novena_ddr_info);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c
index 3bb1b71..a4c1222 100644
--- a/board/kosagi/novena/video.c
+++ b/board/kosagi/novena/video.c
@@ -11,7 +11,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c
index a791b97..d757d97 100644
--- a/board/lego/ev3/legoev3.c
+++ b/board/lego/ev3/legoev3.c
@@ -23,7 +23,7 @@
#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <hwconfig.h>
#ifdef CONFIG_DAVINCI_MMC
diff --git a/board/liebherr/lwmon5/Kconfig b/board/liebherr/lwmon5/Kconfig
index 7f1bb40..ec8349d 100644
--- a/board/liebherr/lwmon5/Kconfig
+++ b/board/liebherr/lwmon5/Kconfig
@@ -9,8 +9,4 @@
config SYS_CONFIG_NAME
default "lwmon5"
-config DISPLAY_BOARDINFO
- bool
- default y
-
endif
diff --git a/board/liebherr/lwmon5/lwmon5.c b/board/liebherr/lwmon5/lwmon5.c
index 8ad6712..bb99a3b 100644
--- a/board/liebherr/lwmon5/lwmon5.c
+++ b/board/liebherr/lwmon5/lwmon5.c
@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <post.h>
#include <flash.h>
+#include <video.h>
#include <mtd/cfi_flash.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index 1f1e5ae..a6aff4e 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -21,7 +21,7 @@
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/musb.h>
#include <asm/mach-types.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index c2bb730..de6a060 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -28,7 +28,7 @@
#include <asm/mach-types.h>
#include <linux/mtd/nand.h>
#include <asm/omap_musb.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
@@ -219,6 +219,10 @@
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+ /* If we do not have an fdtimage, let's autodetect it*/
+ if (getenv("fdtimage"))
+ return 0;
+
switch (gd->bd->bi_arch_number) {
case MACH_TYPE_DM3730_TORPEDO:
setenv("fdtimage", "logicpd-torpedo-37xx-devkit.dtb");
diff --git a/board/micronas/vct/dcgu.c b/board/micronas/vct/dcgu.c
index 20ee3ac..562c827 100644
--- a/board/micronas/vct/dcgu.c
+++ b/board/micronas/vct/dcgu.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "vct.h"
diff --git a/board/micronas/vct/scc.c b/board/micronas/vct/scc.c
index 40f8ecd..0d33cc4 100644
--- a/board/micronas/vct/scc.c
+++ b/board/micronas/vct/scc.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "vct.h"
diff --git a/board/mosaixtech/icon/icon.c b/board/mosaixtech/icon/icon.c
index e3fb1e6..7558234 100644
--- a/board/mosaixtech/icon/icon.c
+++ b/board/mosaixtech/icon/icon.c
@@ -11,11 +11,12 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <netdev.h>
+#include <video.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/4xx_pcie.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c
index 688cc12..234a387 100644
--- a/board/mpc8308_p1m/mpc8308_p1m.c
+++ b/board/mpc8308_p1m/mpc8308_p1m.c
@@ -65,7 +65,7 @@
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
return 0;
}
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 2262175..101b6ef 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -15,12 +15,13 @@
#include <pci.h>
#include <malloc.h>
#include <bzlib.h>
+#include <video.h>
#ifdef CONFIG_PIP405
#include "../pip405/pip405.h"
#include <asm/4xx_pci.h>
#endif
-#ifdef CONFIG_MIP405
+#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
#include "../mip405/mip405.h"
#include <asm/4xx_pci.h>
#endif
@@ -36,7 +37,8 @@
#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN /* ugly, but it works for now */
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
+#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
+ || defined(CONFIG_TARGET_MIP405T)
/*-----------------------------------------------------------------------
* On PIP/MIP405 we have 3 (4) possible boot mode
*
@@ -116,7 +118,7 @@
mtdcr(EBC0_CFGDATA, FLASH_CR_B);
}
}
-#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) */
+#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) */
#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
/* adjust flash start and protection info */
@@ -190,12 +192,11 @@
#if defined(CONFIG_PATI)
int start_sect;
#endif
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
+#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
+ || defined(CONFIG_TARGET_MIP405T) || defined(CONFIG_PATI)
char *copystr = (char *)src;
ulong *magic = (ulong *)src;
-#endif
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
if (uimage_to_cpu (magic[0]) != IH_MAGIC) {
puts("Bad Magic number\n");
return -1;
@@ -241,7 +242,7 @@
return (1);
}
-#else /* #if !defined(CONFIG_PATI */
+#else /* #if !defined(CONFIG_PATI) */
start = FIRM_START;
start_sect = -1;
@@ -272,29 +273,6 @@
return (1);
}
#endif /* defined(CONFIG_PATI) */
-
-#elif defined(CONFIG_VCMA9)
- start = 0;
-
- /* search end sector */
- for (i = 0; i < info->sector_count; i++)
- if (size < info->start[i])
- break;
-
- flash_protect(FLAG_PROTECT_CLEAR,
- start,
- size,
- info);
-
- /* now erase flash */
- printf("Erasing at %lx (sector %d) (start %lx)\n",
- start,0,info->start[0]);
- if ((rc = flash_erase (info, 0, i)) != 0) {
- puts("ERROR ");
- flash_perror(rc);
- return (1);
- }
-
#endif
printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
(ulong)src, size);
@@ -701,7 +679,7 @@
strcpy(buf,"### No HW ID - assuming PIP405");
}
#endif
-#ifdef CONFIG_MIP405
+#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
if (!s || strncmp (s, "MIP405", 6)) {
strcpy(buf,"### No HW ID - assuming MIP405");
}
diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h
index e81ee35..22f5c2e 100644
--- a/board/mpl/common/common_util.h
+++ b/board/mpl/common/common_util.h
@@ -17,12 +17,10 @@
void get_backup_values(backup_t *buf);
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
#define BOOT_MPS 0x01
#define BOOT_PCI 0x02
int get_boot_mode(void);
void setup_cs_reloc(void);
-#endif
void check_env(void);
#if defined(CONFIG_CMD_DOC)
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
index 4193e92..75e8cae 100644
--- a/board/mpl/common/pci_parts.h
+++ b/board/mpl/common/pci_parts.h
@@ -91,7 +91,7 @@
static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
{PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
{PCI_COMMAND, 0x0001, 2}, /* enable IO access */
-#if !defined(CONFIG_MIP405T)
+#if !defined(CONFIG_TARGET_MIP405T)
{PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
#else
{PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */
@@ -101,7 +101,7 @@
/* PIIX4 USB Controller Function 2 */
static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
-#if !defined(CONFIG_MIP405T)
+#if !defined(CONFIG_TARGET_MIP405T)
{PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
{PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */
{PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */
diff --git a/board/mpl/mip405/Kconfig b/board/mpl/mip405/Kconfig
index 48ba91a..e003a43 100644
--- a/board/mpl/mip405/Kconfig
+++ b/board/mpl/mip405/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_MIP405
+if TARGET_MIP405 || TARGET_MIP405T
config SYS_BOARD
default "mip405"
@@ -9,4 +9,9 @@
config SYS_CONFIG_NAME
default "MIP405"
+config ISO_STRING
+ string
+ default "MEV-10082-001" if TARGET_MIP405T
+ default "MEV-10072-001" if TARGET_MIP405
+
endif
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 4a0d696..8b9892b 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -92,7 +92,7 @@
unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
unsigned char ecc; /* if true, ecc is enabled */
} sdram_t;
-#if defined(CONFIG_MIP405T)
+#if defined(CONFIG_TARGET_MIP405T)
const sdram_t sdram_table[] = {
{ 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
3, /* Case Latenty = 3 */
@@ -168,7 +168,7 @@
0xff,
0xff }
};
-#endif /*CONFIG_MIP405T */
+#endif /*CONFIG_TARGET_MIP405T */
void SDRAM_err (const char *s)
{
#ifndef SDRAM_DEBUG
@@ -262,7 +262,7 @@
#endif
/* check board */
bc = in8 (PLD_PART_REG);
-#if defined(CONFIG_MIP405T)
+#if defined(CONFIG_TARGET_MIP405T)
if((bc & 0x80)==0)
SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
#else
@@ -543,7 +543,7 @@
void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
{
-#if !defined(CONFIG_MIP405T)
+#if !defined(CONFIG_TARGET_MIP405T)
unsigned char bc,rc,tmp;
int i;
@@ -575,7 +575,7 @@
* Check Board Identity:
*/
/* serial String: "MIP405_1000" OR "MIP405T_1000" */
-#if !defined(CONFIG_MIP405T)
+#if !defined(CONFIG_TARGET_MIP405T)
#define BOARD_NAME "MIP405"
#else
#define BOARD_NAME "MIP405T"
@@ -777,7 +777,7 @@
(cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
-#if !defined(CONFIG_MIP405T)
+#if !defined(CONFIG_TARGET_MIP405T)
printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
@@ -793,7 +793,7 @@
printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
printf ("IRQs:\n");
printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
-#if !defined(CONFIG_MIP405T)
+#if !defined(CONFIG_TARGET_MIP405T)
printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
#endif
diff --git a/board/mpl/pati/Kconfig b/board/mpl/pati/Kconfig
index b141da3..0eeaf70 100644
--- a/board/mpl/pati/Kconfig
+++ b/board/mpl/pati/Kconfig
@@ -9,4 +9,7 @@
config SYS_CONFIG_NAME
default "PATI"
+config ISO_STRING
+ string
+ default "MEV-10084-001"
endif
diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h
index 2600bba..93a5918 100644
--- a/board/mpl/pati/pati.h
+++ b/board/mpl/pati/pati.h
@@ -201,9 +201,8 @@
#define PCI_VENDOR_ID_MPL 0x18E6
#define PCI_DEVICE_ID_PATI 0x00DA
-#if defined(CONFIG_MIP405)
+#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
#define PATI_FIRMWARE_START_OFFSET 0x00300000
-#define PATI_ISO_STRING "MEV-10084-001"
#endif
#define PATI_ENDIAN_MODE 0x3E
diff --git a/board/mpl/pip405/Kconfig b/board/mpl/pip405/Kconfig
index f485367..e7ae6af 100644
--- a/board/mpl/pip405/Kconfig
+++ b/board/mpl/pip405/Kconfig
@@ -9,4 +9,7 @@
config SYS_CONFIG_NAME
default "PIP405"
+config ISO_STRING
+ string
+ default "MEV-10066-001"
endif
diff --git a/board/mpl/vcma9/Kconfig b/board/mpl/vcma9/Kconfig
deleted file mode 100644
index a156452..0000000
--- a/board/mpl/vcma9/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_VCMA9
-
-config SYS_BOARD
- default "vcma9"
-
-config SYS_VENDOR
- default "mpl"
-
-config SYS_SOC
- default "s3c24x0"
-
-config SYS_CONFIG_NAME
- default "VCMA9"
-
-endif
diff --git a/board/mpl/vcma9/MAINTAINERS b/board/mpl/vcma9/MAINTAINERS
deleted file mode 100644
index 3817436..0000000
--- a/board/mpl/vcma9/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VCMA9 BOARD
-M: David Müller <d.mueller@elsoft.ch>
-S: Maintained
-F: board/mpl/vcma9/
-F: include/configs/VCMA9.h
-F: configs/VCMA9_defconfig
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
deleted file mode 100644
index 175a19f..0000000
--- a/board/mpl/vcma9/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ../common/common_util.o
-obj-y += vcma9.o cmd_vcma9.o
-
-obj-y += lowlevel_init.o
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
deleted file mode 100644
index c2d62e4..0000000
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * (C) Copyright 2002
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * adapted for VCMA9
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include "vcma9.h"
-#include "../common/common_util.h"
-
-#if defined(CONFIG_CS8900)
-#include <../drivers/net/cs8900.h>
-
-static uchar cs8900_chksum(ushort data)
-{
- return((data >> 8) & 0x00FF) + (data & 0x00FF);
-}
-
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct eth_device *dev;
- char cs8900_name[10];
- if (strcmp(argv[1], "info") == 0)
- {
- vcma9_print_info();
- return 0;
- }
-#if defined(CONFIG_CS8900)
- if (strcmp(argv[1], "cs8900") == 0) {
- sprintf(cs8900_name, "%s-0", CS8900_DRIVERNAME);
- dev = eth_get_dev_by_name(cs8900_name);
- if (!dev) {
- printf("Couldn't find CS8900 driver");
- return 0;
- }
- if (strcmp(argv[2], "read") == 0) {
- uchar addr; ushort data;
-
- addr = simple_strtoul(argv[3], NULL, 16);
- cs8900_e2prom_read(dev, addr, &data);
- printf("0x%2.2X: 0x%4.4X\n", addr, data);
- } else if (strcmp(argv[2], "write") == 0) {
- uchar addr; ushort data;
-
- addr = simple_strtoul(argv[3], NULL, 16);
- data = simple_strtoul(argv[4], NULL, 16);
- cs8900_e2prom_write(dev, addr, data);
- } else if (strcmp(argv[2], "setaddr") == 0) {
- uchar addr, i, csum; ushort data;
- uchar ethaddr[6];
-
- /* check for valid ethaddr */
- if (eth_getenv_enetaddr("ethaddr", ethaddr)) {
- addr = 1;
- data = 0x2158;
- cs8900_e2prom_write(dev, addr, data);
- csum = cs8900_chksum(data);
- addr++;
- for (i = 0; i < 6; i+=2) {
- data = ethaddr[i+1] << 8 |
- ethaddr[i];
- cs8900_e2prom_write(dev, addr, data);
- csum += cs8900_chksum(data);
- addr++;
- }
- /* calculate header link byte */
- data = 0xA100 | (addr * 2);
- cs8900_e2prom_write(dev, 0, data);
- csum += cs8900_chksum(data);
- /* write checksum word */
- cs8900_e2prom_write(dev, addr, (0 - csum) << 8);
- } else {
- puts("\nplease defined 'ethaddr'\n");
- }
- } else if (strcmp(argv[2], "dump") == 0) {
- uchar addr = 0, endaddr, csum; ushort data;
-
- puts("Dump of CS8900 config device: ");
- cs8900_e2prom_read(dev, addr, &data);
- if ((data & 0xE000) == 0xA000) {
- endaddr = (data & 0x00FF) / 2;
- csum = cs8900_chksum(data);
- for (addr = 1; addr <= endaddr; addr++) {
- cs8900_e2prom_read(dev, addr, &data);
- printf("\n0x%2.2X: 0x%4.4X", addr, data);
- csum += cs8900_chksum(data);
- }
- printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong");
- } else {
- puts("no valid config found");
- }
- puts("\n");
- }
-
- return 0;
- }
-#endif
-
- return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-
-U_BOOT_CMD(
- vcma9, 6, 1, do_vcma9,
- "VCMA9 specific commands",
- "flash mem [SrcAddr] - updates U-Boot with image in memory\n"
- "vcma9 info - displays board information"
-);
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
deleted file mode 100644
index c0d6cc8..0000000
--- a/board/mpl/vcma9/lowlevel_init.S
+++ /dev/null
@@ -1,500 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for MPL VCMA9 by
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- * (C) Copyright 2002, 2003, 2004, 2005
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <config.h>
-
-/* register definitions */
-
-#define PLD_BASE 0x28000000
-#define MISC_REG 0x103
-#define SDRAM_REG 0x106
-#define BWSCON 0x48000000
-#define CLKBASE 0x4C000000
-#define LOCKTIME 0x0
-#define MPLLCON 0x4
-#define UPLLCON 0x8
-#define GPIOBASE 0x56000000
-#define GSTATUS1 0xB0
-#define FASTCPU 0x02
-
-/* some parameters for the board */
-/* BWSCON */
-#define DW8 (0x0)
-#define DW16 (0x1)
-#define DW32 (0x2)
-#define WAIT (0x1<<2)
-#define UBLB (0x1<<3)
-
-/* BANKSIZE */
-#define BURST_EN (0x1<<7)
-
-/* BANK0CON 200 */
-#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
-#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
-#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
-#define B0_Tcoh_200 0x0 /* 0clk */
-#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */
-#define B0_Tacp_200 0x0 /* page mode is not used */
-#define B0_PMC_200 0x0 /* page mode disabled */
-
-/* BANK0CON 250 */
-#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
-#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
-#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
-#define B0_Tcoh_250 0x0 /* 0clk */
-#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
-#define B0_Tacp_250 0x0 /* page mode is not used */
-#define B0_PMC_250 0x0 /* page mode disabled */
-
-/* BANK0CON 266 */
-#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
-#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
-#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
-#define B0_Tcoh_266 0x0 /* 0clk */
-#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
-#define B0_Tacp_266 0x0 /* page mode is not used */
-#define B0_PMC_266 0x0 /* page mode disabled */
-
-/* BANK1CON 200 */
-#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
-#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
-#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
-#define B1_Tcoh_200 0x0 /* 0clk */
-#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */
-#define B1_Tacp_200 0x0 /* page mode is not used */
-#define B1_PMC_200 0x0 /* page mode disabled */
-
-/* BANK1CON 250 */
-#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
-#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
-#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
-#define B1_Tcoh_250 0x0 /* 0clk */
-#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
-#define B1_Tacp_250 0x0 /* page mode is not used */
-#define B1_PMC_250 0x0 /* page mode disabled */
-
-/* BANK1CON 266 */
-#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
-#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
-#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
-#define B1_Tcoh_266 0x0 /* 0clk */
-#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
-#define B1_Tacp_266 0x0 /* page mode is not used */
-#define B1_PMC_266 0x0 /* page mode disabled */
-
-/* BANK2CON 200 + 250 + 266 */
-#define B2_Tacs 0x3 /* 4clk */
-#define B2_Tcos 0x3 /* 4clk */
-#define B2_Tacc 0x7 /* 14clk */
-#define B2_Tcoh 0x3 /* 4clk */
-#define B2_Tcah 0x3 /* 4clk */
-#define B2_Tacp 0x0 /* page mode is not used */
-#define B2_PMC 0x0 /* page mode disabled */
-
-/* BANK3CON 200 + 250 + 266 */
-#define B3_Tacs 0x3 /* 4clk */
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7 /* 14clk */
-#define B3_Tcoh 0x3 /* 4clk */
-#define B3_Tcah 0x3 /* 4clk */
-#define B3_Tacp 0x0 /* page mode is not used */
-#define B3_PMC 0x0 /* page mode disabled */
-
-/* BANK4CON 200 */
-#define B4_Tacs_200 0x1 /* 1clk */
-#define B4_Tcos_200 0x3 /* 4clk */
-#define B4_Tacc_200 0x7 /* 14clk */
-#define B4_Tcoh_200 0x3 /* 4clk */
-#define B4_Tcah_200 0x2 /* 2clk */
-#define B4_Tacp_200 0x0 /* page mode is not used */
-#define B4_PMC_200 0x0 /* page mode disabled */
-
-/* BANK4CON 250 */
-#define B4_Tacs_250 0x1 /* 1clk */
-#define B4_Tcos_250 0x3 /* 4clk */
-#define B4_Tacc_250 0x7 /* 14clk */
-#define B4_Tcoh_250 0x3 /* 4clk */
-#define B4_Tcah_250 0x2 /* 2clk */
-#define B4_Tacp_250 0x0 /* page mode is not used */
-#define B4_PMC_250 0x0 /* page mode disabled */
-
-/* BANK4CON 266 */
-#define B4_Tacs_266 0x1 /* 1clk */
-#define B4_Tcos_266 0x3 /* 4clk */
-#define B4_Tacc_266 0x7 /* 14clk */
-#define B4_Tcoh_266 0x3 /* 4clk */
-#define B4_Tcah_266 0x2 /* 2clk */
-#define B4_Tacp_266 0x0 /* page mode is not used */
-#define B4_PMC_266 0x0 /* page mode disabled */
-
-/* BANK5CON 200 */
-#define B5_Tacs_200 0x0 /* 0clk */
-#define B5_Tcos_200 0x3 /* 4clk */
-#define B5_Tacc_200 0x4 /* 6clk */
-#define B5_Tcoh_200 0x3 /* 4clk */
-#define B5_Tcah_200 0x1 /* 1clk */
-#define B5_Tacp_200 0x0 /* page mode is not used */
-#define B5_PMC_200 0x0 /* page mode disabled */
-
-/* BANK5CON 250 */
-#define B5_Tacs_250 0x0 /* 0clk */
-#define B5_Tcos_250 0x3 /* 4clk */
-#define B5_Tacc_250 0x5 /* 8clk */
-#define B5_Tcoh_250 0x3 /* 4clk */
-#define B5_Tcah_250 0x1 /* 1clk */
-#define B5_Tacp_250 0x0 /* page mode is not used */
-#define B5_PMC_250 0x0 /* page mode disabled */
-
-/* BANK5CON 266 */
-#define B5_Tacs_266 0x0 /* 0clk */
-#define B5_Tcos_266 0x3 /* 4clk */
-#define B5_Tacc_266 0x5 /* 8clk */
-#define B5_Tcoh_266 0x3 /* 4clk */
-#define B5_Tcah_266 0x1 /* 1clk */
-#define B5_Tacp_266 0x0 /* page mode is not used */
-#define B5_PMC_266 0x0 /* page mode disabled */
-
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd_200 0x0 /* 2clk */
-#define B6_Trcd_250 0x1 /* 3clk */
-#define B6_Trcd_266 0x1 /* 3clk */
-#define B6_SCAN 0x2 /* 10bit */
-
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd_200 0x0 /* 2clk */
-#define B7_Trcd_250 0x1 /* 3clk */
-#define B7_Trcd_266 0x1 /* 3clk */
-#define B7_SCAN 0x2 /* 10bit */
-
-/* REFRESH parameter */
-#define REFEN 0x1 /* Refresh enable */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
-#define Trp_200 0x0 /* 2clk */
-#define Trp_250 0x1 /* 3clk */
-#define Trp_266 0x1 /* 3clk */
-#define Tsrc_200 0x1 /* 5clk */
-#define Tsrc_250 0x2 /* 6clk */
-#define Tsrc_266 0x3 /* 7clk */
-
-/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
-#define REFCNT_200 489
-/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
-#define REFCNT_250 99
-/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
-#define REFCNT_266 0
-/**************************************/
-
-.globl lowlevel_init
-lowlevel_init:
- /* use r0 to relocate DATA read/write to flash rather than memory ! */
- ldr r0, =CONFIG_SYS_TEXT_BASE
- ldr r13, =BWSCON
-
- /* enable minimal access to PLD */
- ldr r1, [r13] /* load default BWSCON */
- orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */
- str r1, [r13] /* set BWSCON */
- ldr r1, =0x7FF0 /* select slowest timing */
- str r1, [r13, #0x18] /* set BANKCON5 */
-
- ldr r1, =PLD_BASE
- ldr r2, =SETUPDATA
- ldrb r1, [r1, #MISC_REG]
- sub r2, r2, r0
- tst r1, #FASTCPU /* FASTCPU available ? */
- addeq r2, r2, #SETUPENTRY_SIZE
-
- /* memory control configuration */
- /* r2 = pointer into timing table */
- /* r13 = pointer to MEM controller regs (starting with BWSCON) */
- add r3, r2, #CSDATA_OFFSET
- add r4, r3, #CSDATAENTRY_SIZE
-0:
- ldr r1, [r3], #4
- str r1, [r13], #4
- cmp r3, r4
- bne 0b
-
- /* PLD access is now possible */
- /* r3 = SDRAMDATA */
- /* r13 = pointer to MEM controller regs */
- ldr r1, =PLD_BASE
- mov r4, #SDRAMENTRY_SIZE
- ldrb r1, [r1, #SDRAM_REG]
- /* calculate start and end point */
- mla r3, r4, r1, r3
- add r4, r3, r4
-0:
- ldr r1, [r3], #4
- str r1, [r13], #4
- cmp r3, r4
- bne 0b
-
- /* setup MPLL registers */
- ldr r1, =CLKBASE
- ldr r4, =0xFFFFFF
- add r3, r2, #4 /* r3 points to PLL values */
- str r4, [r1, #LOCKTIME]
- ldmia r3, {r4,r5}
- str r5, [r1, #UPLLCON] /* writing PLL register */
- /* !! order seems to be important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subs r3, r3, #1
- bne 0b
-
- str r4, [r1, #MPLLCON] /* writing PLL register */
- /* !! order seems to be important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subs r3, r3, #1
- bne 0b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-/* the literal pools origin */
-
-#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
- ((bws1) << 4) + \
- ((bws2) << 8) + \
- ((bws3) << 12) + \
- ((bws4) << 16) + \
- ((bws5) << 20) + \
- ((bws6) << 24) + \
- ((bws7) << 28)
-
-#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
- ((tacs) << 13) + \
- ((tcos) << 11) + \
- ((tacc) << 8) + \
- ((tcoh) << 6) + \
- ((tcah) << 4) + \
- ((tacp) << 2) + \
- (pmc)
-
-#define MK_BANKCON_SDRAM(trcd, scan) \
- ((0x03) << 15) + \
- ((trcd) << 2) + \
- (scan)
-
-#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
- ((enable) << 23) + \
- ((trefmd) << 22) + \
- ((trp) << 20) + \
- ((tsrc) << 18) + \
- (cnt)
-
-SETUPDATA:
- .word 0x32410002
- /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
- .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
- /* PLL values for USB clock */
- .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
-
- /* timing for 250 MHz*/
-0:
- .equiv CSDATA_OFFSET, (. - SETUPDATA)
- .word MK_BWSCON(DW16, \
- DW32, \
- DW32, \
- DW16 + WAIT + UBLB, \
- DW8 + UBLB, \
- DW32, \
- DW32)
-
- .word MK_BANKCON(B0_Tacs_250, \
- B0_Tcos_250, \
- B0_Tacc_250, \
- B0_Tcoh_250, \
- B0_Tcah_250, \
- B0_Tacp_250, \
- B0_PMC_250)
-
- .word MK_BANKCON(B1_Tacs_250, \
- B1_Tcos_250, \
- B1_Tacc_250, \
- B1_Tcoh_250, \
- B1_Tcah_250, \
- B1_Tacp_250, \
- B1_PMC_250)
-
- .word MK_BANKCON(B2_Tacs, \
- B2_Tcos, \
- B2_Tacc, \
- B2_Tcoh, \
- B2_Tcah, \
- B2_Tacp, \
- B2_PMC)
-
- .word MK_BANKCON(B3_Tacs, \
- B3_Tcos, \
- B3_Tacc, \
- B3_Tcoh, \
- B3_Tcah, \
- B3_Tacp, \
- B3_PMC)
-
- .word MK_BANKCON(B4_Tacs_250, \
- B4_Tcos_250, \
- B4_Tacc_250, \
- B4_Tcoh_250, \
- B4_Tcah_250, \
- B4_Tacp_250, \
- B4_PMC_250)
-
- .word MK_BANKCON(B5_Tacs_250, \
- B5_Tcos_250, \
- B5_Tacc_250, \
- B5_Tcoh_250, \
- B5_Tcah_250, \
- B5_Tacp_250, \
- B5_PMC_250)
-
- .equiv CSDATAENTRY_SIZE, (. - 0b)
- /* 4Mx8x4 */
-0:
- .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
- .equiv SDRAMENTRY_SIZE, (. - 0b)
-
- /* 8Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 2Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 4Mx8x2 */
- .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- .equiv SETUPENTRY_SIZE, (. - SETUPDATA)
-
- .word 0x32410000
- /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
- .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
- /* PLL values for USB clock */
- .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
-
- /* timing for 200 MHz and default*/
- .word MK_BWSCON(DW16, \
- DW32, \
- DW32, \
- DW16 + WAIT + UBLB, \
- DW8 + UBLB, \
- DW32, \
- DW32)
-
- .word MK_BANKCON(B0_Tacs_200, \
- B0_Tcos_200, \
- B0_Tacc_200, \
- B0_Tcoh_200, \
- B0_Tcah_200, \
- B0_Tacp_200, \
- B0_PMC_200)
-
- .word MK_BANKCON(B1_Tacs_200, \
- B1_Tcos_200, \
- B1_Tacc_200, \
- B1_Tcoh_200, \
- B1_Tcah_200, \
- B1_Tacp_200, \
- B1_PMC_200)
-
- .word MK_BANKCON(B2_Tacs, \
- B2_Tcos, \
- B2_Tacc, \
- B2_Tcoh, \
- B2_Tcah, \
- B2_Tacp, \
- B2_PMC)
-
- .word MK_BANKCON(B3_Tacs, \
- B3_Tcos, \
- B3_Tacc, \
- B3_Tcoh, \
- B3_Tcah, \
- B3_Tacp, \
- B3_PMC)
-
- .word MK_BANKCON(B4_Tacs_200, \
- B4_Tcos_200, \
- B4_Tacc_200, \
- B4_Tcoh_200, \
- B4_Tcah_200, \
- B4_Tacp_200, \
- B4_PMC_200)
-
- .word MK_BANKCON(B5_Tacs_200, \
- B5_Tcos_200, \
- B5_Tacc_200, \
- B5_Tcoh_200, \
- B5_Tcah_200, \
- B5_Tacp_200, \
- B5_PMC_200)
-
- /* 4Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 8Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 2Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 4Mx8x2 */
- .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- .equiv SETUPDATA_SIZE, (. - SETUPDATA)
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
deleted file mode 100644
index 43a3d47..0000000
--- a/board/mpl/vcma9/vcma9.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002, 2010
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-#include "vcma9.h"
-#include "../common/common_util.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f(void)
-{
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
- /* set up the I/O ports */
- writel(0x007FFFFF, &gpio->gpacon);
- writel(0x002AAAAA, &gpio->gpbcon);
- writel(0x000002BF, &gpio->gpbup);
- writel(0xAAAAAAAA, &gpio->gpccon);
- writel(0x0000FFFF, &gpio->gpcup);
- writel(0xAAAAAAAA, &gpio->gpdcon);
- writel(0x0000FFFF, &gpio->gpdup);
- writel(0xAAAAAAAA, &gpio->gpecon);
- writel(0x000037F7, &gpio->gpeup);
- writel(0x00000000, &gpio->gpfcon);
- writel(0x00000000, &gpio->gpfup);
- writel(0xFFEAFF5A, &gpio->gpgcon);
- writel(0x0000F0DC, &gpio->gpgup);
- writel(0x0028AAAA, &gpio->gphcon);
- writel(0x00000656, &gpio->gphup);
-
- /* setup correct IRQ modes for NIC (rising edge mode) */
- writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2);
-
- /* select USB port 2 to be host or device (setup as host for now) */
- writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x30000100;
-
- icache_enable();
- dcache_enable();
-
- return 0;
-}
-
-/*
- * Get some Board/PLD Info
- */
-
-static u8 get_pld_reg(enum vcma9_pld_regs reg)
-{
- return readb(VCMA9_PLD_BASE + reg);
-}
-
-static u8 get_pld_version(void)
-{
- return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F;
-}
-
-static u8 get_pld_revision(void)
-{
- return get_pld_reg(VCMA9_PLD_ID) & 0x0F;
-}
-
-static uchar get_board_pcb(void)
-{
- return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A';
-}
-
-static u8 get_nr_chips(void)
-{
- switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) {
- case 0: return 4;
- case 1: return 1;
- case 2: return 2;
- default: return 0;
- }
-}
-
-static ulong get_chip_size(void)
-{
- switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
- case 0: return 16 * (1024*1024);
- case 1: return 32 * (1024*1024);
- case 2: return 8 * (1024*1024);
- case 3: return 8 * (1024*1024);
- default: return 0;
- }
-}
-
-static const char *get_chip_geom(void)
-{
- switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
- case 0: return "4Mx8x4";
- case 1: return "8Mx8x4";
- case 2: return "2Mx8x4";
- case 3: return "4Mx8x2";
- default: return "unknown";
- }
-}
-
-static void vcma9_show_info(char *board_name, char *serial)
-{
- printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
- board_name, serial,
- get_board_pcb(), get_pld_version(), get_pld_revision());
- printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom());
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_chip_size() * get_nr_chips();
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard(void)
-{
- char s[50];
- int i;
- backup_t *b = (backup_t *) s;
-
- i = getenv_f("serial#", s, 32);
- if ((i < 0) || strncmp (s, "VCMA9", 5)) {
- get_backup_values (b);
- if (strncmp (b->signature, "MPL\0", 4) != 0) {
- puts ("### No HW ID - assuming VCMA9");
- } else {
- b->serial_name[5] = 0;
- vcma9_show_info(b->serial_name, &b->serial_name[6]);
- }
- } else {
- s[5] = 0;
- vcma9_show_info(s, &s[6]);
- }
-
- return 0;
-}
-
-int board_late_init(void)
-{
- /*
- * check if environment is healthy, otherwise restore values
- * from shadow copy
- */
- check_env();
- return 0;
-}
-
-void vcma9_print_info(void)
-{
- char *s = getenv("serial#");
-
- if (!s) {
- puts ("### No HW ID - assuming VCMA9");
- } else {
- s[5] = 0;
- vcma9_show_info(s, &s[6]);
- }
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F400BB flash.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- info->portwidth = FLASH_CFI_16BIT;
- info->chipwidth = FLASH_CFI_BY16;
- info->interface = FLASH_CFI_X16;
- return 1;
-}
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h
deleted file mode 100644
index c585c8e..0000000
--- a/board/mpl/vcma9/vcma9.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2002, 2003
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- /****************************************************************************
- * Global routines used for VCMA9
- *****************************************************************************/
-
-#include <asm/arch/s3c24x0_cpu.h>
-
-extern void vcma9_print_info(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag,
- int argc, char *const argv[]);
-
-/* VCMA9 PLD registers */
-enum vcma9_pld_regs {
- VCMA9_PLD_ID,
- VCMA9_PLD_NIC,
- VCMA9_PLD_CAN,
- VCMA9_PLD_MISC,
- VCMA9_PLD_GPCD,
- VCMA9_PLD_BOARD,
- VCMA9_PLD_SDRAM
-};
-
-#define VCMA9_PLD_BASE (0x2C000100)
diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile
index b6cdeb4..0cb1dd6 100644
--- a/board/mpr2/Makefile
+++ b/board/mpr2/Makefile
@@ -16,4 +16,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := mpr2.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c
index 7449e03..3788a39 100644
--- a/board/mpr2/mpr2.c
+++ b/board/mpr2/mpr2.c
@@ -11,8 +11,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: MPR2\n");
@@ -138,11 +136,3 @@
return 0;
}
-
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("SDRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile
index 1819c4c..66c25fa 100644
--- a/board/ms7720se/Makefile
+++ b/board/ms7720se/Makefile
@@ -13,4 +13,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := ms7720se.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c
index 534a422..48edcc6 100644
--- a/board/ms7720se/ms7720se.c
+++ b/board/ms7720se/ms7720se.c
@@ -17,8 +17,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define LED_BASE 0xB0800000
int checkboard(void)
@@ -32,14 +30,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
outw(value & 0xFF, LED_BASE);
diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile
index 9f7af78..808d459 100644
--- a/board/ms7722se/Makefile
+++ b/board/ms7722se/Makefile
@@ -10,4 +10,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := ms7722se.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c
index ee1e99c..869b415 100644
--- a/board/ms7722se/ms7722se.c
+++ b/board/ms7722se/ms7722se.c
@@ -15,8 +15,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define LED_BASE 0xB0800000
int checkboard(void)
@@ -33,14 +31,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
writew(value & 0xFF, LED_BASE);
diff --git a/board/ms7750se/Makefile b/board/ms7750se/Makefile
index a8e3ca0..a010e32 100644
--- a/board/ms7750se/Makefile
+++ b/board/ms7750se/Makefile
@@ -6,4 +6,4 @@
#
obj-y := ms7750se.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/ms7750se/ms7750se.c b/board/ms7750se/ms7750se.c
index a7f9346..d252faa 100644
--- a/board/ms7750se/ms7750se.c
+++ b/board/ms7750se/ms7750se.c
@@ -8,8 +8,6 @@
#include <common.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
@@ -21,14 +19,6 @@
return 0;
}
-int dram_init (void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
int board_late_init(void)
{
return 0;
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index fc9c1c9..4e01deb 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -44,6 +44,12 @@
void pin_mux_usb(void)
{
- /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
+ /* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
pinmux_tristate_disable(PMUX_PINGRP_SLXK);
+ /* For USB1's ULPI signals */
+ funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+ /* USB1 PHY reset GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
}
diff --git a/board/omicron/calimain/MAINTAINERS b/board/omicron/calimain/MAINTAINERS
index f6e37a2..ad788a6 100644
--- a/board/omicron/calimain/MAINTAINERS
+++ b/board/omicron/calimain/MAINTAINERS
@@ -1,6 +1,6 @@
CALIMAIN BOARD
-M: Manfred Rudigier <manfred.rudigier@omicron.at>
-M: Christian Riesch <christian.riesch@omicron.at>
+M: Manfred Rudigier <manfred.rudigier@omicronenergy.com>
+M: Christoph Rüdisser <christoph.ruedisser@omicronenergy.com>
S: Maintained
F: board/omicron/calimain/
F: include/configs/calimain.h
diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig
index d67a69a..212f994 100644
--- a/board/phytec/pcm052/Kconfig
+++ b/board/phytec/pcm052/Kconfig
@@ -12,4 +12,28 @@
config SYS_CONFIG_NAME
default "pcm052"
+config PCM052_DDR_SIZE
+ int
+ default 256
+
+endif
+
+if TARGET_BK4R1
+
+config SYS_BOARD
+ default "pcm052"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_SOC
+ default "vf610"
+
+config SYS_CONFIG_NAME
+ default "bk4r1"
+
+config PCM052_DDR_SIZE
+ int
+ default 512
+
endif
diff --git a/board/phytec/pcm052/imximage.cfg b/board/phytec/pcm052/imximage.cfg
index f5a9747..2fbb5c1b 100644
--- a/board/phytec/pcm052/imximage.cfg
+++ b/board/phytec/pcm052/imximage.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index e4f61e1..e75ff4f 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -152,57 +152,6 @@
int dram_init(void)
{
- static const struct ddr3_jedec_timings pcm052_ddr_timings = {
- .tinit = 5,
- .trst_pwron = 80000,
- .cke_inactive = 200000,
- .wrlat = 5,
- .caslat_lin = 12,
- .trc = 6,
- .trrd = 4,
- .tccd = 4,
- .tbst_int_interval = 4,
- .tfaw = 18,
- .trp = 6,
- .twtr = 4,
- .tras_min = 15,
- .tmrd = 4,
- .trtp = 4,
- .tras_max = 14040,
- .tmod = 12,
- .tckesr = 4,
- .tcke = 3,
- .trcd_int = 6,
- .tras_lockout = 1,
- .tdal = 10,
- .bstlen = 3,
- .tdll = 512,
- .trp_ab = 6,
- .tref = 1542,
- .trfc = 64,
- .tref_int = 5,
- .tpdex = 3,
- .txpdll = 10,
- .txsnr = 68,
- .txsr = 506,
- .cksrx = 5,
- .cksre = 5,
- .freq_chg_en = 1,
- .zqcl = 256,
- .zqinit = 512,
- .zqcs = 64,
- .ref_per_zq = 64,
- .zqcs_rotate = 1,
- .aprebit = 10,
- .cmd_age_cnt = 255,
- .age_cnt = 255,
- .q_fullness = 0,
- .odt_rd_mapcs0 = 1,
- .odt_wr_mapcs0 = 1,
- .wlmrd = 40,
- .wldqsen = 25,
- };
-
static const iomux_v3_cfg_t pcm052_pads[] = {
PCM052_VF610_PAD_DDR_A15__DDR_A_15,
PCM052_VF610_PAD_DDR_A14__DDR_A_14,
@@ -256,11 +205,126 @@
PCM052_VF610_PAD_DDR_RESETB,
};
- imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
+#if defined(CONFIG_TARGET_PCM052)
+
+ static const struct ddr3_jedec_timings pcm052_ddr_timings = {
+ .tinit = 5,
+ .trst_pwron = 80000,
+ .cke_inactive = 200000,
+ .wrlat = 5,
+ .caslat_lin = 12,
+ .trc = 6,
+ .trrd = 4,
+ .tccd = 4,
+ .tbst_int_interval = 4,
+ .tfaw = 18,
+ .trp = 6,
+ .twtr = 4,
+ .tras_min = 15,
+ .tmrd = 4,
+ .trtp = 4,
+ .tras_max = 14040,
+ .tmod = 12,
+ .tckesr = 4,
+ .tcke = 3,
+ .trcd_int = 6,
+ .tras_lockout = 1,
+ .tdal = 10,
+ .bstlen = 3,
+ .tdll = 512,
+ .trp_ab = 6,
+ .tref = 1542,
+ .trfc = 64,
+ .tref_int = 5,
+ .tpdex = 3,
+ .txpdll = 10,
+ .txsnr = 68,
+ .txsr = 506,
+ .cksrx = 5,
+ .cksre = 5,
+ .freq_chg_en = 1,
+ .zqcl = 256,
+ .zqinit = 512,
+ .zqcs = 64,
+ .ref_per_zq = 64,
+ .zqcs_rotate = 1,
+ .aprebit = 10,
+ .cmd_age_cnt = 255,
+ .age_cnt = 255,
+ .q_fullness = 0,
+ .odt_rd_mapcs0 = 1,
+ .odt_wr_mapcs0 = 1,
+ .wlmrd = 40,
+ .wldqsen = 25,
+ };
ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
pcm052_phy_settings, 1, 2);
+#elif defined(CONFIG_TARGET_BK4R1)
+
+ static const struct ddr3_jedec_timings pcm052_ddr_timings = {
+ .tinit = 5,
+ .trst_pwron = 80000,
+ .cke_inactive = 200000,
+ .wrlat = 5,
+ .caslat_lin = 12,
+ .trc = 6,
+ .trrd = 4,
+ .tccd = 4,
+ .tbst_int_interval = 0,
+ .tfaw = 16,
+ .trp = 6,
+ .twtr = 4,
+ .tras_min = 15,
+ .tmrd = 4,
+ .trtp = 4,
+ .tras_max = 28080,
+ .tmod = 12,
+ .tckesr = 4,
+ .tcke = 3,
+ .trcd_int = 6,
+ .tras_lockout = 1,
+ .tdal = 12,
+ .bstlen = 3,
+ .tdll = 512,
+ .trp_ab = 6,
+ .tref = 3120,
+ .trfc = 104,
+ .tref_int = 0,
+ .tpdex = 3,
+ .txpdll = 10,
+ .txsnr = 108,
+ .txsr = 512,
+ .cksrx = 5,
+ .cksre = 5,
+ .freq_chg_en = 1,
+ .zqcl = 256,
+ .zqinit = 512,
+ .zqcs = 64,
+ .ref_per_zq = 64,
+ .zqcs_rotate = 1,
+ .aprebit = 10,
+ .cmd_age_cnt = 255,
+ .age_cnt = 255,
+ .q_fullness = 0,
+ .odt_rd_mapcs0 = 1,
+ .odt_wr_mapcs0 = 1,
+ .wlmrd = 40,
+ .wldqsen = 25,
+ };
+
+ ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
+ pcm052_phy_settings, 1, 1);
+
+#else /* Unknown PCM052 variant */
+
+#error DDR characteristics undefined for this target. Please define them.
+
+#endif
+
+ imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
+
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
@@ -513,3 +577,41 @@
return 0;
}
+
+static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ ulong addr;
+
+ /* Consume 'm4go' */
+ argc--; argv++;
+
+ /*
+ * Parse provided address - default to load_addr in case not provided.
+ */
+
+ if (argc)
+ addr = simple_strtoul(argv[0], NULL, 16);
+ else
+ addr = load_addr;
+
+ /*
+ * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0]
+ */
+ writel(addr + 0x401, 0x4006E028);
+
+ /*
+ * Start secondary processor by enabling its clock
+ */
+ writel(0x15a5a, 0x4006B08C);
+
+ return 1;
+}
+
+U_BOOT_CMD(
+ m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go,
+ "start the secondary Cortex-M4 from scatter file image",
+ "[<addr>]\n"
+ " - start secondary Cortex-M4 core using a scatter file image\n"
+ "The argument needs to be a scatter file\n"
+);
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
index 4e2122f..c3607da 100644
--- a/board/phytec/pcm058/pcm058.c
+++ b/board/phytec/pcm058/pcm058.c
@@ -22,7 +22,7 @@
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/spi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <mmc.h>
#include <i2c.h>
diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile
index 4ce2c98..dcb25ac 100644
--- a/board/raspberrypi/rpi/Makefile
+++ b/board/raspberrypi/rpi/Makefile
@@ -5,3 +5,4 @@
#
obj-y := rpi.o
+obj-y += lowlevel_init.o
diff --git a/board/raspberrypi/rpi/lowlevel_init.S b/board/raspberrypi/rpi/lowlevel_init.S
new file mode 100644
index 0000000..cdbd8e1
--- /dev/null
+++ b/board/raspberrypi/rpi/lowlevel_init.S
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2016
+ * Cédric Schieli <cschieli@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.align 8
+.global fw_dtb_pointer
+fw_dtb_pointer:
+#ifdef CONFIG_ARM64
+ .dword 0x0
+#else
+ .word 0x0
+#endif
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: save ATAG/FDT address provided by the firmware at boot time
+ */
+
+.global save_boot_params
+save_boot_params:
+
+ /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+#ifdef CONFIG_ARM64
+ adr x8, fw_dtb_pointer
+ str x0, [x8]
+#else
+ str r2, fw_dtb_pointer
+#endif
+
+ /* Returns */
+ b save_boot_params_ret
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 6245b36..532ea99 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -8,6 +8,7 @@
#include <inttypes.h>
#include <config.h>
#include <dm.h>
+#include <efi_loader.h>
#include <fdt_support.h>
#include <fdt_simplefb.h>
#include <lcd.h>
@@ -17,7 +18,6 @@
#include <asm/arch/mbox.h>
#include <asm/arch/sdhci.h>
#include <asm/global_data.h>
-#include <dm/platform_data/serial_pl01x.h>
#include <dm/platform_data/serial_bcm283x_mu.h>
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
@@ -25,42 +25,9 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct bcm2835_gpio_platdata gpio_platdata = {
- .base = BCM2835_GPIO_BASE,
-};
+/* From lowlevel_init.S */
+extern unsigned long fw_dtb_pointer;
-U_BOOT_DEVICE(bcm2835_gpios) = {
- .name = "gpio_bcm2835",
- .platdata = &gpio_platdata,
-};
-
-#ifdef CONFIG_PL01X_SERIAL
-static const struct pl01x_serial_platdata serial_platdata = {
-#ifndef CONFIG_BCM2835
- .base = 0x3f201000,
-#else
- .base = 0x20201000,
-#endif
- .type = TYPE_PL011,
- .skip_init = true,
-};
-
-U_BOOT_DEVICE(bcm2835_serials) = {
- .name = "serial_pl01x",
- .platdata = &serial_platdata,
-};
-#else
-static struct bcm283x_mu_serial_platdata serial_platdata = {
- .base = 0x3f215040,
- .clock = 250000000,
- .skip_init = true,
-};
-
-U_BOOT_DEVICE(bcm2837_serials) = {
- .name = "serial_bcm283x_mu",
- .platdata = &serial_platdata,
-};
-#endif
struct msg_get_arm_mem {
struct bcm2835_mbox_hdr hdr;
@@ -285,6 +252,31 @@
setenv("fdtfile", fdtfile);
}
+/*
+ * If the firmware provided a valid FDT at boot time, let's expose it in
+ * ${fdt_addr} so it may be passed unmodified to the kernel.
+ */
+static void set_fdt_addr(void)
+{
+ if (getenv("fdt_addr"))
+ return;
+
+ if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+ return;
+
+ setenv_hex("fdt_addr", fw_dtb_pointer);
+}
+
+/*
+ * Prevent relocation from stomping on a firmware provided FDT blob.
+ */
+unsigned long board_get_usable_ram_top(unsigned long total_size)
+{
+ if ((gd->ram_top - fw_dtb_pointer) > SZ_64M)
+ return gd->ram_top;
+ return fw_dtb_pointer & ~0xffff;
+}
+
static void set_usbethaddr(void)
{
ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1);
@@ -356,6 +348,7 @@
int misc_init_r(void)
{
+ set_fdt_addr();
set_fdtfile();
set_usbethaddr();
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -443,15 +436,6 @@
printf("RPI %s (0x%x)\n", model->name, revision);
}
-int board_init(void)
-{
- get_board_rev();
-
- gd->bd->bi_boot_params = 0x100;
-
- return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
-}
-
#ifndef CONFIG_PL01X_SERIAL
static bool rpi_is_serial_active(void)
{
@@ -471,17 +455,38 @@
return true;
}
+
+/* Disable mini-UART I/O if it's not pinmuxed to our pins.
+ * The firmware only enables it if explicitly done in config.txt: enable_uart=1
+ */
+static void rpi_disable_inactive_uart(void)
+{
+ struct udevice *dev;
+ struct bcm283x_mu_serial_platdata *plat;
+
+ if (uclass_get_device_by_driver(UCLASS_SERIAL,
+ DM_GET_DRIVER(serial_bcm283x_mu),
+ &dev) || !dev)
+ return;
+
+ if (!rpi_is_serial_active()) {
+ plat = dev_get_platdata(dev);
+ plat->disabled = true;
+ }
+}
#endif
-int board_early_init_f(void)
+int board_init(void)
{
#ifndef CONFIG_PL01X_SERIAL
- /* Disable mini-UART I/O if it's not pinmuxed to our pins */
- if (!rpi_is_serial_active())
- serial_platdata.disabled = true;
+ rpi_disable_inactive_uart();
#endif
- return 0;
+ get_board_rev();
+
+ gd->bd->bi_boot_params = 0x100;
+
+ return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
}
int board_mmc_init(bd_t *bis)
@@ -505,6 +510,16 @@
msg_clk->get_clock_rate.body.resp.rate_hz);
}
+/*
+ * * If the firmware passed a device tree use for U-Boot.
+ * */
+void *board_fdt_blob_setup(void)
+{
+ if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+ return NULL;
+ return (void *)fw_dtb_pointer;
+}
+
int ft_board_setup(void *blob, bd_t *bd)
{
/*
@@ -514,5 +529,10 @@
*/
lcd_dt_simplefb_add_node(blob);
+#ifdef CONFIG_EFI_LOADER
+ /* Reserve the spin table */
+ efi_add_memory_map(0, 1, EFI_RESERVED_MEMORY_TYPE, 0);
+#endif
+
return 0;
}
diff --git a/board/renesas/MigoR/Makefile b/board/renesas/MigoR/Makefile
index b4691a1..0686f97 100644
--- a/board/renesas/MigoR/Makefile
+++ b/board/renesas/MigoR/Makefile
@@ -10,4 +10,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := migo_r.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c
index fa2bf78..6409a73 100644
--- a/board/renesas/MigoR/migo_r.c
+++ b/board/renesas/MigoR/migo_r.c
@@ -15,8 +15,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas MigoR\n");
@@ -28,14 +26,6 @@
return 0;
}
-int dram_init (void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state (unsigned short value)
{
}
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index a1a26a6..b35b6a3 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -13,7 +13,7 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
diff --git a/board/renesas/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile
index ff72de9..18e1ed5 100644
--- a/board/renesas/ap325rxa/Makefile
+++ b/board/renesas/ap325rxa/Makefile
@@ -9,4 +9,4 @@
#
obj-y := ap325rxa.o cpld-ap325rxa.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/ap325rxa/ap325rxa.c b/board/renesas/ap325rxa/ap325rxa.c
index 518ad7b..218d479 100644
--- a/board/renesas/ap325rxa/ap325rxa.c
+++ b/board/renesas/ap325rxa/ap325rxa.c
@@ -10,8 +10,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* PRI control register */
#define PRPRICR5 0xFF800048 /* LMB */
#define PRPRICR5_D 0x2a
@@ -130,14 +128,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index b2e2e3b..1372050 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -15,7 +15,7 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile
index 943fa47..2e6fb50 100644
--- a/board/renesas/ecovec/Makefile
+++ b/board/renesas/ecovec/Makefile
@@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := ecovec.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
index d862d99..28b557a 100644
--- a/board/renesas/ecovec/ecovec.c
+++ b/board/renesas/ecovec/ecovec.c
@@ -22,16 +22,6 @@
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
static void debug_led(u8 led)
{
/* PDGR[0-4] is debug LED */
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 3a8bf86..359f95e 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -13,7 +13,7 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index b741e2e..dd62145 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 6fed2f9..2ada816 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -16,7 +16,7 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c
index f6467ee..926a657 100644
--- a/board/renesas/porter/porter.c
+++ b/board/renesas/porter/porter.c
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile
index 1f24d92..bfe52d6 100644
--- a/board/renesas/r0p7734/Makefile
+++ b/board/renesas/r0p7734/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := r0p7734.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c
index 2e31ba6..360e0a1 100644
--- a/board/renesas/r0p7734/r0p7734.c
+++ b/board/renesas/r0p7734/r0p7734.c
@@ -11,8 +11,6 @@
#include <netdev.h>
#include <i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODEMR (0xFFCC0020)
#define MODEMR_MASK (0x6)
#define MODEMR_533MHZ (0x2)
@@ -61,15 +59,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
- return 0;
-}
-
#ifdef CONFIG_SMC911X
int board_eth_init(bd_t *bis)
{
diff --git a/board/renesas/r2dplus/Makefile b/board/renesas/r2dplus/Makefile
index acffb6d..4021ab6 100644
--- a/board/renesas/r2dplus/Makefile
+++ b/board/renesas/r2dplus/Makefile
@@ -6,4 +6,4 @@
#
obj-y := r2dplus.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c
index 249c35f..d6fb4da 100644
--- a/board/renesas/r2dplus/r2dplus.c
+++ b/board/renesas/r2dplus/r2dplus.c
@@ -12,8 +12,6 @@
#include <asm/io.h>
#include <asm/pci.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas Solutions R2D Plus\n");
@@ -25,14 +23,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
int board_late_init(void)
{
return 0;
diff --git a/board/renesas/r7780mp/Makefile b/board/renesas/r7780mp/Makefile
index 8dab435..66813a3 100644
--- a/board/renesas/r7780mp/Makefile
+++ b/board/renesas/r7780mp/Makefile
@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := r7780mp.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/r7780mp/r7780mp.c b/board/renesas/r7780mp/r7780mp.c
index 783352d..de259f5 100644
--- a/board/renesas/r7780mp/r7780mp.c
+++ b/board/renesas/r7780mp/r7780mp.c
@@ -13,8 +13,6 @@
#include <netdev.h>
#include "r7780mp.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
#if defined(CONFIG_R7780MP)
@@ -33,14 +31,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile
index 16acfaf..08139a2 100644
--- a/board/renesas/rsk7203/Makefile
+++ b/board/renesas/rsk7203/Makefile
@@ -7,4 +7,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := rsk7203.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/rsk7203/rsk7203.c b/board/renesas/rsk7203/rsk7203.c
index 8800371..72c562d 100644
--- a/board/renesas/rsk7203/rsk7203.c
+++ b/board/renesas/rsk7203/rsk7203.c
@@ -13,8 +13,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas Technology RSK7203\n");
@@ -26,14 +24,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
diff --git a/board/renesas/rsk7264/Makefile b/board/renesas/rsk7264/Makefile
index 7ada697..2a845a0 100644
--- a/board/renesas/rsk7264/Makefile
+++ b/board/renesas/rsk7264/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := rsk7264.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/rsk7264/rsk7264.c b/board/renesas/rsk7264/rsk7264.c
index d938b3a..4ebb27b 100644
--- a/board/renesas/rsk7264/rsk7264.c
+++ b/board/renesas/rsk7264/rsk7264.c
@@ -14,8 +14,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas Technology RSK7264\n");
@@ -27,14 +25,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile
index 0f053d8..86b2263 100644
--- a/board/renesas/rsk7269/Makefile
+++ b/board/renesas/rsk7269/Makefile
@@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := rsk7269.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/rsk7269/rsk7269.c b/board/renesas/rsk7269/rsk7269.c
index ae32b6a..0066f9f 100644
--- a/board/renesas/rsk7269/rsk7269.c
+++ b/board/renesas/rsk7269/rsk7269.c
@@ -15,8 +15,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas RSK7269\n");
@@ -28,14 +26,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 47242c6..0164306 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -16,7 +16,7 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile
index 856af81..fb6eeec 100644
--- a/board/renesas/sh7752evb/Makefile
+++ b/board/renesas/sh7752evb/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := sh7752evb.o spi-boot.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c
index 3aad532..525d979 100644
--- a/board/renesas/sh7752evb/sh7752evb.c
+++ b/board/renesas/sh7752evb/sh7752evb.c
@@ -159,17 +159,6 @@
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
- return 0;
-}
-
int board_mmc_init(bd_t *bis)
{
struct gpio_regs *gpio = GPIO_BASE;
diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds
deleted file mode 100644
index 6cd4056..0000000
--- a/board/renesas/sh7752evb/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2012
- * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- KEEP(arch/sh/cpu/sh4/start.o (.text))
- *(.spiboot1.text)
- *(.spiboot2.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- PROVIDE (__init_end = .);
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss (NOLOAD) :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (__bss_end = .);
-}
diff --git a/board/renesas/sh7753evb/Makefile b/board/renesas/sh7753evb/Makefile
index f7c8e94..4293142 100644
--- a/board/renesas/sh7753evb/Makefile
+++ b/board/renesas/sh7753evb/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := sh7753evb.o spi-boot.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c
index 52a1906..3d1eeda 100644
--- a/board/renesas/sh7753evb/sh7753evb.c
+++ b/board/renesas/sh7753evb/sh7753evb.c
@@ -175,17 +175,6 @@
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
- return 0;
-}
-
int board_mmc_init(bd_t *bis)
{
struct gpio_regs *gpio = GPIO_BASE;
diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds
deleted file mode 100644
index 6cd4056..0000000
--- a/board/renesas/sh7753evb/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2012
- * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- KEEP(arch/sh/cpu/sh4/start.o (.text))
- *(.spiboot1.text)
- *(.spiboot2.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- PROVIDE (__init_end = .);
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss (NOLOAD) :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (__bss_end = .);
-}
diff --git a/board/renesas/sh7757lcr/Makefile b/board/renesas/sh7757lcr/Makefile
index 1fa3992..f1ce0f6 100644
--- a/board/renesas/sh7757lcr/Makefile
+++ b/board/renesas/sh7757lcr/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := sh7757lcr.o spi-boot.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c
index ddcf275..0a04a9d 100644
--- a/board/renesas/sh7757lcr/sh7757lcr.c
+++ b/board/renesas/sh7757lcr/sh7757lcr.c
@@ -224,31 +224,6 @@
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- printf(" Physical address\n");
- printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n",
- SH7757LCR_SDRAM_PHYS_TOP,
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
- printf(" 0x%08x - 0x%08x : No Access Area\n",
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
- printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
- SH7757LCR_SDRAM_DVC_SIZE - 1);
- printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
-
- return 0;
-}
-
int board_mmc_init(bd_t *bis)
{
return mmcif_mmc_init();
diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds
deleted file mode 100644
index d701367..0000000
--- a/board/renesas/sh7757lcr/u-boot.lds
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2011
- * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- KEEP(arch/sh/cpu/sh4/start.o (.text))
- *(.spiboot1.text)
- *(.spiboot2.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- PROVIDE (__init_end = .);
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss (NOLOAD) :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (__bss_end = .);
-}
diff --git a/board/renesas/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile
index cbf38bb..13f7ae9 100644
--- a/board/renesas/sh7763rdp/Makefile
+++ b/board/renesas/sh7763rdp/Makefile
@@ -9,4 +9,4 @@
#
obj-y := sh7763rdp.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/sh7763rdp/sh7763rdp.c b/board/renesas/sh7763rdp/sh7763rdp.c
index 9658a5e..d83e2f8 100644
--- a/board/renesas/sh7763rdp/sh7763rdp.c
+++ b/board/renesas/sh7763rdp/sh7763rdp.c
@@ -12,8 +12,6 @@
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define CPU_CMDREG 0xB1000006
#define PDCR 0xffef0006
#define PECR 0xffef0008
@@ -51,14 +49,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile
index e8cfb05..1bf5d53 100644
--- a/board/renesas/sh7785lcr/Makefile
+++ b/board/renesas/sh7785lcr/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/sh7785lcr/sh7785lcr.c b/board/renesas/sh7785lcr/sh7785lcr.c
index 622e602..a1a0301 100644
--- a/board/renesas/sh7785lcr/sh7785lcr.c
+++ b/board/renesas/sh7785lcr/sh7785lcr.c
@@ -10,8 +10,6 @@
#include <asm/pci.h>
#include <netdev.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
@@ -23,14 +21,6 @@
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
static struct pci_controller hose;
void pci_init_board(void)
{
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
index 4ec3f92..e13a38f 100644
--- a/board/renesas/silk/silk.c
+++ b/board/renesas/silk/silk.c
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c
index 672a730..fe8dd3d 100644
--- a/board/renesas/stout/stout.c
+++ b/board/renesas/stout/stout.c
@@ -17,7 +17,7 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c
index e5582b4..288370a 100644
--- a/board/rockchip/evb_rk3036/evb_rk3036.c
+++ b/board/rockchip/evb_rk3036/evb_rk3036.c
@@ -27,69 +27,3 @@
/* 16bit bw */
config->bw = 1;
}
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = sdram_size();
-
- return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3036_otg_data = {
- .rx_fifo_sz = 512,
- .np_tx_fifo_sz = 16,
- .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- int node;
- const char *mode;
- bool matched = false;
- const void *blob = gd->fdt_blob;
-
- /* find the usb_otg node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3288-usb");
-
- while (node > 0) {
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode && strcmp(mode, "otg") == 0) {
- matched = true;
- break;
- }
-
- node = fdt_node_offset_by_compatible(blob, node,
- "rockchip,rk3288-usb");
- }
- if (!matched) {
- debug("Not found usb_otg device\n");
- return -ENODEV;
- }
- rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
- return dwc2_udc_probe(&rk3036_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-#endif
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index cb2d97d..c437f1b 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -4,12 +4,60 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/armv8/mmu.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-internal.h>
+#include <asm/arch/periph.h>
+#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
+ struct udevice *pinctrl, *regulator;
+ int ret;
+
+ /*
+ * The PWM do not have decicated interrupt number in dts and can
+ * not get periph_id by pinctrl framework, so let's init them here.
+ * The PWM2 and PWM3 are for pwm regulater.
+ */
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ goto out;
+ }
+
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
+ if (ret) {
+ debug("%s PWM2 pinctrl init fail!\n", __func__);
+ goto out;
+ }
+
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3);
+ if (ret) {
+ debug("%s PWM3 pinctrl init fail!\n", __func__);
+ goto out;
+ }
+
+ /* rk3399 need init vdd_center to get correct output voltage */
+ ret = regulator_get_by_platname("vdd_center", ®ulator);
+ if (ret)
+ debug("%s: Cannot get vdd_center regulator\n", __func__);
+
+ ret = regulator_get_by_platname("vcc5v0_host", ®ulator);
+ if (ret) {
+ debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
+ goto out;
+ }
+
+ ret = regulator_set_enable(regulator, true);
+ if (ret) {
+ debug("%s vcc5v0-host-en set fail!\n", __func__);
+ goto out;
+ }
+
+out:
return 0;
}
@@ -23,5 +71,5 @@
{
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
- gd->bd->bi_dram[0].size = 0x80000000;
+ gd->bd->bi_dram[0].size = 0x7e000000;
}
diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c
index 5ade695..7e2edf4 100644
--- a/board/rockchip/kylin_rk3036/kylin_rk3036.c
+++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c
@@ -8,14 +8,11 @@
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/uart.h>
-#include <asm/arch-rockchip/grf_rk3036.h>
#include <asm/arch/sdram_rk3036.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
-#define GRF_BASE 0x20008000
-
void get_ddr_config(struct rk3036_ddr_config *config)
{
/* K4B4G1646Q config */
@@ -43,85 +40,12 @@
#define ROCKCHIP_BOOT_MODE_FASTBOOT 0x5242C309
-int board_late_init(void)
+int rk_board_late_init(void)
{
- struct rk3036_grf * const grf = (void *)GRF_BASE;
- int boot_mode = readl(&grf->os_reg[4]);
-
- /* Clear boot mode */
- writel(0, &grf->os_reg[4]);
-
- if (boot_mode == ROCKCHIP_BOOT_MODE_FASTBOOT ||
- fastboot_key_pressed()) {
+ if (fastboot_key_pressed()) {
printf("enter fastboot!\n");
setenv("preboot", "setenv preboot; fastboot usb0");
}
return 0;
}
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = sdram_size();
-
- return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3036_otg_data = {
- .rx_fifo_sz = 512,
- .np_tx_fifo_sz = 16,
- .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- int node;
- const char *mode;
- bool matched = false;
- const void *blob = gd->fdt_blob;
-
- /* find the usb_otg node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3288-usb");
-
- while (node > 0) {
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode && strcmp(mode, "otg") == 0) {
- matched = true;
- break;
- }
-
- node = fdt_node_offset_by_compatible(blob, node,
- "rockchip,rk3288-usb");
- }
- if (!matched) {
- debug("Not found usb_otg device\n");
- return -ENODEV;
- }
- rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
- return dwc2_udc_probe(&rk3036_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-#endif
diff --git a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
index aad74ef..79541a3 100644
--- a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
+++ b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
@@ -5,11 +5,3 @@
*/
#include <common.h>
-#include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
- /* eMMC prior to sdcard */
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 0eb066c..522e0cd 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -251,7 +251,7 @@
#ifdef CONFIG_GENERIC_MMC
static int init_mmc(void)
{
-#ifdef CONFIG_SDHCI
+#ifdef CONFIG_MMC_SDHCI
return exynos_mmc_init(gd->fdt_blob);
#else
return 0;
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 77d0a4e..203136f 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -101,6 +101,7 @@
#ifdef CONFIG_LCD_MENU
static int power_key_pressed(u32 reg)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
struct pmic *pmic;
u32 status;
u32 mask;
@@ -123,6 +124,9 @@
return 0;
return !!(status & mask);
+#else
+ return 0;
+#endif
}
static int key_pressed(int key)
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 1600568..b066832 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -45,17 +45,15 @@
int power_init_board(void)
{
- int ret;
-
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
/*
* For PMIC the I2C bus is named as I2C5, but it is connected
* to logical I2C adapter 0
*/
- ret = pmic_init(I2C_0);
- if (ret)
- return ret;
-
+ return pmic_init(I2C_0);
+#else
return 0;
+#endif
}
int dram_init(void)
@@ -148,6 +146,7 @@
#ifdef CONFIG_USB_GADGET
static int s5pc1xx_phy_control(int on)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int ret;
static int status;
struct pmic *p = pmic_get("MAX8998_PMIC");
@@ -179,7 +178,7 @@
status = 0;
}
udelay(10000);
-
+#endif
return 0;
}
diff --git a/board/samsung/odroid/MAINTAINERS b/board/samsung/odroid/MAINTAINERS
index 2131d36..3f2cf14 100644
--- a/board/samsung/odroid/MAINTAINERS
+++ b/board/samsung/odroid/MAINTAINERS
@@ -1,5 +1,5 @@
ODROID BOARD
-M: Przemyslaw Marczak <p.marczak@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/odroid/
F: include/configs/odroid.h
diff --git a/board/samsung/smdk2410/Kconfig b/board/samsung/smdk2410/Kconfig
deleted file mode 100644
index e987b64..0000000
--- a/board/samsung/smdk2410/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SMDK2410
-
-config SYS_BOARD
- default "smdk2410"
-
-config SYS_VENDOR
- default "samsung"
-
-config SYS_SOC
- default "s3c24x0"
-
-config SYS_CONFIG_NAME
- default "smdk2410"
-
-endif
diff --git a/board/samsung/smdk2410/MAINTAINERS b/board/samsung/smdk2410/MAINTAINERS
deleted file mode 100644
index 12a25e8..0000000
--- a/board/samsung/smdk2410/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SMDK2410 BOARD
-M: David Müller <d.mueller@elsoft.ch>
-S: Maintained
-F: board/samsung/smdk2410/
-F: include/configs/smdk2410.h
-F: configs/smdk2410_defconfig
diff --git a/board/samsung/smdk2410/Makefile b/board/samsung/smdk2410/Makefile
deleted file mode 100644
index 1939a21..0000000
--- a/board/samsung/smdk2410/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := smdk2410.o
-obj-y += lowlevel_init.o
diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S
deleted file mode 100644
index c3f4187..0000000
--- a/board/samsung/smdk2410/lowlevel_init.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the Samsung SMDK2410 by
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <config.h>
-
-/* some parameters for the board */
-
-/*
- *
- * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
- *
- * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
- *
- */
-
-#define BWSCON 0x48000000
-
-/* BWSCON */
-#define DW8 (0x0)
-#define DW16 (0x1)
-#define DW32 (0x2)
-#define WAIT (0x1<<2)
-#define UBLB (0x1<<3)
-
-#define B1_BWSCON (DW32)
-#define B2_BWSCON (DW16)
-#define B3_BWSCON (DW16 + WAIT + UBLB)
-#define B4_BWSCON (DW16)
-#define B5_BWSCON (DW16)
-#define B6_BWSCON (DW32)
-#define B7_BWSCON (DW32)
-
-/* BANK0CON */
-#define B0_Tacs 0x0 /* 0clk */
-#define B0_Tcos 0x0 /* 0clk */
-#define B0_Tacc 0x7 /* 14clk */
-#define B0_Tcoh 0x0 /* 0clk */
-#define B0_Tah 0x0 /* 0clk */
-#define B0_Tacp 0x0
-#define B0_PMC 0x0 /* normal */
-
-/* BANK1CON */
-#define B1_Tacs 0x0 /* 0clk */
-#define B1_Tcos 0x0 /* 0clk */
-#define B1_Tacc 0x7 /* 14clk */
-#define B1_Tcoh 0x0 /* 0clk */
-#define B1_Tah 0x0 /* 0clk */
-#define B1_Tacp 0x0
-#define B1_PMC 0x0
-
-#define B2_Tacs 0x0
-#define B2_Tcos 0x0
-#define B2_Tacc 0x7
-#define B2_Tcoh 0x0
-#define B2_Tah 0x0
-#define B2_Tacp 0x0
-#define B2_PMC 0x0
-
-#define B3_Tacs 0x0 /* 0clk */
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7 /* 14clk */
-#define B3_Tcoh 0x1 /* 1clk */
-#define B3_Tah 0x0 /* 0clk */
-#define B3_Tacp 0x3 /* 6clk */
-#define B3_PMC 0x0 /* normal */
-
-#define B4_Tacs 0x0 /* 0clk */
-#define B4_Tcos 0x0 /* 0clk */
-#define B4_Tacc 0x7 /* 14clk */
-#define B4_Tcoh 0x0 /* 0clk */
-#define B4_Tah 0x0 /* 0clk */
-#define B4_Tacp 0x0
-#define B4_PMC 0x0 /* normal */
-
-#define B5_Tacs 0x0 /* 0clk */
-#define B5_Tcos 0x0 /* 0clk */
-#define B5_Tacc 0x7 /* 14clk */
-#define B5_Tcoh 0x0 /* 0clk */
-#define B5_Tah 0x0 /* 0clk */
-#define B5_Tacp 0x0
-#define B5_PMC 0x0 /* normal */
-
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd 0x1
-#define B6_SCAN 0x1 /* 9bit */
-
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd 0x1 /* 3clk */
-#define B7_SCAN 0x1 /* 9bit */
-
-/* REFRESH parameter */
-#define REFEN 0x1 /* Refresh enable */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
-#define Trp 0x0 /* 2clk */
-#define Trc 0x3 /* 7clk */
-#define Tchr 0x2 /* 3clk */
-#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
-/**************************************/
-
-.globl lowlevel_init
-lowlevel_init:
- /* memory control configuration */
- /* make r0 relative the current location so that it */
- /* reads SMRDATA out of FLASH rather than memory ! */
- ldr r0, =SMRDATA
- ldr r1, =CONFIG_SYS_TEXT_BASE
- sub r0, r0, r1
- ldr r1, =BWSCON /* Bus Width Status Controller */
- add r2, r0, #13*4
-0:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r2, r0
- bne 0b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-/* the literal pools origin */
-
-SMRDATA:
- .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
- .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
- .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
- .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
- .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
- .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
- .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
- .word 0x32
- .word 0x30
- .word 0x30
diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c
deleted file mode 100644
index 6e678c7..0000000
--- a/board/samsung/smdk2410/smdk2410.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002, 2010
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FCLK_SPEED 1
-
-#if (FCLK_SPEED == 0) /* Fout = 203MHz, Fin = 12MHz for Audio */
-#define M_MDIV 0xC3
-#define M_PDIV 0x4
-#define M_SDIV 0x1
-#elif (FCLK_SPEED == 1) /* Fout = 202.8MHz */
-#define M_MDIV 0xA1
-#define M_PDIV 0x3
-#define M_SDIV 0x1
-#endif
-
-#define USB_CLOCK 1
-
-#if (USB_CLOCK == 0)
-#define U_M_MDIV 0xA1
-#define U_M_PDIV 0x3
-#define U_M_SDIV 0x1
-#elif (USB_CLOCK == 1)
-#define U_M_MDIV 0x48
-#define U_M_PDIV 0x3
-#define U_M_SDIV 0x2
-#endif
-
-static inline void pll_delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b" : "=r" (loops) : "0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f(void)
-{
- struct s3c24x0_clock_power * const clk_power =
- s3c24x0_get_base_clock_power();
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
- /* to reduce PLL lock time, adjust the LOCKTIME register */
- writel(0xFFFFFF, &clk_power->locktime);
-
- /* configure MPLL */
- writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
- &clk_power->mpllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(4000);
-
- /* configure UPLL */
- writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
- &clk_power->upllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(8000);
-
- /* set up the I/O ports */
- writel(0x007FFFFF, &gpio->gpacon);
- writel(0x00044555, &gpio->gpbcon);
- writel(0x000007FF, &gpio->gpbup);
- writel(0xAAAAAAAA, &gpio->gpccon);
- writel(0x0000FFFF, &gpio->gpcup);
- writel(0xAAAAAAAA, &gpio->gpdcon);
- writel(0x0000FFFF, &gpio->gpdup);
- writel(0xAAAAAAAA, &gpio->gpecon);
- writel(0x0000FFFF, &gpio->gpeup);
- writel(0x000055AA, &gpio->gpfcon);
- writel(0x000000FF, &gpio->gpfup);
- writel(0xFF95FFBA, &gpio->gpgcon);
- writel(0x0000FFFF, &gpio->gpgup);
- writel(0x002AFAAA, &gpio->gphcon);
- writel(0x000007FF, &gpio->gphup);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* arch number of SMDK2410-Board */
- gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x30000100;
-
- icache_enable();
- dcache_enable();
-
- return 0;
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29LV800BB flash.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- info->portwidth = FLASH_CFI_16BIT;
- info->chipwidth = FLASH_CFI_BY16;
- info->interface = FLASH_CFI_X16;
- return 1;
-}
diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS
index 0361657..590a114 100644
--- a/board/samsung/smdk5420/MAINTAINERS
+++ b/board/samsung/smdk5420/MAINTAINERS
@@ -10,7 +10,7 @@
F: configs/peach-pi_defconfig
ODROID-XU3 BOARD
-M: Przemyslaw Marczak <p.marczak@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/smdk5420/
F: include/configs/odroid_xu3.h
diff --git a/board/samsung/trats/MAINTAINERS b/board/samsung/trats/MAINTAINERS
index 1b219b4..060bcdb 100644
--- a/board/samsung/trats/MAINTAINERS
+++ b/board/samsung/trats/MAINTAINERS
@@ -1,5 +1,5 @@
TRATS BOARD
-M: Lukasz Majewski <l.majewski@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/trats/
F: include/configs/trats.h
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 66a54d4..7200c2e 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -53,6 +53,7 @@
void i2c_init_board(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int err;
/* I2C_5 -> PMIC */
@@ -67,8 +68,10 @@
gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
+#endif
}
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
static void trats_low_power_mode(void)
{
struct exynos4_clock *clk =
@@ -273,11 +276,14 @@
puts("MAX8997 PMIC setting error!\n");
return -1;
}
+
return 0;
}
+#endif
int exynos_power_init(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int chrg, ret;
struct power_battery *pb;
struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
@@ -341,6 +347,7 @@
if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
puts("CHARGE Battery !\n");
+#endif
return 0;
}
@@ -384,6 +391,7 @@
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int ret = 0;
u32 val = 0;
struct pmic *p = pmic_get("MAX8997_PMIC");
@@ -415,6 +423,7 @@
puts("MAX8997 LDO setting error!\n");
return -1;
}
+#endif
return 0;
}
@@ -435,11 +444,16 @@
int g_dnl_board_usb_cable_connected(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
struct pmic *muic = pmic_get("MAX8997_MUIC");
if (!muic)
return 0;
return !!muic->chrg->chrg_type(muic);
+#else
+ return false;
+#endif
+
}
#endif
@@ -552,6 +566,7 @@
int lcd_power(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int ret = 0;
struct pmic *p = pmic_get("MAX8997_PMIC");
if (!p)
@@ -569,12 +584,13 @@
puts("MAX8997 LDO setting error!\n");
return -1;
}
-
+#endif
return 0;
}
int mipi_power(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int ret = 0;
struct pmic *p = pmic_get("MAX8997_PMIC");
if (!p)
@@ -592,7 +608,7 @@
puts("MAX8997 LDO setting error!\n");
return -1;
}
-
+#endif
return 0;
}
diff --git a/board/samsung/trats2/MAINTAINERS b/board/samsung/trats2/MAINTAINERS
index 7018300..ba17b4e 100644
--- a/board/samsung/trats2/MAINTAINERS
+++ b/board/samsung/trats2/MAINTAINERS
@@ -1,5 +1,5 @@
TRATS2 BOARD
-M: Lukasz Majewski <l.majewski@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/trats2/
F: include/configs/trats2.h
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 7b28ae8..150503e 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -151,8 +151,6 @@
return 0;
}
-static int pmic_init_max77686(void);
-
int exynos_init(void)
{
struct exynos4_power *pwr =
@@ -176,6 +174,7 @@
int exynos_power_init(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int chrg;
struct power_battery *pb;
struct pmic *p_chrg, *p_muic, *p_fg, *p_bat;
@@ -236,13 +235,14 @@
if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
puts("CHARGE Battery !\n");
-
+#endif
return 0;
}
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int ret = 0;
unsigned int val;
struct pmic *p, *p_pmic, *p_muic;
@@ -299,7 +299,7 @@
if (ret)
return -1;
-
+#endif
return 0;
}
@@ -319,14 +319,19 @@
int g_dnl_board_usb_cable_connected(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
struct pmic *muic = pmic_get("MAX77693_MUIC");
if (!muic)
return 0;
return !!muic->chrg->chrg_type(muic);
+#else
+ return false;
+#endif
}
#endif
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
static int pmic_init_max77686(void)
{
struct pmic *p = pmic_get("MAX77686_PMIC");
@@ -379,6 +384,7 @@
return 0;
}
+#endif
/*
* LCD
@@ -387,18 +393,21 @@
#ifdef CONFIG_LCD
int mipi_power(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
struct pmic *p = pmic_get("MAX77686_PMIC");
/* LDO8 VMIPI_1.0V_AP */
max77686_set_ldo_mode(p, 8, OPMODE_ON);
/* LDO10 VMIPI_1.8V_AP */
max77686_set_ldo_mode(p, 10, OPMODE_ON);
+#endif
return 0;
}
void exynos_lcd_power_on(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
struct pmic *p = pmic_get("MAX77686_PMIC");
/* LCD_2.2V_EN: GPC0[1] */
@@ -410,6 +419,7 @@
pmic_probe(p);
max77686_set_ldo_voltage(p, 25, 3100000);
max77686_set_ldo_mode(p, 25, OPMODE_LPM);
+#endif
}
void exynos_reset_lcd(void)
diff --git a/board/samsung/universal_c210/MAINTAINERS b/board/samsung/universal_c210/MAINTAINERS
index 6760678..00d6110 100644
--- a/board/samsung/universal_c210/MAINTAINERS
+++ b/board/samsung/universal_c210/MAINTAINERS
@@ -1,5 +1,5 @@
UNIVERSAL_C210 BOARD
-M: Przemyslaw Marczak <p.marczak@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/universal_c210/
F: include/configs/s5pc210_universal.h
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 81e35b6..c3946ee 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -38,10 +38,9 @@
return board_rev & 0xFF;
}
-static void init_pmic_lcd(void);
-
int exynos_power_init(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int ret;
/*
@@ -53,7 +52,7 @@
return ret;
init_pmic_lcd();
-
+#endif
return 0;
}
@@ -84,6 +83,7 @@
static int adc_power_control(int on)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int ret;
struct pmic *p = pmic_get("MAX8998_PMIC");
if (!p)
@@ -97,6 +97,9 @@
MAX8998_LDO4, !!on);
return ret;
+#else
+ return 0;
+#endif
}
static unsigned int get_hw_revision(void)
@@ -144,6 +147,7 @@
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
int ret = 0;
struct pmic *p = pmic_get("MAX8998_PMIC");
if (!p)
@@ -175,7 +179,7 @@
puts("MAX8998 LDO setting error!\n");
return -1;
}
-
+#endif
return 0;
}
@@ -201,6 +205,7 @@
return 0;
}
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
static void init_pmic_lcd(void)
{
unsigned char val;
@@ -248,6 +253,7 @@
if (ret)
puts("LCD pmic initialisation error!\n");
}
+#endif
void exynos_cfg_lcd_gpio(void)
{
@@ -304,6 +310,7 @@
void exynos_lcd_power_on(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
struct pmic *p = pmic_get("MAX8998_PMIC");
if (!p)
@@ -314,6 +321,7 @@
pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
+#endif
}
void exynos_cfg_ldo(void)
@@ -328,8 +336,9 @@
int exynos_init(void)
{
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
char buf[16];
-
+#endif
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
switch (get_hwrev()) {
@@ -354,13 +363,14 @@
break;
}
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
/* Request soft I2C gpios */
strcpy(buf, "soft_i2c_scl");
gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
strcpy(buf, "soft_i2c_sda");
gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
-
+#endif
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig
new file mode 100644
index 0000000..3447c27
--- /dev/null
+++ b/board/samtec/vining_2000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAMTEC_VINING_2000
+
+config SYS_BOARD
+ default "vining_2000"
+
+config SYS_VENDOR
+ default "samtec"
+
+config SYS_CONFIG_NAME
+ default "vining_2000"
+
+endif
diff --git a/board/samtec/vining_2000/MAINTAINERS b/board/samtec/vining_2000/MAINTAINERS
new file mode 100644
index 0000000..027e527
--- /dev/null
+++ b/board/samtec/vining_2000/MAINTAINERS
@@ -0,0 +1,6 @@
+VINING_2000 BOARD
+M: Ingo Schroeck <open-source@samtec.de>
+S: Maintained
+F: board/samtec/vining_2000/
+F: include/configs/vining_2000.h
+F: configs/vining_2000_defconfig
diff --git a/board/samtec/vining_2000/Makefile b/board/samtec/vining_2000/Makefile
new file mode 100644
index 0000000..1b32f66
--- /dev/null
+++ b/board/samtec/vining_2000/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 samtec automotive software & electronics gmbh
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vining_2000.o
diff --git a/board/samtec/vining_2000/imximage.cfg b/board/samtec/vining_2000/imximage.cfg
new file mode 100644
index 0000000..4133dda
--- /dev/null
+++ b/board/samtec/vining_2000/imximage.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000028
+DATA 4 0x020e02fc 0x00000028
+DATA 4 0x020e05f4 0x00000028
+
+/* Control */
+DATA 4 0x020e0340 0x00000028
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000028
+DATA 4 0x020e0314 0x00000028
+DATA 4 0x020e0614 0x00000028
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00210022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4142013a
+DATA 4 0x021b0840 0x012e0123
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x43474949
+DATA 4 0x021b0850 0x38383c38
+
+/* Read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333040
+DATA 4 0x021b000c 0x676b52f2
+DATA 4 0x021b0010 0x926e8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x02008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
+DATA 4 0x021b001c 0x15108030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00007800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b001c 0x00000000
diff --git a/board/samtec/vining_2000/vining_2000.c b/board/samtec/vining_2000/vining_2000.c
new file mode 100644
index 0000000..c92f37c
--- /dev/null
+++ b/board/samtec/vining_2000/vining_2000.c
@@ -0,0 +1,517 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * Author: Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <pwm.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
+ PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm)
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
+
+#define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST)
+
+#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_PKE)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
+ MUX_MODE_SION,
+ /* LAN8720 PHY Reset */
+ MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwm_led_pads[] = {
+ MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
+ MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
+ MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#define PHY_RESET IMX_GPIO_NR(5, 9)
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+ unsigned char eth1addr[6];
+
+ /* just to get secound mac address */
+ imx_get_mac_from_fuse(1, eth1addr);
+ if (!getenv("eth1addr") && is_valid_ethaddr(eth1addr))
+ eth_setenv_enetaddr("eth1addr", eth1addr);
+
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+ /*
+ * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
+ * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
+ * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1],
+ IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
+ IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ goto eth_fail;
+
+ /* reset phy */
+ gpio_direction_output(PHY_RESET, 0);
+ mdelay(16);
+ gpio_set_value(PHY_RESET, 1);
+ mdelay(1);
+
+ ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
+ IMX_FEC_BASE);
+ if (ret)
+ goto eth_fail;
+
+ return ret;
+
+eth_fail:
+ printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
+ gpio_set_value(PHY_RESET, 0);
+ return ret;
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+ .gp = IMX_GPIO_NR(1, 0),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+ .gp = IMX_GPIO_NR(1, 1),
+ },
+};
+
+static struct pmic *pfuze_init(unsigned char i2cbus)
+{
+ struct pmic *p;
+ int ret;
+ u32 reg;
+
+ ret = power_pfuze100_init(i2cbus);
+ if (ret)
+ return NULL;
+
+ p = pmic_get("PFUZE100");
+ ret = pmic_probe(p);
+ if (ret)
+ return NULL;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+ return p;
+}
+
+static int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+ unsigned char offset, i, switch_num;
+ u32 id;
+ int ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+ id = id & 0xf;
+
+ if (id == 0) {
+ switch_num = 6;
+ offset = PFUZE100_SW1CMODE;
+ } else if (id == 1) {
+ switch_num = 4;
+ offset = PFUZE100_SW2MODE;
+ } else {
+ printf("Not supported, id=%d\n", id);
+ return -EINVAL;
+ }
+
+ ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+ if (ret < 0) {
+ printf("Set SW1AB mode error!\n");
+ return ret;
+ }
+
+ for (i = 0; i < switch_num - 1; i++) {
+ ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+ if (ret < 0) {
+ printf("Set switch 0x%x mode error!\n",
+ offset + i * SWITCH_SIZE);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+
+ p = pfuze_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OGT1 */
+ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_iomux_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+#endif
+
+#ifdef CONFIG_PWM_IMX
+static int set_pwm_leds(void)
+{
+ int ret;
+
+ imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
+ ARRAY_SIZE(pwm_led_pads));
+ /* enable backlight PWM 2, green LED */
+ ret = pwm_init(1, 0, 0);
+ if (ret)
+ goto error;
+ /* duty cycle 200ns, period: 8000ns */
+ ret = pwm_config(1, 200, 8000);
+ if (ret)
+ goto error;
+ ret = pwm_enable(1);
+ if (ret)
+ goto error;
+
+ /* enable backlight PWM 1, blue LED */
+ ret = pwm_init(0, 0, 0);
+ if (ret)
+ goto error;
+ /* duty cycle 200ns, period: 8000ns */
+ ret = pwm_config(0, 200, 8000);
+ if (ret)
+ goto error;
+ ret = pwm_enable(0);
+ if (ret)
+ goto error;
+
+ /* enable backlight PWM 6, red LED */
+ ret = pwm_init(5, 0, 0);
+ if (ret)
+ goto error;
+ /* duty cycle 200ns, period: 8000ns */
+ ret = pwm_config(5, 200, 8000);
+ if (ret)
+ goto error;
+ ret = pwm_enable(5);
+
+error:
+ return ret;
+}
+#else
+static int set_pwm_leds(void)
+{
+ return 0;
+}
+#endif
+
+#define ADCx_HC0 0x00
+#define ADCx_HS 0x08
+#define ADCx_HS_C0 BIT(0)
+#define ADCx_R0 0x0c
+#define ADCx_CFG 0x14
+#define ADCx_CFG_SWMODE 0x308
+#define ADCx_GC 0x18
+#define ADCx_GC_CAL BIT(7)
+
+static int read_adc(u32 *val)
+{
+ int ret;
+ void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
+
+ /* use software mode */
+ writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
+
+ /* start auto calibration */
+ setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
+ ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
+ if (ret)
+ goto adc_exit;
+
+ /* start conversion */
+ writel(0, b + ADCx_HC0);
+
+ /* wait for conversion */
+ ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
+ if (ret)
+ goto adc_exit;
+
+ /* read result */
+ *val = readl(b + ADCx_R0);
+
+adc_exit:
+ if (ret)
+ printf("ADC failure (ret=%i)\n", ret);
+ unmap_physmem(b, MAP_NOCACHE);
+ return ret;
+}
+
+#define VAL_UPPER 2498
+#define VAL_LOWER 1550
+
+static int set_pin_state(void)
+{
+ u32 val;
+ int ret;
+
+ ret = read_adc(&val);
+ if (ret)
+ return ret;
+
+ if (val >= VAL_UPPER)
+ setenv("pin_state", "connected");
+ else if (val < VAL_UPPER && val > VAL_LOWER)
+ setenv("pin_state", "open");
+ else
+ setenv("pin_state", "button");
+
+ return ret;
+}
+
+int board_late_init(void)
+{
+ int ret;
+
+ ret = set_pwm_leds();
+ if (ret)
+ return ret;
+
+ ret = set_pin_state();
+
+ return ret;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ setup_iomux_usb();
+
+ return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC4_BASE_ADDR, 0, 8},
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == USDHC4_BASE_ADDR)
+ return 1;
+ if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+ return !gpio_get_value(USDHC2_CD_GPIO);
+
+ return -EINVAL;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC4
+ * mmc1 USDHC2
+ */
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ if (ret) {
+ printf("Warning: failed to initialize USDHC4\n");
+ return ret;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+ if (ret) {
+ printf("Warning: failed to initialize USDHC2\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: VIN|ING 2000\n");
+
+ return 0;
+}
diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/samtec/vining_fpga/qts/sdram_config.h
index 74cb405..372e8bc 100644
--- a/board/samtec/vining_fpga/qts/sdram_config.h
+++ b/board/samtec/vining_fpga/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
index ed820d3..02d8ab3 100644
--- a/board/sandbox/README.sandbox
+++ b/board/sandbox/README.sandbox
@@ -320,6 +320,25 @@
The idle value on the SPI bus
+Block Device Emulation
+----------------------
+
+U-Boot can use raw disk images for block device emulation. To e.g. list
+the contents of the root directory on the second partion of the image
+"disk.raw", you can use the following commands:
+
+=>host bind 0 ./disk.raw
+=>ls host 0:2
+
+A disk image can be created using the following commands:
+
+$> truncate -s 1200M ./disk.raw
+$> echo -e "label: gpt\n,64M,U\n,,L" | /usr/sbin/sfdisk ./disk.raw
+$> lodev=`sudo losetup -P -f --show ./disk.raw`
+$> sudo mkfs.vfat -n EFI -v ${lodev}p1
+$> sudo mkfs.ext4 -L ROOT -v ${lodev}p2
+
+
Writing Sandbox Drivers
-----------------------
diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c
index 2f14f59..c4abc1d 100644
--- a/board/seco/common/mx6.c
+++ b/board/seco/common/mx6.c
@@ -12,7 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c
index 08566fc..341e727 100644
--- a/board/seco/mx6quq7/mx6quq7.c
+++ b/board/seco/mx6quq7/mx6quq7.c
@@ -12,7 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
diff --git a/board/shmin/Makefile b/board/shmin/Makefile
index daf36de..d169661 100644
--- a/board/shmin/Makefile
+++ b/board/shmin/Makefile
@@ -7,4 +7,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := shmin.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/shmin/shmin.c b/board/shmin/shmin.c
index 74d1e39..42bd126 100644
--- a/board/shmin/shmin.c
+++ b/board/shmin/shmin.c
@@ -33,16 +33,6 @@
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
int board_eth_init(bd_t *bis)
{
return ne2k_register();
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index a67d812..c7483fe 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -9,7 +9,7 @@
#if defined(CONFIG_SYS_NAND_BASE)
#include <nand.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
static int state;
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 3a1ce24..285588d 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -19,7 +19,7 @@
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/video.h>
diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
index edbaf89..83b8a35 100644
--- a/board/sr1500/qts/sdram_config.h
+++ b/board/sr1500/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 68443c9..e1d4ab1 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -1,5 +1,32 @@
if ARCH_SUNXI
+config IDENT_STRING
+ default " Allwinner Technology"
+
+config PRE_CONSOLE_BUFFER
+ default y
+
+config SPL_GPIO_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ default y
+
+config SPL_POWER_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
+
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig
config SUNXI_GEN_SUN4I
@@ -92,6 +119,7 @@
bool "sun9i (Allwinner A80)"
select CPU_V7
select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
@@ -114,11 +142,13 @@
config DRAM_CLK
int "sunxi dram clock speed"
+ default 792 if MACH_SUN9I
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
---help---
- Set the dram clock speed, valid range 240 - 480, must be a multiple
- of 24.
+ Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
+ must be a multiple of 24. For the sun9i (A80), the tested values
+ (for DDR3-1600) are 312 to 792.
if MACH_SUN5I || MACH_SUN7I
config DRAM_MBUS_CLK
@@ -133,6 +163,7 @@
int "sunxi dram zq value"
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
+ default 4145117 if MACH_SUN9I
---help---
Set the dram zq value.
@@ -225,7 +256,7 @@
config SYS_CLK_FREQ
default 816000000 if MACH_SUN50I
default 912000000 if MACH_SUN7I
- default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
+ default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 6f13cf6..e23d45e 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -94,6 +94,11 @@
S: Maintained
F: configs/A33-OLinuXino_defconfig
+A80 OPTIMUS BOARD
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/Merrii_A80_Optimus_defconfig
+
AINOL AW1 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
@@ -117,6 +122,11 @@
F: configs/Cubieboard2_defconfig
F: configs/Cubietruck_defconfig
+CUBIEBOARD4 BOARD
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/Cubieboard4_defconfig
+
CUBIETRUCK-PLUS BOARD
M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
@@ -217,6 +227,16 @@
S: Maintained
F: configs/MSI_Primo81_defconfig
+NANOPI-NEO BOARD
+M: Jelle van der Waa <jelle@vdwaa.nl>
+S: Maintained
+F: configs/nanopi_neo_defconfig
+
+NINTENDO NES CLASSIC EDITION BOARD
+M: FUKAUMI Naoki <naobsd@gmail.com>
+S: Maintained
+F: configs/Nintendo_NES_Classic_Edition_defconfig
+
R16 EVB PARROT BOARD
M: Quentin Schulz <quentin.schulz@free-electrons.com>
S: Maintained
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 6281c9d..5365638 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -307,6 +307,13 @@
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN9I)
+ /* SDC2: PC6-PC16 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
#endif
break;
diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
index 42b7c23..77b5000 100644
--- a/board/sysam/amcore/amcore.c
+++ b/board/sysam/amcore/amcore.c
@@ -1,7 +1,7 @@
/*
* Board functions for Sysam AMCORE (MCF5307 based) board
*
- * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
*
* SPDX-License-Identifier: GPL-2.0+
*
@@ -11,6 +11,8 @@
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
+#include <dm.h>
+#include <dm/platform_data/serial_coldfire.h>
void init_lcd(void)
{
@@ -91,7 +93,7 @@
out_be32((u32 *)0x00000004, 0xbeaddeed);
/* issue AUTOREFRESH */
out_be32(&dc->dacr0, 0x0000b304);
- /* let refresh occour */
+ /* let refresh occur */
fudelay(1);
out_be32(&dc->dacr0, 0x0000b344);
@@ -99,3 +101,14 @@
return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
}
+
+static struct coldfire_serial_platdata mcf5307_serial_plat = {
+ .base = CONFIG_SYS_UART_BASE,
+ .port = 0,
+ .baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DEVICE(coldfire_serial) = {
+ .name = "serial_coldfire",
+ .platdata = &mcf5307_serial_plat,
+};
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index f784459..db0c58f 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -8,7 +8,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
@@ -359,6 +359,39 @@
}
#endif /* CONFIG_VIDEO_IPUV3 */
+static int ar8035_phy_fixup(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ ar8035_phy_fixup(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
diff --git a/board/technexion/pico-imx6ul/imximage.cfg b/board/technexion/pico-imx6ul/imximage.cfg
index 9145b44..c753a71 100644
--- a/board/technexion/pico-imx6ul/imximage.cfg
+++ b/board/technexion/pico-imx6ul/imximage.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
index 48d207f..4a3d094 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -140,7 +140,7 @@
#ifdef CONFIG_SPL_OS_BOOT
/*
- * Do board specific preperation before SPL
+ * Do board specific preparation before SPL
* Linux boot
*/
void spl_board_prepare_for_linux(void)
diff --git a/board/technologic/ts4600/Kconfig b/board/technologic/ts4600/Kconfig
new file mode 100644
index 0000000..d0dc2e1
--- /dev/null
+++ b/board/technologic/ts4600/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TS4600
+
+config SYS_BOARD
+ default "ts4600"
+
+config SYS_VENDOR
+ default "technologic"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "ts4600"
+
+endif
diff --git a/board/technologic/ts4600/MAINTAINERS b/board/technologic/ts4600/MAINTAINERS
new file mode 100644
index 0000000..6f683b5
--- /dev/null
+++ b/board/technologic/ts4600/MAINTAINERS
@@ -0,0 +1,6 @@
+TS4600 BOARD
+M: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+S: Maintained
+F: board/technologic/ts4600/
+F: include/configs/ts4600.h
+F: configs/ts4600_defconfig
diff --git a/board/technologic/ts4600/Makefile b/board/technologic/ts4600/Makefile
new file mode 100644
index 0000000..faa2970
--- /dev/null
+++ b/board/technologic/ts4600/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2016 Savoir-faire Linux
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := ts4600.o
+else
+obj-y := iomux.o
+endif
diff --git a/board/technologic/ts4600/iomux.c b/board/technologic/ts4600/iomux.c
new file mode 100644
index 0000000..1398bbe
--- /dev/null
+++ b/board/technologic/ts4600/iomux.c
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Based on work from TS7680 code by:
+ * Kris Bahnsen <kris@embeddedarm.com>
+ * Mark Featherston <mark@embeddedarm.com>
+ * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
+ *
+ * Derived from MX28EVK code by
+ * Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* DUART */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+ /* MMC0 slot power enable */
+ MX28_PAD_PWM3__GPIO_3_28 |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+};
+
+#define HW_DRAM_CTL29 (0x74 >> 2)
+#define CS_MAP 0xf
+#define COLUMN_SIZE 0x2
+#define ADDR_PINS 0x1
+#define APREBIT 0xa
+
+#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
+ ADDR_PINS << 8 | APREBIT)
+
+#define HW_DRAM_CTL39 (0x9c >> 2)
+#define TFAW 0xb
+#define TDLL 0xc8
+
+#define HW_DRAM_CTL39_CONFIG (TFAW << 24 | TDLL)
+
+#define HW_DRAM_CTL41 (0xa4 >> 2)
+#define TPDEX 0x2
+#define TRCD_INT 0x4
+#define TRC 0xd
+
+#define HW_DRAM_CTL41_CONFIG (TPDEX << 24 | TRCD_INT << 8 | TRC)
+
+#define HW_DRAM_CTL42 (0xa8 >> 2)
+#define TRAS_MAX 0x36a6
+#define TRAS_MIN 0xa
+
+#define HW_DRAM_CTL42_CONFIG (TRAS_MAX << 8 | TRAS_MIN)
+
+#define HW_DRAM_CTL43 (0xac >> 2)
+#define TRP 0x4
+#define TRFC 0x27
+#define TREF 0x2a0
+
+#define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
+ dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG;
+ dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG;
+ dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG;
+ dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/technologic/ts4600/ts4600.c b/board/technologic/ts4600/ts4600.c
new file mode 100644
index 0000000..70dfead
--- /dev/null
+++ b/board/technologic/ts4600/ts4600.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Based on work from TS7680 code by:
+ * Kris Bahnsen <kris@embeddedarm.com>
+ * Mark Featherston <mark@embeddedarm.com>
+ * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
+ *
+ * Derived from MX28EVK code by
+ * Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clocks at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+static int ts4600_mmc_cd(int id)
+{
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ mxs_iomux_setup_pad(MX28_PAD_PWM3__GPIO_3_28);
+
+ /* Power-on SD */
+ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 1);
+ udelay(1000);
+ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+
+ /* SD card */
+ ret = mxsmmc_initialize(bis, 0, NULL, ts4600_mmc_cd);
+ if(ret != 0) {
+ printf("SD controller initialized with %d\n", ret);
+ }
+
+ return ret;
+}
+#endif
+
+int checkboard(void)
+{
+ puts("Board: TS4600\n");
+
+ return 0;
+}
diff --git a/board/technologic/ts4800/ts4800.c b/board/technologic/ts4800/ts4800.c
index 6ef15e1..eef6922 100644
--- a/board/technologic/ts4800/ts4800.c
+++ b/board/technologic/ts4800/ts4800.c
@@ -12,7 +12,7 @@
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx51.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
diff --git a/board/terasic/de0-nano-soc/MAINTAINERS b/board/terasic/de0-nano-soc/MAINTAINERS
index 351c456..7f4cf1e 100644
--- a/board/terasic/de0-nano-soc/MAINTAINERS
+++ b/board/terasic/de0-nano-soc/MAINTAINERS
@@ -1,5 +1,5 @@
SOCFPGA ATLAS BOARD
-M: Dinh Nguyen <dinguyen@opensource.altera.com>
+M: Dinh Nguyen <dinguyen@kernel.org>
S: Maintained
F: include/configs/socfpga_de0_nano_soc.h
F: configs/socfpga_de0_nano_soc_defconfig
diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h
index 7084797..d96b28a 100644
--- a/board/terasic/de0-nano-soc/qts/sdram_config.h
+++ b/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -42,6 +42,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
diff --git a/board/terasic/de1-soc/MAINTAINERS b/board/terasic/de1-soc/MAINTAINERS
new file mode 100644
index 0000000..bd7a8d5
--- /dev/null
+++ b/board/terasic/de1-soc/MAINTAINERS
@@ -0,0 +1,5 @@
+DE1-SoC BOARD
+M: Anatolij Gustschin <agust@denx.de>
+S: Maintained
+F: include/configs/socfpga_de1_soc.h
+F: configs/socfpga_de1_soc_defconfig
diff --git a/board/terasic/de1-soc/Makefile b/board/terasic/de1-soc/Makefile
new file mode 100644
index 0000000..86f9b78
--- /dev/null
+++ b/board/terasic/de1-soc/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o
diff --git a/board/terasic/de1-soc/qts/iocsr_config.h b/board/terasic/de1-soc/qts/iocsr_config.h
new file mode 100644
index 0000000..3ca1968
--- /dev/null
+++ b/board/terasic/de1-soc/qts/iocsr_config.h
@@ -0,0 +1,660 @@
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00018060,
+ 0x00000000,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x00020000,
+ 0x06018000,
+ 0x06000000,
+ 0x00000018,
+ 0x00006018,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x00100000,
+ 0x300C0000,
+ 0x300000C0,
+ 0x000000C0,
+ 0x000300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x20000000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x000300C0,
+ 0x10000000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0000C030,
+ 0x0300C000,
+ 0x03000000,
+ 0x0000300C,
+ 0x0000300C,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x01800000,
+ 0x00000006,
+ 0x00002000,
+ 0x00000400,
+ 0x00000000,
+ 0x00C03000,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000200,
+ 0x00601806,
+ 0x00000000,
+ 0x80600000,
+ 0x80000601,
+ 0x00000601,
+ 0x00000100,
+ 0x00300C03,
+ 0xC0300C00,
+ 0xC0300000,
+ 0xC0000300,
+ 0x000C0300,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x300C0300,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x000300C0,
+ 0x00008000,
+ 0x00080000,
+ 0x18060000,
+ 0x18000000,
+ 0x00018060,
+ 0x00020000,
+ 0x00004000,
+ 0x200300C0,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x00002000,
+ 0x10018060,
+ 0x06018000,
+ 0x06000000,
+ 0x00010018,
+ 0x00006018,
+ 0x00001000,
+ 0x0000C030,
+ 0x00000000,
+ 0x03000000,
+ 0x0000800C,
+ 0x00C0300C,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x0C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xE4400000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x40680208,
+ 0x41034051,
+ 0x02081A00,
+ 0x802080D0,
+ 0x34010406,
+ 0x01A02490,
+ 0x080D0000,
+ 0x51406802,
+ 0x00410340,
+ 0xD000001A,
+ 0x06802080,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000FF0,
+ 0x72200000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x6A1C0000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x1A870001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x40680C30,
+ 0x49034010,
+ 0x12481A02,
+ 0x802080D0,
+ 0x34051406,
+ 0x01A00040,
+ 0x080D0002,
+ 0x51406802,
+ 0x02490340,
+ 0xD012481A,
+ 0x06802080,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xE3CF23DA,
+ 0xF796591E,
+ 0x0344E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x01040680,
+ 0xD271C47A,
+ 0x1EE3CF23,
+ 0x88F79659,
+ 0x000344E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00600391,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xA3CF23DA,
+ 0xF796591E,
+ 0x0344E388,
+ 0x821A028A,
+ 0x0000D000,
+ 0x00000680,
+ 0xD271C47A,
+ 0x1EA2CB23,
+ 0x88F79A69,
+ 0x000344E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x04864000,
+ 0x69A47A01,
+ 0x9228A3D6,
+ 0xF456591E,
+ 0x03549248,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD669A47A,
+ 0x1EE3CF23,
+ 0x48F45659,
+ 0x00035492,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x08864000,
+ 0x71C47A02,
+ 0xA2CB23D2,
+ 0xF796591E,
+ 0x0344A288,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xDA49247A,
+ 0x1EE3CF23,
+ 0x88F79659,
+ 0x000344E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x40002000,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x08000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x20001000,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/qts/pinmux_config.h b/board/terasic/de1-soc/qts/pinmux_config.h
new file mode 100644
index 0000000..9a83e85
--- /dev/null
+++ b/board/terasic/de1-soc/qts/pinmux_config.h
@@ -0,0 +1,219 @@
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 1, /* GENERALIO3 */
+ 1, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 0, /* GENERALIO13 */
+ 0, /* GENERALIO14 */
+ 1, /* GENERALIO15 */
+ 1, /* GENERALIO16 */
+ 1, /* GENERALIO17 */
+ 1, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/qts/pll_config.h b/board/terasic/de1-soc/qts/pll_config.h
new file mode 100644
index 0000000..543b8ea
--- /dev/null
+++ b/board/terasic/de1-soc/qts/pll_config.h
@@ -0,0 +1,91 @@
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/qts/sdram_config.h b/board/terasic/de1-soc/qts/sdram_config.h
new file mode 100644
index 0000000..171a1ad
--- /dev/null
+++ b/board/terasic/de1-soc/qts/sdram_config.h
@@ -0,0 +1,344 @@
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ 0x4C
+#define RW_MGR_GUARANTEED_READ_CONT 0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7B
+#define RW_MGR_IDLE_LOOP2 0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1 0x61
+#define RW_MGR_READ_B2B_WAIT2 0x6B
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7D
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 8
+#define CALIB_VFIFO_OFFSET 6
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 99
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 99
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080431,
+ 0x10080530,
+ 0x10090044,
+ 0x100a0010,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080449,
+ 0x100804c8,
+ 0x100a0024,
+ 0x10090008,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/socfpga.c b/board/terasic/de1-soc/socfpga.c
new file mode 100644
index 0000000..0d29e44
--- /dev/null
+++ b/board/terasic/de1-soc/socfpga.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ spl_boot_list[0] = spl_boot_device();
+
+ switch (spl_boot_list[0]) {
+ case BOOT_DEVICE_MMC1:
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ break;
+ }
+}
diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h
index 769aa77..9906436 100644
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index c1db289..d621682 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -126,6 +126,12 @@
return &theadorable_serdes_cfg[0];
}
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+ /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
+ return 0x01;
+}
+
int board_early_init_f(void)
{
/* Configure MPP */
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
index 97374bd..a84e91b 100644
--- a/board/ti/am335x/Kconfig
+++ b/board/ti/am335x/Kconfig
@@ -1,5 +1,14 @@
if TARGET_AM335X_EVM
+config SPL_ENV_SUPPORT
+ default y
+
+config SPL_WATCHDOG_SUPPORT
+ default y
+
+config SPL_YMODEM_SUPPORT
+ default y
+
config SYS_BOARD
default "am335x"
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 56f4984..8eaf3e9 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -25,6 +25,7 @@
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
+#include <asm/omap_sec_common.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
@@ -46,19 +47,33 @@
#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
+#define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
+#define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
-#if defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-#endif
+
+#define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
+#define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
+
+#define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
+#define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
+
+#define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
+#define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
/*
* Read header information from EEPROM into global structure.
*/
-static inline int __maybe_unused read_eeprom(void)
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+void do_board_detect(void)
{
- return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
+ printf("ti_i2c_eeprom_init failed\n");
}
+#endif
#ifndef CONFIG_DM_SERIAL
struct serial_device *default_serial_console(void)
@@ -94,6 +109,16 @@
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};
+static const struct emif_regs ddr2_evm_emif_reg_data = {
+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+ .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J128MJT125_RD_DQS,
.datawdsratio0 = MT41J128MJT125_WR_DQS,
@@ -183,6 +208,7 @@
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
@@ -193,6 +219,7 @@
.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+ .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
.zq_config = MT41J512M8RH125_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
@@ -239,9 +266,6 @@
{
int mpu_vdd;
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
@@ -379,11 +403,6 @@
const struct dpll_params *get_dpll_ddr_params(void)
{
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
if (board_is_evm_sk())
return &dpll_ddr_evm_sk;
else if (board_is_bone_lt() || board_is_icev2())
@@ -413,9 +432,6 @@
void set_mux_conf_regs(void)
{
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
enable_board_pin_mux();
}
@@ -453,9 +469,6 @@
void sdram_init(void)
{
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
if (board_is_evm_sk()) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
@@ -485,15 +498,18 @@
config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
&ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
0);
+ else if (board_is_gp_evm())
+ config_ddr(266, &ioregs, &ddr2_data,
+ &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
else
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
#endif
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+#if !defined(CONFIG_SPL_BUILD) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void request_and_set_gpio(int gpio, char *name)
+static void request_and_set_gpio(int gpio, char *name, int val)
{
int ret;
@@ -509,7 +525,7 @@
goto err_free_gpio;
}
- gpio_set_value(gpio, 1);
+ gpio_set_value(gpio, val);
return;
@@ -517,7 +533,8 @@
gpio_free(gpio);
}
-#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N);
+#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
+#define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
/**
* RMII mode on ICEv2 board needs 50MHz clock. Given the clock
@@ -547,20 +564,76 @@
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
gpmc_init();
#endif
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
- int rv;
+#if !defined(CONFIG_SPL_BUILD) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (board_is_icev2()) {
+ int rv;
+ u32 reg;
+
REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
- REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
+ /* Make J19 status available on GPIO1_26 */
+ REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
+
REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
+ /*
+ * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
+ * jumpers near the port. Read the jumper value and set
+ * the pinmux, external mux and PHY clock accordingly.
+ * As jumper line is overridden by PHY RX_DV pin immediately
+ * after bootstrap (power-up/reset), we need to sample
+ * it during PHY reset using GPIO rising edge detection.
+ */
REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
+ /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
+ reg = readl(GPIO0_RISINGDETECT) | BIT(11);
+ writel(reg, GPIO0_RISINGDETECT);
+ reg = readl(GPIO1_RISINGDETECT) | BIT(26);
+ writel(reg, GPIO1_RISINGDETECT);
+ /* Reset PHYs to capture the Jumper setting */
+ gpio_set_value(GPIO_PHY_RESET, 0);
+ udelay(2); /* PHY datasheet states 1uS min. */
+ gpio_set_value(GPIO_PHY_RESET, 1);
+
+ reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
+ if (reg) {
+ writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
+ /* RMII mode */
+ printf("ETH0, CPSW\n");
+ } else {
+ /* MII mode */
+ printf("ETH0, PRU\n");
+ cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
+ }
+
+ reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
+ if (reg) {
+ writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
+ /* RMII mode */
+ printf("ETH1, CPSW\n");
+ gpio_set_value(GPIO_MUX_MII_CTRL, 1);
+ } else {
+ /* MII mode */
+ printf("ETH1, PRU\n");
+ cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
+ }
+
+ /* disable rising edge IRQs */
+ reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
+ writel(reg, GPIO0_RISINGDETECT);
+ reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
+ writel(reg, GPIO1_RISINGDETECT);
rv = setup_clock_synthesizer(&cdce913_data);
if (rv) {
printf("Clock synthesizer setup failed %d\n", rv);
return rv;
}
+
+ /* reset PHYs */
+ gpio_set_value(GPIO_PHY_RESET, 0);
+ udelay(2); /* PHY datasheet states 1uS min. */
+ gpio_set_value(GPIO_PHY_RESET, 1);
}
#endif
@@ -570,17 +643,57 @@
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- int rc;
- char *name = NULL;
+#if !defined(CONFIG_SPL_BUILD)
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+#endif
- rc = read_eeprom();
- if (rc)
- puts("Could not get board ID.\n");
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ char *name = NULL;
if (board_is_bbg1())
name = "BBG1";
set_board_info_env(name);
+
+ /*
+ * Default FIT boot on HS devices. Non FIT images are not allowed
+ * on HS devices.
+ */
+ if (get_device_type() == HS_DEVICE)
+ setenv("boot_fit", "1");
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ mac_lo = readl(&cdev->macid1l);
+ mac_hi = readl(&cdev->macid1h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
#endif
return 0;
@@ -651,11 +764,15 @@
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
+#if defined(CONFIG_USB_ETHER) && \
+ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
- __maybe_unused struct ti_am_eeprom *header;
- /* try reading mac address from efuse */
+ /*
+ * use efuse mac address for USB ethernet as we know that
+ * both CPSW and USB ethernet will never be active at the same time
+ */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
@@ -664,35 +781,13 @@
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+#endif
+
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
- if (!getenv("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
#ifdef CONFIG_DRIVER_TI_CPSW
-
- mac_lo = readl(&cdev->macid1l);
- mac_hi = readl(&cdev->macid1h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!getenv("eth1addr")) {
- if (is_valid_ethaddr(mac_addr))
- eth_setenv_enetaddr("eth1addr", mac_addr);
- }
-
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
if (board_is_bone() || board_is_bone_lt() ||
board_is_idk()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
@@ -775,3 +870,10 @@
return -1;
}
#endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+ secure_boot_verify_image(p_image, p_size);
+}
+#endif
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 9776df7..48c139a 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -11,6 +11,19 @@
#ifndef _BOARD_H_
#define _BOARD_H_
+/**
+ * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
+ * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
+ * Synchronization Lost errors. The values are the biggest that work
+ * reliably with offered video modes and the memory subsystem on the
+ * boards. These register have are briefly documented in "7.3.3.5.2
+ * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and
+ * REG_COS_COUNT_2 do not have any effect on current versions of
+ * AM335x.
+ */
+#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414
+#define EMIF_OCP_CONFIG_AM335X_EVM 0x003d3d3d
+
static inline int board_is_bone(void)
{
return board_ti_is("A335BONE");
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 8afa5f9..ad85b3a 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -397,7 +397,7 @@
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
} else {
- puts("Unknown board, cannot configure pinmux.");
- hang();
+ /* Unknown board. We might still be able to boot. */
+ puts("Bad EEPROM or unknown board, cannot configure pinmux.");
}
}
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 27c311e..390cc16 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <spl.h>
#include <usb.h>
#include <asm/omap_sec_common.h>
@@ -39,10 +39,13 @@
/*
* Read header information from EEPROM into global structure.
*/
-static inline int __maybe_unused read_eeprom(void)
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+void do_board_detect(void)
{
- return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
+ if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
+ printf("ti_i2c_eeprom_init failed\n");
}
+#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
@@ -337,9 +340,6 @@
{
int ind = get_sys_clk_index();
- if (read_eeprom() < 0)
- return NULL;
-
if (board_is_eposevm())
return &epos_evm_dpll_ddr[ind];
else if (board_is_evm() || board_is_sk())
@@ -495,9 +495,6 @@
{
const struct dpll_params *mpu_params;
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
/* Ensure I2C is initialized for PMIC configuration */
gpi2c_init();
@@ -537,8 +534,6 @@
void sdram_init(void)
{
- if (read_eeprom() < 0)
- return;
/*
* EPOS EVM has 1GB LPDDR2 connected to EMIF.
* GP EMV has 1GB DDR3 connected to EMIF
@@ -637,6 +632,13 @@
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
set_board_info_env(NULL);
+
+ /*
+ * Default FIT boot on HS devices. Non FIT images are not allowed
+ * on HS devices.
+ */
+ if (get_device_type() == HS_DEVICE)
+ setenv("boot_fit", "1");
#endif
return 0;
}
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 64de602..5f2d4df 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -35,8 +35,14 @@
#include "mux_data.h"
#define board_is_x15() board_ti_is("BBRDX15_")
+#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
+ (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
#define board_is_am572x_evm() board_ti_is("AM572PM_")
+#define board_is_am572x_evm_reva3() \
+ (board_ti_is("AM572PM_") && \
+ (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
#define board_is_am572x_idk() board_ti_is("AM572IDK")
+#define board_is_am571x_idk() board_ti_is("AM571IDK")
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
@@ -49,6 +55,9 @@
#define SYSINFO_BOARD_NAME_MAX_LEN 45
+#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
+#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
+
const struct omap_sysinfo sysinfo = {
"Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
};
@@ -58,9 +67,17 @@
.is_ma_present = 0x1
};
+static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
+ .dmm_lisa_map_3 = 0x80640100,
+ .is_ma_present = 0x1
+};
+
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
- *dmm_lisa_regs = &beagle_x15_lisa_regs;
+ if (board_is_am571x_idk())
+ *dmm_lisa_regs = &am571x_idk_lisa_regs;
+ else
+ *dmm_lisa_regs = &beagle_x15_lisa_regs;
}
static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
@@ -217,35 +234,47 @@
}
struct vcores_data beagle_x15_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS6,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
@@ -253,41 +282,81 @@
};
struct vcores_data am572x_idk_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+int get_voltrail_opp(int rail_offset)
+{
+ int opp;
+
+ switch (rail_offset) {
+ case VOLT_MPU:
+ opp = DRA7_MPU_OPP;
+ break;
+ case VOLT_CORE:
+ opp = DRA7_CORE_OPP;
+ break;
+ case VOLT_GPU:
+ opp = DRA7_GPU_OPP;
+ break;
+ case VOLT_EVE:
+ opp = DRA7_DSPEVE_OPP;
+ break;
+ case VOLT_IVA:
+ opp = DRA7_IVA_OPP;
+ break;
+ default:
+ opp = OPP_NOM;
+ }
+
+ return opp;
+}
+
+
#ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
@@ -322,6 +391,8 @@
bname = "AM572x EVM";
else if (board_is_am572x_idk())
bname = "AM572x IDK";
+ else if (board_is_am571x_idk())
+ bname = "AM571x IDK";
if (bname)
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
@@ -338,15 +409,24 @@
if (rc)
goto invalid_eeprom;
- if (board_is_x15())
- name = "beagle_x15";
- else if (board_is_am572x_evm())
- name = "am57xx_evm";
- else if (board_is_am572x_idk())
+ if (board_is_x15()) {
+ if (board_is_x15_revb1())
+ name = "beagle_x15_revb1";
+ else
+ name = "beagle_x15";
+ } else if (board_is_am572x_evm()) {
+ if (board_is_am572x_evm_reva3())
+ name = "am57xx_evm_reva3";
+ else
+ name = "am57xx_evm";
+ } else if (board_is_am572x_idk()) {
name = "am572x_idk";
- else
+ } else if (board_is_am571x_idk()) {
+ name = "am571x_idk";
+ } else {
printf("Unidentified board claims %s in eeprom header\n",
board_ti_get_name());
+ }
invalid_eeprom:
set_board_info_env(name);
@@ -380,12 +460,33 @@
int board_late_init(void)
{
setup_board_eeprom_env();
+ u8 val;
/*
* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
* This is the POWERHOLD-in-Low behavior.
*/
palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+
+ /*
+ * Default FIT boot on HS devices. Non FIT images are not allowed
+ * on HS devices.
+ */
+ if (get_device_type() == HS_DEVICE)
+ setenv("boot_fit", "1");
+
+ /*
+ * Set the GPIO7 Pad to POWERHOLD. This has higher priority
+ * over DEV_CTRL.DEV_ON bit. This can be reset in case of
+ * PMIC Power off. So to be on the safer side set it back
+ * to POWERHOLD mode irrespective of the current state.
+ */
+ palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
+ &val);
+ val = val | TPS65903X_PAD2_POWERHOLD_MASK;
+ palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
+ val);
+
return 0;
}
@@ -401,21 +502,58 @@
const struct pad_conf_entry *pconf;
const struct iodelay_cfg_entry *iod;
int pconf_sz, iod_sz;
+ int ret;
if (board_is_am572x_idk()) {
pconf = core_padconf_array_essential_am572x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
iod = iodelay_cfg_array_am572x_idk;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+ } else if (board_is_am571x_idk()) {
+ pconf = core_padconf_array_essential_am571x_idk;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
+ iod = iodelay_cfg_array_am571x_idk;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
} else {
/* Common for X15/GPEVM */
pconf = core_padconf_array_essential_x15;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
- iod = iodelay_cfg_array_x15;
- iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
+ /* There never was an SR1.0 X15.. So.. */
+ if (omap_revision() == DRA752_ES1_1) {
+ iod = iodelay_cfg_array_x15_sr1_1;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
+ } else {
+ /* Since full production should switch to SR2.0 */
+ iod = iodelay_cfg_array_x15_sr2_0;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
+ }
}
- __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
+ /* Setup I/O isolation */
+ ret = __recalibrate_iodelay_start();
+ if (ret)
+ goto err;
+
+ /* Do the muxing here */
+ do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+
+ /* Now do the weird minor deltas that should be safe */
+ if (board_is_x15() || board_is_am572x_evm()) {
+ if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
+ pconf = core_padconf_array_delta_x15_sr2_0;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
+ } else {
+ pconf = core_padconf_array_delta_x15_sr1_1;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
+ }
+ do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+ }
+
+ /* Setup IOdelay configuration */
+ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
+err:
+ /* Closeup.. remove isolation */
+ __recalibrate_iodelay_end(ret);
}
#endif
@@ -447,26 +585,6 @@
#endif
#ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss1 = {
- .maximum_speed = USB_SPEED_SUPER,
- .base = DRA7_USB_OTG_SS1_BASE,
- .tx_fifo_resize = false,
- .index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss1_glue = {
- .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
- .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
- .index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy1_device = {
- .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
- .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
- .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
- .index = 0,
-};
-
static struct dwc3_device usb_otg_ss2 = {
.maximum_speed = USB_SPEED_HIGH,
.base = DRA7_USB_OTG_SS2_BASE,
@@ -673,8 +791,8 @@
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
- /* The phy address for the AM572x IDK are different than x15 */
- if (board_is_am572x_idk()) {
+ /* The phy address for the AM57xx IDK are different than x15 */
+ if (board_is_am572x_idk() || board_is_am571x_idk()) {
cpsw_data.slave_data[0].phy_addr = 0;
cpsw_data.slave_data[1].phy_addr = 1;
}
@@ -743,14 +861,23 @@
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
- if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15"))
+ if (board_is_x15()) {
+ if (board_is_x15_revb1()) {
+ if (!strcmp(name, "am57xx-beagle-x15-revb1"))
+ return 0;
+ } else if (!strcmp(name, "am57xx-beagle-x15")) {
+ return 0;
+ }
+ } else if (board_is_am572x_evm() &&
+ !strcmp(name, "am57xx-beagle-x15")) {
return 0;
- else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
+ } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
return 0;
- else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk"))
+ } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
return 0;
- else
- return -1;
+ }
+
+ return -1;
}
#endif
@@ -759,4 +886,11 @@
{
secure_boot_verify_image(p_image, p_size);
}
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+ secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
#endif
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index b5ea8ad..2f5243e 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -13,22 +13,22 @@
#include <asm/arch/mux_dra7xx.h>
const struct pad_conf_entry core_padconf_array_essential_x15[] = {
- {GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
- {GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
- {GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
- {GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
- {GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
- {GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
- {GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
- {GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
- {GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
- {GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
- {GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */
- {GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */
- {GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */
- {GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */
- {GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */
- {GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */
+ {GPMC_AD0, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
+ {GPMC_AD1, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
+ {GPMC_AD2, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
+ {GPMC_AD3, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
+ {GPMC_AD4, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
+ {GPMC_AD5, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
+ {GPMC_AD6, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
+ {GPMC_AD7, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
+ {GPMC_AD8, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
+ {GPMC_AD9, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
+ {GPMC_AD10, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */
+ {GPMC_AD11, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */
+ {GPMC_AD12, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */
+ {GPMC_AD13, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */
+ {GPMC_AD14, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */
+ {GPMC_AD15, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */
{GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */
{GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */
{GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */
@@ -60,7 +60,7 @@
{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
{GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
{GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */
- {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */
+ {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_cs3.vin3a_clk0 */
{GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */
{GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
{GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
@@ -68,7 +68,7 @@
{GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
{GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
{GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */
- {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */
+ {VIN1B_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1b_clk1.gpio2_31 */
{VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */
{VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */
{VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */
@@ -83,120 +83,119 @@
{VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */
{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
{VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */
- {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */
{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
{VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */
{VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */
{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
{VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */
- {VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
+ {VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
- {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D1, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
{VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */
- {VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */
+ {VIN2A_D3, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */
{VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */
- {VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */
+ {VIN2A_D5, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */
{VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */
{VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */
{VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */
{VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */
- {VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */
+ {VIN2A_D10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */
{VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */
- {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
- {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
{VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
{VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */
+ {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_OUTPUT)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */
{RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */
{UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */
{UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */
- {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN)}, /* usb2_drvvbus.usb2_drvvbus */
{GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */
{GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */
{GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */
- {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
+ {XREF_CLK0, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
{XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */
{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
- {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
{MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */
{MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */
{MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */
{MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
- {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
- {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
+ {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.i2c5_sda */
+ {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.i2c5_scl */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */
- {MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */
- {MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */
- {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */
+ {MCASP1_AXR8, (M14 | PIN_INPUT)}, /* mcasp1_axr8.gpio5_10 */
+ {MCASP1_AXR9, (M14 | PIN_INPUT)}, /* mcasp1_axr9.gpio5_11 */
+ {MCASP1_AXR10, (M14 | PIN_INPUT)}, /* mcasp1_axr10.gpio5_12 */
+ {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr11.gpio4_17 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
{MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */
- {MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */
+ {MCASP2_FSX, (M0 | PIN_INPUT)}, /* mcasp2_fsx.mcasp2_fsx */
{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
{MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */
{MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */
{MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */
- {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */
- {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */
+ {MCASP2_AXR2, (M0 | PIN_INPUT)}, /* mcasp2_axr2.mcasp2_axr2 */
+ {MCASP2_AXR3, (M0 | PIN_INPUT)}, /* mcasp2_axr3.mcasp2_axr3 */
{MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */
{MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */
{MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */
@@ -205,84 +204,322 @@
{MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */
{MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */
{MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */
- {MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */
+ {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_aclkx.uart8_rxd */
+ {MCASP4_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */
{MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */
- {MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
- {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */
- {MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */
+ {MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
+ {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_aclkx.uart9_rxd */
+ {MCASP5_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */
{MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */
- {MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
+ {MMC1_CLK, (M0 | PIN_OUTPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */
- {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
- {GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
- {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
- {MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */
- {MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */
- {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */
- {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */
- {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */
- {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */
- {MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */
+ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
+ {GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
+ {GPIO6_11, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
+ {MMC3_CLK, (M0 | PIN_OUTPUT_PULLUP | MANUAL_MODE)}, /* mmc3_clk.mmc3_clk */
+ {MMC3_CMD, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_cmd.mmc3_cmd */
+ {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat0.mmc3_dat0 */
+ {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat1.mmc3_dat1 */
+ {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat2.mmc3_dat2 */
+ {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat3.mmc3_dat3 */
+ {MMC3_DAT4, (M1 | PIN_OUTPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */
{MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */
{MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */
- {MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */
+ {MMC3_DAT7, (M1 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */
{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
- {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
- {SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS0, (M14 | PIN_INPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_INPUT)}, /* spi1_cs1.gpio7_11 */
{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */
{SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */
{SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */
{SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */
- {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */
+ {SPI2_CS0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_cs0.gpio7_17 */
{DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
{DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
- {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */
- {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */
- {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */
- {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
- {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
- {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M0 | PULL_UP)}, /* Wakeup0.Wakeup0 */
- {WAKEUP1, (M0)}, /* Wakeup1.Wakeup1 */
- {WAKEUP2, (M0)}, /* Wakeup2.Wakeup2 */
- {WAKEUP3, (M0 | PULL_UP)}, /* Wakeup3.Wakeup3 */
- {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
- {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
- {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN)}, /* uart1_txd.uart1_txd */
+ {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */
+ {UART1_RTSN, (M14 | PIN_INPUT)}, /* uart1_rtsn.gpio7_25 */
+ {UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_rxd.gpio7_26 */
+ {UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.gpio7_27 */
+ {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_OUTPUT_PULLDOWN)}, /* uart2_rtsn.uart3_txd */
+ {I2C1_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_sda.i2c1_sda */
+ {I2C1_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_scl.i2c1_scl */
+ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
+ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
+ {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */
+ {TDO, (M0 | PIN_OUTPUT)}, /* tdo.tdo */
+ {TCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* tclk.tclk */
+ {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */
+ {RTCK, (M0 | PIN_OUTPUT)}, /* rtck.rtck */
+ {EMU0, (M0 | PIN_INPUT)}, /* emu0.emu0 */
+ {EMU1, (M0 | PIN_INPUT)}, /* emu1.emu1 */
+ {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
+ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = {
+ {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
+};
+
+const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = {
+ {VIN1A_CLK0, (M14 | PIN_INPUT)}, /* vin1a_clk0.gpio2_30 */
};
const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
- {GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
- {GPMC_A1, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
- {GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
- {GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
- {GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
- {GPMC_A5, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
- {GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
- {GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
- {GPMC_A8, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
- {GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
- {GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
- {GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
- {GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
+ {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
+ {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
+ {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
+ {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
+ {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
+ {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
+ {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
+ {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
+ {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
+ {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
+ {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
+ {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
+ {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
+ {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+ {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
+ {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
+ {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */
+ {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */
+ {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
+ {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */
+ {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */
+ {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */
+ {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */
+ {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */
+ {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
+ {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */
+ {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */
+ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
+ {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
+ {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */
+ {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
+ {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
+ {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */
+ {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */
+ {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
+ {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
+ {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
+ {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
+ {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
+ {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
+ {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
+ {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
+ {MCASP1_FSX, (M11 | PIN_INPUT)}, /* mcasp1_fsx.pr2_mdio_data */
+ {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
+ {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
+ {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */
+ {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
+ {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr8.pr2_mii0_txen */
+ {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr9.pr2_mii0_txd3 */
+ {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr10.pr2_mii0_txd2 */
+ {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr11.pr2_mii0_txd1 */
+ {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr12.pr2_mii0_txd0 */
+ {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
+ {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */
+ {MCASP1_AXR15, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
+ {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
+ {MCASP2_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP2_AXR2, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
+ {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr3.pr2_mii0_rxlink */
+ {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */
+ {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
+ {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
+ {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */
+ {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
+ {MCASP3_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.pr2_mii0_col */
+ {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */
+ {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr1.pr2_mii1_rxlink */
+ {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */
+ {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
+ {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
+ {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
+ {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M14 | PIN_INPUT)}, /* mmc1_sdwp.gpio6_28 */
+ {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
+ {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
+ {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
+ {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
+ {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
+ {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
+ {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
+ {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
+ {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
+ {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
+ {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
+ {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
+ {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
+ {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
+ {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
+ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */
+ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
+ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
+ {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
+ {SPI2_D1, (M0 | PIN_OUTPUT)}, /* spi2_d1.spi2_d1 */
+ {SPI2_D0, (M0 | PIN_INPUT)}, /* spi2_d0.spi2_d0 */
+ {SPI2_CS0, (M0 | PIN_OUTPUT)}, /* spi2_cs0.spi2_cs0 */
+ {UART1_RXD, (M14 | PIN_OUTPUT)}, /* uart1_rxd.gpio7_22 */
+ {UART1_TXD, (M14 | PIN_OUTPUT)}, /* uart1_txd.gpio7_23 */
+ {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
+ {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
+ {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
+ {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
+ {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
+ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
+ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
+ {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */
+ {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
+ {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
+ {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
+ {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
+ {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
+ {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
+ {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
+ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
+ {GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a0.vin1b_d0 */
+ {GPMC_A1, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a1.vin1b_d1 */
+ {GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a2.vin1b_d2 */
+ {GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a3.vin1b_d3 */
+ {GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a4.vin1b_d4 */
+ {GPMC_A5, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a5.vin1b_d5 */
+ {GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a6.vin1b_d6 */
+ {GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a7.vin1b_d7 */
+ {GPMC_A8, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a8.vin1b_hsync1 */
+ {GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a9.vin1b_vsync1 */
+ {GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a10.vin1b_clk1 */
+ {GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a11.vin1b_de1 */
+ {GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a12.vin1b_fld1 */
{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
{GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
{GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN) | MANUAL_MODE}, /* gpmc_a17.qspi1_d1 */
{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
@@ -294,37 +531,33 @@
{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
- {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
- {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
- {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
- {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
- {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */
- {VIN1A_D13, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d13.gpio3_17 */
- {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */
- {VIN1A_D15, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d15.gpio3_19 */
- {VIN1A_D17, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d17.gpio3_21 */
- {VIN1A_D18, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
- {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
- {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
- {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
- {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
- {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
+ {GPMC_CS3, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.gpio2_21 */
+ {GPMC_CLK, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_clk.gpio2_22 */
+ {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
+ {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
+ {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
+ {GPMC_BEN0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.gpio2_26 */
+ {GPMC_BEN1, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_ben1.gpio2_27 */
+ {GPMC_WAIT0, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
+ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
+ {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
{VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_vsync0.gpio4_0 */
{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
- {VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.ecap1 */
- {VIN2A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.gpio4_4 */
- {VIN2A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.gpio4_5 */
- {VIN2A_D5, (M13 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.pr1_pru1_gpo2 */
+ {VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.eCAP1_in_PWM1_out */
+ {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mi1_col */
+ {VIN2A_D4, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.pr1_mii1_txd1 */
+ {VIN2A_D5, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.pr1_mii1_txd0 */
{VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */
- {VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.pr1_mii_mii1_txen */
- {VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.pr1_mii_mii1_txd3 */
- {VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.pr1_mii_mii1_txd2 */
+ {VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.pr1_mii1_txen */
+ {VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.pr1_mii1_txd3 */
+ {VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.pr1_mii1_txd2 */
{VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
- {VIN2A_D11, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.pr1_mdio_data */
+ {VIN2A_D11, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d11.pr1_mdio_data */
{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
@@ -337,40 +570,40 @@
{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
- {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
- {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */
+ {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
{RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)}, /* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
- {UART3_RXD, (M11 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.pr1_mii0_rxdv */
- {UART3_TXD, (M11 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.rp1_mii_mr0_clk */
+ {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */
+ {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */
{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
@@ -378,20 +611,20 @@
{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M14 | PIN_OUTPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
- {GPIO6_15, (M0 | PIN_OUTPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
- {GPIO6_16, (M0 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6)_16 */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},/* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
+ {GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
+ {GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6_16 */
{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
- {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.i6_19 */
- {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.Driveroff */
{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
{MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */
{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */
@@ -399,11 +632,11 @@
{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
{MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */
{MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.pr2_mii0_txen */
{MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.pr2_mii0_txd3 */
{MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.pr2_mii0_txd2 */
@@ -414,6 +647,10 @@
{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
{MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.Driveroff */
+ {MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.Driveroff */
+ {MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.Driveroff */
+ {MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.Driveroff */
{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
{MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp2_axr3.pr2_mii0_rxlink */
{MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */
@@ -426,11 +663,20 @@
{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
{MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */
{MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */
- {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
+ {MCASP4_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.Driveroff */
+ {MCASP4_AXR1, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr1.spi3_cs0 */
{MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
- {MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},/* mcasp5_fsx.pr2_pru1_gpi2 */
- {MCASP5_AXR0, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.pr2_pru1_gpo3 */
- {MCASP5_AXR1, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr1.pr2_pru1_gpo4 */
+ {MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
+ {MCASP5_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.Driveroff */
+ {MCASP5_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr1.Driveroff */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M0 | PIN_OUTPUT)}, /* mmc1_sdwp.mmc1_sdwp */
{GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
{GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
{MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
@@ -446,28 +692,29 @@
{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
- {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs0.gpio7_10 */
{SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs1.gpio7_11 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
- {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
- {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
- {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
- {UART1_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_rxd.gpio7_22 */
- {UART1_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio7_23 */
- {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
- {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
- {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
+ {SPI2_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.spi2_sclk */
+ {SPI2_D1, (M0 | PIN_INPUT_SLEW)}, /* spi2_d1.spi2_d1 */
+ {SPI2_D0, (M0 | PIN_INPUT_SLEW)}, /* spi2_d0.spi2_d0 */
+ {SPI2_CS0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
+ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
+ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
+ {UART1_RXD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
+ {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */
+ {UART1_RTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_rtsn.gpio7_25 */
+ {UART2_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_rxd.uart2_rxd */
+ {UART2_TXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_txd.uart2_txd */
+ {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.uart3_txd */
+ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP3, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M0 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_OUTPUT)}, /* rtc_porz.rtc_porz */
{TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
{TDO, (M0 | PIN_INPUT_PULLUP)}, /* tdo.tdo */
@@ -488,7 +735,7 @@
};
#ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
+const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
{0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
{0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
{0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
@@ -524,11 +771,11 @@
{0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
{0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
{0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x074C, 201, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 229, 120}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 141, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 495, 120}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 660, 120}, /* CFG_RGMII0_TXD3_OUT */
{0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
{0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
{0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */
@@ -543,52 +790,165 @@
{0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
};
+const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = {
+ {0x0114, 2519, 702}, /* CFG_GPMC_A0_IN */
+ {0x0120, 2435, 411}, /* CFG_GPMC_A10_IN */
+ {0x012C, 2379, 755}, /* CFG_GPMC_A11_IN */
+ {0x0198, 2384, 778}, /* CFG_GPMC_A1_IN */
+ {0x0204, 2499, 1127}, /* CFG_GPMC_A2_IN */
+ {0x0210, 2455, 1181}, /* CFG_GPMC_A3_IN */
+ {0x021C, 2486, 1039}, /* CFG_GPMC_A4_IN */
+ {0x0228, 2456, 938}, /* CFG_GPMC_A5_IN */
+ {0x0234, 2463, 573}, /* CFG_GPMC_A6_IN */
+ {0x0240, 2608, 783}, /* CFG_GPMC_A7_IN */
+ {0x024C, 2430, 656}, /* CFG_GPMC_A8_IN */
+ {0x0258, 2465, 850}, /* CFG_GPMC_A9_IN */
+ {0x0264, 2316, 301}, /* CFG_GPMC_AD0_IN */
+ {0x0270, 2324, 406}, /* CFG_GPMC_AD10_IN */
+ {0x027C, 2278, 352}, /* CFG_GPMC_AD11_IN */
+ {0x0288, 2297, 160}, /* CFG_GPMC_AD12_IN */
+ {0x0294, 2278, 108}, /* CFG_GPMC_AD13_IN */
+ {0x02A0, 2035, 0}, /* CFG_GPMC_AD14_IN */
+ {0x02AC, 2279, 378}, /* CFG_GPMC_AD15_IN */
+ {0x02B8, 2440, 70}, /* CFG_GPMC_AD1_IN */
+ {0x02C4, 2404, 446}, /* CFG_GPMC_AD2_IN */
+ {0x02D0, 2343, 212}, /* CFG_GPMC_AD3_IN */
+ {0x02DC, 2355, 322}, /* CFG_GPMC_AD4_IN */
+ {0x02E8, 2337, 192}, /* CFG_GPMC_AD5_IN */
+ {0x02F4, 2270, 314}, /* CFG_GPMC_AD6_IN */
+ {0x0300, 2339, 259}, /* CFG_GPMC_AD7_IN */
+ {0x030C, 2308, 577}, /* CFG_GPMC_AD8_IN */
+ {0x0318, 2334, 166}, /* CFG_GPMC_AD9_IN */
+ {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */
+ {0x0678, 0, 386}, /* CFG_MMC3_CLK_IN */
+ {0x0680, 605, 0}, /* CFG_MMC3_CLK_OUT */
+ {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */
+ {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */
+ {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */
+ {0x0690, 171, 0}, /* CFG_MMC3_DAT0_IN */
+ {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */
+ {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */
+ {0x069C, 221, 0}, /* CFG_MMC3_DAT1_IN */
+ {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */
+ {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */
+ {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */
+ {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */
+ {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */
+ {0x06B4, 474, 0}, /* CFG_MMC3_DAT3_IN */
+ {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
+ {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
+ {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 219, 101}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 92, 58}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 135, 100}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 154, 101}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 78, 27}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 411, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 0, 382}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 320, 750}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */
+};
+
const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
- {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
- {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
- {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
- {0x0138, 2605, 45}, /* CFG_GPMC_A12_IN */
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */
- {0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */
- {0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */
- {0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */
- {0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */
- {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
- {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
- {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
- {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
- {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
- {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
- {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
- {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */
- {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
- {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 201, 60}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 229, 120}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 141, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 495, 120}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 660, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0114, 1861, 901}, /* CFG_GPMC_A0_IN */
+ {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
+ {0x012C, 1783, 1178}, /* CFG_GPMC_A11_IN */
+ {0x0138, 1903, 853}, /* CFG_GPMC_A12_IN */
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */
+ {0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0198, 1652, 891}, /* CFG_GPMC_A1_IN */
+ {0x0204, 1888, 1212}, /* CFG_GPMC_A2_IN */
+ {0x0210, 1839, 1274}, /* CFG_GPMC_A3_IN */
+ {0x021C, 1868, 1113}, /* CFG_GPMC_A4_IN */
+ {0x0228, 1757, 1079}, /* CFG_GPMC_A5_IN */
+ {0x0234, 1800, 670}, /* CFG_GPMC_A6_IN */
+ {0x0240, 1967, 898}, /* CFG_GPMC_A7_IN */
+ {0x024C, 1731, 959}, /* CFG_GPMC_A8_IN */
+ {0x0258, 1766, 1150}, /* CFG_GPMC_A9_IN */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x0590, 1000, 4200}, /* CFG_MCASP5_ACLKX_OUT */
+ {0x05AC, 800, 3800}, /* CFG_MCASP5_FSX_IN */
+ {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 90, 70}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 70, 70}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 180, 70}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 35, 70}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 180, 70}, /* CFG_RGMII0_TXD3_OUT */
{0x0A70, 65, 70}, /* CFG_VIN2A_D12_OUT */
{0x0A7C, 125, 70}, /* CFG_VIN2A_D13_OUT */
{0x0A88, 0, 70}, /* CFG_VIN2A_D14_OUT */
{0x0A94, 0, 70}, /* CFG_VIN2A_D15_OUT */
{0x0AA0, 65, 70}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
{0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
{0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
{0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
{0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
{0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
{0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
+ {0x0B30, 0, 0}, /* CFG_VIN2A_D5_OUT */
};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2062, 2277}, /* CFG_GPMC_A14_IN */
+ {0x015C, 1960, 2289}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2058, 2386}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2062, 2350}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
+ {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
+ {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
+};
+
#endif
#endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 0ed4f52..cfdab3e 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -29,7 +29,7 @@
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <asm/omap_musb.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index adf73ab..4980a04 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -1,5 +1,41 @@
+config SPL_ENV_SUPPORT
+ default y
+
config TI_I2C_BOARD_DETECT
bool "Support for Board detection for TI platforms"
help
Support for detection board information on Texas Instrument's
Evaluation Boards which have I2C based EEPROM detection
+
+config SPL_EXT_SUPPORT
+ default y
+
+config SPL_FAT_SUPPORT
+ default y
+
+config SPL_GPIO_SUPPORT
+ default y
+
+config SPL_I2C_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ default y
+
+config SPL_NAND_SUPPORT
+ default y
+
+config SPL_POWER_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index e0ae1a5..a5dba94 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -123,14 +123,17 @@
struct ti_common_eeprom *ep;
ep = TI_EEPROM_DATA;
+#ifndef CONFIG_SPL_BUILD
if (ep->header == TI_EEPROM_HEADER_MAGIC)
- goto already_read;
+ return 0; /* EEPROM has already been read */
+#endif
/* Initialize with a known bad marker for i2c fails.. */
ep->header = TI_DEAD_EEPROM_MAGIC;
ep->name[0] = 0x0;
ep->version[0] = 0x0;
ep->serial[0] = 0x0;
+ ep->config[0] = 0x0;
rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC,
sizeof(am_ep), (uint8_t *)&am_ep);
@@ -156,7 +159,6 @@
memcpy(ep->mac_addr, am_ep.mac_addr,
TI_EEPROM_HDR_NO_OF_MAC_ADDR * TI_EEPROM_HDR_ETH_ALEN);
-already_read:
return 0;
}
@@ -167,14 +169,17 @@
struct ti_common_eeprom *ep;
ep = TI_EEPROM_DATA;
+#ifndef CONFIG_SPL_BUILD
if (ep->header == DRA7_EEPROM_HEADER_MAGIC)
- goto already_read;
+ return 0; /* EEPROM has already been read */
+#endif
/* Initialize with a known bad marker for i2c fails.. */
- ep->header = 0xADEAD12C;
+ ep->header = TI_DEAD_EEPROM_MAGIC;
ep->name[0] = 0x0;
ep->version[0] = 0x0;
ep->serial[0] = 0x0;
+ ep->config[0] = 0x0;
ep->emif1_size = 0;
ep->emif2_size = 0;
@@ -200,7 +205,6 @@
strlcpy(ep->config, dra7_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1);
ti_eeprom_string_cleanup(ep->config);
-already_read:
return 0;
}
@@ -229,9 +233,7 @@
{
struct ti_common_eeprom *ep = TI_EEPROM_DATA;
- if (ep->header == TI_DEAD_EEPROM_MAGIC)
- return NULL;
-
+ /* if ep->header == TI_DEAD_EEPROM_MAGIC, this is empty already */
return ep->version;
}
@@ -239,9 +241,7 @@
{
struct ti_common_eeprom *ep = TI_EEPROM_DATA;
- if (ep->header == TI_DEAD_EEPROM_MAGIC)
- return NULL;
-
+ /* if ep->header == TI_DEAD_EEPROM_MAGIC, this is empty already */
return ep->config;
}
@@ -249,9 +249,7 @@
{
struct ti_common_eeprom *ep = TI_EEPROM_DATA;
- if (ep->header == TI_DEAD_EEPROM_MAGIC)
- return NULL;
-
+ /* if ep->header == TI_DEAD_EEPROM_MAGIC, this is empty already */
return ep->name;
}
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index eb17f6f..343fcb4 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -133,7 +133,7 @@
*
* NOTE: revision information is often messed up (hence the str len match) :(
*
- * Return: false if board information does not match OR eeprom was'nt read.
+ * Return: false if board information does not match OR eeprom wasn't read.
* true otherwise
*/
bool board_ti_rev_is(char *rev_tag, int cmp_len);
@@ -141,7 +141,7 @@
/**
* board_ti_get_rev() - Get board revision for TI EVMs
*
- * Return: NULL if eeprom was'nt read.
+ * Return: Empty string if eeprom wasn't read.
* Board revision otherwise
*/
char *board_ti_get_rev(void);
@@ -149,7 +149,7 @@
/**
* board_ti_get_config() - Get board config for TI EVMs
*
- * Return: NULL if eeprom was'nt read.
+ * Return: Empty string if eeprom wasn't read.
* Board config otherwise
*/
char *board_ti_get_config(void);
@@ -157,7 +157,7 @@
/**
* board_ti_get_name() - Get board name for TI EVMs
*
- * Return: NULL if eeprom was'nt read.
+ * Return: Empty string if eeprom wasn't read.
* Board name otherwise
*/
char *board_ti_get_name(void);
@@ -174,14 +174,14 @@
/**
* board_ti_get_emif1_size() - Get size of the DDR on emif1 for TI EVMs
*
- * Return: NULL if eeprom was'nt read or emif1_size is not available.
+ * Return: NULL if eeprom wasn't read or emif1_size is not available.
*/
u64 board_ti_get_emif1_size(void);
/**
* board_ti_get_emif2_size() - Get size of the DDR on emif2 for TI EVMs
*
- * Return: NULL if eeprom was'nt read or emif2_size is not available.
+ * Return: NULL if eeprom wasn't read or emif2_size is not available.
*/
u64 board_ti_get_emif2_size(void);
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 99e8254..bd1c809 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -36,10 +36,11 @@
#define board_is_dra74x_evm() board_ti_is("5777xCPU")
#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
-#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
- (strncmp("H", board_ti_get_rev(), 1) <= 0)
-#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() && \
- (strncmp("C", board_ti_get_rev(), 1) <= 0)
+#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
+#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
+ (strncmp("H", board_ti_get_rev(), 1) <= 0))
+#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
+ (strncmp("C", board_ti_get_rev(), 1) <= 0))
#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
board_ti_get_emif2_size()
@@ -308,35 +309,47 @@
}
struct vcores_data dra752_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
@@ -344,15 +357,15 @@
};
struct vcores_data dra722_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
@@ -361,28 +374,117 @@
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+struct vcores_data dra718_volts = {
+ /*
+ * In the case of dra71x GPU MPU and CORE
+ * are all powered up by BUCK0 of LP873X PMIC
+ */
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = LP873X_REG_ADDR_BUCK0,
+ .mpu.pmic = &lp8733,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = LP873X_REG_ADDR_BUCK0,
+ .core.pmic = &lp8733,
+
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = LP873X_REG_ADDR_BUCK0,
+ .gpu.pmic = &lp8733,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ /*
+ * The DSPEVE and IVA rails are grouped on DRA71x-evm
+ * and are powered by BUCK1 of LP873X PMIC
+ */
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = LP873X_REG_ADDR_BUCK1,
+ .eve.pmic = &lp8733,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = LP873X_REG_ADDR_BUCK1,
+ .iva.pmic = &lp8733,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+int get_voltrail_opp(int rail_offset)
+{
+ int opp;
+
+ /*
+ * DRA71x supports only OPP_NOM.
+ */
+ if (board_is_dra71x_evm())
+ return OPP_NOM;
+
+ switch (rail_offset) {
+ case VOLT_MPU:
+ opp = DRA7_MPU_OPP;
+ break;
+ case VOLT_CORE:
+ opp = DRA7_CORE_OPP;
+ break;
+ case VOLT_GPU:
+ opp = DRA7_GPU_OPP;
+ break;
+ case VOLT_EVE:
+ opp = DRA7_DSPEVE_OPP;
+ break;
+ case VOLT_IVA:
+ opp = DRA7_IVA_OPP;
+ break;
+ default:
+ opp = OPP_NOM;
+ }
+
+ return opp;
+}
+
/**
* @brief board_init
*
@@ -418,6 +520,8 @@
if (is_dra72x()) {
if (board_is_dra72x_revc_or_later())
name = "dra72x-revc";
+ else if (board_is_dra71x_evm())
+ name = "dra71x";
else
name = "dra72x";
} else {
@@ -426,6 +530,13 @@
set_board_info_env(name);
+ /*
+ * Default FIT boot on HS devices. Non FIT images are not allowed
+ * on HS devices.
+ */
+ if (get_device_type() == HS_DEVICE)
+ setenv("boot_fit", "1");
+
omap_die_id_serial();
#endif
return 0;
@@ -458,6 +569,8 @@
bname = "DRA74x EVM";
} else if (board_is_dra72x_evm()) {
bname = "DRA72x EVM";
+ } else if (board_is_dra71x_evm()) {
+ bname = "DRA71x EVM";
} else {
/* If EEPROM is not populated */
if (is_dra72x())
@@ -478,6 +591,8 @@
*omap_vcores = &dra752_volts;
} else if (board_is_dra72x_evm()) {
*omap_vcores = &dra722_volts;
+ } else if (board_is_dra71x_evm()) {
+ *omap_vcores = &dra718_volts;
} else {
/* If EEPROM is not populated */
if (is_dra72x())
@@ -506,7 +621,12 @@
case DRA722_ES2_0:
pads = dra72x_core_padconf_array_common;
npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
- if (board_is_dra72x_revc_or_later()) {
+ if (board_is_dra71x_evm()) {
+ pads = dra71x_core_padconf_array;
+ npads = ARRAY_SIZE(dra71x_core_padconf_array);
+ iodelay = dra71_iodelay_cfg_array;
+ niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
+ } else if (board_is_dra72x_revc_or_later()) {
delta_pads = dra72x_rgmii_padconf_array_revc;
delta_npads =
ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
@@ -828,12 +948,21 @@
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
- if (is_dra72x() && !strcmp(name, "dra72-evm"))
+ if (is_dra72x()) {
+ if (board_is_dra71x_evm()) {
+ if (!strcmp(name, "dra71-evm"))
+ return 0;
+ }else if(board_is_dra72x_revc_or_later()) {
+ if (!strcmp(name, "dra72-evm-revc"))
+ return 0;
+ } else if (!strcmp(name, "dra72-evm")) {
+ return 0;
+ }
+ } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
return 0;
- else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
- return 0;
- else
- return -1;
+ }
+
+ return -1;
}
#endif
@@ -842,4 +971,11 @@
{
secure_boot_verify_image(p_image, p_size);
}
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+ secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
#endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 34a05dd..2cc4be3 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -193,33 +193,184 @@
const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
{VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
- {RGMII0_TXC, (M0 | PIN_OUTPUT)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {VIN2A_D12, (M3 | PIN_OUTPUT)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d23.rgmii1_rxd0 */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
};
+const struct pad_conf_entry dra71x_core_padconf_array[] = {
+ {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
+ {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
+ {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
+ {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
+ {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
+ {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
+ {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
+ {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
+ {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
+ {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
+ {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
+ {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
+ {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
+ {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
+ {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
+ {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
+ {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
+ {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
+ {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
+ {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
+ {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
+ {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
+ {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
+ {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
+ {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
+ {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
+ {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
+ {GPMC_A11, (M14 | PIN_INPUT)}, /* gpmc_a11.gpio2_1 */
+ {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+ {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
+ {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */
+ {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */
+ {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */
+ {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */
+ {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */
+ {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */
+ {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */
+ {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */
+ {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */
+ {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */
+ {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */
+ {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */
+ {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */
+ {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
+ {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
+ {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
+ {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
+ {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
+ {MCASP1_ACLKX, (M14 | PIN_INPUT)}, /* mcasp1_aclkx.gpio7_31 */
+ {MCASP1_FSX, (M14 | 0x000d0000)}, /* mcasp1_fsx.gpio7_30 */
+ {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
+ {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
+ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
+ {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
+ {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
+ {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
+ {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
+ {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
+ {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
+ {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
+ {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
+ {SPI1_CS1, (M14 | PIN_INPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
+ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
+ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
+ {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
+ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
+ {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
+ {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
+ {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
+ {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */
+ {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
+ {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
+ {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
+ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
+ {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
+};
+
const struct pad_conf_entry early_padconf[] = {
#if (CONFIG_CONS_INDEX == 1)
{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
@@ -277,9 +428,83 @@
{0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
{0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
{0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
+ {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
+ {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
};
+const struct iodelay_cfg_entry dra71_iodelay_cfg_array[] = {
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
+ {0x0A44, 1936, 0}, /* CFG_VIN2A_D0_IN */
+ {0x0A50, 2031, 0}, /* CFG_VIN2A_D10_IN */
+ {0x0A5C, 1702, 0}, /* CFG_VIN2A_D11_IN */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
+ {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
+ {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
+ {0x0B04, 1736, 0}, /* CFG_VIN2A_D2_IN */
+ {0x0B10, 1943, 0}, /* CFG_VIN2A_D3_IN */
+ {0x0B1C, 1601, 0}, /* CFG_VIN2A_D4_IN */
+ {0x0B28, 2052, 0}, /* CFG_VIN2A_D5_IN */
+ {0x0B34, 1571, 0}, /* CFG_VIN2A_D6_IN */
+ {0x0B40, 1855, 0}, /* CFG_VIN2A_D7_IN */
+ {0x0B4C, 1224, 618}, /* CFG_VIN2A_D8_IN */
+ {0x0B58, 1373, 509}, /* CFG_VIN2A_D9_IN */
+ {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */
+ {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */
+};
#endif
const struct pad_conf_entry dra74x_core_padconf_array[] = {
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 7ef2d2b..879f8b5 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -6,12 +6,12 @@
#
obj-y += board.o
-obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
-obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
-obj-$(CONFIG_K2E_EVM) += board_k2e.o
-obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
-obj-$(CONFIG_K2L_EVM) += board_k2l.o
-obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
-obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o
-obj-$(CONFIG_K2G_EVM) += board_k2g.o
-obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o
+obj-$(CONFIG_TARGET_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_TARGET_K2HK_EVM) += ddr3_k2hk.o
+obj-$(CONFIG_TARGET_K2E_EVM) += board_k2e.o
+obj-$(CONFIG_TARGET_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_TARGET_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_k2l.o
+obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_cfg.o
+obj-$(CONFIG_TARGET_K2G_EVM) += board_k2g.o
+obj-$(CONFIG_TARGET_K2G_EVM) += ddr3_k2g.o
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 1de7df0..03254e1 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -50,6 +50,9 @@
if (ddr3_size)
ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+ else
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, gd->ram_size >> 30);
+
return 0;
}
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 8f16845..40edbaa 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -66,7 +66,7 @@
static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
-static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
+static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16};
struct pll_init_data *get_pll_init_data(int pll)
{
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 50da410..b5d5ba9 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -245,10 +245,7 @@
int ehci_hcd_stop(void)
{
- int ret;
-
- ret = omap_ehci_hcd_stop();
- return ret;
+ return omap_ehci_hcd_stop();
}
void usb_hub_reset_devices(int port)
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index 965252f..f785dbe 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -157,7 +157,7 @@
#ifdef CONFIG_SPL_OS_BOOT
/*
- * Do board specific preperation before SPL
+ * Do board specific preparation before SPL
* Linux boot
*/
void spl_board_prepare_for_linux(void)
diff --git a/board/topic/zynq/MAINTAINERS b/board/topic/zynq/MAINTAINERS
new file mode 100644
index 0000000..d795b30
--- /dev/null
+++ b/board/topic/zynq/MAINTAINERS
@@ -0,0 +1,6 @@
+TOPIC BOARD
+M: Mike Looijmans <mike.looijmans@topic.nl>
+S: Maintained
+F: board/topic/zynq/
+F: include/configs/topic*.h
+F: configs/topic_*_defconfig
diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile
new file mode 100644
index 0000000..eaf59cd
--- /dev/null
+++ b/board/topic/zynq/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
+
+# Remove quotes
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o ps7_init_common.o
diff --git a/board/topic/zynq/board.c b/board/topic/zynq/board.c
new file mode 100644
index 0000000..a95c9d1
--- /dev/null
+++ b/board/topic/zynq/board.c
@@ -0,0 +1 @@
+#include "../../xilinx/zynq/board.c"
diff --git a/board/topic/zynq/ps7_init_common.c b/board/topic/zynq/ps7_init_common.c
new file mode 100644
index 0000000..b1d45c2
--- /dev/null
+++ b/board/topic/zynq/ps7_init_common.c
@@ -0,0 +1,117 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "ps7_init_gpl.h"
+#include <asm/io.h>
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+#define APU_FREQ 666666666
+
+#define PS7_MASK_POLL_TIME 100000000
+
+/* IO accessors. No memory barriers desired. */
+static inline void iowrite(unsigned long val, unsigned long addr)
+{
+ __raw_writel(val, addr);
+}
+
+static inline unsigned long ioread(unsigned long addr)
+{
+ return __raw_readl(addr);
+}
+
+/* start timer */
+static void perf_start_clock(void)
+{
+ iowrite((1 << 0) | /* Timer Enable */
+ (1 << 3) | /* Auto-increment */
+ (0 << 8), /* Pre-scale */
+ SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* Compute mask for given delay in miliseconds*/
+static int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ return (APU_FREQ / (2 * 1000)) * delay;
+}
+
+/* stop timer */
+static void perf_disable_clock(void)
+{
+ iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* stop timer and reset timer count regs */
+static void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
+ iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
+}
+
+static void perf_reset_and_start_timer(void)
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
+
+int ps7_config(unsigned long *ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+ unsigned long opcode;
+ unsigned long addr;
+ unsigned long val;
+ unsigned long mask;
+ unsigned int numargs;
+ int i;
+ int delay;
+
+ for (;;) {
+ opcode = ptr[0];
+ if (opcode == OPCODE_EXIT)
+ return PS7_INIT_SUCCESS;
+ addr = (opcode & OPCODE_ADDRESS_MASK);
+
+ switch (opcode & ~OPCODE_ADDRESS_MASK) {
+ case OPCODE_MASKWRITE:
+ numargs = 3;
+ mask = ptr[1];
+ val = ptr[2];
+ iowrite((ioread(addr) & ~mask) | (val & mask), addr);
+ break;
+
+ case OPCODE_MASKPOLL:
+ numargs = 2;
+ mask = ptr[1];
+ i = 0;
+ while (!(ioread(addr) & mask)) {
+ if (i == PS7_MASK_POLL_TIME)
+ return PS7_INIT_TIMEOUT;
+ i++;
+ }
+ break;
+
+ case OPCODE_MASKDELAY:
+ numargs = 2;
+ mask = ptr[1];
+ delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while (ioread(addr) < delay)
+ ;
+ break;
+
+ default:
+ return PS7_INIT_CORRUPT;
+ }
+
+ ptr += numargs;
+ }
+}
diff --git a/board/topic/zynq/ps7_init_gpl.h b/board/topic/zynq/ps7_init_gpl.h
new file mode 100644
index 0000000..ef719ac
--- /dev/null
+++ b/board/topic/zynq/ps7_init_gpl.h
@@ -0,0 +1,34 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define OPCODE_EXIT 0U
+#define OPCODE_MASKWRITE 0U
+#define OPCODE_MASKPOLL 1U
+#define OPCODE_MASKDELAY 2U
+#define OPCODE_ADDRESS_MASK (~3U)
+
+/* Sentinel */
+#define EMIT_EXIT() OPCODE_EXIT
+/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
+#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
+#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask
+#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
+
+/* Returns codes of ps7_init* */
+#define PS7_INIT_SUCCESS (0)
+#define PS7_INIT_CORRUPT (1)
+#define PS7_INIT_TIMEOUT (2)
+#define PS7_POLL_FAILED_DDR_INIT (3)
+#define PS7_POLL_FAILED_DMA (4)
+#define PS7_POLL_FAILED_PLL (5)
+
+/* Called by spl.c */
+int ps7_init(void);
+int ps7_post_config(void);
+
+/* Defined in ps7_init_common.c */
+int ps7_config(unsigned long *ps7_config_init);
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
new file mode 100644
index 0000000..b195d7a
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
@@ -0,0 +1,227 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../ps7_init_gpl.h"
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
+ EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
+ EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_regs.txt b/board/topic/zynq/zynq-topic-miami/ps7_regs.txt
new file mode 100644
index 0000000..2ad9da6
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miami/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
+0xf8000700 0x1210 // MIO configuration
+0xf8000704 0x202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x210
+0xf8000720 0x202
+0xf8000724 0x1210
+0xf8000728 0x1210
+0xf800072c 0x1210
+0xf8000730 0x1210
+0xf8000734 0x1210
+0xf8000738 0x1211
+0xf800073c 0x1200
+0xf8000740 0x1210
+0xf8000744 0x1210
+0xf8000748 0x1210
+0xf800074c 0x1210
+0xf8000750 0x1210
+0xf8000754 0x1210
+0xf8000758 0x1210
+0xf800075c 0x1210
+0xf8000760 0x1201
+0xf8000764 0x200
+0xf8000768 0x12e1
+0xf800076c 0x2e0
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1261
+0xf80007bc 0x1260
+0xf80007c0 0x1261
+0xf80007c4 0x1261
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1240
+0xf80007d4 0x1240
+0xf8000830 0x180037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz)
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0x82FF04EB // LQSPI_CFG - QIOREAD mode, Numonyx/Micron
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
new file mode 100644
index 0000000..5a92336
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
@@ -0,0 +1,233 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../ps7_init_gpl.h"
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
+ EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
+ EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_3_0);
+}
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt b/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt
new file mode 100644
index 0000000..7b102de
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
+0xf8000700 0x1202 // MIO configuration
+0xf8000704 0x1202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x200
+0xf8000720 0x202
+0xf8000724 0x202
+0xf8000728 0x202
+0xf800072c 0x202
+0xf8000730 0x202
+0xf8000734 0x202
+0xf8000738 0x12e1
+0xf800073c 0x12e0
+0xf8000740 0x1202
+0xf8000744 0x1202
+0xf8000748 0x1202
+0xf800074c 0x1202
+0xf8000750 0x1202
+0xf8000754 0x1202
+0xf8000758 0x1203
+0xf800075c 0x1203
+0xf8000760 0x1203
+0xf8000764 0x203
+0xf8000768 0x1203
+0xf800076c 0x203
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1200
+0xf80007bc 0x1201
+0xf80007c0 0x1240
+0xf80007c4 0x1240
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1280
+0xf80007d4 0x1280
+0xf8000830 0x2f0037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash
diff --git a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
new file mode 100644
index 0000000..5cfda26
--- /dev/null
+++ b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016 Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7954
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB328F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09555050
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x432A0338
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03260324
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43340344
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x031E027C
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37
+
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4336453F
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
new file mode 100644
index 0000000..3707910
--- /dev/null
+++ b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016 Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E78f5
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xff328f64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x02888032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03300338
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03240324
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x03440350
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x032C0308
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46
+
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x403E463E
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig
new file mode 100644
index 0000000..14f8c10
--- /dev/null
+++ b/board/toradex/apalis_imx6/Kconfig
@@ -0,0 +1,55 @@
+if TARGET_APALIS_IMX6
+
+config SYS_BOARD
+ default "apalis_imx6"
+
+config SYS_CONFIG_NAME
+ default "apalis_imx6"
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_VENDOR
+ default "toradex"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+config TDX_CMD_IMX_MFGR
+ bool "Enable factory testing commands for Toradex iMX 6 modules"
+ help
+ This adds the commands
+ pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
+ If executed on already fused modules it doesn't change any fuse setting.
+ default y
+
+config TDX_APALIS_IMX6_V1_0
+ bool "Apalis iMX6 V1.0 HW"
+ help
+ Apalis iMX6 V1.0 HW has a different pinout for the UART.
+ The UARTs must be used in DCE mode, RTS/CTS are swapped and
+ thus unusable on standard carrier boards.
+ This option configures DCE mode unconditionally. Whithout this
+ option the config block stating V1.0 HW selects DCE mode,
+ otherwise the UARTs are configuered in DTE mode.
+ default n
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
new file mode 100644
index 0000000..2c70ab4
--- /dev/null
+++ b/board/toradex/apalis_imx6/MAINTAINERS
@@ -0,0 +1,9 @@
+Apalis iMX6
+M: Max Krummenacher <max.krummenacher@toradex.com>
+W: http://developer.toradex.com/software/linux/linux-software
+S: Maintained
+F: board/toradex/apalis_imx6/
+F: include/configs/apalis_imx6.h
+F: configs/apalis_imx6_defconfig
+F: configs/apalis_imx6_nospl_com_defconfig
+F: configs/apalis_imx6_nospl_it_defconfig
diff --git a/board/toradex/apalis_imx6/Makefile b/board/toradex/apalis_imx6/Makefile
new file mode 100644
index 0000000..128f179
--- /dev/null
+++ b/board/toradex/apalis_imx6/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2012-2014 Toradex, Inc.
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := apalis_imx6.o do_fuse.o
+obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
new file mode 100644
index 0000000..09bebeb
--- /dev/null
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -0,0 +1,1292 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ * Copyright (C) 2014-2016, Toradex AG
+ * copied from nitrogen6x
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/platdata.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <imx_thermal.h>
+#include <linux/errno.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include "../common/tdx-cfg-block.h"
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+#include "pf0100.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_SLOW)
+
+#define NO_PULLUP ( \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+ /* use the DDR controllers configured size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ (ulong)imx_ddr_size());
+
+ return 0;
+}
+
+/* Apalis UART1 */
+iomux_v3_cfg_t const uart1_pads_dce[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+iomux_v3_cfg_t const uart1_pads_dte[] = {
+ MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* Apalis I2C1 */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+/* Apalis local, PMIC, SGTL5000, STMPE811 */
+struct i2c_pads_info i2c_pad_info_loc = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+/* Apalis I2C3 / CAM */
+struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+/* Apalis I2C2 / DDC */
+struct i2c_pads_info i2c_pad_info_ddc = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+ .gp = IMX_GPIO_NR(3, 16)
+ }
+};
+
+/* Apalis MMC1 */
+iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+# define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
+};
+
+/* Apalis SD1 */
+iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+# define GPIO_SD_CD IMX_GPIO_NR(6, 14)
+};
+
+/* eMMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* tx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+ return 0;
+}
+
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* KSZ9031 PHY Reset */
+ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+# define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+static int reset_enet_phy(struct mii_dev *bus)
+{
+ /* Reset KSZ9031 PHY */
+ gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
+ mdelay(10);
+ gpio_set_value(GPIO_ENET_PHY_RESET, 1);
+
+ return 0;
+}
+
+/* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
+iomux_v3_cfg_t const gpio_pads[] = {
+ /* Apalis GPIO1 - GPIO8 */
+ MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN),
+ MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_gpio(void)
+{
+ imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+iomux_v3_cfg_t const usb_pads[] = {
+ /* USBH_EN */
+ MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+# define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
+ /* USB_VBUS_DET */
+ MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+# define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
+ /* USBO1_ID */
+ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* USBO1_EN */
+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+# define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
+};
+
+/*
+ * UARTs are used in DTE mode, switch the mode on all UARTs before
+ * any pinmuxing connects a (DCE) output to a transceiver output.
+ */
+#define UFCR 0x90 /* FIFO Control Register */
+#define UFCR_DCEDTE (1<<6) /* DCE=0 */
+
+static void setup_dtemode_uart(void)
+{
+ setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
+ setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
+ setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
+ setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
+}
+static void setup_dcemode_uart(void)
+{
+ clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
+ clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
+ clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
+ clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
+}
+
+static void setup_iomux_dte_uart(void)
+{
+ setup_dtemode_uart();
+ imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
+ ARRAY_SIZE(uart1_pads_dte));
+}
+
+static void setup_iomux_dce_uart(void)
+{
+ setup_dcemode_uart();
+ imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
+ ARRAY_SIZE(uart1_pads_dce));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ /* control OTG power */
+ gpio_direction_output(GPIO_USBO_EN, on);
+ mdelay(100);
+ break;
+ case 1:
+ /* Control MXM USBH */
+ gpio_direction_output(GPIO_USBH_EN, on);
+ mdelay(2);
+ /* Control onboard USB Hub VBUS */
+ gpio_direction_output(GPIO_USB_VBUS_DET, on);
+ mdelay(100);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+/* use the following sequence: eMMC, MMC, SD */
+struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC1_BASE_ADDR},
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = true; /* default: assume inserted */
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ gpio_direction_input(GPIO_MMC_CD);
+ ret = !gpio_get_value(GPIO_MMC_CD);
+ break;
+ case USDHC2_BASE_ADDR:
+ gpio_direction_input(GPIO_SD_CD);
+ ret = !gpio_get_value(GPIO_SD_CD);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+ s32 status = 0;
+ u32 index = 0;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ usdhc_cfg[0].max_bus_width = 8;
+ usdhc_cfg[1].max_bus_width = 8;
+ usdhc_cfg[2].max_bus_width = 4;
+
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
+
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ }
+
+ return status;
+#else
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(&psrc->sbmr1) >> 11;
+ /*
+ * Upon reading BOOT_CFG register the following map is done:
+ * Bit 11 and 12 of BOOT_CFG register can determine the current
+ * mmc port
+ * 0x1 SD1
+ * 0x2 SD2
+ * 0x3 SD4
+ */
+
+ switch (reg & 0x3) {
+ case 0x0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ default:
+ puts("MMC boot device not available");
+ }
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+ bus->reset = reset_enet_phy;
+ /* scan PHY 4,5,6,7 */
+ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+ if (!phydev) {
+ free(bus);
+ puts("no PHY found\n");
+ return 0;
+ }
+ printf("using PHY at %d\n", phydev->addr);
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ free(phydev);
+ free(bus);
+ }
+#endif
+ return 0;
+}
+
+static iomux_v3_cfg_t const pwr_intb_pads[] = {
+ /*
+ * the bootrom sets the iomux to vselect, potentially connecting
+ * two outputs. Set this back to GPIO
+ */
+ MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+ /* Backlight on RGB connector: J15 */
+ MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
+ /* additional CPU pin on BKL_PWM, keep in tristate */
+ MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
+ /* Backlight PWM, used as GPIO in U-Boot */
+ MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
+ /* buffer output enable 0: buffer enabled */
+ MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
+#define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
+ /* PSAVE# integrated VDAC */
+ MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+ MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
+};
+
+static iomux_v3_cfg_t const vga_pads[] = {
+#ifdef FOR_DL_SOLO
+ /* DualLite/Solo doesn't have IPU2 */
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+#else
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02,
+ MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03,
+ MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15,
+#endif
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return (0 == i2c_set_bus_num(dev->bus)) &&
+ (0 == i2c_probe(dev->addr));
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+ u32 reg = readl(&iomux->gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+ writel(reg, &iomux->gpr[2]);
+ gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+ gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+ gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(
+ rgb_pads,
+ ARRAY_SIZE(rgb_pads));
+ gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+ gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+ gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
+}
+
+static int detect_default(struct display_info_t const *dev)
+{
+ (void) dev;
+ return 1;
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .di = 1,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_default,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "vga-rgb",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 33000,
+ .left_margin = 48,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .lower_margin = 11,
+ .hsync_len = 96,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .di = 1,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "wvga-rgb",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 25000,
+ .left_margin = 40,
+ .right_margin = 88,
+ .upper_margin = 33,
+ .lower_margin = 10,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "wsvga-lvds",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+ |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+ |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+
+ /* backlight unconditionally on for now */
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+ /* use 0 for EDT 7", use 1 for LG fullHD panel */
+ gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+ gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
+ gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+#endif /* defined(CONFIG_VIDEO_IPUV3) */
+
+int board_early_init_f(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
+ ARRAY_SIZE(pwr_intb_pads));
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+ setup_iomux_dte_uart();
+#else
+ setup_iomux_dce_uart();
+#endif
+
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+ (void) pmic_init();
+#endif
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
+ setup_iomux_gpio();
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if defined(CONFIG_REVISION_TAG) && \
+ defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+ char env_str[256];
+ u32 rev;
+
+ rev = get_board_rev();
+ snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
+ setenv("board_rev", env_str);
+
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+ if ((rev & 0xfff0) == 0x0100) {
+ char *fdt_env;
+
+ /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
+ setup_iomux_dce_uart();
+
+ /* if using the default device tree, use version for V1.0 HW */
+ fdt_env = getenv("fdt_file");
+ if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
+ setenv("fdt_file", FDT_FILE_V1_0);
+ printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
+#ifndef CONFIG_ENV_IS_NOWHERE
+ saveenv();
+#endif
+ }
+ }
+#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
+#endif /* CONFIG_REVISION_TAG */
+
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
+int ft_system_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+int checkboard(void)
+{
+ char it[] = " IT";
+ int minc, maxc;
+
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_AUTOMOTIVE:
+ case TEMP_INDUSTRIAL:
+ break;
+ case TEMP_EXTCOMMERCIAL:
+ default:
+ it[0] = 0;
+ };
+ printf("Model: Toradex Apalis iMX6 %s %s%s\n",
+ is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
+ (gd->ram_size == 0x80000000) ? "2GB" :
+ (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4-bit bus width */
+ {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+ {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+/* TODO, use external pmic, for now always ldo_enable */
+void ldo_mode_set(int ldo_bypass)
+{
+ return;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+#include "asm/arch/mx6q-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+static int mx6_com_dcd_table[] = {
+/* ddr-setup.cfg */
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC mirroring interleaved (row/bank/col)
+ */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+/* 1066mhz_4x128mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x00020036,
+MX6_MMDC_P0_MDCFG0, 0x555A7954,
+MX6_MMDC_P0_MDCFG1, 0xDB328F64,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x005A1023,
+MX6_MMDC_P0_MDOTC, 0x09555050,
+MX6_MMDC_P0_MDPDC, 0x00025576,
+MX6_MMDC_P0_MDASP, 0x00000027,
+MX6_MMDC_P0_MDCTL, 0x831A0000,
+MX6_MMDC_P0_MDSCR, 0x04088032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00428031,
+MX6_MMDC_P0_MDSCR, 0x19308030,
+MX6_MMDC_P0_MDSCR, 0x04008040,
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00005800,
+MX6_MMDC_P0_MPODTCTRL, 0x00000000,
+MX6_MMDC_P1_MPODTCTRL, 0x00000000,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
+MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
+MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
+MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
+MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
+
+MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
+MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
+MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static int mx6_it_dcd_table[] = {
+/* ddr-setup.cfg */
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC mirroring interleaved (row/bank/col)
+ */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+/* 1066mhz_4x256mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x00020036,
+MX6_MMDC_P0_MDCFG0, 0x898E78f5,
+MX6_MMDC_P0_MDCFG1, 0xff328f64,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x008E1023,
+MX6_MMDC_P0_MDOTC, 0x09444040,
+MX6_MMDC_P0_MDPDC, 0x00025576,
+MX6_MMDC_P0_MDASP, 0x00000047,
+MX6_MMDC_P0_MDCTL, 0x841A0000,
+MX6_MMDC_P0_MDSCR, 0x02888032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00048031,
+MX6_MMDC_P0_MDSCR, 0x19408030,
+MX6_MMDC_P0_MDSCR, 0x04008040,
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00007800,
+MX6_MMDC_P0_MPODTCTRL, 0x00022227,
+MX6_MMDC_P1_MPODTCTRL, 0x00022227,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
+MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
+MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
+MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
+MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
+
+MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
+MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
+MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFFFF3, &ccm->CCGR2);
+ writel(0x3FF0300F, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000F3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+ writel(0x000000FB, &ccm->ccosr);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void ddr_init(int *table, int size)
+{
+ int i;
+
+ for (i = 0; i < size / 2 ; i++)
+ writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+ int minc, maxc;
+
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_COMMERCIAL:
+ case TEMP_EXTCOMMERCIAL:
+ puts("Commercial temperature grade DDR3 timings.\n");
+ ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
+ break;
+ case TEMP_INDUSTRIAL:
+ case TEMP_AUTOMOTIVE:
+ default:
+ puts("Industrial temperature grade DDR3 timings.\n");
+ ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
+ break;
+ };
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+ /* Make sure we use dte mode */
+ setup_dtemode_uart();
+#endif
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+#endif
+
+static struct mxc_serial_platdata mxc_serial_plat = {
+ .reg = (struct mxc_uart *)UART1_BASE,
+ .use_dte = true,
+};
+
+U_BOOT_DEVICE(mxc_serial) = {
+ .name = "serial_mxc",
+ .platdata = &mxc_serial_plat,
+};
diff --git a/board/toradex/apalis_imx6/apalis_imx6q.cfg b/board/toradex/apalis_imx6/apalis_imx6q.cfg
new file mode 100644
index 0000000..b775010
--- /dev/null
+++ b/board/toradex/apalis_imx6/apalis_imx6q.cfg
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#if CONFIG_DDR_MB == 2048
+#include "1066mhz_4x256mx16.cfg"
+#else
+#include "1066mhz_4x128mx16.cfg"
+#endif
+#include "clocks.cfg"
diff --git a/board/toradex/apalis_imx6/clocks.cfg b/board/toradex/apalis_imx6/clocks.cfg
new file mode 100644
index 0000000..be96094
--- /dev/null
+++ b/board/toradex/apalis_imx6/clocks.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/apalis_imx6/ddr-setup.cfg b/board/toradex/apalis_imx6/ddr-setup.cfg
new file mode 100644
index 0000000..de7cdd6
--- /dev/null
+++ b/board/toradex/apalis_imx6/ddr-setup.cfg
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6DL ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 32 bits x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC mirroring interleaved (row/bank/col)
+ */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+/*
+ * MDSCR con_req
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c
new file mode 100644
index 0000000..cff07e9
--- /dev/null
+++ b/board/toradex/apalis_imx6/do_fuse.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Helpers for i.MX OTP fusing during module production
+*/
+
+#include <common.h>
+#ifndef CONFIG_SPL_BUILD
+#include <console.h>
+#include <fuse.h>
+
+static int mfgr_fuse(void)
+{
+ unsigned val, val6;
+
+ fuse_sense(0, 5, &val);
+ printf("Fuse 0, 5: %8x\n", val);
+ fuse_sense(0, 6, &val6);
+ printf("Fuse 0, 6: %8x\n", val6);
+ fuse_sense(4, 3, &val);
+ printf("Fuse 4, 3: %8x\n", val);
+ fuse_sense(4, 2, &val);
+ printf("Fuse 4, 2: %8x\n", val);
+ if (val6 & 0x10) {
+ puts("BT_FUSE_SEL already fused, will do nothing\n");
+ return CMD_RET_FAILURE;
+ }
+ /* boot cfg */
+ fuse_prog(0, 5, 0x00005072);
+ /* BT_FUSE_SEL */
+ fuse_prog(0, 6, 0x00000010);
+ return CMD_RET_SUCCESS;
+}
+
+int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret;
+ puts("Fusing...\n");
+ ret = mfgr_fuse();
+ if (ret == CMD_RET_SUCCESS)
+ puts("done.\n");
+ else
+ puts("failed.\n");
+ return ret;
+}
+
+int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned val;
+ int ret;
+ int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
+
+ /* can be used in scripts for command availability check */
+ if (argc >= 1 && !strcmp(argv[1], "-n"))
+ return CMD_RET_SUCCESS;
+
+ /* boot cfg */
+ fuse_sense(0, 5, &val);
+ printf("Fuse 0, 5: %8x\n", val);
+ if (val & 0x10) {
+ puts("Fast boot mode already fused, no need to fuse\n");
+ return CMD_RET_SUCCESS;
+ }
+ if (!confirmed) {
+ puts("Warning: Programming fuses is an irreversible operation!\n"
+ " Updating to fast boot mode prevents easy\n"
+ " downgrading to previous BSP versions.\n"
+ "\nReally perform this fuse programming? <y/N>\n");
+ if (!confirm_yesno())
+ return CMD_RET_FAILURE;
+ }
+ puts("Fusing fast boot mode...\n");
+ ret = fuse_prog(0, 5, 0x00005072);
+ if (ret == CMD_RET_SUCCESS)
+ puts("done.\n");
+ else
+ puts("failed.\n");
+ return ret;
+}
+
+U_BOOT_CMD(
+ mfgr_fuse, 1, 0, do_mfgr_fuse,
+ "OTP fusing during module production",
+ ""
+);
+
+U_BOOT_CMD(
+ updt_fuse, 2, 0, do_updt_fuse,
+ "OTP fusing during module update",
+ "updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
+);
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
new file mode 100644
index 0000000..0b42438
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+
+#include "pf0100_otp.inc"
+#include "pf0100.h"
+
+/* define for PMIC register dump */
+/*#define DEBUG */
+
+/* use Apalis GPIO1 to switch on VPGM, ON: 1 */
+static iomux_v3_cfg_t const pmic_prog_pads[] = {
+ MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4)
+};
+
+unsigned pmic_init(void)
+{
+ unsigned programmed = 0;
+ uchar bus = 1;
+ uchar devid, revid, val;
+
+ puts("PMIC: ");
+ if (!((0 == i2c_set_bus_num(bus)) &&
+ (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
+ puts("i2c bus failed\n");
+ return 0;
+ }
+ /* get device ident */
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
+ puts("i2c pmic devid read failed\n");
+ return 0;
+ }
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
+ puts("i2c pmic revid read failed\n");
+ return 0;
+ }
+ printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+
+#ifdef DEBUG
+ {
+ unsigned i, j;
+
+ for (i = 0; i < 16; i++)
+ printf("\t%x", i);
+ for (j = 0; j < 0x80; ) {
+ printf("\n%2x", j);
+ for (i = 0; i < 16; i++) {
+ i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+ printf("\t%2x", val);
+ }
+ j += 0x10;
+ }
+ printf("\nEXT Page 1");
+
+ val = PFUZE100_PAGE_REGISTER_PAGE1;
+ if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
+ &val, 1)) {
+ puts("i2c write failed\n");
+ return 0;
+ }
+
+ for (j = 0x80; j < 0x100; ) {
+ printf("\n%2x", j);
+ for (i = 0; i < 16; i++) {
+ i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+ printf("\t%2x", val);
+ }
+ j += 0x10;
+ }
+ printf("\nEXT Page 2");
+
+ val = PFUZE100_PAGE_REGISTER_PAGE2;
+ if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
+ &val, 1)) {
+ puts("i2c write failed\n");
+ return 0;
+ }
+
+ for (j = 0x80; j < 0x100; ) {
+ printf("\n%2x", j);
+ for (i = 0; i < 16; i++) {
+ i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+ printf("\t%2x", val);
+ }
+ j += 0x10;
+ }
+ printf("\n");
+ }
+#endif
+ /* get device programmed state */
+ val = PFUZE100_PAGE_REGISTER_PAGE1;
+ if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
+ puts("i2c write failed\n");
+ return 0;
+ }
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
+ puts("i2c fuse_por read failed\n");
+ return 0;
+ }
+ if (val & PFUZE100_FUSE_POR_M)
+ programmed++;
+
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
+ puts("i2c fuse_por read failed\n");
+ return programmed;
+ }
+ if (val & PFUZE100_FUSE_POR_M)
+ programmed++;
+
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
+ puts("i2c fuse_por read failed\n");
+ return programmed;
+ }
+ if (val & PFUZE100_FUSE_POR_M)
+ programmed++;
+
+ switch (programmed) {
+ case 0:
+ printf("PMIC: not programmed\n");
+ break;
+ case 3:
+ printf("PMIC: programmed\n");
+ break;
+ default:
+ printf("PMIC: undefined programming state\n");
+ break;
+ }
+
+ /* The following is needed during production */
+ if (programmed != 3) {
+ /* set VGEN1 to 1.2V */
+ val = PFUZE100_VGEN1_VAL;
+ if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1,
+ &val, 1)) {
+ puts("i2c write failed\n");
+ return programmed;
+ }
+
+ /* set SWBST to 5.0V */
+ val = PFUZE100_SWBST_VAL;
+ if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1,
+ &val, 1)) {
+ puts("i2c write failed\n");
+ }
+ }
+ return programmed;
+}
+
+int pf0100_prog(void)
+{
+ unsigned char bus = 1;
+ unsigned char val;
+ unsigned int i;
+
+ if (pmic_init() == 3) {
+ puts("PMIC already programmed, exiting\n");
+ return CMD_RET_FAILURE;
+ }
+ /* set up gpio to manipulate vprog, initially off */
+ imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
+ ARRAY_SIZE(pmic_prog_pads));
+ gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
+
+ if (!((0 == i2c_set_bus_num(bus)) &&
+ (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
+ puts("i2c bus failed\n");
+ return CMD_RET_FAILURE;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
+ switch (pmic_otp_prog[i].cmd) {
+ case pmic_i2c:
+ val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
+ if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
+ 1, &val, 1)) {
+ printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
+ pmic_otp_prog[i].reg, val);
+ return CMD_RET_FAILURE;
+ }
+ break;
+ case pmic_delay:
+ udelay(pmic_otp_prog[i].value * 1000);
+ break;
+ case pmic_vpgm:
+ gpio_direction_output(PMIC_PROG_VOLTAGE,
+ pmic_otp_prog[i].value);
+ break;
+ case pmic_pwr:
+ /* TODO */
+ break;
+ }
+ }
+ return CMD_RET_SUCCESS;
+}
+
+int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret;
+ puts("Programming PMIC OTP...");
+ ret = pf0100_prog();
+ if (ret == CMD_RET_SUCCESS)
+ puts("done.\n");
+ else
+ puts("failed.\n");
+ return ret;
+}
+
+U_BOOT_CMD(
+ pf0100_otp_prog, 1, 0, do_pf0100_prog,
+ "Program the OTP fuses on the PMIC PF0100",
+ ""
+);
diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h
new file mode 100644
index 0000000..c84cab8
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#ifndef PF0100_H_
+#define PF0100_H_
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR (0x08)
+/* Register Addresses */
+#define PFUZE100_DEVICEID (0x0)
+#define PFUZE100_REVID (0x3)
+#define PFUZE100_SW1AMODE (0x23)
+#define PFUZE100_SW1ACON 36
+#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
+#define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
+#define PFUZE100_SW1CCON 49
+#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
+#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
+#define PFUZE100_SW1AVOL 32
+#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0)
+#define PFUZE100_SW1CVOL 46
+#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
+#define PFUZE100_VGEN1CTL (0x6c)
+#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */
+#define PFUZE100_SWBSTCTL (0x66)
+/* Always ON, Auto Switching Mode, 5.0V */
+#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00)
+
+/* chooses the extended page (registers 0x80..0xff) */
+#define PFUZE100_PAGE_REGISTER 0x7f
+#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0)
+#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
+#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
+
+/* extended page 1 */
+#define PFUZE100_FUSE_POR1 0xe4
+#define PFUZE100_FUSE_POR2 0xe5
+#define PFUZE100_FUSE_POR3 0xe6
+#define PFUZE100_FUSE_POR_M (0x1 << 1)
+
+
+/* output some informational messages, return the number FUSE_POR=1 */
+/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
+unsigned pmic_init(void);
+
+/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
+int pf0100_prog(void);
+
+#endif /* PF0100_H_ */
diff --git a/board/toradex/apalis_imx6/pf0100_otp.inc b/board/toradex/apalis_imx6/pf0100_otp.inc
new file mode 100644
index 0000000..59e0587
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100_otp.inc
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+// Register Output for PF0100 programmer
+// Customer: Toradex AG
+// Program: Apalis iMX6
+// Sample marking:
+// Date: 12.02.2014
+// Time: 17:16:41
+// Generated from Spreadsheet Revision: P1.8
+
+/* sed commands to get from programmer script to struct */
+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
+ sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
+ sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
+
+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
+struct pmic_otp_prog_t{
+ unsigned char cmd;
+ unsigned char reg;
+ unsigned short value;
+};
+
+struct pmic_otp_prog_t pmic_otp_prog[] = {
+{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
+{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
+{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
+{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
+{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
+{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
+{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
+{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
+{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
+{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
+{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
+{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
+{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
+{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
+{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
+{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
+{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
+{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
+{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
+{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
+{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
+{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
+{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
+{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
+{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
+{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
+{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
+{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
+{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
+{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
+{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
+{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
+
+#if 0 /* TBB mode */
+{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
+{pmic_delay, 0, 10},
+#else
+// Write OTP
+{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
+{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
+{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
+{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
+{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
+{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
+{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
+{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
+//VPGM:DOWN:n
+//VPGM:UP:n
+{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
+//-----------------------------------------------------------------------------------
+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
+//-----------------------------------------------------------------------------------
+// BANK 1
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 2
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 3
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 4
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 5
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 6
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 7
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 8
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 9
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 10
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
+{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
+{pmic_i2c, 0xD0, 0x00}, // Clear
+{pmic_i2c, 0xD1, 0x00}, // Clear
+{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
+{pmic_delay, 0, 500},
+{pmic_pwr, 0, 1},
+#endif
+};
\ No newline at end of file
diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
index f1dcda5..16224da 100644
--- a/board/toradex/apalis_t30/Kconfig
+++ b/board/toradex/apalis_t30/Kconfig
@@ -9,4 +9,22 @@
config SYS_CONFIG_NAME
default "apalis_t30"
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+source "board/toradex/common/Kconfig"
+
endif
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c
index 3f56971..827eefd 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2014
+ * (C) Copyright 2014-2016
* Marcel Ziswiler <marcel@ziswiler.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -14,9 +14,12 @@
#include <asm/io.h>
#include <dm.h>
#include <i2c.h>
+#include "../common/tdx-common.h"
#include "pinmux-config-apalis_t30.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define PMU_I2C_ADDRESS 0x2D
#define MAX_I2C_RETRY 3
@@ -29,6 +32,21 @@
return 0;
}
+int checkboard(void)
+{
+ printf("Model: Toradex Apalis T30 %dGB\n",
+ (gd->ram_size == 0x40000000) ? 1 : 2);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
new file mode 100644
index 0000000..660f9d3
--- /dev/null
+++ b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+/* DDR3 DATA BUS SIZE: 64BIT */
+/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */
+/* DDR3 DATA BUS SIZE: 32BIT */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
new file mode 100644
index 0000000..3bd8576
--- /dev/null
+++ b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+/* DDR3 DATA BUS SIZE: 64BIT */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000
+/* DDR3 DATA BUS SIZE: 32BIT */
+/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig
new file mode 100644
index 0000000..d2ad1ce
--- /dev/null
+++ b/board/toradex/colibri_imx6/Kconfig
@@ -0,0 +1,44 @@
+if TARGET_COLIBRI_IMX6
+
+config SYS_BOARD
+ default "colibri_imx6"
+
+config SYS_CONFIG_NAME
+ default "colibri_imx6"
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_VENDOR
+ default "toradex"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+config TDX_CMD_IMX_MFGR
+ bool "Enable factory testing commands for Toradex iMX 6 modules"
+ help
+ This adds the commands
+ pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
+ If executed on already fused modules it doesn't change any fuse setting.
+ default y
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
new file mode 100644
index 0000000..1cc7ef2
--- /dev/null
+++ b/board/toradex/colibri_imx6/MAINTAINERS
@@ -0,0 +1,8 @@
+Colibri iMX6
+M: Max Krummenacher <max.krummenacher@toradex.com>
+W: http://developer.toradex.com/software/linux/linux-software
+S: Maintained
+F: board/toradex/colibri_imx6/
+F: include/configs/colibri_imx6.h
+F: configs/colibri_imx6_defconfig
+F: configs/colibri_imx6_nospl_defconfig
diff --git a/board/toradex/colibri_imx6/Makefile b/board/toradex/colibri_imx6/Makefile
new file mode 100644
index 0000000..c81bc2d
--- /dev/null
+++ b/board/toradex/colibri_imx6/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2012-2014 Toradex, Inc.
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := colibri_imx6.o do_fuse.o
+obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o
diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg
new file mode 100644
index 0000000..be96094
--- /dev/null
+++ b/board/toradex/colibri_imx6/clocks.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
new file mode 100644
index 0000000..d070677
--- /dev/null
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -0,0 +1,1130 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ * Copyright (C) 2014-2016, Toradex AG
+ * copied from nitrogen6x
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <asm/io.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/platdata.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <imx_thermal.h>
+#include <linux/errno.h>
+#include <malloc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+
+#include "../common/tdx-cfg-block.h"
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+#include "pf0100.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_SLOW)
+
+#define NO_PULLUP ( \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+ /* use the DDR controllers configured size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ (ulong)imx_ddr_size());
+
+ return 0;
+}
+
+/* Colibri UARTA */
+iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* Colibri I2C */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+
+/* Colibri local, PMIC, SGTL5000, STMPE811 */
+struct i2c_pads_info i2c_pad_info_loc = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+ .gp = IMX_GPIO_NR(3, 16)
+ }
+};
+
+/* Apalis MMC */
+iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+# define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
+};
+
+/* eMMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
+iomux_v3_cfg_t const gpio_pads[] = {
+ /* ADDRESS[17:18] [25] used as GPIO */
+ MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* ADDRESS[19:24] used as GPIO */
+ MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* DATA[16:29] [31] used as GPIO */
+ MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* DQM[0:3] used as GPIO */
+ MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* RDY used as GPIO */
+ MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* ADDRESS[16] DATA[30] used as GPIO */
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN),
+ MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* CSI pins used as GPIO */
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN),
+ MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* GPIO */
+ MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* USBH_OC */
+ MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* USBC_ID */
+ MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* USBC_DET */
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_gpio(void)
+{
+ imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+iomux_v3_cfg_t const usb_pads[] = {
+ /* USB_PE */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+# define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
+};
+
+/*
+ * UARTs are used in DTE mode, switch the mode on all UARTs before
+ * any pinmuxing connects a (DCE) output to a transceiver output.
+ */
+#define UFCR 0x90 /* FIFO Control Register */
+#define UFCR_DCEDTE (1<<6) /* DCE=0 */
+
+static void setup_dtemode_uart(void)
+{
+ setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
+ setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
+ setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
+}
+
+static void setup_iomux_uart(void)
+{
+ setup_dtemode_uart();
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ /* control OTG power */
+ /* No special PE for USBC, always on when ID pin signals
+ host mode */
+ break;
+ case 1:
+ /* Control MXM USBH */
+ /* Set MXM USBH power enable, '0' means on */
+ gpio_direction_output(GPIO_USBH_EN, !on);
+ mdelay(100);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+/* use the following sequence: eMMC, MMC */
+struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = true; /* default: assume inserted */
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ gpio_direction_input(GPIO_MMC_CD);
+ ret = !gpio_get_value(GPIO_MMC_CD);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+ s32 status = 0;
+ u32 index = 0;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ usdhc_cfg[0].max_bus_width = 8;
+ usdhc_cfg[1].max_bus_width = 4;
+
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
+
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ }
+
+ return status;
+#else
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(&psrc->sbmr1) >> 11;
+ /*
+ * Upon reading BOOT_CFG register the following map is done:
+ * Bit 11 and 12 of BOOT_CFG register can determine the current
+ * mmc port
+ * 0x1 SD1
+ * 0x2 SD2
+ * 0x3 SD4
+ */
+
+ switch (reg & 0x3) {
+ case 0x0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ default:
+ puts("MMC boot device not available");
+ }
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ /* provide the PHY clock from the i.MX 6 */
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ return ret;
+ /* set gpr1[ENET_CLK_SEL] */
+ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+ setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+ /* scan PHY 1..7 */
+ phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
+ if (!phydev) {
+ free(bus);
+ puts("no PHY found\n");
+ return 0;
+ }
+ phy_reset(phydev);
+ printf("using PHY at %d\n", phydev->addr);
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ free(phydev);
+ free(bus);
+ }
+#endif
+ return 0;
+}
+
+static iomux_v3_cfg_t const pwr_intb_pads[] = {
+ /*
+ * the bootrom sets the iomux to vselect, potentially connecting
+ * two outputs. Set this back to GPIO
+ */
+ MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+ /* Backlight On */
+ MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
+ /* Backlight PWM, used as GPIO in U-Boot */
+ MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
+ MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(
+ rgb_pads,
+ ARRAY_SIZE(rgb_pads));
+ gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+ gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+}
+
+static int detect_default(struct display_info_t const *dev)
+{
+ (void) dev;
+ return 1;
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = detect_default,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "vga-rgb",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 33000,
+ .left_margin = 48,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .lower_margin = 11,
+ .hsync_len = 96,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "wvga-rgb",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 25000,
+ .left_margin = 40,
+ .right_margin = 88,
+ .upper_margin = 33,
+ .lower_margin = 10,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+ |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+ |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+
+ /* backlight unconditionally on for now */
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+ /* use 0 for EDT 7", use 1 for LG fullHD panel */
+ gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+ gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+#endif /* defined(CONFIG_VIDEO_IPUV3) */
+
+int board_early_init_f(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
+ ARRAY_SIZE(pwr_intb_pads));
+ setup_iomux_uart();
+
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
+
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+ (void) pmic_init();
+#endif
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
+ setup_iomux_gpio();
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if defined(CONFIG_REVISION_TAG) && \
+ defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+ char env_str[256];
+ u32 rev;
+
+ rev = get_board_rev();
+ snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
+ setenv("board_rev", env_str);
+#endif
+
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
+int ft_system_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+int checkboard(void)
+{
+ char it[] = " IT";
+ int minc, maxc;
+
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_AUTOMOTIVE:
+ case TEMP_INDUSTRIAL:
+ break;
+ case TEMP_EXTCOMMERCIAL:
+ default:
+ it[0] = 0;
+ };
+ printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
+ is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
+ (gd->ram_size == 0x20000000) ? "512" : "256", it);
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+/* TODO, use external pmic, for now always ldo_enable */
+void ldo_mode_set(int ldo_bypass)
+{
+ return;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+#include "asm/arch/mx6dl-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+static int mx6s_dcd_table[] = {
+/* ddr-setup.cfg */
+
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC mirroring interleaved (row/bank/col)
+ */
+/* TODO: check what the RALAT field does */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+
+/* 800mhz_2x64mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x0002002D,
+MX6_MMDC_P0_MDCFG0, 0x2C305503,
+MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x00301023,
+MX6_MMDC_P0_MDOTC, 0x00333030,
+MX6_MMDC_P0_MDPDC, 0x0002556D,
+/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
+MX6_MMDC_P0_MDASP, 0x00000017,
+/* DDR3 DATA BUS SIZE: 64BIT */
+/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
+/* DDR3 DATA BUS SIZE: 32BIT */
+MX6_MMDC_P0_MDCTL, 0x82190000,
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* MX6_MMDC_P0_MDSCR, 0x04408032, */
+MX6_MMDC_P0_MDSCR, 0x04008032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00048031,
+MX6_MMDC_P0_MDSCR, 0x13208030,
+/* ZQ calibration */
+MX6_MMDC_P0_MDSCR, 0x04008040,
+
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00005800,
+
+MX6_MMDC_P0_MPODTCTRL, 0x00000000,
+MX6_MMDC_P1_MPODTCTRL, 0x00000000,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
+MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
+MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
+MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
+MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
+MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
+MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
+MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static int mx6dl_dcd_table[] = {
+/* ddr-setup.cfg */
+
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC mirroring interleaved (row/bank/col)
+ */
+/* TODO: check what the RALAT field does */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+
+/* 800mhz_2x64mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x0002002D,
+MX6_MMDC_P0_MDCFG0, 0x2C305503,
+MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x00301023,
+MX6_MMDC_P0_MDOTC, 0x00333030,
+MX6_MMDC_P0_MDPDC, 0x0002556D,
+/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
+MX6_MMDC_P0_MDASP, 0x00000017,
+/* DDR3 DATA BUS SIZE: 64BIT */
+MX6_MMDC_P0_MDCTL, 0x821A0000,
+/* DDR3 DATA BUS SIZE: 32BIT */
+/* MX6_MMDC_P0_MDCTL, 0x82190000, */
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* MX6_MMDC_P0_MDSCR, 0x04408032, */
+MX6_MMDC_P0_MDSCR, 0x04008032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00048031,
+MX6_MMDC_P0_MDSCR, 0x13208030,
+/* ZQ calibration */
+MX6_MMDC_P0_MDSCR, 0x04008040,
+
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00005800,
+
+MX6_MMDC_P0_MPODTCTRL, 0x00000000,
+MX6_MMDC_P1_MPODTCTRL, 0x00000000,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
+MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
+MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
+MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
+MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
+MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
+MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
+MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFFFF3, &ccm->CCGR2);
+ writel(0x3FF0300F, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000F3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+ writel(0x000000FB, &ccm->ccosr);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void ddr_init(int *table, int size)
+{
+ int i;
+
+ for (i = 0; i < size / 2 ; i++)
+ writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+ int minc, maxc;
+
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_COMMERCIAL:
+ case TEMP_EXTCOMMERCIAL:
+ if (is_cpu_type(MXC_CPU_MX6DL)) {
+ puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
+ ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+ } else {
+ puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
+ ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
+ }
+ break;
+ case TEMP_INDUSTRIAL:
+ case TEMP_AUTOMOTIVE:
+ default:
+ if (is_cpu_type(MXC_CPU_MX6DL)) {
+ ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+ } else {
+ puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
+ ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
+ }
+ break;
+ };
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* Make sure we use dte mode */
+ setup_dtemode_uart();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+#endif
+
+static struct mxc_serial_platdata mxc_serial_plat = {
+ .reg = (struct mxc_uart *)UART1_BASE,
+ .use_dte = true,
+};
+
+U_BOOT_DEVICE(mxc_serial) = {
+ .name = "serial_mxc",
+ .platdata = &mxc_serial_plat,
+};
diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg
new file mode 100644
index 0000000..e7886de
--- /dev/null
+++ b/board/toradex/colibri_imx6/colibri_imx6.cfg
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014 Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+
+#if CONFIG_DDR_MB == 256
+#include "800mhz_2x64mx16.cfg"
+#elif CONFIG_DDR_MB == 512
+#include "800mhz_4x64mx16.cfg"
+#else
+#error "unknown DDR size"
+#endif
+
+#include "clocks.cfg"
diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg
new file mode 100644
index 0000000..f46ae55
--- /dev/null
+++ b/board/toradex/colibri_imx6/ddr-setup.cfg
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6DL ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 32 bits x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC mirroring interleaved (row/bank/col)
+ */
+/* TODO: check what the RALAT field does */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+/*
+ * MDSCR con_req
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c
new file mode 100644
index 0000000..cff07e9
--- /dev/null
+++ b/board/toradex/colibri_imx6/do_fuse.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Helpers for i.MX OTP fusing during module production
+*/
+
+#include <common.h>
+#ifndef CONFIG_SPL_BUILD
+#include <console.h>
+#include <fuse.h>
+
+static int mfgr_fuse(void)
+{
+ unsigned val, val6;
+
+ fuse_sense(0, 5, &val);
+ printf("Fuse 0, 5: %8x\n", val);
+ fuse_sense(0, 6, &val6);
+ printf("Fuse 0, 6: %8x\n", val6);
+ fuse_sense(4, 3, &val);
+ printf("Fuse 4, 3: %8x\n", val);
+ fuse_sense(4, 2, &val);
+ printf("Fuse 4, 2: %8x\n", val);
+ if (val6 & 0x10) {
+ puts("BT_FUSE_SEL already fused, will do nothing\n");
+ return CMD_RET_FAILURE;
+ }
+ /* boot cfg */
+ fuse_prog(0, 5, 0x00005072);
+ /* BT_FUSE_SEL */
+ fuse_prog(0, 6, 0x00000010);
+ return CMD_RET_SUCCESS;
+}
+
+int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret;
+ puts("Fusing...\n");
+ ret = mfgr_fuse();
+ if (ret == CMD_RET_SUCCESS)
+ puts("done.\n");
+ else
+ puts("failed.\n");
+ return ret;
+}
+
+int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned val;
+ int ret;
+ int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
+
+ /* can be used in scripts for command availability check */
+ if (argc >= 1 && !strcmp(argv[1], "-n"))
+ return CMD_RET_SUCCESS;
+
+ /* boot cfg */
+ fuse_sense(0, 5, &val);
+ printf("Fuse 0, 5: %8x\n", val);
+ if (val & 0x10) {
+ puts("Fast boot mode already fused, no need to fuse\n");
+ return CMD_RET_SUCCESS;
+ }
+ if (!confirmed) {
+ puts("Warning: Programming fuses is an irreversible operation!\n"
+ " Updating to fast boot mode prevents easy\n"
+ " downgrading to previous BSP versions.\n"
+ "\nReally perform this fuse programming? <y/N>\n");
+ if (!confirm_yesno())
+ return CMD_RET_FAILURE;
+ }
+ puts("Fusing fast boot mode...\n");
+ ret = fuse_prog(0, 5, 0x00005072);
+ if (ret == CMD_RET_SUCCESS)
+ puts("done.\n");
+ else
+ puts("failed.\n");
+ return ret;
+}
+
+U_BOOT_CMD(
+ mfgr_fuse, 1, 0, do_mfgr_fuse,
+ "OTP fusing during module production",
+ ""
+);
+
+U_BOOT_CMD(
+ updt_fuse, 2, 0, do_updt_fuse,
+ "OTP fusing during module update",
+ "updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
+);
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c
new file mode 100644
index 0000000..618c571
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+
+#include "pf0100_otp.inc"
+#include "pf0100.h"
+
+/* define for PMIC register dump */
+/*#define DEBUG */
+
+/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
+static iomux_v3_cfg_t const pmic_prog_pads[] = {
+ MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
+};
+
+unsigned pmic_init(void)
+{
+ unsigned programmed = 0;
+ uchar bus = 1;
+ uchar devid, revid, val;
+
+ puts("PMIC: ");
+ if (!((0 == i2c_set_bus_num(bus)) &&
+ (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
+ puts("i2c bus failed\n");
+ return 0;
+ }
+ /* get device ident */
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
+ puts("i2c pmic devid read failed\n");
+ return 0;
+ }
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
+ puts("i2c pmic revid read failed\n");
+ return 0;
+ }
+ printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+
+#ifdef DEBUG
+ {
+ unsigned i, j;
+
+ for (i = 0; i < 16; i++)
+ printf("\t%x", i);
+ for (j = 0; j < 0x80; ) {
+ printf("\n%2x", j);
+ for (i = 0; i < 16; i++) {
+ i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+ printf("\t%2x", val);
+ }
+ j += 0x10;
+ }
+ printf("\nEXT Page 1");
+
+ val = PFUZE100_PAGE_REGISTER_PAGE1;
+ if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
+ &val, 1)) {
+ puts("i2c write failed\n");
+ return 0;
+ }
+
+ for (j = 0x80; j < 0x100; ) {
+ printf("\n%2x", j);
+ for (i = 0; i < 16; i++) {
+ i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+ printf("\t%2x", val);
+ }
+ j += 0x10;
+ }
+ printf("\nEXT Page 2");
+
+ val = PFUZE100_PAGE_REGISTER_PAGE2;
+ if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
+ &val, 1)) {
+ puts("i2c write failed\n");
+ return 0;
+ }
+
+ for (j = 0x80; j < 0x100; ) {
+ printf("\n%2x", j);
+ for (i = 0; i < 16; i++) {
+ i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+ printf("\t%2x", val);
+ }
+ j += 0x10;
+ }
+ printf("\n");
+ }
+#endif
+ /* get device programmed state */
+ val = PFUZE100_PAGE_REGISTER_PAGE1;
+ if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
+ puts("i2c write failed\n");
+ return 0;
+ }
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
+ puts("i2c fuse_por read failed\n");
+ return 0;
+ }
+ if (val & PFUZE100_FUSE_POR_M)
+ programmed++;
+
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
+ puts("i2c fuse_por read failed\n");
+ return programmed;
+ }
+ if (val & PFUZE100_FUSE_POR_M)
+ programmed++;
+
+ if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
+ puts("i2c fuse_por read failed\n");
+ return programmed;
+ }
+ if (val & PFUZE100_FUSE_POR_M)
+ programmed++;
+
+ switch (programmed) {
+ case 0:
+ printf("PMIC: not programmed\n");
+ break;
+ case 3:
+ printf("PMIC: programmed\n");
+ break;
+ default:
+ printf("PMIC: undefined programming state\n");
+ break;
+ }
+
+ return programmed;
+}
+
+int pf0100_prog(void)
+{
+ unsigned char bus = 1;
+ unsigned char val;
+ unsigned int i;
+
+ if (pmic_init() == 3) {
+ puts("PMIC already programmed, exiting\n");
+ return CMD_RET_FAILURE;
+ }
+ /* set up gpio to manipulate vprog, initially off */
+ imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
+ ARRAY_SIZE(pmic_prog_pads));
+ gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
+
+ if (!((0 == i2c_set_bus_num(bus)) &&
+ (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
+ puts("i2c bus failed\n");
+ return CMD_RET_FAILURE;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
+ switch (pmic_otp_prog[i].cmd) {
+ case pmic_i2c:
+ val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
+ if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
+ 1, &val, 1)) {
+ printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
+ pmic_otp_prog[i].reg, val);
+ return CMD_RET_FAILURE;
+ }
+ break;
+ case pmic_delay:
+ udelay(pmic_otp_prog[i].value * 1000);
+ break;
+ case pmic_vpgm:
+ gpio_direction_output(PMIC_PROG_VOLTAGE,
+ pmic_otp_prog[i].value);
+ break;
+ case pmic_pwr:
+ /* TODO */
+ break;
+ }
+ }
+ return CMD_RET_SUCCESS;
+}
+
+int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret;
+ puts("Programming PMIC OTP...");
+ ret = pf0100_prog();
+ if (ret == CMD_RET_SUCCESS)
+ puts("done.\n");
+ else
+ puts("failed.\n");
+ return ret;
+}
+
+U_BOOT_CMD(
+ pf0100_otp_prog, 1, 0, do_pf0100_prog,
+ "Program the OTP fuses on the PMIC PF0100",
+ ""
+);
diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h
new file mode 100644
index 0000000..c84cab8
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#ifndef PF0100_H_
+#define PF0100_H_
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR (0x08)
+/* Register Addresses */
+#define PFUZE100_DEVICEID (0x0)
+#define PFUZE100_REVID (0x3)
+#define PFUZE100_SW1AMODE (0x23)
+#define PFUZE100_SW1ACON 36
+#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
+#define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
+#define PFUZE100_SW1CCON 49
+#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
+#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
+#define PFUZE100_SW1AVOL 32
+#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0)
+#define PFUZE100_SW1CVOL 46
+#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
+#define PFUZE100_VGEN1CTL (0x6c)
+#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */
+#define PFUZE100_SWBSTCTL (0x66)
+/* Always ON, Auto Switching Mode, 5.0V */
+#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00)
+
+/* chooses the extended page (registers 0x80..0xff) */
+#define PFUZE100_PAGE_REGISTER 0x7f
+#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0)
+#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
+#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
+
+/* extended page 1 */
+#define PFUZE100_FUSE_POR1 0xe4
+#define PFUZE100_FUSE_POR2 0xe5
+#define PFUZE100_FUSE_POR3 0xe6
+#define PFUZE100_FUSE_POR_M (0x1 << 1)
+
+
+/* output some informational messages, return the number FUSE_POR=1 */
+/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
+unsigned pmic_init(void);
+
+/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
+int pf0100_prog(void);
+
+#endif /* PF0100_H_ */
diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc
new file mode 100644
index 0000000..255392b
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100_otp.inc
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+// Register Output for PF0100 programmer
+// Customer: Toradex AG
+// Program: Colibri iMX6
+// Sample marking:
+// Date: 24.07.2015
+// Time: 10:52:58
+// Generated from Spreadsheet Revision: P1.8
+
+/* sed commands to get from programmer script to struct */
+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc
+ sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
+ sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
+
+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
+struct pmic_otp_prog_t{
+ unsigned char cmd;
+ unsigned char reg;
+ unsigned short value;
+};
+
+struct pmic_otp_prog_t pmic_otp_prog[] = {
+{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
+{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
+{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
+{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
+{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
+{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
+{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
+{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
+{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
+{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
+{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
+{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
+{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
+{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
+{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
+{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
+{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
+{pmic_i2c, 0xBD, 0x0E}, // Auto gen from Row123
+{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
+{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
+{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
+{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
+{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
+{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
+{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
+{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
+{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
+{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
+{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
+{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158
+
+#if 0 /* TBB mode */
+{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
+{pmic_delay, 0, 10},
+#else
+// Write OTP
+{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
+{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
+{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
+{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
+{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
+{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
+{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
+{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
+//VPGM:DOWN:n
+//VPGM:UP:n
+{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
+//-----------------------------------------------------------------------------------
+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
+//-----------------------------------------------------------------------------------
+// BANK 1
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 2
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 3
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 4
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 5
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 6
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 7
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 8
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 9
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 10
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
+{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
+{pmic_i2c, 0xD0, 0x00}, // Clear
+{pmic_i2c, 0xD1, 0x00}, // Clear
+{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
+{pmic_delay, 0, 500},
+{pmic_pwr, 0, 1},
+#endif
+};
\ No newline at end of file
diff --git a/board/toradex/colibri_imx7/Kconfig b/board/toradex/colibri_imx7/Kconfig
index 7bba26b..414a600 100644
--- a/board/toradex/colibri_imx7/Kconfig
+++ b/board/toradex/colibri_imx7/Kconfig
@@ -16,5 +16,21 @@
clock source.
default y
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_HAVE_NAND
+ default y
+
+config TDX_CFG_BLOCK_OFFSET
+ default "2048"
+
+config TDX_CFG_BLOCK_OFFSET2
+ default "133120"
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+ default y
+
+source "board/toradex/common/Kconfig"
endif
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index 8eedd65..e1340c3 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -12,18 +12,19 @@
#include <asm/gpio.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
#include <fsl_esdhc.h>
-#include <i2c.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <miiphy.h>
#include <netdev.h>
+#include <power/pmic.h>
+#include <power/rn5t567_pmic.h>
#include <usb/ehci-ci.h>
+#include "../common/tdx-common.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -38,9 +39,6 @@
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
-
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_DSE_3P3V_49OHM)
@@ -48,36 +46,6 @@
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC,
- .gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC,
- .gp = IMX_GPIO_NR(1, 4),
- },
- .sda = {
- .i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC,
- .gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC,
- .gp = IMX_GPIO_NR(1, 5),
- },
-};
-/* I2C4 for Colibri I2C */
-static struct i2c_pads_info i2c_pad_info4 = {
- .scl = {
- .i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC,
- .gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC,
- .gp = IMX_GPIO_NR(7, 8),
- },
- .sda = {
- .i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC,
- .gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC,
- .gp = IMX_GPIO_NR(7, 9),
- },
-};
-#endif
-
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -331,11 +299,6 @@
{
setup_iomux_uart();
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
-#endif
-
return 0;
}
@@ -377,6 +340,46 @@
return 0;
}
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int reg, ver;
+ int ret;
+
+
+ ret = pmic_get("rn5t567", &dev);
+ if (ret)
+ return ret;
+ ver = pmic_reg_read(dev, RN5T567_LSIVER);
+ reg = pmic_reg_read(dev, RN5T567_OTPVER);
+
+ printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
+
+ /* set judge and press timer of N_OE to minimal values */
+ pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ struct udevice *dev;
+
+ pmic_get("rn5t567", &dev);
+
+ /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
+ pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
+ pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
+
+ /*
+ * Re-power factor detection on PMIC side is not instant. 1ms
+ * proved to be enough time until reset takes effect.
+ */
+ mdelay(1);
+}
+#endif
+
int checkboard(void)
{
printf("Model: Toradex Colibri iMX7%c\n",
@@ -385,6 +388,13 @@
return 0;
}
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
#ifdef CONFIG_USB_EHCI_MX7
static iomux_v3_cfg_t const usb_otg2_pads[] = {
MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -408,13 +418,3 @@
return 0;
}
#endif
-
-static struct mxc_serial_platdata mxc_serial_plat = {
- .reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR,
- .use_dte = true,
-};
-
-U_BOOT_DEVICE(mxc_serial) = {
- .name = "serial_mxc",
- .platdata = &mxc_serial_plat,
-};
diff --git a/board/toradex/colibri_imx7/imximage.cfg b/board/toradex/colibri_imx7/imximage.cfg
index d891e82..ca3cd89 100644
--- a/board/toradex/colibri_imx7/imximage.cfg
+++ b/board/toradex/colibri_imx7/imximage.cfg
@@ -4,7 +4,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig
index 949407a..f646baa 100644
--- a/board/toradex/colibri_pxa270/Kconfig
+++ b/board/toradex/colibri_pxa270/Kconfig
@@ -9,4 +9,15 @@
config SYS_CONFIG_NAME
default "colibri_pxa270"
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_HAVE_NOR
+ default y
+
+config TDX_CFG_BLOCK_OFFSET
+ default "262144"
+
+source "board/toradex/common/Kconfig"
+
endif
diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c
index 3def0a6..8e94854 100644
--- a/board/toradex/colibri_pxa270/colibri_pxa270.c
+++ b/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -2,18 +2,23 @@
* Toradex Colibri PXA270 Support
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/regs-mmc.h>
#include <asm/arch/pxa.h>
-#include <netdev.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/regs-uart.h>
#include <asm/io.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pxa.h>
+#include <netdev.h>
#include <serial.h>
#include <usb.h>
+#include "../common/tdx-common.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -32,6 +37,20 @@
return 0;
}
+int checkboard(void)
+{
+ puts("Model: Toradex Colibri PXA270\n");
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
int dram_init(void)
{
pxa2xx_dram_init();
@@ -105,3 +124,14 @@
return 0;
}
#endif
+
+static const struct pxa_serial_platdata serial_platdata = {
+ .base = (struct pxa_uart_regs *)FFUART_BASE,
+ .port = FFUART_INDEX,
+ .baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DEVICE(pxa_serials) = {
+ .name = "serial_pxa",
+ .platdata = &serial_platdata,
+};
diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig
index 7f373b2..a43acdd 100644
--- a/board/toradex/colibri_t20/Kconfig
+++ b/board/toradex/colibri_t20/Kconfig
@@ -9,4 +9,15 @@
config SYS_CONFIG_NAME
default "colibri_t20"
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_HAVE_NAND
+ default y
+
+config TDX_CFG_BLOCK_OFFSET
+ default "3145728"
+
+source "board/toradex/common/Kconfig"
+
endif
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 68fbf49..4d298e6 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -14,6 +14,10 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <i2c.h>
+#include <nand.h>
+#include "../common/tdx-common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
#define PMU_I2C_ADDRESS 0x34
#define MAX_I2C_RETRY 3
@@ -61,6 +65,23 @@
return 0;
}
+int checkboard(void)
+{
+ printf("Model: Toradex Colibri T20 %dMB V%s\n",
+ (gd->ram_size == 0x10000000) ? 256 : 512,
+ (nand_info[0]->erasesize >> 10 == 512) ?
+ ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
#ifdef CONFIG_TEGRA_MMC
/*
* Routine: pin_mux_mmc
diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig
index 3e436a2..68ef82b 100644
--- a/board/toradex/colibri_t30/Kconfig
+++ b/board/toradex/colibri_t30/Kconfig
@@ -9,4 +9,22 @@
config SYS_CONFIG_NAME
default "colibri_t30"
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+source "board/toradex/common/Kconfig"
+
endif
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index e32362a..b68d3ca 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2014
+ * (C) Copyright 2014-2016
* Stefan Agner <stefan@agner.ch>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -14,6 +14,7 @@
#include <asm/io.h>
#include <i2c.h>
#include "pinmux-config-colibri_t30.h"
+#include "../common/tdx-common.h"
int arch_misc_init(void)
{
@@ -24,6 +25,20 @@
return 0;
}
+int checkboard(void)
+{
+ puts("Model: Toradex Colibri T30 1GB\n");
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig
index 2c3cb30..bf9bb01 100644
--- a/board/toradex/colibri_vf/Kconfig
+++ b/board/toradex/colibri_vf/Kconfig
@@ -15,4 +15,18 @@
config SYS_CONFIG_NAME
default "colibri_vf"
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_HAVE_NAND
+ default y
+
+config TDX_CFG_BLOCK_OFFSET
+ default "2048"
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+ default y
+
+source "board/toradex/common/Kconfig"
+
endif
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index c65ccb3..7b74eb7 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -15,13 +15,17 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <mmc.h>
+#include <fdt_support.h>
#include <fsl_esdhc.h>
+#include <jffs2/load_kernel.h>
#include <miiphy.h>
+#include <mtd_node.h>
#include <netdev.h>
#include <i2c.h>
#include <g_dnl.h>
#include <asm/gpio.h>
#include <usb.h>
+#include "../common/tdx-common.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -364,12 +368,18 @@
clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
CCM_CCGR10_NFC_CTRL_MASK);
-#ifdef CONFIG_CI_UDC
+#ifdef CONFIG_USB_EHCI_VF
setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
-#endif
-
-#ifdef CONFIG_USB_EHCI
setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
+
+ clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
+ ANADIG_PLL3_CTRL_POWERDOWN |
+ ANADIG_PLL3_CTRL_DIV_SELECT,
+ ANADIG_PLL3_CTRL_ENABLE);
+ clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
+ ANADIG_PLL7_CTRL_POWERDOWN |
+ ANADIG_PLL7_CTRL_DIV_SELECT,
+ ANADIG_PLL7_CTRL_ENABLE);
#endif
clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
@@ -418,7 +428,7 @@
CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
CCM_CSCDR2_NFC_EN);
clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
- CCM_CSCDR3_NFC_PRE_DIV(5));
+ CCM_CSCDR3_NFC_PRE_DIV(3));
clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
CCM_CSCMR2_RMII_CLK_SEL(2));
}
@@ -528,21 +538,22 @@
return 0;
}
-int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
{
- unsigned short usb_pid;
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ static struct node_info nodes[] = {
+ { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+ };
- put_unaligned(CONFIG_TRDX_VID, &dev->idVendor);
+ /* Update partition nodes using info from mtdparts env var */
+ puts(" Updating MTD partitions...\n");
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
- if (is_colibri_vf61())
- usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT;
- else
- usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT;
-
- put_unaligned(usb_pid, &dev->idProduct);
-
- return 0;
+ return ft_common_board_setup(blob, bd);
}
+#endif
#ifdef CONFIG_USB_EHCI_VF
int board_ehci_hcd_init(int port)
diff --git a/board/toradex/colibri_vf/imximage.cfg b/board/toradex/colibri_vf/imximage.cfg
index 8c52886..baab812 100644
--- a/board/toradex/colibri_vf/imximage.cfg
+++ b/board/toradex/colibri_vf/imximage.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/toradex/common/Kconfig b/board/toradex/common/Kconfig
new file mode 100644
index 0000000..b33baef
--- /dev/null
+++ b/board/toradex/common/Kconfig
@@ -0,0 +1,69 @@
+# Copyright (c) 2016 Toradex, Inc.
+# SPDX-License-Identifier: GPL-2.0+
+
+menuconfig TDX_CFG_BLOCK
+ bool "Enable Toradex config block support"
+ select OF_BOARD_SETUP
+ help
+ The Toradex config block stored production data on the on-module
+ flash device (NAND, NOR or eMMC). The area is normally preserved by
+ software and contains the serial number (out of which the MAC
+ address is generated) and the exact module type.
+
+# Helper config to determine the correct default location of the cfg block
+config TDX_HAVE_MMC
+ bool
+
+config TDX_HAVE_NAND
+ bool
+
+config TDX_HAVE_NOR
+ bool
+
+if TDX_CFG_BLOCK
+
+config TDX_CFG_BLOCK_IS_IN_MMC
+ bool
+ depends on TDX_HAVE_MMC
+ default y
+
+config TDX_CFG_BLOCK_IS_IN_NAND
+ bool
+ depends on TDX_HAVE_NAND
+ default y
+
+config TDX_CFG_BLOCK_IS_IN_NOR
+ bool
+ depends on TDX_HAVE_NOR
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ int "Toradex config block eMMC device ID"
+ depends on TDX_CFG_BLOCK_IS_IN_MMC
+
+config TDX_CFG_BLOCK_PART
+ int "Toradex config block eMMC partition ID"
+ depends on TDX_CFG_BLOCK_IS_IN_MMC
+
+config TDX_CFG_BLOCK_OFFSET
+ int "Toradex config block offset"
+ help
+ Specify the byte offset of the Toradex config block within the flash
+ device the config block is stored on.
+
+config TDX_CFG_BLOCK_OFFSET2
+ int "Toradex config block offset, second instance"
+ default 0
+ help
+ Specify the byte offset of the 2nd instance of the Toradex config block
+ within the flash device the config block is stored on.
+ Set to 0 on modules which have no 2nd instance.
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+ bool "Set the second Ethernet address"
+ help
+ For each serial number two Ethernet addresses are available for dual
+ Ethernet carrier boards. This options enables the code to set the
+ second Ethernet address as environment variable (eth1addr).
+
+endif
diff --git a/board/toradex/common/Makefile b/board/toradex/common/Makefile
new file mode 100644
index 0000000..d645f5a
--- /dev/null
+++ b/board/toradex/common/Makefile
@@ -0,0 +1,11 @@
+# Copyright (c) 2016 Toradex, Inc.
+# SPDX-License-Identifier: GPL-2.0+
+
+# Common for all Toradex modules
+ifeq ($(CONFIG_SPL_BUILD),y)
+# Necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-$(CONFIG_TDX_CFG_BLOCK) += tdx-cfg-block.o
+obj-y += tdx-common.o
+endif
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
new file mode 100644
index 0000000..0014ce8
--- /dev/null
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "tdx-cfg-block.h"
+
+#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6)
+#include <asm/arch/sys_proto.h>
+#else
+#define is_cpu_type(cpu) (0)
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+#include <asm/arch-pxa/pxa.h>
+#else
+#define cpu_is_pxa27x(cpu) (0)
+#endif
+#include <cli.h>
+#include <console.h>
+#include <flash.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TAG_VALID 0xcf01
+#define TAG_MAC 0x0000
+#define TAG_HW 0x0008
+#define TAG_INVALID 0xffff
+
+#define TAG_FLAG_VALID 0x1
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+#define TDX_CFG_BLOCK_MAX_SIZE 512
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+#define TDX_CFG_BLOCK_MAX_SIZE 64
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+#define TDX_CFG_BLOCK_MAX_SIZE 64
+#else
+#error Toradex config block location not set
+#endif
+
+struct toradex_tag {
+ u32 len:14;
+ u32 flags:2;
+ u32 id:16;
+};
+
+bool valid_cfgblock;
+struct toradex_hw tdx_hw_tag;
+struct toradex_eth_addr tdx_eth_addr;
+u32 tdx_serial;
+
+const char * const toradex_modules[] = {
+ [0] = "UNKNOWN MODULE",
+ [1] = "Colibri PXA270 312MHz",
+ [2] = "Colibri PXA270 520MHz",
+ [3] = "Colibri PXA320 806MHz",
+ [4] = "Colibri PXA300 208MHz",
+ [5] = "Colibri PXA310 624MHz",
+ [6] = "Colibri PXA320 806MHz IT",
+ [7] = "Colibri PXA300 208MHz XT",
+ [8] = "Colibri PXA270 312MHz",
+ [9] = "Colibri PXA270 520MHz",
+ [10] = "Colibri VF50 128MB", /* not currently on sale */
+ [11] = "Colibri VF61 256MB",
+ [12] = "Colibri VF61 256MB IT",
+ [13] = "Colibri VF50 128MB IT",
+ [14] = "Colibri iMX6 Solo 256MB",
+ [15] = "Colibri iMX6 DualLite 512MB",
+ [16] = "Colibri iMX6 Solo 256MB IT",
+ [17] = "Colibri iMX6 DualLite 512MB IT",
+ [18] = "UNKNOWN MODULE",
+ [19] = "UNKNOWN MODULE",
+ [20] = "Colibri T20 256MB",
+ [21] = "Colibri T20 512MB",
+ [22] = "Colibri T20 512MB IT",
+ [23] = "Colibri T30 1GB",
+ [24] = "Colibri T20 256MB IT",
+ [25] = "Apalis T30 2GB",
+ [26] = "Apalis T30 1GB",
+ [27] = "Apalis iMX6 Quad 1GB",
+ [28] = "Apalis iMX6 Quad 2GB IT",
+ [29] = "Apalis iMX6 Dual 512MB",
+ [30] = "Colibri T30 1GB IT",
+ [31] = "Apalis T30 1GB IT",
+ [32] = "Colibri iMX7 Solo 256MB",
+ [33] = "Colibri iMX7 Dual 512MB",
+ [34] = "Apalis TK1 2GB",
+ [35] = "Apalis iMX6 Dual 1GB IT",
+};
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
+static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
+{
+ struct mmc *mmc;
+ int dev = CONFIG_TDX_CFG_BLOCK_DEV;
+ int offset = CONFIG_TDX_CFG_BLOCK_OFFSET;
+ uint part = CONFIG_TDX_CFG_BLOCK_PART;
+ uint blk_start;
+ int ret = 0;
+
+ /* Read production parameter config block from eMMC */
+ mmc = find_mmc_device(dev);
+ if (!mmc) {
+ puts("No MMC card found\n");
+ ret = -ENODEV;
+ goto out;
+ }
+ if (part != mmc->block_dev.hwpart) {
+ if (blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part)) {
+ puts("MMC partition switch failed\n");
+ ret = -ENODEV;
+ goto out;
+ }
+ }
+ if (offset < 0)
+ offset += mmc->capacity;
+ blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
+
+ if (!write) {
+ /* Careful reads a whole block of 512 bytes into config_block */
+ if (blk_dread(mmc_get_blk_desc(mmc), blk_start, 1,
+ (unsigned char *)config_block) != 1) {
+ ret = -EIO;
+ goto out;
+ }
+ /* Flush cache after read */
+ flush_cache((ulong)(unsigned char *)config_block, 512);
+ } else {
+ /* Just writing one 512 byte block */
+ if (blk_dwrite(mmc_get_blk_desc(mmc), blk_start, 1,
+ (unsigned char *)config_block) != 1) {
+ ret = -EIO;
+ goto out;
+ }
+ }
+
+out:
+ /* Switch back to regular eMMC user partition */
+ blk_select_hwpart_devnum(IF_TYPE_MMC, 0, 0);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NAND
+static int read_tdx_cfg_block_from_nand(unsigned char *config_block)
+{
+ size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+
+ /* Read production parameter config block from NAND page */
+ return nand_read_skip_bad(nand_info[0], CONFIG_TDX_CFG_BLOCK_OFFSET,
+ &size, NULL, TDX_CFG_BLOCK_MAX_SIZE, config_block);
+}
+
+static int write_tdx_cfg_block_to_nand(unsigned char *config_block)
+{
+ size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+
+ /* Write production parameter config block to NAND page */
+ return nand_write_skip_bad(nand_info[0], CONFIG_TDX_CFG_BLOCK_OFFSET,
+ &size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
+ config_block, WITH_WR_VERIFY);
+}
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NOR
+static int read_tdx_cfg_block_from_nor(unsigned char *config_block)
+{
+ /* Read production parameter config block from NOR flash */
+ memcpy(config_block, (void *)CONFIG_TDX_CFG_BLOCK_OFFSET,
+ TDX_CFG_BLOCK_MAX_SIZE);
+ return 0;
+}
+
+static int write_tdx_cfg_block_to_nor(unsigned char *config_block)
+{
+ /* Write production parameter config block to NOR flash */
+ return flash_write((void *)config_block, CONFIG_TDX_CFG_BLOCK_OFFSET,
+ TDX_CFG_BLOCK_MAX_SIZE);
+}
+#endif
+
+int read_tdx_cfg_block(void)
+{
+ int ret = 0;
+ u8 *config_block = NULL;
+ struct toradex_tag *tag;
+ size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+ int offset;
+
+ /* Allocate RAM area for config block */
+ config_block = memalign(ARCH_DMA_MINALIGN, size);
+ if (!config_block) {
+ printf("Not enough malloc space available!\n");
+ return -ENOMEM;
+ }
+
+ memset(config_block, 0, size);
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+ ret = tdx_cfg_block_mmc_storage(config_block, 0);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+ ret = read_tdx_cfg_block_from_nand(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+ ret = read_tdx_cfg_block_from_nor(config_block);
+#else
+ ret = -EINVAL;
+#endif
+ if (ret)
+ goto out;
+
+ /* Expect a valid tag first */
+ tag = (struct toradex_tag *)config_block;
+ if (tag->flags != TAG_FLAG_VALID || tag->id != TAG_VALID) {
+ valid_cfgblock = false;
+ ret = -EINVAL;
+ goto out;
+ }
+ valid_cfgblock = true;
+ offset = 4;
+
+ while (offset < TDX_CFG_BLOCK_MAX_SIZE) {
+ tag = (struct toradex_tag *)(config_block + offset);
+ offset += 4;
+ if (tag->id == TAG_INVALID)
+ break;
+
+ if (tag->flags == TAG_FLAG_VALID) {
+ switch (tag->id) {
+ case TAG_MAC:
+ memcpy(&tdx_eth_addr, config_block + offset,
+ 6);
+
+ /* NIC part of MAC address is serial number */
+ tdx_serial = ntohl(tdx_eth_addr.nic) >> 8;
+ break;
+ case TAG_HW:
+ memcpy(&tdx_hw_tag, config_block + offset, 8);
+ break;
+ }
+ }
+
+ /* Get to next tag according to current tags length */
+ offset += tag->len * 4;
+ }
+
+ /* Cap product id to avoid issues with a yet unknown one */
+ if (tdx_hw_tag.prodid > (sizeof(toradex_modules) /
+ sizeof(toradex_modules[0])))
+ tdx_hw_tag.prodid = 0;
+
+out:
+ free(config_block);
+ return ret;
+}
+
+static int get_cfgblock_interactive(void)
+{
+ char message[CONFIG_SYS_CBSIZE];
+ char *soc;
+ char it = 'n';
+ int len;
+
+ if (cpu_is_pxa27x())
+ sprintf(message, "Is the module the 312 MHz version? [y/N] ");
+ else
+ sprintf(message, "Is the module an IT version? [y/N] ");
+
+ len = cli_readline(message);
+ it = console_buffer[0];
+
+ soc = getenv("soc");
+ if (!strcmp("mx6", soc)) {
+#ifdef CONFIG_MACH_TYPE
+ if (it == 'y' || it == 'Y')
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ tdx_hw_tag.prodid = APALIS_IMX6Q_IT;
+ else
+ tdx_hw_tag.prodid = APALIS_IMX6D_IT;
+ else
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ tdx_hw_tag.prodid = APALIS_IMX6Q;
+ else
+ tdx_hw_tag.prodid = APALIS_IMX6D;
+#else
+ if (it == 'y' || it == 'Y')
+ if (is_cpu_type(MXC_CPU_MX6DL))
+ tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
+ else
+ if (is_cpu_type(MXC_CPU_MX6DL))
+ tdx_hw_tag.prodid = COLIBRI_IMX6DL;
+ else
+ tdx_hw_tag.prodid = COLIBRI_IMX6S;
+#endif /* CONFIG_MACH_TYPE */
+ } else if (!strcmp("imx7d", soc)) {
+ tdx_hw_tag.prodid = COLIBRI_IMX7D;
+ } else if (!strcmp("imx7s", soc)) {
+ tdx_hw_tag.prodid = COLIBRI_IMX7S;
+ } else if (!strcmp("tegra20", soc)) {
+ if (it == 'y' || it == 'Y')
+ if (gd->ram_size == 0x10000000)
+ tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_T20_512MB_IT;
+ else
+ if (gd->ram_size == 0x10000000)
+ tdx_hw_tag.prodid = COLIBRI_T20_256MB;
+ else
+ tdx_hw_tag.prodid = COLIBRI_T20_512MB;
+ } else if (cpu_is_pxa27x()) {
+ if (it == 'y' || it == 'Y')
+ tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ;
+ else
+ tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
+#ifdef CONFIG_MACH_TYPE
+ } else if (!strcmp("tegra30", soc)) {
+ if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
+ if (it == 'y' || it == 'Y')
+ tdx_hw_tag.prodid = APALIS_T30_IT;
+ else
+ if (gd->ram_size == 0x40000000)
+ tdx_hw_tag.prodid = APALIS_T30_1GB;
+ else
+ tdx_hw_tag.prodid = APALIS_T30_2GB;
+ } else {
+ if (it == 'y' || it == 'Y')
+ tdx_hw_tag.prodid = COLIBRI_T30_IT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_T30;
+ }
+#endif /* CONFIG_MACH_TYPE */
+ } else if (!strcmp("tegra124", soc)) {
+ tdx_hw_tag.prodid = APALIS_TK1_2GB;
+ } else if (!strcmp("vf500", soc)) {
+ if (it == 'y' || it == 'Y')
+ tdx_hw_tag.prodid = COLIBRI_VF50_IT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_VF50;
+ } else if (!strcmp("vf610", soc)) {
+ if (it == 'y' || it == 'Y')
+ tdx_hw_tag.prodid = COLIBRI_VF61_IT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_VF61;
+ } else {
+ printf("Module type not detectable due to unknown SoC\n");
+ return -1;
+ }
+
+ while (len < 4) {
+ sprintf(message, "Enter the module version (e.g. V1.1B): V");
+ len = cli_readline(message);
+ }
+
+ tdx_hw_tag.ver_major = console_buffer[0] - '0';
+ tdx_hw_tag.ver_minor = console_buffer[2] - '0';
+ tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
+
+ if (cpu_is_pxa27x() && (tdx_hw_tag.ver_major == 1))
+ tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ -
+ COLIBRI_PXA270_V1_312MHZ);
+
+ while (len < 8) {
+ sprintf(message, "Enter module serial number: ");
+ len = cli_readline(message);
+ }
+
+ tdx_serial = simple_strtoul(console_buffer, NULL, 10);
+
+ return 0;
+}
+
+static int get_cfgblock_barcode(char *barcode)
+{
+ if (strlen(barcode) < 16) {
+ printf("Argument too short, barcode is 16 chars long\n");
+ return -1;
+ }
+
+ /* Get hardware information from the first 8 digits */
+ tdx_hw_tag.ver_major = barcode[4] - '0';
+ tdx_hw_tag.ver_minor = barcode[5] - '0';
+ tdx_hw_tag.ver_assembly = barcode[7] - '0';
+
+ barcode[4] = '\0';
+ tdx_hw_tag.prodid = simple_strtoul(barcode, NULL, 10);
+
+ /* Parse second part of the barcode (serial number */
+ barcode += 8;
+ tdx_serial = simple_strtoul(barcode, NULL, 10);
+
+ return 0;
+}
+
+static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u8 *config_block;
+ struct toradex_tag *tag;
+ size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+ int offset = 0;
+ int ret = CMD_RET_SUCCESS;
+ int err;
+
+ /* Allocate RAM area for config block */
+ config_block = memalign(ARCH_DMA_MINALIGN, size);
+ if (!config_block) {
+ printf("Not enough malloc space available!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ memset(config_block, 0xff, size);
+
+ read_tdx_cfg_block();
+ if (valid_cfgblock) {
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+ /*
+ * On NAND devices, recreation is only allowed if the page is
+ * empty (config block invalid...)
+ */
+ printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
+ CONFIG_TDX_CFG_BLOCK_OFFSET / nand_info[0]->erasesize);
+ goto out;
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+ /*
+ * On NOR devices, recreation is only allowed if the sector is
+ * empty and write protection is off (config block invalid...)
+ */
+ printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
+ CONFIG_TDX_CFG_BLOCK_OFFSET);
+ goto out;
+#else
+ char message[CONFIG_SYS_CBSIZE];
+ sprintf(message,
+ "A valid Toradex config block is present, still recreate? [y/N] ");
+
+ if (!cli_readline(message))
+ goto out;
+
+ if (console_buffer[0] != 'y' && console_buffer[0] != 'Y')
+ goto out;
+#endif
+ }
+
+ /* Parse new Toradex config block data... */
+ if (argc < 3)
+ err = get_cfgblock_interactive();
+ else
+ err = get_cfgblock_barcode(argv[2]);
+
+ if (err) {
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ /* Convert serial number to MAC address (the storage format) */
+ tdx_eth_addr.oui = htonl(0x00142dUL << 8);
+ tdx_eth_addr.nic = htonl(tdx_serial << 8);
+
+ /* Valid Tag */
+ tag = (struct toradex_tag *)config_block;
+ tag->id = TAG_VALID;
+ tag->flags = TAG_FLAG_VALID;
+ tag->len = 0;
+ offset += 4;
+
+ /* Product Tag */
+ tag = (struct toradex_tag *)(config_block + offset);
+ tag->id = TAG_HW;
+ tag->flags = TAG_FLAG_VALID;
+ tag->len = 2;
+ offset += 4;
+
+ memcpy(config_block + offset, &tdx_hw_tag, 8);
+ offset += 8;
+
+ /* MAC Tag */
+ tag = (struct toradex_tag *)(config_block + offset);
+ tag->id = TAG_MAC;
+ tag->flags = TAG_FLAG_VALID;
+ tag->len = 2;
+ offset += 4;
+
+ memcpy(config_block + offset, &tdx_eth_addr, 6);
+ offset += 6;
+ memset(config_block + offset, 0, 32 - offset);
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+ err = tdx_cfg_block_mmc_storage(config_block, 1);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+ err = write_tdx_cfg_block_to_nand(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+ err = write_tdx_cfg_block_to_nor(config_block);
+#else
+ err = -EINVAL;
+#endif
+ if (err) {
+ printf("Failed to write Toradex config block: %d\n", ret);
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ printf("Toradex config block successfully written\n");
+
+out:
+ free(config_block);
+ return ret;
+}
+
+static int do_cfgblock(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(argv[1], "create")) {
+ return do_cfgblock_create(cmdtp, flag, argc, argv);
+ } else if (!strcmp(argv[1], "reload")) {
+ ret = read_tdx_cfg_block();
+ if (ret) {
+ printf("Failed to reload Toradex config block: %d\n",
+ ret);
+ return CMD_RET_FAILURE;
+ }
+ return CMD_RET_SUCCESS;
+ }
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ cfgblock, 3, 0, do_cfgblock,
+ "Toradex config block handling commands",
+ "create [barcode] - (Re-)create Toradex config block\n"
+ "cfgblock reload - Reload Toradex config block from flash"
+);
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
new file mode 100644
index 0000000..fd7c362
--- /dev/null
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TDX_CFG_BLOCK_H
+#define _TDX_CFG_BLOCK_H
+
+#include "tdx-common.h"
+
+struct toradex_hw {
+ u16 ver_major;
+ u16 ver_minor;
+ u16 ver_assembly;
+ u16 prodid;
+};
+
+struct toradex_eth_addr {
+ u32 oui:24;
+ u32 nic:24;
+} __attribute__((__packed__));
+
+enum {
+ COLIBRI_PXA270_V1_312MHZ = 1,
+ COLIBRI_PXA270_V1_520MHZ,
+ COLIBRI_PXA320,
+ COLIBRI_PXA300,
+ COLIBRI_PXA310,
+ COLIBRI_PXA320_IT,
+ COLIBRI_PXA300_XT,
+ COLIBRI_PXA270_312MHZ,
+ COLIBRI_PXA270_520MHZ,
+ COLIBRI_VF50, /* not currently on sale */
+ COLIBRI_VF61,
+ COLIBRI_VF61_IT,
+ COLIBRI_VF50_IT,
+ COLIBRI_IMX6S,
+ COLIBRI_IMX6DL,
+ COLIBRI_IMX6S_IT,
+ COLIBRI_IMX6DL_IT,
+ COLIBRI_T20_256MB = 20,
+ COLIBRI_T20_512MB,
+ COLIBRI_T20_512MB_IT,
+ COLIBRI_T30,
+ COLIBRI_T20_256MB_IT,
+ APALIS_T30_2GB,
+ APALIS_T30_1GB,
+ APALIS_IMX6Q,
+ APALIS_IMX6Q_IT,
+ APALIS_IMX6D,
+ COLIBRI_T30_IT,
+ APALIS_T30_IT,
+ COLIBRI_IMX7S,
+ COLIBRI_IMX7D,
+ APALIS_TK1_2GB,
+ APALIS_IMX6D_IT,
+};
+
+extern const char * const toradex_modules[];
+extern bool valid_cfgblock;
+extern struct toradex_hw tdx_hw_tag;
+extern struct toradex_eth_addr tdx_eth_addr;
+extern u32 tdx_serial;
+
+int read_tdx_cfg_block(void);
+
+#endif /* _TDX_CFG_BLOCK_H */
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
new file mode 100644
index 0000000..2c6fc40
--- /dev/null
+++ b/board/toradex/common/tdx-common.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <g_dnl.h>
+#include <libfdt.h>
+
+#include "tdx-cfg-block.h"
+#include "tdx-common.h"
+
+#ifdef CONFIG_TDX_CFG_BLOCK
+static char tdx_serial_str[9];
+static char tdx_board_rev_str[6];
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+ /* Check validity */
+ if (!tdx_hw_tag.ver_major)
+ return 0;
+
+ return ((tdx_hw_tag.ver_major & 0xff) << 8) |
+ ((tdx_hw_tag.ver_minor & 0xf) << 4) |
+ ((tdx_hw_tag.ver_assembly & 0xf) + 0xa);
+}
+#endif /* CONFIG_TDX_CFG_BLOCK */
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ int array[8];
+ unsigned int serial = tdx_serial;
+ int i;
+
+ serialnr->low = 0;
+ serialnr->high = 0;
+
+ /* Check validity */
+ if (serial) {
+ /*
+ * Convert to Linux serial number format (hexadecimal coded
+ * decimal)
+ */
+ i = 7;
+ while (serial) {
+ array[i--] = serial % 10;
+ serial /= 10;
+ }
+ while (i >= 0)
+ array[i--] = 0;
+ serial = array[0];
+ for (i = 1; i < 8; i++) {
+ serial *= 16;
+ serial += array[i];
+ }
+
+ serialnr->low = serial;
+ }
+}
+#endif /* CONFIG_SERIAL_TAG */
+
+int show_board_info(void)
+{
+ unsigned char ethaddr[6];
+
+ if (read_tdx_cfg_block()) {
+ printf("Missing Toradex config block\n");
+ checkboard();
+ return 0;
+ }
+
+ /* board serial-number */
+ sprintf(tdx_serial_str, "%08u", tdx_serial);
+ sprintf(tdx_board_rev_str, "V%1d.%1d%c",
+ tdx_hw_tag.ver_major,
+ tdx_hw_tag.ver_minor,
+ (char)tdx_hw_tag.ver_assembly + 'A');
+
+ setenv("serial#", tdx_serial_str);
+
+ /*
+ * Check if environment contains a valid MAC address,
+ * set the one from config block if not
+ */
+ if (!eth_getenv_enetaddr("ethaddr", ethaddr))
+ eth_setenv_enetaddr("ethaddr", (u8 *)&tdx_eth_addr);
+
+#ifdef CONFIG_TDX_CFG_BLOCK_2ND_ETHADDR
+ if (!eth_getenv_enetaddr("eth1addr", ethaddr)) {
+ /*
+ * Secondary MAC address is allocated from block
+ * 0x100000 higher then the first MAC address
+ */
+ memcpy(ethaddr, &tdx_eth_addr, 6);
+ ethaddr[3] += 0x10;
+ eth_setenv_enetaddr("eth1addr", ethaddr);
+ }
+#endif
+
+ printf("Model: Toradex %s %s, Serial# %s\n",
+ toradex_modules[tdx_hw_tag.prodid],
+ tdx_board_rev_str,
+ tdx_serial_str);
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_GADGET_DOWNLOAD
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ unsigned short usb_pid;
+
+ usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + tdx_hw_tag.prodid;
+ put_unaligned(usb_pid, &dev->idProduct);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT)
+int ft_common_board_setup(void *blob, bd_t *bd)
+{
+ if (tdx_serial) {
+ fdt_setprop(blob, 0, "serial-number", tdx_serial_str,
+ strlen(tdx_serial_str) + 1);
+ }
+
+ if (tdx_hw_tag.ver_major) {
+ char prod_id[5];
+
+ sprintf(prod_id, "%04u", tdx_hw_tag.prodid);
+ fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5);
+
+ fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str,
+ strlen(tdx_board_rev_str) + 1);
+ }
+
+ return 0;
+}
+#endif
+
+#else /* CONFIG_TDX_CFG_BLOCK */
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+ return 0;
+}
+#endif /* CONFIG_REVISION_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+u32 get_board_serial(void)
+{
+ return 0;
+}
+#endif /* CONFIG_SERIAL_TAG */
+
+int ft_common_board_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+
+#endif /* CONFIG_TDX_CFG_BLOCK */
diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h
new file mode 100644
index 0000000..f8d78f0
--- /dev/null
+++ b/board/toradex/common/tdx-common.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TDX_COMMON_H
+#define _TDX_COMMON_H
+
+#define TORADEX_USB_PRODUCT_NUM_OFFSET 0x4000
+#define TDX_USB_VID 0x1B67
+
+int ft_common_board_setup(void *blob, bd_t *bd);
+
+#endif /* _TDX_COMMON_H */
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
index 8b82c34..fef9d2b 100644
--- a/board/tqc/tqm5200/tqm5200.c
+++ b/board/tqc/tqm5200/tqm5200.c
@@ -18,6 +18,7 @@
#include <asm/processor.h>
#include <libfdt.h>
#include <netdev.h>
+#include <video.h>
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
index 7fc57da..c8fc95d 100644
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@@ -13,7 +13,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/imx-common/mxc_i2c.h>
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
index e58b714..4db1a0b 100644
--- a/board/tqc/tqma6/tqma6_mba6.c
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -14,7 +14,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
diff --git a/board/tqc/tqma6/tqma6_wru4.c b/board/tqc/tqma6/tqma6_wru4.c
index c9a7ab7..2bbb614 100644
--- a/board/tqc/tqma6/tqma6_wru4.c
+++ b/board/tqc/tqma6/tqma6_wru4.c
@@ -16,7 +16,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/mxc_i2c.h>
diff --git a/board/udoo/README b/board/udoo/README
new file mode 100644
index 0000000..6fbcc59
--- /dev/null
+++ b/board/udoo/README
@@ -0,0 +1,21 @@
+How to use U-Boot on MX6Q/DL Udoo boards
+----------------------------------------
+
+- Build U-Boot for MX6Q/DL Udoo boards:
+
+$ make mrproper
+$ make udoo_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Insert the SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig
new file mode 100644
index 0000000..8f474df
--- /dev/null
+++ b/board/udoo/neo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_UDOO_NEO
+
+config SYS_VENDOR
+ default "udoo"
+
+config SYS_BOARD
+ default "neo"
+
+config SYS_CONFIG_NAME
+ default "udoo_neo"
+
+endif
diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS
new file mode 100644
index 0000000..743fe33
--- /dev/null
+++ b/board/udoo/neo/MAINTAINERS
@@ -0,0 +1,7 @@
+UDOO NEO BOARD
+M: Breno Lima <breno.lima@nxp.com>
+M: Francesco Montefoschi <francesco.montefoschi@udoo.org>
+S: Maintained
+F: board/udoo/neo/
+F: include/configs/udoo_neo.h
+F: configs/udoo_neo_defconfig
diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile
new file mode 100644
index 0000000..150cbc1
--- /dev/null
+++ b/board/udoo/neo/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 UDOO Team
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := neo.o
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
new file mode 100644
index 0000000..530c45f
--- /dev/null
+++ b/board/udoo/neo/neo.c
@@ -0,0 +1,596 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) Jasbir Matharu
+ * Copyright (C) UDOO Team
+ *
+ * Author: Breno Lima <breno.lima@nxp.com>
+ * Author: Francesco Montefoschi <francesco.monte@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ UDOO_NEO_TYPE_BASIC,
+ UDOO_NEO_TYPE_BASIC_KS,
+ UDOO_NEO_TYPE_FULL,
+ UDOO_NEO_TYPE_EXTENDED,
+};
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
+
+#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm)
+
+#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
+ MUX_MODE_SION)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+ .gp = IMX_GPIO_NR(1, 0),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+ .gp = IMX_GPIO_NR(1, 1),
+ },
+};
+#endif
+
+#ifdef CONFIG_POWER
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg, rev_id;
+
+ ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
+ if (ret)
+ return ret;
+
+ p = pmic_get("PFUZE3000");
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
+ pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+ /* disable Low Power Mode during standby mode */
+ pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
+ reg |= 0x1;
+ ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
+ if (ret)
+ return ret;
+
+ ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
+ if (ret)
+ return ret;
+
+ ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
+ if (ret)
+ return ret;
+
+ ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
+ if (ret)
+ return ret;
+
+ ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
+ if (ret)
+ return ret;
+
+ /* set SW1A standby voltage 0.975V */
+ pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®);
+ reg &= ~0x3f;
+ reg |= PFUZE3000_SW1AB_SETP(9750);
+ ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
+ if (ret)
+ return ret;
+
+ /* set SW1B standby voltage 0.975V */
+ pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®);
+ reg &= ~0x3f;
+ reg |= PFUZE3000_SW1AB_SETP(9750);
+ ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
+ if (ret)
+ return ret;
+
+ /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE3000_SW1ACONF, ®);
+ reg &= ~0xc0;
+ reg |= 0x40;
+ ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
+ if (ret)
+ return ret;
+
+ /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE3000_SW1BCONF, ®);
+ reg &= ~0xc0;
+ reg |= 0x40;
+ ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
+ if (ret)
+ return ret;
+
+ /* set VDD_ARM_IN to 1.350V */
+ pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®);
+ reg &= ~0x3f;
+ reg |= PFUZE3000_SW1AB_SETP(13500);
+ ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
+ if (ret)
+ return ret;
+
+ /* set VDD_SOC_IN to 1.350V */
+ pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
+ reg &= ~0x3f;
+ reg |= PFUZE3000_SW1AB_SETP(13500);
+ ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
+ if (ret)
+ return ret;
+
+ /* set DDR_1_5V to 1.350V */
+ pmic_reg_read(p, PFUZE3000_SW3VOLT, ®);
+ reg &= ~0x0f;
+ reg |= PFUZE3000_SW3_SETP(13500);
+ ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
+ if (ret)
+ return ret;
+
+ /* set VGEN2_1V5 to 1.5V */
+ pmic_reg_read(p, PFUZE3000_VLDO2CTL, ®);
+ reg &= ~0x0f;
+ reg |= PFUZE3000_VLDO_SETP(15000);
+ /* enable */
+ reg |= 0x10;
+ ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* CD pin */
+ MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* Power */
+ MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const phy_control_pads[] = {
+ /* 25MHz Ethernet PHY Clock */
+ MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
+ MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const board_recognition_pads[] = {
+ /*Connected to R184*/
+ MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
+ /*Connected to R185*/
+ MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
+};
+
+static iomux_v3_cfg_t const wdog_b_pad = {
+ MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const peri_3v3_pads[] = {
+ MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static int setup_fec(int fec_id)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int reg;
+
+ imx_iomux_v3_setup_multiple_pads(phy_control_pads,
+ ARRAY_SIZE(phy_control_pads));
+
+ /* Reset PHY */
+ gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
+ udelay(10000);
+ gpio_set_value(IMX_GPIO_NR(2, 1), 1);
+ udelay(100);
+
+ reg = readl(&anatop->pll_enet);
+ reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
+ writel(reg, &anatop->pll_enet);
+
+ return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+ setup_fec(CONFIG_FEC_ENET_DEV);
+
+ bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
+ if (!bus)
+ return -EINVAL;
+
+ phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
+ PHY_INTERFACE_MODE_RMII);
+ if (!phydev) {
+ free(bus);
+ return -EINVAL;
+ }
+
+ ret = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
+ if (ret) {
+ free(bus);
+ free(phydev);
+ return ret;
+ }
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ /*
+ * Because kernel set WDOG_B mux before pad with the commone pinctrl
+ * framwork now and wdog reset will be triggered once set WDOG_B mux
+ * with default pad setting, we set pad setting here to workaround this.
+ * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
+ * as GPIO mux firstly here to workaround it.
+ */
+ imx_iomux_v3_setup_pad(wdog_b_pad);
+
+ /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
+ imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
+ ARRAY_SIZE(peri_3v3_pads));
+
+ /* Active high for ncp692 */
+ gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+ return 0;
+}
+
+static int get_board_value(void)
+{
+ int r184, r185;
+
+ imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
+ ARRAY_SIZE(board_recognition_pads));
+
+ gpio_direction_input(IMX_GPIO_NR(4, 13));
+ gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+ r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
+ r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
+
+ /*
+ * Machine selection -
+ * Machine r184, r185
+ * ---------------------------------
+ * Basic 0 0
+ * Basic Ks 0 1
+ * Full 1 0
+ * Extended 1 1
+ */
+
+ return (r184 << 1) + r185;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !gpio_get_value(USDHC2_CD_GPIO);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ gpio_direction_input(USDHC2_CD_GPIO);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+static char *board_string(void)
+{
+ switch (get_board_value()) {
+ case UDOO_NEO_TYPE_BASIC:
+ return "BASIC";
+ case UDOO_NEO_TYPE_BASIC_KS:
+ return "BASICKS";
+ case UDOO_NEO_TYPE_FULL:
+ return "FULL";
+ case UDOO_NEO_TYPE_EXTENDED:
+ return "EXTENDED";
+ }
+ return "UNDEFINED";
+}
+
+int checkboard(void)
+{
+ printf("Board: UDOO Neo %s\n", board_string());
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", board_string());
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+#include <libfdt.h>
+#include <asm/arch/mx6-ddr.h>
+
+static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000028,
+ .dram_dqm1 = 0x00000028,
+ .dram_dqm2 = 0x00000028,
+ .dram_dqm3 = 0x00000028,
+ .dram_ras = 0x00000020,
+ .dram_cas = 0x00000020,
+ .dram_odt0 = 0x00000020,
+ .dram_odt1 = 0x00000020,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdqs0 = 0x00000028,
+ .dram_sdqs1 = 0x00000028,
+ .dram_sdqs2 = 0x00000028,
+ .dram_sdqs3 = 0x00000028,
+ .dram_reset = 0x00000020,
+};
+
+static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000020,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000028,
+ .grp_b1ds = 0x00000028,
+ .grp_ctlds = 0x00000020,
+ .grp_ddr_type = 0x000c0000,
+ .grp_b2ds = 0x00000028,
+ .grp_b3ds = 0x00000028,
+};
+
+static const struct mx6_mmdc_calibration neo_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x000E000B,
+ .p0_mpwldectrl1 = 0x000E0010,
+ .p0_mpdgctrl0 = 0x41600158,
+ .p0_mpdgctrl1 = 0x01500140,
+ .p0_mprddlctl = 0x3A383E3E,
+ .p0_mpwrdlctl = 0x3A383C38,
+};
+
+static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x001E0022,
+ .p0_mpwldectrl1 = 0x001C0019,
+ .p0_mpdgctrl0 = 0x41540150,
+ .p0_mpdgctrl1 = 0x01440138,
+ .p0_mprddlctl = 0x403E4644,
+ .p0_mpwrdlctl = 0x3C3A4038,
+};
+
+/* MT41K256M16 */
+static struct mx6_ddr3_cfg neo_mem_ddr = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* MT41K128M16 */
+static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
+ .mem_speed = 1600,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ int board = get_board_value();
+
+ struct mx6_ddr_sysinfo sysinfo = {
+ .dsize = 1, /* width of data bus: 1 = 32 bits */
+ .cs_density = 24,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ };
+
+ mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
+ mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
+ &neo_basic_mem_ddr);
+ else
+ mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+#endif
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index a574a2f..eb7ab65 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -11,7 +11,7 @@
#include <asm/arch/iomux.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/sata.h>
diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c
index 592e69b..f24d21e 100644
--- a/board/udoo/udoo_spl.c
+++ b/board/udoo/udoo_spl.c
@@ -10,7 +10,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/video.h>
diff --git a/board/varisys/cyrus/Kconfig b/board/varisys/cyrus/Kconfig
index d9ea7ef..c7b5253 100644
--- a/board/varisys/cyrus/Kconfig
+++ b/board/varisys/cyrus/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_CYRUS
+if TARGET_CYRUS_P5020 || TARGET_CYRUS_P5040
config SYS_BOARD
default "cyrus"
diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c
index 79c363c..74f4473 100644
--- a/board/varisys/cyrus/cyrus.c
+++ b/board/varisys/cyrus/cyrus.c
@@ -97,7 +97,7 @@
#endif
fdt_fixup_liodn(blob);
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
diff --git a/board/varisys/cyrus/eth.c b/board/varisys/cyrus/eth.c
index bcadc67..fc2192a 100644
--- a/board/varisys/cyrus/eth.c
+++ b/board/varisys/cyrus/eth.c
@@ -19,7 +19,7 @@
#define FIRST_PORT_ADDR 3
#define SECOND_PORT_ADDR 7
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
#define FIRST_PORT FM1_DTSEC5
#define SECOND_PORT FM2_DTSEC5
#else
@@ -83,7 +83,7 @@
fm_disable_port(i);
}
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
if (!IS_VALID_PORT(i))
fm_disable_port(i);
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index 27056e1..d3b1f15 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -39,6 +39,7 @@
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
#define DIP_S1 44
+#define MPCIE_SW 100
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
@@ -330,6 +331,11 @@
return 0;
}
+static struct module_pin_mux pcie_sw_pin_mux[] = {
+ {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
+ {-1},
+};
+
static struct module_pin_mux dip_pin_mux[] = {
{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
{OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
@@ -355,6 +361,18 @@
baltos_set_console();
}
}
+
+ /* turn power for the mPCIe slot */
+ configure_module_pin_mux(pcie_sw_pin_mux);
+ if (gpio_request(MPCIE_SW, "mpcie_sw")) {
+ printf("failed to export GPIO %d\n", MPCIE_SW);
+ return -ENODEV;
+ }
+ if (gpio_direction_output(MPCIE_SW, 1)) {
+ printf("failed to set GPIO %d direction\n", MPCIE_SW);
+ return -ENODEV;
+ }
+
setenv("board_name", model);
#endif
@@ -415,7 +433,6 @@
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
- __maybe_unused struct am335x_baseboard_id header;
/*
* Note here that we're using CPSW1 since that has a 1Gbit PHY while
diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h
index bcdb648..40ddd90 100644
--- a/board/vscom/baltos/board.h
+++ b/board/vscom/baltos/board.h
@@ -11,24 +11,6 @@
#ifndef _BOARD_H_
#define _BOARD_H_
-/*
- * TI AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR 3
-#define HDR_ETH_ALEN 6
-#define HDR_NAME_LEN 8
-
-struct am335x_baseboard_id {
- unsigned int magic;
- char name[HDR_NAME_LEN];
- char version[4];
- char serial[12];
- char config[32];
- char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
typedef struct _BSP_VS_HWPARAM // v1.0
{
uint32_t Magic;
@@ -41,37 +23,6 @@
uint8_t MAC3[6]; // WL1271 WLAN
} __attribute__ ((packed)) BSP_VS_HWPARAM;
-static inline int board_is_bone(struct am335x_baseboard_id *header)
-{
- return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
-{
- return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
-{
- return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
-}
-
-static inline int board_is_idk(struct am335x_baseboard_id *header)
-{
- return !strncmp(header->config, "SKU#02", 6);
-}
-
-static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
-{
- return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
-{
- return (board_is_gp_evm(header) &&
- strncmp("1.5", header->version, 3) <= 0);
-}
-
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
@@ -79,12 +30,6 @@
* is required on the board.
*/
void enable_uart0_pin_mux(void);
-void enable_uart1_pin_mux(void);
-void enable_uart2_pin_mux(void);
-void enable_uart3_pin_mux(void);
-void enable_uart4_pin_mux(void);
-void enable_uart5_pin_mux(void);
-void enable_i2c0_pin_mux(void);
void enable_i2c1_pin_mux(void);
void enable_board_pin_mux(void);
#endif
diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c
index 8783b25..94410ae 100644
--- a/board/vscom/baltos/mux.c
+++ b/board/vscom/baltos/mux.c
@@ -27,36 +27,6 @@
{-1},
};
-static struct module_pin_mux uart1_pin_mux[] = {
- {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
- {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart2_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
- {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart3_pin_mux[] = {
- {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
- {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart4_pin_mux[] = {
- {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
- {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart5_pin_mux[] = {
- {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
- {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
- {-1},
-};
-
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
@@ -68,14 +38,6 @@
{-1},
};
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
static struct module_pin_mux i2c1_pin_mux[] = {
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
@@ -144,36 +106,6 @@
configure_module_pin_mux(uart0_pin_mux);
}
-void enable_uart1_pin_mux(void)
-{
- configure_module_pin_mux(uart1_pin_mux);
-}
-
-void enable_uart2_pin_mux(void)
-{
- configure_module_pin_mux(uart2_pin_mux);
-}
-
-void enable_uart3_pin_mux(void)
-{
- configure_module_pin_mux(uart3_pin_mux);
-}
-
-void enable_uart4_pin_mux(void)
-{
- configure_module_pin_mux(uart4_pin_mux);
-}
-
-void enable_uart5_pin_mux(void)
-{
- configure_module_pin_mux(uart5_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
void enable_i2c1_pin_mux(void)
{
configure_module_pin_mux(i2c1_pin_mux);
@@ -181,7 +113,6 @@
void enable_board_pin_mux()
{
- /* Baltos */
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(gpio0_7_pin_mux);
configure_module_pin_mux(rgmii2_pin_mux);
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 085095c..a21a3d0 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/video.h>
@@ -188,7 +188,7 @@
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
.refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
+ .refr = 3, /* 4 refresh commands per refresh cycle */
};
static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
@@ -231,7 +231,7 @@
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
.refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
+ .refr = 3, /* 4 refresh commands per refresh cycle */
};
/* DDR 32bit 512MB */
@@ -250,7 +250,7 @@
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
.refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
+ .refr = 3, /* 4 refresh commands per refresh cycle */
};
static void ccgr_init(void)
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 1de1e0b..2c9dc8b 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -189,6 +189,39 @@
return 0;
}
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ ar8031_phy_fixup(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
#if defined(CONFIG_VIDEO_IPUV3)
struct i2c_pads_info mx6q_i2c2_pad_info = {
.scl = {
@@ -409,11 +442,13 @@
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#if defined(CONFIG_VIDEO_IPUV3)
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
if (is_mx6dq())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+#endif
return 0;
}
diff --git a/board/warp/imximage.cfg b/board/warp/imximage.cfg
index 7b1d6b7..771dbb3 100644
--- a/board/warp/imximage.cfg
+++ b/board/warp/imximage.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/warp7/imximage.cfg b/board/warp7/imximage.cfg
index e7b6d30..5b42793 100644
--- a/board/warp7/imximage.cfg
+++ b/board/warp7/imximage.cfg
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
index da9afb4..df8e9da 100644
--- a/board/warp7/warp7.c
+++ b/board/warp7/warp7.c
@@ -19,6 +19,7 @@
#include <mmc.h>
#include <asm/arch/crm_regs.h>
#include <usb.h>
+#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../freescale/common/pfuze.h"
@@ -138,6 +139,19 @@
}
#endif
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#ifdef CONFIG_USB_ETHER
+ ret = usb_eth_initialize(bis);
+ if (ret < 0)
+ printf("Error %d registering USB ether.\n", ret);
+#endif
+
+ return ret;
+}
+
int board_init(void)
{
/* address of boot parameters */
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
index 3da61a4..972e74e 100644
--- a/board/woodburn/woodburn.c
+++ b/board/woodburn/woodburn.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index 65d321a..db1f029f 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -6,9 +6,9 @@
#
obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
-obj-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
+obj-$(CONFIG_ARCH_MPC8572) += fsl_8xxx_clk.o
obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
-obj-$(CONFIG_P2020) += fsl_8xxx_clk.o
+obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o
obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
obj-$(CONFIG_NAND_ACTL) += actl_nand.o
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
index 2a604d4..e102b0c 100644
--- a/board/xes/common/fsl_8xxx_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -22,7 +22,7 @@
if (in_be32(&gur->gpporcr) & 0x10000)
return 66666666;
else
-#ifdef CONFIG_P2020
+#ifdef CONFIG_ARCH_P2020
return 100000000;
#else
return 50000000;
@@ -42,7 +42,7 @@
if (ddr_ratio == 0x7)
return get_board_sys_clk(dummy);
-#ifdef CONFIG_P2020
+#ifdef CONFIG_ARCH_P2020
if (in_be32(&gur->gpporcr) & 0x20000)
return 66666666;
else
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index 510f638..6237571 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -55,7 +55,7 @@
} else {
printf("PCI1: disabled\n");
}
-#elif defined CONFIG_MPC8548
+#elif defined CONFIG_ARCH_MPC8548
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* PCI1 not present on MPC8572 */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 183f642..5cd9bbf 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -19,7 +19,10 @@
static xilinx_desc fpga;
/* It can be done differently */
+static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
+static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
@@ -37,9 +40,18 @@
idcode = zynq_slcr_get_idcode();
switch (idcode) {
+ case XILINX_ZYNQ_7007S:
+ fpga = fpga007s;
+ break;
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
+ case XILINX_ZYNQ_7012S:
+ fpga = fpga012s;
+ break;
+ case XILINX_ZYNQ_7014S:
+ fpga = fpga014s;
+ break;
case XILINX_ZYNQ_7015:
fpga = fpga015;
break;
@@ -112,121 +124,15 @@
}
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
- const u32 *cell, int n)
-{
- int i = 0, b, banks;
- int parent_offset = fdt_parent_offset(fdt, nodeoffset);
- int address_cells = fdt_address_cells(fdt, parent_offset);
- int size_cells = fdt_size_cells(fdt, parent_offset);
- char *p = buf;
- u64 val;
- u64 vals;
-
- debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
- __func__, address_cells, size_cells, buf, cell);
-
- /* Check memory bank setup */
- banks = n % (address_cells + size_cells);
- if (banks)
- panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
- n, address_cells, size_cells);
-
- banks = n / (address_cells + size_cells);
-
- for (b = 0; b < banks; b++) {
- debug("%s: Bank #%d:\n", __func__, b);
- if (address_cells == 2) {
- val = cell[i + 1];
- val <<= 32;
- val |= cell[i];
- val = fdt64_to_cpu(val);
- debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
- __func__, val, p, &cell[i]);
- *(phys_addr_t *)p = val;
- } else {
- debug("%s: addr32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
- *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
- }
- p += sizeof(phys_addr_t);
- i += address_cells;
-
- debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
- sizeof(phys_addr_t));
-
- if (size_cells == 2) {
- vals = cell[i + 1];
- vals <<= 32;
- vals |= cell[i];
- vals = fdt64_to_cpu(vals);
-
- debug("%s: size64=%llx, ptr=%p, cell=%p\n",
- __func__, vals, p, &cell[i]);
- *(phys_size_t *)p = vals;
- } else {
- debug("%s: size32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
- *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
- }
- p += sizeof(phys_size_t);
- i += size_cells;
-
- debug("%s: ps=%p, i=%x, size=%zu\n",
- __func__, p, i, sizeof(phys_size_t));
- }
-
- /* Return the first address size */
- return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
-
void dram_init_banksize(void)
{
- int bank;
-
- memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
-
- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- debug("Bank #%d: start %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].start);
- debug("Bank #%d: size %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].size);
- }
+ fdtdec_setup_memory_banksize();
}
int dram_init(void)
{
- int node, len;
- const void *blob = gd->fdt_blob;
- const u32 *cell;
-
- memset(&tmp, 0, sizeof(tmp));
-
- /* find or create "/memory" node. */
- node = fdt_subnode_offset(blob, 0, "memory");
- if (node < 0) {
- printf("%s: Can't get memory node\n", __func__);
- return node;
- }
-
- /* Get pointer to cells and lenght of it */
- cell = fdt_getprop(blob, node, "reg", &len);
- if (!cell) {
- printf("%s: Can't get reg property\n", __func__);
- return -1;
- }
-
- gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
-
- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
zynq_ddrc_init();
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 90f00c6..9d69d65 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -7,7 +7,7 @@
obj-y := zynqmp.o
-hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME))
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
$(hw-platform-y)/psu_init_gpl.o)
@@ -27,3 +27,6 @@
# To include xil_io.h
CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)
+
+# To suppress "warning: cast to pointer from integer of different size"
+CFLAGS_psu_init_gpl.o += -Wno-int-to-pointer-cast
diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
index 57ca4ad..6bbc000 100644
--- a/board/xilinx/zynqmp/xil_io.h
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -7,6 +7,7 @@
/* FIXME remove this when vivado is fixed */
#include <asm/io.h>
+#include <common.h>
#define xil_printf(...)
@@ -32,4 +33,12 @@
return readl(addr);
}
+void mask_delay(u32 delay);
+void usleep(u32 sleep)
+{
+ udelay(sleep);
+}
+int mask_poll(u32 add, u32 mask);
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+
#endif /* XIL_IO_H */
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 0c5d997..4e5871b 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -16,14 +16,125 @@
#include <asm/io.h>
#include <usb.h>
#include <dwc3-uboot.h>
+#include <zynqmppl.h>
#include <i2c.h>
+#include <g_dnl.h>
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
+ !defined(CONFIG_SPL_BUILD)
+static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
+
+static const struct {
+ uint32_t id;
+ char *name;
+} zynqmp_devices[] = {
+ {
+ .id = 0x10,
+ .name = "3eg",
+ },
+ {
+ .id = 0x11,
+ .name = "2eg",
+ },
+ {
+ .id = 0x20,
+ .name = "5ev",
+ },
+ {
+ .id = 0x21,
+ .name = "4ev",
+ },
+ {
+ .id = 0x30,
+ .name = "7ev",
+ },
+ {
+ .id = 0x38,
+ .name = "9eg",
+ },
+ {
+ .id = 0x39,
+ .name = "6eg",
+ },
+ {
+ .id = 0x40,
+ .name = "11eg",
+ },
+ {
+ .id = 0x50,
+ .name = "15eg",
+ },
+ {
+ .id = 0x58,
+ .name = "19eg",
+ },
+ {
+ .id = 0x59,
+ .name = "17eg",
+ },
+};
+
+static int chip_id(void)
+{
+ struct pt_regs regs;
+ regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
+ regs.regs[1] = 0;
+ regs.regs[2] = 0;
+ regs.regs[3] = 0;
+
+ smc_call(®s);
+
+ /*
+ * SMC returns:
+ * regs[0][31:0] = status of the operation
+ * regs[0][63:32] = CSU.IDCODE register
+ * regs[1][31:0] = CSU.version register
+ */
+ regs.regs[0] = upper_32_bits(regs.regs[0]);
+ regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
+ ZYNQMP_CSU_IDCODE_SVD_MASK;
+ regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
+
+ return regs.regs[0];
+}
+
+static char *zynqmp_get_silicon_idcode_name(void)
+{
+ uint32_t i, id;
+
+ id = chip_id();
+ for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
+ if (zynqmp_devices[i].id == id)
+ return zynqmp_devices[i].name;
+ }
+ return "unknown";
+}
+#endif
+
+#define ZYNQMP_VERSION_SIZE 9
+
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
+ !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
+ defined(CONFIG_SPL_BUILD))
+ if (current_el() != 3) {
+ static char version[ZYNQMP_VERSION_SIZE];
+
+ strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
+ zynqmppl.name = strncat(version,
+ zynqmp_get_silicon_idcode_name(),
+ ZYNQMP_VERSION_SIZE);
+ printf("Chip ID:\t%s\n", zynqmppl.name);
+ fpga_init();
+ fpga_add(fpga_xilinx, &zynqmppl);
+ }
+#endif
+
return 0;
}
@@ -69,121 +180,15 @@
}
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
- const u32 *cell, int n)
-{
- int i = 0, b, banks;
- int parent_offset = fdt_parent_offset(fdt, nodeoffset);
- int address_cells = fdt_address_cells(fdt, parent_offset);
- int size_cells = fdt_size_cells(fdt, parent_offset);
- char *p = buf;
- u64 val;
- u64 vals;
-
- debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
- __func__, address_cells, size_cells, buf, cell);
-
- /* Check memory bank setup */
- banks = n % (address_cells + size_cells);
- if (banks)
- panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
- n, address_cells, size_cells);
-
- banks = n / (address_cells + size_cells);
-
- for (b = 0; b < banks; b++) {
- debug("%s: Bank #%d:\n", __func__, b);
- if (address_cells == 2) {
- val = cell[i + 1];
- val <<= 32;
- val |= cell[i];
- val = fdt64_to_cpu(val);
- debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
- __func__, val, p, &cell[i]);
- *(phys_addr_t *)p = val;
- } else {
- debug("%s: addr32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
- *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
- }
- p += sizeof(phys_addr_t);
- i += address_cells;
-
- debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
- sizeof(phys_addr_t));
-
- if (size_cells == 2) {
- vals = cell[i + 1];
- vals <<= 32;
- vals |= cell[i];
- vals = fdt64_to_cpu(vals);
-
- debug("%s: size64=%llx, ptr=%p, cell=%p\n",
- __func__, vals, p, &cell[i]);
- *(phys_size_t *)p = vals;
- } else {
- debug("%s: size32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
- *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
- }
- p += sizeof(phys_size_t);
- i += size_cells;
-
- debug("%s: ps=%p, i=%x, size=%zu\n",
- __func__, p, i, sizeof(phys_size_t));
- }
-
- /* Return the first address size */
- return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
-
void dram_init_banksize(void)
{
- int bank;
-
- memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
-
- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- debug("Bank #%d: start %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].start);
- debug("Bank #%d: size %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].size);
- }
+ fdtdec_setup_memory_banksize();
}
int dram_init(void)
{
- int node, len;
- const void *blob = gd->fdt_blob;
- const u32 *cell;
-
- memset(&tmp, 0, sizeof(tmp));
-
- /* find or create "/memory" node. */
- node = fdt_subnode_offset(blob, 0, "memory");
- if (node < 0) {
- printf("%s: Can't get memory node\n", __func__);
- return node;
- }
-
- /* Get pointer to cells and lenght of it */
- cell = fdt_getprop(blob, node, "reg", &len);
- if (!cell) {
- printf("%s: Can't get reg property\n", __func__);
- return -1;
- }
-
- gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
-
- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
return 0;
}
@@ -200,17 +205,6 @@
{
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void scsi_init(void)
-{
-#if defined(CONFIG_SATA_CEVA)
- init_sata(0);
-#endif
- ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
- scsi_scan(1);
-}
-#endif
-
int board_late_init(void)
{
u32 reg = 0;
@@ -224,10 +218,17 @@
}
reg = readl(&crlapb_base->boot_mode);
+ if (reg >> BOOT_MODE_ALT_SHIFT)
+ reg >>= BOOT_MODE_ALT_SHIFT;
+
bootmode = reg & BOOT_MODES_MASK;
puts("Bootmode: ");
switch (bootmode) {
+ case USB_MODE:
+ puts("USB_MODE\n");
+ mode = "usb";
+ break;
case JTAG_MODE:
puts("JTAG_MODE\n");
mode = "pxe dhcp";
@@ -245,6 +246,9 @@
puts("SD_MODE\n");
mode = "mmc0";
break;
+ case SD1_LSHFT_MODE:
+ puts("LVL_SHFT_");
+ /* fall through */
case SD_MODE1:
puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
@@ -283,22 +287,42 @@
}
#ifdef CONFIG_USB_DWC3
-static struct dwc3_device dwc3_device_data = {
+static struct dwc3_device dwc3_device_data0 = {
.maximum_speed = USB_SPEED_HIGH,
.base = ZYNQMP_USB0_XHCI_BASEADDR,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
};
-int usb_gadget_handle_interrupts(void)
+static struct dwc3_device dwc3_device_data1 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = ZYNQMP_USB1_XHCI_BASEADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 1,
+};
+
+int usb_gadget_handle_interrupts(int index)
{
- dwc3_uboot_handle_interrupt(0);
+ dwc3_uboot_handle_interrupt(index);
return 0;
}
int board_usb_init(int index, enum usb_init_type init)
{
- return dwc3_uboot_init(&dwc3_device_data);
+ debug("%s: index %x\n", __func__, index);
+
+#if defined(CONFIG_USB_GADGET_DOWNLOAD)
+ g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
+#endif
+
+ switch (index) {
+ case 0:
+ return dwc3_uboot_init(&dwc3_device_data0);
+ case 1:
+ return dwc3_uboot_init(&dwc3_device_data1);
+ };
+
+ return -1;
}
int board_usb_cleanup(int index, enum usb_init_type init)
@@ -307,8 +331,3 @@
return 0;
}
#endif
-
-void reset_misc(void)
-{
- psci_system_reset(true);
-}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 3610ab6..f7dd159 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -181,6 +181,34 @@
help
Boot an EFI image from memory.
+config CMD_BOOTEFI_HELLO_COMPILE
+ bool "Compile a standard EFI hello world binary for testing"
+ depends on CMD_BOOTEFI && (ARM || X86)
+ default y
+ help
+ This compiles a standard EFI hello world application with U-Boot so
+ that it can be used with the test/py testing framework. This is useful
+ for testing that EFI is working at a basic level, and for bringing
+ up EFI support on a new architecture.
+
+ No additional space will be required in the resulting U-Boot binary
+ when this option is enabled.
+
+config CMD_BOOTEFI_HELLO
+ bool "Allow booting a standard EFI hello world for testing"
+ depends on CMD_BOOTEFI_HELLO_COMPILE
+ help
+ This adds a standard EFI hello world application to U-Boot so that
+ it can be used with the 'bootefi hello' command. This is useful
+ for testing that EFI is working at a basic level, and for bringing
+ up EFI support on a new architecture.
+
+config CMD_BOOTMENU
+ bool "bootmenu"
+ select MENU
+ help
+ Add an ANSI terminal boot menu command.
+
config CMD_ELF
bool "bootelf, bootvx"
default y
@@ -281,7 +309,7 @@
bool "md, mm, nm, mw, cp, cmp, base, loop"
default y
help
- Memeory commands.
+ Memory commands.
md - memory display
mm - memory modify (auto-incrementing address)
nm - memory modify (constant address)
@@ -289,7 +317,7 @@
cp - memory copy
cmp - memory compare
base - print or set address offset
- loop - initinite loop on address range
+ loop - initialize loop on address range
config CMD_CRC32
bool "crc32"
@@ -413,6 +441,7 @@
config CMD_DFU
bool "dfu"
+ select USB_FUNCTION_DFU
help
Enables the command "dfu" which is used to have U-Boot create a DFU
class device via USB.
@@ -504,6 +533,12 @@
help
Boot image via network using DHCP/TFTP protocol
+config CMD_PXE
+ bool "pxe"
+ select MENU
+ help
+ Boot image via network using PXE protocol
+
config CMD_NFS
bool "nfs"
default y
@@ -558,6 +593,15 @@
help
Show AMBA Plug-n-Play information on startup.
+config CMD_BKOPS_ENABLE
+ bool "mmc bkops enable"
+ depends on CMD_MMC
+ default n
+ help
+ Enable command for setting manual background operations handshake
+ on a eMMC device. The feature is optionally available on eMMC devices
+ conforming to standard >= 4.41.
+
config CMD_BLOCK_CACHE
bool "blkcache - control and stats for block cache"
depends on BLOCK_CACHE
@@ -618,6 +662,9 @@
This provides access to the QEMU firmware interface. The main
feature is to allow easy loading of files passed to qemu-system
via -kernel / -initrd
+
+source "cmd/mvebu/Kconfig"
+
endmenu
config CMD_BOOTSTAGE
@@ -685,6 +732,19 @@
endmenu
+menu "Firmware commands"
+config CMD_CROS_EC
+ bool "Enable crosec command"
+ depends on CROS_EC
+ default y
+ help
+ Enable command-line access to the Chrome OS EC (Embedded
+ Controller). This provides the 'crosec' command which has
+ a number of sub-commands for performing EC tasks such as
+ updating its flash, accessing a small saved context area
+ and talking to the I2C bus behind the EC (if there is one).
+endmenu
+
menu "Filesystem commands"
config CMD_EXT2
bool "ext2 command support"
@@ -714,4 +774,16 @@
fs types.
endmenu
+config CMD_UBI
+ tristate "Enable UBI - Unsorted block images commands"
+ select CRC32
+ select MTD_UBI
+ help
+ UBI is a software layer above MTD layer which admits use of LVM-like
+ logical volumes on top of MTD devices, hides some complexities of
+ flash chips like wear and bad blocks and provides some other useful
+ capabilities. Please, consult the MTD web site for more details
+ (www.linux-mtd.infradead.org). Activate this option if you want
+ to use U-Boot UBI commands.
+
endmenu
diff --git a/cmd/Makefile b/cmd/Makefile
index 277ddef..8af239e 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -129,6 +129,7 @@
obj-$(CONFIG_HUSH_PARSER) += test.o
obj-$(CONFIG_CMD_TPM) += tpm.o
obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
+obj-$(CONFIG_CMD_CROS_EC) += cros_ec.o
obj-$(CONFIG_CMD_TSI148) += tsi148.o
obj-$(CONFIG_CMD_UBI) += ubi.o
obj-$(CONFIG_CMD_UBIFS) += ubifs.o
@@ -163,3 +164,5 @@
# core command
obj-y += nvedit.o
+
+obj-$(CONFIG_ARCH_MVEBU) += mvebu/
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 21fe42c..97a0fc9 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -15,6 +15,8 @@
#include <libfdt_env.h>
#include <memalign.h>
#include <asm/global_data.h>
+#include <asm-generic/sections.h>
+#include <linux/linkage.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -52,7 +54,7 @@
}
};
-static efi_status_t bootefi_open_dp(void *handle, efi_guid_t *protocol,
+static efi_status_t EFIAPI bootefi_open_dp(void *handle, efi_guid_t *protocol,
void **protocol_interface, void *agent_handle,
void *controller_handle, uint32_t attributes)
{
@@ -139,13 +141,26 @@
return new_fdt;
}
+#ifdef CONFIG_ARM64
+static unsigned long efi_run_in_el2(ulong (*entry)(void *image_handle,
+ struct efi_system_table *st), void *image_handle,
+ struct efi_system_table *st)
+{
+ /* Enable caches again */
+ dcache_enable();
+
+ return entry(image_handle, st);
+}
+#endif
+
/*
* Load an EFI payload into a newly allocated piece of memory, register all
* EFI objects it would want to access and jump to it.
*/
static unsigned long do_bootefi_exec(void *efi, void *fdt)
{
- ulong (*entry)(void *image_handle, struct efi_system_table *st);
+ ulong (*entry)(void *image_handle, struct efi_system_table *st)
+ asmlinkage;
ulong fdt_pages, fdt_size, fdt_start, fdt_end;
bootm_headers_t img = { 0 };
@@ -204,7 +219,16 @@
if (!memcmp(bootefi_device_path[0].str, "N\0e\0t", 6))
loaded_image_info.device_handle = nethandle;
+ else
+ loaded_image_info.device_handle = bootefi_device_path;
#endif
+#ifdef CONFIG_GENERATE_SMBIOS_TABLE
+ efi_smbios_register();
+#endif
+
+ /* Initialize EFI runtime services */
+ efi_reset_system_init();
+ efi_get_time_init();
/* Call our payload! */
debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
@@ -214,6 +238,22 @@
return status == EFI_SUCCESS ? 0 : -EINVAL;
}
+#ifdef CONFIG_ARM64
+ /* On AArch64 we need to make sure we call our payload in < EL3 */
+ if (current_el() == 3) {
+ smp_kick_all_cpus();
+ dcache_disable(); /* flush cache before switch to EL2 */
+
+ /* Move into EL2 and keep running there */
+ armv8_switch_to_el2((ulong)entry, (ulong)&loaded_image_info,
+ (ulong)&systab, (ulong)efi_run_in_el2,
+ ES_TO_AARCH64);
+
+ /* Should never reach here, efi exits with longjmp */
+ while (1) { }
+ }
+#endif
+
return entry(&loaded_image_info, &systab);
}
@@ -227,16 +267,26 @@
if (argc < 2)
return CMD_RET_USAGE;
- saddr = argv[1];
+#ifdef CONFIG_CMD_BOOTEFI_HELLO
+ if (!strcmp(argv[1], "hello")) {
+ ulong size = __efi_hello_world_end - __efi_hello_world_begin;
- addr = simple_strtoul(saddr, NULL, 16);
+ addr = CONFIG_SYS_LOAD_ADDR;
+ memcpy((char *)addr, __efi_hello_world_begin, size);
+ } else
+#endif
+ {
+ saddr = argv[1];
- if (argc > 2) {
- sfdt = argv[2];
- fdt_addr = simple_strtoul(sfdt, NULL, 16);
+ addr = simple_strtoul(saddr, NULL, 16);
+
+ if (argc > 2) {
+ sfdt = argv[2];
+ fdt_addr = simple_strtoul(sfdt, NULL, 16);
+ }
}
- printf("## Starting EFI application at 0x%08lx ...\n", addr);
+ printf("## Starting EFI application at %08lx ...\n", addr);
r = do_bootefi_exec((void *)addr, (void*)fdt_addr);
printf("## Application terminated, r = %d\n", r);
@@ -251,7 +301,12 @@
"<image address> [fdt address]\n"
" - boot EFI payload stored at address <image address>.\n"
" If specified, the device tree located at <fdt address> gets\n"
- " exposed as EFI configuration table.\n";
+ " exposed as EFI configuration table.\n"
+#ifdef CONFIG_CMD_BOOTEFI_HELLO
+ "hello\n"
+ " - boot a sample Hello World application stored within U-Boot"
+#endif
+ ;
#endif
U_BOOT_CMD(
diff --git a/cmd/bootm.c b/cmd/bootm.c
index e02a1c5..083f3d1 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -162,7 +162,7 @@
#endif
#if defined(CONFIG_FIT)
"\t\nFor the new multi component uImage format (FIT) addresses\n"
- "\tmust be extened to include component or configuration unit name:\n"
+ "\tmust be extended to include component or configuration unit name:\n"
"\taddr:<subimg_uname> - direct component image specification\n"
"\taddr#<conf_uname> - configuration specification\n"
"\tUse iminfo command to get the list of existing component\n"
diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c
new file mode 100644
index 0000000..9d42f87
--- /dev/null
+++ b/cmd/cros_ec.c
@@ -0,0 +1,388 @@
+/*
+ * Chromium OS cros_ec driver
+ *
+ * Copyright (c) 2016 The Chromium OS Authors.
+ * Copyright (c) 2016 National Instruments Corp
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cros_ec.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+
+/* Note: depends on enum ec_current_image */
+static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Decode a flash region parameter
+ *
+ * @param argc Number of params remaining
+ * @param argv List of remaining parameters
+ * @return flash region (EC_FLASH_REGION_...) or -1 on error
+ */
+static int cros_ec_decode_region(int argc, char * const argv[])
+{
+ if (argc > 0) {
+ if (0 == strcmp(*argv, "rw"))
+ return EC_FLASH_REGION_RW;
+ else if (0 == strcmp(*argv, "ro"))
+ return EC_FLASH_REGION_RO;
+
+ debug("%s: Invalid region '%s'\n", __func__, *argv);
+ } else {
+ debug("%s: Missing region parameter\n", __func__);
+ }
+
+ return -1;
+}
+
+/**
+ * Perform a flash read or write command
+ *
+ * @param dev CROS-EC device to read/write
+ * @param is_write 1 do to a write, 0 to do a read
+ * @param argc Number of arguments
+ * @param argv Arguments (2 is region, 3 is address)
+ * @return 0 for ok, 1 for a usage error or -ve for ec command error
+ * (negative EC_RES_...)
+ */
+static int do_read_write(struct cros_ec_dev *dev, int is_write, int argc,
+ char * const argv[])
+{
+ uint32_t offset, size = -1U, region_size;
+ unsigned long addr;
+ char *endp;
+ int region;
+ int ret;
+
+ region = cros_ec_decode_region(argc - 2, argv + 2);
+ if (region == -1)
+ return 1;
+ if (argc < 4)
+ return 1;
+ addr = simple_strtoul(argv[3], &endp, 16);
+ if (*argv[3] == 0 || *endp != 0)
+ return 1;
+ if (argc > 4) {
+ size = simple_strtoul(argv[4], &endp, 16);
+ if (*argv[4] == 0 || *endp != 0)
+ return 1;
+ }
+
+ ret = cros_ec_flash_offset(dev, region, &offset, ®ion_size);
+ if (ret) {
+ debug("%s: Could not read region info\n", __func__);
+ return ret;
+ }
+ if (size == -1U)
+ size = region_size;
+
+ ret = is_write ?
+ cros_ec_flash_write(dev, (uint8_t *)addr, offset, size) :
+ cros_ec_flash_read(dev, (uint8_t *)addr, offset, size);
+ if (ret) {
+ debug("%s: Could not %s region\n", __func__,
+ is_write ? "write" : "read");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct cros_ec_dev *dev;
+ struct udevice *udev;
+ const char *cmd;
+ int ret = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ cmd = argv[1];
+ if (0 == strcmp("init", cmd)) {
+ /* Remove any existing device */
+ ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev);
+ if (!ret)
+ device_remove(udev);
+ ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
+ if (ret) {
+ printf("Could not init cros_ec device (err %d)\n", ret);
+ return 1;
+ }
+ return 0;
+ }
+
+ ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
+ if (ret) {
+ printf("Cannot get cros-ec device (err=%d)\n", ret);
+ return 1;
+ }
+ dev = dev_get_uclass_priv(udev);
+ if (0 == strcmp("id", cmd)) {
+ char id[MSG_BYTES];
+
+ if (cros_ec_read_id(dev, id, sizeof(id))) {
+ debug("%s: Could not read KBC ID\n", __func__);
+ return 1;
+ }
+ printf("%s\n", id);
+ } else if (0 == strcmp("info", cmd)) {
+ struct ec_response_mkbp_info info;
+
+ if (cros_ec_info(dev, &info)) {
+ debug("%s: Could not read KBC info\n", __func__);
+ return 1;
+ }
+ printf("rows = %u\n", info.rows);
+ printf("cols = %u\n", info.cols);
+ printf("switches = %#x\n", info.switches);
+ } else if (0 == strcmp("curimage", cmd)) {
+ enum ec_current_image image;
+
+ if (cros_ec_read_current_image(dev, &image)) {
+ debug("%s: Could not read KBC image\n", __func__);
+ return 1;
+ }
+ printf("%d\n", image);
+ } else if (0 == strcmp("hash", cmd)) {
+ struct ec_response_vboot_hash hash;
+ int i;
+
+ if (cros_ec_read_hash(dev, &hash)) {
+ debug("%s: Could not read KBC hash\n", __func__);
+ return 1;
+ }
+
+ if (hash.hash_type == EC_VBOOT_HASH_TYPE_SHA256)
+ printf("type: SHA-256\n");
+ else
+ printf("type: %d\n", hash.hash_type);
+
+ printf("offset: 0x%08x\n", hash.offset);
+ printf("size: 0x%08x\n", hash.size);
+
+ printf("digest: ");
+ for (i = 0; i < hash.digest_size; i++)
+ printf("%02x", hash.hash_digest[i]);
+ printf("\n");
+ } else if (0 == strcmp("reboot", cmd)) {
+ int region;
+ enum ec_reboot_cmd cmd;
+
+ if (argc >= 3 && !strcmp(argv[2], "cold")) {
+ cmd = EC_REBOOT_COLD;
+ } else {
+ region = cros_ec_decode_region(argc - 2, argv + 2);
+ if (region == EC_FLASH_REGION_RO)
+ cmd = EC_REBOOT_JUMP_RO;
+ else if (region == EC_FLASH_REGION_RW)
+ cmd = EC_REBOOT_JUMP_RW;
+ else
+ return CMD_RET_USAGE;
+ }
+
+ if (cros_ec_reboot(dev, cmd, 0)) {
+ debug("%s: Could not reboot KBC\n", __func__);
+ return 1;
+ }
+ } else if (0 == strcmp("events", cmd)) {
+ uint32_t events;
+
+ if (cros_ec_get_host_events(dev, &events)) {
+ debug("%s: Could not read host events\n", __func__);
+ return 1;
+ }
+ printf("0x%08x\n", events);
+ } else if (0 == strcmp("clrevents", cmd)) {
+ uint32_t events = 0x7fffffff;
+
+ if (argc >= 3)
+ events = simple_strtol(argv[2], NULL, 0);
+
+ if (cros_ec_clear_host_events(dev, events)) {
+ debug("%s: Could not clear host events\n", __func__);
+ return 1;
+ }
+ } else if (0 == strcmp("read", cmd)) {
+ ret = do_read_write(dev, 0, argc, argv);
+ if (ret > 0)
+ return CMD_RET_USAGE;
+ } else if (0 == strcmp("write", cmd)) {
+ ret = do_read_write(dev, 1, argc, argv);
+ if (ret > 0)
+ return CMD_RET_USAGE;
+ } else if (0 == strcmp("erase", cmd)) {
+ int region = cros_ec_decode_region(argc - 2, argv + 2);
+ uint32_t offset, size;
+
+ if (region == -1)
+ return CMD_RET_USAGE;
+ if (cros_ec_flash_offset(dev, region, &offset, &size)) {
+ debug("%s: Could not read region info\n", __func__);
+ ret = -1;
+ } else {
+ ret = cros_ec_flash_erase(dev, offset, size);
+ if (ret) {
+ debug("%s: Could not erase region\n",
+ __func__);
+ }
+ }
+ } else if (0 == strcmp("regioninfo", cmd)) {
+ int region = cros_ec_decode_region(argc - 2, argv + 2);
+ uint32_t offset, size;
+
+ if (region == -1)
+ return CMD_RET_USAGE;
+ ret = cros_ec_flash_offset(dev, region, &offset, &size);
+ if (ret) {
+ debug("%s: Could not read region info\n", __func__);
+ } else {
+ printf("Region: %s\n", region == EC_FLASH_REGION_RO ?
+ "RO" : "RW");
+ printf("Offset: %x\n", offset);
+ printf("Size: %x\n", size);
+ }
+ } else if (0 == strcmp("flashinfo", cmd)) {
+ struct ec_response_flash_info p;
+
+ ret = cros_ec_read_flashinfo(dev, &p);
+ if (!ret) {
+ printf("Flash size: %u\n", p.flash_size);
+ printf("Write block size: %u\n", p.write_block_size);
+ printf("Erase block size: %u\n", p.erase_block_size);
+ }
+ } else if (0 == strcmp("vbnvcontext", cmd)) {
+ uint8_t block[EC_VBNV_BLOCK_SIZE];
+ char buf[3];
+ int i, len;
+ unsigned long result;
+
+ if (argc <= 2) {
+ ret = cros_ec_read_vbnvcontext(dev, block);
+ if (!ret) {
+ printf("vbnv_block: ");
+ for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++)
+ printf("%02x", block[i]);
+ putc('\n');
+ }
+ } else {
+ /*
+ * TODO(clchiou): Move this to a utility function as
+ * cmd_spi might want to call it.
+ */
+ memset(block, 0, EC_VBNV_BLOCK_SIZE);
+ len = strlen(argv[2]);
+ buf[2] = '\0';
+ for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++) {
+ if (i * 2 >= len)
+ break;
+ buf[0] = argv[2][i * 2];
+ if (i * 2 + 1 >= len)
+ buf[1] = '0';
+ else
+ buf[1] = argv[2][i * 2 + 1];
+ strict_strtoul(buf, 16, &result);
+ block[i] = result;
+ }
+ ret = cros_ec_write_vbnvcontext(dev, block);
+ }
+ if (ret) {
+ debug("%s: Could not %s VbNvContext\n", __func__,
+ argc <= 2 ? "read" : "write");
+ }
+ } else if (0 == strcmp("test", cmd)) {
+ int result = cros_ec_test(dev);
+
+ if (result)
+ printf("Test failed with error %d\n", result);
+ else
+ puts("Test passed\n");
+ } else if (0 == strcmp("version", cmd)) {
+ struct ec_response_get_version *p;
+ char *build_string;
+
+ ret = cros_ec_read_version(dev, &p);
+ if (!ret) {
+ /* Print versions */
+ printf("RO version: %1.*s\n",
+ (int)sizeof(p->version_string_ro),
+ p->version_string_ro);
+ printf("RW version: %1.*s\n",
+ (int)sizeof(p->version_string_rw),
+ p->version_string_rw);
+ printf("Firmware copy: %s\n",
+ (p->current_image <
+ ARRAY_SIZE(ec_current_image_name) ?
+ ec_current_image_name[p->current_image] :
+ "?"));
+ ret = cros_ec_read_build_info(dev, &build_string);
+ if (!ret)
+ printf("Build info: %s\n", build_string);
+ }
+ } else if (0 == strcmp("ldo", cmd)) {
+ uint8_t index, state;
+ char *endp;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ index = simple_strtoul(argv[2], &endp, 10);
+ if (*argv[2] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+ if (argc > 3) {
+ state = simple_strtoul(argv[3], &endp, 10);
+ if (*argv[3] == 0 || *endp != 0)
+ return CMD_RET_USAGE;
+ ret = cros_ec_set_ldo(udev, index, state);
+ } else {
+ ret = cros_ec_get_ldo(udev, index, &state);
+ if (!ret) {
+ printf("LDO%d: %s\n", index,
+ state == EC_LDO_STATE_ON ?
+ "on" : "off");
+ }
+ }
+
+ if (ret) {
+ debug("%s: Could not access LDO%d\n", __func__, index);
+ return ret;
+ }
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ if (ret < 0) {
+ printf("Error: CROS-EC command failed (error %d)\n", ret);
+ ret = 1;
+ }
+
+ return ret;
+}
+
+U_BOOT_CMD(
+ crosec, 6, 1, do_cros_ec,
+ "CROS-EC utility command",
+ "init Re-init CROS-EC (done on startup automatically)\n"
+ "crosec id Read CROS-EC ID\n"
+ "crosec info Read CROS-EC info\n"
+ "crosec curimage Read CROS-EC current image\n"
+ "crosec hash Read CROS-EC hash\n"
+ "crosec reboot [rw | ro | cold] Reboot CROS-EC\n"
+ "crosec events Read CROS-EC host events\n"
+ "crosec clrevents [mask] Clear CROS-EC host events\n"
+ "crosec regioninfo <ro|rw> Read image info\n"
+ "crosec flashinfo Read flash info\n"
+ "crosec erase <ro|rw> Erase EC image\n"
+ "crosec read <ro|rw> <addr> [<size>] Read EC image\n"
+ "crosec write <ro|rw> <addr> [<size>] Write EC image\n"
+ "crosec vbnvcontext [hexstring] Read [write] VbNvContext from EC\n"
+ "crosec ldo <idx> [<state>] Switch/Read LDO state\n"
+ "crosec test run tests on cros_ec\n"
+ "crosec version Read CROS-EC version"
+);
diff --git a/cmd/dfu.c b/cmd/dfu.c
index d8aae26..04291f6 100644
--- a/cmd/dfu.c
+++ b/cmd/dfu.c
@@ -21,7 +21,6 @@
static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- bool dfu_reset = false;
if (argc < 4)
return CMD_RET_USAGE;
@@ -30,7 +29,7 @@
char *interface = argv[2];
char *devstring = argv[3];
- int ret, i = 0;
+ int ret;
#ifdef CONFIG_DFU_TFTP
unsigned long addr = 0;
if (!strcmp(argv[1], "tftp")) {
@@ -52,67 +51,11 @@
}
int controller_index = simple_strtoul(usb_controller, NULL, 0);
- board_usb_init(controller_index, USB_INIT_DEVICE);
- g_dnl_clear_detach();
- g_dnl_register("usb_dnl_dfu");
- while (1) {
- if (g_dnl_detach()) {
- /*
- * Check if USB bus reset is performed after detach,
- * which indicates that -R switch has been passed to
- * dfu-util. In this case reboot the device
- */
- if (dfu_usb_get_reset()) {
- dfu_reset = true;
- goto exit;
- }
- /*
- * This extra number of usb_gadget_handle_interrupts()
- * calls is necessary to assure correct transmission
- * completion with dfu-util
- */
- if (++i == 10000)
- goto exit;
- }
+ run_usb_dnl_gadget(controller_index, "usb_dnl_dfu");
- if (ctrlc())
- goto exit;
-
- if (dfu_get_defer_flush()) {
- /*
- * Call to usb_gadget_handle_interrupts() is necessary
- * to act on ZLP OUT transaction from HOST PC after
- * transmitting the whole file.
- *
- * If this ZLP OUT packet is NAK'ed, the HOST libusb
- * function fails after timeout (by default it is set to
- * 5 seconds). In such situation the dfu-util program
- * exits with error message.
- */
- usb_gadget_handle_interrupts(controller_index);
- ret = dfu_flush(dfu_get_defer_flush(), NULL, 0, 0);
- dfu_set_defer_flush(NULL);
- if (ret) {
- error("Deferred dfu_flush() failed!");
- goto exit;
- }
- }
-
- WATCHDOG_RESET();
- usb_gadget_handle_interrupts(controller_index);
- }
-exit:
- g_dnl_unregister();
- board_usb_cleanup(controller_index, USB_INIT_DEVICE);
done:
dfu_free_entities();
-
- if (dfu_reset)
- run_command("reset", 0);
-
- g_dnl_clear_detach();
-
return ret;
}
diff --git a/cmd/fastboot/Kconfig b/cmd/fastboot/Kconfig
index b2be904..83a3eda 100644
--- a/cmd/fastboot/Kconfig
+++ b/cmd/fastboot/Kconfig
@@ -1,10 +1,9 @@
comment "FASTBOOT"
-config FASTBOOT
- bool ""
+menuconfig FASTBOOT
+ bool "Fastboot support"
-menu "Fastboot support"
- depends on FASTBOOT
+if FASTBOOT
config USB_FUNCTION_FASTBOOT
bool "Enable USB fastboot gadget"
@@ -49,6 +48,14 @@
downloads. This buffer should be as large as possible for a
platform. Define this to the size available RAM for fastboot.
+config FASTBOOT_USB_DEV
+ int "USB controller number"
+ default 0
+ help
+ Some boards have USB OTG controller other than 0. Define this
+ option so it can be used in compiled environment (e.g. in
+ CONFIG_BOOTCOMMAND).
+
config FASTBOOT_FLASH
bool "Enable FASTBOOT FLASH command"
help
@@ -58,11 +65,35 @@
config FASTBOOT_FLASH_MMC_DEV
int "Define FASTBOOT MMC FLASH default device"
+ depends on FASTBOOT_FLASH
help
The fastboot "flash" command requires additional information
regarding the non-volatile storage device. Define this to
the eMMC device that fastboot should use to store the image.
+config FASTBOOT_GPT_NAME
+ string "Target name for updating GPT"
+ depends on FASTBOOT_FLASH
+ default "gpt"
+ help
+ The fastboot "flash" command supports writing the downloaded
+ image to the Protective MBR and the Primary GUID Partition
+ Table. (Additionally, this downloaded image is post-processed
+ to generate and write the Backup GUID Partition Table.)
+ This occurs when the specified "partition name" on the
+ "fastboot flash" command line matches the value defined here.
+ The default target name for updating GPT is "gpt".
+
+config FASTBOOT_MBR_NAME
+ string "Target name for updating MBR"
+ depends on FASTBOOT_FLASH
+ default "mbr"
+ help
+ The fastboot "flash" command allows to write the downloaded image
+ to the Master Boot Record. This occurs when the "partition name"
+ specified on the "fastboot flash" command line matches the value
+ defined here. The default target name for updating MBR is "mbr".
+
endif # USB_FUNCTION_FASTBOOT || UDP_FUNCTION_FASTBOOT
-endmenu
+endif # FASTBOOT
diff --git a/cmd/fat.c b/cmd/fat.c
index 4e20746..ad1dc2a 100644
--- a/cmd/fat.c
+++ b/cmd/fat.c
@@ -126,7 +126,7 @@
return 1;
}
addr = simple_strtoul(argv[3], NULL, 16);
- count = simple_strtoul(argv[5], NULL, 16);
+ count = (argc <= 5) ? 0 : simple_strtoul(argv[5], NULL, 16);
buf = map_sysmem(addr, count);
ret = file_fat_write(argv[4], buf, 0, count, &size);
@@ -145,7 +145,7 @@
U_BOOT_CMD(
fatwrite, 6, 0, do_fat_fswrite,
"write file into a dos filesystem",
- "<interface> <dev[:part]> <addr> <filename> <bytes>\n"
+ "<interface> <dev[:part]> <addr> <filename> [<bytes>]\n"
" - write file 'filename' from the address 'addr' in RAM\n"
" to 'dev' on 'interface'"
);
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 58af772..8bd345a 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -206,7 +206,17 @@
return 1;
}
working_fdt = newaddr;
+#ifdef CONFIG_OF_SYSTEM_SETUP
+ /* Call the board-specific fixup routine */
+ } else if (strncmp(argv[1], "sys", 3) == 0) {
+ int err = ft_system_setup(working_fdt, gd->bd);
+ if (err) {
+ printf("Failed to add system information to FDT: %s\n",
+ fdt_strerror(err));
+ return CMD_RET_FAILURE;
+ }
+#endif
/*
* Make a new node
*/
@@ -577,18 +587,6 @@
}
}
#endif
-#ifdef CONFIG_OF_SYSTEM_SETUP
- /* Call the board-specific fixup routine */
- else if (strncmp(argv[1], "sys", 3) == 0) {
- int err = ft_system_setup(working_fdt, gd->bd);
-
- if (err) {
- printf("Failed to add system information to FDT: %s\n",
- fdt_strerror(err));
- return CMD_RET_FAILURE;
- }
- }
-#endif
/* Create a chosen node */
else if (strncmp(argv[1], "cho", 3) == 0) {
unsigned long initrd_start = 0, initrd_end = 0;
@@ -662,7 +660,12 @@
#endif
/* resize the fdt */
else if (strncmp(argv[1], "re", 2) == 0) {
- fdt_shrink_to_minimum(working_fdt);
+ uint extrasize;
+ if (argc > 2)
+ extrasize = simple_strtoul(argv[2], NULL, 16);
+ else
+ extrasize = 0;
+ fdt_shrink_to_minimum(working_fdt, extrasize);
}
else {
/* Unrecognized command */
@@ -1056,7 +1059,7 @@
"fdt systemsetup - Do system-specific set up\n"
#endif
"fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active\n"
- "fdt resize - Resize fdt to size + padding to 4k addr\n"
+ "fdt resize [<extrasize>] - Resize fdt to size + padding to 4k addr + some optional <extrasize> if needed\n"
"fdt print <path> [<prop>] - Recursive print starting at <path>\n"
"fdt list <path> [<prop>] - Print one level starting at <path>\n"
"fdt get value <var> <path> <prop> - Get <property> and store in <var>\n"
diff --git a/cmd/fuse.c b/cmd/fuse.c
index 5998f9b..2917d83 100644
--- a/cmd/fuse.c
+++ b/cmd/fuse.c
@@ -13,7 +13,7 @@
#include <command.h>
#include <console.h>
#include <fuse.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
static int strtou32(const char *str, unsigned int base, u32 *result)
{
diff --git a/cmd/host.c b/cmd/host.c
index 8d84415..515621b 100644
--- a/cmd/host.c
+++ b/cmd/host.c
@@ -9,7 +9,7 @@
#include <fs.h>
#include <part.h>
#include <sandboxblockdev.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
static int host_curr_device = -1;
@@ -25,6 +25,12 @@
return do_ls(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX);
}
+static int do_host_size(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return do_size(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX);
+}
+
static int do_host_save(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
@@ -138,6 +144,7 @@
U_BOOT_CMD_MKENT(load, 7, 0, do_host_load, "", ""),
U_BOOT_CMD_MKENT(ls, 3, 0, do_host_ls, "", ""),
U_BOOT_CMD_MKENT(save, 6, 0, do_host_save, "", ""),
+ U_BOOT_CMD_MKENT(size, 3, 0, do_host_size, "", ""),
U_BOOT_CMD_MKENT(bind, 3, 0, do_host_bind, "", ""),
U_BOOT_CMD_MKENT(info, 3, 0, do_host_info, "", ""),
U_BOOT_CMD_MKENT(dev, 0, 1, do_host_dev, "", ""),
@@ -174,6 +181,7 @@
"host ls hostfs - <filename> - list files on host\n"
"host save hostfs - <addr> <filename> <bytes> [<offset>] - "
"save a file to host\n"
+ "host size hostfs - <filename> - determine size of file on host"
"host bind <dev> [<filename>] - bind \"host\" device to file\n"
"host info [<dev>] - show device binding & info\n"
"host dev [<dev>] - Set or retrieve the current host device\n"
diff --git a/cmd/load.c b/cmd/load.c
index 65557e4..77c3359 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@ -997,7 +997,7 @@
xyzModem_stream_terminate(false, &getcxmodem);
- flush_cache(offset, size);
+ flush_cache(offset, ALIGN(size, ARCH_DMA_MINALIGN));
printf("## Total Size = 0x%08x = %d Bytes\n", size, size);
setenv_hex("filesize", size);
diff --git a/cmd/mdio.c b/cmd/mdio.c
index fb13d05..21dc103 100644
--- a/cmd/mdio.c
+++ b/cmd/mdio.c
@@ -27,12 +27,12 @@
static int extract_range(char *input, int *plo, int *phi)
{
char *end;
- *plo = simple_strtol(input, &end, 0);
+ *plo = simple_strtol(input, &end, 16);
if (end == input)
return -1;
if ((*end == '-') && *(++end))
- *phi = simple_strtol(end, NULL, 0);
+ *phi = simple_strtol(end, NULL, 16);
else if (*end == '\0')
*phi = *plo;
else
@@ -79,7 +79,7 @@
printf("Reading from bus %s\n", bus->name);
for (addr = addrlo; addr <= addrhi; addr++) {
- printf("PHY at address %d:\n", addr);
+ printf("PHY at address %x:\n", addr);
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
diff --git a/cmd/mmc.c b/cmd/mmc.c
index b2761e9..b8dcc26 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -729,6 +729,31 @@
return ret;
}
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+static int do_mmc_bkops_enable(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int dev;
+ struct mmc *mmc;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ dev = simple_strtoul(argv[1], NULL, 10);
+
+ mmc = init_mmc_device(dev, false);
+ if (!mmc)
+ return CMD_RET_FAILURE;
+
+ if (IS_SD(mmc)) {
+ puts("BKOPS_EN only exists on eMMC\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return mmc_set_bkops_enable(mmc);
+}
+#endif
+
static cmd_tbl_t cmd_mmc[] = {
U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""),
U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""),
@@ -749,6 +774,9 @@
U_BOOT_CMD_MKENT(rpmb, CONFIG_SYS_MAXARGS, 1, do_mmcrpmb, "", ""),
#endif
U_BOOT_CMD_MKENT(setdsr, 2, 0, do_mmc_setdsr, "", ""),
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+ U_BOOT_CMD_MKENT(bkops-enable, 2, 0, do_mmc_bkops_enable, "", ""),
+#endif
};
static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -813,6 +841,10 @@
"mmc rpmb counter - read the value of the write counter\n"
#endif
"mmc setdsr <value> - set DSR register value\n"
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+ "mmc bkops-enable <dev> - enable background operations handshake on device\n"
+ " WARNING: This is a write-once setting.\n"
+#endif
);
/* Old command kept for compatibility. Same as 'mmc info' */
diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig
new file mode 100644
index 0000000..ad10a57
--- /dev/null
+++ b/cmd/mvebu/Kconfig
@@ -0,0 +1,52 @@
+menu "MVEBU commands"
+depends on ARCH_MVEBU
+
+config CMD_MVEBU_BUBT
+ bool "bubt"
+ default n
+ help
+ bubt - Burn a u-boot image to flash
+ For details about bubt command please see the documentation
+ in doc/mvebu/cmd/bubt.txt
+
+choice
+ prompt "Flash for image"
+ default MVEBU_SPI_BOOT
+
+config MVEBU_NAND_BOOT
+ bool "NAND flash boot"
+ depends on NAND_PXA3XX
+ help
+ Enable boot from NAND flash.
+ Allow usage of NAND flash as a target for "bubt" command
+ For details about bubt command please see the documentation
+ in doc/mvebu/cmd/bubt.txt
+
+config MVEBU_SPI_BOOT
+ bool "SPI flash boot"
+ depends on SPI_FLASH
+ help
+ Enable boot from SPI flash.
+ Allow usage of SPI flash as a target for "bubt" command
+ For details about bubt command please see the documentation
+ in doc/mvebu/cmd/bubt.txt
+
+config MVEBU_MMC_BOOT
+ bool "eMMC flash boot"
+ depends on MVEBU_MMC
+ help
+ Enable boot from eMMC boot partition
+ Allow usage of eMMC/SD device as a target for "bubt" command
+ For details about bubt command please see the documentation
+ in doc/mvebu/cmd/bubt.txt
+
+endchoice
+
+config MVEBU_UBOOT_DFLT_NAME
+ string "Default image name for bubt command"
+ default "flash-image.bin"
+ help
+ This option should contain a default file name to be used with
+ MVEBU "bubt" command if the source file name is omitted
+
+endmenu
diff --git a/cmd/mvebu/Makefile b/cmd/mvebu/Makefile
new file mode 100644
index 0000000..03de53e
--- /dev/null
+++ b/cmd/mvebu/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0
+# https://spdx.org/licenses
+
+
+obj-$(CONFIG_CMD_MVEBU_BUBT) += bubt.o
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
new file mode 100644
index 0000000..1cbfcf0
--- /dev/null
+++ b/cmd/mvebu/bubt.c
@@ -0,0 +1,767 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <vsprintf.h>
+#include <errno.h>
+#include <dm.h>
+
+#include <spi_flash.h>
+#include <spi.h>
+#include <nand.h>
+#include <usb.h>
+#include <fs.h>
+#include <mmc.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
+
+#ifndef CONFIG_SYS_MMC_ENV_DEV
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+#if defined(CONFIG_ARMADA_8K)
+#define MAIN_HDR_MAGIC 0xB105B002
+
+struct mvebu_image_header {
+ u32 magic; /* 0-3 */
+ u32 prolog_size; /* 4-7 */
+ u32 prolog_checksum; /* 8-11 */
+ u32 boot_image_size; /* 12-15 */
+ u32 boot_image_checksum; /* 16-19 */
+ u32 rsrvd0; /* 20-23 */
+ u32 load_addr; /* 24-27 */
+ u32 exec_addr; /* 28-31 */
+ u8 uart_cfg; /* 32 */
+ u8 baudrate; /* 33 */
+ u8 ext_count; /* 34 */
+ u8 aux_flags; /* 35 */
+ u32 io_arg_0; /* 36-39 */
+ u32 io_arg_1; /* 40-43 */
+ u32 io_arg_2; /* 43-47 */
+ u32 io_arg_3; /* 48-51 */
+ u32 rsrvd1; /* 52-55 */
+ u32 rsrvd2; /* 56-59 */
+ u32 rsrvd3; /* 60-63 */
+};
+#elif defined(CONFIG_ARMADA_3700) /* A3700 */
+#define HASH_SUM_LEN 16
+#define IMAGE_VERSION_3_6_0 0x030600
+#define IMAGE_VERSION_3_5_0 0x030500
+
+struct common_tim_data {
+ u32 version;
+ u32 identifier;
+ u32 trusted;
+ u32 issue_date;
+ u32 oem_unique_id;
+ u32 reserved[5]; /* Reserve 20 bytes */
+ u32 boot_flash_sign;
+ u32 num_images;
+ u32 num_keys;
+ u32 size_of_reserved;
+};
+
+struct mvebu_image_info {
+ u32 image_id;
+ u32 next_image_id;
+ u32 flash_entry_addr;
+ u32 load_addr;
+ u32 image_size;
+ u32 image_size_to_hash;
+ u32 hash_algorithm_id;
+ u32 hash[HASH_SUM_LEN]; /* Reserve 512 bits for the hash */
+ u32 partition_number;
+ u32 enc_algorithm_id;
+ u32 encrypt_start_offset;
+ u32 encrypt_size;
+};
+#endif /* CONFIG_ARMADA_XXX */
+
+struct bubt_dev {
+ char name[8];
+ size_t (*read)(const char *file_name);
+ int (*write)(size_t image_size);
+ int (*active)(void);
+};
+
+static ulong get_load_addr(void)
+{
+ const char *addr_str;
+ unsigned long addr;
+
+ addr_str = getenv("loadaddr");
+ if (addr_str)
+ addr = simple_strtoul(addr_str, NULL, 16);
+ else
+ addr = CONFIG_SYS_LOAD_ADDR;
+
+ return addr;
+}
+
+/********************************************************************
+ * eMMC services
+ ********************************************************************/
+#ifdef CONFIG_DM_MMC
+static int mmc_burn_image(size_t image_size)
+{
+ struct mmc *mmc;
+ lbaint_t start_lba;
+ lbaint_t blk_count;
+ ulong blk_written;
+ int err;
+ const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
+
+ mmc = find_mmc_device(mmc_dev_num);
+ if (!mmc) {
+ printf("No SD/MMC/eMMC card found\n");
+ return -ENOMEDIUM;
+ }
+
+ err = mmc_init(mmc);
+ if (err) {
+ printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
+ mmc_dev_num);
+ return err;
+ }
+
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ if (mmc->part_num != CONFIG_SYS_MMC_ENV_PART) {
+ err = mmc_switch_part(mmc_dev_num, CONFIG_SYS_MMC_ENV_PART);
+ if (err) {
+ printf("MMC partition switch failed\n");
+ return err;
+ }
+ }
+#endif
+
+ /* SD reserves LBA-0 for MBR and boots from LBA-1,
+ * MMC/eMMC boots from LBA-0
+ */
+ start_lba = IS_SD(mmc) ? 1 : 0;
+ blk_count = image_size / mmc->block_dev.blksz;
+ if (image_size % mmc->block_dev.blksz)
+ blk_count += 1;
+
+ blk_written = mmc->block_dev.block_write(mmc_dev_num,
+ start_lba, blk_count,
+ (void *)get_load_addr());
+ if (blk_written != blk_count) {
+ printf("Error - written %#lx blocks\n", blk_written);
+ return -ENOSPC;
+ }
+ printf("Done!\n");
+
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ if (mmc->part_num != CONFIG_SYS_MMC_ENV_PART)
+ mmc_switch_part(mmc_dev_num, mmc->part_num);
+#endif
+
+ return 0;
+}
+
+static size_t mmc_read_file(const char *file_name)
+{
+ loff_t act_read = 0;
+ int rc;
+ struct mmc *mmc;
+ const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
+
+ mmc = find_mmc_device(mmc_dev_num);
+ if (!mmc) {
+ printf("No SD/MMC/eMMC card found\n");
+ return 0;
+ }
+
+ if (mmc_init(mmc)) {
+ printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
+ mmc_dev_num);
+ return 0;
+ }
+
+ /* Load from data partition (0) */
+ if (fs_set_blk_dev("mmc", "0", FS_TYPE_ANY)) {
+ printf("Error: MMC 0 not found\n");
+ return 0;
+ }
+
+ /* Perfrom file read */
+ rc = fs_read(file_name, get_load_addr(), 0, 0, &act_read);
+ if (rc)
+ return 0;
+
+ return act_read;
+}
+
+static int is_mmc_active(void)
+{
+ return 1;
+}
+#else /* CONFIG_DM_MMC */
+static int mmc_burn_image(size_t image_size)
+{
+ return -ENODEV;
+}
+
+static size_t mmc_read_file(const char *file_name)
+{
+ return 0;
+}
+
+static int is_mmc_active(void)
+{
+ return 0;
+}
+#endif /* CONFIG_DM_MMC */
+
+/********************************************************************
+ * SPI services
+ ********************************************************************/
+#ifdef CONFIG_SPI_FLASH
+static int spi_burn_image(size_t image_size)
+{
+ int ret;
+ struct spi_flash *flash;
+ u32 erase_bytes;
+
+ /* Probe the SPI bus to get the flash device */
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+ CONFIG_ENV_SPI_CS,
+ CONFIG_SF_DEFAULT_SPEED,
+ CONFIG_SF_DEFAULT_MODE);
+ if (!flash) {
+ printf("Failed to probe SPI Flash\n");
+ return -ENOMEDIUM;
+ }
+
+#ifdef CONFIG_SPI_FLASH_PROTECTION
+ spi_flash_protect(flash, 0);
+#endif
+ erase_bytes = image_size +
+ (flash->erase_size - image_size % flash->erase_size);
+ printf("Erasing %d bytes (%d blocks) at offset 0 ...",
+ erase_bytes, erase_bytes / flash->erase_size);
+ ret = spi_flash_erase(flash, 0, erase_bytes);
+ if (ret)
+ printf("Error!\n");
+ else
+ printf("Done!\n");
+
+ printf("Writing %d bytes from 0x%lx to offset 0 ...",
+ (int)image_size, get_load_addr());
+ ret = spi_flash_write(flash, 0, image_size, (void *)get_load_addr());
+ if (ret)
+ printf("Error!\n");
+ else
+ printf("Done!\n");
+
+#ifdef CONFIG_SPI_FLASH_PROTECTION
+ spi_flash_protect(flash, 1);
+#endif
+
+ return ret;
+}
+
+static int is_spi_active(void)
+{
+ return 1;
+}
+
+#else /* CONFIG_SPI_FLASH */
+static int spi_burn_image(size_t image_size)
+{
+ return -ENODEV;
+}
+
+static int is_spi_active(void)
+{
+ return 0;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+/********************************************************************
+ * NAND services
+ ********************************************************************/
+#ifdef CONFIG_CMD_NAND
+static int nand_burn_image(size_t image_size)
+{
+ int ret, block_size;
+ nand_info_t *nand;
+ int dev = nand_curr_device;
+
+ if ((dev < 0) || (dev >= CONFIG_SYS_MAX_NAND_DEVICE) ||
+ (!nand_info[dev].name)) {
+ puts("\nno devices available\n");
+ return -ENOMEDIUM;
+ }
+ nand = &nand_info[dev];
+ block_size = nand->erasesize;
+
+ /* Align U-Boot size to currently used blocksize */
+ image_size = ((image_size + (block_size - 1)) & (~(block_size - 1)));
+
+ /* Erase the U-BOOT image space */
+ printf("Erasing 0x%x - 0x%x:...", 0, (int)image_size);
+ ret = nand_erase(nand, 0, image_size);
+ if (ret) {
+ printf("Error!\n");
+ goto error;
+ }
+ printf("Done!\n");
+
+ /* Write the image to flash */
+ printf("Writing image:...");
+ printf("&image_size = 0x%p\n", (void *)&image_size);
+ ret = nand_write(nand, 0, &image_size, (void *)get_load_addr());
+ if (ret)
+ printf("Error!\n");
+ else
+ printf("Done!\n");
+
+error:
+ return ret;
+}
+
+static int is_nand_active(void)
+{
+ return 1;
+}
+
+#else /* CONFIG_CMD_NAND */
+static int nand_burn_image(size_t image_size)
+{
+ return -ENODEV;
+}
+
+static int is_nand_active(void)
+{
+ return 0;
+}
+#endif /* CONFIG_CMD_NAND */
+
+/********************************************************************
+ * USB services
+ ********************************************************************/
+#if defined(CONFIG_USB_STORAGE) && defined(CONFIG_BLK)
+static size_t usb_read_file(const char *file_name)
+{
+ loff_t act_read = 0;
+ struct udevice *dev;
+ int rc;
+
+ usb_stop();
+
+ if (usb_init() < 0) {
+ printf("Error: usb_init failed\n");
+ return 0;
+ }
+
+ /* Try to recognize storage devices immediately */
+ blk_first_device(IF_TYPE_USB, &dev);
+ if (!dev) {
+ printf("Error: USB storage device not found\n");
+ return 0;
+ }
+
+ /* Always load from usb 0 */
+ if (fs_set_blk_dev("usb", "0", FS_TYPE_ANY)) {
+ printf("Error: USB 0 not found\n");
+ return 0;
+ }
+
+ /* Perfrom file read */
+ rc = fs_read(file_name, get_load_addr(), 0, 0, &act_read);
+ if (rc)
+ return 0;
+
+ return act_read;
+}
+
+static int is_usb_active(void)
+{
+ return 1;
+}
+
+#else /* defined(CONFIG_USB_STORAGE) && defined (CONFIG_BLK) */
+static size_t usb_read_file(const char *file_name)
+{
+ return 0;
+}
+
+static int is_usb_active(void)
+{
+ return 0;
+}
+#endif /* defined(CONFIG_USB_STORAGE) && defined (CONFIG_BLK) */
+
+/********************************************************************
+ * Network services
+ ********************************************************************/
+#ifdef CONFIG_CMD_NET
+static size_t tftp_read_file(const char *file_name)
+{
+ /* update global variable load_addr before tftp file from network */
+ load_addr = get_load_addr();
+ return net_loop(TFTPGET);
+}
+
+static int is_tftp_active(void)
+{
+ return 1;
+}
+
+#else
+static size_t tftp_read_file(const char *file_name)
+{
+ return 0;
+}
+
+static int is_tftp_active(void)
+{
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+
+enum bubt_devices {
+ BUBT_DEV_NET = 0,
+ BUBT_DEV_USB,
+ BUBT_DEV_MMC,
+ BUBT_DEV_SPI,
+ BUBT_DEV_NAND,
+
+ BUBT_MAX_DEV
+};
+
+struct bubt_dev bubt_devs[BUBT_MAX_DEV] = {
+ {"tftp", tftp_read_file, NULL, is_tftp_active},
+ {"usb", usb_read_file, NULL, is_usb_active},
+ {"mmc", mmc_read_file, mmc_burn_image, is_mmc_active},
+ {"spi", NULL, spi_burn_image, is_spi_active},
+ {"nand", NULL, nand_burn_image, is_nand_active},
+};
+
+static int bubt_write_file(struct bubt_dev *dst, size_t image_size)
+{
+ if (!dst->write) {
+ printf("Error: Write not supported on device %s\n", dst->name);
+ return -ENOTSUPP;
+ }
+
+ return dst->write(image_size);
+}
+
+#if defined(CONFIG_ARMADA_8K)
+u32 do_checksum32(u32 *start, int32_t len)
+{
+ u32 sum = 0;
+ u32 *startp = start;
+
+ do {
+ sum += *startp;
+ startp++;
+ len -= 4;
+ } while (len > 0);
+
+ return sum;
+}
+
+static int check_image_header(void)
+{
+ struct mvebu_image_header *hdr =
+ (struct mvebu_image_header *)get_load_addr();
+ u32 header_len = hdr->prolog_size;
+ u32 checksum;
+ u32 checksum_ref = hdr->prolog_checksum;
+
+ /*
+ * For now compare checksum, and magic. Later we can
+ * verify more stuff on the header like interface type, etc
+ */
+ if (hdr->magic != MAIN_HDR_MAGIC) {
+ printf("ERROR: Bad MAGIC 0x%08x != 0x%08x\n",
+ hdr->magic, MAIN_HDR_MAGIC);
+ return -ENOEXEC;
+ }
+
+ /* The checksum value is discarded from checksum calculation */
+ hdr->prolog_checksum = 0;
+
+ checksum = do_checksum32((u32 *)hdr, header_len);
+ if (checksum != checksum_ref) {
+ printf("Error: Bad Image checksum. 0x%x != 0x%x\n",
+ checksum, checksum_ref);
+ return -ENOEXEC;
+ }
+
+ /* Restore the checksum before writing */
+ hdr->prolog_checksum = checksum_ref;
+ printf("Image checksum...OK!\n");
+
+ return 0;
+}
+#elif defined(CONFIG_ARMADA_3700) /* Armada 3700 */
+static int check_image_header(void)
+{
+ struct common_tim_data *hdr = (struct common_tim_data *)get_load_addr();
+ int image_num;
+ u8 hash_160_output[SHA1_SUM_LEN];
+ u8 hash_256_output[SHA256_SUM_LEN];
+ sha1_context hash1_text;
+ sha256_context hash256_text;
+ u8 *hash_output;
+ u32 hash_algorithm_id;
+ u32 image_size_to_hash;
+ u32 flash_entry_addr;
+ u32 *hash_value;
+ u32 internal_hash[HASH_SUM_LEN];
+ const u8 *buff;
+ u32 num_of_image = hdr->num_images;
+ u32 version = hdr->version;
+ u32 trusted = hdr->trusted;
+
+ /* bubt checksum validation only supports nontrusted images */
+ if (trusted == 1) {
+ printf("bypass image validation, ");
+ printf("only untrusted image is supported now\n");
+ return 0;
+ }
+ /* only supports image version 3.5 and 3.6 */
+ if (version != IMAGE_VERSION_3_5_0 && version != IMAGE_VERSION_3_6_0) {
+ printf("Error: Unsupported Image version = 0x%08x\n", version);
+ return -ENOEXEC;
+ }
+ /* validate images hash value */
+ for (image_num = 0; image_num < num_of_image; image_num++) {
+ struct mvebu_image_info *info =
+ (struct mvebu_image_info *)(get_load_addr() +
+ sizeof(struct common_tim_data) +
+ image_num * sizeof(struct mvebu_image_info));
+ hash_algorithm_id = info->hash_algorithm_id;
+ image_size_to_hash = info->image_size_to_hash;
+ flash_entry_addr = info->flash_entry_addr;
+ hash_value = info->hash;
+ buff = (const u8 *)(get_load_addr() + flash_entry_addr);
+
+ if (image_num == 0) {
+ /*
+ * The first image includes hash values in its content.
+ * For hash calculation, we need to save the original
+ * hash values to a local variable that will be
+ * copied back for comparsion and set all zeros to
+ * the orignal hash values for calculating new value.
+ * First image original format :
+ * x...x (datum1) x...x(orig. hash values) x...x(datum2)
+ * Replaced first image format :
+ * x...x (datum1) 0...0(hash values) x...x(datum2)
+ */
+ memcpy(internal_hash, hash_value,
+ sizeof(internal_hash));
+ memset(hash_value, 0, sizeof(internal_hash));
+ }
+ if (image_size_to_hash == 0) {
+ printf("Warning: Image_%d hash checksum is disabled, ",
+ image_num);
+ printf("skip the image validation.\n");
+ continue;
+ }
+ switch (hash_algorithm_id) {
+ case SHA1_SUM_LEN:
+ sha1_starts(&hash1_text);
+ sha1_update(&hash1_text, buff, image_size_to_hash);
+ sha1_finish(&hash1_text, hash_160_output);
+ hash_output = hash_160_output;
+ break;
+ case SHA256_SUM_LEN:
+ sha256_starts(&hash256_text);
+ sha256_update(&hash256_text, buff, image_size_to_hash);
+ sha256_finish(&hash256_text, hash_256_output);
+ hash_output = hash_256_output;
+ break;
+ default:
+ printf("Error: Unsupported hash_algorithm_id = %d\n",
+ hash_algorithm_id);
+ return -ENOEXEC;
+ }
+ if (image_num == 0)
+ memcpy(hash_value, internal_hash,
+ sizeof(internal_hash));
+ if (memcmp(hash_value, hash_output, hash_algorithm_id) != 0) {
+ printf("Error: Image_%d checksum is not correct\n",
+ image_num);
+ return -ENOEXEC;
+ }
+ }
+ printf("Image checksum...OK!\n");
+
+ return 0;
+}
+
+#else /* Not ARMADA? */
+static int check_image_header(void)
+{
+ printf("bubt cmd does not support this SoC device or family!\n");
+ return -ENOEXEC;
+}
+#endif
+
+static int bubt_verify(size_t image_size)
+{
+ int err;
+
+ /* Check a correct image header exists */
+ err = check_image_header();
+ if (err) {
+ printf("Error: Image header verification failed\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int bubt_read_file(struct bubt_dev *src)
+{
+ size_t image_size;
+
+ if (!src->read) {
+ printf("Error: Read not supported on device \"%s\"\n",
+ src->name);
+ return 0;
+ }
+
+ image_size = src->read(net_boot_file_name);
+ if (image_size <= 0) {
+ printf("Error: Failed to read file %s from %s\n",
+ net_boot_file_name, src->name);
+ return 0;
+ }
+
+ return image_size;
+}
+
+static int bubt_is_dev_active(struct bubt_dev *dev)
+{
+ if (!dev->active) {
+ printf("Device \"%s\" not supported by U-BOOT image\n",
+ dev->name);
+ return 0;
+ }
+
+ if (!dev->active()) {
+ printf("Device \"%s\" is inactive\n", dev->name);
+ return 0;
+ }
+
+ return 1;
+}
+
+struct bubt_dev *find_bubt_dev(char *dev_name)
+{
+ int dev;
+
+ for (dev = 0; dev < BUBT_MAX_DEV; dev++) {
+ if (strcmp(bubt_devs[dev].name, dev_name) == 0)
+ return &bubt_devs[dev];
+ }
+
+ return 0;
+}
+
+#define DEFAULT_BUBT_SRC "tftp"
+
+#ifndef DEFAULT_BUBT_DST
+#ifdef CONFIG_MVEBU_SPI_BOOT
+#define DEFAULT_BUBT_DST "spi"
+#elif defined(CONFIG_MVEBU_NAND_BOOT)
+#define DEFAULT_BUBT_DST "nand"
+#elif defined(CONFIG_MVEBU_MMC_BOOT)
+#define DEFAULT_BUBT_DST "mmc"
+else
+#define DEFAULT_BUBT_DST "error"
+#endif
+#endif /* DEFAULT_BUBT_DST */
+
+int do_bubt_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct bubt_dev *src, *dst;
+ size_t image_size;
+ char src_dev_name[8];
+ char dst_dev_name[8];
+ char *name;
+ int err;
+
+ if (argc < 2)
+ copy_filename(net_boot_file_name,
+ CONFIG_MVEBU_UBOOT_DFLT_NAME,
+ sizeof(net_boot_file_name));
+ else
+ copy_filename(net_boot_file_name, argv[1],
+ sizeof(net_boot_file_name));
+
+ if (argc >= 3) {
+ strncpy(dst_dev_name, argv[2], 8);
+ } else {
+ name = DEFAULT_BUBT_DST;
+ strncpy(dst_dev_name, name, 8);
+ }
+
+ if (argc >= 4)
+ strncpy(src_dev_name, argv[3], 8);
+ else
+ strncpy(src_dev_name, DEFAULT_BUBT_SRC, 8);
+
+ /* Figure out the destination device */
+ dst = find_bubt_dev(dst_dev_name);
+ if (!dst) {
+ printf("Error: Unknown destination \"%s\"\n", dst_dev_name);
+ return -EINVAL;
+ }
+
+ if (!bubt_is_dev_active(dst))
+ return -ENODEV;
+
+ /* Figure out the source device */
+ src = find_bubt_dev(src_dev_name);
+ if (!src) {
+ printf("Error: Unknown source \"%s\"\n", src_dev_name);
+ return 1;
+ }
+
+ if (!bubt_is_dev_active(src))
+ return -ENODEV;
+
+ printf("Burning U-BOOT image \"%s\" from \"%s\" to \"%s\"\n",
+ net_boot_file_name, src->name, dst->name);
+
+ image_size = bubt_read_file(src);
+ if (!image_size)
+ return -EIO;
+
+ err = bubt_verify(image_size);
+ if (err)
+ return err;
+
+ err = bubt_write_file(dst, image_size);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ bubt, 4, 0, do_bubt_cmd,
+ "Burn a u-boot image to flash",
+ "[file-name] [destination [source]]\n"
+ "\t-file-name The image file name to burn. Default = flash-image.bin\n"
+ "\t-destination Flash to burn to [spi, nand, mmc]. Default = active boot device\n"
+ "\t-source The source to load image from [tftp, usb, mmc]. Default = tftp\n"
+ "Examples:\n"
+ "\tbubt - Burn flash-image.bin from tftp to active boot device\n"
+ "\tbubt flash-image-new.bin nand - Burn flash-image-new.bin from tftp to NAND flash\n"
+ "\tbubt backup-flash-image.bin mmc usb - Burn backup-flash-image.bin from usb to MMC\n"
+
+);
diff --git a/cmd/net.c b/cmd/net.c
index 5afb5ae..4714f5a 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -142,7 +142,7 @@
}
#if !defined(CONFIG_BOOTP_SERVERIP)
/*
- * Only attempt to change serverip if net/bootp.c:BootpCopyNetParams()
+ * Only attempt to change serverip if net/bootp.c:store_net_params()
* could have set it
*/
if (net_server_ip.s_addr) {
@@ -249,9 +249,6 @@
return CMD_RET_SUCCESS;
}
- /* flush cache */
- flush_cache(load_addr, size);
-
bootstage_mark(BOOTSTAGE_ID_NET_LOADED);
rcode = bootm_maybe_autostart(cmdtp, argv[0]);
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index b67563b..9ca5cb5 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -15,7 +15,7 @@
*
* The "environment" is stored on external storage as a list of '\0'
* terminated "name=value" strings. The end of the list is marked by
- * a double '\0'. The environment is preceeded by a 32 bit CRC over
+ * a double '\0'. The environment is preceded by a 32 bit CRC over
* the data part and, in case of redundant environment, a byte of
* flags.
*
@@ -838,7 +838,7 @@
* With "-c" and size is NOT given, then the export command will
* format the data as currently used for the persistent storage,
* i. e. it will use CONFIG_ENV_SECT_SIZE as output block size and
- * prepend a valid CRC32 checksum and, in case of resundant
+ * prepend a valid CRC32 checksum and, in case of redundant
* environment, a "current" redundancy flag. If size is given, this
* value will be used instead of CONFIG_ENV_SECT_SIZE; again, CRC32
* checksum and redundancy flag will be inserted.
@@ -847,12 +847,12 @@
* terminating '\0' byte) will be written; here the optional size
* argument will be used to make sure not to overflow the user
* provided buffer; the command will abort if the size is not
- * sufficient. Any remainign space will be '\0' padded.
+ * sufficient. Any remaining space will be '\0' padded.
*
* On successful return, the variable "filesize" will be set.
* Note that filesize includes the trailing/terminating '\0' byte(s).
*
- * Usage szenario: create a text snapshot/backup of the current settings:
+ * Usage scenario: create a text snapshot/backup of the current settings:
*
* => env export -t 100000
* => era ${backup_addr} +${filesize}
@@ -970,7 +970,7 @@
/*
* env import [-d] [-t [-r] | -b | -c] addr [size]
* -d: delete existing environment before importing;
- * otherwise overwrite / append to existion definitions
+ * otherwise overwrite / append to existing definitions
* -t: assume text format; either "size" must be given or the
* text data must be '\0' terminated
* -r: handle CRLF like LF, that means exported variables with
diff --git a/cmd/onenand.c b/cmd/onenand.c
index feab01a..d97844f 100644
--- a/cmd/onenand.c
+++ b/cmd/onenand.c
@@ -139,6 +139,12 @@
size_t _retlen = 0;
int ret;
+ if ((to & (mtd->writesize - 1)) != 0) {
+ printf("Attempt to write non block-aligned data\n");
+ *retlen = 0;
+ return 1;
+ }
+
if (to == next_ofs) {
next_ofs = to + len;
to += skip_ofs;
diff --git a/cmd/pci.c b/cmd/pci.c
index 2f4978a..7993c1a 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -92,6 +92,77 @@
}
#endif
+#ifdef CONFIG_DM_PCI
+int pci_bar_show(struct udevice *dev)
+{
+ u8 header_type;
+ int bar_cnt, bar_id, mem_type;
+ bool is_64, is_io;
+ u32 base_low, base_high;
+ u32 size_low, size_high;
+ u64 base, size;
+ u32 reg_addr;
+ int prefetchable;
+
+ dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+
+ if (header_type == PCI_HEADER_TYPE_CARDBUS) {
+ printf("CardBus doesn't support BARs\n");
+ return -ENOSYS;
+ }
+
+ bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
+
+ printf("ID Base Size Width Type\n");
+ printf("----------------------------------------------------------\n");
+
+ bar_id = 0;
+ reg_addr = PCI_BASE_ADDRESS_0;
+ while (bar_cnt) {
+ dm_pci_read_config32(dev, reg_addr, &base_low);
+ dm_pci_write_config32(dev, reg_addr, 0xffffffff);
+ dm_pci_read_config32(dev, reg_addr, &size_low);
+ dm_pci_write_config32(dev, reg_addr, base_low);
+ reg_addr += 4;
+
+ base = base_low & ~0xf;
+ size = size_low & ~0xf;
+ base_high = 0x0;
+ size_high = 0xffffffff;
+ is_64 = 0;
+ prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
+ is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
+ mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
+
+ if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ dm_pci_read_config32(dev, reg_addr, &base_high);
+ dm_pci_write_config32(dev, reg_addr, 0xffffffff);
+ dm_pci_read_config32(dev, reg_addr, &size_high);
+ dm_pci_write_config32(dev, reg_addr, base_high);
+ bar_cnt--;
+ reg_addr += 4;
+ is_64 = 1;
+ }
+
+ base = base | ((u64)base_high << 32);
+ size = size | ((u64)size_high << 32);
+
+ if ((!is_64 && size_low) || (is_64 && size)) {
+ size = ~size + 1;
+ printf(" %d %#016llx %#016llx %d %s %s\n",
+ bar_id, base, size, is_64 ? 64 : 32,
+ is_io ? "I/O" : "MEM",
+ prefetchable ? "Prefetchable" : "");
+ }
+
+ bar_id++;
+ bar_cnt--;
+ }
+
+ return 0;
+}
+#endif
+
static struct pci_reg_info regs_start[] = {
{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
@@ -573,6 +644,9 @@
if (argc > 4)
value = simple_strtoul(argv[4], NULL, 16);
case 'h': /* header */
+#ifdef CONFIG_DM_PCI
+ case 'b': /* bars */
+#endif
if (argc < 3)
goto usage;
if ((bdf = get_pci_dev(argv[2])) == -1)
@@ -641,6 +715,11 @@
ret = pci_cfg_write(dev, addr, size, value);
#endif
break;
+#ifdef CONFIG_DM_PCI
+
+ case 'b': /* bars */
+ return pci_bar_show(dev);
+#endif
default:
ret = CMD_RET_USAGE;
break;
@@ -663,6 +742,10 @@
#endif
"pci header b.d.f\n"
" - show header of PCI device 'bus.device.function'\n"
+#ifdef CONFIG_DM_PCI
+ "pci bar b.d.f\n"
+ " - show BARs base and size for device b.d.f'\n"
+#endif
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
" - display PCI configuration space (CFG)\n"
"pci next[.b, .w, .l] b.d.f address\n"
diff --git a/cmd/regulator.c b/cmd/regulator.c
index bfea6e0..2ef5bc9 100644
--- a/cmd/regulator.c
+++ b/cmd/regulator.c
@@ -292,7 +292,10 @@
return CMD_RET_FAILURE;
}
- ret = regulator_set_value(dev, value);
+ if (!force)
+ ret = regulator_set_value(dev, value);
+ else
+ ret = regulator_set_value_force(dev, value);
if (ret) {
printf("Regulator: %s - can't set the Voltage!\n",
uc_pdata->name);
diff --git a/cmd/sata.c b/cmd/sata.c
index d18b523..f56622a 100644
--- a/cmd/sata.c
+++ b/cmd/sata.c
@@ -32,9 +32,12 @@
}
/* If the user has not yet run `sata init`, do it now */
- if (sata_curr_device == -1)
- if (sata_initialize())
- return 1;
+ if (sata_curr_device == -1) {
+ rc = sata_initialize();
+ if (rc == -1)
+ return rc;
+ sata_curr_device = rc;
+ }
switch (argc) {
case 0:
diff --git a/cmd/scsi.c b/cmd/scsi.c
index 387ca1a..4213ec8 100644
--- a/cmd/scsi.c
+++ b/cmd/scsi.c
@@ -17,7 +17,7 @@
/*
* scsi boot command intepreter. Derived from diskboot
*/
-int do_scsiboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_scsiboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
return common_diskboot(cmdtp, "scsi", argc, argv);
}
@@ -25,8 +25,10 @@
/*
* scsi command intepreter
*/
-int do_scsi(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_scsi(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
+ int ret;
+
switch (argc) {
case 0:
case 1:
@@ -35,8 +37,10 @@
if (strncmp(argv[1], "res", 3) == 0) {
printf("\nReset SCSI\n");
scsi_bus_reset();
- scsi_scan(1);
- return 0;
+ ret = scsi_scan(1);
+ if (ret)
+ return CMD_RET_FAILURE;
+ return ret;
}
if (strncmp(argv[1], "inf", 3) == 0) {
blk_list_devices(IF_TYPE_SCSI);
@@ -51,8 +55,10 @@
return 0;
}
if (strncmp(argv[1], "scan", 4) == 0) {
- scsi_scan(1);
- return 0;
+ ret = scsi_scan(1);
+ if (ret)
+ return CMD_RET_FAILURE;
+ return ret;
}
if (strncmp(argv[1], "part", 4) == 0) {
if (blk_list_part(IF_TYPE_SCSI))
diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c
index 65332d1..3306405 100644
--- a/cmd/tpm_test.c
+++ b/cmd/tpm_test.c
@@ -532,15 +532,15 @@
static int do_tpmtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *c;
+ int i;
printf("argc = %d, argv = ", argc);
- do {
- int i = 0;
- for (i = 0; i < argc; i++)
- printf(" %s", argv[i]);
- printf("\n------\n");
- } while (0);
+ for (i = 0; i < argc; i++)
+ printf(" %s", argv[i]);
+
+ printf("\n------\n");
+
argc--;
argv++;
c = find_cmd_tbl(argv[0], cmd_cros_tpm_sub,
diff --git a/cmd/ubi.c b/cmd/ubi.c
index 4a92d84..7d0d7e7 100644
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -21,7 +21,7 @@
#include <linux/mtd/partitions.h>
#include <linux/err.h>
#include <ubi_uboot.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <jffs2/load_kernel.h>
#undef ubi_msg
@@ -162,7 +162,7 @@
return err;
}
-static int ubi_create_vol(char *volume, int64_t size, int dynamic)
+static int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id)
{
struct ubi_mkvol_req req;
int err;
@@ -172,7 +172,7 @@
else
req.vol_type = UBI_STATIC_VOLUME;
- req.vol_id = UBI_VOL_NUM_AUTO;
+ req.vol_id = vol_id;
req.alignment = 1;
req.bytes = size;
@@ -577,10 +577,17 @@
if (strncmp(argv[1], "create", 6) == 0) {
int dynamic = 1; /* default: dynamic volume */
+ int id = UBI_VOL_NUM_AUTO;
/* Use maximum available size */
size = 0;
+ /* E.g., create volume size type vol_id */
+ if (argc == 6) {
+ id = simple_strtoull(argv[5], NULL, 16);
+ argc--;
+ }
+
/* E.g., create volume size type */
if (argc == 5) {
if (strncmp(argv[4], "s", 1) == 0)
@@ -603,7 +610,7 @@
}
/* E.g., create volume */
if (argc == 3)
- return ubi_create_vol(argv[2], size, dynamic);
+ return ubi_create_vol(argv[2], size, dynamic, id);
}
if (strncmp(argv[1], "remove", 6) == 0) {
@@ -684,7 +691,7 @@
" - Display volume and ubi layout information\n"
"ubi check volumename"
" - check if volumename exists\n"
- "ubi create[vol] volume [size] [type]"
+ "ubi create[vol] volume [size] [type] [id]"
" - create volume name with size\n"
"ubi write[vol] address volume size"
" - Write volume from address with size\n"
diff --git a/common/Kconfig b/common/Kconfig
index 63c4a67..a04ee10 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -170,6 +170,14 @@
See doc/README.autoboot for details.
+menu "Console"
+
+config MENU
+ bool
+ help
+ This is the library functionality to provide a text-based menu of
+ choices for the user to make choices with.
+
config CONSOLE_RECORD
bool "Console recording"
help
@@ -198,6 +206,157 @@
The buffer is allocated immediately after the malloc() region is
ready.
+config IDENT_STRING
+ string "Board specific string to be added to uboot version string"
+ help
+ This options adds the board specific name to u-boot version.
+
+config SILENT_CONSOLE
+ bool "Support a silent console"
+ help
+ This option allows the console to be silenced, meaning that no
+ output will appear on the console devices. This is controlled by
+ setting the environment vaariable 'silent' to a non-empty value.
+ Note this also silences the console when booting Linux.
+
+ When the console is set up, the variable is checked, and the
+ GD_FLG_SILENT flag is set. Changing the environment variable later
+ will update the flag.
+
+config SILENT_U_BOOT_ONLY
+ bool "Only silence the U-Boot console"
+ depends on SILENT_CONSOLE
+ help
+ Normally when the U-Boot console is silenced, Linux's console is
+ also silenced (assuming the board boots into Linux). This option
+ allows the linux console to operate normally, even if U-Boot's
+ is silenced.
+
+config SILENT_CONSOLE_UPDATE_ON_SET
+ bool "Changes to the 'silent' environment variable update immediately"
+ depends on SILENT_CONSOLE
+ default y if SILENT_CONSOLE
+ help
+ When the 'silent' environment variable is changed, update the
+ console silence flag immediately. This allows 'setenv' to be used
+ to silence or un-silence the console.
+
+ The effect is that any change to the variable will affect the
+ GD_FLG_SILENT flag.
+
+config SILENT_CONSOLE_UPDATE_ON_RELOC
+ bool "Allow flags to take effect on relocation"
+ depends on SILENT_CONSOLE
+ help
+ In some cases the environment is not available until relocation
+ (e.g. NAND). This option makes the value of the 'silent'
+ environment variable take effect at relocation.
+
+config PRE_CONSOLE_BUFFER
+ bool "Buffer characters before the console is available"
+ help
+ Prior to the console being initialised (i.e. serial UART
+ initialised etc) all console output is silently discarded.
+ Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
+ buffer any console messages prior to the console being
+ initialised to a buffer. The buffer is a circular buffer, so
+ if it overflows, earlier output is discarded.
+
+ Note that this is not currently supported in SPL. It would be
+ useful to be able to share the pre-console buffer with SPL.
+
+config PRE_CON_BUF_SZ
+ int "Sets the size of the pre-console buffer"
+ depends on PRE_CONSOLE_BUFFER
+ default 4096
+ help
+ The size of the pre-console buffer affects how much console output
+ can be held before it overflows and starts discarding earlier
+ output. Normally there is very little output at this early stage,
+ unless debugging is enabled, so allow enough for ~10 lines of
+ text.
+
+ This is a useful feature if you are using a video console and
+ want to see the full boot output on the console. Without this
+ option only the post-relocation output will be displayed.
+
+config PRE_CON_BUF_ADDR
+ hex "Address of the pre-console buffer"
+ depends on PRE_CONSOLE_BUFFER
+ default 0x2f000000 if ARCH_SUNXI && MACH_SUN9I
+ default 0x4f000000 if ARCH_SUNXI && !MACH_SUN9I
+ help
+ This sets the start address of the pre-console buffer. This must
+ be in available memory and is accessed before relocation and
+ possibly before DRAM is set up. Therefore choose an address
+ carefully.
+
+ We should consider removing this option and allocating the memory
+ in board_init_f_init_reserve() instead.
+
+config CONSOLE_MUX
+ bool "Enable console multiplexing"
+ default y if DM_VIDEO || VIDEO || LCD
+ help
+ This allows multiple devices to be used for each console 'file'.
+ For example, stdout can be set to go to serial and video.
+ Similarly, stdin can be set to come from serial and keyboard.
+ Input can be provided from either source. Console multiplexing
+ adds a small amount of size to U-Boot. Changes to the environment
+ variables stdout, stdin and stderr will take effect immediately.
+
+config SYS_CONSOLE_IS_IN_ENV
+ bool "Select console devices from the environment"
+ default y if CONSOLE_MUX
+ help
+ This allows multiple input/output devices to be set at boot time.
+ For example, if stdout is set to "serial,video" then output will
+ be sent to both the serial and video devices on boot. The
+ environment variables can be updated after boot to change the
+ input/output devices.
+
+config SYS_CONSOLE_OVERWRITE_ROUTINE
+ bool "Allow board control over console overwriting"
+ help
+ If this is enabled, and the board-specific function
+ overwrite_console() returns 1, the stdin, stderr and stdout are
+ switched to the serial port, else the settings in the environment
+ are used. If this is not enabled, the console will not be switched
+ to serial.
+
+config SYS_CONSOLE_ENV_OVERWRITE
+ bool "Update environment variables during console init"
+ help
+ The console environment variables (stdout, stdin, stderr) can be
+ used to determine the correct console devices on start-up. This
+ option writes the console devices to these variables on console
+ start-up (after relocation). This causes the environment to be
+ updated to match the console devices actually chosen.
+
+config SYS_CONSOLE_INFO_QUIET
+ bool "Don't display the console devices on boot"
+ help
+ Normally U-Boot displays the current settings for stdout, stdin
+ and stderr on boot when the post-relocation console is set up.
+ Enable this option to supress this output. It can be obtained by
+ calling stdio_print_current_devices() from board code.
+
+config SYS_STDIO_DEREGISTER
+ bool "Allow deregistering stdio devices"
+ default y if USB_KEYBOARD
+ help
+ Generally there is no need to deregister stdio devices since they
+ are never deactivated. But if a stdio device is used which can be
+ removed (for example a USB keyboard) then this option can be
+ enabled to ensure this is handled correctly.
+
+endmenu
+
+config DEFAULT_FDT_FILE
+ string "Default fdt file"
+ help
+ This option is used to set the default fdt file to boot OS.
+
config SYS_NO_FLASH
bool "Disable support for parallel NOR flash"
default n
@@ -213,3 +372,21 @@
version as printed by the "version" command.
Any change to this variable will be reverted at the
next reset.
+
+config DISPLAY_CPUINFO
+ bool "Display information about the CPU during start up"
+ default y if ARM || BLACKFIN || NIOS2 || X86 || XTENSA
+ help
+ Display information about the CPU that U-Boot is running on
+ when U-Boot starts up. The function print_cpuinfo() is called
+ to do this.
+
+config DISPLAY_BOARDINFO
+ bool "Display information about the board during start up"
+ default y if ARM || M68K || MIPS || PPC || SPARC || XTENSA
+ help
+ Display information about the board that U-Boot is running on
+ when U-Boot starts up. The board function checkboard() is called
+ to do this.
+
+source "common/spl/Kconfig"
diff --git a/common/Makefile b/common/Makefile
index aa18d30..3719597 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -89,6 +89,8 @@
endif # !CONFIG_SPL_BUILD
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu.o
+obj-$(CONFIG_SPL_DFU_SUPPORT) += cli_hush.o
obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
@@ -99,10 +101,16 @@
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
# environment
-ifdef CONFIG_SPL_ENV_SUPPORT
+ifdef CONFIG_TPL_BUILD
+obj-$(CONFIG_TPL_ENV_SUPPORT) += env_attr.o
+obj-$(CONFIG_TPL_ENV_SUPPORT) += env_flags.o
+obj-$(CONFIG_TPL_ENV_SUPPORT) += env_callback.o
+else
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
+endif
+ifneq ($(CONFIG_TPL_ENV_SUPPORT)$(CONFIG_SPL_ENV_SUPPORT),)
obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
@@ -123,7 +131,11 @@
obj-$(CONFIG_HWCONFIG) += hwconfig.o
obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_TPL_BUILD
+obj-$(CONFIG_TPL_SERIAL_SUPPORT) += console.o
+else
obj-$(CONFIG_SPL_SERIAL_SUPPORT) += console.o
+endif
else
obj-y += console.o
endif
@@ -165,6 +177,7 @@
obj-y += cli.o
obj-$(CONFIG_CMDLINE) += cli_readline.o
+obj-$(CONFIG_CMD_DFU) += dfu.o
obj-y += command.o
obj-y += s_record.o
obj-y += xyzModem.o
diff --git a/common/board_f.c b/common/board_f.c
index da381db..cc8aee7 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -49,7 +49,7 @@
#include <trace.h>
#include <video.h>
#include <watchdog.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/sections.h>
#if defined(CONFIG_X86) || defined(CONFIG_ARC)
@@ -276,7 +276,7 @@
#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) || \
defined(CONFIG_XTENSA)
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
-#elif defined(CONFIG_NDS32)
+#elif defined(CONFIG_NDS32) || defined(CONFIG_SH)
gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
#elif defined(CONFIG_SYS_MONITOR_BASE)
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
@@ -290,6 +290,11 @@
return 0;
}
+__weak int mach_cpu_init(void)
+{
+ return 0;
+}
+
#ifdef CONFIG_SANDBOX
static int setup_ram_buf(void)
{
@@ -614,7 +619,8 @@
return 0;
}
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
+#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
+ defined(CONFIG_SH)
static int setup_board_part1(void)
{
bd_t *bd = gd->bd;
@@ -860,6 +866,7 @@
x86_fsp_init,
#endif
arch_cpu_init, /* basic arch cpu dependent setup */
+ mach_cpu_init, /* SoC/machine dependent CPU setup */
initf_dm,
arch_cpu_init_dm,
mark_bootstage, /* need timer, go after init dm */
@@ -878,7 +885,7 @@
#endif
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
- defined(CONFIG_SPARC)
+ defined(CONFIG_SH) || defined(CONFIG_SPARC)
timer_init, /* initialize timer */
#endif
#ifdef CONFIG_SYS_ALLOC_DPRAM
@@ -906,9 +913,6 @@
#ifdef CONFIG_SANDBOX
sandbox_early_getopt_check,
#endif
-#ifdef CONFIG_OF_CONTROL
- fdtdec_prepare_fdt,
-#endif
display_options, /* say that we are here */
display_text_info, /* show debugging info if required */
#if defined(CONFIG_MPC8260)
@@ -918,7 +922,7 @@
#if defined(CONFIG_MPC83xx)
prt_83xx_rsr,
#endif
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH)
checkcpu,
#endif
print_cpuinfo, /* display cpu info (and speed) */
@@ -942,7 +946,8 @@
announce_dram_init,
/* TODO: unify all these dram functions? */
#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \
- defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
+ defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || \
+ defined(CONFIG_SH)
dram_init, /* configure available RAM banks */
#endif
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
@@ -1020,7 +1025,8 @@
reserve_stacks,
setup_dram_config,
show_dram_config,
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
+#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
+ defined(CONFIG_SH)
setup_board_part1,
#endif
#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
@@ -1052,7 +1058,7 @@
{
#ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA
/*
- * For some archtectures, global data is initialized and used before
+ * For some architectures, global data is initialized and used before
* calling this function. The data should be preserved. For others,
* CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack
* here to host global data until relocation.
@@ -1064,7 +1070,7 @@
/*
* Clear global data before it is accessed at debug print
* in initcall_run_list. Otherwise the debug print probably
- * get the wrong vaule of gd->have_console.
+ * get the wrong value of gd->have_console.
*/
zero_global_data();
#endif
diff --git a/common/board_info.c b/common/board_info.c
index bd5dcfa..aa45e24 100644
--- a/common/board_info.c
+++ b/common/board_info.c
@@ -15,9 +15,9 @@
* If the root node of the DTB has a "model" property, show it.
* Then call checkboard().
*/
-int show_board_info(void)
+int __weak show_board_info(void)
{
-#if defined(CONFIG_OF_CONTROL) && !defined(CONFIG_CUSTOM_BOARDINFO)
+#ifdef CONFIG_OF_CONTROL
DECLARE_GLOBAL_DATA_PTR;
const char *model;
diff --git a/common/board_r.c b/common/board_r.c
index d959ad3..a373352 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -191,7 +191,7 @@
return 0;
}
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
static int initr_trap(void)
{
/*
@@ -620,7 +620,7 @@
}
#endif
-#if defined(CONFIG_SCSI)
+#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
static int initr_scsi(void)
{
puts("SCSI: ");
@@ -807,7 +807,7 @@
#ifdef CONFIG_NEEDS_MANUAL_RELOC
initr_manual_reloc_cmdtable,
#endif
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
initr_trap,
#endif
#ifdef CONFIG_ADDR_MAP
@@ -923,7 +923,7 @@
initr_ambapp_print,
#endif
#endif
-#ifdef CONFIG_SCSI
+#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
INIT_FUNC_WATCHDOG_RESET
initr_scsi,
#endif
diff --git a/common/bootm.c b/common/bootm.c
index a4d22a6..b2c0912 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -619,10 +619,8 @@
if (!ret && (states & BOOTM_STATE_FINDOS))
ret = bootm_find_os(cmdtp, flag, argc, argv);
- if (!ret && (states & BOOTM_STATE_FINDOTHER)) {
+ if (!ret && (states & BOOTM_STATE_FINDOTHER))
ret = bootm_find_other(cmdtp, flag, argc, argv);
- argc = 0; /* consume the args */
- }
/* Load the OS */
if (!ret && (states & BOOTM_STATE_LOADOS)) {
diff --git a/common/console.c b/common/console.c
index 12293f3..e1d8476 100644
--- a/common/console.c
+++ b/common/console.c
@@ -16,6 +16,7 @@
#include <stdio_dev.h>
#include <exports.h>
#include <environment.h>
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -65,11 +66,11 @@
static int on_silent(const char *name, const char *value, enum env_op op,
int flags)
{
-#ifndef CONFIG_SILENT_CONSOLE_UPDATE_ON_SET
+#if !CONFIG_IS_ENABLED(CONFIG_SILENT_CONSOLE_UPDATE_ON_SET)
if (flags & H_INTERACTIVE)
return 0;
#endif
-#ifndef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#if !CONFIG_IS_ENABLED(CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC)
if ((flags & H_INTERACTIVE) == 0)
return 0;
#endif
@@ -201,7 +202,7 @@
}
}
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
+#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
static void console_puts_noserial(int file, const char *s)
{
int i;
@@ -247,7 +248,7 @@
stdio_devices[file]->putc(stdio_devices[file], c);
}
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
+#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
static inline void console_puts_noserial(int file, const char *s)
{
if (strcmp(stdio_devices[file]->name, "serial") != 0)
@@ -294,6 +295,7 @@
* Effectively poll for input wherever it may be available.
*/
for (;;) {
+ WATCHDOG_RESET();
/*
* Upper layer may have already called tstc() so
* check for that first.
@@ -413,7 +415,7 @@
#define PRE_CONSOLE_FLUSHPOINT1_SERIAL 0
#define PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL 1
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
+#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
#define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)CONFIG_PRE_CON_BUF_SZ)
static void pre_console_putc(const char c)
@@ -687,15 +689,22 @@
return -1;
}
+static void console_update_silent(void)
+{
+#ifdef CONFIG_SILENT_CONSOLE
+ if (getenv("silent") != NULL)
+ gd->flags |= GD_FLG_SILENT;
+ else
+ gd->flags &= ~GD_FLG_SILENT;
+#endif
+}
+
/* Called before relocation - use serial functions */
int console_init_f(void)
{
gd->have_console = 1;
-#ifdef CONFIG_SILENT_CONSOLE
- if (getenv("silent") != NULL)
- gd->flags |= GD_FLG_SILENT;
-#endif
+ console_update_silent();
print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT1_SERIAL);
@@ -831,6 +840,8 @@
struct list_head *pos;
struct stdio_dev *dev;
+ console_update_silent();
+
#ifdef CONFIG_SPLASH_SCREEN
/*
* suppress all output if splash screen is enabled and we have
diff --git a/common/dfu.c b/common/dfu.c
new file mode 100644
index 0000000..0e9f5f5
--- /dev/null
+++ b/common/dfu.c
@@ -0,0 +1,96 @@
+/*
+ * dfu.c -- dfu command
+ *
+ * Copyright (C) 2015
+ * Lukasz Majewski <l.majewski@majess.pl>
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * authors: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <dfu.h>
+#include <console.h>
+#include <g_dnl.h>
+#include <usb.h>
+#include <net.h>
+
+int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget)
+{
+ bool dfu_reset = false;
+ int ret, i = 0;
+
+ ret = board_usb_init(usbctrl_index, USB_INIT_DEVICE);
+ if (ret) {
+ error("board usb init failed\n");
+ return CMD_RET_FAILURE;
+ }
+ g_dnl_clear_detach();
+ ret = g_dnl_register(usb_dnl_gadget);
+ if (ret) {
+ error("g_dnl_register failed");
+ return CMD_RET_FAILURE;
+ }
+
+ while (1) {
+ if (g_dnl_detach()) {
+ /*
+ * Check if USB bus reset is performed after detach,
+ * which indicates that -R switch has been passed to
+ * dfu-util. In this case reboot the device
+ */
+ if (dfu_usb_get_reset()) {
+ dfu_reset = true;
+ goto exit;
+ }
+
+ /*
+ * This extra number of usb_gadget_handle_interrupts()
+ * calls is necessary to assure correct transmission
+ * completion with dfu-util
+ */
+ if (++i == 10000)
+ goto exit;
+ }
+
+ if (ctrlc())
+ goto exit;
+
+ if (dfu_get_defer_flush()) {
+ /*
+ * Call to usb_gadget_handle_interrupts() is necessary
+ * to act on ZLP OUT transaction from HOST PC after
+ * transmitting the whole file.
+ *
+ * If this ZLP OUT packet is NAK'ed, the HOST libusb
+ * function fails after timeout (by default it is set to
+ * 5 seconds). In such situation the dfu-util program
+ * exits with error message.
+ */
+ usb_gadget_handle_interrupts(usbctrl_index);
+ ret = dfu_flush(dfu_get_defer_flush(), NULL, 0, 0);
+ dfu_set_defer_flush(NULL);
+ if (ret) {
+ error("Deferred dfu_flush() failed!");
+ goto exit;
+ }
+ }
+
+ WATCHDOG_RESET();
+ usb_gadget_handle_interrupts(usbctrl_index);
+ }
+exit:
+ g_dnl_unregister();
+ board_usb_cleanup(usbctrl_index, USB_INIT_DEVICE);
+
+ if (dfu_reset)
+ run_command("reset", 0);
+
+ g_dnl_clear_detach();
+
+ return ret;
+}
diff --git a/common/env_common.c b/common/env_common.c
index 560cad0..7fb62e8 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -226,7 +226,7 @@
return 0;
}
-/* Emport the environment and generate CRC for it. */
+/* Export the environment and generate CRC for it. */
int env_export(env_t *env_out)
{
char *res;
diff --git a/common/env_embedded.c b/common/env_embedded.c
index 56a13cb..b368fda 100644
--- a/common/env_embedded.c
+++ b/common/env_embedded.c
@@ -5,6 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/kconfig.h>
+
#ifndef __ASSEMBLY__
#define __ASSEMBLY__ /* Dirty trick to get only #defines */
#endif
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 3dff263..d6b5585 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -14,8 +14,17 @@
#include <mmc.h>
#include <div64.h>
+/*
+ * FIXME: Ensure we always set these names via Kconfig once xxx_PARTITION is
+ * migrated
+ */
#ifndef CONFIG_FASTBOOT_GPT_NAME
-#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
+#define CONFIG_FASTBOOT_GPT_NAME "gpt"
+#endif
+
+
+#ifndef CONFIG_FASTBOOT_MBR_NAME
+#define CONFIG_FASTBOOT_MBR_NAME "mbr"
#endif
#define FASTBOOT_MAX_BLK_WRITE 16384
@@ -25,12 +34,12 @@
struct blk_desc *dev_desc;
};
-static int part_get_info_efi_by_name_or_alias(struct blk_desc *dev_desc,
+static int part_get_info_by_name_or_alias(struct blk_desc *dev_desc,
const char *name, disk_partition_t *info)
{
int ret;
- ret = part_get_info_efi_by_name(dev_desc, name, info);
+ ret = part_get_info_by_name(dev_desc, name, info);
if (ret) {
/* strlen("fastboot_partition_alias_") + 32(part_name) + 1 */
char env_alias_name[25 + 32 + 1];
@@ -41,7 +50,7 @@
strncat(env_alias_name, name, 32);
aliased_part_name = getenv(env_alias_name);
if (aliased_part_name != NULL)
- ret = part_get_info_efi_by_name(dev_desc,
+ ret = part_get_info_by_name(dev_desc,
aliased_part_name, info);
}
return ret;
@@ -130,6 +139,7 @@
return;
}
+#ifdef CONFIG_EFI_PARTITION
if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) {
printf("%s: updating MBR, Primary and Backup GPT(s)\n",
__func__);
@@ -141,14 +151,37 @@
}
if (write_mbr_and_gpt_partitions(dev_desc, download_buffer)) {
printf("%s: writing GPT partitions failed\n", __func__);
- fastboot_fail(
- "writing GPT partitions failed", response);
+ fastboot_fail("writing GPT partitions failed",
+ response);
return;
}
printf("........ success\n");
fastboot_okay("", response);
return;
- } else if (part_get_info_efi_by_name_or_alias(dev_desc, cmd, &info)) {
+ }
+#endif
+
+#ifdef CONFIG_DOS_PARTITION
+ if (strcmp(cmd, CONFIG_FASTBOOT_MBR_NAME) == 0) {
+ printf("%s: updating MBR\n", __func__);
+ if (is_valid_dos_buf(download_buffer)) {
+ printf("%s: invalid MBR - refusing to write to flash\n",
+ __func__);
+ fastboot_fail("invalid MBR partition", response);
+ return;
+ }
+ if (write_mbr_partition(dev_desc, download_buffer)) {
+ printf("%s: writing MBR partition failed\n", __func__);
+ fastboot_fail("writing MBR partition failed", response);
+ return;
+ }
+ printf("........ success\n");
+ fastboot_okay("", response);
+ return;
+ }
+#endif
+
+ if (part_get_info_by_name_or_alias(dev_desc, cmd, &info)) {
error("cannot find partition: '%s'\n", cmd);
fastboot_fail("cannot find partition", response);
return;
@@ -199,7 +232,7 @@
return;
}
- ret = part_get_info_efi_by_name_or_alias(dev_desc, cmd, &info);
+ ret = part_get_info_by_name_or_alias(dev_desc, cmd, &info);
if (ret) {
error("cannot find partition: '%s'", cmd);
fastboot_fail("cannot find partition", response);
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 2020586..c9f7019 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -381,6 +381,7 @@
do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
}
+#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
/*
* fdt_pack_reg - pack address and size array into the "reg"-suitable stream
*/
@@ -459,6 +460,7 @@
}
return 0;
}
+#endif
int fdt_fixup_memory(void *blob, u64 start, u64 size)
{
@@ -523,7 +525,7 @@
}
/* Resize the fdt to its actual size + a bit of padding */
-int fdt_shrink_to_minimum(void *blob)
+int fdt_shrink_to_minimum(void *blob, uint extrasize)
{
int i;
uint64_t addr, size;
@@ -551,6 +553,7 @@
actualsize = fdt_off_dt_strings(blob) +
fdt_size_dt_strings(blob) + 5 * sizeof(struct fdt_reserve_entry);
+ actualsize += extrasize;
/* Make it so the fdt ends on a page boundary */
actualsize = ALIGN(actualsize + ((uintptr_t)blob & 0xfff), 0x1000);
actualsize = actualsize - ((uintptr_t)blob & 0xfff);
diff --git a/common/hash.c b/common/hash.c
index 41de4df..b645298 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -17,7 +17,7 @@
#include <mapmem.h>
#include <hw_sha.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#else
#include "mkimage.h"
#include <time.h>
diff --git a/common/image-fdt.c b/common/image-fdt.c
index d6ee225..e7540be 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -285,7 +285,7 @@
fdt_noffset = fit_get_node_from_config(images,
FIT_FDT_PROP,
fdt_addr);
- if (fdt_noffset == -ENOLINK)
+ if (fdt_noffset == -ENOENT)
return 0;
else if (fdt_noffset < 0)
return 1;
@@ -474,12 +474,10 @@
printf("ERROR: /chosen node create failed\n");
goto err;
}
-#ifdef CONFIG_ARCH_FIXUP_FDT
if (arch_fixup_fdt(blob) < 0) {
printf("ERROR: arch-specific fdt fixup failed\n");
goto err;
}
-#endif
if (IMAGE_OF_BOARD_SETUP) {
fdt_ret = ft_board_setup(blob, gd->bd);
if (fdt_ret) {
@@ -503,7 +501,7 @@
lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob,
(phys_size_t)fdt_totalsize(blob));
- ret = fdt_shrink_to_minimum(blob);
+ ret = fdt_shrink_to_minimum(blob, 0);
if (ret < 0)
goto err;
of_size = ret;
diff --git a/common/image-fit.c b/common/image-fit.c
index 9ce68f1..95d8bf4 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -14,6 +14,7 @@
#include <time.h>
#else
#include <linux/compiler.h>
+#include <linux/kconfig.h>
#include <common.h>
#include <errno.h>
#include <mapmem.h>
@@ -1026,7 +1027,7 @@
}
/* Process all hash subnodes of the component image node */
- fdt_for_each_subnode(fit, noffset, image_noffset) {
+ fdt_for_each_subnode(noffset, fit, image_noffset) {
const char *name = fit_get_name(fit, noffset, NULL);
/*
@@ -1161,11 +1162,18 @@
int fit_image_check_arch(const void *fit, int noffset, uint8_t arch)
{
uint8_t image_arch;
+ int aarch32_support = 0;
+
+#ifdef CONFIG_ARM64_SUPPORT_AARCH32
+ aarch32_support = 1;
+#endif
if (fit_image_get_arch(fit, noffset, &image_arch))
return 0;
return (arch == image_arch) ||
- (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64);
+ (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64) ||
+ (arch == IH_ARCH_ARM64 && image_arch == IH_ARCH_ARM &&
+ aarch32_support);
}
/**
@@ -1457,7 +1465,7 @@
void fit_conf_print(const void *fit, int noffset, const char *p)
{
char *desc;
- char *uname;
+ const char *uname;
int ret;
int loadables_index;
@@ -1469,7 +1477,7 @@
else
printf("%s\n", desc);
- uname = (char *)fdt_getprop(fit, noffset, FIT_KERNEL_PROP, NULL);
+ uname = fdt_getprop(fit, noffset, FIT_KERNEL_PROP, NULL);
printf("%s Kernel: ", p);
if (uname == NULL)
printf("unavailable\n");
@@ -1477,26 +1485,23 @@
printf("%s\n", uname);
/* Optional properties */
- uname = (char *)fdt_getprop(fit, noffset, FIT_RAMDISK_PROP, NULL);
+ uname = fdt_getprop(fit, noffset, FIT_RAMDISK_PROP, NULL);
if (uname)
printf("%s Init Ramdisk: %s\n", p, uname);
- uname = (char *)fdt_getprop(fit, noffset, FIT_FDT_PROP, NULL);
+ uname = fdt_getprop(fit, noffset, FIT_FDT_PROP, NULL);
if (uname)
printf("%s FDT: %s\n", p, uname);
- uname = (char *)fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
+ uname = fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
if (uname)
printf("%s FPGA: %s\n", p, uname);
/* Print out all of the specified loadables */
for (loadables_index = 0;
- fdt_get_string_index(fit, noffset,
- FIT_LOADABLE_PROP,
- loadables_index,
- (const char **)&uname) == 0;
- loadables_index++)
- {
+ uname = fdt_stringlist_get(fit, noffset, FIT_LOADABLE_PROP,
+ loadables_index, NULL), uname;
+ loadables_index++) {
if (loadables_index == 0) {
printf("%s Loadables: ", p);
} else {
@@ -1508,12 +1513,6 @@
static int fit_image_select(const void *fit, int rd_noffset, int verify)
{
-#if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS)
- const void *data;
- size_t size;
- int ret;
-#endif
-
fit_image_print(fit, rd_noffset, " ");
if (verify) {
@@ -1525,23 +1524,6 @@
puts("OK\n");
}
-#if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS)
- ret = fit_image_get_data(fit, rd_noffset, &data, &size);
- if (ret)
- return ret;
-
- /* perform any post-processing on the image data */
- board_fit_image_post_process((void **)&data, &size);
-
- /*
- * update U-Boot's understanding of the "data" property start address
- * and size according to the performed post-processing
- */
- ret = fdt_setprop((void *)fit, rd_noffset, FIT_DATA_PROP, data, size);
- if (ret)
- return ret;
-#endif
-
return 0;
}
@@ -1560,7 +1542,7 @@
cfg_noffset = fit_conf_get_node(fit_hdr, images->fit_uname_cfg);
if (cfg_noffset < 0) {
debug("* %s: no such config\n", prop_name);
- return -ENOENT;
+ return -EINVAL;
}
noffset = fit_conf_get_prop_node(fit_hdr, cfg_noffset, prop_name);
@@ -1617,6 +1599,9 @@
int type_ok, os_ok;
ulong load, data, len;
uint8_t os;
+#ifndef USE_HOSTCC
+ uint8_t os_arch;
+#endif
const char *prop_name;
int ret;
@@ -1700,6 +1685,12 @@
return -ENOEXEC;
}
#endif
+
+#ifndef USE_HOSTCC
+ fit_image_get_arch(fit, noffset, &os_arch);
+ images->os.arch = os_arch;
+#endif
+
if (image_type == IH_TYPE_FLATDT &&
!fit_image_check_comp(fit, noffset, IH_COMP_NONE)) {
puts("FDT image is compressed");
@@ -1741,6 +1732,12 @@
bootstage_error(bootstage_id + BOOTSTAGE_SUB_GET_DATA);
return -ENOENT;
}
+
+#if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS)
+ /* perform any post-processing on the image data */
+ board_fit_image_post_process((void **)&buf, &size);
+#endif
+
len = (ulong)size;
/* verify that image data is a proper FDT blob */
diff --git a/common/image-sig.c b/common/image-sig.c
index eda5e13..455f2b9 100644
--- a/common/image-sig.c
+++ b/common/image-sig.c
@@ -34,68 +34,74 @@
{
"sha1",
SHA1_SUM_LEN,
- RSA2048_BYTES,
+ SHA1_DER_LEN,
+ sha1_der_prefix,
#if IMAGE_ENABLE_SIGN
EVP_sha1,
#endif
hash_calculate,
- padding_sha1_rsa2048,
},
{
"sha256",
SHA256_SUM_LEN,
+ SHA256_DER_LEN,
+ sha256_der_prefix,
+#if IMAGE_ENABLE_SIGN
+ EVP_sha256,
+#endif
+ hash_calculate,
+ }
+
+};
+
+struct crypto_algo crypto_algos[] = {
+ {
+ "rsa2048",
RSA2048_BYTES,
-#if IMAGE_ENABLE_SIGN
- EVP_sha256,
-#endif
- hash_calculate,
- padding_sha256_rsa2048,
+ rsa_sign,
+ rsa_add_verify_data,
+ rsa_verify,
},
{
- "sha256",
- SHA256_SUM_LEN,
+ "rsa4096",
RSA4096_BYTES,
-#if IMAGE_ENABLE_SIGN
- EVP_sha256,
-#endif
- hash_calculate,
- padding_sha256_rsa4096,
+ rsa_sign,
+ rsa_add_verify_data,
+ rsa_verify,
}
};
-struct image_sig_algo image_sig_algos[] = {
- {
- "sha1,rsa2048",
- rsa_sign,
- rsa_add_verify_data,
- rsa_verify,
- &checksum_algos[0],
- },
- {
- "sha256,rsa2048",
- rsa_sign,
- rsa_add_verify_data,
- rsa_verify,
- &checksum_algos[1],
- },
- {
- "sha256,rsa4096",
- rsa_sign,
- rsa_add_verify_data,
- rsa_verify,
- &checksum_algos[2],
- }
-
-};
-
-struct image_sig_algo *image_get_sig_algo(const char *name)
+struct checksum_algo *image_get_checksum_algo(const char *full_name)
{
int i;
+ const char *name;
- for (i = 0; i < ARRAY_SIZE(image_sig_algos); i++) {
- if (!strcmp(image_sig_algos[i].name, name))
- return &image_sig_algos[i];
+ for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
+ name = checksum_algos[i].name;
+ /* Make sure names match and next char is a comma */
+ if (!strncmp(name, full_name, strlen(name)) &&
+ full_name[strlen(name)] == ',')
+ return &checksum_algos[i];
+ }
+
+ return NULL;
+}
+
+struct crypto_algo *image_get_crypto_algo(const char *full_name)
+{
+ int i;
+ const char *name;
+
+ /* Move name to after the comma */
+ name = strchr(full_name, ',');
+ if (!name)
+ return NULL;
+ name += 1;
+
+ for (i = 0; i < ARRAY_SIZE(crypto_algos); i++) {
+ if (!strcmp(crypto_algos[i].name, name))
+ return &crypto_algos[i];
}
return NULL;
@@ -159,12 +165,14 @@
info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
info->fit = (void *)fit;
info->node_offset = noffset;
- info->algo = image_get_sig_algo(algo_name);
+ info->name = algo_name;
+ info->checksum = image_get_checksum_algo(algo_name);
+ info->crypto = image_get_crypto_algo(algo_name);
info->fdt_blob = gd_fdt_blob();
info->required_keynode = required_keynode;
printf("%s:%s", algo_name, info->keyname);
- if (!info->algo) {
+ if (!info->checksum || !info->crypto) {
*err_msgp = "Unknown signature algorithm";
return -1;
}
@@ -194,7 +202,7 @@
region.data = data;
region.size = size;
- if (info.algo->verify(&info, ®ion, 1, fit_value, fit_value_len)) {
+ if (info.crypto->verify(&info, ®ion, 1, fit_value, fit_value_len)) {
*err_msgp = "Verification failed";
return -1;
}
@@ -212,7 +220,7 @@
int ret;
/* Process all hash subnodes of the component image node */
- fdt_for_each_subnode(fit, noffset, image_noffset) {
+ fdt_for_each_subnode(noffset, fit, image_noffset) {
const char *name = fit_get_name(fit, noffset, NULL);
if (!strncmp(name, FIT_SIG_NODENAME,
@@ -260,7 +268,7 @@
return 0;
}
- fdt_for_each_subnode(sig_blob, noffset, sig_node) {
+ fdt_for_each_subnode(noffset, sig_blob, sig_node) {
const char *required;
int ret;
@@ -375,8 +383,8 @@
struct image_region region[count];
fit_region_make_list(fit, fdt_regions, count, region);
- if (info.algo->verify(&info, region, count, fit_value,
- fit_value_len)) {
+ if (info.crypto->verify(&info, region, count, fit_value,
+ fit_value_len)) {
*err_msgp = "Verification failed";
return -1;
}
@@ -393,7 +401,7 @@
int ret;
/* Process all hash subnodes of the component conf node */
- fdt_for_each_subnode(fit, noffset, conf_noffset) {
+ fdt_for_each_subnode(noffset, fit, conf_noffset) {
const char *name = fit_get_name(fit, noffset, NULL);
if (!strncmp(name, FIT_SIG_NODENAME,
@@ -438,7 +446,7 @@
return 0;
}
- fdt_for_each_subnode(sig_blob, noffset, sig_node) {
+ fdt_for_each_subnode(noffset, sig_blob, sig_node) {
const char *required;
int ret;
diff --git a/common/image.c b/common/image.c
index 7ad04ca..8c35327 100644
--- a/common/image.c
+++ b/common/image.c
@@ -38,7 +38,7 @@
#include <u-boot/md5.h>
#include <u-boot/sha1.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#ifdef CONFIG_CMD_BDI
@@ -161,9 +161,12 @@
{ IH_TYPE_RKIMAGE, "rkimage", "Rockchip Boot Image" },
{ IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" },
{ IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" },
+ { IH_TYPE_VYBRIDIMAGE, "vybridimage", "Vybrid Boot Image", },
{ IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" },
{ IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" },
{ IH_TYPE_FPGA, "fpga", "FPGA Image" },
+ { IH_TYPE_TEE, "tee", "Trusted Execution Environment Image",},
+ { IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" },
{ -1, "", "", },
};
@@ -363,6 +366,11 @@
printf("%s Offset = 0x%08lx\n", p, data);
}
}
+ } else if (image_check_type(hdr, IH_TYPE_FIRMWARE_IVT)) {
+ printf("HAB Blocks: 0x%08x 0x0000 0x%08x\n",
+ image_get_load(hdr) - image_get_header_size(),
+ image_get_size(hdr) + image_get_header_size()
+ - 0x1FE0);
}
}
@@ -586,10 +594,12 @@
static const char *unknown_msg(enum ih_category category)
{
+ static const char unknown_str[] = "Unknown ";
static char msg[30];
- strcpy(msg, "Unknown ");
- strcat(msg, table_info[category].desc);
+ strcpy(msg, unknown_str);
+ strncat(msg, table_info[category].desc,
+ sizeof(msg) - sizeof(unknown_str));
return msg;
}
@@ -1078,7 +1088,7 @@
rd_addr = map_to_sysmem(images->fit_hdr_os);
rd_noffset = fit_get_node_from_config(images,
FIT_RAMDISK_PROP, rd_addr);
- if (rd_noffset == -ENOLINK)
+ if (rd_noffset == -ENOENT)
return 0;
else if (rd_noffset < 0)
return 1;
@@ -1304,7 +1314,7 @@
void *buf;
int conf_noffset;
int fit_img_result;
- char *uname, *name;
+ const char *uname, *name;
int err;
int devnum = 0; /* TODO support multi fpga platforms */
const fpga_desc * const desc = fpga_get_desc(devnum);
@@ -1331,9 +1341,9 @@
case IMAGE_FORMAT_FIT:
conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
- err = fdt_get_string_index(buf, conf_noffset, FIT_FPGA_PROP, 0,
- (const char **)&uname);
- if (err < 0) {
+ uname = fdt_stringlist_get(buf, conf_noffset, FIT_FPGA_PROP, 0,
+ NULL);
+ if (!uname) {
debug("## FPGA image is not specified\n");
return 0;
}
@@ -1371,11 +1381,10 @@
img_len, BIT_PARTIAL);
}
- printf(" Programming %s bitstream... ", name);
if (err)
- printf("failed\n");
- else
- printf("OK\n");
+ return err;
+
+ printf(" Programming %s bitstream... OK\n", name);
break;
default:
printf("The given image format is not supported (corrupt?)\n");
@@ -1386,6 +1395,23 @@
}
#endif
+static void fit_loadable_process(uint8_t img_type,
+ ulong img_data,
+ ulong img_len)
+{
+ int i;
+ const unsigned int count =
+ ll_entry_count(struct fit_loadable_tbl, fit_loadable);
+ struct fit_loadable_tbl *fit_loadable_handler =
+ ll_entry_start(struct fit_loadable_tbl, fit_loadable);
+ /* For each loadable handler */
+ for (i = 0; i < count; i++, fit_loadable_handler++)
+ /* matching this type */
+ if (fit_loadable_handler->type == img_type)
+ /* call that handler with this image data */
+ fit_loadable_handler->handler(img_data, img_len);
+}
+
int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, const ulong *ld_start, ulong * const ld_len)
{
@@ -1403,7 +1429,8 @@
int loadables_index;
int conf_noffset;
int fit_img_result;
- char *uname;
+ const char *uname;
+ uint8_t img_type;
/* Check to see if the images struct has a FIT configuration */
if (!genimg_has_config(images)) {
@@ -1427,15 +1454,14 @@
conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
for (loadables_index = 0;
- fdt_get_string_index(buf, conf_noffset,
- FIT_LOADABLE_PROP,
- loadables_index,
- (const char **)&uname) == 0;
+ uname = fdt_stringlist_get(buf, conf_noffset,
+ FIT_LOADABLE_PROP, loadables_index,
+ NULL), uname;
loadables_index++)
{
fit_img_result = fit_image_load(images,
tmp_img_addr,
- (const char **)&uname,
+ &uname,
&(images->fit_uname_cfg), arch,
IH_TYPE_LOADABLE,
BOOTSTAGE_ID_FIT_LOADABLE_START,
@@ -1445,6 +1471,21 @@
/* Something went wrong! */
return fit_img_result;
}
+
+ fit_img_result = fit_image_get_node(buf, uname);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+ fit_img_result = fit_image_get_type(buf,
+ fit_img_result,
+ &img_type);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ fit_loadable_process(img_type, img_data, img_len);
}
break;
default:
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index d8ebb38..8eb0f76 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -107,6 +107,18 @@
return 0;
}
+int mdio_register_seq(struct mii_dev *bus, int seq)
+{
+ int ret;
+
+ /* Setup a unique name for each mdio bus */
+ ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq);
+ if (ret < 0)
+ return ret;
+
+ return mdio_register(bus);
+}
+
int mdio_unregister(struct mii_dev *bus)
{
if (!bus)
@@ -135,7 +147,7 @@
struct phy_device *phydev = bus->phymap[i];
if (phydev) {
- printf("%d - %s", i, phydev->drv->name);
+ printf("%x - %s", i, phydev->drv->name);
if (phydev->dev)
printf(" <--> %s\n", phydev->dev->name);
diff --git a/common/sata.c b/common/sata.c
index 88f08c9..42ff5c7 100644
--- a/common/sata.c
+++ b/common/sata.c
@@ -51,7 +51,7 @@
int __sata_initialize(void)
{
- int rc;
+ int rc, ret = -1;
int i;
for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
@@ -71,12 +71,14 @@
if (!rc) {
rc = scan_sata(i);
if (!rc && sata_dev_desc[i].lba > 0 &&
- sata_dev_desc[i].blksz > 0)
+ sata_dev_desc[i].blksz > 0) {
part_init(&sata_dev_desc[i]);
+ ret = i;
+ }
}
}
- return rc;
+ return ret;
}
int sata_initialize(void) __attribute__((weak, alias("__sata_initialize")));
diff --git a/common/scsi.c b/common/scsi.c
index dbbf404..e7efa5a 100644
--- a/common/scsi.c
+++ b/common/scsi.c
@@ -10,7 +10,10 @@
#include <inttypes.h>
#include <pci.h>
#include <scsi.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#if !defined(CONFIG_DM_SCSI)
#ifdef CONFIG_SCSI_DEV_LIST
#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
#else
@@ -31,6 +34,7 @@
#endif
#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
#endif
+#endif
#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
@@ -39,11 +43,13 @@
static unsigned char tempbuff[512]; /* temporary data buffer */
+#if !defined(CONFIG_DM_SCSI)
static int scsi_max_devs; /* number of highest available scsi device */
static int scsi_curr_dev; /* current device */
static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
+#endif
/* almost the maximum amount of the scsi_ext command.. */
#define SCSI_MAX_READ_BLK 0xFFFF
@@ -78,7 +84,8 @@
}
#endif
-void scsi_setup_read_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+static void scsi_setup_read_ext(ccb *pccb, lbaint_t start,
+ unsigned short blocks)
{
pccb->cmd[0] = SCSI_READ10;
pccb->cmd[1] = pccb->lun << 5;
@@ -98,7 +105,8 @@
pccb->cmd[7], pccb->cmd[8]);
}
-void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+static void scsi_setup_write_ext(ccb *pccb, lbaint_t start,
+ unsigned short blocks)
{
pccb->cmd[0] = SCSI_WRITE10;
pccb->cmd[1] = pccb->lun << 5;
@@ -119,23 +127,7 @@
pccb->cmd[7], pccb->cmd[8]);
}
-void scsi_setup_read6(ccb *pccb, lbaint_t start, unsigned short blocks)
-{
- pccb->cmd[0] = SCSI_READ6;
- pccb->cmd[1] = pccb->lun << 5 | ((unsigned char)(start >> 16) & 0x1f);
- pccb->cmd[2] = (unsigned char)(start >> 8) & 0xff;
- pccb->cmd[3] = (unsigned char)start & 0xff;
- pccb->cmd[4] = (unsigned char)blocks & 0xff;
- pccb->cmd[5] = 0;
- pccb->cmdlen = 6;
- pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
- debug("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
- pccb->cmd[0], pccb->cmd[1],
- pccb->cmd[2], pccb->cmd[3], pccb->cmd[4]);
-}
-
-
-void scsi_setup_inquiry(ccb *pccb)
+static void scsi_setup_inquiry(ccb *pccb)
{
pccb->cmd[0] = SCSI_INQUIRY;
pccb->cmd[1] = pccb->lun << 5;
@@ -161,43 +153,41 @@
#ifdef CONFIG_BLK
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
#endif
- int device = block_dev->devnum;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks = 0;
ccb *pccb = (ccb *)&tempccb;
- device &= 0xff;
/* Setup device */
- pccb->target = scsi_dev_desc[device].target;
- pccb->lun = scsi_dev_desc[device].lun;
+ pccb->target = block_dev->target;
+ pccb->lun = block_dev->lun;
buf_addr = (unsigned long)buffer;
start = blknr;
blks = blkcnt;
debug("\nscsi_read: dev %d startblk " LBAF
", blccnt " LBAF " buffer %lx\n",
- device, start, blks, (unsigned long)buffer);
+ block_dev->devnum, start, blks, (unsigned long)buffer);
do {
pccb->pdata = (unsigned char *)buf_addr;
#ifdef CONFIG_SYS_64BIT_LBA
if (start > SCSI_LBA48_READ) {
unsigned long blocks;
blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
- pccb->datalen = scsi_dev_desc[device].blksz * blocks;
+ pccb->datalen = block_dev->blksz * blocks;
scsi_setup_read16(pccb, start, blocks);
start += blocks;
blks -= blocks;
} else
#endif
if (blks > SCSI_MAX_READ_BLK) {
- pccb->datalen = scsi_dev_desc[device].blksz *
+ pccb->datalen = block_dev->blksz *
SCSI_MAX_READ_BLK;
smallblks = SCSI_MAX_READ_BLK;
scsi_setup_read_ext(pccb, start, smallblks);
start += SCSI_MAX_READ_BLK;
blks -= SCSI_MAX_READ_BLK;
} else {
- pccb->datalen = scsi_dev_desc[device].blksz * blks;
+ pccb->datalen = block_dev->blksz * blks;
smallblks = (unsigned short)blks;
scsi_setup_read_ext(pccb, start, smallblks);
start += blks;
@@ -236,33 +226,30 @@
#ifdef CONFIG_BLK
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
#endif
- int device = block_dev->devnum;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
ccb *pccb = (ccb *)&tempccb;
- device &= 0xff;
-
/* Setup device */
- pccb->target = scsi_dev_desc[device].target;
- pccb->lun = scsi_dev_desc[device].lun;
+ pccb->target = block_dev->target;
+ pccb->lun = block_dev->lun;
buf_addr = (unsigned long)buffer;
start = blknr;
blks = blkcnt;
debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
- __func__, device, start, blks, (unsigned long)buffer);
+ __func__, block_dev->devnum, start, blks, (unsigned long)buffer);
do {
pccb->pdata = (unsigned char *)buf_addr;
if (blks > SCSI_MAX_WRITE_BLK) {
- pccb->datalen = (scsi_dev_desc[device].blksz *
+ pccb->datalen = (block_dev->blksz *
SCSI_MAX_WRITE_BLK);
smallblks = SCSI_MAX_WRITE_BLK;
scsi_setup_write_ext(pccb, start, smallblks);
start += SCSI_MAX_WRITE_BLK;
blks -= SCSI_MAX_WRITE_BLK;
} else {
- pccb->datalen = scsi_dev_desc[device].blksz * blks;
+ pccb->datalen = block_dev->blksz * blks;
smallblks = (unsigned short)blks;
scsi_setup_write_ext(pccb, start, smallblks);
start += blks;
@@ -282,11 +269,6 @@
return blkcnt;
}
-int scsi_get_disk_count(void)
-{
- return scsi_max_devs;
-}
-
#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
void scsi_init(void)
{
@@ -347,7 +329,8 @@
/* copy src to dest, skipping leading and trailing blanks
* and null terminate the string
*/
-void scsi_ident_cpy(unsigned char *dest, unsigned char *src, unsigned int len)
+static void scsi_ident_cpy(unsigned char *dest, unsigned char *src,
+ unsigned int len)
{
int start, end;
@@ -368,21 +351,8 @@
*dest = '\0';
}
-
-/* Trim trailing blanks, and NUL-terminate string
- */
-void scsi_trim_trail(unsigned char *str, unsigned int len)
-{
- unsigned char *p = str + len - 1;
-
- while (len-- > 0) {
- *p-- = '\0';
- if (*p != ' ')
- return;
- }
-}
-
-int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
+static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
+ unsigned long *blksz)
{
*capacity = 0;
@@ -446,7 +416,7 @@
/*
* Some setup (fill-in) routines
*/
-void scsi_setup_test_unit_ready(ccb *pccb)
+static void scsi_setup_test_unit_ready(ccb *pccb)
{
pccb->cmd[0] = SCSI_TST_U_RDY;
pccb->cmd[1] = pccb->lun << 5;
@@ -458,103 +428,213 @@
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
}
-/*
- * (re)-scan the scsi bus and reports scsi device info
- * to the user if mode = 1
+/**
+ * scsi_init_dev_desc_priv - initialize only SCSI specific blk_desc properties
+ *
+ * @dev_desc: Block device description pointer
*/
-void scsi_scan(int mode)
+static void scsi_init_dev_desc_priv(struct blk_desc *dev_desc)
{
- unsigned char i, perq, modi, lun;
+ dev_desc->target = 0xff;
+ dev_desc->lun = 0xff;
+ dev_desc->log2blksz =
+ LOG2_INVALID(typeof(dev_desc->log2blksz));
+ dev_desc->type = DEV_TYPE_UNKNOWN;
+ dev_desc->vendor[0] = 0;
+ dev_desc->product[0] = 0;
+ dev_desc->revision[0] = 0;
+ dev_desc->removable = false;
+#ifndef CONFIG_BLK
+ dev_desc->block_read = scsi_read;
+ dev_desc->block_write = scsi_write;
+#endif
+}
+
+#if !defined(CONFIG_DM_SCSI)
+/**
+ * scsi_init_dev_desc - initialize all SCSI specific blk_desc properties
+ *
+ * @dev_desc: Block device description pointer
+ * @devnum: Device number
+ */
+static void scsi_init_dev_desc(struct blk_desc *dev_desc, int devnum)
+{
+ dev_desc->lba = 0;
+ dev_desc->blksz = 0;
+ dev_desc->if_type = IF_TYPE_SCSI;
+ dev_desc->devnum = devnum;
+ dev_desc->part_type = PART_TYPE_UNKNOWN;
+
+ scsi_init_dev_desc_priv(dev_desc);
+}
+#endif
+
+/**
+ * scsi_detect_dev - Detect scsi device
+ *
+ * @target: target id
+ * @dev_desc: block device description
+ *
+ * The scsi_detect_dev detects and fills a dev_desc structure when the device is
+ * detected. The LUN number is taken from the struct blk_desc *dev_desc.
+ *
+ * Return: 0 on success, error value otherwise
+ */
+static int scsi_detect_dev(int target, struct blk_desc *dev_desc)
+{
+ unsigned char perq, modi;
lbaint_t capacity;
unsigned long blksz;
ccb *pccb = (ccb *)&tempccb;
+ pccb->target = target;
+ pccb->lun = dev_desc->lun;
+ pccb->pdata = (unsigned char *)&tempbuff;
+ pccb->datalen = 512;
+ scsi_setup_inquiry(pccb);
+ if (scsi_exec(pccb) != true) {
+ if (pccb->contr_stat == SCSI_SEL_TIME_OUT) {
+ /*
+ * selection timeout => assuming no
+ * device present
+ */
+ debug("Selection timeout ID %d\n",
+ pccb->target);
+ return -ETIMEDOUT;
+ }
+ scsi_print_error(pccb);
+ return -ENODEV;
+ }
+ perq = tempbuff[0];
+ modi = tempbuff[1];
+ if ((perq & 0x1f) == 0x1f)
+ return -ENODEV; /* skip unknown devices */
+ if ((modi & 0x80) == 0x80) /* drive is removable */
+ dev_desc->removable = true;
+ /* get info for this device */
+ scsi_ident_cpy((unsigned char *)dev_desc->vendor,
+ &tempbuff[8], 8);
+ scsi_ident_cpy((unsigned char *)dev_desc->product,
+ &tempbuff[16], 16);
+ scsi_ident_cpy((unsigned char *)dev_desc->revision,
+ &tempbuff[32], 4);
+ dev_desc->target = pccb->target;
+ dev_desc->lun = pccb->lun;
+
+ pccb->datalen = 0;
+ scsi_setup_test_unit_ready(pccb);
+ if (scsi_exec(pccb) != true) {
+ if (dev_desc->removable) {
+ dev_desc->type = perq;
+ goto removable;
+ }
+ scsi_print_error(pccb);
+ return -EINVAL;
+ }
+ if (scsi_read_capacity(pccb, &capacity, &blksz)) {
+ scsi_print_error(pccb);
+ return -EINVAL;
+ }
+ dev_desc->lba = capacity;
+ dev_desc->blksz = blksz;
+ dev_desc->log2blksz = LOG2(dev_desc->blksz);
+ dev_desc->type = perq;
+ part_init(&dev_desc[0]);
+removable:
+ return 0;
+}
+
+/*
+ * (re)-scan the scsi bus and reports scsi device info
+ * to the user if mode = 1
+ */
+#if defined(CONFIG_DM_SCSI)
+int scsi_scan(int mode)
+{
+ unsigned char i, lun;
+ struct uclass *uc;
+ struct udevice *dev; /* SCSI controller */
+ int ret;
+
if (mode == 1)
printf("scanning bus for devices...\n");
- for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++) {
- scsi_dev_desc[i].target = 0xff;
- scsi_dev_desc[i].lun = 0xff;
- scsi_dev_desc[i].lba = 0;
- scsi_dev_desc[i].blksz = 0;
- scsi_dev_desc[i].log2blksz =
- LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
- scsi_dev_desc[i].type = DEV_TYPE_UNKNOWN;
- scsi_dev_desc[i].vendor[0] = 0;
- scsi_dev_desc[i].product[0] = 0;
- scsi_dev_desc[i].revision[0] = 0;
- scsi_dev_desc[i].removable = false;
- scsi_dev_desc[i].if_type = IF_TYPE_SCSI;
- scsi_dev_desc[i].devnum = i;
- scsi_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-#ifndef CONFIG_BLK
- scsi_dev_desc[i].block_read = scsi_read;
- scsi_dev_desc[i].block_write = scsi_write;
-#endif
- }
- scsi_max_devs = 0;
- for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
- pccb->target = i;
- for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
- pccb->lun = lun;
- pccb->pdata = (unsigned char *)&tempbuff;
- pccb->datalen = 512;
- scsi_setup_inquiry(pccb);
- if (scsi_exec(pccb) != true) {
- if (pccb->contr_stat == SCSI_SEL_TIME_OUT) {
- /*
- * selection timeout => assuming no
- * device present
- */
- debug("Selection timeout ID %d\n",
- pccb->target);
+
+ ret = uclass_get(UCLASS_SCSI, &uc);
+ if (ret)
+ return ret;
+
+ uclass_foreach_dev(dev, uc) {
+ struct scsi_platdata *plat; /* scsi controller platdata */
+
+ /* probe SCSI controller driver */
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+
+ /* Get controller platdata */
+ plat = dev_get_platdata(dev);
+
+ for (i = 0; i < plat->max_id; i++) {
+ for (lun = 0; lun < plat->max_lun; lun++) {
+ struct udevice *bdev; /* block device */
+ /* block device description */
+ struct blk_desc *bdesc;
+ char str[10];
+
+ /*
+ * Create only one block device and do detection
+ * to make sure that there won't be a lot of
+ * block devices created
+ */
+ snprintf(str, sizeof(str), "id%dlun%d", i, lun);
+ ret = blk_create_devicef(dev, "scsi_blk",
+ str, IF_TYPE_SCSI,
+ -1, 0, 0, &bdev);
+ if (ret) {
+ debug("Can't create device\n");
+ return ret;
+ }
+ bdesc = dev_get_uclass_platdata(bdev);
+
+ scsi_init_dev_desc_priv(bdesc);
+ bdesc->lun = lun;
+ ret = scsi_detect_dev(i, bdesc);
+ if (ret) {
+ device_unbind(bdev);
continue;
}
- scsi_print_error(pccb);
- continue;
- }
- perq = tempbuff[0];
- modi = tempbuff[1];
- if ((perq & 0x1f) == 0x1f)
- continue; /* skip unknown devices */
- if ((modi & 0x80) == 0x80) /* drive is removable */
- scsi_dev_desc[scsi_max_devs].removable = true;
- /* get info for this device */
- scsi_ident_cpy((unsigned char *)&scsi_dev_desc
- [scsi_max_devs].vendor[0],
- &tempbuff[8], 8);
- scsi_ident_cpy((unsigned char *)&scsi_dev_desc
- [scsi_max_devs].product[0],
- &tempbuff[16], 16);
- scsi_ident_cpy((unsigned char *)&scsi_dev_desc
- [scsi_max_devs].revision[0],
- &tempbuff[32], 4);
- scsi_dev_desc[scsi_max_devs].target = pccb->target;
- scsi_dev_desc[scsi_max_devs].lun = pccb->lun;
- pccb->datalen = 0;
- scsi_setup_test_unit_ready(pccb);
- if (scsi_exec(pccb) != true) {
- if (scsi_dev_desc[scsi_max_devs].removable) {
- scsi_dev_desc[scsi_max_devs].type =
- perq;
- goto removable;
- }
- scsi_print_error(pccb);
+ if (mode == 1) {
+ printf(" Device %d: ", 0);
+ dev_print(bdesc);
+ } /* if mode */
+ } /* next LUN */
+ }
+ }
+
+ return 0;
+}
+#else
+int scsi_scan(int mode)
+{
+ unsigned char i, lun;
+ int ret;
+
+ if (mode == 1)
+ printf("scanning bus for devices...\n");
+ for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++)
+ scsi_init_dev_desc(&scsi_dev_desc[i], i);
+
+ scsi_max_devs = 0;
+ for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
+ for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
+ scsi_dev_desc[scsi_max_devs].lun = lun;
+ ret = scsi_detect_dev(i, &scsi_dev_desc[scsi_max_devs]);
+ if (ret)
continue;
- }
- if (scsi_read_capacity(pccb, &capacity, &blksz)) {
- scsi_print_error(pccb);
- continue;
- }
- scsi_dev_desc[scsi_max_devs].lba = capacity;
- scsi_dev_desc[scsi_max_devs].blksz = blksz;
- scsi_dev_desc[scsi_max_devs].log2blksz =
- LOG2(scsi_dev_desc[scsi_max_devs].blksz);
- scsi_dev_desc[scsi_max_devs].type = perq;
- part_init(&scsi_dev_desc[scsi_max_devs]);
-removable:
+
if (mode == 1) {
- printf(" Device %d: ", scsi_max_devs);
+ printf(" Device %d: ", 0);
dev_print(&scsi_dev_desc[scsi_max_devs]);
} /* if mode */
scsi_max_devs++;
@@ -569,7 +649,9 @@
#ifndef CONFIG_SPL_BUILD
setenv_ulong("scsidevs", scsi_max_devs);
#endif
+ return 0;
}
+#endif
#ifdef CONFIG_BLK
static const struct blk_ops scsi_blk_ops = {
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
new file mode 100644
index 0000000..cba51f5d
--- /dev/null
+++ b/common/spl/Kconfig
@@ -0,0 +1,647 @@
+menu "SPL / TPL"
+
+config SUPPORT_SPL
+ bool
+
+config SUPPORT_TPL
+ bool
+
+config SPL
+ bool
+ depends on SUPPORT_SPL
+ prompt "Enable SPL"
+ help
+ If you want to build SPL as well as the normal image, say Y.
+
+config SPL_SYS_MALLOC_SIMPLE
+ bool
+ depends on SPL
+ prompt "Only use malloc_simple functions in the SPL"
+ help
+ Say Y here to only use the *_simple malloc functions from
+ malloc_simple.c, rather then using the versions from dlmalloc.c;
+ this will make the SPL binary smaller at the cost of more heap
+ usage as the *_simple malloc functions do not re-use free-ed mem.
+
+config SPL_STACK_R
+ depends on SPL
+ bool "Enable SDRAM location for SPL stack"
+ help
+ SPL starts off execution in SRAM and thus typically has only a small
+ stack available. Since SPL sets up DRAM while in its board_init_f()
+ function, it is possible for the stack to move there before
+ board_init_r() is reached. This option enables a special SDRAM
+ location for the SPL stack. U-Boot SPL switches to this after
+ board_init_f() completes, and before board_init_r() starts.
+
+config SPL_STACK_R_ADDR
+ depends on SPL_STACK_R
+ hex "SDRAM location for SPL stack"
+ help
+ Specify the address in SDRAM for the SPL stack. This will be set up
+ before board_init_r() is called.
+
+config SPL_STACK_R_MALLOC_SIMPLE_LEN
+ depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
+ hex "Size of malloc_simple heap after switching to DRAM SPL stack"
+ default 0x100000
+ help
+ Specify the amount of the stack to use as memory pool for
+ malloc_simple after switching the stack to DRAM. This may be set
+ to give board_init_r() a larger heap then the initial heap in
+ SRAM which is limited to SYS_MALLOC_F_LEN bytes.
+
+config SPL_SEPARATE_BSS
+ depends on SPL
+ bool "BSS section is in a different memory region from text"
+ help
+ Some platforms need a large BSS region in SPL and can provide this
+ because RAM is already set up. In this case BSS can be moved to RAM.
+ This option should then be enabled so that the correct device tree
+ location is used. Normally we put the device tree at the end of BSS
+ but with this option enabled, it goes at _image_binary_end.
+
+config SPL_DISPLAY_PRINT
+ depends on SPL
+ bool "Display a board-specific message in SPL"
+ help
+ If this option is enabled, U-Boot will call the function
+ spl_display_print() immediately after displaying the SPL console
+ banner ("U-Boot SPL ..."). This function should be provided by
+ the board.
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ bool "MMC raw mode: by sector"
+ depends on SPL
+ default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER ||ARCH_MX6 || \
+ ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \
+ ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
+ OMAP44XX || OMAP54XX || AM33XX || AM43XX
+ help
+ Use sector number for specifying U-Boot location on MMC/SD in
+ raw mode.
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ hex "Address on the MMC to load U-Boot from"
+ depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ default 0x50 if ARCH_SUNXI
+ default 0x75 if ARCH_DAVINCI
+ default 0x80 if ARCH_UNIPHIER
+ default 0x8a if ARCH_MX6
+ default 0x100 if ARCH_ROCKCHIP
+ default 0x140 if ARCH_MVEBU
+ default 0x200 if ARCH_SOCFPGA || ARCH_AT91
+ default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \
+ OMAP54XX || AM33XX || AM43XX
+ help
+ Address on the MMC to load U-Boot from, when the MMC is being used
+ in raw mode. Units: MMC sectors (1 sector = 512 bytes).
+
+config TPL
+ bool
+ depends on SPL && SUPPORT_TPL
+ prompt "Enable TPL"
+ help
+ If you want to build TPL as well as the normal image and SPL, say Y.
+
+config SPL_CRC32_SUPPORT
+ bool "Support CRC32"
+ depends on SPL_FIT
+ help
+ Enable this to support CRC32 in FIT images within SPL. This is a
+ 32-bit checksum value that can be used to verify images. This is
+ the least secure type of checksum, suitable for detected
+ accidental image corruption. For secure applications you should
+ consider SHA1 or SHA256.
+
+config SPL_MD5_SUPPORT
+ bool "Support MD5"
+ depends on SPL_FIT
+ help
+ Enable this to support MD5 in FIT images within SPL. An MD5
+ checksum is a 128-bit hash value used to check that the image
+ contents have not been corrupted. Note that MD5 is not considered
+ secure as it is possible (with a brute-force attack) to adjust the
+ image while still retaining the same MD5 hash value. For secure
+ applications where images may be changed maliciously, you should
+ consider SHA1 or SHA256.
+
+config SPL_SHA1_SUPPORT
+ bool "Support SHA1"
+ depends on SPL_FIT
+ help
+ Enable this to support SHA1 in FIT images within SPL. A SHA1
+ checksum is a 160-bit (20-byte) hash value used to check that the
+ image contents have not been corrupted or maliciously altered.
+ While SHA1 is fairly secure it is coming to the end of its life
+ due to the expanding computing power avaiable to brute-force
+ attacks. For more security, consider SHA256.
+
+config SPL_SHA256_SUPPORT
+ bool "Support SHA256"
+ depends on SPL_FIT
+ help
+ Enable this to support SHA256 in FIT images within SPL. A SHA256
+ checksum is a 256-bit (32-byte) hash value used to check that the
+ image contents have not been corrupted. SHA256 is recommended for
+ use in secure applications since (as at 2016) there is no known
+ feasible attack that could produce a 'collision' with differing
+ input data. Use this for the highest security. Note that only the
+ SHA256 variant is supported: SHA512 and others are not currently
+ supported in U-Boot.
+
+config SPL_CRYPTO_SUPPORT
+ bool "Support crypto drivers"
+ depends on SPL
+ help
+ Enable crypto drivers in SPL. These drivers can be used to
+ accelerate secure boot processing in secure applications. Enable
+ this option to build the drivers in drivers/crypto as part of an
+ SPL build.
+
+config SPL_HASH_SUPPORT
+ bool "Support hashing drivers"
+ depends on SPL
+ help
+ Enable hashing drivers in SPL. These drivers can be used to
+ accelerate secure boot processing in secure applications. Enable
+ this option to build system-specific drivers for hash acceleration
+ as part of an SPL build.
+
+config SPL_DMA_SUPPORT
+ bool "Support DMA drivers"
+ depends on SPL
+ help
+ Enable DMA (direct-memory-access) drivers in SPL. These drivers
+ can be used to handle memory-to-peripheral data transfer without
+ the CPU moving the data. Enable this option to build the drivers
+ in drivers/dma as part of an SPL build.
+
+config SPL_DRIVERS_MISC_SUPPORT
+ bool "Support misc drivers"
+ depends on SPL
+ help
+ Enable miscellaneous drivers in SPL. These drivers perform various
+ tasks that don't fall nicely into other categories, Enable this
+ option to build the drivers in drivers/misc as part of an SPL
+ build, for those that support building in SPL (not all drivers do).
+
+config SPL_ENV_SUPPORT
+ bool "Support an environment"
+ depends on SPL
+ help
+ Enable environment support in SPL. The U-Boot environment provides
+ a number of settings (essentially name/value pairs) which can
+ control many aspects of U-Boot's operation. Normally this is not
+ needed in SPL as it has a much simpler task with less
+ configuration. But some boards use this to support 'Falcon' boot
+ on EXT2 and FAT, where SPL boots directly into Linux without
+ starting U-Boot first. Enabling this option will make getenv()
+ and setenv() available in SPL.
+
+config SPL_SAVEENV
+ bool "Support save environment"
+ depends on SPL && SPL_ENV_SUPPORT
+ help
+ Enable save environment support in SPL after setenv. By default
+ the saveenv option is not provided in SPL, but some boards need
+ this support in 'Falcon' boot, where SPL need to boot from
+ different images based on environment variable set by OS. For
+ example OS may set "reboot_image" environment variable to
+ "recovery" inorder to boot recovery image by SPL. The SPL read
+ "reboot_image" and act accordingly and change the reboot_image
+ to default mode using setenv and save the environemnt.
+
+config SPL_ETH_SUPPORT
+ bool "Support Ethernet"
+ depends on SPL_ENV_SUPPORT
+ help
+ Enable access to the network subsystem and associated Ethernet
+ drivers in SPL. This permits SPL to load U-Boot over an Ethernet
+ link rather than from an on-board peripheral. Environment support
+ is required since the network stack uses a number of environment
+ variables. See also SPL_NET_SUPPORT.
+
+config SPL_EXT_SUPPORT
+ bool "Support EXT filesystems"
+ depends on SPL
+ help
+ Enable support for EXT2/3/4 filesystems with SPL. This permits
+ U-Boot (or Linux in Falcon mode) to be loaded from an EXT
+ filesystem from within SPL. Support for the underlying block
+ device (e.g. MMC or USB) must be enabled separately.
+
+config SPL_FAT_SUPPORT
+ bool "Support FAT filesystems"
+ depends on SPL
+ help
+ Enable support for FAT and VFAT filesystems with SPL. This
+ permits U-Boot (or Linux in Falcon mode) to be loaded from a FAT
+ filesystem from within SPL. Support for the underlying block
+ device (e.g. MMC or USB) must be enabled separately.
+
+config SPL_FPGA_SUPPORT
+ bool "Support FPGAs"
+ depends on SPL
+ help
+ Enable support for FPGAs in SPL. Field-programmable Gate Arrays
+ provide software-configurable hardware which is typically used to
+ implement peripherals (such as UARTs, LCD displays, MMC) or
+ accelerate custom processing functions, such as image processing
+ or machine learning. Sometimes it is useful to program the FPGA
+ as early as possible during boot, and this option can enable that
+ within SPL.
+
+config SPL_GPIO_SUPPORT
+ bool "Support GPIO"
+ depends on SPL
+ help
+ Enable support for GPIOs (General-purpose Input/Output) in SPL.
+ GPIOs allow U-Boot to read the state of an input line (high or
+ low) and set the state of an output line. This can be used to
+ drive LEDs, control power to various system parts and read user
+ input. GPIOs can be useful in SPL to enable a 'sign-of-life' LED,
+ for example. Enable this option to build the drivers in
+ drivers/gpio as part of an SPL build.
+
+config SPL_I2C_SUPPORT
+ bool "Support I2C"
+ depends on SPL
+ help
+ Enable support for the I2C (Inter-Integrated Circuit) bus in SPL.
+ I2C works with a clock and data line which can be driven by a
+ one or more masters or slaves. It is a fairly complex bus but is
+ widely used as it only needs two lines for communication. Speeds of
+ 400kbps are typical but up to 3.4Mbps is supported by some
+ hardware. I2C can be useful in SPL to configure power management
+ ICs (PMICs) before raising the CPU clock speed, for example.
+ Enable this option to build the drivers in drivers/i2c as part of
+ an SPL build.
+
+config SPL_LIBCOMMON_SUPPORT
+ bool "Support common libraries"
+ depends on SPL
+ help
+ Enable support for common U-Boot libraries within SPL. These
+ libraries include common code to deal with U-Boot images,
+ environment and USB, for example. This option is enabled on many
+ boards. Enable this option to build the code in common/ as part of
+ an SPL build.
+
+config SPL_LIBDISK_SUPPORT
+ bool "Support disk paritions"
+ depends on SPL
+ help
+ Enable support for disk partitions within SPL. 'Disk' is something
+ of a misnomer as it includes non-spinning media such as flash (as
+ used in MMC and USB sticks). Partitions provide a way for a disk
+ to be split up into separate regions, with a partition table placed
+ at the start or end which describes the location and size of each
+ 'partition'. These partitions are typically uses as individual block
+ devices, typically with an EXT2 or FAT filesystem in each. This
+ option enables whatever partition support has been enabled in
+ U-Boot to also be used in SPL. It brings in the code in disk/.
+
+config SPL_LIBGENERIC_SUPPORT
+ bool "Support generic libraries"
+ depends on SPL
+ help
+ Enable support for generic U-Boot libraries within SPL. These
+ libraries include generic code to deal with device tree, hashing,
+ printf(), compression and the like. This option is enabled on many
+ boards. Enable this option to build the code in lib/ as part of an
+ SPL build.
+
+config SPL_MMC_SUPPORT
+ bool "Support MMC"
+ depends on SPL
+ help
+ Enable support for MMC (Multimedia Card) within SPL. This enables
+ the MMC protocol implementation and allows any enabled drivers to
+ be used within SPL. MMC can be used with or without disk partition
+ support depending on the application (SPL_LIBDISK_SUPPORT). Enable
+ this option to build the drivers in drivers/mmc as part of an SPL
+ build.
+
+config SPL_MPC8XXX_INIT_DDR_SUPPORT
+ bool "Support MPC8XXX DDR init"
+ depends on SPL
+ help
+ Enable support for DDR-SDRAM (double-data-rate synchronous dynamic
+ random-access memory) on the MPC8XXX family within SPL. This
+ allows DRAM to be set up before loading U-Boot into that DRAM,
+ where it can run.
+
+config SPL_MTD_SUPPORT
+ bool "Support MTD drivers"
+ depends on SPL
+ help
+ Enable support for MTD (Memory Technology Device) within SPL. MTD
+ provides a block interface over raw NAND and can also be used with
+ SPI flash. This allows SPL to load U-Boot from supported MTD
+ devices. See SPL_NAND_SUPPORT and SPL_ONENAND_SUPPORT for how
+ to enable specific MTD drivers.
+
+config SPL_MUSB_NEW_SUPPORT
+ bool "Support new Mentor Graphics USB"
+ depends on SPL
+ help
+ Enable support for Mentor Graphics USB in SPL. This is a new
+ driver used by some boards. Enable this option to build
+ the drivers in drivers/usb/musb-new as part of an SPL build. The
+ old drivers are in drivers/usb/musb.
+
+config SPL_NAND_SUPPORT
+ bool "Support NAND flash"
+ depends on SPL
+ help
+ Enable support for NAND (Negative AND) flash in SPL. NAND flash
+ can be used to allow SPL to load U-Boot from supported devices.
+ This enables the drivers in drivers/mtd/nand as part of an SPL
+ build.
+
+config SPL_NET_SUPPORT
+ bool "Support networking"
+ depends on SPL
+ help
+ Enable support for network devices (such as Ethernet) in SPL.
+ This permits SPL to load U-Boot over a network link rather than
+ from an on-board peripheral. Environment support is required since
+ the network stack uses a number of environment variables. See also
+ SPL_ETH_SUPPORT.
+
+if SPL_NET_SUPPORT
+config SPL_NET_VCI_STRING
+ string "BOOTP Vendor Class Identifier string sent by SPL"
+ help
+ As defined by RFC 2132 the vendor class identifier field can be
+ sent by the client to identify the vendor type and configuration
+ of a client. This is often used in practice to allow for the DHCP
+ server to specify different files to load depending on if the ROM,
+ SPL or U-Boot itself makes the request
+endif # if SPL_NET_SUPPORT
+
+config SPL_NO_CPU_SUPPORT
+ bool "Drop CPU code in SPL"
+ depends on SPL
+ help
+ This is specific to the ARM926EJ-S CPU. It disables the standard
+ start.S start-up code, presumably so that a replacement can be
+ used on that CPU. You should not enable it unless you know what
+ you are doing.
+
+config SPL_NOR_SUPPORT
+ bool "Support NOR flash"
+ depends on SPL
+ help
+ Enable support for loading U-Boot from memory-mapped NOR (Negative
+ OR) flash in SPL. NOR flash is slow to write but fast to read, and
+ a memory-mapped device makes it very easy to access. Loading from
+ NOR is typically achieved with just a memcpy().
+
+config SPL_ONENAND_SUPPORT
+ bool "Support OneNAND flash"
+ depends on SPL
+ help
+ Enable support for OneNAND (Negative AND) flash in SPL. OneNAND is
+ a type of NAND flash and therefore can be used to allow SPL to
+ load U-Boot from supported devices. This enables the drivers in
+ drivers/mtd/onenand as part of an SPL build.
+
+config SPL_OS_BOOT
+ bool "Activate Falcon Mode"
+ depends on SPL && !TI_SECURE_DEVICE
+ default n
+ help
+ Enable booting directly to an OS from SPL.
+ for more info read doc/README.falcon
+
+if SPL_OS_BOOT
+config SYS_OS_BASE
+ hex "addr, where OS is found"
+ depends on SPL && SPL_NOR_SUPPORT
+ help
+ Specify the address, where the OS image is found, which
+ gets booted.
+
+endif # SPL_OS_BOOT
+
+config SPL_POST_MEM_SUPPORT
+ bool "Support POST drivers"
+ depends on SPL
+ help
+ Enable support for POST (Power-on Self Test) in SPL. POST is a
+ procedure that checks that the hardware (CPU or board) appears to
+ be functionally correctly. It is a sanity check that can be
+ performed before booting. This enables the drivers in post/drivers
+ as part of an SPL build.
+
+config SPL_POWER_SUPPORT
+ bool "Support power drivers"
+ depends on SPL
+ help
+ Enable support for power control in SPL. This includes support
+ for PMICs (Power-management Integrated Circuits) and some of the
+ features provided by PMICs. In particular, voltage regulators can
+ be used to enable/disable power and vary its voltage. That can be
+ useful in SPL to turn on boot peripherals and adjust CPU voltage
+ so that the clock speed can be increased. This enables the drivers
+ in drivers/power, drivers/power/pmic and drivers/power/regulator
+ as part of an SPL build.
+
+config SPL_SATA_SUPPORT
+ bool "Support loading from SATA"
+ depends on SPL
+ help
+ Enable support for SATA (Serial AT attachment) in SPL. This allows
+ use of SATA devices such as hard drives and flash drivers for
+ loading U-Boot. SATA is used in higher-end embedded systems and
+ can provide higher performance than MMC , at somewhat higher
+ expense and power consumption. This enables loading from SATA
+ using a configured device.
+
+config SPL_SERIAL_SUPPORT
+ bool "Support serial"
+ depends on SPL
+ help
+ Enable support for serial in SPL. This allows use of a serial UART
+ for displaying messages while SPL is running. It also brings in
+ printf() and panic() functions. This should normally be enabled
+ unless there are space reasons not to. Even then, consider
+ enabling USE_TINY_PRINTF which is a small printf() version.
+
+config SPL_SPI_FLASH_SUPPORT
+ bool "Support SPI flash drivers"
+ depends on SPL
+ help
+ Enable support for using SPI flash in SPL, and loading U-Boot from
+ SPI flash. SPI flash (Serial Peripheral Bus flash) is named after
+ the SPI bus that is used to connect it to a system. It is a simple
+ but fast bidirectional 4-wire bus (clock, chip select and two data
+ lines). This enables the drivers in drivers/mtd/spi as part of an
+ SPL build. This normally requires SPL_SPI_SUPPORT.
+
+config SPL_SPI_SUPPORT
+ bool "Support SPI drivers"
+ depends on SPL
+ help
+ Enable support for using SPI in SPL. This is used for connecting
+ to SPI flash for loading U-Boot. See SPL_SPI_FLASH_SUPPORT for
+ more details on that. The SPI driver provides the transport for
+ data between the SPI flash and the CPU. This option can be used to
+ enable SPI drivers that are needed for other purposes also, such
+ as a SPI PMIC.
+
+config SPL_USB_HOST_SUPPORT
+ bool "Support USB host drivers"
+ depends on SPL
+ help
+ Enable access to USB (Universal Serial Bus) host devices so that
+ SPL can load U-Boot from a connected USB peripheral, such as a USB
+ flash stick. While USB takes a little longer to start up than most
+ buses, it is very flexible since many different types of storage
+ device can be attached. This option enables the drivers in
+ drivers/usb/host as part of an SPL build.
+
+config SPL_USB_SUPPORT
+ bool "Support loading from USB"
+ depends on SPL_USB_HOST_SUPPORT
+ help
+ Enable support for USB devices in SPL. This allows use of USB
+ devices such as hard drives and flash drivers for loading U-Boot.
+ The actual drivers are enabled separately using the normal U-Boot
+ config options. This enables loading from USB using a configured
+ device.
+
+config SPL_USB_GADGET_SUPPORT
+ bool "Suppport USB Gadget drivers"
+ depends on SPL
+ help
+ Enable USB Gadget API which allows to enable USB device functions
+ in SPL.
+
+if SPL_USB_GADGET_SUPPORT
+
+config SPL_USBETH_SUPPORT
+ bool "Support USB Ethernet drivers"
+ help
+ Enable access to the USB network subsystem and associated
+ drivers in SPL. This permits SPL to load U-Boot over a
+ USB-connected Ethernet link (such as a USB Ethernet dongle) rather
+ than from an onboard peripheral. Environment support is required
+ since the network stack uses a number of environment variables.
+ See also SPL_NET_SUPPORT and SPL_ETH_SUPPORT.
+
+config SPL_DFU_SUPPORT
+ bool "Support DFU (Device Firmware Upgarde)"
+ select SPL_HASH_SUPPORT
+ help
+ This feature enables the DFU (Device Firmware Upgarde) in SPL with
+ RAM memory device support. The ROM code will load and execute
+ the SPL built with dfu. The user can load binaries (u-boot/kernel) to
+ selected device partition from host-pc using dfu-utils.
+ This feature is useful to flash the binaries to factory or bare-metal
+ boards using USB interface.
+
+choice
+ bool "DFU device selection"
+ depends on SPL_DFU_SUPPORT
+
+config SPL_DFU_RAM
+ bool "RAM device"
+ depends on SPL_DFU_SUPPORT
+ help
+ select RAM/DDR memory device for loading binary images
+ (u-boot/kernel) to the selected device partition using
+ DFU and execute the u-boot/kernel from RAM.
+
+endchoice
+
+endif
+
+config SPL_WATCHDOG_SUPPORT
+ bool "Support watchdog drivers"
+ depends on SPL
+ help
+ Enable support for watchdog drivers in SPL. A watchdog is
+ typically a hardware peripheral which can reset the system when it
+ detects no activity for a while (such as a software crash). This
+ enables the drivers in drivers/watchdog as part of an SPL build.
+
+config SPL_YMODEM_SUPPORT
+ bool "Support loading using Ymodem"
+ depends on SPL
+ help
+ While loading from serial is slow it can be a useful backup when
+ there is no other option. The Ymodem protocol provides a reliable
+ means of transmitting U-Boot over a serial line for using in SPL,
+ with a checksum to ensure correctness.
+
+config TPL_ENV_SUPPORT
+ bool "Support an environment"
+ depends on TPL
+ help
+ Enable environment support in TPL. See SPL_ENV_SUPPORT for details.
+
+config TPL_I2C_SUPPORT
+ bool "Support I2C"
+ depends on TPL
+ help
+ Enable support for the I2C bus in SPL. See SPL_I2C_SUPPORT for
+ details.
+
+config TPL_LIBCOMMON_SUPPORT
+ bool "Support common libraries"
+ depends on TPL
+ help
+ Enable support for common U-Boot libraries within TPL. See
+ SPL_LIBCOMMON_SUPPORT for details.
+
+config TPL_LIBGENERIC_SUPPORT
+ bool "Support generic libraries"
+ depends on TPL
+ help
+ Enable support for generic U-Boot libraries within TPL. See
+ SPL_LIBGENERIC_SUPPORT for details.
+
+config TPL_MPC8XXX_INIT_DDR_SUPPORT
+ bool "Support MPC8XXX DDR init"
+ depends on TPL
+ help
+ Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See
+ SPL_MPC8XXX_INIT_DDR_SUPPORT for details.
+
+config TPL_MMC_SUPPORT
+ bool "Support MMC"
+ depends on TPL
+ help
+ Enable support for MMC within TPL. See SPL_MMC_SUPPORT for details.
+
+config TPL_NAND_SUPPORT
+ bool "Support NAND flash"
+ depends on TPL
+ help
+ Enable support for NAND in SPL. See SPL_NAND_SUPPORT for details.
+
+config TPL_SERIAL_SUPPORT
+ bool "Support serial"
+ depends on TPL
+ help
+ Enable support for serial in SPL. See SPL_SERIAL_SUPPORT for
+ details.
+
+config TPL_SPI_FLASH_SUPPORT
+ bool "Support SPI flash drivers"
+ depends on TPL
+ help
+ Enable support for using SPI flash in SPL. See SPL_SPI_FLASH_SUPPORT
+ for details.
+
+config TPL_SPI_SUPPORT
+ bool "Support SPI drivers"
+ depends on TPL
+ help
+ Enable support for using SPI in SPL. See SPL_SPI_SUPPORT for
+ details.
+
+endmenu
diff --git a/common/spl/Makefile b/common/spl/Makefile
index b15f0f6..ed02635 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -24,4 +24,6 @@
obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o
obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
+obj-$(CONFIG_SPL_DFU_SUPPORT) += spl_dfu.o
+obj-$(CONFIG_SPL_SPI_LOAD) += spl_spi.o
endif
diff --git a/common/spl/spl.c b/common/spl/spl.c
index e14ec80..f7df834 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -29,7 +29,6 @@
#endif
u32 *boot_params_ptr = NULL;
-struct spl_image_info spl_image;
/* Define board data structure */
static bd_t bdata __attribute__ ((section(".data")));
@@ -82,42 +81,43 @@
/* Nothing to do! */
}
-void spl_set_header_raw_uboot(void)
+void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
{
- spl_image.size = CONFIG_SYS_MONITOR_LEN;
- spl_image.entry_point = CONFIG_SYS_UBOOT_START;
- spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
- spl_image.os = IH_OS_U_BOOT;
- spl_image.name = "U-Boot";
+ spl_image->size = CONFIG_SYS_MONITOR_LEN;
+ spl_image->entry_point = CONFIG_SYS_UBOOT_START;
+ spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
+ spl_image->os = IH_OS_U_BOOT;
+ spl_image->name = "U-Boot";
}
-int spl_parse_image_header(const struct image_header *header)
+int spl_parse_image_header(struct spl_image_info *spl_image,
+ const struct image_header *header)
{
u32 header_size = sizeof(struct image_header);
if (image_get_magic(header) == IH_MAGIC) {
- if (spl_image.flags & SPL_COPY_PAYLOAD_ONLY) {
+ if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) {
/*
* On some system (e.g. powerpc), the load-address and
* entry-point is located at address 0. We can't load
* to 0-0x40. So skip header in this case.
*/
- spl_image.load_addr = image_get_load(header);
- spl_image.entry_point = image_get_ep(header);
- spl_image.size = image_get_data_size(header);
+ spl_image->load_addr = image_get_load(header);
+ spl_image->entry_point = image_get_ep(header);
+ spl_image->size = image_get_data_size(header);
} else {
- spl_image.entry_point = image_get_load(header);
+ spl_image->entry_point = image_get_load(header);
/* Load including the header */
- spl_image.load_addr = spl_image.entry_point -
+ spl_image->load_addr = spl_image->entry_point -
header_size;
- spl_image.size = image_get_data_size(header) +
+ spl_image->size = image_get_data_size(header) +
header_size;
}
- spl_image.os = image_get_os(header);
- spl_image.name = image_get_name(header);
+ spl_image->os = image_get_os(header);
+ spl_image->name = image_get_name(header);
debug("spl: payload image: %.*s load addr: 0x%x size: %d\n",
- (int)sizeof(spl_image.name), spl_image.name,
- spl_image.load_addr, spl_image.size);
+ (int)sizeof(spl_image->name), spl_image->name,
+ spl_image->load_addr, spl_image->size);
} else {
#ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE
/*
@@ -135,13 +135,13 @@
ulong start, end;
if (!bootz_setup((ulong)header, &start, &end)) {
- spl_image.name = "Linux";
- spl_image.os = IH_OS_LINUX;
- spl_image.load_addr = CONFIG_SYS_LOAD_ADDR;
- spl_image.entry_point = CONFIG_SYS_LOAD_ADDR;
- spl_image.size = end - start;
+ spl_image->name = "Linux";
+ spl_image->os = IH_OS_LINUX;
+ spl_image->load_addr = CONFIG_SYS_LOAD_ADDR;
+ spl_image->entry_point = CONFIG_SYS_LOAD_ADDR;
+ spl_image->size = end - start;
debug("spl: payload zImage, load addr: 0x%x size: %d\n",
- spl_image.load_addr, spl_image.size);
+ spl_image->load_addr, spl_image->size);
return 0;
}
#endif
@@ -153,7 +153,7 @@
/* Signature not found - assume u-boot.bin */
debug("mkimage signature not found - ih_magic = %x\n",
header->ih_magic);
- spl_set_header_raw_uboot();
+ spl_set_header_raw_uboot(spl_image);
#endif
}
return 0;
@@ -174,7 +174,7 @@
# define CONFIG_SPL_LOAD_FIT_ADDRESS 0
#endif
-#ifdef CONFIG_SPL_RAM_DEVICE
+#if defined(CONFIG_SPL_RAM_DEVICE) || defined(CONFIG_SPL_DFU_SUPPORT)
static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
@@ -184,12 +184,18 @@
return count;
}
-static int spl_ram_load_image(void)
+static int spl_ram_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
struct image_header *header;
header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
+#if defined(CONFIG_SPL_DFU_SUPPORT)
+ if (bootdev->boot_device == BOOT_DEVICE_DFU)
+ spl_dfu_cmd(0, "dfu_alt_info_ram", "ram", "0");
+#endif
+
if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
image_get_magic(header) == FDT_MAGIC) {
struct spl_load_info load;
@@ -197,7 +203,7 @@
debug("Found FIT\n");
load.bl_len = 1;
load.read = spl_ram_load_read;
- spl_load_simple_fit(&load, 0, header);
+ spl_load_simple_fit(spl_image, &load, 0, header);
} else {
debug("Legacy image\n");
/*
@@ -209,11 +215,17 @@
header = (struct image_header *)
(CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
- spl_parse_image_header(header);
+ spl_parse_image_header(spl_image, header);
}
return 0;
}
+#if defined(CONFIG_SPL_RAM_DEVICE)
+SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, spl_ram_load_image);
+#endif
+#if defined(CONFIG_SPL_DFU_SUPPORT)
+SPL_LOAD_IMAGE_METHOD("USB DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image);
+#endif
#endif
int spl_init(void)
@@ -252,173 +264,79 @@
#define BOOT_DEVICE_NONE 0xdeadbeef
#endif
-static u32 spl_boot_list[] = {
- BOOT_DEVICE_NONE,
- BOOT_DEVICE_NONE,
- BOOT_DEVICE_NONE,
- BOOT_DEVICE_NONE,
- BOOT_DEVICE_NONE,
-};
-
__weak void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
}
-#ifdef CONFIG_SPL_BOARD_LOAD_IMAGE
-__weak void spl_board_announce_boot_device(void) { }
-#endif
+static struct spl_image_loader *spl_ll_find_loader(uint boot_device)
+{
+ struct spl_image_loader *drv =
+ ll_entry_start(struct spl_image_loader, spl_image_loader);
+ const int n_ents =
+ ll_entry_count(struct spl_image_loader, spl_image_loader);
+ struct spl_image_loader *entry;
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-struct boot_device_name {
- u32 boot_dev;
- const char *name;
-};
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ if (boot_device == entry->boot_device)
+ return entry;
+ }
-struct boot_device_name boot_name_table[] = {
-#ifdef CONFIG_SPL_RAM_DEVICE
- { BOOT_DEVICE_RAM, "RAM" },
-#endif
-#ifdef CONFIG_SPL_MMC_SUPPORT
- { BOOT_DEVICE_MMC1, "MMC1" },
- { BOOT_DEVICE_MMC2, "MMC2" },
- { BOOT_DEVICE_MMC2_2, "MMC2_2" },
-#endif
-#ifdef CONFIG_SPL_NAND_SUPPORT
- { BOOT_DEVICE_NAND, "NAND" },
-#endif
-#ifdef CONFIG_SPL_ONENAND_SUPPORT
- { BOOT_DEVICE_ONENAND, "OneNAND" },
-#endif
-#ifdef CONFIG_SPL_NOR_SUPPORT
- { BOOT_DEVICE_NOR, "NOR" },
-#endif
-#ifdef CONFIG_SPL_YMODEM_SUPPORT
- { BOOT_DEVICE_UART, "UART" },
-#endif
-#if defined(CONFIG_SPL_SPI_SUPPORT) || defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
- { BOOT_DEVICE_SPI, "SPI" },
-#endif
-#ifdef CONFIG_SPL_ETH_SUPPORT
-#ifdef CONFIG_SPL_ETH_DEVICE
- { BOOT_DEVICE_CPGMAC, "eth device" },
-#else
- { BOOT_DEVICE_CPGMAC, "net" },
-#endif
-#endif
-#ifdef CONFIG_SPL_USBETH_SUPPORT
- { BOOT_DEVICE_USBETH, "USB eth" },
-#endif
-#ifdef CONFIG_SPL_USB_SUPPORT
- { BOOT_DEVICE_USB, "USB" },
-#endif
-#ifdef CONFIG_SPL_SATA_SUPPORT
- { BOOT_DEVICE_SATA, "SATA" },
-#endif
- /* Keep this entry last */
- { BOOT_DEVICE_NONE, "unknown boot device" },
-};
+ /* Not found */
+ return NULL;
+}
-static void announce_boot_device(u32 boot_device)
+static int spl_load_image(struct spl_image_info *spl_image,
+ struct spl_image_loader *loader)
+{
+ struct spl_boot_device bootdev;
+
+ bootdev.boot_device = loader->boot_device;
+ bootdev.boot_device_name = NULL;
+
+ return loader->load_image(spl_image, &bootdev);
+}
+
+/**
+ * boot_from_devices() - Try loading an booting U-Boot from a list of devices
+ *
+ * @spl_image: Place to put the image details if successful
+ * @spl_boot_list: List of boot devices to try
+ * @count: Number of elements in spl_boot_list
+ * @return 0 if OK, -ve on error
+ */
+static int boot_from_devices(struct spl_image_info *spl_image,
+ u32 spl_boot_list[], int count)
{
int i;
- puts("Trying to boot from ");
+ for (i = 0; i < count && spl_boot_list[i] != BOOT_DEVICE_NONE; i++) {
+ struct spl_image_loader *loader;
-#ifdef CONFIG_SPL_BOARD_LOAD_IMAGE
- if (boot_device == BOOT_DEVICE_BOARD) {
- spl_board_announce_boot_device();
- puts("\n");
- return;
- }
-#endif
- for (i = 0; i < ARRAY_SIZE(boot_name_table) - 1; i++) {
- if (boot_name_table[i].boot_dev == boot_device)
- break;
- }
-
- printf("%s\n", boot_name_table[i].name);
-}
-#else
-static inline void announce_boot_device(u32 boot_device) { }
-#endif
-
-static int spl_load_image(u32 boot_device)
-{
- switch (boot_device) {
-#ifdef CONFIG_SPL_RAM_DEVICE
- case BOOT_DEVICE_RAM:
- return spl_ram_load_image();
-#endif
-#ifdef CONFIG_SPL_MMC_SUPPORT
- case BOOT_DEVICE_MMC1:
- case BOOT_DEVICE_MMC2:
- case BOOT_DEVICE_MMC2_2:
- return spl_mmc_load_image(boot_device);
-#endif
-#ifdef CONFIG_SPL_UBI
- case BOOT_DEVICE_NAND:
- case BOOT_DEVICE_ONENAND:
- return spl_ubi_load_image(boot_device);
-#else
-#ifdef CONFIG_SPL_NAND_SUPPORT
- case BOOT_DEVICE_NAND:
- return spl_nand_load_image();
-#endif
-#ifdef CONFIG_SPL_ONENAND_SUPPORT
- case BOOT_DEVICE_ONENAND:
- return spl_onenand_load_image();
-#endif
-#endif
-#ifdef CONFIG_SPL_NOR_SUPPORT
- case BOOT_DEVICE_NOR:
- return spl_nor_load_image();
-#endif
-#ifdef CONFIG_SPL_YMODEM_SUPPORT
- case BOOT_DEVICE_UART:
- return spl_ymodem_load_image();
-#endif
-#if defined(CONFIG_SPL_SPI_SUPPORT) || defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
- case BOOT_DEVICE_SPI:
- return spl_spi_load_image();
-#endif
-#ifdef CONFIG_SPL_ETH_SUPPORT
- case BOOT_DEVICE_CPGMAC:
-#ifdef CONFIG_SPL_ETH_DEVICE
- return spl_net_load_image(CONFIG_SPL_ETH_DEVICE);
-#else
- return spl_net_load_image(NULL);
-#endif
-#endif
-#ifdef CONFIG_SPL_USBETH_SUPPORT
- case BOOT_DEVICE_USBETH:
- return spl_net_load_image("usb_ether");
-#endif
-#ifdef CONFIG_SPL_USB_SUPPORT
- case BOOT_DEVICE_USB:
- return spl_usb_load_image();
-#endif
-#ifdef CONFIG_SPL_SATA_SUPPORT
- case BOOT_DEVICE_SATA:
- return spl_sata_load_image();
-#endif
-#ifdef CONFIG_SPL_BOARD_LOAD_IMAGE
- case BOOT_DEVICE_BOARD:
- return spl_board_load_image();
-#endif
- default:
+ loader = spl_ll_find_loader(spl_boot_list[i]);
#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- puts("SPL: Unsupported Boot Device!\n");
+ if (loader)
+ printf("Trying to boot from %s", loader->name);
+ else
+ puts("SPL: Unsupported Boot Device!\n");
#endif
- return -ENODEV;
+ if (loader && !spl_load_image(spl_image, loader))
+ return 0;
}
- return -EINVAL;
+ return -ENODEV;
}
void board_init_r(gd_t *dummy1, ulong dummy2)
{
- int i;
+ u32 spl_boot_list[] = {
+ BOOT_DEVICE_NONE,
+ BOOT_DEVICE_NONE,
+ BOOT_DEVICE_NONE,
+ BOOT_DEVICE_NONE,
+ BOOT_DEVICE_NONE,
+ };
+ struct spl_image_info spl_image;
debug(">>spl:board_init_r()\n");
@@ -443,16 +361,11 @@
spl_board_init();
#endif
+ memset(&spl_image, '\0', sizeof(spl_image));
board_boot_order(spl_boot_list);
- for (i = 0; i < ARRAY_SIZE(spl_boot_list) &&
- spl_boot_list[i] != BOOT_DEVICE_NONE; i++) {
- announce_boot_device(spl_boot_list[i]);
- if (!spl_load_image(spl_boot_list[i]))
- break;
- }
- if (i == ARRAY_SIZE(spl_boot_list) ||
- spl_boot_list[i] == BOOT_DEVICE_NONE) {
+ if (boot_from_devices(&spl_image, spl_boot_list,
+ ARRAY_SIZE(spl_boot_list))) {
puts("SPL: failed to boot from all boot devices\n");
hang();
}
@@ -465,7 +378,8 @@
case IH_OS_LINUX:
debug("Jumping to Linux\n");
spl_board_prepare_for_linux();
- jump_to_image_linux((void *)CONFIG_SYS_SPL_ARGS_ADDR);
+ jump_to_image_linux(&spl_image,
+ (void *)CONFIG_SYS_SPL_ARGS_ADDR);
#endif
default:
debug("Unsupported OS image.. Jumping nevertheless..\n");
@@ -536,6 +450,9 @@
ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16);
new_gd = (gd_t *)ptr;
memcpy(new_gd, (void *)gd, sizeof(gd_t));
+#if CONFIG_IS_ENABLED(DM)
+ dm_fixup_for_gd_move(new_gd);
+#endif
#if !defined(CONFIG_ARM)
gd = new_gd;
#endif
diff --git a/common/spl/spl_dfu.c b/common/spl/spl_dfu.c
new file mode 100644
index 0000000..e8d0ba1
--- /dev/null
+++ b/common/spl/spl_dfu.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2016
+ * Texas Instruments, <www.ti.com>
+ *
+ * Ravi B <ravibabu@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <errno.h>
+#include <watchdog.h>
+#include <console.h>
+#include <g_dnl.h>
+#include <usb.h>
+#include <dfu.h>
+#include <environment.h>
+
+static int run_dfu(int usb_index, char *interface, char *devstring)
+{
+ int ret;
+
+ ret = dfu_init_env_entities(interface, devstring);
+ if (ret) {
+ dfu_free_entities();
+ goto exit;
+ }
+
+ run_usb_dnl_gadget(usb_index, "usb_dnl_dfu");
+exit:
+ dfu_free_entities();
+ return ret;
+}
+
+int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr)
+{
+ char *str_env;
+ int ret;
+
+ /* set default environment */
+ set_default_env(0);
+ str_env = getenv(dfu_alt_info);
+ if (!str_env) {
+ error("\"dfu_alt_info\" env variable not defined!\n");
+ return -EINVAL;
+ }
+
+ ret = setenv("dfu_alt_info", str_env);
+ if (ret) {
+ error("unable to set env variable \"dfu_alt_info\"!\n");
+ return -EINVAL;
+ }
+
+ /* invoke dfu command */
+ return run_dfu(usbctrl, interface, devstr);
+}
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index a85dc85..1b8e15e 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -10,9 +10,9 @@
#include <image.h>
#ifdef CONFIG_SPL_EXT_SUPPORT
-int spl_load_image_ext(struct blk_desc *block_dev,
- int partition,
- const char *filename)
+int spl_load_image_ext(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition,
+ const char *filename)
{
s32 err;
struct image_header *header;
@@ -42,19 +42,19 @@
puts("spl: ext4fs_open failed\n");
goto end;
}
- err = ext4fs_read((char *)header, sizeof(struct image_header), &actlen);
+ err = ext4fs_read((char *)header, 0, sizeof(struct image_header), &actlen);
if (err < 0) {
puts("spl: ext4fs_read failed\n");
goto end;
}
- err = spl_parse_image_header(header);
+ err = spl_parse_image_header(spl_image, header);
if (err < 0) {
puts("spl: ext: failed to parse image header\n");
goto end;
}
- err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen);
+ err = ext4fs_read((char *)spl_image->load_addr, 0, filelen, &actlen);
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -67,7 +67,8 @@
}
#ifdef CONFIG_SPL_OS_BOOT
-int spl_load_image_ext_os(struct blk_desc *block_dev, int partition)
+int spl_load_image_ext_os(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition)
{
int err;
__maybe_unused loff_t filelen, actlen;
@@ -96,7 +97,7 @@
puts("spl: ext4fs_open failed\n");
goto defaults;
}
- err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen);
+ err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, filelen, &actlen);
if (err < 0) {
printf("spl: error reading image %s, err - %d, falling back to default\n",
file, err);
@@ -104,7 +105,8 @@
}
file = getenv("falcon_image_file");
if (file) {
- err = spl_load_image_ext(block_dev, partition, file);
+ err = spl_load_image_ext(spl_image, block_dev,
+ partition, file);
if (err != 0) {
puts("spl: falling back to default\n");
goto defaults;
@@ -125,7 +127,7 @@
if (err < 0)
puts("spl: ext4fs_open failed\n");
- err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen);
+ err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, filelen, &actlen);
if (err < 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
@@ -134,11 +136,12 @@
return -1;
}
- return spl_load_image_ext(block_dev, partition,
+ return spl_load_image_ext(spl_image, block_dev, partition,
CONFIG_SPL_FS_LOAD_KERNEL_NAME);
}
#else
-int spl_load_image_ext_os(struct blk_desc *block_dev, int partition)
+int spl_load_image_ext_os(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition)
{
return -ENOSYS;
}
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 73d33f5..a14acce 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -54,9 +54,9 @@
return actread;
}
-int spl_load_image_fat(struct blk_desc *block_dev,
- int partition,
- const char *filename)
+int spl_load_image_fat(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition,
+ const char *filename)
{
int err;
struct image_header *header;
@@ -82,14 +82,14 @@
load.filename = (void *)filename;
load.priv = NULL;
- return spl_load_simple_fit(&load, 0, header);
+ return spl_load_simple_fit(spl_image, &load, 0, header);
} else {
- err = spl_parse_image_header(header);
+ err = spl_parse_image_header(spl_image, header);
if (err)
goto end;
err = file_fat_read(filename,
- (u8 *)(uintptr_t)spl_image.load_addr, 0);
+ (u8 *)(uintptr_t)spl_image->load_addr, 0);
}
end:
@@ -103,7 +103,8 @@
}
#ifdef CONFIG_SPL_OS_BOOT
-int spl_load_image_fat_os(struct blk_desc *block_dev, int partition)
+int spl_load_image_fat_os(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition)
{
int err;
__maybe_unused char *file;
@@ -123,7 +124,8 @@
}
file = getenv("falcon_image_file");
if (file) {
- err = spl_load_image_fat(block_dev, partition, file);
+ err = spl_load_image_fat(spl_image, block_dev,
+ partition, file);
if (err != 0) {
puts("spl: falling back to default\n");
goto defaults;
@@ -148,11 +150,12 @@
return -1;
}
- return spl_load_image_fat(block_dev, partition,
+ return spl_load_image_fat(spl_image, block_dev, partition,
CONFIG_SPL_FS_LOAD_KERNEL_NAME);
}
#else
-int spl_load_image_fat_os(struct blk_desc *block_dev, int partition)
+int spl_load_image_fat_os(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition)
{
return -ENOSYS;
}
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index be86072..aae556f 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -123,7 +123,8 @@
return (data_size + info->bl_len - 1) / info->bl_len;
}
-int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
+int spl_load_simple_fit(struct spl_image_info *spl_image,
+ struct spl_load_info *info, ulong sector, void *fit)
{
int sectors;
ulong size, load;
@@ -184,9 +185,9 @@
data_size = fdt_getprop_u32(fit, node, "data-size");
load = fdt_getprop_u32(fit, node, "load");
debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
- spl_image.load_addr = load;
- spl_image.entry_point = load;
- spl_image.os = IH_OS_U_BOOT;
+ spl_image->load_addr = load;
+ spl_image->entry_point = load;
+ spl_image->os = IH_OS_U_BOOT;
/*
* Work out where to place the image. We read it so that the first
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 7c7f329..85e3de8 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -18,26 +18,26 @@
DECLARE_GLOBAL_DATA_PTR;
-static int mmc_load_legacy(struct mmc *mmc, ulong sector,
- struct image_header *header)
+static int mmc_load_legacy(struct spl_image_info *spl_image, struct mmc *mmc,
+ ulong sector, struct image_header *header)
{
u32 image_size_sectors;
unsigned long count;
int ret;
- ret = spl_parse_image_header(header);
+ ret = spl_parse_image_header(spl_image, header);
if (ret)
return ret;
/* convert size to sectors - round up */
- image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) /
+ image_size_sectors = (spl_image->size + mmc->read_bl_len - 1) /
mmc->read_bl_len;
/* Read the header too to avoid extra memcpy */
count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
- (void *)(ulong)spl_image.load_addr);
+ (void *)(ulong)spl_image->load_addr);
debug("read %x sectors to %x\n", image_size_sectors,
- spl_image.load_addr);
+ spl_image->load_addr);
if (count != image_size_sectors)
return -EIO;
@@ -52,7 +52,8 @@
return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf);
}
-static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
+static int mmc_load_image_raw_sector(struct spl_image_info *spl_image,
+ struct mmc *mmc, unsigned long sector)
{
unsigned long count;
struct image_header *header;
@@ -79,9 +80,9 @@
load.filename = NULL;
load.bl_len = mmc->read_bl_len;
load.read = h_spl_load_read;
- ret = spl_load_simple_fit(&load, sector, header);
+ ret = spl_load_simple_fit(spl_image, &load, sector, header);
} else {
- ret = mmc_load_legacy(mmc, sector, header);
+ ret = mmc_load_legacy(spl_image, mmc, sector, header);
}
end:
@@ -150,7 +151,8 @@
}
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
-static int mmc_load_image_raw_partition(struct mmc *mmc, int partition)
+static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
+ struct mmc *mmc, int partition)
{
disk_partition_t info;
int err;
@@ -163,23 +165,25 @@
return -1;
}
-#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
- return mmc_load_image_raw_sector(mmc, info.start +
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ return mmc_load_image_raw_sector(spl_image, mmc,
+ info.start + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
#else
- return mmc_load_image_raw_sector(mmc, info.start);
+ return mmc_load_image_raw_sector(spl_image, mmc, info.start);
#endif
}
#else
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION -1
-static int mmc_load_image_raw_partition(struct mmc *mmc, int partition)
+static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
+ struct mmc *mmc, int partition)
{
return -ENOSYS;
}
#endif
#ifdef CONFIG_SPL_OS_BOOT
-static int mmc_load_image_raw_os(struct mmc *mmc)
+static int mmc_load_image_raw_os(struct spl_image_info *spl_image,
+ struct mmc *mmc)
{
unsigned long count;
int ret;
@@ -195,12 +199,12 @@
return -1;
}
- ret = mmc_load_image_raw_sector(mmc,
+ ret = mmc_load_image_raw_sector(spl_image, mmc,
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
if (ret)
return ret;
- if (spl_image.os != IH_OS_LINUX) {
+ if (spl_image->os != IH_OS_LINUX) {
puts("Expected Linux image is not found. Trying to start U-boot\n");
return -ENOENT;
}
@@ -212,26 +216,27 @@
{
return 1;
}
-static int mmc_load_image_raw_os(struct mmc *mmc)
+static int mmc_load_image_raw_os(struct spl_image_info *spl_image,
+ struct mmc *mmc)
{
return -ENOSYS;
}
#endif
#ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
-int spl_mmc_do_fs_boot(struct mmc *mmc)
+static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc)
{
int err = -ENOSYS;
#ifdef CONFIG_SPL_FAT_SUPPORT
if (!spl_start_uboot()) {
- err = spl_load_image_fat_os(mmc_get_blk_desc(mmc),
+ err = spl_load_image_fat_os(spl_image, mmc_get_blk_desc(mmc),
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
if (!err)
return err;
}
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
- err = spl_load_image_fat(mmc_get_blk_desc(mmc),
+ err = spl_load_image_fat(spl_image, mmc_get_blk_desc(mmc),
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
if (!err)
@@ -240,13 +245,13 @@
#endif
#ifdef CONFIG_SPL_EXT_SUPPORT
if (!spl_start_uboot()) {
- err = spl_load_image_ext_os(&mmc->block_dev,
+ err = spl_load_image_ext_os(spl_image, mmc_get_blk_desc(mmc),
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
if (!err)
return err;
}
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
- err = spl_load_image_ext(&mmc->block_dev,
+ err = spl_load_image_ext(spl_image, mmc_get_blk_desc(mmc),
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
if (!err)
@@ -261,20 +266,21 @@
return err;
}
#else
-int spl_mmc_do_fs_boot(struct mmc *mmc)
+static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc)
{
return -ENOSYS;
}
#endif
-int spl_mmc_load_image(u32 boot_device)
+int spl_mmc_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
struct mmc *mmc = NULL;
u32 boot_mode;
int err = 0;
__maybe_unused int part;
- err = spl_mmc_find_device(&mmc, boot_device);
+ err = spl_mmc_find_device(&mmc, bootdev->boot_device);
if (err)
return err;
@@ -286,7 +292,7 @@
return err;
}
- boot_mode = spl_boot_mode(boot_device);
+ boot_mode = spl_boot_mode(bootdev->boot_device);
err = -EINVAL;
switch (boot_mode) {
case MMCSD_MODE_EMMCBOOT:
@@ -300,7 +306,11 @@
if (part == 7)
part = 0;
- err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
+ if (CONFIG_IS_ENABLED(MMC_TINY))
+ err = mmc_switch_part(mmc, part);
+ else
+ err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
+
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("spl: mmc partition switch failed\n");
@@ -312,17 +322,17 @@
debug("spl: mmc boot mode: raw\n");
if (!spl_start_uboot()) {
- err = mmc_load_image_raw_os(mmc);
+ err = mmc_load_image_raw_os(spl_image, mmc);
if (!err)
return err;
}
- err = mmc_load_image_raw_partition(mmc,
+ err = mmc_load_image_raw_partition(spl_image, mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
if (!err)
return err;
-#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
- err = mmc_load_image_raw_sector(mmc,
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ err = mmc_load_image_raw_sector(spl_image, mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
if (!err)
return err;
@@ -331,12 +341,11 @@
case MMCSD_MODE_FS:
debug("spl: mmc boot mode: fs\n");
- err = spl_mmc_do_fs_boot(mmc);
+ err = spl_mmc_do_fs_boot(spl_image, mmc);
if (!err)
return err;
break;
- case MMCSD_MODE_UNDEFINED:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
default:
puts("spl: mmc: wrong boot mode\n");
@@ -345,3 +354,7 @@
return err;
}
+
+SPL_LOAD_IMAGE_METHOD("MMC1", 0, BOOT_DEVICE_MMC1, spl_mmc_load_image);
+SPL_LOAD_IMAGE_METHOD("MMC2", 0, BOOT_DEVICE_MMC2, spl_mmc_load_image);
+SPL_LOAD_IMAGE_METHOD("MMC2_2", 0, BOOT_DEVICE_MMC2_2, spl_mmc_load_image);
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 0e35e0f..cd39f9b 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -13,14 +13,15 @@
#include <fdt.h>
#if defined(CONFIG_SPL_NAND_RAW_ONLY)
-int spl_nand_load_image(void)
+int spl_nand_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
nand_init();
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE,
(void *)CONFIG_SYS_NAND_U_BOOT_DST);
- spl_set_header_raw_uboot();
+ spl_set_header_raw_uboot(spl_image);
nand_deselect();
return 0;
@@ -39,7 +40,8 @@
return 0;
}
-static int spl_nand_load_element(int offset, struct image_header *header)
+static int spl_nand_load_element(struct spl_image_info *spl_image,
+ int offset, struct image_header *header)
{
int err;
@@ -57,17 +59,18 @@
load.filename = NULL;
load.bl_len = 1;
load.read = spl_nand_fit_read;
- return spl_load_simple_fit(&load, offset, header);
+ return spl_load_simple_fit(spl_image, &load, offset, header);
} else {
- err = spl_parse_image_header(header);
+ err = spl_parse_image_header(spl_image, header);
if (err)
return err;
- return nand_spl_load_image(offset, spl_image.size,
- (void *)(ulong)spl_image.load_addr);
+ return nand_spl_load_image(offset, spl_image->size,
+ (void *)(ulong)spl_image->load_addr);
}
}
-int spl_nand_load_image(void)
+static int spl_nand_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
int err;
struct image_header *header;
@@ -107,15 +110,15 @@
/* load linux */
nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
sizeof(*header), (void *)header);
- err = spl_parse_image_header(header);
+ err = spl_parse_image_header(spl_image, header);
if (err)
return err;
if (header->ih_os == IH_OS_LINUX) {
/* happy - was a linux */
err = nand_spl_load_image(
CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
- spl_image.size,
- (void *)spl_image.load_addr);
+ spl_image->size,
+ (void *)spl_image->load_addr);
nand_deselect();
return err;
} else {
@@ -127,17 +130,19 @@
}
#endif
#ifdef CONFIG_NAND_ENV_DST
- spl_nand_load_element(CONFIG_ENV_OFFSET, header);
+ spl_nand_load_element(spl_image, CONFIG_ENV_OFFSET, header);
#ifdef CONFIG_ENV_OFFSET_REDUND
- spl_nand_load_element(CONFIG_ENV_OFFSET_REDUND, header);
+ spl_nand_load_element(spl_image, CONFIG_ENV_OFFSET_REDUND, header);
#endif
#endif
/* Load u-boot */
- err = spl_nand_load_element(CONFIG_SYS_NAND_U_BOOT_OFFS, header);
+ err = spl_nand_load_element(spl_image, CONFIG_SYS_NAND_U_BOOT_OFFS,
+ header);
#ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
#if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
if (err)
- err = spl_nand_load_element(CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND,
+ err = spl_nand_load_element(spl_image,
+ CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND,
header);
#endif
#endif
@@ -145,3 +150,5 @@
return err;
}
#endif
+/* Use priorty 1 so that Ubi can override this */
+SPL_LOAD_IMAGE_METHOD("NAND", 1, BOOT_DEVICE_NAND, spl_nand_load_image);
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index ae71d26..0fba017 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -14,7 +14,9 @@
DECLARE_GLOBAL_DATA_PTR;
-int spl_net_load_image(const char *device)
+#if defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)
+static int spl_net_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
int rv;
@@ -27,12 +29,39 @@
printf("No Ethernet devices found\n");
return -ENODEV;
}
- if (device)
- setenv("ethact", device);
+ if (bootdev->boot_device_name)
+ setenv("ethact", bootdev->boot_device_name);
rv = net_loop(BOOTP);
if (rv < 0) {
printf("Problem booting with BOOTP\n");
return rv;
}
- return spl_parse_image_header((struct image_header *)load_addr);
+ return spl_parse_image_header(spl_image,
+ (struct image_header *)load_addr);
}
+#endif
+
+#ifdef CONFIG_SPL_ETH_SUPPORT
+int spl_net_load_image_cpgmac(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+#ifdef CONFIG_SPL_ETH_DEVICE
+ bootdev->boot_device_name = CONFIG_SPL_ETH_DEVICE;
+#endif
+
+ return spl_net_load_image(spl_image, bootdev);
+}
+SPL_LOAD_IMAGE_METHOD("eth device", 0, BOOT_DEVICE_CPGMAC,
+ spl_net_load_image_cpgmac);
+#endif
+
+#ifdef CONFIG_SPL_USBETH_SUPPORT
+int spl_net_load_image_usb(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ bootdev->boot_device_name = "usb_ether";
+
+ return spl_net_load_image(spl_image, bootdev);
+}
+SPL_LOAD_IMAGE_METHOD("USB eth", 0, BOOT_DEVICE_USBETH, spl_net_load_image_usb);
+#endif
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index 8ea874c..d07ca84 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -7,14 +7,15 @@
#include <common.h>
#include <spl.h>
-int spl_nor_load_image(void)
+static int spl_nor_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
int ret;
/*
* Loading of the payload to SDRAM is done with skipping of
* the mkimage header in this SPL NOR driver
*/
- spl_image.flags |= SPL_COPY_PAYLOAD_ONLY;
+ spl_image->flags |= SPL_COPY_PAYLOAD_ONLY;
#ifdef CONFIG_SPL_OS_BOOT
if (!spl_start_uboot()) {
@@ -29,14 +30,14 @@
if (image_get_os(header) == IH_OS_LINUX) {
/* happy - was a Linux */
- ret = spl_parse_image_header(header);
+ ret = spl_parse_image_header(spl_image, header);
if (ret)
return ret;
- memcpy((void *)spl_image.load_addr,
+ memcpy((void *)spl_image->load_addr,
(void *)(CONFIG_SYS_OS_BASE +
sizeof(struct image_header)),
- spl_image.size);
+ spl_image->size);
/*
* Copy DT blob (fdt) to SDRAM. Passing pointer to
@@ -59,14 +60,15 @@
* Load real U-Boot from its location in NOR flash to its
* defined location in SDRAM
*/
- ret = spl_parse_image_header(
+ ret = spl_parse_image_header(spl_image,
(const struct image_header *)CONFIG_SYS_UBOOT_BASE);
if (ret)
return ret;
- memcpy((void *)(unsigned long)spl_image.load_addr,
+ memcpy((void *)(unsigned long)spl_image->load_addr,
(void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)),
- spl_image.size);
+ spl_image->size);
return 0;
}
+SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image);
diff --git a/common/spl/spl_onenand.c b/common/spl/spl_onenand.c
index 1a28a84..fc98e9c 100644
--- a/common/spl/spl_onenand.c
+++ b/common/spl/spl_onenand.c
@@ -14,7 +14,8 @@
#include <asm/io.h>
#include <onenand_uboot.h>
-int spl_onenand_load_image(void)
+static int spl_onenand_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
struct image_header *header;
int ret;
@@ -26,11 +27,14 @@
/* Load u-boot */
onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header);
- ret = spl_parse_image_header(header);
+ ret = spl_parse_image_header(spl_image, header);
if (ret)
return ret;
onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
- spl_image.size, (void *)spl_image.load_addr);
+ spl_image->size, (void *)spl_image->load_addr);
return 0;
}
+/* Use priorty 1 so that Ubi can override this */
+SPL_LOAD_IMAGE_METHOD("OneNAND", 1, BOOT_DEVICE_ONENAND,
+ spl_onenand_load_image);
diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
index 9d8cc7c..5476206 100644
--- a/common/spl/spl_sata.c
+++ b/common/spl/spl_sata.c
@@ -20,7 +20,8 @@
DECLARE_GLOBAL_DATA_PTR;
-int spl_sata_load_image(void)
+static int spl_sata_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
int err;
struct blk_desc *stor_dev;
@@ -40,12 +41,15 @@
}
#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || spl_load_image_fat_os(stor_dev,
- CONFIG_SYS_SATA_FAT_BOOT_PARTITION))
+ if (spl_start_uboot() ||
+ spl_load_image_fat_os(spl_image, stor_dev,
+ CONFIG_SYS_SATA_FAT_BOOT_PARTITION))
#endif
- err = spl_load_image_fat(stor_dev,
- CONFIG_SYS_SATA_FAT_BOOT_PARTITION,
+ {
+ err = spl_load_image_fat(spl_image, stor_dev,
+ CONFIG_SYS_SATA_FAT_BOOT_PARTITION,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ }
if (err) {
puts("Error loading sata device\n");
return err;
@@ -53,3 +57,4 @@
return 0;
}
+SPL_LOAD_IMAGE_METHOD("SATA", 0, BOOT_DEVICE_SATA, spl_sata_load_image);
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
new file mode 100644
index 0000000..cd1d6b2
--- /dev/null
+++ b/common/spl/spl_spi.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * based on drivers/mtd/nand/nand_spl_load.c
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <errno.h>
+#include <spl.h>
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * Load the kernel, check for a valid header we can parse, and if found load
+ * the kernel and then device tree.
+ */
+static int spi_load_image_os(struct spl_image_info *spl_image,
+ struct spi_flash *flash,
+ struct image_header *header)
+{
+ int err;
+
+ /* Read for a header, parse or error out. */
+ spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40,
+ (void *)header);
+
+ if (image_get_magic(header) != IH_MAGIC)
+ return -1;
+
+ err = spl_parse_image_header(spl_image, header);
+ if (err)
+ return err;
+
+ spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS,
+ spl_image->size, (void *)spl_image->load_addr);
+
+ /* Read device tree. */
+ spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS,
+ CONFIG_SYS_SPI_ARGS_SIZE,
+ (void *)CONFIG_SYS_SPL_ARGS_ADDR);
+
+ return 0;
+}
+#endif
+
+static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ struct spi_flash *flash = load->dev;
+ ulong ret;
+
+ ret = spi_flash_read(flash, sector, count, buf);
+ if (!ret)
+ return count;
+ else
+ return 0;
+}
+/*
+ * The main entry for SPI booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from SPI into SDRAM and starts it from there.
+ */
+static int spl_spi_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ int err = 0;
+ struct spi_flash *flash;
+ struct image_header *header;
+
+ /*
+ * Load U-Boot image from SPI flash into RAM
+ */
+
+ flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+ CONFIG_SF_DEFAULT_CS,
+ CONFIG_SF_DEFAULT_SPEED,
+ CONFIG_SF_DEFAULT_MODE);
+ if (!flash) {
+ puts("SPI probe failed.\n");
+ return -ENODEV;
+ }
+
+ /* use CONFIG_SYS_TEXT_BASE as temporary storage area */
+ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+
+#ifdef CONFIG_SPL_OS_BOOT
+ if (spl_start_uboot() || spi_load_image_os(spl_image, flash, header))
+#endif
+ {
+ /* Load u-boot, mkimage header is 64 bytes. */
+ err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
+ (void *)header);
+ if (err)
+ return err;
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
+
+ debug("Found FIT\n");
+ load.dev = flash;
+ load.priv = NULL;
+ load.filename = NULL;
+ load.bl_len = 1;
+ load.read = spl_spi_fit_read;
+ err = spl_load_simple_fit(spl_image, &load,
+ CONFIG_SYS_SPI_U_BOOT_OFFS,
+ header);
+ } else {
+ err = spl_parse_image_header(spl_image, header);
+ if (err)
+ return err;
+ err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+ spl_image->size,
+ (void *)spl_image->load_addr);
+ }
+ }
+
+ return err;
+}
+/* Use priorty 1 so that boards can override this */
+SPL_LOAD_IMAGE_METHOD("SPI", 1, BOOT_DEVICE_SPI, spl_spi_load_image);
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c
index f97e1ef..24633f4 100644
--- a/common/spl/spl_ubi.c
+++ b/common/spl/spl_ubi.c
@@ -12,14 +12,15 @@
#include <ubispl.h>
#include <spl.h>
-int spl_ubi_load_image(u32 boot_device)
+int spl_ubi_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
struct image_header *header;
struct ubispl_info info;
struct ubispl_load volumes[2];
int ret = 1;
- switch (boot_device) {
+ switch (bootdev->boot_device) {
#ifdef CONFIG_SPL_NAND_SUPPORT
case BOOT_DEVICE_NAND:
nand_init();
@@ -54,7 +55,7 @@
ret = ubispl_load_volumes(&info, volumes, 2);
if (!ret) {
header = (struct image_header *)volumes[0].load_addr;
- spl_parse_image_header(header);
+ spl_parse_image_header(spl_image, header);
puts("Linux loaded.\n");
goto out;
}
@@ -68,11 +69,14 @@
ret = ubispl_load_volumes(&info, volumes, 1);
if (!ret)
- spl_parse_image_header(header);
+ spl_parse_image_header(spl_image, header);
out:
#ifdef CONFIG_SPL_NAND_SUPPORT
- if (boot_device == BOOT_DEVICE_NAND)
+ if (bootdev->boot_device == BOOT_DEVICE_NAND)
nand_deselect();
#endif
return ret;
}
+/* Use priorty 0 so that Ubi will override NAND and ONENAND methods */
+SPL_LOAD_IMAGE_METHOD("NAND", 0, BOOT_DEVICE_NAND, spl_ubi_load_image);
+SPL_LOAD_IMAGE_METHOD("OneNAND", 0, BOOT_DEVICE_ONENAND, spl_ubi_load_image);
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index 04fa667..567a450 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -22,7 +22,8 @@
static int usb_stor_curr_dev = -1; /* current device */
#endif
-int spl_usb_load_image(void)
+static int spl_usb_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
int err;
struct blk_desc *stor_dev;
@@ -47,12 +48,15 @@
debug("boot mode - FAT\n");
#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || spl_load_image_fat_os(stor_dev,
- CONFIG_SYS_USB_FAT_BOOT_PARTITION))
+ if (spl_start_uboot() ||
+ spl_load_image_fat_os(spl_image, stor_dev,
+ CONFIG_SYS_USB_FAT_BOOT_PARTITION))
#endif
- err = spl_load_image_fat(stor_dev,
- CONFIG_SYS_USB_FAT_BOOT_PARTITION,
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ {
+ err = spl_load_image_fat(spl_image, stor_dev,
+ CONFIG_SYS_USB_FAT_BOOT_PARTITION,
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ }
if (err) {
puts("Error loading from USB device\n");
@@ -61,3 +65,4 @@
return 0;
}
+SPL_LOAD_IMAGE_METHOD("USB", 0, BOOT_DEVICE_USB, spl_usb_load_image);
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 5402301..ff8085b 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -68,7 +68,8 @@
return size;
}
-int spl_ymodem_load_image(void)
+static int spl_ymodem_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
int size = 0;
int err;
@@ -102,17 +103,17 @@
info.buf = buf;
info.image_read = BUF_SIZE;
load.read = ymodem_read_fit;
- ret = spl_load_simple_fit(&load, 0, (void *)buf);
+ ret = spl_load_simple_fit(spl_image, &load, 0, (void *)buf);
size = info.image_read;
while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0)
size += res;
} else {
- spl_parse_image_header((struct image_header *)buf);
- ret = spl_parse_image_header((struct image_header *)buf);
+ ret = spl_parse_image_header(spl_image,
+ (struct image_header *)buf);
if (ret)
return ret;
- addr = spl_image.load_addr;
+ addr = spl_image->load_addr;
memcpy((void *)addr, buf, res);
size += res;
addr += res;
@@ -131,3 +132,4 @@
printf("Loaded %d bytes\n", size);
return 0;
}
+SPL_LOAD_IMAGE_METHOD("UART", 0, BOOT_DEVICE_UART, spl_ymodem_load_image);
diff --git a/common/stdio.c b/common/stdio.c
index f99cfe7..4d30017 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -37,7 +37,7 @@
#define CONFIG_SYS_DEVICE_NULLDEV 1
#endif
-#ifdef CONFIG_SYS_STDIO_DEREGISTER
+#if CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER)
#define CONFIG_SYS_DEVICE_NULLDEV 1
#endif
@@ -121,19 +121,88 @@
return &(devs.list);
}
-struct stdio_dev* stdio_get_by_name(const char *name)
+#ifdef CONFIG_DM_VIDEO
+/**
+ * stdio_probe_device() - Find a device which provides the given stdio device
+ *
+ * This looks for a device of the given uclass which provides a particular
+ * stdio device. It is currently really only useful for UCLASS_VIDEO.
+ *
+ * Ultimately we want to be able to probe a device by its stdio name. At
+ * present devices register in their probe function (for video devices this
+ * is done in vidconsole_post_probe()) and we don't know what name they will
+ * use until they do so.
+ * TODO(sjg@chromium.org): We should be able to determine the name before
+ * probing, and probe the required device.
+ *
+ * @name: stdio device name (e.g. "vidconsole")
+ * id: Uclass ID of device to look for (e.g. UCLASS_VIDEO)
+ * @sdevp: Returns stdout device, if found, else NULL
+ * @return 0 if found, -ENOENT if no device found with that name, other -ve
+ * on other error
+ */
+static int stdio_probe_device(const char *name, enum uclass_id id,
+ struct stdio_dev **sdevp)
+{
+ struct stdio_dev *sdev;
+ struct udevice *dev;
+ int seq, ret;
+
+ *sdevp = NULL;
+ seq = trailing_strtoln(name, NULL);
+ if (seq == -1)
+ seq = 0;
+ ret = uclass_get_device_by_seq(id, seq, &dev);
+ if (ret == -ENODEV)
+ ret = uclass_first_device_err(id, &dev);
+ if (ret) {
+ debug("No %s device for seq %d (%s)\n", uclass_get_name(id),
+ seq, name);
+ return ret;
+ }
+ /* The device should be be the last one registered */
+ sdev = list_empty(&devs.list) ? NULL :
+ list_last_entry(&devs.list, struct stdio_dev, list);
+ if (!sdev || strcmp(sdev->name, name)) {
+ debug("Device '%s' did not register with stdio as '%s'\n",
+ dev->name, name);
+ return -ENOENT;
+ }
+ *sdevp = sdev;
+
+ return 0;
+}
+#endif
+
+struct stdio_dev *stdio_get_by_name(const char *name)
{
struct list_head *pos;
- struct stdio_dev *dev;
+ struct stdio_dev *sdev;
- if(!name)
+ if (!name)
return NULL;
list_for_each(pos, &(devs.list)) {
- dev = list_entry(pos, struct stdio_dev, list);
- if(strcmp(dev->name, name) == 0)
- return dev;
+ sdev = list_entry(pos, struct stdio_dev, list);
+ if (strcmp(sdev->name, name) == 0)
+ return sdev;
}
+#ifdef CONFIG_DM_VIDEO
+ /*
+ * We did not find a suitable stdio device. If there is a video
+ * driver with a name starting with 'vidconsole', we can try probing
+ * that in the hope that it will produce the required stdio device.
+ *
+ * This function is sometimes called with the entire value of
+ * 'stdout', which may include a list of devices separate by commas.
+ * Obviously this is not going to work, so we ignore that case. The
+ * call path in that case is console_init_r() -> search_device() ->
+ * stdio_get_by_name().
+ */
+ if (!strncmp(name, "vidconsole", 10) && !strchr(name, ',') &&
+ !stdio_probe_device(name, UCLASS_VIDEO, &sdev))
+ return sdev;
+#endif
return NULL;
}
@@ -177,7 +246,7 @@
/* deregister the device "devname".
* returns 0 if success, -1 if device is assigned and 1 if devname not found
*/
-#ifdef CONFIG_SYS_STDIO_DEREGISTER
+#if CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER)
int stdio_deregister_dev(struct stdio_dev *dev, int force)
{
int l;
@@ -224,7 +293,7 @@
return stdio_deregister_dev(dev, force);
}
-#endif /* CONFIG_SYS_STDIO_DEREGISTER */
+#endif /* CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER) */
int stdio_init_tables(void)
{
@@ -282,6 +351,16 @@
#endif
#endif
#ifdef CONFIG_DM_VIDEO
+ /*
+ * If the console setting is not in environment variables then
+ * console_init_r() will not be calling iomux_doenv() (which calls
+ * search_device()). So we will not dynamically add devices by
+ * calling stdio_probe_device().
+ *
+ * So just probe all video devices now so that whichever one is
+ * required will be available.
+ */
+#ifndef CONFIG_SYS_CONSOLE_IS_IN_ENV
struct udevice *vdev;
# ifndef CONFIG_DM_KEYBOARD
int ret;
@@ -293,6 +372,7 @@
;
if (ret)
printf("%s: Video device failed (ret=%d)\n", __func__, ret);
+#endif /* !CONFIG_SYS_CONSOLE_IS_IN_ENV */
#else
# if defined(CONFIG_LCD)
drv_lcd_init ();
diff --git a/common/usb.c b/common/usb.c
index b3ba487..15e1e4c 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -557,12 +557,10 @@
static int usb_get_descriptor(struct usb_device *dev, unsigned char type,
unsigned char index, void *buf, int size)
{
- int res;
- res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
- USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
- (type << 8) + index, 0,
- buf, size, USB_CNTL_TIMEOUT);
- return res;
+ return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+ USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
+ (type << 8) + index, 0, buf, size,
+ USB_CNTL_TIMEOUT);
}
/**********************************************************************
@@ -612,14 +610,10 @@
*/
static int usb_set_address(struct usb_device *dev)
{
- int res;
-
debug("set address %d\n", dev->devnum);
- res = usb_control_msg(dev, usb_snddefctrl(dev),
- USB_REQ_SET_ADDRESS, 0,
- (dev->devnum), 0,
- NULL, 0, USB_CNTL_TIMEOUT);
- return res;
+
+ return usb_control_msg(dev, usb_snddefctrl(dev), USB_REQ_SET_ADDRESS,
+ 0, (dev->devnum), 0, NULL, 0, USB_CNTL_TIMEOUT);
}
/********************************************************************
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 97f79f8..5f9a64a 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -570,7 +570,7 @@
/* Deregister the keyboard. */
int usb_kbd_deregister(int force)
{
-#ifdef CONFIG_SYS_STDIO_DEREGISTER
+#if CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER)
struct stdio_dev *dev;
struct usb_device *usb_kbd_dev;
struct usb_kbd_pdata *data;
@@ -605,11 +605,8 @@
static int usb_kbd_probe(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- int ret;
- ret = probe_usb_keyboard(udev);
-
- return ret;
+ return probe_usb_keyboard(udev);
}
static int usb_kbd_remove(struct udevice *dev)
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 7e6e52d..0345aa2 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -708,13 +708,10 @@
/* clear a stall on an endpoint - special for BBB devices */
static int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt)
{
- int result;
-
/* ENDPOINT_HALT = 0, so set value to 0 */
- result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0),
- USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT,
- 0, endpt, NULL, 0, USB_CNTL_TIMEOUT * 5);
- return result;
+ return usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0),
+ USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0,
+ endpt, NULL, 0, USB_CNTL_TIMEOUT * 5);
}
static int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
diff --git a/common/xyzModem.c b/common/xyzModem.c
index 5656aac..e0d87db 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -71,12 +71,12 @@
static int
CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
{
-#define DELAY 20
- unsigned long counter = 0;
- while (!tstc () && (counter < xyzModem_CHAR_TIMEOUT * 1000 / DELAY))
+
+ ulong now = get_timer(0);
+ while (!tstc ())
{
- udelay (DELAY);
- counter++;
+ if (get_timer(now) > xyzModem_CHAR_TIMEOUT)
+ break;
}
if (tstc ())
{
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index 05fad1e..a7ae4fa 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -3,6 +3,7 @@
CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index dc0d74a..65fab38 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -3,6 +3,7 @@
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 8cb7ac7..50436a7 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -1,14 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_EMR1=4
CONFIG_SYS_CLK_FREQ=912000000
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index 6a0d815..e2bebf8 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG1"
@@ -8,8 +9,8 @@
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index a790856..361d90a 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -12,8 +12,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index d12a3cc..3191098 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
@@ -14,13 +15,14 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
+CONFIG_DFU_RAM=y
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index cc5858e..8fd7c64 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -1,19 +1,30 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
+CONFIG_DFU_RAM=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 7b0309c..26e6ace 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index f121cab..d629eb1 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
@@ -7,9 +8,10 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_VIDEO_VGA=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 57609b3..b5d52db 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -1,7 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC3_CD_PIN="PH0"
CONFIG_MMC3_PINS="PH"
@@ -9,9 +10,10 @@
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index fc1be7d..46c5309 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=123
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index 8262be5..5020724 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG0"
@@ -14,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 44f3982..1e248a7 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 9d5365d..55f956e 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index cc3e9ec..5ee32b8 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_B4420QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_SF=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index 2c2e3c2..69e47a2 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -1,12 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
+CONFIG_TARGET_B4420QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_SF=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index bfd64af..abc6a7c 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -1,12 +1,13 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
+CONFIG_TARGET_B4420QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index 7dbcb45..56e7318 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index c6e560d..3a77f0d 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -1,4 +1,6 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +8,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_SF=y
@@ -27,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index 52f78be..9bebdf7 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -1,12 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index cd80c91..d832455 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -1,12 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GREPENV=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index 1f642e3..fd00b60 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -1,12 +1,13 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_SF=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index b8b654e..8c1ab70 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -1,13 +1,17 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
+CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -21,8 +25,10 @@
CONFIG_CMD_FAT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index c05ad2a..f8de2e6 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -1,13 +1,17 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -21,8 +25,10 @@
CONFIG_CMD_FAT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index 9045567..940b536 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -1,12 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -20,8 +22,10 @@
CONFIG_CMD_FAT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
index 178618c..481fd92 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -1,12 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -20,8 +22,10 @@
CONFIG_CMD_FAT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index 67dc545..c05788c 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,6 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index c4a824b..dde8fdb 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -1,13 +1,16 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
+CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -27,3 +30,4 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index 3db7dea..b501c20 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,6 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index 3c4e296..e44aac3 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -1,13 +1,16 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
+CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -27,3 +30,4 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index bef3077..61655c7 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,6 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
index 4c9c955..db14156 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
@@ -5,8 +5,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -26,3 +27,4 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index 7e54d77..3c71a0b 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,6 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
index 4bc83ef..9076f0b 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
@@ -5,8 +5,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -26,3 +27,4 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index 9ecdff9..63a208c 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,6 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
index f16b1b1..caa7015 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
@@ -5,8 +5,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -26,3 +27,4 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index 773322c..9e540c4 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,6 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
index a9555db..1c42d90 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
@@ -5,8 +5,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -26,3 +27,4 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index 3e7b651..6b445d6 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,6 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
index c86ce6f..258862f 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
@@ -5,8 +5,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -26,3 +27,4 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 7442025..8994e99 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,6 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
index da71c54..cc4e385 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
@@ -5,8 +5,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -26,3 +27,4 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index d9b1bd6..0f2ef1b 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -1,13 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 496c20e..e3bb4b2 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PH0"
@@ -7,9 +8,10 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index 7db345e..e2490dc 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -1,14 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
-CONFIG_SPL=y
-CONFIG_TPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index 1dbb8ad..801c10e 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -1,4 +1,6 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +8,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,SECURE_BOOT"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
@@ -22,4 +24,5 @@
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index 407093c..0639457 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -1,4 +1,6 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +8,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
@@ -22,4 +25,5 @@
CONFIG_SYS_NS16550=y
CONFIG_FSL_ESPI=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
index ff16c7a..dc536a7 100644
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_defconfig
@@ -1,12 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
index 8dd57d2..5d7f03e 100644
--- a/configs/C29XPCIE_defconfig
+++ b/configs/C29XPCIE_defconfig
@@ -1,12 +1,13 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 19ae280..65d0c98 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -1,16 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
# CONFIG_MMC is not set
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_DFU_RAM=y
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/CPCI2DP_defconfig b/configs/CPCI2DP_defconfig
index 470e070..2dfd63c 100644
--- a/configs/CPCI2DP_defconfig
+++ b/configs/CPCI2DP_defconfig
@@ -1,7 +1,9 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CPCI2DP=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig
index 32e1cb1..b5135f7 100644
--- a/configs/CPCI4052_defconfig
+++ b/configs/CPCI4052_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CPCI4052=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index 1cb010d..448ce95 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -6,8 +6,8 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 3257aae..8507f73 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 2ce8cb1..d8272c5 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -16,8 +16,8 @@
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 4b9d722..dfeb66c 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
new file mode 100644
index 0000000..4d36d39
--- /dev/null
+++ b/configs/Cubieboard4_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN9I=y
+CONFIG_DRAM_CLK=672
+CONFIG_MMC0_CD_PIN="PH18"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH16"
+CONFIG_USB1_VBUS_PIN="PH14"
+CONFIG_USB3_VBUS_PIN="PH15"
+CONFIG_AXP_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cubieboard4"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP809_POWER=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index c884115..64aebed 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 4e25392..10f3237 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH1"
@@ -9,14 +10,16 @@
CONFIG_VIDEO_VGA=y
CONFIG_GMAC_TX_DELAY=1
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPH(12)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
+CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index f2c6fe7..dbe3336 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -13,6 +13,7 @@
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index d8c8957..4c124d9 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -1,12 +1,13 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_CYRUS=y
+CONFIG_TARGET_CYRUS_P5020=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
+CONFIG_CONSOLE_MUX=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GREPENV=y
@@ -25,4 +26,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index f5d3cc2..aa68322 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -1,12 +1,13 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_CYRUS=y
+CONFIG_TARGET_CYRUS_P5040=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
+CONFIG_CONSOLE_MUX=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GREPENV=y
@@ -25,4 +26,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 5f01760..831949a 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
@@ -15,8 +16,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig
index 224098f..4b51380 100644
--- a/configs/Empire_electronix_m712_defconfig
+++ b/configs/Empire_electronix_m712_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PG0"
@@ -14,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 3b0c439..dc4133d 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -8,8 +8,8 @@
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index fef3685..41cb877 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_EMR1=4
CONFIG_USB0_VBUS_PIN="PB09"
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index cb6dfe4..baca3e8 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index d2111c6..6fe79e2 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -1,13 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH10"
CONFIG_GMAC_TX_DELAY=4
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),SATAPWR=SUNXI_GPB(3)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 378abce..622d35c 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -1,14 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
CONFIG_USB1_VBUS_PIN="PH11"
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPH(2)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index c3f0421..9d2dfa5a 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=122
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPH(2)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 9d8d325..ab094a6 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -1,12 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 5b0c65a..405405d 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M5208EVBE=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
index 3606700..f7aee4b 100644
--- a/configs/M52277EVB_defconfig
+++ b/configs/M52277EVB_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
index af463c3..200bf35 100644
--- a/configs/M52277EVB_stmicro_defconfig
+++ b/configs/M52277EVB_stmicro_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index eff91ec..6581802 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0xFFC00000
CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_I2C=y
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 28c7f20..15a7f1f 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index 1588c52..2470aa2 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -1,6 +1,8 @@
CONFIG_M68K=y
CONFIG_TARGET_M5249EVB=y
CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_AUTOBOOT is not set
CONFIG_LOOPW=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index e758873..621cb8f 100644
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M5253DEMO=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
diff --git a/configs/M5253EVBE_defconfig b/configs/M5253EVBE_defconfig
index 17ded58..4b81ba4 100644
--- a/configs/M5253EVBE_defconfig
+++ b/configs/M5253EVBE_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M5253EVBE=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 7638b18..9eb3c34 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M5272C3=y
CONFIG_SYS_TEXT_BASE=0xffe00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index a7af356..9abc596 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M5275EVB=y
CONFIG_SYS_TEXT_BASE=0xffe00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index f415f7b..9e2f925 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M5282EVB=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index 9a5d36a..e1b08f4 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M53017EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index f09af5e..9a23f9b 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index 9954afa..aa4897f 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 6f89dd2..41e5a29 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
index be7a37f..cecc78e 100644
--- a/configs/M54418TWR_defconfig
+++ b/configs/M54418TWR_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
index c04e9ca..81ddca9 100644
--- a/configs/M54418TWR_nand_mii_defconfig
+++ b/configs/M54418TWR_nand_mii_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
index 3f454e9..069245a 100644
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ b/configs/M54418TWR_nand_rmii_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
index 2206554..3d80361 100644
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
index 244fc73..f84fa4e 100644
--- a/configs/M54418TWR_serial_mii_defconfig
+++ b/configs/M54418TWR_serial_mii_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
index be7a37f..cecc78e 100644
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ b/configs/M54418TWR_serial_rmii_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig
index 62bd368..190edf0 100644
--- a/configs/M5475AFE_defconfig
+++ b/configs/M5475AFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig
index fa5e1e1..76935b1 100644
--- a/configs/M5475BFE_defconfig
+++ b/configs/M5475BFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig
index 1fa20f1..e947b4c 100644
--- a/configs/M5475CFE_defconfig
+++ b/configs/M5475CFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig
index 5db3b8d..577eced 100644
--- a/configs/M5475DFE_defconfig
+++ b/configs/M5475DFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig
index a0361f7..ad9a57b 100644
--- a/configs/M5475EFE_defconfig
+++ b/configs/M5475EFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig
index bfccc65..7338822 100644
--- a/configs/M5475FFE_defconfig
+++ b/configs/M5475FFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig
index bdba915..751fbc8 100644
--- a/configs/M5475GFE_defconfig
+++ b/configs/M5475GFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig
index cc29cdf..125d85e 100644
--- a/configs/M5485AFE_defconfig
+++ b/configs/M5485AFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig
index 3fd6ba9..431938f 100644
--- a/configs/M5485BFE_defconfig
+++ b/configs/M5485BFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig
index 116ee61..5b9a30c 100644
--- a/configs/M5485CFE_defconfig
+++ b/configs/M5485CFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig
index d4d9344..f9dacc0 100644
--- a/configs/M5485DFE_defconfig
+++ b/configs/M5485DFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig
index 5c23652..6ae30de 100644
--- a/configs/M5485EFE_defconfig
+++ b/configs/M5485EFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig
index c1622d7..f132ac7 100644
--- a/configs/M5485FFE_defconfig
+++ b/configs/M5485FFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig
index c556fe1..4070b26 100644
--- a/configs/M5485GFE_defconfig
+++ b/configs/M5485GFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig
index a5a533a..d520bb4 100644
--- a/configs/M5485HFE_defconfig
+++ b/configs/M5485HFE_defconfig
@@ -10,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig
index c9913ae..76d0ef4 100644
--- a/configs/MIP405T_defconfig
+++ b/configs/MIP405T_defconfig
@@ -1,8 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10082-001 released"
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_4xx=y
-CONFIG_TARGET_MIP405=y
-CONFIG_SYS_EXTRA_OPTIONS="MIP405T"
+CONFIG_TARGET_MIP405T=y
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
@@ -12,3 +19,5 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_SYS_NS16550=y
+CONFIG_CONSOLE_EXTRA_INFO=y
+CONFIG_VIDEO_CT69000=y
diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig
index c32bdd3..0c358f9 100644
--- a/configs/MIP405_defconfig
+++ b/configs/MIP405_defconfig
@@ -1,7 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10072-001 released"
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_4xx=y
CONFIG_TARGET_MIP405=y
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
@@ -14,3 +22,6 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_EXTRA_INFO=y
+CONFIG_VIDEO_CT69000=y
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index 49bb26a..1e8f9db 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index 2fdffa9..2513632 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index 56538cc..9d611fc 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index efabb9a..79a9c27 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -1,11 +1,14 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
-CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
CONFIG_BOOTDELAY=6
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index be0e274..aa4a1c4 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -1,11 +1,14 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
-CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
CONFIG_BOOTDELAY=6
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index 50fa786..4e2b705 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8315ERDB=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index 5e5a2d0..043ab9b 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8323ERDB=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index 72aacf3..7d59149 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
@@ -10,5 +11,6 @@
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index 3e7390f..5a53b1d2 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -1,9 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
+CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1"
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index c65d3c9..9a47c62 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -1,9 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
+CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1"
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index 5c95787..cdd3d77 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -1,9 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index 4d7c52f..af617e6 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,5 +10,6 @@
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index 7ed7923..3a8844e 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349EMDS=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,5 +10,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index f1afcf8..e85ec16 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index 10299f5..56e9607 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 4a63f49..8cdcf2b 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 89f7215..8795f70 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -3,7 +3,6 @@
CONFIG_TARGET_MPC837XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI"
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index c04c256..3113e0f 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -12,5 +12,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index 27d5826..bb975d2 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -14,6 +16,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
index eaeacca..59986ae 100644
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ b/configs/MPC8536DS_SDCARD_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -14,6 +16,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
index 525ccad..83eb24d 100644
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ b/configs/MPC8536DS_SPIFLASH_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -14,6 +16,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
index 0ff061b..9661a81 100644
--- a/configs/MPC8536DS_defconfig
+++ b/configs/MPC8536DS_defconfig
@@ -1,9 +1,11 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -13,6 +15,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig
index e3cb0d5..6291111 100644
--- a/configs/MPC8540ADS_defconfig
+++ b/configs/MPC8540ADS_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8540ADS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
index 1ea8800..fc0aa99 100644
--- a/configs/MPC8541CDS_defconfig
+++ b/configs/MPC8541CDS_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
index ae529d1..61eed37 100644
--- a/configs/MPC8541CDS_legacy_defconfig
+++ b/configs/MPC8541CDS_legacy_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
index 13bbe84..d160f04 100644
--- a/configs/MPC8544DS_defconfig
+++ b/configs/MPC8544DS_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8544DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 5d834e6..65e937f 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_PHYS_64BIT=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index ee400a3..6842170 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index b733461..defdfc0 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
index da42112..9f9168a 100644
--- a/configs/MPC8555CDS_defconfig
+++ b/configs/MPC8555CDS_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
index fb14891..51d17ad 100644
--- a/configs/MPC8555CDS_legacy_defconfig
+++ b/configs/MPC8555CDS_legacy_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig
index 67063c8..5a8cc26 100644
--- a/configs/MPC8560ADS_defconfig
+++ b/configs/MPC8560ADS_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8560ADS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index 2e7dceb..c6bc814 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8568MDS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index ec57018..64210eb 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -1,4 +1,6 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8572DS=y
CONFIG_PHYS_64BIT=y
@@ -7,12 +9,14 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
index 0639b4f..1c6765d 100644
--- a/configs/MPC8572DS_defconfig
+++ b/configs/MPC8572DS_defconfig
@@ -1,4 +1,6 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8572DS=y
CONFIG_FIT=y
@@ -6,12 +8,14 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
index 10607e8..563896d 100644
--- a/configs/MPC8610HPCD_defconfig
+++ b/configs/MPC8610HPCD_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8610HPCD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
@@ -12,4 +15,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_KEYBOARD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index 2292360..9bd0e3d 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -1,10 +1,13 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
@@ -12,4 +15,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_KEYBOARD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index d8f74b3..43a5290 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
@@ -11,4 +14,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_KEYBOARD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index 5559444..87fd3b9 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index cef9794..0d381ff 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -2,9 +2,10 @@
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index 2ac2596..4097e5b 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -7,8 +7,8 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index f076e30..820d5ed 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index eccf372..eb3c74c 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -6,8 +6,8 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index d72dcc0..037e768 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
@@ -8,8 +9,8 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 0d1ba15..e64e452 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -1,14 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=122
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index f0b4384..c4e5993 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -6,8 +6,8 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 198fda9..6397de5 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -1,12 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN9I=y
-CONFIG_DRAM_CLK=360
-CONFIG_DRAM_ZQ=123
-CONFIG_SYS_CLK_FREQ=1008000000
+CONFIG_DRAM_CLK=672
CONFIG_MMC0_CD_PIN="PH18"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH3"
+CONFIG_USB1_VBUS_PIN="PH4"
+CONFIG_USB3_VBUS_PIN="PH5"
+CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_AXP809_POWER=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 53f9bfe..87fac82 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig
index 266f2ce..ff79c12 100644
--- a/configs/MiniFAP_defconfig
+++ b/configs/MiniFAP_defconfig
@@ -1,9 +1,13 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="MINIFAP"
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
@@ -18,4 +22,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig
new file mode 100644
index 0000000..fcda1be
--- /dev/null
+++ b/configs/Nintendo_NES_Classic_Edition_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=600
+CONFIG_DRAM_ZQ=15291
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_MMC is not set
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_AXP_ELDO2_VOLT=1800
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig
index 3b36d8f..36c55b6 100644
--- a/configs/O2D300_defconfig
+++ b/configs/O2D300_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2D300=y
CONFIG_OF_BOARD_SETUP=y
@@ -10,4 +11,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig
index 977da33..b374c28 100644
--- a/configs/O2DNT2_RAMBOOT_defconfig
+++ b/configs/O2DNT2_RAMBOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2DNT2=y
CONFIG_OF_BOARD_SETUP=y
@@ -14,4 +15,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig
index 32e475d..00a713b 100644
--- a/configs/O2DNT2_defconfig
+++ b/configs/O2DNT2_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2DNT2=y
CONFIG_OF_BOARD_SETUP=y
@@ -13,4 +14,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig
index 22e8357..9bc2342 100644
--- a/configs/O2D_defconfig
+++ b/configs/O2D_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2D=y
CONFIG_OF_BOARD_SETUP=y
@@ -10,4 +11,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig
index a1c2794..2f3276c 100644
--- a/configs/O2I_defconfig
+++ b/configs/O2I_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2I=y
CONFIG_OF_BOARD_SETUP=y
@@ -10,4 +11,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig
index f33496c..57c9f7b 100644
--- a/configs/O2MNT_O2M110_defconfig
+++ b/configs/O2MNT_O2M110_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_OF_BOARD_SETUP=y
@@ -11,4 +12,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig
index 04a8fdd..3afa43b 100644
--- a/configs/O2MNT_O2M112_defconfig
+++ b/configs/O2MNT_O2M112_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_OF_BOARD_SETUP=y
@@ -11,4 +12,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig
index 2e4b8ab..a543a3b 100644
--- a/configs/O2MNT_O2M113_defconfig
+++ b/configs/O2MNT_O2M113_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_OF_BOARD_SETUP=y
@@ -11,4 +12,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig
index 9176431..859ba73 100644
--- a/configs/O2MNT_defconfig
+++ b/configs/O2MNT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_OF_BOARD_SETUP=y
@@ -10,4 +11,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig
index 55054ac..c4f2f69 100644
--- a/configs/O3DNT_defconfig
+++ b/configs/O3DNT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O3DNT=y
CONFIG_OF_BOARD_SETUP=y
@@ -10,4 +11,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 00c671b..ccece01 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PH26"
@@ -8,9 +9,10 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index a865255..febdcd0 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH10"
@@ -10,9 +11,10 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index 003b332..3a5b844 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -1,14 +1,16 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 42dbec3..f769d58 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -1,15 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
-CONFIG_TPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index 55f0765..881afc5 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -1,14 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 6de688f..3b6f420 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -1,13 +1,13 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 34e7d8f..45021e9 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -1,14 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index 63b9c31..ed10fcf 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -1,14 +1,16 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 154c790..1d512de 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -1,14 +1,24 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index 5f6d184..8677c66 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -1,13 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -27,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 5bdcae0..09a97ad 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -1,14 +1,24 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
-CONFIG_SPL=y
-CONFIG_TPL=y
+CONFIG_TARGET_P1010RDB_PA=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index e0dff12..9e99739 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -1,13 +1,14 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -27,4 +28,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index e25da5c..f7312f9 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -1,12 +1,12 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index eb96978..d63f4d8 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -1,13 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1010RDB_PA=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index f1a2705..7826443 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -1,13 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -27,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 1cec61a..ace1077 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1010RDB_PA=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index 4639c2e..b1fc348 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -1,14 +1,16 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 3056310..b7e29e3 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -1,15 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
-CONFIG_TPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index b70ff00..53d0adc 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -1,14 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index e751041..091f578 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -1,13 +1,13 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index f4a9b37..089082d 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -1,14 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 5392e61..8bd846c 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -1,14 +1,16 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -28,4 +30,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 9263b68..2d356ae 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -1,14 +1,24 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index 61d503d..3613049 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -1,13 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -27,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index f2aefdd..6310512 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -1,14 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
-CONFIG_SPL=y
-CONFIG_TPL=y
+CONFIG_TARGET_P1010RDB_PB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index 899c8c8..fcba2f0 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -1,13 +1,14 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -27,4 +28,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index d477a88..ec27153 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -1,12 +1,12 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 3b17795..5770ae9 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -1,13 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1010RDB_PB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index 832d3ae..d14bf14 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -1,13 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
+CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -27,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index a6b53b9..f63c0dc 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1010RDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1010RDB_PB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index 1af48fd..d3fb861 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -1,14 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020MBG=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index 3eb32f8..ccf8398 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -1,12 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020MBG=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index f22730e..c9fdcc5 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -1,13 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1020MBG=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
index 4f87745..c832993 100644
--- a/configs/P1020MBG-PC_defconfig
+++ b/configs/P1020MBG-PC_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020MBG=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index b715c76..a316907 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -1,15 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
-CONFIG_TPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 7951088..ce9d293 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -1,14 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 0dba3b8..d6c06fe 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -1,14 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 8033e71..2598e15 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -1,12 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 8aebfd2..7ed4d97 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -1,14 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
-CONFIG_TPL=y
+CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 71d1d0e..b75aa5e 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -1,13 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index ec7f62f..7134a19 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 7411c14..99bc59c 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 62d7e58..86cf952 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -1,14 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
-CONFIG_TPL=y
+CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 4606ab5..7131bce 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -1,13 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 8a4383c..3bc9afd 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index ecb2272..1cae066 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index bea36b5..19e448d 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -1,14 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020UTM=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index 7044b78..aa266f9 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -1,12 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020UTM=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index 94ba43d..c03c7c5 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -1,13 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1020UTM=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
index 9f70afd..c47d514 100644
--- a/configs/P1020UTM-PC_defconfig
+++ b/configs/P1020UTM-PC_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1020UTM=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index bc912d0..82dcec5 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -1,15 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
-CONFIG_TPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index eca4c59..2ef2eda 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -1,14 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index b1b57af..f7910b6 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -1,14 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index 6c1cb28..87d45b2 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -1,12 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index 139be5a..29335b1 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -1,14 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
-CONFIG_TPL=y
+CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 5891165..bde4d3d 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -1,13 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index e5be60e..4f1db4f 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index b7b93e2..e26967b 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index 8303305..3d63c8e 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -1,15 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
-CONFIG_TPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index e365f1b..19f0b0d 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -1,14 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index f0ea572..fdf969d 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -1,14 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index 4292b51..11efa48 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -1,14 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
-CONFIG_SPL=y
-CONFIG_TPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index 55fc15d..1f1f621 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -1,13 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index d921bd7..60b4981 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
index 80fcfe1..3001575 100644
--- a/configs/P1023RDB_defconfig
+++ b/configs/P1023RDB_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_P1023RDB=y
CONFIG_FIT=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index 46cd391..7672464 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -1,12 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1024RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index 082aaa9..f4d5485 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -1,14 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
-CONFIG_TPL=y
+CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index 529b9fd..101647f 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -1,13 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index ef7fb02..94c45c0 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
index 7dffb2b..0d20475 100644
--- a/configs/P1024RDB_defconfig
+++ b/configs/P1024RDB_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index d94c7af..2715182 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -1,12 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1025RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index 02d6d06..90e8367 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -1,14 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
-CONFIG_TPL=y
+CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index b494a35..90b005a 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -1,13 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index 3bae2a8..0e5335d 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index 80e997d..7094db4 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 8b86e92..d8f375b 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -1,15 +1,24 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
-CONFIG_TPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index e1d1b12..d5e44a0 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -1,14 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index f4e3c6e..7112255 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -1,14 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index c422273..a2af2d7 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -1,12 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index ebf61aa..fd36351c 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -1,14 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
-CONFIG_TPL=y
+CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_TPL=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_I2C_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 88f211f..7330926 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -1,13 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index cffbf4b..2d380d5 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
-CONFIG_SPL=y
+CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 7c40cd6..7fc2dcd 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index cc572ff..c751a9b 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,7 +7,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index c88b0e2..dc99ed6 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,7 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +30,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index 6fdbbb6..755dfc5 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,7 +7,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 97d5da9..7b41915 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,7 +7,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index 04da207..60d890d 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,7 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +30,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index 313f95d..b6fdedd 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,7 +7,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index 9d2f97f..8b52375 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,7 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +30,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 68c1b3b..512c7ad 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,7 +7,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig
index 53fdfad..ae1c1b6 100644
--- a/configs/PATI_defconfig
+++ b/configs/PATI_defconfig
@@ -1,7 +1,11 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10084-001 released"
+# CONFIG_MMC is not set
CONFIG_5xx=y
CONFIG_TARGET_PATI=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="pati=> "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_IMLS is not set
@@ -15,3 +19,4 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+# CONFIG_PCI is not set
diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig
index 8ed89a9..229448f 100644
--- a/configs/PIP405_defconfig
+++ b/configs/PIP405_defconfig
@@ -1,7 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING="\n(c) 2002 by MPL AG Switzerland, MEV-10066-001 released"
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_4xx=y
CONFIG_TARGET_PIP405=y
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
@@ -14,3 +22,6 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_EXTRA_INFO=y
+CONFIG_VIDEO_CT69000=y
diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig
index e84a88e..fe26fed 100644
--- a/configs/PLU405_defconfig
+++ b/configs/PLU405_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_PLU405=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
@@ -14,6 +16,7 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig
index 8f1410e..fe96b07 100644
--- a/configs/PMC405DE_defconfig
+++ b/configs/PMC405DE_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_PMC405DE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig
index af38882..8c4454e 100644
--- a/configs/PMC440_defconfig
+++ b/configs/PMC440_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_PMC440=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index ae1f1e8..9ac8912 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -10,8 +10,8 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 013c35e..26b119a 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -3,9 +3,25 @@
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=15291
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_DFU=y
# CONFIG_CMD_FPGA is not set
+CONFIG_DFU_RAM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index 181e1e2..267aaf8 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -6,8 +6,8 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 77b0525..d15ac20 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -13,8 +13,9 @@
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 8e6edda..71de2a5 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -1,13 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1023RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index 9bf1a69..dee5690 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -1,13 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1023RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index 25dd68c..0fae73c 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -1,13 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
+CONFIG_TARGET_T1023RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
@@ -30,4 +32,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index 42f2906..5fd23e8 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1023RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index af99ff0..255da1b 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -1,12 +1,12 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
+CONFIG_TARGET_T1023RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index 2c6f6ad..f067c8c 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -1,13 +1,17 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XQDS=y
+CONFIG_TARGET_T1024QDS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -31,4 +35,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index 7767e0d..b717fd7 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -1,12 +1,15 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XQDS=y
+CONFIG_TARGET_T1024QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index 94ecedd..861025b 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -1,13 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XQDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1024QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -19,6 +31,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 786e5fb..cda5f5c 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -1,13 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XQDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1024QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -19,6 +31,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index f502750..a2afdd4 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -1,13 +1,17 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XQDS=y
+CONFIG_TARGET_T1024QDS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -20,6 +24,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -31,4 +36,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 4b1a22d..c454553 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -1,13 +1,26 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XQDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1024QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -19,6 +32,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index b0e9827..0a9e20c 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -1,12 +1,15 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XQDS=y
+CONFIG_TARGET_T1024QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -18,6 +21,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 2509db0..bf3f46f 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
@@ -20,6 +30,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index e2e38af..1c2b362 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
@@ -20,6 +30,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index cb33280..ba43e80 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -1,13 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
+CONFIG_TARGET_T1024RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
@@ -21,6 +23,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
@@ -30,4 +33,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index f9dd8a0..7855780 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -1,13 +1,24 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
@@ -20,6 +31,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index e013fdc..86eaccc 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -1,12 +1,13 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T102XRDB=y
+CONFIG_TARGET_T1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
@@ -19,6 +20,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index 2cd364b..f807077 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1040D4RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index 9e8e246..ebba63d 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1040D4RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index 87ab7e2..816dbb2 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -1,13 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
+CONFIG_TARGET_T1040D4RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -29,4 +31,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index 77ab8fb..d0b05b8 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -1,13 +1,24 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1040D4RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index fc28d1f..a0ea458 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -1,12 +1,13 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
+CONFIG_TARGET_T1040D4RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index 4f470aa..1c183f4 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -1,12 +1,15 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index 1b4f654..aa1ae6e 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -1,4 +1,6 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,8 +8,10 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -20,6 +24,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -31,4 +36,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index dd53bb4..30b0701 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -1,12 +1,15 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -18,6 +21,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 26bbd62..85b0a4a 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1040RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -19,6 +29,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index e66db8e..1b926c3 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -1,13 +1,23 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1040RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -19,6 +29,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index 43b0539..634a1c2 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -1,13 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
+CONFIG_TARGET_T1040RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -20,6 +22,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
@@ -29,4 +32,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index f700359..257df4b 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -1,13 +1,24 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1040RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -19,6 +30,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index 28b7bb4..7929c99 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -1,12 +1,13 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
+CONFIG_TARGET_T1040RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -18,6 +19,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 0547eca..6dcafb1 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -1,13 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1042D4RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -27,4 +39,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index cbd2f0d..db2b220 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -1,13 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1042D4RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -27,4 +39,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index 97a42db..4318b96 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -1,13 +1,17 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
+CONFIG_TARGET_T1042D4RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -28,5 +32,7 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 319ebe2..78b036a 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -1,13 +1,26 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1042D4RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -27,4 +40,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index f611baf..5992559 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -1,12 +1,15 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
+CONFIG_TARGET_T1042D4RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -26,4 +29,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
index 93d0b9b..0daf8a7 100644
--- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
@@ -1,13 +1,28 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1042RDB_PI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=0
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_CRYPTO_SUPPORT=y
+CONFIG_SPL_HASH_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -20,6 +35,8 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
@@ -28,5 +45,7 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index 1a90e8d..5ea696c 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -1,13 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1042RDB_PI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -19,6 +31,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
@@ -27,4 +40,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index 9e0926f..f36e0ec 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -1,13 +1,25 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1042RDB_PI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -19,6 +31,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
@@ -27,4 +40,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index 3518087..39d9fad 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -1,13 +1,26 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T1042RDB_PI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -19,6 +32,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
@@ -27,4 +41,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index 7d70b57..0eee7a5 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -1,12 +1,15 @@
CONFIG_PPC=y
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
+CONFIG_TARGET_T1042RDB_PI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -18,6 +21,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
@@ -26,4 +30,5 @@
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index c9d360c..6080bf5 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -1,13 +1,15 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
+CONFIG_TARGET_T1042RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -20,6 +22,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
@@ -29,4 +32,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index 817c0dc..19230e55 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -1,12 +1,13 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T104XRDB=y
+CONFIG_TARGET_T1042RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
CONFIG_BOOTDELAY=10
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -18,6 +19,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index a0d709a..834e441 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 060144b..2393bc7 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index f23fb9c..bb13249 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -1,12 +1,12 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
+CONFIG_TARGET_T2080QDS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -31,4 +31,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index de35db3..e4568b6 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -1,13 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 4a80068..282e1c2 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -1,11 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
+CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 7e23651..393d4e5 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
+CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index ca1b699..f548e38 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 78aaa29..ec4e576 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index a4a9285..0e2ff06 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -1,12 +1,12 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XRDB=y
+CONFIG_TARGET_T2080RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
@@ -29,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 5de5714..34e1c67 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -1,13 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XRDB=y
-CONFIG_SPL=y
+CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index 1b8ede8..4b32880 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -1,11 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XRDB=y
+CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 94c2e08..14310c4 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XRDB=y
+CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 0b97fdb..34350aa 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index 9716886..630a5ce 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index 21a7a05..0c43f89 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -1,13 +1,22 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index 4caa2e4..1665ca5 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -1,11 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
+CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index 07ff6b6..822b92f 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T208XQDS=y
+CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index e5cd04c..2d2297b 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T4160QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index ee5902c..95a2a3f 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
-CONFIG_SPL=y
+CONFIG_TARGET_T4160QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 1e32b64..d0e4f11 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -1,12 +1,12 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
+CONFIG_TARGET_T4160QDS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index 109d610..46ec844 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
+CONFIG_TARGET_T4160QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index 9336a3f..b768368 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -1,11 +1,10 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240RDB=y
+CONFIG_TARGET_T4160RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index 4dea4fb..493f3c1 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index 1aa1035..2357d82 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index 26a5717..f2cf58a 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
# CONFIG_SYS_MALLOC_F is not set
@@ -6,7 +7,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
@@ -29,4 +29,5 @@
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index 91cd3cf..7e9b97e 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -5,7 +5,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index a9c263e..559da71 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -5,7 +5,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index b1e4dec..ef299aa 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -1,13 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index b688a57..bf35762 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -5,7 +5,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig
index 8afa7ce..df873ee 100644
--- a/configs/TQM5200S_HIGHBOOT_defconfig
+++ b/configs/TQM5200S_HIGHBOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig
index c30c717..2a59758 100644
--- a/configs/TQM5200S_defconfig
+++ b/configs/TQM5200S_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig
index be90d79..73ff161 100644
--- a/configs/TQM5200_B_HIGHBOOT_defconfig
+++ b/configs/TQM5200_B_HIGHBOOT_defconfig
@@ -1,9 +1,13 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000"
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
@@ -18,4 +22,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig
index a405e92..c0d5c4b 100644
--- a/configs/TQM5200_B_defconfig
+++ b/configs/TQM5200_B_defconfig
@@ -1,9 +1,13 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
@@ -18,4 +22,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig
index 904fcd1..5868912 100644
--- a/configs/TQM5200_STK100_defconfig
+++ b/configs/TQM5200_STK100_defconfig
@@ -1,9 +1,13 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100"
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
@@ -18,4 +22,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig
index e478f4c..9d0e915 100644
--- a/configs/TQM5200_defconfig
+++ b/configs/TQM5200_defconfig
@@ -1,8 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
@@ -17,4 +21,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig
index 38f5119..0c6b2d9 100644
--- a/configs/TQM823L_LCD_defconfig
+++ b/configs/TQM823L_LCD_defconfig
@@ -1,13 +1,17 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20"
+CONFIG_SYS_EXTRA_OPTIONS="NEC_NL6448BC20"
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig
index 3bc2934..7081ed6 100644
--- a/configs/TQM823L_defconfig
+++ b/configs/TQM823L_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig
index 9d40a1f..496dc06 100644
--- a/configs/TQM823M_defconfig
+++ b/configs/TQM823M_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823M=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index b56d780..8b24dfb 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TQM834X=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig
index 8427f58..0f711d1 100644
--- a/configs/TQM850L_defconfig
+++ b/configs/TQM850L_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM850L=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig
index 1c3f424..7a72ce9 100644
--- a/configs/TQM850M_defconfig
+++ b/configs/TQM850M_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM850M=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig
index 0234813..b034a04 100644
--- a/configs/TQM855L_defconfig
+++ b/configs/TQM855L_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM855L=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig
index 15541e5..05b4518 100644
--- a/configs/TQM855M_defconfig
+++ b/configs/TQM855M_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM855M=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig
index becd4e1..5d8a088 100644
--- a/configs/TQM860L_defconfig
+++ b/configs/TQM860L_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM860L=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig
index 3b27e7f..023751d 100644
--- a/configs/TQM860M_defconfig
+++ b/configs/TQM860M_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM860M=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig
index 36e2433..628d687 100644
--- a/configs/TQM862L_defconfig
+++ b/configs/TQM862L_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM862L=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig
index 84d2cb2..d1cf91c 100644
--- a/configs/TQM862M_defconfig
+++ b/configs/TQM862M_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM862M=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig
index ddde240..e0cf770 100644
--- a/configs/TQM866M_defconfig
+++ b/configs/TQM866M_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM866M=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,4 +10,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig
index 92b34f6..889de7b 100644
--- a/configs/TQM885D_defconfig
+++ b/configs/TQM885D_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM885D=y
CONFIG_OF_BOARD_SETUP=y
@@ -12,4 +13,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig
index e545848..97e4330 100644
--- a/configs/TTTech_defconfig
+++ b/configs/TTTech_defconfig
@@ -1,13 +1,17 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01"
+CONFIG_SYS_EXTRA_OPTIONS="SHARP_LQ104V7DS01"
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index d36a5dc..205c9e2 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig
deleted file mode 100644
index 123562c..0000000
--- a/configs/VCMA9_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_VCMA9=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="VCMA9 # "
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig
index 82446e0..aaaf31a 100644
--- a/configs/VOM405_defconfig
+++ b/configs/VOM405_defconfig
@@ -1,13 +1,16 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_VOM405=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index 5f3d624..ecde5db 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index bfc8cba..0735055 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_VGA=y
@@ -9,9 +10,10 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index 20382ae..907afe5 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PB3"
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 65c1d8e..1e42a68 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PH1"
diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig
index c620183..0cfdd98 100644
--- a/configs/a3m071_defconfig
+++ b/configs/a3m071_defconfig
@@ -1,10 +1,20 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_A3M071=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_OS_BASE=0xfc200000
CONFIG_HUSH_PARSER=y
CONFIG_LOOPW=y
# CONFIG_CMD_SETEXPR is not set
@@ -13,5 +23,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_LIB_RAND=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig
index 18dddd9..f68b966 100644
--- a/configs/a4m072_defconfig
+++ b/configs/a4m072_defconfig
@@ -1,7 +1,9 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_A4M072=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_SILENT_CONSOLE=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig
index 61f7da7..da7719c 100644
--- a/configs/a4m2k_defconfig
+++ b/configs/a4m2k_defconfig
@@ -1,11 +1,21 @@
CONFIG_PPC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_A3M071=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_OS_BASE=0xfc200000
CONFIG_HUSH_PARSER=y
CONFIG_LOOPW=y
# CONFIG_CMD_SETEXPR is not set
@@ -14,5 +24,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_LIB_RAND=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ac14xx_defconfig b/configs/ac14xx_defconfig
index 36fb7af..6c84fc6 100644
--- a/configs/ac14xx_defconfig
+++ b/configs/ac14xx_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_AC14XX=y
CONFIG_FIT=y
@@ -10,4 +11,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig
index e29431c..790d8a9 100644
--- a/configs/acadia_defconfig
+++ b/configs/acadia_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_ACADIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
@@ -13,6 +15,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 0def407..23ca68b 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -1,4 +1,5 @@
CONFIG_NDS32=y
+CONFIG_MMC=y
CONFIG_TARGET_ADP_AG101P=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="NDS32 # "
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 9b0f7bc..afef344 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -1,13 +1,29 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_AM335X_BALTOS=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -27,6 +43,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index b4e2a1c..79125ea 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -1,17 +1,21 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -23,15 +27,10 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 2c12402..e68bc98 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -1,20 +1,24 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -26,17 +30,14 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 65a9002..08c1e79 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -1,15 +1,19 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -21,18 +25,16 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 74577fa..91b50d2 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -1,14 +1,18 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_NOR=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MMC=y
@@ -19,14 +23,10 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 98da63f..0a4f8ff 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -1,11 +1,12 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_NOR=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_NOR_BOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MMC=y
@@ -16,14 +17,9 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index af4fac3..7f9cd2e 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -1,14 +1,19 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM335X_EVM=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_SPI_BOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MUSB_NEW_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -20,14 +25,9 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index f8f7c7e..5438c9e 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -1,13 +1,18 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -19,14 +24,10 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig
index efa3a9c..6149beb 100644
--- a/configs/am335x_igep0033_defconfig
+++ b/configs/am335x_igep0033_defconfig
@@ -1,9 +1,25 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_AM335X_IGEP0033=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index be9a99e..9b73f46 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -1,11 +1,26 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SERIES=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 8d6c8d9..ff70580 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -1,12 +1,27 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SHC_ICT=y
CONFIG_SERIES=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index 2e70a51..520d17c 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -1,12 +1,28 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SHC_NETBOOT=y
CONFIG_SERIES=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig
index 764fc9f..d6cc315 100644
--- a/configs/am335x_shc_prompt_defconfig
+++ b/configs/am335x_shc_prompt_defconfig
@@ -1,11 +1,26 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SERIES=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_AUTOBOOT_DELAY_STR="shc"
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index ba77c2d..b4e36b5 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -1,12 +1,27 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig
index ba77c2d..b4e36b5 100644
--- a/configs/am335x_shc_sdboot_prompt_defconfig
+++ b/configs/am335x_shc_sdboot_prompt_defconfig
@@ -1,12 +1,27 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index dae8f1b..99c09b9 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -1,14 +1,29 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_TARGET_AM335X_SL50=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
# CONFIG_AUTOBOOT is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -17,13 +32,6 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index 339c487..08902b8 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_GPIO_SUPPORT is not set
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_AM3517_CRANE=y
-CONFIG_SPL=y
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AM3517_CRANE # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index d5a0e30..291f570 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -1,11 +1,14 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_GPIO_SUPPORT is not set
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_AM3517_EVM=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AM3517_EVM # "
CONFIG_CMD_BOOTZ=y
@@ -27,6 +30,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index c465411..00f186a 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -2,13 +2,17 @@
CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -33,15 +37,22 @@
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 8676f32..7090fd1 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -1,9 +1,16 @@
CONFIG_ARM=y
CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT"
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_ETH_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -25,6 +32,9 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 26872c2..a3f3abd 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -4,6 +4,7 @@
CONFIG_ISW_ENTRY_ADDR=0x30000000
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
CONFIG_QSPI_BOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -26,6 +27,9 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index d8a23c5..6a881dd 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -3,13 +3,19 @@
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -34,8 +40,13 @@
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_SERIAL=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 9494860..60b2122 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -4,15 +4,18 @@
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x403018e0
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND"
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -36,14 +39,21 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index d49129d..a582055 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -1,15 +1,31 @@
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM57XX_EVM=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ARMV7_LPAE=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2f000000
+CONFIG_FASTBOOT_USB_DEV=1
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
@@ -19,26 +35,36 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am572x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk am571x-idk"
CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
@@ -46,5 +72,14 @@
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 0066691..7e08b0a 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -1,9 +1,24 @@
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM57XX_EVM=y
-CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2f000000
+CONFIG_FASTBOOT_USB_DEV=1
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
@@ -31,5 +46,14 @@
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 86f7373..4dcfce4 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -1,18 +1,35 @@
CONFIG_ARM=y
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_DEVICE=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM57XX_EVM=y
+CONFIG_TI_SECURE_EMIF_REGION_START=0xbe000000
+CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
+CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2f000000
+CONFIG_FASTBOOT_USB_DEV=1
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
@@ -22,6 +39,7 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@@ -34,9 +52,13 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
@@ -48,5 +70,14 @@
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index 0361418..5b271b9 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -1,7 +1,10 @@
CONFIG_M68K=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_AMCORE=y
CONFIG_SYS_TEXT_BASE=0xffc00000
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="amcore $ "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
@@ -12,3 +15,5 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
index cb42e1c..d21fa04 100644
--- a/configs/ap121_defconfig
+++ b/configs/ap121_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_ATH79=y
CONFIG_DEFAULT_DEVICE_TREE="ap121"
CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_PROMPT="ap121 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
index 27b5c17..5bb9350 100644
--- a/configs/ap143_defconfig
+++ b/configs/ap143_defconfig
@@ -4,6 +4,7 @@
CONFIG_TARGET_AP143=y
CONFIG_DEFAULT_DEVICE_TREE="ap143"
CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
CONFIG_SYS_PROMPT="ap143 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
new file mode 100644
index 0000000..59a7140
--- /dev/null
+++ b/configs/apalis_imx6_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_APALIS_IMX6=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Apalis iMX6 # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Toradex"
+CONFIG_G_DNL_VENDOR_NUM=0x1b67
+CONFIG_G_DNL_PRODUCT_NUM=0x4020
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig
new file mode 100644
index 0000000..4276c6a
--- /dev/null
+++ b/configs/apalis_imx6_nospl_com_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_APALIS_IMX6=y
+CONFIG_VIDEO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Apalis iMX6 # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Toradex"
+CONFIG_G_DNL_VENDOR_NUM=0x1b67
+CONFIG_G_DNL_PRODUCT_NUM=0x4020
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig
new file mode 100644
index 0000000..2db4421
--- /dev/null
+++ b/configs/apalis_imx6_nospl_it_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_APALIS_IMX6=y
+CONFIG_VIDEO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048"
+CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Apalis iMX6 # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Toradex"
+CONFIG_G_DNL_VENDOR_NUM=0x1b67
+CONFIG_G_DNL_PRODUCT_NUM=0x4020
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 882d409..691148c 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -4,9 +4,10 @@
CONFIG_TARGET_APALIS_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="Apalis T30 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -17,17 +18,17 @@
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 3f24da9..a02e180 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_APF27=y
-CONFIG_SPL=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_IDENT_STRING=" apf27 patch 3.10"
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="BIOS> "
# CONFIG_CMD_IMLS is not set
@@ -17,4 +20,5 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig
index 01d8190..9245ebb 100644
--- a/configs/apx4devkit_defconfig
+++ b/configs/apx4devkit_defconfig
@@ -1,8 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_APX4DEVKIT=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -16,6 +21,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/arches_defconfig b/configs/arches_defconfig
index e367cd9..88bf4df 100644
--- a/configs/arches_defconfig
+++ b/configs/arches_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_ARCHES=y
CONFIG_DEFAULT_DEVICE_TREE="arches"
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/aria_defconfig b/configs/aria_defconfig
index 14919e5..d54708e 100644
--- a/configs/aria_defconfig
+++ b/configs/aria_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_ARIA=y
CONFIG_OF_BOARD_SETUP=y
@@ -10,4 +11,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 84e3bf6..8cdd703 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -1,9 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ARISTAINETOS2=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -22,8 +26,12 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index 21765aa..05e44aa 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -1,9 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ARISTAINETOS2B=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -22,8 +26,12 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index 1e6954e..175054c 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -1,9 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ARISTAINETOS=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -22,8 +26,12 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index 7d0a592..9409b8a 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_TARGET_ARMADILLO_800EVA=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 22e2cb6..cdfb739 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -2,32 +2,28 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_ARNDALE=y
+CONFIG_IDENT_STRING=" for ARNDALE"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
CONFIG_SYS_PROMPT="ARNDALE # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig
index 9ac6657..b4260a1 100644
--- a/configs/aspenite_defconfig
+++ b/configs/aspenite_defconfig
@@ -1,6 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_ASPENITE=y
+CONFIG_IDENT_STRING="\nMarvell-Aspenite DB"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index 1e41628..94e931e 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_TARGET_ASTRO_MCF5373L=y
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="URMEL > "
CONFIG_CMD_I2C=y
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index e4f7196..9674a04 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_SYS_STDIO_DEREGISTER is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -14,4 +18,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index c04cd73..39c1afe 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
CONFIG_BOOTDELAY=3
+# CONFIG_SYS_STDIO_DEREGISTER is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -15,4 +19,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 352cdb1..36423b2 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index e6dd305..3b28172 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index 9b93fa8..4f88507 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 51b3ec1..6b26c78 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
@@ -17,4 +21,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index f5ffbcd..293009d 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
@@ -17,4 +21,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index c985d3a..4760c4e 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
@@ -17,4 +21,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index 09a1404..6605a0e 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -20,4 +23,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index 09a1404..6605a0e 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -20,4 +23,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index 3a18c3b..9c6bab9 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -20,4 +23,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index e4608d2..59c4f9b 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -20,4 +23,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index 4c97c9f..b588871 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -20,4 +23,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 1ee26d9..02cd5fa 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
@@ -17,4 +21,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index de6cacd..453a75d 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
@@ -17,4 +21,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index 257593d..0c82978 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
@@ -17,4 +21,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index 182c704..67c8232 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -3,6 +3,7 @@
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index a15351d..6d2bfa1 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -3,6 +3,7 @@
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index d4538e3..4d94b84 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 4fb0bad..cbe0376 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index c563165..1b53332 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index aaa27f1..7a18ef8 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -1,9 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9M10G45EK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -21,4 +31,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 4924ac5..819fe10 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -1,9 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9M10G45EK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -21,4 +29,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 3eb8666..ef9250b 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -20,4 +23,5 @@
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index af86350..da0ea60 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -1,9 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9N12EK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -21,4 +29,5 @@
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index 1ddfbf5..4e5d102 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -1,9 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9N12EK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -21,4 +30,5 @@
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index 69be1d2..49e1353 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -17,4 +20,5 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_FAT=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index c49bf18..483d9b6 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -17,4 +20,5 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_FAT=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 142122e..d7f2d7f 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -17,4 +20,5 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_FAT=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index 6771f57..e07e217 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -17,8 +20,10 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 7995c23..9a95a04 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -17,8 +20,10 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 7a72bcf..05907b7 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -1,9 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9X5EK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -18,8 +26,10 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index b869db0..5fc512b 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -1,9 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9X5EK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -18,8 +27,10 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index ca3500b..4092bfa 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index 3e98c71..5ff6902 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index b8ad4c1..fea620c 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig
index 52dbefd..be48af1 100644
--- a/configs/atngw100_defconfig
+++ b/configs/atngw100_defconfig
@@ -1,4 +1,5 @@
CONFIG_AVR32=y
+CONFIG_MMC=y
CONFIG_TARGET_ATNGW100=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig
index bfceedb..9c1ee73 100644
--- a/configs/atngw100mkii_defconfig
+++ b/configs/atngw100mkii_defconfig
@@ -1,4 +1,5 @@
CONFIG_AVR32=y
+CONFIG_MMC=y
CONFIG_TARGET_ATNGW100MKII=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig
index df57568..1a5c97d 100644
--- a/configs/atstk1002_defconfig
+++ b/configs/atstk1002_defconfig
@@ -1,4 +1,5 @@
CONFIG_AVR32=y
+CONFIG_MMC=y
CONFIG_TARGET_ATSTK1002=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 220a49b..db988c8 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -1,10 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_TAURUS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index b8d8baf..04f5ffe 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARC=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_CLK_FREQ=750000000
+CONFIG_MMC=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEFAULT_DEVICE_TREE="axs10x"
CONFIG_BOOTDELAY=3
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 5e44633..54fad6d 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARC=y
CONFIG_ISA_ARCV2=y
CONFIG_SYS_CLK_FREQ=100000000
+CONFIG_MMC=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEFAULT_DEVICE_TREE="axs10x"
CONFIG_BOOTDELAY=3
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 1cfb380..c60766c 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_EMR1=4
@@ -8,8 +9,8 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig
index ea69457..54b8380 100644
--- a/configs/bamboo_defconfig
+++ b/configs/bamboo_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_BAMBOO=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
@@ -17,6 +19,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 64e3d31..63d17b1 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -1,4 +1,5 @@
CONFIG_X86=y
+CONFIG_MMC=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
CONFIG_TARGET_BAYLEYBAY=y
@@ -15,6 +16,7 @@
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -39,6 +41,8 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -53,7 +57,10 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index 57cfbd2..bf2f1f7 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -2,6 +2,8 @@
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
@@ -16,6 +18,9 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_KONA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index 586abc0..7df4a52 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -2,6 +2,8 @@
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
@@ -16,6 +18,9 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_KONA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig
index 579a2ba..4c7709c 100644
--- a/configs/bcm23550_w1d_defconfig
+++ b/configs/bcm23550_w1d_defconfig
@@ -2,6 +2,8 @@
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM23550_W1D=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_FASTBOOT=y
CONFIG_USB_FUNCTION_FASTBOOT=y
@@ -22,6 +24,9 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_KONA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index 768bd02..3325a4d 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -2,6 +2,8 @@
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_FASTBOOT=y
@@ -23,6 +25,9 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_KONA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 8a5111f..b161d38 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -3,6 +3,8 @@
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
@@ -17,6 +19,9 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_KONA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
index 97ccec6..adcc152 100644
--- a/configs/bcm911360_entphn-ns_defconfig
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
index bfe358b..e49071d 100644
--- a/configs/bcm911360_entphn_defconfig
+++ b/configs/bcm911360_entphn_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
index ccdbd31..8077c4a 100644
--- a/configs/bcm911360k_defconfig
+++ b/configs/bcm911360k_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
index ff5ee54..26d0b0b 100644
--- a/configs/bcm958300k-ns_defconfig
+++ b/configs/bcm958300k-ns_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index ccdbd31..8077c4a 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
index ccdbd31..8077c4a 100644
--- a/configs/bcm958305k_defconfig
+++ b/configs/bcm958305k_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig
index 4a93a2d..c8679ac 100644
--- a/configs/bcm958622hr_defconfig
+++ b/configs/bcm958622hr_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_BCMNSP=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig
index ad894a2..5dae665 100644
--- a/configs/bct-brettl2_defconfig
+++ b/configs/bct-brettl2_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BCT_BRETTL2=y
CONFIG_BOOTDELAY=1
+CONFIG_SILENT_CONSOLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 28c1b28..5cb73c0 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -4,9 +4,9 @@
CONFIG_TARGET_BEAVER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -20,19 +20,20 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
diff --git a/configs/bf518f-ezbrd_defconfig b/configs/bf518f-ezbrd_defconfig
index e17c969..d5b6e6e 100644
--- a/configs/bf518f-ezbrd_defconfig
+++ b/configs/bf518f-ezbrd_defconfig
@@ -1,6 +1,8 @@
CONFIG_BLACKFIN=y
+CONFIG_MMC=y
CONFIG_TARGET_BF518F_EZBRD=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
index d3cab9b..663a6a3 100644
--- a/configs/bf526-ezbrd_defconfig
+++ b/configs/bf526-ezbrd_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF526_EZBRD=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
diff --git a/configs/bf527-ad7160-eval_defconfig b/configs/bf527-ad7160-eval_defconfig
index 45f4149..d26bd27 100644
--- a/configs/bf527-ad7160-eval_defconfig
+++ b/configs/bf527-ad7160-eval_defconfig
@@ -1,6 +1,8 @@
CONFIG_BLACKFIN=y
+CONFIG_MMC=y
CONFIG_TARGET_BF527_AD7160_EVAL=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
index 3677e0a..d247280 100644
--- a/configs/bf527-ezkit-v2_defconfig
+++ b/configs/bf527-ezkit-v2_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_BF527_EZKIT=y
CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1"
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
index da41fe6..f011277 100644
--- a/configs/bf527-ezkit_defconfig
+++ b/configs/bf527-ezkit_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_EZKIT=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
diff --git a/configs/bf527-sdp_defconfig b/configs/bf527-sdp_defconfig
index fec1307..0c5c4fd 100644
--- a/configs/bf527-sdp_defconfig
+++ b/configs/bf527-sdp_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_SDP=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig
index 853a5d4..53cd831 100644
--- a/configs/bf533-ezkit_defconfig
+++ b/configs/bf533-ezkit_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF533_EZKIT=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig
index e0f5de9..f31b54b 100644
--- a/configs/bf533-stamp_defconfig
+++ b/configs/bf533-stamp_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF533_STAMP=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
diff --git a/configs/bf537-pnav_defconfig b/configs/bf537-pnav_defconfig
index bbc171d..4fd2936 100644
--- a/configs/bf537-pnav_defconfig
+++ b/configs/bf537-pnav_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF537_PNAV=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig
index d189ad4..d06ed7e 100644
--- a/configs/bf537-stamp_defconfig
+++ b/configs/bf537-stamp_defconfig
@@ -1,6 +1,8 @@
CONFIG_BLACKFIN=y
+CONFIG_MMC=y
CONFIG_TARGET_BF537_STAMP=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig
index 8507b40..4e835cc 100644
--- a/configs/bf538f-ezkit_defconfig
+++ b/configs/bf538f-ezkit_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF538F_EZKIT=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
index 8514d85..166b21a 100644
--- a/configs/bf548-ezkit_defconfig
+++ b/configs/bf548-ezkit_defconfig
@@ -1,6 +1,8 @@
CONFIG_BLACKFIN=y
+CONFIG_MMC=y
CONFIG_TARGET_BF548_EZKIT=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig
index 6428d18..744eb1c 100644
--- a/configs/bf561-acvilon_defconfig
+++ b/configs/bf561-acvilon_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF561_ACVILON=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_PROMPT="Acvilon> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig
index f8206b8..abb612c 100644
--- a/configs/bf561-ezkit_defconfig
+++ b/configs/bf561-ezkit_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF561_EZKIT=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig
index 68788a6..8fc0bf9 100644
--- a/configs/bf609-ezkit_defconfig
+++ b/configs/bf609-ezkit_defconfig
@@ -1,5 +1,7 @@
CONFIG_BLACKFIN=y
+CONFIG_MMC=y
CONFIG_TARGET_BF609_EZKIT=y
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index ae54562..319c3e2 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -1,8 +1,14 @@
CONFIG_ARM=y
CONFIG_TARGET_BG0900=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index c721ad5..5e1af1c 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -1,10 +1,26 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_BAV335X=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_BAV_VERSION=1
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -27,6 +43,8 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index 4400bb1..f3771bb 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -1,10 +1,26 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_BAV335X=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_BAV_VERSION=2
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -27,6 +43,8 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
new file mode 100644
index 0000000..39a47ea
--- /dev/null
+++ b/configs/bk4r1_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BK4R1=y
+CONFIG_DEFAULT_DEVICE_TREE="bk4r1"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_VYBRID_GPIO=y
+CONFIG_NAND_VF610_NFC=y
+CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index fa6735d..8dcbdd2 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_BLANCHE=y
+# CONFIG_MMC is not set
CONFIG_BOOTSTAGE_USER_COUNT=0x20
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig
new file mode 100644
index 0000000..6df5429
--- /dev/null
+++ b/configs/boston32r2_defconfig
@@ -0,0 +1,41 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_BOSTON=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="boston # "
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PCH_GBE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_XILINX=y
+CONFIG_SYS_NS16550=y
+CONFIG_LZ4=y
diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig
new file mode 100644
index 0000000..8f8cb5f
--- /dev/null
+++ b/configs/boston32r2el_defconfig
@@ -0,0 +1,42 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_BOSTON=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="boston # "
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PCH_GBE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_XILINX=y
+CONFIG_SYS_NS16550=y
+CONFIG_LZ4=y
diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig
new file mode 100644
index 0000000..3c70f95
--- /dev/null
+++ b/configs/boston64r2_defconfig
@@ -0,0 +1,42 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_BOSTON=y
+CONFIG_CPU_MIPS64_R2=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="boston # "
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PCH_GBE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_XILINX=y
+CONFIG_SYS_NS16550=y
+CONFIG_LZ4=y
diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig
new file mode 100644
index 0000000..b2f53dd
--- /dev/null
+++ b/configs/boston64r2el_defconfig
@@ -0,0 +1,43 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_BOSTON=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS64_R2=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="img,boston"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="boston # "
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PCH_GBE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_XILINX=y
+CONFIG_SYS_NS16550=y
+CONFIG_LZ4=y
diff --git a/configs/br4_defconfig b/configs/br4_defconfig
index db5d915..90ce839 100644
--- a/configs/br4_defconfig
+++ b/configs/br4_defconfig
@@ -1,5 +1,6 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_BR4=y
+CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_PROMPT="br4>"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 881930e..41eac18 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -1,10 +1,27 @@
CONFIG_ARM=y
CONFIG_TARGET_BRPPT1=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
CONFIG_BOOTDELAY=-2
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -35,4 +52,5 @@
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index 9c7c07e..31cd180 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -1,10 +1,28 @@
CONFIG_ARM=y
CONFIG_TARGET_BRPPT1=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+# CONFIG_MMC is not set
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
CONFIG_BOOTDELAY=-2
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -35,4 +53,5 @@
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index fc1f1e6..17b9cb1 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -1,11 +1,30 @@
CONFIG_ARM=y
CONFIG_TARGET_BRPPT1=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=-2
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -41,4 +60,5 @@
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index 3895eec..7c0cf96 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -1,9 +1,25 @@
CONFIG_ARM=y
CONFIG_TARGET_BRXRE1=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_BOOTDELAY=-2
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
@@ -35,5 +51,6 @@
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig
index d18e89e..8a72e44 100644
--- a/configs/bubinga_defconfig
+++ b/configs/bubinga_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_BUBINGA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index c2e454a..78dc4e1 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_VME8349=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index 7d8fe11..67d6b61 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -1,9 +1,12 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_CAIRO=y
-CONFIG_SPL=y
CONFIG_BOOTDELAY=-2
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Cairo # "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig
index 9cc4a85..33a221a 100644
--- a/configs/calimain_defconfig
+++ b/configs/calimain_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_CALIMAIN=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Calimain > "
CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig
index f2da039..3bf1aa7 100644
--- a/configs/cam5200_defconfig
+++ b/configs/cam5200_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
@@ -13,4 +14,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig
index d04ac55..602988e 100644
--- a/configs/cam5200_niosflash_defconfig
+++ b/configs/cam5200_niosflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
@@ -13,4 +14,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig
index f1e3265..f4cf5c3 100644
--- a/configs/canmb_defconfig
+++ b/configs/canmb_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_CANMB=y
CONFIG_BOOTDELAY=5
@@ -7,3 +8,4 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_SNTP=y
+# CONFIG_PCI is not set
diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig
index efe87f3..fb1f9ec 100644
--- a/configs/canyonlands_defconfig
+++ b/configs/canyonlands_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_CANYONLANDS=y
CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 2d361c3..0214758 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -4,9 +4,9 @@
CONFIG_TARGET_CARDHU=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -18,19 +18,17 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index ea515f2..909b367 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -4,9 +4,9 @@
CONFIG_TARGET_CEI_TK1_SOM=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra124 (TK1-SOM) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -20,19 +20,20 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 20c0af0..1392f7e 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -1,9 +1,25 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_CGTQMX6EVAL=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
CONFIG_CMD_BOOTZ=y
@@ -26,12 +42,16 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SF=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Congatec"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/charon_defconfig b/configs/charon_defconfig
index 724441e..67d22b6 100644
--- a/configs/charon_defconfig
+++ b/configs/charon_defconfig
@@ -1,8 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_CHARON=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
@@ -17,4 +21,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
new file mode 100644
index 0000000..9203f73
--- /dev/null
+++ b/configs/chromebit_mickey_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_CHROMEBIT_MICKEY=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_RK808=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
+# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 8688abb..95e5f57 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -1,12 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TARGET_CHROMEBOOK_JERRY=y
-CONFIG_ROCKCHIP_FAST_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x80000
-CONFIG_DM_KEYBOARD=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
@@ -30,7 +33,8 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
@@ -42,8 +46,8 @@
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
+CONFIG_DM_KEYBOARD=y
CONFIG_CROS_EC_KEYB=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
@@ -55,10 +59,8 @@
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK808=y
-CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK808=y
-CONFIG_DM_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
@@ -67,11 +69,14 @@
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
+CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 8c91bfe..8407731 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -10,6 +10,7 @@
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -37,7 +38,6 @@
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SPI_FLASH=y
@@ -57,8 +57,12 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_VIDEO_IVYBRIDGE_IGD=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
new file mode 100644
index 0000000..49cd640
--- /dev/null
+++ b/configs/chromebook_minnie_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_CHROMEBOOK_MINNIE=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_RK808=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
+# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 1822970..e08dffc 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -10,6 +10,7 @@
CONFIG_HAVE_VGA_BIOS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -36,7 +37,6 @@
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_INTEL_BROADWELL_GPIO=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SPI_FLASH=y
@@ -56,9 +56,11 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_DM_VIDEO=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_VIDEO_BROADWELL_IGD=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 2557d35..f8cf92b 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -8,6 +8,7 @@
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -31,7 +32,6 @@
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SPI_FLASH=y
@@ -49,8 +49,11 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig
new file mode 100644
index 0000000..9eadf42
--- /dev/null
+++ b/configs/cl-som-am57x_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_TARGET_CL_SOM_AM57X=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 778cf06..4587807 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -1,9 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CLEARFOG=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -25,7 +35,11 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
diff --git a/configs/cm-bf527_defconfig b/configs/cm-bf527_defconfig
index 773edfb..bc280a4 100644
--- a/configs/cm-bf527_defconfig
+++ b/configs/cm-bf527_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF527=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig
index 6fa231d..5bc851a 100644
--- a/configs/cm-bf533_defconfig
+++ b/configs/cm-bf533_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF533=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/cm-bf537e_defconfig b/configs/cm-bf537e_defconfig
index 16f129b..d687c43 100644
--- a/configs/cm-bf537e_defconfig
+++ b/configs/cm-bf537e_defconfig
@@ -1,6 +1,8 @@
CONFIG_BLACKFIN=y
+CONFIG_MMC=y
CONFIG_TARGET_CM_BF537E=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
diff --git a/configs/cm-bf537u_defconfig b/configs/cm-bf537u_defconfig
index 68e8659..38c6d42 100644
--- a/configs/cm-bf537u_defconfig
+++ b/configs/cm-bf537u_defconfig
@@ -1,6 +1,8 @@
CONFIG_BLACKFIN=y
+CONFIG_MMC=y
CONFIG_TARGET_CM_BF537U=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig
index 0589803..bcf6d8f 100644
--- a/configs/cm-bf548_defconfig
+++ b/configs/cm-bf548_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF548=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/cm-bf561_defconfig b/configs/cm-bf561_defconfig
index 5a32f56..3acbc53 100644
--- a/configs/cm-bf561_defconfig
+++ b/configs/cm-bf561_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF561=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig
index 8b98484..b09f31f 100644
--- a/configs/cm5200_defconfig
+++ b/configs/cm5200_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_CM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
@@ -13,6 +15,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index f01a6dd..dc7544a 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -1,10 +1,21 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_CM_FX6=y
-CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-FX6 # "
CONFIG_CMD_BOOTZ=y
@@ -44,3 +55,4 @@
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 1528d1b..36905fd 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -1,7 +1,22 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_CM_T335=y
-CONFIG_SPL=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T335 # "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index dfc2539..aba8b85 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -2,6 +2,8 @@
CONFIG_OMAP34XX=y
CONFIG_TARGET_CM_T3517=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T3517 # "
CONFIG_CMD_BOOTZ=y
@@ -22,4 +24,5 @@
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index 82738b2..56b78c1 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_CM_T35=y
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T3x # "
CONFIG_CMD_BOOTZ=y
@@ -22,4 +25,5 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index a2ffcb2..2d78841 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -1,7 +1,24 @@
CONFIG_ARM=y
CONFIG_TARGET_CM_T43=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
+CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T43 # "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index 18bb04e..e002e1c 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -1,10 +1,14 @@
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_CM_T54=y
-CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_SPL_SATA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T54 # "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index 400fca0..bd20de8 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_COBRA5272=y
CONFIG_SYS_TEXT_BASE=0xffe00000
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="COBRA > "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
new file mode 100644
index 0000000..f14f701
--- /dev/null
+++ b/configs/colibri_imx6_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_COLIBRI_IMX6=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
+CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Colibri iMX6 # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Toradex"
+CONFIG_G_DNL_VENDOR_NUM=0x1b67
+CONFIG_G_DNL_PRODUCT_NUM=0x4020
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig
new file mode 100644
index 0000000..72e127f
--- /dev/null
+++ b/configs/colibri_imx6_nospl_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_COLIBRI_IMX6=y
+CONFIG_VIDEO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256"
+CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Colibri iMX6 # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Toradex"
+CONFIG_G_DNL_VENDOR_NUM=0x1b67
+CONFIG_G_DNL_PRODUCT_NUM=0x4020
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 5302fe3..341c99d 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -3,8 +3,13 @@
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
# CONFIG_CMD_BOOTD is not set
@@ -29,6 +34,17 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RN5T567=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
@@ -38,4 +54,3 @@
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4020
-CONFIG_OF_LIBFDT=y
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index e7b7bff..e0a36f1 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -1,18 +1,26 @@
CONFIG_ARM=y
CONFIG_TARGET_COLIBRI_PXA270=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="$ "
+# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_PXA_SERIAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_REGEX is not set
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index fb5055b..a543246 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -4,9 +4,9 @@
CONFIG_TARGET_COLIBRI_T20=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SYS_STDIO_DEREGISTER=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="Colibri T20 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -17,19 +17,18 @@
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -48,3 +47,4 @@
CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index bd0250a..2ab6764 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -4,9 +4,10 @@
CONFIG_TARGET_COLIBRI_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="Colibri T30 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -17,16 +18,13 @@
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index a045a3f..54d3581 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -4,6 +4,7 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri VFxx # "
CONFIG_CMD_BOOTZ=y
@@ -23,17 +24,22 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index f0da176..812f516 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -1,4 +1,5 @@
CONFIG_X86=y
+CONFIG_MMC=y
CONFIG_VENDOR_CONGATEC=y
CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
@@ -15,6 +16,7 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -43,6 +45,8 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_WINBOND_W83627=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -61,7 +65,10 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 63c2cbd..cff6cc2 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -1,4 +1,5 @@
CONFIG_X86=y
+CONFIG_MMC=y
CONFIG_VENDOR_CONGATEC=y
CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
@@ -14,6 +15,7 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -42,6 +44,8 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_WINBOND_W83627=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -60,7 +64,10 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index c0a2c77..4b4a905 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -1,4 +1,6 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" controlcenterd 0.01"
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_PHYS_64BIT=y
@@ -8,6 +10,9 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,DEVELOP"
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -28,5 +33,6 @@
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_TPM=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index 73cd33d..cc9f40c 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -1,4 +1,6 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" controlcenterd 0.01"
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_PHYS_64BIT=y
@@ -8,6 +10,9 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -28,5 +33,6 @@
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_TPM=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
index efb8ad6..d71e6af 100644
--- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
@@ -1,8 +1,11 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01"
CONFIG_MPC85xx=y
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
CONFIG_BOOTDELAY=-2
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -10,6 +13,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TPM=y
CONFIG_DM=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig
index 45e8b8f..5c7f2c9 100644
--- a/configs/controlcenterd_TRAILBLAZER_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_defconfig
@@ -1,8 +1,11 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01"
CONFIG_MPC85xx=y
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
CONFIG_BOOTDELAY=-2
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -10,6 +13,7 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TPM=y
CONFIG_DM=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 378d75f..2195fc6 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -4,6 +4,7 @@
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -40,5 +41,9 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_COREBOOT=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 975ac4f..e33d371 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -1,10 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CORVUS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -22,6 +29,7 @@
CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DFU_NAND=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index a55e4a3..233fe09 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -2,6 +2,8 @@
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
CONFIG_TARGET_COUGARCANYON2=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -32,4 +34,5 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index d0cd9db..784c1b3 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -1,13 +1,15 @@
CONFIG_X86=y
+CONFIG_MAX_CPUS=2
+CONFIG_MMC=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
CONFIG_TARGET_CROWNBAY=y
CONFIG_SMP=y
-CONFIG_MAX_CPUS=2
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -31,6 +33,8 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -47,6 +51,9 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index ae9175f..87686aa 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NET2BIG_V2=y
+CONFIG_IDENT_STRING=" D2 v2"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="d2v2> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index ce49340..25fcff1 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -1,10 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index da6615f..e2512ff 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -1,10 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index 1ab9ff3..8120b9d 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -1,9 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_ASKENV=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 9c7d3c9..0db2d1d 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -4,9 +4,9 @@
CONFIG_TARGET_DALMORE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -20,16 +20,14 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index b6df961..20539d1 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -1,10 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_88F6720=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
new file mode 100644
index 0000000..5543be8
--- /dev/null
+++ b/configs/db-88f6820-amc_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_DB_88F6820_AMC=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 7ac7457..bcc3128 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -1,9 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_88F6820_GP=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
@@ -23,9 +32,13 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 510554e..ffd9c50 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -1,10 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_MV784MP_GP=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
@@ -27,6 +37,7 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig
index 8468d8d..6ce8786 100644
--- a/configs/devconcenter_defconfig
+++ b/configs/devconcenter_defconfig
@@ -1,11 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" devconcenter 0.06"
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_INTIP=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index 5e4aefb..2bbea13 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -1,9 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_DEVKIT3250=y
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index 29a246c..e603310 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_DEVKIT8000=y
-CONFIG_SPL=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
index 245d0c7..b7eb006 100644
--- a/configs/dfi-bt700-q7x-151_defconfig
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -1,4 +1,5 @@
CONFIG_X86=y
+CONFIG_MMC=y
CONFIG_VENDOR_DFI=y
CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151"
CONFIG_TARGET_DFI_BT700=y
@@ -14,6 +15,7 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -40,6 +42,8 @@
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_NUVOTON_NCT6102D=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -58,7 +62,10 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index c76af0e..6149c94 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PG0"
@@ -14,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig
index d0743c8..d4b9628 100644
--- a/configs/digsy_mtc_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_RAMBOOT_defconfig
@@ -1,16 +1,19 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_LOOPW=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig
index e2156a1..f8be655 100644
--- a/configs/digsy_mtc_defconfig
+++ b/configs/digsy_mtc_defconfig
@@ -1,14 +1,17 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR=" "
CONFIG_LOOPW=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
index 3b7a7c1..46a4d10 100644
--- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
@@ -1,16 +1,19 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_LOOPW=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig
index 75888ff..6bb8e08 100644
--- a/configs/digsy_mtc_rev5_defconfig
+++ b/configs/digsy_mtc_rev5_defconfig
@@ -1,16 +1,19 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_LOOPW=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig
index 4253b55..2a5af4b 100644
--- a/configs/dlvision-10g_defconfig
+++ b/configs/dlvision-10g_defconfig
@@ -1,11 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" dlvision-10g 0.06"
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_DLVISION_10G=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
@@ -17,5 +21,6 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig
index 8fd5add..f8e96ac 100644
--- a/configs/dlvision_defconfig
+++ b/configs/dlvision_defconfig
@@ -1,11 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" dlvision 0.02"
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_DLVISION=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
@@ -14,5 +18,6 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
index a579af4..9dcb6ad 100644
--- a/configs/dms-ba16-1g_defconfig
+++ b/configs/dms-ba16-1g_defconfig
@@ -2,8 +2,14 @@
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ADVANTECH_DMS_BA16=y
CONFIG_SYS_DDR_1G=y
-CONFIG_HUSH_PARSER=y
+CONFIG_VIDEO=y
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
+CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb"
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -24,11 +30,13 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_OF_LIBFDT=y
CONFIG_USB=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Advantech"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
index 365d05c..664f039 100644
--- a/configs/dms-ba16_defconfig
+++ b/configs/dms-ba16_defconfig
@@ -1,8 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ADVANTECH_DMS_BA16=y
-CONFIG_HUSH_PARSER=y
+CONFIG_VIDEO=y
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
+CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb"
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -23,11 +29,13 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_OF_LIBFDT=y
CONFIG_USB=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Advantech"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index 905f6ff..3a31a66 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DNS325=y
+CONFIG_IDENT_STRING="\nD-Link DNS-325"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -12,6 +16,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 73740dd..2b13f00 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DOCKSTAR=y
+CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="DockStar> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -12,6 +15,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 64184de..64fe038 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -1,15 +1,30 @@
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ARMV7_LPAE=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2f000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
@@ -25,6 +40,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
@@ -32,19 +48,30 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="dra7-evm dra72-evm"
+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_ETH=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_PMIC_LP873X=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_DM_REGULATOR_LP873X=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 3dad0fa..b890a06 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -2,18 +2,34 @@
CONFIG_OMAP54XX=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TI_SECURE_DEVICE=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_TI_SECURE_EMIF_REGION_START=0xbe000000
+CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
+CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2f000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
@@ -29,6 +45,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
@@ -36,18 +53,30 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="dra7-evm dra72-evm"
+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_ETH=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_PMIC_LP873X=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_DM_REGULATOR_LP873X=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 37f4664..0cb4412 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -1,9 +1,26 @@
CONFIG_ARM=y
CONFIG_TARGET_DRACO=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -25,10 +42,14 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DFU_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 656cc81..b40b5ef 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
-CONFIG_HUSH_PARSER=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="dragonboard410c => "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
@@ -9,24 +12,16 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_MSM_GPIO=y
CONFIG_PM8916_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=y
CONFIG_MSM_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PM8916=y
CONFIG_MSM_SERIAL=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index 830b68b..cb15755 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DREAMPLUG=y
+CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig
new file mode 100644
index 0000000..94d3c74
--- /dev/null
+++ b/configs/ds109_defconfig
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_TARGET_DS109=y
+# CONFIG_MMC is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index f95a9df..502d6f8 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -1,9 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DS414=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
@@ -18,10 +27,12 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index f8155b2..ebcfe58 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index be65d6e..33e70ee 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -1,11 +1,14 @@
CONFIG_ARM=y
CONFIG_OMAP44XX=y
+# CONFIG_SPL_I2C_SUPPORT is not set
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_DUOVERO=y
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SPL=y
CONFIG_SYS_PROMPT="duovero # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -15,15 +18,8 @@
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index ca6705a..c5563a4 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -3,7 +3,8 @@
CONFIG_TEGRA210=y
CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (E2220-1170) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
@@ -18,15 +19,13 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig
index 5e31c1b..bb6d3f1 100644
--- a/configs/ea20_defconfig
+++ b/configs/ea20_defconfig
@@ -1,8 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_EA20=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ea20 > "
# CONFIG_CMD_IMLS is not set
@@ -16,6 +24,8 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index bf9177b..03d8e43 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -1,11 +1,15 @@
CONFIG_M68K=y
+CONFIG_VIDEO=y
CONFIG_TARGET_EB_CPU5282=y
CONFIG_SYS_TEXT_BASE=0xFF000000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="\nEB+CPU5282> "
# CONFIG_CMD_LOADB is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
+# CONFIG_CFB_CONSOLE is not set
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 4f6de89..04d094a 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -1,10 +1,14 @@
CONFIG_M68K=y
+CONFIG_VIDEO=y
CONFIG_TARGET_EB_CPU5282=y
CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_LOADB is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
+# CONFIG_CFB_CONSOLE is not set
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index 85f857c..77f3cd5 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -1,9 +1,10 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_ECO5PK=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ECO5-PK # "
# CONFIG_CMD_IMLS is not set
@@ -18,6 +19,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig
index 49f870a..9e8c6bb 100644
--- a/configs/edb9315a_defconfig
+++ b/configs/edb9315a_defconfig
@@ -1,6 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_EDB93XX=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="EDB9315A> "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index c9c7bc1..df054d6 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -1,8 +1,15 @@
CONFIG_ARM=y
CONFIG_ORION5X=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_EDMINIV2=y
-CONFIG_SPL=y
+CONFIG_IDENT_STRING=" EDMiniV2"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="EDMiniV2> "
CONFIG_CMD_I2C=y
diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index eb55e93..1fe6142 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -3,6 +3,8 @@
CONFIG_DEFAULT_DEVICE_TREE="efi"
CONFIG_TARGET_EFI=y
CONFIG_FIT=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_IMLS is not set
@@ -30,4 +32,6 @@
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_EFI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig
index c50da0c..39837e9 100644
--- a/configs/espresso7420_defconfig
+++ b/configs/espresso7420_defconfig
@@ -2,7 +2,12 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS7=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_IDENT_STRING=" for ESPRESSO7420"
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="ESPRESSO7420 # "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_IMLS is not set
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index 7c2b6f8..8fb6ebd 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -1,9 +1,26 @@
CONFIG_ARM=y
CONFIG_TARGET_ETAMIN=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -25,10 +42,14 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DFU_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 58f0f7c..c831aab 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -3,6 +3,7 @@
CONFIG_TARGET_ETHERNUT5=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -24,6 +25,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index b49c562..6546db9 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -4,6 +4,7 @@
CONFIG_TARGET_EVB_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index c7396a5..e5e550c 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -2,9 +2,13 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
CONFIG_TARGET_EVB_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
@@ -47,10 +51,8 @@
CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
-CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_ACT8846=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index fbc23ef..6c27104 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -3,11 +3,13 @@
CONFIG_ROCKCHIP_RK3399=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@@ -17,9 +19,15 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_ROCKCHIP_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_PINCTRL=y
+CONFIG_ROCKCHIP_RK3399_PINCTRL=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
@@ -27,5 +35,11 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index a5c089b..eff5e15 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -2,9 +2,13 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
CONFIG_TARGET_FENNEC_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
@@ -46,10 +50,8 @@
CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK808=y
-CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK808=y
-CONFIG_DM_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index ba461b9..4910c80c 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -5,6 +5,8 @@
CONFIG_TARGET_FIREFLY_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
@@ -49,10 +51,8 @@
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_ACT8846=y
-CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_ACT8846=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
@@ -66,6 +66,7 @@
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index f6e01c1..1dec625 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_FLEA3=y
+# CONFIG_MMC is not set
CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="flea3 U-Boot > "
CONFIG_CMD_SPI=y
@@ -11,3 +14,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig
index e7370d3..dd2f965 100644
--- a/configs/fo300_defconfig
+++ b/configs/fo300_defconfig
@@ -1,9 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="FO300"
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
@@ -16,6 +21,7 @@
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 34e74af..02a8a78 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -16,8 +16,8 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index f79ee2e..7da870f 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -1,4 +1,5 @@
CONFIG_X86=y
+CONFIG_MMC=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="galileo"
CONFIG_TARGET_GALILEO=y
@@ -9,6 +10,8 @@
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -34,6 +37,8 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -48,4 +53,5 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig
index 4df39f6..2a5a484 100644
--- a/configs/gdppc440etx_defconfig
+++ b/configs/gdppc440etx_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_GDPPC440ETX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
@@ -15,5 +18,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index 8577167..6550c9e 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_GE_B450V3=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_DEFAULT_FDT_FILE="/boot/imx6q-b450v3.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index c5f391e..7cf1899 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_GE_B650V3=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_DEFAULT_FDT_FILE="/boot/imx6q-b650v3.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index 2c5aa05..63025bc 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -3,6 +3,9 @@
CONFIG_TARGET_GE_B850V3=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_DEFAULT_FDT_FILE="/boot/imx6q-b850v3.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig
index 7546f33..0343128 100644
--- a/configs/glacier_defconfig
+++ b/configs/glacier_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_GLACIER=y
CONFIG_DEFAULT_DEVICE_TREE="glacier"
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig
index 21f9357..31c9d0b 100644
--- a/configs/glacier_ramboot_defconfig
+++ b/configs/glacier_ramboot_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_GLACIER=y
@@ -6,6 +7,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index c463f60..57a4c78 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GOFLEXHOME=y
+CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="GoFlexHome> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -13,6 +17,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig
index 6e14154..3b22e6c 100644
--- a/configs/gplugd_defconfig
+++ b/configs/gplugd_defconfig
@@ -1,10 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_GPLUGD=y
+CONFIG_IDENT_STRING="\nMarvell-gplugD"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
@@ -14,9 +15,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig
index b30590e..faf493b 100644
--- a/configs/gr_cpci_ax2000_defconfig
+++ b/configs/gr_cpci_ax2000_defconfig
@@ -1,4 +1,5 @@
CONFIG_SPARC=y
+CONFIG_IDENT_STRING=" Gaisler LEON3 GR-CPCI-AX2000"
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_GR_CPCI_AX2000=y
CONFIG_BOOTDELAY=5
diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig
index 302d936..5b045e3 100644
--- a/configs/gr_ep2s60_defconfig
+++ b/configs/gr_ep2s60_defconfig
@@ -1,4 +1,5 @@
CONFIG_SPARC=y
+CONFIG_IDENT_STRING=" Gaisler LEON3 EP2S60"
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_GR_EP2S60=y
CONFIG_BOOTDELAY=5
diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig
index d6ed305..2319307 100644
--- a/configs/gr_xc3s_1500_defconfig
+++ b/configs/gr_xc3s_1500_defconfig
@@ -1,4 +1,5 @@
CONFIG_SPARC=y
+CONFIG_IDENT_STRING=" Gaisler LEON3 GR-XC3S-1500"
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_GR_XC3S_1500=y
CONFIG_BOOTDELAY=5
diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig
index f827113..7e83dc9 100644
--- a/configs/grsim_defconfig
+++ b/configs/grsim_defconfig
@@ -1,4 +1,5 @@
CONFIG_SPARC=y
+CONFIG_IDENT_STRING=" Gaisler GRSIM"
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_GRSIM=y
CONFIG_BOOTDELAY=5
diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig
index f5e7c43..97efdfc 100644
--- a/configs/grsim_leon2_defconfig
+++ b/configs/grsim_leon2_defconfig
@@ -1,4 +1,5 @@
CONFIG_SPARC=y
+CONFIG_IDENT_STRING=" Gaisler GRSIM LEON2"
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_GRSIM_LEON2=y
CONFIG_BOOTDELAY=5
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index a14de0d..913a763 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -15,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
index d2ef958..765f4e7 100644
--- a/configs/gurnard_defconfig
+++ b/configs/gurnard_defconfig
@@ -5,6 +5,7 @@
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index a6e4344..73a1213 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GURUPLUG=y
+CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -15,6 +18,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 71f2d50..0819a22 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -1,14 +1,28 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_GW_VENTANA=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
+# CONFIG_SYS_STDIO_DEREGISTER is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
@@ -29,16 +43,21 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Gateworks"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig
index 22f0759..e7afd81 100644
--- a/configs/h2200_defconfig
+++ b/configs/h2200_defconfig
@@ -1,6 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_H2200=y
+# CONFIG_MMC is not set
CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="> "
# CONFIG_CMD_BDI is not set
@@ -21,3 +25,4 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
+CONFIG_PXA_SERIAL=y
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index c4bd2c5..76dd833 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -9,6 +9,7 @@
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig
index 270d2a3..2447cdd 100644
--- a/configs/haleakala_defconfig
+++ b/configs/haleakala_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 4fbca28..d8712d5 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -4,9 +4,8 @@
CONFIG_TARGET_HARMONY=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -15,18 +14,16 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -39,3 +36,4 @@
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index 56bf948..b1c8afd 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_HIGHBANK=y
+# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n"
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index e20f8bc..27a8638 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -1,18 +1,14 @@
CONFIG_ARM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_IDENT_STRING="hikey"
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
-CONFIG_HUSH_PARSER=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index f67eda7..4e92019 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" hrcon 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
CONFIG_FIT=y
@@ -6,6 +7,8 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 5eff4ac..d7c9ee1 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" hrcon dh 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
CONFIG_FIT=y
@@ -7,6 +8,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 54fa819..8012c07 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -1,12 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 7ec54a7..052454d 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 5e68769..03d7ec9 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=127
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 3dea793..1901125 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_USB0_VBUS_PIN="PG12"
diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig
index 554f5d5..d5e6309 100644
--- a/configs/iNet_D978_rev2_defconfig
+++ b/configs/iNet_D978_rev2_defconfig
@@ -16,8 +16,8 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-d978-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index 89a971c..9c95b47 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_IB62X0=y
+CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ib62x0 => "
CONFIG_CMD_BOOTZ=y
@@ -15,6 +18,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ibf-dsp561_defconfig b/configs/ibf-dsp561_defconfig
index 036a92f..c598298 100644
--- a/configs/ibf-dsp561_defconfig
+++ b/configs/ibf-dsp561_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_IBF_DSP561=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index 548a07e..78cc3bb 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_OLD_SUNXI_KERNEL_COMPAT=y
@@ -12,8 +13,8 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP,CMD_UNZIP"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/icon_defconfig b/configs/icon_defconfig
index 6556fa6..39ae1f3 100644
--- a/configs/icon_defconfig
+++ b/configs/icon_defconfig
@@ -1,9 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_4xx=y
CONFIG_TARGET_ICON=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@@ -17,4 +22,5 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_SYS_NS16550=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index 8ccf515..d869628 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_ICONNECT=y
+CONFIG_IDENT_STRING=" Iomega iConnect"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="iconnect => "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -11,6 +14,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 02ca830..fd43503 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_IDS8313=y
CONFIG_FIT=y
@@ -8,6 +9,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
@@ -19,5 +21,7 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
index 992d48f..c25b6b8 100644
--- a/configs/igep0020_defconfig
+++ b/configs/igep0020_defconfig
@@ -1,10 +1,17 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_ONENAND_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -24,6 +31,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
index 84dd4ad..925c42f 100644
--- a/configs/igep0030_defconfig
+++ b/configs/igep0030_defconfig
@@ -1,11 +1,18 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_ONENAND_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -14,14 +21,9 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0030_nand_defconfig b/configs/igep0030_nand_defconfig
deleted file mode 100644
index 37417c1..0000000
--- a/configs/igep0030_nand_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
index 9529631..dad8dfa 100644
--- a/configs/igep0032_defconfig
+++ b/configs/igep0032_defconfig
@@ -1,11 +1,18 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032"
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_ONENAND_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -14,15 +21,9 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/imgtec_xilfpga_defconfig b/configs/imgtec_xilfpga_defconfig
new file mode 100644
index 0000000..1e57273
--- /dev/null
+++ b/configs/imgtec_xilfpga_defconfig
@@ -0,0 +1,26 @@
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_F_LEN=0x600
+CONFIG_TARGET_XILFPGA=y
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
+CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="MIPSfpga # "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SAVEENV is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_CLK=y
+CONFIG_XILINX_EMACLITE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig
index 136b9d1..d555c8a 100644
--- a/configs/imx31_phycore_defconfig
+++ b/configs/imx31_phycore_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_IMX31_PHYCORE=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="uboot> "
CONFIG_CMD_I2C=y
diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig
index 96252c3..eb56222 100644
--- a/configs/imx31_phycore_eet_defconfig
+++ b/configs/imx31_phycore_eet_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_IMX31_PHYCORE=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/imx6dl_icore_mmc_defconfig b/configs/imx6dl_icore_mmc_defconfig
new file mode 100644
index 0000000..9e8af0a
--- /dev/null
+++ b/configs/imx6dl_icore_mmc_defconfig
@@ -0,0 +1,43 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="icorem6qdl> "
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_SYS_I2C_MXC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
new file mode 100644
index 0000000..da1f6f6
--- /dev/null
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
+CONFIG_SPL=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="icorem6qdl> "
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_SYS_I2C_MXC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_NAND_MXS=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6dl_icore_rqs_mmc_defconfig b/configs/imx6dl_icore_rqs_mmc_defconfig
new file mode 100644
index 0000000..3b10e99
--- /dev/null
+++ b/configs/imx6dl_icore_rqs_mmc_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6Q_ICORE_RQS=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore-rqs"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6dl-icore-rqs.dtb"
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_SYS_I2C_MXC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
diff --git a/configs/imx6q_icore_mmc_defconfig b/configs/imx6q_icore_mmc_defconfig
new file mode 100644
index 0000000..370768e
--- /dev/null
+++ b/configs/imx6q_icore_mmc_defconfig
@@ -0,0 +1,43 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb"
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="icorem6qdl> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_SYS_I2C_MXC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
new file mode 100644
index 0000000..a5a3fc4
--- /dev/null
+++ b/configs/imx6q_icore_nand_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb"
+CONFIG_SPL=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="icorem6qdl> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_SYS_I2C_MXC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_NAND_MXS=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6q_icore_rqs_mmc_defconfig b/configs/imx6q_icore_rqs_mmc_defconfig
new file mode 100644
index 0000000..8df4ef0
--- /dev/null
+++ b/configs/imx6q_icore_rqs_mmc_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6Q_ICORE_RQS=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6q-icore-rqs.dtb"
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_SYS_I2C_MXC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
new file mode 100644
index 0000000..2b53b41
--- /dev/null
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6UL_GEAM=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb"
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="geam6ul> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_SYS_I2C_MXC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig
new file mode 100644
index 0000000..448529a
--- /dev/null
+++ b/configs/imx6ul_geam_nand_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6UL_GEAM=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb"
+CONFIG_SPL=y
+CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_PROMPT="geam6ul> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_NAND_MXS=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index a8b32cb..4fcd2d4 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig
index 55768ba..4ed94dc 100644
--- a/configs/inet86dz_defconfig
+++ b/configs/inet86dz_defconfig
@@ -15,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-inet86dz"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index 0b03e16..bef3cd8 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index 27b5019..7c306f8 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG0"
@@ -14,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 153450f..cc051bd 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 6de6dde..bbe20a1 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
+CONFIG_IDENT_STRING=" IS v2"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/inka4x0_defconfig b/configs/inka4x0_defconfig
index fe033c6..cf21cfb 100644
--- a/configs/inka4x0_defconfig
+++ b/configs/inka4x0_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_INKA4X0=y
CONFIG_BOOTDELAY=1
diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig
index 7b70eed..acef437 100644
--- a/configs/integratorap_cm720t_defconfig
+++ b/configs/integratorap_cm720t_defconfig
@@ -2,8 +2,12 @@
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM720T=y
+# CONFIG_MMC is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_PCI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig
index 4acb12a..fe084db 100644
--- a/configs/integratorap_cm920t_defconfig
+++ b/configs/integratorap_cm920t_defconfig
@@ -2,8 +2,12 @@
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM920T=y
+# CONFIG_MMC is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_PCI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig
index dc66f59..b4bfa6a 100644
--- a/configs/integratorap_cm926ejs_defconfig
+++ b/configs/integratorap_cm926ejs_defconfig
@@ -2,8 +2,12 @@
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM926EJ_S=y
+# CONFIG_MMC is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_PCI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig
index ce16756..4ada1f5 100644
--- a/configs/integratorap_cm946es_defconfig
+++ b/configs/integratorap_cm946es_defconfig
@@ -2,8 +2,12 @@
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM946ES=y
+# CONFIG_MMC is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_PCI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig
index 913ccab..be08259 100644
--- a/configs/integratorcp_cm1136_defconfig
+++ b/configs/integratorcp_cm1136_defconfig
@@ -2,6 +2,9 @@
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM1136=y
+# CONFIG_MMC is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig
index 17c3f94..ef4bbb5 100644
--- a/configs/integratorcp_cm920t_defconfig
+++ b/configs/integratorcp_cm920t_defconfig
@@ -2,6 +2,9 @@
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM920T=y
+# CONFIG_MMC is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig
index c757fad..3641279 100644
--- a/configs/integratorcp_cm926ejs_defconfig
+++ b/configs/integratorcp_cm926ejs_defconfig
@@ -2,6 +2,9 @@
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM926EJ_S=y
+# CONFIG_MMC is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig
index 196eab7..8964a09 100644
--- a/configs/integratorcp_cm946es_defconfig
+++ b/configs/integratorcp_cm946es_defconfig
@@ -2,6 +2,9 @@
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM946ES=y
+# CONFIG_MMC is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
diff --git a/configs/intip_defconfig b/configs/intip_defconfig
index 7e7a6c0..c929277 100644
--- a/configs/intip_defconfig
+++ b/configs/intip_defconfig
@@ -1,11 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" intip 0.06"
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_INTIP=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="INTIB"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/io64_defconfig b/configs/io64_defconfig
index 2093210..2791557 100644
--- a/configs/io64_defconfig
+++ b/configs/io64_defconfig
@@ -1,11 +1,16 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" io64 0.02"
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_IO64=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
@@ -16,5 +21,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/io_defconfig b/configs/io_defconfig
index 6cca9bf..1c9323a 100644
--- a/configs/io_defconfig
+++ b/configs/io_defconfig
@@ -1,11 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" io 0.06"
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_IO=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
@@ -16,5 +20,6 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig
index 54b8c18..175979d 100644
--- a/configs/iocon_defconfig
+++ b/configs/iocon_defconfig
@@ -1,10 +1,14 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" iocon 0.06"
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_IOCON=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
@@ -17,5 +21,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ip04_defconfig b/configs/ip04_defconfig
index 277988c..1e05d3e 100644
--- a/configs/ip04_defconfig
+++ b/configs/ip04_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_IP04=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig
index 64fa54c..258ffe6 100644
--- a/configs/ipam390_defconfig
+++ b/configs/ipam390_defconfig
@@ -1,8 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_IPAM390=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_IMLS is not set
@@ -12,4 +21,5 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig
index 54b873f..a4a637f 100644
--- a/configs/ipek01_defconfig
+++ b/configs/ipek01_defconfig
@@ -1,8 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_IPEK01=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
@@ -12,4 +16,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 9cb8b1d..6e4e6ca 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -1,13 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 21b5747..b0aa3c7 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -4,9 +4,9 @@
CONFIG_TARGET_JETSON_TK1=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -20,19 +20,20 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
diff --git a/configs/jupiter_defconfig b/configs/jupiter_defconfig
index 48249b0..1558ab1 100644
--- a/configs/jupiter_defconfig
+++ b/configs/jupiter_defconfig
@@ -1,7 +1,9 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_JUPITER=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SNTP=y
+# CONFIG_PCI is not set
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index f41fa43..835d0c9 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -1,10 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2E_EVM=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="k2e-evm"
-CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="K2E EVM # "
CONFIG_CMD_BOOTZ=y
@@ -25,6 +34,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 9890ec6..97f7187 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -1,10 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2G_EVM=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="k2g-evm"
-CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -25,9 +33,12 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+# CONFIG_BLK is not set
CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index b492db7..34defa8 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -1,10 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2HK_EVM=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="k2hk-evm"
-CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="K2HK EVM # "
CONFIG_CMD_BOOTZ=y
@@ -25,6 +34,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 9ce8fd5..75bcd9f 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -1,10 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_KEYSTONE=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2L_EVM=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="k2l-evm"
-CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="K2L EVM # "
CONFIG_CMD_BOOTZ=y
@@ -25,6 +34,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig
index bb00400..703347e 100644
--- a/configs/katmai_defconfig
+++ b/configs/katmai_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_KATMAI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index add96a8..76226e9 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_OMAP44XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_KC1=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="kc1 # "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig
index f740b0b..c57dc1b 100644
--- a/configs/kilauea_defconfig
+++ b/configs/kilauea_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig
index 67356b1..ff3d14c 100644
--- a/configs/km_kirkwood_128m16_defconfig
+++ b/configs/km_kirkwood_128m16_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_IDENT_STRING="\nKeymile Kirkwood 128M16"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
@@ -16,6 +19,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig
index 7482b93..1fdf0ac 100644
--- a/configs/km_kirkwood_defconfig
+++ b/configs/km_kirkwood_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_IDENT_STRING="\nKeymile Kirkwood"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
@@ -16,6 +19,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig
index 9b7a5fb..6c03603 100644
--- a/configs/km_kirkwood_pci_defconfig
+++ b/configs/km_kirkwood_pci_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
@@ -16,6 +19,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
index 3125387..9b3061c 100644
--- a/configs/kmcoge4_defconfig
+++ b/configs/kmcoge4_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
@@ -20,6 +21,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index e03d71b..82ba9c1 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig
index 221dcb5..6e4e73e 100644
--- a/configs/kmcoge5un_defconfig
+++ b/configs/kmcoge5un_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_IDENT_STRING="\nKeymile COGE5UN"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
@@ -16,6 +19,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 52f8be1..c4e20f4 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig
index bb38814..6f18dbc 100644
--- a/configs/kmlion1_defconfig
+++ b/configs/kmlion1_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
@@ -20,6 +21,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig
index 01f4fce..634b808 100644
--- a/configs/kmnusa_defconfig
+++ b/configs/kmnusa_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_IDENT_STRING="\nKeymile NUSA"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
@@ -16,6 +19,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index daf5a96..cc80834 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig
index 8e0f6da..af3fbe4 100644
--- a/configs/kmsugp1_defconfig
+++ b/configs/kmsugp1_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_IDENT_STRING="\nKeymile SUGP1"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
@@ -16,6 +19,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 67e11f6..400601b 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig
index eb4d583..7708b11 100644
--- a/configs/kmsuv31_defconfig
+++ b/configs/kmsuv31_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_IDENT_STRING="\nKeymile SUV31"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
@@ -16,6 +19,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index f0b1cca..8082a22 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index 936dd91..a51db85 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index 3e310ba..2013350 100644
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index d8b1eed..a4281c9 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -4,6 +4,7 @@
CONFIG_TARGET_KYLIN_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -12,6 +13,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@@ -31,7 +33,10 @@
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
CONFIG_ROCKCHIP_RK3036_PINCTRL=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig
index ba75147..f764962 100644
--- a/configs/kzm9g_defconfig
+++ b/configs/kzm9g_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_TARGET_KZM9G=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_SYS_PROMPT="KZM-A9-GT# "
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index 5ab3a61..8b01405 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -3,6 +3,8 @@
CONFIG_TARGET_LEGOEV3=y
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
new file mode 100644
index 0000000..11c5b35
--- /dev/null
+++ b/configs/liteboard_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_LITEBOARD=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_BOOTDELAY=1
+CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index c05f031..9b2ca4f 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRDM=y
+CONFIG_QSPI_AHB_INIT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
@@ -9,6 +11,7 @@
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_SF=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 8be68ee..e74141f 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
+CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
@@ -9,6 +10,7 @@
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -29,6 +31,7 @@
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index f7ef2d6..d5ed70f 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
+CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
@@ -9,6 +10,7 @@
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
@@ -29,6 +31,7 @@
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
new file mode 100644
index 0000000..21464cb
--- /dev/null
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AIOT=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
new file mode 100644
index 0000000..1369fe6
--- /dev/null
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AIOT=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 8761b60..7b1bcc3 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -1,12 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -25,6 +28,7 @@
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
@@ -32,3 +36,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 5bb475e..fd5b3b2 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -25,6 +29,7 @@
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
@@ -32,3 +37,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 084885e..1eaa640 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -1,6 +1,14 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -8,6 +16,13 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -22,11 +37,14 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 07959f5..820d6fc 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_SECURE_BOOT=y
+CONFIG_VIDEO=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -22,12 +26,16 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index a59d339..1972fd0 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -1,11 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -22,8 +26,10 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
@@ -31,3 +37,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index c7db8b7..dd44140 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -7,6 +8,9 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -23,8 +27,10 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
@@ -32,3 +38,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 49c88a6..24443e2 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -8,6 +9,9 @@
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -26,10 +30,12 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -38,3 +44,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index dc5b09a..6f14a03 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -1,12 +1,27 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -23,10 +38,13 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index dbad7ee..49bcba0 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -1,12 +1,27 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -25,10 +40,12 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -37,3 +54,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 1a5e0ef..746a66a 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
+CONFIG_SECURE_BOOT=y
+CONFIG_VIDEO=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -24,10 +28,13 @@
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 307153f..2b351aa 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -1,11 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -24,9 +28,11 @@
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 2f95780..daede61 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -7,6 +8,9 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -25,9 +29,11 @@
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index e8ae266..05793e9 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -8,6 +9,9 @@
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -31,6 +35,7 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -39,3 +44,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index a7a4713..6f22f1a 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -1,12 +1,30 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_BOOTDELAY=0
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_CRYPTO_SUPPORT=y
+CONFIG_SPL_HASH_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -21,12 +39,16 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SPL_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 439121d..22be22c 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -1,6 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -8,6 +15,13 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -23,9 +37,11 @@
CONFIG_CMD_FAT=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 70eb312..80329fc 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -1,7 +1,14 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,6 +16,13 @@
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -31,6 +45,7 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
@@ -39,3 +54,4 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index b209486..5507982 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -4,7 +4,6 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -16,6 +15,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -24,9 +24,11 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index a60ea68..ec911e0 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -4,7 +4,7 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -16,6 +16,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -24,10 +25,12 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index db85aed..bb3466f 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -1,13 +1,24 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -18,6 +29,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -26,9 +38,11 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index a844d9d..5aa058b 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -15,6 +15,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -22,10 +23,13 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 92e5e80..4e07ff3 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -4,7 +4,7 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
@@ -18,6 +18,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -26,9 +27,11 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 6bd36ae..5c20633 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -1,13 +1,24 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
@@ -18,6 +29,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -26,9 +38,11 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 71e40ad..707dcb5 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -1,13 +1,24 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -19,6 +30,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -27,9 +39,11 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 818657b..d429017 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -4,7 +4,6 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
@@ -12,6 +11,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -20,10 +20,13 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 5c20e44..9fa8921 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -4,7 +4,6 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
@@ -12,6 +11,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -20,9 +20,11 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 330666d..73e6603 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -1,19 +1,31 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -22,9 +34,11 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index daa802f..171ec37 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -1,19 +1,31 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
@@ -22,9 +34,11 @@
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
new file mode 100644
index 0000000..5636885
--- /dev/null
+++ b/configs/ls1046aqds_defconfig
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
new file mode 100644
index 0000000..83ed0e0
--- /dev/null
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
new file mode 100644
index 0000000..ebb1b5e
--- /dev/null
+++ b/configs/ls1046aqds_nand_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
+CONFIG_NAND_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
new file mode 100644
index 0000000..bdb8433
--- /dev/null
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
new file mode 100644
index 0000000..9995047
--- /dev/null
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
new file mode 100644
index 0000000..4fccce4
--- /dev/null
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -0,0 +1,34 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
new file mode 100644
index 0000000..38117f2
--- /dev/null
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046ARDB=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
new file mode 100644
index 0000000..765868a
--- /dev/null
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046ARDB=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
new file mode 100644
index 0000000..c74e007
--- /dev/null
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046ARDB=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index 21a0283..2d20c28 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080A_EMU=y
+CONFIG_IDENT_STRING=" LS2080A-EMU"
+# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="EMU,LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
@@ -18,10 +20,7 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
CONFIG_SYS_NS16550=y
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index 1b670b0..5a72bd4 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -1,12 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080A_SIMU=y
+CONFIG_IDENT_STRING=" LS2080A-SIMU"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
@@ -19,13 +20,9 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 7d2fe10..b443be3 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -6,33 +6,30 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 53d5774..d26f1b6 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -6,31 +6,27 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 6282f58..91b3b57 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -1,26 +1,28 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
@@ -28,10 +30,12 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 5917f60..803d3bb 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -5,22 +5,16 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,LS2080A"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
@@ -28,10 +22,12 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 163554b..0e6f4dc 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -6,33 +6,30 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index c477961..f22c625 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -6,31 +6,27 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index a362f0d..f42f00a 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -1,31 +1,37 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
+CONFIG_SPL=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index b9aa961..b6d95e9 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -1,8 +1,13 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_LSXL=y
+CONFIG_IDENT_STRING=" LS-CHLv2"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 794ec18..1da81b9 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -1,22 +1,20 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_LSXL=y
+CONFIG_IDENT_STRING=" LS-XHL"
+# CONFIG_MMC is not set
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
CONFIG_BOOTDELAY=3
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/luan_defconfig b/configs/luan_defconfig
index 1b93e5b..8e01f68 100644
--- a/configs/luan_defconfig
+++ b/configs/luan_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_LUAN=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig
index 807b936..dab49e7 100644
--- a/configs/lwmon5_defconfig
+++ b/configs/lwmon5_defconfig
@@ -1,9 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" - v2.0"
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_4xx=y
CONFIG_TARGET_LWMON5=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
@@ -15,7 +21,9 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig
index bace4f6..f145c40 100644
--- a/configs/m28evk_defconfig
+++ b/configs/m28evk_defconfig
@@ -1,9 +1,17 @@
CONFIG_ARM=y
CONFIG_TARGET_M28EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
@@ -23,6 +31,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig
index 042f522..45c169a 100644
--- a/configs/m53evk_defconfig
+++ b/configs/m53evk_defconfig
@@ -1,10 +1,18 @@
CONFIG_ARM=y
CONFIG_TARGET_M53EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
@@ -20,6 +28,8 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index e3431ae..e2a68fb 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -1,11 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_MA5D4EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig
index bb9ee2f..a04a934 100644
--- a/configs/makalu_defconfig
+++ b/configs/makalu_defconfig
@@ -1,8 +1,11 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_MAKALU=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index fcce6c7..4308b4f 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig
@@ -13,4 +13,5 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_OF_EMBED=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
index 002633b..b3b1401 100644
--- a/configs/malta64el_defconfig
+++ b/configs/malta64el_defconfig
@@ -14,4 +14,5 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_OF_EMBED=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index e74f23d..f1c8118 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -12,4 +12,5 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_OF_EMBED=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 3c4c1fe..88012c7 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -13,4 +13,5 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_OF_EMBED=y
+CONFIG_PCI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index dd94d22..23f4d7e 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -1,9 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
+CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
@@ -11,19 +14,13 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 22186c3..39992e8 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -1,9 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MAXBCM=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index feea816..9dc3c5a 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -1,9 +1,14 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_GPIO_SUPPORT is not set
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_MCX=y
-CONFIG_SPL=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mcx # "
# CONFIG_CMD_IMI is not set
@@ -21,9 +26,11 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig
index 98f0068..3612416 100644
--- a/configs/mecp5123_defconfig
+++ b/configs/mecp5123_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_MECP5123=y
CONFIG_OF_BOARD_SETUP=y
@@ -11,4 +12,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 24cace6..a65c3ad 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -5,9 +5,8 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -16,18 +15,13 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index b214a92..5c25eeb 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_MEESC=y
+# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index 727d193..8b42500 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_MEESC=y
+# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig
index 3c3449c..779a9c5 100644
--- a/configs/mgcoge3ne_defconfig
+++ b/configs/mgcoge3ne_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC8260=y
CONFIG_TARGET_KM82XX=y
CONFIG_FIT=y
@@ -15,4 +16,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig
index 6f62fc0..8179922 100644
--- a/configs/mgcoge3un_defconfig
+++ b/configs/mgcoge3un_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_IDENT_STRING="\nKeymile COGE3UN"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
@@ -16,6 +19,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig
index 54c277f..8004d78 100644
--- a/configs/mgcoge_defconfig
+++ b/configs/mgcoge_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC8260=y
CONFIG_TARGET_KM82XX=y
CONFIG_FIT=y
@@ -15,4 +16,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index c184923..38046f4 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -1,4 +1,7 @@
CONFIG_MICROBLAZE=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
@@ -6,11 +9,15 @@
CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
CONFIG_SYS_TEXT_BASE=0x29000000
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_OS_BASE=0x2c060000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot-mONStR> "
CONFIG_CMD_ASKENV=y
@@ -20,6 +27,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NETCONSOLE=y
diff --git a/configs/miniarm-rk3288_defconfig b/configs/miniarm-rk3288_defconfig
index 6354d1a..1e273a6 100644
--- a/configs/miniarm-rk3288_defconfig
+++ b/configs/miniarm-rk3288_defconfig
@@ -2,9 +2,13 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
CONFIG_TARGET_MINIARM_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-miniarm"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
@@ -45,10 +49,8 @@
CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK808=y
-CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK808=y
-CONFIG_DM_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 3d3a30d..f7ac94d 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -1,4 +1,5 @@
CONFIG_X86=y
+CONFIG_MMC=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
CONFIG_TARGET_MINNOWMAX=y
@@ -15,6 +16,7 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -39,6 +41,8 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -57,7 +61,10 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index ce81309..8ca8467 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -7,8 +7,8 @@
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 720aefa..bfd591a 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index d38bc7f..47bbf62 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -4,8 +4,8 @@
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index de1b73f..f9516d1 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig
index add7c06..d5c9317 100644
--- a/configs/motionpro_defconfig
+++ b/configs/motionpro_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_MOTIONPRO=y
CONFIG_OF_BOARD_SETUP=y
@@ -14,4 +15,5 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig
index 34e271b..fff0e9b 100644
--- a/configs/mpc5121ads_defconfig
+++ b/configs/mpc5121ads_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_MPC5121ADS=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig
index 6f60801..4007351 100644
--- a/configs/mpc5121ads_rev2_defconfig
+++ b/configs/mpc5121ads_rev2_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_MPC5121ADS=y
CONFIG_OF_BOARD_SETUP=y
@@ -14,6 +15,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index a1fdcf2..a45c9b7 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308_P1M=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index 648e759..9e330a7 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -1,9 +1,13 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_MT_VENTOUX=y
-CONFIG_SPL=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mt_ventoux => "
# CONFIG_CMD_IMLS is not set
@@ -19,9 +23,11 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/munices_defconfig b/configs/munices_defconfig
index 169fc93..b47c2b3 100644
--- a/configs/munices_defconfig
+++ b/configs/munices_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_MUNICES=y
CONFIG_OF_BOARD_SETUP=y
@@ -6,4 +7,5 @@
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
new file mode 100644
index 0000000..0605174
--- /dev/null
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MVEBU_DB_88F3720=y
+# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_BLOCK_CACHE=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_COMPAT=y
+CONFIG_MISC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_MVEBU_A3700_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=25804800
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_MVEBU_A3700_UART=y
+CONFIG_MVEBU_A3700_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/mvebu_db-88f7040_defconfig b/configs/mvebu_db-88f7040_defconfig
new file mode 100644
index 0000000..8dc455a
--- /dev/null
+++ b/configs/mvebu_db-88f7040_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MVEBU_ARMADA_8K=y
+# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_BLOCK_CACHE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/mvebu_db-88f8040_defconfig b/configs/mvebu_db-88f8040_defconfig
new file mode 100644
index 0000000..4a43e73
--- /dev/null
+++ b/configs/mvebu_db-88f8040_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MVEBU_ARMADA_8K=y
+# CONFIG_MMC is not set
+CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_BLOCK_CACHE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 322d941..ad27842 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -1,8 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_MX23_OLINUXINO=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 4d3a4eb..b60acb5 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -1,8 +1,16 @@
CONFIG_ARM=y
CONFIG_TARGET_MX23EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index b4afb05..87d7fab 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_MX25PDK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
CONFIG_BOOTDELAY=1
+CONFIG_DEFAULT_FDT_FILE="imx25-pdk.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index d026486..83f4a52 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -1,9 +1,17 @@
CONFIG_ARM=y
CONFIG_TARGET_MX28EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -21,6 +29,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index c6a9be0..3bd8de0 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -1,10 +1,18 @@
CONFIG_ARM=y
CONFIG_TARGET_MX28EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -22,6 +30,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index 26c9762..d511247 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -1,9 +1,17 @@
CONFIG_ARM=y
CONFIG_TARGET_MX28EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -21,6 +29,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index 73e5fc0..a3afe14 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -1,9 +1,17 @@
CONFIG_ARM=y
CONFIG_TARGET_MX28EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -21,6 +29,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig
index b4c2ad3..2a098ee 100644
--- a/configs/mx31ads_defconfig
+++ b/configs/mx31ads_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_MX31ADS=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig
index 901f992..bb1f121 100644
--- a/configs/mx31pdk_defconfig
+++ b/configs/mx31pdk_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_MX31PDK=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=1
+CONFIG_SPL=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_SPI=y
diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig
index 812e6d5..c44681f 100644
--- a/configs/mx35pdk_defconfig
+++ b/configs/mx35pdk_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_MX35PDK=y
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MMC=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index c903b41..9ac4b65 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_MX51EVK=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -15,4 +19,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index 7a62c2b..886296b 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_MX53ARD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx53-ard.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
new file mode 100644
index 0000000..9784267
--- /dev/null
+++ b/configs/mx53cx9020_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
+CONFIG_TARGET_MX53CX9020=y
+CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg"
+CONFIG_BOOTDELAY=1
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_FPGA_ALTERA=y
+CONFIG_FPGA_CYCLON2=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX5=y
+CONFIG_MXC_UART=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index b75ba01..a7a4813 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -1,7 +1,12 @@
CONFIG_ARM=y
CONFIG_TARGET_MX53LOCO=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -16,4 +21,5 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index e380570..a1c3dac 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -1,26 +1,31 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6CUBOXI=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index 5f4b979..b81b5ee 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -23,6 +27,8 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
@@ -33,4 +39,5 @@
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 300e9d9..0254a53 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -23,8 +27,11 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
@@ -33,4 +40,5 @@
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index 891f819..8f2c8c5 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -22,6 +26,8 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
@@ -32,4 +38,5 @@
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 08c9bb7..2281522 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -23,6 +27,8 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
@@ -33,4 +39,5 @@
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 4b42d08..d0ecdb9 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -30,10 +33,12 @@
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Boundary"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 2bfdd53..cef7f1a 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -23,8 +27,11 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
@@ -33,4 +40,5 @@
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 36d33bb..bb72615 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -1,9 +1,22 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6SABRESD=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -24,6 +37,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
@@ -32,4 +46,5 @@
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index bb57869..4dd2484 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -1,9 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6SLEVK=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
new file mode 100644
index 0000000..8ae049e
--- /dev/null
+++ b/configs/mx6sllevk_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
new file mode 100644
index 0000000..e6be979
--- /dev/null
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 41d46f6..499c5d9 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -26,5 +26,6 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index c9bd1f0..1a21eb0 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -24,6 +27,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index b984081..f7cbc25 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -1,9 +1,21 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6SXSABRESD=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -24,6 +36,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 49dee49..742dc5d 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -1,9 +1,21 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_14X14_EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -21,6 +33,10 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index f120119..0642895 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -1,9 +1,21 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_9X9_EVK=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -21,6 +33,10 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
new file mode 100644
index 0000000..58de479
--- /dev/null
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_SPI=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
new file mode 100644
index 0000000..56d35dd
--- /dev/null
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_SPI=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 8eac2b7..9541e12 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -4,8 +4,11 @@
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
@@ -29,6 +32,8 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig
index 0a43134..e8ccbd3 100644
--- a/configs/mx7dsabresd_secure_defconfig
+++ b/configs/mx7dsabresd_secure_defconfig
@@ -4,8 +4,11 @@
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
@@ -16,6 +19,7 @@
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
@@ -29,6 +33,10 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
new file mode 100644
index 0000000..5164245
--- /dev/null
+++ b/configs/nanopi_neo_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index 91e33d0..9d42a03 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NAS220=y
+CONFIG_IDENT_STRING="\nNAS 220"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nas220> "
# CONFIG_CMD_IMLS is not set
@@ -14,6 +17,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/neo_defconfig b/configs/neo_defconfig
index 93a402f..2dd2f6e 100644
--- a/configs/neo_defconfig
+++ b/configs/neo_defconfig
@@ -1,11 +1,15 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" neo 0.02"
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_NEO=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
@@ -14,5 +18,6 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index f30c56b..0fb0cde 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NET2BIG_V2=y
+CONFIG_IDENT_STRING=" 2Big v2"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="2big2> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 47aad38..72f761a 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
+CONFIG_IDENT_STRING=" NS v2 Lite"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index 7b9f190..3eb1188 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
+CONFIG_IDENT_STRING=" NS Max v2"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index f46b9a1..16f544c 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
+CONFIG_IDENT_STRING=" NS v2 Mini"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 1b94cee..5b5954b 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
+CONFIG_IDENT_STRING=" NS v2"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 849772f..cd4b675 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -28,10 +31,12 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Boundary"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 4a62c56..7ea8f51 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -28,10 +31,12 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Boundary"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 68cdb89..d9df123 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -28,10 +31,12 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Boundary"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index a380502..0063df7 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -28,10 +31,12 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Boundary"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 3c7b903..1572b9b 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -28,10 +31,12 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Boundary"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 590bb27..6c40616 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
+CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -28,10 +31,12 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Boundary"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index da10392..210a9b1 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -1,10 +1,14 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_NOKIA_RX51=y
+CONFIG_VIDEO=y
CONFIG_BOOTDELAY=30
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Nokia RX-51 # "
CONFIG_AUTOBOOT_KEYED=y
+CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SAVEENV is not set
@@ -20,3 +24,5 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_SYS_NS16550=y
+CONFIG_CFB_CONSOLE_ANSI=y
+# CONFIG_VGA_AS_SINGLE_DEVICE is not set
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 33877ad..dd1f36f 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -1,12 +1,23 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_KOSAGI_NOVENA=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -14,18 +25,14 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index 0a9c153..7233354 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -1,7 +1,9 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NSA310S=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nsa310s => "
CONFIG_CMD_BOOTZ=y
@@ -15,6 +17,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 26ee388..e6f862d 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -6,9 +6,8 @@
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -22,24 +21,21 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_CROS_EC_KEYB=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 3e9ef68..7d0b2b1 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -2,7 +2,11 @@
CONFIG_ARCH_MESON=y
CONFIG_MESON_GXBB=y
CONFIG_TARGET_ODROID_C2=y
+CONFIG_IDENT_STRING=" odroid-c2"
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 15e9bd9..a6ec2ee 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -1,13 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
+CONFIG_IDENT_STRING=" for ODROID-XU3"
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_CONSOLE_MUX=y
CONFIG_SYS_PROMPT="ODROID-XU3 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
@@ -16,21 +18,16 @@
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ADC=y
CONFIG_ADC_EXYNOS=y
-CONFIG_DM_I2C=y
+CONFIG_DFU_MMC=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_S2MPS11=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 4e47032..e12208c 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -6,6 +6,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Odroid # "
CONFIG_CMD_BOOTZ=y
@@ -32,8 +34,11 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_DM_I2C=y
+CONFIG_DFU_MMC=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index 5fd86af..4816a03 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -1,11 +1,13 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_BEAGLE=y
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SPL=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -14,15 +16,8 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 82314bd..6ca7e2c 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -1,8 +1,9 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_EVM=y
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="OMAP3_EVM # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index 3ef3f59..3fcbb76 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -1,9 +1,10 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_TAO3530=y
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index dfd7611..ac1a6a3 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_LOGIC=y
-CONFIG_SPL=y
-CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="OMAP Logic # "
CONFIG_CMD_BOOTZ=y
@@ -26,6 +28,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index 1e282c1..b902283 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_OVERO=y
-CONFIG_SPL=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Overo # "
CONFIG_CMD_BOOTZ=y
@@ -27,6 +30,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
index 0c2c12b..6635c69 100644
--- a/configs/omap3_pandora_defconfig
+++ b/configs/omap3_pandora_defconfig
@@ -1,10 +1,11 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_PANDORA=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Pandora # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
@@ -16,15 +17,9 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig
index e92d9c6..e7f8fd0 100644
--- a/configs/omap3_zoom1_defconfig
+++ b/configs/omap3_zoom1_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_ZOOM1=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index b69124e..8d90248 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -1,10 +1,15 @@
CONFIG_ARM=y
CONFIG_OMAP44XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_I2C_SUPPORT is not set
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_OMAP4_PANDA=y
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -14,15 +19,8 @@
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 684f4e1..de339ca 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -1,10 +1,13 @@
CONFIG_ARM=y
CONFIG_OMAP44XX=y
+# CONFIG_SPL_I2C_SUPPORT is not set
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_OMAP4_SDP4430=y
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -14,14 +17,7 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index ec75672..18843d2 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_OMAP5_UEVM=y
-CONFIG_SPL=y
+CONFIG_ARMV7_LPAE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -23,6 +27,8 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 8cb486d..d030ffa 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -1,11 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_OMAPL138_LCDK=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -16,6 +24,9 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 2e14052..0168579 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
+CONFIG_IDENT_STRING="\nOpenRD-Base"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
@@ -13,6 +15,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index 49bd597..84fa149 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
+CONFIG_IDENT_STRING="\nOpenRD-Client"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
@@ -13,6 +15,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index 5ee4ba2..026204d 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
+CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
@@ -13,6 +15,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/openrisc-generic_defconfig b/configs/openrisc-generic_defconfig
index db80dfd..55f0122 100644
--- a/configs/openrisc-generic_defconfig
+++ b/configs/openrisc-generic_defconfig
@@ -1,5 +1,6 @@
CONFIG_OPENRISC=y
CONFIG_TARGET_OPENRISC_GENERIC=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 95075c2..4727aca 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
@@ -7,6 +8,7 @@
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
index a72d506..8545835 100644
--- a/configs/orangepi_lite_defconfig
+++ b/configs/orangepi_lite_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 5a7aba1..01b4ece 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 0c156bd..910d68e 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -1,11 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig
index 8caca59..f43682b 100644
--- a/configs/orangepi_pc_plus_defconfig
+++ b/configs/orangepi_pc_plus_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
@@ -7,6 +8,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
index 2374f1d..df05d37 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
@@ -7,8 +8,9 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACPWR=SUNXI_GPD(6)"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index f2ed941..bf88fef 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
@@ -8,8 +9,9 @@
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11),MACPWR=SUNXI_GPD(6)"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 6ad01af..0dcc9e8 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -2,7 +2,10 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_ORIGEN=y
+CONFIG_IDENT_STRING=" for ORIGEN"
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ORIGEN # "
@@ -25,6 +28,10 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_DFU_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 782accd..d1bdbde 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -1,9 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_OT1200=y
-CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 7a6b823..0ff4c13 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -4,7 +4,8 @@
CONFIG_TARGET_P2371_0000=y
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
@@ -19,15 +20,13 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index 180dde3..4dfb02d 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -4,7 +4,8 @@
CONFIG_TARGET_P2371_2180=y
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
@@ -19,18 +20,19 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index fa6ca23..e49a42f 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -4,7 +4,8 @@
CONFIG_TARGET_P2571=y
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (P2571) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
@@ -19,15 +20,13 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
index 4c4606a..b4daa12 100644
--- a/configs/p2771-0000-000_defconfig
+++ b/configs/p2771-0000-000_defconfig
@@ -3,7 +3,8 @@
CONFIG_TEGRA186=y
CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
@@ -16,18 +17,17 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
CONFIG_TEGRA186_BPMP_I2C=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_DWC_ETH_QOS=y
CONFIG_E1000=y
CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_POWER_DOMAIN=y
CONFIG_TEGRA186_POWER_DOMAIN=y
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
index b32df1c..02e974d 100644
--- a/configs/p2771-0000-500_defconfig
+++ b/configs/p2771-0000-500_defconfig
@@ -3,7 +3,8 @@
CONFIG_TEGRA186=y
CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-500"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
@@ -16,18 +17,17 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_BLK is not set
CONFIG_TEGRA186_BPMP_I2C=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_DWC_ETH_QOS=y
CONFIG_E1000=y
CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_POWER_DOMAIN=y
CONFIG_TEGRA186_POWER_DOMAIN=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index b86f76c..b3d6f90 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -4,9 +4,8 @@
CONFIG_TARGET_PAZ00=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -15,18 +14,13 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -37,3 +31,4 @@
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig
index ddf7dde..3e39dc0 100644
--- a/configs/pcm030_LOWBOOT_defconfig
+++ b/configs/pcm030_LOWBOOT_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_PCM030=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig
index d3181c8..fdb0d1b 100644
--- a/configs/pcm030_defconfig
+++ b/configs/pcm030_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_PCM030=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index f14ba67..bc6e92d 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -1,8 +1,27 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_TARGET_PCM051=y
-CONFIG_SPL=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="REV1"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_ETH_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 3921886..acdf192 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -1,8 +1,27 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_TARGET_PCM051=y
-CONFIG_SPL=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="REV3"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_ETH_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 52cb1d5..f7db263 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -14,6 +14,7 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index 5c08171..b2f70ea 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -1,10 +1,23 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_PCM058=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -22,6 +35,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_DM=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig
index f3de685..52b5d6f 100644
--- a/configs/pdm360ng_defconfig
+++ b/configs/pdm360ng_defconfig
@@ -1,10 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC512X=y
CONFIG_TARGET_PDM360NG=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_I2C=y
@@ -12,4 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index e6a47cc..ef021184 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -2,13 +2,14 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_PEACH_PI=y
+CONFIG_IDENT_STRING=" for Peach-Pi"
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SPL=y
CONFIG_SYS_PROMPT="Peach-Pi # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -17,29 +18,22 @@
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -65,5 +59,6 @@
CONFIG_DISPLAY=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
+CONFIG_LCD=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 9778341..14fe00e 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -2,13 +2,14 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_PEACH_PIT=y
+CONFIG_IDENT_STRING=" for Peach-Pit"
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SPL=y
CONFIG_SYS_PROMPT="Peach-Pit # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -17,29 +18,22 @@
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -65,5 +59,6 @@
CONFIG_DISPLAY=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
+CONFIG_LCD=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 0035d89..2da2126 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -1,7 +1,28 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_TARGET_PENGWYN=y
-CONFIG_SPL=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_ETH_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index 8a38b89..0592ed9 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -1,7 +1,20 @@
CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_PEPPER=y
-CONFIG_SPL=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="pepper# "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 4e986bb..852eb0a 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -1,11 +1,12 @@
CONFIG_MIPS=y
CONFIG_SYS_MALLOC_F_LEN=0x600
+CONFIG_MMC=y
CONFIG_MACH_PIC32=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="dask # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SAVEENV is not set
@@ -18,21 +19,16 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_RARP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_BLK is not set
CONFIG_CLK=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_PIC32_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_DM_ETH=y
CONFIG_PIC32_ETH=y
CONFIG_PINCTRL=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index a111899..8856afb 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -3,6 +3,7 @@
CONFIG_TARGET_PICO_IMX6UL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -22,6 +23,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 3ecc272..90cc75e 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -1,9 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PICOSAM9G45=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -21,4 +32,5 @@
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 6f82190..6d0198f 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -6,7 +6,9 @@
CONFIG_DRAM_ZQ=3881915
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index 1dbb3d3..71ebc25 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -1,9 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_PLATINUM_PICON=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="picon > "
CONFIG_CMD_BOOTZ=y
@@ -24,6 +35,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index 8174481..51aeff1 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -1,9 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_PLATINUM_TITANIUM=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="titanium > "
CONFIG_CMD_BOOTZ=y
@@ -24,6 +35,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index b1997fe..3c45b9d 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -5,9 +5,9 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -16,16 +16,11 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index 361e9bb..6bc5f6f 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9261=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="pm9261> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
@@ -16,3 +20,4 @@
CONFIG_CMD_CACHE=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index f9f56d2..1a3de43 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9263=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_PROMPT="u-boot-pm9263> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
@@ -16,3 +19,4 @@
CONFIG_CMD_CACHE=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index 8d3ca22..8561097 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9G45=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 2b1d873..b98093e 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_POGO_E02=y
+CONFIG_IDENT_STRING="\nPogo E02"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="PogoE02> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -12,6 +15,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig
index 9bf6fbf..2ac6f4c 100644
--- a/configs/polaroid_mid2407pxe03_defconfig
+++ b/configs/polaroid_mid2407pxe03_defconfig
@@ -15,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2407pxe03"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 04c99b9..d9bcd4f 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -15,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 112e6ae..663724e 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -2,9 +2,13 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
CONFIG_TARGET_POPMETAL_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
@@ -45,10 +49,8 @@
CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK808=y
-CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK808=y
-CONFIG_DM_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig
index 94f9349..4da0cea 100644
--- a/configs/portl2_defconfig
+++ b/configs/portl2_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_IDENT_STRING="\nKeymile Port-L2"
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2"
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
@@ -16,6 +19,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index 9aa5280..8e81e69 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig
index e7cf5e8..a26ba61 100644
--- a/configs/pr1_defconfig
+++ b/configs/pr1_defconfig
@@ -1,5 +1,6 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_PR1=y
+CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_PROMPT="pr1>"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index bafe4f4..650d23d 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -1,10 +1,30 @@
CONFIG_ARM=y
CONFIG_TARGET_PXM2=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -27,10 +47,14 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DFU_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
@@ -41,3 +65,6 @@
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_SYS_CONSOLE_BG_COL=0xff
+CONFIG_SYS_CONSOLE_FG_COL=0x00
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index b467b62..6b516db 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PG0"
@@ -14,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 7391464..971dcea 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -15,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index 16f8600..f99e347 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -15,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index 6378918..182bd9a 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -15,8 +15,8 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 038eb39..6413567 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_QEMU_PPCE500=y
CONFIG_FIT=y
@@ -6,6 +7,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 769adf6..4566d37 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -1,13 +1,14 @@
CONFIG_X86=y
+CONFIG_MAX_CPUS=2
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_SMP=y
-CONFIG_MAX_CPUS=2
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -44,7 +45,10 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu-x86_efi_payload32_defconfig b/configs/qemu-x86_efi_payload32_defconfig
index 75e7203..f580d45 100644
--- a/configs/qemu-x86_efi_payload32_defconfig
+++ b/configs/qemu-x86_efi_payload32_defconfig
@@ -1,10 +1,11 @@
CONFIG_X86=y
+CONFIG_MAX_CPUS=2
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_SMP=y
-CONFIG_MAX_CPUS=2
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -41,9 +42,12 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_EFI=y
CONFIG_EFI_STUB=y
diff --git a/configs/qemu-x86_efi_payload64_defconfig b/configs/qemu-x86_efi_payload64_defconfig
index 4bcd0dc..975714b 100644
--- a/configs/qemu-x86_efi_payload64_defconfig
+++ b/configs/qemu-x86_efi_payload64_defconfig
@@ -1,12 +1,14 @@
CONFIG_X86=y
+CONFIG_MAX_CPUS=2
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_SMP=y
-CONFIG_MAX_CPUS=2
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
@@ -41,9 +43,12 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_EFI=y
CONFIG_EFI_STUB=y
diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index 1c1e304..2637723 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig
@@ -5,4 +5,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
+CONFIG_NETDEVICES=y
+CONFIG_RTL8139=y
+CONFIG_PCI=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 9d9d4bf..afbc9a6 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
CONFIG_USB1_VBUS_PIN="PG13"
diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig
index fbf2dd5..77d9c06 100644
--- a/configs/r7780mp_defconfig
+++ b/configs/r7780mp_defconfig
@@ -20,4 +20,5 @@
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
+CONFIG_PCI=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig
index c0e647e..c76b7b9 100644
--- a/configs/rainier_defconfig
+++ b/configs/rainier_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig
index 7030fe4..7bb948d 100644
--- a/configs/rainier_ramboot_defconfig
+++ b/configs/rainier_ramboot_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index f3bdd79..d3ac645 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -1,9 +1,26 @@
CONFIG_ARM=y
CONFIG_TARGET_RASTABAN=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -25,10 +42,14 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DFU_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig
index b0400eb..9fdfd7d 100644
--- a/configs/redwood_defconfig
+++ b/configs/redwood_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_REDWOOD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
@@ -13,5 +15,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 652b13f..91be32c 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -1,9 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
+CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
@@ -11,19 +14,13 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index fc9ff78..9e332bc 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -2,9 +2,12 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
CONFIG_TARGET_ROCK2=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_HUSH_PARSER=y
@@ -46,10 +49,8 @@
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_ACT8846=y
-CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_ACT8846=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
@@ -62,6 +63,7 @@
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index bda4e95..9d669c9 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -1,24 +1,24 @@
CONFIG_ARM=y
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI_2=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_LCD=y
CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index 8e2c410..d0f7bea 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -2,25 +2,25 @@
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI_3_32B=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_LCD=y
CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index b7354eb..ce28c31 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -2,8 +2,11 @@
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI_3=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -11,15 +14,13 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_LCD=y
CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index ea39231..4a90ca8 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -1,24 +1,24 @@
CONFIG_ARM=y
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_LCD=y
CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 33e47ba..4c99c13 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -1,10 +1,30 @@
CONFIG_ARM=y
CONFIG_TARGET_RUT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -27,10 +47,14 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DFU_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
@@ -41,3 +65,6 @@
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_SYS_CONSOLE_BG_COL=0xff
+CONFIG_SYS_CONSOLE_FG_COL=0x00
diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig
index dfedf82..0da90dc 100644
--- a/configs/s32v234evb_defconfig
+++ b/configs/s32v234evb_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_S32V234EVB=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index b381e21..f716c38 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_S5PC1XX=y
CONFIG_TARGET_S5P_GONI=y
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Goni # "
# CONFIG_AUTOBOOT is not set
@@ -20,6 +21,12 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_DFU_MMC=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_MAX8998=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 5eb7a40..b6cefb1 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -3,6 +3,8 @@
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_S5PC210_UNIVERSAL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Universal # "
CONFIG_CMD_BOOTZ=y
@@ -26,6 +28,10 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_DFU_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/salvator-x_defconfig b/configs/salvator-x_defconfig
index 9df4867..bf8f7c7 100644
--- a/configs/salvator-x_defconfig
+++ b/configs/salvator-x_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
+# CONFIG_MMC is not set
CONFIG_BOOTSTAGE_USER_COUNT=0x20
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig
index d65aed0..5d977bd 100644
--- a/configs/sama5d2_ptc_nandflash_defconfig
+++ b/configs/sama5d2_ptc_nandflash_defconfig
@@ -1,9 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D2_PTC=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig
index 799111a..29238a3 100644
--- a/configs/sama5d2_ptc_spiflash_defconfig
+++ b/configs/sama5d2_ptc_spiflash_defconfig
@@ -1,9 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D2_PTC=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 8051fc8..a6daef4 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -1,10 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D2_XPLAINED=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -13,14 +22,47 @@
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_DM_MMC=y
+CONFIG_ATMEL_SDHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 69b136c..41ab772 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -1,10 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D2_XPLAINED=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -13,14 +21,47 @@
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_DM_MMC=y
+CONFIG_ATMEL_SDHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 225284a..4f4e51b 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -1,10 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D3_XPLAINED=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -20,6 +28,7 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 8710f07..e83d047 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -1,10 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D3_XPLAINED=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -20,6 +26,7 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index a9cddf1..ea6d4b9 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -1,10 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D3XEK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -23,4 +33,5 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 9690de7..f8504cc 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -1,10 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D3XEK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -23,4 +31,5 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 064b9a9..b5cabaf 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -1,10 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D3XEK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -23,4 +32,5 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 820aca8..5ff4688 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -1,10 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D4_XPLAINED=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 8d31742..800a8b2 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -1,10 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D4_XPLAINED=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index ccc9298..e5d2f54 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -1,10 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D4_XPLAINED=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 4cfd821..4899970 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -1,10 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D4EK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -24,4 +34,5 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 5cbe6e7..9ebe295 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -1,10 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D4EK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -24,4 +32,5 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 219a8c2..dff8995 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -1,10 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SAMA5D4EK=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -24,4 +33,5 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index fc9b4ac..8ac231d 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,8 +1,6 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_MMC=y
-CONFIG_PCI=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_I8042_KEYB=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
@@ -16,7 +14,7 @@
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
@@ -38,9 +36,6 @@
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CDP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
@@ -54,11 +49,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_NETCONSOLE=y
@@ -70,7 +61,6 @@
CONFIG_DEBUG_DEVRES=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
-CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
@@ -87,12 +77,12 @@
CONFIG_SPL_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
+CONFIG_I8042_KEYB=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_SANDBOX_MBOX=y
CONFIG_MISC=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_LPC=y
@@ -101,7 +91,6 @@
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC_OPS=y
CONFIG_SANDBOX_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
@@ -114,6 +103,7 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
+CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 85610ed..a9456cc 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -1,7 +1,6 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_PCI=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_I8042_KEYB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
@@ -15,6 +14,7 @@
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
+CONFIG_SILENT_CONSOLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
@@ -68,6 +68,7 @@
CONFIG_DEBUG_DEVRES=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
+# CONFIG_BLK is not set
CONFIG_CLK=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
@@ -84,9 +85,9 @@
CONFIG_SPL_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
+CONFIG_I8042_KEYB=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_LPC=y
@@ -105,6 +106,7 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
+CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 808ac34..f4b656c 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -1,9 +1,12 @@
-CONFIG_MMC=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SANDBOX_SPL=y
-CONFIG_PCI=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_I8042_KEYB=y
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
@@ -17,7 +20,8 @@
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SPL=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
@@ -39,9 +43,6 @@
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CDP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
@@ -55,11 +56,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
@@ -75,7 +72,6 @@
# CONFIG_SPL_SIMPLE_BUS is not set
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
-CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
@@ -92,12 +88,12 @@
CONFIG_SPL_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
+CONFIG_I8042_KEYB=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_SANDBOX_MBOX=y
CONFIG_MISC=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_LPC=y
@@ -105,7 +101,6 @@
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
-CONFIG_DM_MMC_OPS=y
CONFIG_SANDBOX_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
@@ -118,6 +113,7 @@
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
+CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index 7af5935..b25bf1d 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -1,8 +1,16 @@
CONFIG_ARM=y
CONFIG_TARGET_SANSA_FUZE_PLUS=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index 7231b60..201c9ed 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -1,9 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
+CONFIG_SYS_EXTRA_OPTIONS="PCI_33M"
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index bf125a5..afc4d10 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -1,9 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
+CONFIG_SYS_EXTRA_OPTIONS="PCI_66M"
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index daa2313..cafc16d 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_OF_BOARD_SETUP=y
@@ -9,5 +10,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
index c5fc4a0..3af5c70 100644
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ b/configs/sbc8548_PCI_33_PCIE_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
+CONFIG_SYS_EXTRA_OPTIONS="33,PCIE"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
index 1fd17ca..671b35d 100644
--- a/configs/sbc8548_PCI_33_defconfig
+++ b/configs/sbc8548_PCI_33_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
+CONFIG_SYS_EXTRA_OPTIONS="33"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
index 5396e5a..61b7470 100644
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ b/configs/sbc8548_PCI_66_PCIE_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
+CONFIG_SYS_EXTRA_OPTIONS="66,PCIE"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
index ffde056..8c8b38d 100644
--- a/configs/sbc8548_PCI_66_defconfig
+++ b/configs/sbc8548_PCI_66_defconfig
@@ -1,10 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
+CONFIG_SYS_EXTRA_OPTIONS="66"
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
index a8a8a93..fe2a6b9 100644
--- a/configs/sbc8548_defconfig
+++ b/configs/sbc8548_defconfig
@@ -1,13 +1,16 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
index a382794..24305da 100644
--- a/configs/sbc8641d_defconfig
+++ b/configs/sbc8641d_defconfig
@@ -1,9 +1,11 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC86xx=y
CONFIG_TARGET_SBC8641D=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index 30233fc..81fb434 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -1,8 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_SC_SPS_1=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 12cc9b6..c3119dc 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -4,9 +4,7 @@
CONFIG_TARGET_SEABOARD=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -16,18 +14,13 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -35,6 +28,10 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig
index 9bdab0b..33261b8 100644
--- a/configs/sequoia_defconfig
+++ b/configs/sequoia_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig
index 65ae39a..000be91 100644
--- a/configs/sequoia_ramboot_defconfig
+++ b/configs/sequoia_ramboot_defconfig
@@ -1,9 +1,12 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig
index 73b1ac6..ae5e038 100644
--- a/configs/sh7752evb_defconfig
+++ b/configs/sh7752evb_defconfig
@@ -1,4 +1,5 @@
CONFIG_SH=y
+CONFIG_MMC=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7752EVB=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig
index e0037a6..f8b9d86 100644
--- a/configs/sh7753evb_defconfig
+++ b/configs/sh7753evb_defconfig
@@ -1,4 +1,5 @@
CONFIG_SH=y
+CONFIG_MMC=y
CONFIG_TARGET_SH7753EVB=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig
index a80c10c..b12c11e 100644
--- a/configs/sh7757lcr_defconfig
+++ b/configs/sh7757lcr_defconfig
@@ -1,4 +1,5 @@
CONFIG_SH=y
+CONFIG_MMC=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7757LCR=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig
index 8824d53..7d8a230 100644
--- a/configs/sh7785lcr_32bit_defconfig
+++ b/configs/sh7785lcr_32bit_defconfig
@@ -23,6 +23,7 @@
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sh7785lcr_defconfig b/configs/sh7785lcr_defconfig
index 386eb33..c9c9b08 100644
--- a/configs/sh7785lcr_defconfig
+++ b/configs/sh7785lcr_defconfig
@@ -22,6 +22,7 @@
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index dbafcf2..e15355d 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -1,7 +1,9 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_SHEEVAPLUG=y
+CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -16,6 +18,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index cf8bff6..eab598e 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -1,11 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SMARTWEB=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -23,6 +29,7 @@
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DFU_NAND=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig
deleted file mode 100644
index 3d098ba..0000000
--- a/configs/smdk2410_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_SMDK2410=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="SMDK2410 # "
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index dbd3137..b785efe 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -2,13 +2,15 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SMDK5250=y
+CONFIG_IDENT_STRING=" for SMDK5250"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
CONFIG_SYS_PROMPT="SMDK5250 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -17,21 +19,15 @@
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 63a95a8..daa46d4 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -2,13 +2,15 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SMDK5420=y
+CONFIG_IDENT_STRING=" for SMDK5420"
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
CONFIG_SYS_PROMPT="SMDK5420 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -17,18 +19,12 @@
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 0948534..b69f5d4 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_TARGET_SMDKC100=y
+CONFIG_IDENT_STRING=" for SMDKC100"
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 5e3844c..a75a1f0 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS4=y
+CONFIG_IDENT_STRING=" for SMDKC210/V310"
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
@@ -21,5 +22,8 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 28e149a..d66635d 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -1,9 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SNAPPER9260=y
+# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Snapper> "
# CONFIG_CMD_BDI is not set
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index 564d5b4..416f543 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -1,9 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SNAPPER9260=y
+# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 1b313c4..6f55503 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_SNIPER=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="sniper # "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 0c9e3f1..47b498b 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -2,13 +2,14 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SNOW=y
+CONFIG_IDENT_STRING=" for snow"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SPL=y
CONFIG_SYS_PROMPT="snow # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -17,9 +18,6 @@
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
@@ -27,20 +25,16 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -73,5 +67,6 @@
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y
+CONFIG_LCD=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index a6d4945..d91990c 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -1,13 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -30,8 +35,10 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index b34e7e5..905f766 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -1,13 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -30,8 +35,10 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 127f36c..7daf81a 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -1,13 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -30,7 +35,9 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
+CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
new file mode 100644
index 0000000..d8a3b82
--- /dev/null
+++ b/configs/socfpga_de1_soc_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+# CONFIG_SPL_SPI_SUPPORT is not set
+CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USE_TINY_PRINTF=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index d23afbf..5ac6c49 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -1,12 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_IS1=y
+# CONFIG_MMC is not set
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -26,6 +32,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 0100726..5a53246 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -1,13 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -30,7 +35,9 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
+CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index d708e13..9450d21 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -1,13 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -30,8 +35,10 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 35dad70..84a8890 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -1,13 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -31,8 +36,10 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 2a4494f..641dd4d 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -1,13 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SR1500=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -29,6 +35,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 7fdaeca..608cdf8 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -1,14 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -32,9 +37,13 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
@@ -42,6 +51,7 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 75db38f..078a797 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -1,10 +1,14 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_SOCRATES=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
@@ -18,4 +22,5 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
index 4cfaeda..a3ba8c1 100644
--- a/configs/som-db5800-som-6867_defconfig
+++ b/configs/som-db5800-som-6867_defconfig
@@ -14,6 +14,7 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -55,7 +56,10 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig
index 2ef309c..30a00c6 100644
--- a/configs/spear300_defconfig
+++ b/configs/spear300_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
-CONFIG_SYS_EXTRA_OPTIONS="spear300"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR300"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig
index 611631e..0af3a45 100644
--- a/configs/spear300_nand_defconfig
+++ b/configs/spear300_nand_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
-CONFIG_SYS_EXTRA_OPTIONS="spear300,nand"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,NAND"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig
index 5338418..b517b1b 100644
--- a/configs/spear300_usbtty_defconfig
+++ b/configs/spear300_usbtty_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
-CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig
index d525edf..a33459a 100644
--- a/configs/spear300_usbtty_nand_defconfig
+++ b/configs/spear300_usbtty_nand_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
-CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty,nand"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig
index 3f20387..9c9a8ab 100644
--- a/configs/spear310_defconfig
+++ b/configs/spear310_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_SYS_EXTRA_OPTIONS="spear310"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR310"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig
index 2feb9ccf..8da365e 100644
--- a/configs/spear310_nand_defconfig
+++ b/configs/spear310_nand_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_SYS_EXTRA_OPTIONS="spear310,nand"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,NAND"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig
index 4ab49d9..1ff5fea 100644
--- a/configs/spear310_pnor_defconfig
+++ b/configs/spear310_pnor_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_SYS_EXTRA_OPTIONS="spear310,FLASH_PNOR"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,FLASH_PNOR"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig
index 299cf6d..1f20e45 100644
--- a/configs/spear310_usbtty_defconfig
+++ b/configs/spear310_usbtty_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig
index 9ac10f2..2490ac3 100644
--- a/configs/spear310_usbtty_nand_defconfig
+++ b/configs/spear310_usbtty_nand_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,nand"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig
index f582b46..3ebae7b 100644
--- a/configs/spear310_usbtty_pnor_defconfig
+++ b/configs/spear310_usbtty_pnor_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
-CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,FLASH_PNOR"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,FLASH_PNOR"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig
index 4b4f2f6..60feb7e 100644
--- a/configs/spear320_defconfig
+++ b/configs/spear320_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_SYS_EXTRA_OPTIONS="spear320"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR320"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig
index 7308879..0a481e4 100644
--- a/configs/spear320_nand_defconfig
+++ b/configs/spear320_nand_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_SYS_EXTRA_OPTIONS="spear320,nand"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,NAND"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig
index fdffa97..b3e2725 100644
--- a/configs/spear320_pnor_defconfig
+++ b/configs/spear320_pnor_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_SYS_EXTRA_OPTIONS="spear320,FLASH_PNOR"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,FLASH_PNOR"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig
index ee873e9..a729980 100644
--- a/configs/spear320_usbtty_defconfig
+++ b/configs/spear320_usbtty_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig
index a587470..858ee65 100644
--- a/configs/spear320_usbtty_nand_defconfig
+++ b/configs/spear320_usbtty_nand_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,nand"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig
index a65dc11..fea3027 100644
--- a/configs/spear320_usbtty_pnor_defconfig
+++ b/configs/spear320_usbtty_pnor_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
-CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,FLASH_PNOR"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,FLASH_PNOR"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
index 623800c..acd1542 100644
--- a/configs/spear600_defconfig
+++ b/configs/spear600_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
-CONFIG_SYS_EXTRA_OPTIONS="spear600"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR600"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
index 8da9b34..6e0a912 100644
--- a/configs/spear600_nand_defconfig
+++ b/configs/spear600_nand_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
-CONFIG_SYS_EXTRA_OPTIONS="spear600,nand"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,NAND"
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index 68b11cc..f42f1a8 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
-CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index 776c611..b736dc8 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
-CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty,nand"
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
+CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index 030973b..4a782c8 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -2,13 +2,14 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_SPRING=y
+CONFIG_IDENT_STRING=" for spring"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
-CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SPL=y
CONFIG_SYS_PROMPT="spring # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -17,9 +18,6 @@
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
@@ -27,20 +25,16 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_CROS_EC_KEYB=y
-CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
@@ -72,5 +66,6 @@
CONFIG_DISPLAY=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
+CONFIG_LCD=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index ae9976b..c554d2d 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -2,9 +2,13 @@
CONFIG_STM32=y
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIMER=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index e3e6333..55b9eba 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -2,7 +2,10 @@
CONFIG_STM32=y
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 6253615..6ab1f51 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" strider con 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_FIT=y
@@ -7,6 +8,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
index 3d325f4..71193d0 100644
--- a/configs/strider_con_dp_defconfig
+++ b/configs/strider_con_dp_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" strider con dp 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_FIT=y
@@ -7,6 +8,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index 160df24..61963be 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" strider cpu 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_FIT=y
@@ -7,6 +8,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
index 2a2733d..560dc65 100644
--- a/configs/strider_cpu_dp_defconfig
+++ b/configs/strider_cpu_dp_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+CONFIG_IDENT_STRING=" strider cpu dp 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_FIT=y
@@ -7,6 +8,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index 40ca293..f808ce2 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -1,9 +1,12 @@
CONFIG_ARM=y
CONFIG_TARGET_STV0991=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
-CONFIG_SYS_EXTRA_OPTIONS="stv0991"
+CONFIG_SYS_EXTRA_OPTIONS="STV0991"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="STV0991> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 6d39dec..7309022 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index 86c258b..cd5e1cb 100644
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig
index f927c4c..b19146b 100644
--- a/configs/sycamore_defconfig
+++ b/configs/sycamore_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig
index 3e04031..84372a9 100644
--- a/configs/t3corp_defconfig
+++ b/configs/t3corp_defconfig
@@ -1,10 +1,13 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_T3CORP=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index 0f69138..88a3725 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -1,8 +1,9 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_TAO3530=y
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="TAO-3530 # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index f0e95a4..793de29 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -1,10 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_TAURUS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
@@ -23,6 +32,7 @@
CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DFU_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index fbff9fe..9fefa5f 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TBS2910=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Matrix U-Boot> "
CONFIG_CMD_BOOTZ=y
@@ -25,13 +28,16 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
+CONFIG_PCI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="TBS"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/tcm-bf518_defconfig b/configs/tcm-bf518_defconfig
index fd31cfc..9288e56 100644
--- a/configs/tcm-bf518_defconfig
+++ b/configs/tcm-bf518_defconfig
@@ -1,6 +1,7 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_TCM_BF518=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
diff --git a/configs/tcm-bf537_defconfig b/configs/tcm-bf537_defconfig
index d66e499..fd2e76e 100644
--- a/configs/tcm-bf537_defconfig
+++ b/configs/tcm-bf537_defconfig
@@ -1,6 +1,8 @@
CONFIG_BLACKFIN=y
+CONFIG_MMC=y
CONFIG_TARGET_TCM_BF537=y
CONFIG_BOOTDELAY=5
+CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 9441b17..f52f19b 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -5,9 +5,9 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -19,16 +19,11 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index d8ecde2..1ccec73 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -5,9 +5,8 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -16,18 +15,13 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
index cea91b6..f3c2c86 100644
--- a/configs/theadorable-x86-dfi-bt700_defconfig
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -1,4 +1,5 @@
CONFIG_X86=y
+CONFIG_MMC=y
CONFIG_VENDOR_DFI=y
CONFIG_DEFAULT_DEVICE_TREE="theadorable-x86-dfi-bt700"
CONFIG_TARGET_DFI_BT700=y
@@ -14,6 +15,7 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
@@ -40,6 +42,8 @@
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_NUVOTON_NCT6102D=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -55,7 +59,10 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index a918d1f..b97c128 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -1,11 +1,23 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_THEADORABLE=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -32,6 +44,7 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
@@ -42,3 +55,4 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO_MVEBU=y
+# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
index 8757c60..3c2e140 100644
--- a/configs/theadorable_defconfig
+++ b/configs/theadorable_defconfig
@@ -1,11 +1,23 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_THEADORABLE=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_MMC is not set
+CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
@@ -32,5 +44,6 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_VIDEO_MVEBU=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_REGEX=y
CONFIG_LIB_RAND=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 365627f..7e1b63b 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -1,9 +1,26 @@
CONFIG_ARM=y
CONFIG_TARGET_THUBAN=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
-CONFIG_SPL=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
@@ -25,10 +42,14 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_DFU_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index 8242103..196bf6f 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -1,7 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_THUNDERX_88XX=y
+CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core"
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ThunderX_88XX> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index 122dc3d..0297917 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -1,8 +1,21 @@
CONFIG_ARM=y
CONFIG_TARGET_TI814X_EVM=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 7df29cc..7d3a7d6 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -1,8 +1,20 @@
CONFIG_ARM=y
CONFIG_TARGET_TI816X_EVM=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot/ti816x# "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index c64acf2..478eba9 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -23,6 +23,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
new file mode 100644
index 0000000..e7b6c0f
--- /dev/null
+++ b/configs/topic_miami_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="topic"
+CONFIG_SYS_CONFIG_NAME="topic_miami"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
+CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="zynq-uboot> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+# CONFIG_NETDEVICES is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
new file mode 100644
index 0000000..2141949e
--- /dev/null
+++ b/configs/topic_miamiplus_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="topic"
+CONFIG_SYS_CONFIG_NAME="topic_miamiplus"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
+CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="zynq-uboot> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+# CONFIG_NETDEVICES is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
index 76a615c..8d8908d 100644
--- a/configs/tplink_wdr4300_defconfig
+++ b/configs/tplink_wdr4300_defconfig
@@ -5,6 +5,7 @@
CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_DISPLAY_CPUINFO=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMLS is not set
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index a827606..fd623e0 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -5,6 +5,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index 29c7ad9..6dc0941 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -6,6 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index 426b4c0..7b46177 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -6,6 +6,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index 63df5ef..07e0491 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -7,6 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index fa3c7d8..e5cfcc6 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -7,6 +7,7 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6s-wru4.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 1362ffb..9e88201 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -6,6 +6,8 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Trats2 # "
CONFIG_CMD_BOOTZ=y
@@ -29,6 +31,10 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_DFU_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 525bbef..92cf3f7 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -5,6 +5,8 @@
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Trats # "
CONFIG_CMD_BOOTZ=y
@@ -28,6 +30,10 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_DFU_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_S5P=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index 2482888..5bf0c9a 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -1,8 +1,9 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_TRICORDER=y
-CONFIG_SPL=y
CONFIG_BOOTDELAY=0
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
# CONFIG_CMD_IMI is not set
@@ -16,5 +17,6 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index b285a81..68d8fb6 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -1,9 +1,10 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_TRICORDER=y
-CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
CONFIG_BOOTDELAY=0
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
@@ -16,5 +17,6 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 201a870..a145ff8 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -4,9 +4,9 @@
CONFIG_TARGET_TRIMSLICE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -18,19 +18,17 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SFLASH=y
diff --git a/configs/ts4600_defconfig b/configs/ts4600_defconfig
new file mode 100644
index 0000000..1d3acd3
--- /dev/null
+++ b/configs/ts4600_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_TARGET_TS4600=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index a042cf2..c2b8ba8 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index f3f7857..83fb28e 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
@@ -15,5 +16,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_UBI=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 42b88fb..c92bfc8 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -1,9 +1,11 @@
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_TWISTER=y
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="twister => "
# CONFIG_CMD_IMLS is not set
@@ -19,6 +21,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 3c75706..a4a17c1 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -1,9 +1,18 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_UDOO=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
new file mode 100644
index 0000000..2788ac9
--- /dev/null
+++ b/configs/udoo_neo_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_UDOO_NEO=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
index 703d871..e939124 100644
--- a/configs/uniphier_ld11_defconfig
+++ b/configs/uniphier_ld11_defconfig
@@ -1,9 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD11=y
CONFIG_MICRO_SUPPORT_CARD=y
+# CONFIG_MMC is not set
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref"
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
@@ -23,10 +28,7 @@
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index c4a8547..449093a 100644
--- a/configs/uniphier_ld20_defconfig
+++ b/configs/uniphier_ld20_defconfig
@@ -1,9 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD20=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
@@ -24,8 +28,6 @@
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index e3ad160..8391a0a 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -1,9 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_XIMG is not set
@@ -29,10 +35,7 @@
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index a7dcc56..c8a7573 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -1,8 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref"
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_XIMG is not set
@@ -28,8 +34,8 @@
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
index 131c416..560b11b 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -1,9 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_XIMG is not set
@@ -29,8 +35,6 @@
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index 1c5cece..7e30acc 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -1,9 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_SLD3=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref"
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_XIMG is not set
@@ -30,7 +36,6 @@
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_USB=y
-CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index 916a9c6..8ec623b 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_USB_A9263=y
+# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 16f4293..ed16105 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -1,21 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_TARGET_USBARMORY=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig
index d22de9e..fb198b6 100644
--- a/configs/v38b_defconfig
+++ b/configs/v38b_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_V38B=y
CONFIG_BOOTDELAY=3
@@ -9,5 +10,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig
index 65d8d45..eb5a2e5 100644
--- a/configs/vct_platinum_defconfig
+++ b/configs/vct_platinum_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig
index 54f85ab..4896c6b 100644
--- a/configs/vct_platinum_onenand_defconfig
+++ b/configs/vct_platinum_onenand_defconfig
@@ -3,6 +3,7 @@
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_ONENAND=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -13,6 +14,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig
index 3306a45..50d2619 100644
--- a/configs/vct_platinum_onenand_small_defconfig
+++ b/configs/vct_platinum_onenand_small_defconfig
@@ -4,6 +4,7 @@
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
@@ -19,4 +20,5 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig
index 0647613..b22401c 100644
--- a/configs/vct_platinum_small_defconfig
+++ b/configs/vct_platinum_small_defconfig
@@ -3,6 +3,7 @@
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_SMALL_IMAGE=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig
index 1660c66..9778dc3 100644
--- a/configs/vct_platinumavc_defconfig
+++ b/configs/vct_platinumavc_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="VCT# "
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig
index 55dfd4c..ee3b400 100644
--- a/configs/vct_platinumavc_onenand_defconfig
+++ b/configs/vct_platinumavc_onenand_defconfig
@@ -3,6 +3,7 @@
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_ONENAND=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -11,4 +12,5 @@
# CONFIG_CMD_NET is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig
index 98b5ea2..8fb374d 100644
--- a/configs/vct_platinumavc_onenand_small_defconfig
+++ b/configs/vct_platinumavc_onenand_small_defconfig
@@ -4,6 +4,7 @@
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
@@ -19,4 +20,5 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig
index f4a9549..8046c32 100644
--- a/configs/vct_platinumavc_small_defconfig
+++ b/configs/vct_platinumavc_small_defconfig
@@ -3,6 +3,7 @@
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_SMALL_IMAGE=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig
index 192b739..f3ca7be 100644
--- a/configs/vct_premium_defconfig
+++ b/configs/vct_premium_defconfig
@@ -2,6 +2,7 @@
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig
index f5ed55a..e0c8a71 100644
--- a/configs/vct_premium_onenand_defconfig
+++ b/configs/vct_premium_onenand_defconfig
@@ -3,6 +3,7 @@
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_ONENAND=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -13,6 +14,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig
index ff5e7a6..023f22f 100644
--- a/configs/vct_premium_onenand_small_defconfig
+++ b/configs/vct_premium_onenand_small_defconfig
@@ -4,6 +4,7 @@
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
@@ -19,4 +20,5 @@
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig
index c601676..18d8b42 100644
--- a/configs/vct_premium_small_defconfig
+++ b/configs/vct_premium_small_defconfig
@@ -3,6 +3,7 @@
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_SMALL_IMAGE=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index faeb15c..9d1090b 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_VE8313=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index bd6c96c..8ff879f 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -4,9 +4,9 @@
CONFIG_TARGET_VENICE2=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -20,16 +20,14 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 8288c86..1f2809a 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -4,9 +4,7 @@
CONFIG_TARGET_VENTANA=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -15,18 +13,13 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -34,6 +27,10 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
+CONFIG_CONSOLE_SCROLL_LINES=10
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
index 15a7f6f..9fa1095 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_IDENT_STRING=" vexpress_aemv8a"
+# CONFIG_MMC is not set
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
@@ -15,13 +19,9 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index 6930c1c..ae0a691 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS64_JUNO=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_IDENT_STRING=" vexpress_aemv8a"
+# CONFIG_MMC is not set
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
@@ -15,13 +19,9 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index cb04d19..97505da 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_IDENT_STRING=" vexpress_aemv8a"
+# CONFIG_MMC is not set
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
@@ -15,13 +19,9 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index 2f141dd..2c004aa 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -1,9 +1,11 @@
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA15_TC2=y
-CONFIG_HUSH_PARSER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
@@ -14,13 +16,6 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index c495ee5..d2aec18 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -1,9 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA5X2=y
-CONFIG_HUSH_PARSER=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
@@ -14,13 +15,6 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index fcd6e26..d783e66 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -1,9 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA9X4=y
-CONFIG_HUSH_PARSER=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
@@ -14,13 +15,6 @@
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index d196738..5794c28 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -15,6 +15,7 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index faed3e0..60d0126 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -15,6 +15,7 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index eb2cd79..34a02bd 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -3,6 +3,7 @@
CONFIG_TARGET_VINCO=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="vinco => "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
new file mode 100644
index 0000000..9410703
--- /dev/null
+++ b/configs/vining_2000_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_SAMTEC_VINING_2000=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/samtec/vining_2000/imximage.cfg"
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PCI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index b23f235..4213e8a 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_VME8349=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig
index f927c4c..b19146b 100644
--- a/configs/walnut_defconfig
+++ b/configs/walnut_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index d465270..3054a3a 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -1,27 +1,33 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_WANDBOARD=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 4df7ea6..81acd8f 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -23,6 +23,7 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_DFU_MMC=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
@@ -34,3 +35,8 @@
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
+
+CONFIG_CMD_NET=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CMD_DHCP=y
+
diff --git a/configs/warp7_secure_defconfig b/configs/warp7_secure_defconfig
index 34fcdea..c12fc01 100644
--- a/configs/warp7_secure_defconfig
+++ b/configs/warp7_secure_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_TARGET_WARP7=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
@@ -23,14 +24,14 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_DFU_MMC=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
-CONFIG_USB_EHCI_HCD=y
-CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_OF_LIBFDT=y
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index f5c5600..08eb181 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -22,6 +22,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index 33aa977..b7c3ed9 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -4,9 +4,9 @@
CONFIG_TARGET_WHISTLER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Whistler) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -16,16 +16,11 @@
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index a2e5957..aa5d587 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_WOODBURN=y
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="woodburn U-Boot > "
CONFIG_CMD_MMC=y
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index 3b38130..085c2df 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -1,8 +1,17 @@
CONFIG_ARM=y
CONFIG_TARGET_WOODBURN_SD=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="woodburn U-Boot > "
CONFIG_CMD_MMC=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 0c2fb99..a705e8b 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -1,9 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_WORK_92105=y
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig
index 336d8e4..fa2eea0 100644
--- a/configs/wtk_defconfig
+++ b/configs/wtk_defconfig
@@ -1,13 +1,17 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U"
+CONFIG_SYS_EXTRA_OPTIONS="SHARP_LQ065T9DR51U"
CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_PCI is not set
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index dc4f42b..4b47fc6 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -1,7 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_X600=y
-CONFIG_SPL=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_IDENT_STRING="-SPEAr"
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="X600> "
CONFIG_AUTOBOOT_KEYED=y
@@ -18,6 +26,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index bc0828c..6f1aa69 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -1,8 +1,16 @@
CONFIG_ARM=y
CONFIG_TARGET_XFI3=y
-CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_VIDEO=y
CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig
index a17cd4f..f686fe9 100644
--- a/configs/xilinx-ppc405-generic_defconfig
+++ b/configs/xilinx-ppc405-generic_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC405_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic"
@@ -6,7 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="xlx-ppc405:/# "
# CONFIG_CMD_IMLS is not set
@@ -17,5 +20,6 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_XILINX_UARTLITE=y
diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig
index a9dd5a7..ef28222 100644
--- a/configs/xilinx-ppc440-generic_defconfig
+++ b/configs/xilinx-ppc440-generic_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
@@ -6,7 +7,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="board:/# "
CONFIG_CMD_ASKENV=y
@@ -17,5 +20,6 @@
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_NETCONSOLE=y
+# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_XILINX_UARTLITE=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 5f285d8..ef7bf8b 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -5,12 +5,16 @@
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
@@ -29,29 +33,26 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_BLK=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 059db84..0663e16 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -3,14 +3,18 @@
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ZYNQMP_USB=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
@@ -21,28 +25,23 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_BLK=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 0620646..d0b19f4 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -2,15 +2,23 @@
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
+# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_ZYNQMP_USB=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
+# CONFIG_MMC is not set
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
@@ -21,27 +29,21 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_BLK=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=y
CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 3ac22cb..7c75abb 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -1,15 +1,18 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
@@ -17,28 +20,22 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 0e82bf2..401c0d6 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -2,14 +2,18 @@
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
@@ -17,26 +21,20 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_DM_ETH=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 07e29fb..71ada10 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -3,14 +3,19 @@
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ZYNQMP_USB=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
@@ -21,26 +26,23 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_BLK=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 72679db..64aa32f 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -3,14 +3,19 @@
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ZYNQMP_USB=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
-CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
@@ -21,26 +26,23 @@
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_BLK=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig
index f023c73..ee98fc5 100644
--- a/configs/xpedite1000_defconfig
+++ b/configs/xpedite1000_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_XPEDITE1000=y
CONFIG_FIT=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index 2839bc6..731466e 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC86xx=y
CONFIG_TARGET_XPEDITE517X=y
CONFIG_FIT=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index c3b91f4..8763be8 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE520X=y
CONFIG_FIT=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index 5ababef..8e86a33 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE537X=y
CONFIG_FIT=y
@@ -14,5 +15,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index b6d3c8a..e186c7e 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE550X=y
CONFIG_FIT=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index bd6589f..a045918 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -3,6 +3,7 @@
CONFIG_TARGET_XPRESS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index 39406d1..2089a47 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -1,9 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_XPRESS=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig
index 8c061e9..c26c844 100644
--- a/configs/yellowstone_defconfig
+++ b/configs/yellowstone_defconfig
@@ -1,9 +1,11 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
@@ -14,5 +16,6 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig
index 1c94e7a..c77cd22 100644
--- a/configs/yosemite_defconfig
+++ b/configs/yosemite_defconfig
@@ -1,9 +1,11 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
@@ -17,6 +19,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig
index c261b32..ee04b00 100644
--- a/configs/yucca_defconfig
+++ b/configs/yucca_defconfig
@@ -1,8 +1,10 @@
CONFIG_PPC=y
+# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_YUCCA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
index cd5cd73..1b6493c 100644
--- a/configs/zc5202_defconfig
+++ b/configs/zc5202_defconfig
@@ -1,22 +1,29 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_ZC5202=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
+CONFIG_SPL=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
index 4ef7ca1..4e7385e 100644
--- a/configs/zc5601_defconfig
+++ b/configs/zc5601_defconfig
@@ -1,22 +1,28 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_ZC5601=y
-CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
+CONFIG_SPL=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig
index a776055..5846579 100644
--- a/configs/zipitz2_defconfig
+++ b/configs/zipitz2_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_ZIPITZ2=y
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
@@ -12,7 +14,9 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_PXA_SERIAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_LCD=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
index 70f47f2..5eef16a 100644
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@@ -1,6 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_ZMX25=y
+# CONFIG_MMC is not set
CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zmx25> "
CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 3bb090a..7ec5752 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,11 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
@@ -28,7 +30,10 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 5416141..d8c76a7 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
-CONFIG_SPL=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
@@ -24,7 +26,10 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 817ccc1..4c65231 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -2,11 +2,13 @@
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
@@ -30,7 +32,10 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index d9c1d64..935a9c9 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -2,11 +2,13 @@
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
@@ -30,7 +32,10 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 9664b92..16a14ae 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
@@ -28,6 +30,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index 98a348e..247fb6d 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,16 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
@@ -20,4 +24,5 @@
CONFIG_CMD_CACHE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_NAND_ZYNQ=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 00e2e6f..8e80a90 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,11 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_GPIO=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 1b78fdf..286f0bd 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,12 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 22d3419..6f8f3a6 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,11 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
@@ -28,7 +30,10 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 4b85cdb..6706324 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -2,11 +2,13 @@
CONFIG_SYS_CONFIG_NAME="zynq_zybo"
CONFIG_ARCH_ZYNQ=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
-CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
@@ -30,7 +32,10 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/disk/part.c b/disk/part.c
index 6a1c02d..4e37735 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -190,13 +190,13 @@
printf (" Supports 48-bit addressing\n");
#endif
#if defined(CONFIG_SYS_64BIT_LBA)
- printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%Ld x %ld)\n",
+ printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%llu x %lu)\n",
mb_quot, mb_rem,
gb_quot, gb_rem,
lba,
dev_desc->blksz);
#else
- printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n",
+ printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%lu x %lu)\n",
mb_quot, mb_rem,
gb_quot, gb_rem,
(ulong)lba,
@@ -615,3 +615,61 @@
free(dup_str);
return ret;
}
+
+int part_get_info_by_name(struct blk_desc *dev_desc, const char *name,
+ disk_partition_t *info)
+{
+ struct part_driver *first_drv =
+ ll_entry_start(struct part_driver, part_driver);
+ const int n_drvs = ll_entry_count(struct part_driver, part_driver);
+ struct part_driver *part_drv;
+
+ for (part_drv = first_drv; part_drv != first_drv + n_drvs; part_drv++) {
+ int ret;
+ int i;
+ for (i = 1; i < part_drv->max_entries; i++) {
+ ret = part_drv->get_info(dev_desc, i, info);
+ if (ret != 0) {
+ /* no more entries in table */
+ break;
+ }
+ if (strcmp(name, (const char *)info->name) == 0) {
+ /* matched */
+ return 0;
+ }
+ }
+ }
+ return -1;
+}
+
+void part_set_generic_name(const struct blk_desc *dev_desc,
+ int part_num, char *name)
+{
+ char *devtype;
+
+ switch (dev_desc->if_type) {
+ case IF_TYPE_IDE:
+ case IF_TYPE_SATA:
+ case IF_TYPE_ATAPI:
+ devtype = "hd";
+ break;
+ case IF_TYPE_SCSI:
+ devtype = "sd";
+ break;
+ case IF_TYPE_USB:
+ devtype = "usbd";
+ break;
+ case IF_TYPE_DOC:
+ devtype = "docd";
+ break;
+ case IF_TYPE_MMC:
+ case IF_TYPE_SD:
+ devtype = "mmcsd";
+ break;
+ default:
+ devtype = "xx";
+ break;
+ }
+
+ sprintf(name, "%s%c%d", devtype, 'a' + dev_desc->devnum, part_num);
+}
diff --git a/disk/part_amiga.c b/disk/part_amiga.c
index d4316b8..25fe56c 100644
--- a/disk/part_amiga.c
+++ b/disk/part_amiga.c
@@ -381,6 +381,7 @@
U_BOOT_PART_TYPE(amiga) = {
.name = "AMIGA",
.part_type = PART_TYPE_AMIGA,
+ .max_entries = AMIGA_ENTRY_NUMBERS,
.get_info = part_get_info_amiga,
.print = part_print_amiga,
.test = part_test_amiga,
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 511917a..ed78334 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -209,35 +209,8 @@
info->start = (lbaint_t)(ext_part_sector +
le32_to_int(pt->start4));
info->size = (lbaint_t)le32_to_int(pt->size4);
- switch(dev_desc->if_type) {
- case IF_TYPE_IDE:
- case IF_TYPE_SATA:
- case IF_TYPE_ATAPI:
- sprintf((char *)info->name, "hd%c%d",
- 'a' + dev_desc->devnum,
- part_num);
- break;
- case IF_TYPE_SCSI:
- sprintf((char *)info->name, "sd%c%d",
- 'a' + dev_desc->devnum,
- part_num);
- break;
- case IF_TYPE_USB:
- sprintf((char *)info->name, "usbd%c%d",
- 'a' + dev_desc->devnum,
- part_num);
- break;
- case IF_TYPE_DOC:
- sprintf((char *)info->name, "docd%c%d",
- 'a' + dev_desc->devnum,
- part_num);
- break;
- default:
- sprintf((char *)info->name, "xx%c%d",
- 'a' + dev_desc->devnum,
- part_num);
- break;
- }
+ part_set_generic_name(dev_desc, part_num,
+ (char *)info->name);
/* sprintf(info->type, "%d, pt->sys_ind); */
strcpy((char *)info->type, "U-Boot");
info->bootable = is_bootable(pt);
@@ -297,9 +270,30 @@
return part_get_info_extended(dev_desc, 0, 0, 1, part, info, 0);
}
+int is_valid_dos_buf(void *buf)
+{
+ return test_block_type(buf) == DOS_MBR ? 0 : -1;
+}
+
+int write_mbr_partition(struct blk_desc *dev_desc, void *buf)
+{
+ if (is_valid_dos_buf(buf))
+ return -1;
+
+ /* write MBR */
+ if (blk_dwrite(dev_desc, 0, 1, buf) != 1) {
+ printf("%s: failed writing '%s' (1 blks at 0x0)\n",
+ __func__, "MBR");
+ return 1;
+ }
+
+ return 0;
+}
+
U_BOOT_PART_TYPE(dos) = {
.name = "DOS",
.part_type = PART_TYPE_DOS,
+ .max_entries = DOS_ENTRY_NUMBERS,
.get_info = part_get_info_ptr(part_get_info_dos),
.print = part_print_ptr(part_print_dos),
.test = part_test_dos,
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 8d67c09..1924338 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -296,25 +296,6 @@
return 0;
}
-int part_get_info_efi_by_name(struct blk_desc *dev_desc,
- const char *name, disk_partition_t *info)
-{
- int ret;
- int i;
- for (i = 1; i < GPT_ENTRY_NUMBERS; i++) {
- ret = part_get_info_efi(dev_desc, i, info);
- if (ret != 0) {
- /* no more entries in table */
- return -1;
- }
- if (strcmp(name, (const char *)info->name) == 0) {
- /* matched */
- return 0;
- }
- }
- return -2;
-}
-
static int part_test_efi(struct blk_desc *dev_desc)
{
ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
@@ -958,6 +939,7 @@
U_BOOT_PART_TYPE(a_efi) = {
.name = "EFI",
.part_type = PART_TYPE_EFI,
+ .max_entries = GPT_ENTRY_NUMBERS,
.get_info = part_get_info_ptr(part_get_info_efi),
.print = part_print_ptr(part_print_efi),
.test = part_test_efi,
diff --git a/disk/part_iso.c b/disk/part_iso.c
index f9a741d..bb8ed65 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -137,30 +137,7 @@
entry_num=1;
offset=0x20;
strcpy((char *)info->type, "U-Boot");
- switch(dev_desc->if_type) {
- case IF_TYPE_IDE:
- case IF_TYPE_SATA:
- case IF_TYPE_ATAPI:
- sprintf ((char *)info->name, "hd%c%d",
- 'a' + dev_desc->devnum, part_num);
- break;
- case IF_TYPE_SCSI:
- sprintf ((char *)info->name, "sd%c%d",
- 'a' + dev_desc->devnum, part_num);
- break;
- case IF_TYPE_USB:
- sprintf ((char *)info->name, "usbd%c%d",
- 'a' + dev_desc->devnum, part_num);
- break;
- case IF_TYPE_DOC:
- sprintf ((char *)info->name, "docd%c%d",
- 'a' + dev_desc->devnum, part_num);
- break;
- default:
- sprintf ((char *)info->name, "xx%c%d",
- 'a' + dev_desc->devnum, part_num);
- break;
- }
+ part_set_generic_name(dev_desc, part_num, (char *)info->name);
/* the bootcatalog (including validation Entry) is limited to 2048Bytes
* (63 boot entries + validation entry) */
while(offset<2048) {
@@ -257,6 +234,7 @@
U_BOOT_PART_TYPE(iso) = {
.name = "ISO",
.part_type = PART_TYPE_ISO,
+ .max_entries = ISO_ENTRY_NUMBERS,
.get_info = part_get_info_iso,
.print = part_print_iso,
.test = part_test_iso,
diff --git a/disk/part_mac.c b/disk/part_mac.c
index 3952b8d..b6c082e 100644
--- a/disk/part_mac.c
+++ b/disk/part_mac.c
@@ -239,6 +239,7 @@
U_BOOT_PART_TYPE(mac) = {
.name = "MAC",
.part_type = PART_TYPE_MAC,
+ .max_entries = MAC_ENTRY_NUMBERS,
.get_info = part_get_info_mac,
.print = part_print_mac,
.test = part_test_mac,
diff --git a/doc/README.JFFS2 b/doc/README.JFFS2
index f0e9bc1..604e5b9 100644
--- a/doc/README.JFFS2
+++ b/doc/README.JFFS2
@@ -19,52 +19,15 @@
thus you should really consider if you can avoid it!
-There is two ways for JFFS2 to find the disk. The default way uses
-the flash_info structure to find the start of a JFFS2 disk (called
-partition in the code) and you can change where the partition is with
-two defines.
+There only one way for JFFS2 to find the disk. It uses the flash_info
+structure to find the start of a JFFS2 disk (called partition in the code)
+and you can change where the partition is with two defines.
CONFIG_SYS_JFFS2_FIRST_BANK
defined the first flash bank to use
CONFIG_SYS_JFFS2_FIRST_SECTOR
defines the first sector to use
-
-
-The second way is to define CONFIG_SYS_JFFS_CUSTOM_PART and implement the
-jffs2_part_info(int part_num) function in your board specific files.
-In this mode CONFIG_SYS_JFFS2_FIRST_BANK and CONFIG_SYS_JFFS2_FIRST_SECTOR is not
-used.
-
-The input is a partition number starting with 0.
-Return a pointer to struct part_info or NULL for error;
-
-Ex jffs2_part_info() for one partition.
----
-#if defined CONFIG_SYS_JFFS_CUSTOM_PART
-#include <jffs2/jffs2.h>
-
-static struct part_info part;
-
-struct part_info*
-jffs2_part_info(int part_num)
-{
- if(part_num==0){
- if(part.usr_priv==(void*)1)
- return ∂
-
- memset(&part, 0, sizeof(part));
- part.offset=(char*)0xFF800000;
- part.size=1024*1024*8;
-
- /* Mark the struct as ready */
- part.usr_priv=(void*)1;
-
- return ∂
- }
- return 0;
-}
-#endif
---
TODO.
diff --git a/doc/README.JFFS2_NAND b/doc/README.JFFS2_NAND
index 09788d5..92fa0f6 100644
--- a/doc/README.JFFS2_NAND
+++ b/doc/README.JFFS2_NAND
@@ -2,23 +2,7 @@
To enable, use the following #define in the board configuration file:
-#define CONFIG_JFFS2_NAND 1
+#define CONFIG_JFFS2_NAND
Configuration of partitions is similar to how this is done in U-Boot
-for JFFS2 on top NOR flash. If a single partition is used, it can be
-configured using the following #defines in the configuration file:
-
-#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
-#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
-#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */
-
-If more than a single partition is desired, the user can define a
-CONFIG_SYS_JFFS_CUSTOM_PART macro and implement a
-
- struct part_info* jffs2_part_info(int part_num)
-
-function in a board-specific module. An example of such function is
-available in common/cmd_jffs2.c
-
-The default configuration for the DAVE board has a single JFFS2
-partition of 2 MB size.
+for JFFS2 on top NOR flash.
diff --git a/doc/README.android-fastboot b/doc/README.android-fastboot
index ce12bc5..b8afa15 100644
--- a/doc/README.android-fastboot
+++ b/doc/README.android-fastboot
@@ -59,6 +59,44 @@
fastboot_partition_alias_<alias partition name>=<actual partition name>
Example: fastboot_partition_alias_boot=LNX
+Partition Names
+===============
+The Fastboot implementation in U-boot allows to write images into disk
+partitions (currently on eMMC). Target partitions are referred on the host
+computer by their names.
+
+For GPT/EFI the respective partition name is used.
+
+For MBR the partitions are referred by generic names according to the
+following schema:
+
+ <device type> <device index letter> <partition index>
+
+Example: hda3, sdb1, usbda1
+
+The device type is as follows:
+
+ * IDE, ATAPI and SATA disks: hd
+ * SCSI disks: sd
+ * USB media: usbd
+ * MMC and SD cards: mmcsd
+ * Disk on chip: docd
+ * other: xx
+
+The device index starts from 'a' and refers to the interface (e.g. USB
+controller, SD/MMC controller) or disk index. The partition index starts
+from 1 and describes the partition number on the particular device.
+
+Writing Partition Table
+=======================
+Fastboot also allows to write the partition table to the media. This can be
+done by writing the respective partition table image to a special target
+"gpt" or "mbr". These names can be customized by defining the following
+configuration options:
+
+CONFIG_FASTBOOT_GPT_NAME
+CONFIG_FASTBOOT_MBR_NAME
+
In Action
=========
Enter into fastboot by executing the fastboot command in u-boot and you
diff --git a/doc/README.arm64 b/doc/README.arm64
index f658fa2..b0bba0f 100644
--- a/doc/README.arm64
+++ b/doc/README.arm64
@@ -2,23 +2,31 @@
Summary
=======
-No hardware platform of arm64 is available now. The U-Boot is
-simulated on Foundation Model and Fast Model for ARMv8.
+The initial arm64 U-Boot port was developed before hardware was available,
+so the first supported platforms were the Foundation and Fast Model for ARMv8.
+These days U-Boot runs on a variety of 64-bit capable ARM hardware, from
+embedded development boards to servers.
Notes
=====
-1. Currenly, U-Boot run at the highest exception level processor
- supported and jump to EL2 or optionally EL1 before enter OS.
+1. U-Boot can run at any exception level it is entered in, it is
+ recommened to enter it in EL3 if U-Boot takes some responsibilities of a
+ classical firmware (like initial hardware setup, CPU errata workarounds
+ or SMP bringup). U-Boot can be entered in EL2 when its main purpose is
+ that of a boot loader. It can drop to lower exception levels before
+ entering the OS.
2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
is used to encode the initial addend of rela to u-boot.bin. After running,
the U-Boot will be relocated to destination again.
-3. Fdt should be placed at a 2-megabyte boundary and within the first 512
- megabytes from the start of the kernel image. So, fdt_high should be
- defined specially.
+3. Earlier Linux kernel versions required the FDT to be placed at a
+ 2 MB boundary and within the same 512 MB section as the kernel image,
+ resulting in fdt_high to be defined specially.
+ Since kernel version 4.2 Linux is more relaxed about the DT location, so it
+ can be placed anywhere in memory.
Please reference linux/Documentation/arm64/booting.txt for detail.
4. Spin-table is used to wake up secondary processors. One location
@@ -37,9 +45,8 @@
aarch32 specific codes.
-
-Contributor
-===========
+Contributors
+============
Tom Rini <trini@ti.com>
Scott Wood <scottwood@freescale.com>
York Sun <yorksun@freescale.com>
diff --git a/doc/README.at91-soc b/doc/README.at91-soc
deleted file mode 100644
index 9a9f74e..0000000
--- a/doc/README.at91-soc
+++ /dev/null
@@ -1,48 +0,0 @@
- New C structure AT91 SoC access
-=================================
-
-The goal
---------
-
-Currently the at91 arch uses hundreds of address defines and special
-at91_xxxx_write/read functions to access the SOC.
-The u-boot project perferred method is to access memory mapped hw
-regisister via a c structure.
-
-e.g. old
-
- *AT91C_PIOA_IDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
- *AT91C_PIOC_PUDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
- *AT91C_PIOC_PER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
- *AT91C_PIOC_OER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
- *AT91C_PIOC_PIO = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
-
- at91_sys_write(AT91_RSTC_CR,
- AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-
-e.g new
- pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
- writel(pin, &pio->pioa.idr);
- writel(pin, &pio->pioa.pudr);
- writel(pin, &pio->pioa.per);
- writel(pin, &pio->pioa.oer);
- writel(pin, &pio->pioa.sodr);
-
- writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST |
- AT91_RSTC_CR_PERRST, &rstc->cr);
-
-The method for updating
-------------------------
-
-1. add's the temporary CONFIG_AT91_LEGACY to all at91 board configs
-2. Display a compile time warning, if the board has not been converted
-3. add new structures for SoC access
-4. Convert arch, driver and boards file to new SoC
-5. remove legacy code, if all boards and drives are ready
-
-2013-10-30 Andreas Bießmann <andreas@biessmann.org>:
-
-The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but
-remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The
-AT91 spi driver has also some CONFIG_ATMEL_LEGACY stuff left, so another point
-to fix until this README can be removed.
diff --git a/doc/README.boston b/doc/README.boston
new file mode 100644
index 0000000..38f6710
--- /dev/null
+++ b/doc/README.boston
@@ -0,0 +1,58 @@
+MIPS Boston Development Board
+
+---------
+ About
+---------
+
+The MIPS Boston development board is built around an FPGA & 3 PCIe controllers,
+one of which is connected to an Intel EG20T Platform Controller Hub which
+provides most connectivity to the board. It is used during the development &
+testing of both new CPUs and the software support for them. It is essentially
+the successor of the older MIPS Malta board.
+
+--------
+ QEMU
+--------
+
+U-Boot can be run on a currently out-of-tree branch of QEMU with support for
+the Boston board added. This QEMU code can currently be found in the "boston"
+branch of git://git.linux-mips.org/pub/scm/paul/qemu.git and used like so:
+
+ $ git clone git://git.linux-mips.org/pub/scm/paul/qemu.git -b boston
+ $ cd qemu
+ $ ./configure --target-list=mips64el-softmmu
+ $ make
+ $ ./mips64el-softmmu/qemu-system-mips64el -M boston -m 2G \
+ -bios u-boot.bin -serial stdio
+
+Please note that QEMU will default to emulating the I6400 CPU which implements
+the MIPS64r6 ISA, and at the time of writing doesn't implement any earlier CPUs
+with support for the CPS features the Boston board relies upon. You will
+therefore need to configure U-Boot to build for MIPSr6 in order to obtain a
+binary that will work in QEMU.
+
+-------------
+ Toolchain
+-------------
+
+If building for MIPSr6 then you will need a toolchain including GCC 5.x or
+newer, or the Codescape toolchain available for download from Imagination
+Technologies:
+
+ http://codescape-mips-sdk.imgtec.com/components/toolchain/2015.06-05/
+
+The "IMG GNU Linux Toolchain" is capable of building for all current MIPS ISAs,
+architecture revisions & both endiannesses.
+
+--------
+ TODO
+--------
+
+ - AHCI support
+ - CPU driver
+ - Exception handling (+UHI?)
+ - Flash support
+ - IOCU support
+ - L2 cache support
+ - More general LCD display driver
+ - Multi-arch-variant multi-endian fat binary
diff --git a/doc/README.cfi b/doc/README.cfi
index 81e7cf1..ad52850 100644
--- a/doc/README.cfi
+++ b/doc/README.cfi
@@ -1,7 +1,7 @@
The common CFI driver provides this weak default implementation for
flash_cmd_reset():
-void __flash_cmd_reset(flash_info_t *info)
+static void __flash_cmd_reset(flash_info_t *info)
{
/*
* We do not yet know what kind of commandset to use, so we issue
@@ -9,22 +9,43 @@
* that AMD flash roms ignore the Intel command.
*/
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+ udelay(1);
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
}
void flash_cmd_reset(flash_info_t *info)
__attribute__((weak,alias("__flash_cmd_reset")));
+Some flash chips seem to have trouble with this reset sequence.
+In this case, board-specific code can override this weak default
+version with a board-specific function.
-Some flash chips seems to have trouble with this reset sequence. In this case
-the board specific code can override this weak default version with a board
-specific function. For example the digsy_mtc board equipped with the M29W128GH
-from Numonyx needs this version to function properly:
+At the time of writing, there are two boards that define their own
+routine for this.
+
+First, the digsy_mtc board equipped with the M29W128GH from Numonyx
+needs this version to function properly:
void flash_cmd_reset(flash_info_t *info)
{
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
}
+In addition, the t3corp board defines the routine thusly:
+
+void flash_cmd_reset(flash_info_t *info)
+{
+ /*
+ * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
+ * needs the Spansion type reset commands. The other flash chip
+ * is located behind a FPGA (Xilinx DS617) and needs the Intel type
+ * reset command.
+ */
+ if (info->start[0] == CONFIG_SYS_FLASH_BASE)
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+ else
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
+
see also:
http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html
diff --git a/doc/README.efi b/doc/README.efi
index 1fd3f00..66259f3 100644
--- a/doc/README.efi
+++ b/doc/README.efi
@@ -310,6 +310,20 @@
Simple use cases like "Plug this SD card into my ARM device and it just
boots into grub which boots into Linux", work very well.
+
+Running HelloWord.efi
+---------------------
+
+You can run a simple 'hello world' EFI program in U-Boot.
+Enable the option CONFIG_CMD_BOOTEFI_HELLO.
+
+Then you can boot into U-Boot and type:
+
+ > bootefi hello
+
+The 'hello world EFI' program will then run, print a message and exit.
+
+
Future work
-----------
diff --git a/doc/README.imx31 b/doc/README.imx31
deleted file mode 100644
index 91ef766..0000000
--- a/doc/README.imx31
+++ /dev/null
@@ -1,29 +0,0 @@
-U-Boot for Freescale i.MX31
-
-This file contains information for the port of U-Boot to the Freescale
-i.MX31 SoC.
-
-1. CONFIGURATION OPTIONS/SETTINGS
----------------------------------
-
-1.1 Configuration of MC13783 SPI bus
-------------------------------------
- The power management companion chip MC13783 is connected to the
- i.MX31 via an SPI bus. Use the following configuration options
- to setup the bus and chip select used for a particular board.
-
- CONFIG_MC13783_SPI_BUS -- defines the SPI bus the MC13783 is connected to.
- Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3.
- CONFIG_MC13783_SPI_CS -- define the chip select the MC13783 s connected to.
-
-1.2 Timer precision
--------------------
- CONFIG_MX31_TIMER_HIGH_PRECISION
-
- Enable higher precision timer. The low-precision timer
- (default) provides approximately 4% error, whereas the
- high-precision timer is about 0.4% accurate. The extra
- accuracy is achieved at the cost of higher computational
- overhead, which, in places where time is measured, should
- not be critical, so, it should be safe to enable this
- option.
diff --git a/doc/README.imx6 b/doc/README.imx6
index 1823fb2..0e00968 100644
--- a/doc/README.imx6
+++ b/doc/README.imx6
@@ -91,7 +91,7 @@
2. Using imx_usb_loader for first install with SPL
--------------------------------------------------
-imx_usb_loader is a very nice tool by BoundaryDevice that
+imx_usb_loader is a very nice tool by Boundary Devices that
allow to install U-Boot without a JTAG debugger, using
the USB boot mode as described in the manual. It is
a replacement for Freescale's MFGTOOLS.
@@ -138,3 +138,52 @@
The last "c" command tells kermit (from ckermit package in most distros)
to switch from command line mode to communication mode, and when the
script is finished, the U-Boot prompt is shown in the same shell.
+
+3. Using Secure Boot on i.MX6 machines with SPL support
+-------------------------------------------------------
+
+This version of U-Boot is able to build a signable version of the SPL
+as well as a signable version of the U-Boot image. The signature can
+be verified through High Assurance Boot (HAB).
+
+CONFIG_SECURE_BOOT is needed to build those two binaries.
+After building, you need to create a command sequence file and use
+Freescales Code Signing Tool to sign both binaries. After creation,
+the mkimage tool outputs the required information about the HAB Blocks
+parameter for the CSF. During the build, the information is preserved
+in log files named as the binaries. (SPL.log and u-boot-ivt.log).
+
+More information about the CSF and HAB can be found in the AN4581.
+https://cache.freescale.com/files/32bit/doc/app_note/AN4581.pdf
+
+We don't want to explain how to create a PKI tree or SRK table as
+this is well explained in the Application Note.
+
+Example Output of the SPL (imximage) creation:
+ Image Type: Freescale IMX Boot Image
+ Image Ver: 2 (i.MX53/6/7 compatible)
+ Mode: DCD
+ Data Size: 61440 Bytes = 60.00 kB = 0.06 MB
+ Load Address: 00907420
+ Entry Point: 00908000
+ HAB Blocks: 00907400 00000000 0000cc00
+
+Example Output of the u-boot-ivt.img (firmware_ivt) creation:
+ Image Name: U-Boot 2016.11-rc1-31589-g2a4411
+ Created: Sat Nov 5 21:53:28 2016
+ Image Type: ARM U-Boot Firmware with HABv4 IVT (uncompressed)
+ Data Size: 352192 Bytes = 343.94 kB = 0.34 MB
+ Load Address: 17800000
+ Entry Point: 00000000
+ HAB Blocks: 0x177fffc0 0x0000 0x00054020
+
+The CST (Code Signing Tool) can be downloaded from NXP.
+# Compile CSF and create signature
+./cst --o csf-u-boot.bin < command_sequence_uboot.csf
+./cst --o csf-SPL.bin < command_sequence_spl.csf
+# Append compiled CSF to Binary
+cat SPL csf-SPL.bin > SPL-signed
+cat u-boot-ivt.img csf-u-boot.bin > u-boot-signed.img
+
+These two signed binaries can be used on an i.MX6 in closed
+configuration when the according SRK Table Hash has been flashed.
\ No newline at end of file
diff --git a/doc/README.mpc83xxads b/doc/README.mpc83xxads
index 7a8b706..372fdd9 100644
--- a/doc/README.mpc83xxads
+++ b/doc/README.mpc83xxads
@@ -50,7 +50,6 @@
CONFIG_MPC83xx MPC83xx family
CONFIG_MPC8349 MPC8349 specific
- CONFIG_MPC8349ADS MPC8349ADS board specific
CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet
diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot
index d5043cc..e3f5804 100644
--- a/doc/README.mpc85xx-sd-spi-boot
+++ b/doc/README.mpc85xx-sd-spi-boot
@@ -57,23 +57,17 @@
P1022DS config_sram_p1022ds.dat
P2020DS config_sram_p2020ds.dat
-P2010DS config_sram_p2020ds.dat
P1020RDB config_ddr2_1g_p1020rdb_533M.dat
P1020RDB config_ddr2_1g_p1020rdb_667M.dat
P2020RDB config_ddr2_1g_p2020rdb_800M.dat
P2020RDB config_ddr2_1g_p2020rdb_667M.dat
P2020RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat
-P2010RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat
P1020RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1011RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1010RDB config_ddr3_1gb_p1010rdb_800M.dat
-P1014RDB config_ddr3_1gb_p1014rdb_800M.dat
P1021RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
-P1012RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1022DS config_ddr3_2gb_p1022ds.dat
-P1013DS config_ddr3_2gb_p1022ds.dat
P1024RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
-P1013RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
P1025RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
P1016RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
P1020UTM config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads
index ef92739..9b35fb2 100644
--- a/doc/README.mpc85xxads
+++ b/doc/README.mpc85xxads
@@ -136,9 +136,7 @@
CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc)
CONFIG_E500 BOOKE e500 family(Motorola)
CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
- CONFIG_MPC8540 MPC8540 specific
- CONFIG_MPC8540ADS MPC8540ADS board specific
- CONFIG_MPC8560ADS MPC8560ADS board specific
+ CONFIG_ARCH_MPC8540 MPC8540 specific
CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can
also manual config the DDR after undef this
diff --git a/doc/README.nand b/doc/README.nand
index f1c20ff..2295bb2 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -160,7 +160,7 @@
/*
* devnum is the device number to be used in nand commands
- * and in mtd->name. Must be less than CONFIG_SYS_NAND_MAX_DEVICE.
+ * and in mtd->name. Must be less than CONFIG_SYS_MAX_NAND_DEVICE.
*/
if (nand_register(devnum, mtd))
error out
diff --git a/doc/README.ramboot-ppc85xx b/doc/README.ramboot-ppc85xx
index 5cc546a..c9fef53 100644
--- a/doc/README.ramboot-ppc85xx
+++ b/doc/README.ramboot-ppc85xx
@@ -90,8 +90,8 @@
This will finally use the CONFIG_SYS_RAMBOOT.
-3. File name-> arch/powerpc/include/asm/config_mpc85xx.h
- In the section of the particular SOC, for example P1020,
+3. Change CONFIG_SYS_CCSRBAR_DEFAULT in menuconfig accordingly.
+ In the section of the particular SOC, for example P1020, pseudo code
#if defined(CONFIG_GO)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 69b926c..06ec80e 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -149,7 +149,6 @@
Using fastboot on rk3288
========================
-- Define GPT partition layout like kylin_rk3036(see include/configs/kylin_rk3036.h)
- Write GPT partition layout to mmc device which fastboot want to use it to
store the image
@@ -212,7 +211,6 @@
Err: serial@ff690000
=>
-
Future work
===========
@@ -298,6 +296,15 @@
In general all Rockchip drivers should use these features, with SPL-specific
modifications where required.
+GPT partition layout
+----------------------------
+
+Rockchip use a unified GPT partition layout in open source support.
+With this GPT partition layout, uboot can be compatilbe with other components,
+like miniloader, trusted-os, arm-trust-firmware.
+
+There are some documents about partitions in the links below.
+http://rockchip.wikidot.com/partitions
--
Simon Glass <sjg@chromium.org>
diff --git a/doc/README.ti-secure b/doc/README.ti-secure
index 54c996d..9b0fbf9 100644
--- a/doc/README.ti-secure
+++ b/doc/README.ti-secure
@@ -43,6 +43,38 @@
The script is basically the only required interface to the TI SECDEV
package for creating a bootable SPL image for secure TI devices.
+ Invoking the script for AM33xx Secure Devices
+ =============================================
+
+ create-boot-image.sh \
+ <IMAGE_FLAG> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR>
+
+ <IMAGE_FLAG> is a value that specifies the type of the image to
+ generate OR the action the image generation tool will take. Valid
+ values are:
+ SPI_X-LOADER - Generates an image for SPI flash (byte swapped)
+ X-LOADER - Generates an image for non-XIP flash
+ MLO - Generates an image for SD/MMC/eMMC media
+ 2ND - Generates an image for USB, UART and Ethernet
+ XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
+
+ <INPUT_FILE> is the full path and filename of the public world boot
+ loaderbinary file (depending on the boot media, this is usually
+ either u-boot-spl.bin or u-boot.bin).
+
+ <OUTPUT_FILE> is the full path and filename of the final secure
+ image. The output binary images should be used in place of the standard
+ non-secure binary images (see the platform-specific user's guides and
+ releases notes for how the non-secure images are typically used)
+ u-boot-spl_HS_SPI_X-LOADER - byte swapped boot image for SPI flash
+ u-boot-spl_HS_X-LOADER - boot image for NAND or SD/MMC/eMMC rawmode
+ u-boot-spl_HS_MLO - boot image for SD/MMC/eMMC media
+ u-boot-spl_HS_2ND - boot image for USB, UART and Ethernet
+ u-boot_HS_XIP_X-LOADER - boot image for NOR or QSPI Xip flash
+
+ <SPL_LOAD_ADDR> is the address at which SOC ROM should load the
+ <INPUT_FILE>
+
Invoking the script for AM43xx Secure Devices
=============================================
diff --git a/doc/README.uniphier b/doc/README.uniphier
index 49045a0..a42eaa9 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -2,74 +2,67 @@
==============================
-Tested toolchains
------------------
+Recommended toolchains
+----------------------
- (a) Ubuntu packages (CROSS_COMPILE=arm-linux-gnueabi-)
-
- If you are building U-Boot on Ubuntu, its standard package is recommended.
- You can install it as follows:
-
- $ sudo apt-get install gcc-arm-linux-gnueabi-
-
- (b) Linaro compilers (CROSS_COMPILE=arm-linux-gnueabihf-)
-
- You can download pre-built toolchains from:
+The UniPhir platform is well tested with Linaro toolchanis.
+You can download pre-built toolchains from:
http://www.linaro.org/downloads/
- (c) kernel.org compilers (CROSS_COMPILE=arm-unknown-linux-gnueabi-)
-
- You can download pre-built toolchains from:
-
- ftp://www.kernel.org/pub/tools/crosstool/files/bin/
-
Compile the source
------------------
-PH1-sLD3 reference board:
+sLD3 reference board:
$ make uniphier_sld3_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ $ make CROSS_COMPILE=arm-linux-gnueabihf-
-PH1-LD4 reference board:
+LD4 reference board:
$ make uniphier_ld4_sld8_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ $ make CROSS_COMPILE=arm-linux-gnueabihf-
-PH1-sLD8 reference board:
+sLD8 reference board:
$ make uniphier_ld4_sld8_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-sld8-ref
-PH1-Pro4 reference board:
+Pro4 reference board:
$ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ $ make CROSS_COMPILE=arm-linux-gnueabihf-
-PH1-Pro4 Ace board:
+Pro4 Ace board:
$ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-ace
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-ace
-PH1-Pro4 Sanji board:
+Pro4 Sanji board:
$ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-sanji
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-sanji
-PH1-Pro5 4KBOX Board:
+Pro5 4KBOX Board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro5-4kbox
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro5-4kbox
-ProXstream2 Gentil board:
+PXs2 Gentil board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-proxstream2-gentil
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-gentil
-ProXstream2 Vodka board:
+PXs2 Vodka board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ $ make CROSS_COMPILE=arm-linux-gnueabihf-
-PH1-LD6b reference board:
+LD6b reference board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld6b-ref
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref
-You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
-to use your favorite compiler.
+LD11 reference board:
+ $ make uniphier_ld11_defconfig
+ $ make CROSS_COMPILE=aarch64-linux-gnu-
+
+LD20 reference board:
+ $ make uniphier_ld20_defconfig
+ $ make CROSS_COMPILE=aarch64-linux-gnu-
+
+You may wish to change the "CROSS_COMPILE=..." to use your favorite compiler.
Burn U-Boot images to NAND
@@ -119,6 +112,9 @@
- ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)
shows the DDR PHY parameters set by the PHY training
+ - ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP)
+ shows the DDR Multi PHY parameters set by the PHY training
+
Supported devices
-----------------
@@ -179,4 +175,4 @@
--
Masahiro Yamada <yamada.masahiro@socionext.com>
-Feb. 2016
+Oct. 2016
diff --git a/doc/README.x86 b/doc/README.x86
index ba5bb99..a38cc1b 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -381,10 +381,17 @@
- Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
- Keep VESA framebuffer
+And include coreboot_fb.dtsi in your board's device tree source file, like:
+
+ /include/ "coreboot_fb.dtsi"
+
At present it seems that for Minnowboard Max, coreboot does not pass through
the video information correctly (it always says the resolution is 0x0). This
works correctly for link though.
+Note: coreboot framebuffer driver does not work on QEMU. The reason is unknown
+at this point. Patches are welcome if you figure out anything wrong.
+
Test with QEMU for bare mode
----------------------------
QEMU is a fancy emulator that can enable us to test U-Boot without access to
@@ -446,7 +453,7 @@
Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
'zboot' can be used to boot the kernel:
-=> zboot 02000000 - 04000000 1b1ab50
+=> zboot 01000000 - 04000000 1b1ab50
CPU Microcode
-------------
@@ -1070,7 +1077,6 @@
---------
- Audio
- Chrome OS verified boot
-- Support for CONFIG_EFI_LOADER
- Building U-Boot to run in 64-bit mode
References
diff --git a/doc/device-tree-bindings/gpio/bcm2835-gpio.txt b/doc/device-tree-bindings/gpio/bcm2835-gpio.txt
new file mode 100644
index 0000000..21e0610
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/bcm2835-gpio.txt
@@ -0,0 +1,5 @@
+* Broadcom BCM283x GPIO controller
+
+Required properties:
+- compatible: must be "brcm,bcm2835-gpio"
+- reg: exactly one register range with length 0xb4
diff --git a/doc/device-tree-bindings/mtd/spi/spi-flash.txt b/doc/device-tree-bindings/mtd/spi/spi-flash.txt
index 85522d8..3327890 100644
--- a/doc/device-tree-bindings/mtd/spi/spi-flash.txt
+++ b/doc/device-tree-bindings/mtd/spi/spi-flash.txt
@@ -6,7 +6,7 @@
- compatible : Should be the manufacturer and the name of the chip. Bear in
mind that the DT binding is not U-Boot-only, but in case of
U-Boot, see spi_flash_params_table table in
- drivers/mtd/spi/sf_params.c for the list of supported chips.
+ drivers/mtd/spi/spi_flash_ids.c for the list of supported chips.
- reg : Chip-Select number
- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
diff --git a/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt b/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt
new file mode 100644
index 0000000..d93f71c
--- /dev/null
+++ b/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt
@@ -0,0 +1,166 @@
+* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
+
+This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
+IP block. The IP supports multiple options for bus type, clocking and reset
+structure, and feature list. Consequently, a number of properties and list
+entries in properties are marked as optional, or only required in specific HW
+configurations.
+
+Required properties:
+- compatible: One of:
+ - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
+ Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
+ - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
+ Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
+ - "snps,dwc-qos-ethernet-4.10"
+ This combination is deprecated. It should be treated as equivalent to
+ "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
+ compatible with earlier revisions of this binding.
+- reg: Address and length of the register set for the device
+- clocks: Phandle and clock specifiers for each entry in clock-names, in the
+ same order. See ../clock/clock-bindings.txt.
+- clock-names: May contain any/all of the following depending on the IP
+ configuration, in any order:
+ - "tx"
+ The EQOS transmit path clock. The HW signal name is clk_tx_i.
+ In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
+ path. In other configurations, other clocks (such as tx_125, rmii) may
+ drive the PHY TX path.
+ - "rx"
+ The EQOS receive path clock. The HW signal name is clk_rx_i.
+ In some configurations (e.g. GMII/RGMII), this clock is derived from the
+ PHY's RX clock output. In other configurations, other clocks (such as
+ rx_125, rmii) may drive the EQOS RX path.
+ In cases where the PHY clock is directly fed into the EQOS receive path
+ without intervening logic, the DT need not represent this clock, since it
+ is assumed to be fully under the control of the PHY device/driver. In
+ cases where SoC integration adds additional logic to this path, such as a
+ SW-controlled clock gate, this clock should be represented in DT.
+ - "slave_bus"
+ The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
+ APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
+ buses).
+ - "master_bus"
+ The master bus interface clock. Only required in configurations that use a
+ separate clock for the master and slave bus interfaces. The HW signal name
+ is hclk_i (AHB) or aclk_i (AXI).
+ - "ptp_ref"
+ The PTP reference clock. The HW signal name is clk_ptp_ref_i.
+ - "phy_ref_clk"
+ This clock is deprecated and should not be used by new compatible values.
+ It is equivalent to "tx".
+ - "apb_pclk"
+ This clock is deprecated and should not be used by new compatible values.
+ It is equivalent to "slave_bus".
+
+ Note: Support for additional IP configurations may require adding the
+ following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i,
+ clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i.
+ Configurations exist where multiple similar clocks are used at once, e.g. all
+ of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to
+ extend the binding with a separate clock-names entry for each of those RX
+ clocks, rather than repurposing the existing "rx" clock-names entry as a
+ generic/logical clock in a similar fashion to "master_bus" and "slave_bus".
+ This will allow easy support for configurations that support multiple PHY
+ interfaces using a mux, and hence need to have explicit control over
+ specific RX clocks.
+
+ The following compatible values require the following set of clocks:
+ - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
+ - "slave_bus"
+ - "master_bus"
+ - "rx"
+ - "tx"
+ - "ptp_ref"
+ - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
+ - "slave_bus"
+ - "master_bus"
+ - "tx"
+ - "ptp_ref"
+ - "snps,dwc-qos-ethernet-4.10" (deprecated):
+ - "phy_ref_clk"
+ - "apb_clk"
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device
+- interrupts: Should contain the core's combined interrupt signal
+- phy-mode: See ethernet.txt file in the same directory
+- resets: Phandle and reset specifiers for each entry in reset-names, in the
+ same order. See ../reset/reset.txt.
+- reset-names: May contain any/all of the following depending on the IP
+ configuration, in any order:
+ - "eqos". The reset to the entire module. The HW signal name is hreset_n
+ (AHB) or aresetn_i (AXI).
+
+ The following compatible values require the following set of resets:
+ (the reset properties may be omitted if empty)
+ - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
+ - "eqos".
+ - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
+ - None.
+ - "snps,dwc-qos-ethernet-4.10" (deprecated):
+ - None.
+
+Optional properties:
+- dma-coherent: Present if dma operations are coherent
+- mac-address: See ethernet.txt in the same directory
+- local-mac-address: See ethernet.txt in the same directory
+- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.
+ See ../gpio/gpio.txt.
+- snps,en-lpi: If present it enables use of the AXI low-power interface
+- snps,write-requests: Number of write requests that the AXI port can issue.
+ It depends on the SoC configuration.
+- snps,read-requests: Number of read requests that the AXI port can issue.
+ It depends on the SoC configuration.
+- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
+ representing 4, then 8 etc.
+- snps,txpbl: DMA Programmable burst length for the TX DMA
+- snps,rxpbl: DMA Programmable burst length for the RX DMA
+- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
+ TX low-power mode.
+- phy-handle: See ethernet.txt file in the same directory
+- mdio device tree subnode: When the GMAC has a phy connected to its local
+ mdio, there must be device tree subnode with the following
+ required properties:
+ - compatible: Must be "snps,dwc-qos-ethernet-mdio".
+ - #address-cells: Must be <1>.
+ - #size-cells: Must be <0>.
+
+ For each phy on the mdio bus, there must be a node with the following
+ fields:
+
+ - reg: phy id used to communicate to phy.
+ - device_type: Must be "ethernet-phy".
+ - fixed-mode device tree subnode: see fixed-link.txt in the same directory
+
+Examples:
+ethernet2@40010000 {
+ clock-names = "phy_ref_clk", "apb_pclk";
+ clocks = <&clkc 17>, <&clkc 15>;
+ compatible = "snps,dwc-qos-ethernet-4.10";
+ interrupt-parent = <&intc>;
+ interrupts = <0x0 0x1e 0x4>;
+ reg = <0x40010000 0x4000>;
+ phy-handle = <&phy2>;
+ phy-mode = "gmii";
+ phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;
+
+ snps,en-tx-lpi-clockgating;
+ snps,en-lpi;
+ snps,write-requests = <2>;
+ snps,read-requests = <16>;
+ snps,burst-map = <0x7>;
+ snps,txpbl = <8>;
+ snps,rxpbl = <2>;
+
+ dma-coherent;
+
+ mdio {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ phy2: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ device_type = "ethernet-phy";
+ reg = <0x1>;
+ };
+ };
+};
diff --git a/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt
new file mode 100644
index 0000000..51f2f2c
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/marvell,armada-apn806-pinctrl.txt
@@ -0,0 +1,25 @@
+ Functions of Armada APN806 pin controller
+ Function 0x0 for any MPP ID activates GPIO pin mode
+----------------------------------------------------------------------
+MPP# 0x1 0x2 0x3 0x4
+----------------------------------------------------------------------
+0 SDIO_CLK - SPI0_CLK -
+1 SDIO_CMD - SPI0_MISO -
+2 SDIO_D[0] - SPI0_MOSI -
+3 SDIO_D[1] - SPI0_CS0n -
+4 SDIO_D[2] - I2C0_SDA SPI0_CS1n
+5 SDIO_D[3] - I2C0_SCK -
+6 SDIO_DS - - -
+7 SDIO_D[4] - UART1_RXD -
+8 SDIO_D[5] - UART1_TXD -
+9 SDIO_D[6] - SPI0_CS1n -
+10 SDIO_D[7] - - -
+11 - - UART0_TXD -
+12 SDIO_CARD_PW_OFF SDIO_HW_RST - -
+13 - - - -
+14 - - - -
+15 - - - -
+16 - - - -
+17 - - - -
+18 - - - -
+19 - - UART0_RXD -
diff --git a/doc/device-tree-bindings/pinctrl/marvell,armada-cp110-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,armada-cp110-pinctrl.txt
new file mode 100644
index 0000000..3adcf3a
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/marvell,armada-cp110-pinctrl.txt
@@ -0,0 +1,270 @@
+ Functions of Armada CP110 pin controller
+ Function 0x0 for any MPP ID activates GPIO pin mode
+ Function 0xc for any MPP ID activates DEBUG_BUS pin mode
+-------------------------------------------------------------------------------
+MPP# 0x1 0x2 0x3 0x4
+-------------------------------------------------------------------------------
+0 DEV_ALE[1] AU_I2SMCLK GE0_RXD[3] TDM_PCLK
+1 DEV_ALE[0] AU_I2SDO_SPDIFO GE0_RXD[2] TDM_DRX
+2 DEV_AD[15] AU_I2SEXTCLK GE0_RXD[1] TDM_DTX
+3 DEV_AD[14] AU_I2SLRCLK GE0_RXD[0] TDM_FSYNC
+4 DEV_AD[13] AU_I2SBCLK GE0_RXCTL TDM_RSTn
+5 DEV_AD[12] AU_I2SDI GE0_RXCLK TDM_INTn
+6 DEV_AD[11] - GE0_TXD[3] SPI0_CSn[2]
+7 DEV_AD[10] - GE0_TXD[2] SPI0_CSn[1]
+8 DEV_AD[9] - GE0_TXD[1] SPI0_CSn[0]
+9 DEV_AD[8] - GE0_TXD[0] SPI0_MOSI
+10 DEV_READYn - GE0_TXCTL SPI0_MISO
+11 DEV_WEn[1] - GE0_TXCLKOUT SPI0_CLK
+12 DEV_CLK_OUT NF_RBn[1] SPI1_CSn[1] GE0_RXCLK
+13 DEV_BURSTn NF_RBn[0] SPI1_MISO GE0_RXCTL
+14 DEV_BOOTCSn DEV_CSn[0] SPI1_CSn[0] SPI0_CSn[3]
+15 DEV_AD[7] - SPI1_MOSI -
+16 DEV_AD[6] - SPI1_CLK -
+17 DEV_AD[5] - - GE0_TXD[3]
+18 DEV_AD[4] - - GE0_TXD[2]
+19 DEV_AD[3] - - GE0_TXD[1]
+20 DEV_AD[2] - - GE0_TXD[0]
+21 DEV_AD[1] - - GE0_TXCTL
+22 DEV_AD[0] - - GE0_TXCLKOUT
+23 DEV_A[1] - - -
+24 DEV_A[0] - - -
+25 DEV_OEn - - - -
+26 DEV_WEn[0] - - -
+27 DEV_CSn[0] SPI1_MISO MSS_GPIO[4] GE0_RXD[3]
+28 DEV_CSn[1] SPI1_CSn[0] MSS_GPIO[5] GE0_RXD[2]
+29 DEV_CSn[2] SPI1_MOSI MSS_GPIO[6] GE0_RXD[1]
+30 DEV_CSn[3] SPI1_CLK MSS_GPIO[7] GE0_RXD[0]
+31 DEV_A[2] - MSS_GPIO[4] -
+32 MII_COL MII_TXERR MSS_SPI_MISO TDM_DRX
+33 MII_TXCLK SDIO_PWR1[0] MSS_SPI_CSn TDM_FSYNC
+34 MII_RXERR SDIO_PWR1[1] MSS_SPI_MOSI TDM_DTX
+35 SATA1_PRESENT_ACTIVEn TWSI1_SDA MSS_SPI_CLK TDM_PCLK
+36 SYNCE2_CLK TWSI1_SCK PTP_CLK SYNCE1_CLK
+37 UART2_RXD TWSI0_SCK PTP_PCLK_OUT TDM_INTn
+38 UART2_TXD TWSI0_SDA PTP_PULSE TDM_RSTn
+39 SDIO_WR_PROTECT - - AU_I2SBCLK PTP_CLK
+40 SDIO_PWR1[1] SYNCE1_CLK MSS_TWSI_SDA AU_I2SDO_SPDIFO
+41 SDIO_PWR1[0] SDIO_BUS_PWR MSS_TWSI_SCK AU_I2SLRCLK
+42 SDIO_V18_EN SDIO_WR_PROTECT SYNCE2_CLK AU_I2SMCLK
+43 SDIO_CARD_DETECT - SYNCE1_CLK AU_I2SEXTCLK
+44 GE1_TXD[2] - - -
+45 GE1_TXD[3] - - -
+46 GE1_TXD[1] - - -
+47 GE1_TXD[0] - - -
+48 GE1_TXCTL_MII_TXEN - - -
+49 GE1_TXCLKOUT MII_CRS - -
+50 GE1_RXCLK MSS_TWSI_SDA - -
+51 GE1_RXD[0] MSS_TWSI_SCK - -
+52 GE1_RXD[1] SYNCE1_CLK - SYNCE2_CLK
+53 GE1_RXD[2] - PTP_CLK -
+54 GE1_RXD[3] SYNCE2_CLK PTP_PCLK_OUT SYNCE1_CLK
+55 GE1_RXCTL_MII_RXDV - PTP_PULSE -
+56 - - - TDM_DRX
+57 - MSS_TWSI_SDA PTP_PCLK_OUT TDM_INTn
+58 - MSS_TWSI_SCK PTP_CLK TDM_RSTn
+59 MSS_GPIO[7] SYNCE2_CLK - TDM_FSYNC
+60 MSS_GPIO[6] - PTP_PULSE TDM_DTX
+61 MSS_GPIO[5] - PTP_CLK TDM_PCLK
+62 MSS_GPIO[4] SYNCE1_CLK PTP_PCLK_OUT -
+
+-------------------------------------------------------------------------------
+MPP# 0x5 0x6 0x7
+-------------------------------------------------------------------------------
+0 - PTP_PULSE MSS_TWSI_SDA
+1 - PTP_CLK MSS_TWSI_SCK
+2 MSS_UART_RXD PTP_PCLK_OUT TWSI1_SCK
+3 MSS_UART_TXD PCIe_RSTOUTn TWSI1_SDA
+4 MSS_UART_RXD UART1_CTS PCIe0_CLKREQ
+5 MSS_UART_TXD UART1_RTS PCIe1_CLKREQ
+6 AU_I2SEXTCLK SATA1_PRESENT_ACTIVEn PCIe2_CLKREQ
+7 SPI1_CSn[1] SATA0_PRESENT_ACTIVEn LED_DATA
+8 SPI1_CSn[0] UART0_CTS LED_STB
+9 SPI1_MOSI - PCIe_RSTOUTn
+10 SPI1_MISO UART0_CTS SATA1_PRESENT_ACTIVEn
+11 SPI1_CLK UART0_RTS LED_CLK
+12 - - -
+13 - - -
+14 AU_I2SEXTCLK SPI0_MISO SATA0_PRESENT_ACTIVEn
+15 - SPI0_MOSI -
+16 - - -
+17 - - -
+18 - - -
+19 - - -
+20 - - -
+21 - - -
+22 - - -
+23 AU_I2SMCLK - -
+24 AU_I2SLRCLK - -
+25 AU_I2SDO_SPDIFO - -
+26 AU_I2SBCLK - -
+27 SPI0_CSn[4] - -
+28 SPI0_CSn[5] PCIe2_CLKREQ PTP_PULSE
+29 SPI0_CSn[6] PCIe1_CLKREQ PTP_CLK
+30 SPI0_CSn[7] PCIe0_CLKREQ PTP_PCLK_OUT
+31 - PCIe_RSTOUTn -
+32 AU_I2SEXTCLK AU_I2SDI GE_MDIO
+33 AU_I2SMCLK SDIO_BUS_PWR -
+34 AU_I2SLRCLK SDIO_WR_PROTECT GE_MDC
+35 AU_I2SDO_SPDIFO SDIO_CARD_DETECT XG_MDIO
+36 AU_I2SBCLK SATA0_PRESENT_ACTIVEn XG_MDC
+37 MSS_TWSI_SCK SATA1_PRESENT_ACTIVEn GE_MDC
+38 MSS_TWSI_SDA SATA0_PRESENT_ACTIVEn GE_MDIO
+39 SPI0_CSn[1] - -
+40 PTP_PCLK_OUT SPI0_CLK UART1_TXD
+41 PTP_PULSE SPI0_MOSI UART1_RXD
+42 MSS_UART_TXD SPI0_MISO UART1_CTS
+43 MSS_UART_RXD SPI0_CSn[0] UART1_RTS
+44 - - UART0_RTS
+45 - - UART0_TXD
+46 - - UART1_RTS
+47 SPI1_CLK - UART1_TXD
+48 SPI1_MOSI - -
+49 SPI1_MISO - UART1_RXD
+50 SPI1_CSn[0] UART2_TXD UART0_RXD
+51 SPI1_CSn[1] UART2_RXD UART0_CTS
+52 SPI1_CSn[2] - UART1_CTS
+53 SPI1_CSn[3] - UART1_RXD
+54 - - -
+55 - - -
+56 AU_I2SDO_SPDIFO SPI0_CLK UART1_RXD
+57 AU_I2SBCLK SPI0_MOSI UART1_TXD
+58 AU_I2SDI SPI0_MISO UART1_CTS
+59 AU_I2SLRCLK SPI0_CSn[0] UART0_CTS
+60 AU_I2SMCLK SPI0_CSn[1] UART0_RTS
+61 AU_I2SEXTCLK SPI0_CSn[2] UART0_TXD
+62 SATA1_PRESENT_ACTIVEn SPI0_CSn[3] UART0_RXD
+
+-------------------------------------------------------------------------------
+MPP# 0x8 0x9 0xA
+-------------------------------------------------------------------------------
+0 UART0_RXD SATA0_PRESENT_ACTIVEn GE_MDIO
+1 UART0_TXD SATA1_PRESENT_ACTIVEn GE_MDC
+2 UART1_RXD SATA0_PRESENT_ACTIVEn XG_MDC
+3 UART1_TXD SATA1_PRESENT_ACTIVEn XG_MDIO
+4 UART3_RXD - GE_MDC
+5 UART3_TXD - GE_MDIO
+6 UART0_RXD PTP_PULSE -
+7 UART0_TXD PTP_CLK -
+8 UART2_RXD PTP_PCLK_OUT SYNCE1_CLK
+9 - - SYNCE2_CLK
+10 - - -
+11 UART2_TXD SATA0_PRESENT_ACTIVEn -
+12 - - -
+13 MSS_SPI_MISO - -
+14 MSS_SPI_CSn - -
+15 MSS_SPI_MOSI - -
+16 MSS_SPI_CLK - -
+17 - - -
+18 - - -
+19 - - -
+20 - - -
+21 - - -
+22 - - -
+23 - - -
+24 - - -
+25 - - -
+26 - - -
+27 GE_MDIO SATA0_PRESENT_ACTIVEn UART0_RTS
+28 GE_MDC SATA1_PRESENT_ACTIVEn UART0_CTS
+29 MSS_TWSI_SDA SATA0_PRESENT_ACTIVEn UART0_RXD
+30 MSS_TWSI_SCK SATA1_PRESENT_ACTIVEn UART0_TXD
+31 GE_MDC - -
+32 SDIO_V18_EN PCIe1_CLKREQ MSS_GPIO[0]
+33 XG_MDIO PCIe2_CLKREQ MSS_GPIO[1]
+34 - PCIe0_CLKREQ MSS_GPIO[2]
+35 GE_MDIO PCIe_RSTOUTn MSS_GPIO[3]
+36 GE_MDC PCIe2_CLKREQ MSS_GPIO[5]
+37 XG_MDC PCIe1_CLKREQ MSS_GPIO[6]
+38 XG_MDIO AU_I2SEXTCLK MSS_GPIO[7]
+39 SATA1_PRESENT_ACTIVEn MSS_GPIO[0]
+40 GE_MDIO SATA0_PRESENT_ACTIVEn MSS_GPIO[1]
+41 GE_MDC SATA1_PRESENT_ACTIVEn MSS_GPIO[2]
+42 XG_MDC SATA0_PRESENT_ACTIVEn MSS_GPIO[4]
+43 XG_MDIO SATA1_PRESENT_ACTIVEn MSS_GPIO[5]
+44 - - -
+45 - PCIe_RSTOUTn -
+46 - - -
+47 GE_MDC CLKOUT -
+48 XG_MDC - -
+49 GE_MDIO PCIe0_CLKREQ SDIO_V18_EN
+50 XG_MDIO - SDIO_PWR1[1]
+51 - - SDIO_PWR1[0]
+52 LED_CLK PCIe_RSTOUTn PCIe0_CLKREQ
+53 LED_STB - -
+54 LED_DATA - SDIO_HW_RST
+55 - - SDIO_LED
+56 - SATA1_PRESENT_ACTIVEn -
+57 - SATA0_PRESENT_ACTIVEn -
+58 LED_CLK - -
+59 LED_STB UART1_TXD -
+60 LED_DATA UART1_RXD -
+61 UART2_TXD SATA1_PRESENT_ACTIVEn GE_MDIO
+62 UART2_RXD SATA0_PRESENT_ACTIVEn GE_MDC
+
+-------------------------------------------------------------------------------
+MPP# 0xB 0xD 0xE
+-------------------------------------------------------------------------------
+0 - - -
+1 - - -
+2 - - -
+3 - - -
+4 - - -
+5 - - -
+6 - - -
+7 - - -
+8 - - -
+9 - - -
+10 - - -
+11 - CLKOUT_MPP_11 -
+12 - - -
+13 - - -
+14 - - -
+15 PTP_PULSE_CP2CP SAR_IN[5] -
+16 - SAR_IN[3] -
+17 - SAR_IN[6] -
+18 PTP_CLK_CP2CP SAR_IN[11] -
+19 WAKEUP_OUT_CP2CP SAR_IN[7] -
+20 - SAR_IN[9] -
+21 SEI_IN_CP2CP SAR_IN[8] -
+22 WAKEUP_IN_CP2CP SAR_IN[10] -
+23 LINK_RD_IN_CP2CP SAR_IN[4] -
+24 - - -
+25 - CLKOUT_MPP_25 -
+26 - SAR_IN[0] -
+27 REI_IN_CP2CP SAR_IN[1] -
+28 LED_DATA SAR_IN[2] -
+29 LED_STB AVS_FB_IN_CP2CP -
+30 LED_CLK SAR_IN[13] -
+31 - - -
+32 - SAR_CP2CP_OUT[0] -
+33 - SAR_CP2CP_OUT[1] -
+34 - SAR_CP2CP_OUT[2] -
+35 - SAR_CP2CP_OUT[3] -
+36 - CLKIN -
+37 LINK_RD_OUT_CP2CP SAR_CP2CP_OUT[4] -
+38 PTP_PULSE_CP2CP SAR_CP2CP_OUT[5] -
+39 - AVS_FB_OUT_CP2CP -
+40 - - -
+41 REI_OUT_CP2CP - -
+42 - SAR_CP2CP_OUT[9] -
+43 WAKEUP_OUT_CP2CP SAR_CP2CP_OUT[10] -
+44 PTP_CLK_CP2CP SAR_CP2CP_OUT[11] -
+45 - SAR_CP2CP_OUT[6] -
+46 - SAR_CP2CP_OUT[13] -
+47 - - -
+48 WAKEUP_IN_CP2CP SAR_CP2CP_OUT[7] -
+49 SEI_OUT_CP2CP SAR_CP2CP_OUT[8] -
+50 - - -
+51 - - -
+52 - - -
+53 SDIO_LED - -
+54 SDIO_WR_PROTECT - -
+55 SDIO_CARD_DETECT - -
+56 - - SDIO0_CLK
+57 - - SDIO0_CMD
+58 - - SDIO0_D[0]
+59 - - SDIO0_D[1]
+60 - - SDIO0_D[2]
+61 - - SDIO0_D[3]
+62 - - -
diff --git a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt
new file mode 100644
index 0000000..5f86c0a
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -0,0 +1,113 @@
+The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
+pins (mpp) to a specific function.
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for the pinctrl driver:
+- compatible: "marvell,mvebu-pinctrl",
+ "marvell,armada-ap806-pinctrl",
+ "marvell,a70x0-pinctrl",
+ "marvell,a80x0-cp0-pinctrl",
+ "marvell,a80x0-cp1-pinctrl"
+- bank-name: A string defining the pinc controller bank name
+- reg: A pair of values defining the pin controller base address
+ and the address space
+- pin-count: Numeric value defining the amount of multi purpose pins
+ included in this bank
+- max-func: Numeric value defining the maximum function value for
+ pins in this bank
+- pin-func: Array of pin function values for every pin in the bank.
+ When the function value for a specific pin equal 0xFF,
+ the pin configuration is skipped and a default function
+ value is used for this pin.
+
+The A8K is a hybrid SoC that contains several silicon dies interconnected in
+a single package. Each such die may have a separate pin controller.
+
+Example:
+/ {
+ ap806 {
+ config-space {
+ pinctl: pinctl@6F4000 {
+ compatible = "marvell,mvebu-pinctrl",
+ "marvell,armada-ap806-pinctrl";
+ bank-name ="apn-806";
+ reg = <0x6F4000 0x10>;
+ pin-count = <20>;
+ max-func = <3>;
+ /* MPP Bus:
+ * SPI0 [0-3]
+ * I2C0 [4-5]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 3 3 3 3 3 3 0 0 0 0
+ 0 3 0 0 0 0 0 0 0 3>;
+ };
+ };
+ };
+
+ cp110-master {
+ config-space {
+ cpm_pinctl: pinctl@44000 {
+ compatible = "marvell,mvebu-pinctrl",
+ "marvell,a70x0-pinctrl",
+ "marvell,a80x0-cp0-pinctrl";
+ bank-name ="cp0-110";
+ reg = <0x440000 0x20>;
+ pin-count = <63>;
+ max-func = <0xf>;
+ /* MPP Bus:
+ * [0-31] = 0xff: Keep default CP0_shared_pins:
+ * [11] CLKOUT_MPP_11 (out)
+ * [23] LINK_RD_IN_CP2CP (in)
+ * [25] CLKOUT_MPP_25 (out)
+ * [29] AVS_FB_IN_CP2CP (in)
+ * [32,34] SMI
+ * [31] GPIO: push button/Wake
+ * [35-36] GPIO
+ * [37-38] I2C
+ * [40-41] SATA[0/1]_PRESENT_ACTIVEn
+ * [42-43] XSMI
+ * [44-55] RGMII1
+ * [56-62] SD
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0 7 0 7 0 0 2 2 0
+ 0 0 8 8 1 1 1 1 1 1
+ 1 1 1 1 1 1 0xE 0xE 0xE 0xE
+ 0xE 0xE 0xE>;
+ };
+ };
+ };
+
+ cp110-slave {
+ config-space {
+ cps_pinctl: pinctl@44000 {
+ compatible = "marvell,mvebu-pinctrl",
+ "marvell,a80x0-cp1-pinctrl";
+ bank-name ="cp1-110";
+ reg = <0x440000 0x20>;
+ pin-count = <63>;
+ max-func = <0xf>;
+ /* MPP Bus:
+ * [0-11] RGMII0
+ * [27,31] GE_MDIO/MDC
+ * [32-62] = 0xff: Keep default CP1_shared_pins:
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
+ 0x3 0x3 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
+ 0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff>;
+ };
+ };
+ };
+}
diff --git a/doc/device-tree-bindings/pmic/rn5t567.txt b/doc/device-tree-bindings/pmic/rn5t567.txt
new file mode 100644
index 0000000..e9e6885
--- /dev/null
+++ b/doc/device-tree-bindings/pmic/rn5t567.txt
@@ -0,0 +1,17 @@
+Ricoh RN5T567 PMIC
+
+This file describes the binding info for the PMIC driver.
+
+Required properties:
+- compatible: "ricoh,rn5t567"
+- reg: depending on strapping, e.g. 0x33
+
+With those two properties, the PMIC device can be used to read/write
+registers.
+
+Example:
+
+rn5t567@33 {
+ compatible = "ricoh,rn5t567";
+ reg = <0x33>;
+};
diff --git a/doc/device-tree-bindings/regulator/fixed.txt b/doc/device-tree-bindings/regulator/fixed.txt
index 8a0d002..5fd9033 100644
--- a/doc/device-tree-bindings/regulator/fixed.txt
+++ b/doc/device-tree-bindings/regulator/fixed.txt
@@ -12,6 +12,9 @@
- gpio: GPIO to use for enable control
- startup-delay-us: startup time in microseconds
- regulator constraints (binding info: regulator.txt)
+- enable-active-high: Polarity of GPIO is Active high. If this property
+ is missing, the default assumed is Active low.
+
Other kernel-style properties, are currently not used.
@@ -36,4 +39,5 @@
regulator-max-microamp = <15000>;
regulator-always-on;
regulator-boot-on;
+ enable-active-high;
};
diff --git a/doc/device-tree-bindings/serial/bcm2835-aux-uart.txt b/doc/device-tree-bindings/serial/bcm2835-aux-uart.txt
new file mode 100644
index 0000000..75886e5
--- /dev/null
+++ b/doc/device-tree-bindings/serial/bcm2835-aux-uart.txt
@@ -0,0 +1,10 @@
+* BCM283x mini UART
+
+Required properties:
+- compatible: must be "brcm,bcm2835-aux-uart"
+- reg: exactly one register range with length 0x1000
+- clock: input clock frequency for the UART (used to calculate the baud
+ rate divisor)
+
+Optional properties:
+- skip-init: if present, the baud rate divisor is not changed
diff --git a/doc/device-tree-bindings/serial/mxc-serial.txt b/doc/device-tree-bindings/serial/mxc-serial.txt
new file mode 100644
index 0000000..ede92a4
--- /dev/null
+++ b/doc/device-tree-bindings/serial/mxc-serial.txt
@@ -0,0 +1,8 @@
+NXP i.MX (MXC) UART
+
+Required properties:
+- compatible: must be "fsl,imx7d-uart"
+- reg: start address and size of the registers
+
+Optional properties:
+- fsl,dte-mode: use DTE mode
diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt
index 61c27d1..017b1e2 100644
--- a/doc/device-tree-bindings/serial/pl01x.txt
+++ b/doc/device-tree-bindings/serial/pl01x.txt
@@ -5,3 +5,6 @@
- reg: exactly one register range with length 0x1000
- clock: input clock frequency for the UART (used to calculate the baud
rate divisor)
+
+Optional properties:
+- skip-init: if present, the baud rate divisor is not changed
diff --git a/doc/driver-model/i2c-howto.txt b/doc/driver-model/i2c-howto.txt
new file mode 100644
index 0000000..605d3ef
--- /dev/null
+++ b/doc/driver-model/i2c-howto.txt
@@ -0,0 +1,56 @@
+How to port a serial driver to driver model
+===========================================
+
+Over half of the I2C drivers have been converted as at November 2016. These
+ones remain:
+
+ adi_i2c
+ davinci_i2c
+ fti2c010
+ ihs_i2c
+ kona_i2c
+ lpc32xx_i2c
+ pca9564_i2c
+ ppc4xx_i2c
+ rcar_i2c
+ sh_i2c
+ sh_sh7734_i2c
+ soft_i2c
+ tsi108_i2c
+ zynq_i2c
+
+The deadline for this work is the end of June 2017. If no one steps
+forward to convert these, at some point there may come a patch to remove them!
+
+Here is a suggested approach for converting your I2C driver over to driver
+model. Please feel free to update this file with your ideas and suggestions.
+
+- #ifdef out all your own I2C driver code (#ifndef CONFIG_DM_I2C)
+- Define CONFIG_DM_I2C for your board, vendor or architecture
+- If the board does not already use driver model, you need CONFIG_DM also
+- Your board should then build, but will not work fully since there will be
+ no I2C driver
+- Add the U_BOOT_DRIVER piece at the end (e.g. copy tegra_i2c.c for example)
+- Add a private struct for the driver data - avoid using static variables
+- Implement each of the driver methods, perhaps by calling your old methods
+- You may need to adjust the function parameters so that the old and new
+ implementations can share most of the existing code
+- If you convert all existing users of the driver, remove the pre-driver-model
+ code
+
+In terms of patches a conversion series typically has these patches:
+- clean up / prepare the driver for conversion
+- add driver model code
+- convert at least one existing board to use driver model serial
+- (if no boards remain that don't use driver model) remove the old code
+
+This may be a good time to move your board to use device tree also. Mostly
+this involves these steps:
+
+- define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE
+- add your device tree files to arch/<arch>/dts
+- update the Makefile there
+- Add stdout-path to your /chosen device tree node if it is not already there
+- build and get u-boot-dtb.bin so you can test it
+- Your drivers can now use device tree
+- For device tree in SPL, define CONFIG_SPL_OF_CONTROL
diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt
index cddfb9f..a0df9a7 100644
--- a/doc/driver-model/serial-howto.txt
+++ b/doc/driver-model/serial-howto.txt
@@ -4,10 +4,8 @@
Almost all of the serial drivers have been converted as at January 2016. These
ones remain:
- mcfuart.c
serial_bfin.c
serial_pxa.c
- serial_s3c24x0.c
The deadline for this work was the end of January 2016. If no one steps
forward to convert these, at some point there may come a patch to remove them!
diff --git a/doc/git-mailrc b/doc/git-mailrc
index a14629c..b9b5929 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -19,12 +19,13 @@
alias angelo_ts Angelo Dureghello <angelo@sysam.it>
alias bmeng Bin Meng <bmeng.cn@gmail.com>
alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+alias dinh Dinh Nguyen <dinguyen@kernel.org>
alias galak Kumar Gala <galak@kernel.crashing.org>
alias hs Heiko Schocher <hs@denx.de>
alias ijc Ian Campbell <ijc+uboot@hellion.org.uk>
alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
alias jaehoon Jaehoon Chung <jh80.chung@samsung.com>
-alias jagan Jagan Teki <jteki@openedev.com>
+alias jagan Jagan Teki <jagan@openedev.com>
alias jasonjin Jason Jin <jason.jin@freescale.com>
alias jhersh Joe Hershberger <joe.hershberger@ni.com>
alias jwrdegoede Hans de Goede <hdegoede@redhat.com>
@@ -35,9 +36,9 @@
alias marex Marek Vasut <marex@denx.de>
alias masahiro Masahiro Yamada <yamada.masahiro@socionext.com>
alias mateusz Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+alias maxime Maxime Ripard <maxime.ripard@free-electrons.com>
alias monstr Michal Simek <monstr@monstr.eu>
alias prafulla Prafulla Wadaskar <prafulla@marvell.com>
-alias bobenstein Przemyslaw Marczak <p.marczak@samsung.com>
alias prom Minkyu Kang <mk7.kang@samsung.com>
alias rbohmer Remy Bohmer <linux@bohmer.net>
alias reinhardm Reinhard Meyer <u-boot@emk-elektronik.de>
@@ -69,8 +70,8 @@
alias s5pc samsung
alias samsung uboot, prom
alias snapdragon uboot, mateusz
-alias socfpga uboot, marex, Dinh Nguyen <dinguyen@opensource.altera.com>
-alias sunxi uboot, ijc, jwrdegoede
+alias socfpga uboot, marex, dinh
+alias sunxi uboot, jagan, maxime
alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
alias ti uboot, trini
@@ -135,4 +136,4 @@
alias video uboot, ag
alias patman uboot, sjg
alias buildman uboot, sjg
-alias pmic uboot, bobenstein
+alias pmic uboot, jaehoon
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index ffa7d60..3dcdced 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -70,7 +70,7 @@
Pass \-h as the compression to see the list of supported compression type.
.TP
-.BI "\-a [" "load addess" "]"
+.BI "\-a [" "load address" "]"
Set load address with a hex number.
.TP
@@ -138,6 +138,10 @@
creation.
.TP
+.BI "\-i [" "ramdisk_file" "]"
+Appends the ramdisk file to the FIT.
+
+.TP
.BI "\-k [" "key_directory" "]"
Specifies the directory containing keys to use for signing. This directory
should contain a private key file <name>.key for use with signing and a
diff --git a/doc/mvebu/armada-8k-memory.txt b/doc/mvebu/armada-8k-memory.txt
new file mode 100644
index 0000000..064518e
--- /dev/null
+++ b/doc/mvebu/armada-8k-memory.txt
@@ -0,0 +1,56 @@
+ Memory Layout on Armada-8k SoC's
+ ================================
+
+The below desribes the physical memory layout for Marvell's Armada-8k SoC's.
+
+This assumes that the SoC includes Dual CP configuration, in case the flavor is using
+a single CP configuration, then all secondary-CP mappings are invalid.
+
+All "Reserved" areas below, are kept for future usage.
+
+Start End Use
+--------------------------------------------------------------------------
+0x00000000 0xEFFFFFFF DRAM
+
+0xF0000000 0xF0FFFFFF AP Internal registers space
+
+0xF1000000 0xF1FFFFFF Reserved.
+
+0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers
+ space.
+
+0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers
+ space.
+
+0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space.
+
+0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space.
+
+0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space.
+
+0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space.
+
+0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space.
+
+0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space.
+
+0xF9030000 0xF9FFFFFF Reserved.
+
+0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space.
+
+0xFB000000 0xFBFFFFFF CP-1 / PCIe#1 Memory space.
+
+0xFC000000 0xFCFFFFFF CP-1 / PCIe#2 Memory space.
+
+0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space.
+
+0xFD010000 0xFD01FFFF CP-1 / PCIe#1 IO space.
+
+0xFD020000 0xFD02FFFF CP-1 / PCIe#2 IO space.
+
+0xFD030000 0xFFEFFFFF Reserved.
+
+0xFFF00000 0xFFFFFFFF Bootrom
+
+0x100000000 <DRAM Size>-1 DRAM
+
diff --git a/doc/mvebu/cmd/bubt.txt b/doc/mvebu/cmd/bubt.txt
new file mode 100644
index 0000000..6f9f525
--- /dev/null
+++ b/doc/mvebu/cmd/bubt.txt
@@ -0,0 +1,64 @@
+BUBT (Burn ATF) command
+--------------------------
+Bubt command is used to burn a new ATF image to flash device.
+
+The bubt command gets the following parameters: ATF file name, destination device and source device.
+bubt [file-name] [destination [source]]
+ - file-name Image file name to burn. default = flash-image.bin
+ - destination Flash to burn to [spi, nand, mmc]. default = active flash
+ - source Source to load image from [tftp, usb]. default = tftp
+
+Examples:
+ bubt - Burn flash-image.bin from tftp to active flash
+ bubt latest-spi.bin nand - Burn latest-spi.bin from tftp to NAND flash
+
+Notes:
+- For the TFTP interface set serverip and ipaddr.
+- To burn image to SD/eMMC device, the target is defined
+ by parameters CONFIG_SYS_MMC_ENV_DEV and CONFIG_SYS_MMC_ENV_PART.
+
+Bubt command details (burn image step by-step)
+----------------------------------------------
+This section describes bubt command flow:
+
+1. Fetch the requested ATF image from an available interface (USB/SD/SATA/XDB, etc.)
+ into the DRAM, and place it at <load_address>
+ Example: when using the FAT file system on USB flash device:
+ # usb reset
+ # fatls usb 0 (see files in device)
+ # fatload usb 0 <load_address> <file_name>
+
+2. Erase the target device:
+ - NAND: # nand erase 0 100000
+ - SPI: # sf probe 0
+ # sf erase 0 100000
+ - SD/eMMC: # mmc dev <dev_id> <boot_partition>
+
+Notes:
+- The eMMC has 2 boot partitions (BOOT0 and BOOT1) and a user data partition (DATA).
+ The boot partitions are numbered as partition 1 and 2 in MMC driver.
+ Number 0 is used for user data partition and should not be utilized for storing
+ boot images and U-Boot environment in RAW mode since it will break file system
+ structures usually located here.
+ The default boot partition is BOOT0. It is selected by the following parameter:
+ CONFIG_SYS_MMC_ENV_PART=1
+ Valid values for this parameter are 1 for BOOT0 and 2 for BOOT1.
+ Please never use partition number 0 here!
+ The eMMC has 2 boot partitions (BOOT0 and BOOT1) and a user data partition (DATA).
+ The boot partitions are numbered as partition 1 and 2 in MMC driver.
+ Number 0 is used for user data partition and should not be utilized for storing
+ boot images and U-Boot environment in RAW mode since it will break file system
+ structures usually located here.
+ The default boot partition is BOOT0. It is selected by the following parameter:
+ CONFIG_SYS_MMC_ENV_PART=1
+ Valid values for this parameter are 1 for BOOT0 and 2 for BOOT1.
+ Please never use partition number 0 here!
+- The partition number is ignored if the target device is SD card.
+- The boot image offset starts at block 0 for eMMC and block 1 for SD devices.
+ The block 0 on SD devices is left for MBR storage.
+
+3. Write the ATF image:
+ - NAND: # nand write <load_address> 0 <ATF Size>
+ - SPI: # sf write <load_address> 0 <ATF Size>
+ - SD/eMMC: # mmc write <load_address> [0|1] <ATF Size>/<block_size>
+
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 91aa89a..afff301 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -256,7 +256,9 @@
(component image node of a "fpga type").
- loadables : Unit name containing a list of additional binaries to be
loaded at their given locations. "loadables" is a comma-separated list
- of strings. U-Boot will load each binary at its given start-address.
+ of strings. U-Boot will load each binary at its given start-address and
+ may optionaly invoke additional post-processing steps on this binary based
+ on its component image node type.
The FDT blob is required to properly boot FDT based kernel, so the minimal
configuration for 2.6 FDT kernel is (kernel, fdt) pair.
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 4f84469..0e5d97d 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -16,10 +16,14 @@
source "drivers/demo/Kconfig"
+source "drivers/ddr/fsl/Kconfig"
+
source "drivers/dfu/Kconfig"
source "drivers/dma/Kconfig"
+source "drivers/fpga/Kconfig"
+
source "drivers/gpio/Kconfig"
source "drivers/hwmon/Kconfig"
@@ -46,6 +50,8 @@
source "drivers/pcmcia/Kconfig"
+source "drivers/phy/marvell/Kconfig"
+
source "drivers/pinctrl/Kconfig"
source "drivers/power/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 7861d34..c19fa14 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -33,15 +33,31 @@
obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/
obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
-obj-$(CONFIG_SPL_USBETH_SUPPORT) += usb/gadget/
+obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/
+obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/
+obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu/
obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/
obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/
obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+endif
-else
+ifdef CONFIG_TPL_BUILD
+
+obj-$(CONFIG_TPL_I2C_SUPPORT) += i2c/
+obj-$(CONFIG_TPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/
+obj-$(CONFIG_TPL_MMC_SUPPORT) += mmc/
+obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
+obj-$(CONFIG_TPL_NAND_SUPPORT) += mtd/nand/
+obj-$(CONFIG_TPL_SERIAL_SUPPORT) += serial/
+obj-$(CONFIG_TPL_SPI_FLASH_SUPPORT) += mtd/spi/
+obj-$(CONFIG_TPL_SPI_SUPPORT) += spi/
+
+endif
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-y += adc/
obj-$(CONFIG_DM_DEMO) += demo/
@@ -56,6 +72,7 @@
obj-y += pcmcia/
obj-y += dfu/
obj-$(CONFIG_X86) += pch/
+obj-y += phy/marvell/
obj-y += rtc/
obj-y += sound/
obj-y += spmi/
diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index 7717246..2d5b5dc 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -599,7 +599,7 @@
if (clean_up) {
BE_exit();
if (vga_info->BIOSImage &&
- (u32)(vga_info->BIOSImage) != 0xc0000)
+ (ulong)(vga_info->BIOSImage) != 0xc0000)
free(vga_info->BIOSImage);
free(vga_info);
vga_info = NULL;
diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c
index 5752fee..ba18135 100644
--- a/drivers/bios_emulator/x86emu/ops.c
+++ b/drivers/bios_emulator/x86emu/ops.c
@@ -41,7 +41,7 @@
* to the 256 byte-"opcodes" found on the 8086. The table which
* dispatches this is found in the files optab.[ch].
*
-* Each opcode proc has a comment preceeding it which gives it's table
+* Each opcode proc has a comment preceding it which gives it's table
* address. Several opcodes are missing (undefined) in the table.
*
* Each proc includes information for decoding (DECODE_PRINTF and
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 80eea84..88e66e2 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -1,6 +1,7 @@
config BLK
bool "Support block devices"
depends on DM
+ default y if DM_MMC
help
Enable support for block devices, such as SCSI, MMC and USB
flash sticks. These provide a block-level interface which permits
@@ -18,6 +19,15 @@
operations at present. The block device interface has not been converted
to driver model.
+config DM_SCSI
+ bool "Support SCSI controllers with driver model"
+ depends on BLK
+ help
+ This option enables the SCSI (Small Computer System Interface) uclass
+ which supports SCSI and SATA HDDs. For every device configuration
+ (IDs/LUNs) a block device is created with RAW read/write and
+ filesystem support.
+
config BLOCK_CACHE
bool "Use block device cache"
default n
@@ -26,3 +36,16 @@
This is most useful when accessing filesystems under U-Boot since
it will prevent repeated reads from directory structures and other
filesystem data structures.
+
+menu "SATA/SCSI device support"
+
+config SATA_CEVA
+ bool "Ceva Sata controller"
+ depends on AHCI
+ depends on DM_SCSI
+ help
+ This option enables Ceva Sata controller hard IP available on Xilinx
+ ZynqMP. Support up to 2 external devices. Complient with SATA 3.1 and
+ AHCI 1.3 specifications with hot-plug detect feature.
+
+endmenu
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 436b79f..a72feec 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -12,6 +12,7 @@
endif
obj-$(CONFIG_AHCI) += ahci-uclass.o
+obj-$(CONFIG_DM_SCSI) += scsi-uclass.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index e3e783a..3fa14a7 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -13,7 +13,7 @@
#include <dm.h>
#include <pci.h>
#include <asm/processor.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <memalign.h>
@@ -45,7 +45,7 @@
#define WAIT_MS_FLUSH 5000
#define WAIT_MS_LINKUP 200
-static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
+__weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
{
return base + 0x100 + (port * 0x80);
}
@@ -168,7 +168,7 @@
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
-#ifndef CONFIG_SCSI_AHCI_PLAT
+#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
# ifdef CONFIG_DM_PCI
struct udevice *dev = probe_ent->dev;
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
@@ -198,7 +198,7 @@
writel(cap_save, mmio + HOST_CAP);
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
-#ifndef CONFIG_SCSI_AHCI_PLAT
+#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
# ifdef CONFIG_DM_PCI
if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
u16 tmp16;
@@ -327,6 +327,7 @@
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
+#if !defined(CONFIG_DM_SCSI)
#ifndef CONFIG_SCSI_AHCI_PLAT
# ifdef CONFIG_DM_PCI
dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
@@ -338,14 +339,15 @@
pci_write_config_word(pdev, PCI_COMMAND, tmp16);
# endif
#endif
+#endif
return 0;
}
static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
-#ifndef CONFIG_SCSI_AHCI_PLAT
-# ifdef CONFIG_DM_PCI
+#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
+# if defined(CONFIG_DM_PCI)
struct udevice *dev = probe_ent->dev;
# else
pci_dev_t pdev = probe_ent->dev;
@@ -372,7 +374,7 @@
else
speed_s = "?";
-#ifdef CONFIG_SCSI_AHCI_PLAT
+#if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
scc_s = "SATA";
#else
# ifdef CONFIG_DM_PCI
@@ -424,13 +426,15 @@
}
#ifndef CONFIG_SCSI_AHCI_PLAT
-# ifdef CONFIG_DM_PCI
+# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
static int ahci_init_one(struct udevice *dev)
# else
static int ahci_init_one(pci_dev_t dev)
# endif
{
+#if !defined(CONFIG_DM_SCSI)
u16 vendor;
+#endif
int rc;
probe_ent = malloc(sizeof(struct ahci_probe_ent));
@@ -450,6 +454,7 @@
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
+#if !defined(CONFIG_DM_SCSI)
#ifdef CONFIG_DM_PCI
probe_ent->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
PCI_REGION_MEM);
@@ -473,6 +478,10 @@
if (vendor == 0x197b)
pci_write_config_byte(dev, 0x41, 0xa1);
#endif
+#else
+ struct scsi_platdata *plat = dev_get_platdata(dev);
+ probe_ent->mmio_base = (void *)plat->base;
+#endif
debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
/* initialize adapter */
@@ -954,14 +963,17 @@
}
-
+#if defined(CONFIG_DM_SCSI)
+void scsi_low_level_init(int busdevfunc, struct udevice *dev)
+#else
void scsi_low_level_init(int busdevfunc)
+#endif
{
int i;
u32 linkmap;
#ifndef CONFIG_SCSI_AHCI_PLAT
-# ifdef CONFIG_DM_PCI
+# if defined(CONFIG_DM_PCI)
struct udevice *dev;
int ret;
@@ -969,6 +981,8 @@
if (ret)
return;
ahci_init_one(dev);
+# elif defined(CONFIG_DM_SCSI)
+ ahci_init_one(dev);
# else
ahci_init_one(busdevfunc);
# endif
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 6ba1026..38cb938 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -26,7 +26,7 @@
static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
[IF_TYPE_IDE] = UCLASS_INVALID,
- [IF_TYPE_SCSI] = UCLASS_INVALID,
+ [IF_TYPE_SCSI] = UCLASS_SCSI,
[IF_TYPE_ATAPI] = UCLASS_INVALID,
[IF_TYPE_USB] = UCLASS_MASS_STORAGE,
[IF_TYPE_DOC] = UCLASS_INVALID,
@@ -156,6 +156,8 @@
if (ret)
return ret;
+ *descp = desc;
+ return 0;
} else if (desc->devnum > devnum) {
found_more = true;
}
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 6056fe5..c306e92 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -13,7 +13,7 @@
#include <common.h>
#include <malloc.h>
#include <linux/ctype.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <asm/arch/clock.h>
diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c
index 26569d7..36a1512 100644
--- a/drivers/block/pata_bfin.c
+++ b/drivers/block/pata_bfin.c
@@ -14,7 +14,7 @@
#include <asm/byteorder.h>
#include <asm/clock.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/pata.h>
#include <ata.h>
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index ac28f83..36c2ff3 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -12,7 +12,7 @@
#include <os.h>
#include <malloc.h>
#include <sandboxblockdev.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <dm/device-internal.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/block/sata_ceva.c b/drivers/block/sata_ceva.c
index dcc3b90..9b54664 100644
--- a/drivers/block/sata_ceva.c
+++ b/drivers/block/sata_ceva.c
@@ -5,6 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
#include <netdev.h>
#include <ahci.h>
#include <scsi.h>
@@ -73,10 +74,9 @@
#define DRV_NAME "ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2 1
-int init_sata(int dev)
+static int ceva_init_sata(ulong mmio)
{
ulong tmp;
- ulong mmio = ZYNQMP_SATA_BASEADDR;
int i;
/*
@@ -111,3 +111,40 @@
}
return 0;
}
+
+static int sata_ceva_probe(struct udevice *dev)
+{
+ struct scsi_platdata *plat = dev_get_platdata(dev);
+
+ ceva_init_sata(plat->base);
+ return 0;
+}
+
+static const struct udevice_id sata_ceva_ids[] = {
+ { .compatible = "ceva,ahci-1v84" },
+ { }
+};
+
+static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
+{
+ struct scsi_platdata *plat = dev_get_platdata(dev);
+
+ plat->base = dev_get_addr(dev);
+ if (plat->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Hardcode number for ceva sata controller */
+ plat->max_lun = 1; /* Actually two but untested */
+ plat->max_id = 2;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(ceva_host_blk) = {
+ .name = "ceva_sata",
+ .id = UCLASS_SCSI,
+ .of_match = sata_ceva_ids,
+ .probe = sata_ceva_probe,
+ .ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct scsi_platdata),
+};
diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c
index b14985a..a226ca2 100644
--- a/drivers/block/sata_dwc.c
+++ b/drivers/block/sata_dwc.c
@@ -26,7 +26,7 @@
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <ata.h>
diff --git a/drivers/block/sata_mv.c b/drivers/block/sata_mv.c
index 8824934..78e3da4 100644
--- a/drivers/block/sata_mv.c
+++ b/drivers/block/sata_mv.c
@@ -37,7 +37,7 @@
#include <libata.h>
#include <malloc.h>
#include <sata.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <linux/mbus.h>
@@ -572,6 +572,7 @@
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct crqb *req;
int slot;
+ u32 start;
if (len >= 64 * 1024) {
printf("We only support <64K transfers for now\n");
@@ -628,7 +629,9 @@
CRQB_SECTCOUNT_COUNT_EXP_MASK;
/* Flush data */
- flush_dcache_range((u32)req, (u32)req + sizeof(*req));
+ start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
+ flush_dcache_range(start,
+ start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
/* Trigger operation */
slot = get_next_reqip(port);
@@ -643,8 +646,11 @@
process_responses(port);
/* Invalidate data on read */
- if (buffer && len)
- invalidate_dcache_range((u32)buffer, (u32)buffer + len);
+ if (buffer && len) {
+ start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
+ invalidate_dcache_range(start,
+ start + ALIGN(len, ARCH_DMA_MINALIGN));
+ }
return len;
}
diff --git a/drivers/block/scsi-uclass.c b/drivers/block/scsi-uclass.c
new file mode 100644
index 0000000..05da6cd
--- /dev/null
+++ b/drivers/block/scsi-uclass.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016 Xilinx, Inc
+ * Written by Michal Simek
+ *
+ * Based on ahci-uclass.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <scsi.h>
+
+static int scsi_post_probe(struct udevice *dev)
+{
+ debug("%s: device %p\n", __func__, dev);
+ scsi_low_level_init(0, dev);
+ return 0;
+}
+
+UCLASS_DRIVER(scsi) = {
+ .id = UCLASS_SCSI,
+ .name = "scsi",
+ .post_probe = scsi_post_probe,
+};
diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c
index 5daede7..50043e6 100644
--- a/drivers/block/sym53c8xx.c
+++ b/drivers/block/sym53c8xx.c
@@ -284,9 +284,8 @@
*/
unsigned long swap_script(unsigned long val)
{
- unsigned long tmp;
- tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000);
- return tmp;
+ return ((val >> 24) & 0xff) | ((val >> 8) & 0xff00) |
+ ((val << 8) & 0xff0000) | ((val << 24) & 0xff000000);
}
diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c
index e0d2669..ad4cc56 100644
--- a/drivers/bootcount/bootcount_ram.c
+++ b/drivers/bootcount/bootcount_ram.c
@@ -37,7 +37,8 @@
/* Make sure the data is written to RAM */
flush_dcache_range((ulong)&save_addr[0],
- (ulong)&save_addr[REPEAT_PATTERN + OFFS_PATTERN]);
+ (((ulong)&save_addr[REPEAT_PATTERN + OFFS_PATTERN] &
+ ~(ARCH_DMA_MINALIGN - 1)) + ARCH_DMA_MINALIGN));
}
ulong bootcount_load(void)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 8f3b96a..c05ce2a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -20,6 +20,14 @@
setting up clocks within SPL, and allows the same drivers to be
used as U-Boot proper.
+config CLK_BOSTON
+ def_bool y if TARGET_BOSTON
+ depends on CLK
+ select REGMAP
+ select SYSCON
+ help
+ Enable this to support the clocks
+
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 778d748..40a5e8c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -15,3 +15,4 @@
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_AT91) += at91/
+obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig
index 10050d8..904ed48 100644
--- a/drivers/clk/at91/Kconfig
+++ b/drivers/clk/at91/Kconfig
@@ -1,6 +1,7 @@
config CLK_AT91
bool "AT91 clock drivers"
depends on CLK
+ select MISC
help
This option is used to enable the AT91 clock driver.
The driver supports the AT91 clock generator, including
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index f6164cc..d36f64f 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -17,15 +17,41 @@
#define GENERATED_SOURCE_MAX 6
#define GENERATED_MAX_DIV 255
-struct generated_clk_priv {
+/**
+ * generated_clk_bind() - for the generated clock driver
+ * Recursively bind its children as clk devices.
+ *
+ * @return: 0 on success, or negative error code on failure
+ */
+static int generated_clk_bind(struct udevice *dev)
+{
+ return at91_clk_sub_device_bind(dev, "generic-clk");
+}
+
+static const struct udevice_id generated_clk_match[] = {
+ { .compatible = "atmel,sama5d2-clk-generated" },
+ {}
+};
+
+U_BOOT_DRIVER(generated_clk) = {
+ .name = "generated-clk",
+ .id = UCLASS_MISC,
+ .of_match = generated_clk_match,
+ .bind = generated_clk_bind,
+};
+
+/*-------------------------------------------------------------*/
+
+struct generic_clk_priv {
u32 num_parents;
};
-static ulong generated_clk_get_rate(struct clk *clk)
+static ulong generic_clk_get_rate(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk parent;
+ ulong clk_rate;
u32 tmp, gckdiv;
u8 parent_id;
int ret;
@@ -36,18 +62,22 @@
AT91_PMC_PCR_GCKCSS_MASK;
gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
- ret = clk_get_by_index(clk->dev, parent_id, &parent);
+ ret = clk_get_by_index(dev_get_parent(clk->dev), parent_id, &parent);
if (ret)
return 0;
- return clk_get_rate(&parent) / (gckdiv + 1);
+ clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
+
+ clk_free(&parent);
+
+ return clk_rate;
}
-static ulong generated_clk_set_rate(struct clk *clk, ulong rate)
+static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
- struct generated_clk_priv *priv = dev_get_priv(clk->dev);
+ struct generic_clk_priv *priv = dev_get_priv(clk->dev);
struct clk parent, best_parent;
ulong tmp_rate, best_rate = rate, parent_rate;
int tmp_diff, best_diff = -1;
@@ -58,7 +88,7 @@
int ret;
for (i = 0; i < priv->num_parents; i++) {
- ret = clk_get_by_index(clk->dev, i, &parent);
+ ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
if (ret)
return ret;
@@ -111,18 +141,20 @@
return 0;
}
-static struct clk_ops generated_clk_ops = {
- .get_rate = generated_clk_get_rate,
- .set_rate = generated_clk_set_rate,
+static struct clk_ops generic_clk_ops = {
+ .of_xlate = at91_clk_of_xlate,
+ .get_rate = generic_clk_get_rate,
+ .set_rate = generic_clk_set_rate,
};
-static int generated_clk_ofdata_to_platdata(struct udevice *dev)
+static int generic_clk_ofdata_to_platdata(struct udevice *dev)
{
- struct generated_clk_priv *priv = dev_get_priv(dev);
+ struct generic_clk_priv *priv = dev_get_priv(dev);
u32 cells[GENERATED_SOURCE_MAX];
u32 num_parents;
- num_parents = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+ num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
+ dev_get_parent(dev)->of_offset,
"clocks", cells,
GENERATED_SOURCE_MAX);
@@ -134,29 +166,12 @@
return 0;
}
-static int generated_clk_bind(struct udevice *dev)
-{
- return at91_pmc_clk_node_bind(dev);
-}
-
-static int generated_clk_probe(struct udevice *dev)
-{
- return at91_pmc_core_probe(dev);
-}
-
-static const struct udevice_id generated_clk_match[] = {
- { .compatible = "atmel,sama5d2-clk-generated" },
- {}
-};
-
-U_BOOT_DRIVER(generated_clk) = {
- .name = "generated-clk",
+U_BOOT_DRIVER(generic_clk) = {
+ .name = "generic-clk",
.id = UCLASS_CLK,
- .of_match = generated_clk_match,
- .bind = generated_clk_bind,
- .probe = generated_clk_probe,
- .ofdata_to_platdata = generated_clk_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct generated_clk_priv),
+ .probe = at91_clk_probe,
+ .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct generic_clk_priv),
.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
- .ops = &generated_clk_ops,
+ .ops = &generic_clk_ops,
};
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
index 16688e9..e1ed447 100644
--- a/drivers/clk/at91/clk-peripheral.c
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -16,7 +16,32 @@
#define PERIPHERAL_ID_MAX 31
#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
-static int sam9x5_periph_clk_enable(struct clk *clk)
+/**
+ * sam9x5_periph_clk_bind() - for the periph clock driver
+ * Recursively bind its children as clk devices.
+ *
+ * @return: 0 on success, or negative error code on failure
+ */
+static int sam9x5_periph_clk_bind(struct udevice *dev)
+{
+ return at91_clk_sub_device_bind(dev, "periph-clk");
+}
+
+static const struct udevice_id sam9x5_periph_clk_match[] = {
+ { .compatible = "atmel,at91sam9x5-clk-peripheral" },
+ {}
+};
+
+U_BOOT_DRIVER(sam9x5_periph_clk) = {
+ .name = "sam9x5-periph-clk",
+ .id = UCLASS_MISC,
+ .of_match = sam9x5_periph_clk_match,
+ .bind = sam9x5_periph_clk_bind,
+};
+
+/*---------------------------------------------------------*/
+
+static int periph_clk_enable(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
@@ -30,31 +55,36 @@
return 0;
}
-static struct clk_ops sam9x5_periph_clk_ops = {
- .enable = sam9x5_periph_clk_enable,
-};
-
-static int sam9x5_periph_clk_bind(struct udevice *dev)
+static ulong periph_get_rate(struct clk *clk)
{
- return at91_pmc_clk_node_bind(dev);
+ struct udevice *dev;
+ struct clk clk_dev;
+ ulong clk_rate;
+ int ret;
+
+ dev = dev_get_parent(clk->dev);
+
+ ret = clk_get_by_index(dev, 0, &clk_dev);
+ if (ret)
+ return ret;
+
+ clk_rate = clk_get_rate(&clk_dev);
+
+ clk_free(&clk_dev);
+
+ return clk_rate;
}
-static int sam9x5_periph_clk_probe(struct udevice *dev)
-{
- return at91_pmc_core_probe(dev);
-}
-
-static const struct udevice_id sam9x5_periph_clk_match[] = {
- { .compatible = "atmel,at91sam9x5-clk-peripheral" },
- {}
+static struct clk_ops periph_clk_ops = {
+ .of_xlate = at91_clk_of_xlate,
+ .enable = periph_clk_enable,
+ .get_rate = periph_get_rate,
};
-U_BOOT_DRIVER(sam9x5_periph_clk) = {
- .name = "sam9x5-periph-clk",
- .id = UCLASS_CLK,
- .of_match = sam9x5_periph_clk_match,
- .bind = sam9x5_periph_clk_bind,
- .probe = sam9x5_periph_clk_probe,
+U_BOOT_DRIVER(clk_periph) = {
+ .name = "periph-clk",
+ .id = UCLASS_CLK,
.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
- .ops = &sam9x5_periph_clk_ops,
+ .probe = at91_clk_probe,
+ .ops = &periph_clk_ops,
};
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
index fa80bad..5b59a0c 100644
--- a/drivers/clk/at91/clk-system.c
+++ b/drivers/clk/at91/clk-system.c
@@ -14,12 +14,37 @@
#define SYSTEM_MAX_ID 31
+/**
+ * at91_system_clk_bind() - for the system clock driver
+ * Recursively bind its children as clk devices.
+ *
+ * @return: 0 on success, or negative error code on failure
+ */
+static int at91_system_clk_bind(struct udevice *dev)
+{
+ return at91_clk_sub_device_bind(dev, "system-clk");
+}
+
+static const struct udevice_id at91_system_clk_match[] = {
+ { .compatible = "atmel,at91rm9200-clk-system" },
+ {}
+};
+
+U_BOOT_DRIVER(at91_system_clk) = {
+ .name = "at91-system-clk",
+ .id = UCLASS_MISC,
+ .of_match = at91_system_clk_match,
+ .bind = at91_system_clk_bind,
+};
+
+/*----------------------------------------------------------*/
+
static inline int is_pck(int id)
{
return (id >= 8) && (id <= 15);
}
-static int at91_system_clk_enable(struct clk *clk)
+static int system_clk_enable(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
@@ -46,31 +71,15 @@
return 0;
}
-static struct clk_ops at91_system_clk_ops = {
- .enable = at91_system_clk_enable,
+static struct clk_ops system_clk_ops = {
+ .of_xlate = at91_clk_of_xlate,
+ .enable = system_clk_enable,
};
-static int at91_system_clk_bind(struct udevice *dev)
-{
- return at91_pmc_clk_node_bind(dev);
-}
-
-static int at91_system_clk_probe(struct udevice *dev)
-{
- return at91_pmc_core_probe(dev);
-}
-
-static const struct udevice_id at91_system_clk_match[] = {
- { .compatible = "atmel,at91rm9200-clk-system" },
- {}
-};
-
-U_BOOT_DRIVER(at91_system_clk) = {
- .name = "at91-system-clk",
+U_BOOT_DRIVER(system_clk) = {
+ .name = "system-clk",
.id = UCLASS_CLK,
- .of_match = at91_system_clk_match,
- .bind = at91_system_clk_bind,
- .probe = at91_system_clk_probe,
+ .probe = at91_clk_probe,
.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
- .ops = &at91_system_clk_ops,
+ .ops = &system_clk_ops,
};
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index a08d7e8..76ba91a 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -14,23 +14,19 @@
DECLARE_GLOBAL_DATA_PTR;
-static int at91_pmc_bind(struct udevice *dev)
-{
- return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
-}
-
static const struct udevice_id at91_pmc_match[] = {
{ .compatible = "atmel,sama5d2-pmc" },
{}
};
U_BOOT_DRIVER(at91_pmc) = {
- .name = "at91-pmc-core",
- .id = UCLASS_CLK,
+ .name = "at91-pmc",
+ .id = UCLASS_SIMPLE_BUS,
.of_match = at91_pmc_match,
- .bind = at91_pmc_bind,
};
+/*---------------------------------------------------------*/
+
int at91_pmc_core_probe(struct udevice *dev)
{
struct pmc_platdata *plat = dev_get_platdata(dev);
@@ -42,21 +38,41 @@
return 0;
}
-int at91_pmc_clk_node_bind(struct udevice *dev)
+/**
+ * at91_clk_sub_device_bind() - for the at91 clock driver
+ * Recursively bind its children as clk devices.
+ *
+ * @return: 0 on success, or negative error code on failure
+ */
+int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
{
const void *fdt = gd->fdt_blob;
int offset = dev->of_offset;
+ bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
int ret;
for (offset = fdt_first_subnode(fdt, offset);
offset > 0;
offset = fdt_next_subnode(fdt, offset)) {
+ if (pre_reloc_only &&
+ !fdt_getprop(fdt, offset, "u-boot,dm-pre-reloc", NULL))
+ continue;
+ /*
+ * If this node has "compatible" property, this is not
+ * a clock sub-node, but a normal device. skip.
+ */
+ fdt_get_property(fdt, offset, "compatible", &ret);
+ if (ret >= 0)
+ continue;
+
+ if (ret != -FDT_ERR_NOTFOUND)
+ return ret;
+
name = fdt_get_name(fdt, offset, NULL);
if (!name)
return -EINVAL;
-
- ret = device_bind_driver_to_node(dev, "clk", name,
+ ret = device_bind_driver_to_node(dev, drv_name, name,
offset, NULL);
if (ret)
return ret;
@@ -65,7 +81,33 @@
return 0;
}
-U_BOOT_DRIVER(clk_generic) = {
- .id = UCLASS_CLK,
- .name = "clk",
-};
+int at91_clk_of_xlate(struct clk *clk, struct fdtdec_phandle_args *args)
+{
+ int periph;
+
+ if (args->args_count) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1);
+ if (periph < 0)
+ return -EINVAL;
+
+ clk->id = periph;
+
+ return 0;
+}
+
+int at91_clk_probe(struct udevice *dev)
+{
+ struct udevice *dev_periph_container, *dev_pmc;
+ struct pmc_platdata *plat = dev_get_platdata(dev);
+
+ dev_periph_container = dev_get_parent(dev);
+ dev_pmc = dev_get_parent(dev_periph_container);
+
+ plat->reg_base = (struct at91_pmc *)dev_get_addr_ptr(dev_pmc);
+
+ return 0;
+}
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 5444c84..f222fce 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -13,6 +13,9 @@
};
int at91_pmc_core_probe(struct udevice *dev);
-int at91_pmc_clk_node_bind(struct udevice *dev);
+int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name);
+
+int at91_clk_of_xlate(struct clk *clk, struct fdtdec_phandle_args *args);
+int at91_clk_probe(struct udevice *dev);
#endif
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index b207611..6035e20 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -6,25 +6,18 @@
*/
#include <common.h>
-#include <clk-uclass.h>
#include <dm/device.h>
#include <dm/root.h>
DECLARE_GLOBAL_DATA_PTR;
-static int at91_sckc_clk_bind(struct udevice *dev)
-{
- return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
-}
-
-static const struct udevice_id at91_sckc_clk_match[] = {
+static const struct udevice_id at91_sckc_match[] = {
{ .compatible = "atmel,at91sam9x5-sckc" },
{}
};
-U_BOOT_DRIVER(at91_sckc_clk) = {
- .name = "at91_sckc_clk",
- .id = UCLASS_CLK,
- .of_match = at91_sckc_clk_match,
- .bind = at91_sckc_clk_bind,
+U_BOOT_DRIVER(at91_sckc) = {
+ .name = "at91-sckc",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = at91_sckc_match,
};
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 4d78e3f..153ceba 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -80,6 +80,9 @@
__func__, ret);
return ret;
}
+
+ clk->dev = dev_clk;
+
ops = clk_dev_ops(dev_clk);
if (ops->of_xlate)
@@ -101,10 +104,10 @@
debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
- index = fdt_find_string(gd->fdt_blob, dev->of_offset, "clock-names",
- name);
+ index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ "clock-names", name);
if (index < 0) {
- debug("fdt_find_string() failed: %d\n", index);
+ debug("fdt_stringlist_search() failed: %d\n", index);
return index;
}
diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c
new file mode 100644
index 0000000..78f1b75
--- /dev/null
+++ b/drivers/clk/clk_boston.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/boston-clock.h>
+#include <regmap.h>
+#include <syscon.h>
+
+struct clk_boston {
+ struct regmap *regmap;
+};
+
+#define BOSTON_PLAT_MMCMDIV 0x30
+# define BOSTON_PLAT_MMCMDIV_CLK0DIV (0xff << 0)
+# define BOSTON_PLAT_MMCMDIV_INPUT (0xff << 8)
+# define BOSTON_PLAT_MMCMDIV_MUL (0xff << 16)
+# define BOSTON_PLAT_MMCMDIV_CLK1DIV (0xff << 24)
+
+static uint32_t ext_field(uint32_t val, uint32_t mask)
+{
+ return (val & mask) >> (ffs(mask) - 1);
+}
+
+static ulong clk_boston_get_rate(struct clk *clk)
+{
+ struct clk_boston *state = dev_get_platdata(clk->dev);
+ uint32_t in_rate, mul, div;
+ uint mmcmdiv;
+ int err;
+
+ err = regmap_read(state->regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
+ if (err)
+ return 0;
+
+ in_rate = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT);
+ mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
+
+ switch (clk->id) {
+ case BOSTON_CLK_SYS:
+ div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
+ break;
+ case BOSTON_CLK_CPU:
+ div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
+ break;
+ default:
+ return 0;
+ }
+
+ return (in_rate * mul * 1000000) / div;
+}
+
+const struct clk_ops clk_boston_ops = {
+ .get_rate = clk_boston_get_rate,
+};
+
+static int clk_boston_ofdata_to_platdata(struct udevice *dev)
+{
+ struct clk_boston *state = dev_get_platdata(dev);
+ struct udevice *syscon;
+ int err;
+
+ err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "regmap", &syscon);
+ if (err) {
+ error("unable to find syscon device\n");
+ return err;
+ }
+
+ state->regmap = syscon_get_regmap(syscon);
+ if (!state->regmap) {
+ error("unable to find regmap\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id clk_boston_match[] = {
+ {
+ .compatible = "img,boston-clock",
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_boston) = {
+ .name = "boston_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_boston_match,
+ .ofdata_to_platdata = clk_boston_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct clk_boston),
+ .ops = &clk_boston_ops,
+};
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 8899b0c..7e3bf96 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -19,11 +19,6 @@
DECLARE_GLOBAL_DATA_PTR;
-struct rk3036_clk_priv {
- struct rk3036_cru *cru;
- ulong rate;
-};
-
enum {
VCO_MAX_HZ = 2400U * 1000000,
VCO_MIN_HZ = 600 * 1000000,
@@ -49,23 +44,6 @@
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
-void *rockchip_get_cru(void)
-{
- struct udevice *dev;
- fdt_addr_t addr;
- int ret;
-
- ret = uclass_get_device(UCLASS_CLK, 0, &dev);
- if (ret)
- return ERR_PTR(ret);
-
- addr = dev_get_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
- return ERR_PTR(-EINVAL);
-
- return (void *)addr;
-}
-
static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
{
@@ -371,7 +349,7 @@
{ }
};
-U_BOOT_DRIVER(clk_rk3036) = {
+U_BOOT_DRIVER(rockchip_rk3036_cru) = {
.name = "clk_rk3036",
.id = UCLASS_CLK,
.of_match = rk3036_clk_ids,
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index c07203d..d15504c 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -30,12 +30,6 @@
#endif
};
-struct rk3288_clk_priv {
- struct rk3288_grf *grf;
- struct rk3288_cru *cru;
- ulong rate;
-};
-
struct pll_div {
u32 nr;
u32 nf;
@@ -140,21 +134,6 @@
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
-void *rockchip_get_cru(void)
-{
- struct rk3288_clk_priv *priv;
- struct udevice *dev;
- int ret;
-
- ret = rockchip_get_clk(&dev);
- if (ret)
- return ERR_PTR(ret);
-
- priv = dev_get_priv(dev);
-
- return priv->cru;
-}
-
static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
{
@@ -695,6 +674,8 @@
case PCLK_I2C4:
case PCLK_I2C5:
return gclk_rate;
+ case PCLK_PWM:
+ return PD_BUS_PCLK_HZ;
default:
return -ENOENT;
}
@@ -710,6 +691,13 @@
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
switch (clk->id) {
+ case PLL_APLL:
+ /* We only support a fixed rate here */
+ if (rate != 1800000000)
+ return -EINVAL;
+ rk3288_clk_configure_cpu(priv->cru, priv->grf);
+ new_rate = rate;
+ break;
case CLK_DDR:
new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
break;
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 0b4ea82..2e87e4b 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -18,9 +18,8 @@
DECLARE_GLOBAL_DATA_PTR;
-struct rk3399_clk_priv {
- struct rk3399_cru *cru;
- ulong rate;
+struct rk3399_pmuclk_priv {
+ struct rk3399_pmucru *pmucru;
};
struct pll_div {
@@ -95,11 +94,11 @@
/* PMUCRU_CLKSEL_CON2 */
I2C_DIV_CON_MASK = 0x7f,
- I2C8_DIV_CON_SHIFT = 8,
- I2C0_DIV_CON_SHIFT = 0,
+ CLK_I2C8_DIV_CON_SHIFT = 8,
+ CLK_I2C0_DIV_CON_SHIFT = 0,
/* PMUCRU_CLKSEL_CON3 */
- I2C4_DIV_CON_SHIFT = 0,
+ CLK_I2C4_DIV_CON_SHIFT = 0,
/* CLKSEL_CON0 */
ACLKM_CORE_L_DIV_CON_SHIFT = 8,
@@ -507,6 +506,14 @@
(con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
I2C_DIV_CON_MASK;
+#define I2C_PMUCLK_REG_MASK(bus) \
+ (I2C_DIV_CON_MASK << \
+ CLK_I2C ##bus## _DIV_CON_SHIFT)
+
+#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
+ ((clk_div - 1) << \
+ CLK_I2C ##bus## _DIV_CON_SHIFT)
+
static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
{
u32 div, con;
@@ -754,7 +761,7 @@
break;
case DCLK_VOP0:
case DCLK_VOP1:
- rate = rk3399_vop_set_clk(priv->cru, clk->id, rate);
+ ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
break;
default:
return -ENOENT;
@@ -768,23 +775,6 @@
.set_rate = rk3399_clk_set_rate,
};
-void *rockchip_get_cru(void)
-{
- struct udevice *dev;
- fdt_addr_t *addr;
- int ret;
-
- ret = uclass_get_device_by_name(UCLASS_CLK, "clk_rk3399", &dev);
- if (ret)
- return ERR_PTR(ret);
-
- addr = dev_get_addr_ptr(dev);
- if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
- return ERR_PTR(-EINVAL);
-
- return addr;
-}
-
static int rk3399_clk_probe(struct udevice *dev)
{
struct rk3399_clk_priv *priv = dev_get_priv(dev);
@@ -830,3 +820,160 @@
.bind = rk3399_clk_bind,
.probe = rk3399_clk_probe,
};
+
+static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
+{
+ u32 div, con;
+
+ switch (clk_id) {
+ case SCLK_I2C0_PMU:
+ con = readl(&pmucru->pmucru_clksel[2]);
+ div = I2C_CLK_DIV_VALUE(con, 0);
+ break;
+ case SCLK_I2C4_PMU:
+ con = readl(&pmucru->pmucru_clksel[3]);
+ div = I2C_CLK_DIV_VALUE(con, 4);
+ break;
+ case SCLK_I2C8_PMU:
+ con = readl(&pmucru->pmucru_clksel[2]);
+ div = I2C_CLK_DIV_VALUE(con, 8);
+ break;
+ default:
+ printf("do not support this i2c bus\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(PPLL_HZ, div);
+}
+
+static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
+ uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = PPLL_HZ / hz;
+ assert(src_clk_div - 1 < 127);
+
+ switch (clk_id) {
+ case SCLK_I2C0_PMU:
+ rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
+ I2C_PMUCLK_REG_VALUE(0, src_clk_div));
+ break;
+ case SCLK_I2C4_PMU:
+ rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
+ I2C_PMUCLK_REG_VALUE(4, src_clk_div));
+ break;
+ case SCLK_I2C8_PMU:
+ rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
+ I2C_PMUCLK_REG_VALUE(8, src_clk_div));
+ break;
+ default:
+ printf("do not support this i2c bus\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(PPLL_HZ, src_clk_div);
+}
+
+static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
+{
+ u32 div, con;
+
+ /* PWM closk rate is same as pclk_pmu */
+ con = readl(&pmucru->pmucru_clksel[0]);
+ div = con & PMU_PCLK_DIV_CON_MASK;
+
+ return DIV_TO_RATE(PPLL_HZ, div);
+}
+
+static ulong rk3399_pmuclk_get_rate(struct clk *clk)
+{
+ struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ switch (clk->id) {
+ case PCLK_RKPWM_PMU:
+ rate = rk3399_pwm_get_clk(priv->pmucru);
+ break;
+ case SCLK_I2C0_PMU:
+ case SCLK_I2C4_PMU:
+ case SCLK_I2C8_PMU:
+ rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ switch (clk->id) {
+ case SCLK_I2C0_PMU:
+ case SCLK_I2C4_PMU:
+ case SCLK_I2C8_PMU:
+ ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+}
+
+static struct clk_ops rk3399_pmuclk_ops = {
+ .get_rate = rk3399_pmuclk_get_rate,
+ .set_rate = rk3399_pmuclk_set_rate,
+};
+
+static void pmuclk_init(struct rk3399_pmucru *pmucru)
+{
+ u32 pclk_div;
+
+ /* configure pmu pll(ppll) */
+ rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
+
+ /* configure pmu pclk */
+ pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
+ assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f);
+ rk_clrsetreg(&pmucru->pmucru_clksel[0],
+ PMU_PCLK_DIV_CON_MASK,
+ pclk_div << PMU_PCLK_DIV_CON_SHIFT);
+}
+
+static int rk3399_pmuclk_probe(struct udevice *dev)
+{
+ struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
+
+ pmuclk_init(priv->pmucru);
+
+ return 0;
+}
+
+static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
+
+ priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev);
+
+ return 0;
+}
+
+static const struct udevice_id rk3399_pmuclk_ids[] = {
+ { .compatible = "rockchip,rk3399-pmucru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
+ .name = "pmuclk_rk3399",
+ .id = UCLASS_CLK,
+ .of_match = rk3399_pmuclk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
+ .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
+ .ops = &rk3399_pmuclk_ops,
+ .probe = rk3399_pmuclk_probe,
+};
diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
index 659fe02..ce80b1f 100644
--- a/drivers/clk/tegra/Kconfig
+++ b/drivers/clk/tegra/Kconfig
@@ -1,3 +1,10 @@
+config TEGRA_CAR_CLOCK
+ bool "Enable Tegra CAR-based clock driver"
+ depends on TEGRA_CAR
+ help
+ Enable support for manipulating Tegra's on-SoC clocks via direct
+ register access to the Tegra CAR (Clock And Reset controller).
+
config TEGRA186_CLOCK
bool "Enable Tegra186 BPMP-based clock driver"
depends on TEGRA186_BPMP
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index f32998c..0fcc5205 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -2,4 +2,5 @@
#
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_TEGRA_CAR_CLOCK) += tegra-car-clk.o
obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o
diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c
new file mode 100644
index 0000000..b8a2c82
--- /dev/null
+++ b/drivers/clk/tegra/tegra-car-clk.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+
+static int tegra_car_clk_request(struct clk *clk)
+{
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ /*
+ * Note that the first PERIPH_ID_COUNT clock IDs (where the value
+ * varies per SoC) are the peripheral clocks, which use a numbering
+ * scheme that matches HW registers 1:1. There are other clock IDs
+ * beyond this that are assigned arbitrarily by the Tegra CAR DT
+ * binding. Due to the implementation of this driver, it currently
+ * only supports the peripheral IDs.
+ */
+ if (clk->id >= PERIPH_ID_COUNT)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int tegra_car_clk_free(struct clk *clk)
+{
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ return 0;
+}
+
+static ulong tegra_car_clk_get_rate(struct clk *clk)
+{
+ enum clock_id parent;
+
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ parent = clock_get_periph_parent(clk->id);
+ return clock_get_periph_rate(clk->id, parent);
+}
+
+static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
+{
+ enum clock_id parent;
+
+ debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
+ clk->dev, clk->id);
+
+ parent = clock_get_periph_parent(clk->id);
+ return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
+}
+
+static int tegra_car_clk_enable(struct clk *clk)
+{
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ clock_enable(clk->id);
+
+ return 0;
+}
+
+static int tegra_car_clk_disable(struct clk *clk)
+{
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ clock_disable(clk->id);
+
+ return 0;
+}
+
+static struct clk_ops tegra_car_clk_ops = {
+ .request = tegra_car_clk_request,
+ .free = tegra_car_clk_free,
+ .get_rate = tegra_car_clk_get_rate,
+ .set_rate = tegra_car_clk_set_rate,
+ .enable = tegra_car_clk_enable,
+ .disable = tegra_car_clk_disable,
+};
+
+static int tegra_car_clk_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(tegra_car_clk) = {
+ .name = "tegra_car_clk",
+ .id = UCLASS_CLK,
+ .probe = tegra_car_clk_probe,
+ .ops = &tegra_car_clk_ops,
+};
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index 0e90c01..da3e355 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -1,13 +1,10 @@
config CLK_UNIPHIER
- bool
+ bool "Clock driver for UniPhier SoCs"
+ depends on ARCH_UNIPHIER
select CLK
select SPL_CLK
-
-menu "Clock drivers for UniPhier SoCs"
- depends on CLK_UNIPHIER
-
-config CLK_UNIPHIER_MIO
- bool "Clock driver for UniPhier Media I/O block"
default y
-
-endmenu
+ help
+ Support for clock controllers on UniPhier SoCs.
+ Say Y if you want to control clocks provided by System Control
+ block, Media I/O block, Peripheral Block.
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index a3168f9..ed623aa 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -1,3 +1,2 @@
-obj-y += clk-uniphier-core.o
-
-obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o
+obj-y += clk-uniphier-core.o
+obj-y += clk-uniphier-mio.o
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index a91924e..8ad0242 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -6,119 +6,118 @@
*/
#include <common.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <clk-uclass.h>
-#include <dm/device.h>
#include "clk-uniphier.h"
+/**
+ * struct uniphier_clk_priv - private data for UniPhier clock driver
+ *
+ * @base: base address of the clock provider
+ * @data: SoC specific data
+ */
+struct uniphier_clk_priv {
+ void __iomem *base;
+ const struct uniphier_clk_data *data;
+};
+
static int uniphier_clk_enable(struct clk *clk)
{
struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
- struct uniphier_clk_gate_data *gate = priv->socdata->gate;
- unsigned int nr_gate = priv->socdata->nr_gate;
- void __iomem *reg;
- u32 mask, data, tmp;
- int i;
+ unsigned long id = clk->id;
+ const struct uniphier_clk_gate_data *p;
- for (i = 0; i < nr_gate; i++) {
- if (gate[i].index != clk->id)
+ for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) {
+ u32 val;
+
+ if (p->id != id)
continue;
- reg = priv->base + gate[i].reg;
- mask = gate[i].mask;
- data = gate[i].data & mask;
+ val = readl(priv->base + p->reg);
+ val |= BIT(p->bit);
+ writel(val, priv->base + p->reg);
- tmp = readl(reg);
- tmp &= ~mask;
- tmp |= data & mask;
- debug("%s: %p: %08x\n", __func__, reg, tmp);
- writel(tmp, reg);
+ return 0;
}
- return 0;
+ dev_err(priv->dev, "clk_id=%lu was not handled\n", id);
+ return -EINVAL;
+}
+
+static const struct uniphier_clk_mux_data *
+uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id)
+{
+ const struct uniphier_clk_mux_data *p;
+
+ for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) {
+ if (p->id == id)
+ return p;
+ }
+
+ return NULL;
}
static ulong uniphier_clk_get_rate(struct clk *clk)
{
struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
- struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
- unsigned int nr_rdata = priv->socdata->nr_rate;
- void __iomem *reg;
- u32 mask, data;
- ulong matched_rate = 0;
+ const struct uniphier_clk_mux_data *mux;
+ u32 val;
int i;
- for (i = 0; i < nr_rdata; i++) {
- if (rdata[i].index != clk->id)
- continue;
+ mux = uniphier_clk_get_mux_data(priv, clk->id);
+ if (!mux)
+ return 0;
- if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
- return rdata[i].rate;
+ if (!mux->nr_muxs) /* fixed-rate */
+ return mux->rates[0];
- reg = priv->base + rdata[i].reg;
- mask = rdata[i].mask;
- data = rdata[i].data & mask;
- if ((readl(reg) & mask) == data) {
- if (matched_rate && rdata[i].rate != matched_rate) {
- printf("failed to get clk rate for insane register values\n");
- return -EINVAL;
- }
- matched_rate = rdata[i].rate;
- }
- }
+ val = readl(priv->base + mux->reg);
- debug("%s: rate = %lu\n", __func__, matched_rate);
+ for (i = 0; i < mux->nr_muxs; i++)
+ if ((mux->masks[i] & val) == mux->vals[i])
+ return mux->rates[i];
- return matched_rate;
+ return -EINVAL;
}
static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
{
struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
- struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
- unsigned int nr_rdata = priv->socdata->nr_rate;
- void __iomem *reg;
- u32 mask, data, tmp;
+ const struct uniphier_clk_mux_data *mux;
+ u32 val;
+ int i, best_rate_id = -1;
ulong best_rate = 0;
- int i;
+
+ mux = uniphier_clk_get_mux_data(priv, clk->id);
+ if (!mux)
+ return 0;
+
+ if (!mux->nr_muxs) /* fixed-rate */
+ return mux->rates[0];
/* first, decide the best match rate */
- for (i = 0; i < nr_rdata; i++) {
- if (rdata[i].index != clk->id)
- continue;
-
- if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
- return 0;
-
- if (rdata[i].rate > best_rate && rdata[i].rate <= rate)
- best_rate = rdata[i].rate;
+ for (i = 0; i < mux->nr_muxs; i++) {
+ if (mux->rates[i] > best_rate && mux->rates[i] <= rate) {
+ best_rate = mux->rates[i];
+ best_rate_id = i;
+ }
}
- if (!best_rate)
- return -ENODEV;
+ if (best_rate_id < 0)
+ return -EINVAL;
+
+ val = readl(priv->base + mux->reg);
+ val &= ~mux->masks[best_rate_id];
+ val |= mux->vals[best_rate_id];
+ writel(val, priv->base + mux->reg);
debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
rate, best_rate);
- /* second, really set registers */
- for (i = 0; i < nr_rdata; i++) {
- if (rdata[i].index != clk->id || rdata[i].rate != best_rate)
- continue;
-
- reg = priv->base + rdata[i].reg;
- mask = rdata[i].mask;
- data = rdata[i].data & mask;
-
- tmp = readl(reg);
- tmp &= ~mask;
- tmp |= data;
- debug("%s: %p: %08x\n", __func__, reg, tmp);
- writel(tmp, reg);
- }
-
return best_rate;
}
@@ -128,12 +127,12 @@
.set_rate = uniphier_clk_set_rate,
};
-int uniphier_clk_probe(struct udevice *dev)
+static int uniphier_clk_probe(struct udevice *dev)
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = dev_get_addr(dev);
+ addr = dev_get_addr(dev->parent);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
@@ -141,7 +140,52 @@
if (!priv->base)
return -ENOMEM;
- priv->socdata = (void *)dev_get_driver_data(dev);
+ priv->data = (void *)dev_get_driver_data(dev);
return 0;
}
+
+static const struct udevice_id uniphier_clk_match[] = {
+ {
+ .compatible = "socionext,uniphier-sld3-mio-clock",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld4-mio-clock",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-mio-clock",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-mio-clock",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-mio-clock",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-mio-clock",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-mio-clock",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-mio-clock",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_clk) = {
+ .name = "uniphier-clk",
+ .id = UCLASS_CLK,
+ .of_match = uniphier_clk_match,
+ .probe = uniphier_clk_probe,
+ .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
+ .ops = &uniphier_clk_ops,
+};
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index 2eea5eb..18e6856 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -5,181 +5,81 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <dm/device.h>
-
#include "clk-uniphier.h"
-#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \
- { \
- .index = (idx), \
- .reg = 0x20 + 0x200 * (ch), \
- .mask = 0x00000100, \
- .data = 0x00000100, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x110 + 0x200 * (ch), \
- .mask = 0x00000001, \
- .data = 0x00000001, \
+#define UNIPHIER_MIO_CLK_SD_GATE(id, ch) \
+ UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 8)
+
+#define UNIPHIER_MIO_CLK_USB2(id, ch) \
+ UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 28)
+
+#define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \
+ UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 29)
+
+#define UNIPHIER_MIO_CLK_DMAC(id) \
+ UNIPHIER_CLK_GATE((id), 0x20, 25)
+
+#define UNIPHIER_MIO_CLK_SD_MUX(_id, ch) \
+ { \
+ .id = (_id), \
+ .nr_muxs = 8, \
+ .reg = 0x30 + 0x200 * (ch), \
+ .masks = { \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ }, \
+ .vals = { \
+ 0x00000000, \
+ 0x00010000, \
+ 0x00020000, \
+ 0x00030000, \
+ 0x00001000, \
+ 0x00001100, \
+ 0x00001200, \
+ 0x00001300, \
+ }, \
+ .rates = { \
+ 44444444, \
+ 33333333, \
+ 50000000, \
+ 66666666, \
+ 100000000, \
+ 40000000, \
+ 25000000, \
+ 22222222, \
+ }, \
}
-#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00000000, \
- .rate = 44444444, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00010000, \
- .rate = 33333333, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00020000, \
- .rate = 50000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00020000, \
- .rate = 66666666, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001000, \
- .rate = 100000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001100, \
- .rate = 40000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001200, \
- .rate = 25000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001300, \
- .rate = 22222222, \
- }
-
-#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \
- { \
- .index = (idx), \
- .reg = 0x20 + 0x200 * (ch), \
- .mask = 0x30000000, \
- .data = 0x30000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x110 + 0x200 * (ch), \
- .mask = 0x01000000, \
- .data = 0x01000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x114 + 0x200 * (ch), \
- .mask = 0x00000001, \
- .data = 0x00000001, \
- }
-
-#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \
- { \
- .index = (idx), \
- .reg = 0x20, \
- .mask = 0x02000000, \
- .data = 0x02000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x110, \
- .mask = 0x00020000, \
- .data = 0x00020000, \
- }
-
-static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
- UNIPHIER_MIO_CLK_GATE_SD(0, 0),
- UNIPHIER_MIO_CLK_GATE_SD(1, 1),
- UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */
- UNIPHIER_MIO_CLK_GATE_USB(0, 3),
- UNIPHIER_MIO_CLK_GATE_USB(1, 4),
- UNIPHIER_MIO_CLK_GATE_USB(2, 5),
- UNIPHIER_MIO_CLK_GATE_DMAC(6),
- UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */
+static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
+ UNIPHIER_MIO_CLK_SD_GATE(0, 0),
+ UNIPHIER_MIO_CLK_SD_GATE(1, 1),
+ UNIPHIER_MIO_CLK_SD_GATE(2, 2), /* for PH1-Pro4 only */
+ UNIPHIER_MIO_CLK_DMAC(7),
+ UNIPHIER_MIO_CLK_USB2(8, 0),
+ UNIPHIER_MIO_CLK_USB2(9, 1),
+ UNIPHIER_MIO_CLK_USB2(10, 2),
+ UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */
+ UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
+ UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
+ UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
+ UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */
+ UNIPHIER_CLK_END
};
-static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
- UNIPHIER_MIO_CLK_RATE_SD(0, 0),
- UNIPHIER_MIO_CLK_RATE_SD(1, 1),
- UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */
+static const struct uniphier_clk_mux_data uniphier_mio_clk_mux[] = {
+ UNIPHIER_MIO_CLK_SD_MUX(0, 0),
+ UNIPHIER_MIO_CLK_SD_MUX(1, 1),
+ UNIPHIER_MIO_CLK_SD_MUX(2, 2), /* for PH1-Pro4 only */
+ UNIPHIER_CLK_END
};
-static struct uniphier_clk_soc_data uniphier_mio_clk_data = {
+const struct uniphier_clk_data uniphier_mio_clk_data = {
.gate = uniphier_mio_clk_gate,
- .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
- .rate = uniphier_mio_clk_rate,
- .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
-};
-
-static const struct udevice_id uniphier_mio_clk_match[] = {
- {
- .compatible = "socionext,ph1-sld3-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-ld4-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-pro4-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-sld8-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-pro5-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,proxstream2-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-ld11-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-ld20-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(uniphier_mio_clk) = {
- .name = "uniphier-mio-clk",
- .id = UCLASS_CLK,
- .of_match = uniphier_mio_clk_match,
- .probe = uniphier_clk_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
- .ops = &uniphier_clk_ops,
+ .mux = uniphier_mio_clk_mux,
};
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
index 18aa888..f9a560e 100644
--- a/drivers/clk/uniphier/clk-uniphier.h
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -10,48 +10,46 @@
#include <linux/kernel.h>
+#define UNIPHIER_CLK_MAX_NR_MUXS 8
+
struct uniphier_clk_gate_data {
- int index;
+ unsigned int id;
unsigned int reg;
- u32 mask;
- u32 data;
+ unsigned int bit;
};
-struct uniphier_clk_rate_data {
- int index;
+struct uniphier_clk_mux_data {
+ unsigned int id;
+ unsigned int nr_muxs;
unsigned int reg;
-#define UNIPHIER_CLK_RATE_IS_FIXED UINT_MAX
- u32 mask;
- u32 data;
- unsigned long rate;
+ unsigned int masks[UNIPHIER_CLK_MAX_NR_MUXS];
+ unsigned int vals[UNIPHIER_CLK_MAX_NR_MUXS];
+ unsigned long rates[UNIPHIER_CLK_MAX_NR_MUXS];
};
-struct uniphier_clk_soc_data {
- struct uniphier_clk_gate_data *gate;
- unsigned int nr_gate;
- struct uniphier_clk_rate_data *rate;
- unsigned int nr_rate;
+struct uniphier_clk_data {
+ const struct uniphier_clk_gate_data *gate;
+ const struct uniphier_clk_mux_data *mux;
};
-#define UNIPHIER_CLK_FIXED_RATE(i, f) \
+#define UNIPHIER_CLK_ID_END (unsigned int)(-1)
+
+#define UNIPHIER_CLK_END \
+ { .id = UNIPHIER_CLK_ID_END }
+
+#define UNIPHIER_CLK_GATE(_id, _reg, _bit) \
{ \
- .index = i, \
- .reg = UNIPHIER_CLK_RATE_IS_FIXED, \
- .rate = f, \
+ .id = (_id), \
+ .reg = (_reg), \
+ .bit = (_bit), \
}
-/**
- * struct uniphier_clk_priv - private data for UniPhier clock driver
- *
- * @base: base address of the clock provider
- * @socdata: SoC specific data
- */
-struct uniphier_clk_priv {
- void __iomem *base;
- struct uniphier_clk_soc_data *socdata;
-};
+#define UNIPHIER_CLK_FIXED_RATE(_id, _rate) \
+ { \
+ .id = (_id), \
+ .rates = {(_reg),}, \
+ }
-extern const struct clk_ops uniphier_clk_ops;
-int uniphier_clk_probe(struct udevice *dev);
+extern const struct uniphier_clk_data uniphier_mio_clk_data;
#endif /* __CLK_UNIPHIER_H__ */
diff --git a/drivers/core/device.c b/drivers/core/device.c
index b737f1c..ed553d7 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -693,13 +693,35 @@
#endif
}
+fdt_addr_t dev_get_addr_size_index(struct udevice *dev, int index,
+ fdt_size_t *size)
+{
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ /*
+ * Only get the size in this first call. We'll get the addr in the
+ * next call to the exisiting dev_get_xxx function which handles
+ * all config options.
+ */
+ fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+ "reg", index, size, false);
+
+ /*
+ * Get the base address via the existing function which handles
+ * all Kconfig cases
+ */
+ return dev_get_addr_index(dev, index);
+#else
+ return FDT_ADDR_T_NONE;
+#endif
+}
+
fdt_addr_t dev_get_addr_name(struct udevice *dev, const char *name)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
int index;
- index = fdt_find_string(gd->fdt_blob, dev->of_offset, "reg-names",
- name);
+ index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ "reg-names", name);
if (index < 0)
return index;
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 6a634e6..23b6ba7 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -101,36 +101,24 @@
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
/**
- * driver_check_compatible() - Check if a driver is compatible with this node
+ * driver_check_compatible() - Check if a driver matches a compatible string
*
- * @param blob: Device tree pointer
- * @param offset: Offset of node in device tree
* @param of_match: List of compatible strings to match
* @param of_idp: Returns the match that was found
- * @return 0 if there is a match, -ENOENT if no match, -ENODEV if the node
- * does not have a compatible string, other error <0 if there is a device
- * tree error
+ * @param compat: The compatible string to search for
+ * @return 0 if there is a match, -ENOENT if no match
*/
-static int driver_check_compatible(const void *blob, int offset,
- const struct udevice_id *of_match,
- const struct udevice_id **of_idp)
+static int driver_check_compatible(const struct udevice_id *of_match,
+ const struct udevice_id **of_idp,
+ const char *compat)
{
- int ret;
-
- *of_idp = NULL;
if (!of_match)
return -ENOENT;
while (of_match->compatible) {
- ret = fdt_node_check_compatible(blob, offset,
- of_match->compatible);
- if (!ret) {
+ if (!strcmp(of_match->compatible, compat)) {
*of_idp = of_match;
return 0;
- } else if (ret == -FDT_ERR_NOTFOUND) {
- return -ENODEV;
- } else if (ret < 0) {
- return -EINVAL;
}
of_match++;
}
@@ -147,28 +135,46 @@
struct driver *entry;
struct udevice *dev;
bool found = false;
- const char *name;
+ const char *name, *compat_list, *compat;
+ int compat_length, i;
int result = 0;
int ret = 0;
- dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL));
+ name = fdt_get_name(blob, offset, NULL);
+ dm_dbg("bind node %s\n", name);
if (devp)
*devp = NULL;
- for (entry = driver; entry != driver + n_ents; entry++) {
- ret = driver_check_compatible(blob, offset, entry->of_match,
- &id);
- name = fdt_get_name(blob, offset, NULL);
- if (ret == -ENOENT) {
- continue;
- } else if (ret == -ENODEV) {
+
+ compat_list = fdt_getprop(blob, offset, "compatible", &compat_length);
+ if (!compat_list) {
+ if (compat_length == -FDT_ERR_NOTFOUND) {
dm_dbg("Device '%s' has no compatible string\n", name);
- break;
- } else if (ret) {
- dm_warn("Device tree error at offset %d\n", offset);
- result = ret;
- break;
+ return 0;
}
+ dm_warn("Device tree error at offset %d\n", offset);
+ return compat_length;
+ }
+
+ /*
+ * Walk through the compatible string list, attempting to match each
+ * compatible string in order such that we match in order of priority
+ * from the first string to the last.
+ */
+ for (i = 0; i < compat_length; i += strlen(compat) + 1) {
+ compat = compat_list + i;
+ dm_dbg(" - attempt to match compatible string '%s'\n",
+ compat);
+
+ for (entry = driver; entry != driver + n_ents; entry++) {
+ ret = driver_check_compatible(entry->of_match, &id,
+ compat);
+ if (!ret)
+ break;
+ }
+ if (entry == driver + n_ents)
+ continue;
+
dm_dbg(" - found match at '%s'\n", entry->name);
ret = device_bind_with_driver_data(parent, entry, name,
id->data, offset, &dev);
@@ -188,10 +194,8 @@
break;
}
- if (!found && !result && ret != -ENODEV) {
- dm_dbg("No match for node '%s'\n",
- fdt_get_name(blob, offset, NULL));
- }
+ if (!found && !result && ret != -ENODEV)
+ dm_dbg("No match for node '%s'\n", name);
return result;
}
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 0299ff0..c68bcba 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -13,6 +13,8 @@
#include <mapmem.h>
#include <regmap.h>
+#include <asm/io.h>
+
DECLARE_GLOBAL_DATA_PTR;
static struct regmap *regmap_alloc_count(int count)
@@ -117,3 +119,21 @@
return 0;
}
+
+int regmap_read(struct regmap *map, uint offset, uint *valp)
+{
+ uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE);
+
+ *valp = le32_to_cpu(readl(ptr));
+
+ return 0;
+}
+
+int regmap_write(struct regmap *map, uint offset, uint val)
+{
+ uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE);
+
+ writel(cpu_to_le32(val), ptr);
+
+ return 0;
+}
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 33dc9c0..9edfc1e 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -41,6 +41,13 @@
return gd->dm_root;
}
+void dm_fixup_for_gd_move(struct global_data *new_gd)
+{
+ /* The sentinel node has moved, so update things that point to it */
+ new_gd->uclass_root.next->prev = &new_gd->uclass_root;
+ new_gd->uclass_root.prev->next = &new_gd->uclass_root;
+}
+
fdt_addr_t dm_get_translation_offset(void)
{
struct udevice *root = dm_root();
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 01bd968..2148469 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -95,3 +95,14 @@
.per_device_auto_alloc_size = sizeof(struct syscon_uc_info),
.pre_probe = syscon_pre_probe,
};
+
+static const struct udevice_id generic_syscon_ids[] = {
+ { .compatible = "syscon" },
+ { }
+};
+
+U_BOOT_DRIVER(generic_syscon) = {
+ .name = "syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = generic_syscon_ids,
+};
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index de602ae..60610e5 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -148,6 +148,15 @@
return 0;
}
+const char *uclass_get_name(enum uclass_id id)
+{
+ struct uclass *uc;
+
+ if (uclass_get(id, &uc))
+ return NULL;
+ return uc->uc_drv->name;
+}
+
int uclass_find_device(enum uclass_id id, int index, struct udevice **devp)
{
struct uclass *uc;
diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index 7660f99..c57ac16 100644
--- a/drivers/cpu/cpu-uclass.c
+++ b/drivers/cpu/cpu-uclass.c
@@ -44,6 +44,16 @@
return ops->get_count(dev);
}
+int cpu_get_vendor(struct udevice *dev, char *buf, int size)
+{
+ struct cpu_ops *ops = cpu_get_ops(dev);
+
+ if (!ops->get_vendor)
+ return -ENOSYS;
+
+ return ops->get_vendor(dev, buf, size);
+}
+
U_BOOT_DRIVER(cpu_bus) = {
.name = "cpu_bus",
.id = UCLASS_SIMPLE_BUS,
diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c
index efef491..8f3b8b2 100644
--- a/drivers/crypto/ace_sha.c
+++ b/drivers/crypto/ace_sha.c
@@ -10,7 +10,7 @@
#ifdef CONFIG_SHA_HW_ACCEL
#include <u-boot/sha256.h>
#include <u-boot/sha1.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
/* SHA1 value for the message of zero length */
static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 86b2f2f..3188959 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -4,3 +4,42 @@
Enables the Freescale's Cryptographic Accelerator and Assurance
Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
Job Ring as interface to communicate with CAAM.
+
+config SYS_FSL_HAS_SEC
+ bool
+ help
+ Enable Freescale Secure Boot and Trusted Architecture
+
+config SYS_FSL_SEC_COMPAT_2
+ bool
+ help
+ Secure boot and trust architecture compatible version 2
+
+config SYS_FSL_SEC_COMPAT_4
+ bool
+ help
+ Secure boot and trust architecture compatible version 4
+
+config SYS_FSL_SEC_COMPAT_5
+ bool
+ help
+ Secure boot and trust architecture compatible version 5
+
+config SYS_FSL_SEC_COMPAT_6
+ bool
+ help
+ Secure boot and trust architecture compatible version 6
+
+config SYS_FSL_SEC_BE
+ bool "Big-endian access to Freescale Secure Boot"
+
+config SYS_FSL_SEC_COMPAT
+ int "Freescale Secure Boot compatibility"
+ depends on SYS_FSL_HAS_SEC
+ default 2 if SYS_FSL_SEC_COMPAT_2
+ default 4 if SYS_FSL_SEC_COMPAT_4
+ default 5 if SYS_FSL_SEC_COMPAT_5
+ default 6 if SYS_FSL_SEC_COMPAT_6
+
+config SYS_FSL_SEC_LE
+ bool "Little-endian access to Freescale Secure Boot"
diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
index d24b8fc..38c6f94 100644
--- a/drivers/crypto/fsl/fsl_blob.c
+++ b/drivers/crypto/fsl/fsl_blob.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <malloc.h>
#include <fsl_sec.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include "jobdesc.h"
#include "desc.h"
#include "jr.h"
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index 887e88c..a63eba3 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -12,7 +12,7 @@
#include "jr.h"
#include "fsl_hash.h"
#include <hw_sha.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#define CRYPTO_MAX_ALG_NAME 80
#define SHA1_DIGEST_SIZE 20
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index fd0c4f7..6125bbb 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -41,7 +41,7 @@
/*!
* CAAM page allocation:
* Allocates a partition from secure memory, with the id
- * equal to partion_num. This will de-allocate the page
+ * equal to partition_num. This will de-allocate the page
* if it is already allocated. The partition will have
* full access permissions. The permissions are set before,
* running a job descriptor. A memory page of secure RAM
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 4a8cc32..1b88229 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -21,7 +21,7 @@
uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
0,
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
CONFIG_SYS_FSL_SEC_IDX_OFFSET,
2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
#endif
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 7e4606d..e74c5b0 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -418,6 +418,9 @@
debug("Configuring DRAMODT\n");
writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
+
+ debug("Configuring EXTRATIME1\n");
+ writel(cfg->extratime1, &sdr_ctrl->extratime1);
}
/**
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
new file mode 100644
index 0000000..a3d2bd5
--- /dev/null
+++ b/drivers/ddr/fsl/Kconfig
@@ -0,0 +1,172 @@
+config SYS_FSL_DDR
+ bool
+ help
+ Select Freescale General DDR driver, shared between most Freescale
+ PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
+ based Layerscape SoCs (such as ls2080a).
+
+config SYS_FSL_MMDC
+ bool
+ help
+ Select Freescale Multi Mode DDR controller (MMDC).
+
+config SYS_FSL_DDR_BE
+ bool
+ help
+ Access DDR registers in big-endian
+
+config SYS_FSL_DDR_LE
+ bool
+ help
+ Access DDR registers in little-endian
+
+menu "Freescale DDR controllers"
+ depends on SYS_FSL_DDR
+
+config SYS_NUM_DDR_CTLRS
+ int "Maximum DDR controllers"
+ default 3 if ARCH_LS2080A || \
+ ARCH_T4240
+ default 2 if ARCH_B4860 || \
+ ARCH_BSC9132 || \
+ ARCH_MPC8572 || \
+ ARCH_MPC8641 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T4160
+ default 1
+
+config SYS_FSL_DDR_VER
+ int
+ default 50 if SYS_FSL_DDR_VER_50
+ default 47 if SYS_FSL_DDR_VER_47
+ default 46 if SYS_FSL_DDR_VER_46
+ default 44 if SYS_FSL_DDR_VER_44
+
+config SYS_FSL_DDR_VER_50
+ bool
+
+config SYS_FSL_DDR_VER_47
+ bool
+
+config SYS_FSL_DDR_VER_46
+ bool
+
+config SYS_FSL_DDR_VER_44
+ bool
+
+config SYS_FSL_DDRC_GEN1
+ bool
+ help
+ Enable Freescale DDR controller.
+
+config SYS_FSL_DDRC_GEN2
+ bool
+ depends on !MPC86xx
+ help
+ Enable Freescale DDR2 controller.
+
+config SYS_FSL_DDRC_86XX_GEN2
+ bool
+ depends on MPC86xx
+ help
+ Enable Freescale DDR2 controller for MPC86xx SoCs.
+
+config SYS_FSL_DDRC_GEN3
+ bool
+ depends on PPC
+ help
+ Enable Freescale DDR3 controller for PowerPC SoCs.
+
+config SYS_FSL_DDRC_ARM_GEN3
+ bool
+ depends on ARM
+ help
+ Enable Freescale DDR3 controller for ARM SoCs.
+
+config SYS_FSL_DDRC_GEN4
+ bool
+ help
+ Enable Freescale DDR4 controller.
+
+config SYS_FSL_HAS_DDR4
+ bool
+
+config SYS_FSL_HAS_DDR3
+ bool
+
+config SYS_FSL_HAS_DDR2
+ bool
+
+config SYS_FSL_HAS_DDR1
+ bool
+
+choice
+ prompt "DDR technology"
+ default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
+ default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
+ default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
+ default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
+
+config SYS_FSL_DDR4
+ bool "Freescale DDR4 controller"
+ depends on SYS_FSL_HAS_DDR4
+ select SYS_FSL_DDRC_GEN4
+
+config SYS_FSL_DDR3
+ bool "Freescale DDR3 controller"
+ depends on SYS_FSL_HAS_DDR3
+ select SYS_FSL_DDRC_GEN3 if PPC
+ select SYS_FSL_DDRC_ARM_GEN3 if ARM
+
+config SYS_FSL_DDR2
+ bool "Freescale DDR2 controller"
+ depends on SYS_FSL_HAS_DDR2
+ select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
+ select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
+
+config SYS_FSL_DDR1
+ bool "Freescale DDR1 controller"
+ depends on SYS_FSL_HAS_DDR1
+ select SYS_FSL_DDRC_GEN1
+
+endchoice
+
+endmenu
+
+config SYS_FSL_ERRATUM_A008378
+ bool
+
+config SYS_FSL_ERRATUM_A008511
+ bool
+
+config SYS_FSL_ERRATUM_A009663
+ bool
+
+config SYS_FSL_ERRATUM_A009801
+ bool
+
+config SYS_FSL_ERRATUM_A009803
+ bool
+
+config SYS_FSL_ERRATUM_A009942
+ bool
+
+config SYS_FSL_ERRATUM_A010165
+ bool
+
+config SYS_FSL_ERRATUM_NMG_DDR120
+ bool
+
+config SYS_FSL_ERRATUM_DDR_115
+ bool
+
+config SYS_FSL_ERRATUM_DDR111_DDR134
+ bool
+
+config SYS_FSL_ERRATUM_DDR_A003
+ bool
+
+config SYS_FSL_ERRATUM_DDR_A003474
+ bool
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index 01ea862..7935f7d 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -30,6 +30,7 @@
obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
-obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
+obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
+obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 7160da4..5b7ced5 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -40,17 +40,17 @@
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 24fd366..21687dd 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -5,14 +5,14 @@
*/
/*
- * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
+ * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
* Based on code from spd_sdram.c
* Author: James Yang [at freescale.com]
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
-
+#include <fsl_errata.h>
#include <fsl_ddr.h>
#include <fsl_immap.h>
#include <asm/io.h>
@@ -1831,7 +1831,7 @@
unsigned int clk_adjust; /* Clock adjust */
unsigned int ss_en = 0; /* Source synchronous enable */
-#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
/* Per FSL Application Note: AN2805 */
ss_en = 1;
#endif
@@ -2306,6 +2306,38 @@
unsigned int ip_rev = 0;
unsigned int unq_mrs_en = 0;
int cs_en = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+ unsigned int ddr_freq;
+#endif
+#if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
+ defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A009942)
+ struct ccsr_ddr __iomem *ddrc;
+
+ switch (ctrl_num) {
+ case 0:
+ ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+ case 1:
+ ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+ case 2:
+ ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
+ case 3:
+ ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+ break;
+#endif
+ default:
+ printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
+ return 1;
+ }
+#endif
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
@@ -2526,5 +2558,105 @@
ddr->debug[2] |= 0x00000200; /* set bit 22 */
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
+ /* Erratum applies when accumulated ECC is used, or DBI is enabled */
+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
+ if (has_erratum_a008378()) {
+ if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
+ IS_DBI(ddr->ddr_sdram_cfg_3)) {
+ ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
+ ddr->debug[28] |= (0x9 << 20);
+ }
+ }
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+ ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
+ ddr->debug[28] &= 0xff0fff00;
+ if (ddr_freq <= 1333)
+ ddr->debug[28] |= 0x0080006a;
+ else if (ddr_freq <= 1600)
+ ddr->debug[28] |= 0x0070006f;
+ else if (ddr_freq <= 1867)
+ ddr->debug[28] |= 0x00700076;
+ else if (ddr_freq <= 2133)
+ ddr->debug[28] |= 0x0060007b;
+ if (popts->cpo_sample)
+ ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
+ popts->cpo_sample;
+#endif
+
return check_fsl_memctl_config_regs(ddr);
}
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+/*
+ * This additional workaround of A009942 checks the condition to determine if
+ * the CPO value set by the existing A009942 workaround needs to be updated.
+ * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
+ * expected optimal value, the optimal value is highly board dependent.
+ */
+void erratum_a009942_check_cpo(void)
+{
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
+ u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
+ u32 cpo_max = cpo_min;
+ u32 sdram_cfg, i, tmp, lanes, ddr_type;
+ bool update_cpo = false, has_ecc = false;
+
+ sdram_cfg = ddr_in32(&ddr->sdram_cfg);
+ if (sdram_cfg & SDRAM_CFG_32_BE)
+ lanes = 4;
+ else if (sdram_cfg & SDRAM_CFG_16_BE)
+ lanes = 2;
+ else
+ lanes = 8;
+
+ if (sdram_cfg & SDRAM_CFG_ECC_EN)
+ has_ecc = true;
+
+ /* determine the maximum and minimum CPO values */
+ for (i = 9; i < 9 + lanes / 2; i++) {
+ cpo = ddr_in32(&ddr->debug[i]);
+ cpo_e = cpo >> 24;
+ cpo_o = (cpo >> 8) & 0xff;
+ tmp = min(cpo_e, cpo_o);
+ if (tmp < cpo_min)
+ cpo_min = tmp;
+ tmp = max(cpo_e, cpo_o);
+ if (tmp > cpo_max)
+ cpo_max = tmp;
+ }
+
+ if (has_ecc) {
+ cpo = ddr_in32(&ddr->debug[13]);
+ cpo = cpo >> 24;
+ if (cpo < cpo_min)
+ cpo_min = cpo;
+ if (cpo > cpo_max)
+ cpo_max = cpo;
+ }
+
+ cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
+ cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
+ debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
+ cpo_target);
+ debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
+
+ ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
+ SDRAM_CFG_SDRAM_TYPE_SHIFT;
+ if (ddr_type == SDRAM_TYPE_DDR4)
+ update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
+ else if (ddr_type == SDRAM_TYPE_DDR3)
+ update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
+
+ if (update_cpo) {
+ printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
+ printf("in <board>/ddr.c to optimize cpo\n");
+ }
+}
+#endif
diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c
index 00cdc22..369b325 100644
--- a/drivers/ddr/fsl/ddr1_dimm_params.c
+++ b/drivers/ddr/fsl/ddr1_dimm_params.c
@@ -108,22 +108,14 @@
static unsigned int
compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
{
- unsigned int trfc_ps;
-
- trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
+ return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000
+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
-
- return trfc_ps;
}
static unsigned int
compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
{
- unsigned int trc_ps;
-
- trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
-
- return trc_ps;
+ return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
}
/*
diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c
index 59baf6b..af752cc 100644
--- a/drivers/ddr/fsl/ddr2_dimm_params.c
+++ b/drivers/ddr/fsl/ddr2_dimm_params.c
@@ -107,22 +107,14 @@
static unsigned int
compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
{
- unsigned int trfc_ps;
-
- trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
+ return (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
-
- return trfc_ps;
}
static unsigned int
compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
{
- unsigned int trc_ps;
-
- trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
-
- return trc_ps;
+ return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
}
/*
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index d37e247..e0f9e2c 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -47,20 +47,16 @@
{
unsigned int i, bus_width;
struct ccsr_ddr __iomem *ddr;
- u32 temp_sdram_cfg;
+ u32 temp32;
u32 total_gb_size_per_controller;
int timeout;
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
- u32 temp32, mr6;
+ u32 mr6;
u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */
u32 *vref_seq = vref_seq1;
#endif
-#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
- defined(CONFIG_SYS_FSL_ERRATUM_A010165)
- ulong ddr_freq;
- u32 tmp;
-#endif
#ifdef CONFIG_FSL_DDR_BIST
u32 mtcr, err_detect, err_sbe;
u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
@@ -68,22 +64,21 @@
#ifdef CONFIG_FSL_DDR_BIST
char buffer[CONFIG_SYS_CBSIZE];
#endif
-
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
@@ -218,27 +213,16 @@
ddr_out32(&ddr->err_disable, regs->err_disable);
#endif
ddr_out32(&ddr->err_int_en, regs->err_int_en);
- for (i = 0; i < 32; i++) {
+ for (i = 0; i < 64; i++) {
if (regs->debug[i]) {
debug("Write to debug_%d as %08x\n",
i+1, regs->debug[i]);
ddr_out32(&ddr->debug[i], regs->debug[i]);
}
}
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
- /* Erratum applies when accumulated ECC is used, or DBI is enabled */
-#define IS_ACC_ECC_EN(v) ((v) & 0x4)
-#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
- if (has_erratum_a008378()) {
- if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
- IS_DBI(regs->ddr_sdram_cfg_3))
- ddr_setbits32(&ddr->debug[28], 0x9 << 20);
- }
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
/* Part 1 of 2 */
- /* This erraum only applies to verion 5.2.0 */
if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
/* Disable DRAM VRef training */
ddr_out32(&ddr->ddr_cdr2,
@@ -247,13 +231,25 @@
temp32 = ddr_in32(&ddr->debug[28]);
temp32 |= DDR_TX_BD_DIS;
ddr_out32(&ddr->debug[28], temp32);
- /* Disable D_INIT */
- ddr_out32(&ddr->sdram_cfg_2,
- regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
ddr_out32(&ddr->debug[25], 0x9000);
+ } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
+ /* Output enable forced off */
+ ddr_out32(&ddr->debug[37], 1 << 31);
+ /* Enable Vref training */
+ ddr_out32(&ddr->ddr_cdr2,
+ regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
+ } else {
+ debug("Erratum A008511 doesn't apply.\n");
}
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A008511)
+ /* Disable D_INIT */
+ ddr_out32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A009801
temp32 = ddr_in32(&ddr->debug[25]);
temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
@@ -261,24 +257,11 @@
ddr_out32(&ddr->debug[25], temp32);
#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
- ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
- tmp = ddr_in32(&ddr->debug[28]);
- if (ddr_freq <= 1333)
- ddr_out32(&ddr->debug[28], tmp | 0x0080006a);
- else if (ddr_freq <= 1600)
- ddr_out32(&ddr->debug[28], tmp | 0x0070006f);
- else if (ddr_freq <= 1867)
- ddr_out32(&ddr->debug[28], tmp | 0x00700076);
- else if (ddr_freq <= 2133)
- ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
-#endif
-
#ifdef CONFIG_SYS_FSL_ERRATUM_A010165
- ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
- if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
- tmp = ddr_in32(&ddr->debug[28]);
- ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
+ temp32 = get_ddr_freq(ctrl_num) / 1000000;
+ if ((temp32 > 1900) && (temp32 < 2300)) {
+ temp32 = ddr_in32(&ddr->debug[28]);
+ ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
}
#endif
/*
@@ -296,9 +279,9 @@
step2:
/* Set, but do not enable the memory */
- temp_sdram_cfg = regs->ddr_sdram_cfg;
- temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
- ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
+ temp32 = regs->ddr_sdram_cfg;
+ temp32 &= ~(SDRAM_CFG_MEM_EN);
+ ddr_out32(&ddr->sdram_cfg, temp32);
/*
* 500 painful micro-seconds must elapse between
@@ -313,39 +296,39 @@
#ifdef CONFIG_DEEP_SLEEP
if (is_warm_boot()) {
/* enter self-refresh */
- temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
- temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
- ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+ temp32 = ddr_in32(&ddr->sdram_cfg_2);
+ temp32 |= SDRAM_CFG2_FRC_SR;
+ ddr_out32(&ddr->sdram_cfg_2, temp32);
/* do board specific memory setup */
board_mem_sleep_setup();
- temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+ temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
} else
#endif
- temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+ temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
/* Let the controller go */
- ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+ ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
mb();
isb();
#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
defined(CONFIG_SYS_FSL_ERRATUM_A009803)
/* Part 2 of 2 */
- /* This erraum only applies to verion 5.2.0 */
- if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
- /* Wait for idle */
- timeout = 40;
- while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
- (timeout > 0)) {
- udelay(1000);
- timeout--;
- }
- if (timeout <= 0) {
- printf("Controler %d timeout, debug_2 = %x\n",
- ctrl_num, ddr_in32(&ddr->debug[1]));
- }
+ timeout = 40;
+ /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
+ while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
+ (timeout > 0)) {
+ udelay(1000);
+ timeout--;
+ }
+ if (timeout <= 0) {
+ printf("Controler %d timeout, debug_2 = %x\n",
+ ctrl_num, ddr_in32(&ddr->debug[1]));
+ }
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+ /* This erraum only applies to verion 5.2.0 */
+ if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
/* The vref setting sequence is different for range 2 */
if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
vref_seq = vref_seq2;
@@ -392,32 +375,32 @@
printf("Controler %d timeout, debug_2 = %x\n",
ctrl_num, ddr_in32(&ddr->debug[1]));
}
- /* Restore D_INIT */
- ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ }
#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
- if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
- /* if it's RDIMM */
- if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
- continue;
- set_wait_for_bits_clear(&ddr->sdram_md_cntl,
- MD_CNTL_MD_EN |
- MD_CNTL_CS_SEL(i) |
- 0x070000ed,
- MD_CNTL_MD_EN);
- udelay(1);
- }
+ if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+ /* if it's RDIMM */
+ if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+ continue;
+ set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL(i) |
+ 0x070000ed,
+ MD_CNTL_MD_EN);
+ udelay(1);
}
-
- ddr_out32(&ddr->err_disable,
- regs->err_disable & ~DDR_ERR_DISABLE_APED);
}
-#endif
+
+ ddr_out32(&ddr->err_disable,
+ regs->err_disable & ~DDR_ERR_DISABLE_APED);
}
#endif
+ /* Restore D_INIT */
+ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+#endif
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
@@ -467,9 +450,9 @@
#ifdef CONFIG_DEEP_SLEEP
if (is_warm_boot()) {
/* exit self-refresh */
- temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
- temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
- ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+ temp32 = ddr_in32(&ddr->sdram_cfg_2);
+ temp32 &= ~SDRAM_CFG2_FRC_SR;
+ ddr_out32(&ddr->sdram_cfg_2, temp32);
}
#endif
diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
new file mode 100644
index 0000000..52eec0f
--- /dev/null
+++ b/drivers/ddr/fsl/fsl_mmdc.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
+ */
+
+#include <common.h>
+#include <fsl_mmdc.h>
+#include <asm/io.h>
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ printf("Error: %p wait for clear timeout.\n", ptr);
+}
+
+void mmdc_init(const struct fsl_mmdc_info *priv)
+{
+ struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+ unsigned int tmp;
+
+ /* 1. set configuration request */
+ out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+ /* 2. configure the desired timing parameters */
+ out_be32(&mmdc->mdotc, priv->mdotc);
+ out_be32(&mmdc->mdcfg0, priv->mdcfg0);
+ out_be32(&mmdc->mdcfg1, priv->mdcfg1);
+ out_be32(&mmdc->mdcfg2, priv->mdcfg2);
+
+ /* 3. configure DDR type and other miscellaneous parameters */
+ out_be32(&mmdc->mdmisc, priv->mdmisc);
+ out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
+ out_be32(&mmdc->mdrwd, priv->mdrwd);
+ out_be32(&mmdc->mpodtctrl, priv->mpodtctrl);
+
+ /* 4. configure the required delay while leaving reset */
+ out_be32(&mmdc->mdor, priv->mdor);
+
+ /* 5. configure DDR physical parameters */
+ /* set row/column address width, burst length, data bus width */
+ tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1);
+ out_be32(&mmdc->mdctl, tmp);
+ /* configure address space partition */
+ out_be32(&mmdc->mdasp, priv->mdasp);
+
+ /* 6. perform a ZQ calibration - not needed here, doing in #8b */
+
+ /* 7. enable MMDC with the desired chip select */
+#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
+ out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
+#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
+ out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
+#endif
+
+ /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) |
+ CMD_ADDR_LSB_MR_ADDR(0x30) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
+
+ /* 8b. ZQ calibration */
+ out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
+
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, priv->mpzqhwctrl,
+ MPZQHWCTRL_ZQ_HW_FORCE);
+
+ /* 9a. calibrations now, wr lvl */
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+ out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
+ CMD_NORMAL);
+
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
+ MPWLGCR_HW_WL_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+ out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+ mdelay(1);
+
+ /* 9b. read DQS gating calibration */
+ out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+ out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
+
+ /* set absolute read delay offset */
+ if (priv->mprddlctl)
+ out_be32(&mmdc->mprddlctl, priv->mprddlctl);
+ else
+ out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);
+
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3);
+
+ /* 9c. read calibration */
+ out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+ out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
+ MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3);
+
+ /* 10. configure power-down, self-refresh entry, exit parameters */
+ out_be32(&mmdc->mdpdc, priv->mdpdc);
+ out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
+
+ /* 11. ZQ config again? do nothing here */
+
+ /* 12. refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref, priv->mdref,
+ MDREF_START_REFRESH);
+
+ /* 13. disable CON_REQ */
+ out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
+}
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index d23e6e5..202ad13 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -670,7 +670,7 @@
print_option_table(options, n_opts, ddr);
- for (i = 0; i < 32; i++)
+ for (i = 0; i < 64; i++)
printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
}
@@ -763,7 +763,7 @@
debug("fsl_ddr_regs_edit: ctrl_num = %u, "
"regname = %s, value = %s\n",
ctrl_num, regname, value_str);
- if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
+ if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
return;
ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
@@ -771,7 +771,7 @@
if (handle_option_table(options, n_opts, ddr, regname, value_str))
return;
- for (i = 0; i < 32; i++) {
+ for (i = 0; i < 64; i++) {
unsigned int value = simple_strtoul(value_str, NULL, 0);
sprintf(buf, "debug_%u", i + 1);
if (strcmp(buf, regname) == 0) {
@@ -1685,7 +1685,7 @@
/* STEP 1: DIMM SPD data */
if (do_mask & STEP_GET_SPD) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
@@ -1706,7 +1706,7 @@
/* STEP 2: DIMM Parameters */
if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
@@ -1725,7 +1725,7 @@
/* STEP 3: Common Parameters */
if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("\"lowest common\" DIMM parameters: "
@@ -1739,7 +1739,7 @@
/* STEP 4: User Configuration Options */
if (do_mask & STEP_GATHER_OPTS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("User Config Options: Controller=%u\n", i);
@@ -1751,7 +1751,7 @@
/* STEP 5: Address assignment */
if (do_mask & STEP_ASSIGN_ADDRESSES) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
@@ -1766,7 +1766,7 @@
/* STEP 6: computed controller register values */
if (do_mask & STEP_COMPUTE_REGS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("Computed Register Values: Controller=%u\n", i);
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 479184f..159c22e 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -40,35 +40,35 @@
#if defined(SPD_EEPROM_ADDRESS) || \
defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
-#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS,
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
[1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
[2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
@@ -146,7 +146,7 @@
unsigned int i;
unsigned int i2c_address = 0;
- if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
+ if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
return;
}
@@ -430,7 +430,7 @@
assert_reset = pinfo->board_need_mem_reset();
/* data bus width capacity adjust shift amount */
- unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
+ unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
for (i = first_ctrl; i <= last_ctrl; i++)
dbw_capacity_adjust[i] = 0;
@@ -720,7 +720,7 @@
&pinfo->common_timing_params[i],
law_memctl, i);
}
-#if CONFIG_NUM_DDR_CONTROLLERS > 3
+#if CONFIG_SYS_NUM_DDR_CTLRS > 3
else if (i == 2) {
law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
fsl_ddr_set_lawbar(
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index c27288d..c005f52 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -47,7 +47,7 @@
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
+#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
#endif
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 653b7f0..afbed59 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -44,17 +44,17 @@
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
@@ -174,9 +174,6 @@
out_be32(&ddr->debug[i], regs->debug[i]);
}
}
-#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
- out_be32(&ddr->debug[28], 0x30003000);
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
out_be32(&ddr->debug[12], 0x00000015);
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 793d12a..d6a8fcb 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -1077,7 +1077,7 @@
* if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
* with 256 Byte is enabled.
*/
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
;
@@ -1107,39 +1107,39 @@
"ctlr_intlv",
"cacheline", buf)) {
popts->memctl_interleaving_mode =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
popts->memctl_interleaving =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"page", buf)) {
popts->memctl_interleaving_mode =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_PAGE_INTERLEAVING;
popts->memctl_interleaving =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"bank", buf)) {
popts->memctl_interleaving_mode =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_BANK_INTERLEAVING;
popts->memctl_interleaving =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"superbank", buf)) {
popts->memctl_interleaving_mode =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_SUPERBANK_INTERLEAVING;
popts->memctl_interleaving =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
-#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"3way_1KB", buf)) {
@@ -1155,7 +1155,7 @@
"3way_8KB", buf)) {
popts->memctl_interleaving_mode =
FSL_DDR_3WAY_8KB_INTERLEAVING;
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"4way_1KB", buf)) {
@@ -1178,7 +1178,7 @@
}
#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
done:
-#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
+#endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
/* test null first. if CONFIG_HWCONFIG is not defined,
@@ -1356,10 +1356,10 @@
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
-#if (3 == CONFIG_NUM_DDR_CONTROLLERS)
+#if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
k = 2;
#else
- k = CONFIG_NUM_DDR_CONTROLLERS;
+ k = CONFIG_SYS_NUM_DDR_CTLRS;
#endif
break;
case FSL_DDR_3WAY_1KB_INTERLEAVING:
@@ -1369,7 +1369,7 @@
case FSL_DDR_4WAY_4KB_INTERLEAVING:
case FSL_DDR_4WAY_8KB_INTERLEAVING:
default:
- k = CONFIG_NUM_DDR_CONTROLLERS;
+ k = CONFIG_SYS_NUM_DDR_CTLRS;
break;
}
debug("%d of %d controllers are interleaving.\n", j, k);
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 9977779..b58784b 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -30,17 +30,17 @@
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
@@ -174,23 +174,23 @@
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
-#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
#endif
uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
int cas_lat;
-#if CONFIG_NUM_DDR_CONTROLLERS >= 2
+#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 1)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
-#if CONFIG_NUM_DDR_CONTROLLERS >= 3
+#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 2)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
@@ -246,7 +246,7 @@
else
puts(", ECC off)");
-#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
#ifdef CONFIG_E6500
if (*mcintl3r & 0x80000000) {
puts("\n");
@@ -268,7 +268,7 @@
}
#endif
#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
puts("\n");
puts(" DDR Controller Interleaving Mode: ");
@@ -337,8 +337,8 @@
{
unsigned int i;
u32 ddrc_debug20;
- u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
- u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
+ u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
+ u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
struct ccsr_ddr __iomem *ddr;
for (i = first_ctrl; i <= last_ctrl; i++) {
@@ -346,17 +346,17 @@
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
diff --git a/drivers/ddr/marvell/a38x/ddr3_a38x.c b/drivers/ddr/marvell/a38x/ddr3_a38x.c
index f469907..c082122 100644
--- a/drivers/ddr/marvell/a38x/ddr3_a38x.c
+++ b/drivers/ddr/marvell/a38x/ddr3_a38x.c
@@ -706,11 +706,7 @@
int ddr3_silicon_pre_init(void)
{
- int result;
-
- result = ddr3_silicon_init();
-
- return result;
+ return ddr3_silicon_init();
}
int ddr3_post_run_alg(void)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 80ef050..7e0749f 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -1302,7 +1302,7 @@
}
if (mem_mask != 0) {
- /* motib redundent in KW28 */
+ /* motib redundant in KW28 */
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
if_id,
CS_ENABLE_REG, 0, 0x8));
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 6b92064..56a98f5 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -1,5 +1,9 @@
menu "DFU support"
+config USB_FUNCTION_DFU
+ bool
+
+if CMD_DFU
config DFU_TFTP
bool "DFU via TFTP"
help
@@ -7,4 +11,28 @@
sent via TFTP boot.
Detailed description of this feature can be found at ./doc/README.dfutftp
+
+config DFU_MMC
+ bool "MMC back end for DFU"
+ help
+ This option enables using DFU to read and write to MMC based storage.
+
+config DFU_NAND
+ bool "NAND back end for DFU"
+ help
+ This option enables using DFU to read and write to NAND based
+ storage.
+
+config DFU_RAM
+ bool "RAM back end for DFU"
+ help
+ This option enables using DFU to read and write RAM on the target.
+
+config DFU_SF
+ bool "SPI flash back end for DFU"
+ help
+ This option enables using DFU to read and write to SPI flash based
+ storage.
+
+endif
endmenu
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 20dfcbb..8dacc1a 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -482,7 +482,7 @@
const char *dfu_get_dev_type(enum dfu_device_type t)
{
- const char *dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM" };
+ const char *dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM", "SF" };
return dev_t[t];
}
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index a6dc935..a97fa85 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -14,7 +14,7 @@
#include <common.h>
#include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
new file mode 100644
index 0000000..a760944
--- /dev/null
+++ b/drivers/fpga/Kconfig
@@ -0,0 +1,40 @@
+menu "FPGA support"
+
+config FPGA
+ bool
+
+config FPGA_ALTERA
+ bool "Enable Altera FPGA drivers"
+ select FPGA
+ help
+ Say Y here to enable the Altera FPGA driver
+
+ This provides basic infrastructure to support Altera FPGA devices.
+ Enable Altera FPGA specific functions which includes bitstream
+ (in BIT format), fpga and device validation.
+
+config FPGA_CYCLON2
+ bool "Enable Altera FPGA driver for Cyclone II"
+ depends on FPGA_ALTERA
+ help
+ Say Y here to enable the Altera Cyclone II FPGA specific driver
+
+ This provides common functionality for Altera Cyclone II devices.
+ Enable FPGA driver for loading bitstream in BIT and BIN format
+ on Altera Cyclone II device.
+
+config FPGA_XILINX
+ bool "Enable Xilinx FPGA drivers"
+ select FPGA
+ help
+ Enable Xilinx FPGA specific functions which includes bitstream
+ (in BIT format), fpga and device validation.
+
+config FPGA_ZYNQMPPL
+ bool "Enable Xilinx FPGA driver for ZynqMP"
+ depends on FPGA_XILINX
+ help
+ Enable FPGA driver for loading bitstream in BIT and BIN format
+ on Xilinx Zynq UltraScale+ (ZynqMP) device.
+
+endmenu
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index fec3fec..777706f 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -10,6 +10,7 @@
obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
+obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
obj-$(CONFIG_FPGA_XILINX) += xilinx.o
obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
ifdef CONFIG_FPGA_ALTERA
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 4448250..f1b2f2c 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
diff --git a/drivers/fpga/stratixv.c b/drivers/fpga/stratixv.c
index cc035eb..9a81aca 100644
--- a/drivers/fpga/stratixv.c
+++ b/drivers/fpga/stratixv.c
@@ -8,7 +8,7 @@
#include <altera.h>
#include <spi.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
/* Write the RBF data to FPGA via SPI */
static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index d459a2f..2cd0104 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -199,6 +199,9 @@
case xilinx_zynq:
printf("Zynq PL\n");
break;
+ case xilinx_zynqmp:
+ printf("ZynqMP PL\n");
+ break;
/* Add new family types here */
default:
printf ("Unknown family type, %d\n", desc->family);
@@ -227,6 +230,9 @@
case devcfg:
printf("Device configuration interface (Zynq)\n");
break;
+ case csu_dma:
+ printf("csu_dma configuration interface (ZynqMP)\n");
+ break;
/* Add new interface types here */
default:
printf ("Unsupported interface type, %d\n", desc->iface);
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
new file mode 100644
index 0000000..23039c3
--- /dev/null
+++ b/drivers/fpga/zynqmppl.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2015 - 2016, Xilinx, Inc,
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <console.h>
+#include <common.h>
+#include <zynqmppl.h>
+#include <linux/sizes.h>
+
+#define DUMMY_WORD 0xffffffff
+
+/* Xilinx binary format header */
+static const u32 bin_format[] = {
+ DUMMY_WORD, /* Dummy words */
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ 0x000000bb, /* Sync word */
+ 0x11220044, /* Sync word */
+ DUMMY_WORD,
+ DUMMY_WORD,
+ 0xaa995566, /* Sync word */
+};
+
+#define SWAP_NO 1
+#define SWAP_DONE 2
+
+/*
+ * Load the whole word from unaligned buffer
+ * Keep in your mind that it is byte loading on little-endian system
+ */
+static u32 load_word(const void *buf, u32 swap)
+{
+ u32 word = 0;
+ u8 *bitc = (u8 *)buf;
+ int p;
+
+ if (swap == SWAP_NO) {
+ for (p = 0; p < 4; p++) {
+ word <<= 8;
+ word |= bitc[p];
+ }
+ } else {
+ for (p = 3; p >= 0; p--) {
+ word <<= 8;
+ word |= bitc[p];
+ }
+ }
+
+ return word;
+}
+
+static u32 check_header(const void *buf)
+{
+ u32 i, pattern;
+ int swap = SWAP_NO;
+ u32 *test = (u32 *)buf;
+
+ debug("%s: Let's check bitstream header\n", __func__);
+
+ /* Checking that passing bin is not a bitstream */
+ for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
+ pattern = load_word(&test[i], swap);
+
+ /*
+ * Bitstreams in binary format are swapped
+ * compare to regular bistream.
+ * Do not swap dummy word but if swap is done assume
+ * that parsing buffer is binary format
+ */
+ if ((__swab32(pattern) != DUMMY_WORD) &&
+ (__swab32(pattern) == bin_format[i])) {
+ swap = SWAP_DONE;
+ debug("%s: data swapped - let's swap\n", __func__);
+ }
+
+ debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
+ &test[i], pattern, bin_format[i]);
+ }
+ debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
+ buf, swap == SWAP_NO ? "without" : "with");
+
+ return swap;
+}
+
+static void *check_data(u8 *buf, size_t bsize, u32 *swap)
+{
+ u32 word, p = 0; /* possition */
+
+ /* Because buf doesn't need to be aligned let's read it by chars */
+ for (p = 0; p < bsize; p++) {
+ word = load_word(&buf[p], SWAP_NO);
+ debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
+
+ /* Find the first bitstream dummy word */
+ if (word == DUMMY_WORD) {
+ debug("%s: Found dummy word at position %x/%px\n",
+ __func__, p, &buf[p]);
+ *swap = check_header(&buf[p]);
+ if (*swap) {
+ /* FIXME add full bitstream checking here */
+ return &buf[p];
+ }
+ }
+ /* Loop can be huge - support CTRL + C */
+ if (ctrlc())
+ return NULL;
+ }
+ return NULL;
+}
+
+static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
+{
+ u32 *new_buf;
+ u32 i;
+
+ if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
+ new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
+
+ /*
+ * This might be dangerous but permits to flash if
+ * ARCH_DMA_MINALIGN is greater than header size
+ */
+ if (new_buf > (u32 *)buf) {
+ debug("%s: Aligned buffer is after buffer start\n",
+ __func__);
+ new_buf -= ARCH_DMA_MINALIGN;
+ }
+ printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
+ buf, new_buf, swap);
+
+ for (i = 0; i < (len/4); i++)
+ new_buf[i] = load_word(&buf[i], swap);
+
+ buf = new_buf;
+ } else if (swap != SWAP_DONE) {
+ /* For bitstream which are aligned */
+ u32 *new_buf = (u32 *)buf;
+
+ printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
+ swap);
+
+ for (i = 0; i < (len/4); i++)
+ new_buf[i] = load_word(&buf[i], swap);
+ }
+
+ return (ulong)buf;
+}
+
+static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
+ size_t bsize, u32 blocksize, u32 *swap)
+{
+ ulong *buf_start;
+ ulong diff;
+
+ buf_start = check_data((u8 *)buf, blocksize, swap);
+
+ if (!buf_start)
+ return FPGA_FAIL;
+
+ /* Check if data is postpone from start */
+ diff = (ulong)buf_start - (ulong)buf;
+ if (diff) {
+ printf("%s: Bitstream is not validated yet (diff %lx)\n",
+ __func__, diff);
+ return FPGA_FAIL;
+ }
+
+ if ((ulong)buf < SZ_1M) {
+ printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
+ __func__, buf);
+ return FPGA_FAIL;
+ }
+
+ return 0;
+}
+
+static int invoke_smc(ulong id, ulong reg0, ulong reg1, ulong reg2)
+{
+ struct pt_regs regs;
+ regs.regs[0] = id;
+ regs.regs[1] = reg0;
+ regs.regs[2] = reg1;
+ regs.regs[3] = reg2;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
+ bitstream_type bstype)
+{
+ u32 swap;
+ ulong bin_buf, flags;
+ int ret;
+
+ if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
+ return FPGA_FAIL;
+
+ bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
+
+ debug("%s called!\n", __func__);
+ flush_dcache_range(bin_buf, bin_buf + bsize);
+
+ if (bsize % 4)
+ bsize = bsize / 4 + 1;
+ else
+ bsize = bsize / 4;
+
+ flags = (u32)bsize | ((u64)bstype << 32);
+
+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, bin_buf, flags, 0);
+ if (ret)
+ debug("PL FPGA LOAD fail\n");
+
+ return ret;
+}
+
+struct xilinx_fpga_op zynqmp_op = {
+ .load = zynqmp_load,
+};
diff --git a/drivers/gpio/adi_gpio2.c b/drivers/gpio/adi_gpio2.c
index 88cd65b..4db08a3 100644
--- a/drivers/gpio/adi_gpio2.c
+++ b/drivers/gpio/adi_gpio2.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#define RESOURCE_LABEL_SIZE 16
diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c
index 7adea88..cb90b02 100644
--- a/drivers/gpio/atmel_pio4.c
+++ b/drivers/gpio/atmel_pio4.c
@@ -284,27 +284,15 @@
struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct atmel_pioctrl_data *pioctrl_data;
- struct udevice *dev_clk;
struct clk clk;
fdt_addr_t addr_base;
u32 nbanks;
- int periph;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
- periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1);
- if (periph < 0)
- return -EINVAL;
-
- dev_clk = dev_get_parent(clk.dev);
- ret = clk_request(dev_clk, &clk);
- if (ret)
- return ret;
-
- clk.id = periph;
ret = clk_enable(&clk);
if (ret)
return ret;
diff --git a/drivers/gpio/bcm2835_gpio.c b/drivers/gpio/bcm2835_gpio.c
index 8dd7a28..cd5480e 100644
--- a/drivers/gpio/bcm2835_gpio.c
+++ b/drivers/gpio/bcm2835_gpio.c
@@ -10,6 +10,7 @@
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <fdtdec.h>
struct bcm2835_gpios {
struct bcm2835_gpio_regs *reg;
@@ -118,9 +119,32 @@
return 0;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id bcm2835_gpio_id[] = {
+ {.compatible = "brcm,bcm2835-gpio"},
+ {}
+};
+
+static int bcm2835_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+ struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->base = addr;
+ return 0;
+}
+#endif
+
U_BOOT_DRIVER(gpio_bcm2835) = {
.name = "gpio_bcm2835",
.id = UCLASS_GPIO,
+ .of_match = of_match_ptr(bcm2835_gpio_id),
+ .ofdata_to_platdata = of_match_ptr(bcm2835_gpio_ofdata_to_platdata),
+ .platdata_auto_alloc_size = sizeof(struct bcm2835_gpio_platdata),
.ops = &gpio_bcm2835_ops,
.probe = bcm2835_gpio_probe,
.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c
index 72cec48..85e0a86 100644
--- a/drivers/gpio/dwapb_gpio.c
+++ b/drivers/gpio/dwapb_gpio.c
@@ -19,8 +19,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define GPIO_SWPORTA_DR 0x00
-#define GPIO_SWPORTA_DDR 0x04
+#define GPIO_SWPORT_DR(p) (0x00 + (p) * 0xc)
+#define GPIO_SWPORT_DDR(p) (0x04 + (p) * 0xc)
#define GPIO_INTEN 0x30
#define GPIO_INTMASK 0x34
#define GPIO_INTTYPE_LEVEL 0x38
@@ -28,7 +28,7 @@
#define GPIO_INTSTATUS 0x40
#define GPIO_PORTA_DEBOUNCE 0x48
#define GPIO_PORTA_EOI 0x4c
-#define GPIO_EXT_PORTA 0x50
+#define GPIO_EXT_PORT(p) (0x50 + (p) * 4)
struct gpio_dwapb_platdata {
const char *name;
@@ -41,7 +41,7 @@
{
struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
- clrbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin);
+ clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
return 0;
}
@@ -50,12 +50,12 @@
{
struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
- setbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin);
+ setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
if (val)
- setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+ setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
else
- clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+ clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
return 0;
}
@@ -63,7 +63,7 @@
static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin)
{
struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
- return !!(readl(plat->base + GPIO_EXT_PORTA) & (1 << pin));
+ return !!(readl(plat->base + GPIO_EXT_PORT(plat->bank)) & (1 << pin));
}
@@ -72,9 +72,9 @@
struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
if (val)
- setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+ setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
else
- clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+ clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
return 0;
}
@@ -132,7 +132,8 @@
plat->base = base;
plat->bank = bank;
plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0);
- ret = fdt_get_string(blob, node, "bank-name", &plat->name);
+ plat->name = fdt_stringlist_get(blob, node, "bank-name", 0,
+ NULL);
if (ret)
goto err;
diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c
index afb27a3..ad11764 100644
--- a/drivers/gpio/gpio-uniphier.c
+++ b/drivers/gpio/gpio-uniphier.c
@@ -10,7 +10,7 @@
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#define UNIPHIER_GPIO_PORTS_PER_BANK 8
diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c
index 8b50900..81ce446 100644
--- a/drivers/gpio/intel_broadwell_gpio.c
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -9,6 +9,7 @@
#include <fdtdec.h>
#include <pch.h>
#include <pci.h>
+#include <syscon.h>
#include <asm/cpu.h>
#include <asm/gpio.h>
#include <asm/io.h>
@@ -118,6 +119,12 @@
struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_bank_priv *priv = dev_get_priv(dev);
+ struct udevice *pinctrl;
+ int ret;
+
+ /* Set up pin control if available */
+ ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
+ debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c
index 888aa07..407385b 100644
--- a/drivers/gpio/mvgpio.c
+++ b/drivers/gpio/mvgpio.c
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
@@ -11,7 +11,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "mvgpio.h"
#include <asm/gpio.h>
diff --git a/drivers/gpio/mvgpio.h b/drivers/gpio/mvgpio.h
index 1de7395..1eb7acd 100644
--- a/drivers/gpio/mvgpio.h
+++ b/drivers/gpio/mvgpio.h
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index c25b4c1..367b852 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index cd960dc..f906b97 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -23,7 +23,7 @@
#include <fdtdec.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <malloc.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/gpio/pca9698.c b/drivers/gpio/pca9698.c
index 3152bf6..d2663f7 100644
--- a/drivers/gpio/pca9698.c
+++ b/drivers/gpio/pca9698.c
@@ -11,7 +11,7 @@
#include <common.h>
#include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <pca9698.h>
/*
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 64abcba..5dbd228 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index 50f86d3..ff245db 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -13,7 +13,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 4ab2356..64579a1 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -12,7 +12,7 @@
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <dm.h>
#include <fdtdec.h>
@@ -325,7 +325,6 @@
.get_value = zynq_gpio_get_value,
.set_value = zynq_gpio_set_value,
.get_function = zynq_gpio_get_function,
-
};
static const struct udevice_id zynq_gpio_ids[] = {
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 1537b67..051f911 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -109,6 +109,14 @@
the I2C API meaning that any I2C operations will immediately fail
for now.
+config SYS_I2C_MXC
+ bool "NXP i.MX I2C driver"
+ depends on MX6
+ help
+ Add support for the NXP i.MX I2C driver. This supports upto for bus
+ channels and operating on standard mode upto 100 kbits/s and fast
+ mode upto 400 kbits/s.
+
config SYS_I2C_ROCKCHIP
bool "Rockchip I2C driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 2987081..7c86198 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -34,7 +34,7 @@
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
-obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
+obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c
index f0c0841..d340639 100644
--- a/drivers/i2c/adi_i2c.c
+++ b/drivers/i2c/adi_i2c.c
@@ -4,6 +4,9 @@
* Copyright (c) 2006-2014 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/at91_i2c.c b/drivers/i2c/at91_i2c.c
index 8e9c3ad..4bc54ee 100644
--- a/drivers/i2c/at91_i2c.c
+++ b/drivers/i2c/at91_i2c.c
@@ -8,7 +8,7 @@
#include <asm/io.h>
#include <common.h>
-#include <clk_client.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
@@ -176,37 +176,21 @@
static int at91_i2c_enable_clk(struct udevice *dev)
{
struct at91_i2c_bus *bus = dev_get_priv(dev);
- struct udevice *dev_clk;
struct clk clk;
ulong clk_rate;
- int periph;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return -EINVAL;
- periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1);
- if (periph < 0)
- return -EINVAL;
-
- dev_clk = dev_get_parent(clk.dev);
- ret = clk_request(dev_clk, &clk);
- if (ret)
- return ret;
-
- clk.id = periph;
ret = clk_enable(&clk);
if (ret)
return ret;
- ret = clk_get_by_index(dev_clk, 0, &clk);
- if (ret)
- return ret;
-
clk_rate = clk_get_rate(&clk);
if (!clk_rate)
- return -ENODEV;
+ return -EINVAL;
bus->bus_clk_rate = clk_rate;
diff --git a/drivers/i2c/cros_ec_tunnel.c b/drivers/i2c/cros_ec_tunnel.c
index e2c6e44..9cf8e7d 100644
--- a/drivers/i2c/cros_ec_tunnel.c
+++ b/drivers/i2c/cros_ec_tunnel.c
@@ -11,6 +11,12 @@
#include <errno.h>
#include <i2c.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cros_ec_i2c_bus {
+ int remote_bus;
+};
+
static int cros_ec_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
return 0;
@@ -19,7 +25,21 @@
static int cros_ec_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
int nmsgs)
{
- return cros_ec_i2c_tunnel(dev->parent, msg, nmsgs);
+ struct cros_ec_i2c_bus *i2c_bus = dev_get_priv(dev);
+
+ return cros_ec_i2c_tunnel(dev->parent, i2c_bus->remote_bus, msg, nmsgs);
+}
+
+static int cros_ec_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct cros_ec_i2c_bus *i2c_bus = dev_get_priv(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+
+ i2c_bus->remote_bus = fdtdec_get_uint(blob, node, "google,remote-bus",
+ 0);
+
+ return 0;
}
static const struct dm_i2c_ops cros_ec_i2c_ops = {
@@ -36,5 +56,7 @@
.name = "cros_ec_tunnel",
.id = UCLASS_I2C,
.of_match = cros_ec_i2c_ids,
+ .ofdata_to_platdata = cros_ec_i2c_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct cros_ec_i2c_bus),
.ops = &cros_ec_i2c_ops,
};
diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c
index 9ca99c4..c5bd38c 100644
--- a/drivers/i2c/davinci_i2c.c
+++ b/drivers/i2c/davinci_i2c.c
@@ -7,6 +7,9 @@
* --------------------------------------------------------
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index e60fd0a..c68ff64 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -249,6 +249,7 @@
int alen, u8 *buffer, int len)
{
unsigned long start_time_rx;
+ unsigned int active = 0;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
@@ -274,18 +275,28 @@
start_time_rx = get_timer(0);
while (len) {
- if (len == 1)
- writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
- else
- writel(IC_CMD, &i2c_base->ic_cmd_data);
+ if (!active) {
+ /*
+ * Avoid writing to ic_cmd_data multiple times
+ * in case this loop spins too quickly and the
+ * ic_status RFNE bit isn't set after the first
+ * write. Subsequent writes to ic_cmd_data can
+ * trigger spurious i2c transfer.
+ */
+ if (len == 1)
+ writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
+ else
+ writel(IC_CMD, &i2c_base->ic_cmd_data);
+ active = 1;
+ }
if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
len--;
start_time_rx = get_timer(0);
-
+ active = 0;
} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
- return 1;
+ return 1;
}
}
diff --git a/drivers/i2c/exynos_hs_i2c.c b/drivers/i2c/exynos_hs_i2c.c
new file mode 100644
index 0000000..9521aeb
--- /dev/null
+++ b/drivers/i2c/exynos_hs_i2c.c
@@ -0,0 +1,561 @@
+/*
+ * Copyright (c) 2016, Google Inc
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pinmux.h>
+#include "s3c24x0_i2c.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* HSI2C-specific register description */
+
+/* I2C_CTL Register bits */
+#define HSI2C_FUNC_MODE_I2C (1u << 0)
+#define HSI2C_MASTER (1u << 3)
+#define HSI2C_RXCHON (1u << 6) /* Write/Send */
+#define HSI2C_TXCHON (1u << 7) /* Read/Receive */
+#define HSI2C_SW_RST (1u << 31)
+
+/* I2C_FIFO_CTL Register bits */
+#define HSI2C_RXFIFO_EN (1u << 0)
+#define HSI2C_TXFIFO_EN (1u << 1)
+#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
+#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
+
+/* I2C_TRAILING_CTL Register bits */
+#define HSI2C_TRAILING_COUNT (0xff)
+
+/* I2C_INT_EN Register bits */
+#define HSI2C_TX_UNDERRUN_EN (1u << 2)
+#define HSI2C_TX_OVERRUN_EN (1u << 3)
+#define HSI2C_RX_UNDERRUN_EN (1u << 4)
+#define HSI2C_RX_OVERRUN_EN (1u << 5)
+#define HSI2C_INT_TRAILING_EN (1u << 6)
+#define HSI2C_INT_I2C_EN (1u << 9)
+
+#define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
+ HSI2C_TX_OVERRUN_EN |\
+ HSI2C_RX_UNDERRUN_EN |\
+ HSI2C_RX_OVERRUN_EN |\
+ HSI2C_INT_TRAILING_EN)
+
+/* I2C_CONF Register bits */
+#define HSI2C_AUTO_MODE (1u << 31)
+#define HSI2C_10BIT_ADDR_MODE (1u << 30)
+#define HSI2C_HS_MODE (1u << 29)
+
+/* I2C_AUTO_CONF Register bits */
+#define HSI2C_READ_WRITE (1u << 16)
+#define HSI2C_STOP_AFTER_TRANS (1u << 17)
+#define HSI2C_MASTER_RUN (1u << 31)
+
+/* I2C_TIMEOUT Register bits */
+#define HSI2C_TIMEOUT_EN (1u << 31)
+
+/* I2C_TRANS_STATUS register bits */
+#define HSI2C_MASTER_BUSY (1u << 17)
+#define HSI2C_SLAVE_BUSY (1u << 16)
+#define HSI2C_TIMEOUT_AUTO (1u << 4)
+#define HSI2C_NO_DEV (1u << 3)
+#define HSI2C_NO_DEV_ACK (1u << 2)
+#define HSI2C_TRANS_ABORT (1u << 1)
+#define HSI2C_TRANS_SUCCESS (1u << 0)
+#define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
+ HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
+ HSI2C_TRANS_ABORT)
+#define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
+
+
+/* I2C_FIFO_STAT Register bits */
+#define HSI2C_RX_FIFO_EMPTY (1u << 24)
+#define HSI2C_RX_FIFO_FULL (1u << 23)
+#define HSI2C_TX_FIFO_EMPTY (1u << 8)
+#define HSI2C_TX_FIFO_FULL (1u << 7)
+#define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
+#define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
+
+#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
+
+#define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
+
+/*
+ * Wait for transfer completion.
+ *
+ * This function reads the interrupt status register waiting for the INT_I2C
+ * bit to be set, which indicates copletion of a transaction.
+ *
+ * @param i2c: pointer to the appropriate register bank
+ *
+ * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
+ * the status bits do not get set in time, or an approrpiate error
+ * value in case of transfer errors.
+ */
+static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
+{
+ int i = HSI2C_TIMEOUT_US;
+
+ while (i-- > 0) {
+ u32 int_status = readl(&i2c->usi_int_stat);
+
+ if (int_status & HSI2C_INT_I2C_EN) {
+ u32 trans_status = readl(&i2c->usi_trans_status);
+
+ /* Deassert pending interrupt. */
+ writel(int_status, &i2c->usi_int_stat);
+
+ if (trans_status & HSI2C_NO_DEV_ACK) {
+ debug("%s: no ACK from device\n", __func__);
+ return I2C_NACK;
+ }
+ if (trans_status & HSI2C_NO_DEV) {
+ debug("%s: no device\n", __func__);
+ return I2C_NOK;
+ }
+ if (trans_status & HSI2C_TRANS_ABORT) {
+ debug("%s: arbitration lost\n", __func__);
+ return I2C_NOK_LA;
+ }
+ if (trans_status & HSI2C_TIMEOUT_AUTO) {
+ debug("%s: device timed out\n", __func__);
+ return I2C_NOK_TOUT;
+ }
+ return I2C_OK;
+ }
+ udelay(1);
+ }
+ debug("%s: transaction timeout!\n", __func__);
+ return I2C_NOK_TOUT;
+}
+
+static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
+{
+ struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
+ ulong clkin;
+ unsigned int op_clk = i2c_bus->clock_frequency;
+ unsigned int i = 0, utemp0 = 0, utemp1 = 0;
+ unsigned int t_ftl_cycle;
+
+#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
+ clkin = get_i2c_clk();
+#else
+ clkin = get_PCLK();
+#endif
+ /* FPCLK / FI2C =
+ * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
+ * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
+ * uTemp1 = (TSCLK_L + TSCLK_H + 2)
+ * uTemp2 = TSCLK_L + TSCLK_H
+ */
+ t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
+ utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
+
+ /* CLK_DIV max is 256 */
+ for (i = 0; i < 256; i++) {
+ utemp1 = utemp0 / (i + 1);
+ if ((utemp1 < 512) && (utemp1 > 4)) {
+ i2c_bus->clk_cycle = utemp1 - 2;
+ i2c_bus->clk_div = i;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
+{
+ struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
+ unsigned int t_sr_release;
+ unsigned int n_clkdiv;
+ unsigned int t_start_su, t_start_hd;
+ unsigned int t_stop_su;
+ unsigned int t_data_su, t_data_hd;
+ unsigned int t_scl_l, t_scl_h;
+ u32 i2c_timing_s1;
+ u32 i2c_timing_s2;
+ u32 i2c_timing_s3;
+ u32 i2c_timing_sla;
+
+ n_clkdiv = i2c_bus->clk_div;
+ t_scl_l = i2c_bus->clk_cycle / 2;
+ t_scl_h = i2c_bus->clk_cycle / 2;
+ t_start_su = t_scl_l;
+ t_start_hd = t_scl_l;
+ t_stop_su = t_scl_l;
+ t_data_su = t_scl_l / 2;
+ t_data_hd = t_scl_l / 2;
+ t_sr_release = i2c_bus->clk_cycle;
+
+ i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
+ i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
+ i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
+ i2c_timing_sla = t_data_hd << 0;
+
+ writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
+
+ /* Clear to enable Timeout */
+ clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
+
+ /* set AUTO mode */
+ writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
+
+ /* Enable completion conditions' reporting. */
+ writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
+
+ /* Enable FIFOs */
+ writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
+
+ /* Currently operating in Fast speed mode. */
+ writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
+ writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
+ writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
+ writel(i2c_timing_sla, &hsregs->usi_timing_sla);
+}
+
+/* SW reset for the high speed bus */
+static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
+{
+ struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
+ u32 i2c_ctl;
+
+ /* Set and clear the bit for reset */
+ i2c_ctl = readl(&i2c->usi_ctl);
+ i2c_ctl |= HSI2C_SW_RST;
+ writel(i2c_ctl, &i2c->usi_ctl);
+
+ i2c_ctl = readl(&i2c->usi_ctl);
+ i2c_ctl &= ~HSI2C_SW_RST;
+ writel(i2c_ctl, &i2c->usi_ctl);
+
+ /* Initialize the configure registers */
+ hsi2c_ch_init(i2c_bus);
+}
+
+/*
+ * Poll the appropriate bit of the fifo status register until the interface is
+ * ready to process the next byte or timeout expires.
+ *
+ * In addition to the FIFO status register this function also polls the
+ * interrupt status register to be able to detect unexpected transaction
+ * completion.
+ *
+ * When FIFO is ready to process the next byte, this function returns I2C_OK.
+ * If in course of polling the INT_I2C assertion is detected, the function
+ * returns I2C_NOK. If timeout happens before any of the above conditions is
+ * met - the function returns I2C_NOK_TOUT;
+
+ * @param i2c: pointer to the appropriate i2c register bank.
+ * @param rx_transfer: set to True if the receive transaction is in progress.
+ * @return: as described above.
+ */
+static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
+{
+ u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
+ int i = HSI2C_TIMEOUT_US;
+
+ while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
+ if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
+ /*
+ * There is a chance that assertion of
+ * HSI2C_INT_I2C_EN and deassertion of
+ * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
+ * give FIFO status priority and check it one more
+ * time before reporting interrupt. The interrupt will
+ * be reported next time this function is called.
+ */
+ if (rx_transfer &&
+ !(readl(&i2c->usi_fifo_stat) & fifo_bit))
+ break;
+ return I2C_NOK;
+ }
+ if (!i--) {
+ debug("%s: FIFO polling timeout!\n", __func__);
+ return I2C_NOK_TOUT;
+ }
+ udelay(1);
+ }
+ return I2C_OK;
+}
+
+/*
+ * Preapre hsi2c transaction, either read or write.
+ *
+ * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
+ * the 5420 UM.
+ *
+ * @param i2c: pointer to the appropriate i2c register bank.
+ * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
+ * @param len: number of bytes expected to be sent or received
+ * @param rx_transfer: set to true for receive transactions
+ * @param: issue_stop: set to true if i2c stop condition should be generated
+ * after this transaction.
+ * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
+ * I2C_OK otherwise.
+ */
+static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
+ u8 chip,
+ u16 len,
+ bool rx_transfer,
+ bool issue_stop)
+{
+ u32 conf;
+
+ conf = len | HSI2C_MASTER_RUN;
+
+ if (issue_stop)
+ conf |= HSI2C_STOP_AFTER_TRANS;
+
+ /* Clear to enable Timeout */
+ writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
+
+ /* Set slave address */
+ writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
+
+ if (rx_transfer) {
+ /* i2c master, read transaction */
+ writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
+ &i2c->usi_ctl);
+
+ /* read up to len bytes, stop after transaction is finished */
+ writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
+ } else {
+ /* i2c master, write transaction */
+ writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
+ &i2c->usi_ctl);
+
+ /* write up to len bytes, stop after transaction is finished */
+ writel(conf, &i2c->usi_auto_conf);
+ }
+
+ /* Reset all pending interrupt status bits we care about, if any */
+ writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
+
+ return I2C_OK;
+}
+
+/*
+ * Wait while i2c bus is settling down (mostly stop gets completed).
+ */
+static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
+{
+ int i = HSI2C_TIMEOUT_US;
+
+ while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
+ if (!i--) {
+ debug("%s: bus busy\n", __func__);
+ return I2C_NOK_TOUT;
+ }
+ udelay(1);
+ }
+ return I2C_OK;
+}
+
+static int hsi2c_write(struct exynos5_hsi2c *i2c,
+ unsigned char chip,
+ unsigned char addr[],
+ unsigned char alen,
+ unsigned char data[],
+ unsigned short len,
+ bool issue_stop)
+{
+ int i, rv = 0;
+
+ if (!(len + alen)) {
+ /* Writes of zero length not supported in auto mode. */
+ debug("%s: zero length writes not supported\n", __func__);
+ return I2C_NOK;
+ }
+
+ rv = hsi2c_prepare_transaction
+ (i2c, chip, len + alen, false, issue_stop);
+ if (rv != I2C_OK)
+ return rv;
+
+ /* Move address, if any, and the data, if any, into the FIFO. */
+ for (i = 0; i < alen; i++) {
+ rv = hsi2c_poll_fifo(i2c, false);
+ if (rv != I2C_OK) {
+ debug("%s: address write failed\n", __func__);
+ goto write_error;
+ }
+ writel(addr[i], &i2c->usi_txdata);
+ }
+
+ for (i = 0; i < len; i++) {
+ rv = hsi2c_poll_fifo(i2c, false);
+ if (rv != I2C_OK) {
+ debug("%s: data write failed\n", __func__);
+ goto write_error;
+ }
+ writel(data[i], &i2c->usi_txdata);
+ }
+
+ rv = hsi2c_wait_for_trx(i2c);
+
+ write_error:
+ if (issue_stop) {
+ int tmp_ret = hsi2c_wait_while_busy(i2c);
+ if (rv == I2C_OK)
+ rv = tmp_ret;
+ }
+
+ writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
+ return rv;
+}
+
+static int hsi2c_read(struct exynos5_hsi2c *i2c,
+ unsigned char chip,
+ unsigned char addr[],
+ unsigned char alen,
+ unsigned char data[],
+ unsigned short len)
+{
+ int i, rv, tmp_ret;
+ bool drop_data = false;
+
+ if (!len) {
+ /* Reads of zero length not supported in auto mode. */
+ debug("%s: zero length read adjusted\n", __func__);
+ drop_data = true;
+ len = 1;
+ }
+
+ if (alen) {
+ /* Internal register adress needs to be written first. */
+ rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
+ if (rv != I2C_OK)
+ return rv;
+ }
+
+ rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
+
+ if (rv != I2C_OK)
+ return rv;
+
+ for (i = 0; i < len; i++) {
+ rv = hsi2c_poll_fifo(i2c, true);
+ if (rv != I2C_OK)
+ goto read_err;
+ if (drop_data)
+ continue;
+ data[i] = readl(&i2c->usi_rxdata);
+ }
+
+ rv = hsi2c_wait_for_trx(i2c);
+
+ read_err:
+ tmp_ret = hsi2c_wait_while_busy(i2c);
+ if (rv == I2C_OK)
+ rv = tmp_ret;
+
+ writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
+ return rv;
+}
+
+static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
+ struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
+ int ret;
+
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ if (msg->flags & I2C_M_RD) {
+ ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
+ msg->len);
+ } else {
+ ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
+ msg->len, true);
+ }
+ if (ret) {
+ exynos5_i2c_reset(i2c_bus);
+ return -EREMOTEIO;
+ }
+ }
+
+ return 0;
+}
+
+static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
+{
+ struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
+
+ i2c_bus->clock_frequency = speed;
+
+ if (hsi2c_get_clk_details(i2c_bus))
+ return -EFAULT;
+ hsi2c_ch_init(i2c_bus);
+
+ return 0;
+}
+
+static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
+{
+ struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
+ uchar buf[1];
+ int ret;
+
+ buf[0] = 0;
+
+ /*
+ * What is needed is to send the chip address and verify that the
+ * address was <ACK>ed (i.e. there was a chip at that address which
+ * drove the data line low).
+ */
+ ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1);
+
+ return ret != I2C_OK;
+}
+
+static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ const void *blob = gd->fdt_blob;
+ struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
+ int node;
+
+ node = dev->of_offset;
+
+ i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev);
+
+ i2c_bus->id = pinmux_decode_periph_id(blob, node);
+
+ i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
+ "clock-frequency", 100000);
+ i2c_bus->node = node;
+ i2c_bus->bus_num = dev->seq;
+
+ exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE);
+
+ i2c_bus->active = true;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops exynos_hs_i2c_ops = {
+ .xfer = exynos_hs_i2c_xfer,
+ .probe_chip = s3c24x0_i2c_probe,
+ .set_bus_speed = s3c24x0_i2c_set_bus_speed,
+};
+
+static const struct udevice_id exynos_hs_i2c_ids[] = {
+ { .compatible = "samsung,exynos5-hsi2c" },
+ { }
+};
+
+U_BOOT_DRIVER(hs_i2c) = {
+ .name = "i2c_s3c_hs",
+ .id = UCLASS_I2C,
+ .of_match = exynos_hs_i2c_ids,
+ .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
+ .ops = &exynos_hs_i2c_ops,
+};
diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
index 68d9a42..b35d0d2 100644
--- a/drivers/i2c/fti2c010.c
+++ b/drivers/i2c/fti2c010.c
@@ -5,6 +5,9 @@
* Dante Su <dantesu@faraday-tech.com>
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 5642cd9..f49f60b 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -11,7 +11,7 @@
#include <common.h>
#include <linux/types.h>
#include <linux/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <dm/device.h>
#include <dm/root.h>
#include <i2c.h>
diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c
index a56e058..8bfa916 100644
--- a/drivers/i2c/i2c-uniphier-f.c
+++ b/drivers/i2c/i2c-uniphier-f.c
@@ -10,7 +10,7 @@
#include <linux/types.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <dm/device.h>
#include <dm/root.h>
#include <i2c.h>
diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c
index 39a3ebd..f391f11 100644
--- a/drivers/i2c/i2c-uniphier.c
+++ b/drivers/i2c/i2c-uniphier.c
@@ -10,7 +10,7 @@
#include <linux/types.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <dm/device.h>
#include <dm/root.h>
#include <i2c.h>
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
index b05c15f..29612e6 100644
--- a/drivers/i2c/ihs_i2c.c
+++ b/drivers/i2c/ihs_i2c.c
@@ -3,6 +3,9 @@
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c
index a0182dc..550a728 100644
--- a/drivers/i2c/intel_i2c.c
+++ b/drivers/i2c/intel_i2c.c
@@ -248,11 +248,11 @@
static int intel_i2c_probe(struct udevice *dev)
{
struct intel_i2c *priv = dev_get_priv(dev);
- u32 base;
+ ulong base;
/* Save base address from PCI BAR */
- priv->base = (u32)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,
- PCI_REGION_IO);
+ priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,
+ PCI_REGION_IO);
base = priv->base;
/* Set SMBus enable. */
diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c
index 11f29d9..26ee202 100644
--- a/drivers/i2c/kona_i2c.c
+++ b/drivers/i2c/kona_i2c.c
@@ -2,11 +2,14 @@
* Copyright 2013 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include <i2c.h>
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 47163cc..b0167ab 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -5,12 +5,15 @@
* Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
#include <asm/io.h>
#include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/clk.h>
/*
diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index fc02e65..c780272 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -18,18 +18,11 @@
*/
#include <common.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_HARD_I2C
+#include <dm.h>
#include <i2c.h>
+#include <asm/io.h>
#include "mv_i2c.h"
-#ifdef DEBUG_I2C
-#define PRINTD(x) printf x
-#else
-#define PRINTD(x)
-#endif
-
/* All transfers are described by this data structure */
struct mv_i2c_msg {
u8 condition;
@@ -38,6 +31,16 @@
u8 data;
};
+#ifdef CONFIG_ARMADA_3700
+/* Armada 3700 has no padding between the registers */
+struct mv_i2c {
+ u32 ibmr;
+ u32 idbr;
+ u32 icr;
+ u32 isr;
+ u32 isar;
+};
+#else
struct mv_i2c {
u32 ibmr;
u32 pad0;
@@ -49,8 +52,327 @@
u32 pad3;
u32 isar;
};
+#endif
-static struct mv_i2c *base;
+/*
+ * Dummy implementation that can be overwritten by a board
+ * specific function
+ */
+__weak void i2c_clk_enable(void)
+{
+}
+
+/*
+ * i2c_reset: - reset the host controller
+ *
+ */
+static void i2c_reset(struct mv_i2c *base)
+{
+ u32 icr_mode;
+
+ /* Save bus mode (standard or fast speed) for later use */
+ icr_mode = readl(&base->icr) & ICR_MODE_MASK;
+ writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
+ writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
+ udelay(100);
+ writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
+
+ i2c_clk_enable();
+
+ writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
+ /* set control reg values */
+ writel(I2C_ICR_INIT | icr_mode, &base->icr);
+ writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
+ writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
+ udelay(100);
+}
+
+/*
+ * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
+ * are set and cleared
+ *
+ * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
+ */
+static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
+ unsigned long cleared_mask)
+{
+ int timeout = 1000, isr;
+
+ do {
+ isr = readl(&base->isr);
+ udelay(10);
+ if (timeout-- < 0)
+ return 0;
+ } while (((isr & set_mask) != set_mask)
+ || ((isr & cleared_mask) != 0));
+
+ return 1;
+}
+
+/*
+ * i2c_transfer: - Transfer one byte over the i2c bus
+ *
+ * This function can tranfer a byte over the i2c bus in both directions.
+ * It is used by the public API functions.
+ *
+ * @return: 0: transfer successful
+ * -1: message is empty
+ * -2: transmit timeout
+ * -3: ACK missing
+ * -4: receive timeout
+ * -5: illegal parameters
+ * -6: bus is busy and couldn't be aquired
+ */
+static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
+{
+ int ret;
+
+ if (!msg)
+ goto transfer_error_msg_empty;
+
+ switch (msg->direction) {
+ case I2C_WRITE:
+ /* check if bus is not busy */
+ if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
+ goto transfer_error_bus_busy;
+
+ /* start transmission */
+ writel(readl(&base->icr) & ~ICR_START, &base->icr);
+ writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
+ writel(msg->data, &base->idbr);
+ if (msg->condition == I2C_COND_START)
+ writel(readl(&base->icr) | ICR_START, &base->icr);
+ if (msg->condition == I2C_COND_STOP)
+ writel(readl(&base->icr) | ICR_STOP, &base->icr);
+ if (msg->acknack == I2C_ACKNAK_SENDNAK)
+ writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
+ if (msg->acknack == I2C_ACKNAK_SENDACK)
+ writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
+ writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
+ writel(readl(&base->icr) | ICR_TB, &base->icr);
+
+ /* transmit register empty? */
+ if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
+ goto transfer_error_transmit_timeout;
+
+ /* clear 'transmit empty' state */
+ writel(readl(&base->isr) | ISR_ITE, &base->isr);
+
+ /* wait for ACK from slave */
+ if (msg->acknack == I2C_ACKNAK_WAITACK)
+ if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
+ goto transfer_error_ack_missing;
+ break;
+
+ case I2C_READ:
+
+ /* check if bus is not busy */
+ if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
+ goto transfer_error_bus_busy;
+
+ /* start receive */
+ writel(readl(&base->icr) & ~ICR_START, &base->icr);
+ writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
+ if (msg->condition == I2C_COND_START)
+ writel(readl(&base->icr) | ICR_START, &base->icr);
+ if (msg->condition == I2C_COND_STOP)
+ writel(readl(&base->icr) | ICR_STOP, &base->icr);
+ if (msg->acknack == I2C_ACKNAK_SENDNAK)
+ writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
+ if (msg->acknack == I2C_ACKNAK_SENDACK)
+ writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
+ writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
+ writel(readl(&base->icr) | ICR_TB, &base->icr);
+
+ /* receive register full? */
+ if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
+ goto transfer_error_receive_timeout;
+
+ msg->data = readl(&base->idbr);
+
+ /* clear 'receive empty' state */
+ writel(readl(&base->isr) | ISR_IRF, &base->isr);
+ break;
+ default:
+ goto transfer_error_illegal_param;
+ }
+
+ return 0;
+
+transfer_error_msg_empty:
+ debug("i2c_transfer: error: 'msg' is empty\n");
+ ret = -1;
+ goto i2c_transfer_finish;
+
+transfer_error_transmit_timeout:
+ debug("i2c_transfer: error: transmit timeout\n");
+ ret = -2;
+ goto i2c_transfer_finish;
+
+transfer_error_ack_missing:
+ debug("i2c_transfer: error: ACK missing\n");
+ ret = -3;
+ goto i2c_transfer_finish;
+
+transfer_error_receive_timeout:
+ debug("i2c_transfer: error: receive timeout\n");
+ ret = -4;
+ goto i2c_transfer_finish;
+
+transfer_error_illegal_param:
+ debug("i2c_transfer: error: illegal parameters\n");
+ ret = -5;
+ goto i2c_transfer_finish;
+
+transfer_error_bus_busy:
+ debug("i2c_transfer: error: bus is busy\n");
+ ret = -6;
+ goto i2c_transfer_finish;
+
+i2c_transfer_finish:
+ debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
+ i2c_reset(base);
+ return ret;
+}
+
+static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
+ uchar *buffer, int len)
+{
+ struct mv_i2c_msg msg;
+
+ debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
+ "len=0x%02x)\n", chip, *addr, alen, len);
+
+ if (len == 0) {
+ printf("reading zero byte is invalid\n");
+ return -EINVAL;
+ }
+
+ i2c_reset(base);
+
+ /* dummy chip address write */
+ debug("i2c_read: dummy chip address write\n");
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1);
+ msg.data &= 0xFE;
+ if (i2c_transfer(base, &msg))
+ return -1;
+
+ /*
+ * send memory address bytes;
+ * alen defines how much bytes we have to send.
+ */
+ while (--alen >= 0) {
+ debug("i2c_read: send address byte %02x (alen=%d)\n",
+ *addr, alen);
+ msg.condition = I2C_COND_NORMAL;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = addr[alen];
+ if (i2c_transfer(base, &msg))
+ return -1;
+ }
+
+ /* start read sequence */
+ debug("i2c_read: start read sequence\n");
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1);
+ msg.data |= 0x01;
+ if (i2c_transfer(base, &msg))
+ return -1;
+
+ /* read bytes; send NACK at last byte */
+ while (len--) {
+ if (len == 0) {
+ msg.condition = I2C_COND_STOP;
+ msg.acknack = I2C_ACKNAK_SENDNAK;
+ } else {
+ msg.condition = I2C_COND_NORMAL;
+ msg.acknack = I2C_ACKNAK_SENDACK;
+ }
+
+ msg.direction = I2C_READ;
+ msg.data = 0x00;
+ if (i2c_transfer(base, &msg))
+ return -1;
+
+ *buffer = msg.data;
+ debug("i2c_read: reading byte (%p)=0x%02x\n",
+ buffer, *buffer);
+ buffer++;
+ }
+
+ i2c_reset(base);
+
+ return 0;
+}
+
+static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
+ uchar *buffer, int len)
+{
+ struct mv_i2c_msg msg;
+
+ debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
+ "len=0x%02x)\n", chip, *addr, alen, len);
+
+ i2c_reset(base);
+
+ /* chip address write */
+ debug("i2c_write: chip address write\n");
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1);
+ msg.data &= 0xFE;
+ if (i2c_transfer(base, &msg))
+ return -1;
+
+ /*
+ * send memory address bytes;
+ * alen defines how much bytes we have to send.
+ */
+ while (--alen >= 0) {
+ debug("i2c_read: send address byte %02x (alen=%d)\n",
+ *addr, alen);
+ msg.condition = I2C_COND_NORMAL;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = addr[alen];
+ if (i2c_transfer(base, &msg))
+ return -1;
+ }
+
+ /* write bytes; send NACK at last byte */
+ while (len--) {
+ debug("i2c_write: writing byte (%p)=0x%02x\n",
+ buffer, *buffer);
+
+ if (len == 0)
+ msg.condition = I2C_COND_STOP;
+ else
+ msg.condition = I2C_COND_NORMAL;
+
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = *(buffer++);
+
+ if (i2c_transfer(base, &msg))
+ return -1;
+ }
+
+ i2c_reset(base);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_I2C
+
+static struct mv_i2c *base_glob;
+
static void i2c_board_init(struct mv_i2c *base)
{
#ifdef CONFIG_SYS_I2C_INIT_BOARD
@@ -84,11 +406,11 @@
return -1;
}
- base = (struct mv_i2c *)i2c_regs[bus];
+ base_glob = (struct mv_i2c *)i2c_regs[bus];
current_bus = bus;
if (!bus_initialized[current_bus]) {
- i2c_board_init(base);
+ i2c_board_init(base_glob);
bus_initialized[current_bus] = 1;
}
@@ -101,181 +423,48 @@
}
#endif
-/*
- * i2c_reset: - reset the host controller
- *
- */
-static void i2c_reset(void)
-{
- writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
- writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
- udelay(100);
- writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
-
- i2c_clk_enable();
-
- writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
- writel(I2C_ICR_INIT, &base->icr); /* set control reg values */
- writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
- writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
- udelay(100);
-}
-
-/*
- * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
- * are set and cleared
- *
- * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
- */
-static int i2c_isr_set_cleared(unsigned long set_mask,
- unsigned long cleared_mask)
-{
- int timeout = 1000, isr;
-
- do {
- isr = readl(&base->isr);
- udelay(10);
- if (timeout-- < 0)
- return 0;
- } while (((isr & set_mask) != set_mask)
- || ((isr & cleared_mask) != 0));
-
- return 1;
-}
-
-/*
- * i2c_transfer: - Transfer one byte over the i2c bus
- *
- * This function can tranfer a byte over the i2c bus in both directions.
- * It is used by the public API functions.
- *
- * @return: 0: transfer successful
- * -1: message is empty
- * -2: transmit timeout
- * -3: ACK missing
- * -4: receive timeout
- * -5: illegal parameters
- * -6: bus is busy and couldn't be aquired
- */
-int i2c_transfer(struct mv_i2c_msg *msg)
-{
- int ret;
-
- if (!msg)
- goto transfer_error_msg_empty;
-
- switch (msg->direction) {
- case I2C_WRITE:
- /* check if bus is not busy */
- if (!i2c_isr_set_cleared(0, ISR_IBB))
- goto transfer_error_bus_busy;
-
- /* start transmission */
- writel(readl(&base->icr) & ~ICR_START, &base->icr);
- writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
- writel(msg->data, &base->idbr);
- if (msg->condition == I2C_COND_START)
- writel(readl(&base->icr) | ICR_START, &base->icr);
- if (msg->condition == I2C_COND_STOP)
- writel(readl(&base->icr) | ICR_STOP, &base->icr);
- if (msg->acknack == I2C_ACKNAK_SENDNAK)
- writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
- if (msg->acknack == I2C_ACKNAK_SENDACK)
- writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
- writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
- writel(readl(&base->icr) | ICR_TB, &base->icr);
-
- /* transmit register empty? */
- if (!i2c_isr_set_cleared(ISR_ITE, 0))
- goto transfer_error_transmit_timeout;
-
- /* clear 'transmit empty' state */
- writel(readl(&base->isr) | ISR_ITE, &base->isr);
-
- /* wait for ACK from slave */
- if (msg->acknack == I2C_ACKNAK_WAITACK)
- if (!i2c_isr_set_cleared(0, ISR_ACKNAK))
- goto transfer_error_ack_missing;
- break;
-
- case I2C_READ:
-
- /* check if bus is not busy */
- if (!i2c_isr_set_cleared(0, ISR_IBB))
- goto transfer_error_bus_busy;
-
- /* start receive */
- writel(readl(&base->icr) & ~ICR_START, &base->icr);
- writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
- if (msg->condition == I2C_COND_START)
- writel(readl(&base->icr) | ICR_START, &base->icr);
- if (msg->condition == I2C_COND_STOP)
- writel(readl(&base->icr) | ICR_STOP, &base->icr);
- if (msg->acknack == I2C_ACKNAK_SENDNAK)
- writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
- if (msg->acknack == I2C_ACKNAK_SENDACK)
- writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
- writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
- writel(readl(&base->icr) | ICR_TB, &base->icr);
-
- /* receive register full? */
- if (!i2c_isr_set_cleared(ISR_IRF, 0))
- goto transfer_error_receive_timeout;
-
- msg->data = readl(&base->idbr);
-
- /* clear 'receive empty' state */
- writel(readl(&base->isr) | ISR_IRF, &base->isr);
- break;
- default:
- goto transfer_error_illegal_param;
- }
-
- return 0;
-
-transfer_error_msg_empty:
- PRINTD(("i2c_transfer: error: 'msg' is empty\n"));
- ret = -1; goto i2c_transfer_finish;
-
-transfer_error_transmit_timeout:
- PRINTD(("i2c_transfer: error: transmit timeout\n"));
- ret = -2; goto i2c_transfer_finish;
-
-transfer_error_ack_missing:
- PRINTD(("i2c_transfer: error: ACK missing\n"));
- ret = -3; goto i2c_transfer_finish;
-
-transfer_error_receive_timeout:
- PRINTD(("i2c_transfer: error: receive timeout\n"));
- ret = -4; goto i2c_transfer_finish;
-
-transfer_error_illegal_param:
- PRINTD(("i2c_transfer: error: illegal parameters\n"));
- ret = -5; goto i2c_transfer_finish;
-
-transfer_error_bus_busy:
- PRINTD(("i2c_transfer: error: bus is busy\n"));
- ret = -6; goto i2c_transfer_finish;
-
-i2c_transfer_finish:
- PRINTD(("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr)));
- i2c_reset();
- return ret;
-}
-
-/* ------------------------------------------------------------------------ */
-/* API Functions */
-/* ------------------------------------------------------------------------ */
+/* API Functions */
void i2c_init(int speed, int slaveaddr)
{
+ u32 val;
+
#ifdef CONFIG_I2C_MULTI_BUS
current_bus = 0;
- base = (struct mv_i2c *)i2c_regs[current_bus];
+ base_glob = (struct mv_i2c *)i2c_regs[current_bus];
#else
- base = (struct mv_i2c *)CONFIG_MV_I2C_REG;
+ base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
#endif
- i2c_board_init(base);
+ if (speed > 100000)
+ val = ICR_FM;
+ else
+ val = ICR_SM;
+ clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
+
+ i2c_board_init(base_glob);
+}
+
+static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
+{
+ struct mv_i2c_msg msg;
+
+ i2c_reset(base);
+
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1) + 1;
+ if (i2c_transfer(base, &msg))
+ return -1;
+
+ msg.condition = I2C_COND_STOP;
+ msg.acknack = I2C_ACKNAK_SENDNAK;
+ msg.direction = I2C_READ;
+ msg.data = 0x00;
+ if (i2c_transfer(base, &msg))
+ return -1;
+
+ return 0;
}
/*
@@ -286,25 +475,7 @@
*/
int i2c_probe(uchar chip)
{
- struct mv_i2c_msg msg;
-
- i2c_reset();
-
- msg.condition = I2C_COND_START;
- msg.acknack = I2C_ACKNAK_WAITACK;
- msg.direction = I2C_WRITE;
- msg.data = (chip << 1) + 1;
- if (i2c_transfer(&msg))
- return -1;
-
- msg.condition = I2C_COND_STOP;
- msg.acknack = I2C_ACKNAK_SENDNAK;
- msg.direction = I2C_READ;
- msg.data = 0x00;
- if (i2c_transfer(&msg))
- return -1;
-
- return 0;
+ return __i2c_probe_chip(base_glob, chip);
}
/*
@@ -313,86 +484,23 @@
* The higher level routines take into account that this function is only
* called with len < page length of the device (see configuration file)
*
- * @chip: address of the chip which is to be read
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to write the data
- * @len: how much byte do we want to read
- * @return: 0 in case of success
+ * @chip: address of the chip which is to be read
+ * @addr: i2c data address within the chip
+ * @alen: length of the i2c data address (1..2 bytes)
+ * @buffer: where to write the data
+ * @len: how much byte do we want to read
+ * @return: 0 in case of success
*/
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
- struct mv_i2c_msg msg;
- u8 addr_bytes[3]; /* lowest...highest byte of data address */
+ u8 addr_bytes[4];
- PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
- "len=0x%02x)\n", chip, addr, alen, len));
+ addr_bytes[0] = (addr >> 0) & 0xFF;
+ addr_bytes[1] = (addr >> 8) & 0xFF;
+ addr_bytes[2] = (addr >> 16) & 0xFF;
+ addr_bytes[3] = (addr >> 24) & 0xFF;
- i2c_reset();
-
- /* dummy chip address write */
- PRINTD(("i2c_read: dummy chip address write\n"));
- msg.condition = I2C_COND_START;
- msg.acknack = I2C_ACKNAK_WAITACK;
- msg.direction = I2C_WRITE;
- msg.data = (chip << 1);
- msg.data &= 0xFE;
- if (i2c_transfer(&msg))
- return -1;
-
- /*
- * send memory address bytes;
- * alen defines how much bytes we have to send.
- */
- /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */
- addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
- addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
- addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
-
- while (--alen >= 0) {
- PRINTD(("i2c_read: send memory word address byte %1d\n", alen));
- msg.condition = I2C_COND_NORMAL;
- msg.acknack = I2C_ACKNAK_WAITACK;
- msg.direction = I2C_WRITE;
- msg.data = addr_bytes[alen];
- if (i2c_transfer(&msg))
- return -1;
- }
-
- /* start read sequence */
- PRINTD(("i2c_read: start read sequence\n"));
- msg.condition = I2C_COND_START;
- msg.acknack = I2C_ACKNAK_WAITACK;
- msg.direction = I2C_WRITE;
- msg.data = (chip << 1);
- msg.data |= 0x01;
- if (i2c_transfer(&msg))
- return -1;
-
- /* read bytes; send NACK at last byte */
- while (len--) {
- if (len == 0) {
- msg.condition = I2C_COND_STOP;
- msg.acknack = I2C_ACKNAK_SENDNAK;
- } else {
- msg.condition = I2C_COND_NORMAL;
- msg.acknack = I2C_ACKNAK_SENDACK;
- }
-
- msg.direction = I2C_READ;
- msg.data = 0x00;
- if (i2c_transfer(&msg))
- return -1;
-
- *buffer = msg.data;
- PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",
- (unsigned int)buffer, *buffer));
- buffer++;
- }
-
- i2c_reset();
-
- return 0;
+ return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len);
}
/*
@@ -410,62 +518,88 @@
*/
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
- struct mv_i2c_msg msg;
- u8 addr_bytes[3]; /* lowest...highest byte of data address */
+ u8 addr_bytes[4];
- PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
- "len=0x%02x)\n", chip, addr, alen, len));
+ addr_bytes[0] = (addr >> 0) & 0xFF;
+ addr_bytes[1] = (addr >> 8) & 0xFF;
+ addr_bytes[2] = (addr >> 16) & 0xFF;
+ addr_bytes[3] = (addr >> 24) & 0xFF;
- i2c_reset();
+ return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len);
+}
- /* chip address write */
- PRINTD(("i2c_write: chip address write\n"));
- msg.condition = I2C_COND_START;
- msg.acknack = I2C_ACKNAK_WAITACK;
- msg.direction = I2C_WRITE;
- msg.data = (chip << 1);
- msg.data &= 0xFE;
- if (i2c_transfer(&msg))
- return -1;
+#else /* CONFIG_DM_I2C */
+
+struct mv_i2c_priv {
+ struct mv_i2c *base;
+};
+
+static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ struct mv_i2c_priv *i2c = dev_get_priv(bus);
+ struct i2c_msg *dmsg, *omsg, dummy;
+
+ memset(&dummy, 0, sizeof(struct i2c_msg));
/*
- * send memory address bytes;
- * alen defines how much bytes we have to send.
+ * We expect either two messages (one with an offset and one with the
+ * actual data) or one message (just data or offset/data combined)
*/
- addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
- addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
- addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
-
- while (--alen >= 0) {
- PRINTD(("i2c_write: send memory word address\n"));
- msg.condition = I2C_COND_NORMAL;
- msg.acknack = I2C_ACKNAK_WAITACK;
- msg.direction = I2C_WRITE;
- msg.data = addr_bytes[alen];
- if (i2c_transfer(&msg))
- return -1;
+ if (nmsgs > 2 || nmsgs == 0) {
+ debug("%s: Only one or two messages are supported.", __func__);
+ return -1;
}
- /* write bytes; send NACK at last byte */
- while (len--) {
- PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",
- (unsigned int)buffer, *buffer));
+ omsg = nmsgs == 1 ? &dummy : msg;
+ dmsg = nmsgs == 1 ? msg : msg + 1;
- if (len == 0)
- msg.condition = I2C_COND_STOP;
- else
- msg.condition = I2C_COND_NORMAL;
+ if (dmsg->flags & I2C_M_RD)
+ return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
+ omsg->len, dmsg->buf, dmsg->len);
+ else
+ return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
+ omsg->len, dmsg->buf, dmsg->len);
+}
- msg.acknack = I2C_ACKNAK_WAITACK;
- msg.direction = I2C_WRITE;
- msg.data = *(buffer++);
+static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct mv_i2c_priv *priv = dev_get_priv(bus);
+ u32 val;
- if (i2c_transfer(&msg))
- return -1;
- }
-
- i2c_reset();
+ if (speed > 100000)
+ val = ICR_FM;
+ else
+ val = ICR_SM;
+ clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
return 0;
}
-#endif /* CONFIG_HARD_I2C */
+
+static int mv_i2c_probe(struct udevice *bus)
+{
+ struct mv_i2c_priv *priv = dev_get_priv(bus);
+
+ priv->base = (void *)dev_get_addr_ptr(bus);
+
+ return 0;
+}
+
+static const struct dm_i2c_ops mv_i2c_ops = {
+ .xfer = mv_i2c_xfer,
+ .set_bus_speed = mv_i2c_set_bus_speed,
+};
+
+static const struct udevice_id mv_i2c_ids[] = {
+ { .compatible = "marvell,armada-3700-i2c" },
+ { }
+};
+
+U_BOOT_DRIVER(i2c_mv) = {
+ .name = "i2c_mv",
+ .id = UCLASS_I2C,
+ .of_match = mv_i2c_ids,
+ .probe = mv_i2c_probe,
+ .priv_auto_alloc_size = sizeof(struct mv_i2c_priv),
+ .ops = &mv_i2c_ops,
+};
+#endif /* CONFIG_DM_I2C */
diff --git a/drivers/i2c/mv_i2c.h b/drivers/i2c/mv_i2c.h
index ae27c44..1e62892 100644
--- a/drivers/i2c/mv_i2c.h
+++ b/drivers/i2c/mv_i2c.h
@@ -23,12 +23,7 @@
#define I2C_READ 0
#define I2C_WRITE 1
-#if (CONFIG_SYS_I2C_SPEED == 400000)
-#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \
- | ICR_SCLE)
-#else
#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
-#endif
#define I2C_ISR_INIT 0x7FF
/* ----- Control register bits ---------------------------------------- */
@@ -48,7 +43,15 @@
#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
#define ICR_SADIE 0x2000 /* slave address detected int enable */
#define ICR_UR 0x4000 /* unit reset */
-#define ICR_FM 0x8000 /* Fast Mode */
+#ifdef CONFIG_ARMADA_3700
+#define ICR_SM 0x00000 /* Standard Mode */
+#define ICR_FM 0x10000 /* Fast Mode */
+#define ICR_MODE_MASK 0x30000 /* Mode mask */
+#else
+#define ICR_SM 0x00000 /* Standard Mode */
+#define ICR_FM 0x08000 /* Fast Mode */
+#define ICR_MODE_MASK 0x18000 /* Mode mask */
+#endif
/* ----- Status register bits ----------------------------------------- */
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 3765fed..cea3da0 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <linux/compat.h>
#ifdef CONFIG_DM_I2C
@@ -29,7 +29,7 @@
#include <asm/arch/orion5x.h>
#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
#include <asm/arch/soc.h>
-#elif defined(CONFIG_SUNXI)
+#elif defined(CONFIG_ARCH_SUNXI)
#include <asm/arch/i2c.h>
#else
#error Driver mvtwsi not supported by SoC or board
@@ -40,7 +40,7 @@
* TWSI register structure
*/
-#ifdef CONFIG_SUNXI
+#ifdef CONFIG_ARCH_SUNXI
struct mvtwsi_registers {
u32 slave_address;
@@ -399,7 +399,7 @@
*/
static uint twsi_calc_freq(const int n, const int m)
{
-#ifdef CONFIG_SUNXI
+#ifdef CONFIG_ARCH_SUNXI
return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
#else
return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
@@ -830,6 +830,7 @@
static const struct udevice_id mvtwsi_i2c_ids[] = {
{ .compatible = "marvell,mv64xxx-i2c", },
+ { .compatible = "marvell,mv78230-i2c", },
{ /* sentinel */ }
};
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index f340208..94d9027 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -17,7 +17,7 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/io.h>
#include <i2c.h>
@@ -773,9 +773,9 @@
* See Documentation/devicetree/bindings/i2c/i2c-imx.txt
* Use gpio to force bus idle when necessary.
*/
- ret = fdt_find_string(fdt, node, "pinctrl-names", "gpio");
+ ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
if (ret < 0) {
- dev_info(dev, "i2c bus %d at %lu, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
+ debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
} else {
ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios",
0, &i2c_bus->scl_gpio,
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index 87e05c7..d454410 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -16,7 +16,7 @@
#include <common.h>
#include <malloc.h>
#include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/i2c/pca9564_i2c.c b/drivers/i2c/pca9564_i2c.c
index 313288d..4ed0923 100644
--- a/drivers/i2c/pca9564_i2c.c
+++ b/drivers/i2c/pca9564_i2c.c
@@ -12,6 +12,9 @@
* Bugs:
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/ppc4xx_i2c.c b/drivers/i2c/ppc4xx_i2c.c
index df88885..8a38d11 100644
--- a/drivers/i2c/ppc4xx_i2c.c
+++ b/drivers/i2c/ppc4xx_i2c.c
@@ -8,6 +8,9 @@
* Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index 90ad116..bfba443 100644
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -5,6 +5,9 @@
* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index 63b1418..7c701cb 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -258,7 +258,7 @@
while (bytes_remain_len) {
if (bytes_remain_len > RK_I2C_FIFO_SIZE)
- bytes_xferred = 32;
+ bytes_xferred = RK_I2C_FIFO_SIZE;
else
bytes_xferred = bytes_remain_len;
words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
@@ -269,17 +269,17 @@
if ((i * 4 + j) == bytes_xferred)
break;
- if (i == 0 && j == 0) {
+ if (i == 0 && j == 0 && pbuf == buf) {
txdata |= (chip << 1);
- } else if (i == 0 && j <= r_len) {
+ } else if (i == 0 && j <= r_len && pbuf == buf) {
txdata |= (reg &
(0xff << ((j - 1) * 8))) << 8;
} else {
txdata |= (*pbuf++)<<(j * 8);
}
- writel(txdata, ®s->txdata[i]);
}
- debug("I2c Write TXDATA[%d] = 0x%x\n", i, txdata);
+ writel(txdata, ®s->txdata[i]);
+ debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata);
}
writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), ®s->con);
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index eab49d0..2ece9f4 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -24,170 +24,9 @@
#include <i2c.h>
#include "s3c24x0_i2c.h"
-#define I2C_WRITE 0
-#define I2C_READ 1
-
-#define I2C_OK 0
-#define I2C_NOK 1
-#define I2C_NACK 2
-#define I2C_NOK_LA 3 /* Lost arbitration */
-#define I2C_NOK_TOUT 4 /* time out */
-
-/* HSI2C specific register description */
-
-/* I2C_CTL Register bits */
-#define HSI2C_FUNC_MODE_I2C (1u << 0)
-#define HSI2C_MASTER (1u << 3)
-#define HSI2C_RXCHON (1u << 6) /* Write/Send */
-#define HSI2C_TXCHON (1u << 7) /* Read/Receive */
-#define HSI2C_SW_RST (1u << 31)
-
-/* I2C_FIFO_CTL Register bits */
-#define HSI2C_RXFIFO_EN (1u << 0)
-#define HSI2C_TXFIFO_EN (1u << 1)
-#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
-#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
-
-/* I2C_TRAILING_CTL Register bits */
-#define HSI2C_TRAILING_COUNT (0xff)
-
-/* I2C_INT_EN Register bits */
-#define HSI2C_TX_UNDERRUN_EN (1u << 2)
-#define HSI2C_TX_OVERRUN_EN (1u << 3)
-#define HSI2C_RX_UNDERRUN_EN (1u << 4)
-#define HSI2C_RX_OVERRUN_EN (1u << 5)
-#define HSI2C_INT_TRAILING_EN (1u << 6)
-#define HSI2C_INT_I2C_EN (1u << 9)
-
-#define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
- HSI2C_TX_OVERRUN_EN |\
- HSI2C_RX_UNDERRUN_EN |\
- HSI2C_RX_OVERRUN_EN |\
- HSI2C_INT_TRAILING_EN)
-
-/* I2C_CONF Register bits */
-#define HSI2C_AUTO_MODE (1u << 31)
-#define HSI2C_10BIT_ADDR_MODE (1u << 30)
-#define HSI2C_HS_MODE (1u << 29)
-
-/* I2C_AUTO_CONF Register bits */
-#define HSI2C_READ_WRITE (1u << 16)
-#define HSI2C_STOP_AFTER_TRANS (1u << 17)
-#define HSI2C_MASTER_RUN (1u << 31)
-
-/* I2C_TIMEOUT Register bits */
-#define HSI2C_TIMEOUT_EN (1u << 31)
-
-/* I2C_TRANS_STATUS register bits */
-#define HSI2C_MASTER_BUSY (1u << 17)
-#define HSI2C_SLAVE_BUSY (1u << 16)
-#define HSI2C_TIMEOUT_AUTO (1u << 4)
-#define HSI2C_NO_DEV (1u << 3)
-#define HSI2C_NO_DEV_ACK (1u << 2)
-#define HSI2C_TRANS_ABORT (1u << 1)
-#define HSI2C_TRANS_SUCCESS (1u << 0)
-#define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
- HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
- HSI2C_TRANS_ABORT)
-#define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
-
-
-/* I2C_FIFO_STAT Register bits */
-#define HSI2C_RX_FIFO_EMPTY (1u << 24)
-#define HSI2C_RX_FIFO_FULL (1u << 23)
-#define HSI2C_TX_FIFO_EMPTY (1u << 8)
-#define HSI2C_TX_FIFO_FULL (1u << 7)
-#define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
-#define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
-
-#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
-
-/* S3C I2C Controller bits */
-#define I2CSTAT_BSY 0x20 /* Busy bit */
-#define I2CSTAT_NACK 0x01 /* Nack bit */
-#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
-#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
-#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
-#define I2C_MODE_MR 0x80 /* Master Receive Mode */
-#define I2C_START_STOP 0x20 /* START / STOP */
-#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
-
-#define I2C_TIMEOUT_MS 10 /* 10 ms */
-
-#define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
-
-
-/* To support VCMA9 boards and other who dont define max_i2c_num */
-#ifndef CONFIG_MAX_I2C_NUM
-#define CONFIG_MAX_I2C_NUM 1
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
/*
- * For SPL boot some boards need i2c before SDRAM is initialised so force
- * variables to live in SRAM
- */
-#ifdef CONFIG_SYS_I2C
-static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
- __attribute__((section(".data")));
-#endif
-
-enum exynos_i2c_type {
- EXYNOS_I2C_STD,
- EXYNOS_I2C_HS,
-};
-
-#ifdef CONFIG_SYS_I2C
-/**
- * Get a pointer to the given bus index
- *
- * @bus_idx: Bus index to look up
- * @return pointer to bus, or NULL if invalid or not available
- */
-static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
-{
- if (bus_idx < ARRAY_SIZE(i2c_bus)) {
- struct s3c24x0_i2c_bus *bus;
-
- bus = &i2c_bus[bus_idx];
- if (bus->active)
- return bus;
- }
-
- debug("Undefined bus: %d\n", bus_idx);
- return NULL;
-}
-#endif
-
-#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
-static int GetI2CSDA(void)
-{
- struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
- return (readl(&gpio->gpedat) & 0x8000) >> 15;
-#endif
-#ifdef CONFIG_S3C2400
- return (readl(&gpio->pgdat) & 0x0020) >> 5;
-#endif
-}
-
-static void SetI2CSCL(int x)
-{
- struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
- writel((readl(&gpio->gpedat) & ~0x4000) |
- (x & 1) << 14, &gpio->gpedat);
-#endif
-#ifdef CONFIG_S3C2400
- writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
-#endif
-}
-#endif
-
-/*
* Wait til the byte transfer is completed.
*
* @param i2c- pointer to the appropriate i2c register bank.
@@ -209,79 +48,11 @@
return I2C_NOK_TOUT;
}
-/*
- * Wait for transfer completion.
- *
- * This function reads the interrupt status register waiting for the INT_I2C
- * bit to be set, which indicates copletion of a transaction.
- *
- * @param i2c: pointer to the appropriate register bank
- *
- * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
- * the status bits do not get set in time, or an approrpiate error
- * value in case of transfer errors.
- */
-static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
-{
- int i = HSI2C_TIMEOUT_US;
-
- while (i-- > 0) {
- u32 int_status = readl(&i2c->usi_int_stat);
-
- if (int_status & HSI2C_INT_I2C_EN) {
- u32 trans_status = readl(&i2c->usi_trans_status);
-
- /* Deassert pending interrupt. */
- writel(int_status, &i2c->usi_int_stat);
-
- if (trans_status & HSI2C_NO_DEV_ACK) {
- debug("%s: no ACK from device\n", __func__);
- return I2C_NACK;
- }
- if (trans_status & HSI2C_NO_DEV) {
- debug("%s: no device\n", __func__);
- return I2C_NOK;
- }
- if (trans_status & HSI2C_TRANS_ABORT) {
- debug("%s: arbitration lost\n", __func__);
- return I2C_NOK_LA;
- }
- if (trans_status & HSI2C_TIMEOUT_AUTO) {
- debug("%s: device timed out\n", __func__);
- return I2C_NOK_TOUT;
- }
- return I2C_OK;
- }
- udelay(1);
- }
- debug("%s: transaction timeout!\n", __func__);
- return I2C_NOK_TOUT;
-}
-
static void read_write_byte(struct s3c24x0_i2c *i2c)
{
clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
}
-#ifdef CONFIG_SYS_I2C
-static struct s3c24x0_i2c *get_base_i2c(int bus)
-{
-#ifdef CONFIG_EXYNOS4
- struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
- + (EXYNOS4_I2C_SPACING
- * bus));
- return i2c;
-#elif defined CONFIG_EXYNOS5
- struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
- + (EXYNOS5_I2C_SPACING
- * bus));
- return i2c;
-#else
- return s3c24x0_get_base_i2c();
-#endif
-}
-#endif
-
static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
ulong freq, pres = 16, div;
@@ -309,438 +80,14 @@
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}
-static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
-{
- struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
- ulong clkin;
- unsigned int op_clk = i2c_bus->clock_frequency;
- unsigned int i = 0, utemp0 = 0, utemp1 = 0;
- unsigned int t_ftl_cycle;
-
-#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
- clkin = get_i2c_clk();
-#else
- clkin = get_PCLK();
-#endif
- /* FPCLK / FI2C =
- * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
- * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
- * uTemp1 = (TSCLK_L + TSCLK_H + 2)
- * uTemp2 = TSCLK_L + TSCLK_H
- */
- t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
- utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
-
- /* CLK_DIV max is 256 */
- for (i = 0; i < 256; i++) {
- utemp1 = utemp0 / (i + 1);
- if ((utemp1 < 512) && (utemp1 > 4)) {
- i2c_bus->clk_cycle = utemp1 - 2;
- i2c_bus->clk_div = i;
- return 0;
- }
- }
- return -EINVAL;
-}
-
-static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
-{
- struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
- unsigned int t_sr_release;
- unsigned int n_clkdiv;
- unsigned int t_start_su, t_start_hd;
- unsigned int t_stop_su;
- unsigned int t_data_su, t_data_hd;
- unsigned int t_scl_l, t_scl_h;
- u32 i2c_timing_s1;
- u32 i2c_timing_s2;
- u32 i2c_timing_s3;
- u32 i2c_timing_sla;
-
- n_clkdiv = i2c_bus->clk_div;
- t_scl_l = i2c_bus->clk_cycle / 2;
- t_scl_h = i2c_bus->clk_cycle / 2;
- t_start_su = t_scl_l;
- t_start_hd = t_scl_l;
- t_stop_su = t_scl_l;
- t_data_su = t_scl_l / 2;
- t_data_hd = t_scl_l / 2;
- t_sr_release = i2c_bus->clk_cycle;
-
- i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
- i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
- i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
- i2c_timing_sla = t_data_hd << 0;
-
- writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
-
- /* Clear to enable Timeout */
- clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
-
- /* set AUTO mode */
- writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
-
- /* Enable completion conditions' reporting. */
- writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
-
- /* Enable FIFOs */
- writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
-
- /* Currently operating in Fast speed mode. */
- writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
- writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
- writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
- writel(i2c_timing_sla, &hsregs->usi_timing_sla);
-}
-
-/* SW reset for the high speed bus */
-static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
-{
- struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
- u32 i2c_ctl;
-
- /* Set and clear the bit for reset */
- i2c_ctl = readl(&i2c->usi_ctl);
- i2c_ctl |= HSI2C_SW_RST;
- writel(i2c_ctl, &i2c->usi_ctl);
-
- i2c_ctl = readl(&i2c->usi_ctl);
- i2c_ctl &= ~HSI2C_SW_RST;
- writel(i2c_ctl, &i2c->usi_ctl);
-
- /* Initialize the configure registers */
- hsi2c_ch_init(i2c_bus);
-}
-
-#ifdef CONFIG_SYS_I2C
-static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
-{
- struct s3c24x0_i2c *i2c;
- struct s3c24x0_i2c_bus *bus;
-#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
- struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-#endif
- ulong start_time = get_timer(0);
-
- i2c = get_base_i2c(adap->hwadapnr);
- bus = &i2c_bus[adap->hwadapnr];
- if (!bus)
- return;
-
- /*
- * In case the previous transfer is still going, wait to give it a
- * chance to finish.
- */
- while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
- if (get_timer(start_time) > I2C_TIMEOUT_MS) {
- printf("%s: I2C bus busy for %p\n", __func__,
- &i2c->iicstat);
- return;
- }
- }
-
-#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
- int i;
-
- if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
- ulong old_gpecon = readl(&gpio->gpecon);
-#endif
-#ifdef CONFIG_S3C2400
- ulong old_gpecon = readl(&gpio->pgcon);
-#endif
- /* bus still busy probably by (most) previously interrupted
- transfer */
-
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
- /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
- writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
- &gpio->gpecon);
-#endif
-#ifdef CONFIG_S3C2400
- /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
- writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
- &gpio->pgcon);
-#endif
-
- /* toggle I2CSCL until bus idle */
- SetI2CSCL(0);
- udelay(1000);
- i = 10;
- while ((i > 0) && (GetI2CSDA() != 1)) {
- SetI2CSCL(1);
- udelay(1000);
- SetI2CSCL(0);
- udelay(1000);
- i--;
- }
- SetI2CSCL(1);
- udelay(1000);
-
- /* restore pin functions */
-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
- writel(old_gpecon, &gpio->gpecon);
-#endif
-#ifdef CONFIG_S3C2400
- writel(old_gpecon, &gpio->pgcon);
-#endif
- }
-#endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
-
- i2c_ch_init(i2c, speed, slaveadd);
-
- bus->active = true;
- bus->regs = i2c;
-}
-#endif /* CONFIG_SYS_I2C */
-
-/*
- * Poll the appropriate bit of the fifo status register until the interface is
- * ready to process the next byte or timeout expires.
- *
- * In addition to the FIFO status register this function also polls the
- * interrupt status register to be able to detect unexpected transaction
- * completion.
- *
- * When FIFO is ready to process the next byte, this function returns I2C_OK.
- * If in course of polling the INT_I2C assertion is detected, the function
- * returns I2C_NOK. If timeout happens before any of the above conditions is
- * met - the function returns I2C_NOK_TOUT;
-
- * @param i2c: pointer to the appropriate i2c register bank.
- * @param rx_transfer: set to True if the receive transaction is in progress.
- * @return: as described above.
- */
-static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
-{
- u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
- int i = HSI2C_TIMEOUT_US;
-
- while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
- if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
- /*
- * There is a chance that assertion of
- * HSI2C_INT_I2C_EN and deassertion of
- * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
- * give FIFO status priority and check it one more
- * time before reporting interrupt. The interrupt will
- * be reported next time this function is called.
- */
- if (rx_transfer &&
- !(readl(&i2c->usi_fifo_stat) & fifo_bit))
- break;
- return I2C_NOK;
- }
- if (!i--) {
- debug("%s: FIFO polling timeout!\n", __func__);
- return I2C_NOK_TOUT;
- }
- udelay(1);
- }
- return I2C_OK;
-}
-
-/*
- * Preapre hsi2c transaction, either read or write.
- *
- * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
- * the 5420 UM.
- *
- * @param i2c: pointer to the appropriate i2c register bank.
- * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
- * @param len: number of bytes expected to be sent or received
- * @param rx_transfer: set to true for receive transactions
- * @param: issue_stop: set to true if i2c stop condition should be generated
- * after this transaction.
- * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
- * I2C_OK otherwise.
- */
-static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
- u8 chip,
- u16 len,
- bool rx_transfer,
- bool issue_stop)
-{
- u32 conf;
-
- conf = len | HSI2C_MASTER_RUN;
-
- if (issue_stop)
- conf |= HSI2C_STOP_AFTER_TRANS;
-
- /* Clear to enable Timeout */
- writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
-
- /* Set slave address */
- writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
-
- if (rx_transfer) {
- /* i2c master, read transaction */
- writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
- &i2c->usi_ctl);
-
- /* read up to len bytes, stop after transaction is finished */
- writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
- } else {
- /* i2c master, write transaction */
- writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
- &i2c->usi_ctl);
-
- /* write up to len bytes, stop after transaction is finished */
- writel(conf, &i2c->usi_auto_conf);
- }
-
- /* Reset all pending interrupt status bits we care about, if any */
- writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
-
- return I2C_OK;
-}
-
-/*
- * Wait while i2c bus is settling down (mostly stop gets completed).
- */
-static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
-{
- int i = HSI2C_TIMEOUT_US;
-
- while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
- if (!i--) {
- debug("%s: bus busy\n", __func__);
- return I2C_NOK_TOUT;
- }
- udelay(1);
- }
- return I2C_OK;
-}
-
-static int hsi2c_write(struct exynos5_hsi2c *i2c,
- unsigned char chip,
- unsigned char addr[],
- unsigned char alen,
- unsigned char data[],
- unsigned short len,
- bool issue_stop)
-{
- int i, rv = 0;
-
- if (!(len + alen)) {
- /* Writes of zero length not supported in auto mode. */
- debug("%s: zero length writes not supported\n", __func__);
- return I2C_NOK;
- }
-
- rv = hsi2c_prepare_transaction
- (i2c, chip, len + alen, false, issue_stop);
- if (rv != I2C_OK)
- return rv;
-
- /* Move address, if any, and the data, if any, into the FIFO. */
- for (i = 0; i < alen; i++) {
- rv = hsi2c_poll_fifo(i2c, false);
- if (rv != I2C_OK) {
- debug("%s: address write failed\n", __func__);
- goto write_error;
- }
- writel(addr[i], &i2c->usi_txdata);
- }
-
- for (i = 0; i < len; i++) {
- rv = hsi2c_poll_fifo(i2c, false);
- if (rv != I2C_OK) {
- debug("%s: data write failed\n", __func__);
- goto write_error;
- }
- writel(data[i], &i2c->usi_txdata);
- }
-
- rv = hsi2c_wait_for_trx(i2c);
-
- write_error:
- if (issue_stop) {
- int tmp_ret = hsi2c_wait_while_busy(i2c);
- if (rv == I2C_OK)
- rv = tmp_ret;
- }
-
- writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
- return rv;
-}
-
-static int hsi2c_read(struct exynos5_hsi2c *i2c,
- unsigned char chip,
- unsigned char addr[],
- unsigned char alen,
- unsigned char data[],
- unsigned short len)
-{
- int i, rv, tmp_ret;
- bool drop_data = false;
-
- if (!len) {
- /* Reads of zero length not supported in auto mode. */
- debug("%s: zero length read adjusted\n", __func__);
- drop_data = true;
- len = 1;
- }
-
- if (alen) {
- /* Internal register adress needs to be written first. */
- rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
- if (rv != I2C_OK)
- return rv;
- }
-
- rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
-
- if (rv != I2C_OK)
- return rv;
-
- for (i = 0; i < len; i++) {
- rv = hsi2c_poll_fifo(i2c, true);
- if (rv != I2C_OK)
- goto read_err;
- if (drop_data)
- continue;
- data[i] = readl(&i2c->usi_rxdata);
- }
-
- rv = hsi2c_wait_for_trx(i2c);
-
- read_err:
- tmp_ret = hsi2c_wait_while_busy(i2c);
- if (rv == I2C_OK)
- rv = tmp_ret;
-
- writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
- return rv;
-}
-
-#ifdef CONFIG_SYS_I2C
-static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
-#else
static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
-#endif
{
- struct s3c24x0_i2c_bus *i2c_bus;
+ struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
-#ifdef CONFIG_SYS_I2C
- i2c_bus = get_bus(adap->hwadapnr);
- if (!i2c_bus)
- return -EFAULT;
-#else
- i2c_bus = dev_get_priv(dev);
-#endif
i2c_bus->clock_frequency = speed;
- if (i2c_bus->is_highspeed) {
- if (hsi2c_get_clk_details(i2c_bus))
- return -EFAULT;
- hsi2c_ch_init(i2c_bus);
- } else {
- i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
- CONFIG_SYS_I2C_S3C24X0_SLAVE);
- }
+ i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE);
return 0;
}
@@ -857,23 +204,12 @@
return result;
}
-#ifdef CONFIG_SYS_I2C
-static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
-#else
static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
-#endif
{
- struct s3c24x0_i2c_bus *i2c_bus;
+ struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
uchar buf[1];
int ret;
-#ifdef CONFIG_SYS_I2C
- i2c_bus = get_bus(adap->hwadapnr);
- if (!i2c_bus)
- return -EFAULT;
-#else
- i2c_bus = dev_get_priv(dev);
-#endif
buf[0] = 0;
/*
@@ -881,433 +217,11 @@
* address was <ACK>ed (i.e. there was a chip at that address which
* drove the data line low).
*/
- if (i2c_bus->is_highspeed) {
- ret = hsi2c_read(i2c_bus->hsregs,
- chip, 0, 0, buf, 1);
- } else {
- ret = i2c_transfer(i2c_bus->regs,
- I2C_READ, chip << 1, 0, 0, buf, 1);
- }
+ ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
return ret != I2C_OK;
}
-#ifdef CONFIG_SYS_I2C
-static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buffer, int len)
-{
- struct s3c24x0_i2c_bus *i2c_bus;
- uchar xaddr[4];
- int ret;
-
- i2c_bus = get_bus(adap->hwadapnr);
- if (!i2c_bus)
- return -EFAULT;
-
- if (alen > 4) {
- debug("I2C read: addr len %d not supported\n", alen);
- return -EADDRNOTAVAIL;
- }
-
- if (alen > 0) {
- xaddr[0] = (addr >> 24) & 0xFF;
- xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
- }
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
- /*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- * address and the extra bits end up in the "chip address"
- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
- * four 256 byte chips.
- *
- * Note that we consider the length of the address field to
- * still be one byte because the extra address bits are
- * hidden in the chip address.
- */
- if (alen > 0)
- chip |= ((addr >> (alen * 8)) &
- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
-#endif
- if (i2c_bus->is_highspeed)
- ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen],
- alen, buffer, len);
- else
- ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1,
- &xaddr[4 - alen], alen, buffer, len);
-
- if (ret) {
- if (i2c_bus->is_highspeed)
- exynos5_i2c_reset(i2c_bus);
- debug("I2c read failed %d\n", ret);
- return -EIO;
- }
- return 0;
-}
-
-static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
- int alen, uchar *buffer, int len)
-{
- struct s3c24x0_i2c_bus *i2c_bus;
- uchar xaddr[4];
- int ret;
-
- i2c_bus = get_bus(adap->hwadapnr);
- if (!i2c_bus)
- return -EFAULT;
-
- if (alen > 4) {
- debug("I2C write: addr len %d not supported\n", alen);
- return -EINVAL;
- }
-
- if (alen > 0) {
- xaddr[0] = (addr >> 24) & 0xFF;
- xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
- }
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
- /*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- * address and the extra bits end up in the "chip address"
- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
- * four 256 byte chips.
- *
- * Note that we consider the length of the address field to
- * still be one byte because the extra address bits are
- * hidden in the chip address.
- */
- if (alen > 0)
- chip |= ((addr >> (alen * 8)) &
- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
-#endif
- if (i2c_bus->is_highspeed)
- ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen],
- alen, buffer, len, true);
- else
- ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, chip << 1,
- &xaddr[4 - alen], alen, buffer, len);
-
- if (ret != 0) {
- if (i2c_bus->is_highspeed)
- exynos5_i2c_reset(i2c_bus);
- return 1;
- } else {
- return 0;
- }
-}
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static void process_nodes(const void *blob, int node_list[], int count,
- int is_highspeed)
-{
- struct s3c24x0_i2c_bus *bus;
- int i, flags;
-
- for (i = 0; i < count; i++) {
- int node = node_list[i];
-
- if (node <= 0)
- continue;
-
- bus = &i2c_bus[i];
- bus->active = true;
- bus->is_highspeed = is_highspeed;
-
- if (is_highspeed) {
- flags = PINMUX_FLAG_HS_MODE;
- bus->hsregs = (struct exynos5_hsi2c *)
- fdtdec_get_addr(blob, node, "reg");
- } else {
- flags = 0;
- bus->regs = (struct s3c24x0_i2c *)
- fdtdec_get_addr(blob, node, "reg");
- }
-
- bus->id = pinmux_decode_periph_id(blob, node);
- bus->clock_frequency = fdtdec_get_int(blob, node,
- "clock-frequency",
- CONFIG_SYS_I2C_S3C24X0_SPEED);
- bus->node = node;
- bus->bus_num = i;
- exynos_pinmux_config(bus->id, flags);
-
- /* Mark position as used */
- node_list[i] = -1;
- }
-}
-
-void board_i2c_init(const void *blob)
-{
- int node_list[CONFIG_MAX_I2C_NUM];
- int count;
-
- /* First get the normal i2c ports */
- count = fdtdec_find_aliases_for_id(blob, "i2c",
- COMPAT_SAMSUNG_S3C2440_I2C, node_list,
- CONFIG_MAX_I2C_NUM);
- process_nodes(blob, node_list, count, 0);
-
- /* Now look for high speed i2c ports */
- count = fdtdec_find_aliases_for_id(blob, "i2c",
- COMPAT_SAMSUNG_EXYNOS5_I2C, node_list,
- CONFIG_MAX_I2C_NUM);
- process_nodes(blob, node_list, count, 1);
-}
-
-int i2c_get_bus_num_fdt(int node)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) {
- if (node == i2c_bus[i].node)
- return i;
- }
-
- debug("%s: Can't find any matched I2C bus\n", __func__);
- return -EINVAL;
-}
-
-int i2c_reset_port_fdt(const void *blob, int node)
-{
- struct s3c24x0_i2c_bus *i2c_bus;
- int bus;
-
- bus = i2c_get_bus_num_fdt(node);
- if (bus < 0) {
- debug("could not get bus for node %d\n", node);
- return bus;
- }
-
- i2c_bus = get_bus(bus);
- if (!i2c_bus) {
- debug("get_bus() failed for node %d\n", node);
- return -EFAULT;
- }
-
- if (i2c_bus->is_highspeed) {
- if (hsi2c_get_clk_details(i2c_bus))
- return -EINVAL;
- hsi2c_ch_init(i2c_bus);
- } else {
- i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
- CONFIG_SYS_I2C_S3C24X0_SLAVE);
- }
-
- return 0;
-}
-#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
-
-#ifdef CONFIG_EXYNOS5
-static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- /* This will override the speed selected in the fdt for that port */
- debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
- if (i2c_set_bus_speed(speed))
- error("i2c_init: failed to init bus for speed = %d", speed);
-}
-#endif /* CONFIG_EXYNOS5 */
-
-/*
- * Register s3c24x0 i2c adapters
- */
-#if defined(CONFIG_EXYNOS5420)
-U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
-U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
-U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
-U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
-U_BOOT_I2C_ADAP_COMPLETE(i2c04, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
-U_BOOT_I2C_ADAP_COMPLETE(i2c05, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
-U_BOOT_I2C_ADAP_COMPLETE(i2c06, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
-U_BOOT_I2C_ADAP_COMPLETE(i2c07, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
-U_BOOT_I2C_ADAP_COMPLETE(i2c08, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
-U_BOOT_I2C_ADAP_COMPLETE(i2c09, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
-U_BOOT_I2C_ADAP_COMPLETE(i2c10, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
-#elif defined(CONFIG_EXYNOS5250)
-U_BOOT_I2C_ADAP_COMPLETE(i2c00, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
-U_BOOT_I2C_ADAP_COMPLETE(i2c01, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
-U_BOOT_I2C_ADAP_COMPLETE(i2c02, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
-U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
-U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
-U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
-U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
-U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
-U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
-U_BOOT_I2C_ADAP_COMPLETE(i2c09, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
-U_BOOT_I2C_ADAP_COMPLETE(s3c10, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
-#elif defined(CONFIG_EXYNOS4)
-U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
-U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
-U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
-U_BOOT_I2C_ADAP_COMPLETE(i2c03, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
-U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
-U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
-U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
-U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
-U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
-#else
-U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
- s3c24x0_i2c_read, s3c24x0_i2c_write,
- s3c24x0_i2c_set_bus_speed,
- CONFIG_SYS_I2C_S3C24X0_SPEED,
- CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
-#endif
-#endif /* CONFIG_SYS_I2C */
-
-#ifdef CONFIG_DM_I2C
-static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
- int nmsgs)
-{
- struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
- struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
- int ret;
-
- for (; nmsgs > 0; nmsgs--, msg++) {
- if (msg->flags & I2C_M_RD) {
- ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
- msg->len);
- } else {
- ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
- msg->len, true);
- }
- if (ret) {
- exynos5_i2c_reset(i2c_bus);
- return -EREMOTEIO;
- }
- }
-
- return 0;
-}
-
static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
int seq)
{
@@ -1390,18 +304,11 @@
{
const void *blob = gd->fdt_blob;
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
- int node, flags;
+ int node;
- i2c_bus->is_highspeed = dev_get_driver_data(dev);
node = dev->of_offset;
- if (i2c_bus->is_highspeed) {
- flags = PINMUX_FLAG_HS_MODE;
- i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev);
- } else {
- flags = 0;
- i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
- }
+ i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
i2c_bus->id = pinmux_decode_periph_id(blob, node);
@@ -1410,7 +317,7 @@
i2c_bus->node = node;
i2c_bus->bus_num = dev->seq;
- exynos_pinmux_config(i2c_bus->id, flags);
+ exynos_pinmux_config(i2c_bus->id, 0);
i2c_bus->active = true;
@@ -1424,7 +331,7 @@
};
static const struct udevice_id s3c_i2c_ids[] = {
- { .compatible = "samsung,s3c2440-i2c", .data = EXYNOS_I2C_STD },
+ { .compatible = "samsung,s3c2440-i2c" },
{ }
};
@@ -1436,28 +343,3 @@
.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
.ops = &s3c_i2c_ops,
};
-
-/*
- * TODO(sjg@chromium.org): Move this to a separate file when everything uses
- * driver model
- */
-static const struct dm_i2c_ops exynos_hs_i2c_ops = {
- .xfer = exynos_hs_i2c_xfer,
- .probe_chip = s3c24x0_i2c_probe,
- .set_bus_speed = s3c24x0_i2c_set_bus_speed,
-};
-
-static const struct udevice_id exynos_hs_i2c_ids[] = {
- { .compatible = "samsung,exynos5-hsi2c", .data = EXYNOS_I2C_HS },
- { }
-};
-
-U_BOOT_DRIVER(hs_i2c) = {
- .name = "i2c_s3c_hs",
- .id = UCLASS_I2C,
- .of_match = exynos_hs_i2c_ids,
- .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
- .ops = &exynos_hs_i2c_ops,
-};
-#endif /* CONFIG_DM_I2C */
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h
index 1ae73d2..aa10fc7 100644
--- a/drivers/i2c/s3c24x0_i2c.h
+++ b/drivers/i2c/s3c24x0_i2c.h
@@ -59,4 +59,26 @@
unsigned clk_cycle;
unsigned clk_div;
};
+
+#define I2C_WRITE 0
+#define I2C_READ 1
+
+#define I2C_OK 0
+#define I2C_NOK 1
+#define I2C_NACK 2
+#define I2C_NOK_LA 3 /* Lost arbitration */
+#define I2C_NOK_TOUT 4 /* time out */
+
+/* S3C I2C Controller bits */
+#define I2CSTAT_BSY 0x20 /* Busy bit */
+#define I2CSTAT_NACK 0x01 /* Nack bit */
+#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
+#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
+#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
+#define I2C_MODE_MR 0x80 /* Master Receive Mode */
+#define I2C_START_STOP 0x20 /* START / STOP */
+#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
+
+#define I2C_TIMEOUT_MS 10 /* 10 ms */
+
#endif /* _S3C24X0_I2C_H */
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index e7e9692..ef79725 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -3,6 +3,9 @@
* Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c
index 6c2f221..1c12fb8 100644
--- a/drivers/i2c/sh_sh7734_i2c.c
+++ b/drivers/i2c/sh_sh7734_i2c.c
@@ -3,6 +3,9 @@
* Copyright (C) 2012 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index 05bf4d4..c102a1a 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -11,6 +11,9 @@
* This has been changed substantially by Gerald Van Baren, Custom IDEAS,
* vanbaren@cideas.com. It was heavily influenced by LiMon, written by
* Neil Russell.
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 0dbcc5a..898f12a 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -12,27 +12,15 @@
#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
-#ifdef CONFIG_TEGRA186
#include <clk.h>
#include <reset.h>
-#else
+#ifndef CONFIG_TEGRA186
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/clk_rst.h>
#endif
#include <asm/arch/gpio.h>
#include <asm/arch-tegra/tegra_i2c.h>
-/*
- * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
- * should not be present. These are needed because newer Tegra SoCs support
- * only the standard clock/reset APIs, whereas older Tegra SoCs support only
- * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
- * fixed to implement the standard APIs, and all drivers converted to solely
- * use the new standard APIs, with no ifdefs.
- */
-
DECLARE_GLOBAL_DATA_PTR;
enum i2c_type {
@@ -44,12 +32,8 @@
/* Information about i2c controller */
struct i2c_bus {
int id;
-#ifdef CONFIG_TEGRA186
struct reset_ctl reset_ctl;
struct clk clk;
-#else
- enum periph_id periph_id;
-#endif
int speed;
int pinmux_config;
struct i2c_control *control;
@@ -81,20 +65,15 @@
static void i2c_reset_controller(struct i2c_bus *i2c_bus)
{
/* Reset I2C controller. */
-#ifdef CONFIG_TEGRA186
reset_assert(&i2c_bus->reset_ctl);
udelay(1);
reset_deassert(&i2c_bus->reset_ctl);
udelay(1);
-#else
- reset_periph(i2c_bus->periph_id, 1);
-#endif
/* re-program config register to packet mode */
set_packet_mode(i2c_bus);
}
-#ifdef CONFIG_TEGRA186
static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
{
int ret;
@@ -114,7 +93,6 @@
return 0;
}
-#endif
static void i2c_init_controller(struct i2c_bus *i2c_bus)
{
@@ -126,12 +104,7 @@
* here, in section 23.3.1, but in fact we seem to need a factor of
* 16 to get the right frequency.
*/
-#ifdef CONFIG_TEGRA186
i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
-#else
- clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
- i2c_bus->speed * 2 * 8);
-#endif
if (i2c_bus->type == TYPE_114) {
/*
@@ -151,12 +124,7 @@
debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
clk_div_stdfst_mode);
-#ifdef CONFIG_TEGRA186
i2c_init_clock(i2c_bus, rate);
-#else
- clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
- rate);
-#endif
}
/* Reset I2C controller. */
@@ -170,7 +138,7 @@
}
#ifndef CONFIG_TEGRA186
- funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
+ funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
#endif
}
@@ -392,23 +360,13 @@
static int tegra_i2c_probe(struct udevice *dev)
{
struct i2c_bus *i2c_bus = dev_get_priv(dev);
-#ifdef CONFIG_TEGRA186
int ret;
-#else
- const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
-#endif
bool is_dvc;
i2c_bus->id = dev->seq;
i2c_bus->type = dev_get_driver_data(dev);
i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev);
- /*
- * We don't have a binding for pinmux yet. Leave it out for now. So
- * far no one needs anything other than the default.
- */
-#ifdef CONFIG_TEGRA186
ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
if (ret) {
error("reset_get_by_name() failed: %d\n", ret);
@@ -419,9 +377,13 @@
error("clk_get_by_name() failed: %d\n", ret);
return ret;
}
-#else
+
+#ifndef CONFIG_TEGRA186
+ /*
+ * We don't have a binding for pinmux yet. Leave it out for now. So
+ * far no one needs anything other than the default.
+ */
i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
- i2c_bus->periph_id = clock_decode_periph_id(blob, node);
/*
* We can't specify the pinmux config in the fdt, so I2C2 will not
@@ -429,11 +391,9 @@
* You could add in this little hack if you need to use it.
* The correct solution is a pinmux binding in the fdt.
*
- * if (i2c_bus->periph_id == PERIPH_ID_I2C2)
+ * if (i2c_bus->clk.id == PERIPH_ID_I2C2)
* i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
*/
- if (i2c_bus->periph_id == -1)
- return -EINVAL;
#endif
is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
@@ -444,14 +404,8 @@
i2c_bus->control = &i2c_bus->regs->control;
}
i2c_init_controller(i2c_bus);
- debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
- is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs,
-#ifndef CONFIG_TEGRA186
- i2c_bus->periph_id,
-#else
- -1,
-#endif
- i2c_bus->speed);
+ debug("%s: controller bus %d at %p, speed %d: ",
+ is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);
return 0;
}
diff --git a/drivers/i2c/tsi108_i2c.c b/drivers/i2c/tsi108_i2c.c
index c077907..90292d2 100644
--- a/drivers/i2c/tsi108_i2c.c
+++ b/drivers/i2c/tsi108_i2c.c
@@ -3,6 +3,9 @@
* Author: Alex Bounine
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <config.h>
diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c
index 380863b..85be58f 100644
--- a/drivers/i2c/zynq_i2c.c
+++ b/drivers/i2c/zynq_i2c.c
@@ -8,12 +8,15 @@
* Copyright (c) 2012-2013 Xilinx, Michal Simek
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE: This driver should be converted to driver model before June 2017.
+ * Please see doc/driver-model/i2c-howto.txt for instructions.
*/
#include <common.h>
#include <asm/io.h>
#include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/hardware.h>
/* i2c register set */
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index d560328..b3873c1 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -17,6 +17,7 @@
config I8042_KEYB
bool "Enable Intel i8042 keyboard support"
depends on DM_KEYBOARD
+ default X86
help
This adds a driver for the i8042 keyboard controller, allowing the
keyboard to be used on devices which support this controller. The
diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c
index 48255bd..7af5868 100644
--- a/drivers/input/keyboard.c
+++ b/drivers/input/keyboard.c
@@ -20,8 +20,8 @@
static int kbd_read_keys(struct input_config *config)
{
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || \
- defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
#endif
diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c
index 40f851d..a7fcde5 100644
--- a/drivers/mailbox/mailbox-uclass.c
+++ b/drivers/mailbox/mailbox-uclass.c
@@ -85,10 +85,10 @@
debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan);
- index = fdt_find_string(gd->fdt_blob, dev->of_offset, "mbox-names",
- name);
+ index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ "mbox-names", name);
if (index < 0) {
- debug("fdt_find_string() failed: %d\n", index);
+ debug("fdt_stringlist_search() failed: %d\n", index);
return index;
}
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 8990489..1aae4bc 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -129,6 +129,13 @@
help
The I2C address of the PCA9551 LED controller.
+config TEGRA_CAR
+ bool "Enable support for the Tegra CAR driver"
+ depends on TEGRA_NO_BPMP
+ help
+ The Tegra CAR (Clock and Reset Controller) is a HW module that
+ controls almost all clocks and resets in a Tegra SoC.
+
config TEGRA186_BPMP
bool "Enable support for the Tegra186 BPMP driver"
depends on TEGRA186
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index c0e5f03..9fbb5a7 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -16,7 +16,6 @@
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
-obj-$(CONFIG_FSL_DEBUG_SERVER) += fsl_debug_server.o
endif
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_GPIO_LED) += gpio_led.o
@@ -43,6 +42,7 @@
endif
endif
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
+obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index aea8d61..759bb46 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -22,7 +22,7 @@
#include <fdtdec.h>
#include <malloc.h>
#include <spi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <dm/device-internal.h>
@@ -43,9 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Note: depends on enum ec_current_image */
-static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"};
-
void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, int len)
{
#ifdef DEBUG
@@ -750,15 +747,24 @@
static int cros_ec_flash_write_block(struct cros_ec_dev *dev,
const uint8_t *data, uint32_t offset, uint32_t size)
{
- struct ec_params_flash_write p;
+ struct ec_params_flash_write *p;
+ int ret;
- p.offset = offset;
- p.size = size;
- assert(data && p.size <= EC_FLASH_WRITE_VER0_SIZE);
- memcpy(&p + 1, data, p.size);
+ p = malloc(sizeof(*p) + size);
+ if (!p)
+ return -ENOMEM;
- return ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
- &p, sizeof(p), NULL, 0) >= 0 ? 0 : -1;
+ p->offset = offset;
+ p->size = size;
+ assert(data && p->size <= EC_FLASH_WRITE_VER0_SIZE);
+ memcpy(p + 1, data, p->size);
+
+ ret = ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
+ p, sizeof(*p) + size, NULL, 0) >= 0 ? 0 : -1;
+
+ free(p);
+
+ return ret;
}
/**
@@ -790,6 +796,27 @@
return 1;
}
+/**
+ * Read back flash parameters
+ *
+ * This function reads back parameters of the flash as reported by the EC
+ *
+ * @param dev Pointer to device
+ * @param info Pointer to output flash info struct
+ */
+int cros_ec_read_flashinfo(struct cros_ec_dev *dev,
+ struct ec_response_flash_info *info)
+{
+ int ret;
+
+ ret = ec_command(dev, EC_CMD_FLASH_INFO, 0,
+ NULL, 0, info, sizeof(*info));
+ if (ret < 0)
+ return ret;
+
+ return ret < sizeof(*info) ? -1 : 0;
+}
+
int cros_ec_flash_write(struct cros_ec_dev *dev, const uint8_t *data,
uint32_t offset, uint32_t size)
{
@@ -997,22 +1024,6 @@
return 0;
}
-int cros_ec_decode_region(int argc, char * const argv[])
-{
- if (argc > 0) {
- if (0 == strcmp(*argv, "rw"))
- return EC_FLASH_REGION_RW;
- else if (0 == strcmp(*argv, "ro"))
- return EC_FLASH_REGION_RO;
-
- debug("%s: Invalid region '%s'\n", __func__, *argv);
- } else {
- debug("%s: Missing region parameter\n", __func__);
- }
-
- return -1;
-}
-
int cros_ec_decode_ec_flash(const void *blob, int node,
struct fdt_cros_ec *config)
{
@@ -1058,7 +1069,8 @@
return 0;
}
-int cros_ec_i2c_tunnel(struct udevice *dev, struct i2c_msg *in, int nmsgs)
+int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *in,
+ int nmsgs)
{
struct cros_ec_dev *cdev = dev_get_uclass_priv(dev);
union {
@@ -1078,7 +1090,7 @@
int rv;
int i;
- p->port = 0;
+ p->port = port;
p->num_msgs = nmsgs;
size = sizeof(*p) + p->num_msgs * sizeof(*msg);
@@ -1133,344 +1145,6 @@
return 0;
}
-#ifdef CONFIG_CMD_CROS_EC
-
-/**
- * Perform a flash read or write command
- *
- * @param dev CROS-EC device to read/write
- * @param is_write 1 do to a write, 0 to do a read
- * @param argc Number of arguments
- * @param argv Arguments (2 is region, 3 is address)
- * @return 0 for ok, 1 for a usage error or -ve for ec command error
- * (negative EC_RES_...)
- */
-static int do_read_write(struct cros_ec_dev *dev, int is_write, int argc,
- char * const argv[])
-{
- uint32_t offset, size = -1U, region_size;
- unsigned long addr;
- char *endp;
- int region;
- int ret;
-
- region = cros_ec_decode_region(argc - 2, argv + 2);
- if (region == -1)
- return 1;
- if (argc < 4)
- return 1;
- addr = simple_strtoul(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- return 1;
- if (argc > 4) {
- size = simple_strtoul(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- return 1;
- }
-
- ret = cros_ec_flash_offset(dev, region, &offset, ®ion_size);
- if (ret) {
- debug("%s: Could not read region info\n", __func__);
- return ret;
- }
- if (size == -1U)
- size = region_size;
-
- ret = is_write ?
- cros_ec_flash_write(dev, (uint8_t *)addr, offset, size) :
- cros_ec_flash_read(dev, (uint8_t *)addr, offset, size);
- if (ret) {
- debug("%s: Could not %s region\n", __func__,
- is_write ? "write" : "read");
- return ret;
- }
-
- return 0;
-}
-
-static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct cros_ec_dev *dev;
- struct udevice *udev;
- const char *cmd;
- int ret = 0;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- cmd = argv[1];
- if (0 == strcmp("init", cmd)) {
- /* Remove any existing device */
- ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev);
- if (!ret)
- device_remove(udev);
- ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
- if (ret) {
- printf("Could not init cros_ec device (err %d)\n", ret);
- return 1;
- }
- return 0;
- }
-
- ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
- if (ret) {
- printf("Cannot get cros-ec device (err=%d)\n", ret);
- return 1;
- }
- dev = dev_get_uclass_priv(udev);
- if (0 == strcmp("id", cmd)) {
- char id[MSG_BYTES];
-
- if (cros_ec_read_id(dev, id, sizeof(id))) {
- debug("%s: Could not read KBC ID\n", __func__);
- return 1;
- }
- printf("%s\n", id);
- } else if (0 == strcmp("info", cmd)) {
- struct ec_response_mkbp_info info;
-
- if (cros_ec_info(dev, &info)) {
- debug("%s: Could not read KBC info\n", __func__);
- return 1;
- }
- printf("rows = %u\n", info.rows);
- printf("cols = %u\n", info.cols);
- printf("switches = %#x\n", info.switches);
- } else if (0 == strcmp("curimage", cmd)) {
- enum ec_current_image image;
-
- if (cros_ec_read_current_image(dev, &image)) {
- debug("%s: Could not read KBC image\n", __func__);
- return 1;
- }
- printf("%d\n", image);
- } else if (0 == strcmp("hash", cmd)) {
- struct ec_response_vboot_hash hash;
- int i;
-
- if (cros_ec_read_hash(dev, &hash)) {
- debug("%s: Could not read KBC hash\n", __func__);
- return 1;
- }
-
- if (hash.hash_type == EC_VBOOT_HASH_TYPE_SHA256)
- printf("type: SHA-256\n");
- else
- printf("type: %d\n", hash.hash_type);
-
- printf("offset: 0x%08x\n", hash.offset);
- printf("size: 0x%08x\n", hash.size);
-
- printf("digest: ");
- for (i = 0; i < hash.digest_size; i++)
- printf("%02x", hash.hash_digest[i]);
- printf("\n");
- } else if (0 == strcmp("reboot", cmd)) {
- int region;
- enum ec_reboot_cmd cmd;
-
- if (argc >= 3 && !strcmp(argv[2], "cold"))
- cmd = EC_REBOOT_COLD;
- else {
- region = cros_ec_decode_region(argc - 2, argv + 2);
- if (region == EC_FLASH_REGION_RO)
- cmd = EC_REBOOT_JUMP_RO;
- else if (region == EC_FLASH_REGION_RW)
- cmd = EC_REBOOT_JUMP_RW;
- else
- return CMD_RET_USAGE;
- }
-
- if (cros_ec_reboot(dev, cmd, 0)) {
- debug("%s: Could not reboot KBC\n", __func__);
- return 1;
- }
- } else if (0 == strcmp("events", cmd)) {
- uint32_t events;
-
- if (cros_ec_get_host_events(dev, &events)) {
- debug("%s: Could not read host events\n", __func__);
- return 1;
- }
- printf("0x%08x\n", events);
- } else if (0 == strcmp("clrevents", cmd)) {
- uint32_t events = 0x7fffffff;
-
- if (argc >= 3)
- events = simple_strtol(argv[2], NULL, 0);
-
- if (cros_ec_clear_host_events(dev, events)) {
- debug("%s: Could not clear host events\n", __func__);
- return 1;
- }
- } else if (0 == strcmp("read", cmd)) {
- ret = do_read_write(dev, 0, argc, argv);
- if (ret > 0)
- return CMD_RET_USAGE;
- } else if (0 == strcmp("write", cmd)) {
- ret = do_read_write(dev, 1, argc, argv);
- if (ret > 0)
- return CMD_RET_USAGE;
- } else if (0 == strcmp("erase", cmd)) {
- int region = cros_ec_decode_region(argc - 2, argv + 2);
- uint32_t offset, size;
-
- if (region == -1)
- return CMD_RET_USAGE;
- if (cros_ec_flash_offset(dev, region, &offset, &size)) {
- debug("%s: Could not read region info\n", __func__);
- ret = -1;
- } else {
- ret = cros_ec_flash_erase(dev, offset, size);
- if (ret) {
- debug("%s: Could not erase region\n",
- __func__);
- }
- }
- } else if (0 == strcmp("regioninfo", cmd)) {
- int region = cros_ec_decode_region(argc - 2, argv + 2);
- uint32_t offset, size;
-
- if (region == -1)
- return CMD_RET_USAGE;
- ret = cros_ec_flash_offset(dev, region, &offset, &size);
- if (ret) {
- debug("%s: Could not read region info\n", __func__);
- } else {
- printf("Region: %s\n", region == EC_FLASH_REGION_RO ?
- "RO" : "RW");
- printf("Offset: %x\n", offset);
- printf("Size: %x\n", size);
- }
- } else if (0 == strcmp("vbnvcontext", cmd)) {
- uint8_t block[EC_VBNV_BLOCK_SIZE];
- char buf[3];
- int i, len;
- unsigned long result;
-
- if (argc <= 2) {
- ret = cros_ec_read_vbnvcontext(dev, block);
- if (!ret) {
- printf("vbnv_block: ");
- for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++)
- printf("%02x", block[i]);
- putc('\n');
- }
- } else {
- /*
- * TODO(clchiou): Move this to a utility function as
- * cmd_spi might want to call it.
- */
- memset(block, 0, EC_VBNV_BLOCK_SIZE);
- len = strlen(argv[2]);
- buf[2] = '\0';
- for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++) {
- if (i * 2 >= len)
- break;
- buf[0] = argv[2][i * 2];
- if (i * 2 + 1 >= len)
- buf[1] = '0';
- else
- buf[1] = argv[2][i * 2 + 1];
- strict_strtoul(buf, 16, &result);
- block[i] = result;
- }
- ret = cros_ec_write_vbnvcontext(dev, block);
- }
- if (ret) {
- debug("%s: Could not %s VbNvContext\n", __func__,
- argc <= 2 ? "read" : "write");
- }
- } else if (0 == strcmp("test", cmd)) {
- int result = cros_ec_test(dev);
-
- if (result)
- printf("Test failed with error %d\n", result);
- else
- puts("Test passed\n");
- } else if (0 == strcmp("version", cmd)) {
- struct ec_response_get_version *p;
- char *build_string;
-
- ret = cros_ec_read_version(dev, &p);
- if (!ret) {
- /* Print versions */
- printf("RO version: %1.*s\n",
- (int)sizeof(p->version_string_ro),
- p->version_string_ro);
- printf("RW version: %1.*s\n",
- (int)sizeof(p->version_string_rw),
- p->version_string_rw);
- printf("Firmware copy: %s\n",
- (p->current_image <
- ARRAY_SIZE(ec_current_image_name) ?
- ec_current_image_name[p->current_image] :
- "?"));
- ret = cros_ec_read_build_info(dev, &build_string);
- if (!ret)
- printf("Build info: %s\n", build_string);
- }
- } else if (0 == strcmp("ldo", cmd)) {
- uint8_t index, state;
- char *endp;
-
- if (argc < 3)
- return CMD_RET_USAGE;
- index = simple_strtoul(argv[2], &endp, 10);
- if (*argv[2] == 0 || *endp != 0)
- return CMD_RET_USAGE;
- if (argc > 3) {
- state = simple_strtoul(argv[3], &endp, 10);
- if (*argv[3] == 0 || *endp != 0)
- return CMD_RET_USAGE;
- ret = cros_ec_set_ldo(udev, index, state);
- } else {
- ret = cros_ec_get_ldo(udev, index, &state);
- if (!ret) {
- printf("LDO%d: %s\n", index,
- state == EC_LDO_STATE_ON ?
- "on" : "off");
- }
- }
-
- if (ret) {
- debug("%s: Could not access LDO%d\n", __func__, index);
- return ret;
- }
- } else {
- return CMD_RET_USAGE;
- }
-
- if (ret < 0) {
- printf("Error: CROS-EC command failed (error %d)\n", ret);
- ret = 1;
- }
-
- return ret;
-}
-
-U_BOOT_CMD(
- crosec, 6, 1, do_cros_ec,
- "CROS-EC utility command",
- "init Re-init CROS-EC (done on startup automatically)\n"
- "crosec id Read CROS-EC ID\n"
- "crosec info Read CROS-EC info\n"
- "crosec curimage Read CROS-EC current image\n"
- "crosec hash Read CROS-EC hash\n"
- "crosec reboot [rw | ro | cold] Reboot CROS-EC\n"
- "crosec events Read CROS-EC host events\n"
- "crosec clrevents [mask] Clear CROS-EC host events\n"
- "crosec regioninfo <ro|rw> Read image info\n"
- "crosec erase <ro|rw> Erase EC image\n"
- "crosec read <ro|rw> <addr> [<size>] Read EC image\n"
- "crosec write <ro|rw> <addr> [<size>] Write EC image\n"
- "crosec vbnvcontext [hexstring] Read [write] VbNvContext from EC\n"
- "crosec ldo <idx> [<state>] Switch/Read LDO state\n"
- "crosec test run tests on cros_ec\n"
- "crosec version Read CROS-EC version"
-);
-#endif
-
UCLASS_DRIVER(cros_ec) = {
.id = UCLASS_CROS_EC,
.name = "cros_ec",
diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c
deleted file mode 100644
index 98d9fbe..0000000
--- a/drivers/misc/fsl_debug_server.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/system.h>
-
-#include <fsl-mc/fsl_mc.h>
-#include <fsl_debug_server.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-static int debug_server_ver_info_maj, debug_server_ver_info_min;
-
-/**
- * Copying Debug Server firmware to DDR
- */
-static int debug_server_copy_image(const char *title, u64 image_addr,
- u32 image_size, u64 debug_server_ram_addr)
-{
- debug("%s copied to address %p\n", title,
- (void *)debug_server_ram_addr);
- memcpy((void *)debug_server_ram_addr, (void *)image_addr, image_size);
-
- return 0;
-}
-
-/**
- * Debug Server FIT image parser checks if the image is in FIT
- * format, verifies integrity of the image and calculates
- * raw image address and size values.
- *
- * Returns 0 if success and -1 if any of the above mentioned
- * task fail.
- **/
-int debug_server_parse_firmware_fit_image(const void **raw_image_addr,
- size_t *raw_image_size)
-{
- int format;
- void *fit_hdr;
- int node_offset;
- const void *data;
- size_t size;
- const char *uname = "firmware";
- char *desc;
- char *debug_server_ver_info;
- char *debug_server_ver_info_major, *debug_server_ver_info_minor;
-
- /* Check if the image is in NOR flash */
-#ifdef CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
- fit_hdr = (void *)CONFIG_SYS_DEBUG_SERVER_FW_ADDR;
-#else
-#error "CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR not defined"
-#endif
-
- /* Check if Image is in FIT format */
- format = genimg_get_format(fit_hdr);
- if (format != IMAGE_FORMAT_FIT) {
- printf("Debug Server FW: Not a FIT image\n");
- goto out_error;
- }
-
- if (!fit_check_format(fit_hdr)) {
- printf("Debug Server FW: Bad FIT image format\n");
- goto out_error;
- }
-
- node_offset = fit_image_get_node(fit_hdr, uname);
- if (node_offset < 0) {
- printf("Debug Server FW:Can not find %s subimage\n", uname);
- goto out_error;
- }
-
- /* Verify Debug Server firmware image */
- if (!fit_image_verify(fit_hdr, node_offset)) {
- printf("Debug Server FW: Bad Debug Server firmware hash");
- goto out_error;
- }
-
- if (fit_get_desc(fit_hdr, node_offset, &desc) < 0) {
- printf("Debug Server FW: Failed to get FW description");
- goto out_error;
- }
-
- debug_server_ver_info = strstr(desc, "Version");
- debug_server_ver_info_major = strtok(debug_server_ver_info, ".");
- debug_server_ver_info_minor = strtok(NULL, ".");
-
- debug_server_ver_info_maj =
- simple_strtoul(debug_server_ver_info_major, NULL, 10);
- debug_server_ver_info_min =
- simple_strtoul(debug_server_ver_info_minor, NULL, 10);
-
- /* Debug server version checking */
- if ((debug_server_ver_info_maj < DEBUG_SERVER_VER_MAJOR) ||
- (debug_server_ver_info_min < DEBUG_SERVER_VER_MINOR)) {
- printf("Debug server FW mismatches the min version required\n");
- printf("Expected:%d.%d, Got %d.%d\n",
- DEBUG_SERVER_VER_MAJOR, DEBUG_SERVER_VER_MINOR,
- debug_server_ver_info_maj,
- debug_server_ver_info_min);
- goto out_error;
- }
-
- /* Get address and size of raw image */
- fit_image_get_data(fit_hdr, node_offset, &data, &size);
-
- *raw_image_addr = data;
- *raw_image_size = size;
-
- return 0;
-
-out_error:
- return -1;
-}
-
-/**
- * Return the actual size of the Debug Server private DRAM block.
- *
- * NOTE: For now this function always returns the minimum required size,
- * However, in the future, the actual size may be obtained from an environment
- * variable.
- */
-unsigned long debug_server_get_dram_block_size(void)
-{
- return CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE;
-}
-
-int debug_server_init(void)
-{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- int error, timeout = CONFIG_SYS_DEBUG_SERVER_TIMEOUT;
- int debug_server_boot_status;
- u64 debug_server_ram_addr, debug_server_ram_size;
- const void *raw_image_addr;
- size_t raw_image_size = 0;
-
- debug("debug_server_init called\n");
- /*
- * The Debug Server private DRAM block was already carved at the end of
- * DRAM by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
- */
- debug_server_ram_size = debug_server_get_dram_block_size();
- if (gd->bd->bi_dram[1].start)
- debug_server_ram_addr =
- gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
- else
- debug_server_ram_addr =
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
-
-#ifdef CONFIG_FSL_MC_ENET
- debug_server_ram_addr += mc_get_dram_block_size();
-#endif
-
- error = debug_server_parse_firmware_fit_image(&raw_image_addr,
- &raw_image_size);
- if (error != 0)
- goto out;
-
- debug("debug server (ram addr = 0x%llx, ram size = 0x%llx)\n",
- debug_server_ram_addr, debug_server_ram_size);
- /*
- * Load the Debug Server FW at the beginning of the Debug Server
- * private DRAM block:
- */
- debug_server_copy_image("Debug Server Firmware",
- (u64)raw_image_addr, raw_image_size,
- debug_server_ram_addr);
-
- /* flush dcache */
- flush_dcache_range((unsigned long)debug_server_ram_addr,
- (unsigned long)debug_server_ram_addr +
- (unsigned long)debug_server_ram_size);
-
- /*
- * Tell SP that the Debug Server FW is about to be launched. Before that
- * populate the following:
- * 1. Write the size allocated to SP Memory region into Bits {31:16} of
- * SCRATCHRW5.
- * 2. Write the start address of the SP memory regions into
- * SCRATCHRW5 (Bits {15:0}, contain most significant bits, Bits
- * {47:32} of the SP Memory Region physical start address
- * (SoC address)) and SCRATCHRW6 (Bits {31:0}).
- * 3. To know the Debug Server FW boot status, set bit 0 of SCRATCHRW11
- * to 1. The Debug Server sets this to 0 to indicate a
- * successul boot.
- * 4. Wakeup SP by writing 0x1F to VSG GIC reg VIGR2.
- */
-
- /* 512 MB */
- out_le32(&gur->scratchrw[5 - 1],
- (u32)((u64)debug_server_ram_addr >> 32) | (0x000D << 16));
- out_le32(&gur->scratchrw[6 - 1],
- ((u32)debug_server_ram_addr) & 0xFFFFFFFF);
-
- out_le32(&gur->scratchrw[11 - 1], DEBUG_SERVER_INIT_STATUS);
- /* Allow the changes to reflect in GUR block */
- mb();
-
- /*
- * Program VGIC to raise an interrupt to SP
- */
- out_le32(CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2, 0x1F);
- /* Allow the changes to reflect in VIGR2 */
- mb();
-
- dmb();
- debug("Polling for Debug server to launch ...\n");
-
- while (1) {
- debug_server_boot_status = in_le32(&gur->scratchrw[11 - 1]);
- if (!(debug_server_boot_status & DEBUG_SERVER_INIT_STATUS_MASK))
- break;
-
- udelay(1); /* throttle polling */
- if (timeout-- <= 0)
- break;
- }
-
- if (timeout <= 0) {
- printf("Debug Server FW timed out (boot status: 0x%x)\n",
- debug_server_boot_status);
- error = -ETIMEDOUT;
- goto out;
- }
-
- if (debug_server_boot_status & DEBUG_SERVER_INIT_STATUS_MASK) {
- printf("Debug server FW error'ed out (boot status: 0x%x)\n",
- debug_server_boot_status);
- error = -ENODEV;
- goto out;
- }
-
- printf("Debug server booted\n");
- printf("Detected firmware %d.%d, (boot status: 0x0%x)\n",
- debug_server_ver_info_maj, debug_server_ver_info_min,
- debug_server_boot_status);
-
-out:
- if (error != 0)
- debug_server_boot_status = -error;
- else
- debug_server_boot_status = 0;
-
- return debug_server_boot_status;
-}
-
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
index 36433a7..2feb182 100644
--- a/drivers/misc/fsl_iim.c
+++ b/drivers/misc/fsl_iim.c
@@ -11,7 +11,7 @@
#include <common.h>
#include <fuse.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#ifndef CONFIG_MPC512X
#include <asm/arch/imx-regs.h>
diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c
index d482a7d..415232e 100644
--- a/drivers/misc/fsl_sec_mon.c
+++ b/drivers/misc/fsl_sec_mon.c
@@ -7,140 +7,158 @@
#include <common.h>
#include <fsl_sec_mon.h>
-int change_sec_mon_state(u32 initial_state, u32 final_state)
+static u32 get_sec_mon_state(void)
{
struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
(CONFIG_SYS_SEC_MON_ADDR);
- u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+ return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK;
+}
+
+static int set_sec_mon_state_non_sec(void)
+{
+ u32 sts;
int timeout = 10;
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
- if ((sts & HPSR_SSM_ST_MASK) != initial_state)
- return -1;
+ sts = get_sec_mon_state();
- if (initial_state == HPSR_SSM_ST_TRUST) {
- switch (final_state) {
- case HPSR_SSM_ST_NON_SECURE:
- printf("SEC_MON state transitioning to Soft Fail.\n");
- sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
+ switch (sts) {
+ /*
+ * If initial state is check or Non-Secure, then set the Software
+ * Security Violation Bit and transition to Non-Secure State.
+ */
+ case HPSR_SSM_ST_CHECK:
+ printf("SEC_MON state transitioning to Non Secure.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
- /*
- * poll till SEC_MON is in
- * Soft Fail state
- */
- while (((sts & HPSR_SSM_ST_MASK) !=
- HPSR_SSM_ST_SOFT_FAIL)) {
- while (timeout) {
- sts = sec_mon_in32
- (&sec_mon_regs->hp_stat);
+ /* polling loop till SEC_MON is in Non Secure state */
+ while (timeout) {
+ sts = get_sec_mon_state();
- if ((sts & HPSR_SSM_ST_MASK) ==
- HPSR_SSM_ST_SOFT_FAIL)
- break;
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_NON_SECURE)
+ break;
- udelay(10);
- timeout--;
- }
- }
+ udelay(10);
+ timeout--;
+ }
- if (timeout == 0) {
- printf("SEC_MON state transition timeout.\n");
- return -1;
- }
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
- timeout = 10;
+ /*
+ * If initial state is Trusted, Secure or Soft-Fail, then first set
+ * the Software Security Violation Bit and transition to Soft-Fail
+ * State.
+ */
+ case HPSR_SSM_ST_TRUST:
+ case HPSR_SSM_ST_SECURE:
+ case HPSR_SSM_ST_SOFT_FAIL:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
+ /* polling loop till SEC_MON is in Soft-Fail state */
+ while (timeout) {
+ sts = get_sec_mon_state();
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+
+ timeout = 10;
+
+ /*
+ * If SSM Soft Fail to Non-Secure State Transition
+ * disable is not set, then set SSM_ST bit and
+ * transition to Non-Secure State.
+ */
+ if ((sec_mon_in32(&sec_mon_regs->hp_com) &
+ HPCOMR_SSM_SFNS_DIS) == 0) {
printf("SEC_MON state transitioning to Non Secure.\n");
sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST);
- /*
- * poll till SEC_MON is in
- * Non Secure state
- */
- while (((sts & HPSR_SSM_ST_MASK) !=
- HPSR_SSM_ST_NON_SECURE)) {
- while (timeout) {
- sts = sec_mon_in32
- (&sec_mon_regs->hp_stat);
+ /* polling loop till SEC_MON is in Non Secure*/
+ while (timeout) {
+ sts = get_sec_mon_state();
- if ((sts & HPSR_SSM_ST_MASK) ==
- HPSR_SSM_ST_NON_SECURE)
- break;
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_NON_SECURE)
+ break;
- udelay(10);
- timeout--;
- }
+ udelay(10);
+ timeout--;
}
if (timeout == 0) {
printf("SEC_MON state transition timeout.\n");
return -1;
}
- break;
- case HPSR_SSM_ST_SOFT_FAIL:
- printf("SEC_MON state transitioning to Soft Fail.\n");
- sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
-
- /*
- * polling loop till SEC_MON is in
- * Soft Fail state
- */
- while (((sts & HPSR_SSM_ST_MASK) !=
- HPSR_SSM_ST_SOFT_FAIL)) {
- while (timeout) {
- sts = sec_mon_in32
- (&sec_mon_regs->hp_stat);
-
- if ((sts & HPSR_SSM_ST_MASK) ==
- HPSR_SSM_ST_SOFT_FAIL)
- break;
-
- udelay(10);
- timeout--;
- }
- }
-
- if (timeout == 0) {
- printf("SEC_MON state transition timeout.\n");
- return -1;
- }
- break;
- default:
- return -1;
}
- } else if (initial_state == HPSR_SSM_ST_NON_SECURE) {
- switch (final_state) {
- case HPSR_SSM_ST_SOFT_FAIL:
- printf("SEC_MON state transitioning to Soft Fail.\n");
- sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
+ break;
+ default:
+ printf("SEC_MON already in Non Secure state.\n");
+ return 0;
+ }
+ return 0;
+}
- /*
- * polling loop till SEC_MON is in
- * Soft Fail state
- */
- while (((sts & HPSR_SSM_ST_MASK) !=
- HPSR_SSM_ST_SOFT_FAIL)) {
- while (timeout) {
- sts = sec_mon_in32
- (&sec_mon_regs->hp_stat);
+static int set_sec_mon_state_soft_fail(void)
+{
+ u32 sts;
+ int timeout = 10;
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
- if ((sts & HPSR_SSM_ST_MASK) ==
- HPSR_SSM_ST_SOFT_FAIL)
- break;
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
- udelay(10);
- timeout--;
- }
- }
+ /* polling loop till SEC_MON is in Soft-Fail state */
+ while (timeout) {
+ sts = get_sec_mon_state();
- if (timeout == 0) {
- printf("SEC_MON state transition timeout.\n");
- return -1;
- }
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
break;
- default:
- return -1;
- }
+
+ udelay(10);
+ timeout--;
}
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
return 0;
}
+
+int set_sec_mon_state(u32 state)
+{
+ int ret = -1;
+
+ switch (state) {
+ case HPSR_SSM_ST_NON_SECURE:
+ ret = set_sec_mon_state_non_sec();
+ break;
+ case HPSR_SSM_ST_SOFT_FAIL:
+ ret = set_sec_mon_state_soft_fail();
+ break;
+ default:
+ printf("SEC_MON state transition not supported.\n");
+ return 0;
+ }
+
+ return ret;
+}
diff --git a/drivers/misc/mc9sdz60.c b/drivers/misc/mc9sdz60.c
index cd56b58..61ed50d 100644
--- a/drivers/misc/mc9sdz60.c
+++ b/drivers/misc/mc9sdz60.c
@@ -7,7 +7,7 @@
#include <config.h>
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/types.h>
#include <i2c.h>
#include <mc9sdz60.h>
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 38344e8..0b1c050 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -14,10 +14,11 @@
#include <common.h>
#include <fuse.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/sys_proto.h>
#define BO_CTRL_WR_UNLOCK 16
#define BM_CTRL_WR_UNLOCK 0xffff0000
@@ -61,6 +62,8 @@
#define FUSE_BANK_SIZE 0x80
#ifdef CONFIG_MX6SL
#define FUSE_BANKS 8
+#elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
+#define FUSE_BANKS 9
#else
#define FUSE_BANKS 16
#endif
@@ -72,11 +75,11 @@
#endif
#if defined(CONFIG_MX6)
-#include <asm/arch/sys_proto.h>
/*
* There is a hole in shadow registers address map of size 0x100
- * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
+ * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
+ * iMX6UL, i.MX6ULL and i.MX6SLL.
* Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
* we should account for this hole in address space.
*
@@ -97,7 +100,10 @@
if (is_mx6sl()) {
phy_index = index;
- } else if (is_mx6ul()) {
+ } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
+ if ((is_mx6ull() || is_mx6sll()) && index == 8)
+ index = 7;
+
if (index >= 6)
phy_index = fuse_bank_physical(5) + (index - 6) + 3;
else
@@ -112,11 +118,27 @@
}
return phy_index;
}
+
+u32 fuse_word_physical(u32 bank, u32 word_index)
+{
+ if (is_mx6ull() || is_mx6sll()) {
+ if (bank == 8)
+ word_index = word_index + 4;
+ }
+
+ return word_index;
+}
#else
u32 fuse_bank_physical(int index)
{
return index;
}
+
+u32 fuse_word_physical(u32 bank, u32 word_index)
+{
+ return word_index;
+}
+
#endif
static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
@@ -142,6 +164,14 @@
return -EINVAL;
}
+ if (is_mx6ull() || is_mx6sll()) {
+ if ((bank == 7 || bank == 8) &&
+ word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
+ printf("mxc_ocotp %s(): Invalid argument\n", caller);
+ return -EINVAL;
+ }
+ }
+
enable_ocotp_clk(1);
wait_busy(*regs, 1);
@@ -176,14 +206,16 @@
struct ocotp_regs *regs;
int ret;
u32 phy_bank;
+ u32 phy_word;
ret = prepare_read(®s, bank, word, val, __func__);
if (ret)
return ret;
phy_bank = fuse_bank_physical(bank);
+ phy_word = fuse_word_physical(bank, word);
- *val = readl(®s->bank[phy_bank].fuse_regs[word << 2]);
+ *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]);
return finish_access(regs, __func__);
}
@@ -237,7 +269,13 @@
#ifdef CONFIG_MX7
u32 addr = bank;
#else
- u32 addr = bank << 3 | word;
+ u32 addr;
+ /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
+ if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
+ bank = bank - 1;
+ word += 4;
+ }
+ addr = bank << 3 | word;
#endif
set_timing(regs);
@@ -325,14 +363,16 @@
struct ocotp_regs *regs;
int ret;
u32 phy_bank;
+ u32 phy_word;
ret = prepare_write(®s, bank, word, __func__);
if (ret)
return ret;
phy_bank = fuse_bank_physical(bank);
+ phy_word = fuse_word_physical(bank, word);
- writel(val, ®s->bank[phy_bank].fuse_regs[word << 2]);
+ writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]);
return finish_access(regs, __func__);
}
diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c
index 6c0d247..a42164c 100644
--- a/drivers/misc/mxs_ocotp.c
+++ b/drivers/misc/mxs_ocotp.c
@@ -14,7 +14,7 @@
#include <common.h>
#include <fuse.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/misc/tegra_car.c b/drivers/misc/tegra_car.c
new file mode 100644
index 0000000..0eb0096
--- /dev/null
+++ b/drivers/misc/tegra_car.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+
+/**
+ * The CAR exposes multiple different services. We create a sub-device for
+ * each separate type of service, since each device must be of the appropriate
+ * UCLASS.
+ */
+static int tegra_car_bpmp_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *child;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ ret = device_bind_driver_to_node(dev, "tegra_car_clk", "tegra_car_clk",
+ dev->of_offset, &child);
+ if (ret)
+ return ret;
+
+ ret = device_bind_driver_to_node(dev, "tegra_car_reset",
+ "tegra_car_reset", dev->of_offset,
+ &child);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int tegra_car_bpmp_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+static int tegra_car_bpmp_remove(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+static const struct udevice_id tegra_car_bpmp_ids[] = {
+ { .compatible = "nvidia,tegra20-car" },
+ { .compatible = "nvidia,tegra30-car" },
+ { .compatible = "nvidia,tegra114-car" },
+ { .compatible = "nvidia,tegra124-car" },
+ { .compatible = "nvidia,tegra210-car" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra_car_bpmp) = {
+ .name = "tegra_car",
+ .id = UCLASS_MISC,
+ .of_match = tegra_car_bpmp_ids,
+ .bind = tegra_car_bpmp_bind,
+ .probe = tegra_car_bpmp_probe,
+ .remove = tegra_car_bpmp_remove,
+};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index a71afa5..c3462ab 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -1,10 +1,14 @@
menu "MMC Host controller Support"
config MMC
- bool "Enable MMC support"
- depends on ARCH_SUNXI || SANDBOX
+ bool "MMC/SD/SDIO card support"
+ default ARM || PPC || SANDBOX
help
- TODO: Move all architectures to use this option
+ This selects MultiMediaCard, Secure Digital and Secure
+ Digital I/O support.
+
+ If you want MMC/SD/SDIO support, you should say Y here and
+ also to your specific host controller driver.
config DM_MMC
bool "Enable MMC controllers using Driver Model"
@@ -19,15 +23,34 @@
config DM_MMC_OPS
bool "Support MMC controller operations using Driver Model"
depends on DM_MMC
+ default y if DM_MMC
help
Driver model provides a means of supporting device operations. This
option moves MMC operations under the control of driver model. The
option will be removed as soon as all DM_MMC drivers use it, as it
will the only supported behaviour.
+if MMC
+
+config SPL_MMC_TINY
+ bool "Tiny MMC framework in SPL"
+ help
+ Enable MMC framework tinification support. This option is useful if
+ if your SPL is extremely size constrained. Heed the warning, enable
+ this option if and only if you know exactly what you are doing, if
+ you are reading this help text, you most likely have no idea :-)
+
+ The MMC framework is reduced to bare minimum to be useful. No malloc
+ support is needed for the MMC framework operation with this option
+ enabled. The framework supports exactly one MMC device and exactly
+ one MMC driver. The MMC driver can be adjusted to avoid any malloc
+ operations too, which can remove the need for malloc support in SPL
+ and thus further reduce footprint.
+
config MSM_SDHCI
bool "Qualcomm SDHCI controller"
depends on DM_MMC && BLK && DM_MMC_OPS
+ depends on MMC_SDHCI
help
Enables support for SDHCI 2.0 controller present on some Qualcomm
Snapdragon devices. This device is compatible with eMMC v4.5 and
@@ -37,6 +60,7 @@
config ATMEL_SDHCI
bool "Atmel SDHCI controller support"
depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
+ depends on MMC_SDHCI
help
This enables support for the Atmel SDHCI controller, which supports
the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
@@ -62,24 +86,28 @@
config PIC32_SDHCI
bool "Microchip PIC32 on-chip SDHCI support"
depends on DM_MMC && MACH_PIC32
+ depends on MMC_SDHCI
help
Support for Microchip PIC32 SDHCI controller.
config ZYNQ_SDHCI
bool "Arasan SDHCI controller support"
- depends on DM_MMC && OF_CONTROL
+ depends on DM_MMC && OF_CONTROL && BLK && DM_MMC_OPS
+ depends on MMC_SDHCI
help
Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform
config ROCKCHIP_SDHCI
bool "Arasan SDHCI controller for Rockchip support"
depends on DM_MMC && BLK && DM_MMC_OPS
+ depends on MMC_SDHCI
help
Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform
config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
+ depends on BLK
select DM_MMC_OPS
help
This selects support for the SD/MMC Host Controller on UniPhier SoCs.
@@ -93,4 +121,101 @@
improves build coverage for sandbox and makes it easier to detect
MMC build errors with sandbox.
+config MMC_SDHCI
+ bool "Secure Digital Host Controller Interface support"
+ help
+ This selects the generic Secure Digital Host Controller Interface.
+ It is used by manufacturers such as Texas Instruments(R), Ricoh(R)
+ and Toshiba(R). Most controllers found in laptops are of this type.
+
+ If you have a controller with this interface, say Y here.
+
+ If unsure, say N.
+
+config MMC_SDHCI_IO_ACCESSORS
+ bool
+ depends on MMC_SDHCI
+ help
+ This is silent Kconfig symbol that is selected by the drivers that
+ need to overwrite SDHCI IO memory accessors.
+
+config MMC_SDHCI_SDMA
+ bool "Support SDHCI SDMA"
+ depends on MMC_SDHCI
+ help
+ This enables support for the SDMA (Single Operation DMA) defined
+ in the SD Host Controller Standard Specification Version 1.00 .
+
+config MMC_SDHCI_BCM2835
+ tristate "SDHCI support for the BCM2835 SD/MMC Controller"
+ depends on ARCH_BCM283X
+ depends on MMC_SDHCI
+ select MMC_SDHCI_IO_ACCESSORS
+ help
+ This selects the BCM2835 SD/MMC controller.
+
+ If you have a BCM2835 platform with SD or MMC devices,
+ say Y here.
+
+ If unsure, say N.
+
+config MMC_SDHCI_KONA
+ bool "SDHCI support on Broadcom KONA platform"
+ depends on MMC_SDHCI
+ help
+ This selects the Broadcom Kona Secure Digital Host Controller
+ Interface(SDHCI) support.
+ This is used in Broadcom mobile SoCs.
+
+ If you have a controller with this interface, say Y here.
+
+config MMC_SDHCI_MV
+ bool "SDHCI support on Marvell platform"
+ depends on ARCH_MVEBU
+ depends on MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface on
+ Marvell platform.
+
+ If you have a controller with this interface, say Y here.
+
+ If unsure, say N.
+
+config MMC_SDHCI_S5P
+ bool "SDHCI support on Samsung S5P SoC"
+ depends on MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ on Samsung S5P SoCs.
+
+ If you have a controller with this interface, say Y here.
+
+ If unsure, say N.
+
+config MMC_SDHCI_SPEAR
+ bool "SDHCI support on ST SPEAr platform"
+ depends on MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ often referrered to as the HSMMC block in some of the ST SPEAR range
+ of SoC
+
+ If you have a controller with this interface, say Y here.
+
+ If unsure, say N.
+
+endif
+
endmenu
+
+config SYS_FSL_ERRATUM_ESDHC111
+ bool
+
+config SYS_FSL_ERRATUM_ESDHC13
+ bool
+
+config SYS_FSL_ERRATUM_ESDHC135
+ bool
+
+config SYS_FSL_ERRATUM_ESDHC_A001
+ bool
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 18351fb..2b136ea 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -15,7 +15,6 @@
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
-obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
obj-$(CONFIG_DWMMC) += dw_mmc.o
@@ -29,10 +28,8 @@
obj-$(CONFIG_GENERIC_MMC) += mmc_boot.o
endif
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
-obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
obj-$(CONFIG_MMC_SPI) += mmc_spi.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
-obj-$(CONFIG_MV_SDHCI) += mv_sdhci.o
obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
obj-$(CONFIG_MXC_MMC) += mxcmmc.o
obj-$(CONFIG_MXS_MMC) += mxsmmc.o
@@ -42,17 +39,14 @@
obj-$(CONFIG_ROCKCHIP_DWMMC) += rockchip_dw_mmc.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
-obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
ifdef CONFIG_BLK
ifdef CONFIG_GENERIC_MMC
obj-$(CONFIG_SANDBOX) += sandbox_mmc.o
endif
endif
-obj-$(CONFIG_SDHCI) += sdhci.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
-obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
@@ -60,8 +54,17 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
+obj-$(CONFIG_SPL_SAVEENV) += mmc_write.o
else
obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
endif
obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o
+
+# SDHCI
+obj-$(CONFIG_MMC_SDHCI) += sdhci.o
+obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index dd6bd33..6654b54 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -29,7 +29,6 @@
host->name = "atmel_sdhci";
host->ioaddr = regbase;
host->quirks = 0;
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
max_clk = at91_get_periph_generated_clk(id);
if (!max_clk) {
printf("%s: Failed to get the proper clock\n", __func__);
@@ -51,29 +50,6 @@
struct mmc mmc;
};
-static int atmel_sdhci_get_clk(struct udevice *dev, int index, struct clk *clk)
-{
- struct udevice *dev_clk;
- int periph, ret;
-
- ret = clk_get_by_index(dev, index, clk);
- if (ret)
- return ret;
-
- periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1);
- if (periph < 0)
- return -EINVAL;
-
- dev_clk = dev_get_parent(clk->dev);
- ret = clk_request(dev_clk, clk);
- if (ret)
- return ret;
-
- clk->id = periph;
-
- return 0;
-}
-
static int atmel_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
@@ -86,7 +62,7 @@
struct clk clk;
int ret;
- ret = atmel_sdhci_get_clk(dev, 0, &clk);
+ ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
@@ -107,7 +83,7 @@
clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
gck_rate = clk_base * 1000000 * (clk_mul + 1);
- ret = atmel_sdhci_get_clk(dev, 1, &clk);
+ ret = clk_get_by_index(dev, 1, &clk);
if (ret)
return ret;
@@ -136,13 +112,8 @@
static int atmel_sdhci_bind(struct udevice *dev)
{
struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
- int ret;
- ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
- if (ret)
- return ret;
-
- return 0;
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static const struct udevice_id atmel_sdhci_ids[] = {
diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index 5bc1785..9ae271c 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -160,7 +160,7 @@
bcm_host = calloc(1, sizeof(*bcm_host));
if (!bcm_host) {
printf("sdhci_host calloc fail!\n");
- return 1;
+ return -ENOMEM;
}
/*
@@ -187,7 +187,6 @@
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->ops = &bcm2835_ops;
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
add_sdhci(host, emmc_freq, MIN_FREQ);
return 0;
diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c
index 0e493da..993a00c 100644
--- a/drivers/mmc/bfin_sdh.c
+++ b/drivers/mmc/bfin_sdh.c
@@ -12,7 +12,7 @@
#include <mmc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/byteorder.h>
#include <asm/blackfin.h>
#include <asm/clock.h>
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index afc674d..d6ac46c 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -120,9 +120,9 @@
if (host->fifo_mode && size) {
len = 0;
- if (data->flags == MMC_DATA_READ) {
- if ((dwmci_readl(host, DWMCI_RINTSTS) &
- DWMCI_INTMSK_RXDR)) {
+ if (data->flags == MMC_DATA_READ &&
+ (mask & DWMCI_INTMSK_RXDR)) {
+ while (size) {
len = dwmci_readl(host, DWMCI_STATUS);
len = (len >> DWMCI_FIFO_SHIFT) &
DWMCI_FIFO_MASK;
@@ -130,12 +130,13 @@
for (i = 0; i < len; i++)
*buf++ =
dwmci_readl(host, DWMCI_DATA);
- dwmci_writel(host, DWMCI_RINTSTS,
- DWMCI_INTMSK_RXDR);
+ size = size > len ? (size - len) : 0;
}
- } else {
- if ((dwmci_readl(host, DWMCI_RINTSTS) &
- DWMCI_INTMSK_TXDR)) {
+ dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_RXDR);
+ } else if (data->flags == MMC_DATA_WRITE &&
+ (mask & DWMCI_INTMSK_TXDR)) {
+ while (size) {
len = dwmci_readl(host, DWMCI_STATUS);
len = fifo_depth - ((len >>
DWMCI_FIFO_SHIFT) &
@@ -144,11 +145,11 @@
for (i = 0; i < len; i++)
dwmci_writel(host, DWMCI_DATA,
*buf++);
- dwmci_writel(host, DWMCI_RINTSTS,
- DWMCI_INTMSK_TXDR);
+ size = size > len ? (size - len) : 0;
}
+ dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_TXDR);
}
- size = size > len ? (size - len) : 0;
}
/* Data arrived correctly. */
@@ -487,10 +488,10 @@
};
#endif
-void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
- uint caps, u32 max_clk, u32 min_clk)
+void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
+ u32 max_clk, u32 min_clk)
{
- cfg->name = name;
+ cfg->name = host->name;
#ifndef CONFIG_DM_MMC_OPS
cfg->ops = &dwmci_ops;
#endif
@@ -499,9 +500,9 @@
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- cfg->host_caps = caps;
+ cfg->host_caps = host->caps;
- if (buswidth == 8) {
+ if (host->buswidth == 8) {
cfg->host_caps |= MMC_MODE_8BIT;
cfg->host_caps &= ~MMC_MODE_4BIT;
} else {
@@ -521,8 +522,7 @@
#else
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
{
- dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
- max_clk, min_clk);
+ dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 57271f1..c440399 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -271,8 +271,7 @@
if (err)
return err;
- dwmci_setup_cfg(&plat->cfg, host->name, host->buswidth, host->caps,
- DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
+ dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
host->mmc = &plat->mmc;
host->mmc->priv = &priv->host;
host->priv = dev;
@@ -284,13 +283,8 @@
static int exynos_dwmmc_bind(struct udevice *dev)
{
struct exynos_mmc_plat *plat = dev_get_platdata(dev);
- int ret;
- ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
- if (ret)
- return ret;
-
- return 0;
+ return dwmci_bind(dev, &plat->mmc, &plat->cfg);
}
static const struct udevice_id exynos_dwmmc_ids[] = {
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 103b32e..9796d39 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -1010,6 +1010,7 @@
}
upriv->mmc = priv->mmc;
+ priv->mmc->dev = dev;
return 0;
}
diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
index c02740f..e88c632 100644
--- a/drivers/mmc/ftsdc010_mci.c
+++ b/drivers/mmc/ftsdc010_mci.c
@@ -13,7 +13,7 @@
#include <mmc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/byteorder.h>
#include <faraday/ftsdc010.h>
diff --git a/drivers/mmc/ftsdc021_sdhci.c b/drivers/mmc/ftsdc021_sdhci.c
index 1f6cdba..6e9fefa 100644
--- a/drivers/mmc/ftsdc021_sdhci.c
+++ b/drivers/mmc/ftsdc021_sdhci.c
@@ -21,7 +21,7 @@
host = calloc(1, sizeof(struct sdhci_host));
if (!host) {
puts("sdh_host malloc fail!\n");
- return 1;
+ return -ENOMEM;
}
host->name = "FTSDC021";
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 69770df..cca0b04 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -14,7 +14,7 @@
#include <part.h>
#include <malloc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/byteorder.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
index b0d063c..fdaf1e4 100644
--- a/drivers/mmc/hi6220_dw_mmc.c
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <dwmmc.h>
#include <malloc.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#define DWMMC_MAX_CH_NUM 4
diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c
index 3653d00..549f6bc 100644
--- a/drivers/mmc/kona_sdhci.c
+++ b/drivers/mmc/kona_sdhci.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <malloc.h>
#include <sdhci.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/kona-common/clk.h>
#define SDHCI_CORECTRL_OFFSET 0x00008000
@@ -27,7 +27,7 @@
if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
printf("%s: sd host controller reset error\n", __func__);
- return 1;
+ return -EBUSY;
}
/* For kona a hardware reset before anything else. */
@@ -39,7 +39,7 @@
do {
if (timeout == 0) {
printf("%s: reset timeout error\n", __func__);
- return 1;
+ return -ETIMEDOUT;
}
timeout--;
udelay(100);
@@ -67,7 +67,7 @@
while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
if (timeout == 0) {
printf("%s: CARD DETECT timeout error\n", __func__);
- return 1;
+ return -ETIMEDOUT;
}
timeout--;
udelay(100);
@@ -127,11 +127,6 @@
return -EINVAL;
}
- if (quirks & SDHCI_QUIRK_REG32_RW)
- host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
- else
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-
add_sdhci(host, max_clk, min_clk);
return ret;
}
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 425abb1..2fe5d61 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -116,13 +116,7 @@
int mmc_get_next_devnum(void)
{
- int ret;
-
- ret = blk_find_max_devnum(IF_TYPE_MMC);
- if (ret < 0)
- return ret;
-
- return ret;
+ return blk_find_max_devnum(IF_TYPE_MMC);
}
struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
@@ -243,7 +237,6 @@
struct udevice *mmc_dev = dev_get_parent(bdev);
struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
struct blk_desc *desc = dev_get_uclass_platdata(bdev);
- int ret;
if (desc->hwpart == hwpart)
return 0;
@@ -251,17 +244,14 @@
if (mmc->part_config == MMCPART_NOAVAILABLE)
return -EMEDIUMTYPE;
- ret = mmc_switch_part(mmc, hwpart);
- if (ret)
- return ret;
-
- return 0;
+ return mmc_switch_part(mmc, hwpart);
}
static const struct blk_ops mmc_blk_ops = {
.read = mmc_bread,
#ifndef CONFIG_SPL_BUILD
.write = mmc_bwrite,
+ .erase = mmc_berase,
#endif
.select_hwpart = mmc_select_hwpart,
};
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 43ea0bb..9f8368a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -15,12 +15,44 @@
#include <errno.h>
#include <mmc.h>
#include <part.h>
+#include <power/regulator.h>
#include <malloc.h>
#include <memalign.h>
#include <linux/list.h>
#include <div64.h>
#include "mmc_private.h"
+static const unsigned int sd_au_size[] = {
+ 0, SZ_16K / 512, SZ_32K / 512,
+ SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
+ SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
+ SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
+ SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
+};
+
+#if CONFIG_IS_ENABLED(MMC_TINY)
+static struct mmc mmc_static;
+struct mmc *find_mmc_device(int dev_num)
+{
+ return &mmc_static;
+}
+
+void mmc_do_preinit(void)
+{
+ struct mmc *m = &mmc_static;
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ mmc_set_preinit(m, 1);
+#endif
+ if (m->preinit)
+ mmc_start_init(m);
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+ return &mmc->block_dev;
+}
+#endif
+
#ifndef CONFIG_DM_MMC_OPS
__weak int board_mmc_getwp(struct mmc *mmc)
{
@@ -250,7 +282,11 @@
if (!mmc)
return 0;
- err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
+ if (CONFIG_IS_ENABLED(MMC_TINY))
+ err = mmc_switch_part(mmc, block_dev->hwpart);
+ else
+ err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
+
if (err < 0)
return 0;
@@ -485,6 +521,7 @@
{
struct mmc_cmd cmd;
int timeout = 1000;
+ int retries = 3;
int ret;
cmd.cmdidx = MMC_CMD_SWITCH;
@@ -493,11 +530,17 @@
(index << 16) |
(value << 8);
- ret = mmc_send_cmd(mmc, &cmd, NULL);
+ while (retries > 0) {
+ ret = mmc_send_cmd(mmc, &cmd, NULL);
- /* Waiting for the ready status */
- if (!ret)
- ret = mmc_send_status(mmc, timeout);
+ /* Waiting for the ready status */
+ if (!ret) {
+ ret = mmc_send_status(mmc, timeout);
+ return ret;
+ }
+
+ retries--;
+ }
return ret;
@@ -945,6 +988,62 @@
return 0;
}
+static int sd_read_ssr(struct mmc *mmc)
+{
+ int err, i;
+ struct mmc_cmd cmd;
+ ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
+ struct mmc_data data;
+ int timeout = 3;
+ unsigned int au, eo, et, es;
+
+ cmd.cmdidx = MMC_CMD_APP_CMD;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = mmc->rca << 16;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
+
+ cmd.cmdidx = SD_CMD_APP_SD_STATUS;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+
+retry_ssr:
+ data.dest = (char *)ssr;
+ data.blocksize = 64;
+ data.blocks = 1;
+ data.flags = MMC_DATA_READ;
+
+ err = mmc_send_cmd(mmc, &cmd, &data);
+ if (err) {
+ if (timeout--)
+ goto retry_ssr;
+
+ return err;
+ }
+
+ for (i = 0; i < 16; i++)
+ ssr[i] = be32_to_cpu(ssr[i]);
+
+ au = (ssr[2] >> 12) & 0xF;
+ if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
+ mmc->ssr.au = sd_au_size[au];
+ es = (ssr[3] >> 24) & 0xFF;
+ es |= (ssr[2] & 0xFF) << 8;
+ et = (ssr[3] >> 18) & 0x3F;
+ if (es && et) {
+ eo = (ssr[3] >> 16) & 0x3;
+ mmc->ssr.erase_timeout = (et * 1000) / es;
+ mmc->ssr.erase_offset = eo * 1000;
+ }
+ } else {
+ debug("Invalid Allocation Unit Size.\n");
+ }
+
+ return 0;
+}
+
/* frequency bases */
/* divided by 10 to be nice to platforms without floating point */
static const int fbase[] = {
@@ -1350,6 +1449,10 @@
mmc_set_bus_width(mmc, 4);
}
+ err = sd_read_ssr(mmc);
+ if (err)
+ return err;
+
if (mmc->card_caps & MMC_MODE_HS)
mmc->tran_speed = 50000000;
else
@@ -1514,6 +1617,31 @@
{
}
+static int mmc_power_init(struct mmc *mmc)
+{
+ board_mmc_power_init();
+
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_DM_REGULATOR) && \
+ !defined(CONFIG_SPL_BUILD)
+ struct udevice *vmmc_supply;
+ int ret;
+
+ ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
+ &vmmc_supply);
+ if (ret) {
+ debug("%s: No vmmc supply\n", mmc->dev->name);
+ return 0;
+ }
+
+ ret = regulator_set_enable(vmmc_supply, true);
+ if (ret) {
+ puts("Error enabling VMMC supply\n");
+ return ret;
+ }
+#endif
+ return 0;
+}
+
int mmc_start_init(struct mmc *mmc)
{
bool no_card;
@@ -1538,7 +1666,9 @@
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
mmc_adapter_card_type_ident();
#endif
- board_mmc_power_init();
+ err = mmc_power_init(mmc);
+ if (err)
+ return err;
#ifdef CONFIG_DM_MMC_OPS
/* The device has already been probed ready for use */
@@ -1605,7 +1735,7 @@
int mmc_init(struct mmc *mmc)
{
int err = 0;
- unsigned start;
+ __maybe_unused unsigned start;
#ifdef CONFIG_DM_MMC
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
@@ -1701,8 +1831,10 @@
initialized = 1;
#ifndef CONFIG_BLK
+#if !CONFIG_IS_ENABLED(MMC_TINY)
mmc_list_init();
#endif
+#endif
ret = mmc_probe(bis);
if (ret)
return ret;
@@ -1714,3 +1846,37 @@
mmc_do_preinit();
return 0;
}
+
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+int mmc_set_bkops_enable(struct mmc *mmc)
+{
+ int err;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+
+ err = mmc_send_ext_csd(mmc, ext_csd);
+ if (err) {
+ puts("Could not get ext_csd register values\n");
+ return err;
+ }
+
+ if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
+ puts("Background operations not supported on device\n");
+ return -EMEDIUMTYPE;
+ }
+
+ if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
+ puts("Background operations already enabled\n");
+ return 0;
+ }
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
+ if (err) {
+ puts("Failed to enable manual background operations\n");
+ return err;
+ }
+
+ puts("Enabled manual background operations\n");
+
+ return 0;
+}
+#endif
diff --git a/drivers/mmc/mmc_boot.c b/drivers/mmc/mmc_boot.c
index 756a982..ac6f56f 100644
--- a/drivers/mmc/mmc_boot.c
+++ b/drivers/mmc/mmc_boot.c
@@ -85,16 +85,10 @@
*/
int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
{
- int err;
-
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
- EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
- EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
- EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
-
- if (err)
- return err;
- return 0;
+ return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
+ EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
+ EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
+ EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
}
/*
@@ -106,16 +100,10 @@
*/
int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
{
- int err;
-
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
- EXT_CSD_BOOT_ACK(ack) |
- EXT_CSD_BOOT_PART_NUM(part_num) |
- EXT_CSD_PARTITION_ACCESS(access));
-
- if (err)
- return err;
- return 0;
+ return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
+ EXT_CSD_BOOT_ACK(ack) |
+ EXT_CSD_BOOT_PART_NUM(part_num) |
+ EXT_CSD_PARTITION_ACCESS(access));
}
/*
diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
index 25361d1..bdf9d98 100644
--- a/drivers/mmc/mmc_legacy.c
+++ b/drivers/mmc/mmc_legacy.c
@@ -13,6 +13,7 @@
static struct list_head mmc_devices;
static int cur_dev_num = -1;
+#if !CONFIG_IS_ENABLED(MMC_TINY)
struct mmc *find_mmc_device(int dev_num)
{
struct mmc *m;
@@ -62,6 +63,7 @@
mmc_start_init(m);
}
}
+#endif
void mmc_list_init(void)
{
@@ -109,6 +111,35 @@
void print_mmc_devices(char separator) { }
#endif
+#if CONFIG_IS_ENABLED(MMC_TINY)
+static struct mmc mmc_static = {
+ .dsr_imp = 0,
+ .dsr = 0xffffffff,
+ .block_dev = {
+ .if_type = IF_TYPE_MMC,
+ .removable = 1,
+ .devnum = 0,
+ .block_read = mmc_bread,
+ .block_write = mmc_bwrite,
+ .block_erase = mmc_berase,
+ .part_type = 0,
+ },
+};
+
+struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
+{
+ struct mmc *mmc = &mmc_static;
+
+ mmc->cfg = cfg;
+ mmc->priv = priv;
+
+ return mmc;
+}
+
+void mmc_destroy(struct mmc *mmc)
+{
+}
+#else
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
{
struct blk_desc *bdesc;
@@ -157,6 +188,7 @@
/* only freeing memory for now */
free(mmc);
}
+#endif
static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
{
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 49ec022..03bf24d 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -28,22 +28,21 @@
void *dst);
#endif
-#ifndef CONFIG_SPL_BUILD
-
-unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
- lbaint_t blkcnt);
+#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV))
#ifdef CONFIG_BLK
ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
const void *src);
+ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt);
#else
ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
const void *src);
+ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt);
#endif
-#else /* CONFIG_SPL_BUILD */
+#else /* CONFIG_SPL_BUILD and CONFIG_SPL_SAVEENV is not defined */
-/* SPL will never write or erase, declare dummies to reduce code size. */
+/* declare dummies to reduce code size. */
#ifdef CONFIG_BLK
static inline unsigned long mmc_berase(struct udevice *dev,
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 0f8b5c7..54acbf7 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -66,9 +66,15 @@
return err;
}
-unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
- lbaint_t blkcnt)
+#ifdef CONFIG_BLK
+ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
+#else
+ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
+#endif
{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
int dev_num = block_dev->devnum;
int err = 0;
u32 start_rem, blkcnt_rem;
@@ -100,8 +106,13 @@
& ~(mmc->erase_grp_size - 1)) - 1);
while (blk < blkcnt) {
- blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
- mmc->erase_grp_size : (blkcnt - blk);
+ if (IS_SD(mmc) && mmc->ssr.au) {
+ blk_r = ((blkcnt - blk) > mmc->ssr.au) ?
+ mmc->ssr.au : (blkcnt - blk);
+ } else {
+ blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
+ mmc->erase_grp_size : (blkcnt - blk);
+ }
err = mmc_erase_t(mmc, start + blk, blk_r);
if (err)
break;
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 8d4399e..f33714b 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -140,9 +140,6 @@
writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
}
- /* Set host controller version */
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
host->mmc = &plat->mmc;
if (ret)
@@ -190,13 +187,8 @@
static int msm_sdc_bind(struct udevice *dev)
{
struct msm_sdhc_plat *plat = dev_get_platdata(dev);
- int ret;
- ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
- if (ret)
- return ret;
-
- return 0;
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static const struct udevice_id msm_mmc_ids[] = {
diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 82c695f..e388ad1 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -71,7 +71,7 @@
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
if (!host) {
printf("sdh_host malloc fail!\n");
- return 1;
+ return -ENOMEM;
}
host->name = MVSDH_NAME;
@@ -88,9 +88,5 @@
sdhci_mvebu_mbus_config((void __iomem *)regbase);
}
- if (quirks & SDHCI_QUIRK_REG32_RW)
- host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
- else
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
return add_sdhci(host, max_clk, min_clk);
}
diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c
index 8038f90..5a385a3 100644
--- a/drivers/mmc/mxcmmc.c
+++ b/drivers/mmc/mxcmmc.c
@@ -23,7 +23,7 @@
#include <part.h>
#include <malloc.h>
#include <mmc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 40f3eaa..0896028 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -20,7 +20,7 @@
#include <common.h>
#include <malloc.h>
#include <mmc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index fceafe1..0a1ee40 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -96,44 +96,6 @@
}
#endif
-#if defined(CONFIG_OMAP44XX)
-static void omap4_vmmc_pbias_config(struct mmc *mmc)
-{
- u32 value = 0;
-
- value = readl((*ctrl)->control_pbiaslite);
- value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
- writel(value, (*ctrl)->control_pbiaslite);
- value = readl((*ctrl)->control_pbiaslite);
- value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
- writel(value, (*ctrl)->control_pbiaslite);
-}
-#endif
-
-#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
-static void omap5_pbias_config(struct mmc *mmc)
-{
- u32 value = 0;
-
- value = readl((*ctrl)->control_pbias);
- value &= ~SDCARD_PWRDNZ;
- writel(value, (*ctrl)->control_pbias);
- udelay(10); /* wait 10 us */
- value &= ~SDCARD_BIAS_PWRDNZ;
- writel(value, (*ctrl)->control_pbias);
-
- palmas_mmc1_poweron_ldo();
-
- value = readl((*ctrl)->control_pbias);
- value |= SDCARD_BIAS_PWRDNZ;
- writel(value, (*ctrl)->control_pbias);
- udelay(150); /* wait 150 us */
- value |= SDCARD_PWRDNZ;
- writel(value, (*ctrl)->control_pbias);
- udelay(150); /* wait 150 us */
-}
-#endif
-
static unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_OMAP34XX)
@@ -173,14 +135,10 @@
&prcm_base->iclken1_core);
#endif
-#if defined(CONFIG_OMAP44XX)
+#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
/* PBIAS config needed for MMC1 only */
if (mmc->block_dev.devnum == 0)
- omap4_vmmc_pbias_config(mmc);
-#endif
-#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
- if (mmc->block_dev.devnum == 0)
- omap5_pbias_config(mmc);
+ vmmc_pbias_config(LDO_VOLT_3V0);
#endif
return 0;
@@ -214,7 +172,6 @@
writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}
-
static int omap_hsmmc_init_setup(struct mmc *mmc)
{
struct hsmmc *mmc_base;
@@ -700,8 +657,7 @@
case 1:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
- defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
- defined(CONFIG_AM33XX) || \
+ defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
@@ -712,7 +668,7 @@
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
-#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
+#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 340eef6..3d587cc 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -30,7 +30,7 @@
mmc_host->name = name;
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
- mmc_host->ioaddr = (void *)iobase;
+ mmc_host->ioaddr = (void *)(ulong)iobase;
mmc_host->quirks = 0;
ret = add_sdhci(mmc_host, 0, 0);
if (ret)
diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
index abe7429..2abf943 100644
--- a/drivers/mmc/pic32_sdhci.c
+++ b/drivers/mmc/pic32_sdhci.c
@@ -10,7 +10,7 @@
#include <dm.h>
#include <common.h>
#include <sdhci.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <mach/pic32.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c
index 19ae81d..a5462e2 100644
--- a/drivers/mmc/pxa_mmc_gen.c
+++ b/drivers/mmc/pxa_mmc_gen.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/regs-mmc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <mmc.h>
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 020a59b..47db678 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -129,8 +129,7 @@
return ret;
}
#endif
- dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
- priv->minmax[1], priv->minmax[0]);
+ dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
host->mmc = &plat->mmc;
host->mmc->priv = &priv->host;
host->mmc->dev = dev;
@@ -142,13 +141,8 @@
static int rockchip_dwmmc_bind(struct udevice *dev)
{
struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
- int ret;
- ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
- if (ret)
- return ret;
-
- return 0;
+ return dwmci_bind(dev, &plat->mmc, &plat->cfg);
}
static const struct udevice_id rockchip_dwmmc_ids[] = {
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 624029b..c56e1a3 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -62,13 +62,8 @@
static int rockchip_sdhci_bind(struct udevice *dev)
{
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
- int ret;
- ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
- if (ret)
- return ret;
-
- return 0;
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static const struct udevice_id arasan_sdhci_ids[] = {
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 3bace21..ac737e0 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <malloc.h>
#include <sdhci.h>
#include <fdtdec.h>
@@ -16,6 +17,15 @@
#include <errno.h>
#include <asm/arch/pinmux.h>
+#ifdef CONFIG_DM_MMC
+struct s5p_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
static char *S5P_NAME = "SAMSUNG SDHCI";
static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
{
@@ -71,7 +81,6 @@
SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
host->set_control_reg = &s5p_sdhci_set_control_reg;
host->set_clock = set_mmc_clk;
@@ -79,7 +88,11 @@
if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
+#ifndef CONFIG_BLK
return add_sdhci(host, 52000000, 400000);
+#else
+ return 0;
+#endif
}
int s5p_sdhci_init(u32 regbase, int index, int bus_width)
@@ -87,7 +100,7 @@
struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host));
if (!host) {
printf("sdhci__host allocation fail!\n");
- return 1;
+ return -ENOMEM;
}
host->ioaddr = (void *)regbase;
host->index = index;
@@ -139,9 +152,9 @@
/* Get device id */
dev_id = pinmux_decode_periph_id(blob, node);
- if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
+ if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) {
debug("MMC: Can't get device id\n");
- return -1;
+ return -EINVAL;
}
host->index = dev_id - PERIPH_ID_SDMMC0;
@@ -149,7 +162,7 @@
bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
if (bus_width <= 0) {
debug("MMC: Can't get bus-width\n");
- return -1;
+ return -EINVAL;
}
host->bus_width = bus_width;
@@ -157,7 +170,7 @@
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
debug("MMC: Can't get base address\n");
- return -1;
+ return -EINVAL;
}
host->ioaddr = (void *)base;
@@ -215,3 +228,60 @@
return process_nodes(blob, node_list, count);
}
#endif
+
+#ifdef CONFIG_DM_MMC
+static int s5p_sdhci_probe(struct udevice *dev)
+{
+ struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ ret = sdhci_get_config(gd->fdt_blob, dev->of_offset, host);
+ if (ret)
+ return ret;
+
+ ret = do_sdhci_init(host);
+ if (ret)
+ return ret;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 52000000, 400000);
+ if (ret)
+ return ret;
+
+ host->mmc = &plat->mmc;
+ host->mmc->priv = host;
+ host->mmc->dev = dev;
+ upriv->mmc = host->mmc;
+
+ return sdhci_probe(dev);
+}
+
+static int s5p_sdhci_bind(struct udevice *dev)
+{
+ struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id s5p_sdhci_ids[] = {
+ { .compatible = "samsung,exynos4412-sdhci"},
+ { }
+};
+
+U_BOOT_DRIVER(s5p_sdhci_drv) = {
+ .name = "s5p_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = s5p_sdhci_ids,
+ .bind = s5p_sdhci_bind,
+ .ops = &sdhci_ops,
+ .probe = s5p_sdhci_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+ .platdata_auto_alloc_size = sizeof(struct s5p_sdhci_plat),
+};
+#endif /* CONFIG_DM_MMC */
diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c
index 5f1333b..fdb29a5 100644
--- a/drivers/mmc/sandbox_mmc.c
+++ b/drivers/mmc/sandbox_mmc.c
@@ -112,7 +112,6 @@
{
struct sandbox_mmc_plat *plat = dev_get_platdata(dev);
struct mmc_config *cfg = &plat->cfg;
- int ret;
cfg->name = dev->name;
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT;
@@ -121,11 +120,7 @@
cfg->f_max = 52000000;
cfg->b_max = U32_MAX;
- ret = mmc_bind(dev, &plat->mmc, cfg);
- if (ret)
- return ret;
-
- return 0;
+ return mmc_bind(dev, &plat->mmc, cfg);
}
int sandbox_mmc_unbind(struct udevice *dev)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 7ddb549..cbf5f56 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -72,7 +72,7 @@
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
-#ifdef CONFIG_MMC_SDMA
+#ifdef CONFIG_MMC_SDHCI_SDMA
unsigned char ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
@@ -87,7 +87,7 @@
if (stat & SDHCI_INT_ERROR) {
printf("%s: Error detected in status(0x%X)!\n",
__func__, stat);
- return -1;
+ return -EIO;
}
if (stat & rdy) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
@@ -98,7 +98,7 @@
if (++block >= data->blocks)
break;
}
-#ifdef CONFIG_MMC_SDMA
+#ifdef CONFIG_MMC_SDHCI_SDMA
if (stat & SDHCI_INT_DMA_END) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
@@ -110,7 +110,7 @@
udelay(10);
else {
printf("%s: Transfer data timeout\n", __func__);
- return -1;
+ return -ETIMEDOUT;
}
} while (!(stat & SDHCI_INT_DATA_END));
return 0;
@@ -121,13 +121,10 @@
* for card ready state.
* Every time when card is busy after timeout then (last) timeout value will be
* increased twice but only if it doesn't exceed global defined maximum.
- * Each function call will use last timeout value. Max timeout can be redefined
- * in board config file.
+ * Each function call will use last timeout value.
*/
-#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
-#define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
-#endif
-#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
+#define SDHCI_CMD_MAX_TIMEOUT 3200
+#define SDHCI_CMD_DEFAULT_TIMEOUT 100
#define SDHCI_READ_STATUS_TIMEOUT 1000
#ifdef CONFIG_DM_MMC_OPS
@@ -151,7 +148,7 @@
unsigned start = get_timer(0);
/* Timeout unit - ms */
- static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
+ static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
@@ -164,7 +161,7 @@
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
if (time >= cmd_timeout) {
printf("%s: MMC: %d busy ", __func__, mmc_dev);
- if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
+ if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
cmd_timeout += cmd_timeout;
printf("timeout increasing to: %u ms.\n",
cmd_timeout);
@@ -207,7 +204,7 @@
if (data->flags == MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
-#ifdef CONFIG_MMC_SDMA
+#ifdef CONFIG_MMC_SDHCI_SDMA
if (data->flags == MMC_DATA_READ)
start_addr = (unsigned long)data->dest;
else
@@ -244,7 +241,8 @@
}
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
-#ifdef CONFIG_MMC_SDMA
+#ifdef CONFIG_MMC_SDHCI_SDMA
+ trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
flush_cache(start_addr, trans_bytes);
#endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
@@ -297,7 +295,7 @@
static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
struct sdhci_host *host = mmc->priv;
- unsigned int div, clk, timeout, reg;
+ unsigned int div, clk = 0, timeout, reg;
/* Wait max 20 ms */
timeout = 200;
@@ -306,7 +304,7 @@
if (timeout == 0) {
printf("%s: Timeout to wait cmd & data inhibit\n",
__func__);
- return -1;
+ return -EBUSY;
}
timeout--;
@@ -321,14 +319,36 @@
return 0;
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
- /* Version 3.00 divisors must be a multiple of 2. */
- if (mmc->cfg->f_max <= clock)
- div = 1;
- else {
- for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
- if ((mmc->cfg->f_max / div) <= clock)
+ /*
+ * Check if the Host Controller supports Programmable Clock
+ * Mode.
+ */
+ if (host->clk_mul) {
+ for (div = 1; div <= 1024; div++) {
+ if ((mmc->cfg->f_max * host->clk_mul / div)
+ <= clock)
break;
}
+
+ /*
+ * Set Programmable Clock Mode in the Clock
+ * Control register.
+ */
+ clk = SDHCI_PROG_CLOCK_MODE;
+ div--;
+ } else {
+ /* Version 3.00 divisors must be a multiple of 2. */
+ if (mmc->cfg->f_max <= clock) {
+ div = 1;
+ } else {
+ for (div = 2;
+ div < SDHCI_MAX_DIV_SPEC_300;
+ div += 2) {
+ if ((mmc->cfg->f_max / div) <= clock)
+ break;
+ }
+ }
+ div >>= 1;
}
} else {
/* Version 2.00 divisors must be a power of 2. */
@@ -336,13 +356,13 @@
if ((mmc->cfg->f_max / div) <= clock)
break;
}
+ div >>= 1;
}
- div >>= 1;
if (host->set_clock)
host->set_clock(host->index, div);
- clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
+ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
clk |= SDHCI_CLOCK_INT_EN;
@@ -355,7 +375,7 @@
if (timeout == 0) {
printf("%s: Internal clock never stabilised.\n",
__func__);
- return -1;
+ return -EBUSY;
}
timeout--;
udelay(1000);
@@ -451,12 +471,14 @@
{
struct sdhci_host *host = mmc->priv;
+ sdhci_reset(host, SDHCI_RESET_ALL);
+
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
aligned_buffer = memalign(8, 512*1024);
if (!aligned_buffer) {
printf("%s: Aligned buffer alloc failed!!!\n",
__func__);
- return -1;
+ return -ENOMEM;
}
}
@@ -514,10 +536,22 @@
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
u32 max_clk, u32 min_clk)
{
- u32 caps;
+ u32 caps, caps_1;
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+#ifdef CONFIG_MMC_SDHCI_SDMA
+ if (!(caps & SDHCI_CAN_DO_SDMA)) {
+ printf("%s: Your controller doesn't support SDMA!!\n",
+ __func__);
+ return -EINVAL;
+ }
+#endif
+ if (host->quirks & SDHCI_QUIRK_REG32_RW)
+ host->version =
+ sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
+ else
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
cfg->name = host->name;
#ifndef CONFIG_DM_MMC_OPS
@@ -534,8 +568,11 @@
SDHCI_CLOCK_BASE_SHIFT;
cfg->f_max *= 1000000;
}
- if (cfg->f_max == 0)
+ if (cfg->f_max == 0) {
+ printf("%s: Hardware doesn't specify base clock frequency\n",
+ __func__);
return -EINVAL;
+ }
if (min_clk)
cfg->f_min = min_clk;
else {
@@ -552,6 +589,9 @@
if (caps & SDHCI_CAN_VDD_180)
cfg->voltages |= MMC_VDD_165_195;
+ if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
+ cfg->voltages |= host->voltages;
+
cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
if (caps & SDHCI_CAN_DO_8BIT)
@@ -564,6 +604,16 @@
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ /*
+ * In case of Host Controller v3.00, find out whether clock
+ * multiplier is supported.
+ */
+ if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
+ caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
+ SDHCI_CLOCK_MUL_SHIFT;
+ }
+
return 0;
}
@@ -575,32 +625,16 @@
#else
int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
{
-#ifdef CONFIG_MMC_SDMA
- unsigned int caps;
+ int ret;
- caps = sdhci_readl(host, SDHCI_CAPABILITIES);
- if (!(caps & SDHCI_CAN_DO_SDMA)) {
- printf("%s: Your controller doesn't support SDMA!!\n",
- __func__);
- return -1;
- }
-#endif
-
- if (sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk)) {
- printf("%s: Hardware doesn't specify base clock frequency\n",
- __func__);
- return -EINVAL;
- }
-
- if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
- host->cfg.voltages |= host->voltages;
-
- sdhci_reset(host, SDHCI_RESET_ALL);
+ ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
+ if (ret)
+ return ret;
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL) {
printf("%s: mmc create fail!\n", __func__);
- return -1;
+ return -ENOMEM;
}
return 0;
diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c
index bc4b344..69ded9e 100644
--- a/drivers/mmc/sh_mmcif.c
+++ b/drivers/mmc/sh_mmcif.c
@@ -12,7 +12,7 @@
#include <command.h>
#include <mmc.h>
#include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include "sh_mmcif.h"
diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c
index ea82e2b..78e2ef6 100644
--- a/drivers/mmc/sh_sdhi.c
+++ b/drivers/mmc/sh_sdhi.c
@@ -13,7 +13,7 @@
#include <common.h>
#include <malloc.h>
#include <mmc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/sh_sdhi.h>
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 8a96302..0a22e58 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -111,8 +111,7 @@
struct dwmci_host *host = &priv->host;
#ifdef CONFIG_BLK
- dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
- host->bus_hz, 400000);
+ dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
host->mmc = &plat->mmc;
#else
int ret;
@@ -152,7 +151,9 @@
.id = UCLASS_MMC,
.of_match = socfpga_dwmmc_ids,
.ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
+ .ops = &dm_dwmci_ops,
.bind = socfpga_dwmmc_bind,
.probe = socfpga_dwmmc_probe,
.priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
+ .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
};
diff --git a/drivers/mmc/spear_sdhci.c b/drivers/mmc/spear_sdhci.c
deleted file mode 100644
index 6ca96a2..0000000
--- a/drivers/mmc/spear_sdhci.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * (C) Copyright 2012
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <sdhci.h>
-
-int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
-{
- struct sdhci_host *host = NULL;
- host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
- if (!host) {
- printf("sdhci host malloc fail!\n");
- return 1;
- }
-
- host->name = "sdhci";
- host->ioaddr = (void *)regbase;
- host->quirks = quirks;
-
- if (quirks & SDHCI_QUIRK_REG32_RW)
- host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
- else
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-
- add_sdhci(host, max_clk, min_clk);
- return 0;
-}
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 6953acc..b8716c9 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -463,7 +463,7 @@
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
-#ifdef CONFIG_MACH_SUN50I
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
if (sdc_no == 2)
cfg->host_caps = MMC_MODE_8BIT;
#endif
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 3d0845e..97b1154 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -2,7 +2,7 @@
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Jaehoon Chung <jh80.chung@samsung.com>
- * Portions Copyright 2011-2015 NVIDIA Corporation
+ * Portions Copyright 2011-2016 NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -13,32 +13,26 @@
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#ifndef CONFIG_TEGRA186
-#include <asm/arch/clock.h>
-#include <asm/arch-tegra/clk_rst.h>
-#endif
-#include <asm/arch-tegra/mmc.h>
#include <asm/arch-tegra/tegra_mmc.h>
#include <mmc.h>
-/*
- * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
- * should not be present. These are needed because newer Tegra SoCs support
- * only the standard clock/reset APIs, whereas older Tegra SoCs support only
- * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
- * fixed to implement the standard APIs, and all drivers converted to solely
- * use the new standard APIs, with no ifdefs.
- */
-
DECLARE_GLOBAL_DATA_PTR;
-struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];
+struct tegra_mmc_priv {
+ struct tegra_mmc *reg;
+ struct reset_ctl reset_ctl;
+ struct clk clk;
+ struct gpio_desc cd_gpio; /* Change Detect GPIO */
+ struct gpio_desc pwr_gpio; /* Power GPIO */
+ struct gpio_desc wp_gpio; /* Write Protect GPIO */
+ unsigned int version; /* SDHCI spec. version */
+ unsigned int clock; /* Current clock (MHz) */
+ struct mmc_config cfg; /* mmc configuration */
+ struct mmc *mmc;
+};
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
-#error "Please enable device tree support to use this driver"
-#endif
-
-static void mmc_set_power(struct mmc_host *host, unsigned short power)
+static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
+ unsigned short power)
{
u8 pwr = 0;
debug("%s: power = %x\n", __func__, power);
@@ -61,17 +55,18 @@
debug("%s: pwr = %X\n", __func__, pwr);
/* Set the bus voltage first (if any) */
- writeb(pwr, &host->reg->pwrcon);
+ writeb(pwr, &priv->reg->pwrcon);
if (pwr == 0)
return;
/* Now enable bus power */
pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
- writeb(pwr, &host->reg->pwrcon);
+ writeb(pwr, &priv->reg->pwrcon);
}
-static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
- struct bounce_buffer *bbstate)
+static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
+ struct mmc_data *data,
+ struct bounce_buffer *bbstate)
{
unsigned char ctrl;
@@ -80,7 +75,7 @@
bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
data->blocksize);
- writel((u32)(unsigned long)bbstate->bounce_buffer, &host->reg->sysad);
+ writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
/*
* DMASEL[4:3]
* 00 = Selects SDMA
@@ -88,17 +83,18 @@
* 10 = Selects 32-bit Address ADMA2
* 11 = Selects 64-bit Address ADMA2
*/
- ctrl = readb(&host->reg->hostctl);
+ ctrl = readb(&priv->reg->hostctl);
ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
- writeb(ctrl, &host->reg->hostctl);
+ writeb(ctrl, &priv->reg->hostctl);
/* We do not handle DMA boundaries, so set it to max (512 KiB) */
- writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
- writew(data->blocks, &host->reg->blkcnt);
+ writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
+ writew(data->blocks, &priv->reg->blkcnt);
}
-static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
+static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
+ struct mmc_data *data)
{
unsigned short mode;
debug(" mmc_set_transfer_mode called\n");
@@ -121,13 +117,13 @@
if (data->flags & MMC_DATA_READ)
mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
- writew(mode, &host->reg->trnmod);
+ writew(mode, &priv->reg->trnmod);
}
-static int mmc_wait_inhibit(struct mmc_host *host,
- struct mmc_cmd *cmd,
- struct mmc_data *data,
- unsigned int timeout)
+static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
+ struct mmc_cmd *cmd,
+ struct mmc_data *data,
+ unsigned int timeout)
{
/*
* PRNSTS
@@ -143,7 +139,7 @@
if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
- while (readl(&host->reg->prnsts) & mask) {
+ while (readl(&priv->reg->prnsts) & mask) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return -1;
@@ -155,29 +151,30 @@
return 0;
}
-static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data, struct bounce_buffer *bbstate)
+static int tegra_mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data,
+ struct bounce_buffer *bbstate)
{
- struct mmc_host *host = mmc->priv;
+ struct tegra_mmc_priv *priv = mmc->priv;
int flags, i;
int result;
unsigned int mask = 0;
unsigned int retry = 0x100000;
debug(" mmc_send_cmd called\n");
- result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
+ result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
if (result < 0)
return result;
if (data)
- mmc_prepare_data(host, data, bbstate);
+ tegra_mmc_prepare_data(priv, data, bbstate);
debug("cmd->arg: %08x\n", cmd->cmdarg);
- writel(cmd->cmdarg, &host->reg->argument);
+ writel(cmd->cmdarg, &priv->reg->argument);
if (data)
- mmc_set_transfer_mode(host, data);
+ tegra_mmc_set_transfer_mode(priv, data);
if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
return -1;
@@ -212,33 +209,33 @@
debug("cmd: %d\n", cmd->cmdidx);
- writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
+ writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
for (i = 0; i < retry; i++) {
- mask = readl(&host->reg->norintsts);
+ mask = readl(&priv->reg->norintsts);
/* Command Complete */
if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
if (!data)
- writel(mask, &host->reg->norintsts);
+ writel(mask, &priv->reg->norintsts);
break;
}
}
if (i == retry) {
printf("%s: waiting for status update\n", __func__);
- writel(mask, &host->reg->norintsts);
+ writel(mask, &priv->reg->norintsts);
return -ETIMEDOUT;
}
if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
/* Timeout Error */
debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
- writel(mask, &host->reg->norintsts);
+ writel(mask, &priv->reg->norintsts);
return -ETIMEDOUT;
} else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
/* Error Interrupt */
debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
- writel(mask, &host->reg->norintsts);
+ writel(mask, &priv->reg->norintsts);
return -1;
}
@@ -246,8 +243,8 @@
if (cmd->resp_type & MMC_RSP_136) {
/* CRC is stripped so we need to do some shifting. */
for (i = 0; i < 4; i++) {
- unsigned long offset =
- (unsigned long)(&host->reg->rspreg3 - i);
+ unsigned long offset = (unsigned long)
+ (&priv->reg->rspreg3 - i);
cmd->response[i] = readl(offset) << 8;
if (i != 3) {
@@ -260,21 +257,21 @@
} else if (cmd->resp_type & MMC_RSP_BUSY) {
for (i = 0; i < retry; i++) {
/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
- if (readl(&host->reg->prnsts)
+ if (readl(&priv->reg->prnsts)
& (1 << 20)) /* DAT[0] */
break;
}
if (i == retry) {
printf("%s: card is still busy\n", __func__);
- writel(mask, &host->reg->norintsts);
+ writel(mask, &priv->reg->norintsts);
return -ETIMEDOUT;
}
- cmd->response[0] = readl(&host->reg->rspreg0);
+ cmd->response[0] = readl(&priv->reg->rspreg0);
debug("cmd->resp[0]: %08x\n", cmd->response[0]);
} else {
- cmd->response[0] = readl(&host->reg->rspreg0);
+ cmd->response[0] = readl(&priv->reg->rspreg0);
debug("cmd->resp[0]: %08x\n", cmd->response[0]);
}
}
@@ -283,11 +280,11 @@
unsigned long start = get_timer(0);
while (1) {
- mask = readl(&host->reg->norintsts);
+ mask = readl(&priv->reg->norintsts);
if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
/* Error Interrupt */
- writel(mask, &host->reg->norintsts);
+ writel(mask, &priv->reg->norintsts);
printf("%s: error during transfer: 0x%08x\n",
__func__, mask);
return -1;
@@ -296,31 +293,31 @@
* DMA Interrupt, restart the transfer where
* it was interrupted.
*/
- unsigned int address = readl(&host->reg->sysad);
+ unsigned int address = readl(&priv->reg->sysad);
debug("DMA end\n");
writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
- &host->reg->norintsts);
- writel(address, &host->reg->sysad);
+ &priv->reg->norintsts);
+ writel(address, &priv->reg->sysad);
} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
/* Transfer Complete */
debug("r/w is done\n");
break;
} else if (get_timer(start) > 8000UL) {
- writel(mask, &host->reg->norintsts);
+ writel(mask, &priv->reg->norintsts);
printf("%s: MMC Timeout\n"
" Interrupt status 0x%08x\n"
" Interrupt status enable 0x%08x\n"
" Interrupt signal enable 0x%08x\n"
" Present status 0x%08x\n",
__func__, mask,
- readl(&host->reg->norintstsen),
- readl(&host->reg->norintsigen),
- readl(&host->reg->prnsts));
+ readl(&priv->reg->norintstsen),
+ readl(&priv->reg->norintsigen),
+ readl(&priv->reg->prnsts));
return -1;
}
}
- writel(mask, &host->reg->norintsts);
+ writel(mask, &priv->reg->norintsts);
}
udelay(1000);
@@ -328,7 +325,7 @@
}
static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+ struct mmc_data *data)
{
void *buf;
unsigned int bbflags;
@@ -349,7 +346,7 @@
bounce_buffer_start(&bbstate, buf, len, bbflags);
}
- ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
+ ret = tegra_mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
if (data)
bounce_buffer_stop(&bbstate);
@@ -357,8 +354,9 @@
return ret;
}
-static void mmc_change_clock(struct mmc_host *host, uint clock)
+static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
{
+ ulong rate;
int div;
unsigned short clk;
unsigned long timeout;
@@ -370,18 +368,12 @@
*/
if (clock == 0)
goto out;
-#ifdef CONFIG_TEGRA186
- {
- ulong rate = clk_set_rate(&host->clk, clock);
- div = (rate + clock - 1) / clock;
- }
-#else
- clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
- &div);
-#endif
+
+ rate = clk_set_rate(&priv->clk, clock);
+ div = (rate + clock - 1) / clock;
debug("div = %d\n", div);
- writew(0, &host->reg->clkcon);
+ writew(0, &priv->reg->clkcon);
/*
* CLKCON
@@ -393,11 +385,11 @@
div >>= 1;
clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
- writew(clk, &host->reg->clkcon);
+ writew(clk, &priv->reg->clkcon);
/* Wait max 10 ms */
timeout = 10;
- while (!(readw(&host->reg->clkcon) &
+ while (!(readw(&priv->reg->clkcon) &
TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
@@ -408,26 +400,26 @@
}
clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
- writew(clk, &host->reg->clkcon);
+ writew(clk, &priv->reg->clkcon);
debug("mmc_change_clock: clkcon = %08X\n", clk);
out:
- host->clock = clock;
+ priv->clock = clock;
}
static void tegra_mmc_set_ios(struct mmc *mmc)
{
- struct mmc_host *host = mmc->priv;
+ struct tegra_mmc_priv *priv = mmc->priv;
unsigned char ctrl;
debug(" mmc_set_ios called\n");
debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
/* Change clock first */
- mmc_change_clock(host, mmc->clock);
+ tegra_mmc_change_clock(priv, mmc->clock);
- ctrl = readb(&host->reg->hostctl);
+ ctrl = readb(&priv->reg->hostctl);
/*
* WIDE8[5]
@@ -444,11 +436,38 @@
else
ctrl &= ~(1 << 1);
- writeb(ctrl, &host->reg->hostctl);
+ writeb(ctrl, &priv->reg->hostctl);
debug("mmc_set_ios: hostctl = %08X\n", ctrl);
}
-static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
+static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
+{
+#if defined(CONFIG_TEGRA30)
+ u32 val;
+
+ debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
+
+ /* Set the pad drive strength for SDMMC1 or 3 only */
+ if (priv->reg != (void *)0x78000000 &&
+ priv->reg != (void *)0x78000400) {
+ debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
+ __func__);
+ return;
+ }
+
+ val = readl(&priv->reg->sdmemcmppadctl);
+ val &= 0xFFFFFFF0;
+ val |= MEMCOMP_PADCTRL_VREF;
+ writel(val, &priv->reg->sdmemcmppadctl);
+
+ val = readl(&priv->reg->autocalcfg);
+ val &= 0xFFFF0000;
+ val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+ writel(val, &priv->reg->autocalcfg);
+#endif
+}
+
+static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
{
unsigned int timeout;
debug(" mmc_reset called\n");
@@ -458,15 +477,15 @@
* 1 = reset
* 0 = work
*/
- writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
+ writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
- host->clock = 0;
+ priv->clock = 0;
/* Wait max 100 ms */
timeout = 100;
/* hw clears the bit when it's done */
- while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
+ while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return;
@@ -476,30 +495,30 @@
}
/* Set SD bus voltage & enable bus power */
- mmc_set_power(host, fls(mmc->cfg->voltages) - 1);
+ tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
debug("%s: power control = %02X, host control = %02X\n", __func__,
- readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
+ readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
/* Make sure SDIO pads are set up */
- pad_init_mmc(host);
+ tegra_mmc_pad_init(priv);
}
-static int tegra_mmc_core_init(struct mmc *mmc)
+static int tegra_mmc_init(struct mmc *mmc)
{
- struct mmc_host *host = mmc->priv;
+ struct tegra_mmc_priv *priv = mmc->priv;
unsigned int mask;
- debug(" mmc_core_init called\n");
+ debug(" tegra_mmc_init called\n");
- mmc_reset(host, mmc);
+ tegra_mmc_reset(priv, mmc);
- host->version = readw(&host->reg->hcver);
- debug("host version = %x\n", host->version);
+ priv->version = readw(&priv->reg->hcver);
+ debug("host version = %x\n", priv->version);
/* mask all */
- writel(0xffffffff, &host->reg->norintstsen);
- writel(0xffffffff, &host->reg->norintsigen);
+ writel(0xffffffff, &priv->reg->norintstsen);
+ writel(0xffffffff, &priv->reg->norintsigen);
- writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
+ writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
/*
* NORMAL Interrupt Status Enable Register init
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
@@ -508,35 +527,35 @@
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
* [0] ENSTACMDCMPLT : Command Complete Status Enable
*/
- mask = readl(&host->reg->norintstsen);
+ mask = readl(&priv->reg->norintstsen);
mask &= ~(0xffff);
mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
- writel(mask, &host->reg->norintstsen);
+ writel(mask, &priv->reg->norintstsen);
/*
* NORMAL Interrupt Signal Enable Register init
* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
*/
- mask = readl(&host->reg->norintsigen);
+ mask = readl(&priv->reg->norintsigen);
mask &= ~(0xffff);
mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
- writel(mask, &host->reg->norintsigen);
+ writel(mask, &priv->reg->norintsigen);
return 0;
}
static int tegra_mmc_getcd(struct mmc *mmc)
{
- struct mmc_host *host = mmc->priv;
+ struct tegra_mmc_priv *priv = mmc->priv;
debug("tegra_mmc_getcd called\n");
- if (dm_gpio_is_valid(&host->cd_gpio))
- return dm_gpio_get_value(&host->cd_gpio);
+ if (dm_gpio_is_valid(&priv->cd_gpio))
+ return dm_gpio_get_value(&priv->cd_gpio);
return 1;
}
@@ -544,61 +563,29 @@
static const struct mmc_ops tegra_mmc_ops = {
.send_cmd = tegra_mmc_send_cmd,
.set_ios = tegra_mmc_set_ios,
- .init = tegra_mmc_core_init,
+ .init = tegra_mmc_init,
.getcd = tegra_mmc_getcd,
};
-static int do_mmc_init(int dev_index, bool removable)
+static int tegra_mmc_probe(struct udevice *dev)
{
- struct mmc_host *host;
- struct mmc *mmc;
-#ifdef CONFIG_TEGRA186
- int ret;
-#endif
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct tegra_mmc_priv *priv = dev_get_priv(dev);
+ int bus_width, ret;
- /* DT should have been read & host config filled in */
- host = &mmc_host[dev_index];
- if (!host->enabled)
- return -1;
+ priv->cfg.name = "Tegra SD/MMC";
+ priv->cfg.ops = &tegra_mmc_ops;
- debug(" do_mmc_init: index %d, bus width %d pwr_gpio %d cd_gpio %d\n",
- dev_index, host->width, gpio_get_number(&host->pwr_gpio),
- gpio_get_number(&host->cd_gpio));
+ bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width",
+ 1);
- host->clock = 0;
-
-#ifdef CONFIG_TEGRA186
- ret = reset_assert(&host->reset_ctl);
- if (ret)
- return ret;
- ret = clk_enable(&host->clk);
- if (ret)
- return ret;
- ret = clk_set_rate(&host->clk, 20000000);
- if (IS_ERR_VALUE(ret))
- return ret;
- ret = reset_deassert(&host->reset_ctl);
- if (ret)
- return ret;
-#else
- clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
-#endif
-
- if (dm_gpio_is_valid(&host->pwr_gpio))
- dm_gpio_set_value(&host->pwr_gpio, 1);
-
- memset(&host->cfg, 0, sizeof(host->cfg));
-
- host->cfg.name = "Tegra SD/MMC";
- host->cfg.ops = &tegra_mmc_ops;
-
- host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- host->cfg.host_caps = 0;
- if (host->width == 8)
- host->cfg.host_caps |= MMC_MODE_8BIT;
- if (host->width >= 4)
- host->cfg.host_caps |= MMC_MODE_4BIT;
- host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ priv->cfg.host_caps = 0;
+ if (bus_width == 8)
+ priv->cfg.host_caps |= MMC_MODE_8BIT;
+ if (bus_width >= 4)
+ priv->cfg.host_caps |= MMC_MODE_4BIT;
+ priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* min freq is for card identification, and is the highest
@@ -606,182 +593,71 @@
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
*/
- host->cfg.f_min = 375000;
- host->cfg.f_max = 48000000;
+ priv->cfg.f_min = 375000;
+ priv->cfg.f_max = 48000000;
- host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- mmc = mmc_create(&host->cfg, host);
- mmc->block_dev.removable = removable;
- if (mmc == NULL)
- return -1;
+ priv->reg = (void *)dev_get_addr(dev);
- return 0;
-}
-
-/**
- * Get the host address and peripheral ID for a node.
- *
- * @param blob fdt blob
- * @param node Device index (0-3)
- * @param host Structure to fill in (reg, width, mmc_id)
- */
-static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
- bool *removablep)
-{
- debug("%s: node = %d\n", __func__, node);
-
- host->enabled = fdtdec_get_is_enabled(blob, node);
-
- host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
- if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
- debug("%s: no sdmmc base reg info found\n", __func__);
- return -FDT_ERR_NOTFOUND;
+ ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
+ if (ret) {
+ debug("reset_get_by_name() failed: %d\n", ret);
+ return ret;
+ }
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret) {
+ debug("clk_get_by_index() failed: %d\n", ret);
+ return ret;
}
-#ifdef CONFIG_TEGRA186
- {
- /*
- * FIXME: This variable should go away when the MMC device
- * actually is a udevice.
- */
- struct udevice dev;
- int ret;
- dev.of_offset = node;
- ret = reset_get_by_name(&dev, "sdhci", &host->reset_ctl);
- if (ret) {
- debug("reset_get_by_name() failed: %d\n", ret);
- return ret;
- }
- ret = clk_get_by_index(&dev, 0, &host->clk);
- if (ret) {
- debug("clk_get_by_index() failed: %d\n", ret);
- return ret;
- }
- }
-#else
- host->mmc_id = clock_decode_periph_id(blob, node);
- if (host->mmc_id == PERIPH_ID_NONE) {
- debug("%s: could not decode periph id\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
-#endif
-
- /*
- * NOTE: mmc->bus_width is determined by mmc.c dynamically.
- * TBD: Override it with this value?
- */
- host->width = fdtdec_get_int(blob, node, "bus-width", 0);
- if (!host->width)
- debug("%s: no sdmmc width found\n", __func__);
+ ret = reset_assert(&priv->reset_ctl);
+ if (ret)
+ return ret;
+ ret = clk_enable(&priv->clk);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(&priv->clk, 20000000);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ ret = reset_deassert(&priv->reset_ctl);
+ if (ret)
+ return ret;
/* These GPIOs are optional */
- gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio,
- GPIOD_IS_IN);
- gpio_request_by_name_nodev(blob, node, "wp-gpios", 0, &host->wp_gpio,
- GPIOD_IS_IN);
- gpio_request_by_name_nodev(blob, node, "power-gpios", 0,
- &host->pwr_gpio, GPIOD_IS_OUT);
- *removablep = !fdtdec_get_bool(blob, node, "non-removable");
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+ GPIOD_IS_IN);
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
+ GPIOD_IS_IN);
+ gpio_request_by_name(dev, "power-gpios", 0,
+ &priv->pwr_gpio, GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&priv->pwr_gpio))
+ dm_gpio_set_value(&priv->pwr_gpio, 1);
- debug("%s: found controller at %p, width = %d, periph_id = %d\n",
- __func__, host->reg, host->width,
-#ifndef CONFIG_TEGRA186
- host->mmc_id
-#else
- -1
-#endif
- );
+ priv->mmc = mmc_create(&priv->cfg, priv);
+ if (priv->mmc == NULL)
+ return -1;
+
+ priv->mmc->dev = dev;
+ upriv->mmc = priv->mmc;
+
return 0;
}
-/*
- * Process a list of nodes, adding them to our list of SDMMC ports.
- *
- * @param blob fdt blob
- * @param node_list list of nodes to process (any <=0 are ignored)
- * @param count number of nodes to process
- * @return 0 if ok, -1 on error
- */
-static int process_nodes(const void *blob, int node_list[], int count)
-{
- struct mmc_host *host;
- bool removable;
- int i, node;
+static const struct udevice_id tegra_mmc_ids[] = {
+ { .compatible = "nvidia,tegra20-sdhci" },
+ { .compatible = "nvidia,tegra30-sdhci" },
+ { .compatible = "nvidia,tegra114-sdhci" },
+ { .compatible = "nvidia,tegra124-sdhci" },
+ { .compatible = "nvidia,tegra210-sdhci" },
+ { .compatible = "nvidia,tegra186-sdhci" },
+ { }
+};
- debug("%s: count = %d\n", __func__, count);
-
- /* build mmc_host[] for each controller */
- for (i = 0; i < count; i++) {
- node = node_list[i];
- if (node <= 0)
- continue;
-
- host = &mmc_host[i];
- host->id = i;
-
- if (mmc_get_config(blob, node, host, &removable)) {
- printf("%s: failed to decode dev %d\n", __func__, i);
- return -1;
- }
- do_mmc_init(i, removable);
- }
- return 0;
-}
-
-void tegra_mmc_init(void)
-{
- int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count;
- const void *blob = gd->fdt_blob;
- debug("%s entry\n", __func__);
-
- /* See if any Tegra186 MMC controllers are present */
- count = fdtdec_find_aliases_for_id(blob, "sdhci",
- COMPAT_NVIDIA_TEGRA186_SDMMC, node_list,
- CONFIG_SYS_MMC_MAX_DEVICE);
- debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count);
- if (process_nodes(blob, node_list, count)) {
- printf("%s: Error processing T186 mmc node(s)!\n", __func__);
- return;
- }
-
- /* See if any Tegra210 MMC controllers are present */
- count = fdtdec_find_aliases_for_id(blob, "sdhci",
- COMPAT_NVIDIA_TEGRA210_SDMMC, node_list,
- CONFIG_SYS_MMC_MAX_DEVICE);
- debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__, count);
- if (process_nodes(blob, node_list, count)) {
- printf("%s: Error processing T210 mmc node(s)!\n", __func__);
- return;
- }
-
- /* See if any Tegra124 MMC controllers are present */
- count = fdtdec_find_aliases_for_id(blob, "sdhci",
- COMPAT_NVIDIA_TEGRA124_SDMMC, node_list,
- CONFIG_SYS_MMC_MAX_DEVICE);
- debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
- if (process_nodes(blob, node_list, count)) {
- printf("%s: Error processing T124 mmc node(s)!\n", __func__);
- return;
- }
-
- /* See if any Tegra30 MMC controllers are present */
- count = fdtdec_find_aliases_for_id(blob, "sdhci",
- COMPAT_NVIDIA_TEGRA30_SDMMC, node_list,
- CONFIG_SYS_MMC_MAX_DEVICE);
- debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
- if (process_nodes(blob, node_list, count)) {
- printf("%s: Error processing T30 mmc node(s)!\n", __func__);
- return;
- }
-
- /* Now look for any Tegra20 MMC controllers */
- count = fdtdec_find_aliases_for_id(blob, "sdhci",
- COMPAT_NVIDIA_TEGRA20_SDMMC, node_list,
- CONFIG_SYS_MMC_MAX_DEVICE);
- debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
- if (process_nodes(blob, node_list, count)) {
- printf("%s: Error processing T20 mmc node(s)!\n", __func__);
- return;
- }
-}
+U_BOOT_DRIVER(tegra_mmc_drv) = {
+ .name = "tegra_mmc",
+ .id = UCLASS_MMC,
+ .of_match = tegra_mmc_ids,
+ .probe = tegra_mmc_probe,
+ .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
+};
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 701b26f..4af7fdb 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -119,9 +119,12 @@
/* alignment required by the DMA engine of this controller */
#define UNIPHIER_SD_DMA_MINALIGN 0x10
-struct uniphier_sd_priv {
+struct uniphier_sd_plat {
struct mmc_config cfg;
- struct mmc *mmc;
+ struct mmc mmc;
+};
+
+struct uniphier_sd_priv {
void __iomem *regbase;
unsigned long mclk;
unsigned int version;
@@ -654,8 +657,16 @@
}
}
+static int uniphier_sd_bind(struct udevice *dev)
+{
+ struct uniphier_sd_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
static int uniphier_sd_probe(struct udevice *dev)
{
+ struct uniphier_sd_plat *plat = dev_get_platdata(dev);
struct uniphier_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
fdt_addr_t base;
@@ -691,15 +702,15 @@
return ret;
}
- priv->cfg.name = dev->name;
- priv->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ plat->cfg.name = dev->name;
+ plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
case 8:
- priv->cfg.host_caps |= MMC_MODE_8BIT;
+ plat->cfg.host_caps |= MMC_MODE_8BIT;
break;
case 4:
- priv->cfg.host_caps |= MMC_MODE_4BIT;
+ plat->cfg.host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
@@ -722,27 +733,13 @@
uniphier_sd_host_init(priv);
- priv->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
- priv->cfg.f_min = priv->mclk /
+ plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+ plat->cfg.f_min = priv->mclk /
(priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
- priv->cfg.f_max = priv->mclk;
- priv->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
+ plat->cfg.f_max = priv->mclk;
+ plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
- priv->mmc = mmc_create(&priv->cfg, priv);
- if (!priv->mmc)
- return -EIO;
-
- upriv->mmc = priv->mmc;
- priv->mmc->dev = dev;
-
- return 0;
-}
-
-static int uniphier_sd_remove(struct udevice *dev)
-{
- struct uniphier_sd_priv *priv = dev_get_priv(dev);
-
- mmc_destroy(priv->mmc);
+ upriv->mmc = &plat->mmc;
return 0;
}
@@ -756,8 +753,9 @@
.name = "uniphier-mmc",
.id = UCLASS_MMC,
.of_match = uniphier_sd_match,
+ .bind = uniphier_sd_bind,
.probe = uniphier_sd_probe,
- .remove = uniphier_sd_remove,
.priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
+ .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat),
.ops = &uniphier_sd_ops,
};
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 3815b94..3da1385 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -36,8 +36,6 @@
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
#endif
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-
ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
host->mmc = &plat->mmc;
@@ -63,13 +61,8 @@
static int arasan_sdhci_bind(struct udevice *dev)
{
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
- int ret;
- ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
- if (ret)
- return ret;
-
- return 0;
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
static const struct udevice_id arasan_sdhci_ids[] = {
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 390e9e4..3a9705c 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -40,3 +40,5 @@
source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/spi/Kconfig"
+
+source "drivers/mtd/ubi/Kconfig"
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 33c4a93..e036b88 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -1456,8 +1456,8 @@
cmd = FLASH_CMD_PROTECT_SET;
else
cmd = FLASH_CMD_PROTECT_CLEAR;
- flash_write_cmd(info, sector, 0,
- FLASH_CMD_PROTECT);
+
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
flash_write_cmd(info, sector, 0, cmd);
/* re-enable interrupts if necessary */
if (flag)
diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c
index 709a486..3c06173 100644
--- a/drivers/mtd/cfi_mtd.c
+++ b/drivers/mtd/cfi_mtd.c
@@ -10,7 +10,7 @@
#include <flash.h>
#include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/concat.h>
#include <mtd/cfi_flash.h>
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index cddfb16..5e42c4b 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -20,7 +20,7 @@
#include <common.h>
#include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/compat.h>
#include <ubi_uboot.h>
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5ce7d6d..65bb040 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -80,6 +80,20 @@
controller. This uses the hardware ECC for read and
write operations.
+config NAND_MXS
+ bool "MXS NAND support"
+ depends on MX6
+ help
+ This enables NAND driver for the NAND flash controller on the
+ MXS processors.
+
+config NAND_ZYNQ
+ bool "Support for Zynq Nand controller"
+ select SYS_NAND_SELF_INIT
+ help
+ This enables Nand driver support for Nand flash controller
+ found on Zynq SoC.
+
comment "Generic NAND options"
# Enhance depends when converting drivers to Kconfig which use this config
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1df9273..fd4bb66 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -67,6 +67,7 @@
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_PLAT) += nand_plat.o
obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
+obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
else # minimal SPL drivers
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 320cbaa..a8f795d 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
@@ -853,6 +853,8 @@
reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
}
+ reg_val &= ~ARASAN_NAND_CMD_ECC_ON_MASK;
+
reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
addr_cycles = arasan_nand_get_addrcycle(mtd);
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 48a8ca7..0624644 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -799,6 +799,9 @@
#ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
nand->options |= NAND_NO_SUBPAGE_WRITE;
#endif
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ nand->options |= NAND_BUSWIDTH_16;
+#endif
#ifdef CONFIG_SYS_NAND_HW_ECC
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = 512;
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 601e744..18280b0 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <malloc.h>
#include <nand.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include "denali.h"
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index f621f14..b3c23b0 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -17,7 +17,7 @@
#include <linux/mtd/nand_ecc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#ifdef VERBOSE_DEBUG
#define DEBUG_ELBC
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 7001cbd..bc6bdc9 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -16,7 +16,7 @@
#include <linux/mtd/nand_ecc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <fsl_ifc.h>
#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index d2b3881..4a45b87 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -10,7 +10,7 @@
#include <config.h>
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/fsl_upm.h>
#include <nand.h>
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c
index a793115..3af7e6d 100644
--- a/drivers/mtd/nand/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -22,7 +22,7 @@
#include <common.h>
#include <nand.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/clk.h>
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c
index daa1e7a..f7e27b3 100644
--- a/drivers/mtd/nand/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -15,7 +15,7 @@
#include <common.h>
#include <nand.h>
#include <linux/mtd/nand_ecc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/config.h>
#include <asm/arch/clk.h>
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 8a8775c..7faabdd 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -19,7 +19,7 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/compat.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <nand.h>
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 4bf564e..9200544 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -18,7 +18,7 @@
#include <linux/mtd/nand.h>
#include <linux/types.h>
#include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index ff28df4..b6c9208 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -153,7 +153,7 @@
nand_chip.numchips = 1;
/* identify flash device */
- puts("NAND : ");
+ puts(": ");
if (mxs_flash_ident(mtd)) {
printf("Failed to identify\n");
return -1;
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d1287bc..d9e5fc9 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -44,7 +44,7 @@
#include <linux/mtd/partitions.h>
#endif
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
/* Define default oob placement schemes for large and small page devices */
static struct nand_ecclayout nand_oob_8 = {
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 083e0e9..8b548b2 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -25,7 +25,7 @@
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand_ecc.h>
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index ce0a14e..d36f900 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -46,6 +46,9 @@
{"TC58NVG2S0F 4G 3.3V 8-bit",
{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
+ {"TC58NVG2S0H 4G 3.3V 8-bit",
+ { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00} },
+ SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
{"TC58NVG3S0F 8G 3.3V 8-bit",
{ .id = {0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08} },
SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index e8bcc34..9c8a373 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -26,7 +26,7 @@
#include <memalign.h>
#include <div64.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/mtd/mtd.h>
#include <nand.h>
#include <jffs2/jffs2.h>
diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c
index d963e6c..9ef1b21 100644
--- a/drivers/mtd/nand/omap_elm.c
+++ b/drivers/mtd/nand/omap_elm.c
@@ -15,7 +15,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/mtd/omap_elm.h>
#include <asm/arch/hardware.h>
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index af618fc..d1e1bdd 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/mem.h>
#include <linux/mtd/omap_gpmc.h>
#include <linux/mtd/nand_ecc.h>
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index b1d58e0..dfe8966 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <malloc.h>
#include <nand.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <linux/mtd/mtd.h>
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index 38bd7a5..5c9b485 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -14,7 +14,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch-tegra/clk_rst.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <fdtdec.h>
#include <bouncebuf.h>
diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c
new file mode 100644
index 0000000..cb3340d
--- /dev/null
+++ b/drivers/mtd/nand/zynq_nand.c
@@ -0,0 +1,1186 @@
+/*
+ * (C) Copyright 2016 Xilinx, Inc.
+ *
+ * Xilinx Zynq NAND Flash Controller Driver
+ * This driver is based on plat_nand.c and mxc_nand.c drivers
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand_ecc.h>
+#include <asm/arch/hardware.h>
+
+/* The NAND flash driver defines */
+#define ZYNQ_NAND_CMD_PHASE 1
+#define ZYNQ_NAND_DATA_PHASE 2
+#define ZYNQ_NAND_ECC_SIZE 512
+#define ZYNQ_NAND_SET_OPMODE_8BIT (0 << 0)
+#define ZYNQ_NAND_SET_OPMODE_16BIT (1 << 0)
+#define ZYNQ_NAND_ECC_STATUS (1 << 6)
+#define ZYNQ_MEMC_CLRCR_INT_CLR1 (1 << 4)
+#define ZYNQ_MEMC_SR_RAW_INT_ST1 (1 << 6)
+#define ZYNQ_MEMC_SR_INT_ST1 (1 << 4)
+#define ZYNQ_MEMC_NAND_ECC_MODE_MASK 0xC
+
+/* Flash memory controller operating parameters */
+#define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \
+ (0x1 << 4) | /* Clear interrupt */ \
+ (0x1 << 6)) /* Disable ECC interrupt */
+
+/* Assuming 50MHz clock (20ns cycle time) and 3V operation */
+#define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
+ (0x2 << 17) | /* t_ar from nand_cycles */ \
+ (0x1 << 14) | /* t_clr from nand_cycles */ \
+ (0x3 << 11) | /* t_wp from nand_cycles */ \
+ (0x2 << 8) | /* t_rea from nand_cycles */ \
+ (0x5 << 4) | /* t_wc from nand_cycles */ \
+ (0x5 << 0)) /* t_rc from nand_cycles */
+
+
+#define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
+ (0x2 << 21)) /* UpdateRegs operation */
+
+#define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
+ (0x1 << 4) | /* ECC read at end of page */ \
+ (0x0 << 5)) /* No Jumping */
+
+#define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
+ (0x00 << 8) | /* Read command */ \
+ (0x30 << 16) | /* Read End command */ \
+ (0x1 << 24)) /* Read End command calid */
+
+#define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
+ (0x05 << 8) | /* Read col change cmd */ \
+ (0xE0 << 16) | /* Read col change end cmd */ \
+ (0x1 << 24)) /* Read col change
+ end cmd valid */
+/* AXI Address definitions */
+#define START_CMD_SHIFT 3
+#define END_CMD_SHIFT 11
+#define END_CMD_VALID_SHIFT 20
+#define ADDR_CYCLES_SHIFT 21
+#define CLEAR_CS_SHIFT 21
+#define ECC_LAST_SHIFT 10
+#define COMMAND_PHASE (0 << 19)
+#define DATA_PHASE (1 << 19)
+#define ONDIE_ECC_FEATURE_ADDR 0x90
+#define ONDIE_ECC_FEATURE_ENABLE 0x08
+
+#define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */
+#define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */
+
+/* ECC block registers bit position and bit mask */
+#define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
+#define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
+
+
+/* SMC register set */
+struct zynq_nand_smc_regs {
+ u32 csr; /* 0x00 */
+ u32 reserved0[2];
+ u32 cfr; /* 0x0C */
+ u32 dcr; /* 0x10 */
+ u32 scr; /* 0x14 */
+ u32 sor; /* 0x18 */
+ u32 reserved1[249];
+ u32 esr; /* 0x400 */
+ u32 emcr; /* 0x404 */
+ u32 emcmd1r; /* 0x408 */
+ u32 emcmd2r; /* 0x40C */
+ u32 reserved2[2];
+ u32 eval0r; /* 0x418 */
+};
+#define zynq_nand_smc_base ((struct zynq_nand_smc_regs __iomem *)\
+ ZYNQ_SMC_BASEADDR)
+
+/*
+ * struct zynq_nand_info - Defines the NAND flash driver instance
+ * @parts: Pointer to the mtd_partition structure
+ * @nand_base: Virtual address of the NAND flash device
+ * @end_cmd_pending: End command is pending
+ * @end_cmd: End command
+ */
+struct zynq_nand_info {
+ void __iomem *nand_base;
+ u8 end_cmd_pending;
+ u8 end_cmd;
+};
+
+/*
+ * struct zynq_nand_command_format - Defines NAND flash command format
+ * @start_cmd: First cycle command (Start command)
+ * @end_cmd: Second cycle command (Last command)
+ * @addr_cycles: Number of address cycles required to send the address
+ * @end_cmd_valid: The second cycle command is valid for cmd or data phase
+ */
+struct zynq_nand_command_format {
+ u8 start_cmd;
+ u8 end_cmd;
+ u8 addr_cycles;
+ u8 end_cmd_valid;
+};
+
+/* The NAND flash operations command format */
+static const struct zynq_nand_command_format zynq_nand_commands[] = {
+ {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
+ {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
+ {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
+ {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
+ {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
+ {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
+ {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
+ {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
+ {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
+ {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
+ {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
+ {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
+ /* Add all the flash commands supported by the flash device */
+};
+
+/* Define default oob placement schemes for large and small page devices */
+static struct nand_ecclayout nand_oob_16 = {
+ .eccbytes = 3,
+ .eccpos = {0, 1, 2},
+ .oobfree = {
+ { .offset = 8, .length = 8 }
+ }
+};
+
+static struct nand_ecclayout nand_oob_64 = {
+ .eccbytes = 12,
+ .eccpos = {
+ 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 61, 62, 63},
+ .oobfree = {
+ { .offset = 2, .length = 50 }
+ }
+};
+
+static struct nand_ecclayout ondie_nand_oob_64 = {
+ .eccbytes = 32,
+
+ .eccpos = {
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 56, 57, 58, 59, 60, 61, 62, 63
+ },
+
+ .oobfree = {
+ { .offset = 4, .length = 4 },
+ { .offset = 20, .length = 4 },
+ { .offset = 36, .length = 4 },
+ { .offset = 52, .length = 4 }
+ }
+};
+
+/* bbt decriptors for chips with on-die ECC and
+ chips with 64-byte OOB */
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 4,
+ .len = 4,
+ .veroffs = 20,
+ .maxblocks = 4,
+ .pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 4,
+ .len = 4,
+ .veroffs = 20,
+ .maxblocks = 4,
+ .pattern = mirror_pattern
+};
+
+/*
+ * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
+ *
+ * returns: status for command completion, -1 for Timeout
+ */
+static int zynq_nand_waitfor_ecc_completion(void)
+{
+ unsigned long timeout;
+ u32 status;
+
+ /* Wait max 10us */
+ timeout = 10;
+ status = readl(&zynq_nand_smc_base->esr);
+ while (status & ZYNQ_NAND_ECC_BUSY) {
+ status = readl(&zynq_nand_smc_base->esr);
+ if (timeout == 0)
+ return -1;
+ timeout--;
+ udelay(1);
+ }
+
+ return status;
+}
+
+/*
+ * zynq_nand_init_nand_flash - Initialize NAND controller
+ * @option: Device property flags
+ *
+ * This function initializes the NAND flash interface on the NAND controller.
+ *
+ * returns: 0 on success or error value on failure
+ */
+static int zynq_nand_init_nand_flash(int option)
+{
+ u32 status;
+
+ /* disable interrupts */
+ writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
+ /* Initialize the NAND interface by setting cycles and operation mode */
+ writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
+ if (option & NAND_BUSWIDTH_16)
+ writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
+ else
+ writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
+
+ writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
+
+ /* Wait till the ECC operation is complete */
+ status = zynq_nand_waitfor_ecc_completion();
+ if (status < 0) {
+ printf("%s: Timeout\n", __func__);
+ return status;
+ }
+
+ /* Set the command1 and command2 register */
+ writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
+ writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
+
+ return 0;
+}
+
+/*
+ * zynq_nand_calculate_hwecc - Calculate Hardware ECC
+ * @mtd: Pointer to the mtd_info structure
+ * @data: Pointer to the page data
+ * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored
+ *
+ * This function retrieves the Hardware ECC data from the controller and returns
+ * ECC data back to the MTD subsystem.
+ *
+ * returns: 0 on success or error value on failure
+ */
+static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
+ u8 *ecc_code)
+{
+ u32 ecc_value = 0;
+ u8 ecc_reg, ecc_byte;
+ u32 ecc_status;
+
+ /* Wait till the ECC operation is complete */
+ ecc_status = zynq_nand_waitfor_ecc_completion();
+ if (ecc_status < 0) {
+ printf("%s: Timeout\n", __func__);
+ return ecc_status;
+ }
+
+ for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
+ /* Read ECC value for each block */
+ ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
+
+ /* Get the ecc status from ecc read value */
+ ecc_status = (ecc_value >> 24) & 0xFF;
+
+ /* ECC value valid */
+ if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
+ for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
+ /* Copy ECC bytes to MTD buffer */
+ *ecc_code = ecc_value & 0xFF;
+ ecc_value = ecc_value >> 8;
+ ecc_code++;
+ }
+ } else {
+ debug("%s: ecc status failed\n", __func__);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * onehot - onehot function
+ * @value: value to check for onehot
+ *
+ * This function checks whether a value is onehot or not.
+ * onehot is if and only if one bit is set.
+ *
+ * FIXME: Try to move this in common.h
+ */
+static bool onehot(unsigned short value)
+{
+ bool onehot;
+
+ onehot = value && !(value & (value - 1));
+ return onehot;
+}
+
+/*
+ * zynq_nand_correct_data - ECC correction function
+ * @mtd: Pointer to the mtd_info structure
+ * @buf: Pointer to the page data
+ * @read_ecc: Pointer to the ECC value read from spare data area
+ * @calc_ecc: Pointer to the calculated ECC value
+ *
+ * This function corrects the ECC single bit errors & detects 2-bit errors.
+ *
+ * returns: 0 if no ECC errors found
+ * 1 if single bit error found and corrected.
+ * -1 if multiple ECC errors found.
+ */
+static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
+ unsigned char *read_ecc, unsigned char *calc_ecc)
+{
+ unsigned char bit_addr;
+ unsigned int byte_addr;
+ unsigned short ecc_odd, ecc_even;
+ unsigned short read_ecc_lower, read_ecc_upper;
+ unsigned short calc_ecc_lower, calc_ecc_upper;
+
+ read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
+ read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
+
+ calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
+ calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
+
+ ecc_odd = read_ecc_lower ^ calc_ecc_lower;
+ ecc_even = read_ecc_upper ^ calc_ecc_upper;
+
+ if ((ecc_odd == 0) && (ecc_even == 0))
+ return 0; /* no error */
+
+ if (ecc_odd == (~ecc_even & 0xfff)) {
+ /* bits [11:3] of error code is byte offset */
+ byte_addr = (ecc_odd >> 3) & 0x1ff;
+ /* bits [2:0] of error code is bit offset */
+ bit_addr = ecc_odd & 0x7;
+ /* Toggling error bit */
+ buf[byte_addr] ^= (1 << bit_addr);
+ return 1;
+ }
+
+ if (onehot(ecc_odd | ecc_even))
+ return 1; /* one error in parity */
+
+ return -1; /* Uncorrectable error */
+}
+
+/*
+ * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to read
+ * @sndcmd: flag whether to issue read command or not
+ */
+static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ unsigned long data_phase_addr = 0;
+ int data_width = 4;
+ u8 *p;
+
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+
+ p = chip->oob_poi;
+ chip->read_buf(mtd, p, (mtd->oobsize - data_width));
+ p += mtd->oobsize - data_width;
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+ chip->read_buf(mtd, p, data_width);
+
+ return 0;
+}
+
+/*
+ * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to write
+ */
+static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ int status = 0, data_width = 4;
+ const u8 *buf = chip->oob_poi;
+ unsigned long data_phase_addr = 0;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+ chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
+ buf += mtd->oobsize - data_width;
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+ chip->write_buf(mtd, buf, data_width);
+
+ /* Send command to program the OOB data */
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/*
+ * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to read
+ */
+static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ u8 *buf, int oob_required, int page)
+{
+ unsigned long data_width = 4;
+ unsigned long data_phase_addr = 0;
+ u8 *p;
+
+ chip->read_buf(mtd, buf, mtd->writesize);
+
+ p = chip->oob_poi;
+ chip->read_buf(mtd, p, (mtd->oobsize - data_width));
+ p += (mtd->oobsize - data_width);
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+
+ chip->read_buf(mtd, p, data_width);
+ return 0;
+}
+
+static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
+ struct nand_chip *chip, u8 *buf, int oob_required, int page)
+{
+ chip->read_buf(mtd, buf, mtd->writesize);
+ return 0;
+}
+
+static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, u32 data_offs,
+ u32 readlen, u8 *buf, int page)
+{
+ if (data_offs != 0) {
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
+ buf += data_offs;
+ }
+ chip->read_buf(mtd, buf, readlen);
+
+ return 0;
+}
+
+/*
+ * zynq_nand_write_page_raw - [Intern] raw page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ */
+static int zynq_nand_write_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, const u8 *buf, int oob_required, int page)
+{
+ unsigned long data_width = 4;
+ unsigned long data_phase_addr = 0;
+ u8 *p;
+
+ chip->write_buf(mtd, buf, mtd->writesize);
+
+ p = chip->oob_poi;
+ chip->write_buf(mtd, p, (mtd->oobsize - data_width));
+ p += (mtd->oobsize - data_width);
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+
+ chip->write_buf(mtd, p, data_width);
+
+ return 0;
+}
+
+/*
+ * nand_write_page_hwecc - Hardware ECC based page write function
+ * @mtd: Pointer to the mtd info structure
+ * @chip: Pointer to the NAND chip info structure
+ * @buf: Pointer to the data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ *
+ * This functions writes data and hardware generated ECC values in to the page.
+ */
+static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const u8 *buf, int oob_required, int page)
+{
+ int i, eccsteps, eccsize = chip->ecc.size;
+ u8 *ecc_calc = chip->buffers->ecccalc;
+ const u8 *p = buf;
+ u32 *eccpos = chip->ecc.layout->eccpos;
+ unsigned long data_phase_addr = 0;
+ unsigned long data_width = 4;
+ u8 *oob_ptr;
+
+ for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
+ chip->write_buf(mtd, p, eccsize);
+ p += eccsize;
+ }
+ chip->write_buf(mtd, p, (eccsize - data_width));
+ p += eccsize - data_width;
+
+ /* Set ECC Last bit to 1 */
+ data_phase_addr = (unsigned long) chip->IO_ADDR_W;
+ data_phase_addr |= ZYNQ_NAND_ECC_LAST;
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+ chip->write_buf(mtd, p, data_width);
+
+ /* Wait for ECC to be calculated and read the error values */
+ p = buf;
+ chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+
+ for (i = 0; i < chip->ecc.total; i++)
+ chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
+
+ /* Clear ECC last bit */
+ data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+ data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+
+ /* Write the spare area with ECC bytes */
+ oob_ptr = chip->oob_poi;
+ chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+ oob_ptr += (mtd->oobsize - data_width);
+ chip->write_buf(mtd, oob_ptr, data_width);
+
+ return 0;
+}
+
+/*
+ * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
+ * write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ */
+static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const u8 *buf, int oob_required, int page)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ u8 *ecc_calc = chip->buffers->ecccalc;
+ const u8 *p = buf;
+ u32 *eccpos = chip->ecc.layout->eccpos;
+
+ /* Software ecc calculation */
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ for (i = 0; i < chip->ecc.total; i++)
+ chip->oob_poi[eccpos[i]] = ecc_calc[i];
+
+ return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
+}
+
+/*
+ * nand_read_page_hwecc - Hardware ECC based page read function
+ * @mtd: Pointer to the mtd info structure
+ * @chip: Pointer to the NAND chip info structure
+ * @buf: Pointer to the buffer to store read data
+ * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to read
+ *
+ * This functions reads data and checks the data integrity by comparing hardware
+ * generated ECC values and read ECC values from spare area.
+ *
+ * returns: 0 always and updates ECC operation status in to MTD structure
+ */
+static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, u8 *buf, int oob_required, int page)
+{
+ int i, stat, eccsteps, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ u8 *p = buf;
+ u8 *ecc_calc = chip->buffers->ecccalc;
+ u8 *ecc_code = chip->buffers->ecccode;
+ u32 *eccpos = chip->ecc.layout->eccpos;
+ unsigned long data_phase_addr = 0;
+ unsigned long data_width = 4;
+ u8 *oob_ptr;
+
+ for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
+ chip->read_buf(mtd, p, eccsize);
+ p += eccsize;
+ }
+ chip->read_buf(mtd, p, (eccsize - data_width));
+ p += eccsize - data_width;
+
+ /* Set ECC Last bit to 1 */
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr |= ZYNQ_NAND_ECC_LAST;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+ chip->read_buf(mtd, p, data_width);
+
+ /* Read the calculated ECC value */
+ p = buf;
+ chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+
+ /* Clear ECC last bit */
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+
+ /* Read the stored ECC value */
+ oob_ptr = chip->oob_poi;
+ chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
+
+ /* de-assert chip select */
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+
+ oob_ptr += (mtd->oobsize - data_width);
+ chip->read_buf(mtd, oob_ptr, data_width);
+
+ for (i = 0; i < chip->ecc.total; i++)
+ ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
+
+ eccsteps = chip->ecc.steps;
+ p = buf;
+
+ /* Check ECC error for all blocks and correct if it is correctable */
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+ }
+ return 0;
+}
+
+/*
+ * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
+ * read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @page: page number to read
+ */
+static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
+ struct nand_chip *chip, u8 *buf, int oob_required, int page)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ u8 *p = buf;
+ u8 *ecc_calc = chip->buffers->ecccalc;
+ u8 *ecc_code = chip->buffers->ecccode;
+ u32 *eccpos = chip->ecc.layout->eccpos;
+
+ chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ for (i = 0; i < chip->ecc.total; i++)
+ ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+ eccsteps = chip->ecc.steps;
+ p = buf;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+ }
+ return 0;
+}
+
+/*
+ * zynq_nand_select_chip - Select the flash device
+ * @mtd: Pointer to the mtd_info structure
+ * @chip: Chip number to be selected
+ *
+ * This function is empty as the NAND controller handles chip select line
+ * internally based on the chip address passed in command and data phase.
+ */
+static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ /* Not support multiple chips yet */
+}
+
+/*
+ * zynq_nand_cmd_function - Send command to NAND device
+ * @mtd: Pointer to the mtd_info structure
+ * @command: The command to be sent to the flash device
+ * @column: The column address for this command, -1 if none
+ * @page_addr: The page address for this command, -1 if none
+ */
+static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd->priv;
+ const struct zynq_nand_command_format *curr_cmd = NULL;
+ struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
+ void *cmd_addr;
+ unsigned long cmd_data = 0;
+ unsigned long cmd_phase_addr = 0;
+ unsigned long data_phase_addr = 0;
+ u8 end_cmd = 0;
+ u8 end_cmd_valid = 0;
+ u32 index;
+
+ if (xnand->end_cmd_pending) {
+ /* Check for end command if this command request is same as the
+ * pending command then return
+ */
+ if (xnand->end_cmd == command) {
+ xnand->end_cmd = 0;
+ xnand->end_cmd_pending = 0;
+ return;
+ }
+ }
+
+ /* Emulate NAND_CMD_READOOB for large page device */
+ if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
+ (command == NAND_CMD_READOOB)) {
+ column += mtd->writesize;
+ command = NAND_CMD_READ0;
+ }
+
+ /* Get the command format */
+ for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
+ if (command == zynq_nand_commands[index].start_cmd)
+ break;
+
+ if (index == ARRAY_SIZE(zynq_nand_commands)) {
+ printf("%s: Unsupported start cmd %02x\n", __func__, command);
+ return;
+ }
+ curr_cmd = &zynq_nand_commands[index];
+
+ /* Clear interrupt */
+ writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
+
+ /* Get the command phase address */
+ if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
+ end_cmd_valid = 1;
+
+ if (curr_cmd->end_cmd == NAND_CMD_NONE)
+ end_cmd = 0x0;
+ else
+ end_cmd = curr_cmd->end_cmd;
+
+ cmd_phase_addr = (unsigned long)xnand->nand_base |
+ (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT) |
+ (end_cmd_valid << END_CMD_VALID_SHIFT) |
+ (COMMAND_PHASE) |
+ (end_cmd << END_CMD_SHIFT) |
+ (curr_cmd->start_cmd << START_CMD_SHIFT);
+
+ cmd_addr = (void __iomem *)cmd_phase_addr;
+
+ /* Get the data phase address */
+ end_cmd_valid = 0;
+
+ data_phase_addr = (unsigned long)xnand->nand_base |
+ (0x0 << CLEAR_CS_SHIFT) |
+ (end_cmd_valid << END_CMD_VALID_SHIFT) |
+ (DATA_PHASE) |
+ (end_cmd << END_CMD_SHIFT) |
+ (0x0 << ECC_LAST_SHIFT);
+
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+ chip->IO_ADDR_W = chip->IO_ADDR_R;
+
+ /* Command phase AXI Read & Write */
+ if (column != -1 && page_addr != -1) {
+ /* Adjust columns for 16 bit bus width */
+ if (chip->options & NAND_BUSWIDTH_16)
+ column >>= 1;
+ cmd_data = column;
+ if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
+ cmd_data |= page_addr << 16;
+ /* Another address cycle for devices > 128MiB */
+ if (chip->chipsize > (128 << 20)) {
+ writel(cmd_data, cmd_addr);
+ cmd_data = (page_addr >> 16);
+ }
+ } else {
+ cmd_data |= page_addr << 8;
+ }
+ } else if (page_addr != -1) { /* Erase */
+ cmd_data = page_addr;
+ } else if (column != -1) { /* Change read/write column, read id etc */
+ /* Adjust columns for 16 bit bus width */
+ if ((chip->options & NAND_BUSWIDTH_16) &&
+ ((command == NAND_CMD_READ0) ||
+ (command == NAND_CMD_SEQIN) ||
+ (command == NAND_CMD_RNDOUT) ||
+ (command == NAND_CMD_RNDIN)))
+ column >>= 1;
+ cmd_data = column;
+ }
+
+ writel(cmd_data, cmd_addr);
+
+ if (curr_cmd->end_cmd_valid) {
+ xnand->end_cmd = curr_cmd->end_cmd;
+ xnand->end_cmd_pending = 1;
+ }
+
+ ndelay(100);
+
+ if ((command == NAND_CMD_READ0) ||
+ (command == NAND_CMD_RESET) ||
+ (command == NAND_CMD_PARAM) ||
+ (command == NAND_CMD_GET_FEATURES))
+ /* wait until command is processed */
+ nand_wait_ready(mtd);
+}
+
+/*
+ * zynq_nand_read_buf - read chip data into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
+static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ /* Make sure that buf is 32 bit aligned */
+ if (((unsigned long)buf & 0x3) != 0) {
+ if (((unsigned long)buf & 0x1) != 0) {
+ if (len) {
+ *buf = readb(chip->IO_ADDR_R);
+ buf += 1;
+ len--;
+ }
+ }
+
+ if (((unsigned long)buf & 0x3) != 0) {
+ if (len >= 2) {
+ *(u16 *)buf = readw(chip->IO_ADDR_R);
+ buf += 2;
+ len -= 2;
+ }
+ }
+ }
+
+ /* copy aligned data */
+ while (len >= 4) {
+ *(u32 *)buf = readl(chip->IO_ADDR_R);
+ buf += 4;
+ len -= 4;
+ }
+
+ /* mop up any remaining bytes */
+ if (len) {
+ if (len >= 2) {
+ *(u16 *)buf = readw(chip->IO_ADDR_R);
+ buf += 2;
+ len -= 2;
+ }
+ if (len)
+ *buf = readb(chip->IO_ADDR_R);
+ }
+}
+
+/*
+ * zynq_nand_write_buf - write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ const u32 *nand = chip->IO_ADDR_W;
+
+ /* Make sure that buf is 32 bit aligned */
+ if (((unsigned long)buf & 0x3) != 0) {
+ if (((unsigned long)buf & 0x1) != 0) {
+ if (len) {
+ writeb(*buf, nand);
+ buf += 1;
+ len--;
+ }
+ }
+
+ if (((unsigned long)buf & 0x3) != 0) {
+ if (len >= 2) {
+ writew(*(u16 *)buf, nand);
+ buf += 2;
+ len -= 2;
+ }
+ }
+ }
+
+ /* copy aligned data */
+ while (len >= 4) {
+ writel(*(u32 *)buf, nand);
+ buf += 4;
+ len -= 4;
+ }
+
+ /* mop up any remaining bytes */
+ if (len) {
+ if (len >= 2) {
+ writew(*(u16 *)buf, nand);
+ buf += 2;
+ len -= 2;
+ }
+
+ if (len)
+ writeb(*buf, nand);
+ }
+}
+
+/*
+ * zynq_nand_device_ready - Check device ready/busy line
+ * @mtd: Pointer to the mtd_info structure
+ *
+ * returns: 0 on busy or 1 on ready state
+ */
+static int zynq_nand_device_ready(struct mtd_info *mtd)
+{
+ u32 csr_val;
+
+ csr_val = readl(&zynq_nand_smc_base->csr);
+ /* Check the raw_int_status1 bit */
+ if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
+ /* Clear the interrupt condition */
+ writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
+ return 1;
+ }
+
+ return 0;
+}
+
+static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+{
+ struct zynq_nand_info *xnand;
+ struct mtd_info *mtd;
+ unsigned long ecc_page_size;
+ u8 maf_id, dev_id, i;
+ u8 get_feature[4];
+ u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
+ unsigned long ecc_cfg;
+ int ondie_ecc_enabled = 0;
+ int err = -1;
+
+ xnand = calloc(1, sizeof(struct zynq_nand_info));
+ if (!xnand) {
+ printf("%s: failed to allocate\n", __func__);
+ goto fail;
+ }
+
+ xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
+ mtd = (struct mtd_info *)&nand_info[0];
+
+ nand_chip->priv = xnand;
+ mtd->priv = nand_chip;
+
+ /* Set address of NAND IO lines */
+ nand_chip->IO_ADDR_R = xnand->nand_base;
+ nand_chip->IO_ADDR_W = xnand->nand_base;
+
+ /* Set the driver entry points for MTD */
+ nand_chip->cmdfunc = zynq_nand_cmd_function;
+ nand_chip->dev_ready = zynq_nand_device_ready;
+ nand_chip->select_chip = zynq_nand_select_chip;
+
+ /* If we don't set this delay driver sets 20us by default */
+ nand_chip->chip_delay = 30;
+
+ /* Buffer read/write routines */
+ nand_chip->read_buf = zynq_nand_read_buf;
+ nand_chip->write_buf = zynq_nand_write_buf;
+
+ nand_chip->bbt_options = NAND_BBT_USE_FLASH;
+
+ /* Initialize the NAND flash interface on NAND controller */
+ if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
+ printf("%s: nand flash init failed\n", __func__);
+ goto fail;
+ }
+
+ /* first scan to find the device and get the page size */
+ if (nand_scan_ident(mtd, 1, NULL)) {
+ printf("%s: nand_scan_ident failed\n", __func__);
+ goto fail;
+ }
+ /* Send the command for reading device ID */
+ nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+ /* Read manufacturer and device IDs */
+ maf_id = nand_chip->read_byte(mtd);
+ dev_id = nand_chip->read_byte(mtd);
+
+ if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
+ (dev_id == 0xa1) || (dev_id == 0xb1) ||
+ (dev_id == 0xaa) || (dev_id == 0xba) ||
+ (dev_id == 0xda) || (dev_id == 0xca) ||
+ (dev_id == 0xac) || (dev_id == 0xbc) ||
+ (dev_id == 0xdc) || (dev_id == 0xcc) ||
+ (dev_id == 0xa3) || (dev_id == 0xb3) ||
+ (dev_id == 0xd3) || (dev_id == 0xc3))) {
+ nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
+ ONDIE_ECC_FEATURE_ADDR, -1);
+ for (i = 0; i < 4; i++)
+ writeb(set_feature[i], nand_chip->IO_ADDR_W);
+
+ /* Wait for 1us after writing data with SET_FEATURES command */
+ ndelay(1000);
+
+ nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
+ ONDIE_ECC_FEATURE_ADDR, -1);
+ nand_chip->read_buf(mtd, get_feature, 4);
+
+ if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
+ debug("%s: OnDie ECC flash\n", __func__);
+ ondie_ecc_enabled = 1;
+ } else {
+ printf("%s: Unable to detect OnDie ECC\n", __func__);
+ }
+ }
+
+ if (ondie_ecc_enabled) {
+ /* Bypass the controller ECC block */
+ ecc_cfg = readl(&zynq_nand_smc_base->emcr);
+ ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
+ writel(ecc_cfg, &zynq_nand_smc_base->emcr);
+
+ /* The software ECC routines won't work
+ * with the SMC controller
+ */
+ nand_chip->ecc.mode = NAND_ECC_HW;
+ nand_chip->ecc.strength = 1;
+ nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
+ nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
+ nand_chip->ecc.write_page = zynq_nand_write_page_raw;
+ nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
+ nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
+ nand_chip->ecc.read_oob = zynq_nand_read_oob;
+ nand_chip->ecc.write_oob = zynq_nand_write_oob;
+ nand_chip->ecc.size = mtd->writesize;
+ nand_chip->ecc.bytes = 0;
+
+ /* NAND with on-die ECC supports subpage reads */
+ nand_chip->options |= NAND_SUBPAGE_READ;
+
+ /* On-Die ECC spare bytes offset 8 is used for ECC codes */
+ if (ondie_ecc_enabled) {
+ nand_chip->ecc.layout = &ondie_nand_oob_64;
+ /* Use the BBT pattern descriptors */
+ nand_chip->bbt_td = &bbt_main_descr;
+ nand_chip->bbt_md = &bbt_mirror_descr;
+ }
+ } else {
+ /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
+ nand_chip->ecc.mode = NAND_ECC_HW;
+ nand_chip->ecc.strength = 1;
+ nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
+ nand_chip->ecc.bytes = 3;
+ nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
+ nand_chip->ecc.correct = zynq_nand_correct_data;
+ nand_chip->ecc.hwctl = NULL;
+ nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
+ nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
+ nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
+ nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
+ nand_chip->ecc.read_oob = zynq_nand_read_oob;
+ nand_chip->ecc.write_oob = zynq_nand_write_oob;
+
+ switch (mtd->writesize) {
+ case 512:
+ ecc_page_size = 0x1;
+ /* Set the ECC memory config register */
+ writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
+ &zynq_nand_smc_base->emcr);
+ break;
+ case 1024:
+ ecc_page_size = 0x2;
+ /* Set the ECC memory config register */
+ writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
+ &zynq_nand_smc_base->emcr);
+ break;
+ case 2048:
+ ecc_page_size = 0x3;
+ /* Set the ECC memory config register */
+ writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
+ &zynq_nand_smc_base->emcr);
+ break;
+ default:
+ nand_chip->ecc.mode = NAND_ECC_SOFT;
+ nand_chip->ecc.calculate = nand_calculate_ecc;
+ nand_chip->ecc.correct = nand_correct_data;
+ nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
+ nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
+ nand_chip->ecc.size = 256;
+ break;
+ }
+
+ if (mtd->oobsize == 16)
+ nand_chip->ecc.layout = &nand_oob_16;
+ else if (mtd->oobsize == 64)
+ nand_chip->ecc.layout = &nand_oob_64;
+ else
+ printf("%s: No oob layout found\n", __func__);
+ }
+
+ /* Second phase scan */
+ if (nand_scan_tail(mtd)) {
+ printf("%s: nand_scan_tail failed\n", __func__);
+ goto fail;
+ }
+ if (nand_register(devnum, mtd))
+ goto fail;
+ return 0;
+fail:
+ free(xnand);
+ return err;
+}
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+void board_nand_init(void)
+{
+ struct nand_chip *nand = &nand_chip[0];
+
+ if (zynq_nand_init(nand, 0))
+ puts("ZYNQ NAND init failed\n");
+}
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 0e35dc5..2e3d0e5 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -27,7 +27,7 @@
#include <linux/mtd/onenand.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <malloc.h>
/* It should access 16-bit instead of 8-bit */
diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c
index 52509f1..2050700 100644
--- a/drivers/mtd/onenand/onenand_bbt.c
+++ b/drivers/mtd/onenand/onenand_bbt.c
@@ -20,7 +20,7 @@
#include <linux/mtd/onenand.h>
#include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
/**
* check_short_pattern - [GENERIC] check if a pattern is in the buffer
diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c
index 5e56a29..10dd268 100644
--- a/drivers/mtd/onenand/samsung.c
+++ b/drivers/mtd/onenand/samsung.c
@@ -19,7 +19,7 @@
#include <linux/mtd/samsung_onenand.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#define ONENAND_ERASE_STATUS 0x00
#define ONENAND_MULTI_ERASE_SET 0x01
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 6f47a66..fcda023 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -8,12 +8,11 @@
obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
obj-$(CONFIG_SPL_SPI_SUNXI) += sunxi_spi_spl.o
endif
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o sf_params.o sf.o
+obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index b915469..1dd44e2 100644
--- a/drivers/mtd/spi/fsl_espi_spl.c
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -12,7 +12,7 @@
#define ESPI_BOOT_IMAGE_ADDR 0x50
#define CONFIG_CFG_DATA_SECTOR 0
-void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
+void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
{
struct spi_flash *flash;
@@ -31,7 +31,7 @@
* configured and available since this code loads the main U-Boot image
* from SPI into SDRAM and starts it from there.
*/
-void spi_boot(void)
+void fsl_spi_boot(void)
{
void (*uboot)(void) __noreturn;
u32 offset, code_len, copy_len = 0;
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 53470b9..4944059 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -88,7 +88,7 @@
/* The current flash status (see STAT_XXX defines above) */
u16 status;
/* Data describing the flash we're emulating */
- const struct spi_flash_params *data;
+ const struct spi_flash_info *data;
/* The file on disk to serv up data from */
int fd;
};
@@ -112,7 +112,7 @@
struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
const char *file;
size_t len, idname_len;
- const struct spi_flash_params *data;
+ const struct spi_flash_info *data;
struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
struct sandbox_state *state = state_get_current();
struct udevice *bus = dev->parent;
@@ -168,7 +168,7 @@
}
debug("%s: device='%s'\n", __func__, spec);
- for (data = spi_flash_params_table; data->name; data++) {
+ for (data = spi_flash_ids; data->name; data++) {
len = strlen(data->name);
if (idname_len != len)
continue;
@@ -289,13 +289,10 @@
/* we only support erase here */
if (sbsf->cmd == CMD_ERASE_CHIP) {
sbsf->erase_size = sbsf->data->sector_size *
- sbsf->data->nr_sectors;
+ sbsf->data->n_sectors;
} else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) {
sbsf->erase_size = 4 << 10;
- } else if (sbsf->cmd == CMD_ERASE_32K && (flags & SECT_32K)) {
- sbsf->erase_size = 32 << 10;
- } else if (sbsf->cmd == CMD_ERASE_64K &&
- !(flags & (SECT_4K | SECT_32K))) {
+ } else if (sbsf->cmd == CMD_ERASE_64K && !(flags & SECT_4K)) {
sbsf->erase_size = 64 << 10;
} else {
debug(" cmd unknown: %#x\n", sbsf->cmd);
@@ -362,7 +359,8 @@
debug(" id: off:%u tx:", sbsf->off);
if (sbsf->off < IDCODE_LEN) {
/* Extract correct byte from ID 0x00aabbcc */
- id = sbsf->data->jedec >>
+ id = ((JEDEC_MFR(sbsf->data) << 16) |
+ JEDEC_ID(sbsf->data)) >>
(8 * (IDCODE_LEN - 1 - sbsf->off));
} else {
id = 0;
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index 664e860..d5e175c 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -18,10 +18,6 @@
unsigned long flags = SPI_XFER_BEGIN;
int ret;
-#ifdef CONFIG_SF_DUAL_FLASH
- if (spi->flags & SPI_XFER_U_PAGE)
- flags |= SPI_XFER_U_PAGE;
-#endif
if (data_len == 0)
flags |= SPI_XFER_END;
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index b2a56da..bcddfa0 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -1,12 +1,12 @@
/*
- *
* Atmel DataFlash probing
*
* Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
* Haikun Wang (haikun.wang@freescale.com)
*
* SPDX-License-Identifier: GPL-2.0+
-*/
+ */
+
#include <common.h>
#include <dm.h>
#include <errno.h>
@@ -67,15 +67,12 @@
#define OP_WRITE_SECURITY_REVC 0x9A
#define OP_WRITE_SECURITY 0x9B /* revision D */
-
struct dataflash {
uint8_t command[16];
unsigned short page_offset; /* offset in flash address */
};
-/*
- * Return the status of the DataFlash device.
- */
+/* Return the status of the DataFlash device */
static inline int dataflash_status(struct spi_slave *spi)
{
int ret;
@@ -114,9 +111,7 @@
return -ETIME;
}
-/*
- * Erase pages of flash.
- */
+/* Erase pages of flash */
static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
{
struct dataflash *dataflash;
@@ -147,7 +142,7 @@
status = spi_claim_bus(spi);
if (status) {
- debug("SPI DATAFLASH: unable to claim SPI bus\n");
+ debug("dataflash: unable to claim SPI bus\n");
return status;
}
@@ -232,7 +227,7 @@
status = spi_claim_bus(spi);
if (status) {
- debug("SPI DATAFLASH: unable to claim SPI bus\n");
+ debug("dataflash: unable to claim SPI bus\n");
return status;
}
@@ -290,7 +285,7 @@
status = spi_claim_bus(spi);
if (status) {
- debug("SPI DATAFLASH: unable to claim SPI bus\n");
+ debug("dataflash: unable to claim SPI bus\n");
return status;
}
@@ -387,7 +382,7 @@
/* Check result of the compare operation */
if (status & (1 << 6)) {
- printf("SPI DataFlash: write compare page %u, err %d\n",
+ printf("dataflash: write compare page %u, err %d\n",
pageaddr, status);
remaining = 0;
status = -EIO;
@@ -501,9 +496,10 @@
{ "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
};
-static struct flash_info *jedec_probe(struct spi_slave *spi, u8 *id)
+static struct flash_info *jedec_probe(struct spi_slave *spi)
{
int tmp;
+ uint8_t id[5];
uint32_t jedec;
struct flash_info *info;
int status;
@@ -517,6 +513,11 @@
* That's not an error; only rev C and newer chips handle it, and
* only Atmel sells these chips.
*/
+ tmp = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id));
+ if (tmp < 0) {
+ printf("dataflash: error %d reading JEDEC ID\n", tmp);
+ return ERR_PTR(tmp);
+ }
if (id[0] != 0x1f)
return NULL;
@@ -533,7 +534,7 @@
if (info->flags & SUP_POW2PS) {
status = dataflash_status(spi);
if (status < 0) {
- debug("SPI DataFlash: status error %d\n",
+ debug("dataflash: status error %d\n",
status);
return NULL;
}
@@ -555,10 +556,8 @@
* size (it might be binary) even when we can tell which density
* class is involved (legacy chip id scheme).
*/
- printf("SPI DataFlash: Unsupported flash IDs: ");
- printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
- id[0], jedec, id[3] << 8 | id[4]);
- return NULL;
+ printf("dataflash: JEDEC id %06x not handled\n", jedec);
+ return ERR_PTR(-ENODEV);
}
/*
@@ -580,21 +579,15 @@
struct spi_slave *spi = dev_get_parent_priv(dev);
struct spi_flash *spi_flash;
struct flash_info *info;
- u8 idcode[5];
- int ret, status = 0;
+ int status;
spi_flash = dev_get_uclass_priv(dev);
+ spi_flash->spi = spi;
spi_flash->dev = dev;
- ret = spi_claim_bus(spi);
- if (ret)
- return ret;
-
- ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
- if (ret) {
- printf("SPI DataFlash: Failed to get idcodes\n");
- goto err_read_cmd;
- }
+ status = spi_claim_bus(spi);
+ if (status)
+ return status;
/*
* Try to detect dataflash by JEDEC ID.
@@ -603,79 +596,70 @@
* Both support the security register, though with different
* write procedures.
*/
- info = jedec_probe(spi, idcode);
- if (info != NULL)
- add_dataflash(dev, info->name, info->nr_pages,
- info->pagesize, info->pageoffset,
- (info->flags & SUP_POW2PS) ? 'd' : 'c');
- else {
- /*
- * Older chips support only legacy commands, identifing
- * capacity using bits in the status byte.
- */
- status = dataflash_status(spi);
- if (status <= 0 || status == 0xff) {
- printf("SPI DataFlash: read status error %d\n", status);
- if (status == 0 || status == 0xff)
- status = -ENODEV;
- goto err_read_cmd;
- }
- /*
- * if there's a device there, assume it's dataflash.
- * board setup should have set spi->max_speed_max to
- * match f(car) for continuous reads, mode 0 or 3.
- */
- switch (status & 0x3c) {
- case 0x0c: /* 0 0 1 1 x x */
- status = add_dataflash(dev, "AT45DB011B",
- 512, 264, 9, 0);
- break;
- case 0x14: /* 0 1 0 1 x x */
- status = add_dataflash(dev, "AT45DB021B",
- 1024, 264, 9, 0);
- break;
- case 0x1c: /* 0 1 1 1 x x */
- status = add_dataflash(dev, "AT45DB041x",
- 2048, 264, 9, 0);
- break;
- case 0x24: /* 1 0 0 1 x x */
- status = add_dataflash(dev, "AT45DB081B",
- 4096, 264, 9, 0);
- break;
- case 0x2c: /* 1 0 1 1 x x */
- status = add_dataflash(dev, "AT45DB161x",
- 4096, 528, 10, 0);
- break;
- case 0x34: /* 1 1 0 1 x x */
- status = add_dataflash(dev, "AT45DB321x",
- 8192, 528, 10, 0);
- break;
- case 0x38: /* 1 1 1 x x x */
- case 0x3c:
- status = add_dataflash(dev, "AT45DB642x",
- 8192, 1056, 11, 0);
- break;
- /* obsolete AT45DB1282 not (yet?) supported */
- default:
- dev_info(&spi->dev, "unsupported device (%x)\n",
- status & 0x3c);
- status = -ENODEV;
- goto err_read_cmd;
- }
+ info = jedec_probe(spi);
+ if (IS_ERR(info))
+ goto err_jedec_probe;
+ if (info != NULL) {
+ status = add_dataflash(dev, info->name, info->nr_pages,
+ info->pagesize, info->pageoffset,
+ (info->flags & SUP_POW2PS) ? 'd' : 'c');
+ if (status < 0)
+ goto err_status;
}
- /* Assign spi data */
- spi_flash->spi = spi;
- spi_flash->memory_map = spi->memory_map;
- spi_flash->dual_flash = spi->option;
+ /*
+ * Older chips support only legacy commands, identifing
+ * capacity using bits in the status byte.
+ */
+ status = dataflash_status(spi);
+ if (status <= 0 || status == 0xff) {
+ printf("dataflash: read status error %d\n", status);
+ if (status == 0 || status == 0xff)
+ status = -ENODEV;
+ goto err_jedec_probe;
+ }
+ /*
+ * if there's a device there, assume it's dataflash.
+ * board setup should have set spi->max_speed_max to
+ * match f(car) for continuous reads, mode 0 or 3.
+ */
+ switch (status & 0x3c) {
+ case 0x0c: /* 0 0 1 1 x x */
+ status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0);
+ break;
+ case 0x14: /* 0 1 0 1 x x */
+ status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0);
+ break;
+ case 0x1c: /* 0 1 1 1 x x */
+ status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0);
+ break;
+ case 0x24: /* 1 0 0 1 x x */
+ status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0);
+ break;
+ case 0x2c: /* 1 0 1 1 x x */
+ status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0);
+ break;
+ case 0x34: /* 1 1 0 1 x x */
+ status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0);
+ break;
+ case 0x38: /* 1 1 1 x x x */
+ case 0x3c:
+ status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0);
+ break;
+ /* obsolete AT45DB1282 not (yet?) supported */
+ default:
+ printf("dataflash: unsupported device (%x)\n", status & 0x3c);
+ status = -ENODEV;
+ goto err_status;
+ }
+
+ return status;
+
+err_status:
+ spi_free_slave(spi);
+err_jedec_probe:
spi_release_bus(spi);
-
- return 0;
-
-err_read_cmd:
- spi_release_bus(spi);
-
return status;
}
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index da2bb7b..839cdbe 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -20,37 +20,10 @@
SF_DUAL_PARALLEL_FLASH = BIT(1),
};
-/* Enum list - Full read commands */
-enum spi_read_cmds {
- ARRAY_SLOW = BIT(0),
- ARRAY_FAST = BIT(1),
- DUAL_OUTPUT_FAST = BIT(2),
- QUAD_OUTPUT_FAST = BIT(3),
- DUAL_IO_FAST = BIT(4),
- QUAD_IO_FAST = BIT(5),
-};
-
-/* Normal - Extended - Full command set */
-#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
-#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
-#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
-
-/* sf param flags */
-enum {
-#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
- SECT_4K = 0,
-#else
- SECT_4K = BIT(0),
-#endif
- SECT_32K = BIT(1),
- E_FSR = BIT(2),
- SST_WR = BIT(3),
- WR_QPP = BIT(4),
-};
-
enum spi_nor_option_flags {
SNOR_F_SST_WR = BIT(0),
SNOR_F_USE_FSR = BIT(1),
+ SNOR_F_USE_UPAGE = BIT(3),
};
#define SPI_FLASH_3B_ADDR_LEN 3
@@ -67,7 +40,6 @@
/* Erase commands */
#define CMD_ERASE_4K 0x20
-#define CMD_ERASE_32K 0x52
#define CMD_ERASE_CHIP 0xc7
#define CMD_ERASE_64K 0xd8
@@ -77,7 +49,6 @@
#define CMD_WRITE_DISABLE 0x04
#define CMD_WRITE_ENABLE 0x06
#define CMD_QUAD_PAGE_PROGRAM 0x32
-#define CMD_WRITE_EVCR 0x61
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
@@ -91,7 +62,6 @@
#define CMD_READ_STATUS1 0x35
#define CMD_READ_CONFIG 0x35
#define CMD_FLAG_STATUS 0x70
-#define CMD_READ_EVCR 0x65
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
@@ -106,7 +76,6 @@
#define STATUS_QEB_WINSPAN BIT(1)
#define STATUS_QEB_MXIC BIT(6)
#define STATUS_PEC BIT(7)
-#define STATUS_QEB_MICRON BIT(7)
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
@@ -127,34 +96,45 @@
const void *buf);
#endif
-#ifdef CONFIG_SPI_FLASH_SPANSION
-/* Used for Spansion S25FS-S family flash only. */
-#define CMD_SPANSION_RDAR 0x65 /* Read any device register */
-#define CMD_SPANSION_WRAR 0x71 /* Write any device register */
-#endif
-/**
- * struct spi_flash_params - SPI/QSPI flash device params structure
- *
- * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
- * @ext_jedec: Device ext_jedec ID
- * @sector_size: Isn't necessarily a sector size from vendor,
- * the size listed here is what works with CMD_ERASE_64K
- * @nr_sectors: No.of sectors on this device
- * @e_rd_cmd: Enum list for read commands
- * @flags: Important param, for flash specific behaviour
- */
-struct spi_flash_params {
- const char *name;
- u32 jedec;
- u16 ext_jedec;
- u32 sector_size;
- u32 nr_sectors;
- u8 e_rd_cmd;
- u16 flags;
+#define JEDEC_MFR(info) ((info)->id[0])
+#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
+#define JEDEC_EXT(info) (((info)->id[3]) << 8 | ((info)->id[4]))
+#define SPI_FLASH_MAX_ID_LEN 6
+
+struct spi_flash_info {
+ /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */
+ const char *name;
+
+ /*
+ * This array stores the ID bytes.
+ * The first three bytes are the JEDIC ID.
+ * JEDEC ID zero means "no ID" (mostly older chips).
+ */
+ u8 id[SPI_FLASH_MAX_ID_LEN];
+ u8 id_len;
+
+ /*
+ * The size listed here is what works with SPINOR_OP_SE, which isn't
+ * necessarily called a "sector" by the vendor.
+ */
+ u32 sector_size;
+ u32 n_sectors;
+
+ u16 page_size;
+
+ u16 flags;
+#define SECT_4K BIT(0) /* CMD_ERASE_4K works uniformly */
+#define E_FSR BIT(1) /* use flag status register for */
+#define SST_WR BIT(2) /* use SST byte/word programming */
+#define WR_QPP BIT(3) /* use Quad Page Program */
+#define RD_QUAD BIT(4) /* use Quad Read */
+#define RD_DUAL BIT(5) /* use Dual Read */
+#define RD_QUADIO BIT(6) /* use Quad IO Read */
+#define RD_DUALIO BIT(7) /* use Dual IO Read */
+#define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO)
};
-extern const struct spi_flash_params spi_flash_params_table[];
+extern const struct spi_flash_info spi_flash_ids[];
/* Send a single-byte command to the device and read the response */
int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
@@ -203,7 +183,7 @@
* - SPI claim
* - spi_flash_cmd_write_enable
* - spi_flash_cmd_write
- * - spi_flash_cmd_wait_ready
+ * - spi_flash_wait_till_ready
* - SPI release
*/
int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c
index 0b9cb62..935ae4d 100644
--- a/drivers/mtd/spi/sf_mtd.c
+++ b/drivers/mtd/spi/sf_mtd.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/mtd/mtd.h>
#include <spi_flash.h>
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
deleted file mode 100644
index 70ca236..0000000
--- a/drivers/mtd/spi/sf_params.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * SPI flash Params table
- *
- * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spi.h>
-#include <spi_flash.h>
-
-#include "sf_internal.h"
-
-/* SPI/QSPI flash device params structure */
-const struct spi_flash_params spi_flash_params_table[] = {
-#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K},
- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K},
- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"AT25DF321A", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
- {"AT25DF321", 0x1f4700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
- {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_EON /* EON */
- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0},
- {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0},
-#endif
-#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
- {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_NORM, 0},
- {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, RD_NORM, 0},
-#endif
-#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0},
- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0},
- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0},
- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0},
- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0},
- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
- {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
-#endif
-#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0},
- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0},
- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0},
- {"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, RD_NORM, 0},
- {"S25FL164K", 0x014017, 0x0140, 64 * 1024, 128, RD_NORM, 0},
- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP},
- {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP},
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
- {"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL, WR_QPP},
- {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
- {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
-#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0},
- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0},
- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0},
- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0},
- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0},
- {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0},
- {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0},
- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0},
- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0},
- {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"N25Q016A", 0x20bb15, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_SST /* SST */
- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR},
- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR},
- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR},
- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR},
- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR},
- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
- {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
-#endif
-#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0},
- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0},
- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
-#endif
- {}, /* Empty entry to terminate the list */
- /*
- * Note:
- * Below paired flash devices has similar spi_flash params.
- * (S25FL129P_64K, S25FL128S_64K)
- * (W25Q80BL, W25Q80BV)
- * (W25Q16CL, W25Q16DV)
- * (W25Q32BV, W25Q32FV_SPI)
- * (W25Q64CV, W25Q64FV_SPI)
- * (W25Q128BV, W25Q128FV_SPI)
- * (W25Q32DW, W25Q32FV_QPI)
- * (W25Q64DW, W25Q64FV_QPI)
- * (W25Q128FW, W25Q128FV_QPI)
- */
-};
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 64d4e0f..2e378dc 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -112,39 +112,8 @@
}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int read_evcr(struct spi_flash *flash, u8 *evcr)
-{
- int ret;
- const u8 cmd = CMD_READ_EVCR;
-
- ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
- if (ret < 0) {
- debug("SF: error reading EVCR\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_evcr(struct spi_flash *flash, u8 evcr)
-{
- u8 cmd;
- int ret;
-
- cmd = CMD_WRITE_EVCR;
- ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
- if (ret < 0) {
- debug("SF: error while writing EVCR register\n");
- return ret;
- }
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_SPI_FLASH_BAR
-static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
+static int write_bar(struct spi_flash *flash, u32 offset)
{
u8 cmd, bank_sel;
int ret;
@@ -165,7 +134,7 @@
return flash->bank_curr;
}
-static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0)
+static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
{
u8 curr_bank = 0;
int ret;
@@ -173,7 +142,7 @@
if (flash->size <= SPI_FLASH_16MB_BOUN)
goto bar_end;
- switch (idcode0) {
+ switch (JEDEC_MFR(info)) {
case SPI_FLASH_CFI_MFR_SPANSION:
flash->bank_read_cmd = CMD_BANKADDR_BRRD;
flash->bank_write_cmd = CMD_BANKADDR_BRWR;
@@ -199,15 +168,13 @@
#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
{
- struct spi_slave *spi = flash->spi;
-
switch (flash->dual_flash) {
case SF_DUAL_STACKED_FLASH:
if (*addr >= (flash->size >> 1)) {
*addr -= flash->size >> 1;
- spi->flags |= SPI_XFER_U_PAGE;
+ flash->flags |= SNOR_F_USE_UPAGE;
} else {
- spi->flags &= ~SPI_XFER_U_PAGE;
+ flash->flags &= ~SNOR_F_USE_UPAGE;
}
break;
case SF_DUAL_PARALLEL_FLASH:
@@ -262,8 +229,8 @@
return sr && fsr;
}
-static int spi_flash_cmd_wait_ready(struct spi_flash *flash,
- unsigned long timeout)
+static int spi_flash_wait_till_ready(struct spi_flash *flash,
+ unsigned long timeout)
{
unsigned long timebase;
int ret;
@@ -311,7 +278,7 @@
return ret;
}
- ret = spi_flash_cmd_wait_ready(flash, timeout);
+ ret = spi_flash_wait_till_ready(flash, timeout);
if (ret < 0) {
debug("SF: write %s timed out\n",
timeout == SPI_FLASH_PROG_TIMEOUT ?
@@ -353,7 +320,7 @@
spi_flash_dual(flash, &erase_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, erase_addr);
+ ret = write_bar(flash, erase_addr);
if (ret < 0)
return ret;
#endif
@@ -404,7 +371,7 @@
spi_flash_dual(flash, &write_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, write_addr);
+ ret = write_bar(flash, write_addr);
if (ret < 0)
return ret;
#endif
@@ -508,7 +475,7 @@
spi_flash_dual(flash, &read_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, read_addr);
+ ret = write_bar(flash, read_addr);
if (ret < 0)
return ret;
bank_sel = flash->bank_curr;
@@ -560,7 +527,7 @@
if (ret)
return ret;
- return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
}
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
@@ -608,7 +575,7 @@
break;
}
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret)
break;
@@ -896,37 +863,35 @@
}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int micron_quad_enable(struct spi_flash *flash)
+static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
{
- u8 qeb_status;
- int ret;
+ int tmp;
+ u8 id[SPI_FLASH_MAX_ID_LEN];
+ const struct spi_flash_info *info;
- ret = read_evcr(flash, &qeb_status);
- if (ret < 0)
- return ret;
-
- if (!(qeb_status & STATUS_QEB_MICRON))
- return 0;
-
- ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
- if (ret < 0)
- return ret;
-
- /* read EVCR and check it */
- ret = read_evcr(flash, &qeb_status);
- if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
- printf("SF: Micron EVCR Quad bit not clear\n");
- return -EINVAL;
+ tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
+ if (tmp < 0) {
+ printf("SF: error %d reading JEDEC ID\n", tmp);
+ return ERR_PTR(tmp);
}
- return ret;
-}
-#endif
+ info = spi_flash_ids;
+ for (; info->name != NULL; info++) {
+ if (info->id_len) {
+ if (!memcmp(info->id, id, info->id_len))
+ return info;
+ }
+ }
-static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
+ printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
+ id[0], id[1], id[2]);
+ return ERR_PTR(-ENODEV);
+}
+
+static int set_quad_mode(struct spi_flash *flash,
+ const struct spi_flash_info *info)
{
- switch (idcode0) {
+ switch (JEDEC_MFR(info)) {
#ifdef CONFIG_SPI_FLASH_MACRONIX
case SPI_FLASH_CFI_MFR_MACRONIX:
return macronix_quad_enable(flash);
@@ -938,10 +903,12 @@
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO:
- return micron_quad_enable(flash);
+ debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
+ return 0;
#endif
default:
- printf("SF: Need set QEB func for %02x flash\n", idcode0);
+ printf("SF: Need set QEB func for %02x flash\n",
+ JEDEC_MFR(info));
return -1;
}
}
@@ -960,7 +927,7 @@
return 0;
}
- if (flash->size != size) {
+ if (flash->size > size) {
debug("%s: Memory map must cover entire device\n", __func__);
return -1;
}
@@ -971,145 +938,28 @@
}
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
-#ifdef CONFIG_SPI_FLASH_SPANSION
-static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
-{
- u8 cmd[4];
- u32 offset = 0x800004; /* CR3V register offset */
- u8 cr3v;
- int ret;
-
- cmd[0] = CMD_SPANSION_RDAR;
- cmd[1] = offset >> 16;
- cmd[2] = offset >> 8;
- cmd[3] = offset >> 0;
-
- ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
- if (ret)
- return -EIO;
- /* CR3V bit3: 4-KB Erase */
- if (cr3v & 0x8)
- return 0;
-
- cmd[0] = CMD_SPANSION_WRAR;
- cr3v |= 0x8;
- ret = spi_flash_cmd_write(spi, cmd, 4, &cr3v, 1);
- if (ret)
- return -EIO;
-
- cmd[0] = CMD_SPANSION_RDAR;
- ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
- if (ret)
- return -EIO;
- if (!(cr3v & 0x8))
- return -EFAULT;
-
- return 0;
-}
-#endif
-
int spi_flash_scan(struct spi_flash *flash)
{
struct spi_slave *spi = flash->spi;
- const struct spi_flash_params *params;
- u16 jedec, ext_jedec;
- u8 cmd, idcode[5];
+ const struct spi_flash_info *info = NULL;
int ret;
- static u8 spi_read_cmds_array[] = {
- CMD_READ_ARRAY_SLOW,
- CMD_READ_ARRAY_FAST,
- CMD_READ_DUAL_OUTPUT_FAST,
- CMD_READ_QUAD_OUTPUT_FAST,
- CMD_READ_DUAL_IO_FAST,
- CMD_READ_QUAD_IO_FAST };
- /* Read the ID codes */
- ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
- if (ret) {
- printf("SF: Failed to get idcodes\n");
- return ret;
- }
+ info = spi_flash_read_id(flash);
+ if (IS_ERR_OR_NULL(info))
+ return -ENOENT;
-#ifdef DEBUG
- printf("SF: Got idcodes\n");
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
-#endif
-
- jedec = idcode[1] << 8 | idcode[2];
- ext_jedec = idcode[3] << 8 | idcode[4];
-
- /* Validate params from spi_flash_params table */
- params = spi_flash_params_table;
- for (; params->name != NULL; params++) {
- if ((params->jedec >> 16) == idcode[0]) {
- if ((params->jedec & 0xFFFF) == jedec) {
- if (params->ext_jedec == 0)
- break;
- else if (params->ext_jedec == ext_jedec)
- break;
- }
- }
- }
-
- if (!params->name) {
- printf("SF: Unsupported flash IDs: ");
- printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
- idcode[0], jedec, ext_jedec);
- return -EPROTONOSUPPORT;
- }
-
-#ifdef CONFIG_SPI_FLASH_SPANSION
- /*
- * The S25FS-S family physical sectors may be configured as a
- * hybrid combination of eight 4-kB parameter sectors
- * at the top or bottom of the address space with all
- * but one of the remaining sectors being uniform size.
- * The Parameter Sector Erase commands (20h or 21h) must
- * be used to erase the 4-kB parameter sectors individually.
- * The Sector (uniform sector) Erase commands (D8h or DCh)
- * must be used to erase any of the remaining
- * sectors, including the portion of highest or lowest address
- * sector that is not overlaid by the parameter sectors.
- * The uniform sector erase command has no effect on parameter sectors.
- */
- if ((jedec == 0x0219 || (jedec == 0x0220)) &&
- (ext_jedec & 0xff00) == 0x4d00) {
- int ret;
- u8 id[6];
-
- /* Read the ID codes again, 6 bytes */
- ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
- if (ret)
- return -EIO;
-
- ret = memcmp(id, idcode, 5);
- if (ret)
- return -EIO;
-
- /* 0x81: S25FS-S family 0x80: S25FL-S family */
- if (id[5] == 0x81) {
- ret = spansion_s25fss_disable_4KB_erase(spi);
- if (ret)
- return ret;
- }
- }
-#endif
/* Flash powers up read-only, so clear BP# bits */
- if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
- idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
- idcode[0] == SPI_FLASH_CFI_MFR_SST)
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
+ JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
+ JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
write_sr(flash, 0);
- /* Assign spi data */
- flash->name = params->name;
+ flash->name = info->name;
flash->memory_map = spi->memory_map;
- flash->dual_flash = spi->option;
- /* Assign spi flash flags */
- if (params->flags & SST_WR)
+ if (info->flags & SST_WR)
flash->flags |= SNOR_F_SST_WR;
- /* Assign spi_flash ops */
#ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
@@ -1124,52 +974,46 @@
flash->read = spi_flash_cmd_read_ops;
#endif
- /* lock hooks are flash specific - assign them based on idcode0 */
- switch (idcode[0]) {
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
- case SPI_FLASH_CFI_MFR_STMICRO:
- case SPI_FLASH_CFI_MFR_SST:
+ /* NOR protection support for STmicro/Micron chips and similar */
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO ||
+ JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) {
flash->flash_lock = stm_lock;
flash->flash_unlock = stm_unlock;
flash->flash_is_locked = stm_is_locked;
-#endif
- break;
- default:
- debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
}
+#endif
/* Compute the flash size */
flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
+ flash->page_size = info->page_size;
/*
* The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
* 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
* the 0x4d00 Extended JEDEC code have 512b pages. All of the others
* have 256b pages.
*/
- if (ext_jedec == 0x4d00) {
- if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
- flash->page_size = 256;
- else
+ if (JEDEC_EXT(info) == 0x4d00) {
+ if ((JEDEC_ID(info) != 0x0215) &&
+ (JEDEC_ID(info) != 0x0216))
flash->page_size = 512;
- } else {
- flash->page_size = 256;
}
flash->page_size <<= flash->shift;
- flash->sector_size = params->sector_size << flash->shift;
- flash->size = flash->sector_size * params->nr_sectors << flash->shift;
+ flash->sector_size = info->sector_size << flash->shift;
+ flash->size = flash->sector_size * info->n_sectors << flash->shift;
#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
flash->size <<= 1;
#endif
+#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
/* Compute erase sector and command */
- if (params->flags & SECT_4K) {
+ if (info->flags & SECT_4K) {
flash->erase_cmd = CMD_ERASE_4K;
flash->erase_size = 4096 << flash->shift;
- } else if (params->flags & SECT_32K) {
- flash->erase_cmd = CMD_ERASE_32K;
- flash->erase_size = 32768 << flash->shift;
- } else {
+ } else
+#endif
+ {
flash->erase_cmd = CMD_ERASE_64K;
flash->erase_size = flash->sector_size;
}
@@ -1177,18 +1021,17 @@
/* Now erase size becomes valid sector size */
flash->sector_size = flash->erase_size;
- /* Look for the fastest read cmd */
- cmd = fls(params->e_rd_cmd & spi->mode_rx);
- if (cmd) {
- cmd = spi_read_cmds_array[cmd - 1];
- flash->read_cmd = cmd;
- } else {
- /* Go for default supported read cmd */
- flash->read_cmd = CMD_READ_ARRAY_FAST;
- }
+ /* Look for read commands */
+ flash->read_cmd = CMD_READ_ARRAY_FAST;
+ if (spi->mode & SPI_RX_SLOW)
+ flash->read_cmd = CMD_READ_ARRAY_SLOW;
+ else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
+ flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
+ else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
+ flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
- /* Not require to look for fastest only two write cmds yet */
- if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
+ /* Look for write commands */
+ if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else
/* Go for default supported write cmd */
@@ -1198,9 +1041,10 @@
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- ret = set_quad_mode(flash, idcode[0]);
+ ret = set_quad_mode(flash, info);
if (ret) {
- debug("SF: Fail to set QEB for %02x\n", idcode[0]);
+ debug("SF: Fail to set QEB for %02x\n",
+ JEDEC_MFR(info));
return -EINVAL;
}
}
@@ -1225,18 +1069,18 @@
}
#ifdef CONFIG_SPI_FLASH_STMICRO
- if (params->flags & E_FSR)
+ if (info->flags & E_FSR)
flash->flags |= SNOR_F_USE_FSR;
#endif
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_read_bar(flash, idcode[0]);
+ ret = read_bar(flash, info);
if (ret < 0)
return ret;
#endif
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
ret = spi_flash_decode_fdt(gd->fdt_blob, flash);
if (ret) {
debug("SF: FDT decode error\n");
@@ -1264,5 +1108,5 @@
}
#endif
- return ret;
+ return 0;
}
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
new file mode 100644
index 0000000..edca94e
--- /dev/null
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -0,0 +1,184 @@
+/*
+ * SPI Flash ID's.
+ *
+ * Copyright (C) 2016 Jagan Teki <jagan@openedev.com>
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+#include "sf_internal.h"
+
+/* Used when the "_ext_id" is two bytes at most */
+#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
+ .id = { \
+ ((_jedec_id) >> 16) & 0xff, \
+ ((_jedec_id) >> 8) & 0xff, \
+ (_jedec_id) & 0xff, \
+ ((_ext_id) >> 8) & 0xff, \
+ (_ext_id) & 0xff, \
+ }, \
+ .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
+ .sector_size = (_sector_size), \
+ .n_sectors = (_n_sectors), \
+ .page_size = 256, \
+ .flags = (_flags),
+
+#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
+ .id = { \
+ ((_jedec_id) >> 16) & 0xff, \
+ ((_jedec_id) >> 8) & 0xff, \
+ (_jedec_id) & 0xff, \
+ ((_ext_id) >> 16) & 0xff, \
+ ((_ext_id) >> 8) & 0xff, \
+ (_ext_id) & 0xff, \
+ }, \
+ .id_len = 6, \
+ .sector_size = (_sector_size), \
+ .n_sectors = (_n_sectors), \
+ .page_size = 256, \
+ .flags = (_flags),
+
+const struct spi_flash_info spi_flash_ids[] = {
+#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
+ {"at45db011d", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
+ {"at45db021d", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
+ {"at45db041d", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) },
+ {"at45db081d", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) },
+ {"at45db161d", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) },
+ {"at45db321d", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) },
+ {"at45db641d", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) },
+ {"at25df321a", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) },
+ {"at25df321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) },
+ {"at26df081a", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) },
+#endif
+#ifdef CONFIG_SPI_FLASH_EON /* EON */
+ {"en25q32b", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) },
+ {"en25q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) },
+ {"en25q128b", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) },
+ {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) },
+#endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
+ {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) },
+ {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) },
+#endif
+#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
+ {"is25lp032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) },
+ {"is25lp064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) },
+ {"is25lp128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) },
+#endif
+#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
+ {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) },
+ {"mx25l4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) },
+ {"mx25l8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) },
+ {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) },
+ {"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) },
+ {"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) },
+ {"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) },
+ {"mx25l25635f", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) },
+ {"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) },
+ {"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) },
+ {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) },
+ {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) },
+#endif
+#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
+ {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) },
+ {"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) },
+ {"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) },
+ {"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) },
+ {"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 128, 0) },
+ {"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) },
+ {"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) },
+ {"s25fl128p_64k", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) },
+ {"s25fl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) },
+ {"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) },
+ {"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) },
+ {"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) },
+ {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) },
+ {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) },
+ {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
+ {"s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
+ {"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) },
+ {"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) },
+ {"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) },
+#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
+ {"m25p10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) },
+ {"m25p20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) },
+ {"m25p40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) },
+ {"m25p80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) },
+ {"m25p16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) },
+ {"m25pE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) },
+ {"m25pX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) },
+ {"m25p32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) },
+ {"m25p64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) },
+ {"m25p128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) },
+ {"m25pX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K) },
+ {"n25q016a", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) },
+ {"n25q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) },
+ {"n25q32a", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) },
+ {"n25q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) },
+ {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) },
+ {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) },
+ {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) },
+ {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
+ {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
+ {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+ {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+ {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+ {"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+ {"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+ {"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+#endif
+#ifdef CONFIG_SPI_FLASH_SST /* SST */
+ {"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) },
+ {"sst25vf080b", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) },
+ {"sst25vf016b", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) },
+ {"sst25vf032b", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) },
+ {"sst25vf064c", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) },
+ {"sst25wf512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) },
+ {"sst25wf010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) },
+ {"sst25wf020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) },
+ {"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) },
+ {"sst25wf040b", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) },
+ {"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) },
+#endif
+#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
+ {"w25p80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) },
+ {"w25p16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) },
+ {"w25p32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) },
+ {"w25x40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K) },
+ {"w25x16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K) },
+ {"w25x32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K) },
+ {"w25x64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K) },
+ {"w25q80bl", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q16cl", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q32bv", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q64cv", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q128bv", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q80bw", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q16dw", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q32dw", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q64dw", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) },
+ {"w25q128fw", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) },
+#endif
+ {}, /* Empty entry to terminate the list */
+ /*
+ * Note:
+ * Below paired flash devices has similar spi_flash params.
+ * (s25fl129p_64k, s25fl128s_64k)
+ * (w25q80bl, w25q80bv)
+ * (w25q16cl, w25q16dv)
+ * (w25q32bv, w25q32fv_spi)
+ * (w25q64cv, w25q64fv_spi)
+ * (w25q128bv, w25q128fv_spi)
+ * (w25q32dw, w25q32fv_qpi)
+ * (w25q64dw, w25q64fv_qpi)
+ * (w25q128fw, w25q128fv_qpi)
+ */
+};
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
deleted file mode 100644
index bac1e85..0000000
--- a/drivers/mtd/spi/spi_spl_load.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright (C) 2011 OMICRON electronics GmbH
- *
- * based on drivers/mtd/nand/nand_spl_load.c
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <errno.h>
-#include <spl.h>
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * Load the kernel, check for a valid header we can parse, and if found load
- * the kernel and then device tree.
- */
-static int spi_load_image_os(struct spi_flash *flash,
- struct image_header *header)
-{
- int err;
-
- /* Read for a header, parse or error out. */
- spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40,
- (void *)header);
-
- if (image_get_magic(header) != IH_MAGIC)
- return -1;
-
- err = spl_parse_image_header(header);
- if (err)
- return err;
-
- spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS,
- spl_image.size, (void *)spl_image.load_addr);
-
- /* Read device tree. */
- spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS,
- CONFIG_SYS_SPI_ARGS_SIZE,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR);
-
- return 0;
-}
-#endif
-
-static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
- ulong count, void *buf)
-{
- struct spi_flash *flash = load->dev;
- ulong ret;
-
- ret = spi_flash_read(flash, sector, count, buf);
- if (!ret)
- return count;
- else
- return 0;
-}
-/*
- * The main entry for SPI booting. It's necessary that SDRAM is already
- * configured and available since this code loads the main U-Boot image
- * from SPI into SDRAM and starts it from there.
- */
-int spl_spi_load_image(void)
-{
- int err = 0;
- struct spi_flash *flash;
- struct image_header *header;
-
- /*
- * Load U-Boot image from SPI flash into RAM
- */
-
- flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
- CONFIG_SF_DEFAULT_CS,
- CONFIG_SF_DEFAULT_SPEED,
- CONFIG_SF_DEFAULT_MODE);
- if (!flash) {
- puts("SPI probe failed.\n");
- return -ENODEV;
- }
-
- /* use CONFIG_SYS_TEXT_BASE as temporary storage area */
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
-
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || spi_load_image_os(flash, header))
-#endif
- {
- /* Load u-boot, mkimage header is 64 bytes. */
- err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
- (void *)header);
- if (err)
- return err;
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.dev = flash;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spl_spi_fit_read;
- err = spl_load_simple_fit(&load,
- CONFIG_SYS_SPI_U_BOOT_OFFS,
- header);
- } else {
- err = spl_parse_image_header(header);
- if (err)
- return err;
- err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
- spl_image.size,
- (void *)spl_image.load_addr);
- }
- }
-
- return err;
-}
diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c
index e3ded5b..e70064c 100644
--- a/drivers/mtd/spi/sunxi_spi_spl.c
+++ b/drivers/mtd/spi/sunxi_spi_spl.c
@@ -158,9 +158,10 @@
(1 << AHB_RESET_SPI0_SHIFT));
}
-static int spi0_init(void)
+static void spi0_init(void)
{
unsigned int pin_function = SUNXI_GPC_SPI0;
+
if (IS_ENABLED(CONFIG_MACH_SUN50I))
pin_function = SUN50I_GPC_SPI0;
@@ -262,7 +263,8 @@
/*****************************************************************************/
-int spl_spi_load_image(void)
+static int spl_spi_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
int err;
struct image_header *header;
@@ -271,13 +273,15 @@
spi0_init();
spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
- err = spl_parse_image_header(header);
+ err = spl_parse_image_header(spl_image, header);
if (err)
return err;
- spi0_read_data((void *)spl_image.load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS,
- spl_image.size);
+ spi0_read_data((void *)spl_image->load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS,
+ spl_image->size);
spi0_deinit();
return 0;
}
+/* Use priorty 0 to override the default if it happens to be linked in */
+SPL_LOAD_IMAGE_METHOD("sunxi SPI" 0, BOOT_DEVICE_SPI, spl_spi_load_image);
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
new file mode 100644
index 0000000..0c82395
--- /dev/null
+++ b/drivers/mtd/ubi/Kconfig
@@ -0,0 +1,98 @@
+menu "UBI support"
+
+config MTD_UBI
+ bool "Enable UBI - Unsorted block images"
+ select CRC32
+ help
+ UBI is a software layer above MTD layer which admits of LVM-like
+ logical volumes on top of MTD devices, hides some complexities of
+ flash chips like wear and bad blocks and provides some other useful
+ capabilities. Please, consult the MTD web site for more details
+ (www.linux-mtd.infradead.org).
+
+if MTD_UBI
+
+config MTD_UBI_WL_THRESHOLD
+ int "UBI wear-leveling threshold"
+ default 4096
+ range 2 65536
+ help
+ This parameter defines the maximum difference between the highest
+ erase counter value and the lowest erase counter value of eraseblocks
+ of UBI devices. When this threshold is exceeded, UBI starts performing
+ wear leveling by means of moving data from eraseblock with low erase
+ counter to eraseblocks with high erase counter.
+
+ The default value should be OK for SLC NAND flashes, NOR flashes and
+ other flashes which have eraseblock life-cycle 100000 or more.
+ However, in case of MLC NAND flashes which typically have eraseblock
+ life-cycle less than 10000, the threshold should be lessened (e.g.,
+ to 128 or 256, although it does not have to be power of 2).
+
+config MTD_UBI_BEB_LIMIT
+ int "Maximum expected bad eraseblock count per 1024 eraseblocks"
+ default 20
+ range 0 768
+ help
+ This option specifies the maximum bad physical eraseblocks UBI
+ expects on the MTD device (per 1024 eraseblocks). If the underlying
+ flash does not admit of bad eraseblocks (e.g. NOR flash), this value
+ is ignored.
+
+ NAND datasheets often specify the minimum and maximum NVM (Number of
+ Valid Blocks) for the flashes' endurance lifetime. The maximum
+ expected bad eraseblocks per 1024 eraseblocks then can be calculated
+ as "1024 * (1 - MinNVB / MaxNVB)", which gives 20 for most NANDs
+ (MaxNVB is basically the total count of eraseblocks on the chip).
+
+ To put it differently, if this value is 20, UBI will try to reserve
+ about 1.9% of physical eraseblocks for bad blocks handling. And that
+ will be 1.9% of eraseblocks on the entire NAND chip, not just the MTD
+ partition UBI attaches. This means that if you have, say, a NAND
+ flash chip admits maximum 40 bad eraseblocks, and it is split on two
+ MTD partitions of the same size, UBI will reserve 40 eraseblocks when
+ attaching a partition.
+
+ This option can be overridden by the "mtd=" UBI module parameter or
+ by the "attach" ioctl.
+
+ Leave the default value if unsure.
+
+config MTD_UBI_FASTMAP
+ bool "UBI Fastmap (Experimental feature)"
+ default n
+ help
+ Important: this feature is experimental so far and the on-flash
+ format for fastmap may change in the next kernel versions
+
+ Fastmap is a mechanism which allows attaching an UBI device
+ in nearly constant time. Instead of scanning the whole MTD device it
+ only has to locate a checkpoint (called fastmap) on the device.
+ The on-flash fastmap contains all information needed to attach
+ the device. Using fastmap makes only sense on large devices where
+ attaching by scanning takes long. UBI will not automatically install
+ a fastmap on old images, but you can set the UBI module parameter
+ fm_autoconvert to 1 if you want so. Please note that fastmap-enabled
+ images are still usable with UBI implementations without
+ fastmap support. On typical flash devices the whole fastmap fits
+ into one PEB. UBI will reserve PEBs to hold two fastmaps.
+
+ If in doubt, say "N".
+
+config MTD_UBI_FASTMAP_AUTOCONVERT
+ int "enable UBI Fastmap autoconvert"
+ depends on MTD_UBI_FASTMAP
+ default 0
+ help
+ Set this parameter to enable fastmap automatically on images
+ without a fastmap.
+
+config MTD_UBI_FM_DEBUG
+ int "Enable UBI fastmap debug"
+ depends on MTD_UBI_FASTMAP
+ default 0
+ help
+ Enable UBI fastmap debug
+
+endif # MTD_UBI
+endmenu # "Enable UBI - Unsorted block images"
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index b718481..ca11396 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -899,7 +899,7 @@
* current transfer) have got the time to arrived before
* netloop calls eth_halt
*/
- printf ("About preceeding transfer (eth%d):\n"
+ printf ("About preceding transfer (eth%d):\n"
"- Sent packet number %d\n"
"- Received packet number %d\n"
"- Handled packet number %d\n",
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index be3ed73..929b9e2 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -64,6 +64,17 @@
Please find details on the "Triple-Speed Ethernet MegaCore Function
Resource Center" of Altera.
+config DWC_ETH_QOS
+ bool "Synopsys DWC Ethernet QOS device support"
+ depends on DM_ETH
+ select PHYLIB
+ help
+ This driver supports the Synopsys Designware Ethernet QOS (Quality
+ Of Service) IP block. The IP supports many options for bus type,
+ clocking/reset structure, and feature list. This driver currently
+ supports the specific configuration used in NVIDIA's Tegra186 chip,
+ but should be extensible to other combinations quite easily.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
help
@@ -129,6 +140,13 @@
help
This MAC is present in OpenRISC and Xtensa XTFPGA boards.
+config FEC_MXC
+ bool "FEC Ethernet controller"
+ depends on MX5 || MX6
+ help
+ This driver supports the 10/100 Fast Ethernet controller for
+ NXP i.MX processors.
+
config MVPP2
bool "Marvell Armada 375 network interface support"
depends on ARMADA_375
@@ -175,7 +193,7 @@
This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
config XILINX_EMACLITE
- depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || MIPS)
select PHYLIB
select MII
bool "Xilinx Ethernetlite"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a448526..9a7bfc6 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -76,3 +76,4 @@
obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
+obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
index ba2cb1a..caca8fd 100644
--- a/drivers/net/armada100_fec.c
+++ b/drivers/net/armada100_fec.c
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h
index 5a0a3d9..826048e 100644
--- a/drivers/net/armada100_fec.h
+++ b/drivers/net/armada100_fec.h
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c
index 43a67a5..261fde0 100644
--- a/drivers/net/ax88180.c
+++ b/drivers/net/ax88180.c
@@ -698,11 +698,7 @@
}
}
-/*
-===========================================================================
-<<<<<< Exported SubProgram Bodies >>>>>>
-===========================================================================
-*/
+/* Exported SubProgram Bodies */
int ax88180_initialize (bd_t * bis)
{
struct eth_device *dev;
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 81ccc61..cbce683 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -21,7 +21,7 @@
#include <net.h>
#include <netdev.h>
#include <cpsw.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <phy.h>
@@ -225,6 +225,18 @@
void *hdp, *cp, *rxfree;
};
+/* AM33xx SoC specific definitions for the CONTROL port */
+#define AM33XX_GMII_SEL_MODE_MII 0
+#define AM33XX_GMII_SEL_MODE_RMII 1
+#define AM33XX_GMII_SEL_MODE_RGMII 2
+
+#define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4)
+#define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5)
+#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
+#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
+
+#define GMII_SEL_MODE_MASK 0x3
+
#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
#define desc_read(desc, fld) __raw_readl(&(desc)->fld)
#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
@@ -1150,12 +1162,129 @@
false);
}
+static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
+ phy_interface_t phy_mode)
+{
+ u32 reg;
+ u32 mask;
+ u32 mode = 0;
+ bool rgmii_id = false;
+ int slave = priv->data.active_slave;
+
+ reg = readl(priv->data.gmii_sel);
+
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = AM33XX_GMII_SEL_MODE_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ mode = AM33XX_GMII_SEL_MODE_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ mode = AM33XX_GMII_SEL_MODE_RGMII;
+ rgmii_id = true;
+ break;
+
+ case PHY_INTERFACE_MODE_MII:
+ default:
+ mode = AM33XX_GMII_SEL_MODE_MII;
+ break;
+ };
+
+ mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
+ mode <<= slave * 2;
+
+ if (priv->data.rmii_clock_external) {
+ if (slave == 0)
+ mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
+ else
+ mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
+ }
+
+ if (rgmii_id) {
+ if (slave == 0)
+ mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
+ else
+ mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
+ }
+
+ reg &= ~mask;
+ reg |= mode;
+
+ writel(reg, priv->data.gmii_sel);
+}
+
+static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
+ phy_interface_t phy_mode)
+{
+ u32 reg;
+ u32 mask;
+ u32 mode = 0;
+ int slave = priv->data.active_slave;
+
+ reg = readl(priv->data.gmii_sel);
+
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = AM33XX_GMII_SEL_MODE_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ mode = AM33XX_GMII_SEL_MODE_RGMII;
+ break;
+
+ case PHY_INTERFACE_MODE_MII:
+ default:
+ mode = AM33XX_GMII_SEL_MODE_MII;
+ break;
+ };
+
+ switch (slave) {
+ case 0:
+ mask = GMII_SEL_MODE_MASK;
+ break;
+ case 1:
+ mask = GMII_SEL_MODE_MASK << 4;
+ mode <<= 4;
+ break;
+ default:
+ dev_err(priv->dev, "invalid slave number...\n");
+ return;
+ }
+
+ if (priv->data.rmii_clock_external)
+ dev_err(priv->dev, "RMII External clock is not supported\n");
+
+ reg &= ~mask;
+ reg |= mode;
+
+ writel(reg, priv->data.gmii_sel);
+}
+
+static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
+ phy_interface_t phy_mode)
+{
+ if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
+ cpsw_gmii_sel_am3352(priv, phy_mode);
+ if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
+ cpsw_gmii_sel_am3352(priv, phy_mode);
+ else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
+ cpsw_gmii_sel_dra7xx(priv, phy_mode);
+}
+
static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct cpsw_priv *priv = dev_get_priv(dev);
struct gpio_desc *mode_gpios;
const char *phy_mode;
+ const char *phy_sel_compat = NULL;
const void *fdt = gd->fdt_blob;
int node = dev->of_offset;
int subnode;
@@ -1219,7 +1348,7 @@
active_slave = fdtdec_get_int(fdt, node, "active_slave", 0);
priv->data.active_slave = active_slave;
- fdt_for_each_subnode(fdt, subnode, node) {
+ fdt_for_each_subnode(subnode, fdt, node) {
int len;
const char *name;
@@ -1271,6 +1400,17 @@
error("Not able to get gmii_sel reg address\n");
return -ENOENT;
}
+
+ if (fdt_get_property(fdt, subnode, "rmii-clock-ext",
+ NULL))
+ priv->data.rmii_clock_external = true;
+
+ phy_sel_compat = fdt_getprop(fdt, subnode, "compatible",
+ NULL);
+ if (!phy_sel_compat) {
+ error("Not able to get gmii_sel compatible\n");
+ return -ENOENT;
+ }
}
}
@@ -1293,20 +1433,9 @@
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
- switch (pdata->phy_interface) {
- case PHY_INTERFACE_MODE_MII:
- writel(MII_MODE_ENABLE, priv->data.gmii_sel);
- break;
- case PHY_INTERFACE_MODE_RMII:
- writel(RMII_MODE_ENABLE, priv->data.gmii_sel);
- break;
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- writel(RGMII_MODE_ENABLE, priv->data.gmii_sel);
- break;
- }
+
+ /* Select phy interface in control module */
+ cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface);
return 0;
}
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
new file mode 100644
index 0000000..81eeba2
--- /dev/null
+++ b/drivers/net/dwc_eth_qos.c
@@ -0,0 +1,1552 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Portions based on U-Boot's rtl8169.c.
+ */
+
+/*
+ * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
+ * Service) IP block. The IP supports multiple options for bus type, clocking/
+ * reset structure, and feature list.
+ *
+ * The driver is written such that generic core logic is kept separate from
+ * configuration-specific logic. Code that interacts with configuration-
+ * specific resources is split out into separate functions to avoid polluting
+ * common code. If/when this driver is enhanced to support multiple
+ * configurations, the core code should be adapted to call all configuration-
+ * specific functions through function pointers, with the definition of those
+ * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
+ * field.
+ *
+ * The following configurations are currently supported:
+ * tegra186:
+ * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
+ * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
+ * supports a single RGMII PHY. This configuration also has SW control over
+ * all clock and reset signals to the HW block.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <memalign.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <phy.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+/* Core registers */
+
+#define EQOS_MAC_REGS_BASE 0x000
+struct eqos_mac_regs {
+ uint32_t configuration; /* 0x000 */
+ uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
+ uint32_t q0_tx_flow_ctrl; /* 0x070 */
+ uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
+ uint32_t rx_flow_ctrl; /* 0x090 */
+ uint32_t unused_094; /* 0x094 */
+ uint32_t txq_prty_map0; /* 0x098 */
+ uint32_t unused_09c; /* 0x09c */
+ uint32_t rxq_ctrl0; /* 0x0a0 */
+ uint32_t unused_0a4; /* 0x0a4 */
+ uint32_t rxq_ctrl2; /* 0x0a8 */
+ uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
+ uint32_t us_tic_counter; /* 0x0dc */
+ uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
+ uint32_t hw_feature0; /* 0x11c */
+ uint32_t hw_feature1; /* 0x120 */
+ uint32_t hw_feature2; /* 0x124 */
+ uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
+ uint32_t mdio_address; /* 0x200 */
+ uint32_t mdio_data; /* 0x204 */
+ uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
+ uint32_t address0_high; /* 0x300 */
+ uint32_t address0_low; /* 0x304 */
+};
+
+#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
+#define EQOS_MAC_CONFIGURATION_CST BIT(21)
+#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
+#define EQOS_MAC_CONFIGURATION_WD BIT(19)
+#define EQOS_MAC_CONFIGURATION_JD BIT(17)
+#define EQOS_MAC_CONFIGURATION_JE BIT(16)
+#define EQOS_MAC_CONFIGURATION_PS BIT(15)
+#define EQOS_MAC_CONFIGURATION_FES BIT(14)
+#define EQOS_MAC_CONFIGURATION_DM BIT(13)
+#define EQOS_MAC_CONFIGURATION_TE BIT(1)
+#define EQOS_MAC_CONFIGURATION_RE BIT(0)
+
+#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
+#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
+#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
+
+#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
+
+#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
+#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
+
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
+
+#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
+#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
+
+#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
+#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
+#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
+#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
+
+#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
+#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
+#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
+#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
+#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
+#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
+#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
+#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
+#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
+#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
+
+#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
+
+#define EQOS_MTL_REGS_BASE 0xd00
+struct eqos_mtl_regs {
+ uint32_t txq0_operation_mode; /* 0xd00 */
+ uint32_t unused_d04; /* 0xd04 */
+ uint32_t txq0_debug; /* 0xd08 */
+ uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
+ uint32_t txq0_quantum_weight; /* 0xd18 */
+ uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
+ uint32_t rxq0_operation_mode; /* 0xd30 */
+ uint32_t unused_d34; /* 0xd34 */
+ uint32_t rxq0_debug; /* 0xd38 */
+};
+
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
+#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
+
+#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
+#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
+#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
+
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
+#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
+
+#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
+#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
+#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
+#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
+
+#define EQOS_DMA_REGS_BASE 0x1000
+struct eqos_dma_regs {
+ uint32_t mode; /* 0x1000 */
+ uint32_t sysbus_mode; /* 0x1004 */
+ uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
+ uint32_t ch0_control; /* 0x1100 */
+ uint32_t ch0_tx_control; /* 0x1104 */
+ uint32_t ch0_rx_control; /* 0x1108 */
+ uint32_t unused_110c; /* 0x110c */
+ uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
+ uint32_t ch0_txdesc_list_address; /* 0x1114 */
+ uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
+ uint32_t ch0_rxdesc_list_address; /* 0x111c */
+ uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
+ uint32_t unused_1124; /* 0x1124 */
+ uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
+ uint32_t ch0_txdesc_ring_length; /* 0x112c */
+ uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
+};
+
+#define EQOS_DMA_MODE_SWR BIT(0)
+
+#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
+#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
+#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
+#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
+#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
+#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
+
+#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
+
+#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
+#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
+#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
+#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
+
+#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
+#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
+#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
+#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
+#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
+
+/* These registers are Tegra186-specific */
+#define EQOS_TEGRA186_REGS_BASE 0x8800
+struct eqos_tegra186_regs {
+ uint32_t sdmemcomppadctrl; /* 0x8800 */
+ uint32_t auto_cal_config; /* 0x8804 */
+ uint32_t unused_8808; /* 0x8808 */
+ uint32_t auto_cal_status; /* 0x880c */
+};
+
+#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
+
+#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
+#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
+
+#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
+
+/* Descriptors */
+
+#define EQOS_DESCRIPTOR_WORDS 4
+#define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
+/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
+#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
+#define EQOS_DESCRIPTORS_TX 4
+#define EQOS_DESCRIPTORS_RX 4
+#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
+#define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
+ EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
+#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
+#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
+#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
+
+/*
+ * Warn if the cache-line size is larger than the descriptor size. In such
+ * cases the driver will likely fail because the CPU needs to flush the cache
+ * when requeuing RX buffers, therefore descriptors written by the hardware
+ * may be discarded. Architectures with full IO coherence, such as x86, do not
+ * experience this issue, and hence are excluded from this condition.
+ *
+ * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
+ * the driver to allocate descriptors from a pool of non-cached memory.
+ */
+#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
+#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
+ !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+#warning Cache line size is larger than descriptor size
+#endif
+#endif
+
+struct eqos_desc {
+ u32 des0;
+ u32 des1;
+ u32 des2;
+ u32 des3;
+};
+
+#define EQOS_DESC3_OWN BIT(31)
+#define EQOS_DESC3_FD BIT(29)
+#define EQOS_DESC3_LD BIT(28)
+#define EQOS_DESC3_BUF1V BIT(24)
+
+struct eqos_config {
+ bool reg_access_always_ok;
+};
+
+struct eqos_priv {
+ struct udevice *dev;
+ const struct eqos_config *config;
+ fdt_addr_t regs;
+ struct eqos_mac_regs *mac_regs;
+ struct eqos_mtl_regs *mtl_regs;
+ struct eqos_dma_regs *dma_regs;
+ struct eqos_tegra186_regs *tegra186_regs;
+ struct reset_ctl reset_ctl;
+ struct gpio_desc phy_reset_gpio;
+ struct clk clk_master_bus;
+ struct clk clk_rx;
+ struct clk clk_ptp_ref;
+ struct clk clk_tx;
+ struct clk clk_slave_bus;
+ struct mii_dev *mii;
+ struct phy_device *phy;
+ void *descs;
+ struct eqos_desc *tx_descs;
+ struct eqos_desc *rx_descs;
+ int tx_desc_idx, rx_desc_idx;
+ void *tx_dma_buf;
+ void *rx_dma_buf;
+ void *rx_pkt;
+ bool started;
+ bool reg_access_ok;
+};
+
+/*
+ * TX and RX descriptors are 16 bytes. This causes problems with the cache
+ * maintenance on CPUs where the cache-line size exceeds the size of these
+ * descriptors. What will happen is that when the driver receives a packet
+ * it will be immediately requeued for the hardware to reuse. The CPU will
+ * therefore need to flush the cache-line containing the descriptor, which
+ * will cause all other descriptors in the same cache-line to be flushed
+ * along with it. If one of those descriptors had been written to by the
+ * device those changes (and the associated packet) will be lost.
+ *
+ * To work around this, we make use of non-cached memory if available. If
+ * descriptors are mapped uncached there's no need to manually flush them
+ * or invalidate them.
+ *
+ * Note that this only applies to descriptors. The packet data buffers do
+ * not have the same constraints since they are 1536 bytes large, so they
+ * are unlikely to share cache-lines.
+ */
+static void *eqos_alloc_descs(unsigned int num)
+{
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+ return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
+ EQOS_DESCRIPTOR_ALIGN);
+#else
+ return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
+#endif
+}
+
+static void eqos_free_descs(void *descs)
+{
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+ /* FIXME: noncached_alloc() has no opposite */
+#else
+ free(descs);
+#endif
+}
+
+static void eqos_inval_desc(void *desc)
+{
+#ifndef CONFIG_SYS_NONCACHED_MEMORY
+ unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
+ ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+#endif
+}
+
+static void eqos_flush_desc(void *desc)
+{
+#ifndef CONFIG_SYS_NONCACHED_MEMORY
+ flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
+#endif
+}
+
+static void eqos_inval_buffer(void *buf, size_t size)
+{
+ unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+}
+
+static void eqos_flush_buffer(void *buf, size_t size)
+{
+ flush_cache((unsigned long)buf, size);
+}
+
+static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
+{
+ return wait_for_bit(__func__, &eqos->mac_regs->mdio_address,
+ EQOS_MAC_MDIO_ADDRESS_GB, false, 1000000, true);
+}
+
+static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
+ int mdio_reg)
+{
+ struct eqos_priv *eqos = bus->priv;
+ u32 val;
+ int ret;
+
+ debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
+ mdio_reg);
+
+ ret = eqos_mdio_wait_idle(eqos);
+ if (ret) {
+ error("MDIO not idle at entry");
+ return ret;
+ }
+
+ val = readl(&eqos->mac_regs->mdio_address);
+ val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
+ EQOS_MAC_MDIO_ADDRESS_C45E;
+ val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
+ (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
+ (EQOS_MAC_MDIO_ADDRESS_CR_20_35 <<
+ EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
+ (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
+ EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
+ EQOS_MAC_MDIO_ADDRESS_GB;
+ writel(val, &eqos->mac_regs->mdio_address);
+
+ udelay(10);
+
+ ret = eqos_mdio_wait_idle(eqos);
+ if (ret) {
+ error("MDIO read didn't complete");
+ return ret;
+ }
+
+ val = readl(&eqos->mac_regs->mdio_data);
+ val &= EQOS_MAC_MDIO_DATA_GD_MASK;
+
+ debug("%s: val=%x\n", __func__, val);
+
+ return val;
+}
+
+static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
+ int mdio_reg, u16 mdio_val)
+{
+ struct eqos_priv *eqos = bus->priv;
+ u32 val;
+ int ret;
+
+ debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
+ mdio_addr, mdio_reg, mdio_val);
+
+ ret = eqos_mdio_wait_idle(eqos);
+ if (ret) {
+ error("MDIO not idle at entry");
+ return ret;
+ }
+
+ writel(mdio_val, &eqos->mac_regs->mdio_data);
+
+ val = readl(&eqos->mac_regs->mdio_address);
+ val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
+ EQOS_MAC_MDIO_ADDRESS_C45E;
+ val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
+ (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
+ (EQOS_MAC_MDIO_ADDRESS_CR_20_35 <<
+ EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
+ (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
+ EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
+ EQOS_MAC_MDIO_ADDRESS_GB;
+ writel(val, &eqos->mac_regs->mdio_address);
+
+ udelay(10);
+
+ ret = eqos_mdio_wait_idle(eqos);
+ if (ret) {
+ error("MDIO read didn't complete");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int eqos_start_clks_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ ret = clk_enable(&eqos->clk_slave_bus);
+ if (ret < 0) {
+ error("clk_enable(clk_slave_bus) failed: %d", ret);
+ goto err;
+ }
+
+ ret = clk_enable(&eqos->clk_master_bus);
+ if (ret < 0) {
+ error("clk_enable(clk_master_bus) failed: %d", ret);
+ goto err_disable_clk_slave_bus;
+ }
+
+ ret = clk_enable(&eqos->clk_rx);
+ if (ret < 0) {
+ error("clk_enable(clk_rx) failed: %d", ret);
+ goto err_disable_clk_master_bus;
+ }
+
+ ret = clk_enable(&eqos->clk_ptp_ref);
+ if (ret < 0) {
+ error("clk_enable(clk_ptp_ref) failed: %d", ret);
+ goto err_disable_clk_rx;
+ }
+
+ ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
+ if (ret < 0) {
+ error("clk_set_rate(clk_ptp_ref) failed: %d", ret);
+ goto err_disable_clk_ptp_ref;
+ }
+
+ ret = clk_enable(&eqos->clk_tx);
+ if (ret < 0) {
+ error("clk_enable(clk_tx) failed: %d", ret);
+ goto err_disable_clk_ptp_ref;
+ }
+
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_disable_clk_ptp_ref:
+ clk_disable(&eqos->clk_ptp_ref);
+err_disable_clk_rx:
+ clk_disable(&eqos->clk_rx);
+err_disable_clk_master_bus:
+ clk_disable(&eqos->clk_master_bus);
+err_disable_clk_slave_bus:
+ clk_disable(&eqos->clk_slave_bus);
+err:
+ debug("%s: FAILED: %d\n", __func__, ret);
+ return ret;
+}
+
+void eqos_stop_clks_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clk_disable(&eqos->clk_tx);
+ clk_disable(&eqos->clk_ptp_ref);
+ clk_disable(&eqos->clk_rx);
+ clk_disable(&eqos->clk_master_bus);
+ clk_disable(&eqos->clk_slave_bus);
+
+ debug("%s: OK\n", __func__);
+}
+
+static int eqos_start_resets_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
+ if (ret < 0) {
+ error("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
+ return ret;
+ }
+
+ udelay(2);
+
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0) {
+ error("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
+ return ret;
+ }
+
+ ret = reset_assert(&eqos->reset_ctl);
+ if (ret < 0) {
+ error("reset_assert() failed: %d", ret);
+ return ret;
+ }
+
+ udelay(2);
+
+ ret = reset_deassert(&eqos->reset_ctl);
+ if (ret < 0) {
+ error("reset_deassert() failed: %d", ret);
+ return ret;
+ }
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static int eqos_stop_resets_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ reset_assert(&eqos->reset_ctl);
+ dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
+
+ return 0;
+}
+
+static int eqos_calibrate_pads_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
+ EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
+
+ udelay(1);
+
+ setbits_le32(&eqos->tegra186_regs->auto_cal_config,
+ EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
+
+ ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status,
+ EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
+ if (ret) {
+ error("calibrate didn't start");
+ goto failed;
+ }
+
+ ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status,
+ EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
+ if (ret) {
+ error("calibrate didn't finish");
+ goto failed;
+ }
+
+ ret = 0;
+
+failed:
+ clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
+ EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
+
+ debug("%s: returns %d\n", __func__, ret);
+
+ return ret;
+}
+
+static int eqos_disable_calibration_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
+ EQOS_AUTO_CAL_CONFIG_ENABLE);
+
+ return 0;
+}
+
+static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ return clk_get_rate(&eqos->clk_slave_bus);
+}
+
+static int eqos_set_full_duplex(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
+
+ return 0;
+}
+
+static int eqos_set_half_duplex(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
+
+ /* WAR: Flush TX queue when switching to half-duplex */
+ setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
+ EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
+
+ return 0;
+}
+
+static int eqos_set_gmii_speed(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clrbits_le32(&eqos->mac_regs->configuration,
+ EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
+
+ return 0;
+}
+
+static int eqos_set_mii_speed_100(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ setbits_le32(&eqos->mac_regs->configuration,
+ EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
+
+ return 0;
+}
+
+static int eqos_set_mii_speed_10(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clrsetbits_le32(&eqos->mac_regs->configuration,
+ EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
+
+ return 0;
+}
+
+static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ ulong rate;
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ switch (eqos->phy->speed) {
+ case SPEED_1000:
+ rate = 125 * 1000 * 1000;
+ break;
+ case SPEED_100:
+ rate = 25 * 1000 * 1000;
+ break;
+ case SPEED_10:
+ rate = 2.5 * 1000 * 1000;
+ break;
+ default:
+ error("invalid speed %d", eqos->phy->speed);
+ return -EINVAL;
+ }
+
+ ret = clk_set_rate(&eqos->clk_tx, rate);
+ if (ret < 0) {
+ error("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int eqos_adjust_link(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+ bool en_calibration;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ if (eqos->phy->duplex)
+ ret = eqos_set_full_duplex(dev);
+ else
+ ret = eqos_set_half_duplex(dev);
+ if (ret < 0) {
+ error("eqos_set_*_duplex() failed: %d", ret);
+ return ret;
+ }
+
+ switch (eqos->phy->speed) {
+ case SPEED_1000:
+ en_calibration = true;
+ ret = eqos_set_gmii_speed(dev);
+ break;
+ case SPEED_100:
+ en_calibration = true;
+ ret = eqos_set_mii_speed_100(dev);
+ break;
+ case SPEED_10:
+ en_calibration = false;
+ ret = eqos_set_mii_speed_10(dev);
+ break;
+ default:
+ error("invalid speed %d", eqos->phy->speed);
+ return -EINVAL;
+ }
+ if (ret < 0) {
+ error("eqos_set_*mii_speed*() failed: %d", ret);
+ return ret;
+ }
+
+ if (en_calibration) {
+ ret = eqos_calibrate_pads_tegra186(dev);
+ if (ret < 0) {
+ error("eqos_calibrate_pads_tegra186() failed: %d", ret);
+ return ret;
+ }
+ } else {
+ ret = eqos_disable_calibration_tegra186(dev);
+ if (ret < 0) {
+ error("eqos_disable_calibration_tegra186() failed: %d",
+ ret);
+ return ret;
+ }
+ }
+
+ ret = eqos_set_tx_clk_speed_tegra186(dev);
+ if (ret < 0) {
+ error("eqos_set_tx_clk_speed_tegra186() failed: %d", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int eqos_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ uint32_t val;
+
+ /*
+ * This function may be called before start() or after stop(). At that
+ * time, on at least some configurations of the EQoS HW, all clocks to
+ * the EQoS HW block will be stopped, and a reset signal applied. If
+ * any register access is attempted in this state, bus timeouts or CPU
+ * hangs may occur. This check prevents that.
+ *
+ * A simple solution to this problem would be to not implement
+ * write_hwaddr(), since start() always writes the MAC address into HW
+ * anyway. However, it is desirable to implement write_hwaddr() to
+ * support the case of SW that runs subsequent to U-Boot which expects
+ * the MAC address to already be programmed into the EQoS registers,
+ * which must happen irrespective of whether the U-Boot user (or
+ * scripts) actually made use of the EQoS device, and hence
+ * irrespective of whether start() was ever called.
+ *
+ * Note that this requirement by subsequent SW is not valid for
+ * Tegra186, and is likely not valid for any non-PCI instantiation of
+ * the EQoS HW block. This function is implemented solely as
+ * future-proofing with the expectation the driver will eventually be
+ * ported to some system where the expectation above is true.
+ */
+ if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
+ return 0;
+
+ /* Update the MAC address */
+ val = (plat->enetaddr[5] << 8) |
+ (plat->enetaddr[4]);
+ writel(val, &eqos->mac_regs->address0_high);
+ val = (plat->enetaddr[3] << 24) |
+ (plat->enetaddr[2] << 16) |
+ (plat->enetaddr[1] << 8) |
+ (plat->enetaddr[0]);
+ writel(val, &eqos->mac_regs->address0_low);
+
+ return 0;
+}
+
+static int eqos_start(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret, i;
+ ulong rate;
+ u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
+ ulong last_rx_desc;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ eqos->tx_desc_idx = 0;
+ eqos->rx_desc_idx = 0;
+
+ ret = eqos_start_clks_tegra186(dev);
+ if (ret < 0) {
+ error("eqos_start_clks_tegra186() failed: %d", ret);
+ goto err;
+ }
+
+ ret = eqos_start_resets_tegra186(dev);
+ if (ret < 0) {
+ error("eqos_start_resets_tegra186() failed: %d", ret);
+ goto err_stop_clks;
+ }
+
+ udelay(10);
+
+ eqos->reg_access_ok = true;
+
+ ret = wait_for_bit(__func__, &eqos->dma_regs->mode,
+ EQOS_DMA_MODE_SWR, false, 10, false);
+ if (ret) {
+ error("EQOS_DMA_MODE_SWR stuck");
+ goto err_stop_resets;
+ }
+
+ ret = eqos_calibrate_pads_tegra186(dev);
+ if (ret < 0) {
+ error("eqos_calibrate_pads_tegra186() failed: %d", ret);
+ goto err_stop_resets;
+ }
+
+ rate = eqos_get_tick_clk_rate_tegra186(dev);
+ val = (rate / 1000000) - 1;
+ writel(val, &eqos->mac_regs->us_tic_counter);
+
+ eqos->phy = phy_connect(eqos->mii, 0, dev, 0);
+ if (!eqos->phy) {
+ error("phy_connect() failed");
+ goto err_stop_resets;
+ }
+ ret = phy_config(eqos->phy);
+ if (ret < 0) {
+ error("phy_config() failed: %d", ret);
+ goto err_shutdown_phy;
+ }
+ ret = phy_startup(eqos->phy);
+ if (ret < 0) {
+ error("phy_startup() failed: %d", ret);
+ goto err_shutdown_phy;
+ }
+
+ if (!eqos->phy->link) {
+ error("No link");
+ goto err_shutdown_phy;
+ }
+
+ ret = eqos_adjust_link(dev);
+ if (ret < 0) {
+ error("eqos_adjust_link() failed: %d", ret);
+ goto err_shutdown_phy;
+ }
+
+ /* Configure MTL */
+
+ /* Enable Store and Forward mode for TX */
+ /* Program Tx operating mode */
+ setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
+ EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
+ (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
+ EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
+
+ /* Transmit Queue weight */
+ writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
+
+ /* Enable Store and Forward mode for RX, since no jumbo frame */
+ setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
+ EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
+
+ /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
+ val = readl(&eqos->mac_regs->hw_feature1);
+ tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
+ EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
+ rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
+ EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
+
+ /*
+ * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
+ * r/tqs is encoded as (n / 256) - 1.
+ */
+ tqs = (128 << tx_fifo_sz) / 256 - 1;
+ rqs = (128 << rx_fifo_sz) / 256 - 1;
+
+ clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
+ EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
+ EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
+ tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
+ clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
+ EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
+ rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
+
+ /* Flow control used only if each channel gets 4KB or more FIFO */
+ if (rqs >= ((4096 / 256) - 1)) {
+ u32 rfd, rfa;
+
+ setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
+ EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
+
+ /*
+ * Set Threshold for Activating Flow Contol space for min 2
+ * frames ie, (1500 * 1) = 1500 bytes.
+ *
+ * Set Threshold for Deactivating Flow Contol for space of
+ * min 1 frame (frame size 1500bytes) in receive fifo
+ */
+ if (rqs == ((4096 / 256) - 1)) {
+ /*
+ * This violates the above formula because of FIFO size
+ * limit therefore overflow may occur inspite of this.
+ */
+ rfd = 0x3; /* Full-3K */
+ rfa = 0x1; /* Full-1.5K */
+ } else if (rqs == ((8192 / 256) - 1)) {
+ rfd = 0x6; /* Full-4K */
+ rfa = 0xa; /* Full-6K */
+ } else if (rqs == ((16384 / 256) - 1)) {
+ rfd = 0x6; /* Full-4K */
+ rfa = 0x12; /* Full-10K */
+ } else {
+ rfd = 0x6; /* Full-4K */
+ rfa = 0x1E; /* Full-16K */
+ }
+
+ clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
+ (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
+ (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
+ (rfd <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
+ (rfa <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
+ }
+
+ /* Configure MAC */
+
+ clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
+ EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
+ EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
+ EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB <<
+ EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
+
+ /* Set TX flow control parameters */
+ /* Set Pause Time */
+ setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
+ 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
+ /* Assign priority for TX flow control */
+ clrbits_le32(&eqos->mac_regs->txq_prty_map0,
+ EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
+ EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
+ /* Assign priority for RX flow control */
+ clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
+ EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
+ EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
+ /* Enable flow control */
+ setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
+ EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
+ setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
+ EQOS_MAC_RX_FLOW_CTRL_RFE);
+
+ clrsetbits_le32(&eqos->mac_regs->configuration,
+ EQOS_MAC_CONFIGURATION_GPSLCE |
+ EQOS_MAC_CONFIGURATION_WD |
+ EQOS_MAC_CONFIGURATION_JD |
+ EQOS_MAC_CONFIGURATION_JE,
+ EQOS_MAC_CONFIGURATION_CST |
+ EQOS_MAC_CONFIGURATION_ACS);
+
+ eqos_write_hwaddr(dev);
+
+ /* Configure DMA */
+
+ /* Enable OSP mode */
+ setbits_le32(&eqos->dma_regs->ch0_tx_control,
+ EQOS_DMA_CH0_TX_CONTROL_OSP);
+
+ /* RX buffer size. Must be a multiple of bus width */
+ clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
+ EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
+ EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
+ EQOS_MAX_PACKET_SIZE <<
+ EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
+
+ setbits_le32(&eqos->dma_regs->ch0_control,
+ EQOS_DMA_CH0_CONTROL_PBLX8);
+
+ /*
+ * Burst length must be < 1/2 FIFO size.
+ * FIFO size in tqs is encoded as (n / 256) - 1.
+ * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
+ * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
+ */
+ pbl = tqs + 1;
+ if (pbl > 32)
+ pbl = 32;
+ clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
+ EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
+ EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
+ pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
+
+ clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
+ EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
+ EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
+ 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
+
+ /* DMA performance configuration */
+ val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
+ EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
+ EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
+ writel(val, &eqos->dma_regs->sysbus_mode);
+
+ /* Set up descriptors */
+
+ memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
+ for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
+ struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
+ rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
+ (i * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+ }
+ flush_cache((unsigned long)eqos->descs, EQOS_DESCRIPTORS_SIZE);
+
+ writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
+ writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
+ writel(EQOS_DESCRIPTORS_TX - 1,
+ &eqos->dma_regs->ch0_txdesc_ring_length);
+
+ writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
+ writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
+ writel(EQOS_DESCRIPTORS_RX - 1,
+ &eqos->dma_regs->ch0_rxdesc_ring_length);
+
+ /* Enable everything */
+
+ setbits_le32(&eqos->mac_regs->configuration,
+ EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
+
+ setbits_le32(&eqos->dma_regs->ch0_tx_control,
+ EQOS_DMA_CH0_TX_CONTROL_ST);
+ setbits_le32(&eqos->dma_regs->ch0_rx_control,
+ EQOS_DMA_CH0_RX_CONTROL_SR);
+
+ /* TX tail pointer not written until we need to TX a packet */
+ /*
+ * Point RX tail pointer at last descriptor. Ideally, we'd point at the
+ * first descriptor, implying all descriptors were available. However,
+ * that's not distinguishable from none of the descriptors being
+ * available.
+ */
+ last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
+ writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
+
+ eqos->started = true;
+
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_shutdown_phy:
+ phy_shutdown(eqos->phy);
+ eqos->phy = NULL;
+err_stop_resets:
+ eqos_stop_resets_tegra186(dev);
+err_stop_clks:
+ eqos_stop_clks_tegra186(dev);
+err:
+ error("FAILED: %d", ret);
+ return ret;
+}
+
+void eqos_stop(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int i;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ if (!eqos->started)
+ return;
+ eqos->started = false;
+ eqos->reg_access_ok = false;
+
+ /* Disable TX DMA */
+ clrbits_le32(&eqos->dma_regs->ch0_tx_control,
+ EQOS_DMA_CH0_TX_CONTROL_ST);
+
+ /* Wait for TX all packets to drain out of MTL */
+ for (i = 0; i < 1000000; i++) {
+ u32 val = readl(&eqos->mtl_regs->txq0_debug);
+ u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
+ EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
+ u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
+ if ((trcsts != 1) && (!txqsts))
+ break;
+ }
+
+ /* Turn off MAC TX and RX */
+ clrbits_le32(&eqos->mac_regs->configuration,
+ EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
+
+ /* Wait for all RX packets to drain out of MTL */
+ for (i = 0; i < 1000000; i++) {
+ u32 val = readl(&eqos->mtl_regs->rxq0_debug);
+ u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
+ EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
+ u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
+ EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
+ if ((!prxq) && (!rxqsts))
+ break;
+ }
+
+ /* Turn off RX DMA */
+ clrbits_le32(&eqos->dma_regs->ch0_rx_control,
+ EQOS_DMA_CH0_RX_CONTROL_SR);
+
+ if (eqos->phy) {
+ phy_shutdown(eqos->phy);
+ eqos->phy = NULL;
+ }
+ eqos_stop_resets_tegra186(dev);
+ eqos_stop_clks_tegra186(dev);
+
+ debug("%s: OK\n", __func__);
+}
+
+int eqos_send(struct udevice *dev, void *packet, int length)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eqos_desc *tx_desc;
+ int i;
+
+ debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
+ length);
+
+ memcpy(eqos->tx_dma_buf, packet, length);
+ eqos_flush_buffer(eqos->tx_dma_buf, length);
+
+ tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
+ eqos->tx_desc_idx++;
+ eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
+
+ tx_desc->des0 = (ulong)eqos->tx_dma_buf;
+ tx_desc->des1 = 0;
+ tx_desc->des2 = length;
+ /*
+ * Make sure that if HW sees the _OWN write below, it will see all the
+ * writes to the rest of the descriptor too.
+ */
+ mb();
+ tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
+ eqos_flush_desc(tx_desc);
+
+ writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
+
+ for (i = 0; i < 1000000; i++) {
+ eqos_inval_desc(tx_desc);
+ if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
+ return 0;
+ udelay(1);
+ }
+
+ debug("%s: TX timeout\n", __func__);
+
+ return -ETIMEDOUT;
+}
+
+int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eqos_desc *rx_desc;
+ int length;
+
+ debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
+
+ rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
+ if (rx_desc->des3 & EQOS_DESC3_OWN) {
+ debug("%s: RX packet not available\n", __func__);
+ return -EAGAIN;
+ }
+
+ *packetp = eqos->rx_dma_buf +
+ (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
+ length = rx_desc->des3 & 0x7fff;
+ debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
+
+ eqos_inval_buffer(*packetp, length);
+
+ return length;
+}
+
+int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ uchar *packet_expected;
+ struct eqos_desc *rx_desc;
+
+ debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
+
+ packet_expected = eqos->rx_dma_buf +
+ (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
+ if (packet != packet_expected) {
+ debug("%s: Unexpected packet (expected %p)\n", __func__,
+ packet_expected);
+ return -EINVAL;
+ }
+
+ rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
+ rx_desc->des0 = (u32)(ulong)packet;
+ rx_desc->des1 = 0;
+ rx_desc->des2 = 0;
+ /*
+ * Make sure that if HW sees the _OWN write below, it will see all the
+ * writes to the rest of the descriptor too.
+ */
+ mb();
+ rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+ eqos_flush_desc(rx_desc);
+
+ writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
+
+ eqos->rx_desc_idx++;
+ eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
+
+ return 0;
+}
+
+static int eqos_probe_resources_core(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
+ EQOS_DESCRIPTORS_RX);
+ if (!eqos->descs) {
+ debug("%s: eqos_alloc_descs() failed\n", __func__);
+ ret = -ENOMEM;
+ goto err;
+ }
+ eqos->tx_descs = (struct eqos_desc *)eqos->descs;
+ eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
+ debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
+ eqos->rx_descs);
+
+ eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
+ if (!eqos->tx_dma_buf) {
+ debug("%s: memalign(tx_dma_buf) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_descs;
+ }
+ debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
+
+ eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
+ if (!eqos->rx_dma_buf) {
+ debug("%s: memalign(rx_dma_buf) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_tx_dma_buf;
+ }
+ debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
+
+ eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
+ if (!eqos->rx_pkt) {
+ debug("%s: malloc(rx_pkt) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_rx_dma_buf;
+ }
+ debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_free_rx_dma_buf:
+ free(eqos->rx_dma_buf);
+err_free_tx_dma_buf:
+ free(eqos->tx_dma_buf);
+err_free_descs:
+ eqos_free_descs(eqos->descs);
+err:
+
+ debug("%s: returns %d\n", __func__, ret);
+ return ret;
+}
+
+static int eqos_remove_resources_core(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ free(eqos->rx_pkt);
+ free(eqos->rx_dma_buf);
+ free(eqos->tx_dma_buf);
+ eqos_free_descs(eqos->descs);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static int eqos_probe_resources_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
+ if (ret) {
+ error("reset_get_by_name(rst) failed: %d", ret);
+ return ret;
+ }
+
+ ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
+ &eqos->phy_reset_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret) {
+ error("gpio_request_by_name(phy reset) failed: %d", ret);
+ goto err_free_reset_eqos;
+ }
+
+ ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
+ if (ret) {
+ error("clk_get_by_name(slave_bus) failed: %d", ret);
+ goto err_free_gpio_phy_reset;
+ }
+
+ ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
+ if (ret) {
+ error("clk_get_by_name(master_bus) failed: %d", ret);
+ goto err_free_clk_slave_bus;
+ }
+
+ ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
+ if (ret) {
+ error("clk_get_by_name(rx) failed: %d", ret);
+ goto err_free_clk_master_bus;
+ }
+
+ ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
+ if (ret) {
+ error("clk_get_by_name(ptp_ref) failed: %d", ret);
+ goto err_free_clk_rx;
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
+ if (ret) {
+ error("clk_get_by_name(tx) failed: %d", ret);
+ goto err_free_clk_ptp_ref;
+ }
+
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_free_clk_ptp_ref:
+ clk_free(&eqos->clk_ptp_ref);
+err_free_clk_rx:
+ clk_free(&eqos->clk_rx);
+err_free_clk_master_bus:
+ clk_free(&eqos->clk_master_bus);
+err_free_clk_slave_bus:
+ clk_free(&eqos->clk_slave_bus);
+err_free_gpio_phy_reset:
+ dm_gpio_free(dev, &eqos->phy_reset_gpio);
+err_free_reset_eqos:
+ reset_free(&eqos->reset_ctl);
+
+ debug("%s: returns %d\n", __func__, ret);
+ return ret;
+}
+
+static int eqos_remove_resources_tegra186(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clk_free(&eqos->clk_tx);
+ clk_free(&eqos->clk_ptp_ref);
+ clk_free(&eqos->clk_rx);
+ clk_free(&eqos->clk_slave_bus);
+ clk_free(&eqos->clk_master_bus);
+ dm_gpio_free(dev, &eqos->phy_reset_gpio);
+ reset_free(&eqos->reset_ctl);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static int eqos_probe(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ eqos->dev = dev;
+ eqos->config = (void *)dev_get_driver_data(dev);
+
+ eqos->regs = dev_get_addr(dev);
+ if (eqos->regs == FDT_ADDR_T_NONE) {
+ error("dev_get_addr() failed");
+ return -ENODEV;
+ }
+ eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
+ eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
+ eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
+ eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
+
+ ret = eqos_probe_resources_core(dev);
+ if (ret < 0) {
+ error("eqos_probe_resources_core() failed: %d", ret);
+ return ret;
+ }
+
+ ret = eqos_probe_resources_tegra186(dev);
+ if (ret < 0) {
+ error("eqos_probe_resources_tegra186() failed: %d", ret);
+ goto err_remove_resources_core;
+ }
+
+ eqos->mii = mdio_alloc();
+ if (!eqos->mii) {
+ error("mdio_alloc() failed");
+ goto err_remove_resources_tegra;
+ }
+ eqos->mii->read = eqos_mdio_read;
+ eqos->mii->write = eqos_mdio_write;
+ eqos->mii->priv = eqos;
+ strcpy(eqos->mii->name, dev->name);
+
+ ret = mdio_register(eqos->mii);
+ if (ret < 0) {
+ error("mdio_register() failed: %d", ret);
+ goto err_free_mdio;
+ }
+
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_free_mdio:
+ mdio_free(eqos->mii);
+err_remove_resources_tegra:
+ eqos_remove_resources_tegra186(dev);
+err_remove_resources_core:
+ eqos_remove_resources_core(dev);
+
+ debug("%s: returns %d\n", __func__, ret);
+ return ret;
+}
+
+static int eqos_remove(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ mdio_unregister(eqos->mii);
+ mdio_free(eqos->mii);
+ eqos_remove_resources_tegra186(dev);
+ eqos_probe_resources_core(dev);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static const struct eth_ops eqos_ops = {
+ .start = eqos_start,
+ .stop = eqos_stop,
+ .send = eqos_send,
+ .recv = eqos_recv,
+ .free_pkt = eqos_free_pkt,
+ .write_hwaddr = eqos_write_hwaddr,
+};
+
+static const struct eqos_config eqos_tegra186_config = {
+ .reg_access_always_ok = false,
+};
+
+static const struct udevice_id eqos_ids[] = {
+ {
+ .compatible = "nvidia,tegra186-eqos",
+ .data = (ulong)&eqos_tegra186_config
+ },
+ { }
+};
+
+U_BOOT_DRIVER(eth_eqos) = {
+ .name = "eth_eqos",
+ .id = UCLASS_ETH,
+ .of_match = eqos_ids,
+ .probe = eqos_probe,
+ .remove = eqos_remove,
+ .ops = &eqos_ops,
+ .priv_auto_alloc_size = sizeof(struct eqos_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 3332ad9..875682b 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -1522,11 +1522,10 @@
reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
- /* IGB is cool */
- if (hw->mac_type == e1000_igb)
- return;
switch (hw->mac_type) {
+ case e1000_igb: /* IGB is cool */
+ return;
case e1000_82571:
case e1000_82572:
/* Clear PHY TX compatible mode bits */
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index e871b3e..3304fddc 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -9,19 +9,21 @@
*/
#include <common.h>
+#include <dm.h>
#include <malloc.h>
#include <memalign.h>
+#include <miiphy.h>
#include <net.h>
#include <netdev.h>
-#include <miiphy.h>
#include "fec_mxc.h"
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <linux/compiler.h>
+
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/sys_proto.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -79,11 +81,9 @@
}
#endif
-/*
- * MII-interface related functions
- */
-static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
- uint8_t regAddr)
+/* MII-interface related functions */
+static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
+ uint8_t regaddr)
{
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
@@ -95,15 +95,13 @@
* programming the FEC's MII data register.
*/
writel(FEC_IEVENT_MII, ð->ievent);
- reg = regAddr << FEC_MII_DATA_RA_SHIFT;
- phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
+ reg = regaddr << FEC_MII_DATA_RA_SHIFT;
+ phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
phy | reg, ð->mii_data);
- /*
- * wait for the related interrupt
- */
+ /* wait for the related interrupt */
start = get_timer(0);
while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
@@ -112,17 +110,13 @@
}
}
- /*
- * clear mii interrupt bit
- */
+ /* clear mii interrupt bit */
writel(FEC_IEVENT_MII, ð->ievent);
- /*
- * it's now safe to read the PHY's register
- */
+ /* it's now safe to read the PHY's register */
val = (unsigned short)readl(ð->mii_data);
- debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
- regAddr, val);
+ debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
+ regaddr, val);
return val;
}
@@ -153,22 +147,20 @@
debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
}
-static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
- uint8_t regAddr, uint16_t data)
+static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
+ uint8_t regaddr, uint16_t data)
{
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
uint32_t start;
- reg = regAddr << FEC_MII_DATA_RA_SHIFT;
- phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
+ reg = regaddr << FEC_MII_DATA_RA_SHIFT;
+ phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
- /*
- * wait for the MII interrupt
- */
+ /* wait for the MII interrupt */
start = get_timer(0);
while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
@@ -177,26 +169,24 @@
}
}
- /*
- * clear MII interrupt bit
- */
+ /* clear MII interrupt bit */
writel(FEC_IEVENT_MII, ð->ievent);
- debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
- regAddr, data);
+ debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
+ regaddr, data);
return 0;
}
-static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
- int regAddr)
+static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
+ int regaddr)
{
- return fec_mdio_read(bus->priv, phyAddr, regAddr);
+ return fec_mdio_read(bus->priv, phyaddr, regaddr);
}
-static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
- int regAddr, u16 data)
+static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
+ int regaddr, u16 data)
{
- return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
+ return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
}
#ifndef CONFIG_PHYLIB
@@ -217,14 +207,12 @@
fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
udelay(1000);
- /*
- * Set the auto-negotiation advertisement register bits
- */
+ /* Set the auto-negotiation advertisement register bits */
fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
- LPA_100FULL | LPA_100HALF | LPA_10FULL |
- LPA_10HALF | PHY_ANLPAR_PSB_802_3);
+ LPA_100FULL | LPA_100HALF | LPA_10FULL |
+ LPA_10HALF | PHY_ANLPAR_PSB_802_3);
fec_mdio_write(eth, fec->phy_id, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
+ BMCR_ANENABLE | BMCR_ANRESTART);
if (fec->mii_postcall)
ret = fec->mii_postcall(fec->phy_id);
@@ -241,9 +229,7 @@
struct fec_priv *fec = (struct fec_priv *)dev->priv;
struct ethernet_regs *eth = fec->bus->priv;
- /*
- * Wait for AN completion
- */
+ /* Wait for AN completion */
start = get_timer(0);
do {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
@@ -254,7 +240,7 @@
status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
if (status < 0) {
printf("%s: Autonegotiation failed. status: %d\n",
- dev->name, status);
+ dev->name, status);
return -1;
}
} while (!(status & BMSR_LSTATUS));
@@ -351,65 +337,63 @@
/**
* Mark the given read buffer descriptor as free
* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
- * @param[in] pRbd buffer descriptor to mark free again
+ * @param[in] prbd buffer descriptor to mark free again
*/
-static void fec_rbd_clean(int last, struct fec_bd *pRbd)
+static void fec_rbd_clean(int last, struct fec_bd *prbd)
{
unsigned short flags = FEC_RBD_EMPTY;
if (last)
flags |= FEC_RBD_WRAP;
- writew(flags, &pRbd->status);
- writew(0, &pRbd->data_length);
+ writew(flags, &prbd->status);
+ writew(0, &prbd->data_length);
}
-static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
- unsigned char *mac)
+static int fec_get_hwaddr(int dev_id, unsigned char *mac)
{
imx_get_mac_from_fuse(dev_id, mac);
return !is_valid_ethaddr(mac);
}
+#ifdef CONFIG_DM_ETH
+static int fecmxc_set_hwaddr(struct udevice *dev)
+#else
static int fec_set_hwaddr(struct eth_device *dev)
+#endif
{
+#ifdef CONFIG_DM_ETH
+ struct fec_priv *fec = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ uchar *mac = pdata->enetaddr;
+#else
uchar *mac = dev->enetaddr;
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+#endif
writel(0, &fec->eth->iaddr1);
writel(0, &fec->eth->iaddr2);
writel(0, &fec->eth->gaddr1);
writel(0, &fec->eth->gaddr2);
- /*
- * Set physical address
- */
+ /* Set physical address */
writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
- &fec->eth->paddr1);
+ &fec->eth->paddr1);
writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
return 0;
}
-/*
- * Do initial configuration of the FEC registers
- */
+/* Do initial configuration of the FEC registers */
static void fec_reg_setup(struct fec_priv *fec)
{
uint32_t rcntrl;
- /*
- * Set interrupt mask register
- */
+ /* Set interrupt mask register */
writel(0x00000000, &fec->eth->imask);
- /*
- * Clear FEC-Lite interrupt event register(IEVENT)
- */
+ /* Clear FEC-Lite interrupt event register(IEVENT) */
writel(0xffffffff, &fec->eth->ievent);
-
- /*
- * Set FEC-Lite receive control register(R_CNTRL):
- */
+ /* Set FEC-Lite receive control register(R_CNTRL): */
/* Start with frame length = 1518, common for all modes. */
rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
@@ -427,9 +411,17 @@
* Start the FEC engine
* @param[in] dev Our device to handle
*/
+#ifdef CONFIG_DM_ETH
+static int fec_open(struct udevice *dev)
+#else
static int fec_open(struct eth_device *edev)
+#endif
{
+#ifdef CONFIG_DM_ETH
+ struct fec_priv *fec = dev_get_priv(dev);
+#else
struct fec_priv *fec = (struct fec_priv *)edev->priv;
+#endif
int speed;
uint32_t addr, size;
int i;
@@ -453,22 +445,19 @@
#ifdef FEC_QUIRK_ENET_MAC
/* Enable ENET HW endian SWAP */
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
- &fec->eth->ecntrl);
+ &fec->eth->ecntrl);
/* Enable ENET store and forward mode */
writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
- &fec->eth->x_wmrk);
+ &fec->eth->x_wmrk);
#endif
- /*
- * Enable FEC-Lite controller
- */
+ /* Enable FEC-Lite controller */
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
- &fec->eth->ecntrl);
+ &fec->eth->ecntrl);
+
#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
udelay(100);
- /*
- * setup the MII gasket for RMII mode
- */
+ /* setup the MII gasket for RMII mode */
/* disable the gasket */
writew(0, &fec->eth->miigsk_enr);
@@ -526,27 +515,35 @@
#endif
debug("%s:Speed=%i\n", __func__, speed);
- /*
- * Enable SmartDMA receive task
- */
+ /* Enable SmartDMA receive task */
fec_rx_task_enable(fec);
udelay(100000);
return 0;
}
-static int fec_init(struct eth_device *dev, bd_t* bd)
+#ifdef CONFIG_DM_ETH
+static int fecmxc_init(struct udevice *dev)
+#else
+static int fec_init(struct eth_device *dev, bd_t *bd)
+#endif
{
+#ifdef CONFIG_DM_ETH
+ struct fec_priv *fec = dev_get_priv(dev);
+#else
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+#endif
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
int i;
/* Initialize MAC address */
+#ifdef CONFIG_DM_ETH
+ fecmxc_set_hwaddr(dev);
+#else
fec_set_hwaddr(dev);
+#endif
- /*
- * Setup transmit descriptors, there are two in total.
- */
+ /* Setup transmit descriptors, there are two in total. */
fec_tbd_init(fec);
/* Setup receive descriptors. */
@@ -557,18 +554,14 @@
if (fec->xcv_type != SEVENWIRE)
fec_mii_setspeed(fec->bus->priv);
- /*
- * Set Opcode/Pause Duration Register
- */
+ /* Set Opcode/Pause Duration Register */
writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
writel(0x2, &fec->eth->x_wmrk);
- /*
- * Set multicast address filter
- */
+
+ /* Set multicast address filter */
writel(0x00000000, &fec->eth->gaddr1);
writel(0x00000000, &fec->eth->gaddr2);
-
/* Do not access reserved register for i.MX6UL */
if (!is_mx6ul()) {
/* clear MIB RAM */
@@ -596,27 +589,29 @@
* Halt the FEC engine
* @param[in] dev Our device to handle
*/
+#ifdef CONFIG_DM_ETH
+static void fecmxc_halt(struct udevice *dev)
+#else
static void fec_halt(struct eth_device *dev)
+#endif
{
+#ifdef CONFIG_DM_ETH
+ struct fec_priv *fec = dev_get_priv(dev);
+#else
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+#endif
int counter = 0xffff;
- /*
- * issue graceful stop command to the FEC transmitter if necessary
- */
+ /* issue graceful stop command to the FEC transmitter if necessary */
writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
- &fec->eth->x_cntrl);
+ &fec->eth->x_cntrl);
debug("eth_halt: wait for stop regs\n");
- /*
- * wait for graceful stop to register
- */
+ /* wait for graceful stop to register */
while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
udelay(1);
- /*
- * Disable SmartDMA tasks
- */
+ /* Disable SmartDMA tasks */
fec_tx_task_disable(fec);
fec_rx_task_disable(fec);
@@ -625,7 +620,7 @@
* Note: this will also reset the BD index counter!
*/
writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
- &fec->eth->ecntrl);
+ &fec->eth->ecntrl);
fec->rbd_index = 0;
fec->tbd_index = 0;
debug("eth_halt: done\n");
@@ -638,7 +633,11 @@
* @param[in] length Data count in bytes
* @return 0 on success
*/
+#ifdef CONFIG_DM_ETH
+static int fecmxc_send(struct udevice *dev, void *packet, int length)
+#else
static int fec_send(struct eth_device *dev, void *packet, int length)
+#endif
{
unsigned int status;
uint32_t size, end;
@@ -650,7 +649,11 @@
* This routine transmits one frame. This routine only accepts
* 6-byte Ethernet addresses.
*/
+#ifdef CONFIG_DM_ETH
+ struct fec_priv *fec = dev_get_priv(dev);
+#else
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+#endif
/*
* Check for valid length of data.
@@ -720,9 +723,7 @@
*/
readl(addr + size - 4);
- /*
- * Enable SmartDMA transmit task
- */
+ /* Enable SmartDMA transmit task */
fec_tx_task_enable(fec);
/*
@@ -767,8 +768,8 @@
out:
debug("fec_send: status 0x%x index %d ret %i\n",
- readw(&fec->tbd_base[fec->tbd_index].status),
- fec->tbd_index, ret);
+ readw(&fec->tbd_base[fec->tbd_index].status),
+ fec->tbd_index, ret);
/* for next transmission use the other buffer */
if (fec->tbd_index)
fec->tbd_index = 0;
@@ -783,9 +784,17 @@
* @param[in] dev Our ethernet device to handle
* @return Length of packet read
*/
+#ifdef CONFIG_DM_ETH
+static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
+#else
static int fec_recv(struct eth_device *dev)
+#endif
{
+#ifdef CONFIG_DM_ETH
+ struct fec_priv *fec = dev_get_priv(dev);
+#else
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+#endif
struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
unsigned long ievent;
int frame_length, len = 0;
@@ -794,30 +803,41 @@
int i;
ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
- /*
- * Check if any critical events have happened
- */
+ /* Check if any critical events have happened */
ievent = readl(&fec->eth->ievent);
writel(ievent, &fec->eth->ievent);
debug("fec_recv: ievent 0x%lx\n", ievent);
if (ievent & FEC_IEVENT_BABR) {
+#ifdef CONFIG_DM_ETH
+ fecmxc_halt(dev);
+ fecmxc_init(dev);
+#else
fec_halt(dev);
fec_init(dev, fec->bd);
+#endif
printf("some error: 0x%08lx\n", ievent);
return 0;
}
if (ievent & FEC_IEVENT_HBERR) {
/* Heartbeat error */
writel(0x00000001 | readl(&fec->eth->x_cntrl),
- &fec->eth->x_cntrl);
+ &fec->eth->x_cntrl);
}
if (ievent & FEC_IEVENT_GRA) {
/* Graceful stop complete */
if (readl(&fec->eth->x_cntrl) & 0x00000001) {
+#ifdef CONFIG_DM_ETH
+ fecmxc_halt(dev);
+#else
fec_halt(dev);
+#endif
writel(~0x00000001 & readl(&fec->eth->x_cntrl),
- &fec->eth->x_cntrl);
+ &fec->eth->x_cntrl);
+#ifdef CONFIG_DM_ETH
+ fecmxc_init(dev);
+#else
fec_init(dev, fec->bd);
+#endif
}
}
@@ -844,22 +864,16 @@
if (!(bd_status & FEC_RBD_EMPTY)) {
if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
- ((readw(&rbd->data_length) - 4) > 14)) {
- /*
- * Get buffer address and size
- */
+ ((readw(&rbd->data_length) - 4) > 14)) {
+ /* Get buffer address and size */
addr = readl(&rbd->data_pointer);
frame_length = readw(&rbd->data_length) - 4;
- /*
- * Invalidate data cache over the buffer
- */
+ /* Invalidate data cache over the buffer */
end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
addr &= ~(ARCH_DMA_MINALIGN - 1);
invalidate_dcache_range(addr, end);
- /*
- * Fill the buffer and pass it to upper layers
- */
+ /* Fill the buffer and pass it to upper layers */
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)addr, frame_length);
#endif
@@ -887,7 +901,7 @@
&fec->rbd_base[i]);
}
flush_dcache_range(addr,
- addr + ARCH_DMA_MINALIGN);
+ addr + ARCH_DMA_MINALIGN);
}
fec_rx_task_enable(fec);
@@ -971,6 +985,33 @@
free(fec->tbd_base);
}
+struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
+{
+ struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
+ struct mii_dev *bus;
+ int ret;
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("mdio_alloc failed\n");
+ return NULL;
+ }
+ bus->read = fec_phy_read;
+ bus->write = fec_phy_write;
+ bus->priv = eth;
+ fec_set_dev_name(bus->name, dev_id);
+
+ ret = mdio_register(bus);
+ if (ret) {
+ printf("mdio_register failed\n");
+ free(bus);
+ return NULL;
+ }
+ fec_mii_setspeed(eth);
+ return bus;
+}
+
+#ifndef CONFIG_DM_ETH
#ifdef CONFIG_PHYLIB
int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, struct phy_device *phydev)
@@ -1024,7 +1065,7 @@
start = get_timer(0);
while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
- printf("FEC MXC: Timeout reseting chip\n");
+ printf("FEC MXC: Timeout resetting chip\n");
goto err4;
}
udelay(10);
@@ -1045,7 +1086,7 @@
#endif
eth_register(edev);
- if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
+ if (fec_get_hwaddr(dev_id, ethaddr) == 0) {
debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
if (!getenv("ethaddr"))
@@ -1062,32 +1103,6 @@
return ret;
}
-struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
-{
- struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
- struct mii_dev *bus;
- int ret;
-
- bus = mdio_alloc();
- if (!bus) {
- printf("mdio_alloc failed\n");
- return NULL;
- }
- bus->read = fec_phy_read;
- bus->write = fec_phy_write;
- bus->priv = eth;
- fec_set_dev_name(bus->name, dev_id);
-
- ret = mdio_register(bus);
- if (ret) {
- printf("mdio_register failed\n");
- free(bus);
- return NULL;
- }
- fec_mii_setspeed(eth);
- return bus;
-}
-
int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
{
uint32_t base_mii;
@@ -1147,3 +1162,151 @@
return 0;
}
#endif
+
+#else
+
+static int fecmxc_read_rom_hwaddr(struct udevice *dev)
+{
+ struct fec_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
+}
+
+static const struct eth_ops fecmxc_ops = {
+ .start = fecmxc_init,
+ .send = fecmxc_send,
+ .recv = fecmxc_recv,
+ .stop = fecmxc_halt,
+ .write_hwaddr = fecmxc_set_hwaddr,
+ .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
+};
+
+static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
+{
+ struct phy_device *phydev;
+ int mask = 0xffffffff;
+
+#ifdef CONFIG_PHYLIB
+ mask = 1 << CONFIG_FEC_MXC_PHYADDR;
+#endif
+
+ phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+ if (!phydev)
+ return -ENODEV;
+
+ phy_connect_dev(phydev, dev);
+
+ priv->phydev = phydev;
+ phy_config(phydev);
+
+ return 0;
+}
+
+static int fecmxc_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct fec_priv *priv = dev_get_priv(dev);
+ struct mii_dev *bus = NULL;
+ int dev_id = -1;
+ uint32_t start;
+ int ret;
+
+ ret = fec_alloc_descs(priv);
+ if (ret)
+ return ret;
+
+ bus = fec_get_miibus((uint32_t)priv->eth, dev_id);
+ if (!bus)
+ goto err_mii;
+
+ priv->bus = bus;
+ priv->xcv_type = CONFIG_FEC_XCV_TYPE;
+ priv->interface = pdata->phy_interface;
+ ret = fec_phy_init(priv, dev);
+ if (ret)
+ goto err_phy;
+
+ /* Reset chip. */
+ writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
+ &priv->eth->ecntrl);
+ start = get_timer(0);
+ while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
+ if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
+ printf("FEC MXC: Timeout reseting chip\n");
+ goto err_timeout;
+ }
+ udelay(10);
+ }
+
+ fec_reg_setup(priv);
+ fec_set_dev_name((char *)dev->name, dev_id);
+ priv->dev_id = (dev_id == -1) ? 0 : dev_id;
+
+ return 0;
+
+err_timeout:
+ free(priv->phydev);
+err_phy:
+ mdio_unregister(bus);
+ free(bus);
+err_mii:
+ fec_free_descs(priv);
+ return ret;
+}
+
+static int fecmxc_remove(struct udevice *dev)
+{
+ struct fec_priv *priv = dev_get_priv(dev);
+
+ free(priv->phydev);
+ fec_free_descs(priv);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+
+ return 0;
+}
+
+static int fecmxc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct fec_priv *priv = dev_get_priv(dev);
+ const char *phy_mode;
+
+ pdata->iobase = (phys_addr_t)dev_get_addr(dev);
+ priv->eth = (struct ethernet_regs *)pdata->iobase;
+
+ pdata->phy_interface = -1;
+ phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ /* TODO
+ * Need to get the reset-gpio and related properties from DT
+ * and implemet the enet reset code on .probe call
+ */
+
+ return 0;
+}
+
+static const struct udevice_id fecmxc_ids[] = {
+ { .compatible = "fsl,imx6q-fec" },
+ { }
+};
+
+U_BOOT_DRIVER(fecmxc_gem) = {
+ .name = "fecmxc",
+ .id = UCLASS_ETH,
+ .of_match = fecmxc_ids,
+ .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
+ .probe = fecmxc_probe,
+ .remove = fecmxc_remove,
+ .ops = &fecmxc_ops,
+ .priv_auto_alloc_size = sizeof(struct fec_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+#endif
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 0717cc6..43a7d7b 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -14,21 +14,14 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-
#ifndef __FEC_MXC_H
#define __FEC_MXC_H
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-
-/**
- * Layout description of the FEC
- */
+/* Layout description of the FEC */
struct ethernet_regs {
+ /* [10:2]addr = 00 */
-/* [10:2]addr = 00 */
-
-/* Control and status Registers (offset 000-1FF) */
-
+ /* Control and status Registers (offset 000-1FF) */
uint32_t res0[1]; /* MBAR_ETH + 0x000 */
uint32_t ievent; /* MBAR_ETH + 0x004 */
uint32_t imask; /* MBAR_ETH + 0x008 */
@@ -71,8 +64,7 @@
uint32_t emrbr; /* MBAR_ETH + 0x188 */
uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */
-/* MIB COUNTERS (Offset 200-2FF) */
-
+ /* MIB COUNTERS (Offset 200-2FF) */
uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */
uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */
uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
@@ -174,7 +166,6 @@
#define FEC_IMASKT_RL 0x00100000
#define FEC_IMASK_UN 0x00080000
-
#define FEC_RCNTRL_MAX_FL_SHIFT 16
#define FEC_RCNTRL_LOOP 0x00000001
#define FEC_RCNTRL_DRT 0x00000002
@@ -233,9 +224,7 @@
uint32_t data_pointer; /* payload's buffer address */
};
-/**
- * Supported phy types on this platform
- */
+/* Supported phy types on this platform */
enum xceiver_type {
SEVENWIRE, /* 7-wire */
MII10, /* MII 10Mbps */
@@ -244,9 +233,7 @@
RGMII, /* RGMII */
};
-/**
- * @brief i.MX27-FEC private structure
- */
+/* @brief i.MX27-FEC private structure */
struct fec_priv {
struct ethernet_regs *eth; /* pointer to register'S base */
enum xceiver_type xcv_type; /* transceiver type */
@@ -264,8 +251,14 @@
int phy_id;
int (*mii_postcall)(int);
#endif
+
+#ifdef CONFIG_DM_ETH
+ u32 interface;
+#endif
};
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
/**
* @brief Numbers of buffer descriptors for receiving
*
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 344fbe2..fa96bad 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -17,26 +17,22 @@
obj-$(CONFIG_SYS_FMAN_V3) += memac.o
# SoC specific SERDES support
-obj-$(CONFIG_P1017) += p1023.o
-obj-$(CONFIG_P1023) += p1023.o
+obj-$(CONFIG_ARCH_P1023) += p1023.o
# The P204x, P304x, and P5020 are the same
-obj-$(CONFIG_PPC_P2041) += p5020.o
-obj-$(CONFIG_PPC_P3041) += p5020.o
-obj-$(CONFIG_PPC_P4080) += p4080.o
-obj-$(CONFIG_PPC_P5020) += p5020.o
-obj-$(CONFIG_PPC_P5040) += p5040.o
-obj-$(CONFIG_PPC_T1040) += t1040.o
-obj-$(CONFIG_PPC_T1042) += t1040.o
-obj-$(CONFIG_PPC_T1020) += t1040.o
-obj-$(CONFIG_PPC_T1022) += t1040.o
-obj-$(CONFIG_PPC_T1023) += t1024.o
-obj-$(CONFIG_PPC_T1024) += t1024.o
-obj-$(CONFIG_PPC_T2080) += t2080.o
-obj-$(CONFIG_PPC_T2081) += t2080.o
-obj-$(CONFIG_PPC_T4240) += t4240.o
-obj-$(CONFIG_PPC_T4160) += t4240.o
-obj-$(CONFIG_PPC_T4080) += t4240.o
-obj-$(CONFIG_PPC_B4420) += b4860.o
-obj-$(CONFIG_PPC_B4860) += b4860.o
+obj-$(CONFIG_ARCH_P2041) += p5020.o
+obj-$(CONFIG_ARCH_P3041) += p5020.o
+obj-$(CONFIG_ARCH_P4080) += p4080.o
+obj-$(CONFIG_ARCH_P5020) += p5020.o
+obj-$(CONFIG_ARCH_P5040) += p5040.o
+obj-$(CONFIG_ARCH_T1040) += t1040.o
+obj-$(CONFIG_ARCH_T1042) += t1040.o
+obj-$(CONFIG_ARCH_T1023) += t1024.o
+obj-$(CONFIG_ARCH_T1024) += t1024.o
+obj-$(CONFIG_ARCH_T2080) += t2080.o
+obj-$(CONFIG_ARCH_T2081) += t2080.o
+obj-$(CONFIG_ARCH_T4240) += t4240.o
+obj-$(CONFIG_ARCH_T4160) += t4240.o
+obj-$(CONFIG_ARCH_B4420) += b4860.o
+obj-$(CONFIG_ARCH_B4860) += b4860.o
obj-$(CONFIG_LS1043A) += ls1043.o
-obj-$(CONFIG_LS1046A) += ls1046.o
+obj-$(CONFIG_ARCH_LS1046A) += ls1046.o
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index eb058c9..5aeeb87 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -47,7 +47,7 @@
phy_interface_t fman_port_enet_if(enum fm_port port)
{
-#if defined(CONFIG_B4860QDS)
+#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
u32 serdes2_prtcl;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
@@ -60,7 +60,8 @@
/*B4860 has two 10Gig Mac*/
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
- #if !defined(CONFIG_B4860QDS)
+ #if (!defined(CONFIG_TARGET_B4860QDS) && \
+ !defined(CONFIG_TARGET_B4R420QDS))
(is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10)) ||
#endif
@@ -68,7 +69,7 @@
))
return PHY_INTERFACE_MODE_XGMII;
-#if defined(CONFIG_B4860QDS)
+#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index eb8e936..bf5f89b 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -45,9 +45,12 @@
qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
- value = PHY_SGMII_IF_MODE_SGMII;
- if (!sgmii_2500)
- value |= PHY_SGMII_IF_MODE_AN;
+ if (sgmii_2500)
+ value = PHY_SGMII_CR_PHY_RESET |
+ PHY_SGMII_IF_SPEED_GIGABIT |
+ PHY_SGMII_IF_MODE_SGMII;
+ else
+ value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
@@ -55,15 +58,24 @@
value = PHY_SGMII_DEV_ABILITY_SGMII;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
- /* Adjust link timer for SGMII -
- 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
- memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3);
- memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
+ if (sgmii_2500) {
+ /* Adjust link timer for 2.5G SGMII,
+ * 1.6 ms in units of 3.2 ns:
+ * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
+ */
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
+ } else {
+ /* Adjust link timer for SGMII,
+ * 1.6 ms in units of 8 ns:
+ * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
+ */
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
+ }
/* Restart AN */
- value = PHY_SGMII_CR_DEF_VAL;
- if (!sgmii_2500)
- value |= PHY_SGMII_CR_RESET_AN;
+ value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
@@ -391,6 +403,7 @@
/* For some reason we need to set SPEED_100 */
if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
+ (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
(fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 5eb773e..89f0d6a 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "fm.h"
#include <fsl_qe.h> /* For struct qe_firmware */
@@ -368,8 +368,18 @@
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
+#ifdef CONFIG_DM_SPI_FLASH
+ struct udevice *new;
+
+ /* speed and mode will be read from DT */
+ ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ 0, 0, &new);
+
+ ucode_flash = dev_get_uclass_priv(new);
+#else
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+#endif
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index fa9bc9f..64cc971 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -88,7 +88,7 @@
#define PRAM_MODE_GLOBAL 0x20000000
#define PRAM_MODE_GRACEFUL_STOP 0x00800000
-#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#if defined(CONFIG_ARCH_P1023)
#define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */
#else
#define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 81a64bf..1b5779c 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -90,6 +90,7 @@
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);
diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.c b/drivers/net/fsl-mc/dpio/qbman_portal.c
index 4b64c8a..86dc13d 100644
--- a/drivers/net/fsl-mc/dpio/qbman_portal.c
+++ b/drivers/net/fsl-mc/dpio/qbman_portal.c
@@ -25,7 +25,7 @@
#define QBMAN_CENA_SWP_VDQCR 0x780
/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
-#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0xff) >> 6)
+#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6)
/*******************************/
/* Pre-defined attribute codes */
@@ -65,6 +65,7 @@
{
int ret;
struct qbman_swp *p = malloc(sizeof(struct qbman_swp));
+ u32 major = 0, minor = 0;
if (!p)
return NULL;
@@ -80,8 +81,20 @@
atomic_set(&p->vdq.busy, 1);
p->vdq.valid_bit = QB_VALID_BIT;
p->dqrr.next_idx = 0;
+
+ qbman_version(&major, &minor);
+ if (!major) {
+ printf("invalid qbman version\n");
+ return NULL;
+ }
+
+ if (major >= 4 && minor >= 1)
+ p->dqrr.dqrr_size = QBMAN_VER_4_1_DQRR_SIZE;
+ else
+ p->dqrr.dqrr_size = QBMAN_VER_4_0_DQRR_SIZE;
+
p->dqrr.valid_bit = QB_VALID_BIT;
- ret = qbman_swp_sys_init(&p->sys, d);
+ ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size);
if (ret) {
free(p);
printf("qbman_swp_sys_init() failed %d\n", ret);
@@ -380,7 +393,7 @@
/* There's something there. Move "next_idx" attention to the next ring
* entry (and prefetch it) before returning what we found. */
s->dqrr.next_idx++;
- s->dqrr.next_idx &= QBMAN_DQRR_SIZE - 1; /* Wrap around at 4 */
+ s->dqrr.next_idx &= s->dqrr.dqrr_size - 1;/* Wrap around at dqrr_size */
/* TODO: it's possible to do all this without conditionals, optimise it
* later. */
if (!s->dqrr.next_idx)
diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.h b/drivers/net/fsl-mc/dpio/qbman_portal.h
index 86e2c3a..97a47aa 100644
--- a/drivers/net/fsl-mc/dpio/qbman_portal.h
+++ b/drivers/net/fsl-mc/dpio/qbman_portal.h
@@ -14,8 +14,8 @@
/* Management command result codes */
#define QBMAN_MC_RSLT_OK 0xf0
-/* TBD: as of QBMan 4.1, DQRR will be 8 rather than 4! */
-#define QBMAN_DQRR_SIZE 4
+#define QBMAN_VER_4_0_DQRR_SIZE 4
+#define QBMAN_VER_4_1_DQRR_SIZE 8
/* --------------------- */
@@ -71,6 +71,7 @@
struct {
uint32_t next_idx;
uint32_t valid_bit;
+ uint8_t dqrr_size;
} dqrr;
};
diff --git a/drivers/net/fsl-mc/dpio/qbman_private.h b/drivers/net/fsl-mc/dpio/qbman_private.h
index f1f16b8..73bbae3 100644
--- a/drivers/net/fsl-mc/dpio/qbman_private.h
+++ b/drivers/net/fsl-mc/dpio/qbman_private.h
@@ -11,6 +11,7 @@
#include <linux/types.h>
#include <asm/atomic.h>
#include <malloc.h>
+#include <asm/arch/soc.h>
#include <fsl-mc/fsl_qbman_base.h>
#define QBMAN_CHECKING
@@ -166,4 +167,22 @@
#define lwsync()
+void qbman_version(u32 *major, u32 *minor)
+{
+ u32 svr_dev_id;
+
+ /*
+ * LS2080A SoC and its personalities has qbman cotroller version 4.0
+ * New SoCs like LS2088A, LS1088A has qbman conroller version 4.1
+ */
+ svr_dev_id = get_svr() >> 16;
+ if (svr_dev_id == SVR_DEV_LS2080A) {
+ *major = 4;
+ *minor = 0;
+ } else {
+ *major = 4;
+ *minor = 1;
+ }
+}
+
#include "qbman_sys.h"
diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h
index 7a537fb..72d74c5 100644
--- a/drivers/net/fsl-mc/dpio/qbman_sys.h
+++ b/drivers/net/fsl-mc/dpio/qbman_sys.h
@@ -239,16 +239,18 @@
{
uint32_t reg;
- reg = e32_uint8_t(20, 3, max_fill) | e32_uint8_t(16, 3, est) |
- e32_uint8_t(12, 2, rpm) | e32_uint8_t(10, 2, dcm) |
- e32_uint8_t(8, 2, epm) | e32_int(5, 1, sd) |
- e32_int(4, 1, sp) | e32_int(3, 1, se) | e32_int(2, 1, dp) |
- e32_int(1, 1, de) | e32_int(0, 1, ep) | e32_uint8_t(14, 1, wn);
+ reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) |
+ e32_uint8_t(16, 3, est) | e32_uint8_t(12, 2, rpm) |
+ e32_uint8_t(10, 2, dcm) | e32_uint8_t(8, 2, epm) |
+ e32_int(5, 1, sd) | e32_int(4, 1, sp) | e32_int(3, 1, se) |
+ e32_int(2, 1, dp) | e32_int(1, 1, de) | e32_int(0, 1, ep) |
+ e32_uint8_t(14, 1, wn);
return reg;
}
static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
- const struct qbman_swp_desc *d)
+ const struct qbman_swp_desc *d,
+ uint8_t dqrr_size)
{
uint32_t reg;
@@ -270,9 +272,9 @@
BUG_ON(reg);
#endif
#ifdef QBMAN_CINH_ONLY
- reg = qbman_set_swp_cfg(4, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
+ reg = qbman_set_swp_cfg(dqrr_size, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
#else
- reg = qbman_set_swp_cfg(4, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
+ reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
#endif
qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 1811b0f..46b8a6b 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -40,6 +40,7 @@
struct fsl_dpbp_obj *dflt_dpbp = NULL;
struct fsl_dpio_obj *dflt_dpio = NULL;
struct fsl_dpni_obj *dflt_dpni = NULL;
+static u64 mc_lazy_dpl_addr;
#ifdef DEBUG
void dump_ram_words(const char *title, void *addr)
@@ -572,6 +573,9 @@
u64 mc_ram_addr = mc_get_dram_addr();
size_t mc_ram_size = mc_get_dram_block_size();
+ if (!mc_dpl_addr)
+ return -1;
+
error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr);
if (error != 0)
return error;
@@ -1156,6 +1160,11 @@
{
int err = 0;
+ if (bd && mc_lazy_dpl_addr && !fsl_mc_ldpaa_exit(NULL)) {
+ mc_apply_dpl(mc_lazy_dpl_addr);
+ mc_lazy_dpl_addr = 0;
+ }
+
/* MC is not loaded intentionally, So return success. */
if (bd && get_mc_boot_status() != 0)
return 0;
@@ -1259,6 +1268,7 @@
}
break;
+ case 'l':
case 'a': {
u64 mc_dpl_addr;
@@ -1279,8 +1289,17 @@
return -ENODEV;
}
- if (!fsl_mc_ldpaa_exit(NULL))
- err = mc_apply_dpl(mc_dpl_addr);
+ if (argv[1][0] == 'l') {
+ /*
+ * We will do the actual dpaa exit and dpl apply
+ * later from announce_and_cleanup().
+ */
+ mc_lazy_dpl_addr = mc_dpl_addr;
+ } else {
+ /* The user wants it applied now */
+ if (!fsl_mc_ldpaa_exit(NULL))
+ err = mc_apply_dpl(mc_dpl_addr);
+ }
break;
}
default:
@@ -1298,5 +1317,6 @@
"DPAA2 command to manage Management Complex (MC)",
"start mc [FW_addr] [DPC_addr] - Start Management Complex\n"
"fsl_mc apply DPL [DPL_addr] - Apply DPL file\n"
+ "fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n"
"fsl_mc start aiop [FW_addr] - Start AIOP\n"
);
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 77b9739..bd56166 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,7 +11,7 @@
#include <phy.h>
#include <fsl_mdio.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum, int value)
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
index 8fa767a..bbe56f1 100644
--- a/drivers/net/ftmac110.c
+++ b/drivers/net/ftmac110.c
@@ -11,7 +11,7 @@
#include <command.h>
#include <malloc.h>
#include <net.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/dma-mapping.h>
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index e41b7d1..a5120e0 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -56,13 +56,16 @@
#ifdef CONFIG_DM_ETH
enum link_type {
- LINK_TYPE_MAC_TO_MAC_AUTO = 0,
- LINK_TYPE_MAC_TO_PHY_MODE = 1,
- LINK_TYPE_MAC_TO_MAC_FORCED_MODE = 2,
- LINK_TYPE_MAC_TO_FIBRE_MODE = 3,
- LINK_TYPE_MAC_TO_PHY_NO_MDIO_MODE = 4,
- LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
- LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
+ LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
+ LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
+ LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
+ LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
+ LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
+ LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
+ LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
+ LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
+ LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
+ LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
};
#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
@@ -990,7 +993,7 @@
char *slave_name;
interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
- fdt_for_each_subnode(fdt, slave, interfaces) {
+ fdt_for_each_subnode(slave, fdt, interfaces) {
int slave_no;
slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
@@ -1015,7 +1018,7 @@
}
sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
- fdt_for_each_subnode(fdt, slave, sec_slave) {
+ fdt_for_each_subnode(slave, fdt, sec_slave) {
int slave_no;
slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
@@ -1077,11 +1080,15 @@
priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
}
- if (priv->link_type == LINK_TYPE_MAC_TO_PHY_MODE) {
+ if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
priv->phy_if = PHY_INTERFACE_MODE_SGMII;
pdata->phy_interface = priv->phy_if;
priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
priv->has_mdio = true;
+ } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
+ priv->phy_if = PHY_INTERFACE_MODE_RGMII;
+ pdata->phy_interface = priv->phy_if;
+ priv->has_mdio = true;
}
return 0;
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 75b2b6b..4e61700 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -420,13 +420,14 @@
goto err_dpmac_setup;
#ifdef CONFIG_PHYLIB
- if (priv->phydev)
+ if (priv->phydev) {
err = phy_startup(priv->phydev);
if (err) {
printf("%s: Could not initialize\n",
priv->phydev->dev->name);
goto err_dpamc_bind;
}
+ }
#else
priv->phydev = (struct phy_device *)malloc(sizeof(struct phy_device));
memset(priv->phydev, 0, sizeof(struct phy_device));
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
index 2dd69f3..cbef335 100644
--- a/drivers/net/lpc32xx_eth.c
+++ b/drivers/net/lpc32xx_eth.c
@@ -12,7 +12,7 @@
#include <malloc.h>
#include <miiphy.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/types.h>
#include <asm/system.h>
#include <asm/byteorder.h>
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 921537f..01527f7 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -39,7 +39,7 @@
#include <asm/io.h>
#include <asm/dma-mapping.h>
#include <asm/arch/clk.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include "macb.h"
@@ -251,33 +251,35 @@
static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
{
if (rx)
- invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
- MACB_RX_DMA_DESC_SIZE);
+ invalidate_dcache_range(macb->rx_ring_dma,
+ ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
+ PKTALIGN));
else
- invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
- MACB_TX_DMA_DESC_SIZE);
+ invalidate_dcache_range(macb->tx_ring_dma,
+ ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
+ PKTALIGN));
}
static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
{
if (rx)
flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
- MACB_RX_DMA_DESC_SIZE);
+ ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
else
flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
- MACB_TX_DMA_DESC_SIZE);
+ ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
}
static inline void macb_flush_rx_buffer(struct macb_device *macb)
{
flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
- MACB_RX_BUFFER_SIZE);
+ ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
}
static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
{
invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
- MACB_RX_BUFFER_SIZE);
+ ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
}
#if defined(CONFIG_CMD_NET)
@@ -596,7 +598,7 @@
macb->dummy_desc->ctrl = TXBUF_USED;
macb->dummy_desc->addr = 0;
flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
- MACB_TX_DUMMY_DMA_DESC_SIZE);
+ ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
for (i = 1; i < num_queues; i++)
gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index a1c7ea0..f833efb 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -17,7 +17,7 @@
#include <malloc.h>
#include <miiphy.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/types.h>
#include <asm/system.h>
#include <asm/byteorder.h>
@@ -177,25 +177,6 @@
}
#endif
-#if defined(CONFIG_PHYLIB)
-int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
- int reg_addr)
-{
- u16 data;
- int ret;
- ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data);
- if (ret)
- return ret;
- return data;
-}
-
-int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
- int reg_addr, u16 data)
-{
- return smi_reg_write(bus->name, phy_addr, reg_addr, data);
-}
-#endif
-
/* Stop and checks all queues */
static void stop_queue(u32 * qreg)
{
@@ -676,8 +657,8 @@
printf("mdio_alloc failed\n");
return -ENOMEM;
}
- bus->read = mvgbe_phy_read;
- bus->write = mvgbe_phy_write;
+ bus->read = smi_reg_read;
+ bus->write = smi_reg_write;
strcpy(bus->name, dev->name);
ret = mdio_register(bus);
@@ -688,7 +669,7 @@
}
/* Set phy address of the port */
- mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
+ smi_reg_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index fa20f54..00f378f 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -20,7 +20,7 @@
#include <config.h>
#include <malloc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <phy.h>
#include <miiphy.h>
#include <watchdog.h>
@@ -91,7 +91,11 @@
#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
+#define MVNETA_WIN_SIZE_MASK (0xffff0000)
#define MVNETA_BASE_ADDR_ENABLE 0x2290
+#define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
+#define MVNETA_PORT_ACCESS_PROTECT 0x2294
+#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
#define MVNETA_PORT_CONFIG 0x2400
#define MVNETA_UNI_PROMISC_MODE BIT(0)
#define MVNETA_DEF_RXQ(q) ((q) << 1)
@@ -1022,7 +1026,7 @@
txq->size = pp->tx_ring_size;
/* Allocate memory for TX descriptors */
- txq->descs_phys = (u32)txq->descs;
+ txq->descs_phys = (dma_addr_t)txq->descs;
if (txq->descs == NULL)
return -ENOMEM;
@@ -1241,6 +1245,32 @@
}
/* platform glue : initialize decoding windows */
+
+/*
+ * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
+ * First layer is: GbE Address window that resides inside the GBE unit,
+ * Second layer is: Fabric address window which is located in the NIC400
+ * (South Fabric).
+ * To simplify the address decode configuration for Armada3700, we bypass the
+ * first layer of GBE decode window by setting the first window to 4GB.
+ */
+static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
+{
+ /*
+ * Set window size to 4GB, to bypass GBE address decode, leave the
+ * work to MBUS decode window
+ */
+ mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
+
+ /* Enable GBE address decode window 0 by set bit 0 to 0 */
+ clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
+ MVNETA_BASE_ADDR_ENABLE_BIT);
+
+ /* Set GBE address decode window 0 to full Access (read or write) */
+ setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
+ MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
+}
+
static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
{
const struct mbus_dram_target_info *dram;
@@ -1504,9 +1534,10 @@
/* Get a descriptor for the first part of the packet */
tx_desc = mvneta_txq_next_desc_get(txq);
- tx_desc->buf_phys_addr = (u32)packet;
+ tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
tx_desc->data_size = length;
- flush_dcache_range((u32)packet, (u32)packet + length);
+ flush_dcache_range((ulong)packet,
+ (ulong)packet + ALIGN(length, PKTALIGN));
/* First and Last descriptor */
tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
@@ -1562,7 +1593,7 @@
rx_bytes = rx_desc->data_size - 6;
/* give packet to stack - skip on first 2 bytes */
- data = (u8 *)rx_desc->buf_cookie + 2;
+ data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
/*
* No cache invalidation needed here, since the rx_buffer's are
* located in a uncached memory region
@@ -1588,18 +1619,18 @@
/*
* Allocate buffer area for descs and rx_buffers. This is only
* done once for all interfaces. As only one interface can
- * be active. Make this area DMA save by disabling the D-cache
+ * be active. Make this area DMA safe by disabling the D-cache
*/
if (!buffer_loc.tx_descs) {
/* Align buffer area for descs and rx_buffers to 1MiB */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
- mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE,
+ mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
DCACHE_OFF);
buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
buffer_loc.rx_descs = (struct mvneta_rx_desc *)
- ((u32)bd_space +
+ ((phys_addr_t)bd_space +
MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
- buffer_loc.rx_buffers = (u32)
+ buffer_loc.rx_buffers = (phys_addr_t)
(bd_space +
MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
@@ -1608,7 +1639,10 @@
pp->base = (void __iomem *)pdata->iobase;
/* Configure MBUS address windows */
- mvneta_conf_mbus_windows(pp);
+ if (of_device_is_compatible(dev, "marvell,armada-3700-neta"))
+ mvneta_bypass_mbus_windows(pp);
+ else
+ mvneta_conf_mbus_windows(pp);
/* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
pp->phy_interface = pdata->phy_interface;
@@ -1671,6 +1705,7 @@
static const struct udevice_id mvneta_ids[] = {
{ .compatible = "marvell,armada-370-neta" },
{ .compatible = "marvell,armada-xp-neta" },
+ { .compatible = "marvell,armada-3700-neta" },
{ }
};
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 900a04c..405776a 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -22,7 +22,7 @@
#include <config.h>
#include <malloc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <phy.h>
#include <miiphy.h>
#include <watchdog.h>
@@ -4153,7 +4153,7 @@
return -ENOENT;
}
- fdt_for_each_subnode(blob, subnode, node) {
+ fdt_for_each_subnode(subnode, blob, node) {
/* Skip disabled ports */
if (!fdtdec_get_is_enabled(blob, subnode))
continue;
diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c
index 137818b..d40fff0 100644
--- a/drivers/net/pch_gbe.c
+++ b/drivers/net/pch_gbe.c
@@ -118,14 +118,14 @@
memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
for (i = 0; i < PCH_GBE_DESC_NUM; i++)
rx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev,
- (u32)(priv->rx_buff[i]));
+ (ulong)(priv->rx_buff[i]));
- writel(dm_pci_phys_to_mem(priv->dev, (u32)rx_desc),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)rx_desc),
&mac_regs->rx_dsc_base);
writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
&mac_regs->rx_dsc_size);
- writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_desc + 1)),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_desc + 1)),
&mac_regs->rx_dsc_sw_p);
}
@@ -137,11 +137,11 @@
memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
- writel(dm_pci_phys_to_mem(priv->dev, (u32)tx_desc),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)tx_desc),
&mac_regs->tx_dsc_base);
writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
&mac_regs->tx_dsc_size);
- writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_desc + 1)),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_desc + 1)),
&mac_regs->tx_dsc_sw_p);
}
@@ -251,7 +251,7 @@
if (length < 64)
frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
- tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)packet);
+ tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (ulong)packet);
tx_desc->length = length;
tx_desc->tx_words_eob = length + 3;
tx_desc->tx_frame_ctrl = frame_ctrl;
@@ -262,7 +262,7 @@
if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
priv->tx_idx = 0;
- writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_head + priv->tx_idx)),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_head + priv->tx_idx)),
&mac_regs->tx_dsc_sw_p);
start = get_timer(0);
@@ -283,7 +283,7 @@
struct pch_gbe_priv *priv = dev_get_priv(dev);
struct pch_gbe_regs *mac_regs = priv->mac_regs;
struct pch_gbe_rx_desc *rx_desc;
- u32 hw_desc, buffer_addr, length;
+ ulong hw_desc, buffer_addr, length;
rx_desc = &priv->rx_desc[priv->rx_idx];
@@ -291,7 +291,7 @@
hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
/* Just return if not receiving any packet */
- if ((u32)rx_desc == hw_desc)
+ if ((ulong)rx_desc == hw_desc)
return -EAGAIN;
buffer_addr = dm_pci_mem_to_phys(priv->dev, rx_desc->buffer_addr);
@@ -315,7 +315,7 @@
if (++rx_swp >= PCH_GBE_DESC_NUM)
rx_swp = 0;
- writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_head + rx_swp)),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_head + rx_swp)),
&mac_regs->rx_dsc_sw_p);
return 0;
@@ -421,7 +421,7 @@
{
struct pch_gbe_priv *priv;
struct eth_pdata *plat = dev_get_platdata(dev);
- u32 iobase;
+ void *iobase;
/*
* The priv structure contains the descriptors and frame buffers which
@@ -432,11 +432,9 @@
priv->dev = dev;
- dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
- iobase &= PCI_BASE_ADDRESS_MEM_MASK;
- iobase = dm_pci_mem_to_phys(dev, iobase);
+ iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
- plat->iobase = iobase;
+ plat->iobase = (ulong)iobase;
priv->mac_regs = (struct pch_gbe_regs *)iobase;
/* Read MAC address from SROM and initialize dev->enetaddr with it */
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index e57c412..b34cdd3 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -8,6 +8,15 @@
*/
#include <phy.h>
+#define AR803x_PHY_DEBUG_ADDR_REG 0x1d
+#define AR803x_PHY_DEBUG_DATA_REG 0x1e
+
+#define AR803x_DEBUG_REG_5 0x5
+#define AR803x_RGMII_TX_CLK_DLY 0x100
+
+#define AR803x_DEBUG_REG_0 0x0
+#define AR803x_RGMII_RX_CLK_DLY 0x8000
+
static int ar8021_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
@@ -17,6 +26,32 @@
return 0;
}
+static int ar8031_config(struct phy_device *phydev)
+{
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_5);
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+ AR803x_RGMII_TX_CLK_DLY);
+ }
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_0);
+ phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+ AR803x_RGMII_RX_CLK_DLY);
+ }
+
+ phydev->supported = phydev->drv->features;
+
+ genphy_config_aneg(phydev);
+ genphy_restart_aneg(phydev);
+
+ return 0;
+}
+
static int ar8035_config(struct phy_device *phydev)
{
int regval;
@@ -31,6 +66,22 @@
regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
+ if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
+ (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
+ /* select debug reg 5 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
+ /* enable tx delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
+ }
+
+ if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
+ (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
+ /* select debug reg 0 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
+ /* enable rx delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
+ }
+
phydev->supported = phydev->drv->features;
genphy_config_aneg(phydev);
@@ -54,7 +105,7 @@
.uid = 0x4dd074,
.mask = 0xffffffef,
.features = PHY_GBIT_FEATURES,
- .config = ar8035_config,
+ .config = ar8031_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 6b313a9..7163fa2 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -300,10 +300,11 @@
};
int i, ret = 0;
- for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+ for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
if (ret)
return ret;
+ }
return 0;
}
@@ -408,18 +409,39 @@
};
int i, ret = 0;
- for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+ for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
if (ret)
return ret;
+ }
return 0;
}
+
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+ struct phy_driver *drv = phydev->drv;
+ int ret = 0;
+
+ if (!drv || !drv->writeext)
+ return -EOPNOTSUPP;
+
+ ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
+ if (ret)
+ return ret;
+
+ ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
+ return ret;
+}
#else
static int ksz9031_of_config(struct phy_device *phydev)
{
return 0;
}
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+ return 0;
+}
#endif
/* Accessors to extended registers*/
@@ -472,6 +494,9 @@
ret = ksz9031_of_config(phydev);
if (ret)
return ret;
+ ret = ksz9031_center_flp_timing(phydev);
+ if (ret)
+ return ret;
return genphy_config(phydev);
}
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 74d5609..a2fd168 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -40,7 +40,7 @@
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
-#define PORT_COUNT 7
+#define PORT_COUNT 11
#define PORT_MASK ((1 << PORT_COUNT) - 1)
/* Device addresses */
@@ -103,8 +103,16 @@
#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
#define PORT_REG_STATUS_CMODE_SGMII 0xa
+#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
+#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
+#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
+#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
+#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
+#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
+#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
+#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
#define PORT_REG_CTRL_PSTATE_SHIFT 0
#define PORT_REG_CTRL_PSTATE_WIDTH 2
@@ -166,7 +174,17 @@
#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
#endif
+/*
+ * These are ports without PHYs that may be wired directly
+ * to other serdes interfaces
+ */
+#ifndef CONFIG_MV88E61XX_FIXED_PORTS
+#define CONFIG_MV88E61XX_FIXED_PORTS 0
+#endif
+
/* ID register values for different switch models */
+#define PORT_SWITCH_ID_6096 0x0980
+#define PORT_SWITCH_ID_6097 0x0990
#define PORT_SWITCH_ID_6172 0x1720
#define PORT_SWITCH_ID_6176 0x1760
#define PORT_SWITCH_ID_6240 0x2400
@@ -580,7 +598,7 @@
}
static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
- u8 mask)
+ u16 mask)
{
int val;
@@ -791,6 +809,27 @@
return 0;
}
+static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
+{
+ int val;
+
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+ if (val < 0)
+ return val;
+
+ val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
+ PORT_REG_PHYS_CTRL_FC_VALUE);
+ val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
+ PORT_REG_PHYS_CTRL_PCS_AN_RST |
+ PORT_REG_PHYS_CTRL_FC_FORCE |
+ PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
+ PORT_REG_PHYS_CTRL_DUPLEX_FORCE |
+ PORT_REG_PHYS_CTRL_SPD1000;
+
+ return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+ val);
+}
+
static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
{
int val;
@@ -909,6 +948,12 @@
/* Return success if any PHY succeeds */
ret = 0;
+ } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) {
+ res = mv88e61xx_fixed_port_setup(phydev, i);
+ if (res < 0) {
+ printf("Error configuring port %i\n", i);
+ continue;
+ }
}
}
@@ -974,9 +1019,21 @@
.shutdown = &genphy_shutdown,
};
+static struct phy_driver mv88e609x_driver = {
+ .name = "Marvell MV88E609x",
+ .uid = 0x1410c89,
+ .mask = 0xfffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .probe = mv88e61xx_probe,
+ .config = mv88e61xx_phy_config,
+ .startup = mv88e61xx_phy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
int phy_mv88e61xx_init(void)
{
phy_register(&mv88e61xx_driver);
+ phy_register(&mv88e609x_driver);
return 0;
}
diff --git a/drivers/net/phy/mv88e6352.c b/drivers/net/phy/mv88e6352.c
index f639a42..d2b3ce6 100644
--- a/drivers/net/phy/mv88e6352.c
+++ b/drivers/net/phy/mv88e6352.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <miiphy.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <mv88e6352.h>
#define SMI_HDR ((0x8 | 0x1) << 12)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 7a99cb0..635acf5 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -9,13 +9,16 @@
*/
#include <config.h>
#include <common.h>
+#include <linux/bitops.h>
#include <phy.h>
+#define PHY_RTL8211x_FORCE_MASTER BIT(1)
+
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
/* RTL8211x 1000BASE-T Control Register */
-#define MIIM_RTL8211x_CTRL1000T_MSCE (1 << 12);
-#define MIIM_RTL8211X_CTRL1000T_MASTER (1 << 11);
+#define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12);
+#define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11);
/* RTL8211x PHY Status Register */
#define MIIM_RTL8211x_PHY_STATUS 0x11
@@ -48,6 +51,15 @@
#define MIIM_RTL8211F_TX_DELAY 0x100
#define MIIM_RTL8211F_LCR 0x10
+static int rtl8211b_probe(struct phy_device *phydev)
+{
+#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
+ phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
+#endif
+
+ return 0;
+}
+
/* RealTek RTL8211x */
static int rtl8211x_config(struct phy_device *phydev)
{
@@ -58,14 +70,17 @@
*/
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
MIIM_RTL8211x_PHY_INTR_DIS);
-#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
- unsigned int reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
- /* force manual master/slave configuration */
- reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
- /* force master mode */
- reg |= MIIM_RTL8211X_CTRL1000T_MASTER;
- phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
-#endif
+
+ if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
+ unsigned int reg;
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
+ /* force manual master/slave configuration */
+ reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
+ /* force master mode */
+ reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
+ }
/* read interrupt status just to clear it */
phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
@@ -248,6 +263,7 @@
.uid = 0x1cc912,
.mask = 0xffffff,
.features = PHY_GBIT_FEATURES,
+ .probe = &rtl8211b_probe,
.config = &rtl8211x_config,
.startup = &rtl8211x_startup,
.shutdown = &genphy_shutdown,
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 2635b82..a077b98 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -30,9 +30,8 @@
#define MIIM_CIS8204_SLEDCON_INIT 0x1115
/* Vitesse VSC8601 Extended PHY Control Register 1 */
-#define MIIM_VSC8601_EPHY_CON 0x17
-#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
-#define MIIM_VSC8601_SKEW_CTRL 0x1c
+#define MII_VSC8601_EPHY_CTL 0x17
+#define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
#define PHY_EXT_PAGE_ACCESS 0x1f
#define PHY_EXT_PAGE_ACCESS_GENERAL 0x10
@@ -142,26 +141,32 @@
}
/* Vitesse VSC8601 */
+/* This adds a skew for both TX and RX clocks, so the skew should only be
+ * applied to "rgmii-id" interfaces. It may not work as expected
+ * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
+static int vsc8601_add_skew(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL);
+ if (ret < 0)
+ return ret;
+
+ ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
+ return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret);
+}
+
static int vsc8601_config(struct phy_device *phydev)
{
- /* Configure some basic stuff */
-#ifdef CONFIG_SYS_VSC8601_SKEWFIX
- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_EPHY_CON,
- MIIM_VSC8601_EPHY_CON_INIT_SKEW);
-#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
- phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 1);
-#define VSC8101_SKEW \
- ((CONFIG_SYS_VSC8601_SKEW_TX << 14) \
- | (CONFIG_SYS_VSC8601_SKEW_RX << 12))
- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_SKEW_CTRL,
- VSC8101_SKEW);
- phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
-#endif
-#endif
+ int ret = 0;
- genphy_config_aneg(phydev);
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ ret = vsc8601_add_skew(phydev);
- return 0;
+ if (ret < 0)
+ return ret;
+
+ return genphy_config_aneg(phydev);
}
static int vsc8574_config(struct phy_device *phydev)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 1cc0b40..5297e30 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -339,9 +339,6 @@
static struct rtl8169_private *tpc;
-static const u16 rtl8169_intr_mask =
- SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
- TxOK | RxErr | RxOK;
static const unsigned int rtl8169_rx_config =
(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
@@ -629,11 +626,12 @@
/* point to the current txb incase multiple tx_rings are used */
ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
memcpy(ptxb, (char *)packet, (int)length);
- rtl_flush_buffer(ptxb, length);
while (len < ETH_ZLEN)
ptxb[len++] = '\0';
+ rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
+
tpc->TxDescArray[entry].buf_Haddr = 0;
#ifdef CONFIG_DM_ETH
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 79c1db2..a7c265b 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -15,7 +15,7 @@
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include "sh_eth.h"
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 4c149e1..abd9cc8 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -180,8 +180,8 @@
miiaddr |= MDIO_CMD_MII_WRITE;
miiaddr |= MDIO_CMD_MII_BUSY;
- writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
writel(val, priv->mac_reg + EMAC_MII_DATA);
+ writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
start = get_timer(0);
while (get_timer(start) < timeout) {
@@ -456,8 +456,9 @@
for (i = 0; ; i++) {
int pin;
- if (fdt_get_string_index(gd->fdt_blob, offset,
- "allwinner,pins", i, &pin_name))
+ pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
+ "allwinner,pins", i, NULL);
+ if (!pin_name)
break;
if (pin_name[0] != 'P')
continue;
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index be0f382..7df4c63 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -16,7 +16,7 @@
#include <command.h>
#include <tsec.h>
#include <fsl_mdio.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/processor.h>
#include <asm/io.h>
diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
index c6d6dce..0724210 100644
--- a/drivers/net/vsc7385.c
+++ b/drivers/net/vsc7385.c
@@ -16,7 +16,7 @@
#include <common.h>
#include <console.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "vsc7385.h"
/*
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 5de06ef..51c7426 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -648,9 +648,8 @@
priv->bus->read = axiemac_miiphy_read;
priv->bus->write = axiemac_miiphy_write;
priv->bus->priv = priv;
- strcpy(priv->bus->name, "axi_emac");
- ret = mdio_register(priv->bus);
+ ret = mdio_register_seq(priv->bus, dev->seq);
if (ret)
return ret;
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 7b85aa0..ea93cf9 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -17,8 +17,9 @@
#include <phy.h>
#include <miiphy.h>
#include <fdtdec.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <linux/kernel.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -154,7 +155,7 @@
unsigned long start = get_timer(0);
while (1) {
- val = readl(reg);
+ val = __raw_readl(reg);
if (!set)
val = ~val;
@@ -193,16 +194,17 @@
if (mdio_wait(regs))
return 1;
- u32 ctrl_reg = in_be32(®s->mdioctrl);
- out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK |
- ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
- out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+ u32 ctrl_reg = __raw_readl(®s->mdioctrl);
+ __raw_writel(XEL_MDIOADDR_OP_MASK
+ | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
+ | registernum), ®s->mdioaddr);
+ __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
if (mdio_wait(regs))
return 1;
/* Read data */
- *data = in_be32(®s->mdiord);
+ *data = __raw_readl(®s->mdiord);
return 0;
}
@@ -220,11 +222,12 @@
* Data register. Finally, set the Status bit in the MDIO Control
* register to start a MDIO write transaction.
*/
- u32 ctrl_reg = in_be32(®s->mdioctrl);
- out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
- ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
- out_be32(®s->mdiowr, data);
- out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+ u32 ctrl_reg = __raw_readl(®s->mdioctrl);
+ __raw_writel(~XEL_MDIOADDR_OP_MASK
+ & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
+ | registernum), ®s->mdioaddr);
+ __raw_writel(data, ®s->mdiowr);
+ __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
if (mdio_wait(regs))
return 1;
@@ -327,27 +330,27 @@
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
- out_be32(®s->tx_ping_tsr, 0);
+ __raw_writel(0, ®s->tx_ping_tsr);
/* Copy MAC address */
xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
ENET_ADDR_LENGTH);
/* Set the length */
- out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH);
+ __raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr);
/* Update the MAC address in the EMAC Lite */
- out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
+ __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr);
/* Wait for EMAC Lite to finish with the MAC address update */
- while ((in_be32 (®s->tx_ping_tsr) &
+ while ((__raw_readl(®s->tx_ping_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
if (emaclite->txpp) {
/* The same operation with PONG TX */
- out_be32(®s->tx_pong_tsr, 0);
+ __raw_writel(0, ®s->tx_pong_tsr);
xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
ENET_ADDR_LENGTH);
- out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH);
- out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
- while ((in_be32(®s->tx_pong_tsr) &
+ __raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr);
+ __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr);
+ while ((__raw_readl(®s->tx_pong_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
}
@@ -356,13 +359,13 @@
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
- out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
+ __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr);
if (emaclite->rxpp)
- out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
+ __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr);
- out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
- if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
+ __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl);
+ if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
if (!setup_phy(dev))
return -1;
@@ -379,9 +382,9 @@
* Read the other buffer register
* and determine if the other buffer is available
*/
- tmp = ~in_be32(®s->tx_ping_tsr);
+ tmp = ~__raw_readl(®s->tx_ping_tsr);
if (emaclite->txpp)
- tmp |= ~in_be32(®s->tx_pong_tsr);
+ tmp |= ~__raw_readl(®s->tx_pong_tsr);
return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
}
@@ -405,40 +408,42 @@
if (!maxtry) {
printf("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
- out_be32(®s->tx_ping_tsr, 0);
+ __raw_writel(0, ®s->tx_ping_tsr);
if (emaclite->txpp) {
- out_be32(®s->tx_pong_tsr, 0);
+ __raw_writel(0, ®s->tx_pong_tsr);
}
return -1;
}
/* Determine if the expected buffer address is empty */
- reg = in_be32(®s->tx_ping_tsr);
+ reg = __raw_readl(®s->tx_ping_tsr);
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
debug("Send packet from tx_ping buffer\n");
/* Write the frame to the buffer */
xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
- out_be32(®s->tx_ping_tplr, len &
- (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
- reg = in_be32(®s->tx_ping_tsr);
+ __raw_writel(len
+ & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
+ ®s->tx_ping_tplr);
+ reg = __raw_readl(®s->tx_ping_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
- out_be32(®s->tx_ping_tsr, reg);
+ __raw_writel(reg, ®s->tx_ping_tsr);
return 0;
}
if (emaclite->txpp) {
/* Determine if the expected buffer address is empty */
- reg = in_be32(®s->tx_pong_tsr);
+ reg = __raw_readl(®s->tx_pong_tsr);
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
debug("Send packet from tx_pong buffer\n");
/* Write the frame to the buffer */
xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
- out_be32(®s->tx_pong_tplr, len &
+ __raw_writel(len &
(XEL_TPLR_LENGTH_MASK_HI |
- XEL_TPLR_LENGTH_MASK_LO));
- reg = in_be32(®s->tx_pong_tsr);
+ XEL_TPLR_LENGTH_MASK_LO),
+ ®s->tx_pong_tplr);
+ reg = __raw_readl(®s->tx_pong_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
- out_be32(®s->tx_pong_tsr, reg);
+ __raw_writel(reg, ®s->tx_pong_tsr);
return 0;
}
}
@@ -458,7 +463,7 @@
try_again:
if (!emaclite->use_rx_pong_buffer_next) {
- reg = in_be32(®s->rx_ping_rsr);
+ reg = __raw_readl(®s->rx_ping_rsr);
debug("Testing data at rx_ping\n");
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
debug("Data found in rx_ping buffer\n");
@@ -478,7 +483,7 @@
goto try_again;
}
} else {
- reg = in_be32(®s->rx_pong_rsr);
+ reg = __raw_readl(®s->rx_pong_rsr);
debug("Testing data at rx_pong\n");
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
debug("Data found in rx_pong buffer\n");
@@ -525,9 +530,9 @@
length - first_read);
/* Acknowledge the frame */
- reg = in_be32(ack);
+ reg = __raw_readl(ack);
reg &= ~XEL_RSR_RECV_DONE_MASK;
- out_be32(ack, reg);
+ __raw_writel(reg, ack);
debug("Packet receive from 0x%p, length %dB\n", addr, length);
*packetp = etherrxbuff;
@@ -561,9 +566,8 @@
emaclite->bus->read = emaclite_miiphy_read;
emaclite->bus->write = emaclite_miiphy_write;
emaclite->bus->priv = emaclite;
- strcpy(emaclite->bus->name, "emaclite");
- ret = mdio_register(emaclite->bus);
+ ret = mdio_register_seq(emaclite->bus, dev->seq);
if (ret)
return ret;
@@ -595,7 +599,8 @@
int offset = 0;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
- emaclite->regs = (struct emaclite_regs *)pdata->iobase;
+ emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
+ 0x10000);
emaclite->phyaddr = -1;
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 519699d..d2e5e7c 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -24,7 +24,7 @@
#include <asm/system.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -53,16 +53,16 @@
#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
-#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
-#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
-#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
-#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
-#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */
-#define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */
+#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
+#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
+#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
+#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
+#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
+#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
#ifdef CONFIG_ARM64
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
#else
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
#endif
#ifdef CONFIG_ARM64
@@ -647,9 +647,8 @@
priv->bus->read = zynq_gem_miiphy_read;
priv->bus->write = zynq_gem_miiphy_write;
priv->bus->priv = priv;
- strcpy(priv->bus->name, "gem");
- ret = mdio_register(priv->bus);
+ ret = mdio_register_seq(priv->bus, dev->seq);
if (ret)
return ret;
@@ -706,7 +705,7 @@
priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
- printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
+ printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 669e37b..275b29b 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -1,7 +1,15 @@
-menu "PCI"
+menuconfig PCI
+ bool "PCI support"
+ default y if PPC || X86
+ help
+ Enable support for PCI (Peripheral Interconnect Bus), a type of bus
+ used on some devices to allow the CPU to communicate with its
+ peripherals.
+
+if PCI
config DM_PCI
- bool "Enable driver mode for PCI"
+ bool "Enable driver model for PCI"
depends on DM
help
Use driver model for PCI. Driver model is the new method for
@@ -18,6 +26,23 @@
measure when porting a board to use driver model for PCI. Once the
board is fully supported, this option should be disabled.
+config PCI_PNP
+ bool "Enable Plug & Play support for PCI"
+ depends on PCI || DM_PCI
+ default y
+ help
+ Enable PCI memory and I/O space resource allocation and assignment.
+
+config PCIE_DW_MVEBU
+ bool "Enable Armada-8K PCIe driver (DesignWare core)"
+ default n
+ depends on DM_PCI
+ depends on ARMADA_8K
+ help
+ Say Y here if you want to enable PCIe controller support on
+ Armada-8K SoCs. The PCIe controller on Armada-8K is based on
+ DesignWare hardware.
+
config PCI_SANDBOX
bool "Sandbox PCI support"
depends on SANDBOX && DM_PCI
@@ -39,4 +64,11 @@
with a total of 5 lanes. Some boards require this for Ethernet
support to work (e.g. beaver, jetson-tk1).
-endmenu
+config PCI_XILINX
+ bool "Xilinx AXI Bridge for PCI Express"
+ depends on DM_PCI
+ help
+ Enable support for the Xilinx AXI bridge for PCI express, an IP block
+ which can be used on some generations of Xilinx FPGAs.
+
+endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index f8be9bf..86717a4 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -30,4 +30,6 @@
obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
+obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
+obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 342b78c..3b00e6a 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -837,7 +837,7 @@
hose = bus->uclass_priv;
/* For bridges, use the top-level PCI controller */
- if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
+ if (!device_is_on_pci_bus(bus)) {
hose->ctlr = bus;
ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
bus->of_offset);
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 4eedfe1..0f44970 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -12,7 +12,7 @@
#include <common.h>
#include <pci.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 399055b..cd083f7 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -31,6 +31,7 @@
#include <pci.h>
#include <pci_rom.h>
#include <vbe.h>
+#include <video.h>
#include <video_fb.h>
#include <linux/screen_info.h>
@@ -348,3 +349,64 @@
free(ram);
return ret;
}
+
+#ifdef CONFIG_DM_VIDEO
+int vbe_setup_video_priv(struct vesa_mode_info *vesa,
+ struct video_priv *uc_priv,
+ struct video_uc_platdata *plat)
+{
+ if (!vesa->x_resolution)
+ return -ENXIO;
+ uc_priv->xsize = vesa->x_resolution;
+ uc_priv->ysize = vesa->y_resolution;
+ switch (vesa->bits_per_pixel) {
+ case 32:
+ case 24:
+ uc_priv->bpix = VIDEO_BPP32;
+ break;
+ case 16:
+ uc_priv->bpix = VIDEO_BPP16;
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+ plat->base = vesa->phys_base_ptr;
+ plat->size = vesa->bytes_per_scanline * vesa->y_resolution;
+
+ return 0;
+}
+
+int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
+
+ printf("Video: ");
+
+ /* If we are running from EFI or coreboot, this can't work */
+ if (!ll_boot_init()) {
+ printf("Not available (previous bootloader prevents it)\n");
+ return -EPERM;
+ }
+ bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
+ ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
+ PCI_ROM_ALLOW_FALLBACK);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
+ if (ret) {
+ debug("failed to run video BIOS: %d\n", ret);
+ return ret;
+ }
+
+ ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat);
+ if (ret) {
+ debug("No video mode configured\n");
+ return ret;
+ }
+
+ printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+ mode_info.vesa.bits_per_pixel);
+
+ return 0;
+}
+#endif
diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c
index f189ed8..8a50445 100644
--- a/drivers/pci/pci_sh7751.c
+++ b/drivers/pci/pci_sh7751.c
@@ -66,9 +66,6 @@
#define SH7751_PCI_IO_BASE 0xFE240000
#define SH7751_PCI_IO_SIZE 0x00040000
-#define SH7751_CS3_BASE_ADDR 0x0C000000
-#define SH7751_P2CS3_BASE_ADDR 0xAC000000
-
#define SH7751_PCIPAR (vu_long *)0xFE2001C0
#define SH7751_PCIPDR (vu_long *)0xFE200220
@@ -153,18 +150,19 @@
/* Set up target memory mappings (for external DMA access) */
/* Map both P0 and P2 range to Area 3 RAM for ease of use */
- p4_out((64 - 1) << 20, SH7751_PCILSR0);
- p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0);
+ p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
+ p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
+ p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
+
p4_out(0, SH7751_PCILSR1);
p4_out(0, SH7751_PCILAR1);
- p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5);
p4_out(0xd0000000, SH7751_PCICONF6);
/* Map memory window to same address on PCI bus */
p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
/* Map IO window to same address on PCI bus */
- p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR);
+ p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
/* set BREQEN */
p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index ea8adb98..430270e 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -531,7 +531,7 @@
}
#endif
- fdt_for_each_subnode(fdt, subnode, node) {
+ fdt_for_each_subnode(subnode, fdt, node) {
unsigned int index = 0, num_lanes = 0;
struct tegra_pcie_port *port;
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
new file mode 100644
index 0000000..17fa024
--- /dev/null
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -0,0 +1,535 @@
+/*
+ * Copyright (C) 2015 Marvell International Ltd.
+ *
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * Based on:
+ * - drivers/pci/pcie_imx.c
+ * - drivers/pci/pci_mvebu.c
+ * - drivers/pci/pcie_xilinx.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PCI Config space registers */
+#define PCIE_CONFIG_BAR0 0x10
+#define PCIE_LINK_STATUS_REG 0x80
+#define PCIE_LINK_STATUS_SPEED_OFF 16
+#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
+#define PCIE_LINK_STATUS_WIDTH_OFF 20
+#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
+
+/* Resizable bar capability registers */
+#define RESIZABLE_BAR_CAP 0x250
+#define RESIZABLE_BAR_CTL0 0x254
+#define RESIZABLE_BAR_CTL1 0x258
+
+/* iATU registers */
+#define PCIE_ATU_VIEWPORT 0x900
+#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
+#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
+#define PCIE_ATU_CR1 0x904
+#define PCIE_ATU_TYPE_MEM (0x0 << 0)
+#define PCIE_ATU_TYPE_IO (0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_CR2 0x908
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_LOWER_BASE 0x90C
+#define PCIE_ATU_UPPER_BASE 0x910
+#define PCIE_ATU_LIMIT 0x914
+#define PCIE_ATU_LOWER_TARGET 0x918
+#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET 0x91C
+
+#define PCIE_LINK_CAPABILITY 0x7C
+#define PCIE_LINK_CTL_2 0xA0
+#define TARGET_LINK_SPEED_MASK 0xF
+#define LINK_SPEED_GEN_1 0x1
+#define LINK_SPEED_GEN_2 0x2
+#define LINK_SPEED_GEN_3 0x3
+
+#define PCIE_GEN3_RELATED 0x890
+#define GEN3_EQU_DISABLE (1 << 16)
+#define GEN3_ZRXDC_NON_COMP (1 << 0)
+
+#define PCIE_GEN3_EQU_CTRL 0x8A8
+#define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
+
+#define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
+
+#define PCIE_LINK_UP_TIMEOUT_MS 100
+
+#define PCIE_GLOBAL_CONTROL 0x8000
+#define PCIE_APP_LTSSM_EN (1 << 2)
+#define PCIE_DEVICE_TYPE_OFFSET (4)
+#define PCIE_DEVICE_TYPE_MASK (0xF)
+#define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
+#define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
+#define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
+
+#define PCIE_GLOBAL_STATUS 0x8008
+#define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
+#define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
+
+#define PCIE_ARCACHE_TRC 0x8050
+#define PCIE_AWCACHE_TRC 0x8054
+#define ARCACHE_SHAREABLE_CACHEABLE 0x3511
+#define AWCACHE_SHAREABLE_CACHEABLE 0x5311
+
+#define LINK_SPEED_GEN_1 0x1
+#define LINK_SPEED_GEN_2 0x2
+#define LINK_SPEED_GEN_3 0x3
+
+/**
+ * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
+ *
+ * @ctrl_base: The base address of the register space
+ * @cfg_base: The base address of the configuration space
+ * @cfg_size: The size of the configuration space which is needed
+ * as it gets written into the PCIE_ATU_LIMIT register
+ * @first_busno: This driver supports multiple PCIe controllers.
+ * first_busno stores the bus number of the PCIe root-port
+ * number which may vary depending on the PCIe setup
+ * (PEX switches etc).
+ */
+struct pcie_dw_mvebu {
+ void *ctrl_base;
+ void *cfg_base;
+ fdt_size_t cfg_size;
+ int first_busno;
+};
+
+static int pcie_dw_get_link_speed(const void *regs_base)
+{
+ return (readl(regs_base + PCIE_LINK_STATUS_REG) &
+ PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
+}
+
+static int pcie_dw_get_link_width(const void *regs_base)
+{
+ return (readl(regs_base + PCIE_LINK_STATUS_REG) &
+ PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
+}
+
+/**
+ * set_cfg_address() - Configure the PCIe controller config space access
+ *
+ * @pcie: Pointer to the PCI controller state
+ * @d: PCI device to access
+ * @where: Offset in the configuration space
+ *
+ * Configures the PCIe controller to access the configuration space of
+ * a specific PCIe device and returns the address to use for this
+ * access.
+ *
+ * Return: Address that can be used to access the configation space
+ * of the requested device / offset
+ */
+static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
+ pci_dev_t d, uint where)
+{
+ uintptr_t va_address;
+
+ /*
+ * Region #0 is used for Outbound CFG space access.
+ * Direction = Outbound
+ * Region Index = 0
+ */
+ writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT);
+
+ if (PCI_BUS(d) == (pcie->first_busno + 1))
+ /* For local bus, change TLP Type field to 4. */
+ writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1);
+ else
+ /* Otherwise, change TLP Type field to 5. */
+ writel(PCIE_ATU_TYPE_CFG1, pcie->ctrl_base + PCIE_ATU_CR1);
+
+ if (PCI_BUS(d) == pcie->first_busno) {
+ /* Accessing root port configuration space. */
+ va_address = (uintptr_t)pcie->ctrl_base;
+ } else {
+ writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
+ va_address = (uintptr_t)pcie->cfg_base;
+ }
+
+ va_address += where & ~0x3;
+
+ return va_address;
+}
+
+/**
+ * pcie_dw_addr_valid() - Check for valid bus address
+ *
+ * @d: The PCI device to access
+ * @first_busno: Bus number of the PCIe controller root complex
+ *
+ * Return 1 (true) if the PCI device can be accessed by this controller.
+ *
+ * Return: 1 on valid, 0 on invalid
+ */
+static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
+{
+ if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
+ return 0;
+ if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
+ return 0;
+
+ return 1;
+}
+
+/**
+ * pcie_dw_mvebu_read_config() - Read from configuration space
+ *
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ *
+ * Return: 0 on success
+ */
+static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
+ uintptr_t va_address;
+ ulong value;
+
+ debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+
+ if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
+ debug("- out of range\n");
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ va_address = set_cfg_address(pcie, bdf, offset);
+
+ value = readl(va_address);
+
+ debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
+ *valuep = pci_conv_32_to_size(value, offset, size);
+
+ return 0;
+}
+
+/**
+ * pcie_dw_mvebu_write_config() - Write to configuration space
+ *
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ *
+ * Return: 0 on success
+ */
+static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
+ uintptr_t va_address;
+ ulong old;
+
+ debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
+
+ if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
+ debug("- out of range\n");
+ return 0;
+ }
+
+ va_address = set_cfg_address(pcie, bdf, offset);
+
+ old = readl(va_address);
+ value = pci_conv_size_to_32(old, value, offset, size);
+ writel(value, va_address);
+
+ return 0;
+}
+
+/**
+ * pcie_dw_configure() - Configure link capabilities and speed
+ *
+ * @regs_base: A pointer to the PCIe controller registers
+ * @cap_speed: The capabilities and speed to configure
+ *
+ * Configure the link capabilities and speed in the PCIe root complex.
+ */
+static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
+{
+ /*
+ * TODO (shadi@marvell.com, sr@denx.de):
+ * Need to read the serdes speed from the dts and according to it
+ * configure the PCIe gen
+ */
+
+ /* Set link to GEN 3 */
+ clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
+ TARGET_LINK_SPEED_MASK, cap_speed);
+ clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
+ TARGET_LINK_SPEED_MASK, cap_speed);
+ setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
+}
+
+/**
+ * is_link_up() - Return the link state
+ *
+ * @regs_base: A pointer to the PCIe controller registers
+ *
+ * Return: 1 (true) for active line and 0 (false) for no link
+ */
+static int is_link_up(const void *regs_base)
+{
+ u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
+ u32 reg;
+
+ reg = readl(regs_base + PCIE_GLOBAL_STATUS);
+ if ((reg & mask) == mask)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * wait_link_up() - Wait for the link to come up
+ *
+ * @regs_base: A pointer to the PCIe controller registers
+ *
+ * Return: 1 (true) for active line and 0 (false) for no link (timeout)
+ */
+static int wait_link_up(const void *regs_base)
+{
+ unsigned long timeout;
+
+ timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
+ while (!is_link_up(regs_base)) {
+ if (get_timer(0) > timeout)
+ return 0;
+ };
+
+ return 1;
+}
+
+/**
+ * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
+ *
+ * @regs_base: A pointer to the PCIe controller registers
+ * @cap_speed: The capabilities and speed to configure
+ *
+ * Configure the PCIe controller root complex depending on the
+ * requested link capabilities and speed.
+ *
+ * Return: 1 (true) for active line and 0 (false) for no link
+ */
+static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
+{
+ if (!is_link_up(regs_base)) {
+ /* Disable LTSSM state machine to enable configuration */
+ clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
+ PCIE_APP_LTSSM_EN);
+ }
+
+ clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
+ PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
+ PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
+
+ /* Set the PCIe master AXI attributes */
+ writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
+ writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
+
+ /* DW pre link configurations */
+ pcie_dw_configure(regs_base, cap_speed);
+
+ if (!is_link_up(regs_base)) {
+ /* Configuration done. Start LTSSM */
+ setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
+ PCIE_APP_LTSSM_EN);
+ }
+
+ /* Check that link was established */
+ if (!wait_link_up(regs_base))
+ return 0;
+
+ /*
+ * Link can be established in Gen 1. still need to wait
+ * till MAC nagaotiation is completed
+ */
+ udelay(100);
+
+ return 1;
+}
+
+/**
+ * pcie_dw_regions_setup() - iATU region setup
+ *
+ * @pcie: Pointer to the PCI controller state
+ *
+ * Configure the iATU regions in the PCIe controller for outbound access.
+ */
+static void pcie_dw_regions_setup(struct pcie_dw_mvebu *pcie)
+{
+ /*
+ * Region #0 is used for Outbound CFG space access.
+ * Direction = Outbound
+ * Region Index = 0
+ */
+ writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT);
+
+ writel((u32)(uintptr_t)pcie->cfg_base, pcie->ctrl_base
+ + PCIE_ATU_LOWER_BASE);
+ writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
+ writel((u32)(uintptr_t)pcie->cfg_base + pcie->cfg_size,
+ pcie->ctrl_base + PCIE_ATU_LIMIT);
+
+ writel(0, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
+ writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
+ writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1);
+ writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
+}
+
+/**
+ * pcie_dw_set_host_bars() - Configure the host BARs
+ *
+ * @regs_base: A pointer to the PCIe controller registers
+ *
+ * Configure the host BARs of the PCIe controller root port so that
+ * PCI(e) devices may access the system memory.
+ */
+static void pcie_dw_set_host_bars(const void *regs_base)
+{
+ u32 size = gd->ram_size;
+ u64 max_size;
+ u32 reg;
+ u32 bar0;
+
+ /* Verify the maximal BAR size */
+ reg = readl(regs_base + RESIZABLE_BAR_CAP);
+ max_size = 1ULL << (5 + (reg + (1 << 4)));
+
+ if (size > max_size) {
+ size = max_size;
+ printf("Warning: PCIe BARs can't map all DRAM space\n");
+ }
+
+ /* Set the BAR base and size towards DDR */
+ bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
+ bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
+ writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
+
+ reg = ((size >> 20) - 1) << 12;
+ writel(size, regs_base + RESIZABLE_BAR_CTL0);
+}
+
+/**
+ * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
+ *
+ * @dev: A pointer to the device being operated on
+ *
+ * Probe for an active link on the PCIe bus and configure the controller
+ * to enable this port.
+ *
+ * Return: 0 on success, else -ENODEV
+ */
+static int pcie_dw_mvebu_probe(struct udevice *dev)
+{
+ struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+
+ pcie->first_busno = dev->seq;
+
+ /* Don't register host if link is down */
+ if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
+ printf("PCIE-%d: Link down\n", dev->seq);
+ return -ENODEV;
+ }
+
+ printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
+ pcie_dw_get_link_speed(pcie->ctrl_base),
+ pcie_dw_get_link_width(pcie->ctrl_base), hose->first_busno);
+
+ pcie_dw_regions_setup(pcie);
+
+ /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
+ clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
+ 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
+
+ pcie_dw_set_host_bars(pcie->ctrl_base);
+
+ return 0;
+}
+
+/**
+ * pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state
+ *
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev)
+{
+ struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
+
+ /* Get the controller base address */
+ pcie->ctrl_base = (void *)dev_get_addr_index(dev, 0);
+ if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Get the config space base address and size */
+ pcie->cfg_base = (void *)dev_get_addr_size_index(dev, 1,
+ &pcie->cfg_size);
+ if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops pcie_dw_mvebu_ops = {
+ .read_config = pcie_dw_mvebu_read_config,
+ .write_config = pcie_dw_mvebu_write_config,
+};
+
+static const struct udevice_id pcie_dw_mvebu_ids[] = {
+ { .compatible = "marvell,armada8k-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pcie_dw_mvebu) = {
+ .name = "pcie_dw_mvebu",
+ .id = UCLASS_PCI,
+ .of_match = pcie_dw_mvebu_ids,
+ .ops = &pcie_dw_mvebu_ops,
+ .ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata,
+ .probe = pcie_dw_mvebu_probe,
+ .priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu),
+};
diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
new file mode 100644
index 0000000..5216001
--- /dev/null
+++ b/drivers/pci/pcie_xilinx.c
@@ -0,0 +1,220 @@
+/*
+ * Xilinx AXI Bridge for PCI Express Driver
+ *
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+
+#include <asm/io.h>
+
+/**
+ * struct xilinx_pcie - Xilinx PCIe controller state
+ * @hose: The parent classes PCI controller state
+ * @cfg_base: The base address of memory mapped configuration space
+ */
+struct xilinx_pcie {
+ struct pci_controller hose;
+ void *cfg_base;
+};
+
+/* Register definitions */
+#define XILINX_PCIE_REG_PSCR 0x144
+#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
+
+/**
+ * pcie_xilinx_link_up() - Check whether the PCIe link is up
+ * @pcie: Pointer to the PCI controller state
+ *
+ * Checks whether the PCIe link for the given device is up or down.
+ *
+ * Return: true if the link is up, else false
+ */
+static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
+{
+ uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
+
+ return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
+}
+
+/**
+ * pcie_xilinx_config_address() - Calculate the address of a config access
+ * @pcie: Pointer to the PCI controller state
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @paddress: Pointer to the pointer to write the calculates address to
+ *
+ * Calculates the address that should be accessed to perform a PCIe
+ * configuration space access for a given device identified by the PCIe
+ * controller device @pcie and the bus, device & function numbers in @bdf. If
+ * access to the device is not valid then the function will return an error
+ * code. Otherwise the address to access will be written to the pointer pointed
+ * to by @paddress.
+ *
+ * Return: 0 on success, else -ENODEV
+ */
+static int pcie_xilinx_config_address(struct xilinx_pcie *pcie, pci_dev_t bdf,
+ uint offset, void **paddress)
+{
+ unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ unsigned int func = PCI_FUNC(bdf);
+ void *addr;
+
+ if ((bus > 0) && !pcie_xilinx_link_up(pcie))
+ return -ENODEV;
+
+ /*
+ * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
+ * limited to a single device each.
+ */
+ if ((bus < 2) && (dev > 0))
+ return -ENODEV;
+
+ addr = pcie->cfg_base;
+ addr += bus << 20;
+ addr += dev << 15;
+ addr += func << 12;
+ addr += offset;
+ *paddress = addr;
+
+ return 0;
+}
+
+/**
+ * pcie_xilinx_read_config() - Read from configuration space
+ * @pcie: Pointer to the PCI controller state
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ *
+ * Return: 0 on success, else -ENODEV or -EINVAL
+ */
+static int pcie_xilinx_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct xilinx_pcie *pcie = dev_get_priv(bus);
+ void *address;
+ int err;
+
+ err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
+ if (err < 0) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = __raw_readb(address);
+ return 0;
+ case PCI_SIZE_16:
+ *valuep = __raw_readw(address);
+ return 0;
+ case PCI_SIZE_32:
+ *valuep = __raw_readl(address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+/**
+ * pcie_xilinx_write_config() - Write to configuration space
+ * @pcie: Pointer to the PCI controller state
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ *
+ * Return: 0 on success, else -ENODEV or -EINVAL
+ */
+static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct xilinx_pcie *pcie = dev_get_priv(bus);
+ void *address;
+ int err;
+
+ err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
+ if (err < 0)
+ return 0;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ __raw_writeb(value, address);
+ return 0;
+ case PCI_SIZE_16:
+ __raw_writew(value, address);
+ return 0;
+ case PCI_SIZE_32:
+ __raw_writel(value, address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+/**
+ * pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pcie_xilinx_ofdata_to_platdata(struct udevice *dev)
+{
+ struct xilinx_pcie *pcie = dev_get_priv(dev);
+ struct fdt_resource reg_res;
+ DECLARE_GLOBAL_DATA_PTR;
+ int err;
+
+ err = fdt_get_resource(gd->fdt_blob, dev->of_offset, "reg",
+ 0, ®_res);
+ if (err < 0) {
+ error("\"reg\" resource not found\n");
+ return err;
+ }
+
+ pcie->cfg_base = map_physmem(reg_res.start,
+ fdt_resource_size(®_res),
+ MAP_NOCACHE);
+
+ return 0;
+}
+
+static const struct dm_pci_ops pcie_xilinx_ops = {
+ .read_config = pcie_xilinx_read_config,
+ .write_config = pcie_xilinx_write_config,
+};
+
+static const struct udevice_id pcie_xilinx_ids[] = {
+ { .compatible = "xlnx,axi-pcie-host-1.00.a" },
+ { }
+};
+
+U_BOOT_DRIVER(pcie_xilinx) = {
+ .name = "pcie_xilinx",
+ .id = UCLASS_PCI,
+ .of_match = pcie_xilinx_ids,
+ .ops = &pcie_xilinx_ops,
+ .ofdata_to_platdata = pcie_xilinx_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct xilinx_pcie),
+};
diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig
new file mode 100644
index 0000000..4240028
--- /dev/null
+++ b/drivers/phy/marvell/Kconfig
@@ -0,0 +1,9 @@
+config MVEBU_COMPHY_SUPPORT
+ bool "ComPhy SerDes driver"
+ default n
+ help
+ Choose this option to add support
+ for Comphy driver.
+ This driver passes over the lanes
+ and initialize the lane depends on the
+ type and speed.
diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile
new file mode 100644
index 0000000..f181505
--- /dev/null
+++ b/drivers/phy/marvell/Makefile
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_core.o
+obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_mux.o
+obj-$(CONFIG_ARMADA_3700) += comphy_a3700.o
+obj-$(CONFIG_ARMADA_8K) += comphy_cp110.o
diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h
new file mode 100644
index 0000000..0a15692
--- /dev/null
+++ b/drivers/phy/marvell/comphy.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _COMPHY_H_
+#define _COMPHY_H_
+
+#include <dt-bindings/comphy/comphy_data.h>
+#include <fdtdec.h>
+
+#if defined(DEBUG)
+#define debug_enter() printf("----> Enter %s\n", __func__);
+#define debug_exit() printf("<---- Exit %s\n", __func__);
+#else
+#define debug_enter()
+#define debug_exit()
+#endif
+
+/* COMPHY registers */
+#define COMMON_PHY_CFG1_REG 0x0
+#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
+#define COMMON_PHY_CFG1_PWR_UP_MASK \
+ (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
+#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
+#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
+ (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
+#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
+#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
+ (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
+#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
+#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
+ (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
+#define COMMON_PHY_PHY_MODE_OFFSET 15
+#define COMMON_PHY_PHY_MODE_MASK \
+ (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
+
+#define COMMON_PHY_CFG6_REG 0x14
+#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
+#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
+ (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
+
+#define COMMON_SELECTOR_PHY_OFFSET 0x140
+#define COMMON_SELECTOR_PIPE_OFFSET 0x144
+
+#define COMMON_PHY_SD_CTRL1 0x148
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
+#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
+#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
+ (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
+#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
+#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
+ (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
+#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
+#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
+ (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
+#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
+#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
+ (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
+
+/* ToDo: Get this address via DT */
+#define MVEBU_CP0_REGS_BASE 0xF2000000UL
+
+#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
+#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
+#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
+ (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
+
+#define MAX_LANE_OPTIONS 10
+#define MAX_UTMI_PHY_COUNT 3
+
+struct comphy_mux_options {
+ u32 type;
+ u32 mux_value;
+};
+
+struct comphy_mux_data {
+ u32 max_lane_values;
+ struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
+};
+
+struct comphy_map {
+ u32 type;
+ u32 speed;
+ u32 invert;
+ bool clk_src;
+};
+
+struct chip_serdes_phy_config {
+ struct comphy_mux_data *mux_data;
+ int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
+ struct comphy_map *);
+ void __iomem *comphy_base_addr;
+ void __iomem *hpipe3_base_addr;
+ u32 comphy_lanes_count;
+ u32 comphy_mux_bitcount;
+ u32 comphy_index;
+};
+
+/* Register helper functions */
+void reg_set(void __iomem *addr, u32 data, u32 mask);
+void reg_set_silent(void __iomem *addr, u32 data, u32 mask);
+void reg_set16(void __iomem *addr, u16 data, u16 mask);
+void reg_set_silent16(void __iomem *addr, u16 data, u16 mask);
+
+/* SoC specific init functions */
+#ifdef CONFIG_ARMADA_3700
+int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map);
+#else
+static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_ARMADA_8K
+int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map);
+#else
+static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
+#endif
+
+void comphy_dedicated_phys_init(void);
+
+/* MUX function */
+void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *comphy_map_data,
+ void __iomem *selector_base);
+
+void comphy_pcie_config_set(u32 comphy_max_count,
+ struct comphy_map *serdes_map);
+void comphy_pcie_config_detect(u32 comphy_max_count,
+ struct comphy_map *serdes_map);
+void comphy_pcie_unit_general_config(u32 pex_index);
+
+#endif /* _COMPHY_H_ */
+
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
new file mode 100644
index 0000000..faa62f9
--- /dev/null
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -0,0 +1,962 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "comphy_a3700.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sgmii_phy_init_data_fix {
+ u16 addr;
+ u16 value;
+};
+
+/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
+static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = {
+ {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
+ {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
+ {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
+ {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
+ {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
+ {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
+ {0x104, 0x0C10}
+};
+
+/* 40M1G25 mode init data */
+static u16 sgmii_phy_init[512] = {
+ /* 0 1 2 3 4 5 6 7 */
+ /*-----------------------------------------------------------*/
+ /* 8 9 A B C D E F */
+ 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
+ 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
+ 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
+ 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
+ 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
+ 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
+ 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
+ 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
+ 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
+ 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
+ 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
+ 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
+ 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
+ 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
+ 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
+ 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
+ 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
+ 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
+ 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
+ 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
+ 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
+ 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
+ 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
+ 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
+ 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
+ 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
+ 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
+ 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
+ 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
+ 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
+ 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
+ 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
+ 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
+ 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
+};
+
+/*
+ * comphy_poll_reg
+ *
+ * return: 1 on success, 0 on timeout
+ */
+static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u32 timeout,
+ u8 op_type)
+{
+ u32 rval = 0xDEAD;
+
+ for (; timeout > 0; timeout--) {
+ if (op_type == POLL_16B_REG)
+ rval = readw(addr); /* 16 bit */
+ else
+ rval = readl(addr) ; /* 32 bit */
+
+ if ((rval & mask) == val)
+ return 1;
+
+ udelay(10000);
+ }
+
+ debug("Time out waiting (%p = %#010x)\n", addr, rval);
+ return 0;
+}
+
+/*
+ * comphy_pcie_power_up
+ *
+ * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
+ */
+static int comphy_pcie_power_up(u32 speed, u32 invert)
+{
+ int ret;
+
+ debug_enter();
+
+ /*
+ * 1. Enable max PLL.
+ */
+ reg_set16((void __iomem *)LANE_CFG1_ADDR(PCIE),
+ bf_use_max_pll_rate, 0);
+
+ /*
+ * 2. Select 20 bit SERDES interface.
+ */
+ reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(PCIE),
+ bf_cfg_sel_20b, 0);
+
+ /*
+ * 3. Force to use reg setting for PCIe mode
+ */
+ reg_set16((void __iomem *)MISC_REG1_ADDR(PCIE),
+ bf_sel_bits_pcie_force, 0);
+
+ /*
+ * 4. Change RX wait
+ */
+ reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF);
+
+ /*
+ * 5. Enable idle sync
+ */
+ reg_set16((void __iomem *)UNIT_CTRL_ADDR(PCIE),
+ 0x60 | rb_idle_sync_en, 0xFFFF);
+
+ /*
+ * 6. Enable the output of 100M/125M/500M clock
+ */
+ reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE),
+ 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
+
+ /*
+ * 7. Enable TX
+ */
+ reg_set((void __iomem *)PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
+
+ /*
+ * 8. Check crystal jumper setting and program the Power and PLL
+ * Control accordingly
+ */
+ if (get_ref_clk() == 40) {
+ reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE),
+ 0xFC63, 0xFFFF); /* 40 MHz */
+ } else {
+ reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE),
+ 0xFC62, 0xFFFF); /* 25 MHz */
+ }
+
+ /*
+ * 9. Override Speed_PLL value and use MAC PLL
+ */
+ reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(PCIE),
+ 0x0040 | rb_use_max_pll_rate, 0xFFFF);
+
+ /*
+ * 10. Check the Polarity invert bit
+ */
+ if (invert & PHY_POLARITY_TXD_INVERT) {
+ reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE),
+ phy_txd_inv, 0);
+ }
+
+ if (invert & PHY_POLARITY_RXD_INVERT) {
+ reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE),
+ phy_rxd_inv, 0);
+ }
+
+ /*
+ * 11. Release SW reset
+ */
+ reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(PCIE),
+ rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
+ bf_soft_rst | bf_mode_refdiv);
+
+ /* Wait for > 55 us to allow PCLK be enabled */
+ udelay(PLL_SET_DELAY_US);
+
+ /* Assert PCLK enabled */
+ ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(PCIE), /* address */
+ rb_txdclk_pclk_en, /* value */
+ rb_txdclk_pclk_en, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_16B_REG); /* 16bit */
+ if (ret == 0)
+ printf("Failed to lock PCIe PLL\n");
+
+ debug_exit();
+
+ /* Return the status of the PLL */
+ return ret;
+}
+
+/*
+ * comphy_sata_power_up
+ *
+ * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
+ */
+static int comphy_sata_power_up(void)
+{
+ int ret;
+
+ debug_enter();
+
+ /*
+ * 0. Swap SATA TX lines
+ */
+ reg_set((void __iomem *)rh_vsreg_addr,
+ vphy_sync_pattern_reg, 0xFFFFFFFF);
+ reg_set((void __iomem *)rh_vsreg_data, bs_txd_inv, bs_txd_inv);
+
+ /*
+ * 1. Select 40-bit data width width
+ */
+ reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);
+ reg_set((void __iomem *)rh_vsreg_data, 0x800, bs_phyintf_40bit);
+
+ /*
+ * 2. Select reference clock and PHY mode (SATA)
+ */
+ reg_set((void __iomem *)rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF);
+ if (get_ref_clk() == 40) {
+ reg_set((void __iomem *)rh_vsreg_data,
+ 0x3, 0x00FF); /* 40 MHz */
+ } else {
+ reg_set((void __iomem *)rh_vsreg_data,
+ 0x1, 0x00FF); /* 25 MHz */
+ }
+
+ /*
+ * 3. Use maximum PLL rate (no power save)
+ */
+ reg_set((void __iomem *)rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF);
+ reg_set((void __iomem *)rh_vsreg_data,
+ bs_max_pll_rate, bs_max_pll_rate);
+
+ /*
+ * 4. Reset reserved bit (??)
+ */
+ reg_set((void __iomem *)rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF);
+ reg_set((void __iomem *)rh_vsreg_data, 0, bs_phyctrl_frm_pin);
+
+ /*
+ * 5. Set vendor-specific configuration (??)
+ */
+ reg_set((void __iomem *)rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF);
+ reg_set((void __iomem *)rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll);
+
+ /* Wait for > 55 us to allow PLL be enabled */
+ udelay(PLL_SET_DELAY_US);
+
+ /* Assert SATA PLL enabled */
+ reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);
+ ret = comphy_poll_reg((void *)rh_vsreg_data, /* address */
+ bs_pll_ready_tx, /* value */
+ bs_pll_ready_tx, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_32B_REG); /* 32bit */
+ if (ret == 0)
+ printf("Failed to lock SATA PLL\n");
+
+ debug_exit();
+
+ return ret;
+}
+
+/*
+ * comphy_usb3_power_up
+ *
+ * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
+ */
+static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
+{
+ int ret;
+
+ debug_enter();
+
+ /*
+ * 1. Power up OTG module
+ */
+ reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
+
+ /*
+ * 2. Set counter for 100us pulse in USB3 Host and Device
+ * restore default burst size limit (Reference Clock 31:24)
+ */
+ reg_set((void __iomem *)USB3_CTRPUL_VAL_REG,
+ 0x8 << 24, rb_usb3_ctr_100ns);
+
+
+ /* 0xd005c300 = 0x1001 */
+ /* set PRD_TXDEEMPH (3.5db de-emph) */
+ reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF);
+
+ /*
+ * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in
+ * low impedance mode during electrical idle
+ */
+ /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */
+ /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */
+ reg_set16((void __iomem *)LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF);
+
+
+ /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
+ reg_set16((void __iomem *)LANE_CFG4_ADDR(USB3),
+ bf_spread_spectrum_clock_en, 0x80);
+
+ /*
+ * set Override Margining Controls From the MAC: Use margining signals
+ * from lane configuration
+ */
+ reg_set16((void __iomem *)TEST_MODE_CTRL_ADDR(USB3),
+ rb_mode_margin_override, 0xFFFF);
+
+ /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
+ /* set Mode Clock Source = PCLK is generated from REFCLK */
+ reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF);
+
+ /* set G2 Spread Spectrum Clock Amplitude at 4K */
+ reg_set16((void __iomem *)GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp,
+ 0xF000);
+
+ /*
+ * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
+ * Master Current Select
+ */
+ reg_set16((void __iomem *)GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF);
+
+ /*
+ * 3. Check crystal jumper setting and program the Power and PLL
+ * Control accordingly
+ */
+ if (get_ref_clk() == 40) {
+ reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA3,
+ 0xFFFF); /* 40 MHz */
+ } else {
+ reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA2,
+ 0xFFFF); /* 25 MHz */
+ }
+
+ /*
+ * 4. Change RX wait
+ */
+ reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF);
+
+ /*
+ * 5. Enable idle sync
+ */
+ reg_set16((void __iomem *)UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en,
+ 0xFFFF);
+
+ /*
+ * 6. Enable the output of 500M clock
+ */
+ reg_set16((void __iomem *)MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en,
+ 0xFFFF);
+
+ /*
+ * 7. Set 20-bit data width
+ */
+ reg_set16((void __iomem *)DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF);
+
+ /*
+ * 8. Override Speed_PLL value and use MAC PLL
+ */
+ reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(USB3),
+ 0x0040 | rb_use_max_pll_rate, 0xFFFF);
+
+ /*
+ * 9. Check the Polarity invert bit
+ */
+ if (invert & PHY_POLARITY_TXD_INVERT) {
+ reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3),
+ phy_txd_inv, 0);
+ }
+
+ if (invert & PHY_POLARITY_RXD_INVERT) {
+ reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3),
+ phy_rxd_inv, 0);
+ }
+
+ /*
+ * 10. Release SW reset
+ */
+ reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(USB3),
+ rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20,
+ 0xFFFF);
+
+ /* Wait for > 55 us to allow PCLK be enabled */
+ udelay(PLL_SET_DELAY_US);
+
+ /* Assert PCLK enabled */
+ ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(USB3), /* address */
+ rb_txdclk_pclk_en, /* value */
+ rb_txdclk_pclk_en, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_16B_REG); /* 16bit */
+ if (ret == 0)
+ printf("Failed to lock USB3 PLL\n");
+
+ /*
+ * Set Soft ID for Host mode (Device mode works with Hard ID
+ * detection)
+ */
+ if (type == PHY_TYPE_USB3_HOST0) {
+ /*
+ * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
+ * clear BIT1: set SOFT_ID = Host
+ * set BIT4: set INT_MODE = ID. Interrupt Mode: enable
+ * interrupt by ID instead of using both interrupts
+ * of HOST and Device ORed simultaneously
+ * INT_MODE=ID in order to avoid unexpected
+ * behaviour or both interrupts together
+ */
+ reg_set((void __iomem *)USB32_CTRL_BASE,
+ usb32_ctrl_id_mode | usb32_ctrl_int_mode,
+ usb32_ctrl_id_mode | usb32_ctrl_soft_id |
+ usb32_ctrl_int_mode);
+ }
+
+ debug_exit();
+
+ return ret;
+}
+
+/*
+ * comphy_usb2_power_up
+ *
+ * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
+ */
+static int comphy_usb2_power_up(u8 usb32)
+{
+ int ret;
+
+ debug_enter();
+
+ if (usb32 != 0 && usb32 != 1) {
+ printf("invalid usb32 value: (%d), should be either 0 or 1\n",
+ usb32);
+ debug_exit();
+ return 0;
+ }
+
+ /*
+ * 0. Setup PLL. 40MHz clock uses defaults.
+ * See "PLL Settings for Typical REFCLK" table
+ */
+ if (get_ref_clk() == 25) {
+ reg_set((void __iomem *)USB2_PHY_BASE(usb32),
+ 5 | (96 << 16), 0x3F | (0xFF << 16) | (0x3 << 28));
+ }
+
+ /*
+ * 1. PHY pull up and disable USB2 suspend
+ */
+ reg_set((void __iomem *)USB2_PHY_CTRL_ADDR(usb32),
+ RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0);
+
+ if (usb32 != 0) {
+ /*
+ * 2. Power up OTG module
+ */
+ reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
+
+ /*
+ * 3. Configure PHY charger detection
+ */
+ reg_set((void __iomem *)USB2_PHY_CHRGR_DET_ADDR, 0,
+ rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto |
+ rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc);
+ }
+
+ /* Assert PLL calibration done */
+ ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32),
+ rb_usb2phy_pllcal_done, /* value */
+ rb_usb2phy_pllcal_done, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_32B_REG); /* 32bit */
+ if (ret == 0)
+ printf("Failed to end USB2 PLL calibration\n");
+
+ /* Assert impedance calibration done */
+ ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32),
+ rb_usb2phy_impcal_done, /* value */
+ rb_usb2phy_impcal_done, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_32B_REG); /* 32bit */
+ if (ret == 0)
+ printf("Failed to end USB2 impedance calibration\n");
+
+ /* Assert squetch calibration done */
+ ret = comphy_poll_reg((void *)USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
+ rb_usb2phy_sqcal_done, /* value */
+ rb_usb2phy_sqcal_done, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_32B_REG); /* 32bit */
+ if (ret == 0)
+ printf("Failed to end USB2 unknown calibration\n");
+
+ /* Assert PLL is ready */
+ ret = comphy_poll_reg((void *)USB2_PHY_PLL_CTRL0_ADDR(usb32),
+ rb_usb2phy_pll_ready, /* value */
+ rb_usb2phy_pll_ready, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_32B_REG); /* 32bit */
+
+ if (ret == 0)
+ printf("Failed to lock USB2 PLL\n");
+
+ debug_exit();
+
+ return ret;
+}
+
+/*
+ * comphy_emmc_power_up
+ *
+ * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
+ */
+static int comphy_emmc_power_up(void)
+{
+ debug_enter();
+
+ /*
+ * 1. Bus power ON, Bus voltage 1.8V
+ */
+ reg_set((void __iomem *)SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00);
+
+ /*
+ * 2. Set FIFO parameters
+ */
+ reg_set((void __iomem *)SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF);
+
+ /*
+ * 3. Set Capabilities 1_2
+ */
+ reg_set((void __iomem *)SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF);
+
+ /*
+ * 4. Set Endian
+ */
+ reg_set((void __iomem *)SDIO_ENDIAN_ADDR, 0x00c00000, 0);
+
+ /*
+ * 4. Init PHY
+ */
+ reg_set((void __iomem *)SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000);
+ reg_set((void __iomem *)SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000,
+ 0xF0000000);
+
+ /*
+ * 5. DLL reset
+ */
+ reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0);
+ reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0x00010000, 0);
+
+ debug_exit();
+
+ return 1;
+}
+
+/*
+ * comphy_sgmii_power_up
+ *
+ * return:
+ */
+static void comphy_sgmii_phy_init(u32 lane, u32 speed)
+{
+ const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix);
+ int addr, fix_idx;
+ u16 val;
+
+ fix_idx = 0;
+ for (addr = 0; addr < 512; addr++) {
+ /*
+ * All PHY register values are defined in full for 3.125Gbps
+ * SERDES speed. The values required for 1.25 Gbps are almost
+ * the same and only few registers should be "fixed" in
+ * comparison to 3.125 Gbps values. These register values are
+ * stored in "sgmii_phy_init_fix" array.
+ */
+ if ((speed != PHY_SPEED_1_25G) &&
+ (sgmii_phy_init_fix[fix_idx].addr == addr)) {
+ /* Use new value */
+ val = sgmii_phy_init_fix[fix_idx].value;
+ if (fix_idx < fix_arr_sz)
+ fix_idx++;
+ } else {
+ val = sgmii_phy_init[addr];
+ }
+
+ phy_write16(lane, addr, val, 0xFFFF);
+ }
+}
+
+/*
+ * comphy_sgmii_power_up
+ *
+ * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
+ */
+static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
+{
+ int ret;
+
+ debug_enter();
+
+ /*
+ * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0
+ */
+ reg_set((void __iomem *)COMPHY_SEL_ADDR, 0, rf_compy_select(lane));
+
+ /*
+ * 2. Reset PHY by setting PHY input port PIN_RESET=1.
+ * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
+ * PHY TXP/TXN output to idle state during PHY initialization
+ * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
+ */
+ reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
+ rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref,
+ rb_pin_reset_core | rb_pin_pu_pll |
+ rb_pin_pu_rx | rb_pin_pu_tx);
+
+ /*
+ * 5. Release reset to the PHY by setting PIN_RESET=0.
+ */
+ reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
+ 0, rb_pin_reset_comphy);
+
+ /*
+ * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
+ * COMPHY bit rate
+ */
+ if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */
+ reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
+ (0x8 << rf_gen_rx_sel_shift) |
+ (0x8 << rf_gen_tx_sel_shift),
+ rf_gen_rx_select | rf_gen_tx_select);
+
+ } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */
+ reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
+ (0x6 << rf_gen_rx_sel_shift) |
+ (0x6 << rf_gen_tx_sel_shift),
+ rf_gen_rx_select | rf_gen_tx_select);
+ } else {
+ printf("Unsupported COMPHY speed!\n");
+ return 0;
+ }
+
+ /*
+ * 8. Wait 1mS for bandgap and reference clocks to stabilize;
+ * then start SW programming.
+ */
+ mdelay(10);
+
+ /* 9. Program COMPHY register PHY_MODE */
+ phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
+ PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
+
+ /*
+ * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
+ * source
+ */
+ phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel);
+
+ /*
+ * 11. Set correct reference clock frequency in COMPHY register
+ * REF_FREF_SEL.
+ */
+ if (get_ref_clk() == 40) {
+ phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
+ 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
+ } else {
+ /* 25MHz */
+ phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
+ 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
+ }
+
+ /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */
+ /*
+ * This step is mentioned in the flow received from verification team.
+ * However the PHY_GEN_MAX value is only meaningful for other
+ * interfaces (not SGMII). For instance, it selects SATA speed
+ * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps
+ */
+
+ /*
+ * 13. Program COMPHY register SEL_BITS to set correct parallel data
+ * bus width
+ */
+ /* 10bit */
+ phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask);
+
+ /*
+ * 14. As long as DFE function needs to be enabled in any mode,
+ * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
+ * for real chip during COMPHY power on.
+ */
+ /*
+ * The step 14 exists (and empty) in the original initialization flow
+ * obtained from the verification team. According to the functional
+ * specification DFE_UPDATE_EN already has the default value 0x3F
+ */
+
+ /*
+ * 15. Program COMPHY GEN registers.
+ * These registers should be programmed based on the lab testing
+ * result to achieve optimal performance. Please contact the CEA
+ * group to get the related GEN table during real chip bring-up.
+ * We only requred to run though the entire registers programming
+ * flow defined by "comphy_sgmii_phy_init" when the REF clock is
+ * 40 MHz. For REF clock 25 MHz the default values stored in PHY
+ * registers are OK.
+ */
+ debug("Running C-DPI phy init %s mode\n",
+ speed == PHY_SPEED_3_125G ? "2G5" : "1G");
+ if (get_ref_clk() == 40)
+ comphy_sgmii_phy_init(lane, speed);
+
+ /*
+ * 16. [Simulation Only] should not be used for real chip.
+ * By pass power up calibration by programming EXT_FORCE_CAL_DONE
+ * (R02h[9]) to 1 to shorten COMPHY simulation time.
+ */
+ /*
+ * 17. [Simulation Only: should not be used for real chip]
+ * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX
+ * training simulation time.
+ */
+
+ /*
+ * 18. Check the PHY Polarity invert bit
+ */
+ if (invert & PHY_POLARITY_TXD_INVERT)
+ phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0);
+
+ if (invert & PHY_POLARITY_RXD_INVERT)
+ phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0);
+
+ /*
+ * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
+ * to start PHY power up sequence. All the PHY register
+ * programming should be done before PIN_PU_PLL=1. There should be
+ * no register programming for normal PHY operation from this point.
+ */
+ reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
+ rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx,
+ rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx);
+
+ /*
+ * 20. Wait for PHY power up sequence to finish by checking output ports
+ * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
+ */
+ ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */
+ rb_pll_ready_tx | rb_pll_ready_rx, /* value */
+ rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_32B_REG); /* 32bit */
+ if (ret == 0)
+ printf("Failed to lock PLL for SGMII PHY %d\n", lane);
+
+ /*
+ * 21. Set COMPHY input port PIN_TX_IDLE=0
+ */
+ reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),
+ 0x0, rb_pin_tx_idle);
+
+ /*
+ * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1.
+ * to start RX initialization. PIN_RX_INIT_DONE will be cleared to
+ * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE
+ * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after
+ * PIN_RX_INIT_DONE= 1.
+ * Please refer to RX initialization part for details.
+ */
+ reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init,
+ 0x0);
+
+ ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */
+ rb_rx_init_done, /* value */
+ rb_rx_init_done, /* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_32B_REG); /* 32bit */
+ if (ret == 0)
+ printf("Failed to init RX of SGMII PHY %d\n", lane);
+
+ debug_exit();
+
+ return ret;
+}
+
+void comphy_dedicated_phys_init(void)
+{
+ int node, usb32, ret = 1;
+ const void *blob = gd->fdt_blob;
+
+ debug_enter();
+
+ for (usb32 = 0; usb32 <= 1; usb32++) {
+ /*
+ * There are 2 UTMI PHYs in this SOC.
+ * One is independendent and one is paired with USB3 port (OTG)
+ */
+ if (usb32 == 0) {
+ node = fdt_node_offset_by_compatible(
+ blob, -1, "marvell,armada-3700-ehci");
+ } else {
+ node = fdt_node_offset_by_compatible(
+ blob, -1, "marvell,armada3700-xhci");
+ }
+
+ if (node > 0) {
+ if (fdtdec_get_is_enabled(blob, node)) {
+ ret = comphy_usb2_power_up(usb32);
+ if (ret == 0)
+ printf("Failed to initialize UTMI PHY\n");
+ else
+ debug("UTMI PHY init succeed\n");
+ } else {
+ debug("USB%d node is disabled\n",
+ usb32 == 0 ? 2 : 3);
+ }
+ } else {
+ debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3);
+ }
+ }
+
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "marvell,armada-3700-ahci");
+ if (node > 0) {
+ if (fdtdec_get_is_enabled(blob, node)) {
+ ret = comphy_sata_power_up();
+ if (ret == 0)
+ printf("Failed to initialize SATA PHY\n");
+ else
+ debug("SATA PHY init succeed\n");
+ } else {
+ debug("SATA node is disabled\n");
+ }
+ } else {
+ debug("No SATA node in DT\n");
+ }
+
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "marvell,armada-3700-sdio");
+ if (node <= 0) {
+ debug("No SDIO node in DT, looking for MMC one\n");
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "marvell,xenon-sdhci");
+ }
+
+ if (node > 0) {
+ if (fdtdec_get_is_enabled(blob, node)) {
+ ret = comphy_emmc_power_up();
+ if (ret == 0)
+ printf("Failed to initialize SDIO/eMMC PHY\n");
+ else
+ debug("SDIO/eMMC PHY init succeed\n");
+ } else {
+ debug("SDIO/eMMC node is disabled\n");
+ }
+ } else {
+ debug("No SDIO/eMMC node in DT\n");
+ }
+
+ debug_exit();
+}
+
+int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
+ struct comphy_map *serdes_map)
+{
+ struct comphy_map *comphy_map;
+ u32 comphy_max_count = chip_cfg->comphy_lanes_count;
+ u32 lane, ret = 0;
+
+ debug_enter();
+
+ for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;
+ lane++, comphy_map++) {
+ debug("Initialize serdes number %d\n", lane);
+ debug("Serdes type = 0x%x invert=%d\n",
+ comphy_map->type, comphy_map->invert);
+
+ switch (comphy_map->type) {
+ case PHY_TYPE_UNCONNECTED:
+ continue;
+ break;
+
+ case PHY_TYPE_PEX0:
+ ret = comphy_pcie_power_up(comphy_map->speed,
+ comphy_map->invert);
+ break;
+
+ case PHY_TYPE_USB3_HOST0:
+ case PHY_TYPE_USB3_DEVICE:
+ ret = comphy_usb3_power_up(comphy_map->type,
+ comphy_map->speed,
+ comphy_map->invert);
+ break;
+
+ case PHY_TYPE_SGMII0:
+ case PHY_TYPE_SGMII1:
+ ret = comphy_sgmii_power_up(lane, comphy_map->speed,
+ comphy_map->invert);
+ break;
+
+ default:
+ debug("Unknown SerDes type, skip initialize SerDes %d\n",
+ lane);
+ ret = 1;
+ break;
+ }
+ if (ret == 0)
+ printf("PLL is not locked - Failed to initialize lane %d\n",
+ lane);
+ }
+
+ debug_exit();
+ return ret;
+}
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
new file mode 100644
index 0000000..dd60b88
--- /dev/null
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -0,0 +1,275 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _COMPHY_A3700_H_
+#define _COMPHY_A3700_H_
+
+#include "comphy.h"
+#include "comphy_hpipe.h"
+
+#define MVEBU_REG(offs) ((uintptr_t)MVEBU_REGISTER(offs))
+
+#define DEFAULT_REFCLK_MHZ 25
+#define PLL_SET_DELAY_US 600
+#define PLL_LOCK_TIMEOUT 1000
+#define POLL_16B_REG 1
+#define POLL_32B_REG 0
+
+/*
+ * COMPHY SB definitions
+ */
+#define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC)
+#define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0))
+
+#define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28)
+#define rb_pin_pu_iveref BIT(1)
+#define rb_pin_reset_core BIT(11)
+#define rb_pin_reset_comphy BIT(12)
+#define rb_pin_pu_pll BIT(16)
+#define rb_pin_pu_rx BIT(17)
+#define rb_pin_pu_tx BIT(18)
+#define rb_pin_tx_idle BIT(19)
+#define rf_gen_rx_sel_shift 22
+#define rf_gen_rx_select (0x0F << rf_gen_rx_sel_shift)
+#define rf_gen_tx_sel_shift 26
+#define rf_gen_tx_select (0x0F << rf_gen_tx_sel_shift)
+#define rb_phy_rx_init BIT(30)
+
+#define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (lane) * 0x28)
+#define rb_rx_init_done BIT(0)
+#define rb_pll_ready_rx BIT(2)
+#define rb_pll_ready_tx BIT(3)
+
+/*
+ * PCIe/USB/SGMII definitions
+ */
+#define PCIE_BASE MVEBU_REG(0x070000)
+#define PCIETOP_BASE MVEBU_REG(0x080000)
+#define PCIE_RAMBASE MVEBU_REG(0x08C000)
+#define PCIEPHY_BASE MVEBU_REG(0x01F000)
+#define PCIEPHY_SHFT 2
+
+#define USB32_BASE MVEBU_REG(0x050000) /* usb3 device */
+#define USB32H_BASE MVEBU_REG(0x058000) /* usb3 host */
+#define USB3PHY_BASE MVEBU_REG(0x05C000)
+#define USB2PHY_BASE MVEBU_REG(0x05D000)
+#define USB2PHY2_BASE MVEBU_REG(0x05F000)
+#define USB32_CTRL_BASE MVEBU_REG(0x05D800)
+#define USB3PHY_SHFT 2
+
+#define SGMIIPHY_BASE(l) (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE)
+#define SGMIIPHY_ADDR(l, a) (((a & 0x00007FF) * 2) | SGMIIPHY_BASE(l))
+
+#define phy_read16(l, a) read16((void __iomem *)SGMIIPHY_ADDR(l, a))
+#define phy_write16(l, a, data, mask) \
+ reg_set16((void __iomem *)SGMIIPHY_ADDR(l, a), data, mask)
+
+/* units */
+#define PCIE 1
+#define USB3 2
+
+#define PHY_BASE(unit) ((unit == PCIE) ? PCIEPHY_BASE : USB3PHY_BASE)
+#define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT)
+
+/* bit definition for USB32_CTRL_BASE (USB32 Control Mode) */
+#define usb32_ctrl_id_mode BIT(0)
+#define usb32_ctrl_soft_id BIT(1)
+#define usb32_ctrl_int_mode BIT(4)
+
+
+#define PHY_PWR_PLL_CTRL_ADDR 0x01 /* for phy_read16 and phy_write16 */
+#define PWR_PLL_CTRL_ADDR(unit) \
+ (PHY_PWR_PLL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
+#define rf_phy_mode_shift 5
+#define rf_phy_mode_mask (0x7 << rf_phy_mode_shift)
+#define rf_ref_freq_sel_shift 0
+#define rf_ref_freq_sel_mask (0x1F << rf_ref_freq_sel_shift)
+#define PHY_MODE_SGMII 0x4
+
+/* for phy_read16 and phy_write16 */
+#define PHY_REG_KVCO_CAL_CTRL_ADDR 0x02
+#define KVCO_CAL_CTRL_ADDR(unit) \
+ (PHY_REG_KVCO_CAL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
+#define rb_use_max_pll_rate BIT(12)
+#define rb_force_calibration_done BIT(9)
+
+/* for phy_read16 and phy_write16 */
+#define PHY_DIG_LB_EN_ADDR 0x23
+#define DIG_LB_EN_ADDR(unit) \
+ (PHY_DIG_LB_EN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
+#define rf_data_width_shift 10
+#define rf_data_width_mask (0x3 << rf_data_width_shift)
+
+/* for phy_read16 and phy_write16 */
+#define PHY_SYNC_PATTERN_ADDR 0x24
+#define SYNC_PATTERN_ADDR(unit) \
+ (PHY_SYNC_PATTERN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
+#define phy_txd_inv BIT(10)
+#define phy_rxd_inv BIT(11)
+
+/* for phy_read16 and phy_write16 */
+#define PHY_REG_UNIT_CTRL_ADDR 0x48
+#define UNIT_CTRL_ADDR(unit) \
+ (PHY_REG_UNIT_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
+#define rb_idle_sync_en BIT(12)
+
+/* for phy_read16 and phy_write16 */
+#define PHY_REG_GEN2_SETTINGS_2 0x3e
+#define GEN2_SETTING_2_ADDR(unit) \
+ (PHY_REG_GEN2_SETTINGS_2 * PHY_SHFT(unit) + PHY_BASE(unit))
+#define g2_tx_ssc_amp BIT(14)
+
+/* for phy_read16 and phy_write16 */
+#define PHY_REG_GEN2_SETTINGS_3 0x3f
+#define GEN2_SETTING_3_ADDR(unit) \
+ (PHY_REG_GEN2_SETTINGS_3 * PHY_SHFT(unit) + PHY_BASE(unit))
+
+/* for phy_read16 and phy_write16 */
+#define PHY_MISC_REG0_ADDR 0x4f
+#define MISC_REG0_ADDR(unit) \
+ (PHY_MISC_REG0_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
+#define rb_clk100m_125m_en BIT(4)
+#define rb_clk500m_en BIT(7)
+#define rb_ref_clk_sel BIT(10)
+
+/* for phy_read16 and phy_write16 */
+#define PHY_REG_IFACE_REF_CLK_CTRL_ADDR 0x51
+#define UNIT_IFACE_REF_CLK_CTRL_ADDR(unit) \
+ (PHY_REG_IFACE_REF_CLK_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
+#define rb_ref1m_gen_div_force BIT(8)
+#define rf_ref1m_gen_div_value_shift 0
+#define rf_ref1m_gen_div_value_mask (0xFF << rf_ref1m_gen_div_value_shift)
+
+/* for phy_read16 and phy_write16 */
+#define PHY_REG_ERR_CNT_CONST_CTRL_ADDR 0x6A
+#define UNIT_ERR_CNT_CONST_CTRL_ADDR(unit) \
+ (PHY_REG_ERR_CNT_CONST_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
+#define rb_fast_dfe_enable BIT(13)
+
+#define MISC_REG1_ADDR(u) (0x73 * PHY_SHFT(u) + PHY_BASE(u))
+#define bf_sel_bits_pcie_force BIT(15)
+
+#define LANE_CFG0_ADDR(u) (0x180 * PHY_SHFT(u) + PHY_BASE(u))
+#define bf_use_max_pll_rate BIT(9)
+#define LANE_CFG1_ADDR(u) (0x181 * PHY_SHFT(u) + PHY_BASE(u))
+#define bf_use_max_pll_rate BIT(9)
+/* 0x5c310 = 0x93 (set BIT7) */
+#define LANE_CFG4_ADDR(u) (0x188 * PHY_SHFT(u) + PHY_BASE(u))
+#define bf_spread_spectrum_clock_en BIT(7)
+
+#define LANE_STAT1_ADDR(u) (0x183 * PHY_SHFT(u) + PHY_BASE(u))
+#define rb_txdclk_pclk_en BIT(0)
+
+#define GLOB_PHY_CTRL0_ADDR(u) (0x1c1 * PHY_SHFT(u) + PHY_BASE(u))
+#define bf_soft_rst BIT(0)
+#define bf_mode_refdiv 0x30
+#define rb_mode_core_clk_freq_sel BIT(9)
+#define rb_mode_pipe_width_32 BIT(3)
+
+#define TEST_MODE_CTRL_ADDR(u) (0x1c2 * PHY_SHFT(u) + PHY_BASE(u))
+#define rb_mode_margin_override BIT(2)
+
+#define GLOB_CLK_SRC_LO_ADDR(u) (0x1c3 * PHY_SHFT(u) + PHY_BASE(u))
+#define bf_cfg_sel_20b BIT(15)
+
+#define PWR_MGM_TIM1_ADDR(u) (0x1d0 * PHY_SHFT(u) + PHY_BASE(u))
+
+#define PHY_REF_CLK_ADDR (0x4814 + PCIE_BASE)
+
+#define USB3_CTRPUL_VAL_REG (0x20 + USB32_BASE)
+#define USB3H_CTRPUL_VAL_REG (0x3454 + USB32H_BASE)
+#define rb_usb3_ctr_100ns 0xff000000
+
+#define USB2_OTG_PHY_CTRL_ADDR (0x820 + USB2PHY_BASE)
+#define rb_usb2phy_suspm BIT(14)
+#define rb_usb2phy_pu BIT(0)
+
+#define USB2_PHY_OTG_CTRL_ADDR (0x34 + USB2PHY_BASE)
+#define rb_pu_otg BIT(4)
+
+#define USB2_PHY_CHRGR_DET_ADDR (0x38 + USB2PHY_BASE)
+#define rb_cdp_en BIT(2)
+#define rb_dcp_en BIT(3)
+#define rb_pd_en BIT(4)
+#define rb_pu_chrg_dtc BIT(5)
+#define rb_cdp_dm_auto BIT(7)
+#define rb_enswitch_dp BIT(12)
+#define rb_enswitch_dm BIT(13)
+
+#define USB2_CAL_CTRL_ADDR (0x8 + USB2PHY_BASE)
+#define rb_usb2phy_pllcal_done BIT(31)
+#define rb_usb2phy_impcal_done BIT(23)
+
+#define USB2_PLL_CTRL0_ADDR (0x0 + USB2PHY_BASE)
+#define rb_usb2phy_pll_ready BIT(31)
+
+#define USB2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY_BASE)
+#define rb_usb2phy_sqcal_done BIT(31)
+
+#define USB2_PHY2_CTRL_ADDR (0x804 + USB2PHY2_BASE)
+#define rb_usb2phy2_suspm BIT(7)
+#define rb_usb2phy2_pu BIT(0)
+#define USB2_PHY2_CAL_CTRL_ADDR (0x8 + USB2PHY2_BASE)
+#define USB2_PHY2_PLL_CTRL0_ADDR (0x0 + USB2PHY2_BASE)
+#define USB2_PHY2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY2_BASE)
+
+#define USB2_PHY_BASE(usb32) (usb32 == 0 ? USB2PHY2_BASE : USB2PHY_BASE)
+#define USB2_PHY_CTRL_ADDR(usb32) \
+ (usb32 == 0 ? USB2_PHY2_CTRL_ADDR : USB2_OTG_PHY_CTRL_ADDR)
+#define RB_USB2PHY_SUSPM(usb32) \
+ (usb32 == 0 ? rb_usb2phy2_suspm : rb_usb2phy_suspm)
+#define RB_USB2PHY_PU(usb32) \
+ (usb32 == 0 ? rb_usb2phy2_pu : rb_usb2phy_pu)
+#define USB2_PHY_CAL_CTRL_ADDR(usb32) \
+ (usb32 == 0 ? USB2_PHY2_CAL_CTRL_ADDR : USB2_CAL_CTRL_ADDR)
+#define USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32) \
+ (usb32 == 0 ? USB2_PHY2_RX_CHAN_CTRL1_ADDR : USB2_RX_CHAN_CTRL1_ADDR)
+#define USB2_PHY_PLL_CTRL0_ADDR(usb32) \
+ (usb32 == 0 ? USB2_PHY2_PLL_CTRL0_ADDR : USB2_PLL_CTRL0_ADDR)
+
+/*
+ * SATA definitions
+ */
+#define AHCI_BASE MVEBU_REG(0xE0000)
+
+#define rh_vsreg_addr (AHCI_BASE + 0x178)
+#define rh_vsreg_data (AHCI_BASE + 0x17C)
+#define rh_vs0_a (AHCI_BASE + 0xA0)
+#define rh_vs0_d (AHCI_BASE + 0xA4)
+
+#define vphy_sync_pattern_reg 0x224
+#define bs_txd_inv BIT(10)
+#define bs_rxd_inv BIT(11)
+
+#define vphy_loopback_reg0 0x223
+#define bs_phyintf_40bit 0x0C00
+#define bs_pll_ready_tx 0x10
+
+#define vphy_power_reg0 0x201
+
+#define vphy_calctl_reg 0x202
+#define bs_max_pll_rate BIT(12)
+
+#define vphy_reserve_reg 0x0e
+#define bs_phyctrl_frm_pin BIT(13)
+
+#define vsata_ctrl_reg 0x00
+#define bs_phy_pu_pll BIT(6)
+
+/*
+ * SDIO/eMMC definitions
+ */
+#define SDIO_BASE MVEBU_REG(0xD8000)
+
+#define SDIO_HOST_CTRL1_ADDR (SDIO_BASE + 0x28)
+#define SDIO_SDHC_FIFO_ADDR (SDIO_BASE + 0x12C)
+#define SDIO_CAP_12_ADDR (SDIO_BASE + 0x40)
+#define SDIO_ENDIAN_ADDR (SDIO_BASE + 0x1A4)
+#define SDIO_PHY_TIMING_ADDR (SDIO_BASE + 0x170)
+#define SDIO_PHY_PAD_CTRL0_ADDR (SDIO_BASE + 0x178)
+#define SDIO_DLL_RST_ADDR (SDIO_BASE + 0x148)
+
+#endif /* _COMPHY_A3700_H_ */
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
new file mode 100644
index 0000000..bc2508b
--- /dev/null
+++ b/drivers/phy/marvell/comphy_core.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+
+#include "comphy.h"
+
+#define COMPHY_MAX_CHIP 4
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char *get_speed_string(u32 speed)
+{
+ char *speed_strings[] = {"1.25 Gbps", "1.5 Gbps", "2.5 Gbps",
+ "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps",
+ "6.25 Gbps", "10.31 Gbps" };
+
+ if (speed < 0 || speed > PHY_SPEED_MAX)
+ return "invalid";
+
+ return speed_strings[speed];
+}
+
+static char *get_type_string(u32 type)
+{
+ char *type_strings[] = {"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
+ "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0",
+ "SGMII1", "SGMII2", "SGMII3", "QSGMII",
+ "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
+ "XAUI0", "XAUI1", "XAUI2", "XAUI3",
+ "RXAUI0", "RXAUI1", "KR"};
+
+ if (type < 0 || type > PHY_TYPE_MAX)
+ return "invalid";
+
+ return type_strings[type];
+}
+
+void reg_set(void __iomem *addr, u32 data, u32 mask)
+{
+ debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ",
+ (unsigned long)addr, data, mask);
+ debug("old value = %#010x ==> ", readl(addr));
+ reg_set_silent(addr, data, mask);
+ debug("new value %#010x\n", readl(addr));
+}
+
+void reg_set_silent(void __iomem *addr, u32 data, u32 mask)
+{
+ u32 reg_data;
+
+ reg_data = readl(addr);
+ reg_data &= ~mask;
+ reg_data |= data;
+ writel(reg_data, addr);
+}
+
+void reg_set16(void __iomem *addr, u16 data, u16 mask)
+{
+ debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ",
+ (unsigned long)addr, data, mask);
+ debug("old value = %#06x ==> ", readw(addr));
+ reg_set_silent16(addr, data, mask);
+ debug("new value %#06x\n", readw(addr));
+}
+
+void reg_set_silent16(void __iomem *addr, u16 data, u16 mask)
+{
+ u16 reg_data;
+
+ reg_data = readw(addr);
+ reg_data &= ~mask;
+ reg_data |= data;
+ writew(reg_data, addr);
+}
+
+void comphy_print(struct chip_serdes_phy_config *chip_cfg,
+ struct comphy_map *comphy_map_data)
+{
+ u32 lane;
+
+ for (lane = 0; lane < chip_cfg->comphy_lanes_count;
+ lane++, comphy_map_data++) {
+ if (comphy_map_data->type == PHY_TYPE_UNCONNECTED)
+ continue;
+
+ if (comphy_map_data->speed == PHY_SPEED_INVALID) {
+ printf("Comphy-%d: %-13s\n", lane,
+ get_type_string(comphy_map_data->type));
+ } else {
+ printf("Comphy-%d: %-13s %-10s\n", lane,
+ get_type_string(comphy_map_data->type),
+ get_speed_string(comphy_map_data->speed));
+ }
+ }
+}
+
+static int comphy_probe(struct udevice *dev)
+{
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
+ struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
+ int subnode;
+ int lane;
+ int last_idx = 0;
+
+ /* Save base addresses for later use */
+ chip_cfg->comphy_base_addr = (void *)dev_get_addr_index(dev, 0);
+ if (IS_ERR(chip_cfg->comphy_base_addr))
+ return PTR_ERR(chip_cfg->comphy_base_addr);
+
+ chip_cfg->hpipe3_base_addr = (void *)dev_get_addr_index(dev, 1);
+ if (IS_ERR(chip_cfg->hpipe3_base_addr))
+ return PTR_ERR(chip_cfg->hpipe3_base_addr);
+
+ chip_cfg->comphy_lanes_count = fdtdec_get_int(blob, node,
+ "max-lanes", 0);
+ if (chip_cfg->comphy_lanes_count <= 0) {
+ dev_err(&dev->dev, "comphy max lanes is wrong\n");
+ return -EINVAL;
+ }
+
+ chip_cfg->comphy_mux_bitcount = fdtdec_get_int(blob, node,
+ "mux-bitcount", 0);
+ if (chip_cfg->comphy_mux_bitcount <= 0) {
+ dev_err(&dev->dev, "comphy mux bit count is wrong\n");
+ return -EINVAL;
+ }
+
+ if (of_device_is_compatible(dev, "marvell,comphy-armada-3700"))
+ chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
+
+ if (of_device_is_compatible(dev, "marvell,comphy-cp110"))
+ chip_cfg->ptr_comphy_chip_init = comphy_cp110_init;
+
+ /*
+ * Bail out if no chip_init function is defined, e.g. no
+ * compatible node is found
+ */
+ if (!chip_cfg->ptr_comphy_chip_init) {
+ dev_err(&dev->dev, "comphy: No compatible DT node found\n");
+ return -ENODEV;
+ }
+
+ lane = 0;
+ fdt_for_each_subnode(subnode, blob, node) {
+ /* Skip disabled ports */
+ if (!fdtdec_get_is_enabled(blob, subnode))
+ continue;
+
+ comphy_map_data[lane].speed = fdtdec_get_int(
+ blob, subnode, "phy-speed", PHY_TYPE_INVALID);
+ comphy_map_data[lane].type = fdtdec_get_int(
+ blob, subnode, "phy-type", PHY_SPEED_INVALID);
+ comphy_map_data[lane].invert = fdtdec_get_int(
+ blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT);
+ comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode,
+ "clk-src");
+ if (comphy_map_data[lane].type == PHY_TYPE_INVALID) {
+ printf("no phy type for lane %d, setting lane as unconnected\n",
+ lane + 1);
+ }
+
+ lane++;
+ }
+
+ /* Save comphy index for MultiCP devices (A8K) */
+ chip_cfg->comphy_index = dev->seq;
+ /* PHY power UP sequence */
+ chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data);
+ /* PHY print SerDes status */
+ if (of_machine_is_compatible("marvell,armada8040"))
+ printf("Comphy chip #%d:\n", chip_cfg->comphy_index);
+ comphy_print(chip_cfg, comphy_map_data);
+
+ /*
+ * Only run the dedicated PHY init code once, in the last PHY init call
+ */
+ if (of_machine_is_compatible("marvell,armada8040"))
+ last_idx = 1;
+
+ if (chip_cfg->comphy_index == last_idx) {
+ /* Initialize dedicated PHYs (not muxed SerDes lanes) */
+ comphy_dedicated_phys_init();
+ }
+
+ return 0;
+}
+
+static const struct udevice_id comphy_ids[] = {
+ { .compatible = "marvell,mvebu-comphy" },
+ { }
+};
+
+U_BOOT_DRIVER(mvebu_comphy) = {
+ .name = "mvebu_comphy",
+ .id = UCLASS_MISC,
+ .of_match = comphy_ids,
+ .probe = comphy_probe,
+ .priv_auto_alloc_size = sizeof(struct chip_serdes_phy_config),
+};
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
new file mode 100644
index 0000000..25c067d
--- /dev/null
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -0,0 +1,1726 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "comphy.h"
+#include "comphy_hpipe.h"
+#include "sata.h"
+#include "utmi_phy.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SD_ADDR(base, lane) (base + 0x1000 * lane)
+#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
+#define COMPHY_ADDR(base, lane) (base + 0x28 * lane)
+
+struct utmi_phy_data {
+ void __iomem *utmi_base_addr;
+ void __iomem *usb_cfg_addr;
+ void __iomem *utmi_cfg_addr;
+ u32 utmi_phy_port;
+};
+
+/*
+ * For CP-110 we have 2 Selector registers "PHY Selectors",
+ * and "PIPE Selectors".
+ * PIPE selector include USB and PCIe options.
+ * PHY selector include the Ethernet and SATA options, every Ethernet
+ * option has different options, for example: serdes lane2 had option
+ * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, KR)
+ */
+struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
+ {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */
+ {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+ {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, /* Lane 1 */
+ {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } },
+ {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
+ {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
+ {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4} } },
+ {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */
+ {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
+ {PHY_TYPE_KR, 0x1}, {PHY_TYPE_XAUI1, 0x1},
+ {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+ {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
+ {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1},
+ {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } },
+ {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */
+ {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1},
+ {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+};
+
+struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
+ {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
+ {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
+ {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
+ {PHY_TYPE_PEX0, 0x4} } },
+ {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
+ {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
+ {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
+ {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
+ {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
+ {PHY_TYPE_USB3_HOST1, 0x1},
+ {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
+ {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
+};
+
+static u32 polling_with_timeout(void __iomem *addr, u32 val,
+ u32 mask, unsigned long usec_timout)
+{
+ u32 data;
+
+ do {
+ udelay(1);
+ data = readl(addr) & mask;
+ } while (data != val && --usec_timout > 0);
+
+ if (usec_timout == 0)
+ return data;
+
+ return 0;
+}
+
+static int comphy_pcie_power_up(u32 lane, u32 pcie_width,
+ bool clk_src, void __iomem *hpipe_base,
+ void __iomem *comphy_base)
+{
+ u32 mask, data, ret = 1;
+ void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
+ void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
+ void __iomem *addr;
+ u32 pcie_clk = 0; /* set input by default */
+
+ debug_enter();
+
+ /*
+ * ToDo:
+ * Add SAR (Sample-At-Reset) configuration for the PCIe clock
+ * direction. SAR code is currently not ported from Marvell
+ * U-Boot to mainline version.
+ *
+ * SerDes Lane 4/5 got the PCIe ref-clock #1,
+ * and SerDes Lane 0 got PCIe ref-clock #0
+ */
+ debug("PCIe clock = %x\n", pcie_clk);
+ debug("PCIe width = %d\n", pcie_width);
+
+ /* enable PCIe by4 and by2 */
+ if (lane == 0) {
+ if (pcie_width == 4) {
+ reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
+ 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET,
+ COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
+ } else if (pcie_width == 2) {
+ reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
+ 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET,
+ COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
+ }
+ }
+
+ /*
+ * If PCIe clock is output and clock source from SerDes lane 5,
+ * we need to configure the clock-source MUX.
+ * By default, the clock source is from lane 4
+ */
+ if (pcie_clk && clk_src && (lane == 5)) {
+ reg_set((void __iomem *)DFX_DEV_GEN_CTRL12,
+ 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET,
+ DFX_DEV_GEN_PCIE_CLK_SRC_MASK);
+ }
+
+ debug("stage: RFU configurations - hard reset comphy\n");
+ /* RFU configurations - hard reset comphy */
+ mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+ data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+ mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+ data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+ mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+ mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+ mask |= COMMON_PHY_PHY_MODE_MASK;
+ data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
+ reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
+
+ /* release from hard reset */
+ mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+ data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+ mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+ data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+ reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
+
+ /* Wait 1ms - until band gap and ref clock ready */
+ mdelay(1);
+ /* Start comphy Configuration */
+ debug("stage: Comphy configuration\n");
+ /* Set PIPE soft reset */
+ mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
+ data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
+ /* Set PHY datapath width mode for V0 */
+ mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
+ data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
+ /* Set Data bus width USB mode for V0 */
+ mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
+ data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
+ /* Set CORE_CLK output frequency for 250Mhz */
+ mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
+ data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
+ /* Set PLL ready delay for 0x2 */
+ data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
+ mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
+ if (pcie_width != 1) {
+ data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET;
+ mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK;
+ data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
+ mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
+ }
+ reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
+
+ /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */
+ data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
+ mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
+ if (pcie_width != 1) {
+ mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK;
+ mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK;
+ mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
+ if (lane == 0) {
+ data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET;
+ data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
+ } else if (lane == (pcie_width - 1)) {
+ data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
+ }
+ }
+ reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
+ /* Config update polarity equalization */
+ reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG,
+ 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET,
+ HPIPE_CFG_UPDATE_POLARITY_MASK);
+ /* Set PIPE version 4 to mode enable */
+ reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG,
+ 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET,
+ HPIPE_DFE_CTRL_28_PIPE4_MASK);
+ /* TODO: check if pcie clock is output/input - for bringup use input*/
+ /* Enable PIN clock 100M_125M */
+ mask = 0;
+ data = 0;
+ /* Only if clock is output, configure the clock-source mux */
+ if (pcie_clk) {
+ mask |= HPIPE_MISC_CLK100M_125M_MASK;
+ data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
+ }
+ /*
+ * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz
+ * clock
+ */
+ mask |= HPIPE_MISC_TXDCLK_2X_MASK;
+ data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
+ /* Enable 500MHz Clock */
+ mask |= HPIPE_MISC_CLK500_EN_MASK;
+ data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
+ if (pcie_clk) { /* output */
+ /* Set reference clock comes from group 1 */
+ mask |= HPIPE_MISC_REFCLK_SEL_MASK;
+ data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
+ } else {
+ /* Set reference clock comes from group 2 */
+ mask |= HPIPE_MISC_REFCLK_SEL_MASK;
+ data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
+ }
+ reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
+ if (pcie_clk) { /* output */
+ /* Set reference frequcency select - 0x2 for 25MHz*/
+ mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+ data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+ } else {
+ /* Set reference frequcency select - 0x0 for 100MHz*/
+ mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+ data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+ }
+ /* Set PHY mode to PCIe */
+ mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+ data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
+
+ /* ref clock alignment */
+ if (pcie_width != 1) {
+ mask = HPIPE_LANE_ALIGN_OFF_MASK;
+ data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET;
+ reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
+ }
+
+ /*
+ * Set the amount of time spent in the LoZ state - set for 0x7 only if
+ * the PCIe clock is output
+ */
+ if (pcie_clk) {
+ reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
+ 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
+ HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
+ }
+
+ /* Set Maximal PHY Generation Setting(8Gbps) */
+ mask = HPIPE_INTERFACE_GEN_MAX_MASK;
+ data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
+ /* Set Link Train Mode (Tx training control pins are used) */
+ mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
+ data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
+
+ /* Set Idle_sync enable */
+ mask = HPIPE_PCIE_IDLE_SYNC_MASK;
+ data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
+ /* Select bits for PCIE Gen3(32bit) */
+ mask |= HPIPE_PCIE_SEL_BITS_MASK;
+ data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
+
+ /* Enable Tx_adapt_g1 */
+ mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
+ data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
+ /* Enable Tx_adapt_gn1 */
+ mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
+ data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
+ /* Disable Tx_adapt_g0 */
+ mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
+ data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
+
+ /* Set reg_tx_train_chk_init */
+ mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
+ data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
+ /* Enable TX_COE_FM_PIN_PCIE3_EN */
+ mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
+ data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
+
+ debug("stage: TRx training parameters\n");
+ /* Set Preset sweep configurations */
+ mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK;
+ data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET;
+
+ mask |= HPIPE_TX_NUM_OF_PRESET_MASK;
+ data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET;
+
+ mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK;
+ data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
+
+ /* Tx train start configuration */
+ mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK;
+ data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET;
+
+ mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK;
+ data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET;
+
+ mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK;
+ data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET;
+
+ mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
+ data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
+
+ /* Enable Tx train P2P */
+ mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
+ data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
+
+ /* Configure Tx train timeout */
+ mask = HPIPE_TRX_TRAIN_TIMER_MASK;
+ data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
+
+ /* Disable G0/G1/GN1 adaptation */
+ mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK
+ | HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
+ data = 0;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
+
+ /* Disable DTL frequency loop */
+ mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
+ data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
+
+ /* Configure G3 DFE */
+ mask = HPIPE_G3_DFE_RES_MASK;
+ data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
+
+ /* Force DFE resolution (use GEN table value) */
+ mask = HPIPE_DFE_RES_FORCE_MASK;
+ data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
+
+ /* Configure initial and final coefficient value for receiver */
+ mask = HPIPE_G3_RX_SELMUPI_MASK;
+ data = 0x1 << HPIPE_G3_RX_SELMUPI_OFFSET;
+
+ mask |= HPIPE_G3_RX_SELMUPF_MASK;
+ data |= 0x1 << HPIPE_G3_RX_SELMUPF_OFFSET;
+
+ mask |= HPIPE_G3_SETTING_BIT_MASK;
+ data |= 0x0 << HPIPE_G3_SETTING_BIT_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G3_SETTINGS_1_REG, data, mask);
+
+ /* Trigger sampler enable pulse */
+ mask = HPIPE_SMAPLER_MASK;
+ data = 0x1 << HPIPE_SMAPLER_OFFSET;
+ reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
+ udelay(5);
+ reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask);
+
+ /* FFE resistor tuning for different bandwidth */
+ mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
+ data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
+
+ mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
+ data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
+
+ /* Set phy in root complex mode */
+ mask = HPIPE_CFG_PHY_RC_EP_MASK;
+ data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
+ reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
+
+ debug("stage: Comphy power up\n");
+
+ /*
+ * For PCIe by4 or by2 - release from reset only after finish to
+ * configure all lanes
+ */
+ if ((pcie_width == 1) || (lane == (pcie_width - 1))) {
+ u32 i, start_lane, end_lane;
+
+ if (pcie_width != 1) {
+ /* allows writing to all lanes in one write */
+ reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
+ 0x0 <<
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
+ start_lane = 0;
+ end_lane = pcie_width;
+
+ /*
+ * Release from PIPE soft reset
+ * for PCIe by4 or by2 - release from soft reset
+ * all lanes - can't use read modify write
+ */
+ reg_set(HPIPE_ADDR(hpipe_base, 0) +
+ HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff);
+ } else {
+ start_lane = lane;
+ end_lane = lane + 1;
+
+ /*
+ * Release from PIPE soft reset
+ * for PCIe by4 or by2 - release from soft reset
+ * all lanes
+ */
+ reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
+ 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
+ HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
+ }
+
+
+ if (pcie_width != 1) {
+ /* disable writing to all lanes with one write */
+ reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
+ 0x3210 <<
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
+ COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
+ }
+
+ debug("stage: Check PLL\n");
+ /* Read lane status */
+ for (i = start_lane; i < end_lane; i++) {
+ addr = HPIPE_ADDR(hpipe_base, i) +
+ HPIPE_LANE_STATUS1_REG;
+ data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 15000);
+ if (data != 0) {
+ debug("Read from reg = %p - value = 0x%x\n",
+ hpipe_addr + HPIPE_LANE_STATUS1_REG,
+ data);
+ error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
+ ret = 0;
+ }
+ }
+ }
+
+ debug_exit();
+ return ret;
+}
+
+static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
+ void __iomem *comphy_base)
+{
+ u32 mask, data, ret = 1;
+ void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
+ void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
+ void __iomem *addr;
+
+ debug_enter();
+ debug("stage: RFU configurations - hard reset comphy\n");
+ /* RFU configurations - hard reset comphy */
+ mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+ data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+ mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+ data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+ mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+ mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+ mask |= COMMON_PHY_PHY_MODE_MASK;
+ data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
+ reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
+
+ /* release from hard reset */
+ mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+ data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+ mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+ data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+ reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
+
+ /* Wait 1ms - until band gap and ref clock ready */
+ mdelay(1);
+
+ /* Start comphy Configuration */
+ debug("stage: Comphy configuration\n");
+ /* Set PIPE soft reset */
+ mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
+ data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
+ /* Set PHY datapath width mode for V0 */
+ mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
+ data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
+ /* Set Data bus width USB mode for V0 */
+ mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
+ data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
+ /* Set CORE_CLK output frequency for 250Mhz */
+ mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
+ data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
+ /* Set PLL ready delay for 0x2 */
+ reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
+ 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
+ HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
+ /* Set reference clock to come from group 1 - 25Mhz */
+ reg_set(hpipe_addr + HPIPE_MISC_REG,
+ 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
+ HPIPE_MISC_REFCLK_SEL_MASK);
+ /* Set reference frequcency select - 0x2 */
+ mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+ data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+ /* Set PHY mode to USB - 0x5 */
+ mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+ data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
+ /* Set the amount of time spent in the LoZ state - set for 0x7 */
+ reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
+ 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
+ HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
+ /* Set max PHY generation setting - 5Gbps */
+ reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
+ 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
+ HPIPE_INTERFACE_GEN_MAX_MASK);
+ /* Set select data width 20Bit (SEL_BITS[2:0]) */
+ reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
+ 0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
+ HPIPE_LOOPBACK_SEL_MASK);
+ /* select de-emphasize 3.5db */
+ reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
+ 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
+ HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
+ /* override tx margining from the MAC */
+ reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
+ 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
+ HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
+
+ /* Start analog paramters from ETP(HW) */
+ debug("stage: Analog paramters from ETP(HW)\n");
+ /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
+ mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
+ data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
+ /* Set Override PHY DFE control pins for 0x1 */
+ mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
+ data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
+ /* Set Spread Spectrum Clock Enable fot 0x1 */
+ mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
+ data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
+ /* End of analog parameters */
+
+ debug("stage: Comphy power up\n");
+ /* Release from PIPE soft reset */
+ reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
+ 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
+ HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
+
+ /* wait 15ms - for comphy calibration done */
+ debug("stage: Check PLL\n");
+ /* Read lane status */
+ addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
+ data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 15000);
+ if (data != 0) {
+ debug("Read from reg = %p - value = 0x%x\n",
+ hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
+ error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
+ ret = 0;
+ }
+
+ debug_exit();
+ return ret;
+}
+
+static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
+ void __iomem *comphy_base, int comphy_index)
+{
+ u32 mask, data, i, ret = 1;
+ void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
+ void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
+ void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
+ void __iomem *addr;
+ void __iomem *sata_base = NULL;
+ int sata_node = -1; /* Set to -1 in order to read the first sata node */
+
+ debug_enter();
+
+ /*
+ * Assumption - each CP has only one SATA controller
+ * Calling fdt_node_offset_by_compatible first time (with sata_node = -1
+ * will return the first node always.
+ * In order to parse each CPs SATA node, fdt_node_offset_by_compatible
+ * must be called again (according to the CP id)
+ */
+ for (i = 0; i < (comphy_index + 1); i++)
+ sata_node = fdt_node_offset_by_compatible(
+ gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
+
+ if (sata_node == 0) {
+ error("SATA node not found in FDT\n");
+ return 0;
+ }
+
+ sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, sata_node, "reg", 0, NULL, true);
+ if (sata_base == NULL) {
+ error("SATA address not found in FDT\n");
+ return 0;
+ }
+
+ debug("SATA address found in FDT %p\n", sata_base);
+
+ debug("stage: MAC configuration - power down comphy\n");
+ /*
+ * MAC configuration powe down comphy use indirect address for
+ * vendor spesific SATA control register
+ */
+ reg_set(sata_base + SATA3_VENDOR_ADDRESS,
+ SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
+ SATA3_VENDOR_ADDR_MASK);
+ /* SATA 0 power down */
+ mask = SATA3_CTRL_SATA0_PD_MASK;
+ data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
+ /* SATA 1 power down */
+ mask |= SATA3_CTRL_SATA1_PD_MASK;
+ data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
+ /* SATA SSU disable */
+ mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
+ data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
+ /* SATA port 1 disable */
+ mask |= SATA3_CTRL_SATA_SSU_MASK;
+ data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
+ reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
+
+ debug("stage: RFU configurations - hard reset comphy\n");
+ /* RFU configurations - hard reset comphy */
+ mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+ data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+ mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+ mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+ mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+ reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
+
+ /* Set select data width 40Bit - SATA mode only */
+ reg_set(comphy_addr + COMMON_PHY_CFG6_REG,
+ 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET,
+ COMMON_PHY_CFG6_IF_40_SEL_MASK);
+
+ /* release from hard reset in SD external */
+ mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+ /* Wait 1ms - until band gap and ref clock ready */
+ mdelay(1);
+
+ debug("stage: Comphy configuration\n");
+ /* Start comphy Configuration */
+ /* Set reference clock to comes from group 1 - choose 25Mhz */
+ reg_set(hpipe_addr + HPIPE_MISC_REG,
+ 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
+ HPIPE_MISC_REFCLK_SEL_MASK);
+ /* Reference frequency select set 1 (for SATA = 25Mhz) */
+ mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+ data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+ /* PHY mode select (set SATA = 0x0 */
+ mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+ data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
+ /* Set max PHY generation setting - 6Gbps */
+ reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
+ 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
+ HPIPE_INTERFACE_GEN_MAX_MASK);
+ /* Set select data width 40Bit (SEL_BITS[2:0]) */
+ reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
+ 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
+
+ debug("stage: Analog paramters from ETP(HW)\n");
+ /*
+ * TODO: Set analog paramters from ETP(HW) - for now use the
+ * default datas
+ */
+
+ /* DFE reset sequence */
+ reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
+ 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
+ HPIPE_PWR_CTR_RST_DFE_MASK);
+ reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
+ 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
+ HPIPE_PWR_CTR_RST_DFE_MASK);
+ /* SW reset for interupt logic */
+ reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
+ 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
+ HPIPE_PWR_CTR_SFT_RST_MASK);
+ reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
+ 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
+ HPIPE_PWR_CTR_SFT_RST_MASK);
+
+ debug("stage: Comphy power up\n");
+ /*
+ * MAC configuration power up comphy - power up PLL/TX/RX
+ * use indirect address for vendor spesific SATA control register
+ */
+ reg_set(sata_base + SATA3_VENDOR_ADDRESS,
+ SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
+ SATA3_VENDOR_ADDR_MASK);
+ /* SATA 0 power up */
+ mask = SATA3_CTRL_SATA0_PD_MASK;
+ data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
+ /* SATA 1 power up */
+ mask |= SATA3_CTRL_SATA1_PD_MASK;
+ data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
+ /* SATA SSU enable */
+ mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
+ data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
+ /* SATA port 1 enable */
+ mask |= SATA3_CTRL_SATA_SSU_MASK;
+ data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
+ reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
+
+ /* MBUS request size and interface select register */
+ reg_set(sata_base + SATA3_VENDOR_ADDRESS,
+ SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
+ SATA3_VENDOR_ADDR_MASK);
+ /* Mbus regret enable */
+ reg_set(sata_base + SATA3_VENDOR_DATA,
+ 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK);
+
+ debug("stage: Check PLL\n");
+
+ addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
+ data = SD_EXTERNAL_STATUS0_PLL_TX_MASK &
+ SD_EXTERNAL_STATUS0_PLL_RX_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 15000);
+ if (data != 0) {
+ debug("Read from reg = %p - value = 0x%x\n",
+ hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
+ error("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n",
+ (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK),
+ (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK));
+ ret = 0;
+ }
+
+ debug_exit();
+ return ret;
+}
+
+static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed,
+ void __iomem *hpipe_base,
+ void __iomem *comphy_base)
+{
+ u32 mask, data, ret = 1;
+ void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
+ void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
+ void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
+ void __iomem *addr;
+
+ debug_enter();
+ debug("stage: RFU configurations - hard reset comphy\n");
+ /* RFU configurations - hard reset comphy */
+ mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+ data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+ mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+ reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
+
+ /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
+ mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
+ data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
+ if (sgmii_speed == PHY_SPEED_1_25G) {
+ data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
+ data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
+ } else {
+ /* 3.125G */
+ data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
+ data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
+ }
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
+ data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
+ data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
+ data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
+
+ /* release from hard reset */
+ mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+ data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+ data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
+ data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+ /* release from hard reset */
+ mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+
+ /* Wait 1ms - until band gap and ref clock ready */
+ mdelay(1);
+
+ /* Start comphy Configuration */
+ debug("stage: Comphy configuration\n");
+ /* set reference clock */
+ mask = HPIPE_MISC_REFCLK_SEL_MASK;
+ data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
+ /* Power and PLL Control */
+ mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+ data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+ mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+ data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
+ /* Loopback register */
+ mask = HPIPE_LOOPBACK_SEL_MASK;
+ data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
+ /* rx control 1 */
+ mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
+ data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
+ mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
+ data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
+ /* DTL Control */
+ mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
+ data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
+
+ /* Set analog paramters from ETP(HW) - for now use the default datas */
+ debug("stage: Analog paramters from ETP(HW)\n");
+
+ reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
+ 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
+ HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
+
+ debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
+ /* SERDES External Configuration */
+ mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
+
+ /* check PLL rx & tx ready */
+ addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
+ data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
+ SD_EXTERNAL_STATUS0_PLL_TX_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 15000);
+ if (data != 0) {
+ debug("Read from reg = %p - value = 0x%x\n",
+ sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
+ error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
+ (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
+ (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
+ ret = 0;
+ }
+
+ /* RX init */
+ mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+ /* check that RX init done */
+ addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
+ data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 100);
+ if (data != 0) {
+ debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
+ error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
+ ret = 0;
+ }
+
+ debug("stage: RF Reset\n");
+ /* RF Reset */
+ mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
+ data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+ debug_exit();
+ return ret;
+}
+
+static int comphy_kr_power_up(u32 lane, void __iomem *hpipe_base,
+ void __iomem *comphy_base)
+{
+ u32 mask, data, ret = 1;
+ void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
+ void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
+ void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
+ void __iomem *addr;
+
+ debug_enter();
+ debug("stage: RFU configurations - hard reset comphy\n");
+ /* RFU configurations - hard reset comphy */
+ mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+ data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+ mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+ reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
+
+ /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
+ mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
+ data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
+ data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
+ data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
+ data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
+ data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
+ data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
+
+ /* release from hard reset */
+ mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+ data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+ data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
+ data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+ mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+
+ /* Wait 1ms - until band gap and ref clock ready */
+ mdelay(1);
+
+ /* Start comphy Configuration */
+ debug("stage: Comphy configuration\n");
+ /* set reference clock */
+ mask = HPIPE_MISC_ICP_FORCE_MASK;
+ data = 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
+ mask |= HPIPE_MISC_REFCLK_SEL_MASK;
+ data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
+ /* Power and PLL Control */
+ mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+ data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+ mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+ data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
+ /* Loopback register */
+ mask = HPIPE_LOOPBACK_SEL_MASK;
+ data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
+ /* rx control 1 */
+ mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
+ data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
+ mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
+ data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
+ /* DTL Control */
+ mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
+ data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
+
+ /* Set analog paramters from ETP(HW) */
+ debug("stage: Analog paramters from ETP(HW)\n");
+ /* SERDES External Configuration 2 */
+ mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
+ /* 0x7-DFE Resolution control */
+ mask = HPIPE_DFE_RES_FORCE_MASK;
+ data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
+ /* 0xd-G1_Setting_0 */
+ mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
+ data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
+ mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
+ data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
+ /* Genration 1 setting 2 (G1_Setting_2) */
+ mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK;
+ data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET;
+ mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK;
+ data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
+ /* Transmitter Slew Rate Control register (tx_reg1) */
+ mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK;
+ data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET;
+ mask |= HPIPE_TX_REG1_SLC_EN_MASK;
+ data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask);
+ /* Impedance Calibration Control register (cal_reg1) */
+ mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK;
+ data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
+ mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK;
+ data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask);
+ /* Generation 1 Setting 5 (g1_setting_5) */
+ mask = HPIPE_G1_SETTING_5_G1_ICP_MASK;
+ data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
+ /* 0xE-G1_Setting_1 */
+ mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
+ data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
+ /* 0xA-DFE_Reg3 */
+ mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
+ data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
+ mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
+ data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
+
+ /* 0x111-G1_Setting_4 */
+ mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
+ data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
+ /* Genration 1 setting 3 (G1_Setting_3) */
+ mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK;
+ data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
+
+ debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
+ /* SERDES External Configuration */
+ mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
+
+
+ /* check PLL rx & tx ready */
+ addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
+ data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
+ SD_EXTERNAL_STATUS0_PLL_TX_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 15000);
+ if (data != 0) {
+ debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
+ error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
+ (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
+ (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
+ ret = 0;
+ }
+
+ /* RX init */
+ mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+
+ /* check that RX init done */
+ addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
+ data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 100);
+ if (data != 0) {
+ debug("Read from reg = %p - value = 0x%x\n",
+ sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
+ error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
+ ret = 0;
+ }
+
+ debug("stage: RF Reset\n");
+ /* RF Reset */
+ mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
+ data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+ debug_exit();
+ return ret;
+}
+
+static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base,
+ void __iomem *comphy_base)
+{
+ u32 mask, data, ret = 1;
+ void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
+ void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
+ void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
+ void __iomem *addr;
+
+ debug_enter();
+ debug("stage: RFU configurations - hard reset comphy\n");
+ /* RFU configurations - hard reset comphy */
+ mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+ data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+ mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+ data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+ reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
+
+ if (lane == 2) {
+ reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
+ 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
+ COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
+ }
+ if (lane == 4) {
+ reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
+ 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
+ COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
+ }
+
+ /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
+ mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
+ data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
+ data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
+ data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
+ data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
+ data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
+ data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
+
+ /* release from hard reset */
+ mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+ data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+ data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
+ data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+ mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+ /* Wait 1ms - until band gap and ref clock ready */
+ mdelay(1);
+
+ /* Start comphy Configuration */
+ debug("stage: Comphy configuration\n");
+ /* set reference clock */
+ reg_set(hpipe_addr + HPIPE_MISC_REG,
+ 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
+ HPIPE_MISC_REFCLK_SEL_MASK);
+ /* Power and PLL Control */
+ mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+ data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+ mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+ data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
+ /* Loopback register */
+ reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
+ 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
+ /* rx control 1 */
+ mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
+ data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
+ mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
+ data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
+ /* DTL Control */
+ reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
+ 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
+ HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
+
+ /* Set analog paramters from ETP(HW) */
+ debug("stage: Analog paramters from ETP(HW)\n");
+ /* SERDES External Configuration 2 */
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
+ 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
+ SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
+ /* 0x7-DFE Resolution control */
+ reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
+ HPIPE_DFE_RES_FORCE_MASK);
+ /* 0xd-G1_Setting_0 */
+ reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
+ 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
+ HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
+ /* 0xE-G1_Setting_1 */
+ mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
+ data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
+ /* 0xA-DFE_Reg3 */
+ mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
+ data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
+ mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
+ data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
+
+ /* 0x111-G1_Setting_4 */
+ mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
+ data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
+
+ debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
+ /* SERDES External Configuration */
+ mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
+
+
+ /* check PLL rx & tx ready */
+ addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
+ data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
+ SD_EXTERNAL_STATUS0_PLL_TX_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 15000);
+ if (data != 0) {
+ debug("Read from reg = %p - value = 0x%x\n",
+ sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
+ error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
+ (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
+ (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
+ ret = 0;
+ }
+
+ /* RX init */
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
+ 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
+ SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
+
+ /* check that RX init done */
+ addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
+ data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 100);
+ if (data != 0) {
+ debug("Read from reg = %p - value = 0x%x\n",
+ sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
+ error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
+ ret = 0;
+ }
+
+ debug("stage: RF Reset\n");
+ /* RF Reset */
+ mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
+ data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
+ debug_exit();
+ return ret;
+}
+
+static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
+ void __iomem *usb_cfg_addr,
+ void __iomem *utmi_cfg_addr,
+ u32 utmi_phy_port)
+{
+ u32 mask, data;
+
+ debug_enter();
+ debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n",
+ utmi_index);
+ /* Power down UTMI PHY */
+ reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET,
+ UTMI_PHY_CFG_PU_MASK);
+
+ /*
+ * If UTMI connected to USB Device, configure mux prior to PHY init
+ * (Device can be connected to UTMI0 or to UTMI1)
+ */
+ if (utmi_phy_port == UTMI_PHY_TO_USB_DEVICE0) {
+ debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n",
+ utmi_index);
+ /* USB3 Device UTMI enable */
+ mask = UTMI_USB_CFG_DEVICE_EN_MASK;
+ data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
+ /* USB3 Device UTMI MUX */
+ mask |= UTMI_USB_CFG_DEVICE_MUX_MASK;
+ data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET;
+ reg_set(usb_cfg_addr, data, mask);
+ }
+
+ /* Set Test suspendm mode */
+ mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK;
+ data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET;
+ /* Enable Test UTMI select */
+ mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK;
+ data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET;
+ reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask);
+
+ /* Wait for UTMI power down */
+ mdelay(1);
+
+ debug_exit();
+ return;
+}
+
+static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
+ void __iomem *usb_cfg_addr,
+ void __iomem *utmi_cfg_addr,
+ u32 utmi_phy_port)
+{
+ u32 mask, data;
+
+ debug_exit();
+ debug("stage: Configure UTMI PHY %d registers\n", utmi_index);
+ /* Reference Clock Divider Select */
+ mask = UTMI_PLL_CTRL_REFDIV_MASK;
+ data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET;
+ /* Feedback Clock Divider Select - 90 for 25Mhz*/
+ mask |= UTMI_PLL_CTRL_FBDIV_MASK;
+ data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET;
+ /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
+ mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
+ data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
+ reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask);
+
+ /* Impedance Calibration Threshold Setting */
+ reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
+ 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
+ UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
+
+ /* Set LS TX driver strength coarse control */
+ mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
+ data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
+ /* Set LS TX driver fine adjustment */
+ mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
+ data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
+ reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
+
+ /* Enable SQ */
+ mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
+ data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
+ /* Enable analog squelch detect */
+ mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
+ data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+ reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
+
+ /* Set External squelch calibration number */
+ mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK;
+ data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET;
+ /* Enable the External squelch calibration */
+ mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK;
+ data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET;
+ reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask);
+
+ /* Set Control VDAT Reference Voltage - 0.325V */
+ mask = UTMI_CHGDTC_CTRL_VDAT_MASK;
+ data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET;
+ /* Set Control VSRC Reference Voltage - 0.6V */
+ mask |= UTMI_CHGDTC_CTRL_VSRC_MASK;
+ data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET;
+ reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask);
+
+ debug_exit();
+ return;
+}
+
+static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
+ void __iomem *usb_cfg_addr,
+ void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
+{
+ u32 data, mask, ret = 1;
+ void __iomem *addr;
+
+ debug_enter();
+ debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n",
+ utmi_index);
+ /* Power UP UTMI PHY */
+ reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET,
+ UTMI_PHY_CFG_PU_MASK);
+ /* Disable Test UTMI select */
+ reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG,
+ 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET,
+ UTMI_CTRL_STATUS0_TEST_SEL_MASK);
+
+ debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
+ addr = utmi_base_addr + UTMI_CALIB_CTRL_REG;
+ data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 100);
+ if (data != 0) {
+ error("Impedance calibration is not done\n");
+ debug("Read from reg = %p - value = 0x%x\n", addr, data);
+ ret = 0;
+ }
+
+ data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 100);
+ if (data != 0) {
+ error("PLL calibration is not done\n");
+ debug("Read from reg = %p - value = 0x%x\n", addr, data);
+ ret = 0;
+ }
+
+ addr = utmi_base_addr + UTMI_PLL_CTRL_REG;
+ data = UTMI_PLL_CTRL_PLL_RDY_MASK;
+ mask = data;
+ data = polling_with_timeout(addr, data, mask, 100);
+ if (data != 0) {
+ error("PLL is not ready\n");
+ debug("Read from reg = %p - value = 0x%x\n", addr, data);
+ ret = 0;
+ }
+
+ if (ret)
+ debug("Passed\n");
+ else
+ debug("\n");
+
+ debug_exit();
+ return ret;
+}
+
+/*
+ * comphy_utmi_phy_init initialize the UTMI PHY
+ * the init split in 3 parts:
+ * 1. Power down transceiver and PLL
+ * 2. UTMI PHY configure
+ * 3. Powe up transceiver and PLL
+ * Note: - Power down/up should be once for both UTMI PHYs
+ * - comphy_dedicated_phys_init call this function if at least there is
+ * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
+ * legal
+ */
+static void comphy_utmi_phy_init(u32 utmi_phy_count,
+ struct utmi_phy_data *cp110_utmi_data)
+{
+ u32 i;
+
+ debug_enter();
+ /* UTMI Power down */
+ for (i = 0; i < utmi_phy_count; i++) {
+ comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr,
+ cp110_utmi_data[i].usb_cfg_addr,
+ cp110_utmi_data[i].utmi_cfg_addr,
+ cp110_utmi_data[i].utmi_phy_port);
+ }
+ /* PLL Power down */
+ debug("stage: UTMI PHY power down PLL\n");
+ for (i = 0; i < utmi_phy_count; i++) {
+ reg_set(cp110_utmi_data[i].usb_cfg_addr,
+ 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
+ }
+ /* UTMI configure */
+ for (i = 0; i < utmi_phy_count; i++) {
+ comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr,
+ cp110_utmi_data[i].usb_cfg_addr,
+ cp110_utmi_data[i].utmi_cfg_addr,
+ cp110_utmi_data[i].utmi_phy_port);
+ }
+ /* UTMI Power up */
+ for (i = 0; i < utmi_phy_count; i++) {
+ if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr,
+ cp110_utmi_data[i].usb_cfg_addr,
+ cp110_utmi_data[i].utmi_cfg_addr,
+ cp110_utmi_data[i].utmi_phy_port)) {
+ error("Failed to initialize UTMI PHY %d\n", i);
+ continue;
+ }
+ printf("UTMI PHY %d initialized to ", i);
+ if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_TO_USB_DEVICE0)
+ printf("USB Device\n");
+ else
+ printf("USB Host%d\n",
+ cp110_utmi_data[i].utmi_phy_port);
+ }
+ /* PLL Power up */
+ debug("stage: UTMI PHY power up PLL\n");
+ for (i = 0; i < utmi_phy_count; i++) {
+ reg_set(cp110_utmi_data[i].usb_cfg_addr,
+ 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
+ }
+
+ debug_exit();
+ return;
+}
+
+/*
+ * comphy_dedicated_phys_init initialize the dedicated PHYs
+ * - not muxed SerDes lanes e.g. UTMI PHY
+ */
+void comphy_dedicated_phys_init(void)
+{
+ struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
+ int node;
+ int i;
+
+ debug_enter();
+ debug("Initialize USB UTMI PHYs\n");
+
+ /* Find the UTMI phy node in device tree and go over them */
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ "marvell,mvebu-utmi-2.6.0");
+
+ i = 0;
+ while (node > 0) {
+ /* get base address of UTMI phy */
+ cp110_utmi_data[i].utmi_base_addr =
+ (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, node, "reg", 0, NULL, true);
+ if (cp110_utmi_data[i].utmi_base_addr == NULL) {
+ error("UTMI PHY base address is invalid\n");
+ i++;
+ continue;
+ }
+
+ /* get usb config address */
+ cp110_utmi_data[i].usb_cfg_addr =
+ (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, node, "reg", 1, NULL, true);
+ if (cp110_utmi_data[i].usb_cfg_addr == NULL) {
+ error("UTMI PHY base address is invalid\n");
+ i++;
+ continue;
+ }
+
+ /* get UTMI config address */
+ cp110_utmi_data[i].utmi_cfg_addr =
+ (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, node, "reg", 2, NULL, true);
+ if (cp110_utmi_data[i].utmi_cfg_addr == NULL) {
+ error("UTMI PHY base address is invalid\n");
+ i++;
+ continue;
+ }
+
+ /*
+ * get the port number (to check if the utmi connected to
+ * host/device)
+ */
+ cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int(
+ gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
+ if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) {
+ error("UTMI PHY port type is invalid\n");
+ i++;
+ continue;
+ }
+
+ node = fdt_node_offset_by_compatible(
+ gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0");
+ i++;
+ }
+
+ if (i > 0)
+ comphy_utmi_phy_init(i, cp110_utmi_data);
+
+ debug_exit();
+}
+
+static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map)
+{
+ void __iomem *comphy_base_addr;
+ struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS];
+ struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS];
+ u32 lane, comphy_max_count;
+
+ comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
+ comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
+
+ /*
+ * Copy the SerDes map configuration for PIPE map and PHY map
+ * the comphy_mux_init modify the type of the lane if the type
+ * is not valid because we have 2 selectores run the
+ * comphy_mux_init twice and after that update the original
+ * serdes_map
+ */
+ for (lane = 0; lane < comphy_max_count; lane++) {
+ comphy_map_pipe_data[lane].type = serdes_map[lane].type;
+ comphy_map_pipe_data[lane].speed = serdes_map[lane].speed;
+ comphy_map_phy_data[lane].type = serdes_map[lane].type;
+ comphy_map_phy_data[lane].speed = serdes_map[lane].speed;
+ }
+ ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data;
+ comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data,
+ comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET);
+
+ ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data;
+ comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data,
+ comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
+ /* Fix the type after check the PHY and PIPE configuration */
+ for (lane = 0; lane < comphy_max_count; lane++) {
+ if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
+ (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
+ serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
+ }
+}
+
+int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+ struct comphy_map *serdes_map)
+{
+ struct comphy_map *ptr_comphy_map;
+ void __iomem *comphy_base_addr, *hpipe_base_addr;
+ u32 comphy_max_count, lane, ret = 0;
+ u32 pcie_width = 0;
+
+ debug_enter();
+
+ comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
+ comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
+ hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
+
+ /* Config Comphy mux configuration */
+ comphy_mux_cp110_init(ptr_chip_cfg, serdes_map);
+
+ /* Check if the first 4 lanes configured as By-4 */
+ for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
+ lane++, ptr_comphy_map++) {
+ if (ptr_comphy_map->type != PHY_TYPE_PEX0)
+ break;
+ pcie_width++;
+ }
+
+ for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count;
+ lane++, ptr_comphy_map++) {
+ debug("Initialize serdes number %d\n", lane);
+ debug("Serdes type = 0x%x\n", ptr_comphy_map->type);
+ if (lane == 4) {
+ /*
+ * PCIe lanes above the first 4 lanes, can be only
+ * by1
+ */
+ pcie_width = 1;
+ }
+ switch (ptr_comphy_map->type) {
+ case PHY_TYPE_UNCONNECTED:
+ continue;
+ break;
+ case PHY_TYPE_PEX0:
+ case PHY_TYPE_PEX1:
+ case PHY_TYPE_PEX2:
+ case PHY_TYPE_PEX3:
+ ret = comphy_pcie_power_up(
+ lane, pcie_width, ptr_comphy_map->clk_src,
+ hpipe_base_addr, comphy_base_addr);
+ break;
+ case PHY_TYPE_SATA0:
+ case PHY_TYPE_SATA1:
+ case PHY_TYPE_SATA2:
+ case PHY_TYPE_SATA3:
+ ret = comphy_sata_power_up(
+ lane, hpipe_base_addr, comphy_base_addr,
+ ptr_chip_cfg->comphy_index);
+ break;
+ case PHY_TYPE_USB3_HOST0:
+ case PHY_TYPE_USB3_HOST1:
+ case PHY_TYPE_USB3_DEVICE:
+ ret = comphy_usb3_power_up(lane, hpipe_base_addr,
+ comphy_base_addr);
+ break;
+ case PHY_TYPE_SGMII0:
+ case PHY_TYPE_SGMII1:
+ case PHY_TYPE_SGMII2:
+ case PHY_TYPE_SGMII3:
+ if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
+ debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
+ lane);
+ ptr_comphy_map->speed = PHY_SPEED_1_25G;
+ }
+ ret = comphy_sgmii_power_up(
+ lane, ptr_comphy_map->speed, hpipe_base_addr,
+ comphy_base_addr);
+ break;
+ case PHY_TYPE_KR:
+ ret = comphy_kr_power_up(lane, hpipe_base_addr,
+ comphy_base_addr);
+ break;
+ case PHY_TYPE_RXAUI0:
+ case PHY_TYPE_RXAUI1:
+ ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
+ comphy_base_addr);
+ break;
+ default:
+ debug("Unknown SerDes type, skip initialize SerDes %d\n",
+ lane);
+ break;
+ }
+ if (ret == 0) {
+ /*
+ * If interface wans't initialiuzed, set the lane to
+ * PHY_TYPE_UNCONNECTED state.
+ */
+ ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
+ error("PLL is not locked - Failed to initialize lane %d\n",
+ lane);
+ }
+ }
+
+ debug_exit();
+ return 0;
+}
diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h
new file mode 100644
index 0000000..179e910
--- /dev/null
+++ b/drivers/phy/marvell/comphy_hpipe.h
@@ -0,0 +1,420 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _COMPHY_HPIPE_H_
+#define _COMPHY_HPIPE_H_
+
+/* SerDes IP register */
+#define SD_EXTERNAL_CONFIG0_REG 0
+#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
+#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
+ (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
+#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
+#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
+ (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
+#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
+#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
+ (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
+#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
+#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
+ (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
+#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
+#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
+ (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
+#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
+#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
+ (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
+#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
+#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
+ (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
+
+#define SD_EXTERNAL_CONFIG1_REG 0x4
+#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
+#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
+ (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
+#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
+#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
+ (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
+#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
+#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
+ (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
+#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
+#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
+ (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
+
+#define SD_EXTERNAL_CONFIG2_REG 0x8
+#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
+#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
+ (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
+
+#define SD_EXTERNAL_STATUS0_REG 0x18
+#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
+#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
+ (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
+#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
+#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
+ (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
+#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
+#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
+ (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
+#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
+#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
+ (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
+
+/* HPIPE register */
+#define HPIPE_PWR_PLL_REG 0x4
+#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
+#define HPIPE_PWR_PLL_REF_FREQ_MASK \
+ (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
+#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
+#define HPIPE_PWR_PLL_PHY_MODE_MASK \
+ (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
+
+#define HPIPE_KVCO_CALIB_CTRL_REG 0x8
+#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
+#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
+ (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
+
+#define HPIPE_CAL_REG1_REG 0xc
+#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
+#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
+ (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
+#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
+#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
+ (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
+
+#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
+
+#define HPIPE_DFE_REG0 0x01C
+#define HPIPE_DFE_RES_FORCE_OFFSET 15
+#define HPIPE_DFE_RES_FORCE_MASK \
+ (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
+
+#define HPIPE_DFE_F3_F5_REG 0x028
+#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
+#define HPIPE_DFE_F3_F5_DFE_EN_MASK \
+ (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
+#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
+#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
+ (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
+
+#define HPIPE_G1_SET_0_REG 0x034
+#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
+#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
+ (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
+#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
+#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
+ (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
+
+#define HPIPE_G1_SET_1_REG 0x038
+#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
+#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
+ (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
+#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
+ (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
+#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
+ (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
+
+#define HPIPE_G2_SETTINGS_1_REG 0x040
+
+#define HPIPE_G3_SETTINGS_1_REG 0x048
+#define HPIPE_G3_RX_SELMUPI_OFFSET 0
+#define HPIPE_G3_RX_SELMUPI_MASK \
+ (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET)
+#define HPIPE_G3_RX_SELMUPF_OFFSET 3
+#define HPIPE_G3_RX_SELMUPF_MASK \
+ (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET)
+#define HPIPE_G3_SETTING_BIT_OFFSET 13
+#define HPIPE_G3_SETTING_BIT_MASK \
+ (0x1 << HPIPE_G3_SETTING_BIT_OFFSET)
+
+#define HPIPE_LOOPBACK_REG 0x08c
+#define HPIPE_LOOPBACK_SEL_OFFSET 1
+#define HPIPE_LOOPBACK_SEL_MASK \
+ (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
+
+#define HPIPE_SYNC_PATTERN_REG 0x090
+
+#define HPIPE_INTERFACE_REG 0x94
+#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
+#define HPIPE_INTERFACE_GEN_MAX_MASK \
+ (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
+#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
+#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
+ (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
+
+#define HPIPE_ISOLATE_MODE_REG 0x98
+#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
+#define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
+ (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
+#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
+#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
+ (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
+
+#define HPIPE_G1_SET_2_REG 0xf4
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
+ (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
+ (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
+
+#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
+
+#define HPIPE_PCIE_REG0 0x120
+#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
+#define HPIPE_PCIE_IDLE_SYNC_MASK \
+ (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
+#define HPIPE_PCIE_SEL_BITS_OFFSET 13
+#define HPIPE_PCIE_SEL_BITS_MASK \
+ (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
+
+#define HPIPE_LANE_ALIGN_REG 0x124
+#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
+#define HPIPE_LANE_ALIGN_OFF_MASK \
+ (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
+
+#define HPIPE_MISC_REG 0x13C
+#define HPIPE_MISC_CLK100M_125M_OFFSET 4
+#define HPIPE_MISC_CLK100M_125M_MASK \
+ (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
+#define HPIPE_MISC_ICP_FORCE_OFFSET 5
+#define HPIPE_MISC_ICP_FORCE_MASK \
+ (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
+#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
+#define HPIPE_MISC_TXDCLK_2X_MASK \
+ (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
+#define HPIPE_MISC_CLK500_EN_OFFSET 7
+#define HPIPE_MISC_CLK500_EN_MASK \
+ (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
+#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
+#define HPIPE_MISC_REFCLK_SEL_MASK \
+ (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
+
+#define HPIPE_RX_CONTROL_1_REG 0x140
+#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
+#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
+ (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
+#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
+#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
+ (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
+
+#define HPIPE_PWR_CTR_REG 0x148
+#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
+#define HPIPE_PWR_CTR_RST_DFE_MASK \
+ (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
+#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
+#define HPIPE_PWR_CTR_SFT_RST_MASK \
+ (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
+
+#define HPIPE_PLLINTP_REG1 0x150
+
+#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
+#define HPIPE_SMAPLER_OFFSET 12
+#define HPIPE_SMAPLER_MASK \
+ (0x1 << HPIPE_SMAPLER_OFFSET)
+
+#define HPIPE_TX_REG1_REG 0x174
+#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
+#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
+ (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
+#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
+#define HPIPE_TX_REG1_SLC_EN_MASK \
+ (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
+
+#define HPIPE_PWR_CTR_DTL_REG 0x184
+#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
+#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
+ (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
+
+#define HPIPE_RX_REG3 0x188
+
+#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
+#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
+#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
+ (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
+
+#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
+#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
+#define HPIPE_TX_TRAIN_CTRL_G1_MASK \
+ (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
+#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
+#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
+ (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
+#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
+#define HPIPE_TX_TRAIN_CTRL_G0_MASK \
+ (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
+
+#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
+#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
+#define HPIPE_TRX_TRAIN_TIMER_MASK \
+ (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
+
+#define HPIPE_PCIE_REG1 0x288
+#define HPIPE_PCIE_REG3 0x290
+
+#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
+#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
+#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
+ (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
+#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
+#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
+ (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
+#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
+#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
+ (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
+#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
+#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
+ (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
+
+#define HPIPE_TX_TRAIN_REG 0x31C
+#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
+#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
+ (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
+#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
+#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
+ (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
+
+#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
+#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
+#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
+ (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
+#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
+#define HPIPE_TX_NUM_OF_PRESET_MASK \
+ (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
+#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
+#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
+ (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
+
+#define HPIPE_G1_SETTINGS_3_REG 0x440
+#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
+#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
+ (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
+
+#define HPIPE_G1_SETTINGS_4_REG 0x444
+#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
+#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
+ (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
+
+#define HPIPE_G2_SETTINGS_3_REG 0x448
+#define HPIPE_G2_SETTINGS_4_REG 0x44C
+
+#define HPIPE_G3_SETTING_3_REG 0x450
+#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
+#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
+ (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
+#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
+#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
+ (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
+
+#define HPIPE_G3_SETTING_4_REG 0x454
+#define HPIPE_G3_DFE_RES_OFFSET 8
+#define HPIPE_G3_DFE_RES_MASK \
+ (0x3 << HPIPE_G3_DFE_RES_OFFSET)
+
+#define HPIPE_DFE_CTRL_28_REG 0x49C
+#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
+#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
+ (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
+
+#define HPIPE_G1_SETTING_5_REG 0x538
+#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
+#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
+ (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
+
+#define HPIPE_LANE_CONFIG0_REG 0x600
+#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
+#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
+ (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
+
+#define HPIPE_LANE_CONFIG1_REG 0x604
+#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
+#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
+ (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
+#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
+#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
+ (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
+
+#define HPIPE_LANE_STATUS1_REG 0x60C
+#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
+#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
+ (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
+
+#define HPIPE_LANE_CFG4_REG 0x620
+#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
+#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
+ (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
+#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
+#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
+ (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
+#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
+#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
+ (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
+
+#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
+#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
+#define HPIPE_CFG_PHY_RC_EP_MASK \
+ (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
+
+#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
+#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
+#define HPIPE_CFG_UPDATE_POLARITY_MASK \
+ (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
+
+#define HPIPE_RST_CLK_CTRL_REG 0x704
+#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
+#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
+ (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
+#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
+#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
+ (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
+#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
+#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
+ (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
+#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
+#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
+ (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
+
+#define HPIPE_TST_MODE_CTRL_REG 0x708
+#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
+#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
+ (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
+
+#define HPIPE_CLK_SRC_LO_REG 0x70c
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
+ (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
+#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
+ (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
+#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
+#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
+ (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
+
+#define HPIPE_CLK_SRC_HI_REG 0x710
+#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
+#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
+ (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
+#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
+#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
+ (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
+#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
+#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
+ (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
+#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
+#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
+ (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
+
+#define HPIPE_GLOBAL_MISC_CTRL 0x718
+#define HPIPE_GLOBAL_PM_CTRL 0x740
+#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
+#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
+ (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
+
+#endif /* _COMPHY_HPIPE_H_ */
+
diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c
new file mode 100644
index 0000000..1dc7426
--- /dev/null
+++ b/drivers/phy/marvell/comphy_mux.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "comphy.h"
+#include "comphy_hpipe.h"
+
+/*
+ * comphy_mux_check_config()
+ * description: this function passes over the COMPHY lanes and check if the type
+ * is valid for specific lane. If the type is not valid,
+ * the function update the struct and set the type of the lane as
+ * PHY_TYPE_UNCONNECTED
+ */
+static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
+ struct comphy_map *comphy_map_data, int comphy_max_lanes)
+{
+ struct comphy_mux_options *mux_opt;
+ int lane, opt, valid;
+
+ debug_enter();
+
+ for (lane = 0; lane < comphy_max_lanes;
+ lane++, comphy_map_data++, mux_data++) {
+ mux_opt = mux_data->mux_values;
+ for (opt = 0, valid = 0; opt < mux_data->max_lane_values;
+ opt++, mux_opt++) {
+ if (mux_opt->type == comphy_map_data->type) {
+ valid = 1;
+ break;
+ }
+ }
+ if (valid == 0) {
+ debug("lane number %d, had invalid type %d\n",
+ lane, comphy_map_data->type);
+ debug("set lane %d as type %d\n", lane,
+ PHY_TYPE_UNCONNECTED);
+ comphy_map_data->type = PHY_TYPE_UNCONNECTED;
+ } else {
+ debug("lane number %d, has type %d\n",
+ lane, comphy_map_data->type);
+ }
+ }
+
+ debug_exit();
+}
+
+static u32 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data,
+ u32 type, int lane)
+{
+ struct comphy_mux_options *mux_opt;
+ int opt;
+ u32 value = 0;
+
+ debug_enter();
+
+ mux_opt = mux_data->mux_values;
+ for (opt = 0 ; opt < mux_data->max_lane_values; opt++, mux_opt++) {
+ if (mux_opt->type == type) {
+ value = mux_opt->mux_value;
+ break;
+ }
+ }
+
+ debug_exit();
+
+ return value;
+}
+
+static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,
+ struct comphy_map *comphy_map_data,
+ int comphy_max_lanes,
+ void __iomem *selector_base, u32 bitcount)
+{
+ u32 lane, value, offset, mask;
+
+ debug_enter();
+
+ for (lane = 0; lane < comphy_max_lanes;
+ lane++, comphy_map_data++, mux_data++) {
+ offset = lane * bitcount;
+ mask = (((1 << bitcount) - 1) << offset);
+ value = (comphy_mux_get_mux_value(mux_data,
+ comphy_map_data->type,
+ lane) << offset);
+ reg_set(selector_base, value, mask);
+ }
+
+ debug_exit();
+}
+
+void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg,
+ struct comphy_map *comphy_map_data,
+ void __iomem *selector_base)
+{
+ struct comphy_mux_data *mux_data;
+ u32 mux_bitcount;
+ u32 comphy_max_lanes;
+
+ debug_enter();
+
+ comphy_max_lanes = chip_cfg->comphy_lanes_count;
+ mux_data = chip_cfg->mux_data;
+ mux_bitcount = chip_cfg->comphy_mux_bitcount;
+
+ /* check if the configuration is valid */
+ comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes);
+ /* Init COMPHY selectors */
+ comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes,
+ selector_base, mux_bitcount);
+
+ debug_exit();
+}
diff --git a/drivers/phy/marvell/sata.h b/drivers/phy/marvell/sata.h
new file mode 100644
index 0000000..be2ba54
--- /dev/null
+++ b/drivers/phy/marvell/sata.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SATA_H_
+#define _SATA_H_
+
+/* SATA3 Unit address */
+#define SATA3_VENDOR_ADDRESS 0xA0
+#define SATA3_VENDOR_ADDR_OFSSET 0
+#define SATA3_VENDOR_ADDR_MASK (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET)
+#define SATA3_VENDOR_DATA 0xA4
+
+#define SATA_CONTROL_REG 0x0
+#define SATA3_CTRL_SATA0_PD_OFFSET 6
+#define SATA3_CTRL_SATA0_PD_MASK (1 << SATA3_CTRL_SATA0_PD_OFFSET)
+#define SATA3_CTRL_SATA1_PD_OFFSET 14
+#define SATA3_CTRL_SATA1_PD_MASK (1 << SATA3_CTRL_SATA1_PD_OFFSET)
+#define SATA3_CTRL_SATA1_ENABLE_OFFSET 22
+#define SATA3_CTRL_SATA1_ENABLE_MASK (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET)
+#define SATA3_CTRL_SATA_SSU_OFFSET 23
+#define SATA3_CTRL_SATA_SSU_MASK (1 << SATA3_CTRL_SATA_SSU_OFFSET)
+
+#define SATA_MBUS_SIZE_SELECT_REG 0x4
+#define SATA_MBUS_REGRET_EN_OFFSET 7
+#define SATA_MBUS_REGRET_EN_MASK (0x1 << SATA_MBUS_REGRET_EN_OFFSET)
+
+#endif /* _SATA_H_ */
diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h
new file mode 100644
index 0000000..01e53ba
--- /dev/null
+++ b/drivers/phy/marvell/utmi_phy.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _UTMI_PHY_H_
+#define _UTMI_PHY_H_
+
+#define UTMI_USB_CFG_DEVICE_EN_OFFSET 0
+#define UTMI_USB_CFG_DEVICE_EN_MASK \
+ (0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET)
+#define UTMI_USB_CFG_DEVICE_MUX_OFFSET 1
+#define UTMI_USB_CFG_DEVICE_MUX_MASK \
+ (0x1 << UTMI_USB_CFG_DEVICE_MUX_OFFSET)
+#define UTMI_USB_CFG_PLL_OFFSET 25
+#define UTMI_USB_CFG_PLL_MASK \
+ (0x1 << UTMI_USB_CFG_PLL_OFFSET)
+
+#define UTMI_PHY_CFG_PU_OFFSET 5
+#define UTMI_PHY_CFG_PU_MASK \
+ (0x1 << UTMI_PHY_CFG_PU_OFFSET)
+
+#define UTMI_PLL_CTRL_REG 0x0
+#define UTMI_PLL_CTRL_REFDIV_OFFSET 0
+#define UTMI_PLL_CTRL_REFDIV_MASK \
+ (0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET)
+#define UTMI_PLL_CTRL_FBDIV_OFFSET 16
+#define UTMI_PLL_CTRL_FBDIV_MASK \
+ (0x1FF << UTMI_PLL_CTRL_FBDIV_OFFSET)
+#define UTMI_PLL_CTRL_SEL_LPFR_OFFSET 28
+#define UTMI_PLL_CTRL_SEL_LPFR_MASK \
+ (0x3 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET)
+#define UTMI_PLL_CTRL_PLL_RDY_OFFSET 31
+#define UTMI_PLL_CTRL_PLL_RDY_MASK \
+ (0x1 << UTMI_PLL_CTRL_PLL_RDY_OFFSET)
+
+#define UTMI_CALIB_CTRL_REG 0x8
+#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8
+#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \
+ (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
+#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23
+#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \
+ (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
+#define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31
+#define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \
+ (0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
+
+#define UTMI_TX_CH_CTRL_REG 0xC
+#define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12
+#define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \
+ (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
+#define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16
+#define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \
+ (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
+
+#define UTMI_RX_CH_CTRL0_REG 0x14
+#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
+#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
+ (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
+#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28
+#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \
+ (0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
+
+#define UTMI_RX_CH_CTRL1_REG 0x18
+#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0
+#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \
+ (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
+#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3
+#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \
+ (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
+
+#define UTMI_CTRL_STATUS0_REG 0x24
+#define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22
+#define UTMI_CTRL_STATUS0_SUSPENDM_MASK \
+ (0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
+#define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET 25
+#define UTMI_CTRL_STATUS0_TEST_SEL_MASK \
+ (0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
+
+#define UTMI_CHGDTC_CTRL_REG 0x38
+#define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8
+#define UTMI_CHGDTC_CTRL_VDAT_MASK \
+ (0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
+#define UTMI_CHGDTC_CTRL_VSRC_OFFSET 10
+#define UTMI_CHGDTC_CTRL_VSRC_MASK \
+ (0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET)
+
+#endif /* _UTMI_PHY_H_ */
+
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f8cfd4b..efcb4c0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -148,6 +148,15 @@
This option is to enable the AT91 pinctrl driver for AT91 PIO4
controller which is available on SAMA5D2 SoC.
+config ROCKCHIP_RK3399_PINCTRL
+ bool "Rockchip pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rk3399 SoCs. The driver
+ is controlled by a device tree node which contains both the GPIO
+ definitions and pin control functions for each available multiplex
+ function.
+
config PINCTRL_SANDBOX
bool "Sandbox pinctrl driver"
depends on SANDBOX
@@ -172,5 +181,6 @@
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
+source "drivers/pinctrl/mvebu/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f28b5c1..512112a 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -15,3 +15,4 @@
obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON) += meson/
+obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c
index a28405f..dd0a16e 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -71,7 +71,7 @@
{
const void *fdt = gd->fdt_blob;
int node = config->of_offset;
- unsigned int count, idx, pin_num, ret;
+ unsigned int count, idx, pin_num;
unsigned int pinfunc, pinpud, pindrv;
unsigned long reg, value;
const char *name;
@@ -80,7 +80,7 @@
* refer to the following document for the pinctrl bindings
* linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
*/
- count = fdt_count_strings(fdt, node, "samsung,pins");
+ count = fdt_stringlist_count(fdt, node, "samsung,pins");
if (count <= 0)
return -EINVAL;
@@ -89,9 +89,8 @@
pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
for (idx = 0; idx < count; idx++) {
- ret = fdt_get_string_index(fdt, node, "samsung,pins",
- idx, &name);
- if (ret < 0)
+ name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
+ if (!name)
continue;
reg = pin_to_bank_base(dev, name, &pin_num);
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index d21a3dd..30f7cfc 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -122,7 +122,7 @@
int index, len = 0;
const fdt32_t *reg;
- index = fdt_find_string(gd->fdt_blob, offset, "reg-names", name);
+ index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", name);
if (index < 0)
return FDT_ADDR_T_NONE;
@@ -154,7 +154,7 @@
return -EINVAL;
}
- fdt_for_each_subnode(gd->fdt_blob, node, dev->of_offset) {
+ fdt_for_each_subnode(node, gd->fdt_blob, dev->of_offset) {
if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
gpio = node;
break;
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
new file mode 100644
index 0000000..cf9c299
--- /dev/null
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -0,0 +1,7 @@
+config PINCTRL_MVEBU
+ depends on ARCH_MVEBU
+ bool
+ default y
+ help
+ Support pin multiplexing and pin configuration control on
+ Marvell's Armada-8K SoC.
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
new file mode 100644
index 0000000..f4f7864
--- /dev/null
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0
+# https://spdx.org/licenses
+
+obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
new file mode 100644
index 0000000..b077639
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <config.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/arch-armada8k/soc-info.h>
+#include "pinctrl-mvebu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * mvebu_pinctrl_set_state: configure pin functions.
+ * @dev: the pinctrl device to be configured.
+ * @config: the state to be configured.
+ * @return: 0 in success
+ */
+int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ const void *blob = gd->fdt_blob;
+ int node = config->of_offset;
+ struct mvebu_pinctrl_priv *priv;
+ u32 pin_arr[MVEBU_MAX_PINS_PER_BANK];
+ u32 function;
+ int i, pin_count;
+
+ priv = dev_get_priv(dev);
+
+ pin_count = fdtdec_get_int_array_count(blob, node,
+ "marvell,pins",
+ pin_arr,
+ MVEBU_MAX_PINS_PER_BANK);
+ if (pin_count <= 0) {
+ debug("Failed reading pins array for pinconfig %s (%d)\n",
+ config->name, pin_count);
+ return -EINVAL;
+ }
+
+ function = fdtdec_get_int(blob, node, "marvell,function", 0xff);
+
+ for (i = 0; i < pin_count; i++) {
+ int reg_offset;
+ int field_offset;
+ int pin = pin_arr[i];
+
+ if (function > priv->max_func) {
+ debug("Illegal function %d for pinconfig %s\n",
+ function, config->name);
+ return -EINVAL;
+ }
+
+ /* Calculate register address and bit in register */
+ reg_offset = priv->reg_direction * 4 *
+ (pin >> (PIN_REG_SHIFT));
+ field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK);
+
+ clrsetbits_le32(priv->base_reg + reg_offset,
+ PIN_FUNC_MASK << field_offset,
+ (function & PIN_FUNC_MASK) << field_offset);
+ }
+
+ return 0;
+}
+
+/*
+ * mvebu_pinctrl_set_state_all: configure the entire bank pin functions.
+ * @dev: the pinctrl device to be configured.
+ * @config: the state to be configured.
+ * @return: 0 in success
+ */
+static int mvebu_pinctrl_set_state_all(struct udevice *dev,
+ struct udevice *config)
+{
+ const void *blob = gd->fdt_blob;
+ int node = config->of_offset;
+ struct mvebu_pinctrl_priv *priv;
+ u32 func_arr[MVEBU_MAX_PINS_PER_BANK];
+ int pin, err;
+
+ priv = dev_get_priv(dev);
+
+ err = fdtdec_get_int_array(blob, node, "pin-func",
+ func_arr, priv->pin_cnt);
+ if (err) {
+ debug("Failed reading pin functions for bank %s\n",
+ priv->bank_name);
+ return -EINVAL;
+ }
+
+ for (pin = 0; pin < priv->pin_cnt; pin++) {
+ int reg_offset;
+ int field_offset;
+ u32 func = func_arr[pin];
+
+ /* Bypass pins with function 0xFF */
+ if (func == 0xff) {
+ debug("Warning: pin %d value is not modified ", pin);
+ debug("(kept as default)\n");
+ continue;
+ } else if (func > priv->max_func) {
+ debug("Illegal function %d for pin %d\n", func, pin);
+ return -EINVAL;
+ }
+
+ /* Calculate register address and bit in register */
+ reg_offset = priv->reg_direction * 4 *
+ (pin >> (PIN_REG_SHIFT));
+ field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK);
+
+ clrsetbits_le32(priv->base_reg + reg_offset,
+ PIN_FUNC_MASK << field_offset,
+ (func & PIN_FUNC_MASK) << field_offset);
+ }
+
+ return 0;
+}
+
+int mvebu_pinctl_probe(struct udevice *dev)
+{
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ struct mvebu_pinctrl_priv *priv;
+
+ priv = dev_get_priv(dev);
+ if (!priv) {
+ debug("%s: Failed to get private\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->base_reg = dev_get_addr_ptr(dev);
+ if (priv->base_reg == (void *)FDT_ADDR_T_NONE) {
+ debug("%s: Failed to get base address\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->pin_cnt = fdtdec_get_int(blob, node, "pin-count",
+ MVEBU_MAX_PINS_PER_BANK);
+ priv->max_func = fdtdec_get_int(blob, node, "max-func",
+ MVEBU_MAX_FUNC);
+ priv->bank_name = fdt_getprop(blob, node, "bank-name", NULL);
+
+ priv->reg_direction = 1;
+ if (fdtdec_get_bool(blob, node, "reverse-reg"))
+ priv->reg_direction = -1;
+
+ return mvebu_pinctrl_set_state_all(dev, dev);
+}
+
+static struct pinctrl_ops mvebu_pinctrl_ops = {
+ .set_state = mvebu_pinctrl_set_state
+};
+
+static const struct udevice_id mvebu_pinctrl_ids[] = {
+ { .compatible = "marvell,mvebu-pinctrl" },
+ { .compatible = "marvell,armada-ap806-pinctrl" },
+ { .compatible = "marvell,a70x0-pinctrl" },
+ { .compatible = "marvell,a80x0-cp0-pinctrl" },
+ { .compatible = "marvell,a80x0-cp1-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_mvebu) = {
+ .name = "mvebu_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mvebu_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct mvebu_pinctrl_priv),
+ .ops = &mvebu_pinctrl_ops,
+ .probe = mvebu_pinctl_probe
+};
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
new file mode 100644
index 0000000..1a1d3ef
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+ #ifndef __PINCTRL_MVEBU_H_
+ #define __PINCTRL_MVEBU_H_
+
+ #define MVEBU_MAX_PINCTL_BANKS 4
+ #define MVEBU_MAX_PINS_PER_BANK 100
+ #define MVEBU_MAX_FUNC 0xF
+
+/*
+ * struct mvebu_pin_bank_data: mvebu-pinctrl bank data
+ * @base_reg: controller base address for this bank
+ * @pin_cnt: number of pins included in this bank
+ * @max_func: maximum configurable function value for pins in this bank
+ * @reg_direction:
+ * @bank_name: the pin's bank name
+ */
+struct mvebu_pinctrl_priv {
+ void *base_reg;
+ uint pin_cnt;
+ uint max_func;
+ int reg_direction;
+ const char *bank_name;
+};
+
+#endif /* __PINCTRL_MVEBU_H_ */
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 35640f0..238f77d 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -1,6 +1,20 @@
config PINCTRL_IMX
bool
+config PINCTRL_IMX5
+ bool "IMX5 pinctrl driver"
+ depends on ARCH_MX5 && PINCTRL_FULL
+ select DEVRES
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx5 pinctrl driver
+
+ This provides a simple pinctrl driver for i.MX 53SoC familiy,
+ i.MX53. This feature depends on device tree
+ configuration. This driver is different from the linux one,
+ this is a simple implementation, only parses the 'fsl,pins'
+ property and configure related registers.
+
config PINCTRL_IMX6
bool "IMX6 pinctrl driver"
depends on ARCH_MX6 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index 0ee7f2f..e0f7325 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o
obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o
obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c
index 40b0616..949d0f3 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx.c
@@ -222,7 +222,7 @@
return -ENOMEM;
}
- dev_info(dev, "initialized IMX pinctrl driver\n");
+ dev_dbg(dev, "initialized IMX pinctrl driver\n");
return 0;
}
diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c
new file mode 100644
index 0000000..6942f39
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx5.c
@@ -0,0 +1,44 @@
+
+/*
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imx5_pinctrl_soc_info;
+
+static int imx5_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_pinctrl_soc_info *info =
+ (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imx5_pinctrl_match[] = {
+ {
+ .compatible = "fsl,imx53-iomuxc",
+ .data = (ulong)&imx5_pinctrl_soc_info
+ },
+ {
+ .compatible = "fsl,imx53-iomuxc-gpr",
+ .data = (ulong)&imx5_pinctrl_soc_info
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imx5_pinctrl) = {
+ .name = "imx5-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imx5_pinctrl_match),
+ .probe = imx5_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .ops = &imx_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c
index 24f139e..4488b16 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx6.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
@@ -12,6 +12,10 @@
static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info;
+static struct imx_pinctrl_soc_info imx6_snvs_pinctrl_soc_info = {
+ .flags = ZERO_OFFSET_VALID,
+};
+
static int imx6_pinctrl_probe(struct udevice *dev)
{
struct imx_pinctrl_soc_info *info =
@@ -24,8 +28,11 @@
{ .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6sl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
+ { .compatible = "fsl,imx6sll-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info },
+ { .compatible = "fsl,imx6sll-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
+ { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info },
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
index baff40f..3629322 100644
--- a/drivers/pinctrl/pinctrl-generic.c
+++ b/drivers/pinctrl/pinctrl-generic.c
@@ -306,12 +306,12 @@
const char *name;
int strings_count, selector, i, ret;
- strings_count = fdt_count_strings(fdt, node, subnode_target_type);
+ strings_count = fdt_stringlist_count(fdt, node, subnode_target_type);
if (strings_count < 0) {
subnode_target_type = "groups";
is_group = true;
- strings_count = fdt_count_strings(fdt, node,
- subnode_target_type);
+ strings_count = fdt_stringlist_count(fdt, node,
+ subnode_target_type);
if (strings_count < 0) {
/* skip this node; may contain config child nodes */
return 0;
@@ -319,9 +319,9 @@
}
for (i = 0; i < strings_count; i++) {
- ret = fdt_get_string_index(fdt, node, subnode_target_type,
- i, &name);
- if (ret < 0)
+ name = fdt_stringlist_get(fdt, node, subnode_target_type, i,
+ NULL);
+ if (!name)
return -EINVAL;
if (is_group)
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index 7397de2..02ab9b4 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -72,7 +72,7 @@
struct udevice *config;
int state, size, i, ret;
- state = fdt_find_string(fdt, node, "pinctrl-names", statename);
+ state = fdt_stringlist_search(fdt, node, "pinctrl-names", statename);
if (state < 0) {
char *end;
/*
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 64e9587..805c833 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -7,3 +7,4 @@
obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3399_PINCTRL) += pinctrl_rk3399.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
new file mode 100644
index 0000000..17ea165
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -0,0 +1,439 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/grf_rk3399.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/clock.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3399_pinctrl_priv {
+ struct rk3399_grf_regs *grf;
+ struct rk3399_pmugrf_regs *pmugrf;
+};
+
+enum {
+ /* GRF_GPIO2B_IOMUX */
+ GRF_GPIO2B1_SEL_SHIFT = 0,
+ GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
+ GRF_SPI2TPM_RXD = 1,
+ GRF_GPIO2B2_SEL_SHIFT = 2,
+ GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
+ GRF_SPI2TPM_TXD = 1,
+ GRF_GPIO2B3_SEL_SHIFT = 6,
+ GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT,
+ GRF_SPI2TPM_CLK = 1,
+ GRF_GPIO2B4_SEL_SHIFT = 8,
+ GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
+ GRF_SPI2TPM_CSN0 = 1,
+
+ /* GRF_GPIO3A_IOMUX */
+ GRF_GPIO3A4_SEL_SHIFT = 8,
+ GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT,
+ GRF_SPI0NORCODEC_RXD = 2,
+ GRF_GPIO3A5_SEL_SHIFT = 10,
+ GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT,
+ GRF_SPI0NORCODEC_TXD = 2,
+ GRF_GPIO3A6_SEL_SHIFT = 12,
+ GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT,
+ GRF_SPI0NORCODEC_CLK = 2,
+ GRF_GPIO3A7_SEL_SHIFT = 14,
+ GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT,
+ GRF_SPI0NORCODEC_CSN0 = 2,
+
+ /* GRF_GPIO3B_IOMUX */
+ GRF_GPIO3B0_SEL_SHIFT = 0,
+ GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT,
+ GRF_SPI0NORCODEC_CSN1 = 2,
+
+ /* GRF_GPIO4B_IOMUX */
+ GRF_GPIO4B0_SEL_SHIFT = 0,
+ GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT,
+ GRF_SDMMC_DATA0 = 1,
+ GRF_UART2DBGA_SIN = 2,
+ GRF_GPIO4B1_SEL_SHIFT = 2,
+ GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT,
+ GRF_SDMMC_DATA1 = 1,
+ GRF_UART2DBGA_SOUT = 2,
+ GRF_GPIO4B2_SEL_SHIFT = 4,
+ GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT,
+ GRF_SDMMC_DATA2 = 1,
+ GRF_GPIO4B3_SEL_SHIFT = 6,
+ GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT,
+ GRF_SDMMC_DATA3 = 1,
+ GRF_GPIO4B4_SEL_SHIFT = 8,
+ GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT,
+ GRF_SDMMC_CLKOUT = 1,
+ GRF_GPIO4B5_SEL_SHIFT = 10,
+ GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT,
+ GRF_SDMMC_CMD = 1,
+
+ /* GRF_GPIO4C_IOMUX */
+ GRF_GPIO4C2_SEL_SHIFT = 4,
+ GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
+ GRF_PWM_0 = 1,
+ GRF_GPIO4C3_SEL_SHIFT = 6,
+ GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
+ GRF_UART2DGBC_SIN = 1,
+ GRF_GPIO4C4_SEL_SHIFT = 8,
+ GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
+ GRF_UART2DBGC_SOUT = 1,
+ GRF_GPIO4C6_SEL_SHIFT = 12,
+ GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT,
+ GRF_PWM_1 = 1,
+
+ /* PMUGRF_GPIO0A_IOMUX */
+ PMUGRF_GPIO0A6_SEL_SHIFT = 12,
+ PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
+ PMUGRF_PWM_3A = 1,
+
+ /* PMUGRF_GPIO1A_IOMUX */
+ PMUGRF_GPIO1A7_SEL_SHIFT = 14,
+ PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
+ PMUGRF_SPI1EC_RXD = 2,
+
+ /* PMUGRF_GPIO1B_IOMUX */
+ PMUGRF_GPIO1B0_SEL_SHIFT = 0,
+ PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
+ PMUGRF_SPI1EC_TXD = 2,
+ PMUGRF_GPIO1B1_SEL_SHIFT = 2,
+ PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
+ PMUGRF_SPI1EC_CLK = 2,
+ PMUGRF_GPIO1B2_SEL_SHIFT = 4,
+ PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
+ PMUGRF_SPI1EC_CSN0 = 2,
+ PMUGRF_GPIO1B6_SEL_SHIFT = 12,
+ PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
+ PMUGRF_PWM_3B = 1,
+ PMUGRF_GPIO1B7_SEL_SHIFT = 14,
+ PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
+ PMUGRF_I2C0PMU_SDA = 2,
+
+ /* PMUGRF_GPIO1C_IOMUX */
+ PMUGRF_GPIO1C0_SEL_SHIFT = 0,
+ PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
+ PMUGRF_I2C0PMU_SCL = 2,
+ PMUGRF_GPIO1C3_SEL_SHIFT = 6,
+ PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
+ PMUGRF_PWM_2 = 1,
+
+};
+static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
+ struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
+{
+ switch (pwm_id) {
+ case PERIPH_ID_PWM0:
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GRF_GPIO4C2_SEL_MASK,
+ GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
+ break;
+ case PERIPH_ID_PWM1:
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GRF_GPIO4C6_SEL_MASK,
+ GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
+ break;
+ case PERIPH_ID_PWM2:
+ rk_clrsetreg(&pmugrf->gpio1c_iomux,
+ PMUGRF_GPIO1C3_SEL_MASK,
+ PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
+ break;
+ case PERIPH_ID_PWM3:
+ if (readl(&pmugrf->soc_con0) & (1 << 5))
+ rk_clrsetreg(&pmugrf->gpio1b_iomux,
+ PMUGRF_GPIO1B6_SEL_MASK,
+ PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
+ else
+ rk_clrsetreg(&pmugrf->gpio0a_iomux,
+ PMUGRF_GPIO0A6_SEL_MASK,
+ PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
+ break;
+ default:
+ debug("pwm id = %d iomux error!\n", pwm_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
+ struct rk3399_pmugrf_regs *pmugrf,
+ int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ rk_clrsetreg(&pmugrf->gpio1b_iomux,
+ PMUGRF_GPIO1B7_SEL_MASK,
+ PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
+ rk_clrsetreg(&pmugrf->gpio1c_iomux,
+ PMUGRF_GPIO1C0_SEL_MASK,
+ PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ default:
+ debug("i2c id = %d iomux error!\n", i2c_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
+{
+ switch (lcd_id) {
+ case PERIPH_ID_LCDC0:
+ break;
+ default:
+ debug("lcdc id = %d iomux error!\n", lcd_id);
+ break;
+ }
+}
+
+static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
+ struct rk3399_pmugrf_regs *pmugrf,
+ enum periph_id spi_id, int cs)
+{
+ switch (spi_id) {
+ case PERIPH_ID_SPI0:
+ switch (cs) {
+ case 0:
+ rk_clrsetreg(&grf->gpio3a_iomux,
+ GRF_GPIO3A7_SEL_MASK,
+ GRF_SPI0NORCODEC_CSN0
+ << GRF_GPIO3A7_SEL_SHIFT);
+ break;
+ case 1:
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GRF_GPIO3B0_SEL_MASK,
+ GRF_SPI0NORCODEC_CSN1
+ << GRF_GPIO3B0_SEL_SHIFT);
+ break;
+ default:
+ goto err;
+ }
+ rk_clrsetreg(&grf->gpio3a_iomux,
+ GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
+ | GRF_GPIO3A6_SEL_SHIFT,
+ GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
+ | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
+ | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
+ break;
+ case PERIPH_ID_SPI1:
+ if (cs != 0)
+ goto err;
+ rk_clrsetreg(&pmugrf->gpio1a_iomux,
+ PMUGRF_GPIO1A7_SEL_MASK,
+ PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
+ rk_clrsetreg(&pmugrf->gpio1b_iomux,
+ PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
+ | PMUGRF_GPIO1B2_SEL_MASK,
+ PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
+ | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
+ | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
+ break;
+ case PERIPH_ID_SPI2:
+ if (cs != 0)
+ goto err;
+ rk_clrsetreg(&grf->gpio2b_iomux,
+ GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
+ | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
+ GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
+ | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
+ | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
+ | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
+ break;
+ default:
+ goto err;
+ }
+
+ return 0;
+err:
+ debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
+ return -ENOENT;
+}
+
+static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
+ struct rk3399_pmugrf_regs *pmugrf,
+ int uart_id)
+{
+ switch (uart_id) {
+ case PERIPH_ID_UART2:
+ /* Using channel-C by default */
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GRF_GPIO4C3_SEL_MASK,
+ GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GRF_GPIO4C4_SEL_MASK,
+ GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
+ break;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_UART4:
+ default:
+ debug("uart id = %d iomux error!\n", uart_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ break;
+ case PERIPH_ID_SDCARD:
+ rk_clrsetreg(&grf->gpio4b_iomux,
+ GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
+ | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
+ | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
+ GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
+ | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
+ | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
+ | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
+ | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
+ | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
+ break;
+ default:
+ debug("mmc id = %d iomux error!\n", mmc_id);
+ break;
+ }
+}
+
+static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ case PERIPH_ID_PWM4:
+ pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
+ break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
+ break;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_UART4:
+ pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
+ break;
+ case PERIPH_ID_LCDC0:
+ case PERIPH_ID_LCDC1:
+ pinctrl_rk3399_lcdc_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ pinctrl_rk3399_sdmmc_config(priv->grf, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[3];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[1]) {
+ case 68:
+ return PERIPH_ID_SPI0;
+ case 53:
+ return PERIPH_ID_SPI1;
+ case 52:
+ return PERIPH_ID_SPI2;
+ case 57:
+ return PERIPH_ID_I2C0;
+ case 59: /* Note strange order */
+ return PERIPH_ID_I2C1;
+ case 35:
+ return PERIPH_ID_I2C2;
+ case 34:
+ return PERIPH_ID_I2C3;
+ case 56:
+ return PERIPH_ID_I2C4;
+ case 38:
+ return PERIPH_ID_I2C5;
+ case 65:
+ return PERIPH_ID_SDMMC1;
+ }
+
+ return -ENOENT;
+}
+
+static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = rk3399_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+
+ return rk3399_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk3399_pinctrl_ops = {
+ .set_state_simple = rk3399_pinctrl_set_state_simple,
+ .request = rk3399_pinctrl_request,
+ .get_periph_id = rk3399_pinctrl_get_periph_id,
+};
+
+static int rk3399_pinctrl_probe(struct udevice *dev)
+{
+ struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret = 0;
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+ debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
+
+ return ret;
+}
+
+static const struct udevice_id rk3399_pinctrl_ids[] = {
+ { .compatible = "rockchip,rk3399-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3399) = {
+ .name = "rockchip_rk3399_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3399_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
+ .ops = &rk3399_pinctrl_ops,
+ .bind = dm_scan_fdt_dev,
+ .probe = rk3399_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 7febea2..689e576 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -3,6 +3,12 @@
config PINCTRL_UNIPHIER
bool
+config PINCTRL_UNIPHIER_SLD3
+ bool "UniPhier PH1-sLD3 SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_SLD3
+ default y
+ select PINCTRL_UNIPHIER
+
config PINCTRL_UNIPHIER_LD4
bool "UniPhier PH1-LD4 SoC pinctrl driver"
depends on ARCH_UNIPHIER_LD4
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index 4de251b..fd003ad 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -4,6 +4,7 @@
obj-y += pinctrl-uniphier-core.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3) += pinctrl-uniphier-sld3.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 3f891f1..51144b8 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -13,6 +13,10 @@
#include "pinctrl-uniphier.h"
+#define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
+#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
+#define UNIPHIER_PINCTRL_IECTRL 0x1d00
+
static const char *uniphier_pinctrl_dummy_name = "_dummy";
static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
@@ -101,8 +105,10 @@
int muxval)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
- unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
- bool load_pinctrl;
+ unsigned reg, reg_end, shift, mask;
+ unsigned mux_bits = 8;
+ unsigned reg_stride = 4;
+ bool load_pinctrl = false;
u32 tmp;
/* some pins need input-enabling */
@@ -111,24 +117,18 @@
if (muxval < 0)
return; /* dedicated pin; nothing to do for pin-mux */
+ if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT)
+ mux_bits = 4;
+
if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
/*
* Mode offset bit
* Normal 4 * n shift+3:shift
* Debug 4 * n shift+7:shift+4
*/
- mux_bits = 4;
+ mux_bits /= 2;
reg_stride = 8;
load_pinctrl = true;
- } else {
- /*
- * Mode offset bit
- * Normal 8 * n shift+3:shift
- * Debug 8 * n + 4 shift+3:shift
- */
- mux_bits = 8;
- reg_stride = 4;
- load_pinctrl = false;
}
reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index e42602b..1d318d8 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -28,6 +28,12 @@
static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17};
static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
+ 14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2};
+static const unsigned system_bus_cs1_pins[] = {0};
+static const int system_bus_cs1_muxvals[] = {0};
static const unsigned uart0_pins[] = {54, 55};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart1_pins[] = {58, 59};
@@ -52,6 +58,8 @@
UNIPHIER_PINCTRL_GROUP(i2c3),
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
+ UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@@ -69,6 +77,7 @@
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index d6ae512..4ca39e6 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -34,6 +34,12 @@
static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
static const int sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3}; /* No SDVOLC */
+static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
+ 14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2};
+static const unsigned system_bus_cs1_pins[] = {0};
+static const int system_bus_cs1_muxvals[] = {0};
static const unsigned uart0_pins[] = {54, 55};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart1_pins[] = {58, 59};
@@ -62,6 +68,8 @@
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
+ UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@@ -82,6 +90,7 @@
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 955858a..9b3db9d 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -51,6 +51,18 @@
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {16, 17, 18, 19, 20, 165, 166, 167,
+ 168, 169, 170, 171, 172, 173};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1};
+static const unsigned system_bus_cs0_pins[] = {155};
+static const int system_bus_cs0_muxvals[] = {1};
+static const unsigned system_bus_cs1_pins[] = {174};
+static const int system_bus_cs1_muxvals[] = {-1};
+static const unsigned system_bus_cs2_pins[] = {64};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {156};
+static const int system_bus_cs3_muxvals[] = {1};
static const unsigned uart0_pins[] = {85, 88};
static const int uart0_muxvals[] = {1, 1};
static const unsigned uart1_pins[] = {155, 156};
@@ -82,6 +94,11 @@
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart1b),
@@ -103,6 +120,7 @@
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 5f9407e..80d782c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -48,6 +48,20 @@
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
+ 11, 12, 13};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0};
+static const unsigned system_bus_cs1_pins[] = {14};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned system_bus_cs2_pins[] = {37};
+static const int system_bus_cs2_muxvals[] = {6};
+static const unsigned system_bus_cs3_pins[] = {38};
+static const int system_bus_cs3_muxvals[] = {6};
+static const unsigned system_bus_cs4_pins[] = {115};
+static const int system_bus_cs4_muxvals[] = {6};
+static const unsigned system_bus_cs5_pins[] = {55};
+static const int system_bus_cs5_muxvals[] = {6};
static const unsigned uart0_pins[] = {135, 136};
static const int uart0_muxvals[] = {3, 3};
static const unsigned uart0b_pins[] = {11, 12};
@@ -81,6 +95,12 @@
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
@@ -103,6 +123,7 @@
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index 6f349dc..f1624da 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -53,6 +53,26 @@
static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
327};
static const int sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {25, 26, 27, 28, 29, 30, 31, 32, 33,
+ 34, 35, 36, 37, 38};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0};
+static const unsigned system_bus_cs0_pins[] = {318};
+static const int system_bus_cs0_muxvals[] = {5};
+static const unsigned system_bus_cs1_pins[] = {24};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned system_bus_cs2_pins[] = {315};
+static const int system_bus_cs2_muxvals[] = {5};
+static const unsigned system_bus_cs3_pins[] = {313};
+static const int system_bus_cs3_muxvals[] = {5};
+static const unsigned system_bus_cs4_pins[] = {305};
+static const int system_bus_cs4_muxvals[] = {5};
+static const unsigned system_bus_cs5_pins[] = {303};
+static const int system_bus_cs5_muxvals[] = {6};
+static const unsigned system_bus_cs6_pins[] = {307};
+static const int system_bus_cs6_muxvals[] = {6};
+static const unsigned system_bus_cs7_pins[] = {312};
+static const int system_bus_cs7_muxvals[] = {6};
static const unsigned uart0_pins[] = {127, 128};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart1_pins[] = {129, 130};
@@ -86,6 +106,15 @@
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(sd1),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs6),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@@ -109,6 +138,7 @@
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(sd1),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 268cdea..9670f25 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -50,6 +50,26 @@
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+ 14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0};
+static const unsigned system_bus_cs0_pins[] = {105};
+static const int system_bus_cs0_muxvals[] = {1};
+static const unsigned system_bus_cs1_pins[] = {18};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned system_bus_cs2_pins[] = {106};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {100};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned system_bus_cs4_pins[] = {101};
+static const int system_bus_cs4_muxvals[] = {1};
+static const unsigned system_bus_cs5_pins[] = {102};
+static const int system_bus_cs5_muxvals[] = {1};
+static const unsigned system_bus_cs6_pins[] = {69};
+static const int system_bus_cs6_muxvals[] = {5};
+static const unsigned system_bus_cs7_pins[] = {70};
+static const int system_bus_cs7_muxvals[] = {5};
static const unsigned uart0_pins[] = {47, 48};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart0b_pins[] = {227, 228};
@@ -81,6 +101,15 @@
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs6),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
@@ -101,6 +130,7 @@
UNIPHIER_PINMUX_FUNCTION(i2c6),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index b534274..1d29170 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -53,6 +53,12 @@
static const int nand_cs1_muxvals[] = {8, 8};
static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
static const int sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
+static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
+ 11, 12, 13};
+static const int system_bus_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8};
+static const unsigned system_bus_cs1_pins[] = {14};
+static const int system_bus_cs1_muxvals[] = {8};
static const unsigned uart0_pins[] = {217, 218};
static const int uart0_muxvals[] = {8, 8};
static const unsigned uart0b_pins[] = {179, 180};
@@ -89,6 +95,8 @@
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
@@ -114,6 +122,7 @@
UNIPHIER_PINMUX_FUNCTION(i2c6),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
new file mode 100644
index 0000000..d3a507e
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {55, 56, 60};
+static const int emmc_muxvals[] = {1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {57};
+static const int emmc_dat8_muxvals[] = {1};
+static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112,
+ 113};
+static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2};
+static const unsigned ether_rmii_pins[] = {35};
+static const int ether_rmii_muxvals[] = {1};
+static const unsigned i2c0_pins[] = {36};
+static const int i2c0_muxvals[] = {0};
+static const unsigned nand_pins[] = {38, 39, 40, 58, 59};
+static const int nand_muxvals[] = {1, 1, 1, 1, 1};
+static const unsigned nand_cs1_pins[] = {41};
+static const int nand_cs1_muxvals[] = {1};
+static const unsigned sd_pins[] = {42, 43, 44, 45};
+static const int sd_muxvals[] = {1, 1, 1, 1};
+static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76,
+ 77, 78, 79, 80, 88, 89, 91, 92, 99};
+static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1};
+static const unsigned system_bus_cs0_pins[] = {93};
+static const int system_bus_cs0_muxvals[] = {1};
+static const unsigned system_bus_cs1_pins[] = {94};
+static const int system_bus_cs1_muxvals[] = {1};
+static const unsigned system_bus_cs2_pins[] = {95};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {96};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned system_bus_cs4_pins[] = {81};
+static const int system_bus_cs4_muxvals[] = {1};
+static const unsigned system_bus_cs5_pins[] = {82};
+static const int system_bus_cs5_muxvals[] = {1};
+static const unsigned uart0_pins[] = {63, 64};
+static const int uart0_muxvals[] = {0, 1};
+static const unsigned uart1_pins[] = {65, 66};
+static const int uart1_muxvals[] = {0, 1};
+static const unsigned uart2_pins[] = {96, 102};
+static const int uart2_muxvals[] = {2, 2};
+static const unsigned usb0_pins[] = {13, 14};
+static const int usb0_muxvals[] = {0, 1};
+static const unsigned usb1_pins[] = {15, 16};
+static const int usb1_muxvals[] = {0, 1};
+static const unsigned usb2_pins[] = {17, 18};
+static const int usb2_muxvals[] = {0, 1};
+static const unsigned usb3_pins[] = {19, 20};
+static const int usb3_muxvals[] = {0, 1};
+
+static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = {
+ UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+ UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_mii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+ UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3)
+};
+
+static const char * const uniphier_sld3_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_mii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
+ UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+ UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+ UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
+ UNIPHIER_PINMUX_FUNCTION(usb3),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = {
+ .groups = uniphier_sld3_groups,
+ .groups_count = ARRAY_SIZE(uniphier_sld3_groups),
+ .functions = uniphier_sld3_functions,
+ .functions_count = ARRAY_SIZE(uniphier_sld3_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT,
+};
+
+static int uniphier_sld3_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_sld3_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-sld3-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_sld3_pinctrl) = {
+ .name = "uniphier-sld3-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(uniphier_sld3_pinctrl_match),
+ .probe = uniphier_sld3_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index a85e055..471fb67 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -65,6 +65,20 @@
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {136, 137, 138, 139, 140, 141, 142,
+ 143, 144, 145, 146, 147, 148, 149};
+static const int system_bus_muxvals[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1};
+static const unsigned system_bus_cs1_pins[] = {150};
+static const int system_bus_cs1_muxvals[] = {-1};
+static const unsigned system_bus_cs2_pins[] = {10};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {11};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned system_bus_cs4_pins[] = {12};
+static const int system_bus_cs4_muxvals[] = {1};
+static const unsigned system_bus_cs5_pins[] = {13};
+static const int system_bus_cs5_muxvals[] = {1};
static const unsigned uart0_pins[] = {70, 71};
static const int uart0_muxvals[] = {3, 3};
static const unsigned uart1_pins[] = {114, 115};
@@ -92,6 +106,12 @@
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@@ -111,6 +131,7 @@
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 4de5b03..21e2d37 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -13,10 +13,6 @@
#include <linux/kernel.h>
#include <linux/types.h>
-#define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
-#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
-#define UNIPHIER_PINCTRL_IECTRL 0x1d00
-
#define UNIPHIER_PIN_ATTR_PACKED(iectrl) (iectrl)
static inline unsigned int uniphier_pin_get_iectrl(unsigned long data)
@@ -71,8 +67,9 @@
const char * const *functions;
int functions_count;
unsigned caps;
-#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
-#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
+#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2)
+#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1)
+#define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0)
};
#define UNIPHIER_PINCTRL_PIN(a, b) \
@@ -94,7 +91,12 @@
#define __UNIPHIER_PINMUX_FUNCTION(func) #func
#ifdef CONFIG_SPL_BUILD
-#define UNIPHIER_PINCTRL_GROUP(grp) { .name = NULL }
+ /*
+ * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL,
+ * suppressing "defined but not used" warnings.
+ */
+#define UNIPHIER_PINCTRL_GROUP(grp) \
+ { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) }
#define UNIPHIER_PINMUX_FUNCTION(func) NULL
#else
#define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp)
diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c
index fc162a1..731b75e 100644
--- a/drivers/power/axp209.c
+++ b/drivers/power/axp209.c
@@ -167,6 +167,22 @@
return rc;
}
+ /*
+ * Turn off LDOIO regulators / tri-state GPIO pins, when rebooting
+ * from android these are sometimes on.
+ */
+ rc = pmic_bus_write(AXP_GPIO0_CTRL, AXP_GPIO_CTRL_INPUT);
+ if (rc)
+ return rc;
+
+ rc = pmic_bus_write(AXP_GPIO1_CTRL, AXP_GPIO_CTRL_INPUT);
+ if (rc)
+ return rc;
+
+ rc = pmic_bus_write(AXP_GPIO2_CTRL, AXP_GPIO_CTRL_INPUT);
+ if (rc)
+ return rc;
+
return 0;
}
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index 727ab09..109d3f4 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -223,6 +223,18 @@
if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17))
return -ENODEV;
+ /*
+ * Turn off LDOIO regulators / tri-state GPIO pins, when rebooting
+ * from android these are sometimes on.
+ */
+ ret = pmic_bus_write(AXP_GPIO0_CTRL, AXP_GPIO_CTRL_INPUT);
+ if (ret)
+ return ret;
+
+ ret = pmic_bus_write(AXP_GPIO1_CTRL, AXP_GPIO_CTRL_INPUT);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c
index c8b76cf..c5b608d 100644
--- a/drivers/power/axp809.c
+++ b/drivers/power/axp809.c
@@ -217,13 +217,7 @@
int axp_init(void)
{
- int ret;
-
- ret = pmic_bus_init();
- if (ret)
- return ret;
-
- return 0;
+ return pmic_bus_init();
}
int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 6430fe0..4f9a62c 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -23,11 +23,30 @@
#endif
}
-int palmas_mmc1_poweron_ldo(void)
+#if defined(CONFIG_OMAP54XX)
+int lp873x_mmc1_poweron_ldo(uint voltage)
+{
+ if (palmas_i2c_write_u8(LP873X_LDO1_ADDR, LP873X_LDO1_VOLTAGE,
+ voltage)) {
+ printf("lp873x: could not set LDO1 voltage.\n");
+ return 1;
+ }
+ /* TURN ON LDO1 */
+ if (palmas_i2c_write_u8(LP873X_LDO1_ADDR, LP873X_LDO1_CTRL,
+ LP873X_LDO_CTRL_EN | LP873X_LDO_CTRL_RDIS_EN)) {
+ printf("lp873x: could not turn on LDO1.\n");
+ return 1;
+ }
+ return 0;
+
+}
+#endif
+
+int palmas_mmc1_poweron_ldo(uint voltage)
{
u8 val = 0;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
/*
* Currently valid for the dra7xx_evm board:
* Set TPS659038 LDO1 to 3.0 V
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 69f8d51..5e244c8 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -54,6 +54,13 @@
This config enables implementation of driver-model pmic uclass features
for PMIC MAX77686. The driver implements read/write operations.
+config DM_PMIC_MAX8998
+ bool "Enable Driver Model for PMIC MAX8998"
+ depends on DM_PMIC
+ ---help---
+ This config enables implementation of driver-model pmic uclass features
+ for PMIC MAX8998. The driver implements read/write operations.
+
config PMIC_PM8916
bool "Enable Driver Model for Qualcomm PM8916 PMIC"
depends on DM_PMIC
@@ -127,6 +134,14 @@
driver provides basic register access and sets up the attached
regulators if regulator support is enabled.
+config PMIC_RN5T567
+ bool "Enable driver for Ricoh RN5T567 PMIC"
+ depends on DM_PMIC
+ ---help---
+ The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO
+ regulators Real-Time Clock and 4 GPIOs. This driver provides
+ register access only.
+
config PMIC_TPS65090
bool "Enable driver for Texas Instruments TPS65090 PMIC"
depends on DM_PMIC
@@ -135,3 +150,17 @@
FETs and a battery charger. This driver provides register access
only, and you can enable the regulator/charger drivers separately if
required.
+
+config PMIC_PALMAS
+ bool "Enable driver for Texas Instruments PALMAS PMIC"
+ depends on DM_PMIC
+ ---help---
+ The PALMAS is a PMIC containing several LDOs, SMPS.
+ This driver binds the pmic children.
+
+config PMIC_LP873X
+ bool "Enable driver for Texas Instruments LP873X PMIC"
+ depends on DM_PMIC
+ ---help---
+ The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
+ This driver binds the pmic children.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 52b4f71..b4ac7d2 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -7,14 +7,18 @@
obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
+obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
obj-$(CONFIG_PMIC_PM8916) += pm8916.o
obj-$(CONFIG_PMIC_RK808) += rk808.o
+obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
+obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
+obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
diff --git a/drivers/power/pmic/lp873x.c b/drivers/power/pmic/lp873x.c
new file mode 100644
index 0000000..307f96b
--- /dev/null
+++ b/drivers/power/pmic/lp873x.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp873x.h>
+#include <dm/device.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo", .driver = LP873X_LDO_DRIVER },
+ { .prefix = "buck", .driver = LP873X_BUCK_DRIVER },
+ { },
+};
+
+static int lp873x_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ if (dm_i2c_write(dev, reg, buff, len)) {
+ error("write error to device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int lp873x_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ if (dm_i2c_read(dev, reg, buff, len)) {
+ error("read error from device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int lp873x_bind(struct udevice *dev)
+{
+ int regulators_node;
+ const void *blob = gd->fdt_blob;
+ int children;
+ int node = dev->of_offset;
+
+ regulators_node = fdt_subnode_offset(blob, node, "regulators");
+
+ if (regulators_node <= 0) {
+ printf("%s: %s reg subnode not found!", __func__, dev->name);
+ return -ENXIO;
+ }
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ printf("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops lp873x_ops = {
+ .read = lp873x_read,
+ .write = lp873x_write,
+};
+
+static const struct udevice_id lp873x_ids[] = {
+ { .compatible = "ti,lp8732", .data = LP8732 },
+ { .compatible = "ti,lp8733" , .data = LP8733 },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_lp873x) = {
+ .name = "lp873x_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = lp873x_ids,
+ .bind = lp873x_bind,
+ .ops = &lp873x_ops,
+};
diff --git a/drivers/power/pmic/max8998.c b/drivers/power/pmic/max8998.c
new file mode 100644
index 0000000..3baa8da
--- /dev/null
+++ b/drivers/power/pmic/max8998.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/max8998_pmic.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int max8998_reg_count(struct udevice *dev)
+{
+ return PMIC_NUM_OF_REGS;
+}
+
+static int max8998_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret)
+ error("write error to device: %p register: %#x!", dev, reg);
+
+ return ret;
+}
+
+static int max8998_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret)
+ error("read error from device: %p register: %#x!", dev, reg);
+
+ return ret;
+}
+
+static struct dm_pmic_ops max8998_ops = {
+ .reg_count = max8998_reg_count,
+ .read = max8998_read,
+ .write = max8998_write,
+};
+
+static const struct udevice_id max8998_ids[] = {
+ { .compatible = "maxim,max8998" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_max8998) = {
+ .name = "max8998_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = max8998_ids,
+ .ops = &max8998_ops,
+};
diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c
new file mode 100644
index 0000000..0ab425e
--- /dev/null
+++ b/drivers/power/pmic/palmas.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/palmas.h>
+#include <dm/device.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo", .driver = PALMAS_LDO_DRIVER },
+ { .prefix = "smps", .driver = PALMAS_SMPS_DRIVER },
+ { },
+};
+
+static int palmas_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ if (dm_i2c_write(dev, reg, buff, len)) {
+ error("write error to device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int palmas_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ if (dm_i2c_read(dev, reg, buff, len)) {
+ error("read error from device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int palmas_bind(struct udevice *dev)
+{
+ int pmic_node = -1, regulators_node;
+ const void *blob = gd->fdt_blob;
+ int children;
+ int node = dev->of_offset;
+ int subnode, len;
+
+ fdt_for_each_subnode(subnode, blob, node) {
+ const char *name;
+ char *temp;
+
+ name = fdt_get_name(blob, subnode, &len);
+ temp = strstr(name, "pmic");
+ if (temp) {
+ pmic_node = subnode;
+ break;
+ }
+ }
+
+ if (pmic_node <= 0) {
+ debug("%s: %s pmic subnode not found!", __func__, dev->name);
+ return -ENXIO;
+ }
+
+ regulators_node = fdt_subnode_offset(blob, pmic_node, "regulators");
+
+ if (regulators_node <= 0) {
+ debug("%s: %s reg subnode not found!", __func__, dev->name);
+ return -ENXIO;
+ }
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops palmas_ops = {
+ .read = palmas_read,
+ .write = palmas_write,
+};
+
+static const struct udevice_id palmas_ids[] = {
+ { .compatible = "ti,tps659038", .data = TPS659038 },
+ { .compatible = "ti,tps65917" , .data = TPS65917 },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_palmas) = {
+ .name = "palmas_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = palmas_ids,
+ .bind = palmas_bind,
+ .ops = &palmas_ops,
+};
diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c
index 2123685..23f9a9c 100644
--- a/drivers/power/pmic/pmic_tps62362.c
+++ b/drivers/power/pmic/pmic_tps62362.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <power/pmic.h>
#include <power/tps62362.h>
diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c
index 0fd0ad4..f32fa40 100644
--- a/drivers/power/pmic/pmic_tps65218.c
+++ b/drivers/power/pmic/pmic_tps65218.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <power/pmic.h>
#include <power/tps65218.h>
diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c
new file mode 100644
index 0000000..001e695
--- /dev/null
+++ b/drivers/power/pmic/rn5t567.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 Toradex AG
+ * Stefan Agner <stefan.agner@toradex.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <power/rn5t567_pmic.h>
+#include <power/pmic.h>
+
+static int rn5t567_reg_count(struct udevice *dev)
+{
+ return RN5T567_NUM_OF_REGS;
+}
+
+static int rn5t567_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret) {
+ debug("write error to device: %p register: %#x!", dev, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rn5t567_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret) {
+ debug("read error from device: %p register: %#x!", dev, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct dm_pmic_ops rn5t567_ops = {
+ .reg_count = rn5t567_reg_count,
+ .read = rn5t567_read,
+ .write = rn5t567_write,
+};
+
+static const struct udevice_id rn5t567_ids[] = {
+ { .compatible = "ricoh,rn5t567" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_rn5t567) = {
+ .name = "rn5t567 pmic",
+ .id = UCLASS_PMIC,
+ .of_match = rn5t567_ids,
+ .ops = &rn5t567_ops,
+};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 17f22dd..f870e8b 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -42,6 +42,16 @@
features for REGULATOR PFUZE100. The driver implements get/set api for:
value, enable and mode.
+config REGULATOR_PWM
+ bool "Enable driver for PWM regulators"
+ depends on DM_REGULATOR
+ ---help---
+ Enable support for the PWM regulator functions which voltage are
+ controlled by PWM duty ratio. Some of Rockchip board using this kind
+ of regulator. The driver implements get/set api for the various BUCKS.
+ This driver is controlled by a device tree node
+ which includes voltage limits.
+
config DM_REGULATOR_MAX77686
bool "Enable Driver Model for REGULATOR MAX77686"
depends on DM_REGULATOR && DM_PMIC_MAX77686
@@ -58,6 +68,14 @@
features for fixed value regulators. The driver implements get/set api
for enable and get only for voltage value.
+config DM_REGULATOR_GPIO
+ bool "Enable Driver Model for GPIO REGULATOR"
+ depends on DM_REGULATOR
+ ---help---
+ This config enables implementation of driver-model regulator uclass
+ features for gpio regulators. The driver implements get/set for
+ voltage value.
+
config REGULATOR_RK808
bool "Enable driver for RK808 regulators"
depends on DM_REGULATOR && PMIC_RK808
@@ -115,3 +133,19 @@
regulators, one for each FET. The standard regulator interface is
supported, but it is only possible to turn the regulators on or off.
There is no voltage/current control.
+
+config DM_REGULATOR_PALMAS
+ bool "Enable driver for PALMAS PMIC regulators"
+ depends on PMIC_PALMAS
+ ---help---
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR PALMAS and the family of PALMAS PMICs.
+ The driver implements get/set api for: value and enable.
+
+config DM_REGULATOR_LP873X
+ bool "Enable driver for LP873X PMIC regulators"
+ depends on PMIC_LP873X
+ ---help---
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR LP873X and the family of LP873X PMICs.
+ The driver implements get/set api for: value and enable.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 1590d85..6002c88 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -9,8 +9,12 @@
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
+obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_RK808) += rk808.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c
index 37b8400..3d2d908 100644
--- a/drivers/power/regulator/fixed.c
+++ b/drivers/power/regulator/fixed.c
@@ -27,6 +27,8 @@
struct dm_regulator_uclass_platdata *uc_pdata;
struct fixed_regulator_platdata *dev_pdata;
struct gpio_desc *gpio;
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset, flags = GPIOD_IS_OUT;
int ret;
dev_pdata = dev_get_platdata(dev);
@@ -37,11 +39,18 @@
/* Set type to fixed */
uc_pdata->type = REGULATOR_TYPE_FIXED;
- /* Get fixed regulator gpio desc */
+ if (fdtdec_get_bool(blob, node, "enable-active-high"))
+ flags |= GPIOD_IS_OUT_ACTIVE;
+
+ /* Get fixed regulator optional enable GPIO desc */
gpio = &dev_pdata->gpio;
- ret = gpio_request_by_name(dev, "gpio", 0, gpio, GPIOD_IS_OUT);
- if (ret)
- debug("Fixed regulator gpio - not found! Error: %d", ret);
+ ret = gpio_request_by_name(dev, "gpio", 0, gpio, flags);
+ if (ret) {
+ debug("Fixed regulator optional enable GPIO - not found! Error: %d\n",
+ ret);
+ if (ret != -ENOENT)
+ return ret;
+ }
/* Get optional ramp up delay */
dev_pdata->startup_delay_us = fdtdec_get_uint(gd->fdt_blob,
@@ -87,8 +96,9 @@
{
struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ /* Enable GPIO is optional */
if (!dev_pdata->gpio.dev)
- return false;
+ return true;
return dm_gpio_get_value(&dev_pdata->gpio);
}
@@ -98,8 +108,12 @@
struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev);
int ret;
- if (!dev_pdata->gpio.dev)
- return -ENOSYS;
+ /* Enable GPIO is optional */
+ if (!dev_pdata->gpio.dev) {
+ if (!enable)
+ return -ENOSYS;
+ return 0;
+ }
ret = dm_gpio_set_value(&dev_pdata->gpio, enable);
if (ret) {
diff --git a/drivers/power/regulator/gpio-regulator.c b/drivers/power/regulator/gpio-regulator.c
new file mode 100644
index 0000000..0a60a9c
--- /dev/null
+++ b/drivers/power/regulator/gpio-regulator.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define GPIO_REGULATOR_MAX_STATES 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct gpio_regulator_platdata {
+ struct gpio_desc gpio; /* GPIO for regulator voltage control */
+ int states[GPIO_REGULATOR_MAX_STATES];
+ int voltages[GPIO_REGULATOR_MAX_STATES];
+};
+
+static int gpio_regulator_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct gpio_regulator_platdata *dev_pdata;
+ struct gpio_desc *gpio;
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ int ret, count, i, j;
+ u32 states_array[8];
+
+ dev_pdata = dev_get_platdata(dev);
+ uc_pdata = dev_get_uclass_platdata(dev);
+ if (!uc_pdata)
+ return -ENXIO;
+
+ /* Set type to gpio */
+ uc_pdata->type = REGULATOR_TYPE_GPIO;
+
+ /*
+ * Get gpio regulator gpio desc
+ * Assuming one GPIO per regulator.
+ * Can be extended later to multiple GPIOs
+ * per gpio-regulator. As of now no instance with multiple
+ * gpios is presnt
+ */
+ gpio = &dev_pdata->gpio;
+ ret = gpio_request_by_name(dev, "gpios", 0, gpio, GPIOD_IS_OUT);
+ if (ret)
+ debug("regulator gpio - not found! Error: %d", ret);
+
+ count = fdtdec_get_int_array_count(blob, node, "states",
+ states_array, 8);
+
+ if (!count)
+ return -EINVAL;
+
+ for (i = 0, j = 0; i < count; i += 2) {
+ dev_pdata->voltages[j] = states_array[i];
+ dev_pdata->states[j] = states_array[i + 1];
+ j++;
+ }
+
+ return 0;
+}
+
+static int gpio_regulator_get_value(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ int enable;
+
+ if (!dev_pdata->gpio.dev)
+ return -ENOSYS;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ if (uc_pdata->min_uV > uc_pdata->max_uV) {
+ debug("Invalid constraints for: %s\n", uc_pdata->name);
+ return -EINVAL;
+ }
+
+ enable = dm_gpio_get_value(&dev_pdata->gpio);
+ if (enable == dev_pdata->states[0])
+ return dev_pdata->voltages[0];
+ else
+ return dev_pdata->voltages[1];
+}
+
+static int gpio_regulator_set_value(struct udevice *dev, int uV)
+{
+ struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ int ret;
+ bool enable;
+
+ if (!dev_pdata->gpio.dev)
+ return -ENOSYS;
+
+ if (uV == dev_pdata->voltages[0])
+ enable = dev_pdata->states[0];
+ else if (uV == dev_pdata->voltages[1])
+ enable = dev_pdata->states[1];
+ else
+ return -EINVAL;
+
+ ret = dm_gpio_set_value(&dev_pdata->gpio, enable);
+ if (ret) {
+ error("Can't set regulator : %s gpio to: %d\n", dev->name,
+ enable);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dm_regulator_ops gpio_regulator_ops = {
+ .get_value = gpio_regulator_get_value,
+ .set_value = gpio_regulator_set_value,
+};
+
+static const struct udevice_id gpio_regulator_ids[] = {
+ { .compatible = "regulator-gpio" },
+ { },
+};
+
+U_BOOT_DRIVER(gpio_regulator) = {
+ .name = "gpio regulator",
+ .id = UCLASS_REGULATOR,
+ .ops = &gpio_regulator_ops,
+ .of_match = gpio_regulator_ids,
+ .ofdata_to_platdata = gpio_regulator_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct gpio_regulator_platdata),
+};
diff --git a/drivers/power/regulator/lp873x_regulator.c b/drivers/power/regulator/lp873x_regulator.c
new file mode 100644
index 0000000..dcb19ff
--- /dev/null
+++ b/drivers/power/regulator/lp873x_regulator.c
@@ -0,0 +1,357 @@
+/*
+ * (C) Copyright 2016
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp873x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char lp873x_buck_ctrl[LP873X_BUCK_NUM] = {0x2, 0x4};
+static const char lp873x_buck_volt[LP873X_BUCK_NUM] = {0x6, 0x7};
+static const char lp873x_ldo_ctrl[LP873X_LDO_NUM] = {0x8, 0x9};
+static const char lp873x_ldo_volt[LP873X_LDO_NUM] = {0xA, 0xB};
+
+static int lp873x_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP873X_BUCK_MODE_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= LP873X_BUCK_MODE_MASK;
+ else
+ ret &= ~(LP873X_BUCK_MODE_MASK);
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lp873x_buck_volt2hex(int uV)
+{
+ if (uV > LP873X_BUCK_VOLT_MAX)
+ return -EINVAL;
+ else if (uV > 1400000)
+ return (uV - 1420000) / 20000 + 0x9E;
+ else if (uV > 730000)
+ return (uV - 735000) / 5000 + 0x18;
+ else if (uV >= 700000)
+ return (uV - 700000) / 10000 + 0x1;
+ else
+ return -EINVAL;
+}
+
+static int lp873x_buck_hex2volt(int hex)
+{
+ if (hex > LP873X_BUCK_VOLT_MAX_HEX)
+ return -EINVAL;
+ else if (hex > 0x9D)
+ return 1400000 + (hex - 0x9D) * 20000;
+ else if (hex > 0x17)
+ return 730000 + (hex - 0x17) * 5000;
+ else if (hex >= 0x14)
+ return 700000 + (hex - 0x14) * 10000;
+ else
+ return -EINVAL;
+}
+
+static int lp873x_buck_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP873X_BUCK_VOLT_MASK;
+ ret = lp873x_buck_hex2volt(ret);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+
+ return 0;
+ }
+
+ hex = lp873x_buck_volt2hex(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= 0x0;
+ ret |= hex;
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+
+ return ret;
+}
+
+static int lp873x_ldo_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP873X_LDO_MODE_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= LP873X_LDO_MODE_MASK;
+ else
+ ret &= ~(LP873X_LDO_MODE_MASK);
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lp873x_ldo_volt2hex(int uV)
+{
+ if (uV > LP873X_LDO_VOLT_MAX)
+ return -EINVAL;
+
+ return (uV - 800000) / 100000;
+}
+
+static int lp873x_ldo_hex2volt(int hex)
+{
+ if (hex > LP873X_LDO_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ if (!hex)
+ return 0;
+
+ return (hex * 100000) + 800000;
+}
+
+static int lp873x_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP873X_LDO_VOLT_MASK;
+ ret = lp873x_ldo_hex2volt(ret);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+ return 0;
+ }
+
+ hex = lp873x_ldo_volt2hex(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= ~LP873X_LDO_VOLT_MASK;
+ ret |= hex;
+ if (*uV > 1650000)
+ ret |= 0x80;
+ ret = pmic_reg_write(dev->parent, adr, ret);
+
+ return ret;
+}
+
+static int lp873x_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+
+ int idx = dev->driver_data;
+ if (idx >= LP873X_LDO_NUM) {
+ printf("Wrong ID for regulator\n");
+ return -1;
+ }
+
+ uc_pdata->ctrl_reg = lp873x_ldo_ctrl[idx];
+ uc_pdata->volt_reg = lp873x_ldo_volt[idx];
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = lp873x_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return lp873x_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool ldo_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = lp873x_ldo_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ return lp873x_ldo_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int lp873x_buck_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ int idx;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ idx = dev->driver_data;
+ if (idx >= LP873X_BUCK_NUM) {
+ printf("Wrong ID for regulator\n");
+ return -1;
+ }
+
+ uc_pdata->ctrl_reg = lp873x_buck_ctrl[idx];
+ uc_pdata->volt_reg = lp873x_buck_volt[idx];
+
+ return 0;
+}
+
+static int buck_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = lp873x_buck_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int buck_set_value(struct udevice *dev, int uV)
+{
+ return lp873x_buck_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool buck_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+
+ ret = lp873x_buck_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int buck_set_enable(struct udevice *dev, bool enable)
+{
+ return lp873x_buck_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops lp873x_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+};
+
+U_BOOT_DRIVER(lp873x_ldo) = {
+ .name = LP873X_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &lp873x_ldo_ops,
+ .probe = lp873x_ldo_probe,
+};
+
+static const struct dm_regulator_ops lp873x_buck_ops = {
+ .get_value = buck_get_value,
+ .set_value = buck_set_value,
+ .get_enable = buck_get_enable,
+ .set_enable = buck_set_enable,
+};
+
+U_BOOT_DRIVER(lp873x_buck) = {
+ .name = LP873X_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &lp873x_buck_ops,
+ .probe = lp873x_buck_probe,
+};
diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c
new file mode 100644
index 0000000..cce7cd2
--- /dev/null
+++ b/drivers/power/regulator/palmas_regulator.c
@@ -0,0 +1,453 @@
+/*
+ * (C) Copyright 2016
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/palmas.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REGULATOR_ON 0x1
+#define REGULATOR_OFF 0x0
+
+#define SMPS_MODE_MASK 0x3
+#define SMPS_MODE_SHIFT 0x0
+#define LDO_MODE_MASK 0x1
+#define LDO_MODE_SHIFT 0x0
+
+static const char palmas_smps_ctrl[][PALMAS_SMPS_NUM] = {
+ {0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 0x3c},
+ {0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38},
+ {0x20, 0x24, 0x2c, 0x30, 0x38},
+};
+
+static const char palmas_smps_volt[][PALMAS_SMPS_NUM] = {
+ {0x23, 0x27, 0x2b, 0x2f, 0x33, 0x37, 0x3b, 0x3c},
+ {0x23, 0x27, 0x2b, 0x2f, 0x33, 0x37, 0x3b},
+ {0x23, 0x27, 0x2f, 0x33, 0x3B}
+};
+
+static const char palmas_ldo_ctrl[][PALMAS_LDO_NUM] = {
+ {0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e, 0x60, 0x62, 0x64},
+ {0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e, 0x60, 0x62, 0x64},
+ {0x50, 0x52, 0x54, 0x5e, 0x62}
+};
+
+static const char palmas_ldo_volt[][PALMAS_LDO_NUM] = {
+ {0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d, 0x5f, 0x61, 0x63, 0x65},
+ {0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d, 0x5f, 0x61, 0x63, 0x65},
+ {0x51, 0x53, 0x55, 0x5f, 0x63}
+};
+
+static int palmas_smps_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= PALMAS_SMPS_STATUS_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= PALMAS_SMPS_MODE_MASK;
+ else
+ ret &= ~(PALMAS_SMPS_MODE_MASK);
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int palmas_smps_volt2hex(int uV)
+{
+ if (uV > PALMAS_LDO_VOLT_MAX)
+ return -EINVAL;
+
+ if (uV > 1650000)
+ return (uV - 1000000) / 20000 + 0x6;
+
+ if (uV == 500000)
+ return 0x6;
+ else
+ return 0x6 + ((uV - 500000) / 10000);
+}
+
+static int palmas_smps_hex2volt(int hex, bool range)
+{
+ unsigned int uV = 0;
+
+ if (hex > PALMAS_SMPS_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ if (hex < 0x7)
+ uV = 500000;
+ else
+ uV = 500000 + (hex - 0x6) * 10000;
+
+ if (range)
+ uV *= 2;
+
+ return uV;
+}
+
+static int palmas_smps_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+ bool range;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ if (ret & PALMAS_SMPS_RANGE_MASK)
+ range = true;
+ else
+ range = false;
+
+ ret &= PALMAS_SMPS_VOLT_MASK;
+ ret = palmas_smps_hex2volt(ret, range);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+
+ return 0;
+ }
+
+ hex = palmas_smps_volt2hex(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= ~PALMAS_SMPS_VOLT_MASK;
+ ret |= hex;
+ if (*uV > 1650000)
+ ret |= PALMAS_SMPS_RANGE_MASK;
+
+ return pmic_reg_write(dev->parent, adr, ret);
+}
+
+static int palmas_ldo_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= PALMAS_LDO_STATUS_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= PALMAS_LDO_MODE_MASK;
+ else
+ ret &= ~(PALMAS_LDO_MODE_MASK);
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int palmas_ldo_volt2hex(int uV)
+{
+ if (uV > PALMAS_LDO_VOLT_MAX)
+ return -EINVAL;
+
+ return (uV - 850000) / 50000;
+}
+
+static int palmas_ldo_hex2volt(int hex)
+{
+ if (hex > PALMAS_LDO_VOLT_MAX_HEX)
+ return -EINVAL;
+
+ if (!hex)
+ return 0;
+
+ return (hex * 50000) + 850000;
+}
+
+static int palmas_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= PALMAS_LDO_VOLT_MASK;
+ ret = palmas_ldo_hex2volt(ret);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+ return 0;
+ }
+
+ hex = palmas_ldo_volt2hex(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= ~PALMAS_LDO_VOLT_MASK;
+ ret |= hex;
+ if (*uV > 1650000)
+ ret |= 0x80;
+
+ return pmic_reg_write(dev->parent, adr, ret);
+}
+
+static int palmas_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct udevice *parent;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ parent = dev_get_parent(dev);
+ int type = dev_get_driver_data(parent);
+
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+
+ if (dev->driver_data) {
+ u8 idx = dev->driver_data - 1;
+ uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][idx];
+ uc_pdata->volt_reg = palmas_ldo_volt[type][idx];
+ } else {
+ /* check for ldoln and ldousb cases */
+ if (!strcmp("ldoln", dev->name)) {
+ uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9];
+ uc_pdata->volt_reg = palmas_ldo_volt[type][9];
+ } else if (!strcmp("ldousb", dev->name)) {
+ uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10];
+ uc_pdata->volt_reg = palmas_ldo_volt[type][10];
+ }
+ }
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = palmas_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return palmas_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool ldo_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = palmas_ldo_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ return palmas_ldo_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int palmas_smps_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct udevice *parent;
+ int idx;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ parent = dev_get_parent(dev);
+ int type = dev_get_driver_data(parent);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ switch (type) {
+ case PALMAS:
+ case TPS659038:
+ switch (dev->driver_data) {
+ case 123:
+ case 12:
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][0];
+ uc_pdata->volt_reg = palmas_smps_volt[type][0];
+ break;
+ case 3:
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][1];
+ uc_pdata->volt_reg = palmas_smps_volt[type][1];
+ break;
+ case 45:
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][2];
+ uc_pdata->volt_reg = palmas_smps_volt[type][2];
+ break;
+ case 6:
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ idx = dev->driver_data - 4;
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
+ uc_pdata->volt_reg = palmas_smps_volt[type][idx];
+ break;
+
+ default:
+ printf("Wrong ID for regulator\n");
+ }
+ break;
+
+ case TPS65917:
+ switch (dev->driver_data) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ idx = dev->driver_data - 1;
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
+ uc_pdata->volt_reg = palmas_smps_volt[type][idx];
+ break;
+
+ default:
+ printf("Wrong ID for regulator\n");
+ }
+ break;
+
+ default:
+ printf("Invalid PMIC ID\n");
+ }
+
+ return 0;
+}
+
+static int smps_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = palmas_smps_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int smps_set_value(struct udevice *dev, int uV)
+{
+ return palmas_smps_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool smps_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = palmas_smps_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int smps_set_enable(struct udevice *dev, bool enable)
+{
+ return palmas_smps_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops palmas_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+};
+
+U_BOOT_DRIVER(palmas_ldo) = {
+ .name = PALMAS_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &palmas_ldo_ops,
+ .probe = palmas_ldo_probe,
+};
+
+static const struct dm_regulator_ops palmas_smps_ops = {
+ .get_value = smps_get_value,
+ .set_value = smps_set_value,
+ .get_enable = smps_get_enable,
+ .set_enable = smps_set_enable,
+};
+
+U_BOOT_DRIVER(palmas_smps) = {
+ .name = PALMAS_SMPS_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &palmas_smps_ops,
+ .probe = palmas_smps_probe,
+};
diff --git a/drivers/power/regulator/pwm_regulator.c b/drivers/power/regulator/pwm_regulator.c
new file mode 100644
index 0000000..b0a4c5d
--- /dev/null
+++ b/drivers/power/regulator/pwm_regulator.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd
+ *
+ * Based on kernel drivers/regulator/pwm-regulator.c
+ * Copyright (C) 2014 - STMicroelectronics Inc.
+ * Author: Lee Jones <lee.jones@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <pwm.h>
+#include <power/regulator.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pwm_regulator_info {
+ /* pwm id corresponding to the PWM driver */
+ int pwm_id;
+ /* the period of one PWM cycle */
+ int period_ns;
+ struct udevice *pwm;
+ /* initialize voltage of regulator */
+ unsigned int init_voltage;
+ /* the maximum voltage of regulator */
+ unsigned int max_voltage;
+ /* the minimum voltage of regulator */
+ unsigned int min_voltage;
+ /* the current voltage of regulator */
+ unsigned int volt_uV;
+};
+
+static int pwm_regulator_enable(struct udevice *dev, bool enable)
+{
+ struct pwm_regulator_info *priv = dev_get_priv(dev);
+
+ return pwm_set_enable(priv->pwm, priv->pwm_id, enable);
+}
+
+static int pwm_voltage_to_duty_cycle_percentage(struct udevice *dev, int req_uV)
+{
+ struct pwm_regulator_info *priv = dev_get_priv(dev);
+ int min_uV = priv->min_voltage;
+ int max_uV = priv->max_voltage;
+ int diff = max_uV - min_uV;
+
+ return 100 - (((req_uV * 100) - (min_uV * 100)) / diff);
+}
+
+static int pwm_regulator_get_voltage(struct udevice *dev)
+{
+ struct pwm_regulator_info *priv = dev_get_priv(dev);
+
+ return priv->volt_uV;
+}
+
+static int pwm_regulator_set_voltage(struct udevice *dev, int uvolt)
+{
+ struct pwm_regulator_info *priv = dev_get_priv(dev);
+ int duty_cycle;
+ int ret = 0;
+
+ duty_cycle = pwm_voltage_to_duty_cycle_percentage(dev, uvolt);
+
+ ret = pwm_set_config(priv->pwm, priv->pwm_id,
+ (priv->period_ns / 100) * duty_cycle, priv->period_ns);
+ if (ret) {
+ dev_err(dev, "Failed to configure PWM\n");
+ return ret;
+ }
+
+ ret = pwm_set_enable(priv->pwm, priv->pwm_id, true);
+ if (ret) {
+ dev_err(dev, "Failed to enable PWM\n");
+ return ret;
+ }
+ priv->volt_uV = uvolt;
+ return ret;
+}
+
+static int pwm_regulator_ofdata_to_platdata(struct udevice *dev)
+{
+ struct pwm_regulator_info *priv = dev_get_priv(dev);
+ struct fdtdec_phandle_args args;
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ int ret;
+
+ ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
+ 0, 0, &args);
+ if (ret) {
+ debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
+ return ret;
+ }
+ /* TODO: pwm_id here from device tree if needed */
+
+ priv->period_ns = args.args[1];
+
+ priv->init_voltage = fdtdec_get_int(blob, node,
+ "regulator-init-microvolt", -1);
+ if (priv->init_voltage < 0) {
+ printf("Cannot find regulator pwm init_voltage\n");
+ return -EINVAL;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
+ if (ret) {
+ debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int pwm_regulator_probe(struct udevice *dev)
+{
+ struct pwm_regulator_info *priv = dev_get_priv(dev);
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+ uc_pdata->mode_count = 0;
+ priv->max_voltage = uc_pdata->max_uV;
+ priv->min_voltage = uc_pdata->min_uV;
+
+ if (priv->init_voltage)
+ pwm_regulator_set_voltage(dev, priv->init_voltage);
+
+ pwm_regulator_enable(dev, 1);
+
+ return 0;
+}
+
+static const struct dm_regulator_ops pwm_regulator_ops = {
+ .get_value = pwm_regulator_get_voltage,
+ .set_value = pwm_regulator_set_voltage,
+ .set_enable = pwm_regulator_enable,
+};
+
+static const struct udevice_id pwm_regulator_ids[] = {
+ { .compatible = "pwm-regulator" },
+ { }
+};
+
+U_BOOT_DRIVER(pwm_regulator) = {
+ .name = "pwm_regulator",
+ .id = UCLASS_REGULATOR,
+ .ops = &pwm_regulator_ops,
+ .probe = pwm_regulator_probe,
+ .of_match = pwm_regulator_ids,
+ .ofdata_to_platdata = pwm_regulator_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct pwm_regulator_info),
+};
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 4434e36..52a1070 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -41,6 +41,27 @@
int regulator_set_value(struct udevice *dev, int uV)
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV)
+ return -EINVAL;
+ if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV)
+ return -EINVAL;
+
+ if (!ops || !ops->set_value)
+ return -ENOSYS;
+
+ return ops->set_value(dev, uV);
+}
+
+/*
+ * To be called with at most caution as there is no check
+ * before setting the actual voltage value.
+ */
+int regulator_set_value_force(struct udevice *dev, int uV)
+{
+ const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_value)
return -ENOSYS;
@@ -61,6 +82,13 @@
int regulator_set_current(struct udevice *dev, int uA)
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ if (uc_pdata->min_uA != -ENODATA && uA < uc_pdata->min_uA)
+ return -EINVAL;
+ if (uc_pdata->max_uA != -ENODATA && uA > uc_pdata->max_uA)
+ return -EINVAL;
if (!ops || !ops->set_current)
return -ENOSYS;
diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c
index 05c79be..cd53200 100644
--- a/drivers/power/twl6030.c
+++ b/drivers/power/twl6030.c
@@ -231,9 +231,9 @@
/* Enable P1 output for VMMC */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VMMC_CFG_STATE,
TWL6030_CFG_STATE_P1 | TWL6030_CFG_STATE_ON);
-
- twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_PH_STS_BOOT, &value);
} else if (dev_index == 1) {
+ twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_PH_STS_BOOT,
+ &value);
/* BOOT2 indicates 1.8V/2.8V VAUX1 for eMMC */
if (value & TWL6030_PH_STS_BOOT2) {
/* 1.8V voltage output for VAUX1 */
diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c
index f92c370..534dd8e 100644
--- a/drivers/pwm/pwm-imx-util.c
+++ b/drivers/pwm/pwm-imx-util.c
@@ -2,7 +2,7 @@
* (C) Copyright 2014
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
- * Basic support for the pwm modul on imx6.
+ * Basic support for the pwm module on imx6.
*
* Based on linux:drivers/pwm/pwm-imx.c
* from
@@ -15,7 +15,7 @@
#include <div64.h>
#include <asm/arch/imx-regs.h>
-/* pwm_id from 0..3 */
+/* pwm_id from 0..7 */
struct pwm_regs *pwm_id_to_reg(int pwm_id)
{
switch (pwm_id) {
@@ -27,6 +27,16 @@
return (struct pwm_regs *)PWM3_BASE_ADDR;
case 3:
return (struct pwm_regs *)PWM4_BASE_ADDR;
+#ifdef CONFIG_MX6SX
+ case 4:
+ return (struct pwm_regs *)PWM5_BASE_ADDR;
+ case 5:
+ return (struct pwm_regs *)PWM6_BASE_ADDR;
+ case 6:
+ return (struct pwm_regs *)PWM7_BASE_ADDR;
+ case 7:
+ return (struct pwm_regs *)PWM8_BASE_ADDR;
+#endif
default:
printf("unknown pwm_id: %d\n", pwm_id);
break;
diff --git a/drivers/pwm/pwm-imx-util.h b/drivers/pwm/pwm-imx-util.h
index 45465c4..5c18651 100644
--- a/drivers/pwm/pwm-imx-util.h
+++ b/drivers/pwm/pwm-imx-util.h
@@ -2,7 +2,7 @@
* (C) Copyright 2014
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
- * Basic support for the pwm modul on imx6.
+ * Basic support for the pwm module on imx6.
*
* SPDX-License-Identifier: GPL-2.0
*/
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 47799fc..3f808f9 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -2,7 +2,7 @@
* (C) Copyright 2014
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
- * Basic support for the pwm modul on imx6.
+ * Basic support for the pwm module on imx6.
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
index 2d289a4..9254f5b 100644
--- a/drivers/pwm/rk_pwm.c
+++ b/drivers/pwm/rk_pwm.c
@@ -6,15 +6,13 @@
*/
#include <common.h>
+#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <pwm.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
#include <asm/arch/pwm.h>
#include <power/regulator.h>
@@ -22,7 +20,7 @@
struct rk_pwm_priv {
struct rk3288_pwm *regs;
- struct rk3288_grf *grf;
+ ulong freq;
};
static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
@@ -38,8 +36,8 @@
RK_PWM_DISABLE,
®s->ctrl);
- period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
- duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
+ period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
+ duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
writel(period, ®s->period_hpr);
writel(duty, ®s->duty_lpr);
@@ -62,13 +60,8 @@
static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
- struct regmap *map;
priv->regs = (struct rk3288_pwm *)dev_get_addr(dev);
- map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
- if (IS_ERR(map))
- return PTR_ERR(map);
- priv->grf = regmap_get_range(map, 0);
return 0;
}
@@ -76,8 +69,15 @@
static int rk_pwm_probe(struct udevice *dev)
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret = 0;
- rk_setreg(&priv->grf->soc_con2, 1 << 0);
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ debug("%s get clock fail!\n", __func__);
+ return -EINVAL;
+ }
+ priv->freq = clk_get_rate(&clk);
return 0;
}
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 2b98984..4231594 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -7,11 +7,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "common.h"
+#include <common.h>
#include <command.h>
-#include "asm/errno.h"
-#include "asm/io.h"
-#include "linux/immap_qe.h"
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <linux/immap_qe.h>
#include <fsl_qe.h>
#ifdef CONFIG_LS102XA
#include <asm/arch/immap_ls102xa.h>
diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c
index e011886..bab5453 100644
--- a/drivers/qe/uccf.c
+++ b/drivers/qe/uccf.c
@@ -7,11 +7,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "common.h"
-#include "malloc.h"
-#include "asm/errno.h"
-#include "asm/io.h"
-#include "linux/immap_qe.h"
+#include <common.h>
+#include <malloc.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <linux/immap_qe.h>
#include "uccf.h"
#include <fsl_qe.h>
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 468c92e..b3af707 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -6,12 +6,12 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "common.h"
-#include "net.h"
-#include "malloc.h"
-#include "asm/errno.h"
-#include "asm/io.h"
-#include "linux/immap_qe.h"
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <linux/immap_qe.h>
#include "uccf.h"
#include "uec.h"
#include "uec_phy.h"
@@ -567,7 +567,7 @@
{
uec_private_t *uec = (uec_private_t *)dev->priv;
-#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
@@ -578,7 +578,7 @@
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
-#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
/*
* QE12 is muxed with LBCTL, it needs to be released for enabling
* LBCTL signal for LBC usage.
@@ -1193,14 +1193,14 @@
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
-#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
-#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
@@ -1232,7 +1232,7 @@
udelay(100000);
} while (1);
-#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
/* QE12 needs to be released for enabling LBCTL signal*/
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 272874d..9604270 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -10,12 +10,12 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "common.h"
-#include "net.h"
-#include "malloc.h"
-#include "asm/errno.h"
-#include "linux/immap_qe.h"
-#include "asm/io.h"
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <linux/errno.h>
+#include <linux/immap_qe.h>
+#include <asm/io.h>
#include "uccf.h"
#include "uec.h"
#include "uec_phy.h"
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 5b84f21..c42b0bc 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -20,6 +20,13 @@
simply accepts requests to reset various HW modules without actually
doing anything beyond a little error checking.
+config TEGRA_CAR_RESET
+ bool "Enable Tegra CAR-based reset driver"
+ depends on TEGRA_CAR
+ help
+ Enable support for manipulating Tegra's on-SoC reset signals via
+ direct register access to the Tegra CAR (Clock And Reset controller).
+
config TEGRA186_RESET
bool "Enable Tegra186 BPMP-based reset driver"
depends on TEGRA186_BPMP
@@ -27,4 +34,13 @@
Enable support for manipulating Tegra's on-SoC reset signals via IPC
requests to the BPMP (Boot and Power Management Processor).
+config RESET_UNIPHIER
+ bool "Reset controller driver for UniPhier SoCs"
+ depends on ARCH_UNIPHIER
+ default y
+ help
+ Support for reset controllers on UniPhier SoCs.
+ Say Y if you want to control reset signals provided by System Control
+ block, Media I/O block, Peripheral Block.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index ff0e090..5c4305c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -5,4 +5,6 @@
obj-$(CONFIG_DM_RESET) += reset-uclass.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
+obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
+obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index edaecfb..d3744ef 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -88,10 +88,10 @@
debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name,
reset_ctl);
- index = fdt_find_string(gd->fdt_blob, dev->of_offset, "reset-names",
- name);
+ index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ "reset-names", name);
if (index < 0) {
- debug("fdt_find_string() failed: %d\n", index);
+ debug("fdt_stringlist_search() failed: %d\n", index);
return index;
}
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
new file mode 100644
index 0000000..29c4d4d
--- /dev/null
+++ b/drivers/reset/reset-uniphier.c
@@ -0,0 +1,376 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <reset-uclass.h>
+#include <dm/device.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+struct uniphier_reset_data {
+ unsigned int id;
+ unsigned int reg;
+ unsigned int bit;
+ unsigned int flags;
+#define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
+};
+
+#define UNIPHIER_RESET_ID_END (unsigned int)(-1)
+
+#define UNIPHIER_RESET_END \
+ { .id = UNIPHIER_RESET_ID_END }
+
+#define UNIPHIER_RESET(_id, _reg, _bit) \
+ { \
+ .id = (_id), \
+ .reg = (_reg), \
+ .bit = (_bit), \
+ }
+
+#define UNIPHIER_RESETX(_id, _reg, _bit) \
+ { \
+ .id = (_id), \
+ .reg = (_reg), \
+ .bit = (_bit), \
+ .flags = UNIPHIER_RESET_ACTIVE_LOW, \
+ }
+
+/* System reset data */
+#define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \
+ UNIPHIER_RESETX((id), 0x2000, 10)
+
+#define UNIPHIER_LD11_SYS_RESET_STDMAC(id) \
+ UNIPHIER_RESETX((id), 0x200c, 8)
+
+#define UNIPHIER_PRO4_SYS_RESET_GIO(id) \
+ UNIPHIER_RESETX((id), 0x2000, 6)
+
+#define UNIPHIER_LD20_SYS_RESET_GIO(id) \
+ UNIPHIER_RESETX((id), 0x200c, 5)
+
+#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
+ UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
+
+const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
+ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
+ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */
+ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */
+ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
+ UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
+ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */
+ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */
+ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
+ UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
+ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */
+ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
+ UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+ UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
+ UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
+ UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
+ UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
+ UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
+ UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
+ UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
+ UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
+ UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */
+ UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */
+ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
+ UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
+ UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
+ UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
+ UNIPHIER_RESET_END,
+};
+
+/* Media I/O reset data */
+#define UNIPHIER_MIO_RESET_SD(id, ch) \
+ UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
+
+#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \
+ UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
+
+#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \
+ UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
+
+#define UNIPHIER_MIO_RESET_USB2(id, ch) \
+ UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
+
+#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \
+ UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
+
+#define UNIPHIER_MIO_RESET_DMAC(id) \
+ UNIPHIER_RESETX((id), 0x110, 17)
+
+const struct uniphier_reset_data uniphier_mio_reset_data[] = {
+ UNIPHIER_MIO_RESET_SD(0, 0),
+ UNIPHIER_MIO_RESET_SD(1, 1),
+ UNIPHIER_MIO_RESET_SD(2, 2),
+ UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
+ UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
+ UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
+ UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
+ UNIPHIER_MIO_RESET_DMAC(7),
+ UNIPHIER_MIO_RESET_USB2(8, 0),
+ UNIPHIER_MIO_RESET_USB2(9, 1),
+ UNIPHIER_MIO_RESET_USB2(10, 2),
+ UNIPHIER_MIO_RESET_USB2(11, 3),
+ UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
+ UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
+ UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
+ UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3),
+ UNIPHIER_RESET_END,
+};
+
+/* Peripheral reset data */
+#define UNIPHIER_PERI_RESET_UART(id, ch) \
+ UNIPHIER_RESETX((id), 0x114, 19 + (ch))
+
+#define UNIPHIER_PERI_RESET_I2C(id, ch) \
+ UNIPHIER_RESETX((id), 0x114, 5 + (ch))
+
+#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
+ UNIPHIER_RESETX((id), 0x114, 24 + (ch))
+
+const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
+ UNIPHIER_PERI_RESET_UART(0, 0),
+ UNIPHIER_PERI_RESET_UART(1, 1),
+ UNIPHIER_PERI_RESET_UART(2, 2),
+ UNIPHIER_PERI_RESET_UART(3, 3),
+ UNIPHIER_PERI_RESET_I2C(4, 0),
+ UNIPHIER_PERI_RESET_I2C(5, 1),
+ UNIPHIER_PERI_RESET_I2C(6, 2),
+ UNIPHIER_PERI_RESET_I2C(7, 3),
+ UNIPHIER_PERI_RESET_I2C(8, 4),
+ UNIPHIER_RESET_END,
+};
+
+const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
+ UNIPHIER_PERI_RESET_UART(0, 0),
+ UNIPHIER_PERI_RESET_UART(1, 1),
+ UNIPHIER_PERI_RESET_UART(2, 2),
+ UNIPHIER_PERI_RESET_UART(3, 3),
+ UNIPHIER_PERI_RESET_FI2C(4, 0),
+ UNIPHIER_PERI_RESET_FI2C(5, 1),
+ UNIPHIER_PERI_RESET_FI2C(6, 2),
+ UNIPHIER_PERI_RESET_FI2C(7, 3),
+ UNIPHIER_PERI_RESET_FI2C(8, 4),
+ UNIPHIER_PERI_RESET_FI2C(9, 5),
+ UNIPHIER_PERI_RESET_FI2C(10, 6),
+ UNIPHIER_RESET_END,
+};
+
+/* core implementaton */
+struct uniphier_reset_priv {
+ void __iomem *base;
+ const struct uniphier_reset_data *data;
+};
+
+static int uniphier_reset_request(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int uniphier_reset_free(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert)
+{
+ struct uniphier_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ unsigned long id = reset_ctl->id;
+ const struct uniphier_reset_data *p;
+
+ for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
+ u32 mask, val;
+
+ if (p->id != id)
+ continue;
+
+ val = readl(priv->base + p->reg);
+
+ if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
+ assert = !assert;
+
+ mask = BIT(p->bit);
+
+ if (assert)
+ val |= mask;
+ else
+ val &= ~mask;
+
+ writel(val, priv->base + p->reg);
+
+ return 0;
+ }
+
+ dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
+ return -EINVAL;
+}
+
+static int uniphier_reset_assert(struct reset_ctl *reset_ctl)
+{
+ return uniphier_reset_update(reset_ctl, 1);
+}
+
+static int uniphier_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ return uniphier_reset_update(reset_ctl, 0);
+}
+
+static const struct reset_ops uniphier_reset_ops = {
+ .request = uniphier_reset_request,
+ .free = uniphier_reset_free,
+ .rst_assert = uniphier_reset_assert,
+ .rst_deassert = uniphier_reset_deassert,
+};
+
+static int uniphier_reset_probe(struct udevice *dev)
+{
+ struct uniphier_reset_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev->parent);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = devm_ioremap(dev, addr, SZ_4K);
+ if (!priv->base)
+ return -ENOMEM;
+
+ priv->data = (void *)dev_get_driver_data(dev);
+
+ return 0;
+}
+
+static const struct udevice_id uniphier_reset_match[] = {
+ /* System reset */
+ {
+ .compatible = "socionext,uniphier-sld3-reset",
+ .data = (ulong)uniphier_sld3_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld4-reset",
+ .data = (ulong)uniphier_sld3_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-reset",
+ .data = (ulong)uniphier_pro4_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-reset",
+ .data = (ulong)uniphier_sld3_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-reset",
+ .data = (ulong)uniphier_pro5_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-reset",
+ .data = (ulong)uniphier_pxs2_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-reset",
+ .data = (ulong)uniphier_ld11_sys_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-reset",
+ .data = (ulong)uniphier_ld20_sys_reset_data,
+ },
+ /* Media I/O reset */
+ {
+ .compatible = "socionext,uniphier-sld3-mio-clock",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld4-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-mio-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ /* Peripheral reset */
+ {
+ .compatible = "socionext,uniphier-ld4-peri-reset",
+ .data = (ulong)uniphier_ld4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-peri-reset",
+ .data = (ulong)uniphier_ld4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_reset) = {
+ .name = "uniphier-reset",
+ .id = UCLASS_RESET,
+ .of_match = uniphier_reset_match,
+ .probe = uniphier_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct uniphier_reset_priv),
+ .ops = &uniphier_reset_ops,
+};
diff --git a/drivers/reset/tegra-car-reset.c b/drivers/reset/tegra-car-reset.c
new file mode 100644
index 0000000..3147a50
--- /dev/null
+++ b/drivers/reset/tegra-car-reset.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+
+static int tegra_car_reset_request(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ /* PERIPH_ID_COUNT varies per SoC */
+ if (reset_ctl->id >= PERIPH_ID_COUNT)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int tegra_car_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int tegra_car_reset_assert(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ reset_set_enable(reset_ctl->id, 1);
+
+ return 0;
+}
+
+static int tegra_car_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ reset_set_enable(reset_ctl->id, 0);
+
+ return 0;
+}
+
+struct reset_ops tegra_car_reset_ops = {
+ .request = tegra_car_reset_request,
+ .free = tegra_car_reset_free,
+ .rst_assert = tegra_car_reset_assert,
+ .rst_deassert = tegra_car_reset_deassert,
+};
+
+static int tegra_car_reset_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(tegra_car_reset) = {
+ .name = "tegra_car_reset",
+ .id = UCLASS_RESET,
+ .probe = tegra_car_reset_probe,
+ .ops = &tegra_car_reset_ops,
+};
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index b5d9048..57af1b5 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -13,4 +13,10 @@
drivers to perform the actual functions. See rtc.h for a
description of the API.
+config RTC_PCF2127
+ bool "Enable PCF2127 driver"
+ depends on DM_RTC
+ help
+ Enable pcf2127 driver which provides rtc get and set function
+
endmenu
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index fc38a3f..c919427 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -45,6 +45,7 @@
obj-$(CONFIG_RTC_MX27) += mx27rtc.o
obj-$(CONFIG_RTC_MXS) += mxsrtc.o
obj-$(CONFIG_RTC_PCF8563) += pcf8563.o
+obj-$(CONFIG_RTC_PCF2127) += pcf2127.o
obj-$(CONFIG_RTC_PL031) += pl031.o
obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
diff --git a/drivers/rtc/at91sam9_rtt.c b/drivers/rtc/at91sam9_rtt.c
index a684ad6..18fb09d 100644
--- a/drivers/rtc/at91sam9_rtt.c
+++ b/drivers/rtc/at91sam9_rtt.c
@@ -23,7 +23,7 @@
#include <command.h>
#include <rtc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_rtt.h>
#include <asm/arch/at91_gpbr.h>
diff --git a/drivers/rtc/m48t35ax.c b/drivers/rtc/m48t35ax.c
index 021b91f..36011a5 100644
--- a/drivers/rtc/m48t35ax.c
+++ b/drivers/rtc/m48t35ax.c
@@ -127,10 +127,8 @@
static uchar rtc_read (uchar reg)
{
- uchar val;
- val = *(unsigned char *)
+ return *(unsigned char *)
((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg);
- return val;
}
static void rtc_write (uchar reg, uchar val)
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index da804d5..4df9eda 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -14,7 +14,7 @@
#include <dm.h>
#include <rtc.h>
-#if defined(__I386__) || defined(CONFIG_MALTA)
+#if defined(CONFIG_X86) || defined(CONFIG_MALTA)
#include <asm/io.h>
#define in8(p) inb(p)
#define out8(p, v) outb(v, p)
diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c
new file mode 100644
index 0000000..bc59c6c
--- /dev/null
+++ b/drivers/rtc/pcf2127.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2016 by NXP Semiconductors Inc.
+ * Date & Time support for PCF2127 RTC
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <i2c.h>
+#include <rtc.h>
+
+#define PCF2127_REG_CTRL1 (0x00)
+#define PCF2127_REG_CTRL2 (0x01)
+#define PCF2127_REG_CTRL3 (0x02)
+#define PCF2127_REG_SC (0x03) /* datetime */
+#define PCF2127_REG_MN (0x04)
+#define PCF2127_REG_HR (0x05)
+#define PCF2127_REG_DM (0x06)
+#define PCF2127_REG_DW (0x07)
+#define PCF2127_REG_MO (0x08)
+#define PCF2127_REG_YR (0x09)
+
+static int pcf2127_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+ uchar buf[8];
+ int i = 0;
+
+ /* start register address */
+ buf[i++] = PCF2127_REG_SC;
+
+ /* hours, minutes and seconds */
+ buf[i++] = bin2bcd(tm->tm_sec);
+ buf[i++] = bin2bcd(tm->tm_min);
+ buf[i++] = bin2bcd(tm->tm_hour);
+ buf[i++] = bin2bcd(tm->tm_mday);
+ buf[i++] = tm->tm_wday & 0x07;
+
+ /* month, 1 - 12 */
+ buf[i++] = bin2bcd(tm->tm_mon + 1);
+
+ /* year */
+ buf[i++] = bin2bcd(tm->tm_year % 100);
+
+ /* write register's data */
+ if (dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)) < 0)
+ return -1;
+
+ return 0;
+}
+
+static int pcf2127_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+ int rel = 0;
+ uchar buf[10] = { PCF2127_REG_CTRL1 };
+
+ if (dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, 1) < 0)
+ return -1;
+ if (dm_i2c_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)) < 0)
+ return -1;
+
+ if (buf[PCF2127_REG_CTRL3] & 0x04)
+ puts("### Warning: RTC Low Voltage - date/time not reliable\n");
+
+ tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F);
+ tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
+ tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F);
+ tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
+ tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1;
+ tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]) + 1900;
+ if (tm->tm_year < 1970)
+ tm->tm_year += 100; /* assume we are in 1970...2069 */
+ tm->tm_wday = buf[PCF2127_REG_DW] & 0x07;
+ tm->tm_yday = 0;
+ tm->tm_isdst = 0;
+
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ return rel;
+}
+
+static int pcf2127_rtc_reset(struct udevice *dev)
+{
+ /*Doing nothing here*/
+ return 0;
+}
+
+static const struct rtc_ops pcf2127_rtc_ops = {
+ .get = pcf2127_rtc_get,
+ .set = pcf2127_rtc_set,
+ .reset = pcf2127_rtc_reset,
+};
+
+static const struct udevice_id pcf2127_rtc_ids[] = {
+ { .compatible = "pcf2127-rtc" },
+ { }
+};
+
+U_BOOT_DRIVER(rtc_pcf2127) = {
+ .name = "rtc-pcf2127",
+ .id = UCLASS_RTC,
+ .of_match = pcf2127_rtc_ids,
+ .ops = &pcf2127_rtc_ops,
+};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index ab5df70..b26ada3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -98,6 +98,13 @@
driver will be available until the real driver model serial is
running.
+config DEBUG_UART_ATMEL
+ bool "Atmel USART"
+ help
+ Select this to enable a debug UART using the atmel usart driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
config DEBUG_UART_NS16550
bool "ns16550"
help
@@ -147,6 +154,13 @@
This port is available at least on ARMv6, ARMv7, ARMv8 and XScale
architectures.
+config DEBUG_MVEBU_A3700_UART
+ bool "Marvell Armada 3700"
+ help
+ Select this to enable a debug UART using the serial_mvebu driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
config DEBUG_UART_ZYNQ
bool "Xilinx Zynq"
help
@@ -289,12 +303,33 @@
tree binding to operate, please refer to the document at
doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
+config ATMEL_USART
+ bool "Atmel USART support"
+ help
+ Select this to enable USART support for Atmel SoCs. It can be
+ configured in the device tree, and input clock frequency can
+ be got from the clk node.
+
config FSL_LPUART
bool "Freescale LPUART support"
help
Select this to enable a Low Power UART for Freescale VF610 and
QorIQ Layerscape devices.
+config MVEBU_A3700_UART
+ bool "UART support for Armada 3700"
+ default n
+ help
+ Choose this option to add support for UART driver on the Marvell
+ Armada 3700 SoC. The base address is configured via DT.
+
+config MXC_UART
+ bool "IMX serial port support"
+ depends on MX5 || MX6
+ help
+ If you have a machine based on a Motorola IMX CPU you
+ can enable its onboard serial port by enabling this option.
+
config PIC32_SERIAL
bool "Support for Microchip PIC32 on-chip UART"
depends on DM_SERIAL && MACH_PIC32
@@ -371,4 +406,11 @@
It should support all Qualcomm devices with UARTDM version 1.4,
for example APQ8016 and MSM8916.
Single baudrate is supported in current implementation (115200).
+
+config PXA_SERIAL
+ bool "PXA serial port support"
+ help
+ If you have a machine based on a Marvell XScale PXA2xx CPU you
+ can enable its onboard serial ports by enabling this option.
+
endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 6986d65..8430668 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -31,7 +31,6 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
endif
-obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
@@ -46,6 +45,7 @@
obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
+obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index e450135..7674f97 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -11,6 +11,7 @@
#include <errno.h>
#include <watchdog.h>
#include <serial.h>
+#include <debug_uart.h>
#include <linux/compiler.h>
#include <asm/io.h>
@@ -226,3 +227,24 @@
.priv_auto_alloc_size = sizeof(struct atmel_serial_priv),
};
#endif
+
+#ifdef CONFIG_DEBUG_UART_ATMEL
+static inline void _debug_uart_init(void)
+{
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
+
+ atmel_serial_setbrg_internal(usart, 0, CONFIG_BAUDRATE);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
+
+ while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
+ ;
+
+ writel(ch, &usart->thr);
+}
+
+DEBUG_UART_FUNCS
+#endif
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 88fca15..9b423a5 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
@@ -120,6 +121,13 @@
return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
}
+static u32 ns16550_getfcr(NS16550_t port)
+{
+ struct ns16550_platdata *plat = port->plat;
+
+ return plat->fcr;
+}
+
/* We can clean these up once everything is moved to driver model */
#define serial_out(value, addr) \
ns16550_writeb(com_port, \
@@ -127,6 +135,11 @@
#define serial_in(addr) \
ns16550_readb(com_port, \
(unsigned char *)addr - (unsigned char *)com_port)
+#else
+static u32 ns16550_getfcr(NS16550_t port)
+{
+ return UART_FCRVAL;
+}
#endif
int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
@@ -170,7 +183,7 @@
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
serial_out(UART_MCRVAL, &com_port->mcr);
- serial_out(UART_FCRVAL, &com_port->fcr);
+ serial_out(ns16550_getfcr(com_port), &com_port->fcr);
if (baud_divisor != -1)
NS16550_setbrg(com_port, baud_divisor);
#if defined(CONFIG_OMAP) || \
@@ -191,7 +204,7 @@
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
NS16550_setbrg(com_port, 0);
serial_out(UART_MCRVAL, &com_port->mcr);
- serial_out(UART_FCRVAL, &com_port->fcr);
+ serial_out(ns16550_getfcr(com_port), &com_port->fcr);
NS16550_setbrg(com_port, baud_divisor);
}
#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
@@ -347,11 +360,21 @@
return 0;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+enum {
+ PORT_NS16550 = 0,
+ PORT_JZ4780,
+};
+#endif
+
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev->platdata;
+ const u32 port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
+ struct clk clk;
+ int err;
/* try Processor Local Bus device first */
addr = dev_get_addr(dev);
@@ -397,14 +420,30 @@
"reg-offset", 0);
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"reg-shift", 0);
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "clock-frequency",
- CONFIG_SYS_NS16550_CLK);
+
+ err = clk_get_by_index(dev, 0, &clk);
+ if (!err) {
+ err = clk_get_rate(&clk);
+ if (!IS_ERR_VALUE(err))
+ plat->clock = err;
+ } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
+ debug("ns16550 failed to get clock\n");
+ return err;
+ }
+
+ if (!plat->clock)
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency",
+ CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("ns16550 clock not defined\n");
return -EINVAL;
}
+ plat->fcr = UART_FCRVAL;
+ if (port_type == PORT_JZ4780)
+ plat->fcr |= UART_FCR_UME;
+
return 0;
}
#endif
@@ -424,16 +463,17 @@
* compatible string to your dts.
*/
static const struct udevice_id ns16550_serial_ids[] = {
- { .compatible = "ns16550" },
- { .compatible = "ns16550a" },
- { .compatible = "nvidia,tegra20-uart" },
- { .compatible = "snps,dw-apb-uart" },
- { .compatible = "ti,omap2-uart" },
- { .compatible = "ti,omap3-uart" },
- { .compatible = "ti,omap4-uart" },
- { .compatible = "ti,am3352-uart" },
- { .compatible = "ti,am4372-uart" },
- { .compatible = "ti,dra742-uart" },
+ { .compatible = "ns16550", .data = PORT_NS16550 },
+ { .compatible = "ns16550a", .data = PORT_NS16550 },
+ { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
+ { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
+ { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
+ { .compatible = "ti,omap2-uart", .data = PORT_NS16550 },
+ { .compatible = "ti,omap3-uart", .data = PORT_NS16550 },
+ { .compatible = "ti,omap4-uart", .data = PORT_NS16550 },
+ { .compatible = "ti,am3352-uart", .data = PORT_NS16550 },
+ { .compatible = "ti,am4372-uart", .data = PORT_NS16550 },
+ { .compatible = "ti,dra742-uart", .data = PORT_NS16550 },
{}
};
#endif
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 19f38e1..43c028e 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -346,7 +346,7 @@
static int serial_pre_remove(struct udevice *dev)
{
-#ifdef CONFIG_SYS_STDIO_DEREGISTER
+#if CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER)
struct serial_dev_priv *upriv = dev_get_uclass_priv(dev);
if (stdio_deregister_dev(upriv->sdev, 0))
diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c
index f4e062f..3884f74 100644
--- a/drivers/serial/serial_bcm283x_mu.c
+++ b/drivers/serial/serial_bcm283x_mu.c
@@ -25,6 +25,8 @@
#include <linux/compiler.h>
#include <fdtdec.h>
+DECLARE_GLOBAL_DATA_PTR;
+
struct bcm283x_mu_regs {
u32 io;
u32 iir;
@@ -57,7 +59,7 @@
struct bcm283x_mu_regs *regs = priv->regs;
u32 divider;
- if (plat->skip_init)
+ if (plat->disabled || plat->skip_init)
return 0;
divider = plat->clock / (baudrate * 8);
@@ -83,10 +85,14 @@
static int bcm283x_mu_serial_getc(struct udevice *dev)
{
+ struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
struct bcm283x_mu_regs *regs = priv->regs;
u32 data;
+ if (plat->disabled)
+ return -EAGAIN;
+
/* Wait until there is data in the FIFO */
if (!(readl(®s->lsr) & BCM283X_MU_LSR_RX_READY))
return -EAGAIN;
@@ -98,9 +104,13 @@
static int bcm283x_mu_serial_putc(struct udevice *dev, const char data)
{
+ struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
struct bcm283x_mu_regs *regs = priv->regs;
+ if (plat->disabled)
+ return 0;
+
/* Wait until there is space in the FIFO */
if (!(readl(®s->lsr) & BCM283X_MU_LSR_TX_EMPTY))
return -EAGAIN;
@@ -113,9 +123,15 @@
static int bcm283x_mu_serial_pending(struct udevice *dev, bool input)
{
+ struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
struct bcm283x_mu_regs *regs = priv->regs;
- unsigned int lsr = readl(®s->lsr);
+ unsigned int lsr;
+
+ if (plat->disabled)
+ return 0;
+
+ lsr = readl(®s->lsr);
if (input) {
WATCHDOG_RESET();
@@ -132,9 +148,35 @@
.setbrg = bcm283x_mu_serial_setbrg,
};
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id bcm283x_mu_serial_id[] = {
+ {.compatible = "brcm,bcm2835-aux-uart"},
+ {}
+};
+
+static int bcm283x_mu_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->base = addr;
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
+ plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ "skip-init");
+ plat->disabled = false;
+ return 0;
+}
+#endif
+
U_BOOT_DRIVER(serial_bcm283x_mu) = {
.name = "serial_bcm283x_mu",
.id = UCLASS_SERIAL,
+ .of_match = of_match_ptr(bcm283x_mu_serial_id),
+ .ofdata_to_platdata = of_match_ptr(bcm283x_mu_serial_ofdata_to_platdata),
.platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata),
.probe = bcm283x_mu_serial_probe,
.ops = &bcm283x_mu_serial_ops,
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 042e9a2..beb4243 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -170,9 +170,14 @@
}
#else
+u32 __weak get_lpuart_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
{
- u32 clk = CONFIG_SYS_CLK_FREQ;
+ u32 clk = get_lpuart_clk();
u32 sbr;
sbr = (clk / (16 * baudrate));
diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c
new file mode 100644
index 0000000..192e79a
--- /dev/null
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <serial.h>
+#include <asm/io.h>
+
+struct mvebu_platdata {
+ void __iomem *base;
+};
+
+/*
+ * Register offset
+ */
+#define UART_RX_REG 0x00
+#define UART_TX_REG 0x04
+#define UART_CTRL_REG 0x08
+#define UART_STATUS_REG 0x0c
+#define UART_BAUD_REG 0x10
+#define UART_POSSR_REG 0x14
+
+#define UART_STATUS_RX_RDY 0x10
+#define UART_STATUS_TXFIFO_FULL 0x800
+
+#define UART_CTRL_RXFIFO_RESET 0x4000
+#define UART_CTRL_TXFIFO_RESET 0x8000
+
+#define CONFIG_UART_BASE_CLOCK 25804800
+
+static int mvebu_serial_putc(struct udevice *dev, const char ch)
+{
+ struct mvebu_platdata *plat = dev_get_platdata(dev);
+ void __iomem *base = plat->base;
+
+ while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
+ ;
+
+ writel(ch, base + UART_TX_REG);
+
+ return 0;
+}
+
+static int mvebu_serial_getc(struct udevice *dev)
+{
+ struct mvebu_platdata *plat = dev_get_platdata(dev);
+ void __iomem *base = plat->base;
+
+ while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
+ ;
+
+ return readl(base + UART_RX_REG) & 0xff;
+}
+
+static int mvebu_serial_pending(struct udevice *dev, bool input)
+{
+ struct mvebu_platdata *plat = dev_get_platdata(dev);
+ void __iomem *base = plat->base;
+
+ if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
+ return 1;
+
+ return 0;
+}
+
+static int mvebu_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct mvebu_platdata *plat = dev_get_platdata(dev);
+ void __iomem *base = plat->base;
+
+ /*
+ * Calculate divider
+ * baudrate = clock / 16 / divider
+ */
+ writel(CONFIG_UART_BASE_CLOCK / baudrate / 16, base + UART_BAUD_REG);
+
+ /*
+ * Set Programmable Oversampling Stack to 0,
+ * UART defaults to 16x scheme
+ */
+ writel(0, base + UART_POSSR_REG);
+
+ return 0;
+}
+
+static int mvebu_serial_probe(struct udevice *dev)
+{
+ struct mvebu_platdata *plat = dev_get_platdata(dev);
+ void __iomem *base = plat->base;
+
+ /* reset FIFOs */
+ writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
+ base + UART_CTRL_REG);
+
+ /* No Parity, 1 Stop */
+ writel(0, base + UART_CTRL_REG);
+
+ return 0;
+}
+
+static int mvebu_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mvebu_platdata *plat = dev_get_platdata(dev);
+
+ plat->base = dev_get_addr_ptr(dev);
+
+ return 0;
+}
+
+static const struct dm_serial_ops mvebu_serial_ops = {
+ .putc = mvebu_serial_putc,
+ .pending = mvebu_serial_pending,
+ .getc = mvebu_serial_getc,
+ .setbrg = mvebu_serial_setbrg,
+};
+
+static const struct udevice_id mvebu_serial_ids[] = {
+ { .compatible = "marvell,armada-3700-uart" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_mvebu) = {
+ .name = "serial_mvebu",
+ .id = UCLASS_SERIAL,
+ .of_match = mvebu_serial_ids,
+ .ofdata_to_platdata = mvebu_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct mvebu_platdata),
+ .probe = mvebu_serial_probe,
+ .ops = &mvebu_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_MVEBU_A3700_UART
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+ void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+
+ /* reset FIFOs */
+ writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
+ base + UART_CTRL_REG);
+
+ /* No Parity, 1 Stop */
+ writel(0, base + UART_CTRL_REG);
+
+ /*
+ * Calculate divider
+ * baudrate = clock / 16 / divider
+ */
+ writel(CONFIG_UART_BASE_CLOCK / 115200 / 16, base + UART_BAUD_REG);
+
+ /*
+ * Set Programmable Oversampling Stack to 0,
+ * UART defaults to 16x scheme
+ */
+ writel(0, base + UART_POSSR_REG);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+
+ while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
+ ;
+
+ writel(ch, base + UART_TX_REG);
+}
+
+DEBUG_UART_FUNCS
+#endif
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 8545714..4fd2b1d 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -108,6 +108,8 @@
#define UTS_RXFULL (1<<3) /* RxFIFO full */
#define UTS_SOFTRST (1<<0) /* Software reset */
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_DM_SERIAL
#ifndef CONFIG_MXC_UART_BASE
@@ -135,8 +137,6 @@
#define UBRC 0xac /* Baud Rate Count Register */
#define UTS 0xb4 /* UART Test Register (mx31) */
-DECLARE_GLOBAL_DATA_PTR;
-
#define TXTL 2 /* reset default */
#define RXTL 1 /* reset default */
#define RFDIV 4 /* divide input clock by 2 */
@@ -347,9 +347,37 @@
.setbrg = mxc_serial_setbrg,
};
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mxc_serial_platdata *plat = dev->platdata;
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->reg = (struct mxc_uart *)addr;
+
+ plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ "fsl,dte-mode");
+ return 0;
+}
+
+static const struct udevice_id mxc_serial_ids[] = {
+ { .compatible = "fsl,imx7d-uart" },
+ { }
+};
+#endif
+
U_BOOT_DRIVER(serial_mxc) = {
.name = "serial_mxc",
.id = UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .of_match = mxc_serial_ids,
+ .ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
+#endif
.probe = mxc_serial_probe,
.ops = &mxc_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 6f83835..a8d3d67 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -356,6 +356,8 @@
plat->base = addr;
plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
plat->type = dev_get_driver_data(dev);
+ plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ "skip-init");
return 0;
}
#endif
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
index 1eb19ec..ea5971b 100644
--- a/drivers/serial/serial_pxa.c
+++ b/drivers/serial/serial_pxa.c
@@ -14,6 +14,9 @@
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
+ * Modified to add driver model (DM) support
+ * (C) Copyright 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -21,73 +24,17 @@
#include <asm/arch/pxa-regs.h>
#include <asm/arch/regs-uart.h>
#include <asm/io.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pxa.h>
#include <linux/compiler.h>
#include <serial.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
-/*
- * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
- * easily handle enabling of clock.
- */
-#ifdef CONFIG_CPU_MONAHANS
-#define UART_CLK_BASE CKENA_21_BTUART
-#define UART_CLK_REG CKENA
-#define BTUART_INDEX 0
-#define FFUART_INDEX 1
-#define STUART_INDEX 2
-#elif CONFIG_CPU_PXA25X
-#define UART_CLK_BASE (1 << 4) /* HWUART */
-#define UART_CLK_REG CKEN
-#define HWUART_INDEX 0
-#define STUART_INDEX 1
-#define FFUART_INDEX 2
-#define BTUART_INDEX 3
-#else /* PXA27x */
-#define UART_CLK_BASE CKEN5_STUART
-#define UART_CLK_REG CKEN
-#define STUART_INDEX 0
-#define FFUART_INDEX 1
-#define BTUART_INDEX 2
-#endif
-
-/*
- * Only PXA250 has HWUART, to avoid poluting the code with more macros,
- * artificially introduce this.
- */
-#ifndef CONFIG_CPU_PXA25X
-#define HWUART_INDEX 0xff
-#endif
-
-static uint32_t pxa_uart_get_baud_divider(void)
+static uint32_t pxa_uart_get_baud_divider(int baudrate)
{
- if (gd->baudrate == 1200)
- return 768;
- else if (gd->baudrate == 9600)
- return 96;
- else if (gd->baudrate == 19200)
- return 48;
- else if (gd->baudrate == 38400)
- return 24;
- else if (gd->baudrate == 57600)
- return 16;
- else if (gd->baudrate == 115200)
- return 8;
- else /* Unsupported baudrate */
- return 0;
-}
-
-static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
-{
- switch (uart_index) {
- case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
- case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
- case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
- case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
- default:
- return NULL;
- }
+ return 921600 / baudrate;
}
static void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
@@ -110,20 +57,14 @@
/*
* Enable clock and set baud rate, parity etc.
*/
-void pxa_setbrg_dev(uint32_t uart_index)
+void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int baudrate)
{
- uint32_t divider = 0;
- struct pxa_uart_regs *uart_regs;
-
- divider = pxa_uart_get_baud_divider();
+ uint32_t divider = pxa_uart_get_baud_divider(baudrate);
if (!divider)
hang();
- uart_regs = pxa_uart_index_to_regs(uart_index);
- if (!uart_regs)
- hang();
- pxa_uart_toggle_clock(uart_index, 1);
+ pxa_uart_toggle_clock(port, 1);
/* Disable interrupts and FIFOs */
writel(0, &uart_regs->ier);
@@ -139,13 +80,38 @@
writel(IER_UUE, &uart_regs->ier);
}
+#ifndef CONFIG_DM_SERIAL
+static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
+{
+ switch (uart_index) {
+ case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
+ case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
+ case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
+ case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
+ default:
+ return NULL;
+ }
+}
+
+/*
+ * Enable clock and set baud rate, parity etc.
+ */
+void pxa_setbrg_dev(uint32_t uart_index)
+{
+ struct pxa_uart_regs *uart_regs = pxa_uart_index_to_regs(uart_index);
+ if (!uart_regs)
+ panic("Failed getting UART registers\n");
+
+ pxa_setbrg_common(uart_regs, uart_index, gd->baudrate);
+}
+
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
int pxa_init_dev(unsigned int uart_index)
{
- pxa_setbrg_dev (uart_index);
+ pxa_setbrg_dev(uart_index);
return 0;
}
@@ -297,3 +263,80 @@
serial_register(&serial_stuart_device);
#endif
}
+#endif /* CONFIG_DM_SERIAL */
+
+#ifdef CONFIG_DM_SERIAL
+static int pxa_serial_probe(struct udevice *dev)
+{
+ struct pxa_serial_platdata *plat = dev->platdata;
+
+ pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port,
+ plat->baudrate);
+ return 0;
+}
+
+static int pxa_serial_putc(struct udevice *dev, const char ch)
+{
+ struct pxa_serial_platdata *plat = dev->platdata;
+ struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
+
+ /* Wait for last character to go. */
+ if (!(readl(&uart_regs->lsr) & LSR_TEMT))
+ return -EAGAIN;
+
+ writel(ch, &uart_regs->thr);
+
+ return 0;
+}
+
+static int pxa_serial_getc(struct udevice *dev)
+{
+ struct pxa_serial_platdata *plat = dev->platdata;
+ struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
+
+ /* Wait for a character to arrive. */
+ if (!(readl(&uart_regs->lsr) & LSR_DR))
+ return -EAGAIN;
+
+ return readl(&uart_regs->rbr) & 0xff;
+}
+
+int pxa_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct pxa_serial_platdata *plat = dev->platdata;
+ struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
+ int port = plat->port;
+
+ pxa_setbrg_common(uart_regs, port, baudrate);
+
+ return 0;
+}
+
+static int pxa_serial_pending(struct udevice *dev, bool input)
+{
+ struct pxa_serial_platdata *plat = dev->platdata;
+ struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
+
+ if (input)
+ return readl(&uart_regs->lsr) & LSR_DR ? 1 : 0;
+ else
+ return readl(&uart_regs->lsr) & LSR_TEMT ? 0 : 1;
+
+ return 0;
+}
+
+static const struct dm_serial_ops pxa_serial_ops = {
+ .putc = pxa_serial_putc,
+ .pending = pxa_serial_pending,
+ .getc = pxa_serial_getc,
+ .setbrg = pxa_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_pxa) = {
+ .name = "serial_pxa",
+ .id = UCLASS_SERIAL,
+ .probe = pxa_serial_probe,
+ .ops = &pxa_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+#endif /* CONFIG_DM_SERIAL */
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
deleted file mode 100644
index 0f0878a..0000000
--- a/drivers/serial/serial_s3c24x0.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/compiler.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SERIAL1
-#define UART_NR S3C24X0_UART0
-
-#elif defined(CONFIG_SERIAL2)
-#define UART_NR S3C24X0_UART1
-
-#elif defined(CONFIG_SERIAL3)
-#define UART_NR S3C24X0_UART2
-
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
-
-#include <asm/io.h>
-#include <serial.h>
-
-/* Multi serial device functions */
-#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \
- int s3serial##port##_init(void) \
- { \
- return serial_init_dev(port); \
- } \
- void s3serial##port##_setbrg(void) \
- { \
- serial_setbrg_dev(port); \
- } \
- int s3serial##port##_getc(void) \
- { \
- return serial_getc_dev(port); \
- } \
- int s3serial##port##_tstc(void) \
- { \
- return serial_tstc_dev(port); \
- } \
- void s3serial##port##_putc(const char c) \
- { \
- serial_putc_dev(port, c); \
- } \
- void s3serial##port##_puts(const char *s) \
- { \
- serial_puts_dev(port, s); \
- }
-
-#define INIT_S3C_SERIAL_STRUCTURE(port, __name) { \
- .name = __name, \
- .start = s3serial##port##_init, \
- .stop = NULL, \
- .setbrg = s3serial##port##_setbrg, \
- .getc = s3serial##port##_getc, \
- .tstc = s3serial##port##_tstc, \
- .putc = s3serial##port##_putc, \
- .puts = s3serial##port##_puts, \
-}
-
-static void _serial_setbrg(const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
- unsigned int reg = 0;
- int i;
-
- /* value is calculated so : (int)(PCLK/16./baudrate) -1 */
- reg = get_PCLK() / (16 * gd->baudrate) - 1;
-
- writel(reg, &uart->ubrdiv);
- for (i = 0; i < 100; i++)
- /* Delay */ ;
-}
-
-static inline void serial_setbrg_dev(unsigned int dev_index)
-{
- _serial_setbrg(dev_index);
-}
-
-/* Initialise the serial port. The settings are always 8 data bits, no parity,
- * 1 stop bit, no start bits.
- */
-static int serial_init_dev(const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
-
- /* FIFO enable, Tx/Rx FIFO clear */
- writel(0x07, &uart->ufcon);
- writel(0x0, &uart->umcon);
-
- /* Normal,No parity,1 stop,8 bit */
- writel(0x3, &uart->ulcon);
- /*
- * tx=level,rx=edge,disable timeout int.,enable rx error int.,
- * normal,interrupt or polling
- */
- writel(0x245, &uart->ucon);
-
- _serial_setbrg(dev_index);
-
- return (0);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int _serial_getc(const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
-
- while (!(readl(&uart->utrstat) & 0x1))
- /* wait for character to arrive */ ;
-
- return readb(&uart->urxh) & 0xff;
-}
-
-static inline int serial_getc_dev(unsigned int dev_index)
-{
- return _serial_getc(dev_index);
-}
-
-/*
- * Output a single byte to the serial port.
- */
-static void _serial_putc(const char c, const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-
- while (!(readl(&uart->utrstat) & 0x2))
- /* wait for room in the tx FIFO */ ;
-
- writeb(c, &uart->utxh);
-}
-
-static inline void serial_putc_dev(unsigned int dev_index, const char c)
-{
- _serial_putc(c, dev_index);
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-static int _serial_tstc(const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
-
- return readl(&uart->utrstat) & 0x1;
-}
-
-static inline int serial_tstc_dev(unsigned int dev_index)
-{
- return _serial_tstc(dev_index);
-}
-
-static void _serial_puts(const char *s, const int dev_index)
-{
- while (*s) {
- _serial_putc(*s++, dev_index);
- }
-}
-
-static inline void serial_puts_dev(int dev_index, const char *s)
-{
- _serial_puts(s, dev_index);
-}
-
-DECLARE_S3C_SERIAL_FUNCTIONS(0);
-struct serial_device s3c24xx_serial0_device =
-INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0");
-DECLARE_S3C_SERIAL_FUNCTIONS(1);
-struct serial_device s3c24xx_serial1_device =
-INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1");
-DECLARE_S3C_SERIAL_FUNCTIONS(2);
-struct serial_device s3c24xx_serial2_device =
-INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2");
-
-__weak struct serial_device *default_serial_console(void)
-{
-#if defined(CONFIG_SERIAL1)
- return &s3c24xx_serial0_device;
-#elif defined(CONFIG_SERIAL2)
- return &s3c24xx_serial1_device;
-#elif defined(CONFIG_SERIAL3)
- return &s3c24xx_serial2_device;
-#else
-#error "CONFIG_SERIAL? missing."
-#endif
-}
-
-void s3c24xx_serial_initialize(void)
-{
- serial_register(&s3c24xx_serial0_device);
- serial_register(&s3c24xx_serial1_device);
- serial_register(&s3c24xx_serial2_device);
-}
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index ab607b7..4ea5304 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -9,7 +9,7 @@
#include <linux/io.h>
#include <linux/serial_reg.h>
#include <linux/sizes.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <dm/device.h>
#include <serial.h>
#include <fdtdec.h>
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index aca385d..0f51b3a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -32,6 +32,14 @@
uses driver model and requires a device tree binding to operate.
please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+config ATMEL_SPI
+ bool "Atmel SPI driver"
+ depends on ARCH_AT91
+ help
+ This enables driver for the Atmel SPI Controller, present on
+ many AT32 (AVR32) and AT91 (ARM) chips. This driver can be
+ used to access the SPI Flash, such as AT25DF321.
+
config CADENCE_QSPI
bool "Cadence QSPI driver"
help
@@ -61,13 +69,6 @@
this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
use this driver.
-config FSL_QSPI
- bool "Freescale QSPI driver"
- help
- Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
- used to access the SPI NOR flash on platforms embedding this
- Freescale IP core.
-
config ICH_SPI
bool "Intel ICH SPI driver"
help
@@ -75,6 +76,13 @@
access the SPI NOR flash on platforms embedding this Intel
ICH IP core.
+config MVEBU_A3700_SPI
+ bool "Marvell Armada 3700 SPI driver"
+ help
+ Enable the Marvell Armada 3700 SPI driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ Marvell IP core.
+
config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32
@@ -188,6 +196,13 @@
access the SPI interface and SPI NOR flash on platforms embedding
this Freescale eSPI IP core.
+config FSL_QSPI
+ bool "Freescale QSPI driver"
+ help
+ Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ Freescale IP core.
+
config TI_QSPI
bool "TI QSPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index b1d9e20..c1ce158 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -16,7 +16,6 @@
endif
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
-obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
@@ -35,8 +34,8 @@
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
-obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
+obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
diff --git a/drivers/spi/armada100_spi.c b/drivers/spi/armada100_spi.c
deleted file mode 100644
index 53aaf95..0000000
--- a/drivers/spi/armada100_spi.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Based on SSP driver
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/io.h>
-#include <asm/arch/spi.h>
-#include <asm/gpio.h>
-
-#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave)
-
-struct armd_spi_slave {
- struct spi_slave slave;
- struct ssp_reg *spi_reg;
- u32 cr0, cr1;
- u32 int_cr1;
- u32 clear_sr;
- const void *tx;
- void *rx;
- int gpio_cs_inverted;
-};
-
-static int spi_armd_write(struct armd_spi_slave *pss)
-{
- int wait_timeout = SSP_FLUSH_NUM;
- while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF))
- ;
- if (!wait_timeout) {
- debug("%s: timeout error\n", __func__);
- return -1;
- }
-
- if (pss->tx != NULL) {
- writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr);
- ++pss->tx;
- } else {
- writel(0, &pss->spi_reg->ssdr);
- }
- return 0;
-}
-
-static int spi_armd_read(struct armd_spi_slave *pss)
-{
- int wait_timeout = SSP_FLUSH_NUM;
- while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE))
- ;
- if (!wait_timeout) {
- debug("%s: timeout error\n", __func__);
- return -1;
- }
-
- if (pss->rx != NULL) {
- *(u8 *)pss->rx = readl(&pss->spi_reg->ssdr);
- ++pss->rx;
- } else {
- readl(&pss->spi_reg->ssdr);
- }
- return 0;
-}
-
-static int spi_armd_flush(struct armd_spi_slave *pss)
-{
- unsigned long limit = SSP_FLUSH_NUM;
-
- do {
- while (readl(&pss->spi_reg->sssr) & SSSR_RNE)
- readl(&pss->spi_reg->ssdr);
- } while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--);
-
- writel(SSSR_ROR, &pss->spi_reg->sssr);
-
- return limit;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
-
- gpio_set_value(slave->cs, pss->gpio_cs_inverted);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
-
- gpio_set_value(slave->cs, !pss->gpio_cs_inverted);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct armd_spi_slave *pss;
-
- pss = spi_alloc_slave(struct armd_spi_slave, bus, cs);
- if (!pss)
- return NULL;
-
- pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT);
-
- pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE;
-
- pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) |
- (SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT);
- pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
- pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
- | (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
-
- pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
- pss->clear_sr = SSSR_ROR | SSSR_TINT;
-
- pss->gpio_cs_inverted = mode & SPI_CS_HIGH;
- gpio_set_value(cs, !pss->gpio_cs_inverted);
-
- return &pss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
-
- free(pss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- if (spi_armd_flush(pss) == 0)
- return -1;
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct armd_spi_slave *pss = to_armd_spi_slave(slave);
- uint bytes = bitlen / 8;
- unsigned long limit;
- int ret = 0;
-
- if (bitlen == 0)
- goto done;
-
- /* we can only do 8 bit transfers */
- if (bitlen % 8) {
- flags |= SPI_XFER_END;
- goto done;
- }
-
- pss->tx = dout;
- pss->rx = din;
-
- if (flags & SPI_XFER_BEGIN) {
- spi_cs_activate(slave);
- writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1);
- writel(TIMEOUT_DEF, &pss->spi_reg->ssto);
- writel(pss->cr0, &pss->spi_reg->sscr0);
- }
-
- while (bytes--) {
- limit = SSP_FLUSH_NUM;
- ret = spi_armd_write(pss);
- if (ret)
- break;
-
- while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--)
- udelay(1);
-
- ret = spi_armd_read(pss);
- if (ret)
- break;
- }
-
- done:
- if (flags & SPI_XFER_END) {
- /* Stop SSP */
- writel(pss->clear_sr, &pss->spi_reg->sssr);
- clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1);
- writel(0, &pss->spi_reg->ssto);
- spi_cs_deactivate(slave);
- }
-
- return ret;
-}
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index ed6278b..7649114 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -4,16 +4,30 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
#include <spi.h>
#include <malloc.h>
+#include <wait_bit.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
+#ifdef CONFIG_DM_SPI
+#include <asm/arch/at91_spi.h>
+#endif
+#ifdef CONFIG_DM_GPIO
+#include <asm/gpio.h>
+#endif
#include "atmel_spi.h"
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_DM_SPI
+
static int spi_has_wdrbt(struct atmel_spi_slave *slave)
{
unsigned int ver;
@@ -209,3 +223,277 @@
return 0;
}
+
+#else
+
+#define MAX_CS_COUNT 4
+
+struct atmel_spi_platdata {
+ struct at91_spi *regs;
+};
+
+struct atmel_spi_priv {
+ unsigned int freq; /* Default frequency */
+ unsigned int mode;
+ ulong bus_clk_rate;
+ struct gpio_desc cs_gpios[MAX_CS_COUNT];
+};
+
+static int atmel_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
+ struct atmel_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct at91_spi *reg_base = bus_plat->regs;
+ u32 cs = slave_plat->cs;
+ u32 freq = priv->freq;
+ u32 scbr, csrx, mode;
+
+ scbr = (priv->bus_clk_rate + freq - 1) / freq;
+ if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
+ return -EINVAL;
+
+ if (scbr < 1)
+ scbr = 1;
+
+ csrx = ATMEL_SPI_CSRx_SCBR(scbr);
+ csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
+
+ if (!(priv->mode & SPI_CPHA))
+ csrx |= ATMEL_SPI_CSRx_NCPHA;
+ if (priv->mode & SPI_CPOL)
+ csrx |= ATMEL_SPI_CSRx_CPOL;
+
+ writel(csrx, ®_base->csr[cs]);
+
+ mode = ATMEL_SPI_MR_MSTR |
+ ATMEL_SPI_MR_MODFDIS |
+ ATMEL_SPI_MR_WDRBT |
+ ATMEL_SPI_MR_PCS(~(1 << cs));
+
+ writel(mode, ®_base->mr);
+
+ writel(ATMEL_SPI_CR_SPIEN, ®_base->cr);
+
+ return 0;
+}
+
+static int atmel_spi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
+
+ writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
+
+ return 0;
+}
+
+static void atmel_spi_cs_activate(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct atmel_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ u32 cs = slave_plat->cs;
+
+ dm_gpio_set_value(&priv->cs_gpios[cs], 0);
+}
+
+static void atmel_spi_cs_deactivate(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct atmel_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ u32 cs = slave_plat->cs;
+
+ dm_gpio_set_value(&priv->cs_gpios[cs], 1);
+}
+
+static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
+ struct at91_spi *reg_base = bus_plat->regs;
+
+ u32 len_tx, len_rx, len;
+ u32 status;
+ const u8 *txp = dout;
+ u8 *rxp = din;
+ u8 value;
+
+ if (bitlen == 0)
+ goto out;
+
+ /*
+ * The controller can do non-multiple-of-8 bit
+ * transfers, but this driver currently doesn't support it.
+ *
+ * It's also not clear how such transfers are supposed to be
+ * represented as a stream of bytes...this is a limitation of
+ * the current SPI interface.
+ */
+ if (bitlen % 8) {
+ /* Errors always terminate an ongoing transfer */
+ flags |= SPI_XFER_END;
+ goto out;
+ }
+
+ len = bitlen / 8;
+
+ /*
+ * The controller can do automatic CS control, but it is
+ * somewhat quirky, and it doesn't really buy us much anyway
+ * in the context of U-Boot.
+ */
+ if (flags & SPI_XFER_BEGIN) {
+ atmel_spi_cs_activate(dev);
+
+ /*
+ * sometimes the RDR is not empty when we get here,
+ * in theory that should not happen, but it DOES happen.
+ * Read it here to be on the safe side.
+ * That also clears the OVRES flag. Required if the
+ * following loop exits due to OVRES!
+ */
+ readl(®_base->rdr);
+ }
+
+ for (len_tx = 0, len_rx = 0; len_rx < len; ) {
+ status = readl(®_base->sr);
+
+ if (status & ATMEL_SPI_SR_OVRES)
+ return -1;
+
+ if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
+ if (txp)
+ value = *txp++;
+ else
+ value = 0;
+ writel(value, ®_base->tdr);
+ len_tx++;
+ }
+
+ if (status & ATMEL_SPI_SR_RDRF) {
+ value = readl(®_base->rdr);
+ if (rxp)
+ *rxp++ = value;
+ len_rx++;
+ }
+ }
+
+out:
+ if (flags & SPI_XFER_END) {
+ /*
+ * Wait until the transfer is completely done before
+ * we deactivate CS.
+ */
+ wait_for_bit(__func__, ®_base->sr,
+ ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
+
+ atmel_spi_cs_deactivate(dev);
+ }
+
+ return 0;
+}
+
+static int atmel_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct atmel_spi_priv *priv = dev_get_priv(bus);
+
+ priv->freq = speed;
+
+ return 0;
+}
+
+static int atmel_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct atmel_spi_priv *priv = dev_get_priv(bus);
+
+ priv->mode = mode;
+
+ return 0;
+}
+
+static const struct dm_spi_ops atmel_spi_ops = {
+ .claim_bus = atmel_spi_claim_bus,
+ .release_bus = atmel_spi_release_bus,
+ .xfer = atmel_spi_xfer,
+ .set_speed = atmel_spi_set_speed,
+ .set_mode = atmel_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static int atmel_spi_enable_clk(struct udevice *bus)
+{
+ struct atmel_spi_priv *priv = dev_get_priv(bus);
+ struct clk clk;
+ ulong clk_rate;
+ int ret;
+
+ ret = clk_get_by_index(bus, 0, &clk);
+ if (ret)
+ return -EINVAL;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ return ret;
+
+ clk_rate = clk_get_rate(&clk);
+ if (!clk_rate)
+ return -EINVAL;
+
+ priv->bus_clk_rate = clk_rate;
+
+ clk_free(&clk);
+
+ return 0;
+}
+
+static int atmel_spi_probe(struct udevice *bus)
+{
+ struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
+ struct atmel_spi_priv *priv = dev_get_priv(bus);
+ int i, ret;
+
+ ret = atmel_spi_enable_clk(bus);
+ if (ret)
+ return ret;
+
+ bus_plat->regs = (struct at91_spi *)dev_get_addr(bus);
+
+ ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
+ ARRAY_SIZE(priv->cs_gpios), 0);
+ if (ret < 0) {
+ error("Can't get %s gpios! Error: %d", bus->name, ret);
+ return ret;
+ }
+
+ for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
+ dm_gpio_set_dir_flags(&priv->cs_gpios[i],
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ }
+
+ writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
+
+ return 0;
+}
+
+static const struct udevice_id atmel_spi_ids[] = {
+ { .compatible = "atmel,at91rm9200-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(atmel_spi) = {
+ .name = "atmel_spi",
+ .id = UCLASS_SPI,
+ .of_match = atmel_spi_ids,
+ .ops = &atmel_spi_ops,
+ .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
+ .probe = atmel_spi_probe,
+};
+#endif
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index a5244ff..f16f90d 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -10,7 +10,7 @@
#include <fdtdec.h>
#include <malloc.h>
#include <spi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "cadence_qspi.h"
#define CQSPI_STIG_READ 0
@@ -170,14 +170,12 @@
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
- unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
- unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
/* Set SPI mode */
- cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
+ cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
/* Enable QSPI */
cadence_qspi_apb_controller_enable(priv->regbase);
@@ -251,7 +249,7 @@
break;
case CQSPI_INDIRECT_READ:
err = cadence_qspi_apb_indirect_read_setup(plat,
- priv->cmd_len, dm_plat->mode_rx, cmd_buf);
+ priv->cmd_len, dm_plat->mode, cmd_buf);
if (!err) {
err = cadence_qspi_apb_indirect_read_execute
(plat, data_bytes, din);
@@ -298,6 +296,7 @@
plat->regbase = (void *)data[0];
plat->ahbbase = (void *)data[2];
+ plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
/* All other paramters are embedded in the child node */
subnode = fdt_first_subnode(blob, node);
@@ -317,7 +316,6 @@
plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
- plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index a849f7b..d1927a4 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -63,8 +63,7 @@
void cadence_qspi_apb_chipselect(void *reg_base,
unsigned int chip_select, unsigned int decoder_enable);
-void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
- unsigned int clk_pol, unsigned int clk_pha);
+void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
unsigned int ref_clk_hz, unsigned int sclk_hz);
void cadence_qspi_apb_delay(void *reg_base,
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 1d68379..e02f221 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -27,42 +27,43 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <wait_bit.h>
#include <spi.h>
+#include <bouncebuf.h>
#include "cadence_qspi.h"
-#define CQSPI_REG_POLL_US (1) /* 1us */
-#define CQSPI_REG_RETRY (10000)
-#define CQSPI_POLL_IDLE_RETRY (3)
+#define CQSPI_REG_POLL_US 1 /* 1us */
+#define CQSPI_REG_RETRY 10000
+#define CQSPI_POLL_IDLE_RETRY 3
-#define CQSPI_FIFO_WIDTH (4)
+#define CQSPI_FIFO_WIDTH 4
-#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
+#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50
/* Transfer mode */
-#define CQSPI_INST_TYPE_SINGLE (0)
-#define CQSPI_INST_TYPE_DUAL (1)
-#define CQSPI_INST_TYPE_QUAD (2)
+#define CQSPI_INST_TYPE_SINGLE 0
+#define CQSPI_INST_TYPE_DUAL 1
+#define CQSPI_INST_TYPE_QUAD 2
-#define CQSPI_STIG_DATA_LEN_MAX (8)
+#define CQSPI_STIG_DATA_LEN_MAX 8
-#define CQSPI_DUMMY_CLKS_PER_BYTE (8)
-#define CQSPI_DUMMY_BYTES_MAX (4)
-
+#define CQSPI_DUMMY_CLKS_PER_BYTE 8
+#define CQSPI_DUMMY_BYTES_MAX 4
#define CQSPI_REG_SRAM_FILL_THRESHOLD \
((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
+
/****************************************************************************
* Controller's configuration and status register (offset from QSPI_BASE)
****************************************************************************/
#define CQSPI_REG_CONFIG 0x00
-#define CQSPI_REG_CONFIG_CLK_POL_LSB 1
-#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2
-#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
-#define CQSPI_REG_CONFIG_DIRECT_MASK BIT(7)
-#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
-#define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18)
+#define CQSPI_REG_CONFIG_ENABLE BIT(0)
+#define CQSPI_REG_CONFIG_CLK_POL BIT(1)
+#define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
+#define CQSPI_REG_CONFIG_DIRECT BIT(7)
+#define CQSPI_REG_CONFIG_DECODE BIT(9)
+#define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_BAUD_LSB 19
#define CQSPI_REG_CONFIG_IDLE_LSB 31
@@ -94,10 +95,10 @@
#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
-#define CQSPI_READLCAPTURE 0x10
-#define CQSPI_READLCAPTURE_BYPASS_LSB 0
-#define CQSPI_READLCAPTURE_DELAY_LSB 1
-#define CQSPI_READLCAPTURE_DELAY_MASK 0xF
+#define CQSPI_REG_RD_DATA_CAPTURE 0x10
+#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
+#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
+#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
#define CQSPI_REG_SIZE 0x14
#define CQSPI_REG_SIZE_ADDRESS_LSB 0
@@ -123,18 +124,18 @@
#define CQSPI_REG_IRQMASK 0x44
#define CQSPI_REG_INDIRECTRD 0x60
-#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
-#define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
-#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK BIT(2)
-#define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
+#define CQSPI_REG_INDIRECTRD_START BIT(0)
+#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
+#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
+#define CQSPI_REG_INDIRECTRD_DONE BIT(5)
#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
#define CQSPI_REG_INDIRECTRDBYTES 0x6C
#define CQSPI_REG_CMDCTRL 0x90
-#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
-#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
+#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
+#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
@@ -150,10 +151,10 @@
#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
#define CQSPI_REG_INDIRECTWR 0x70
-#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
-#define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
-#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK BIT(2)
-#define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
+#define CQSPI_REG_INDIRECTWR_START BIT(0)
+#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
+#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
+#define CQSPI_REG_INDIRECTWR_DONE BIT(5)
#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
@@ -169,9 +170,6 @@
((readl(base + CQSPI_REG_CONFIG) >> \
CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
-#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
- ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
-
#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
@@ -197,18 +195,16 @@
{
unsigned int reg;
reg = readl(reg_base + CQSPI_REG_CONFIG);
- reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
+ reg |= CQSPI_REG_CONFIG_ENABLE;
writel(reg, reg_base + CQSPI_REG_CONFIG);
- return;
}
void cadence_qspi_apb_controller_disable(void *reg_base)
{
unsigned int reg;
reg = readl(reg_base + CQSPI_REG_CONFIG);
- reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
+ reg &= ~CQSPI_REG_CONFIG_ENABLE;
writel(reg, reg_base + CQSPI_REG_CONFIG);
- return;
}
/* Return 1 if idle, otherwise return 0 (busy). */
@@ -244,23 +240,22 @@
unsigned int reg;
cadence_qspi_apb_controller_disable(reg_base);
- reg = readl(reg_base + CQSPI_READLCAPTURE);
+ reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
if (bypass)
- reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
+ reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
else
- reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
+ reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
- reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
- << CQSPI_READLCAPTURE_DELAY_LSB);
+ reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
+ << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
- reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
- << CQSPI_READLCAPTURE_DELAY_LSB);
+ reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
+ << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
- writel(reg, reg_base + CQSPI_READLCAPTURE);
+ writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
@@ -273,54 +268,42 @@
reg = readl(reg_base + CQSPI_REG_CONFIG);
reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
- div = ref_clk_hz / sclk_hz;
-
- if (div > 32)
- div = 32;
-
- /* Check if even number. */
- if ((div & 1)) {
- div = (div / 2);
- } else {
- if (ref_clk_hz % sclk_hz)
- /* ensure generated SCLK doesn't exceed user
- specified sclk_hz */
- div = (div / 2);
- else
- div = (div / 2) - 1;
- }
-
- debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
- ref_clk_hz, sclk_hz, div);
+ /*
+ * The baud_div field in the config reg is 4 bits, and the ref clock is
+ * divided by 2 * (baud_div + 1). Round up the divider to ensure the
+ * SPI clock rate is less than or equal to the requested clock rate.
+ */
+ div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
/* ensure the baud rate doesn't exceed the max value */
if (div > CQSPI_REG_CONFIG_BAUD_MASK)
div = CQSPI_REG_CONFIG_BAUD_MASK;
+ debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
+ ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
+
reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
-void cadence_qspi_apb_set_clk_mode(void *reg_base,
- unsigned int clk_pol, unsigned int clk_pha)
+void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
{
unsigned int reg;
cadence_qspi_apb_controller_disable(reg_base);
reg = readl(reg_base + CQSPI_REG_CONFIG);
- reg &= ~(1 <<
- (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
+ reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
- reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
- reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
+ if (mode & SPI_CPOL)
+ reg |= CQSPI_REG_CONFIG_CLK_POL;
+ if (mode & SPI_CPHA)
+ reg |= CQSPI_REG_CONFIG_CLK_PHA;
writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
void cadence_qspi_apb_chipselect(void *reg_base,
@@ -336,9 +319,9 @@
reg = readl(reg_base + CQSPI_REG_CONFIG);
/* docoder */
if (decoder_enable) {
- reg |= CQSPI_REG_CONFIG_DECODE_MASK;
+ reg |= CQSPI_REG_CONFIG_DECODE;
} else {
- reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
+ reg &= ~CQSPI_REG_CONFIG_DECODE;
/* Convert CS if without decoder.
* CS0 to 4b'1110
* CS1 to 4b'1101
@@ -355,7 +338,6 @@
writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
void cadence_qspi_apb_delay(void *reg_base,
@@ -371,16 +353,20 @@
cadence_qspi_apb_controller_disable(reg_base);
/* Convert to ns. */
- ref_clk_ns = (1000000000) / ref_clk;
+ ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
/* Convert to ns. */
- sclk_ns = (1000000000) / sclk_hz;
+ sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
- /* Plus 1 to round up 1 clock cycle. */
- tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
- tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
- tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
- tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
+ /* The controller adds additional delay to that programmed in the reg */
+ if (tshsl_ns >= sclk_ns + ref_clk_ns)
+ tshsl_ns -= sclk_ns + ref_clk_ns;
+ if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
+ tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
+ tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
+ tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
+ tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
+ tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
<< CQSPI_REG_DELAY_TSHSL_LSB);
@@ -393,7 +379,6 @@
writel(reg, reg_base + CQSPI_REG_DELAY);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
@@ -421,7 +406,6 @@
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
cadence_qspi_apb_controller_enable(plat->regbase);
- return;
}
static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
@@ -432,12 +416,12 @@
/* Write the CMDCTRL without start execution. */
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
/* Start execute */
- reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
+ reg |= CQSPI_REG_CMDCTRL_EXECUTE;
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
while (retry--) {
reg = readl(reg_base + CQSPI_REG_CMDCTRL);
- if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
+ if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
break;
udelay(1);
}
@@ -650,14 +634,21 @@
{
unsigned int remaining = n_rx;
unsigned int bytes_to_read = 0;
+ struct bounce_buffer bb;
+ u8 *bb_rxbuf;
int ret;
writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
/* Start the indirect read transfer */
- writel(CQSPI_REG_INDIRECTRD_START_MASK,
+ writel(CQSPI_REG_INDIRECTRD_START,
plat->regbase + CQSPI_REG_INDIRECTRD);
+ ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
+ if (ret)
+ return ret;
+ bb_rxbuf = bb.bounce_buffer;
+
while (remaining > 0) {
ret = cadence_qspi_wait_for_data(plat);
if (ret < 0) {
@@ -671,12 +662,13 @@
bytes_to_read *= CQSPI_FIFO_WIDTH;
bytes_to_read = bytes_to_read > remaining ?
remaining : bytes_to_read;
- /* Handle non-4-byte aligned access to avoid data abort. */
- if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
- readsb(plat->ahbbase, rxbuf, bytes_to_read);
- else
- readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
- rxbuf += bytes_to_read;
+ readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2);
+ if (bytes_to_read % 4)
+ readsb(plat->ahbbase,
+ bb_rxbuf + rounddown(bytes_to_read, 4),
+ bytes_to_read % 4);
+
+ bb_rxbuf += bytes_to_read;
remaining -= bytes_to_read;
bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
}
@@ -684,22 +676,24 @@
/* Check indirect done status */
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
- CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0);
+ CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
if (ret) {
printf("Indirect read completion error (%i)\n", ret);
goto failrd;
}
/* Clear indirect completion status */
- writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
+ writel(CQSPI_REG_INDIRECTRD_DONE,
plat->regbase + CQSPI_REG_INDIRECTRD);
+ bounce_buffer_stop(&bb);
return 0;
failrd:
/* Cancel the indirect read */
- writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
+ writel(CQSPI_REG_INDIRECTRD_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTRD);
+ bounce_buffer_stop(&bb);
return ret;
}
@@ -741,21 +735,32 @@
unsigned int remaining = n_tx;
unsigned int write_bytes;
int ret;
+ struct bounce_buffer bb;
+ u8 *bb_txbuf;
+
+ /*
+ * Handle non-4-byte aligned accesses via bounce buffer to
+ * avoid data abort.
+ */
+ ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
+ if (ret)
+ return ret;
+ bb_txbuf = bb.bounce_buffer;
/* Configure the indirect read transfer bytes */
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
/* Start the indirect write transfer */
- writel(CQSPI_REG_INDIRECTWR_START_MASK,
+ writel(CQSPI_REG_INDIRECTWR_START,
plat->regbase + CQSPI_REG_INDIRECTWR);
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
- /* Handle non-4-byte aligned access to avoid data abort. */
- if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
- writesb(plat->ahbbase, txbuf, write_bytes);
- else
- writesl(plat->ahbbase, txbuf, write_bytes >> 2);
+ writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
+ if (write_bytes % 4)
+ writesb(plat->ahbbase,
+ bb_txbuf + rounddown(write_bytes, 4),
+ write_bytes % 4);
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
CQSPI_REG_SDRAMLEVEL_WR_MASK <<
@@ -765,27 +770,29 @@
goto failwr;
}
- txbuf += write_bytes;
+ bb_txbuf += write_bytes;
remaining -= write_bytes;
}
/* Check indirect done status */
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
- CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0);
+ CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
if (ret) {
printf("Indirect write completion error (%i)\n", ret);
goto failwr;
}
+ bounce_buffer_stop(&bb);
/* Clear indirect completion status */
- writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
+ writel(CQSPI_REG_INDIRECTWR_DONE,
plat->regbase + CQSPI_REG_INDIRECTWR);
return 0;
failwr:
/* Cancel the indirect write */
- writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
+ writel(CQSPI_REG_INDIRECTWR_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTWR);
+ bounce_buffer_stop(&bb);
return ret;
}
@@ -795,9 +802,9 @@
/* enter XiP mode immediately and enable direct mode */
reg = readl(reg_base + CQSPI_REG_CONFIG);
- reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
- reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
- reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
+ reg |= CQSPI_REG_CONFIG_ENABLE;
+ reg |= CQSPI_REG_CONFIG_DIRECT;
+ reg |= CQSPI_REG_CONFIG_XIP_IMM;
writel(reg, reg_base + CQSPI_REG_CONFIG);
/* keep the XiP mode */
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index c8dcb27..f213587 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -594,7 +594,7 @@
priv = dev_get_priv(bus);
- /* processor special prepartion work */
+ /* processor special preparation work */
cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
/* configure transfer mode */
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 2144fca..4d378c2 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -865,6 +865,7 @@
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
+ u32 mcr_val;
struct fsl_qspi *qspi;
struct fsl_qspi_regs *regs;
u32 total_size;
@@ -896,8 +897,10 @@
qspi->slave.max_write_size = TX_BUFFER_SIZE;
+ mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr);
qspi_write32(qspi->priv.flags, ®s->mcr,
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
+ QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
+ (mcr_val & QSPI_MCR_END_CFD_MASK));
qspi_cfg_smpr(&qspi->priv,
~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
@@ -975,6 +978,7 @@
static int fsl_qspi_probe(struct udevice *bus)
{
+ u32 mcr_val;
u32 amba_size_per_chip;
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
@@ -999,8 +1003,10 @@
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
+ mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
qspi_write32(priv->flags, &priv->regs->mcr,
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
+ QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
+ (mcr_val & QSPI_MCR_END_CFD_MASK));
qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
@@ -1092,7 +1098,7 @@
}
/* Count flash numbers */
- fdt_for_each_subnode(blob, subnode, node)
+ fdt_for_each_subnode(subnode, blob, node)
++flash_num;
if (flash_num == 0) {
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 00b2fed..caf0103 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -649,10 +649,8 @@
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash
*/
- if (plat->ich_version == ICHV_7) {
- slave->mode_rx = SPI_RX_SLOW;
- slave->mode = SPI_TX_BYTE;
- }
+ if (plat->ich_version == ICHV_7)
+ slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
return 0;
}
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 6851ba9..791f3e8 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -271,6 +271,21 @@
static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data = readl(®->cfg);
+
+ data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
+
+ if (mode & SPI_CPHA)
+ data |= KWSPI_CPHA;
+ if (mode & SPI_CPOL)
+ data |= KWSPI_CPOL;
+ if (mode & SPI_LSB_FIRST)
+ data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
+
+ writel(data, ®->cfg);
+
return 0;
}
diff --git a/drivers/spi/mpc52xx_spi.c b/drivers/spi/mpc52xx_spi.c
deleted file mode 100644
index 4613bec..0000000
--- a/drivers/spi/mpc52xx_spi.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * (C) Copyright 2009
- * Frank Bodammer <frank.bodammer@gcd-solutions.de>
- * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <spi.h>
-#include <mpc5xxx.h>
-
-void spi_init(void)
-{
- struct mpc5xxx_spi *spi = (struct mpc5xxx_spi *)MPC5XXX_SPI;
- /*
- * Its important to use the correct order when initializing the
- * registers
- */
- out_8(&spi->ddr, 0x0F); /* set all SPI pins as output */
- out_8(&spi->pdr, 0x00); /* set SS low */
- /* SPI is master, SS is general purpose output */
- out_8(&spi->cr1, SPI_CR_MSTR | SPI_CR_SPE);
- out_8(&spi->cr2, 0x00); /* normal operation */
- out_8(&spi->brr, 0x77); /* baud rate: IPB clock / 2048 */
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct spi_slave *slave;
-
- slave = spi_alloc_slave_base(bus, cs);
- if (!slave)
- return NULL;
-
- return slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- free(slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- return;
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct mpc5xxx_spi *spi = (struct mpc5xxx_spi *)MPC5XXX_SPI;
- int i, iter = bitlen >> 3;
- const uchar *txp = dout;
- uchar *rxp = din;
-
- debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
- slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
-
- if (flags & SPI_XFER_BEGIN)
- setbits_8(&spi->pdr, SPI_PDR_SS);
-
- for (i = 0; i < iter; i++) {
- udelay(1000);
- debug("spi_xfer: sending %x\n", txp[i]);
- out_8(&spi->dr, txp[i]);
- while (!(in_8(&spi->sr) & SPI_SR_SPIF)) {
- udelay(1000);
- if (in_8(&spi->sr) & SPI_SR_WCOL) {
- rxp[i] = in_8(&spi->dr);
- puts("spi_xfer: write collision\n");
- return -1;
- }
- }
- rxp[i] = in_8(&spi->dr);
- debug("spi_xfer: received %x\n", rxp[i]);
- }
- if (flags & SPI_XFER_END)
- clrbits_8(&spi->pdr, SPI_PDR_SS);
-
- return 0;
-}
diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
new file mode 100644
index 0000000..7c58c36
--- /dev/null
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -0,0 +1,295 @@
+/*
+ * Copyright (C) 2015 Marvell International Ltd.
+ *
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <spi.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MVEBU_SPI_A3700_XFER_RDY BIT(1)
+#define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9)
+#define MVEBU_SPI_A3700_BYTE_LEN BIT(5)
+#define MVEBU_SPI_A3700_CLK_PHA BIT(6)
+#define MVEBU_SPI_A3700_CLK_POL BIT(7)
+#define MVEBU_SPI_A3700_FIFO_EN BIT(17)
+#define MVEBU_SPI_A3700_SPI_EN_0 BIT(16)
+#define MVEBU_SPI_A3700_CLK_PRESCALE_BIT 0
+#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK \
+ (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT)
+
+/* SPI registers */
+struct spi_reg {
+ u32 ctrl; /* 0x10600 */
+ u32 cfg; /* 0x10604 */
+ u32 dout; /* 0x10608 */
+ u32 din; /* 0x1060c */
+};
+
+struct mvebu_spi_platdata {
+ struct spi_reg *spireg;
+ unsigned int frequency;
+ unsigned int clock;
+};
+
+static void spi_cs_activate(struct spi_reg *reg, int cs)
+{
+ setbits_le32(®->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
+}
+
+static void spi_cs_deactivate(struct spi_reg *reg, int cs)
+{
+ clrbits_le32(®->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
+}
+
+/**
+ * spi_legacy_shift_byte() - triggers the real SPI transfer
+ * @bytelen: Indicate how many bytes to transfer.
+ * @dout: Buffer address of what to send.
+ * @din: Buffer address of where to receive.
+ *
+ * This function triggers the real SPI transfer in legacy mode. It
+ * will shift out char buffer from @dout, and shift in char buffer to
+ * @din, if necessary.
+ *
+ * This function assumes that only one byte is shifted at one time.
+ * However, it is not its responisbility to set the transfer type to
+ * one-byte. Also, it does not guarantee that it will work if transfer
+ * type becomes two-byte. See spi_set_legacy() for details.
+ *
+ * In legacy mode, simply write to the SPI_DOUT register will trigger
+ * the transfer.
+ *
+ * If @dout == NULL, which means no actual data needs to be sent out,
+ * then the function will shift out 0x00 in order to shift in data.
+ * The XFER_RDY flag is checked every time before accessing SPI_DOUT
+ * and SPI_DIN register.
+ *
+ * The number of transfers to be triggerred is decided by @bytelen.
+ *
+ * Return: 0 - cool
+ * -ETIMEDOUT - XFER_RDY flag timeout
+ */
+static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
+ const void *dout, void *din)
+{
+ const u8 *dout_8;
+ u8 *din_8;
+ int ret;
+
+ /* Use 0x00 as dummy dout */
+ const u8 dummy_dout = 0x0;
+ u32 pending_dout = 0x0;
+
+ /* dout_8: pointer of current dout */
+ dout_8 = dout;
+ /* din_8: pointer of current din */
+ din_8 = din;
+
+ while (bytelen) {
+ ret = wait_for_bit(__func__, ®->ctrl,
+ MVEBU_SPI_A3700_XFER_RDY, true, 100, false);
+ if (ret)
+ return ret;
+
+ if (dout)
+ pending_dout = (u32)*dout_8;
+ else
+ pending_dout = (u32)dummy_dout;
+
+ /* Trigger the xfer */
+ writel(pending_dout, ®->dout);
+
+ if (din) {
+ ret = wait_for_bit(__func__, ®->ctrl,
+ MVEBU_SPI_A3700_XFER_RDY,
+ true, 100, false);
+ if (ret)
+ return ret;
+
+ /* Read what is transferred in */
+ *din_8 = (u8)readl(®->din);
+ }
+
+ /* Don't increment the current pointer if NULL */
+ if (dout)
+ dout_8++;
+ if (din)
+ din_8++;
+
+ bytelen--;
+ }
+
+ return 0;
+}
+
+static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct spi_reg *reg = plat->spireg;
+ unsigned int bytelen;
+ int ret;
+
+ bytelen = bitlen / 8;
+
+ if (dout && din)
+ debug("This is a duplex transfer.\n");
+
+ /* Activate CS */
+ if (flags & SPI_XFER_BEGIN) {
+ debug("SPI: activate cs.\n");
+ spi_cs_activate(reg, spi_chip_select(dev));
+ }
+
+ /* Send and/or receive */
+ if (dout || din) {
+ ret = spi_legacy_shift_byte(reg, bytelen, dout, din);
+ if (ret)
+ return ret;
+ }
+
+ /* Deactivate CS */
+ if (flags & SPI_XFER_END) {
+ ret = wait_for_bit(__func__, ®->ctrl,
+ MVEBU_SPI_A3700_XFER_RDY, true, 100, false);
+ if (ret)
+ return ret;
+
+ debug("SPI: deactivate cs.\n");
+ spi_cs_deactivate(reg, spi_chip_select(dev));
+ }
+
+ return 0;
+}
+
+static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct spi_reg *reg = plat->spireg;
+ u32 data;
+
+ data = readl(®->cfg);
+
+ /* Set Prescaler */
+ data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
+
+ /* Calculate Prescaler = (spi_input_freq / spi_max_freq) */
+ if (hz > plat->frequency)
+ hz = plat->frequency;
+ data |= plat->clock / hz;
+
+ writel(data, ®->cfg);
+
+ return 0;
+}
+
+static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct spi_reg *reg = plat->spireg;
+
+ /*
+ * Set SPI polarity
+ * 0: Serial interface clock is low when inactive
+ * 1: Serial interface clock is high when inactive
+ */
+ if (mode & SPI_CPOL)
+ setbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_POL);
+ else
+ clrbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_POL);
+ if (mode & SPI_CPHA)
+ setbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_PHA);
+ else
+ clrbits_le32(®->cfg, MVEBU_SPI_A3700_CLK_PHA);
+
+ return 0;
+}
+
+static int mvebu_spi_probe(struct udevice *bus)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct spi_reg *reg = plat->spireg;
+ u32 data;
+ int ret;
+
+ /*
+ * Settings SPI controller to be working in legacy mode, which
+ * means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0)
+ * for Data In.
+ */
+
+ /* Flush read/write FIFO */
+ data = readl(®->cfg);
+ writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, ®->cfg);
+ ret = wait_for_bit(__func__, ®->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
+ false, 1000, false);
+ if (ret)
+ return ret;
+
+ /* Disable FIFO mode */
+ data &= ~MVEBU_SPI_A3700_FIFO_EN;
+
+ /* Always shift 1 byte at a time */
+ data &= ~MVEBU_SPI_A3700_BYTE_LEN;
+
+ writel(data, ®->cfg);
+
+ return 0;
+}
+
+static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+ plat->spireg = (struct spi_reg *)dev_get_addr(bus);
+
+ /*
+ * FIXME
+ * Right now, mvebu does not have a clock infrastructure in U-Boot
+ * which should be used to query the input clock to the SPI
+ * controller. Once this clock driver is integrated into U-Boot
+ * it should be used to read the input clock and the DT property
+ * can be removed.
+ */
+ plat->clock = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "clock-frequency", 160000);
+ plat->frequency = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "spi-max-frequency", 40000);
+
+ return 0;
+}
+
+static const struct dm_spi_ops mvebu_spi_ops = {
+ .xfer = mvebu_spi_xfer,
+ .set_speed = mvebu_spi_set_speed,
+ .set_mode = mvebu_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id mvebu_spi_ids[] = {
+ { .compatible = "marvell,armada-3700-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mvebu_spi) = {
+ .name = "mvebu_spi",
+ .id = UCLASS_SPI,
+ .of_match = mvebu_spi_ids,
+ .ops = &mvebu_spi_ops,
+ .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
+ .probe = mvebu_spi_probe,
+};
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 0881599..fc2786e 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <malloc.h>
#include <spi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 627644b..61daeba 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -14,7 +14,7 @@
#include <malloc.h>
#include <memalign.h>
#include <spi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index bc6dfd8..15cf0bd 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -12,9 +12,10 @@
#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <dt-structs.h>
#include <errno.h>
#include <spi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
@@ -27,6 +28,9 @@
#define DEBUG_RK_SPI 0
struct rockchip_spi_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_rockchip_rk3288_spi of_plat;
+#endif
s32 frequency; /* Default clock frequency, -1 for none */
fdt_addr_t base;
uint deactivate_delay_us; /* Delay to wait after deactivate */
@@ -106,6 +110,14 @@
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
+ /* If it's too soon to do another transaction, wait */
+ if (plat->deactivate_delay_us && priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < plat->deactivate_delay_us)
+ udelay(plat->deactivate_delay_us - delay_us);
+ }
+
debug("activate cs%u\n", cs);
writel(1 << cs, ®s->ser);
if (plat->activate_delay_us)
@@ -127,9 +139,29 @@
priv->last_transaction_us = timer_get_us();
}
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
+{
+ struct rockchip_spi_platdata *plat = dev->platdata;
+ struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
+ struct rockchip_spi_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ plat->base = dtplat->reg[0];
+ plat->frequency = 20000000;
+ ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
+ if (ret < 0)
+ return ret;
+ dev->req_seq = 0;
+
+ return 0;
+}
+#endif
+
static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
{
- struct rockchip_spi_platdata *plat = bus->platdata;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
@@ -153,6 +185,7 @@
debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
__func__, (uint)plat->base, plat->frequency,
plat->deactivate_delay_us);
+#endif
return 0;
}
@@ -164,6 +197,11 @@
int ret;
debug("%s: probe\n", __func__);
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ ret = conv_of_platdata(bus);
+ if (ret)
+ return ret;
+#endif
priv->regs = (struct rockchip_spi *)plat->base;
priv->last_transaction_us = timer_get_us();
@@ -369,7 +407,11 @@
};
U_BOOT_DRIVER(rockchip_spi) = {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ .name = "rockchip_rk3288_spi",
+#else
.name = "rockchip_spi",
+#endif
.id = UCLASS_SPI,
.of_match = rockchip_spi_ids,
.ops = &rockchip_spi_ops,
diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c
index bad5660..092b13b 100644
--- a/drivers/spi/sandbox_spi.c
+++ b/drivers/spi/sandbox_spi.c
@@ -15,7 +15,7 @@
#include <spi_flash.h>
#include <os.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/spi.h>
#include <asm/state.h>
#include <dm/device-internal.h>
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 247abfa..1ab5b75 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -108,6 +108,7 @@
return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
}
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static int spi_child_post_bind(struct udevice *dev)
{
struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
@@ -117,14 +118,16 @@
return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
}
+#endif
static int spi_post_probe(struct udevice *bus)
{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
"spi-max-frequency", 0);
-
+#endif
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
@@ -164,7 +167,6 @@
slave->max_hz = plat->max_hz;
slave->mode = plat->mode;
- slave->mode_rx = plat->mode_rx;
slave->wordlen = SPI_DEFAULT_WORDLEN;
return 0;
@@ -275,7 +277,11 @@
bool created = false;
int ret;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ ret = uclass_first_device_err(UCLASS_SPI, &bus);
+#else
ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus);
+#endif
if (ret) {
printf("Invalid bus %d (err=%d)\n", busnum, ret);
return ret;
@@ -291,8 +297,11 @@
debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n",
__func__, dev_name, busnum, cs, drv_name);
ret = device_bind_driver(bus, drv_name, dev_name, &dev);
- if (ret)
+ if (ret) {
+ debug("%s: Unable to bind driver (ret=%d)\n", __func__,
+ ret);
return ret;
+ }
plat = dev_get_parent_platdata(dev);
plat->cs = cs;
plat->max_hz = speed;
@@ -381,7 +390,7 @@
int spi_slave_ofdata_to_platdata(const void *blob, int node,
struct dm_spi_slave_platdata *plat)
{
- int mode = 0, mode_rx = 0;
+ int mode = 0;
int value;
plat->cs = fdtdec_get_int(blob, node, "reg", -1);
@@ -409,28 +418,26 @@
mode |= SPI_TX_QUAD;
break;
default:
- error("spi-tx-bus-width %d not supported\n", value);
+ warn_non_spl("spi-tx-bus-width %d not supported\n", value);
break;
}
- plat->mode = mode;
-
value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
switch (value) {
case 1:
break;
case 2:
- mode_rx |= SPI_RX_DUAL;
+ mode |= SPI_RX_DUAL;
break;
case 4:
- mode_rx |= SPI_RX_QUAD;
+ mode |= SPI_RX_QUAD;
break;
default:
- error("spi-rx-bus-width %d not supported\n", value);
+ warn_non_spl("spi-rx-bus-width %d not supported\n", value);
break;
}
- plat->mode_rx = mode_rx;
+ plat->mode = mode;
return 0;
}
@@ -439,14 +446,18 @@
.id = UCLASS_SPI,
.name = "spi",
.flags = DM_UC_FLAG_SEQ_ALIAS,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.post_bind = dm_scan_fdt_dev,
+#endif
.post_probe = spi_post_probe,
.child_pre_probe = spi_child_pre_probe,
.per_device_auto_alloc_size = sizeof(struct dm_spi_bus),
.per_child_auto_alloc_size = sizeof(struct spi_slave),
.per_child_platdata_auto_alloc_size =
sizeof(struct dm_spi_slave_platdata),
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.child_post_bind = spi_child_post_bind,
+#endif
};
UCLASS_DRIVER(spi_generic) = {
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index bb72cb0..6f9f983 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -16,6 +16,7 @@
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -23,6 +24,9 @@
#define QSPI_TIMEOUT 2000000
#define QSPI_FCLK 192000000
#define QSPI_DRA7XX_FCLK 76800000
+#define QSPI_WLEN_MAX_BITS 128
+#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
+#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
/* clock control */
#define QSPI_CLK_EN BIT(31)
#define QSPI_CLK_DIV_MAX 0xffff
@@ -115,21 +119,18 @@
if (!hz)
clk_div = 0;
else
- clk_div = (priv->fclk / hz) - 1;
+ clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
+
+ /* truncate clk_div value to QSPI_CLK_DIV_MAX */
+ if (clk_div > QSPI_CLK_DIV_MAX)
+ clk_div = QSPI_CLK_DIV_MAX;
debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
/* disable SCLK */
writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
&priv->base->clk_ctrl);
-
- /* assign clk_div values */
- if (clk_div < 0)
- clk_div = 0;
- else if (clk_div > QSPI_CLK_DIV_MAX)
- clk_div = QSPI_CLK_DIV_MAX;
-
- /* enable SCLK */
+ /* enable SCLK and program the clk divider */
writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
}
@@ -223,20 +224,34 @@
priv->cmd |= QSPI_3_PIN;
priv->cmd |= 0xfff;
-/* FIXME: This delay is required for successfull
- * completion of read/write/erase. Once its root
- * caused, it will be remove from the driver.
- */
-#ifdef CONFIG_AM43XX
- udelay(100);
-#endif
- while (words--) {
+ while (words) {
+ u8 xfer_len = 0;
+
if (txp) {
- debug("tx cmd %08x dc %08x data %02x\n",
- priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
- writel(*txp++, &priv->base->data);
- writel(priv->cmd | QSPI_WR_SNGL,
- &priv->base->cmd);
+ u32 cmd = priv->cmd;
+
+ if (words >= QSPI_WLEN_MAX_BYTES) {
+ u32 *txbuf = (u32 *)txp;
+ u32 data;
+
+ data = cpu_to_be32(*txbuf++);
+ writel(data, &priv->base->data3);
+ data = cpu_to_be32(*txbuf++);
+ writel(data, &priv->base->data2);
+ data = cpu_to_be32(*txbuf++);
+ writel(data, &priv->base->data1);
+ data = cpu_to_be32(*txbuf++);
+ writel(data, &priv->base->data);
+ cmd &= ~QSPI_WLEN_MASK;
+ cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
+ xfer_len = QSPI_WLEN_MAX_BYTES;
+ } else {
+ writeb(*txp, &priv->base->data);
+ xfer_len = 1;
+ }
+ debug("tx cmd %08x dc %08x\n",
+ cmd | QSPI_WR_SNGL, priv->dc);
+ writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
@@ -246,6 +261,7 @@
}
status = readl(&priv->base->status);
}
+ txp += xfer_len;
debug("tx done, status %08x\n", status);
}
if (rxp) {
@@ -262,9 +278,11 @@
status = readl(&priv->base->status);
}
*rxp++ = readl(&priv->base->data);
+ xfer_len = 1;
debug("rx done, status %08x, read %02x\n",
status, *(rxp-1));
}
+ words -= xfer_len;
}
/* Terminate frame */
@@ -336,7 +354,7 @@
QSPI_SETUP0_NUM_D_BYTES_8_BITS |
QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
QSPI_NUM_DUMMY_BITS);
- slave->mode_rx = SPI_RX_QUAD;
+ slave->mode |= SPI_RX_QUAD;
#else
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
@@ -365,7 +383,7 @@
priv->base = (struct ti_qspi_regs *)QSPI_BASE;
priv->mode = mode;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
priv->fclk = QSPI_DRA7XX_FCLK;
@@ -422,7 +440,7 @@
bool enable)
{
u32 memval;
- u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
+ u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
if (!enable) {
writel(0, &priv->base->setup0);
@@ -436,7 +454,7 @@
memval |= QSPI_CMD_READ_QUAD;
memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
memval |= QSPI_SETUP0_READ_QUAD;
- slave->mode_rx = SPI_RX_QUAD;
+ slave->mode |= SPI_RX_QUAD;
break;
case SPI_RX_DUAL:
memval |= QSPI_CMD_READ_DUAL;
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 09ae1be..15ca271 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -92,7 +92,8 @@
u32 confr;
/* Disable SPI */
- writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
+ confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
+ writel(~confr, ®s->enr);
/* Disable Interrupts */
writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr);
@@ -173,8 +174,10 @@
struct udevice *bus = dev->parent;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
+ u32 confr;
- writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
+ confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
+ writel(~confr, ®s->enr);
return 0;
}
@@ -230,7 +233,7 @@
/* Read the data from RX FIFO */
status = readl(®s->isr);
- while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
+ while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
buf = readl(®s->rxdr);
if (rx_buf)
*rx_buf++ = buf;
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 8e22ea7..886f5fa 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -5,3 +5,16 @@
temperature sensors to permit warnings, speed throttling or even
automatic power-off when the temperature gets too high or low. Other
devices may be discrete but connected on a suitable bus.
+
+if DM_THERMAL
+
+config IMX_THERMAL
+ bool "Temperature sensor driver for Freescale i.MX SoCs"
+ depends on MX6 || MX7
+ help
+ Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs.
+ It supports one critical trip point and one passive trip point. The
+ cpufreq is used as the cooling device to throttle CPUs when the
+ passive trip is crossed.
+
+endif # if DM_THERMAL
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index f8ddf93..5c63e6b 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <dm/lists.h>
#include <dm/device-internal.h>
+#include <clk.h>
#include <errno.h>
#include <timer.h>
@@ -42,9 +43,19 @@
static int timer_pre_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct clk timer_clk;
+ int err;
+ ulong ret;
- uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "clock-frequency", 0);
+ err = clk_get_by_index(dev, 0, &timer_clk);
+ if (!err) {
+ ret = clk_get_rate(&timer_clk);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ uc_priv->clock_rate = ret;
+ } else
+ uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob,
+ dev->of_offset, "clock-frequency", 0);
return 0;
}
diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c
index a4b6741..ef3ff0d 100644
--- a/drivers/tpm/tpm_tis_infineon.c
+++ b/drivers/tpm/tpm_tis_infineon.c
@@ -25,7 +25,7 @@
#include <fdtdec.h>
#include <i2c.h>
#include <tpm.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/unaligned/be_byteshift.h>
diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c
index 257d035..d2b3783 100644
--- a/drivers/tpm/tpm_tis_lpc.c
+++ b/drivers/tpm/tpm_tis_lpc.c
@@ -21,6 +21,21 @@
#define PREFIX "lpc_tpm: "
+enum i2c_chip_type {
+ SLB9635,
+ AT97SC3204,
+};
+
+static const char * const chip_name[] = {
+ [SLB9635] = "Infineon SLB9635 TT 1.2",
+ [AT97SC3204] = "Atmel AT97SC3204",
+};
+
+static const u32 chip_didvid[] = {
+ [SLB9635] = 0xb15d1,
+ [AT97SC3204] = 0x32041114,
+};
+
struct tpm_locality {
u32 access;
u8 padding0[4];
@@ -146,9 +161,9 @@
static int tpm_tis_lpc_probe(struct udevice *dev)
{
struct tpm_tis_lpc_priv *priv = dev_get_priv(dev);
- u32 vid, did;
fdt_addr_t addr;
u32 didvid;
+ ulong chip_type = dev_get_driver_data(dev);
addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@@ -156,14 +171,15 @@
priv->regs = map_sysmem(addr, 0);
didvid = tpm_read_word(priv, &priv->regs[0].did_vid);
- vid = didvid & 0xffff;
- did = (didvid >> 16) & 0xffff;
- if (vid != 0x15d1 || did != 0xb) {
+ if (didvid != chip_didvid[chip_type]) {
+ u32 vid, did;
+ vid = didvid & 0xffff;
+ did = (didvid >> 16) & 0xffff;
debug("Invalid vendor/device ID %04x/%04x\n", vid, did);
- return -ENOSYS;
+ return -ENODEV;
}
- debug("Found TPM %s by %s\n", "SLB9635 TT 1.2", "Infineon");
+ debug("Found TPM: %s\n", chip_name[chip_type]);
return 0;
}
@@ -204,7 +220,7 @@
/* Wait till the device is ready to accept more data. */
while (!burst) {
if (max_cycles++ == MAX_DELAY_US) {
- printf("%s:%d failed to feed %d bytes of %d\n",
+ printf("%s:%d failed to feed %zd bytes of %zd\n",
__FILE__, __LINE__, len - offset, len);
return -ETIMEDOUT;
}
@@ -224,7 +240,7 @@
* changes to zero exactly after the last byte is fed into the
* FIFO.
*/
- count = min((u32)burst, len - offset - 1);
+ count = min((size_t)burst, len - offset - 1);
while (count--)
tpm_write_byte(priv, data[offset++],
®s[locality].data);
@@ -421,11 +437,13 @@
static int tpm_tis_get_desc(struct udevice *dev, char *buf, int size)
{
+ ulong chip_type = dev_get_driver_data(dev);
+
if (size < 50)
return -ENOSPC;
- return snprintf(buf, size, "1.2 TPM (vendor %s, chip %s)",
- "Infineon", "SLB9635 TT 1.2");
+ return snprintf(buf, size, "1.2 TPM (%s)",
+ chip_name[chip_type]);
}
@@ -438,7 +456,8 @@
};
static const struct udevice_id tpm_tis_lpc_ids[] = {
- { .compatible = "infineon,slb9635lpc" },
+ { .compatible = "infineon,slb9635lpc", .data = SLB9635 },
+ { .compatible = "atmel,at97sc3204", .data = AT97SC3204 },
{ }
};
diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
index 9c48852..63a24f7 100644
--- a/drivers/usb/common/fsl-dt-fixup.c
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -86,8 +86,9 @@
return node_offset;
}
-static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
- const char *controller_type, int start_offset)
+static int fsl_fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
+ const char *controller_type,
+ int start_offset)
{
int node_offset, err;
const char *node_type = NULL;
@@ -114,24 +115,24 @@
return node_offset;
}
-static int fdt_fixup_erratum(int *usb_erratum_off, void *blob,
- const char *controller_type, char *str,
- bool (*has_erratum)(void))
+static int fsl_fdt_fixup_erratum(int *usb_erratum_off, void *blob,
+ const char *controller_type, char *str,
+ bool (*has_erratum)(void))
{
char buf[32] = {0};
snprintf(buf, sizeof(buf), "fsl,usb-erratum-%s", str);
if (!has_erratum())
return -EINVAL;
- *usb_erratum_off = fdt_fixup_usb_erratum(blob, buf, controller_type,
- *usb_erratum_off);
+ *usb_erratum_off = fsl_fdt_fixup_usb_erratum(blob, buf, controller_type,
+ *usb_erratum_off);
if (*usb_erratum_off < 0)
return -ENOSPC;
debug("Adding USB erratum %s\n", str);
return 0;
}
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+void fsl_fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
static const char * const modes[] = { "host", "peripheral", "otg" };
static const char * const phys[] = { "ulpi", "utmi", "utmi_dual" };
@@ -198,29 +199,29 @@
if (usb_phy_off < 0)
return;
- ret = fdt_fixup_erratum(&usb_erratum_a006261_off, blob,
- CHIPIDEA_USB2, "a006261",
- has_erratum_a006261);
+ ret = fsl_fdt_fixup_erratum(&usb_erratum_a006261_off, blob,
+ CHIPIDEA_USB2, "a006261",
+ has_erratum_a006261);
if (ret == -ENOSPC)
return;
- ret = fdt_fixup_erratum(&usb_erratum_a007075_off, blob,
- CHIPIDEA_USB2, "a007075",
- has_erratum_a007075);
+ ret = fsl_fdt_fixup_erratum(&usb_erratum_a007075_off, blob,
+ CHIPIDEA_USB2, "a007075",
+ has_erratum_a007075);
if (ret == -ENOSPC)
return;
- ret = fdt_fixup_erratum(&usb_erratum_a007792_off, blob,
- CHIPIDEA_USB2, "a007792",
- has_erratum_a007792);
+ ret = fsl_fdt_fixup_erratum(&usb_erratum_a007792_off, blob,
+ CHIPIDEA_USB2, "a007792",
+ has_erratum_a007792);
if (ret == -ENOSPC)
return;
- ret = fdt_fixup_erratum(&usb_erratum_a005697_off, blob,
- CHIPIDEA_USB2, "a005697",
- has_erratum_a005697);
+ ret = fsl_fdt_fixup_erratum(&usb_erratum_a005697_off, blob,
+ CHIPIDEA_USB2, "a005697",
+ has_erratum_a005697);
if (ret == -ENOSPC)
return;
- ret = fdt_fixup_erratum(&usb_erratum_a008751_off, blob,
- SNPS_DWC3, "a008751",
- has_erratum_a008751);
+ ret = fsl_fdt_fixup_erratum(&usb_erratum_a008751_off, blob,
+ SNPS_DWC3, "a008751",
+ has_erratum_a008751);
if (ret == -ENOSPC)
return;
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 183bf2b..6069c93 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -53,7 +53,8 @@
case SVR_P2041:
case SVR_P2040:
return IS_SVR_REV(svr, 1, 0) ||
- IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+ IS_SVR_REV(svr, 1, 1) ||
+ IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
case SVR_P3041:
return IS_SVR_REV(svr, 1, 0) ||
IS_SVR_REV(svr, 1, 1) ||
@@ -63,16 +64,10 @@
case SVR_P5021:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T4240:
- case SVR_T4160:
- case SVR_T4080:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_T1040:
- return IS_SVR_REV(svr, 1, 0);
- case SVR_T2080:
- case SVR_T2081:
- return IS_SVR_REV(svr, 1, 0);
case SVR_P5040:
- return IS_SVR_REV(svr, 1, 0);
+ return IS_SVR_REV(svr, 1, 0) ||
+ IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
#endif
}
@@ -144,6 +139,10 @@
case SVR_9132:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
+#ifdef ONFIG_ARM64
+ case SVR_LS1012A:
+ return IS_SVR_REV(svr, 1, 0);
+#endif
}
return false;
}
@@ -190,4 +189,30 @@
return false;
}
+bool has_erratum_a010151(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+#ifdef CONFIG_ARM64
+ case SVR_LS2080A:
+ case SVR_LS2085A:
+ case SVR_LS1046A:
+ case SVR_LS1012A:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_LS1043A:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+#ifdef CONFIG_LS102XA
+ case SOC_VER_LS1020:
+ case SOC_VER_LS1021:
+ case SOC_VER_LS1022:
+ case SOC_VER_SLS1020:
+ return IS_SVR_REV(svr, 2, 0);
+#endif
+ }
+ return false;
+}
+
#endif
diff --git a/drivers/usb/dwc3/ti_usb_phy.c b/drivers/usb/dwc3/ti_usb_phy.c
index 4159e5a..218a8e5 100644
--- a/drivers/usb/dwc3/ti_usb_phy.c
+++ b/drivers/usb/dwc3/ti_usb_phy.c
@@ -193,7 +193,7 @@
val = readl(phy->usb2_phy_power);
if (on) {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
if (phy->index == 1)
val &= ~OMAP_CTRL_USB2_PHY_PD;
else
@@ -205,7 +205,7 @@
AM437X_CTRL_USB2_OTGSESSEND_EN);
#endif
} else {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
if (phy->index == 1)
val |= OMAP_CTRL_USB2_PHY_PD;
else
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index a610ae4..1c6e967 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -67,11 +67,8 @@
AX_MEDIUM_AC | AX_MEDIUM_RE)
/* AX88772 & AX88178 RX_CTL values */
-#define AX_RX_CTL_RH2M 0x0200 /* 32-bit aligned RX IP header */
-#define AX_RX_CTL_RH1M 0x0100 /* Enable RX header format type 1 */
-#define AX_RX_CTL_SO 0x0080
-#define AX_RX_CTL_AB 0x0008
-#define AX_RX_HEADER_DEFAULT (AX_RX_CTL_RH1M | AX_RX_CTL_RH2M)
+#define AX_RX_CTL_SO 0x0080
+#define AX_RX_CTL_AB 0x0008
#define AX_DEFAULT_RX_CTL \
(AX_RX_CTL_SO | AX_RX_CTL_AB)
@@ -98,8 +95,6 @@
#define FLAG_TYPE_AX88772B (1U << 2)
#define FLAG_EEPROM_MAC (1U << 3) /* initial mac address in eeprom */
-#define ASIX_USB_VENDOR_ID 0x0b95
-#define AX88772B_USB_PRODUCT_ID 0x772b
/* driver private */
struct asix_private {
@@ -431,15 +426,10 @@
int timeout = 0;
#define TIMEOUT_RESOLUTION 50 /* ms */
int link_detected;
- u32 ctl = AX_DEFAULT_RX_CTL;
debug("** %s()\n", __func__);
- if ((dev->pusb_dev->descriptor.idVendor == ASIX_USB_VENDOR_ID) &&
- (dev->pusb_dev->descriptor.idProduct == AX88772B_USB_PRODUCT_ID))
- ctl |= AX_RX_HEADER_DEFAULT;
-
- if (asix_write_rx_ctl(dev, ctl) < 0)
+ if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
goto out_err;
if (asix_write_hwaddr_common(dev, enetaddr) < 0)
@@ -572,12 +562,6 @@
return -1;
}
- if ((dev->pusb_dev->descriptor.idVendor ==
- ASIX_USB_VENDOR_ID) &&
- (dev->pusb_dev->descriptor.idProduct ==
- AX88772B_USB_PRODUCT_ID))
- buf_ptr += 2;
-
/* Notify net stack */
net_process_received_packet(buf_ptr + sizeof(packet_len),
packet_len);
@@ -819,11 +803,6 @@
}
*packetp = ptr + sizeof(packet_len);
-
- if ((ueth->pusb_dev->descriptor.idVendor == ASIX_USB_VENDOR_ID) &&
- (ueth->pusb_dev->descriptor.idProduct == AX88772B_USB_PRODUCT_ID))
- *packetp += 2;
-
return packet_len;
err:
diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
index 070aadf..ed441f3 100644
--- a/drivers/usb/eth/r8152.c
+++ b/drivers/usb/eth/r8152.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <memalign.h>
#include <usb.h>
#include <usb/lin_gadget_compat.h>
#include <linux/mii.h>
@@ -71,17 +72,25 @@
static
int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
{
- return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
- RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
- value, index, data, size, 500);
+ ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
+ int ret;
+
+ ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
+ RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
+ value, index, tmp, size, 500);
+ memcpy(data, tmp, size);
+ return ret;
}
static
int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
{
+ ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
+
+ memcpy(tmp, data, size);
return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
- value, index, data, size, 500);
+ value, index, tmp, size, 500);
}
int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
@@ -1216,7 +1225,8 @@
u32 opts1, opts2 = 0;
int err;
int actual_len;
- unsigned char msg[PKTSIZE + sizeof(struct tx_desc)];
+ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg,
+ PKTSIZE + sizeof(struct tx_desc));
struct tx_desc *tx_desc = (struct tx_desc *)msg;
debug("** %s(), len %d\n", __func__, length);
@@ -1257,7 +1267,7 @@
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
- static unsigned char recv_buf[RTL8152_AGG_BUF_SZ];
+ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ);
unsigned char *pkt_ptr;
int err;
int actual_len;
diff --git a/drivers/usb/eth/r8152_fw.c b/drivers/usb/eth/r8152_fw.c
index b6c8228..81c3754 100644
--- a/drivers/usb/eth/r8152_fw.c
+++ b/drivers/usb/eth/r8152_fw.c
@@ -871,10 +871,10 @@
} else if (tp->version == RTL_VER_04) {
r8153_pre_ram_code(tp, 0x7001);
- for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
- ocp_write_word(tp, MCU_TYPE_PLA,
- r8153_ram_code_bc[i],
- r8153_ram_code_bc[i+1]);
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_bc[i],
+ r8153_ram_code_bc[i+1]);
r8153_post_ram_code(tp);
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index 7d9abfd..d4c8ea4 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -519,9 +519,11 @@
debug("timeout waiting for PHY Reset\n");
return -ETIMEDOUT;
}
+#ifndef CONFIG_DM_ETH
if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
0)
priv->have_hwaddr = 1;
+#endif
if (!priv->have_hwaddr) {
puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
return -EADDRNOTAVAIL;
@@ -1022,6 +1024,19 @@
return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
}
+int smsc95xx_read_rom_hwaddr(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ int ret;
+
+ ret = smsc95xx_init_mac_address(pdata->enetaddr, udev);
+ if (ret)
+ memset(pdata->enetaddr, 0, 6);
+
+ return 0;
+}
+
static int smsc95xx_eth_probe(struct udevice *dev)
{
struct smsc95xx_private *priv = dev_get_priv(dev);
@@ -1037,6 +1052,7 @@
.free_pkt = smsc95xx_free_pkt,
.stop = smsc95xx_eth_stop,
.write_hwaddr = smsc95xx_write_hwaddr,
+ .read_rom_hwaddr = smsc95xx_read_rom_hwaddr,
};
U_BOOT_DRIVER(smsc95xx_eth) = {
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index c915c79..0fbbb7c 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -8,6 +8,11 @@
obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o
obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += g_dnl.o
+obj-$(CONFIG_SPL_DFU_SUPPORT) += f_dfu.o
+endif
+
# new USB gadget layer dependencies
ifdef CONFIG_USB_GADGET
obj-$(CONFIG_USB_GADGET_AT91) += at91_udc.o
@@ -17,12 +22,14 @@
obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
obj-$(CONFIG_CI_UDC) += ci_udc.o
+ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o
obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o
obj-$(CONFIG_USB_FUNCTION_DFU) += f_dfu.o
obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o
obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o
endif
+endif
ifdef CONFIG_USB_ETHER
obj-y += ether.o
obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 4070803..f5bc277 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -15,7 +15,7 @@
#undef PACKET_TRACE
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 1e23d09..ad31703 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -9,7 +9,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <linux/list.h>
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index d36bcf6..05c01ce 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -14,7 +14,7 @@
#include <net.h>
#include <malloc.h>
#include <asm/byteorder.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/unaligned.h>
#include <linux/types.h>
diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c
index 64284b0..525dc79 100644
--- a/drivers/usb/gadget/config.c
+++ b/drivers/usb/gadget/config.c
@@ -11,7 +11,7 @@
#include <common.h>
#include <asm/unaligned.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/list.h>
#include <linux/string.h>
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index 029927f..d72bfdf 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -19,7 +19,7 @@
*/
#undef DEBUG
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/list.h>
#include <malloc.h>
diff --git a/drivers/usb/gadget/dwc2_udc_otg_phy.c b/drivers/usb/gadget/dwc2_udc_otg_phy.c
index e0cbbc0..0c4620d 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_phy.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_phy.c
@@ -19,7 +19,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/list.h>
#include <malloc.h>
diff --git a/drivers/usb/gadget/dwc2_udc_otg_priv.h b/drivers/usb/gadget/dwc2_udc_otg_priv.h
index b2c1fc4..c40ecf8 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_priv.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_priv.h
@@ -8,7 +8,7 @@
#ifndef __DWC2_UDC_OTG_PRIV__
#define __DWC2_UDC_OTG_PRIV__
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/sizes.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index a53a6dc..6d6dbcb 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -13,7 +13,7 @@
#include <common.h>
#include <linux/usb/ch9.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/usb/gadget.h>
#include <asm/unaligned.h>
#include "gadget_chips.h"
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 9b06f02..289e5f1 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <console.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/usb/ch9.h>
#include <linux/usb/cdc.h>
@@ -24,6 +24,10 @@
#include "gadget_chips.h"
#include "rndis.h"
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
#define USB_NET_NAME "usb_ether"
#define atomic_read
@@ -76,7 +80,6 @@
/* Based on linux 2.6.27 version */
#define DRIVER_VERSION "May Day 2005"
-static const char shortname[] = "ether";
static const char driver_desc[] = DRIVER_DESC;
#define RX_EXTRA 20 /* guard against rx overflows */
@@ -101,6 +104,9 @@
struct usb_gadget *gadget;
struct usb_request *req; /* for control responses */
struct usb_request *stat_req; /* for cdc & rndis status */
+#ifdef CONFIG_DM_USB
+ struct udevice *usb_udev;
+#endif
u8 config;
struct usb_ep *in_ep, *out_ep, *status_ep;
@@ -134,9 +140,14 @@
*/
/*-------------------------------------------------------------------------*/
-static struct eth_dev l_ethdev;
-static struct eth_device l_netdev;
-static struct usb_gadget_driver eth_driver;
+struct ether_priv {
+ struct eth_dev ethdev;
+ struct eth_device netdev;
+ struct usb_gadget_driver eth_driver;
+};
+
+struct ether_priv eth_priv;
+struct ether_priv *l_priv = ð_priv;
/*-------------------------------------------------------------------------*/
@@ -1135,7 +1146,7 @@
event->bNotificationType, value);
if (event->bNotificationType ==
USB_CDC_NOTIFY_SPEED_CHANGE) {
- l_ethdev.network_started = 1;
+ dev->network_started = 1;
printf("USB network up!\n");
}
}
@@ -1323,7 +1334,7 @@
* that network is working. So we signalize it
* here.
*/
- l_ethdev.network_started = 1;
+ dev->network_started = 1;
debug("USB network up!\n");
goto done_set_intf;
}
@@ -1823,10 +1834,10 @@
debug("rndis control ack complete --> %d, %d/%d\n",
req->status, req->actual, req->length);
- if (!l_ethdev.network_started) {
+ if (!dev->network_started) {
if (rndis_get_state(dev->rndis_config)
== RNDIS_DATA_INITIALIZED) {
- l_ethdev.network_started = 1;
+ dev->network_started = 1;
printf("USB RNDIS network up!\n");
}
}
@@ -1841,7 +1852,8 @@
static int rndis_control_ack(struct eth_device *net)
{
- struct eth_dev *dev = &l_ethdev;
+ struct ether_priv *priv = (struct ether_priv *)net->priv;
+ struct eth_dev *dev = &priv->ethdev;
int length;
struct usb_request *resp = dev->stat_req;
@@ -1982,7 +1994,7 @@
static int eth_bind(struct usb_gadget *gadget)
{
- struct eth_dev *dev = &l_ethdev;
+ struct eth_dev *dev = &l_priv->ethdev;
u8 cdc = 1, zlp = 1, rndis = 1;
struct usb_ep *in_ep, *out_ep, *status_ep = NULL;
int status = -ENOMEM;
@@ -2175,7 +2187,7 @@
/* network device setup */
- dev->net = &l_netdev;
+ dev->net = &l_priv->netdev;
dev->cdc = cdc;
dev->zlp = zlp;
@@ -2303,19 +2315,39 @@
/*-------------------------------------------------------------------------*/
-static int usb_eth_init(struct eth_device *netdev, bd_t *bd)
+#ifdef CONFIG_DM_USB
+int dm_usb_init(struct eth_dev *e_dev)
{
- struct eth_dev *dev = &l_ethdev;
+ struct udevice *dev = NULL;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev);
+ if (!dev || ret) {
+ error("No USB device found\n");
+ return -ENODEV;
+ }
+
+ e_dev->usb_udev = dev;
+
+ return ret;
+}
+#endif
+
+static int _usb_eth_init(struct ether_priv *priv)
+{
+ struct eth_dev *dev = &priv->ethdev;
struct usb_gadget *gadget;
unsigned long ts;
unsigned long timeout = USB_CONNECT_TIMEOUT;
- if (!netdev) {
- error("received NULL ptr");
- goto fail;
+#ifdef CONFIG_DM_USB
+ if (dm_usb_init(dev)) {
+ error("USB ether not found\n");
+ return -ENODEV;
}
-
+#else
board_usb_init(0, USB_INIT_DEVICE);
+#endif
/* Configure default mac-addresses for the USB ethernet device */
#ifdef CONFIG_USBNET_DEV_ADDR
@@ -2342,7 +2374,15 @@
goto fail;
}
- if (usb_gadget_register_driver(ð_driver) < 0)
+ priv->eth_driver.speed = DEVSPEED;
+ priv->eth_driver.bind = eth_bind;
+ priv->eth_driver.unbind = eth_unbind;
+ priv->eth_driver.setup = eth_setup;
+ priv->eth_driver.reset = eth_disconnect;
+ priv->eth_driver.disconnect = eth_disconnect;
+ priv->eth_driver.suspend = eth_suspend;
+ priv->eth_driver.resume = eth_resume;
+ if (usb_gadget_register_driver(&priv->eth_driver) < 0)
goto fail;
dev->network_started = 0;
@@ -2357,7 +2397,7 @@
timeout = simple_strtoul(getenv("cdc_connect_timeout"),
NULL, 10) * CONFIG_SYS_HZ;
ts = get_timer(0);
- while (!l_ethdev.network_started) {
+ while (!dev->network_started) {
/* Handle control-c and timeouts */
if (ctrlc() || (get_timer(ts) > timeout)) {
error("The remote end did not respond in time.");
@@ -2373,11 +2413,11 @@
return -1;
}
-static int usb_eth_send(struct eth_device *netdev, void *packet, int length)
+static int _usb_eth_send(struct ether_priv *priv, void *packet, int length)
{
int retval;
void *rndis_pkt = NULL;
- struct eth_dev *dev = &l_ethdev;
+ struct eth_dev *dev = &priv->ethdev;
struct usb_request *req = dev->tx_req;
unsigned long ts;
unsigned long timeout = USB_CONNECT_TIMEOUT;
@@ -2442,34 +2482,16 @@
return -ENOMEM;
}
-static int usb_eth_recv(struct eth_device *netdev)
+static int _usb_eth_recv(struct ether_priv *priv)
{
- struct eth_dev *dev = &l_ethdev;
-
usb_gadget_handle_interrupts(0);
- if (packet_received) {
- debug("%s: packet received\n", __func__);
- if (dev->rx_req) {
- net_process_received_packet(net_rx_packets[0],
- dev->rx_req->length);
- packet_received = 0;
-
- rx_submit(dev, dev->rx_req, 0);
- } else
- error("dev->rx_req invalid");
- }
return 0;
}
-void usb_eth_halt(struct eth_device *netdev)
+void _usb_eth_halt(struct ether_priv *priv)
{
- struct eth_dev *dev = &l_ethdev;
-
- if (!netdev) {
- error("received NULL ptr");
- return;
- }
+ struct eth_dev *dev = &priv->ethdev;
/* If the gadget not registered, simple return */
if (!dev->gadget)
@@ -2496,27 +2518,65 @@
dev->network_started = 0;
}
- usb_gadget_unregister_driver(ð_driver);
+ usb_gadget_unregister_driver(&priv->eth_driver);
+#ifdef CONFIG_DM_USB
+ device_remove(dev->usb_udev);
+#else
board_usb_cleanup(0, USB_INIT_DEVICE);
+#endif
}
-static struct usb_gadget_driver eth_driver = {
- .speed = DEVSPEED,
+static int usb_eth_init(struct eth_device *netdev, bd_t *bd)
+{
+ struct ether_priv *priv = (struct ether_priv *)netdev->priv;
- .bind = eth_bind,
- .unbind = eth_unbind,
+ return _usb_eth_init(priv);
+}
- .setup = eth_setup,
- .reset = eth_disconnect,
- .disconnect = eth_disconnect,
+static int usb_eth_send(struct eth_device *netdev, void *packet, int length)
+{
+ struct ether_priv *priv = (struct ether_priv *)netdev->priv;
- .suspend = eth_suspend,
- .resume = eth_resume,
-};
+ return _usb_eth_send(priv, packet, length);
+}
+
+static int usb_eth_recv(struct eth_device *netdev)
+{
+ struct ether_priv *priv = (struct ether_priv *)netdev->priv;
+ struct eth_dev *dev = &priv->ethdev;
+ int ret;
+
+ ret = _usb_eth_recv(priv);
+ if (ret) {
+ error("error packet receive\n");
+ return ret;
+ }
+
+ if (!packet_received)
+ return 0;
+
+ if (dev->rx_req) {
+ net_process_received_packet(net_rx_packets[0],
+ dev->rx_req->length);
+ } else {
+ error("dev->rx_req invalid");
+ }
+ packet_received = 0;
+ rx_submit(dev, dev->rx_req, 0);
+
+ return 0;
+}
+
+void usb_eth_halt(struct eth_device *netdev)
+{
+ struct ether_priv *priv = (struct ether_priv *)netdev->priv;
+
+ _usb_eth_halt(priv);
+}
int usb_eth_initialize(bd_t *bi)
{
- struct eth_device *netdev = &l_netdev;
+ struct eth_device *netdev = &l_priv->netdev;
strlcpy(netdev->name, USB_NET_NAME, sizeof(netdev->name));
@@ -2524,6 +2584,7 @@
netdev->send = usb_eth_send;
netdev->recv = usb_eth_recv;
netdev->halt = usb_eth_halt;
+ netdev->priv = l_priv;
#ifdef CONFIG_MCAST_TFTP
#error not supported
diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c
index 1d8f58f..e061b2e 100644
--- a/drivers/usb/gadget/fotg210.c
+++ b/drivers/usb/gadget/fotg210.c
@@ -13,7 +13,7 @@
#include <net.h>
#include <malloc.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/types.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c
index 48463db..844a0c7 100644
--- a/drivers/usb/gadget/rndis.c
+++ b/drivers/usb/gadget/rndis.c
@@ -28,7 +28,7 @@
#include <asm/byteorder.h>
#include <asm/unaligned.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#undef RNDIS_PM
#undef RNDIS_WAKEUP
@@ -41,8 +41,6 @@
#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */
#define ETH_DATA_LEN 1500 /* Max. octets in payload */
#define ETH_FRAME_LEN PKTSIZE_ALIGN /* Max. octets in frame sans FCS */
-#define ENOTSUPP 524 /* Operation is not supported */
-
/*
* The driver for your USB chip needs to support ep0 OUT to work with
diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c
index 3e24fbf..67e98c0 100644
--- a/drivers/usb/gadget/usbstring.c
+++ b/drivers/usb/gadget/usbstring.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index e0699d4..b9c5fbe 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -15,19 +15,28 @@
if USB_XHCI_HCD
-config USB_XHCI_UNIPHIER
- bool "Support for UniPhier on-chip xHCI USB controller"
- depends on ARCH_UNIPHIER
- default y
- ---help---
- Enables support for the on-chip xHCI controller on UniPhier SoCs.
-
config USB_XHCI_DWC3
bool "DesignWare USB3 DRD Core Support"
help
Say Y or if your system has a Dual Role SuperSpeed
USB controller based on the DesignWare USB3 IP Core.
+config USB_XHCI_MVEBU
+ bool "MVEBU USB 3.0 support"
+ default y
+ depends on ARCH_MVEBU
+ help
+ Choose this option to add support for USB 3.0 driver on mvebu
+ SoCs, which includes Armada8K, Armada3700 and other Armada
+ family SoCs.
+
+config USB_XHCI_ROCKCHIP
+ bool "Support for Rockchip on-chip xHCI USB controller"
+ depends on ARCH_ROCKCHIP
+ default y
+ help
+ Enables support for the on-chip xHCI controller on Rockchip SoCs.
+
endif # USB_XHCI_HCD
config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 620d114..58c0cf5 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -56,13 +56,14 @@
# xhci
obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
+obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
+obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
-obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/ehci-armada100.c b/drivers/usb/host/ehci-armada100.c
index 012eb3a..237d287 100644
--- a/drivers/usb/host/ehci-armada100.c
+++ b/drivers/usb/host/ehci-armada100.c
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2012
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* This driver is based on Kirkwood echi driver
* (C) Copyright 2009
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index d65bbe9..a5c6d34 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -56,9 +56,7 @@
static int ehci_atmel_enable_clk(struct udevice *dev)
{
- struct udevice *dev_clk;
struct clk clk;
- int periph;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
@@ -73,19 +71,6 @@
if (ret)
return -EINVAL;
- periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1);
- if (periph < 0)
- return -EINVAL;
-
- dev_clk = dev_get_parent(clk.dev);
- if (!dev_clk)
- return -ENODEV;
-
- ret = clk_request(dev_clk, &clk);
- if (ret)
- return ret;
-
- clk.id = periph;
ret = clk_enable(&clk);
if (ret)
return ret;
@@ -128,17 +113,6 @@
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}
-static int ehci_atmel_remove(struct udevice *dev)
-{
- int ret;
-
- ret = ehci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "atmel,at91sam9g45-ehci", },
{ }
@@ -149,7 +123,7 @@
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
.probe = ehci_atmel_probe,
- .remove = ehci_atmel_remove,
+ .remove = ehci_deregister,
.ops = &ehci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
.priv_auto_alloc_size = sizeof(struct ehci_atmel_priv),
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index bede04b..53281d7 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -18,7 +18,7 @@
#include <asm/arch/system.h>
#include <asm/arch/power.h>
#include <asm/gpio.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <linux/compat.h>
#include "ehci.h"
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index f5e3ae7..9c32921 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -118,17 +118,6 @@
return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
}
-static int ehci_fsl_remove(struct udevice *dev)
-{
- int ret;
-
- ret = ehci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "fsl-usb2-mph", },
{ .compatible = "fsl-usb2-dr", },
@@ -141,7 +130,7 @@
.of_match = ehci_usb_ids,
.ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
.probe = ehci_fsl_probe,
- .remove = ehci_fsl_remove,
+ .remove = ehci_deregister,
.ops = &ehci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
.priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index e0377ca..2190adb 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <clk.h>
+#include <reset.h>
#include <asm/io.h>
#include <dm.h>
#include "ehci.h"
@@ -37,6 +38,18 @@
clk_free(&clk);
}
+ for (i = 0; ; i++) {
+ struct reset_ctl reset;
+ int ret;
+
+ ret = reset_get_by_index(dev, i, &reset);
+ if (ret < 0)
+ break;
+ if (reset_deassert(&reset))
+ printf("failed to deassert reset %d\n", i);
+ reset_free(&reset);
+ }
+
hccr = map_physmem(dev_get_addr(dev), 0x100, MAP_NOCACHE);
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
@@ -44,11 +57,6 @@
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}
-static int ehci_usb_remove(struct udevice *dev)
-{
- return ehci_deregister(dev);
-}
-
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "generic-ehci" },
{ }
@@ -59,7 +67,7 @@
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
.probe = ehci_usb_probe,
- .remove = ehci_usb_remove,
+ .remove = ehci_deregister,
.ops = &ehci_usb_ops,
.priv_auto_alloc_size = sizeof(struct generic_ehci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 5b0f46a..4642470 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -26,6 +26,16 @@
#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
#define USB_TARGET_DRAM 0x0
+#define USB2_SBUSCFG_OFF 0x90
+
+#define USB_SBUSCFG_BAWR_OFF 0x6
+#define USB_SBUSCFG_BARD_OFF 0x3
+#define USB_SBUSCFG_AHBBRST_OFF 0x0
+
+#define USB_SBUSCFG_BAWR_ALIGN_64B 0x4
+#define USB_SBUSCFG_BARD_ALIGN_64B 0x4
+#define USB_SBUSCFG_AHBBRST_INCR16 0x7
+
/*
* USB 2.0 Bridge Address Decoding registers setup
*/
@@ -41,7 +51,7 @@
* to the common mvebu archticture including the mbus setup, this
* will be the only function needed to configure the access windows
*/
-static void usb_brg_adrdec_setup(u32 base)
+static void usb_brg_adrdec_setup(void *base)
{
const struct mbus_dram_target_info *dram;
int i;
@@ -66,6 +76,29 @@
}
}
+static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
+ uint32_t *status_reg, uint32_t *reg)
+{
+ struct ehci_mvebu_priv *priv = ctrl->priv;
+
+ /*
+ * Set default value for reg SBUSCFG, which is Control for the AMBA
+ * system bus interface:
+ * BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes
+ * AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes
+ */
+ writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) |
+ (USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) |
+ (USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF),
+ priv->hcd_base + USB2_SBUSCFG_OFF);
+
+ mdelay(50);
+}
+
+static struct ehci_ops marvell_ehci_ops = {
+ .powerup_fixup = NULL,
+};
+
static int ehci_mvebu_probe(struct udevice *dev)
{
struct ehci_mvebu_priv *priv = dev_get_priv(dev);
@@ -81,32 +114,33 @@
return -ENXIO;
}
- usb_brg_adrdec_setup(priv->hcd_base);
+ /*
+ * For SoCs without hlock like Armada3700 we need to program the sbuscfg
+ * reg to guarantee AHB master's burst will not overrun or underrun
+ * the FIFO. Otherwise all USB2 write option will fail.
+ * Also, the address decoder doesn't need to get setup with this
+ * SoC, so don't call usb_brg_adrdec_setup().
+ */
+ if (of_device_is_compatible(dev, "marvell,armada3700-ehci"))
+ marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
+ else
+ usb_brg_adrdec_setup((void *)priv->hcd_base);
hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
hcor = (struct ehci_hcor *)
- ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
- (u32)hccr, (u32)hcor,
- (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
+ (uintptr_t)hccr, (uintptr_t)hcor,
+ (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
-}
-
-static int ehci_mvebu_remove(struct udevice *dev)
-{
- int ret;
-
- ret = ehci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
+ return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
+ USB_INIT_HOST);
}
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "marvell,orion-ehci", },
+ { .compatible = "marvell,armada3700-ehci", },
{ }
};
@@ -115,7 +149,7 @@
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
.probe = ehci_mvebu_probe,
- .remove = ehci_mvebu_remove,
+ .remove = ehci_deregister,
.ops = &ehci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
.priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv),
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 602fec5..48889c1 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -451,17 +451,6 @@
return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
}
-static int ehci_usb_remove(struct udevice *dev)
-{
- int ret;
-
- ret = ehci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static const struct udevice_id mx6_usb_ids[] = {
{ .compatible = "fsl,imx27-usb" },
{ }
@@ -472,7 +461,7 @@
.id = UCLASS_USB,
.of_match = mx6_usb_ids,
.probe = ehci_usb_probe,
- .remove = ehci_usb_remove,
+ .remove = ehci_deregister,
.ops = &ehci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
.priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index f21a1fa..f20fc33 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -32,8 +32,8 @@
hcor = (struct ehci_hcor *)((uintptr_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
- (u32)hccr, (u32)hcor,
+ debug("EHCI-PCI init hccr %#lx and hcor %#lx hc_length %d\n",
+ (ulong)hccr, (ulong)hcor,
(u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
*ret_hccr = hccr;
@@ -126,17 +126,6 @@
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}
-static int ehci_pci_remove(struct udevice *dev)
-{
- int ret;
-
- ret = ehci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static const struct udevice_id ehci_pci_ids[] = {
{ .compatible = "ehci-pci" },
{ }
@@ -146,7 +135,7 @@
.name = "ehci_pci",
.id = UCLASS_USB,
.probe = ehci_pci_probe,
- .remove = ehci_pci_remove,
+ .remove = ehci_deregister,
.of_match = ehci_pci_ids,
.ops = &ehci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index f2d83e3..5bb97ff 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -45,10 +45,10 @@
* clocks resp. phys.
*/
priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
-#ifdef CONFIG_MACH_SUN8I_H3
+#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
#endif
- priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
+ priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
priv->phy_index++; /* Non otg phys start at 1 */
@@ -63,7 +63,7 @@
sunxi_usb_phy_init(priv->phy_index);
sunxi_usb_phy_power_on(priv->phy_index);
- hcor = (struct ehci_hcor *)((uint32_t)hccr +
+ hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type);
@@ -98,6 +98,7 @@
{ .compatible = "allwinner,sun8i-a83t-ehci", },
{ .compatible = "allwinner,sun8i-h3-ehci", },
{ .compatible = "allwinner,sun9i-a80-ehci", },
+ { .compatible = "allwinner,sun50i-a64-ehci", },
{ }
};
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 31d54ab..e3620da 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <dm.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <asm/arch/clock.h>
@@ -600,9 +600,18 @@
/* reset ULPI phy */
if (dm_gpio_is_valid(&config->phy_reset_gpio)) {
- dm_gpio_set_value(&config->phy_reset_gpio, 0);
- mdelay(5);
+ /*
+ * This GPIO is typically active-low, and marked as such in
+ * device tree. dm_gpio_set_value() takes this into account
+ * and inverts the value we pass here if required. In other
+ * words, this first call logically asserts the reset signal,
+ * which typically results in driving the physical GPIO low,
+ * and the second call logically de-asserts the reset signal,
+ * which typically results in driver the GPIO high.
+ */
dm_gpio_set_value(&config->phy_reset_gpio, 1);
+ mdelay(5);
+ dm_gpio_set_value(&config->phy_reset_gpio, 0);
}
/* Reset the usb controller */
@@ -846,17 +855,6 @@
plat->init_type);
}
-static int ehci_usb_remove(struct udevice *dev)
-{
- int ret;
-
- ret = ehci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
{ .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
@@ -871,7 +869,7 @@
.of_match = ehci_usb_ids,
.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
.probe = ehci_usb_probe,
- .remove = ehci_usb_remove,
+ .remove = ehci_deregister,
.ops = &ehci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
.priv_auto_alloc_size = sizeof(struct fdt_usb),
diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c
index 61789dd..f389bff 100644
--- a/drivers/usb/host/ehci-vf.c
+++ b/drivers/usb/host/ehci-vf.c
@@ -8,16 +8,20 @@
*/
#include <common.h>
+#include <dm.h>
#include <usb.h>
#include <errno.h>
#include <linux/compiler.h>
#include <asm/io.h>
+#include <asm-generic/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/regs-usbphy.h>
#include <usb/ehci-ci.h>
+#include <libfdt.h>
+#include <fdtdec.h>
#include "ehci.h"
@@ -32,6 +36,8 @@
#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
+DECLARE_GLOBAL_DATA_PTR;
+
static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
USB_PHY1_BASE_ADDR,
@@ -131,24 +137,39 @@
return 0;
}
+int ehci_vf_common_init(struct usb_ehci *ehci, int index)
+{
+ int ret;
+
+ /* Do board specific initialisation */
+ ret = board_ehci_hcd_init(index);
+ if (ret)
+ return ret;
+
+ usb_power_config(index);
+ usb_oc_config(index);
+ usb_internal_phy_clock_gate(index);
+ usb_phy_enable(index, ehci);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_USB
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
enum usb_init_type type;
+ int ret;
if (index >= ARRAY_SIZE(nc_reg_bases))
return -EINVAL;
ehci = (struct usb_ehci *)nc_reg_bases[index];
- /* Do board specific initialisation */
- board_ehci_hcd_init(index);
-
- usb_power_config(index);
- usb_oc_config(index);
- usb_internal_phy_clock_gate(index);
- usb_phy_enable(index, ehci);
+ ret = ehci_vf_common_init(index);
+ if (ret)
+ return ret;
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
@@ -175,3 +196,165 @@
{
return 0;
}
+#else
+/* Possible port types (dual role mode) */
+enum dr_mode {
+ DR_MODE_NONE = 0,
+ DR_MODE_HOST, /* supports host operation */
+ DR_MODE_DEVICE, /* supports device operation */
+ DR_MODE_OTG, /* supports both */
+};
+
+struct ehci_vf_priv_data {
+ struct ehci_ctrl ctrl;
+ struct usb_ehci *ehci;
+ struct gpio_desc cdet_gpio;
+ enum usb_init_type init_type;
+ enum dr_mode dr_mode;
+ u32 portnr;
+};
+
+static int vf_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ehci_vf_priv_data *priv = dev_get_priv(dev);
+ const void *dt_blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ const char *mode;
+
+ priv->portnr = dev->seq;
+
+ priv->ehci = (struct usb_ehci *)dev_get_addr(dev);
+ mode = fdt_getprop(dt_blob, node, "dr_mode", NULL);
+ if (mode) {
+ if (0 == strcmp(mode, "host")) {
+ priv->dr_mode = DR_MODE_HOST;
+ priv->init_type = USB_INIT_HOST;
+ } else if (0 == strcmp(mode, "peripheral")) {
+ priv->dr_mode = DR_MODE_DEVICE;
+ priv->init_type = USB_INIT_DEVICE;
+ } else if (0 == strcmp(mode, "otg")) {
+ priv->dr_mode = DR_MODE_OTG;
+ /*
+ * We set init_type to device by default when OTG
+ * mode is requested. If a valid gpio is provided
+ * we will switch the init_type based on the state
+ * of the gpio pin.
+ */
+ priv->init_type = USB_INIT_DEVICE;
+ } else {
+ debug("%s: Cannot decode dr_mode '%s'\n",
+ __func__, mode);
+ return -EINVAL;
+ }
+ } else {
+ priv->dr_mode = DR_MODE_HOST;
+ priv->init_type = USB_INIT_HOST;
+ }
+
+ if (priv->dr_mode == DR_MODE_OTG) {
+ gpio_request_by_name_nodev(dt_blob, node, "fsl,cdet-gpio", 0,
+ &priv->cdet_gpio, GPIOD_IS_IN);
+ if (dm_gpio_is_valid(&priv->cdet_gpio)) {
+ if (dm_gpio_get_value(&priv->cdet_gpio))
+ priv->init_type = USB_INIT_DEVICE;
+ else
+ priv->init_type = USB_INIT_HOST;
+ }
+ }
+
+ return 0;
+}
+
+static int vf_init_after_reset(struct ehci_ctrl *dev)
+{
+ struct ehci_vf_priv_data *priv = dev->priv;
+ enum usb_init_type type = priv->init_type;
+ struct usb_ehci *ehci = priv->ehci;
+ int ret;
+
+ ret = ehci_vf_common_init(priv->ehci, priv->portnr);
+ if (ret)
+ return ret;
+
+ if (type == USB_INIT_DEVICE)
+ return 0;
+
+ setbits_le32(&ehci->usbmode, CM_HOST);
+ writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+
+ mdelay(10);
+
+ return 0;
+}
+
+static const struct ehci_ops vf_ehci_ops = {
+ .init_after_reset = vf_init_after_reset
+};
+
+static int vf_usb_bind(struct udevice *dev)
+{
+ static int num_controllers;
+
+ /*
+ * Without this hack, if we return ENODEV for USB Controller 0, on
+ * probe for the next controller, USB Controller 1 will be given a
+ * sequence number of 0. This conflicts with our requirement of
+ * sequence numbers while initialising the peripherals.
+ */
+ dev->req_seq = num_controllers;
+ num_controllers++;
+
+ return 0;
+}
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ struct ehci_vf_priv_data *priv = dev_get_priv(dev);
+ struct usb_ehci *ehci = priv->ehci;
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ int ret;
+
+ ret = ehci_vf_common_init(ehci, priv->portnr);
+ if (ret)
+ return ret;
+
+ if (priv->init_type != plat->init_type)
+ return -ENODEV;
+
+ if (priv->init_type == USB_INIT_HOST) {
+ setbits_le32(&ehci->usbmode, CM_HOST);
+ writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+ }
+
+ mdelay(10);
+
+ hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ hcor = (struct ehci_hcor *)((uint32_t)hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ return ehci_register(dev, hccr, hcor, &vf_ehci_ops, 0, priv->init_type);
+}
+
+static const struct udevice_id vf_usb_ids[] = {
+ { .compatible = "fsl,vf610-usb" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_ehci) = {
+ .name = "ehci_vf",
+ .id = UCLASS_USB,
+ .of_match = vf_usb_ids,
+ .bind = vf_usb_bind,
+ .probe = ehci_usb_probe,
+ .remove = ehci_deregister,
+ .ops = &ehci_usb_ops,
+ .ofdata_to_platdata = vf_usb_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct ehci_vf_priv_data),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c
index 76642cd..1e3b800 100644
--- a/drivers/usb/host/ehci-zynq.c
+++ b/drivers/usb/host/ehci-zynq.c
@@ -73,17 +73,6 @@
return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type);
}
-static int ehci_zynq_remove(struct udevice *dev)
-{
- int ret;
-
- ret = ehci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static const struct udevice_id ehci_zynq_ids[] = {
{ .compatible = "xlnx,zynq-usb-2.20a" },
{ }
@@ -95,7 +84,7 @@
.of_match = ehci_zynq_ids,
.ofdata_to_platdata = ehci_zynq_ofdata_to_platdata,
.probe = ehci_zynq_probe,
- .remove = ehci_zynq_remove,
+ .remove = ehci_deregister,
.ops = &ehci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
.priv_auto_alloc_size = sizeof(struct zynq_ehci_priv),
diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c
index 0556f32..32874d7 100644
--- a/drivers/usb/host/isp116x-hcd.c
+++ b/drivers/usb/host/isp116x-hcd.c
@@ -428,10 +428,10 @@
isp116x_write_reg16(isp116x, HCuPINTENB, 0);
irqstat = isp116x_read_reg16(isp116x, HCuPINT);
isp116x_write_reg16(isp116x, HCuPINT, irqstat);
- DBG(">>>>>> irqstat %x <<<<<<", irqstat);
+ DBG("------ irqstat %x ------", irqstat);
if (irqstat & HCuPINT_ATL) {
- DBG(">>>>>> HCuPINT_ATL <<<<<<");
+ DBG("------ HCuPINT_ATL ------");
udelay(500);
ret = 1;
}
@@ -439,7 +439,7 @@
if (irqstat & HCuPINT_OPR) {
intstat = isp116x_read_reg32(isp116x, HCINTSTAT);
isp116x_write_reg32(isp116x, HCINTSTAT, intstat);
- DBG(">>>>>> HCuPINT_OPR %x <<<<<<", intstat);
+ DBG("------ HCuPINT_OPR %x ------", intstat);
if (intstat & HCINT_UE) {
ERR("unrecoverable error, controller disabled");
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index ccbfc02..80cfe11 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -682,7 +682,7 @@
ed->hwNextED = 0;
flush_dcache_ed(ed);
if (ohci->ed_controltail == NULL)
- ohci_writel(ed, &ohci->regs->ed_controlhead);
+ ohci_writel((uintptr_t)ed, &ohci->regs->ed_controlhead);
else
ohci->ed_controltail->hwNextED =
m32_swap((unsigned long)ed);
@@ -700,7 +700,7 @@
ed->hwNextED = 0;
flush_dcache_ed(ed);
if (ohci->ed_bulktail == NULL)
- ohci_writel(ed, &ohci->regs->ed_bulkhead);
+ ohci_writel((uintptr_t)ed, &ohci->regs->ed_bulkhead);
else
ohci->ed_bulktail->hwNextED =
m32_swap((unsigned long)ed);
@@ -753,7 +753,7 @@
/* ED might have been unlinked through another path */
while (*ed_p != 0) {
- if (((struct ed *)
+ if (((struct ed *)(uintptr_t)
m32_swap((unsigned long)ed_p)) == ed) {
*ed_p = ed->hwNextED;
aligned_ed_p = (unsigned long)ed_p;
@@ -762,7 +762,7 @@
aligned_ed_p + ARCH_DMA_MINALIGN);
break;
}
- ed_p = &(((struct ed *)
+ ed_p = &(((struct ed *)(uintptr_t)
m32_swap((unsigned long)ed_p))->hwNextED);
}
}
@@ -798,7 +798,7 @@
if (ohci->ed_controltail == ed) {
ohci->ed_controltail = ed->ed_prev;
} else {
- ((ed_t *)m32_swap(
+ ((ed_t *)(uintptr_t)m32_swap(
*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
}
break;
@@ -819,7 +819,7 @@
if (ohci->ed_bulktail == ed) {
ohci->ed_bulktail = ed->ed_prev;
} else {
- ((ed_t *)m32_swap(
+ ((ed_t *)(uintptr_t)m32_swap(
*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
}
break;
@@ -914,12 +914,13 @@
/* fill the old dummy TD */
td = urb_priv->td [index] =
- (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf);
+ (td_t *)(uintptr_t)
+ (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
td->ed = urb_priv->ed;
td->next_dl_td = NULL;
td->index = index;
- td->data = (__u32)data;
+ td->data = (uintptr_t)data;
#ifdef OHCI_FILL_TRACE
if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
for (i = 0; i < len; i++)
@@ -963,7 +964,7 @@
flush_dcache_buffer(buffer, data_len);
/* OHCI handles the DATA-toggles itself, we just use the USB-toggle
- * bits for reseting */
+ * bits for resetting */
if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
toggle = TD_T_TOGGLE;
} else {
@@ -1099,7 +1100,7 @@
* we reverse the reversed done-list */
static td_t *dl_reverse_done_list(ohci_t *ohci)
{
- __u32 td_list_hc;
+ uintptr_t td_list_hc;
td_t *td_rev = NULL;
td_t *td_list = NULL;
@@ -1862,7 +1863,7 @@
ohci_writel(0, &ohci->regs->ed_controlhead);
ohci_writel(0, &ohci->regs->ed_bulkhead);
- ohci_writel((__u32)ohci->hcca,
+ ohci_writel((uintptr_t)ohci->hcca,
&ohci->regs->hcca); /* reset clears this */
fminterval = 0x2edf;
diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c
index 8bb2275..28b9ab5 100644
--- a/drivers/usb/host/ohci-s3c24xx.c
+++ b/drivers/usb/host/ohci-s3c24xx.c
@@ -677,7 +677,7 @@
unsigned int toggle = 0;
/* OHCI handles the DATA-toggles itself, we just
- use the USB-toggle bits for reseting */
+ use the USB-toggle bits for resetting */
if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
toggle = TD_T_TOGGLE;
} else {
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index 2a1e8bf..0c45eec 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -51,7 +51,7 @@
extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
#endif
priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
- priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
+ priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
priv->usb_gate_mask <<= priv->phy_index;
@@ -101,6 +101,7 @@
{ .compatible = "allwinner,sun8i-a83t-ohci", },
{ .compatible = "allwinner,sun8i-h3-ohci", },
{ .compatible = "allwinner,sun9i-a80-ohci", },
+ { .compatible = "allwinner,sun50i-a64-ohci", },
{ }
};
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index 9b0c4a2..db0924c 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -10,12 +10,15 @@
/*
* e.g. PCI controllers need this
*/
+
+#include <asm/io.h>
+
#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-# define ohci_readl(a) __swap_32(*((volatile u32 *)(a)))
-# define ohci_writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
+# define ohci_readl(a) __swap_32(readl(a))
+# define ohci_writel(v, a) writel(__swap_32(v), a)
#else
-# define ohci_readl(a) (*((volatile u32 *)(a)))
-# define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
+# define ohci_readl(a) readl(a)
+# define ohci_writel(v, a) writel(v, a)
#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
#if ARCH_DMA_MINALIGN > 16
diff --git a/drivers/usb/host/utmi-armada100.c b/drivers/usb/host/utmi-armada100.c
index 1e87828..17fc132 100644
--- a/drivers/usb/host/utmi-armada100.c
+++ b/drivers/usb/host/utmi-armada100.c
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2012
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
index 28416ed..82fcd84 100644
--- a/drivers/usb/host/xhci-exynos5.c
+++ b/drivers/usb/host/xhci-exynos5.c
@@ -24,7 +24,7 @@
#include <asm/arch/power.h>
#include <asm/arch/xhci-exynos.h>
#include <asm/gpio.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <linux/compat.h>
#include <linux/usb/dwc3.h>
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index bdcd4f1..798c358 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <usb.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <linux/compat.h>
#include <linux/usb/xhci-fsl.h>
#include <linux/usb/dwc3.h>
@@ -58,6 +58,13 @@
}
}
+static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
+{
+ clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,
+ USB3_ENABLE_BEAT_BURST);
+ setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);
+}
+
static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
{
int ret = 0;
@@ -74,6 +81,22 @@
/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
+ /* Change beat burst and outstanding pipelined transfers requests */
+ fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
+
+ /*
+ * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
+ * reliably support Rx Detect in P3 mode(P3 is the default
+ * setting). Therefore, some USB3.0 devices may not be detected
+ * reliably in Super Speed mode. So, USB controller to configure
+ * USB in P2 mode whenever the Receive Detect feature is required.
+ * whenever the Receive Detect feature is required.
+ */
+ if (has_erratum_a010151())
+ clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
+ DWC3_GUSB3PIPECTL_DISRXDETP3,
+ DWC3_GUSB3PIPECTL_DISRXDETP3);
+
return ret;
}
@@ -129,15 +152,10 @@
static int xhci_fsl_remove(struct udevice *dev)
{
struct xhci_fsl_priv *priv = dev_get_priv(dev);
- int ret;
fsl_xhci_core_exit(&priv->ctx);
- ret = xhci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
+ return xhci_deregister(dev);
}
static const struct udevice_id xhci_usb_ids[] = {
diff --git a/drivers/usb/host/xhci-keystone.c b/drivers/usb/host/xhci-keystone.c
index 924fb76..f322a80 100644
--- a/drivers/usb/host/xhci-keystone.c
+++ b/drivers/usb/host/xhci-keystone.c
@@ -14,7 +14,7 @@
#include <asm/io.h>
#include <linux/usb/dwc3.h>
#include <asm/arch/xhci-keystone.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <linux/list.h>
#include "xhci.h"
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 3744452..62db51d 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -20,7 +20,7 @@
#include <usb.h>
#include <malloc.h>
#include <asm/cache.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include "xhci.h"
diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
new file mode 100644
index 0000000..46eb937
--- /dev/null
+++ b/drivers/usb/host/xhci-mvebu.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2015 Marvell International Ltd.
+ *
+ * MVEBU USB HOST xHCI Controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <usb.h>
+#include <asm/gpio.h>
+
+#include "xhci.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mvebu_xhci_platdata {
+ fdt_addr_t hcd_base;
+};
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct mvebu_xhci {
+ struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
+ struct usb_platdata usb_plat;
+ struct xhci_hccr *hcd;
+};
+
+/*
+ * Dummy implementation that can be overwritten by a board
+ * specific function
+ */
+__weak int board_xhci_enable(void)
+{
+ return 0;
+}
+
+static int xhci_usb_probe(struct udevice *dev)
+{
+ struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_xhci *ctx = dev_get_priv(dev);
+ struct xhci_hcor *hcor;
+ int len;
+
+ ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
+ len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase));
+ hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);
+
+ /* Enable USB xHCI (VBUS, reset etc) in board specific code */
+ board_xhci_enable();
+
+ return xhci_register(dev, ctx->hcd, hcor);
+}
+
+static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
+
+ /*
+ * Get the base address for XHCI controller from the device node
+ */
+ plat->hcd_base = dev_get_addr(dev);
+ if (plat->hcd_base == FDT_ADDR_T_NONE) {
+ debug("Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id xhci_usb_ids[] = {
+ { .compatible = "marvell,armada3700-xhci" },
+ { .compatible = "marvell,armada-8k-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_mvebu",
+ .id = UCLASS_USB,
+ .of_match = xhci_usb_ids,
+ .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
+ .probe = xhci_usb_probe,
+ .remove = xhci_deregister,
+ .ops = &xhci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct mvebu_xhci_platdata),
+ .priv_auto_alloc_size = sizeof(struct mvebu_xhci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index fd19f79..b881b19 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -11,7 +11,7 @@
#include <common.h>
#include <usb.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <asm/omap_common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 361fcce..63daaa6 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -7,12 +7,15 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <pci.h>
#include <usb.h>
#include "xhci.h"
+#ifndef CONFIG_DM_USB
+
/*
* Create the appropriate control structures to manage a new XHCI host
* controller.
@@ -58,3 +61,81 @@
void xhci_hcd_stop(int index)
{
}
+
+#else
+
+struct xhci_pci_priv {
+ struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
+};
+
+static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
+ struct xhci_hcor **ret_hcor)
+{
+ struct xhci_hccr *hccr;
+ struct xhci_hcor *hcor;
+ u32 cmd;
+
+ hccr = (struct xhci_hccr *)dm_pci_map_bar(dev,
+ PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ hcor = (struct xhci_hcor *)((uintptr_t) hccr +
+ HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
+
+ debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
+ (u32)hccr, (u32)hcor,
+ (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
+
+ *ret_hccr = hccr;
+ *ret_hcor = hcor;
+
+ /* enable busmaster */
+ dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER;
+ dm_pci_write_config32(dev, PCI_COMMAND, cmd);
+}
+
+static int xhci_pci_probe(struct udevice *dev)
+{
+ struct xhci_hccr *hccr;
+ struct xhci_hcor *hcor;
+
+ xhci_pci_init(dev, &hccr, &hcor);
+
+ return xhci_register(dev, hccr, hcor);
+}
+
+static int xhci_pci_remove(struct udevice *dev)
+{
+ int ret;
+
+ ret = xhci_deregister(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id xhci_pci_ids[] = {
+ { .compatible = "xhci-pci" },
+ { }
+};
+
+U_BOOT_DRIVER(xhci_pci) = {
+ .name = "xhci_pci",
+ .id = UCLASS_USB,
+ .probe = xhci_pci_probe,
+ .remove = xhci_pci_remove,
+ .of_match = xhci_pci_ids,
+ .ops = &xhci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct xhci_pci_priv),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static struct pci_device_id xhci_pci_supported[] = {
+ { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0) },
+ {},
+};
+
+U_BOOT_PCI_DEVICE(xhci_pci, xhci_pci_supported);
+
+#endif /* CONFIG_DM_USB */
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 5a1391f..2675a8f 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -18,7 +18,7 @@
#include <asm/byteorder.h>
#include <usb.h>
#include <asm/unaligned.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include "xhci.h"
diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c
new file mode 100644
index 0000000..8cbcb8f
--- /dev/null
+++ b/drivers/usb/host/xhci-rockchip.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2016 Rockchip, Inc.
+ * Authors: Daniel Meng <daniel.meng@rock-chips.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
+#include <usb.h>
+#include <watchdog.h>
+#include <asm/gpio.h>
+#include <linux/errno.h>
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+
+#include "xhci.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rockchip_xhci_platdata {
+ fdt_addr_t hcd_base;
+ fdt_addr_t phy_base;
+ struct gpio_desc vbus_gpio;
+};
+
+/*
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct rockchip_xhci {
+ struct usb_platdata usb_plat;
+ struct xhci_ctrl ctrl;
+ struct xhci_hccr *hcd;
+ struct dwc3 *dwc3_reg;
+};
+
+static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
+ struct udevice *child;
+ int ret = 0;
+
+ /*
+ * Get the base address for XHCI controller from the device node
+ */
+ plat->hcd_base = dev_get_addr(dev);
+ if (plat->hcd_base == FDT_ADDR_T_NONE) {
+ debug("Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
+
+ /* Get the base address for usbphy from the device node */
+ for (device_find_first_child(dev, &child); child;
+ device_find_next_child(&child)) {
+ if (!of_device_is_compatible(child, "rockchip,rk3399-usb3-phy"))
+ continue;
+ plat->phy_base = dev_get_addr(child);
+ break;
+ }
+
+ if (plat->phy_base == FDT_ADDR_T_NONE) {
+ debug("Can't get the usbphy register address\n");
+ return -ENXIO;
+ }
+
+ /* Vbus gpio */
+ ret = gpio_request_by_name(dev, "rockchip,vbus-gpio", 0,
+ &plat->vbus_gpio, GPIOD_IS_OUT);
+ if (ret)
+ debug("rockchip,vbus-gpio node missing!");
+
+ return 0;
+}
+
+/*
+ * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
+ * @dwc: Pointer to our controller context structure
+ * @dev: Pointer to ulcass device
+ */
+static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
+ struct udevice *dev)
+{
+ u32 reg;
+ const void *blob = gd->fdt_blob;
+ u32 utmi_bits;
+
+ /* Set dwc3 usb2 phy config */
+ reg = readl(&dwc3_reg->g_usb2phycfg[0]);
+
+ if (fdtdec_get_bool(blob, dev->of_offset,
+ "snps,dis-enblslpm-quirk"))
+ reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+
+ utmi_bits = fdtdec_get_int(blob, dev->of_offset,
+ "snps,phyif-utmi-bits", -1);
+ if (utmi_bits == 16) {
+ reg |= DWC3_GUSB2PHYCFG_PHYIF;
+ reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
+ reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
+ } else if (utmi_bits == 8) {
+ reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
+ reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
+ reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
+ }
+
+ if (fdtdec_get_bool(blob, dev->of_offset,
+ "snps,dis-u2-freeclk-exists-quirk"))
+ reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
+
+ if (fdtdec_get_bool(blob, dev->of_offset,
+ "snps,dis-u2-susphy-quirk"))
+ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+
+ writel(reg, &dwc3_reg->g_usb2phycfg[0]);
+}
+
+static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
+ struct udevice *dev)
+{
+ int ret;
+
+ ret = dwc3_core_init(rkxhci->dwc3_reg);
+ if (ret) {
+ debug("failed to initialize core\n");
+ return ret;
+ }
+
+ rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return 0;
+}
+
+static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
+{
+ return 0;
+}
+
+static int xhci_usb_probe(struct udevice *dev)
+{
+ struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
+ struct rockchip_xhci *ctx = dev_get_priv(dev);
+ struct xhci_hcor *hcor;
+ int ret;
+
+ ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
+ ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
+ hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
+ HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
+
+ /* setup the Vbus gpio here */
+ if (dm_gpio_is_valid(&plat->vbus_gpio))
+ dm_gpio_set_value(&plat->vbus_gpio, 1);
+
+ ret = rockchip_xhci_core_init(ctx, dev);
+ if (ret) {
+ debug("XHCI: failed to initialize controller\n");
+ return ret;
+ }
+
+ return xhci_register(dev, ctx->hcd, hcor);
+}
+
+static int xhci_usb_remove(struct udevice *dev)
+{
+ struct rockchip_xhci *ctx = dev_get_priv(dev);
+ int ret;
+
+ ret = xhci_deregister(dev);
+ if (ret)
+ return ret;
+ ret = rockchip_xhci_core_exit(ctx);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id xhci_usb_ids[] = {
+ { .compatible = "rockchip,rk3399-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_rockchip",
+ .id = UCLASS_USB,
+ .of_match = xhci_usb_ids,
+ .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
+ .probe = xhci_usb_probe,
+ .remove = xhci_usb_remove,
+ .ops = &xhci_usb_ops,
+ .bind = dm_scan_fdt_dev,
+ .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
+ .priv_auto_alloc_size = sizeof(struct rockchip_xhci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static const struct udevice_id usb_phy_ids[] = {
+ { .compatible = "rockchip,rk3399-usb3-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_phy) = {
+ .name = "usb_phy_rockchip",
+ .of_match = usb_phy_ids,
+};
diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c
deleted file mode 100644
index 1b3f3d2..0000000
--- a/drivers/usb/host/xhci-uniphier.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <usb.h>
-#include <fdtdec.h>
-#include "xhci.h"
-
-static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
-{
- DECLARE_GLOBAL_DATA_PTR;
- int node_list[2];
- fdt_addr_t addr;
- int count;
-
- count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
- COMPAT_SOCIONEXT_XHCI, node_list,
- ARRAY_SIZE(node_list));
-
- if (index >= count)
- return -ENODEV;
-
- addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
- if (addr == FDT_ADDR_T_NONE)
- return -ENODEV;
-
- *base = (struct xhci_hccr *)addr;
-
- return 0;
-}
-
-#define USB3_RST_CTRL 0x00100040
-#define IOMMU_RST_N (1 << 5)
-#define LINK_RST_N (1 << 4)
-
-static void uniphier_xhci_reset(void __iomem *base, int on)
-{
- u32 tmp;
-
- tmp = readl(base + USB3_RST_CTRL);
-
- if (on)
- tmp &= ~(IOMMU_RST_N | LINK_RST_N);
- else
- tmp |= IOMMU_RST_N | LINK_RST_N;
-
- writel(tmp, base + USB3_RST_CTRL);
-}
-
-int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
-{
- int ret;
- struct xhci_hccr *cr;
- struct xhci_hcor *or;
-
- ret = get_uniphier_xhci_base(index, &cr);
- if (ret < 0)
- return ret;
-
- uniphier_xhci_reset(cr, 0);
-
- or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
-
- *hccr = cr;
- *hcor = or;
-
- return 0;
-}
-
-void xhci_hcd_stop(int index)
-{
- int ret;
- struct xhci_hccr *cr;
-
- ret = get_uniphier_xhci_base(index, &cr);
- if (ret < 0)
- return;
-
- uniphier_xhci_reset(cr, 1);
-}
diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c
index a735369..cec1bc4 100644
--- a/drivers/usb/host/xhci-zynqmp.c
+++ b/drivers/usb/host/xhci-zynqmp.c
@@ -12,7 +12,7 @@
#include <common.h>
#include <usb.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <asm/arch-zynqmp/hardware.h>
#include <linux/compat.h>
#include <linux/usb/dwc3.h>
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index cb8a04b..3201177 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -28,7 +28,7 @@
#include <watchdog.h>
#include <asm/cache.h>
#include <asm/unaligned.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include "xhci.h"
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index c264859..caba42c 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -14,6 +14,15 @@
help
Enables the MUSB USB dual-role controller in gadget mode.
+config USB_MUSB_TI
+ bool "Enable TI OTG USB controller"
+ depends on DM_USB
+ default n
+ help
+ Say y here to enable support for the dual role high
+ speed USB controller based on the Mentor Graphics
+ silicon IP.
+
if USB_MUSB_HOST || USB_MUSB_GADGET
config USB_MUSB_PIC32
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index df1c3c8..296f230 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -12,6 +12,7 @@
obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
+obj-$(CONFIG_USB_MUSB_TI) += ti-musb.o
ccflags-y := $(call cc-option,-Wno-unused-variable) \
$(call cc-option,-Wno-unused-but-set-variable) \
diff --git a/drivers/usb/musb-new/am35x.c b/drivers/usb/musb-new/am35x.c
index b8791dd..0167ea7 100644
--- a/drivers/usb/musb-new/am35x.c
+++ b/drivers/usb/musb-new/am35x.c
@@ -336,7 +336,7 @@
if (ret == IRQ_HANDLED || epintr || usbintr) {
/* clear level interrupt */
if (data->clear_irq)
- data->clear_irq();
+ data->clear_irq(data->dev);
/* write EOI */
musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
}
@@ -401,14 +401,14 @@
/* Reset the musb */
if (data->reset)
- data->reset();
+ data->reset(data->dev);
/* Reset the controller */
musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(1);
+ data->set_phy_power(data->dev, 1);
msleep(5);
@@ -416,7 +416,7 @@
/* clear level interrupt */
if (data->clear_irq)
- data->clear_irq();
+ data->clear_irq(data->dev);
return 0;
}
@@ -439,7 +439,7 @@
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(0);
+ data->set_phy_power(data->dev, 0);
#ifndef __UBOOT__
usb_put_phy(musb->xceiv);
@@ -630,7 +630,7 @@
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(0);
+ data->set_phy_power(data->dev, 0);
clk_disable(glue->phy_clk);
clk_disable(glue->clk);
@@ -647,7 +647,7 @@
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(1);
+ data->set_phy_power(data->dev, 1);
ret = clk_enable(glue->phy_clk);
if (ret) {
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index dd0443c..84cb21b 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -79,7 +79,7 @@
#else
#include <common.h>
#include <usb.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
diff --git a/drivers/usb/musb-new/musb_core.h b/drivers/usb/musb-new/musb_core.h
index 2fe4ed5..4ae0ae2 100644
--- a/drivers/usb/musb-new/musb_core.h
+++ b/drivers/usb/musb-new/musb_core.h
@@ -21,7 +21,7 @@
#include <linux/usb.h>
#include <linux/usb/otg.h>
#else
-#include <asm/errno.h>
+#include <linux/errno.h>
#endif
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c
index a71db76..399b85b 100644
--- a/drivers/usb/musb-new/musb_dsps.c
+++ b/drivers/usb/musb-new/musb_dsps.c
@@ -452,7 +452,7 @@
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(1);
+ data->set_phy_power(data->dev, 1);
musb->isr = dsps_interrupt;
@@ -493,7 +493,7 @@
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(0);
+ data->set_phy_power(data->dev, 0);
#ifndef __UBOOT__
/* NOP driver needs change if supporting dual instance */
@@ -693,7 +693,7 @@
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(0);
+ data->set_phy_power(data->dev, 0);
return 0;
}
@@ -705,7 +705,7 @@
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(1);
+ data->set_phy_power(data->dev, 1);
return 0;
}
diff --git a/drivers/usb/musb-new/musb_gadget.h b/drivers/usb/musb-new/musb_gadget.h
index ddd567b..bd1d4f6 100644
--- a/drivers/usb/musb-new/musb_gadget.h
+++ b/drivers/usb/musb-new/musb_gadget.h
@@ -14,7 +14,7 @@
#include <linux/list.h>
#ifdef __UBOOT__
#include <asm/byteorder.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#endif
diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
index 6ce528c..ea71f75 100644
--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
@@ -4,7 +4,7 @@
#ifdef CONFIG_ARCH_SUNXI
#include <asm/arch/usb_phy.h>
#endif
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index c016a0b..469377f 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -201,10 +201,11 @@
/* musb_core does not call enable / disable in a balanced manner <sigh> */
static bool enabled = false;
-static struct musb *sunxi_musb;
static int sunxi_musb_enable(struct musb *musb)
{
+ int ret;
+
pr_debug("%s():\n", __func__);
musb_ep_select(musb->mregs, 0);
@@ -217,26 +218,17 @@
musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
if (is_host_enabled(musb)) {
- int id = sunxi_usb_phy_id_detect(0);
-
- if (id == 1 && sunxi_usb_phy_power_is_on(0))
- sunxi_usb_phy_power_off(0);
-
- if (!sunxi_usb_phy_power_is_on(0)) {
- int vbus = sunxi_usb_phy_vbus_detect(0);
- if (vbus == 1) {
- printf("A charger is plugged into the OTG: ");
- return -ENODEV;
- }
+ ret = sunxi_usb_phy_vbus_detect(0);
+ if (ret == 1) {
+ printf("A charger is plugged into the OTG: ");
+ return -ENODEV;
}
-
- if (id == 1) {
+ ret = sunxi_usb_phy_id_detect(0);
+ if (ret == 1) {
printf("No host cable detected: ");
return -ENODEV;
}
-
- if (!sunxi_usb_phy_power_is_on(0))
- sunxi_usb_phy_power_on(0);
+ sunxi_usb_phy_power_on(0); /* port power on */
}
USBC_ForceVbusValidToHigh(musb->mregs);
@@ -252,6 +244,9 @@
if (!enabled)
return;
+ if (is_host_enabled(musb))
+ sunxi_usb_phy_power_off(0); /* port power off */
+
USBC_ForceVbusValidToLow(musb->mregs);
mdelay(200); /* Wait for the current session to timeout */
@@ -313,7 +308,9 @@
};
#ifdef CONFIG_USB_MUSB_HOST
-int musb_usb_probe(struct udevice *dev)
+static int musb_usb_remove(struct udevice *dev);
+
+static int musb_usb_probe(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
@@ -321,23 +318,21 @@
priv->desc_before_addr = true;
- if (!sunxi_musb) {
- sunxi_musb = musb_init_controller(&musb_plat, NULL,
- (void *)SUNXI_USB0_BASE);
- }
-
- host->host = sunxi_musb;
+ host->host = musb_init_controller(&musb_plat, NULL,
+ (void *)SUNXI_USB0_BASE);
if (!host->host)
return -EIO;
ret = musb_lowlevel_init(host);
if (ret == 0)
printf("MUSB OTG\n");
+ else
+ musb_usb_remove(dev);
return ret;
}
-int musb_usb_remove(struct udevice *dev)
+static int musb_usb_remove(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
@@ -350,6 +345,9 @@
#endif
clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+ free(host->host);
+ host->host = NULL;
+
return 0;
}
diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c
new file mode 100644
index 0000000..1c15aa2
--- /dev/null
+++ b/drivers/usb/musb-new/ti-musb.c
@@ -0,0 +1,255 @@
+/*
+ * MISC driver for TI MUSB Glue.
+ *
+ * (C) Copyright 2016
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <dm.h>
+#include <linux/usb/otg.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+#include <asm/io.h>
+#include <asm/omap_musb.h>
+#include "musb_uboot.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DM_USB
+
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN (1 << 0)
+#define CM_PHY_OTG_PWRDN (1 << 1)
+#define OTGVDET_EN (1 << 19)
+#define OTGSESSENDEN (1 << 20)
+
+#define AM335X_USB1_CTRL 0x8
+
+struct ti_musb_platdata {
+ void *base;
+ void *ctrl_mod_base;
+ struct musb_hdrc_platform_data plat;
+ struct musb_hdrc_config musb_config;
+ struct omap_musb_board_data otg_board_data;
+};
+
+static int ti_musb_get_usb_index(int node)
+{
+ const void *fdt = gd->fdt_blob;
+ int i = 0;
+ char path[64];
+ const char *alias_path;
+ char alias[16];
+
+ fdt_get_path(fdt, node, path, sizeof(path));
+
+ do {
+ snprintf(alias, sizeof(alias), "usb%d", i);
+ alias_path = fdt_get_alias(fdt, alias);
+ if (alias_path == NULL) {
+ debug("USB index not found\n");
+ return -ENOENT;
+ }
+
+ if (!strcmp(path, alias_path))
+ return i;
+
+ i++;
+ } while (alias_path);
+
+ return -ENOENT;
+}
+
+static void ti_musb_set_phy_power(struct udevice *dev, u8 on)
+{
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+
+ if (on) {
+ clrsetbits_le32(platdata->ctrl_mod_base,
+ CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+ OTGVDET_EN | OTGSESSENDEN);
+ } else {
+ clrsetbits_le32(platdata->ctrl_mod_base, 0,
+ CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+ }
+}
+
+static int ti_musb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev->of_offset;
+ int phys;
+ int ctrl_mod;
+ int usb_index;
+
+ platdata->base = (void *)dev_get_addr_index(dev, 1);
+
+ phys = fdtdec_lookup_phandle(fdt, node, "phys");
+ ctrl_mod = fdtdec_lookup_phandle(fdt, phys, "ti,ctrl_mod");
+ platdata->ctrl_mod_base = (void *)fdtdec_get_addr(fdt, ctrl_mod, "reg");
+ usb_index = ti_musb_get_usb_index(node);
+ switch (usb_index) {
+ case 1:
+ platdata->ctrl_mod_base += AM335X_USB1_CTRL;
+ case 0:
+ default:
+ break;
+ }
+
+ platdata->musb_config.multipoint = fdtdec_get_int(fdt, node,
+ "mentor,multipoint",
+ -1);
+ if (platdata->musb_config.multipoint < 0) {
+ error("MUSB multipoint DT entry missing\n");
+ return -ENOENT;
+ }
+
+ platdata->musb_config.dyn_fifo = 1;
+
+ platdata->musb_config.num_eps = fdtdec_get_int(fdt, node,
+ "mentor,num-eps", -1);
+ if (platdata->musb_config.num_eps < 0) {
+ error("MUSB num-eps DT entry missing\n");
+ return -ENOENT;
+ }
+
+ platdata->musb_config.ram_bits = fdtdec_get_int(fdt, node,
+ "mentor,ram-bits", -1);
+ if (platdata->musb_config.ram_bits < 0) {
+ error("MUSB ram-bits DT entry missing\n");
+ return -ENOENT;
+ }
+
+ platdata->otg_board_data.set_phy_power = ti_musb_set_phy_power;
+ platdata->otg_board_data.dev = dev;
+ platdata->plat.config = &platdata->musb_config;
+
+ platdata->plat.power = fdtdec_get_int(fdt, node, "mentor,power", -1);
+ if (platdata->plat.power < 0) {
+ error("MUSB mentor,power DT entry missing\n");
+ return -ENOENT;
+ }
+
+ platdata->plat.platform_ops = &musb_dsps_ops;
+ platdata->plat.board_data = &platdata->otg_board_data;
+
+ return 0;
+}
+
+static int ti_musb_host_probe(struct udevice *dev)
+{
+ struct musb_host_data *host = dev_get_priv(dev);
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+ struct omap_musb_board_data *otg_board_data;
+ int ret;
+
+ priv->desc_before_addr = true;
+
+ otg_board_data = &platdata->otg_board_data;
+
+ host->host = musb_init_controller(&platdata->plat,
+ (struct device *)otg_board_data,
+ platdata->base);
+ if (!host->host)
+ return -EIO;
+
+ ret = musb_lowlevel_init(host);
+
+ return ret;
+}
+
+static int ti_musb_host_remove(struct udevice *dev)
+{
+ struct musb_host_data *host = dev_get_priv(dev);
+
+ musb_stop(host->host);
+
+ return 0;
+}
+
+static int ti_musb_host_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev->of_offset;
+ int ret;
+
+ ret = ti_musb_ofdata_to_platdata(dev);
+ if (ret) {
+ error("platdata dt parse error\n");
+ return ret;
+ }
+
+ platdata->plat.mode = MUSB_HOST;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(ti_musb_host) = {
+ .name = "ti-musb-host",
+ .id = UCLASS_USB,
+ .ofdata_to_platdata = ti_musb_host_ofdata_to_platdata,
+ .probe = ti_musb_host_probe,
+ .remove = ti_musb_host_remove,
+ .ops = &musb_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct ti_musb_platdata),
+ .priv_auto_alloc_size = sizeof(struct musb_host_data),
+};
+
+static int ti_musb_wrapper_bind(struct udevice *parent)
+{
+ const void *fdt = gd->fdt_blob;
+ int node;
+ int ret;
+
+ for (node = fdt_first_subnode(fdt, parent->of_offset); node > 0;
+ node = fdt_next_subnode(fdt, node)) {
+ struct udevice *dev;
+ const char *name = fdt_get_name(fdt, node, NULL);
+ enum usb_dr_mode dr_mode;
+ struct driver *drv;
+
+ if (strncmp(name, "usb@", 4))
+ continue;
+
+ dr_mode = usb_get_dr_mode(node);
+ switch (dr_mode) {
+ case USB_DR_MODE_PERIPHERAL:
+ /* Bind MUSB device */
+ break;
+ case USB_DR_MODE_HOST:
+ /* Bind MUSB host */
+ ret = device_bind_driver_to_node(parent, "ti-musb-host",
+ name, node, &dev);
+ if (ret) {
+ error("musb - not able to bind usb host node\n");
+ return ret;
+ }
+ break;
+ default:
+ break;
+ };
+ }
+ return 0;
+}
+
+static const struct udevice_id ti_musb_ids[] = {
+ { .compatible = "ti,am33xx-usb" },
+ { }
+};
+
+U_BOOT_DRIVER(ti_musb_wrapper) = {
+ .name = "ti-musb-wrapper",
+ .id = UCLASS_MISC,
+ .of_match = ti_musb_ids,
+ .bind = ti_musb_wrapper_bind,
+};
+
+#endif /* CONFIG_DM_USB */
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index 1993da1..7c7fba2 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -11,7 +11,7 @@
#include <common.h>
#include <usb.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <asm/omap_common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 8361a71..2069576 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -101,6 +101,15 @@
to update the environment, the breakage may be confusing for users.
This option will be removed around the end of 2016.
+config VIDEO_COREBOOT
+ bool "Enable coreboot framebuffer driver support"
+ depends on X86 && SYS_COREBOOT
+ help
+ Turn on this option to enable a framebuffer driver when U-Boot is
+ loaded by coreboot where the graphics device is configured by
+ coreboot already. This can in principle be used with any platform
+ that coreboot supports.
+
config VIDEO_VESA
bool "Enable VESA video driver support"
default n
@@ -366,7 +375,19 @@
bool "Enable Intel Broadwell integrated graphics device"
depends on X86
help
- This enabled support for integrated graphics on Intel broadwell
+ This enables support for integrated graphics on Intel broadwell
+ devices. Initialisation is mostly performed by a VGA boot ROM, with
+ some setup handled by U-Boot itself. The graphics adaptor works as
+ a VESA device and supports LCD panels, eDP and LVDS outputs.
+ Configuration of most aspects of device operation is performed using
+ a special tool which configures the VGA ROM, but the graphics
+ resolution can be selected in U-Boot.
+
+config VIDEO_IVYBRIDGE_IGD
+ bool "Enable Intel Ivybridge integration graphics support"
+ depends on X86
+ help
+ This enables support for integrated graphics on Intel ivybridge
devices. Initialisation is mostly performed by a VGA boot ROM, with
some setup handled by U-Boot itself. The graphics adaptor works as
a VESA device and supports LCD panels, eDP and LVDS outputs.
@@ -413,4 +434,167 @@
source "drivers/video/bridge/Kconfig"
+config VIDEO
+ bool "Enable legacy video support"
+ depends on !DM_VIDEO
+ help
+ Define this for video support, without using driver model. Some
+ drivers use this because they are not yet converted to driver
+ model. Video drivers typically provide a colour text console and
+ cursor.
+
+config VIDEO_IPUV3
+ bool "i.MX IPUv3 Core video support"
+ depends on VIDEO && MX6
+ help
+ This enables framebuffer driver for i.MX processors working
+ on the IPUv3(Image Processing Unit) internal graphic processor.
+
+config CFB_CONSOLE
+ bool "Enable colour frame buffer console"
+ depends on VIDEO
+ default y if VIDEO
+ help
+ Enables the colour frame buffer driver. This supports colour
+ output on a bitmap display from an in-memory frame buffer.
+ Several colour devices are supported along with various options to
+ adjust the supported features. The driver is implemented in
+ cfb_console.c
+
+ The following defines are needed (cf. smiLynxEM, i8042)
+ VIDEO_FB_LITTLE_ENDIAN graphic memory organisation
+ (default big endian)
+ VIDEO_HW_RECTFILL graphic chip supports
+ rectangle fill (cf. smiLynxEM)
+ VIDEO_HW_BITBLT graphic chip supports
+ bit-blit (cf. smiLynxEM)
+ VIDEO_VISIBLE_COLS visible pixel columns (cols=pitch)
+ VIDEO_VISIBLE_ROWS visible pixel rows
+ VIDEO_PIXEL_SIZE bytes per pixel
+ VIDEO_DATA_FORMAT graphic data format
+ (0-5, cf. cfb_console.c)
+ VIDEO_FB_ADRS framebuffer address
+ VIDEO_KBD_INIT_FCT keyboard int fct (i.e. rx51_kp_init())
+ VIDEO_TSTC_FCT test char fct (i.e. rx51_kp_tstc)
+ VIDEO_GETC_FCT get char fct (i.e. rx51_kp_getc)
+ CONFIG_VIDEO_LOGO display Linux logo in upper left corner
+ CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of linux_logo.h
+ for logo. Requires CONFIG_VIDEO_LOGO
+ CONFIG_CONSOLE_EXTRA_INFO
+ additional board info beside
+ the logo
+ CONFIG_HIDE_LOGO_VERSION
+ do not display bootloader
+ version string
+
+ When CONFIG_CFB_CONSOLE is defined, the video console is the
+ default console. The serial console can be forced by setting the
+ environment 'console=serial'.
+
+config CFB_CONSOLE_ANSI
+ bool "Support ANSI escape sequences"
+ depends on CFB_CONSOLE
+ help
+ This allows the colour buffer frame buffer driver to support
+ a limited number of ANSI escape sequences (cursor control,
+ erase functions and limited graphics rendition control). Normal
+ output from U-Boot will pass through this filter.
+
+config VGA_AS_SINGLE_DEVICE
+ bool "Set the video as an output-only device"
+ depends on CFB_CONSOLE
+ default y
+ help
+ If enable the framebuffer device will be initialized as an
+ output-only device. The Keyboard driver will not be set up. This
+ may be used if you have no keyboard device, or more than one
+ (USB Keyboard, AT Keyboard).
+
+config VIDEO_SW_CURSOR
+ bool "Enable a software cursor"
+ depends on CFB_CONSOLE
+ default y if CFB_CONSOLE
+ help
+ This draws a cursor after the last character. No blinking is
+ provided. This makes it possible to see the current cursor
+ position when entering text on the console. It is recommended to
+ enable this.
+
+config CONSOLE_EXTRA_INFO
+ bool "Display additional board information"
+ depends on CFB_CONSOLE
+ help
+ Display additional board information strings that normally go to
+ the serial port. When this option is enabled, a board-specific
+ function video_get_info_str() is called to get the string for
+ each line of the display. The function should return the string,
+ which can be empty if there is nothing to display for that line.
+
+config CONSOLE_SCROLL_LINES
+ int "Number of lines to scroll the console by"
+ depends on CFB_CONSOLE || DM_VIDEO || LCD
+ default 1
+ help
+ When the console need to be scrolled, this is the number of
+ lines to scroll by. It defaults to 1. Increasing this makes the
+ console jump but can help speed up operation when scrolling
+ is slow.
+
+config VIDEO_CT69000
+ bool "Enable Chips & Technologies 69000 video driver"
+ depends on VIDEO
+ help
+ This enables a frame buffer driver for the Chips & Technologies
+ ct69000, a fairly old graphics device (circa 2000) which is used
+ on some hardware. It operates over the ISA bus, and supports
+ some acceleration features.
+
+ For the CT69000 and SMI_LYNXEM drivers, videomode is
+ selected via environment 'videomode'. Two different ways
+ are possible:
+ - "videomode=num" 'num' is a standard LiLo mode numbers.
+ Following standard modes are supported (* is default):
+
+ Colors 640x480 800x600 1024x768 1152x864 1280x1024
+ -------------+---------------------------------------------
+ 8 bits | 0x301* 0x303 0x305 0x161 0x307
+ 15 bits | 0x310 0x313 0x316 0x162 0x319
+ 16 bits | 0x311 0x314 0x317 0x163 0x31A
+ 24 bits | 0x312 0x315 0x318 ? 0x31B
+ -------------+---------------------------------------------
+ (i.e. setenv videomode 317; saveenv; reset;)
+
+ - "videomode=bootargs" all the video parameters are parsed
+ from the bootargs. (See drivers/video/videomodes.c)
+
+config SYS_CONSOLE_BG_COL
+ hex "Background colour"
+ depends on CFB_CONSOLE || VIDEO_CT69000
+ default 0x00
+ help
+ Defines the background colour for the console. The value is from
+ 0x00 to 0xff and the meaning depends on the graphics card.
+ Typically, 0x00 means black and 0xff means white. Do not set
+ the background and foreground to the same colour or you will see
+ nothing.
+
+config SYS_CONSOLE_FG_COL
+ hex "Foreground colour"
+ depends on CFB_CONSOLE || VIDEO_CT69000
+ default 0xa0
+ help
+ Defines the foreground colour for the console. The value is from
+ 0x00 to 0xff and the meaning depends on the graphics card.
+ Typically, 0x00 means black and 0xff means white. Do not set
+ the background and foreground to the same colour or you will see
+ nothing.
+
+config LCD
+ bool "Enable legacy LCD support"
+ help
+ Define this to enable LCD support (for output to LCD display).
+ You will also need to select an LCD driver using an additional
+ CONFIG option. See the README for details. Drives which have been
+ converted to driver model will instead used CONFIG_DM_VIDEO.
+
endmenu
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 3f045fe..db34904 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -20,6 +20,7 @@
endif
obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
+obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
@@ -36,10 +37,9 @@
obj-$(CONFIG_LD9040) += ld9040.o
obj-$(CONFIG_SED156X) += sed156x.o
obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
-obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
+obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
-obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o
obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
@@ -49,15 +49,12 @@
obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
-obj-$(CONFIG_VIDEO_S3C) += s3c-fb.o videomodes.o
obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
-obj-$(CONFIG_VIDEO_SED13806) += sed13806.o
obj-$(CONFIG_VIDEO_SM501) += sm501.o
-obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
-obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o
+obj-$(CONFIG_VIDEO_VESA) += vesa.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_LG4573) += lg4573.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c
index 5748951..07a29ea 100644
--- a/drivers/video/ati_radeon_fb.c
+++ b/drivers/video/ati_radeon_fb.c
@@ -22,7 +22,7 @@
#include <bios_emul.h>
#include <pci.h>
#include <asm/processor.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <video_fb.h>
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index cd605e6..cc6454f 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -71,9 +71,9 @@
msg_setup->virtual_w_h.body.req.width = w;
msg_setup->virtual_w_h.body.req.height = h;
BCM2835_MBOX_INIT_TAG(&msg_setup->depth, SET_DEPTH);
- msg_setup->depth.body.req.bpp = 16;
+ msg_setup->depth.body.req.bpp = 32;
BCM2835_MBOX_INIT_TAG(&msg_setup->pixel_order, SET_PIXEL_ORDER);
- msg_setup->pixel_order.body.req.order = BCM2835_MBOX_PIXEL_ORDER_BGR;
+ msg_setup->pixel_order.body.req.order = BCM2835_MBOX_PIXEL_ORDER_RGB;
BCM2835_MBOX_INIT_TAG(&msg_setup->alpha_mode, SET_ALPHA_MODE);
msg_setup->alpha_mode.body.req.alpha = BCM2835_MBOX_ALPHA_MODE_IGNORED;
BCM2835_MBOX_INIT_TAG(&msg_setup->virtual_offset, SET_VIRTUAL_OFFSET);
@@ -103,7 +103,7 @@
panel_info.vl_col = w;
panel_info.vl_row = h;
- panel_info.vl_bpix = LCD_COLOR16;
+ panel_info.vl_bpix = LCD_COLOR32;
gd->fb_base = bus_to_phys(
msg_setup->allocate_buffer.body.resp.fb_address);
diff --git a/drivers/video/bridge/ptn3460.c b/drivers/video/bridge/ptn3460.c
index 2e2ae7c..f9d3720 100644
--- a/drivers/video/bridge/ptn3460.c
+++ b/drivers/video/bridge/ptn3460.c
@@ -11,14 +11,9 @@
static int ptn3460_attach(struct udevice *dev)
{
- int ret;
-
debug("%s: %s\n", __func__, dev->name);
- ret = video_bridge_set_active(dev, true);
- if (ret)
- return ret;
- return 0;
+ return video_bridge_set_active(dev, true);
}
struct video_bridge_ops ptn3460_ops = {
diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c
index ce4f296..beef770 100644
--- a/drivers/video/broadwell_igd.c
+++ b/drivers/video/broadwell_igd.c
@@ -9,10 +9,8 @@
#include <common.h>
#include <bios_emul.h>
#include <dm.h>
-#include <pci_rom.h>
#include <vbe.h>
#include <video.h>
-#include <video_fb.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
@@ -20,11 +18,9 @@
#include <asm/arch/cpu.h>
#include <asm/arch/iomap.h>
#include <asm/arch/pch.h>
-#include <linux/log2.h>
#include "i915_reg.h"
struct broadwell_igd_priv {
- GraphicDevice ctfb;
u8 *regs;
};
@@ -323,10 +319,7 @@
static unsigned long gtt_read(struct broadwell_igd_priv *priv,
unsigned long reg)
{
- u32 val;
-
- val = readl(priv->regs + reg);
- return val;
+ return readl(priv->regs + reg);
}
static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
@@ -667,10 +660,7 @@
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struct broadwell_igd_priv *priv = dev_get_priv(dev);
bool is_broadwell;
- GraphicDevice *gdev = &priv->ctfb;
- int bits_per_pixel;
int ret;
if (!ll_boot_init()) {
@@ -686,13 +676,9 @@
debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
ret = igd_pre_init(dev, is_broadwell);
if (!ret) {
- ret = dm_pci_run_vga_bios(dev, broadwell_igd_int15_handler,
- PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
- if (ret) {
- printf("failed to run video BIOS: %d\n", ret);
- ret = -EIO;
- }
+ ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
+ if (ret)
+ debug("failed to run video BIOS: %d\n", ret);
}
if (!ret)
ret = igd_post_init(dev, is_broadwell);
@@ -700,13 +686,8 @@
if (ret)
return ret;
- if (vbe_get_video_info(gdev)) {
- printf("No video mode configured\n");
- return -ENXIO;
- }
-
- /* Use write-through for the graphics memory, 256MB */
- ret = mtrr_add_request(MTRR_TYPE_WRTHROUGH, gdev->pciBase, 256 << 20);
+ /* Use write-combining for the graphics memory, 256MB */
+ ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20);
if (!ret)
ret = mtrr_commit(true);
if (ret && ret != -ENOSYS) {
@@ -714,17 +695,8 @@
ret);
}
- bits_per_pixel = gdev->gdfBytesPP * 8;
- sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
- bits_per_pixel);
- printf("%s\n", gdev->modeIdent);
- uc_priv->xsize = gdev->winSizeX;
- uc_priv->ysize = gdev->winSizeY;
- uc_priv->bpix = ilog2(bits_per_pixel);
- plat->base = gdev->pciBase;
- plat->size = gdev->memSize;
- debug("fb=%x, size %x, display size=%d %d %d\n", gdev->pciBase,
- gdev->memSize, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
+ debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
+ plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
return 0;
}
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 30b53db..c0b1b8d 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -27,7 +27,6 @@
*
* (for SMI LynxE graphic chip)
*
- * CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810
* VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian
* VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill
* VIDEO_HW_BITBLT - graphic driver supports hardware bit blt
@@ -59,46 +58,21 @@
* info);
* that fills a info buffer at i=row.
* s.a: board/eltec/bab7xx.
- * CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be
- * initialized as an output only device.
- * The Keyboard driver will not be
- * set-up. This may be used, if you have
- * no or more than one Keyboard devices
- * (USB Keyboard, AT Keyboard).
*
* CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last
* character. No blinking is provided.
* Uses the macros CURSOR_SET and
* CURSOR_OFF.
- *
- * CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability
- * of the graphic chip. Uses the macro
- * CURSOR_SET. ATTENTION: If booting an
- * OS, the display driver must disable
- * the hardware register of the graphic
- * chip. Otherwise a blinking field is
- * displayed.
*/
#include <common.h>
#include <fdtdec.h>
#include <version.h>
#include <malloc.h>
+#include <video.h>
#include <linux/compiler.h>
/*
- * Console device defines with SMI graphic
- * Any other graphic must change this section
- */
-
-#ifdef CONFIG_VIDEO_SMI_LYNXEM
-
-#define VIDEO_FB_LITTLE_ENDIAN
-#define VIDEO_HW_RECTFILL
-#define VIDEO_HW_BITBLT
-#endif
-
-/*
* Defines for the CT69000 driver
*/
#ifdef CONFIG_VIDEO_CT69000
@@ -108,16 +82,7 @@
#define VIDEO_HW_BITBLT
#endif
-/*
- * Defines for the SED13806 driver
- */
-#ifdef CONFIG_VIDEO_SED13806
-#define VIDEO_FB_LITTLE_ENDIAN
-#define VIDEO_HW_RECTFILL
-#define VIDEO_HW_BITBLT
-#endif
-
-#if defined(CONFIG_VIDEO_MXS) || defined(CONFIG_VIDEO_S3C)
+#if defined(CONFIG_VIDEO_MXS)
#define VIDEO_FB_16BPP_WORD_SWAP
#endif
@@ -177,18 +142,7 @@
#include <splash.h>
#endif
-/*
- * Cursor definition:
- * CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No
- * blinking is provided. Uses the macros CURSOR_SET
- * and CURSOR_OFF.
- * CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the
- * graphic chip. Uses the macro CURSOR_SET.
- * ATTENTION: If booting an OS, the display driver
- * must disable the hardware register of the graphic
- * chip. Otherwise a blinking field is displayed
- */
-#if !defined(CONFIG_VIDEO_SW_CURSOR) && !defined(CONFIG_VIDEO_HW_CURSOR)
+#if !defined(CONFIG_VIDEO_SW_CURSOR)
/* no Cursor defined */
#define CURSOR_ON
#define CURSOR_OFF
@@ -196,10 +150,6 @@
#endif
#if defined(CONFIG_VIDEO_SW_CURSOR)
-#if defined(CONFIG_VIDEO_HW_CURSOR)
-#error only one of CONFIG_VIDEO_SW_CURSOR or CONFIG_VIDEO_HW_CURSOR can be \
- defined
-#endif
void console_cursor(int state);
#define CURSOR_ON console_cursor(1)
@@ -207,17 +157,6 @@
#define CURSOR_SET video_set_cursor()
#endif /* CONFIG_VIDEO_SW_CURSOR */
-#ifdef CONFIG_VIDEO_HW_CURSOR
-#ifdef CURSOR_ON
-#error only one of CONFIG_VIDEO_SW_CURSOR or CONFIG_VIDEO_HW_CURSOR can be \
- defined
-#endif
-#define CURSOR_ON
-#define CURSOR_OFF
-#define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \
- (console_row * VIDEO_FONT_HEIGHT) + video_logo_height)
-#endif /* CONFIG_VIDEO_HW_CURSOR */
-
#ifdef CONFIG_VIDEO_LOGO
#ifdef CONFIG_VIDEO_BMP_LOGO
#include <bmp_logo.h>
@@ -297,16 +236,6 @@
#endif
#endif
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * setup a board string: type, speed, etc.
- *
- * line_number: location to place info string beside logo
- * info: buffer for info string
- */
-extern void video_get_info_str(int line_number, char *info);
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
/* Locals */
@@ -885,7 +814,7 @@
CURSOR_SET;
}
-static void video_putc(struct stdio_dev *dev, const char c)
+static void cfb_video_putc(struct stdio_dev *dev, const char c)
{
#ifdef CONFIG_CFB_CONSOLE_ANSI
int i;
@@ -1099,7 +1028,7 @@
flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE);
}
-static void video_puts(struct stdio_dev *dev, const char *s)
+static void cfb_video_puts(struct stdio_dev *dev, const char *s)
{
int flush = cfb_do_flush_cache;
int count = strlen(s);
@@ -1108,7 +1037,7 @@
cfb_do_flush_cache = 0;
while (count--)
- video_putc(dev, *s++);
+ cfb_video_putc(dev, *s++);
if (flush) {
cfb_do_flush_cache = flush;
@@ -2075,7 +2004,7 @@
#endif
}
-static int video_init(void)
+static int cfg_video_init(void)
{
unsigned char color8;
@@ -2084,79 +2013,78 @@
return -1;
video_fb_address = (void *) VIDEO_FB_ADRS;
-#ifdef CONFIG_VIDEO_HW_CURSOR
- video_init_hw_cursor(VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT);
-#endif
cfb_do_flush_cache = cfb_fb_is_in_dram() && dcache_status();
/* Init drawing pats */
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
- video_set_lut(0x01, CONSOLE_FG_COL, CONSOLE_FG_COL,
- CONSOLE_FG_COL);
- video_set_lut(0x00, CONSOLE_BG_COL, CONSOLE_BG_COL,
- CONSOLE_BG_COL);
+ video_set_lut(0x01, CONFIG_SYS_CONSOLE_FG_COL,
+ CONFIG_SYS_CONSOLE_FG_COL,
+ CONFIG_SYS_CONSOLE_FG_COL);
+ video_set_lut(0x00, CONFIG_SYS_CONSOLE_BG_COL,
+ CONFIG_SYS_CONSOLE_BG_COL,
+ CONFIG_SYS_CONSOLE_BG_COL);
fgx = 0x01010101;
bgx = 0x00000000;
break;
case GDF__8BIT_332RGB:
- color8 = ((CONSOLE_FG_COL & 0xe0) |
- ((CONSOLE_FG_COL >> 3) & 0x1c) |
- CONSOLE_FG_COL >> 6);
+ color8 = ((CONFIG_SYS_CONSOLE_FG_COL & 0xe0) |
+ ((CONFIG_SYS_CONSOLE_FG_COL >> 3) & 0x1c) |
+ CONFIG_SYS_CONSOLE_FG_COL >> 6);
fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) |
color8;
- color8 = ((CONSOLE_BG_COL & 0xe0) |
- ((CONSOLE_BG_COL >> 3) & 0x1c) |
- CONSOLE_BG_COL >> 6);
+ color8 = ((CONFIG_SYS_CONSOLE_BG_COL & 0xe0) |
+ ((CONFIG_SYS_CONSOLE_BG_COL >> 3) & 0x1c) |
+ CONFIG_SYS_CONSOLE_BG_COL >> 6);
bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) |
color8;
break;
case GDF_15BIT_555RGB:
- fgx = (((CONSOLE_FG_COL >> 3) << 26) |
- ((CONSOLE_FG_COL >> 3) << 21) |
- ((CONSOLE_FG_COL >> 3) << 16) |
- ((CONSOLE_FG_COL >> 3) << 10) |
- ((CONSOLE_FG_COL >> 3) << 5) |
- (CONSOLE_FG_COL >> 3));
- bgx = (((CONSOLE_BG_COL >> 3) << 26) |
- ((CONSOLE_BG_COL >> 3) << 21) |
- ((CONSOLE_BG_COL >> 3) << 16) |
- ((CONSOLE_BG_COL >> 3) << 10) |
- ((CONSOLE_BG_COL >> 3) << 5) |
- (CONSOLE_BG_COL >> 3));
+ fgx = (((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 26) |
+ ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 21) |
+ ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 16) |
+ ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 10) |
+ ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 5) |
+ (CONFIG_SYS_CONSOLE_FG_COL >> 3));
+ bgx = (((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 26) |
+ ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 21) |
+ ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 16) |
+ ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 10) |
+ ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 5) |
+ (CONFIG_SYS_CONSOLE_BG_COL >> 3));
break;
case GDF_16BIT_565RGB:
- fgx = (((CONSOLE_FG_COL >> 3) << 27) |
- ((CONSOLE_FG_COL >> 2) << 21) |
- ((CONSOLE_FG_COL >> 3) << 16) |
- ((CONSOLE_FG_COL >> 3) << 11) |
- ((CONSOLE_FG_COL >> 2) << 5) |
- (CONSOLE_FG_COL >> 3));
- bgx = (((CONSOLE_BG_COL >> 3) << 27) |
- ((CONSOLE_BG_COL >> 2) << 21) |
- ((CONSOLE_BG_COL >> 3) << 16) |
- ((CONSOLE_BG_COL >> 3) << 11) |
- ((CONSOLE_BG_COL >> 2) << 5) |
- (CONSOLE_BG_COL >> 3));
+ fgx = (((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 27) |
+ ((CONFIG_SYS_CONSOLE_FG_COL >> 2) << 21) |
+ ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 16) |
+ ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 11) |
+ ((CONFIG_SYS_CONSOLE_FG_COL >> 2) << 5) |
+ (CONFIG_SYS_CONSOLE_FG_COL >> 3));
+ bgx = (((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 27) |
+ ((CONFIG_SYS_CONSOLE_BG_COL >> 2) << 21) |
+ ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 16) |
+ ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 11) |
+ ((CONFIG_SYS_CONSOLE_BG_COL >> 2) << 5) |
+ (CONFIG_SYS_CONSOLE_BG_COL >> 3));
break;
case GDF_32BIT_X888RGB:
- fgx = (CONSOLE_FG_COL << 16) |
- (CONSOLE_FG_COL << 8) |
- CONSOLE_FG_COL;
- bgx = (CONSOLE_BG_COL << 16) |
- (CONSOLE_BG_COL << 8) |
- CONSOLE_BG_COL;
+ fgx = (CONFIG_SYS_CONSOLE_FG_COL << 16) |
+ (CONFIG_SYS_CONSOLE_FG_COL << 8) |
+ CONFIG_SYS_CONSOLE_FG_COL;
+ bgx = (CONFIG_SYS_CONSOLE_BG_COL << 16) |
+ (CONFIG_SYS_CONSOLE_BG_COL << 8) |
+ CONFIG_SYS_CONSOLE_BG_COL;
break;
case GDF_24BIT_888RGB:
- fgx = (CONSOLE_FG_COL << 24) |
- (CONSOLE_FG_COL << 16) |
- (CONSOLE_FG_COL << 8) |
- CONSOLE_FG_COL;
- bgx = (CONSOLE_BG_COL << 24) |
- (CONSOLE_BG_COL << 16) |
- (CONSOLE_BG_COL << 8) |
- CONSOLE_BG_COL;
+ fgx = (CONFIG_SYS_CONSOLE_FG_COL << 24) |
+ (CONFIG_SYS_CONSOLE_FG_COL << 16) |
+ (CONFIG_SYS_CONSOLE_FG_COL << 8) |
+ CONFIG_SYS_CONSOLE_FG_COL;
+ bgx = (CONFIG_SYS_CONSOLE_BG_COL << 24) |
+ (CONFIG_SYS_CONSOLE_BG_COL << 16) |
+ (CONFIG_SYS_CONSOLE_BG_COL << 8) |
+ CONFIG_SYS_CONSOLE_BG_COL;
break;
}
eorx = fgx ^ bgx;
@@ -2202,7 +2130,7 @@
return 0;
/* Init video chip - returns with framebuffer cleared */
- if (video_init() == -1)
+ if (cfg_video_init() == -1)
return 0;
if (board_cfb_skip())
@@ -2227,8 +2155,8 @@
memset(&console_dev, 0, sizeof(console_dev));
strcpy(console_dev.name, "vga");
console_dev.flags = DEV_FLAGS_OUTPUT;
- console_dev.putc = video_putc; /* 'putc' function */
- console_dev.puts = video_puts; /* 'puts' function */
+ console_dev.putc = cfb_video_putc; /* 'putc' function */
+ console_dev.puts = cfb_video_puts; /* 'puts' function */
#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
if (have_keyboard && keyboard_ok) {
diff --git a/drivers/video/coreboot.c b/drivers/video/coreboot.c
new file mode 100644
index 0000000..3a94aa1
--- /dev/null
+++ b/drivers/video/coreboot.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <vbe.h>
+#include <video.h>
+#include <asm/arch/sysinfo.h>
+
+static int save_vesa_mode(struct cb_framebuffer *fb,
+ struct vesa_mode_info *vesa)
+{
+ /*
+ * If there is no framebuffer structure, bail out and keep
+ * running on the serial console.
+ */
+ if (!fb)
+ return -ENXIO;
+
+ vesa->x_resolution = fb->x_resolution;
+ vesa->y_resolution = fb->y_resolution;
+ vesa->bits_per_pixel = fb->bits_per_pixel;
+ vesa->bytes_per_scanline = fb->bytes_per_line;
+ vesa->phys_base_ptr = fb->physical_address;
+ vesa->red_mask_size = fb->red_mask_size;
+ vesa->red_mask_pos = fb->red_mask_pos;
+ vesa->green_mask_size = fb->green_mask_size;
+ vesa->green_mask_pos = fb->green_mask_pos;
+ vesa->blue_mask_size = fb->blue_mask_size;
+ vesa->blue_mask_pos = fb->blue_mask_pos;
+ vesa->reserved_mask_size = fb->reserved_mask_size;
+ vesa->reserved_mask_pos = fb->reserved_mask_pos;
+
+ return 0;
+}
+
+static int coreboot_video_probe(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
+ struct vesa_mode_info *vesa = &mode_info.vesa;
+ int ret;
+
+ printf("Video: ");
+
+ /* Initialize vesa_mode_info structure */
+ ret = save_vesa_mode(fb, vesa);
+ if (ret)
+ goto err;
+
+ ret = vbe_setup_video_priv(vesa, uc_priv, plat);
+ if (ret)
+ goto err;
+
+ printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+ vesa->bits_per_pixel);
+
+ return 0;
+
+err:
+ printf("No video mode configured in coreboot!\n");
+ return ret;
+}
+
+static const struct udevice_id coreboot_video_ids[] = {
+ { .compatible = "coreboot-fb" },
+ { }
+};
+
+U_BOOT_DRIVER(coreboot_video) = {
+ .name = "coreboot_video",
+ .id = UCLASS_VIDEO,
+ .of_match = coreboot_video_ids,
+ .probe = coreboot_video_probe,
+};
diff --git a/drivers/video/coreboot_fb.c b/drivers/video/coreboot_fb.c
deleted file mode 100644
index feb5463..0000000
--- a/drivers/video/coreboot_fb.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * coreboot Framebuffer driver.
- *
- * Copyright (C) 2011 The Chromium OS authors
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sysinfo.h>
-#include <vbe.h>
-#include <video_fb.h>
-#include "videomodes.h"
-
-/*
- * The Graphic Device
- */
-GraphicDevice ctfb;
-
-static void save_vesa_mode(void)
-{
- struct vesa_mode_info *vesa = &mode_info.vesa;
- struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
-
- vesa->x_resolution = fb->x_resolution;
- vesa->y_resolution = fb->y_resolution;
- vesa->bits_per_pixel = fb->bits_per_pixel;
- vesa->bytes_per_scanline = fb->bytes_per_line;
- vesa->phys_base_ptr = fb->physical_address;
- vesa->red_mask_size = fb->red_mask_size;
- vesa->red_mask_pos = fb->red_mask_pos;
- vesa->green_mask_size = fb->green_mask_size;
- vesa->green_mask_pos = fb->green_mask_pos;
- vesa->blue_mask_size = fb->blue_mask_size;
- vesa->blue_mask_pos = fb->blue_mask_pos;
- vesa->reserved_mask_size = fb->reserved_mask_size;
- vesa->reserved_mask_pos = fb->reserved_mask_pos;
-}
-
-static int parse_coreboot_table_fb(GraphicDevice *gdev)
-{
- struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
-
- /* If there is no framebuffer structure, bail out and keep
- * running on the serial console.
- */
- if (!fb)
- return 0;
-
- gdev->winSizeX = fb->x_resolution;
- gdev->winSizeY = fb->y_resolution;
-
- gdev->plnSizeX = fb->x_resolution;
- gdev->plnSizeY = fb->y_resolution;
-
- gdev->gdfBytesPP = fb->bits_per_pixel / 8;
-
- switch (fb->bits_per_pixel) {
- case 24:
- gdev->gdfIndex = GDF_32BIT_X888RGB;
- break;
- case 16:
- gdev->gdfIndex = GDF_16BIT_565RGB;
- break;
- default:
- gdev->gdfIndex = GDF__8BIT_INDEX;
- break;
- }
-
- gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
- gdev->pciBase = (unsigned int)fb->physical_address;
-
- gdev->frameAdrs = (unsigned int)fb->physical_address;
- gdev->memSize = fb->bytes_per_line * fb->y_resolution;
-
- gdev->vprBase = (unsigned int)fb->physical_address;
- gdev->cprBase = (unsigned int)fb->physical_address;
-
- return 1;
-}
-
-void *video_hw_init(void)
-{
- GraphicDevice *gdev = &ctfb;
- int bits_per_pixel;
-
- printf("Video: ");
-
- if (!parse_coreboot_table_fb(gdev)) {
- printf("No video mode configured in coreboot!\n");
- return NULL;
- }
-
- bits_per_pixel = gdev->gdfBytesPP * 8;
-
- /* fill in Graphic device struct */
- sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
- bits_per_pixel);
- printf("%s\n", gdev->modeIdent);
-
- memset((void *)gdev->pciBase, 0,
- gdev->winSizeX * gdev->winSizeY * gdev->gdfBytesPP);
-
- /* Initialize vesa_mode_info structure */
- save_vesa_mode();
-
- return (void *)gdev;
-}
diff --git a/drivers/video/ct69000.c b/drivers/video/ct69000.c
index 22b3441..a74e4e6 100644
--- a/drivers/video/ct69000.c
+++ b/drivers/video/ct69000.c
@@ -804,84 +804,6 @@
#endif
-#ifdef CONFIG_VIDEO_HW_CURSOR
-/***************************************************************
- * Set Hardware Cursor in Pixel
- */
-void
-video_set_hw_cursor (int x, int y)
-{
- int sig_x = 0, sig_y = 0;
- if (x < 0) {
- x *= -1;
- sig_x = 1;
- }
- if (y < 0) {
- y *= -1;
- sig_y = 1;
- }
- ctWrite_i (CT_XR_O, 0xa4, x & 0xff);
- ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7);
- ctWrite_i (CT_XR_O, 0xa6, y & 0xff);
- ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7);
-}
-
-/***************************************************************
- * Init Hardware Cursor. To know the size of the Cursor,
- * we have to know the Font size.
- */
-void
-video_init_hw_cursor (int font_width, int font_height)
-{
- unsigned char xr_80;
- unsigned long *curs, pattern;
- int i;
- int cursor_start;
- GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-
- cursor_start = pGD->dprBase;
- xr_80 = ctRead_i (CT_XR_O, 0x80);
- /* set start address */
- ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0);
- ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f);
- /* set cursor shape */
- curs = (unsigned long *) cursor_start;
- i = 0;
- while (i < 0x400) {
- curs[i++] = 0xffffffff; /* AND mask */
- curs[i++] = 0xffffffff; /* AND mask */
- curs[i++] = 0; /* XOR mask */
- curs[i++] = 0; /* XOR mask */
- /* Transparent */
- }
- pattern = 0xffffffff >> font_width;
- i = 0;
- while (i < (font_height * 2)) {
- curs[i++] = pattern; /* AND mask */
- curs[i++] = pattern; /* AND mask */
- curs[i++] = 0; /* XOR mask */
- curs[i++] = 0; /* XOR mask */
- /* Cursor Color 0 */
- }
- /* set blink rate */
- ctWrite_i (CT_FP_O, 0x19, 0xf);
-
- /* set cursors colors */
- xr_80 = ctRead_i (CT_XR_O, 0x80);
- xr_80 |= 0x1; /* alternate palette select */
- ctWrite_i (CT_XR_O, 0x80, xr_80);
- video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL);
- /* position 4 is color 0 cursor 0 */
- xr_80 &= 0xfe; /* normal palette select */
- ctWrite_i (CT_XR_O, 0x80, xr_80);
- /* cursor enable */
- ctWrite_i (CT_XR_O, 0xa0, 0x91);
- xr_80 |= 0x10; /* enable hwcursor */
- ctWrite_i (CT_XR_O, 0x80, xr_80);
- video_set_hw_cursor (0, 0);
-}
-#endif /* CONFIG_VIDEO_HW_CURSOR */
-
/***************************************************************
* Wait for BitBlt ready
*/
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 468f385d..bbd384d 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -19,7 +19,7 @@
#include <linux/list.h>
#include <linux/fb.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
index e4763de..e752eb0 100644
--- a/drivers/video/display-uclass.c
+++ b/drivers/video/display-uclass.c
@@ -23,10 +23,19 @@
const struct display_timing *timing)
{
struct dm_display_ops *ops = display_get_ops(dev);
+ struct display_plat *disp_uc_plat;
+ int ret;
if (!ops || !ops->enable)
return -ENOSYS;
- return ops->enable(dev, panel_bpp, timing);
+ ret = ops->enable(dev, panel_bpp, timing);
+ if (ret)
+ return ret;
+
+ disp_uc_plat = dev_get_uclass_platdata(dev);
+ disp_uc_plat->in_use = true;
+
+ return 0;
}
int display_read_timing(struct udevice *dev, struct display_timing *timing)
@@ -48,6 +57,13 @@
return edid_get_timing(buf, ret, timing, &panel_bits_per_colour);
}
+bool display_in_use(struct udevice *dev)
+{
+ struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+
+ return disp_uc_plat->in_use;
+}
+
UCLASS_DRIVER(display) = {
.id = UCLASS_DISPLAY,
.name = "display",
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c
index f978473..aae78a8 100644
--- a/drivers/video/exynos/exynos_dp_lowlevel.c
+++ b/drivers/video/exynos/exynos_dp_lowlevel.c
@@ -881,11 +881,7 @@
unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs)
{
- unsigned int reg;
-
- reg = readl(&dp_regs->lane_count_set);
-
- return reg;
+ return readl(&dp_regs->lane_count_set);
}
unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index 97228cd..5483d66 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -27,7 +27,7 @@
#include <asm/arch/pinmux.h>
#include <asm/arch/system.h>
#include <asm/gpio.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/video/imx25lcdc.c b/drivers/video/imx25lcdc.c
deleted file mode 100644
index ef5767b..0000000
--- a/drivers/video/imx25lcdc.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2011
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * imx25lcdc.c - Graphic interface for i.MX25 lcd controller
- */
-
-#include <common.h>
-
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <video_fb.h>
-#include "videomodes.h"
-
-/*
- * 4MB (at the end of system RAM)
- */
-#define VIDEO_MEM_SIZE 0x400000
-
-#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */
-
-/*
- * Graphic Device
- */
-static GraphicDevice imx25fb;
-
-void *video_hw_init(void)
-{
- struct lcdc_regs *lcdc = (struct lcdc_regs *)IMX_LCDC_BASE;
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
- GraphicDevice *pGD = &imx25fb;
- char *s;
- u32 *videomem;
-
- memset(pGD, 0, sizeof(GraphicDevice));
-
- pGD->gdfIndex = GDF_16BIT_565RGB;
- pGD->gdfBytesPP = 2;
- pGD->memSize = VIDEO_MEM_SIZE;
- pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
-
- videomem = (u32 *)pGD->frameAdrs;
-
- s = getenv("videomode");
- if (s != NULL) {
- struct ctfb_res_modes var_mode;
- u32 lsr, lpcr, lhcr, lvcr;
- unsigned long div;
- int bpp;
-
- /* Disable all clocks of the LCDC */
- writel(readl(&ccm->cgr0) & ~((1<<7) | (1<<24)), &ccm->cgr0);
- writel(readl(&ccm->cgr1) & ~(1<<29), &ccm->cgr1);
-
- bpp = video_get_params(&var_mode, s);
-
- if (bpp == 0) {
- var_mode.xres = 320;
- var_mode.yres = 240;
- var_mode.pixclock = 154000;
- var_mode.left_margin = 68;
- var_mode.right_margin = 20;
- var_mode.upper_margin = 4;
- var_mode.lower_margin = 18;
- var_mode.hsync_len = 40;
- var_mode.vsync_len = 6;
- var_mode.sync = 0;
- var_mode.vmode = 0;
- }
-
- /* Fill memory with white */
- memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2);
-
- imx25fb.winSizeX = var_mode.xres;
- imx25fb.winSizeY = var_mode.yres;
-
- /* LCD base clock is 66.6MHZ. We do calculations in kHz */
- div = 66000 / (1000000000L / var_mode.pixclock);
- if (div > 63)
- div = 63;
- if (0 == div)
- div = 1;
-
- lsr = ((var_mode.xres / 16) << 20) |
- var_mode.yres;
- lpcr = (1 << 31) |
- (1 << 30) |
- (5 << 25) |
- (1 << 23) |
- (1 << 22) |
- (1 << 19) |
- (1 << 7) |
- div;
- lhcr = (var_mode.right_margin << 0) |
- (var_mode.left_margin << 8) |
- (var_mode.hsync_len << 26);
-
- lvcr = (var_mode.lower_margin << 0) |
- (var_mode.upper_margin << 8) |
- (var_mode.vsync_len << 26);
-
- writel((uint32_t)videomem, &lcdc->lssar);
- writel(lsr, &lcdc->lsr);
- writel(var_mode.xres * 2 / 4, &lcdc->lvpwr);
- writel(lpcr, &lcdc->lpcr);
- writel(lhcr, &lcdc->lhcr);
- writel(lvcr, &lcdc->lvcr);
- writel(0x00040060, &lcdc->ldcr);
-
- writel(0xA90300, &lcdc->lpccr);
-
- /* Ensable all clocks of the LCDC */
- writel(readl(&ccm->cgr0) | ((1<<7) | (1<<24)), &ccm->cgr0);
- writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1);
- }
-
- return pGD;
-}
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 5676a0f..f8d4488 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -16,7 +16,7 @@
#include <linux/types.h>
#include <linux/err.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <div64.h>
diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c
index cbac9f7..47d7417 100644
--- a/drivers/video/ipu_disp.c
+++ b/drivers/video/ipu_disp.c
@@ -15,7 +15,7 @@
#include <common.h>
#include <linux/types.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c
new file mode 100644
index 0000000..94db3dd
--- /dev/null
+++ b/drivers/video/ivybridge_igd.c
@@ -0,0 +1,843 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pci_rom.h>
+#include <vbe.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/mtrr.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+struct gt_powermeter {
+ u16 reg;
+ u32 value;
+};
+
+/* These are magic values - unfortunately the meaning is unknown */
+static const struct gt_powermeter snb_pm_gt1[] = {
+ { 0xa200, 0xcc000000 },
+ { 0xa204, 0x07000040 },
+ { 0xa208, 0x0000fe00 },
+ { 0xa20c, 0x00000000 },
+ { 0xa210, 0x17000000 },
+ { 0xa214, 0x00000021 },
+ { 0xa218, 0x0817fe19 },
+ { 0xa21c, 0x00000000 },
+ { 0xa220, 0x00000000 },
+ { 0xa224, 0xcc000000 },
+ { 0xa228, 0x07000040 },
+ { 0xa22c, 0x0000fe00 },
+ { 0xa230, 0x00000000 },
+ { 0xa234, 0x17000000 },
+ { 0xa238, 0x00000021 },
+ { 0xa23c, 0x0817fe19 },
+ { 0xa240, 0x00000000 },
+ { 0xa244, 0x00000000 },
+ { 0xa248, 0x8000421e },
+ { 0 }
+};
+
+static const struct gt_powermeter snb_pm_gt2[] = {
+ { 0xa200, 0x330000a6 },
+ { 0xa204, 0x402d0031 },
+ { 0xa208, 0x00165f83 },
+ { 0xa20c, 0xf1000000 },
+ { 0xa210, 0x00000000 },
+ { 0xa214, 0x00160016 },
+ { 0xa218, 0x002a002b },
+ { 0xa21c, 0x00000000 },
+ { 0xa220, 0x00000000 },
+ { 0xa224, 0x330000a6 },
+ { 0xa228, 0x402d0031 },
+ { 0xa22c, 0x00165f83 },
+ { 0xa230, 0xf1000000 },
+ { 0xa234, 0x00000000 },
+ { 0xa238, 0x00160016 },
+ { 0xa23c, 0x002a002b },
+ { 0xa240, 0x00000000 },
+ { 0xa244, 0x00000000 },
+ { 0xa248, 0x8000421e },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt1[] = {
+ { 0xa800, 0x00000000 },
+ { 0xa804, 0x00021c00 },
+ { 0xa808, 0x00000403 },
+ { 0xa80c, 0x02001700 },
+ { 0xa810, 0x05000200 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00690500 },
+ { 0xa81c, 0x0000007f },
+ { 0xa820, 0x01002501 },
+ { 0xa824, 0x00000300 },
+ { 0xa828, 0x01000331 },
+ { 0xa82c, 0x0000000c },
+ { 0xa830, 0x00010016 },
+ { 0xa834, 0x01100101 },
+ { 0xa838, 0x00010103 },
+ { 0xa83c, 0x00041300 },
+ { 0xa840, 0x00000b30 },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0x7f000000 },
+ { 0xa84c, 0x05000008 },
+ { 0xa850, 0x00000001 },
+ { 0xa854, 0x00000004 },
+ { 0xa858, 0x00000007 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00010000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00001c00 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x06000000 },
+ { 0xa910, 0x09000200 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00590000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x04002501 },
+ { 0xa924, 0x00000100 },
+ { 0xa928, 0x03000410 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00020000 },
+ { 0xa934, 0x02070106 },
+ { 0xa938, 0x00010100 },
+ { 0xa93c, 0x00401c00 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x10000e00 },
+ { 0xa94c, 0x02000004 },
+ { 0xa950, 0x00000001 },
+ { 0xa954, 0x00000004 },
+ { 0xa960, 0x00060000 },
+ { 0xaa3c, 0x00001c00 },
+ { 0xaa54, 0x00000004 },
+ { 0xaa60, 0x00060000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2[] = {
+ { 0xa800, 0x10000000 },
+ { 0xa804, 0x00033800 },
+ { 0xa808, 0x00000902 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x12000400 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20800 },
+ { 0xa81c, 0x00000002 },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00010032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x0000151d },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0x20001b00 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000000 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x00000008 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003500 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000500 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000200 },
+ { 0xa928, 0x07000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x050f020d },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_17w[] = {
+ { 0xa800, 0x20000000 },
+ { 0xa804, 0x000e3800 },
+ { 0xa808, 0x00000806 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x0c000800 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20d00 },
+ { 0xa81c, 0x000000ff },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00020032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x000016ff },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0xff000000 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000002 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x0000000f },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003800 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000800 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000300 },
+ { 0xa928, 0x01000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x15150406 },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_35w[] = {
+ { 0xa800, 0x00000000 },
+ { 0xa804, 0x00030400 },
+ { 0xa808, 0x00000806 },
+ { 0xa80c, 0x0c002f00 },
+ { 0xa810, 0x0c000300 },
+ { 0xa814, 0x00000000 },
+ { 0xa818, 0x00d20d00 },
+ { 0xa81c, 0x000000ff },
+ { 0xa820, 0x03004b02 },
+ { 0xa824, 0x00000600 },
+ { 0xa828, 0x07000773 },
+ { 0xa82c, 0x00000000 },
+ { 0xa830, 0x00020032 },
+ { 0xa834, 0x1520040d },
+ { 0xa838, 0x00020105 },
+ { 0xa83c, 0x00083700 },
+ { 0xa840, 0x000016ff },
+ { 0xa844, 0x00000000 },
+ { 0xa848, 0xff000000 },
+ { 0xa84c, 0x0a000010 },
+ { 0xa850, 0x00000001 },
+ { 0xa854, 0x00000008 },
+ { 0xa858, 0x00000008 },
+ { 0xa85c, 0x00000000 },
+ { 0xa860, 0x00020000 },
+ { 0xa248, 0x0000221e },
+ { 0xa900, 0x00000000 },
+ { 0xa904, 0x00003800 },
+ { 0xa908, 0x00000000 },
+ { 0xa90c, 0x0c000000 },
+ { 0xa910, 0x12000800 },
+ { 0xa914, 0x00000000 },
+ { 0xa918, 0x00b20000 },
+ { 0xa91c, 0x00000000 },
+ { 0xa920, 0x08004b02 },
+ { 0xa924, 0x00000300 },
+ { 0xa928, 0x01000820 },
+ { 0xa92c, 0x00000000 },
+ { 0xa930, 0x00030000 },
+ { 0xa934, 0x15150406 },
+ { 0xa938, 0x00020300 },
+ { 0xa93c, 0x00903900 },
+ { 0xa940, 0x00000000 },
+ { 0xa944, 0x00000000 },
+ { 0xa948, 0x20001b00 },
+ { 0xa94c, 0x0a000010 },
+ { 0xa950, 0x00000000 },
+ { 0xa954, 0x00000008 },
+ { 0xa960, 0x00110000 },
+ { 0xaa3c, 0x00003900 },
+ { 0xaa54, 0x00000008 },
+ { 0xaa60, 0x00110000 },
+ { 0 }
+};
+
+static inline u32 gtt_read(void *bar, u32 reg)
+{
+ return readl(bar + reg);
+}
+
+static inline void gtt_write(void *bar, u32 reg, u32 data)
+{
+ writel(data, bar + reg);
+}
+
+static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
+{
+ for (; pm && pm->reg; pm++)
+ gtt_write(bar, pm->reg, pm->value);
+}
+
+#define GTT_RETRY 1000
+static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
+{
+ unsigned try = GTT_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = gtt_read(bar, reg);
+ if ((data & mask) == value)
+ return 1;
+ udelay(10);
+ }
+
+ printf("GT init timeout\n");
+ return 0;
+}
+
+static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
+{
+ u32 reg32;
+
+ debug("GT Power Management Init, silicon = %#x\n", rev);
+
+ if (rev < IVB_STEP_C0) {
+ /* 1: Enable force wake */
+ gtt_write(gtt_bar, 0xa18c, 0x00000001);
+ gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
+ } else {
+ gtt_write(gtt_bar, 0xa180, 1 << 5);
+ gtt_write(gtt_bar, 0xa188, 0xffff0001);
+ gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
+ }
+
+ if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
+ /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
+ reg32 = gtt_read(gtt_bar, 0x42004);
+ reg32 |= (1 << 14) | (1 << 15);
+ gtt_write(gtt_bar, 0x42004, reg32);
+ }
+
+ if (rev >= IVB_STEP_A0) {
+ /* Display Reset Acknowledge Settings */
+ reg32 = gtt_read(gtt_bar, 0x45010);
+ reg32 |= (1 << 1) | (1 << 0);
+ gtt_write(gtt_bar, 0x45010, reg32);
+ }
+
+ /* 2: Get GT SKU from GTT+0x911c[13] */
+ reg32 = gtt_read(gtt_bar, 0x911c);
+ if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (reg32 & (1 << 13)) {
+ debug("SNB GT1 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, snb_pm_gt1);
+ } else {
+ debug("SNB GT2 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, snb_pm_gt2);
+ }
+ } else {
+ u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
+
+ if (reg32 & (1 << 13)) {
+ /* GT1 SKU */
+ debug("IVB GT1 Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
+ } else {
+ /* GT2 SKU */
+ u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
+ tdp /= (1 << unit);
+
+ if (tdp <= 17) {
+ /* <=17W ULV */
+ debug("IVB GT2 17W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
+ } else if ((tdp >= 25) && (tdp <= 35)) {
+ /* 25W-35W */
+ debug("IVB GT2 25W-35W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
+ } else {
+ /* All others */
+ debug("IVB GT2 35W Power Meter Weights\n");
+ gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
+ }
+ }
+ }
+
+ /* 3: Gear ratio map */
+ gtt_write(gtt_bar, 0xa004, 0x00000010);
+
+ /* 4: GFXPAUSE */
+ gtt_write(gtt_bar, 0xa000, 0x00070020);
+
+ /* 5: Dynamic EU trip control */
+ gtt_write(gtt_bar, 0xa080, 0x00000004);
+
+ /* 6: ECO bits */
+ reg32 = gtt_read(gtt_bar, 0xa180);
+ reg32 |= (1 << 26) | (1 << 31);
+ /* (bit 20=1 for SNB step D1+ / IVB A0+) */
+ if (rev >= SNB_STEP_D1)
+ reg32 |= (1 << 20);
+ gtt_write(gtt_bar, 0xa180, reg32);
+
+ /* 6a: for SnB step D2+ only */
+ if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
+ (rev >= SNB_STEP_D2)) {
+ reg32 = gtt_read(gtt_bar, 0x9400);
+ reg32 |= (1 << 7);
+ gtt_write(gtt_bar, 0x9400, reg32);
+
+ reg32 = gtt_read(gtt_bar, 0x941c);
+ reg32 &= 0xf;
+ reg32 |= (1 << 1);
+ gtt_write(gtt_bar, 0x941c, reg32);
+ gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
+ }
+
+ if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
+ reg32 = gtt_read(gtt_bar, 0x907c);
+ reg32 |= (1 << 16);
+ gtt_write(gtt_bar, 0x907c, reg32);
+
+ /* 6b: Clocking reset controls */
+ gtt_write(gtt_bar, 0x9424, 0x00000001);
+ } else {
+ /* 6b: Clocking reset controls */
+ gtt_write(gtt_bar, 0x9424, 0x00000000);
+ }
+
+ /* 7 */
+ if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
+ gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
+ /* Mailbox Cmd for RC6 VID */
+ gtt_write(gtt_bar, 0x138124, 0x80000004);
+ if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
+ gtt_write(gtt_bar, 0x138124, 0x8000000a);
+ gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
+ }
+
+ /* 8 */
+ gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
+ gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
+ gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
+ gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
+
+ /* 9 */
+ gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
+ gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
+ gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
+
+ /* 10 */
+ gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
+ gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
+ gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
+ gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
+ gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
+
+ /* 11 */
+ gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
+ gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
+ gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
+ gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
+ gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
+ gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
+ gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
+
+ /* 11a: Enable Render Standby (RC6) */
+ if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
+ /*
+ * IvyBridge should also support DeepRenderStandby.
+ *
+ * Unfortunately it does not work reliably on all SKUs so
+ * disable it here and it can be enabled by the kernel.
+ */
+ gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
+ } else {
+ gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
+ }
+
+ /* 12: Normal Frequency Request */
+ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
+ reg32 = readl(MCHBAR_REG(0x5998));
+ reg32 >>= 16;
+ reg32 &= 0xef;
+ reg32 <<= 25;
+ gtt_write(gtt_bar, 0xa008, reg32);
+
+ /* 13: RP Control */
+ gtt_write(gtt_bar, 0xa024, 0x00000592);
+
+ /* 14: Enable PM Interrupts */
+ gtt_write(gtt_bar, 0x4402c, 0x03000076);
+
+ /* Clear 0x6c024 [8:6] */
+ reg32 = gtt_read(gtt_bar, 0x6c024);
+ reg32 &= ~0x000001c0;
+ gtt_write(gtt_bar, 0x6c024, reg32);
+
+ return 0;
+}
+
+static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
+{
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ u32 reg32, cycle_delay;
+
+ debug("GT Power Management Init (post VBIOS)\n");
+
+ /* 15: Deassert Force Wake */
+ if (rev < IVB_STEP_C0) {
+ gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
+ gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
+ } else {
+ gtt_write(gtt_bar, 0xa188, 0x1fffe);
+ if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
+ gtt_write(gtt_bar, 0xa188,
+ gtt_read(gtt_bar, 0xa188) | 1);
+ }
+ }
+
+ /* 16: SW RC Control */
+ gtt_write(gtt_bar, 0xa094, 0x00060000);
+
+ /* Setup Digital Port Hotplug */
+ reg32 = gtt_read(gtt_bar, 0xc4030);
+ if (!reg32) {
+ u32 dp_hotplug[3];
+
+ if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
+ dp_hotplug, ARRAY_SIZE(dp_hotplug)))
+ return -EINVAL;
+
+ reg32 = (dp_hotplug[0] & 0x7) << 2;
+ reg32 |= (dp_hotplug[0] & 0x7) << 10;
+ reg32 |= (dp_hotplug[0] & 0x7) << 18;
+ gtt_write(gtt_bar, 0xc4030, reg32);
+ }
+
+ /* Setup Panel Power On Delays */
+ reg32 = gtt_read(gtt_bar, 0xc7208);
+ if (!reg32) {
+ reg32 = (unsigned)fdtdec_get_int(blob, node,
+ "panel-port-select", 0) << 30;
+ reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
+ << 16;
+ reg32 |= fdtdec_get_int(blob, node,
+ "panel-power-backlight-on-delay", 0);
+ gtt_write(gtt_bar, 0xc7208, reg32);
+ }
+
+ /* Setup Panel Power Off Delays */
+ reg32 = gtt_read(gtt_bar, 0xc720c);
+ if (!reg32) {
+ reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
+ << 16;
+ reg32 |= fdtdec_get_int(blob, node,
+ "panel-power-backlight-off-delay", 0);
+ gtt_write(gtt_bar, 0xc720c, reg32);
+ }
+
+ /* Setup Panel Power Cycle Delay */
+ cycle_delay = fdtdec_get_int(blob, node,
+ "intel,panel-power-cycle-delay", 0);
+ if (cycle_delay) {
+ reg32 = gtt_read(gtt_bar, 0xc7210);
+ reg32 &= ~0xff;
+ reg32 |= cycle_delay;
+ gtt_write(gtt_bar, 0xc7210, reg32);
+ }
+
+ /* Enable Backlight if needed */
+ reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
+ if (reg32) {
+ gtt_write(gtt_bar, 0x48250, (1 << 31));
+ gtt_write(gtt_bar, 0x48254, reg32);
+ }
+ reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
+ if (reg32) {
+ gtt_write(gtt_bar, 0xc8250, (1 << 31));
+ gtt_write(gtt_bar, 0xc8254, reg32);
+ }
+
+ return 0;
+}
+
+/*
+ * Some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ */
+
+uint32_t board_map_oprom_vendev(uint32_t vendev)
+{
+ switch (vendev) {
+ case 0x80860102: /* GT1 Desktop */
+ case 0x8086010a: /* GT1 Server */
+ case 0x80860112: /* GT2 Desktop */
+ case 0x80860116: /* GT2 Mobile */
+ case 0x80860122: /* GT2 Desktop >=1.3GHz */
+ case 0x80860126: /* GT2 Mobile >=1.3GHz */
+ case 0x80860156: /* IVB */
+ case 0x80860166: /* IVB */
+ return 0x80860106; /* GT1 Mobile */
+ }
+
+ return vendev;
+}
+
+static int int15_handler(void)
+{
+ int res = 0;
+
+ debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0x00; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000; /* Use video bios default */
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0003; /* eDP */
+ res = 1;
+ break;
+ case 0x5f70:
+ switch (M.x86.R_CH) {
+ case 0:
+ /* Get Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ debug("Unknown INT15 5f70 function: 0x%02x\n",
+ M.x86.R_CH);
+ break;
+ }
+ break;
+ case 0x5fac:
+ res = 1;
+ break;
+ default:
+ debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
+ break;
+ }
+ return res;
+}
+
+static void sandybridge_setup_graphics(struct udevice *dev,
+ struct udevice *video_dev)
+{
+ u32 reg32;
+ u16 reg16;
+ u8 reg8;
+
+ dm_pci_read_config16(video_dev, PCI_DEVICE_ID, ®16);
+ switch (reg16) {
+ case 0x0102: /* GT1 Desktop */
+ case 0x0106: /* GT1 Mobile */
+ case 0x010a: /* GT1 Server */
+ case 0x0112: /* GT2 Desktop */
+ case 0x0116: /* GT2 Mobile */
+ case 0x0122: /* GT2 Desktop >=1.3GHz */
+ case 0x0126: /* GT2 Mobile >=1.3GHz */
+ case 0x0156: /* IvyBridge */
+ case 0x0166: /* IvyBridge */
+ break;
+ default:
+ debug("Graphics not supported by this CPU/chipset\n");
+ return;
+ }
+
+ debug("Initialising Graphics\n");
+
+ /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+ dm_pci_read_config16(dev, GGC, ®16);
+ reg16 &= ~0x00f8;
+ reg16 |= 1 << 3;
+ /* Program GTT memory by setting GGC[9:8] = 2MB */
+ reg16 &= ~0x0300;
+ reg16 |= 2 << 8;
+ /* Enable VGA decode */
+ reg16 &= ~0x0002;
+ dm_pci_write_config16(dev, GGC, reg16);
+
+ /* Enable 256MB aperture */
+ dm_pci_read_config8(video_dev, MSAC, ®8);
+ reg8 &= ~0x06;
+ reg8 |= 0x02;
+ dm_pci_write_config8(video_dev, MSAC, reg8);
+
+ /* Erratum workarounds */
+ reg32 = readl(MCHBAR_REG(0x5f00));
+ reg32 |= (1 << 9) | (1 << 10);
+ writel(reg32, MCHBAR_REG(0x5f00));
+
+ /* Enable SA Clock Gating */
+ reg32 = readl(MCHBAR_REG(0x5f00));
+ writel(reg32 | 1, MCHBAR_REG(0x5f00));
+
+ /* GPU RC6 workaround for sighting 366252 */
+ reg32 = readl(MCHBAR_REG(0x5d14));
+ reg32 |= (1 << 31);
+ writel(reg32, MCHBAR_REG(0x5d14));
+
+ /* VLW */
+ reg32 = readl(MCHBAR_REG(0x6120));
+ reg32 &= ~(1 << 0);
+ writel(reg32, MCHBAR_REG(0x6120));
+
+ reg32 = readl(MCHBAR_REG(0x5418));
+ reg32 |= (1 << 4) | (1 << 5);
+ writel(reg32, MCHBAR_REG(0x5418));
+}
+
+static int gma_func0_init(struct udevice *dev)
+{
+ struct udevice *nbridge;
+ void *gtt_bar;
+ ulong base;
+ u32 reg32;
+ int ret;
+ int rev;
+
+ /* Enable PCH Display Port */
+ writew(0x0010, RCB_REG(DISPBDF));
+ setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
+
+ ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
+ if (ret)
+ return ret;
+ rev = bridge_silicon_revision(nbridge);
+ sandybridge_setup_graphics(nbridge, dev);
+
+ /* IGD needs to be Bus Master */
+ dm_pci_read_config32(dev, PCI_COMMAND, ®32);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ dm_pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* Use write-combining for the graphics memory, 256MB */
+ base = dm_pci_read_bar32(dev, 2);
+ mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
+ mtrr_commit(true);
+
+ gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
+ debug("GT bar %p\n", gtt_bar);
+ ret = gma_pm_init_pre_vbios(gtt_bar, rev);
+ if (ret)
+ return ret;
+
+ return rev;
+}
+
+static int bd82x6x_video_probe(struct udevice *dev)
+{
+ void *gtt_bar;
+ int ret, rev;
+
+ rev = gma_func0_init(dev);
+ if (rev < 0)
+ return rev;
+ ret = vbe_setup_video(dev, int15_handler);
+ if (ret)
+ return ret;
+
+ /* Post VBIOS init */
+ gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
+ ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id bd82x6x_video_ids[] = {
+ { .compatible = "intel,gma" },
+ { }
+};
+
+U_BOOT_DRIVER(bd82x6x_video) = {
+ .name = "bd82x6x_video",
+ .id = UCLASS_VIDEO,
+ .of_match = bd82x6x_video_ids,
+ .probe = bd82x6x_video_probe,
+};
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index 3f10d5c..51d06d6 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -12,7 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include "videomodes.h"
diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
index 265274b..0d0a0a9 100644
--- a/drivers/video/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc_ipuv3_fb.c
@@ -12,7 +12,7 @@
*/
#include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/global_data.h>
#include <linux/string.h>
#include <linux/list.h>
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index ddbb118..3cc03ca 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -12,7 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/imx-common/dma.h>
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 7976c5e..032b1de 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -132,8 +132,8 @@
static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts)
{
- u8 cts3;
- u8 n3;
+ uint cts3;
+ uint n3;
/* first set ncts_atomic_write (if present) */
n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
@@ -199,7 +199,7 @@
static void hdmi_video_sample(struct rk3288_hdmi *regs)
{
u32 color_format = 0x01;
- u8 val;
+ uint val;
val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
@@ -256,7 +256,7 @@
u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
u32 color_depth = 0;
- u8 val, vp_conf;
+ uint val, vp_conf;
/* set the packetizer registers */
val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
@@ -297,7 +297,7 @@
output_select);
}
-static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, u8 bit)
+static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit)
{
clrsetbits_le32(®s->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
@@ -382,7 +382,7 @@
static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock)
{
ulong start;
- u8 i, val;
+ uint i, val;
writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
®s->mc_flowctrl);
@@ -481,8 +481,8 @@
static void hdmi_av_composer(struct rk3288_hdmi *regs,
const struct display_timing *edid)
{
- u8 mdataenablepolarity = 1;
- u8 inv_val;
+ bool mdataenablepolarity = true;
+ uint inv_val;
uint hbl;
uint vbl;
@@ -553,7 +553,7 @@
/* hdmi initialization step b.4 */
static void hdmi_enable_video_path(struct rk3288_hdmi *regs)
{
- u8 clkdis;
+ uint clkdis;
/* control period minimum duration */
writel(12, ®s->fc_ctrldur);
@@ -580,7 +580,7 @@
/* workaround to clear the overflow condition */
static void hdmi_clear_overflow(struct rk3288_hdmi *regs)
{
- u8 val, count;
+ uint val, count;
/* tmds software reset */
writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, ®s->mc_swrstz);
@@ -614,7 +614,7 @@
static void hdmi_init_interrupt(struct rk3288_hdmi *regs)
{
- u8 ih_mute;
+ uint ih_mute;
/*
* boot up defaults are:
@@ -650,11 +650,11 @@
writel(HDMI_IH_PHY_STAT0_HPD, ®s->ih_phy_stat0);
}
-static u8 hdmi_get_plug_in_status(struct rk3288_hdmi *regs)
+static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs)
{
- u8 val = readl(®s->phy_stat0) & HDMI_PHY_HPD;
+ uint val = readl(®s->phy_stat0) & HDMI_PHY_HPD;
- return !!(val);
+ return !!val;
}
static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs)
@@ -753,7 +753,7 @@
return edid_read_err;
}
-static u8 pre_buf[] = {
+static const u8 pre_buf[] = {
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
@@ -899,7 +899,8 @@
rk_setreg(&priv->grf->soc_con6, 1 << 15);
/* hdmi data from vop id */
- rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 4) : (1 << 4));
+ rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
+ (vop_id == 1) ? (1 << 4) : 0);
ret = hdmi_wait_for_hpd(priv->regs);
if (ret < 0) {
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index c6d88d9..eab5486 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -195,7 +195,6 @@
struct udevice *disp;
int ret, remote, i, offset;
struct display_plat *disp_uc_plat;
- struct udevice *dev_clk;
struct clk clk;
vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
@@ -222,6 +221,11 @@
disp_uc_plat = dev_get_uclass_platdata(disp);
debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
+ if (display_in_use(disp)) {
+ debug(" - device in use\n");
+ return -EBUSY;
+ }
+
disp_uc_plat->source_id = remote_vop_id;
disp_uc_plat->src_dev = dev;
@@ -238,11 +242,7 @@
return ret;
}
- ret = rockchip_get_clk(&dev_clk);
- if (!ret) {
- clk.id = DCLK_VOP0 + remote_vop_id;
- ret = clk_request(dev_clk, &clk);
- }
+ ret = clk_get_by_index(dev, 1, &clk);
if (!ret)
ret = clk_set_rate(&clk, timing.pixelclock.typ);
if (ret) {
@@ -316,6 +316,10 @@
/*
* Try all the ports until we find one that works. In practice this
* tries EDP first if available, then HDMI.
+ *
+ * Note that rockchip_vop_set_clk() always uses NPLL as the source
+ * clock so it is currently not possible to use more than one display
+ * device simultaneously.
*/
port = fdt_subnode_offset(blob, dev->of_offset, "port");
if (port < 0)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
deleted file mode 100644
index 521eb75..0000000
--- a/drivers/video/s3c-fb.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * S3C24x0 LCD driver
- *
- * NOTE: Only 16/24 bpp operation with TFT LCD is supported.
- *
- * Copyright (C) 2014 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <malloc.h>
-#include <video_fb.h>
-
-#include <asm/errno.h>
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-#include "videomodes.h"
-
-static GraphicDevice panel;
-
-/* S3C requires the FB to be 4MiB aligned. */
-#define S3CFB_ALIGN (4 << 20)
-
-#define S3CFB_LCDCON1_CLKVAL(x) ((x) << 8)
-#define S3CFB_LCDCON1_PNRMODE_TFT (0x3 << 5)
-#define S3CFB_LCDCON1_BPPMODE_TFT_16BPP (0xc << 1)
-#define S3CFB_LCDCON1_BPPMODE_TFT_24BPP (0xd << 1)
-
-#define S3CFB_LCDCON2_VBPD(x) ((x) << 24)
-#define S3CFB_LCDCON2_LINEVAL(x) ((x) << 14)
-#define S3CFB_LCDCON2_VFPD(x) ((x) << 6)
-#define S3CFB_LCDCON2_VSPW(x) ((x) << 0)
-
-#define S3CFB_LCDCON3_HBPD(x) ((x) << 19)
-#define S3CFB_LCDCON3_HOZVAL(x) ((x) << 8)
-#define S3CFB_LCDCON3_HFPD(x) ((x) << 0)
-
-#define S3CFB_LCDCON4_HSPW(x) ((x) << 0)
-
-#define S3CFB_LCDCON5_BPP24BL (1 << 12)
-#define S3CFB_LCDCON5_FRM565 (1 << 11)
-#define S3CFB_LCDCON5_HWSWP (1 << 0)
-
-#define PS2KHZ(ps) (1000000000UL / (ps))
-
-/*
- * Example:
- * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\
- * pclk:30066,le:41,ri:89,up:45,lo:12,
- * hs:1,vs:1,sync:100663296,vmode:0
- */
-static void s3c_lcd_init(GraphicDevice *panel,
- struct ctfb_res_modes *mode, int bpp)
-{
- uint32_t clk_divider;
- struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd();
-
- /* Stop the controller. */
- clrbits_le32(®s->lcdcon1, 1);
-
- /* Calculate clock divider. */
- clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000;
- clk_divider = DIV_ROUND_UP(clk_divider, 2);
- if (clk_divider)
- clk_divider -= 1;
-
- /* Program LCD configuration. */
- switch (bpp) {
- case 16:
- writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP |
- S3CFB_LCDCON1_PNRMODE_TFT |
- S3CFB_LCDCON1_CLKVAL(clk_divider),
- ®s->lcdcon1);
- writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565,
- ®s->lcdcon5);
- break;
- case 24:
- writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP |
- S3CFB_LCDCON1_PNRMODE_TFT |
- S3CFB_LCDCON1_CLKVAL(clk_divider),
- ®s->lcdcon1);
- writel(S3CFB_LCDCON5_BPP24BL, ®s->lcdcon5);
- break;
- }
-
- writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) |
- S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) |
- S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) |
- S3CFB_LCDCON2_VSPW(mode->vsync_len - 1),
- ®s->lcdcon2);
-
- writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) |
- S3CFB_LCDCON3_HFPD(mode->left_margin - 1) |
- S3CFB_LCDCON3_HOZVAL(mode->xres - 1),
- ®s->lcdcon3);
-
- writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1),
- ®s->lcdcon4);
-
- /* Write FB address. */
- writel(panel->frameAdrs >> 1, ®s->lcdsaddr1);
- writel((panel->frameAdrs +
- (mode->xres * mode->yres * panel->gdfBytesPP)) >> 1,
- ®s->lcdsaddr2);
- writel(mode->xres * bpp / 16, ®s->lcdsaddr3);
-
- /* Start the controller. */
- setbits_le32(®s->lcdcon1, 1);
-}
-
-void *video_hw_init(void)
-{
- int bpp = -1;
- char *penv;
- void *fb;
- struct ctfb_res_modes mode;
-
- puts("Video: ");
-
- /* Suck display configuration from "videomode" variable */
- penv = getenv("videomode");
- if (!penv) {
- puts("S3CFB: 'videomode' variable not set!\n");
- return NULL;
- }
-
- bpp = video_get_params(&mode, penv);
-
- /* fill in Graphic device struct */
- sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
-
- panel.winSizeX = mode.xres;
- panel.winSizeY = mode.yres;
- panel.plnSizeX = mode.xres;
- panel.plnSizeY = mode.yres;
-
- switch (bpp) {
- case 24:
- panel.gdfBytesPP = 4;
- panel.gdfIndex = GDF_32BIT_X888RGB;
- break;
- case 16:
- panel.gdfBytesPP = 2;
- panel.gdfIndex = GDF_16BIT_565RGB;
- break;
- default:
- printf("S3CFB: Invalid BPP specified! (bpp = %i)\n", bpp);
- return NULL;
- }
-
- panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
-
- /* Allocate framebuffer */
- fb = memalign(S3CFB_ALIGN, roundup(panel.memSize, S3CFB_ALIGN));
- if (!fb) {
- printf("S3CFB: Error allocating framebuffer!\n");
- return NULL;
- }
-
- /* Wipe framebuffer */
- memset(fb, 0, panel.memSize);
-
- panel.frameAdrs = (u32)fb;
-
- printf("%s\n", panel.modeIdent);
-
- /* Start framebuffer */
- s3c_lcd_init(&panel, &mode, bpp);
-
- return (void *)&panel;
-}
diff --git a/drivers/video/sed13806.c b/drivers/video/sed13806.c
deleted file mode 100644
index cd7fac6..0000000
--- a/drivers/video/sed13806.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* Video support for Epson SED13806 chipset */
-
-#include <common.h>
-
-#include <video_fb.h>
-#include <sed13806.h>
-
-#define readByte(ptrReg) \
- *(volatile unsigned char *)(sed13806.isaBase + ptrReg)
-
-#define writeByte(ptrReg,value) \
- *(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value
-
-#define writeWord(ptrReg,value) \
- (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00))
-
-GraphicDevice sed13806;
-
-/*-----------------------------------------------------------------------------
- * EpsonSetRegs --
- *-----------------------------------------------------------------------------
- */
-static void EpsonSetRegs (void)
-{
- /* the content of the chipset register depends on the board (clocks, ...)*/
- const S1D_REGS *preg = board_get_regs ();
- while (preg -> Index) {
- writeByte (preg -> Index, preg -> Value);
- preg ++;
- }
-}
-
-/*-----------------------------------------------------------------------------
- * video_hw_init --
- *-----------------------------------------------------------------------------
- */
-void *video_hw_init (void)
-{
- unsigned int *vm, i;
-
- memset (&sed13806, 0, sizeof (GraphicDevice));
-
- /* Initialization of the access to the graphic chipset
- Retreive base address of the chipset
- (see board/RPXClassic/eccx.c) */
- if ((sed13806.isaBase = board_video_init ()) == 0) {
- return (NULL);
- }
-
- sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET;
- sed13806.winSizeX = board_get_width ();
- sed13806.winSizeY = board_get_height ();
-
-#if defined(CONFIG_VIDEO_SED13806_8BPP)
- sed13806.gdfIndex = GDF__8BIT_INDEX;
- sed13806.gdfBytesPP = 1;
-
-#elif defined(CONFIG_VIDEO_SED13806_16BPP)
- sed13806.gdfIndex = GDF_16BIT_565RGB;
- sed13806.gdfBytesPP = 2;
-
-#else
-#error Unsupported SED13806 BPP
-#endif
-
- sed13806.memSize = sed13806.winSizeX * sed13806.winSizeY * sed13806.gdfBytesPP;
-
- /* Load SED registers */
- EpsonSetRegs ();
-
- /* (see board/RPXClassic/RPXClassic.c) */
- board_validate_screen (sed13806.isaBase);
-
- /* Clear video memory */
- i = sed13806.memSize/4;
- vm = (unsigned int *)sed13806.frameAdrs;
- while(i--)
- *vm++ = 0;
-
-
- return (&sed13806);
-}
-/*-----------------------------------------------------------------------------
- * Epson_wait_idle -- Wait for hardware to become idle
- *-----------------------------------------------------------------------------
- */
-static void Epson_wait_idle (void)
-{
- while (readByte (BLT_CTRL0) & 0x80);
-
- /* Read a word in the BitBLT memory area to shutdown the BitBLT engine */
- *(volatile unsigned short *)(sed13806.isaBase + BLT_REG);
-}
-
-/*-----------------------------------------------------------------------------
- * video_hw_bitblt --
- *-----------------------------------------------------------------------------
- */
-void video_hw_bitblt (
- unsigned int bpp, /* bytes per pixel */
- unsigned int src_x, /* source pos x */
- unsigned int src_y, /* source pos y */
- unsigned int dst_x, /* dest pos x */
- unsigned int dst_y, /* dest pos y */
- unsigned int dim_x, /* frame width */
- unsigned int dim_y /* frame height */
- )
-{
- register GraphicDevice *pGD = (GraphicDevice *)&sed13806;
- unsigned long srcAddr, dstAddr;
- unsigned int stride = bpp * pGD -> winSizeX;
-
- srcAddr = (src_y * stride) + (src_x * bpp);
- dstAddr = (dst_y * stride) + (dst_x * bpp);
-
- Epson_wait_idle ();
-
- writeByte(BLT_ROP,0x0C); /* source */
- writeByte(BLT_OP,0x02);/* move blit in positive direction with ROP */
- writeWord(BLT_MEM_OFF0, stride / 2);
- if (pGD -> gdfIndex == GDF__8BIT_INDEX) {
- writeByte(BLT_CTRL1,0x00);
- }
- else {
- writeByte(BLT_CTRL1,0x01);
- }
-
- writeWord(BLT_WIDTH0,(dim_x - 1));
- writeWord(BLT_HEIGHT0,(dim_y - 1));
-
- /* set up blit registers */
- writeByte(BLT_SRC_ADDR0,srcAddr);
- writeByte(BLT_SRC_ADDR1,srcAddr>>8);
- writeByte(BLT_SRC_ADDR2,srcAddr>>16);
-
- writeByte(BLT_DST_ADDR0,dstAddr);
- writeByte(BLT_DST_ADDR1,dstAddr>>8);
- writeByte(BLT_DST_ADDR2,dstAddr>>16);
-
- /* Engage the blt engine */
- /* rectangular region for src and dst */
- writeByte(BLT_CTRL0,0x80);
-
- /* wait untill current blits finished */
- Epson_wait_idle ();
-}
-/*-----------------------------------------------------------------------------
- * video_hw_rectfill --
- *-----------------------------------------------------------------------------
- */
-void video_hw_rectfill (
- unsigned int bpp, /* bytes per pixel */
- unsigned int dst_x, /* dest pos x */
- unsigned int dst_y, /* dest pos y */
- unsigned int dim_x, /* frame width */
- unsigned int dim_y, /* frame height */
- unsigned int color /* fill color */
- )
-{
- register GraphicDevice *pGD = (GraphicDevice *)&sed13806;
- unsigned long dstAddr;
- unsigned int stride = bpp * pGD -> winSizeX;
-
- dstAddr = (dst_y * stride) + (dst_x * bpp);
-
- Epson_wait_idle ();
-
- /* set up blit registers */
- writeByte(BLT_DST_ADDR0,dstAddr);
- writeByte(BLT_DST_ADDR1,dstAddr>>8);
- writeByte(BLT_DST_ADDR2,dstAddr>>16);
-
- writeWord(BLT_WIDTH0,(dim_x - 1));
- writeWord(BLT_HEIGHT0,(dim_y - 1));
- writeWord(BLT_FGCOLOR0,color);
-
- writeByte(BLT_OP,0x0C); /* solid fill */
- writeWord(BLT_MEM_OFF0,stride / 2);
-
- if (pGD -> gdfIndex == GDF__8BIT_INDEX) {
- writeByte(BLT_CTRL1,0x00);
- }
- else {
- writeByte(BLT_CTRL1,0x01);
- }
-
- /* Engage the blt engine */
- /* rectangular region for src and dst */
- writeByte(BLT_CTRL0,0x80);
-
- /* wait untill current blits finished */
- Epson_wait_idle ();
-}
-
-/*-----------------------------------------------------------------------------
- * video_set_lut --
- *-----------------------------------------------------------------------------
- */
-void video_set_lut (
- unsigned int index, /* color number */
- unsigned char r, /* red */
- unsigned char g, /* green */
- unsigned char b /* blue */
- )
-{
- writeByte(REG_LUT_ADDR, index );
- writeByte(REG_LUT_DATA, r);
- writeByte(REG_LUT_DATA, g);
- writeByte(REG_LUT_DATA, b);
-}
-#ifdef CONFIG_VIDEO_HW_CURSOR
-/*-----------------------------------------------------------------------------
- * video_set_hw_cursor --
- *-----------------------------------------------------------------------------
- */
-void video_set_hw_cursor (int x, int y)
-{
- writeByte (LCD_CURSOR_XL, (x & 0xff));
- writeByte (LCD_CURSOR_XM, (x >> 8));
- writeByte (LCD_CURSOR_YL, (y & 0xff));
- writeByte (LCD_CURSOR_YM, (y >> 8));
-}
-
-/*-----------------------------------------------------------------------------
- * video_init_hw_cursor --
- *-----------------------------------------------------------------------------
- */
-void video_init_hw_cursor (int font_width, int font_height)
-{
- volatile unsigned char *ptr;
- unsigned char pattern;
- int i;
-
-
- /* Init cursor content
- Cursor size is 64x64 pixels
- Start of the cursor memory depends on panel type (dual panel ...) */
- if ((i = readByte (LCD_CURSOR_START)) == 0) {
- ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE);
- }
- else {
- ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192));
- }
-
- /* Fill the first line and the first empty line after cursor */
- for (i = 0, pattern = 0; i < 64; i++) {
- if (i < font_width) {
- /* Invert background */
- pattern |= 0x3;
-
- }
- else {
- /* Background */
- pattern |= 0x2;
- }
- if ((i & 3) == 3) {
- *ptr = pattern;
- *(ptr + font_height * 16) = 0xaa;
- ptr ++;
- pattern = 0;
- }
- pattern <<= 2;
- }
-
- /* Duplicate this line */
- for (i = 1; i < font_height; i++) {
- memcpy ((void *)ptr, (void *)(ptr - 16), 16);
- ptr += 16;
- }
-
- for (; i < 64; i++) {
- memcpy ((void *)(ptr + 16), (void *)ptr, 16);
- ptr += 16;
- }
-
- /* Select cursor mode */
- writeByte (LCD_CURSOR_CNTL, 1);
-}
-#endif
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index b2fe345..baa95f6 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -42,7 +42,7 @@
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret) {
- debug("%s: Warning: cnnot get power supply: ret=%d\n",
+ debug("%s: Warning: cannot get power supply: ret=%d\n",
__func__, ret);
if (ret != -ENOENT)
return ret;
diff --git a/drivers/video/smiLynxEM.c b/drivers/video/smiLynxEM.c
deleted file mode 100644
index 1880ccc..0000000
--- a/drivers/video/smiLynxEM.c
+++ /dev/null
@@ -1,835 +0,0 @@
-/*
- * (C) Copyright 1997-2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * smiLynxEM.c
- *
- * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
- *
- * modification history
- * --------------------
- * 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
- *
- * 18-03-2004 - Unify videomodes handling with the ct69000
- * - The video output can be set via the variable "videoout"
- * in the environment.
- * videoout=1 output on LCD
- * videoout=2 output on CRT (default value)
- * <p.aubert@staubli.com>
- */
-
-#include <common.h>
-
-#include <pci.h>
-#include <video_fb.h>
-#include "videomodes.h"
-/*
- * Export Graphic Device
- */
-GraphicDevice smi;
-
-/*
- * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external
- */
-#define VIDEO_MEM_SIZE 0x400000
-
-
-/*
- * ISA mapped regs
- */
-#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */
-#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */
-#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */
-#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */
-#define SMI_ISR1 (pGD->isaBase + 0x03ca)
-#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */
-#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */
-#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */
-#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */
-#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */
-#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */
-#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/
-#define SMI_INDX_ATTR (pGD->isaBase + 0x03c0) /* attributes index reg */
-
-/*
- * Video processor control
- */
-typedef struct {
- unsigned int control;
- unsigned int colorKey;
- unsigned int colorKeyMask;
- unsigned int start;
- unsigned short offset;
- unsigned short width;
- unsigned int fifoPrio;
- unsigned int fifoERL;
- unsigned int YUVtoRGB;
-} SmiVideoProc;
-
-/*
- * Video window control
- */
-typedef struct {
- unsigned short top;
- unsigned short left;
- unsigned short bottom;
- unsigned short right;
- unsigned int srcStart;
- unsigned short width;
- unsigned short offset;
- unsigned char hStretch;
- unsigned char vStretch;
-} SmiVideoWin;
-
-/*
- * Capture port control
- */
-typedef struct {
- unsigned int control;
- unsigned short topClip;
- unsigned short leftClip;
- unsigned short srcHeight;
- unsigned short srcWidth;
- unsigned int srcBufStart1;
- unsigned int srcBufStart2;
- unsigned short srcOffset;
- unsigned short fifoControl;
-} SmiCapturePort;
-
-
-/*
- * Register values for common video modes
- */
-static char SMI_SCR[] = {
- /* all modes */
- 0x10, 0xff, 0x11, 0xff, 0x12, 0xff, 0x13, 0xff, 0x15, 0x90,
- 0x17, 0x20, 0x18, 0xb1, 0x19, 0x00,
-};
-static char SMI_EXT_CRT[] = {
- 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
- 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00,
-};
-static char SMI_ATTR [] = {
- 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05,
- 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0b,
- 0x0c, 0x0c, 0x0d, 0x0d, 0x0e, 0x0e, 0x0f, 0x0f, 0x10, 0x41, 0x11, 0x00,
- 0x12, 0x0f, 0x13, 0x00, 0x14, 0x00,
-};
-static char SMI_GCR[18] = {
- 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x40,
- 0x06, 0x05, 0x07, 0x0f, 0x08, 0xff,
-};
-static char SMI_SEQR[] = {
- 0x00, 0x00, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e, 0x00, 0x03,
-};
-static char SMI_PCR [] = {
- 0x20, 0x04, 0x21, 0x30, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00,
-};
-static char SMI_MCR[] = {
- 0x60, 0x01, 0x61, 0x00,
-};
-
-static char SMI_HCR[] = {
- 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
- 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00,
-};
-
-
-/*******************************************************************************
- *
- * Write SMI ISA register
- */
-static void smiWrite (unsigned short index, char reg, char val)
-{
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
-
- out8 ((pGD->isaBase + index), reg);
- out8 ((pGD->isaBase + index + 1), val);
-}
-
-/*******************************************************************************
- *
- * Write a table of SMI ISA register
- */
-static void smiLoadRegs (
- unsigned int iReg,
- unsigned int dReg,
- char *regTab,
- unsigned int tabSize
- )
-{
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
- register int i;
-
- for (i=0; i<tabSize; i+=2) {
- if (iReg == SMI_INDX_ATTR) {
- /* Reset the Flip Flop */
- in8 (SMI_ISR1);
- out8 (iReg, regTab[i]);
- out8 (iReg, regTab[i+1]);
- } else {
- out8 (iReg, regTab[i]);
- out8 (dReg, regTab[i+1]);
- }
- }
-}
-
-/*******************************************************************************
- *
- * Init capture port registers
- */
-static void smiInitCapturePort (void)
-{
- SmiCapturePort smiCP = { 0x01400600, 0x30, 0x40, 480, 640, 0, 0, 2560, 6 };
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
- register SmiCapturePort *pCP = (SmiCapturePort *)&smiCP;
-
- out32r ((pGD->cprBase + 0x0004), ((pCP->topClip<<16) | pCP->leftClip));
- out32r ((pGD->cprBase + 0x0008), ((pCP->srcHeight<<16) | pCP->srcWidth));
- out32r ((pGD->cprBase + 0x000c), pCP->srcBufStart1/8);
- out32r ((pGD->cprBase + 0x0010), pCP->srcBufStart2/8);
- out32r ((pGD->cprBase + 0x0014), pCP->srcOffset/8);
- out32r ((pGD->cprBase + 0x0018), pCP->fifoControl);
- out32r ((pGD->cprBase + 0x0000), pCP->control);
-}
-
-
-/*******************************************************************************
- *
- * Init video processor registers
- */
-static void smiInitVideoProcessor (void)
-{
- SmiVideoProc smiVP = { 0x100000, 0, 0, 0, 0, 1600, 0x1200543, 4, 0xededed };
- SmiVideoWin smiVW = { 0, 0, 599, 799, 0, 1600, 0, 0, 0 };
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
- register SmiVideoProc *pVP = (SmiVideoProc *)&smiVP;
- register SmiVideoWin *pVWin = (SmiVideoWin *)&smiVW;
-
- pVP->width = pGD->plnSizeX * pGD->gdfBytesPP;
- pVP->control |= pGD->gdfIndex << 16;
- pVWin->bottom = pGD->winSizeY - 1;
- pVWin->right = pGD->winSizeX - 1;
- pVWin->width = pVP->width;
-
- /* color key */
- out32r ((pGD->vprBase + 0x0004), pVP->colorKey);
-
- /* color key mask */
- out32r ((pGD->vprBase + 0x0008), pVP->colorKeyMask);
-
- /* data src start adrs */
- out32r ((pGD->vprBase + 0x000c), pVP->start / 8);
-
- /* data width and offset */
- out32r ((pGD->vprBase + 0x0010),
- ((pVP->offset / 8 * pGD->gdfBytesPP) << 16) |
- (pGD->plnSizeX / 8 * pGD->gdfBytesPP));
-
- /* video window 1 */
- out32r ((pGD->vprBase + 0x0014),
- ((pVWin->top << 16) | pVWin->left));
-
- out32r ((pGD->vprBase + 0x0018),
- ((pVWin->bottom << 16) | pVWin->right));
-
- out32r ((pGD->vprBase + 0x001c), pVWin->srcStart / 8);
-
- out32r ((pGD->vprBase + 0x0020),
- (((pVWin->offset / 8) << 16) | (pVWin->width / 8)));
-
- out32r ((pGD->vprBase + 0x0024),
- (((pVWin->hStretch) << 8) | pVWin->vStretch));
-
- /* video window 2 */
- out32r ((pGD->vprBase + 0x0028),
- ((pVWin->top << 16) | pVWin->left));
-
- out32r ((pGD->vprBase + 0x002c),
- ((pVWin->bottom << 16) | pVWin->right));
-
- out32r ((pGD->vprBase + 0x0030),
- pVWin->srcStart / 8);
-
- out32r ((pGD->vprBase + 0x0034),
- (((pVWin->offset / 8) << 16) | (pVWin->width / 8)));
-
- out32r ((pGD->vprBase + 0x0038),
- (((pVWin->hStretch) << 8) | pVWin->vStretch));
-
- /* fifo prio control */
- out32r ((pGD->vprBase + 0x0054), pVP->fifoPrio);
-
- /* fifo empty request levell */
- out32r ((pGD->vprBase + 0x0058), pVP->fifoERL);
-
- /* conversion constant */
- out32r ((pGD->vprBase + 0x005c), pVP->YUVtoRGB);
-
- /* vpr control word */
- out32r ((pGD->vprBase + 0x0000), pVP->control);
-}
-
-/******************************************************************************
- *
- * Init drawing engine registers
- */
-static void smiInitDrawingEngine (void)
-{
- GraphicDevice *pGD = (GraphicDevice *)&smi;
- unsigned int val;
-
- /* don't start now */
- out32r ((pGD->dprBase + 0x000c), 0x000f0000);
-
- /* set rop2 to copypen */
- val = 0xffff3ff0 & in32r ((pGD->dprBase + 0x000c));
- out32r ((pGD->dprBase + 0x000c), (val | 0x8000 | 0x0c));
-
- /* set clip rect */
- out32r ((pGD->dprBase + 0x002c), 0);
- out32r ((pGD->dprBase + 0x0030),
- ((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP ));
-
- /* src row pitch */
- val = 0xffff0000 & (in32r ((pGD->dprBase + 0x0010)));
- out32r ((pGD->dprBase + 0x0010),
- (val | pGD->plnSizeX * pGD->gdfBytesPP));
-
- /* dst row pitch */
- val = 0x0000ffff & (in32r ((pGD->dprBase + 0x0010)));
- out32r ((pGD->dprBase + 0x0010),
- (((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val));
-
- /* window width src/dst */
- out32r ((pGD->dprBase + 0x003c),
- (((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) |
- (pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)));
- out16r ((pGD->dprBase + 0x001e), 0x0000);
-
- /* src base adrs */
- out32r ((pGD->dprBase + 0x0040),
- (((pGD->frameAdrs/8) & 0x000fffff)));
-
- /* dst base adrs */
- out32r ((pGD->dprBase + 0x0044),
- (((pGD->frameAdrs/8) & 0x000fffff)));
-
- /* foreground color */
- out32r ((pGD->dprBase + 0x0014), pGD->fg);
-
- /* background color */
- out32r ((pGD->dprBase + 0x0018), pGD->bg);
-
- /* xcolor */
- out32r ((pGD->dprBase + 0x0020), 0x00ffffff);
-
- /* xcolor mask */
- out32r ((pGD->dprBase + 0x0024), 0x00ffffff);
-
- /* bit mask */
- out32r ((pGD->dprBase + 0x0028), 0x00ffffff);
-
- /* load mono pattern */
- out32r ((pGD->dprBase + 0x0034), 0);
- out32r ((pGD->dprBase + 0x0038), 0);
-}
-
-static struct pci_device_id supported[] = {
- { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_710 },
- { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_712 },
- { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_810 },
- { }
-};
-
-/*****************************************************************************/
-static void smiLoadMsr (struct ctfb_res_modes *mode)
-{
- unsigned char h_synch_high, v_synch_high;
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
-
- h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */
- v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */
- out8 (SMI_MISC_REG, (h_synch_high | v_synch_high | 0x29));
- /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
- * Selects the upper 64KB page.Bit5=1
- * CLK2 (left reserved in standard VGA) Bit3|2=1|0
- * Disables CPU access to frame buffer. Bit1=0
- * Sets the I/O address decode for ST01, FCR, and all CR registers
- * to the 3Dx I/O address range (CGA emulation). Bit0=1
- */
-}
-/*****************************************************************************/
-static void smiLoadCrt (struct ctfb_res_modes *var, int bits_per_pixel)
-{
- unsigned char cr[0x7a];
- int i;
- unsigned int hd, hs, he, ht, hbs, hbe; /* Horizontal. */
- unsigned int vd, vs, ve, vt, vbs, vbe; /* vertical */
- unsigned int bpp, wd, dblscan, interlaced;
-
- const int LineCompare = 0x3ff;
- unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
-
- /* Horizontal */
- hd = (var->xres) / 8; /* HDisp. */
- hs = (var->xres + var->right_margin) / 8; /* HsStrt */
- he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */
- ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */
- /* Blank */
- hbs = hd;
- hbe = 0; /* Blank end at 0 */
-
- /* Vertical */
- vd = var->yres; /* VDisplay */
- vs = var->yres + var->lower_margin; /* VSyncStart */
- ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */
- vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */
- vbs = vd;
- vbe = 0;
-
- bpp = bits_per_pixel;
- dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0;
- interlaced = var->vmode & FB_VMODE_INTERLACED;
-
-
- if (bpp == 15)
- bpp = 16;
- wd = var->xres * bpp / 64; /* double words per line */
- if (interlaced) { /* we divide all vertical timings, exept vd */
- vs >>= 1;
- vbs >>= 1;
- ve >>= 1;
- vt >>= 1;
- }
-
- memset (cr, 0, sizeof (cr));
- cr[0x00] = ht - 5;
- cr[0x01] = hd - 1;
- cr[0x02] = hbs - 1;
- cr[0x03] = (hbe & 0x1F);
- cr[0x04] = hs;
- cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
-
- cr[0x06] = (vt - 2) & 0xFF;
- cr[0x07] = (((vt - 2) & 0x100) >> 8)
- | (((vd - 1) & 0x100) >> 7)
- | ((vs & 0x100) >> 6)
- | (((vbs - 1) & 0x100) >> 5)
- | ((LineCompare & 0x100) >> 4)
- | (((vt - 2) & 0x200) >> 4)
- | (((vd - 1) & 0x200) >> 3)
- | ((vs & 0x200) >> 2);
-
- cr[0x30] = ((vt - 2) & 0x400) >> 7
- | (((vd - 1) & 0x400) >> 8)
- | (((vbs - 1) & 0x400) >> 9)
- | ((vs & 0x400) >> 10)
- | (interlaced) ? 0x80 : 0;
-
-
- cr[0x08] = 0x00;
- cr[0x09] = (dblscan << 7)
- | ((LineCompare & 0x200) >> 3)
- | (((vbs - 1) & 0x200) >> 4)
- | (TextScanLines - 1);
-
- cr[0x10] = vs & 0xff; /* VSyncPulseStart */
- cr[0x11] = (ve & 0x0f);
- cr[0x12] = (vd - 1) & 0xff; /* LineCount */
- cr[0x13] = wd & 0xff;
- cr[0x14] = 0x40;
- cr[0x15] = (vbs - 1) & 0xff;
- cr[0x16] = vbe & 0xff;
- cr[0x17] = 0xe3; /* but it does not work */
- cr[0x18] = 0xff & LineCompare;
- cr[0x22] = 0x00; /* todo? */
-
-
- /* now set the registers */
- for (i = 0; i <= 0x18; i++) { /*CR00 .. CR18 */
- smiWrite (SMI_INDX_D4, i, cr[i]);
- }
- i = 0x22; /*CR22 */
- smiWrite (SMI_INDX_D4, i, cr[i]);
- i = 0x30; /*CR30 */
- smiWrite (SMI_INDX_D4, i, cr[i]);
-}
-
-/*****************************************************************************/
-#define REF_FREQ 14318180
-#define PMIN 1
-#define PMAX 255
-#define QMIN 1
-#define QMAX 63
-
-static unsigned int FindPQ (unsigned int freq, unsigned int *pp, unsigned int *pq)
-{
- unsigned int n = QMIN, m = 0;
- long long int L = 0, P = freq, Q = REF_FREQ, H = P >> 1;
- long long int D = 0x7ffffffffffffffLL;
-
- for (n = QMIN; n <= QMAX; n++) {
- m = PMIN; /* p/q ~ freq/ref -> p*ref-freq*q ~ 0 */
- L = P * n - m * Q;
- while (L > 0 && m < PMAX) {
- L -= REF_FREQ; /* difference is greater as 0 subtract fref */
- m++; /* and increment m */
- }
- /* difference is less or equal than 0 or m > maximum */
- if (m > PMAX)
- break; /* no solution: if we increase n we get the same situation */
- /* L is <= 0 now */
- if (-L > H && m > PMIN) { /* if difference > the half fref */
- L += REF_FREQ; /* we take the situation before */
- m--; /* because its closer to 0 */
- }
- L = (L < 0) ? -L : +L; /* absolute value */
- if (D < L) /* if last difference was better take next n */
- continue;
- D = L;
- *pp = m;
- *pq = n; /* keep improved data */
- if (D == 0)
- break; /* best result we can get */
- }
- return (unsigned int) (0xffffffff & D);
-}
-
-/*****************************************************************************/
-static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id)
-{
- unsigned int p = 0;
- unsigned int q = 0;
- long long freq;
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
-
- smiWrite (SMI_INDX_C4, 0x65, 0);
- smiWrite (SMI_INDX_C4, 0x66, 0);
- smiWrite (SMI_INDX_C4, 0x68, 0x50);
- if (device_id == PCI_DEVICE_ID_SMI_810) {
- smiWrite (SMI_INDX_C4, 0x69, 0x3);
- } else {
- smiWrite (SMI_INDX_C4, 0x69, 0x0);
- }
-
- /* Memory clock */
- switch (device_id) {
- case PCI_DEVICE_ID_SMI_710 :
- smiWrite (SMI_INDX_C4, 0x6a, 0x75);
- break;
- case PCI_DEVICE_ID_SMI_712 :
- smiWrite (SMI_INDX_C4, 0x6a, 0x80);
- break;
- default :
- smiWrite (SMI_INDX_C4, 0x6a, 0x53);
- break;
- }
- smiWrite (SMI_INDX_C4, 0x6b, 0x15);
-
- /* VCLK */
- freq = 1000000000000LL / var -> pixclock;
-
- FindPQ ((unsigned int)freq, &p, &q);
-
- smiWrite (SMI_INDX_C4, 0x6c, p);
- smiWrite (SMI_INDX_C4, 0x6d, q);
-
-}
-
-/*******************************************************************************
- *
- * Init video chip with common Linux graphic modes (lilo)
- */
-void *video_hw_init (void)
-{
- GraphicDevice *pGD = (GraphicDevice *)&smi;
- unsigned short device_id;
- pci_dev_t devbusfn;
- int videomode;
- unsigned long t1, hsynch, vsynch;
- unsigned int pci_mem_base, *vm;
- char *penv;
- int tmp, i, bits_per_pixel;
- struct ctfb_res_modes *res_mode;
- struct ctfb_res_modes var_mode;
- unsigned char videoout;
-
- /* Search for video chip */
- printf("Video: ");
-
- if ((devbusfn = pci_find_devices(supported, 0)) < 0)
- {
- printf ("Controller not found !\n");
- return (NULL);
- }
-
- /* PCI setup */
- pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
- pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
- pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
- pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
-
- tmp = 0;
-
- videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
- /* get video mode via environment */
- if ((penv = getenv ("videomode")) != NULL) {
- /* deceide if it is a string */
- if (penv[0] <= '9') {
- videomode = (int) simple_strtoul (penv, NULL, 16);
- tmp = 1;
- }
- } else {
- tmp = 1;
- }
- if (tmp) {
- /* parameter are vesa modes */
- /* search params */
- for (i = 0; i < VESA_MODES_COUNT; i++) {
- if (vesa_modes[i].vesanr == videomode)
- break;
- }
- if (i == VESA_MODES_COUNT) {
- printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE);
- i = 0;
- }
- res_mode =
- (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].
- resindex];
- bits_per_pixel = vesa_modes[i].bits_per_pixel;
- } else {
-
- res_mode = (struct ctfb_res_modes *) &var_mode;
- bits_per_pixel = video_get_params (res_mode, penv);
- }
-
- /* calculate hsynch and vsynch freq (info only) */
- t1 = (res_mode->left_margin + res_mode->xres +
- res_mode->right_margin + res_mode->hsync_len) / 8;
- t1 *= 8;
- t1 *= res_mode->pixclock;
- t1 /= 1000;
- hsynch = 1000000000L / t1;
- t1 *=
- (res_mode->upper_margin + res_mode->yres +
- res_mode->lower_margin + res_mode->vsync_len);
- t1 /= 1000;
- vsynch = 1000000000L / t1;
-
- /* fill in Graphic device struct */
- sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
- res_mode->yres, bits_per_pixel, (hsynch / 1000),
- (vsynch / 1000));
- printf ("%s\n", pGD->modeIdent);
- pGD->winSizeX = res_mode->xres;
- pGD->winSizeY = res_mode->yres;
- pGD->plnSizeX = res_mode->xres;
- pGD->plnSizeY = res_mode->yres;
- switch (bits_per_pixel) {
- case 8:
- pGD->gdfBytesPP = 1;
- pGD->gdfIndex = GDF__8BIT_INDEX;
- break;
- case 15:
- pGD->gdfBytesPP = 2;
- pGD->gdfIndex = GDF_15BIT_555RGB;
- break;
- case 16:
- pGD->gdfBytesPP = 2;
- pGD->gdfIndex = GDF_16BIT_565RGB;
- break;
- case 24:
- pGD->gdfBytesPP = 3;
- pGD->gdfIndex = GDF_24BIT_888RGB;
- break;
- }
-
- pGD->isaBase = CONFIG_SYS_ISA_IO;
- pGD->pciBase = pci_mem_base;
- pGD->dprBase = (pci_mem_base + 0x400000 + 0x8000);
- pGD->vprBase = (pci_mem_base + 0x400000 + 0xc000);
- pGD->cprBase = (pci_mem_base + 0x400000 + 0xe000);
- pGD->frameAdrs = pci_mem_base;
- pGD->memSize = VIDEO_MEM_SIZE;
-
- /* Set up hardware : select color mode,
- set Register base to isa 3dx for 3?x regs*/
- out8 (SMI_MISC_REG, 0x01);
-
- /* Turn off display */
- smiWrite (SMI_INDX_C4, 0x01, 0x20);
-
- /* Unlock ext. crt regs */
- out8 (SMI_LOCK_REG, 0x40);
-
- /* Unlock crt regs 0-7 */
- smiWrite (SMI_INDX_D4, 0x11, 0x0e);
-
- /* Sytem Control Register */
- smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SCR, sizeof(SMI_SCR));
-
- /* extented CRT Register */
- smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, SMI_EXT_CRT, sizeof(SMI_EXT_CRT));
-
- /* Attributes controller registers */
- smiLoadRegs (SMI_INDX_ATTR, SMI_INDX_ATTR, SMI_ATTR, sizeof(SMI_ATTR));
-
- /* Graphics Controller Register */
- smiLoadRegs (SMI_INDX_CE, SMI_DATA_CF, SMI_GCR, sizeof(SMI_GCR));
-
- /* Sequencer Register */
- smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SEQR, sizeof(SMI_SEQR));
-
- /* Power Control Register */
- smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_PCR, sizeof(SMI_PCR));
-
- /* Memory Control Register */
- /* Register MSR62 is a power on configurable register. We don't */
- /* modify it */
- smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_MCR, sizeof(SMI_MCR));
-
- /* Set misc output register */
- smiLoadMsr (res_mode);
-
- /* Set CRT and Clock control registers */
- smiLoadCrt (res_mode, bits_per_pixel);
-
- smiLoadCcr (res_mode, device_id);
-
- /* Hardware Cusor Register */
- smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_HCR, sizeof(SMI_HCR));
-
- /* Enable Display */
- videoout = 2; /* Default output is CRT */
- if ((penv = getenv ("videoout")) != NULL) {
- /* deceide if it is a string */
- videoout = (int) simple_strtoul (penv, NULL, 16);
- }
- smiWrite (SMI_INDX_C4, 0x31, videoout);
-
- /* Video processor default setup */
- smiInitVideoProcessor ();
-
- /* Capture port default setup */
- smiInitCapturePort ();
-
- /* Drawing engine default setup */
- smiInitDrawingEngine ();
-
- /* Turn on display */
- smiWrite (0x3c4, 0x01, 0x01);
-
- /* Clear video memory */
- i = pGD->memSize/4;
- vm = (unsigned int *)pGD->pciBase;
- while(i--)
- *vm++ = 0;
- return ((void*)&smi);
-}
-
-/*******************************************************************************
- *
- * Drawing engine fill on screen region
- */
-void video_hw_rectfill (
- unsigned int bpp, /* bytes per pixel */
- unsigned int dst_x, /* dest pos x */
- unsigned int dst_y, /* dest pos y */
- unsigned int dim_x, /* frame width */
- unsigned int dim_y, /* frame height */
- unsigned int color /* fill color */
- )
-{
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
- register unsigned int control;
-
- dim_x *= bpp;
-
- out32r ((pGD->dprBase + 0x0014), color);
- out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y));
- out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y));
-
- control = 0x0000ffff & in32r ((pGD->dprBase + 0x000c));
-
- control |= 0x80010000;
-
- out32r ((pGD->dprBase + 0x000c), control);
-
- /* Wait for drawing processor */
- do
- {
- out8 ((pGD->isaBase + 0x3c4), 0x16);
- } while (in8 (pGD->isaBase + 0x3c5) & 0x08);
-}
-
-/*******************************************************************************
- *
- * Drawing engine bitblt with screen region
- */
-void video_hw_bitblt (
- unsigned int bpp, /* bytes per pixel */
- unsigned int src_x, /* source pos x */
- unsigned int src_y, /* source pos y */
- unsigned int dst_x, /* dest pos x */
- unsigned int dst_y, /* dest pos y */
- unsigned int dim_x, /* frame width */
- unsigned int dim_y /* frame height */
- )
-{
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
- register unsigned int control;
-
- dim_x *= bpp;
-
- if ((src_y<dst_y) || ((src_y==dst_y) && (src_x<dst_x)))
- {
- out32r ((pGD->dprBase + 0x0000), (((src_x+dim_x-1)<<16) | (src_y+dim_y-1)));
- out32r ((pGD->dprBase + 0x0004), (((dst_x+dim_x-1)<<16) | (dst_y+dim_y-1)));
- control = 0x88000000;
- } else {
- out32r ((pGD->dprBase + 0x0000), ((src_x<<16) | src_y));
- out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y));
- control = 0x80000000;
- }
-
- out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y));
- control |= (0x0000ffff & in32r ((pGD->dprBase + 0x000c)));
- out32r ((pGD->dprBase + 0x000c), control);
-
- /* Wait for drawing processor */
- do
- {
- out8 ((pGD->isaBase + 0x3c4), 0x16);
- } while (in8 (pGD->isaBase + 0x3c5) & 0x08);
-}
-
-/*******************************************************************************
- *
- * Set a RGB color in the LUT (8 bit index)
- */
-void video_set_lut (
- unsigned int index, /* color number */
- unsigned char r, /* red */
- unsigned char g, /* green */
- unsigned char b /* blue */
- )
-{
- register GraphicDevice *pGD = (GraphicDevice *)&smi;
-
- out8 (SMI_LUT_MASK, 0xff);
-
- out8 (SMI_LUT_START, (char)index);
-
- out8 (SMI_LUT_RGB, r>>2); /* red */
- udelay (10);
- out8 (SMI_LUT_RGB, g>>2); /* green */
- udelay (10);
- out8 (SMI_LUT_RGB, b>>2); /* blue */
- udelay (10);
-}
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index 50b16a9..6f8ee01 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -1562,8 +1562,8 @@
offset = fdt_node_offset_by_compatible(blob, -1,
"allwinner,simple-framebuffer");
while (offset >= 0) {
- ret = fdt_find_string(blob, offset, "allwinner,pipeline",
- pipeline);
+ ret = fdt_stringlist_search(blob, offset, "allwinner,pipeline",
+ pipeline);
if (ret == 0)
break;
offset = fdt_node_offset_by_compatible(blob, offset,
diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c
index 2f1f0df..28db96c 100644
--- a/drivers/video/tegra124/display.c
+++ b/drivers/video/tegra124/display.c
@@ -326,13 +326,7 @@
int *panel_bppp,
struct display_timing *timing)
{
- int ret;
-
- ret = display_read_timing(dp_dev, timing);
- if (ret)
- return ret;
-
- return 0;
+ return display_read_timing(dp_dev, timing);
}
static int display_init(struct udevice *dev, void *lcdbase,
@@ -349,7 +343,7 @@
/*
* Before we probe the display device (eDP), tell it that this device
- * is are the source of the display data.
+ * is the source of the display data.
*/
ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
if (ret) {
diff --git a/drivers/video/vesa.c b/drivers/video/vesa.c
new file mode 100644
index 0000000..ddf8df8
--- /dev/null
+++ b/drivers/video/vesa.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <vbe.h>
+
+static int vesa_video_probe(struct udevice *dev)
+{
+ return vbe_setup_video(dev, NULL);
+}
+
+static const struct udevice_id vesa_video_ids[] = {
+ { .compatible = "vesa-fb" },
+ { }
+};
+
+U_BOOT_DRIVER(vesa_video) = {
+ .name = "vesa_video",
+ .id = UCLASS_VIDEO,
+ .of_match = vesa_video_ids,
+ .probe = vesa_video_probe,
+};
+
+static struct pci_device_id vesa_video_supported[] = {
+ { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, ~0) },
+ { },
+};
+
+U_BOOT_PCI_DEVICE(vesa_video, vesa_video_supported);
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
deleted file mode 100644
index 021c1d6..0000000
--- a/drivers/video/vesa_fb.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * VESA frame buffer driver
- *
- * Copyright (C) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <pci_rom.h>
-#include <video_fb.h>
-#include <vbe.h>
-
-/*
- * The Graphic Device
- */
-GraphicDevice ctfb;
-
-void *video_hw_init(void)
-{
- GraphicDevice *gdev = &ctfb;
- struct udevice *dev;
- int bits_per_pixel;
- int ret;
-
- printf("Video: ");
- if (!ll_boot_init()) {
- /*
- * If we are running from EFI or coreboot, this driver can't
- * work.
- */
- printf("Not available (previous bootloader prevents it)\n");
- return NULL;
- }
- if (vbe_get_video_info(gdev)) {
- ret = dm_pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0, &dev);
- if (ret) {
- printf("no card detected\n");
- return NULL;
- }
- bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
- ret = dm_pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
- if (ret) {
- printf("failed to run video BIOS: %d\n", ret);
- return NULL;
- }
- }
-
- if (vbe_get_video_info(gdev)) {
- printf("No video mode configured\n");
- return NULL;
- }
-
- bits_per_pixel = gdev->gdfBytesPP * 8;
- sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
- bits_per_pixel);
- printf("%s\n", gdev->modeIdent);
- debug("Frame buffer at %x\n", gdev->pciBase);
-
- return (void *)gdev;
-}
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index c8cc05e..e9a90b1 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -190,7 +190,6 @@
{
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
struct stdio_dev *sdev = &priv->sdev;
- int ret;
if (!priv->tab_width_frac)
priv->tab_width_frac = VID_TO_POS(priv->x_charsize) * 8;
@@ -206,11 +205,8 @@
sdev->putc = vidconsole_putc;
sdev->puts = vidconsole_puts;
sdev->priv = dev;
- ret = stdio_register(sdev);
- if (ret)
- return ret;
- return 0;
+ return stdio_register(sdev);
}
UCLASS_DRIVER(vidconsole) = {
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index b6dd0f5..3036e3a 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -54,6 +54,9 @@
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
ulong base, align, size;
+ if (!plat->size)
+ return 0;
+
align = plat->align ? plat->align : 1 << 20;
base = *addrp - plat->size;
base &= ~(align - 1);
@@ -114,7 +117,8 @@
if (priv->flush_dcache) {
flush_dcache_range((ulong)priv->fb,
- (ulong)priv->fb + priv->fb_size);
+ ALIGN((ulong)priv->fb + priv->fb_size,
+ CONFIG_SYS_CACHELINE_SIZE));
}
#elif defined(CONFIG_VIDEO_SANDBOX_SDL)
struct video_priv *priv = dev_get_uclass_priv(vid);
diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index fb7943e..32a4e7f 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -312,7 +312,7 @@
fb_put_word(&fb, &bmap);
bmap += (padded_width - width) * 2;
- fb -= width * 2 + lcd_line_length;
+ fb -= width * 2 + priv->line_length;
}
break;
#endif /* CONFIG_BMP_16BPP */
@@ -325,7 +325,7 @@
*(fb++) = *(bmap++);
*(fb++) = 0;
}
- fb -= lcd_line_length + width * (bpix / 8);
+ fb -= priv->line_length + width * (bpix / 8);
}
break;
#endif /* CONFIG_BMP_24BMP */
@@ -338,7 +338,7 @@
*(fb++) = *(bmap++);
*(fb++) = *(bmap++);
}
- fb -= lcd_line_length + width * (bpix / 8);
+ fb -= priv->line_length + width * (bpix / 8);
}
break;
#endif /* CONFIG_BMP_32BPP */
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 2938d9f..3f826d1 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -34,7 +34,7 @@
#endif
timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
- SET_WCR_WT(timeout), &wdog->wcr);
+ WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
hw_watchdog_reset();
}
#endif
diff --git a/examples/standalone/mem_to_mem_idma2intr.c b/examples/standalone/mem_to_mem_idma2intr.c
index 17da8db..ce6e6c4 100644
--- a/examples/standalone/mem_to_mem_idma2intr.c
+++ b/examples/standalone/mem_to_mem_idma2intr.c
@@ -186,13 +186,6 @@
}
return 0;
}
-void * memset(void * s,int c,size_t count)
-{
- char *xs = (char *) s;
- while (count--)
- *xs++ = c;
- return s;
-}
int memcmp(const void * cs,const void * ct,size_t count)
{
const unsigned char *su1, *su2;
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index eb49fce..621c61e 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -33,20 +33,156 @@
struct ext2_data *ext4fs_root;
struct ext2fs_node *ext4fs_file;
-uint32_t *ext4fs_indir1_block;
+__le32 *ext4fs_indir1_block;
int ext4fs_indir1_size;
int ext4fs_indir1_blkno = -1;
-uint32_t *ext4fs_indir2_block;
+__le32 *ext4fs_indir2_block;
int ext4fs_indir2_size;
int ext4fs_indir2_blkno = -1;
-uint32_t *ext4fs_indir3_block;
+__le32 *ext4fs_indir3_block;
int ext4fs_indir3_size;
int ext4fs_indir3_blkno = -1;
struct ext2_inode *g_parent_inode;
static int symlinknest;
#if defined(CONFIG_EXT4_WRITE)
+struct ext2_block_group *ext4fs_get_group_descriptor
+ (const struct ext_filesystem *fs, uint32_t bg_idx)
+{
+ return (struct ext2_block_group *)(fs->gdtable + (bg_idx * fs->gdsize));
+}
+
+static inline void ext4fs_sb_free_inodes_dec(struct ext2_sblock *sb)
+{
+ sb->free_inodes = cpu_to_le32(le32_to_cpu(sb->free_inodes) - 1);
+}
+
+static inline void ext4fs_sb_free_blocks_dec(struct ext2_sblock *sb)
+{
+ uint64_t free_blocks = le32_to_cpu(sb->free_blocks);
+ free_blocks += (uint64_t)le32_to_cpu(sb->free_blocks_high) << 32;
+ free_blocks--;
+
+ sb->free_blocks = cpu_to_le32(free_blocks & 0xffffffff);
+ sb->free_blocks_high = cpu_to_le16(free_blocks >> 32);
+}
+
+static inline void ext4fs_bg_free_inodes_dec
+ (struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+ uint32_t free_inodes = le16_to_cpu(bg->free_inodes);
+ if (fs->gdsize == 64)
+ free_inodes += le16_to_cpu(bg->free_inodes_high) << 16;
+ free_inodes--;
+
+ bg->free_inodes = cpu_to_le16(free_inodes & 0xffff);
+ if (fs->gdsize == 64)
+ bg->free_inodes_high = cpu_to_le16(free_inodes >> 16);
+}
+
+static inline void ext4fs_bg_free_blocks_dec
+ (struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+ uint32_t free_blocks = le16_to_cpu(bg->free_blocks);
+ if (fs->gdsize == 64)
+ free_blocks += le16_to_cpu(bg->free_blocks_high) << 16;
+ free_blocks--;
+
+ bg->free_blocks = cpu_to_le16(free_blocks & 0xffff);
+ if (fs->gdsize == 64)
+ bg->free_blocks_high = cpu_to_le16(free_blocks >> 16);
+}
+
+static inline void ext4fs_bg_itable_unused_dec
+ (struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+ uint32_t free_inodes = le16_to_cpu(bg->bg_itable_unused);
+ if (fs->gdsize == 64)
+ free_inodes += le16_to_cpu(bg->bg_itable_unused_high) << 16;
+ free_inodes--;
+
+ bg->bg_itable_unused = cpu_to_le16(free_inodes & 0xffff);
+ if (fs->gdsize == 64)
+ bg->bg_itable_unused_high = cpu_to_le16(free_inodes >> 16);
+}
+
+uint64_t ext4fs_sb_get_free_blocks(const struct ext2_sblock *sb)
+{
+ uint64_t free_blocks = le32_to_cpu(sb->free_blocks);
+ free_blocks += (uint64_t)le32_to_cpu(sb->free_blocks_high) << 32;
+ return free_blocks;
+}
+
+void ext4fs_sb_set_free_blocks(struct ext2_sblock *sb, uint64_t free_blocks)
+{
+ sb->free_blocks = cpu_to_le32(free_blocks & 0xffffffff);
+ sb->free_blocks_high = cpu_to_le16(free_blocks >> 32);
+}
+
+uint32_t ext4fs_bg_get_free_blocks(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs)
+{
+ uint32_t free_blocks = le16_to_cpu(bg->free_blocks);
+ if (fs->gdsize == 64)
+ free_blocks += le16_to_cpu(bg->free_blocks_high) << 16;
+ return free_blocks;
+}
+
+static inline
+uint32_t ext4fs_bg_get_free_inodes(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs)
+{
+ uint32_t free_inodes = le16_to_cpu(bg->free_inodes);
+ if (fs->gdsize == 64)
+ free_inodes += le16_to_cpu(bg->free_inodes_high) << 16;
+ return free_inodes;
+}
+
+static inline uint16_t ext4fs_bg_get_flags(const struct ext2_block_group *bg)
+{
+ return le16_to_cpu(bg->bg_flags);
+}
+
+static inline void ext4fs_bg_set_flags(struct ext2_block_group *bg,
+ uint16_t flags)
+{
+ bg->bg_flags = cpu_to_le16(flags);
+}
+
+/* Block number of the block bitmap */
+uint64_t ext4fs_bg_get_block_id(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs)
+{
+ uint64_t block_nr = le32_to_cpu(bg->block_id);
+ if (fs->gdsize == 64)
+ block_nr += (uint64_t)le32_to_cpu(bg->block_id_high) << 32;
+ return block_nr;
+}
+
+/* Block number of the inode bitmap */
+uint64_t ext4fs_bg_get_inode_id(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs)
+{
+ uint64_t block_nr = le32_to_cpu(bg->inode_id);
+ if (fs->gdsize == 64)
+ block_nr += (uint64_t)le32_to_cpu(bg->inode_id_high) << 32;
+ return block_nr;
+}
+#endif
+
+/* Block number of the inode table */
+uint64_t ext4fs_bg_get_inode_table_id(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs)
+{
+ uint64_t block_nr = le32_to_cpu(bg->inode_table_id);
+ if (fs->gdsize == 64)
+ block_nr +=
+ (uint64_t)le32_to_cpu(bg->inode_table_id_high) << 32;
+ return block_nr;
+}
+
+#if defined(CONFIG_EXT4_WRITE)
uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n)
{
uint32_t res = size / n;
@@ -112,7 +248,7 @@
while (*ptr == 255) {
ptr++;
count += 8;
- if (count > ext4fs_root->sblock.inodes_per_group)
+ if (count > le32_to_cpu(ext4fs_root->sblock.inodes_per_group))
return -1;
}
@@ -138,18 +274,12 @@
static int _get_new_blk_no(unsigned char *buffer)
{
- unsigned char input;
- int operand, status;
+ int operand;
int count = 0;
- int j = 0;
+ int i;
unsigned char *ptr = buffer;
struct ext_filesystem *fs = get_fs();
- if (fs->blksz != 1024)
- count = 0;
- else
- count = 1;
-
while (*ptr == 255) {
ptr++;
count += 8;
@@ -157,21 +287,17 @@
return -1;
}
- for (j = 0; j < fs->blksz; j++) {
- input = *ptr;
- int i = 0;
- while (i <= 7) {
- operand = 1 << i;
- status = input & operand;
- if (status) {
- i++;
- count++;
- } else {
- *ptr |= operand;
- return count;
- }
+ if (fs->blksz == 1024)
+ count += 1;
+
+ for (i = 0; i <= 7; i++) {
+ operand = 1 << i;
+ if (*ptr & operand) {
+ count++;
+ } else {
+ *ptr |= operand;
+ return count;
}
- ptr = ptr + 1;
}
return -1;
@@ -249,7 +375,7 @@
unsigned char *ptr = buffer;
unsigned char operand;
- inode_no -= (index * ext4fs_root->sblock.inodes_per_group);
+ inode_no -= (index * le32_to_cpu(ext4fs_root->sblock.inodes_per_group));
i = inode_no / 8;
remainder = inode_no % 8;
if (remainder == 0) {
@@ -274,7 +400,7 @@
unsigned char *ptr = buffer;
unsigned char operand;
- inode_no -= (index * ext4fs_root->sblock.inodes_per_group);
+ inode_no -= (index * le32_to_cpu(ext4fs_root->sblock.inodes_per_group));
i = inode_no / 8;
remainder = inode_no % 8;
if (remainder == 0) {
@@ -289,19 +415,20 @@
*ptr = *ptr & ~(operand);
}
-int ext4fs_checksum_update(unsigned int i)
+uint16_t ext4fs_checksum_update(uint32_t i)
{
struct ext2_block_group *desc;
struct ext_filesystem *fs = get_fs();
- __u16 crc = 0;
+ uint16_t crc = 0;
+ __le32 le32_i = cpu_to_le32(i);
- desc = (struct ext2_block_group *)&fs->bgd[i];
- if (fs->sb->feature_ro_compat & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) {
+ desc = ext4fs_get_group_descriptor(fs, i);
+ if (le32_to_cpu(fs->sb->feature_ro_compat) & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) {
int offset = offsetof(struct ext2_block_group, bg_checksum);
crc = ext2fs_crc16(~0, fs->sb->unique_id,
sizeof(fs->sb->unique_id));
- crc = ext2fs_crc16(crc, &i, sizeof(i));
+ crc = ext2fs_crc16(crc, &le32_i, sizeof(le32_i));
crc = ext2fs_crc16(crc, desc, offset);
offset += sizeof(desc->bg_checksum); /* skip checksum */
assert(offset == sizeof(*desc));
@@ -322,7 +449,7 @@
dentry_length = sizeof(struct ext2_dirent) +
dir->namelen + padding_factor;
- sizeof_void_space = dir->direntlen - dentry_length;
+ sizeof_void_space = le16_to_cpu(dir->direntlen) - dentry_length;
if (sizeof_void_space == 0)
return 0;
@@ -333,58 +460,57 @@
new_entry_byte_reqd = strlen(filename) +
sizeof(struct ext2_dirent) + padding_factor;
if (sizeof_void_space >= new_entry_byte_reqd) {
- dir->direntlen = dentry_length;
+ dir->direntlen = cpu_to_le16(dentry_length);
return sizeof_void_space;
}
return 0;
}
-void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type)
+int ext4fs_update_parent_dentry(char *filename, int file_type)
{
unsigned int *zero_buffer = NULL;
char *root_first_block_buffer = NULL;
- int direct_blk_idx;
- long int root_blknr;
+ int blk_idx;
long int first_block_no_of_root = 0;
- long int previous_blknr = -1;
int totalbytes = 0;
- short int padding_factor = 0;
unsigned int new_entry_byte_reqd;
- unsigned int last_entry_dirlen;
int sizeof_void_space = 0;
int templength = 0;
- int inodeno;
+ int inodeno = -1;
int status;
struct ext_filesystem *fs = get_fs();
/* directory entry */
struct ext2_dirent *dir;
char *temp_dir = NULL;
+ uint32_t new_blk_no;
+ uint32_t new_size;
+ uint32_t new_blockcnt;
+ uint32_t directory_blocks;
zero_buffer = zalloc(fs->blksz);
if (!zero_buffer) {
printf("No Memory\n");
- return;
+ return -1;
}
root_first_block_buffer = zalloc(fs->blksz);
if (!root_first_block_buffer) {
free(zero_buffer);
printf("No Memory\n");
- return;
+ return -1;
}
+ new_entry_byte_reqd = ROUND(strlen(filename) +
+ sizeof(struct ext2_dirent), 4);
restart:
+ directory_blocks = le32_to_cpu(g_parent_inode->size) >>
+ LOG2_BLOCK_SIZE(ext4fs_root);
+ blk_idx = directory_blocks - 1;
+restart_read:
/* read the block no allocated to a file */
- for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS;
- direct_blk_idx++) {
- root_blknr = read_allocated_block(g_parent_inode,
- direct_blk_idx);
- if (root_blknr == 0) {
- first_block_no_of_root = previous_blknr;
- break;
- }
- previous_blknr = root_blknr;
- }
+ first_block_no_of_root = read_allocated_block(g_parent_inode, blk_idx);
+ if (first_block_no_of_root <= 0)
+ goto fail;
status = ext4fs_devread((lbaint_t)first_block_no_of_root
* fs->sect_perblk,
@@ -396,66 +522,63 @@
goto fail;
dir = (struct ext2_dirent *)root_first_block_buffer;
totalbytes = 0;
- while (dir->direntlen > 0) {
- /*
- * blocksize-totalbytes because last directory length
- * i.e. dir->direntlen is free availble space in the
- * block that means it is a last entry of directory
- * entry
- */
- /* traversing the each directory entry */
- if (fs->blksz - totalbytes == dir->direntlen) {
- if (strlen(filename) % 4 != 0)
- padding_factor = 4 - (strlen(filename) % 4);
+ while (le16_to_cpu(dir->direntlen) > 0) {
+ unsigned short used_len = ROUND(dir->namelen +
+ sizeof(struct ext2_dirent), 4);
- new_entry_byte_reqd = strlen(filename) +
- sizeof(struct ext2_dirent) + padding_factor;
- padding_factor = 0;
- /*
- * update last directory entry length to its
- * length because we are creating new directory
- * entry
- */
- if (dir->namelen % 4 != 0)
- padding_factor = 4 - (dir->namelen % 4);
+ /* last entry of block */
+ if (fs->blksz - totalbytes == le16_to_cpu(dir->direntlen)) {
- last_entry_dirlen = dir->namelen +
- sizeof(struct ext2_dirent) + padding_factor;
- if ((fs->blksz - totalbytes - last_entry_dirlen) <
- new_entry_byte_reqd) {
- printf("1st Block Full:Allocate new block\n");
+ /* check if new entry fits */
+ if ((used_len + new_entry_byte_reqd) <=
+ le16_to_cpu(dir->direntlen)) {
+ dir->direntlen = cpu_to_le16(used_len);
+ break;
+ } else {
+ if (blk_idx > 0) {
+ printf("Block full, trying previous\n");
+ blk_idx--;
+ goto restart_read;
+ }
+ printf("All blocks full: Allocate new\n");
- if (direct_blk_idx == INDIRECT_BLOCKS - 1) {
+ if (le32_to_cpu(g_parent_inode->flags) &
+ EXT4_EXTENTS_FL) {
+ printf("Directory uses extents\n");
+ goto fail;
+ }
+ if (directory_blocks >= INDIRECT_BLOCKS) {
printf("Directory exceeds limit\n");
goto fail;
}
- g_parent_inode->b.blocks.dir_blocks
- [direct_blk_idx] = ext4fs_get_new_blk_no();
- if (g_parent_inode->b.blocks.dir_blocks
- [direct_blk_idx] == -1) {
+ new_blk_no = ext4fs_get_new_blk_no();
+ if (new_blk_no == -1) {
printf("no block left to assign\n");
goto fail;
}
- put_ext4(((uint64_t)
- ((uint64_t)g_parent_inode->b.
- blocks.dir_blocks[direct_blk_idx] *
- (uint64_t)fs->blksz)), zero_buffer, fs->blksz);
- g_parent_inode->size =
- g_parent_inode->size + fs->blksz;
- g_parent_inode->blockcnt =
- g_parent_inode->blockcnt + fs->sect_perblk;
+ put_ext4((uint64_t)new_blk_no * fs->blksz, zero_buffer, fs->blksz);
+ g_parent_inode->b.blocks.
+ dir_blocks[directory_blocks] =
+ cpu_to_le32(new_blk_no);
+
+ new_size = le32_to_cpu(g_parent_inode->size);
+ new_size += fs->blksz;
+ g_parent_inode->size = cpu_to_le32(new_size);
+
+ new_blockcnt = le32_to_cpu(g_parent_inode->blockcnt);
+ new_blockcnt += fs->sect_perblk;
+ g_parent_inode->blockcnt = cpu_to_le32(new_blockcnt);
+
if (ext4fs_put_metadata
(root_first_block_buffer,
first_block_no_of_root))
goto fail;
goto restart;
}
- dir->direntlen = last_entry_dirlen;
- break;
}
- templength = dir->direntlen;
+ templength = le16_to_cpu(dir->direntlen);
totalbytes = totalbytes + templength;
sizeof_void_space = check_void_in_dentry(dir, filename);
if (sizeof_void_space)
@@ -465,7 +588,7 @@
}
/* make a pointer ready for creating next directory entry */
- templength = dir->direntlen;
+ templength = le16_to_cpu(dir->direntlen);
totalbytes = totalbytes + templength;
dir = (struct ext2_dirent *)((char *)dir + templength);
@@ -475,11 +598,11 @@
printf("no inode left to assign\n");
goto fail;
}
- dir->inode = inodeno;
+ dir->inode = cpu_to_le32(inodeno);
if (sizeof_void_space)
- dir->direntlen = sizeof_void_space;
+ dir->direntlen = cpu_to_le16(sizeof_void_space);
else
- dir->direntlen = fs->blksz - totalbytes;
+ dir->direntlen = cpu_to_le16(fs->blksz - totalbytes);
dir->namelen = strlen(filename);
dir->filetype = FILETYPE_REG; /* regular file */
@@ -487,8 +610,6 @@
temp_dir = temp_dir + sizeof(struct ext2_dirent);
memcpy(temp_dir, filename, strlen(filename));
- *p_ino = inodeno;
-
/* update or write the 1st block of root inode */
if (ext4fs_put_metadata(root_first_block_buffer,
first_block_no_of_root))
@@ -497,82 +618,65 @@
fail:
free(zero_buffer);
free(root_first_block_buffer);
+
+ return inodeno;
}
static int search_dir(struct ext2_inode *parent_inode, char *dirname)
{
int status;
- int inodeno;
- int totalbytes;
- int templength;
- int direct_blk_idx;
+ int inodeno = 0;
+ int offset;
+ int blk_idx;
long int blknr;
- int found = 0;
- char *ptr = NULL;
- unsigned char *block_buffer = NULL;
+ char *block_buffer = NULL;
struct ext2_dirent *dir = NULL;
- struct ext2_dirent *previous_dir = NULL;
struct ext_filesystem *fs = get_fs();
+ uint32_t directory_blocks;
+ char *direntname;
- /* read the block no allocated to a file */
- for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS;
- direct_blk_idx++) {
- blknr = read_allocated_block(parent_inode, direct_blk_idx);
- if (blknr == 0)
+ directory_blocks = le32_to_cpu(parent_inode->size) >>
+ LOG2_BLOCK_SIZE(ext4fs_root);
+
+ block_buffer = zalloc(fs->blksz);
+ if (!block_buffer)
+ goto fail;
+
+ /* get the block no allocated to a file */
+ for (blk_idx = 0; blk_idx < directory_blocks; blk_idx++) {
+ blknr = read_allocated_block(parent_inode, blk_idx);
+ if (blknr <= 0)
goto fail;
- /* read the blocks of parenet inode */
- block_buffer = zalloc(fs->blksz);
- if (!block_buffer)
- goto fail;
-
+ /* read the directory block */
status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk,
0, fs->blksz, (char *)block_buffer);
if (status == 0)
goto fail;
- dir = (struct ext2_dirent *)block_buffer;
- ptr = (char *)dir;
- totalbytes = 0;
- while (dir->direntlen >= 0) {
- /*
- * blocksize-totalbytes because last directory
- * length i.e.,*dir->direntlen is free availble
- * space in the block that means
- * it is a last entry of directory entry
- */
- if (strlen(dirname) == dir->namelen) {
- if (strncmp(dirname, ptr +
- sizeof(struct ext2_dirent),
- dir->namelen) == 0) {
- previous_dir->direntlen +=
- dir->direntlen;
- inodeno = dir->inode;
- dir->inode = 0;
- found = 1;
- break;
- }
- }
+ offset = 0;
+ do {
+ dir = (struct ext2_dirent *)(block_buffer + offset);
+ direntname = (char*)(dir) + sizeof(struct ext2_dirent);
- if (fs->blksz - totalbytes == dir->direntlen)
+ int direntlen = le16_to_cpu(dir->direntlen);
+ if (direntlen < sizeof(struct ext2_dirent))
break;
- /* traversing the each directory entry */
- templength = dir->direntlen;
- totalbytes = totalbytes + templength;
- previous_dir = dir;
- dir = (struct ext2_dirent *)((char *)dir + templength);
- ptr = (char *)dir;
- }
+ if (dir->inode && (strlen(dirname) == dir->namelen) &&
+ (strncmp(dirname, direntname, dir->namelen) == 0)) {
+ inodeno = le32_to_cpu(dir->inode);
+ break;
+ }
- if (found == 1) {
+ offset += direntlen;
+
+ } while (offset < fs->blksz);
+
+ if (inodeno > 0) {
free(block_buffer);
- block_buffer = NULL;
return inodeno;
}
-
- free(block_buffer);
- block_buffer = NULL;
}
fail:
@@ -720,7 +824,7 @@
if (matched_inode_no != -1) {
ext4fs_iget(matched_inode_no, &temp_inode);
- if (temp_inode.mode & S_IFDIR) {
+ if (le16_to_cpu(temp_inode.mode) & S_IFDIR) {
printf("It is a Directory\n");
result_inode_no = -1;
goto fail;
@@ -748,94 +852,89 @@
return result_inode_no;
}
-static int check_filename(char *filename, unsigned int blknr)
+static int unlink_filename(char *filename, unsigned int blknr)
{
- unsigned int first_block_no_of_root;
- int totalbytes = 0;
- int templength = 0;
- int status, inodeno;
- int found = 0;
- char *root_first_block_buffer = NULL;
- char *root_first_block_addr = NULL;
+ int status;
+ int inodeno = 0;
+ int offset;
+ char *block_buffer = NULL;
struct ext2_dirent *dir = NULL;
- struct ext2_dirent *previous_dir = NULL;
- char *ptr = NULL;
+ struct ext2_dirent *previous_dir;
struct ext_filesystem *fs = get_fs();
int ret = -1;
+ char *direntname;
- /* get the first block of root */
- first_block_no_of_root = blknr;
- root_first_block_buffer = zalloc(fs->blksz);
- if (!root_first_block_buffer)
+ block_buffer = zalloc(fs->blksz);
+ if (!block_buffer)
return -ENOMEM;
- root_first_block_addr = root_first_block_buffer;
- status = ext4fs_devread((lbaint_t)first_block_no_of_root *
- fs->sect_perblk, 0,
- fs->blksz, root_first_block_buffer);
+
+ /* read the directory block */
+ status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
+ fs->blksz, block_buffer);
if (status == 0)
goto fail;
- if (ext4fs_log_journal(root_first_block_buffer, first_block_no_of_root))
- goto fail;
- dir = (struct ext2_dirent *)root_first_block_buffer;
- ptr = (char *)dir;
- totalbytes = 0;
- while (dir->direntlen >= 0) {
- /*
- * blocksize-totalbytes because last
- * directory length i.e., *dir->direntlen
- * is free availble space in the block that
- * means it is a last entry of directory entry
- */
- if (strlen(filename) == dir->namelen) {
- if (strncmp(filename, ptr + sizeof(struct ext2_dirent),
- dir->namelen) == 0) {
- printf("file found deleting\n");
- previous_dir->direntlen += dir->direntlen;
- inodeno = dir->inode;
- dir->inode = 0;
- found = 1;
- break;
- }
- }
+ offset = 0;
+ do {
+ previous_dir = dir;
+ dir = (struct ext2_dirent *)(block_buffer + offset);
+ direntname = (char *)(dir) + sizeof(struct ext2_dirent);
- if (fs->blksz - totalbytes == dir->direntlen)
+ int direntlen = le16_to_cpu(dir->direntlen);
+ if (direntlen < sizeof(struct ext2_dirent))
break;
- /* traversing the each directory entry */
- templength = dir->direntlen;
- totalbytes = totalbytes + templength;
- previous_dir = dir;
- dir = (struct ext2_dirent *)((char *)dir + templength);
- ptr = (char *)dir;
- }
+ if (dir->inode && (strlen(filename) == dir->namelen) &&
+ (strncmp(direntname, filename, dir->namelen) == 0)) {
+ inodeno = le32_to_cpu(dir->inode);
+ break;
+ }
+ offset += direntlen;
- if (found == 1) {
- if (ext4fs_put_metadata(root_first_block_addr,
- first_block_no_of_root))
+ } while (offset < fs->blksz);
+
+ if (inodeno > 0) {
+ printf("file found, deleting\n");
+ if (ext4fs_log_journal(block_buffer, blknr))
+ goto fail;
+
+ if (previous_dir) {
+ /* merge dir entry with predecessor */
+ uint16_t new_len;
+ new_len = le16_to_cpu(previous_dir->direntlen);
+ new_len += le16_to_cpu(dir->direntlen);
+ previous_dir->direntlen = cpu_to_le16(new_len);
+ } else {
+ /* invalidate dir entry */
+ dir->inode = 0;
+ }
+ if (ext4fs_put_metadata(block_buffer, blknr))
goto fail;
ret = inodeno;
}
fail:
- free(root_first_block_buffer);
+ free(block_buffer);
return ret;
}
-int ext4fs_filename_check(char *filename)
+int ext4fs_filename_unlink(char *filename)
{
- short direct_blk_idx = 0;
+ int blk_idx;
long int blknr = -1;
int inodeno = -1;
+ uint32_t directory_blocks;
+
+ directory_blocks = le32_to_cpu(g_parent_inode->size) >>
+ LOG2_BLOCK_SIZE(ext4fs_root);
/* read the block no allocated to a file */
- for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS;
- direct_blk_idx++) {
- blknr = read_allocated_block(g_parent_inode, direct_blk_idx);
- if (blknr == 0)
+ for (blk_idx = 0; blk_idx < directory_blocks; blk_idx++) {
+ blknr = read_allocated_block(g_parent_inode, blk_idx);
+ if (blknr <= 0)
break;
- inodeno = check_filename(filename, blknr);
+ inodeno = unlink_filename(filename, blknr);
if (inodeno != -1)
return inodeno;
}
@@ -843,53 +942,54 @@
return -1;
}
-long int ext4fs_get_new_blk_no(void)
+uint32_t ext4fs_get_new_blk_no(void)
{
short i;
short status;
int remainder;
unsigned int bg_idx;
static int prev_bg_bitmap_index = -1;
- unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ unsigned int blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
struct ext_filesystem *fs = get_fs();
char *journal_buffer = zalloc(fs->blksz);
char *zero_buffer = zalloc(fs->blksz);
if (!journal_buffer || !zero_buffer)
goto fail;
- struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable;
if (fs->first_pass_bbmap == 0) {
for (i = 0; i < fs->no_blkgrp; i++) {
- if (bgd[i].free_blocks) {
- if (bgd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) {
- put_ext4(((uint64_t) ((uint64_t)bgd[i].block_id *
- (uint64_t)fs->blksz)),
- zero_buffer, fs->blksz);
- bgd[i].bg_flags =
- bgd[i].
- bg_flags & ~EXT4_BG_BLOCK_UNINIT;
+ struct ext2_block_group *bgd = NULL;
+ bgd = ext4fs_get_group_descriptor(fs, i);
+ if (ext4fs_bg_get_free_blocks(bgd, fs)) {
+ uint16_t bg_flags = ext4fs_bg_get_flags(bgd);
+ uint64_t b_bitmap_blk =
+ ext4fs_bg_get_block_id(bgd, fs);
+ if (bg_flags & EXT4_BG_BLOCK_UNINIT) {
memcpy(fs->blk_bmaps[i], zero_buffer,
fs->blksz);
+ put_ext4(b_bitmap_blk * fs->blksz,
+ fs->blk_bmaps[i], fs->blksz);
+ bg_flags &= ~EXT4_BG_BLOCK_UNINIT;
+ ext4fs_bg_set_flags(bgd, bg_flags);
}
fs->curr_blkno =
_get_new_blk_no(fs->blk_bmaps[i]);
if (fs->curr_blkno == -1)
- /* if block bitmap is completely fill */
+ /* block bitmap is completely filled */
continue;
fs->curr_blkno = fs->curr_blkno +
(i * fs->blksz * 8);
fs->first_pass_bbmap++;
- bgd[i].free_blocks--;
- fs->sb->free_blocks--;
- status = ext4fs_devread((lbaint_t)
- bgd[i].block_id *
- fs->sect_perblk, 0,
- fs->blksz,
+ ext4fs_bg_free_blocks_dec(bgd, fs);
+ ext4fs_sb_free_blocks_dec(fs->sb);
+ status = ext4fs_devread(b_bitmap_blk *
+ fs->sect_perblk,
+ 0, fs->blksz,
journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- bgd[i].block_id))
+ b_bitmap_blk))
goto fail;
goto success;
} else {
@@ -899,8 +999,8 @@
goto fail;
} else {
-restart:
fs->curr_blkno++;
+restart:
/* get the blockbitmap index respective to blockno */
bg_idx = fs->curr_blkno / blk_per_grp;
if (fs->blksz == 1024) {
@@ -916,45 +1016,47 @@
if (bg_idx >= fs->no_blkgrp)
goto fail;
- if (bgd[bg_idx].free_blocks == 0) {
+ struct ext2_block_group *bgd = NULL;
+ bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+ if (ext4fs_bg_get_free_blocks(bgd, fs) == 0) {
debug("block group %u is full. Skipping\n", bg_idx);
- fs->curr_blkno = fs->curr_blkno + blk_per_grp;
- fs->curr_blkno--;
+ fs->curr_blkno = (bg_idx + 1) * blk_per_grp;
+ if (fs->blksz == 1024)
+ fs->curr_blkno += 1;
goto restart;
}
- if (bgd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) {
- memset(zero_buffer, '\0', fs->blksz);
- put_ext4(((uint64_t) ((uint64_t)bgd[bg_idx].block_id *
- (uint64_t)fs->blksz)), zero_buffer, fs->blksz);
+ uint16_t bg_flags = ext4fs_bg_get_flags(bgd);
+ uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+ if (bg_flags & EXT4_BG_BLOCK_UNINIT) {
memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz);
- bgd[bg_idx].bg_flags = bgd[bg_idx].bg_flags &
- ~EXT4_BG_BLOCK_UNINIT;
+ put_ext4(b_bitmap_blk * fs->blksz,
+ zero_buffer, fs->blksz);
+ bg_flags &= ~EXT4_BG_BLOCK_UNINIT;
+ ext4fs_bg_set_flags(bgd, bg_flags);
}
if (ext4fs_set_block_bmap(fs->curr_blkno, fs->blk_bmaps[bg_idx],
bg_idx) != 0) {
debug("going for restart for the block no %ld %u\n",
fs->curr_blkno, bg_idx);
+ fs->curr_blkno++;
goto restart;
}
/* journal backup */
if (prev_bg_bitmap_index != bg_idx) {
- memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread((lbaint_t)bgd[bg_idx].block_id
- * fs->sect_perblk,
+ status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk,
0, fs->blksz, journal_buffer);
if (status == 0)
goto fail;
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
+ if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
goto fail;
prev_bg_bitmap_index = bg_idx;
}
- bgd[bg_idx].free_blocks--;
- fs->sb->free_blocks--;
+ ext4fs_bg_free_blocks_dec(bgd, fs);
+ ext4fs_sb_free_blocks_dec(fs->sb);
goto success;
}
success:
@@ -975,51 +1077,55 @@
short status;
unsigned int ibmap_idx;
static int prev_inode_bitmap_index = -1;
- unsigned int inodes_per_grp = ext4fs_root->sblock.inodes_per_group;
+ unsigned int inodes_per_grp = le32_to_cpu(ext4fs_root->sblock.inodes_per_group);
struct ext_filesystem *fs = get_fs();
char *journal_buffer = zalloc(fs->blksz);
char *zero_buffer = zalloc(fs->blksz);
if (!journal_buffer || !zero_buffer)
goto fail;
- struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable;
+ int has_gdt_chksum = le32_to_cpu(fs->sb->feature_ro_compat) &
+ EXT4_FEATURE_RO_COMPAT_GDT_CSUM ? 1 : 0;
if (fs->first_pass_ibmap == 0) {
for (i = 0; i < fs->no_blkgrp; i++) {
- if (bgd[i].free_inodes) {
- if (bgd[i].bg_itable_unused !=
- bgd[i].free_inodes)
- bgd[i].bg_itable_unused =
- bgd[i].free_inodes;
- if (bgd[i].bg_flags & EXT4_BG_INODE_UNINIT) {
- put_ext4(((uint64_t)
- ((uint64_t)bgd[i].inode_id *
- (uint64_t)fs->blksz)),
+ uint32_t free_inodes;
+ struct ext2_block_group *bgd = NULL;
+ bgd = ext4fs_get_group_descriptor(fs, i);
+ free_inodes = ext4fs_bg_get_free_inodes(bgd, fs);
+ if (free_inodes) {
+ uint16_t bg_flags = ext4fs_bg_get_flags(bgd);
+ uint64_t i_bitmap_blk =
+ ext4fs_bg_get_inode_id(bgd, fs);
+ if (has_gdt_chksum)
+ bgd->bg_itable_unused = free_inodes;
+ if (bg_flags & EXT4_BG_INODE_UNINIT) {
+ put_ext4(i_bitmap_blk * fs->blksz,
zero_buffer, fs->blksz);
- bgd[i].bg_flags = bgd[i].bg_flags &
- ~EXT4_BG_INODE_UNINIT;
+ bg_flags &= ~EXT4_BG_INODE_UNINIT;
+ ext4fs_bg_set_flags(bgd, bg_flags);
memcpy(fs->inode_bmaps[i],
zero_buffer, fs->blksz);
}
fs->curr_inode_no =
_get_new_inode_no(fs->inode_bmaps[i]);
if (fs->curr_inode_no == -1)
- /* if block bitmap is completely fill */
+ /* inode bitmap is completely filled */
continue;
fs->curr_inode_no = fs->curr_inode_no +
(i * inodes_per_grp);
fs->first_pass_ibmap++;
- bgd[i].free_inodes--;
- bgd[i].bg_itable_unused--;
- fs->sb->free_inodes--;
- status = ext4fs_devread((lbaint_t)
- bgd[i].inode_id *
- fs->sect_perblk, 0,
- fs->blksz,
+ ext4fs_bg_free_inodes_dec(bgd, fs);
+ if (has_gdt_chksum)
+ ext4fs_bg_itable_unused_dec(bgd, fs);
+ ext4fs_sb_free_inodes_dec(fs->sb);
+ status = ext4fs_devread(i_bitmap_blk *
+ fs->sect_perblk,
+ 0, fs->blksz,
journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- bgd[i].inode_id))
+ i_bitmap_blk))
goto fail;
goto success;
} else
@@ -1031,13 +1137,16 @@
fs->curr_inode_no++;
/* get the blockbitmap index respective to blockno */
ibmap_idx = fs->curr_inode_no / inodes_per_grp;
- if (bgd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) {
- memset(zero_buffer, '\0', fs->blksz);
- put_ext4(((uint64_t) ((uint64_t)bgd[ibmap_idx].inode_id *
- (uint64_t)fs->blksz)), zero_buffer,
- fs->blksz);
- bgd[ibmap_idx].bg_flags =
- bgd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT;
+ struct ext2_block_group *bgd =
+ ext4fs_get_group_descriptor(fs, ibmap_idx);
+ uint16_t bg_flags = ext4fs_bg_get_flags(bgd);
+ uint64_t i_bitmap_blk = ext4fs_bg_get_inode_id(bgd, fs);
+
+ if (bg_flags & EXT4_BG_INODE_UNINIT) {
+ put_ext4(i_bitmap_blk * fs->blksz,
+ zero_buffer, fs->blksz);
+ bg_flags &= ~EXT4_BG_INODE_UNINIT;
+ ext4fs_bg_set_flags(bgd, bg_flags);
memcpy(fs->inode_bmaps[ibmap_idx], zero_buffer,
fs->blksz);
}
@@ -1052,25 +1161,19 @@
/* journal backup */
if (prev_inode_bitmap_index != ibmap_idx) {
- memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread((lbaint_t)
- bgd[ibmap_idx].inode_id
- * fs->sect_perblk,
+ status = ext4fs_devread(i_bitmap_blk * fs->sect_perblk,
0, fs->blksz, journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- bgd[ibmap_idx].inode_id))
+ le32_to_cpu(bgd->inode_id)))
goto fail;
prev_inode_bitmap_index = ibmap_idx;
}
- if (bgd[ibmap_idx].bg_itable_unused !=
- bgd[ibmap_idx].free_inodes)
- bgd[ibmap_idx].bg_itable_unused =
- bgd[ibmap_idx].free_inodes;
- bgd[ibmap_idx].free_inodes--;
- bgd[ibmap_idx].bg_itable_unused--;
- fs->sb->free_inodes--;
+ ext4fs_bg_free_inodes_dec(bgd, fs);
+ if (has_gdt_chksum)
+ bgd->bg_itable_unused = bgd->free_inodes;
+ ext4fs_sb_free_inodes_dec(fs->sb);
goto success;
}
@@ -1097,8 +1200,8 @@
long int actual_block_no;
long int si_blockno;
/* si :single indirect */
- unsigned int *si_buffer = NULL;
- unsigned int *si_start_addr = NULL;
+ __le32 *si_buffer = NULL;
+ __le32 *si_start_addr = NULL;
struct ext_filesystem *fs = get_fs();
if (*total_remaining_blocks != 0) {
@@ -1128,7 +1231,7 @@
printf("no block left to assign\n");
goto fail;
}
- *si_buffer = actual_block_no;
+ *si_buffer = cpu_to_le32(actual_block_no);
debug("SIAB %u: %u\n", *si_buffer,
*total_remaining_blocks);
@@ -1141,7 +1244,7 @@
/* write the block to disk */
put_ext4(((uint64_t) ((uint64_t)si_blockno * (uint64_t)fs->blksz)),
si_start_addr, fs->blksz);
- file_inode->b.blocks.indir_block = si_blockno;
+ file_inode->b.blocks.indir_block = cpu_to_le32(si_blockno);
}
fail:
free(si_start_addr);
@@ -1158,10 +1261,10 @@
/* di:double indirect */
long int di_blockno_parent;
long int di_blockno_child;
- unsigned int *di_parent_buffer = NULL;
- unsigned int *di_child_buff = NULL;
- unsigned int *di_block_start_addr = NULL;
- unsigned int *di_child_buff_start = NULL;
+ __le32 *di_parent_buffer = NULL;
+ __le32 *di_child_buff = NULL;
+ __le32 *di_block_start_addr = NULL;
+ __le32 *di_child_buff_start = NULL;
struct ext_filesystem *fs = get_fs();
if (*total_remaining_blocks != 0) {
@@ -1205,7 +1308,7 @@
goto fail;
di_child_buff_start = di_child_buff;
- *di_parent_buffer = di_blockno_child;
+ *di_parent_buffer = cpu_to_le32(di_blockno_child);
di_parent_buffer++;
(*no_blks_reqd)++;
debug("DICB %ld: %u\n", di_blockno_child,
@@ -1228,7 +1331,7 @@
printf("no block left to assign\n");
goto fail;
}
- *di_child_buff = actual_block_no;
+ *di_child_buff = cpu_to_le32(actual_block_no);
debug("DIAB %ld: %u\n", actual_block_no,
*total_remaining_blocks);
@@ -1248,7 +1351,7 @@
}
put_ext4(((uint64_t) ((uint64_t)di_blockno_parent * (uint64_t)fs->blksz)),
di_block_start_addr, fs->blksz);
- file_inode->b.blocks.double_indir_block = di_blockno_parent;
+ file_inode->b.blocks.double_indir_block = cpu_to_le32(di_blockno_parent);
}
fail:
free(di_block_start_addr);
@@ -1266,12 +1369,12 @@
long int ti_gp_blockno;
long int ti_parent_blockno;
long int ti_child_blockno;
- unsigned int *ti_gp_buff = NULL;
- unsigned int *ti_parent_buff = NULL;
- unsigned int *ti_child_buff = NULL;
- unsigned int *ti_gp_buff_start_addr = NULL;
- unsigned int *ti_pbuff_start_addr = NULL;
- unsigned int *ti_cbuff_start_addr = NULL;
+ __le32 *ti_gp_buff = NULL;
+ __le32 *ti_parent_buff = NULL;
+ __le32 *ti_child_buff = NULL;
+ __le32 *ti_gp_buff_start_addr = NULL;
+ __le32 *ti_pbuff_start_addr = NULL;
+ __le32 *ti_cbuff_start_addr = NULL;
struct ext_filesystem *fs = get_fs();
if (*total_remaining_blocks != 0) {
/* triple indirect grand parent block connecting to inode */
@@ -1301,7 +1404,7 @@
goto fail;
ti_pbuff_start_addr = ti_parent_buff;
- *ti_gp_buff = ti_parent_blockno;
+ *ti_gp_buff = cpu_to_le32(ti_parent_blockno);
ti_gp_buff++;
(*no_blks_reqd)++;
debug("TIPB %ld: %u\n", ti_parent_blockno,
@@ -1319,7 +1422,7 @@
goto fail1;
ti_cbuff_start_addr = ti_child_buff;
- *ti_parent_buff = ti_child_blockno;
+ *ti_parent_buff = cpu_to_le32(ti_child_blockno);
ti_parent_buff++;
(*no_blks_reqd)++;
debug("TICB %ld: %u\n", ti_parent_blockno,
@@ -1335,7 +1438,7 @@
free(ti_cbuff_start_addr);
goto fail1;
}
- *ti_child_buff = actual_block_no;
+ *ti_child_buff = cpu_to_le32(actual_block_no);
debug("TIAB %ld: %u\n", actual_block_no,
*total_remaining_blocks);
@@ -1364,7 +1467,7 @@
/* write the grand parent block */
put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)),
ti_gp_buff_start_addr, fs->blksz);
- file_inode->b.blocks.triple_indir_block = ti_gp_blockno;
+ file_inode->b.blocks.triple_indir_block = cpu_to_le32(ti_gp_blockno);
free(ti_gp_buff_start_addr);
return;
}
@@ -1389,7 +1492,7 @@
printf("no block left to assign\n");
return;
}
- file_inode->b.blocks.dir_blocks[i] = direct_blockno;
+ file_inode->b.blocks.dir_blocks[i] = cpu_to_le32(direct_blockno);
debug("DB %ld: %u\n", direct_blockno, total_remaining_blocks);
total_remaining_blocks--;
@@ -1420,7 +1523,7 @@
index = (struct ext4_extent_idx *)(ext_block + 1);
if (le16_to_cpu(ext_block->eh_magic) != EXT4_EXT_MAGIC)
- return 0;
+ return NULL;
if (ext_block->eh_depth == 0)
return ext_block;
@@ -1432,7 +1535,7 @@
} while (fileblock >= le32_to_cpu(index[i].ei_block));
if (--i < 0)
- return 0;
+ return NULL;
block = le16_to_cpu(index[i].ei_leaf_hi);
block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo);
@@ -1441,7 +1544,7 @@
buf))
ext_block = (struct ext4_extent_header *)buf;
else
- return 0;
+ return NULL;
}
}
@@ -1451,20 +1554,20 @@
long int blkno;
unsigned int blkoff, desc_per_blk;
int log2blksz = get_fs()->dev_desc->log2blksz;
+ int desc_size = get_fs()->gdsize;
- desc_per_blk = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group);
+ desc_per_blk = EXT2_BLOCK_SIZE(data) / desc_size;
- blkno = __le32_to_cpu(data->sblock.first_data_block) + 1 +
+ blkno = le32_to_cpu(data->sblock.first_data_block) + 1 +
group / desc_per_blk;
- blkoff = (group % desc_per_blk) * sizeof(struct ext2_block_group);
+ blkoff = (group % desc_per_blk) * desc_size;
debug("ext4fs read %d group descriptor (blkno %ld blkoff %u)\n",
group, blkno, blkoff);
return ext4fs_devread((lbaint_t)blkno <<
(LOG2_BLOCK_SIZE(data) - log2blksz),
- blkoff, sizeof(struct ext2_block_group),
- (char *)blkgrp);
+ blkoff, desc_size, (char *)blkgrp);
}
int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode)
@@ -1479,14 +1582,14 @@
/* It is easier to calculate if the first inode is 0. */
ino--;
- status = ext4fs_blockgroup(data, ino / __le32_to_cpu
+ status = ext4fs_blockgroup(data, ino / le32_to_cpu
(sblock->inodes_per_group), &blkgrp);
if (status == 0)
return 0;
inodes_per_block = EXT2_BLOCK_SIZE(data) / fs->inodesz;
- blkno = __le32_to_cpu(blkgrp.inode_table_id) +
- (ino % __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
+ blkno = ext4fs_bg_get_inode_table_id(&blkgrp, fs) +
+ (ino % le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
blkoff = (ino % inodes_per_block) * fs->inodesz;
/* Read the inode. */
status = ext4fs_devread((lbaint_t)blkno << (LOG2_BLOCK_SIZE(data) -
@@ -1514,12 +1617,13 @@
- get_fs()->dev_desc->log2blksz;
if (le32_to_cpu(inode->flags) & EXT4_EXTENTS_FL) {
+ long int startblock, endblock;
char *buf = zalloc(blksz);
if (!buf)
return -ENOMEM;
struct ext4_extent_header *ext_block;
struct ext4_extent *extent;
- int i = -1;
+ int i;
ext_block =
ext4fs_get_extent_block(ext4fs_root, buf,
(struct ext4_extent_header *)
@@ -1533,33 +1637,31 @@
extent = (struct ext4_extent *)(ext_block + 1);
- do {
- i++;
- if (i >= le16_to_cpu(ext_block->eh_entries))
- break;
- } while (fileblock >= le32_to_cpu(extent[i].ee_block));
- if (--i >= 0) {
- fileblock -= le32_to_cpu(extent[i].ee_block);
- if (fileblock >= le16_to_cpu(extent[i].ee_len)) {
+ for (i = 0; i < le16_to_cpu(ext_block->eh_entries); i++) {
+ startblock = le32_to_cpu(extent[i].ee_block);
+ endblock = startblock + le16_to_cpu(extent[i].ee_len);
+
+ if (startblock > fileblock) {
+ /* Sparse file */
free(buf);
return 0;
- }
- start = le16_to_cpu(extent[i].ee_start_hi);
- start = (start << 32) +
+ } else if (fileblock < endblock) {
+ start = le16_to_cpu(extent[i].ee_start_hi);
+ start = (start << 32) +
le32_to_cpu(extent[i].ee_start_lo);
- free(buf);
- return fileblock + start;
+ free(buf);
+ return (fileblock - startblock) + start;
+ }
}
- printf("Extent Error\n");
free(buf);
- return -1;
+ return 0;
}
/* Direct blocks. */
if (fileblock < INDIRECT_BLOCKS)
- blknr = __le32_to_cpu(inode->b.blocks.dir_blocks[fileblock]);
+ blknr = le32_to_cpu(inode->b.blocks.dir_blocks[fileblock]);
/* Indirect. */
else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) {
@@ -1586,23 +1688,23 @@
}
ext4fs_indir1_size = blksz;
}
- if ((__le32_to_cpu(inode->b.blocks.indir_block) <<
+ if ((le32_to_cpu(inode->b.blocks.indir_block) <<
log2_blksz) != ext4fs_indir1_blkno) {
status =
- ext4fs_devread((lbaint_t)__le32_to_cpu
+ ext4fs_devread((lbaint_t)le32_to_cpu
(inode->b.blocks.
indir_block) << log2_blksz, 0,
blksz, (char *)ext4fs_indir1_block);
if (status == 0) {
printf("** SI ext2fs read block (indir 1)"
"failed. **\n");
- return 0;
+ return -1;
}
ext4fs_indir1_blkno =
- __le32_to_cpu(inode->b.blocks.
+ le32_to_cpu(inode->b.blocks.
indir_block) << log2_blksz;
}
- blknr = __le32_to_cpu(ext4fs_indir1_block
+ blknr = le32_to_cpu(ext4fs_indir1_block
[fileblock - INDIRECT_BLOCKS]);
}
/* Double indirect. */
@@ -1635,10 +1737,10 @@
}
ext4fs_indir1_size = blksz;
}
- if ((__le32_to_cpu(inode->b.blocks.double_indir_block) <<
+ if ((le32_to_cpu(inode->b.blocks.double_indir_block) <<
log2_blksz) != ext4fs_indir1_blkno) {
status =
- ext4fs_devread((lbaint_t)__le32_to_cpu
+ ext4fs_devread((lbaint_t)le32_to_cpu
(inode->b.blocks.
double_indir_block) << log2_blksz,
0, blksz,
@@ -1649,7 +1751,7 @@
return -1;
}
ext4fs_indir1_blkno =
- __le32_to_cpu(inode->b.blocks.double_indir_block) <<
+ le32_to_cpu(inode->b.blocks.double_indir_block) <<
log2_blksz;
}
@@ -1676,9 +1778,9 @@
}
ext4fs_indir2_size = blksz;
}
- if ((__le32_to_cpu(ext4fs_indir1_block[rblock / perblock]) <<
+ if ((le32_to_cpu(ext4fs_indir1_block[rblock / perblock]) <<
log2_blksz) != ext4fs_indir2_blkno) {
- status = ext4fs_devread((lbaint_t)__le32_to_cpu
+ status = ext4fs_devread((lbaint_t)le32_to_cpu
(ext4fs_indir1_block
[rblock /
perblock]) << log2_blksz, 0,
@@ -1690,12 +1792,12 @@
return -1;
}
ext4fs_indir2_blkno =
- __le32_to_cpu(ext4fs_indir1_block[rblock
+ le32_to_cpu(ext4fs_indir1_block[rblock
/
perblock]) <<
log2_blksz;
}
- blknr = __le32_to_cpu(ext4fs_indir2_block[rblock % perblock]);
+ blknr = le32_to_cpu(ext4fs_indir2_block[rblock % perblock]);
}
/* Tripple indirect. */
else {
@@ -1727,11 +1829,11 @@
}
ext4fs_indir1_size = blksz;
}
- if ((__le32_to_cpu(inode->b.blocks.triple_indir_block) <<
+ if ((le32_to_cpu(inode->b.blocks.triple_indir_block) <<
log2_blksz) != ext4fs_indir1_blkno) {
status = ext4fs_devread
((lbaint_t)
- __le32_to_cpu(inode->b.blocks.triple_indir_block)
+ le32_to_cpu(inode->b.blocks.triple_indir_block)
<< log2_blksz, 0, blksz,
(char *)ext4fs_indir1_block);
if (status == 0) {
@@ -1740,7 +1842,7 @@
return -1;
}
ext4fs_indir1_blkno =
- __le32_to_cpu(inode->b.blocks.triple_indir_block) <<
+ le32_to_cpu(inode->b.blocks.triple_indir_block) <<
log2_blksz;
}
@@ -1767,11 +1869,11 @@
}
ext4fs_indir2_size = blksz;
}
- if ((__le32_to_cpu(ext4fs_indir1_block[rblock /
+ if ((le32_to_cpu(ext4fs_indir1_block[rblock /
perblock_parent]) <<
log2_blksz)
!= ext4fs_indir2_blkno) {
- status = ext4fs_devread((lbaint_t)__le32_to_cpu
+ status = ext4fs_devread((lbaint_t)le32_to_cpu
(ext4fs_indir1_block
[rblock /
perblock_parent]) <<
@@ -1783,7 +1885,7 @@
return -1;
}
ext4fs_indir2_blkno =
- __le32_to_cpu(ext4fs_indir1_block[rblock /
+ le32_to_cpu(ext4fs_indir1_block[rblock /
perblock_parent])
<< log2_blksz;
}
@@ -1811,12 +1913,12 @@
}
ext4fs_indir3_size = blksz;
}
- if ((__le32_to_cpu(ext4fs_indir2_block[rblock
+ if ((le32_to_cpu(ext4fs_indir2_block[rblock
/
perblock_child]) <<
log2_blksz) != ext4fs_indir3_blkno) {
status =
- ext4fs_devread((lbaint_t)__le32_to_cpu
+ ext4fs_devread((lbaint_t)le32_to_cpu
(ext4fs_indir2_block
[(rblock / perblock_child)
% (blksz / 4)]) << log2_blksz, 0,
@@ -1827,14 +1929,14 @@
return -1;
}
ext4fs_indir3_blkno =
- __le32_to_cpu(ext4fs_indir2_block[(rblock /
+ le32_to_cpu(ext4fs_indir2_block[(rblock /
perblock_child) %
(blksz /
4)]) <<
log2_blksz;
}
- blknr = __le32_to_cpu(ext4fs_indir3_block
+ blknr = le32_to_cpu(ext4fs_indir3_block
[rblock % perblock_child]);
}
debug("read_allocated_block %ld\n", blknr);
@@ -1907,7 +2009,7 @@
return 0;
}
/* Search the file. */
- while (fpos < __le32_to_cpu(diro->inode.size)) {
+ while (fpos < le32_to_cpu(diro->inode.size)) {
struct ext2_dirent dirent;
status = ext4fs_read_file(diro, fpos,
@@ -1939,7 +2041,7 @@
return 0;
fdiro->data = diro->data;
- fdiro->ino = __le32_to_cpu(dirent.inode);
+ fdiro->ino = le32_to_cpu(dirent.inode);
filename[dirent.namelen] = '\0';
@@ -1954,7 +2056,7 @@
type = FILETYPE_REG;
} else {
status = ext4fs_read_inode(diro->data,
- __le32_to_cpu
+ le32_to_cpu
(dirent.inode),
&fdiro->inode);
if (status == 0) {
@@ -1963,15 +2065,15 @@
}
fdiro->inode_read = 1;
- if ((__le16_to_cpu(fdiro->inode.mode) &
+ if ((le16_to_cpu(fdiro->inode.mode) &
FILETYPE_INO_MASK) ==
FILETYPE_INO_DIRECTORY) {
type = FILETYPE_DIRECTORY;
- } else if ((__le16_to_cpu(fdiro->inode.mode)
+ } else if ((le16_to_cpu(fdiro->inode.mode)
& FILETYPE_INO_MASK) ==
FILETYPE_INO_SYMLINK) {
type = FILETYPE_SYMLINK;
- } else if ((__le16_to_cpu(fdiro->inode.mode)
+ } else if ((le16_to_cpu(fdiro->inode.mode)
& FILETYPE_INO_MASK) ==
FILETYPE_INO_REG) {
type = FILETYPE_REG;
@@ -1990,7 +2092,7 @@
} else {
if (fdiro->inode_read == 0) {
status = ext4fs_read_inode(diro->data,
- __le32_to_cpu(
+ le32_to_cpu(
dirent.inode),
&fdiro->inode);
if (status == 0) {
@@ -2014,12 +2116,12 @@
break;
}
printf("%10u %s\n",
- __le32_to_cpu(fdiro->inode.size),
+ le32_to_cpu(fdiro->inode.size),
filename);
}
free(fdiro);
}
- fpos += __le16_to_cpu(dirent.direntlen);
+ fpos += le16_to_cpu(dirent.direntlen);
}
return 0;
}
@@ -2034,25 +2136,25 @@
if (!diro->inode_read) {
status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
if (status == 0)
- return 0;
+ return NULL;
}
- symlink = zalloc(__le32_to_cpu(diro->inode.size) + 1);
+ symlink = zalloc(le32_to_cpu(diro->inode.size) + 1);
if (!symlink)
- return 0;
+ return NULL;
- if (__le32_to_cpu(diro->inode.size) < sizeof(diro->inode.b.symlink)) {
+ if (le32_to_cpu(diro->inode.size) < sizeof(diro->inode.b.symlink)) {
strncpy(symlink, diro->inode.b.symlink,
- __le32_to_cpu(diro->inode.size));
+ le32_to_cpu(diro->inode.size));
} else {
status = ext4fs_read_file(diro, 0,
- __le32_to_cpu(diro->inode.size),
+ le32_to_cpu(diro->inode.size),
symlink, &actread);
if ((status < 0) || (actread == 0)) {
free(symlink);
- return 0;
+ return NULL;
}
}
- symlink[__le32_to_cpu(diro->inode.size)] = '\0';
+ symlink[le32_to_cpu(diro->inode.size)] = '\0';
return symlink;
}
@@ -2200,7 +2302,7 @@
if (status == 0)
goto fail;
}
- *len = __le32_to_cpu(fdiro->inode.size);
+ *len = le32_to_cpu(fdiro->inode.size);
ext4fs_file = fdiro;
return 0;
@@ -2226,26 +2328,28 @@
goto fail;
/* Make sure this is an ext2 filesystem. */
- if (__le16_to_cpu(data->sblock.magic) != EXT2_MAGIC)
+ if (le16_to_cpu(data->sblock.magic) != EXT2_MAGIC)
goto fail;
- /*
- * The 64bit feature was enabled when metadata_csum was enabled
- * and we do not support metadata_csum (and cannot reliably find
- * files when it is set. Refuse to mount.
- */
- if (data->sblock.feature_incompat & EXT4_FEATURE_INCOMPAT_64BIT) {
- printf("Unsupported feature found (64bit, possibly metadata_csum), not mounting\n");
- goto fail;
+
+ if (le32_to_cpu(data->sblock.revision_level) == 0) {
+ fs->inodesz = 128;
+ fs->gdsize = 32;
+ } else {
+ debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n",
+ __le32_to_cpu(data->sblock.feature_compatibility),
+ __le32_to_cpu(data->sblock.feature_incompat),
+ __le32_to_cpu(data->sblock.feature_ro_compat));
+
+ fs->inodesz = le16_to_cpu(data->sblock.inode_size);
+ fs->gdsize = le32_to_cpu(data->sblock.feature_incompat) &
+ EXT4_FEATURE_INCOMPAT_64BIT ?
+ le16_to_cpu(data->sblock.descriptor_size) : 32;
}
- if (__le32_to_cpu(data->sblock.revision_level == 0))
- fs->inodesz = 128;
- else
- fs->inodesz = __le16_to_cpu(data->sblock.inode_size);
-
- debug("EXT2 rev %d, inode_size %d\n",
- __le32_to_cpu(data->sblock.revision_level), fs->inodesz);
+ debug("EXT2 rev %d, inode_size %d, descriptor size %d\n",
+ le32_to_cpu(data->sblock.revision_level),
+ fs->inodesz, fs->gdsize);
data->diropen.data = data;
data->diropen.ino = 2;
diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h
index 48fd2ac..04d5602 100644
--- a/fs/ext4/ext4_common.h
+++ b/fs/ext4/ext4_common.h
@@ -24,7 +24,7 @@
#include <ext_common.h>
#include <ext4fs.h>
#include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#if defined(CONFIG_EXT4_WRITE)
#include "ext4_journal.h"
#include "crc16.h"
@@ -59,10 +59,10 @@
#if defined(CONFIG_EXT4_WRITE)
uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n);
-int ext4fs_checksum_update(unsigned int i);
+uint16_t ext4fs_checksum_update(unsigned int i);
int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags);
-void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type);
-long int ext4fs_get_new_blk_no(void);
+int ext4fs_update_parent_dentry(char *filename, int file_type);
+uint32_t ext4fs_get_new_blk_no(void);
int ext4fs_get_new_inode_no(void);
void ext4fs_reset_block_bmap(long int blockno, unsigned char *buffer,
int index);
@@ -74,5 +74,17 @@
unsigned int total_remaining_blocks,
unsigned int *total_no_of_block);
void put_ext4(uint64_t off, void *buf, uint32_t size);
+struct ext2_block_group *ext4fs_get_group_descriptor
+ (const struct ext_filesystem *fs, uint32_t bg_idx);
+uint64_t ext4fs_bg_get_block_id(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs);
+uint64_t ext4fs_bg_get_inode_id(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs);
+uint64_t ext4fs_bg_get_inode_table_id(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs);
+uint64_t ext4fs_sb_get_free_blocks(const struct ext2_sblock *sb);
+void ext4fs_sb_set_free_blocks(struct ext2_sblock *sb, uint64_t free_blocks);
+uint32_t ext4fs_bg_get_free_blocks(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs);
#endif
#endif
diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c
index 3f61335..5a25be4 100644
--- a/fs/ext4/ext4_journal.c
+++ b/fs/ext4/ext4_journal.c
@@ -151,7 +151,7 @@
* journal_buffer -- Buffer containing meta data
* blknr -- Block number on disk of the meta data buffer
*/
-int ext4fs_log_journal(char *journal_buffer, long int blknr)
+int ext4fs_log_journal(char *journal_buffer, uint32_t blknr)
{
struct ext_filesystem *fs = get_fs();
short i;
@@ -183,14 +183,18 @@
* metadata_buffer -- Buffer containing meta data
* blknr -- Block number on disk of the meta data buffer
*/
-int ext4fs_put_metadata(char *metadata_buffer, long int blknr)
+int ext4fs_put_metadata(char *metadata_buffer, uint32_t blknr)
{
struct ext_filesystem *fs = get_fs();
if (!metadata_buffer) {
printf("Invalid input arguments %s\n", __func__);
return -EINVAL;
}
- dirty_block_ptr[gd_index]->buf = zalloc(fs->blksz);
+ if (dirty_block_ptr[gd_index]->buf)
+ assert(dirty_block_ptr[gd_index]->blknr == blknr);
+ else
+ dirty_block_ptr[gd_index]->buf = zalloc(fs->blksz);
+
if (!dirty_block_ptr[gd_index]->buf)
return -ENOMEM;
memcpy(dirty_block_ptr[gd_index]->buf, metadata_buffer, fs->blksz);
@@ -215,7 +219,7 @@
printf("total bytes %d\n", max);
while (offset < max) {
- blocknr = be32_to_cpu(*((long int *)(revk_blk + offset)));
+ blocknr = be32_to_cpu(*((__be32 *)(revk_blk + offset)));
printf("revoke blknr is %ld\n", blocknr);
offset += 4;
}
@@ -302,7 +306,7 @@
max = be32_to_cpu(header->r_count);
while (offset < max) {
- blocknr = be32_to_cpu(*((long int *)
+ blocknr = be32_to_cpu(*((__be32 *)
(revk_blk + offset)));
if (blocknr == blknr)
goto found;
@@ -420,7 +424,7 @@
temp_buff);
jsb = (struct journal_superblock_t *) temp_buff;
- if (fs->sb->feature_incompat & EXT3_FEATURE_INCOMPAT_RECOVER) {
+ if (le32_to_cpu(fs->sb->feature_incompat) & EXT3_FEATURE_INCOMPAT_RECOVER) {
if (recovery_flag == RECOVER)
printf("Recovery required\n");
} else {
@@ -517,11 +521,14 @@
end:
if (recovery_flag == RECOVER) {
+ uint32_t new_feature_incompat;
jsb->s_start = cpu_to_be32(1);
jsb->s_sequence = cpu_to_be32(be32_to_cpu(jsb->s_sequence) + 1);
/* get the superblock */
ext4_read_superblock((char *)fs->sb);
- fs->sb->feature_incompat |= EXT3_FEATURE_INCOMPAT_RECOVER;
+ new_feature_incompat = le32_to_cpu(fs->sb->feature_incompat);
+ new_feature_incompat |= EXT3_FEATURE_INCOMPAT_RECOVER;
+ fs->sb->feature_incompat = cpu_to_le32(new_feature_incompat);
/* Update the super block */
put_ext4((uint64_t) (SUPERBLOCK_SIZE),
diff --git a/fs/ext4/ext4_journal.h b/fs/ext4/ext4_journal.h
index d926094..3d05ad5 100644
--- a/fs/ext4/ext4_journal.h
+++ b/fs/ext4/ext4_journal.h
@@ -49,9 +49,9 @@
/* Standard header for all descriptor blocks: */
struct journal_header_t {
- __u32 h_magic;
- __u32 h_blocktype;
- __u32 h_sequence;
+ __be32 h_magic;
+ __be32 h_blocktype;
+ __be32 h_sequence;
};
/* The journal superblock. All fields are in big-endian byte order. */
@@ -60,35 +60,35 @@
struct journal_header_t s_header;
/* Static information describing the journal */
- __u32 s_blocksize; /* journal device blocksize */
- __u32 s_maxlen; /* total blocks in journal file */
- __u32 s_first; /* first block of log information */
+ __be32 s_blocksize; /* journal device blocksize */
+ __be32 s_maxlen; /* total blocks in journal file */
+ __be32 s_first; /* first block of log information */
/* Dynamic information describing the current state of the log */
- __u32 s_sequence; /* first commit ID expected in log */
- __u32 s_start; /* blocknr of start of log */
+ __be32 s_sequence; /* first commit ID expected in log */
+ __be32 s_start; /* blocknr of start of log */
/* Error value, as set by journal_abort(). */
- __s32 s_errno;
+ __be32 s_errno;
/* Remaining fields are only valid in a version-2 superblock */
- __u32 s_feature_compat; /* compatible feature set */
- __u32 s_feature_incompat; /* incompatible feature set */
- __u32 s_feature_ro_compat; /* readonly-compatible feature set */
+ __be32 s_feature_compat; /* compatible feature set */
+ __be32 s_feature_incompat; /* incompatible feature set */
+ __be32 s_feature_ro_compat; /* readonly-compatible feature set */
/* 0x0030 */
__u8 s_uuid[16]; /* 128-bit uuid for journal */
/* 0x0040 */
- __u32 s_nr_users; /* Nr of filesystems sharing log */
+ __be32 s_nr_users; /* Nr of filesystems sharing log */
- __u32 s_dynsuper; /* Blocknr of dynamic superblock copy */
+ __be32 s_dynsuper; /* Blocknr of dynamic superblock copy */
/* 0x0048 */
- __u32 s_max_transaction; /* Limit of journal blocks per trans. */
- __u32 s_max_trans_data; /* Limit of data blocks per trans. */
+ __be32 s_max_transaction; /* Limit of journal blocks per trans. */
+ __be32 s_max_trans_data; /* Limit of data blocks per trans. */
/* 0x0050 */
- __u32 s_padding[44];
+ __be32 s_padding[44];
/* 0x0100 */
__u8 s_users[16 * 48]; /* ids of all fs'es sharing the log */
@@ -96,13 +96,13 @@
} ;
struct ext3_journal_block_tag {
- uint32_t block;
- uint32_t flags;
+ __be32 block;
+ __be32 flags;
};
struct journal_revoke_header_t {
struct journal_header_t r_header;
- int r_count; /* Count of bytes used in the block */
+ __be32 r_count; /* Count of bytes used in the block */
};
struct revoke_blk_list {
@@ -115,8 +115,8 @@
int ext4fs_init_journal(void);
int ext4fs_log_gdt(char *gd_table);
int ext4fs_check_journal_state(int recovery_flag);
-int ext4fs_log_journal(char *journal_buffer, long int blknr);
-int ext4fs_put_metadata(char *metadata_buffer, long int blknr);
+int ext4fs_log_journal(char *journal_buffer, uint32_t blknr);
+int ext4fs_put_metadata(char *metadata_buffer, uint32_t blknr);
void ext4fs_update_journal(void);
void ext4fs_dump_metadata(void);
void ext4fs_push_revoke_blk(char *buffer);
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index e027916..d710a86 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -28,26 +28,67 @@
#include <div64.h>
#include "ext4_common.h"
+static inline void ext4fs_sb_free_inodes_inc(struct ext2_sblock *sb)
+{
+ sb->free_inodes = cpu_to_le32(le32_to_cpu(sb->free_inodes) + 1);
+}
+
+static inline void ext4fs_sb_free_blocks_inc(struct ext2_sblock *sb)
+{
+ sb->free_blocks = cpu_to_le32(le32_to_cpu(sb->free_blocks) + 1);
+}
+
+static inline void ext4fs_bg_free_inodes_inc
+ (struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+ uint32_t free_inodes = le16_to_cpu(bg->free_inodes);
+ if (fs->gdsize == 64)
+ free_inodes += le16_to_cpu(bg->free_inodes_high) << 16;
+ free_inodes++;
+
+ bg->free_inodes = cpu_to_le16(free_inodes & 0xffff);
+ if (fs->gdsize == 64)
+ bg->free_inodes_high = cpu_to_le16(free_inodes >> 16);
+}
+
+static inline void ext4fs_bg_free_blocks_inc
+ (struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+ uint32_t free_blocks = le16_to_cpu(bg->free_blocks);
+ if (fs->gdsize == 64)
+ free_blocks += le16_to_cpu(bg->free_blocks_high) << 16;
+ free_blocks++;
+
+ bg->free_blocks = cpu_to_le16(free_blocks & 0xffff);
+ if (fs->gdsize == 64)
+ bg->free_blocks_high = cpu_to_le16(free_blocks >> 16);
+}
+
static void ext4fs_update(void)
{
short i;
ext4fs_update_journal();
struct ext_filesystem *fs = get_fs();
+ struct ext2_block_group *bgd = NULL;
/* update super block */
put_ext4((uint64_t)(SUPERBLOCK_SIZE),
(struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
- /* update block groups */
+ /* update block bitmaps */
for (i = 0; i < fs->no_blkgrp; i++) {
- fs->bgd[i].bg_checksum = ext4fs_checksum_update(i);
- put_ext4((uint64_t)((uint64_t)fs->bgd[i].block_id * (uint64_t)fs->blksz),
+ bgd = ext4fs_get_group_descriptor(fs, i);
+ bgd->bg_checksum = cpu_to_le16(ext4fs_checksum_update(i));
+ uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+ put_ext4(b_bitmap_blk * fs->blksz,
fs->blk_bmaps[i], fs->blksz);
}
- /* update inode table groups */
+ /* update inode bitmaps */
for (i = 0; i < fs->no_blkgrp; i++) {
- put_ext4((uint64_t) ((uint64_t)fs->bgd[i].inode_id * (uint64_t)fs->blksz),
+ bgd = ext4fs_get_group_descriptor(fs, i);
+ uint64_t i_bitmap_blk = ext4fs_bg_get_inode_id(bgd, fs);
+ put_ext4(i_bitmap_blk * fs->blksz,
fs->inode_bmaps[i], fs->blksz);
}
@@ -65,15 +106,12 @@
int ext4fs_get_bgdtable(void)
{
int status;
- int grp_desc_size;
struct ext_filesystem *fs = get_fs();
- grp_desc_size = sizeof(struct ext2_block_group);
- fs->no_blk_pergdt = (fs->no_blkgrp * grp_desc_size) / fs->blksz;
- if ((fs->no_blkgrp * grp_desc_size) % fs->blksz)
- fs->no_blk_pergdt++;
+ int gdsize_total = ROUND(fs->no_blkgrp * fs->gdsize, fs->blksz);
+ fs->no_blk_pergdt = gdsize_total / fs->blksz;
/* allocate memory for gdtable */
- fs->gdtable = zalloc(fs->blksz * fs->no_blk_pergdt);
+ fs->gdtable = zalloc(gdsize_total);
if (!fs->gdtable)
return -ENOMEM;
/* read the group descriptor table */
@@ -99,24 +137,22 @@
{
struct ext2_block_group *bgd = NULL;
static int prev_bg_bmap_idx = -1;
- long int blknr;
+ uint32_t blknr;
int remainder;
int bg_idx;
int status;
- unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
struct ext_filesystem *fs = get_fs();
char *journal_buffer = zalloc(fs->blksz);
if (!journal_buffer) {
printf("No memory\n");
return;
}
- /* get block group descriptor table */
- bgd = (struct ext2_block_group *)fs->gdtable;
/* deleting the single indirect block associated with inode */
if (inode->b.blocks.indir_block != 0) {
- debug("SIPB releasing %u\n", inode->b.blocks.indir_block);
- blknr = inode->b.blocks.indir_block;
+ blknr = le32_to_cpu(inode->b.blocks.indir_block);
+ debug("SIPB releasing %u\n", blknr);
bg_idx = blknr / blk_per_grp;
if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
@@ -124,18 +160,19 @@
bg_idx--;
}
ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
+ /* get block group descriptor table */
+ bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+ ext4fs_bg_free_blocks_inc(bgd, fs);
+ ext4fs_sb_free_blocks_inc(fs->sb);
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
- status =
- ext4fs_devread((lbaint_t)bgd[bg_idx].block_id *
- fs->sect_perblk, 0, fs->blksz,
- journal_buffer);
+ uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+ status = ext4fs_devread(
+ b_bitmap_blk * fs->sect_perblk,
+ 0, fs->blksz, journal_buffer);
if (status == 0)
goto fail;
- if (ext4fs_log_journal
- (journal_buffer, bgd[bg_idx].block_id))
+ if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
@@ -149,12 +186,12 @@
int i;
short status;
static int prev_bg_bmap_idx = -1;
- long int blknr;
+ uint32_t blknr;
int remainder;
int bg_idx;
- unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
- unsigned int *di_buffer = NULL;
- unsigned int *DIB_start_addr = NULL;
+ uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
+ __le32 *di_buffer = NULL;
+ void *dib_start_addr = NULL;
struct ext2_block_group *bgd = NULL;
struct ext_filesystem *fs = get_fs();
char *journal_buffer = zalloc(fs->blksz);
@@ -162,8 +199,6 @@
printf("No memory\n");
return;
}
- /* get the block group descriptor table */
- bgd = (struct ext2_block_group *)fs->gdtable;
if (inode->b.blocks.double_indir_block != 0) {
di_buffer = zalloc(fs->blksz);
@@ -171,8 +206,8 @@
printf("No memory\n");
return;
}
- DIB_start_addr = (unsigned int *)di_buffer;
- blknr = inode->b.blocks.double_indir_block;
+ dib_start_addr = di_buffer;
+ blknr = le32_to_cpu(inode->b.blocks.double_indir_block);
status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
fs->blksz, (char *)di_buffer);
for (i = 0; i < fs->blksz / sizeof(int); i++) {
@@ -180,21 +215,24 @@
break;
debug("DICB releasing %u\n", *di_buffer);
- bg_idx = *di_buffer / blk_per_grp;
+ bg_idx = le32_to_cpu(*di_buffer) / blk_per_grp;
if (fs->blksz == 1024) {
- remainder = *di_buffer % blk_per_grp;
+ remainder = le32_to_cpu(*di_buffer) % blk_per_grp;
if (!remainder)
bg_idx--;
}
- ext4fs_reset_block_bmap(*di_buffer,
+ /* get block group descriptor table */
+ bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+ ext4fs_reset_block_bmap(le32_to_cpu(*di_buffer),
fs->blk_bmaps[bg_idx], bg_idx);
di_buffer++;
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
+ ext4fs_bg_free_blocks_inc(bgd, fs);
+ ext4fs_sb_free_blocks_inc(fs->sb);
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
- status = ext4fs_devread((lbaint_t)
- bgd[bg_idx].block_id
+ uint64_t b_bitmap_blk =
+ ext4fs_bg_get_block_id(bgd, fs);
+ status = ext4fs_devread(b_bitmap_blk
* fs->sect_perblk, 0,
fs->blksz,
journal_buffer);
@@ -202,41 +240,41 @@
goto fail;
if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
+ b_bitmap_blk))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
}
/* removing the parent double indirect block */
- blknr = inode->b.blocks.double_indir_block;
+ blknr = le32_to_cpu(inode->b.blocks.double_indir_block);
bg_idx = blknr / blk_per_grp;
if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
if (!remainder)
bg_idx--;
}
+ /* get block group descriptor table */
+ bgd = ext4fs_get_group_descriptor(fs, bg_idx);
ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
+ ext4fs_bg_free_blocks_inc(bgd, fs);
+ ext4fs_sb_free_blocks_inc(fs->sb);
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
- memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread((lbaint_t)bgd[bg_idx].block_id *
- fs->sect_perblk, 0, fs->blksz,
- journal_buffer);
+ uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+ status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk,
+ 0, fs->blksz, journal_buffer);
if (status == 0)
goto fail;
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
+ if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
- debug("DIPB releasing %ld\n", blknr);
+ debug("DIPB releasing %d\n", blknr);
}
fail:
- free(DIB_start_addr);
+ free(dib_start_addr);
free(journal_buffer);
}
@@ -245,14 +283,14 @@
int i, j;
short status;
static int prev_bg_bmap_idx = -1;
- long int blknr;
+ uint32_t blknr;
int remainder;
int bg_idx;
- unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
- unsigned int *tigp_buffer = NULL;
- unsigned int *tib_start_addr = NULL;
- unsigned int *tip_buffer = NULL;
- unsigned int *tipb_start_addr = NULL;
+ uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
+ __le32 *tigp_buffer = NULL;
+ void *tib_start_addr = NULL;
+ __le32 *tip_buffer = NULL;
+ void *tipb_start_addr = NULL;
struct ext2_block_group *bgd = NULL;
struct ext_filesystem *fs = get_fs();
char *journal_buffer = zalloc(fs->blksz);
@@ -260,8 +298,6 @@
printf("No memory\n");
return;
}
- /* get block group descriptor table */
- bgd = (struct ext2_block_group *)fs->gdtable;
if (inode->b.blocks.triple_indir_block != 0) {
tigp_buffer = zalloc(fs->blksz);
@@ -269,8 +305,8 @@
printf("No memory\n");
return;
}
- tib_start_addr = (unsigned int *)tigp_buffer;
- blknr = inode->b.blocks.triple_indir_block;
+ tib_start_addr = tigp_buffer;
+ blknr = le32_to_cpu(inode->b.blocks.triple_indir_block);
status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
fs->blksz, (char *)tigp_buffer);
for (i = 0; i < fs->blksz / sizeof(int); i++) {
@@ -281,33 +317,36 @@
tip_buffer = zalloc(fs->blksz);
if (!tip_buffer)
goto fail;
- tipb_start_addr = (unsigned int *)tip_buffer;
- status = ext4fs_devread((lbaint_t)(*tigp_buffer) *
+ tipb_start_addr = tip_buffer;
+ status = ext4fs_devread((lbaint_t)le32_to_cpu(*tigp_buffer) *
fs->sect_perblk, 0, fs->blksz,
(char *)tip_buffer);
for (j = 0; j < fs->blksz / sizeof(int); j++) {
- if (*tip_buffer == 0)
+ if (le32_to_cpu(*tip_buffer) == 0)
break;
- bg_idx = *tip_buffer / blk_per_grp;
+ bg_idx = le32_to_cpu(*tip_buffer) / blk_per_grp;
if (fs->blksz == 1024) {
- remainder = *tip_buffer % blk_per_grp;
+ remainder = le32_to_cpu(*tip_buffer) % blk_per_grp;
if (!remainder)
bg_idx--;
}
- ext4fs_reset_block_bmap(*tip_buffer,
+ ext4fs_reset_block_bmap(le32_to_cpu(*tip_buffer),
fs->blk_bmaps[bg_idx],
bg_idx);
tip_buffer++;
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
+ /* get block group descriptor table */
+ bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+ ext4fs_bg_free_blocks_inc(bgd, fs);
+ ext4fs_sb_free_blocks_inc(fs->sb);
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
+ uint64_t b_bitmap_blk =
+ ext4fs_bg_get_block_id(bgd, fs);
status =
ext4fs_devread(
- (lbaint_t)
- bgd[bg_idx].block_id *
+ b_bitmap_blk *
fs->sect_perblk, 0,
fs->blksz,
journal_buffer);
@@ -315,8 +354,7 @@
goto fail;
if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].
- block_id))
+ b_bitmap_blk))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
@@ -328,38 +366,41 @@
* removing the grand parent blocks
* which is connected to inode
*/
- bg_idx = *tigp_buffer / blk_per_grp;
+ bg_idx = le32_to_cpu(*tigp_buffer) / blk_per_grp;
if (fs->blksz == 1024) {
- remainder = *tigp_buffer % blk_per_grp;
+ remainder = le32_to_cpu(*tigp_buffer) % blk_per_grp;
if (!remainder)
bg_idx--;
}
- ext4fs_reset_block_bmap(*tigp_buffer,
+ ext4fs_reset_block_bmap(le32_to_cpu(*tigp_buffer),
fs->blk_bmaps[bg_idx], bg_idx);
tigp_buffer++;
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
+ /* get block group descriptor table */
+ bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+ ext4fs_bg_free_blocks_inc(bgd, fs);
+ ext4fs_sb_free_blocks_inc(fs->sb);
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
+ uint64_t b_bitmap_blk =
+ ext4fs_bg_get_block_id(bgd, fs);
memset(journal_buffer, '\0', fs->blksz);
- status =
- ext4fs_devread((lbaint_t)
- bgd[bg_idx].block_id *
- fs->sect_perblk, 0,
- fs->blksz, journal_buffer);
+ status = ext4fs_devread(b_bitmap_blk *
+ fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
+ b_bitmap_blk))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
}
/* removing the grand parent triple indirect block */
- blknr = inode->b.blocks.triple_indir_block;
+ blknr = le32_to_cpu(inode->b.blocks.triple_indir_block);
bg_idx = blknr / blk_per_grp;
if (fs->blksz == 1024) {
remainder = blknr % blk_per_grp;
@@ -367,23 +408,23 @@
bg_idx--;
}
ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
+ /* get block group descriptor table */
+ bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+ ext4fs_bg_free_blocks_inc(bgd, fs);
+ ext4fs_sb_free_blocks_inc(fs->sb);
/* journal backup */
if (prev_bg_bmap_idx != bg_idx) {
- memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread((lbaint_t)bgd[bg_idx].block_id *
- fs->sect_perblk, 0, fs->blksz,
- journal_buffer);
+ uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+ status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk,
+ 0, fs->blksz, journal_buffer);
if (status == 0)
goto fail;
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
+ if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
goto fail;
prev_bg_bmap_idx = bg_idx;
}
- debug("tigp buffer itself releasing %ld\n", blknr);
+ debug("tigp buffer itself releasing %d\n", blknr);
}
fail:
free(tib_start_addr);
@@ -402,126 +443,87 @@
int ibmap_idx;
char *read_buffer = NULL;
char *start_block_address = NULL;
- unsigned int no_blocks;
+ uint32_t no_blocks;
static int prev_bg_bmap_idx = -1;
unsigned int inodes_per_block;
- long int blkno;
+ uint32_t blkno;
unsigned int blkoff;
- unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
- unsigned int inode_per_grp = ext4fs_root->sblock.inodes_per_group;
+ uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
+ uint32_t inode_per_grp = le32_to_cpu(ext4fs_root->sblock.inodes_per_group);
struct ext2_inode *inode_buffer = NULL;
struct ext2_block_group *bgd = NULL;
struct ext_filesystem *fs = get_fs();
char *journal_buffer = zalloc(fs->blksz);
if (!journal_buffer)
return -ENOMEM;
- /* get the block group descriptor table */
- bgd = (struct ext2_block_group *)fs->gdtable;
status = ext4fs_read_inode(ext4fs_root, inodeno, &inode);
if (status == 0)
goto fail;
/* read the block no allocated to a file */
- no_blocks = inode.size / fs->blksz;
- if (inode.size % fs->blksz)
+ no_blocks = le32_to_cpu(inode.size) / fs->blksz;
+ if (le32_to_cpu(inode.size) % fs->blksz)
no_blocks++;
if (le32_to_cpu(inode.flags) & EXT4_EXTENTS_FL) {
- struct ext2fs_node *node_inode =
- zalloc(sizeof(struct ext2fs_node));
- if (!node_inode)
- goto fail;
- node_inode->data = ext4fs_root;
- node_inode->ino = inodeno;
- node_inode->inode_read = 0;
- memcpy(&(node_inode->inode), &inode, sizeof(struct ext2_inode));
-
- for (i = 0; i < no_blocks; i++) {
- blknr = read_allocated_block(&(node_inode->inode), i);
- bg_idx = blknr / blk_per_grp;
- if (fs->blksz == 1024) {
- remainder = blknr % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
- ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
- bg_idx);
- debug("EXT4_EXTENTS Block releasing %ld: %d\n",
- blknr, bg_idx);
-
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
-
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- status =
- ext4fs_devread((lbaint_t)
- bgd[bg_idx].block_id *
- fs->sect_perblk, 0,
- fs->blksz, journal_buffer);
- if (status == 0)
- goto fail;
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
- }
- if (node_inode) {
- free(node_inode);
- node_inode = NULL;
- }
+ /* FIXME delete extent index blocks, i.e. eh_depth >= 1 */
+ struct ext4_extent_header *eh =
+ (struct ext4_extent_header *)
+ inode.b.blocks.dir_blocks;
+ debug("del: dep=%d entries=%d\n", eh->eh_depth, eh->eh_entries);
} else {
-
delete_single_indirect_block(&inode);
delete_double_indirect_block(&inode);
delete_triple_indirect_block(&inode);
+ }
- /* read the block no allocated to a file */
- no_blocks = inode.size / fs->blksz;
- if (inode.size % fs->blksz)
- no_blocks++;
- for (i = 0; i < no_blocks; i++) {
- blknr = read_allocated_block(&inode, i);
- bg_idx = blknr / blk_per_grp;
- if (fs->blksz == 1024) {
- remainder = blknr % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
- ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
- bg_idx);
- debug("ActualB releasing %ld: %d\n", blknr, bg_idx);
+ /* release data blocks */
+ for (i = 0; i < no_blocks; i++) {
+ blknr = read_allocated_block(&inode, i);
+ if (blknr == 0)
+ continue;
+ if (blknr < 0)
+ goto fail;
+ bg_idx = blknr / blk_per_grp;
+ if (fs->blksz == 1024) {
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
+ bg_idx);
+ debug("EXT4 Block releasing %ld: %d\n", blknr, bg_idx);
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread((lbaint_t)
- bgd[bg_idx].block_id
- * fs->sect_perblk,
- 0, fs->blksz,
- journal_buffer);
- if (status == 0)
- goto fail;
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
+ /* get block group descriptor table */
+ bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+ ext4fs_bg_free_blocks_inc(bgd, fs);
+ ext4fs_sb_free_blocks_inc(fs->sb);
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+ status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk,
+ 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
}
}
+ /* release inode */
/* from the inode no to blockno */
inodes_per_block = fs->blksz / fs->inodesz;
ibmap_idx = inodeno / inode_per_grp;
/* get the block no */
inodeno--;
- blkno = __le32_to_cpu(bgd[ibmap_idx].inode_table_id) +
- (inodeno % __le32_to_cpu(inode_per_grp)) / inodes_per_block;
+ /* get block group descriptor table */
+ bgd = ext4fs_get_group_descriptor(fs, ibmap_idx);
+ blkno = ext4fs_bg_get_inode_table_id(bgd, fs) +
+ (inodeno % inode_per_grp) / inodes_per_block;
/* get the offset of the inode */
blkoff = ((inodeno) % inodes_per_block) * fs->inodesz;
@@ -541,7 +543,7 @@
read_buffer = read_buffer + blkoff;
inode_buffer = (struct ext2_inode *)read_buffer;
- memset(inode_buffer, '\0', sizeof(struct ext2_inode));
+ memset(inode_buffer, '\0', fs->inodesz);
/* write the inode to original position in inode table */
if (ext4fs_put_metadata(start_block_address, blkno))
@@ -550,15 +552,15 @@
/* update the respective inode bitmaps */
inodeno++;
ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx);
- bgd[ibmap_idx].free_inodes++;
- fs->sb->free_inodes++;
+ ext4fs_bg_free_inodes_inc(bgd, fs);
+ ext4fs_sb_free_inodes_inc(fs->sb);
/* journal backup */
memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread((lbaint_t)bgd[ibmap_idx].inode_id *
+ status = ext4fs_devread(ext4fs_bg_get_inode_id(bgd, fs) *
fs->sect_perblk, 0, fs->blksz, journal_buffer);
if (status == 0)
goto fail;
- if (ext4fs_log_journal(journal_buffer, bgd[ibmap_idx].inode_id))
+ if (ext4fs_log_journal(journal_buffer, ext4fs_bg_get_inode_id(bgd, fs)))
goto fail;
ext4fs_update();
@@ -585,12 +587,11 @@
{
short status;
int i;
- unsigned int real_free_blocks = 0;
+ uint32_t real_free_blocks = 0;
struct ext_filesystem *fs = get_fs();
/* populate fs */
fs->blksz = EXT2_BLOCK_SIZE(ext4fs_root);
- fs->inodesz = INODE_SIZE_FILESYSTEM(ext4fs_root);
fs->sect_perblk = fs->blksz >> fs->dev_desc->log2blksz;
/* get the superblock */
@@ -606,9 +607,9 @@
/* get total no of blockgroups */
fs->no_blkgrp = (uint32_t)ext4fs_div_roundup(
- (ext4fs_root->sblock.total_blocks -
- ext4fs_root->sblock.first_data_block),
- ext4fs_root->sblock.blocks_per_group);
+ le32_to_cpu(ext4fs_root->sblock.total_blocks)
+ - le32_to_cpu(ext4fs_root->sblock.first_data_block),
+ le32_to_cpu(ext4fs_root->sblock.blocks_per_group));
/* get the block group descriptor table */
fs->gdtable_blkno = ((EXT2_MIN_BLOCK_SIZE == fs->blksz) + 1);
@@ -616,7 +617,6 @@
printf("Error in getting the block group descriptor table\n");
goto fail;
}
- fs->bgd = (struct ext2_block_group *)fs->gdtable;
/* load all the available bitmap block of the partition */
fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *));
@@ -629,8 +629,9 @@
}
for (i = 0; i < fs->no_blkgrp; i++) {
- status =
- ext4fs_devread((lbaint_t)fs->bgd[i].block_id *
+ struct ext2_block_group *bgd =
+ ext4fs_get_group_descriptor(fs, i);
+ status = ext4fs_devread(ext4fs_bg_get_block_id(bgd, fs) *
fs->sect_perblk, 0,
fs->blksz, (char *)fs->blk_bmaps[i]);
if (status == 0)
@@ -648,7 +649,9 @@
}
for (i = 0; i < fs->no_blkgrp; i++) {
- status = ext4fs_devread((lbaint_t)fs->bgd[i].inode_id *
+ struct ext2_block_group *bgd =
+ ext4fs_get_group_descriptor(fs, i);
+ status = ext4fs_devread(ext4fs_bg_get_inode_id(bgd, fs) *
fs->sect_perblk,
0, fs->blksz,
(char *)fs->inode_bmaps[i]);
@@ -662,10 +665,14 @@
* with the blockgroups freeblocks when improper
* reboot of a linux kernel
*/
- for (i = 0; i < fs->no_blkgrp; i++)
- real_free_blocks = real_free_blocks + fs->bgd[i].free_blocks;
- if (real_free_blocks != fs->sb->free_blocks)
- fs->sb->free_blocks = real_free_blocks;
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ struct ext2_block_group *bgd =
+ ext4fs_get_group_descriptor(fs, i);
+ real_free_blocks = real_free_blocks +
+ ext4fs_bg_get_free_blocks(bgd, fs);
+ }
+ if (real_free_blocks != ext4fs_sb_get_free_blocks(fs->sb))
+ ext4fs_sb_set_free_blocks(fs->sb, real_free_blocks);
return 0;
fail:
@@ -679,8 +686,9 @@
int i;
struct ext2_inode inode_journal;
struct journal_superblock_t *jsb;
- long int blknr;
+ uint32_t blknr;
struct ext_filesystem *fs = get_fs();
+ uint32_t new_feature_incompat;
/* free journal */
char *temp_buff = zalloc(fs->blksz);
@@ -692,7 +700,7 @@
ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz,
temp_buff);
jsb = (struct journal_superblock_t *)temp_buff;
- jsb->s_start = cpu_to_be32(0);
+ jsb->s_start = 0;
put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
(struct journal_superblock_t *)temp_buff, fs->blksz);
free(temp_buff);
@@ -701,7 +709,9 @@
/* get the superblock */
ext4_read_superblock((char *)fs->sb);
- fs->sb->feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER;
+ new_feature_incompat = le32_to_cpu(fs->sb->feature_incompat);
+ new_feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER;
+ fs->sb->feature_incompat = cpu_to_le32(new_feature_incompat);
put_ext4((uint64_t)(SUPERBLOCK_SIZE),
(struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
free(fs->sb);
@@ -728,7 +738,6 @@
free(fs->gdtable);
fs->gdtable = NULL;
- fs->bgd = NULL;
/*
* reinitiliazed the global inode and
* block bitmap first execution check variables
@@ -739,12 +748,16 @@
fs->curr_blkno = 0;
}
+/*
+ * Write data to filesystem blocks. Uses same optimization for
+ * contigous sectors as ext4fs_read_file
+ */
static int ext4fs_write_file(struct ext2_inode *file_inode,
int pos, unsigned int len, char *buf)
{
int i;
int blockcnt;
- unsigned int filesize = __le32_to_cpu(file_inode->size);
+ uint32_t filesize = le32_to_cpu(file_inode->size);
struct ext_filesystem *fs = get_fs();
int log2blksz = fs->dev_desc->log2blksz;
int log2_fs_blocksize = LOG2_BLOCK_SIZE(ext4fs_root) - log2blksz;
@@ -765,7 +778,7 @@
int blockend = fs->blksz;
int skipfirst = 0;
blknr = read_allocated_block(file_inode, i);
- if (blknr < 0)
+ if (blknr <= 0)
return -1;
blknr = blknr << log2_fs_blocksize;
@@ -839,11 +852,12 @@
struct ext2_sblock *sblock = &(ext4fs_root->sblock);
unsigned int inodes_per_block;
unsigned int ibmap_idx;
+ struct ext2_block_group *bgd = NULL;
struct ext_filesystem *fs = get_fs();
ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256);
memset(filename, 0x00, 256);
- g_parent_inode = zalloc(sizeof(struct ext2_inode));
+ g_parent_inode = zalloc(fs->inodesz);
if (!g_parent_inode)
goto fail;
@@ -857,8 +871,13 @@
goto fail;
if (ext4fs_iget(parent_inodeno, g_parent_inode))
goto fail;
+ /* do not mess up a directory using hash trees */
+ if (le32_to_cpu(g_parent_inode->flags) & EXT4_INDEX_FL) {
+ printf("hash tree directory\n");
+ goto fail;
+ }
/* check if the filename is already present in root */
- existing_file_inodeno = ext4fs_filename_check(filename);
+ existing_file_inodeno = ext4fs_filename_unlink(filename);
if (existing_file_inodeno != -1) {
ret = ext4fs_delete_file(existing_file_inodeno);
fs->first_pass_bbmap = 0;
@@ -878,39 +897,42 @@
}
blocks_remaining = blks_reqd_for_file;
/* test for available space in partition */
- if (fs->sb->free_blocks < blks_reqd_for_file) {
+ if (le32_to_cpu(fs->sb->free_blocks) < blks_reqd_for_file) {
printf("Not enough space on partition !!!\n");
goto fail;
}
- ext4fs_update_parent_dentry(filename, &inodeno, FILETYPE_REG);
+ inodeno = ext4fs_update_parent_dentry(filename, FILETYPE_REG);
+ if (inodeno == -1)
+ goto fail;
/* prepare file inode */
inode_buffer = zalloc(fs->inodesz);
if (!inode_buffer)
goto fail;
file_inode = (struct ext2_inode *)inode_buffer;
- file_inode->mode = S_IFREG | S_IRWXU |
- S_IRGRP | S_IROTH | S_IXGRP | S_IXOTH;
+ file_inode->mode = cpu_to_le16(S_IFREG | S_IRWXU |
+ S_IRGRP | S_IROTH | S_IXGRP | S_IXOTH);
/* ToDo: Update correct time */
- file_inode->mtime = timestamp;
- file_inode->atime = timestamp;
- file_inode->ctime = timestamp;
- file_inode->nlinks = 1;
- file_inode->size = sizebytes;
+ file_inode->mtime = cpu_to_le32(timestamp);
+ file_inode->atime = cpu_to_le32(timestamp);
+ file_inode->ctime = cpu_to_le32(timestamp);
+ file_inode->nlinks = cpu_to_le16(1);
+ file_inode->size = cpu_to_le32(sizebytes);
/* Allocate data blocks */
ext4fs_allocate_blocks(file_inode, blocks_remaining,
&blks_reqd_for_file);
- file_inode->blockcnt = (blks_reqd_for_file * fs->blksz) >>
- fs->dev_desc->log2blksz;
+ file_inode->blockcnt = cpu_to_le32((blks_reqd_for_file * fs->blksz) >>
+ fs->dev_desc->log2blksz);
temp_ptr = zalloc(fs->blksz);
if (!temp_ptr)
goto fail;
- ibmap_idx = inodeno / ext4fs_root->sblock.inodes_per_group;
+ ibmap_idx = inodeno / le32_to_cpu(ext4fs_root->sblock.inodes_per_group);
inodeno--;
- itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
- (inodeno % __le32_to_cpu(sblock->inodes_per_group)) /
+ bgd = ext4fs_get_group_descriptor(fs, ibmap_idx);
+ itable_blkno = ext4fs_bg_get_inode_table_id(bgd, fs) +
+ (inodeno % le32_to_cpu(sblock->inodes_per_group)) /
inodes_per_block;
blkoff = (inodeno % inodes_per_block) * fs->inodesz;
ext4fs_devread((lbaint_t)itable_blkno * fs->sect_perblk, 0, fs->blksz,
@@ -924,13 +946,15 @@
/* copy the file content into data blocks */
if (ext4fs_write_file(file_inode, 0, sizebytes, (char *)buffer) == -1) {
printf("Error in copying content\n");
+ /* FIXME: Deallocate data blocks */
goto fail;
}
- ibmap_idx = parent_inodeno / ext4fs_root->sblock.inodes_per_group;
+ ibmap_idx = parent_inodeno / le32_to_cpu(ext4fs_root->sblock.inodes_per_group);
parent_inodeno--;
- parent_itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
+ bgd = ext4fs_get_group_descriptor(fs, ibmap_idx);
+ parent_itable_blkno = ext4fs_bg_get_inode_table_id(bgd, fs) +
(parent_inodeno %
- __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
+ le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz;
if (parent_itable_blkno != itable_blkno) {
memset(temp_ptr, '\0', fs->blksz);
@@ -939,22 +963,18 @@
if (ext4fs_log_journal(temp_ptr, parent_itable_blkno))
goto fail;
- memcpy(temp_ptr + blkoff, g_parent_inode,
- sizeof(struct ext2_inode));
+ memcpy(temp_ptr + blkoff, g_parent_inode, fs->inodesz);
if (ext4fs_put_metadata(temp_ptr, parent_itable_blkno))
goto fail;
- free(temp_ptr);
} else {
/*
* If parent and child fall in same inode table block
* both should be kept in 1 buffer
*/
- memcpy(temp_ptr + blkoff, g_parent_inode,
- sizeof(struct ext2_inode));
+ memcpy(temp_ptr + blkoff, g_parent_inode, fs->inodesz);
gd_index--;
if (ext4fs_put_metadata(temp_ptr, itable_blkno))
goto fail;
- free(temp_ptr);
}
ext4fs_update();
ext4fs_deinit();
@@ -965,6 +985,7 @@
fs->curr_inode_no = 0;
free(inode_buffer);
free(g_parent_inode);
+ free(temp_ptr);
g_parent_inode = NULL;
return 0;
@@ -972,6 +993,7 @@
ext4fs_deinit();
free(inode_buffer);
free(g_parent_inode);
+ free(temp_ptr);
g_parent_inode = NULL;
return -1;
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 43c8897..7187dcf 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -55,7 +55,7 @@
int log2blksz = fs->dev_desc->log2blksz;
int log2_fs_blocksize = LOG2_BLOCK_SIZE(node->data) - log2blksz;
int blocksize = (1 << (log2_fs_blocksize + log2blksz));
- unsigned int filesize = __le32_to_cpu(node->inode.size);
+ unsigned int filesize = le32_to_cpu(node->inode.size);
lbaint_t previous_block_number = -1;
lbaint_t delayed_start = 0;
lbaint_t delayed_extent = 0;
@@ -65,8 +65,8 @@
short status;
/* Adjust len so it we can't read past the end of the file. */
- if (len > filesize)
- len = filesize;
+ if (len + pos > filesize)
+ len = (filesize - pos);
blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize);
@@ -190,12 +190,12 @@
return ext4fs_open(filename, size);
}
-int ext4fs_read(char *buf, loff_t len, loff_t *actread)
+int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread)
{
if (ext4fs_root == NULL || ext4fs_file == NULL)
- return 0;
+ return -1;
- return ext4fs_read_file(ext4fs_file, 0, len, buf, actread);
+ return ext4fs_read_file(ext4fs_file, offset, len, buf, actread);
}
int ext4fs_probe(struct blk_desc *fs_dev_desc,
@@ -217,11 +217,6 @@
loff_t file_len;
int ret;
- if (offset != 0) {
- printf("** Cannot support non-zero offset **\n");
- return -1;
- }
-
ret = ext4fs_open(filename, &file_len);
if (ret < 0) {
printf("** File not found %s **\n", filename);
@@ -231,7 +226,7 @@
if (len == 0)
len = file_len;
- return ext4fs_read(buf, len, len_read);
+ return ext4fs_read(buf, offset, len, len_read);
}
int ext4fs_uuid(char *uuid_str)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 826bd85..fe899d0 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -162,6 +162,16 @@
downcase(s_name);
}
+static int flush_dirty_fat_buffer(fsdata *mydata);
+#if !defined(CONFIG_FAT_WRITE)
+/* Stub for read only operation */
+int flush_dirty_fat_buffer(fsdata *mydata)
+{
+ (void)(mydata);
+ return 0;
+}
+#endif
+
/*
* Get the entry at index 'entry' in a FAT (12/16/32) table.
* On failure 0x00 is returned.
@@ -171,7 +181,11 @@
__u32 bufnum;
__u32 off16, offset;
__u32 ret = 0x00;
- __u16 val1, val2;
+
+ if (CHECK_CLUST(entry, mydata->fatsize)) {
+ printf("Error: Invalid FAT entry: 0x%08x\n", entry);
+ return ret;
+ }
switch (mydata->fatsize) {
case 32:
@@ -192,7 +206,7 @@
return ret;
}
- debug("FAT%d: entry: 0x%04x = %d, offset: 0x%04x = %d\n",
+ debug("FAT%d: entry: 0x%08x = %d, offset: 0x%04x = %d\n",
mydata->fatsize, entry, entry, offset, offset);
/* Read a new block of FAT entries into the cache. */
@@ -202,11 +216,16 @@
__u32 fatlength = mydata->fatlength;
__u32 startblock = bufnum * FATBUFBLOCKS;
+ /* Cap length if fatlength is not a multiple of FATBUFBLOCKS */
if (startblock + getsize > fatlength)
getsize = fatlength - startblock;
startblock += mydata->fat_sect; /* Offset from start of disk */
+ /* Write back the fatbuf to the disk */
+ if (flush_dirty_fat_buffer(mydata) < 0)
+ return -1;
+
if (disk_read(startblock, getsize, bufptr) < 0) {
debug("Error reading FAT blocks\n");
return ret;
@@ -223,38 +242,15 @@
ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[offset]);
break;
case 12:
- off16 = (offset * 3) / 4;
+ off16 = (offset * 3) / 2;
+ ret = FAT2CPU16(*(__u16 *)(mydata->fatbuf + off16));
- switch (offset & 0x3) {
- case 0:
- ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[off16]);
- ret &= 0xfff;
- break;
- case 1:
- val1 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16]);
- val1 &= 0xf000;
- val2 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16 + 1]);
- val2 &= 0x00ff;
- ret = (val2 << 4) | (val1 >> 12);
- break;
- case 2:
- val1 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16]);
- val1 &= 0xff00;
- val2 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16 + 1]);
- val2 &= 0x000f;
- ret = (val2 << 8) | (val1 >> 8);
- break;
- case 3:
- ret = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16]);
- ret = (ret & 0xfff0) >> 4;
- break;
- default:
- break;
- }
- break;
+ if (offset & 0x1)
+ ret >>= 4;
+ ret &= 0xfff;
}
- debug("FAT%d: ret: %08x, offset: %04x\n",
- mydata->fatsize, ret, offset);
+ debug("FAT%d: ret: 0x%08x, entry: 0x%08x, offset: 0x%04x\n",
+ mydata->fatsize, ret, entry, offset);
return ret;
}
@@ -876,6 +872,7 @@
}
mydata->fatbufnum = -1;
+ mydata->fat_dirty = 0;
mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
if (mydata->fatbuf == NULL) {
debug("Error: allocating memory\n");
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index eb3a916..f6f0628 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -104,17 +104,24 @@
/*
* Write fat buffer into block device
*/
-static int flush_fat_buffer(fsdata *mydata)
+static int flush_dirty_fat_buffer(fsdata *mydata)
{
int getsize = FATBUFBLOCKS;
__u32 fatlength = mydata->fatlength;
__u8 *bufptr = mydata->fatbuf;
__u32 startblock = mydata->fatbufnum * FATBUFBLOCKS;
- startblock += mydata->fat_sect;
+ debug("debug: evicting %d, dirty: %d\n", mydata->fatbufnum,
+ (int)mydata->fat_dirty);
- if (getsize > fatlength)
- getsize = fatlength;
+ if ((!mydata->fat_dirty) || (mydata->fatbufnum == -1))
+ return 0;
+
+ /* Cap length if fatlength is not a multiple of FATBUFBLOCKS */
+ if (startblock + getsize > fatlength)
+ getsize = fatlength - startblock;
+
+ startblock += mydata->fat_sect;
/* Write FAT buf */
if (disk_write(startblock, getsize, bufptr) < 0) {
@@ -130,121 +137,12 @@
return -1;
}
}
+ mydata->fat_dirty = 0;
return 0;
}
/*
- * Get the entry at index 'entry' in a FAT (12/16/32) table.
- * On failure 0x00 is returned.
- * When bufnum is changed, write back the previous fatbuf to the disk.
- */
-static __u32 get_fatent_value(fsdata *mydata, __u32 entry)
-{
- __u32 bufnum;
- __u32 off16, offset;
- __u32 ret = 0x00;
- __u16 val1, val2;
-
- if (CHECK_CLUST(entry, mydata->fatsize)) {
- printf("Error: Invalid FAT entry: 0x%08x\n", entry);
- return ret;
- }
-
- switch (mydata->fatsize) {
- case 32:
- bufnum = entry / FAT32BUFSIZE;
- offset = entry - bufnum * FAT32BUFSIZE;
- break;
- case 16:
- bufnum = entry / FAT16BUFSIZE;
- offset = entry - bufnum * FAT16BUFSIZE;
- break;
- case 12:
- bufnum = entry / FAT12BUFSIZE;
- offset = entry - bufnum * FAT12BUFSIZE;
- break;
-
- default:
- /* Unsupported FAT size */
- return ret;
- }
-
- debug("FAT%d: entry: 0x%04x = %d, offset: 0x%04x = %d\n",
- mydata->fatsize, entry, entry, offset, offset);
-
- /* Read a new block of FAT entries into the cache. */
- if (bufnum != mydata->fatbufnum) {
- int getsize = FATBUFBLOCKS;
- __u8 *bufptr = mydata->fatbuf;
- __u32 fatlength = mydata->fatlength;
- __u32 startblock = bufnum * FATBUFBLOCKS;
-
- if (getsize > fatlength)
- getsize = fatlength;
-
- fatlength *= mydata->sect_size; /* We want it in bytes now */
- startblock += mydata->fat_sect; /* Offset from start of disk */
-
- /* Write back the fatbuf to the disk */
- if (mydata->fatbufnum != -1) {
- if (flush_fat_buffer(mydata) < 0)
- return -1;
- }
-
- if (disk_read(startblock, getsize, bufptr) < 0) {
- debug("Error reading FAT blocks\n");
- return ret;
- }
- mydata->fatbufnum = bufnum;
- }
-
- /* Get the actual entry from the table */
- switch (mydata->fatsize) {
- case 32:
- ret = FAT2CPU32(((__u32 *) mydata->fatbuf)[offset]);
- break;
- case 16:
- ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[offset]);
- break;
- case 12:
- off16 = (offset * 3) / 4;
-
- switch (offset & 0x3) {
- case 0:
- ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[off16]);
- ret &= 0xfff;
- break;
- case 1:
- val1 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16]);
- val1 &= 0xf000;
- val2 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16 + 1]);
- val2 &= 0x00ff;
- ret = (val2 << 4) | (val1 >> 12);
- break;
- case 2:
- val1 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16]);
- val1 &= 0xff00;
- val2 = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16 + 1]);
- val2 &= 0x000f;
- ret = (val2 << 8) | (val1 >> 8);
- break;
- case 3:
- ret = FAT2CPU16(((__u16 *)mydata->fatbuf)[off16]);
- ret = (ret & 0xfff0) >> 4;
- break;
- default:
- break;
- }
- break;
- }
- debug("FAT%d: ret: %08x, entry: %08x, offset: %04x\n",
- mydata->fatsize, ret, entry, offset);
-
- return ret;
-}
-
-/*
* Set the file name information from 'name' into 'slotptr',
*/
static int str2slot(dir_slot *slotptr, const char *name, int *idx)
@@ -323,13 +221,12 @@
static void
fill_dir_slot(fsdata *mydata, dir_entry **dentptr, const char *l_name)
{
- dir_slot *slotptr = (dir_slot *)get_contents_vfatname_block;
+ __u8 temp_dir_slot_buffer[MAX_LFN_SLOT * sizeof(dir_slot)];
+ dir_slot *slotptr = (dir_slot *)temp_dir_slot_buffer;
__u8 counter = 0, checksum;
int idx = 0, ret;
- char s_name[16];
- /* Get short file name and checksum value */
- strncpy(s_name, (*dentptr)->name, 16);
+ /* Get short file name checksum value */
checksum = mkcksum((*dentptr)->name, (*dentptr)->ext);
do {
@@ -402,7 +299,7 @@
if ((__u8 *)slotptr >= buflimit) {
if (curclust == 0)
return -1;
- curclust = get_fatent_value(mydata, dir_curclust);
+ curclust = get_fatent(mydata, dir_curclust);
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
printf("Invalid FAT entry\n");
@@ -464,11 +361,12 @@
}
/*
- * Set the entry at index 'entry' in a FAT (16/32) table.
+ * Set the entry at index 'entry' in a FAT (12/16/32) table.
*/
static int set_fatent_value(fsdata *mydata, __u32 entry, __u32 entry_value)
{
- __u32 bufnum, offset;
+ __u32 bufnum, offset, off16;
+ __u16 val1, val2;
switch (mydata->fatsize) {
case 32:
@@ -479,6 +377,10 @@
bufnum = entry / FAT16BUFSIZE;
offset = entry - bufnum * FAT16BUFSIZE;
break;
+ case 12:
+ bufnum = entry / FAT12BUFSIZE;
+ offset = entry - bufnum * FAT12BUFSIZE;
+ break;
default:
/* Unsupported FAT size */
return -1;
@@ -491,17 +393,15 @@
__u32 fatlength = mydata->fatlength;
__u32 startblock = bufnum * FATBUFBLOCKS;
- fatlength *= mydata->sect_size;
+ /* Cap length if fatlength is not a multiple of FATBUFBLOCKS */
+ if (startblock + getsize > fatlength)
+ getsize = fatlength - startblock;
+
+ if (flush_dirty_fat_buffer(mydata) < 0)
+ return -1;
+
startblock += mydata->fat_sect;
- if (getsize > fatlength)
- getsize = fatlength;
-
- if (mydata->fatbufnum != -1) {
- if (flush_fat_buffer(mydata) < 0)
- return -1;
- }
-
if (disk_read(startblock, getsize, bufptr) < 0) {
debug("Error reading FAT blocks\n");
return -1;
@@ -509,6 +409,9 @@
mydata->fatbufnum = bufnum;
}
+ /* Mark as dirty */
+ mydata->fat_dirty = 1;
+
/* Set the actual entry */
switch (mydata->fatsize) {
case 32:
@@ -517,6 +420,45 @@
case 16:
((__u16 *) mydata->fatbuf)[offset] = cpu_to_le16(entry_value);
break;
+ case 12:
+ off16 = (offset * 3) / 4;
+
+ switch (offset & 0x3) {
+ case 0:
+ val1 = cpu_to_le16(entry_value) & 0xfff;
+ ((__u16 *)mydata->fatbuf)[off16] &= ~0xfff;
+ ((__u16 *)mydata->fatbuf)[off16] |= val1;
+ break;
+ case 1:
+ val1 = cpu_to_le16(entry_value) & 0xf;
+ val2 = (cpu_to_le16(entry_value) >> 4) & 0xff;
+
+ ((__u16 *)mydata->fatbuf)[off16] &= ~0xf000;
+ ((__u16 *)mydata->fatbuf)[off16] |= (val1 << 12);
+
+ ((__u16 *)mydata->fatbuf)[off16 + 1] &= ~0xff;
+ ((__u16 *)mydata->fatbuf)[off16 + 1] |= val2;
+ break;
+ case 2:
+ val1 = cpu_to_le16(entry_value) & 0xff;
+ val2 = (cpu_to_le16(entry_value) >> 8) & 0xf;
+
+ ((__u16 *)mydata->fatbuf)[off16] &= ~0xff00;
+ ((__u16 *)mydata->fatbuf)[off16] |= (val1 << 8);
+
+ ((__u16 *)mydata->fatbuf)[off16 + 1] &= ~0xf;
+ ((__u16 *)mydata->fatbuf)[off16 + 1] |= val2;
+ break;
+ case 3:
+ val1 = cpu_to_le16(entry_value) & 0xfff;
+ ((__u16 *)mydata->fatbuf)[off16] &= ~0xfff0;
+ ((__u16 *)mydata->fatbuf)[off16] |= (val1 << 4);
+ break;
+ default:
+ break;
+ }
+
+ break;
default:
return -1;
}
@@ -525,15 +467,17 @@
}
/*
- * Determine the entry value at index 'entry' in a FAT (16/32) table
+ * Determine the next free cluster after 'entry' in a FAT (12/16/32) table
+ * and link it to 'entry'. EOC marker is not set on returned entry.
*/
static __u32 determine_fatent(fsdata *mydata, __u32 entry)
{
__u32 next_fat, next_entry = entry + 1;
while (1) {
- next_fat = get_fatent_value(mydata, next_entry);
+ next_fat = get_fatent(mydata, next_entry);
if (next_fat == 0) {
+ /* found free entry, link to entry */
set_fatent_value(mydata, entry, next_entry);
break;
}
@@ -617,7 +561,7 @@
__u32 fat_val, entry = 3;
while (1) {
- fat_val = get_fatent_value(mydata, entry);
+ fat_val = get_fatent(mydata, entry);
if (fat_val == 0)
break;
entry++;
@@ -645,10 +589,12 @@
set_fatent_value(mydata, dir_newclust, 0xffffff8);
else if (mydata->fatsize == 16)
set_fatent_value(mydata, dir_newclust, 0xfff8);
+ else if (mydata->fatsize == 12)
+ set_fatent_value(mydata, dir_newclust, 0xff8);
dir_curclust = dir_newclust;
- if (flush_fat_buffer(mydata) < 0)
+ if (flush_dirty_fat_buffer(mydata) < 0)
return;
memset(get_dentfromdir_block, 0x00,
@@ -664,21 +610,18 @@
{
__u32 fat_val;
- while (1) {
- fat_val = get_fatent_value(mydata, entry);
+ while (!CHECK_CLUST(entry, mydata->fatsize)) {
+ fat_val = get_fatent(mydata, entry);
if (fat_val != 0)
set_fatent_value(mydata, entry, 0);
else
break;
- if (fat_val == 0xfffffff || fat_val == 0xffff)
- break;
-
entry = fat_val;
}
/* Flush fat buffer */
- if (flush_fat_buffer(mydata) < 0)
+ if (flush_dirty_fat_buffer(mydata) < 0)
return -1;
return 0;
@@ -744,7 +687,9 @@
*gotsize += actsize;
/* Mark end of file in FAT */
- if (mydata->fatsize == 16)
+ if (mydata->fatsize == 12)
+ newclust = 0xfff;
+ else if (mydata->fatsize == 16)
newclust = 0xffff;
else if (mydata->fatsize == 32)
newclust = 0xfffffff;
@@ -943,7 +888,7 @@
return NULL;
}
- curclust = get_fatent_value(mydata, dir_curclust);
+ curclust = get_fatent(mydata, dir_curclust);
if (IS_LAST_CLUST(curclust, mydata->fatsize)) {
empty_dentptr = dentptr;
return NULL;
@@ -1014,6 +959,7 @@
}
mydata->fatbufnum = -1;
+ mydata->fat_dirty = 0;
mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
if (mydata->fatbuf == NULL) {
debug("Error: allocating memory\n");
@@ -1114,7 +1060,7 @@
debug("attempt to write 0x%llx bytes\n", *actwrite);
/* Flush fat buffer */
- ret = flush_fat_buffer(mydata);
+ ret = flush_dirty_fat_buffer(mydata);
if (ret) {
printf("Error: flush fat buffer\n");
goto exit;
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index f771e94..ed60c5b 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -122,7 +122,7 @@
#include <jffs2/jffs2.h>
#include <jffs2/jffs2_1pass.h>
#include <linux/compat.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "jffs2_private.h"
diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c
index 2703eed..ca80261 100644
--- a/fs/sandbox/sandboxfs.c
+++ b/fs/sandbox/sandboxfs.c
@@ -88,14 +88,16 @@
ret = os_dirent_ls(dirname, &head);
if (ret)
- return ret;
+ goto out;
for (node = head; node; node = node->next) {
printf("%s %10lu %s\n", os_dirent_get_typename(node->type),
node->size, node->name);
}
+out:
+ os_dirent_free(head);
- return 0;
+ return ret;
}
int sandbox_fs_exists(const char *filename)
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index cdc04c6..cc397d6 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -854,7 +854,7 @@
*actread = 0;
if (offset & (PAGE_SIZE - 1)) {
- printf("ubifs: Error offset must be a multple of %d\n",
+ printf("ubifs: Error offset must be a multiple of %d\n",
PAGE_SIZE);
return -1;
}
diff --git a/fs/yaffs2/yaffs_mtdif.c b/fs/yaffs2/yaffs_mtdif.c
index 6fcba04..636c777 100644
--- a/fs/yaffs2/yaffs_mtdif.c
+++ b/fs/yaffs2/yaffs_mtdif.c
@@ -19,10 +19,10 @@
#include "yaffs_mtdif.h"
-#include "linux/mtd/mtd.h"
-#include "linux/types.h"
-#include "linux/time.h"
-#include "linux/mtd/nand.h"
+#include <linux/mtd/mtd.h>
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/mtd/nand.h>
static inline void translate_spare2oob(const struct yaffs_spare *spare, u8 *oob)
diff --git a/fs/yaffs2/yaffs_mtdif2.c b/fs/yaffs2/yaffs_mtdif2.c
index 234cb70..0d9d5cc 100644
--- a/fs/yaffs2/yaffs_mtdif2.c
+++ b/fs/yaffs2/yaffs_mtdif2.c
@@ -15,16 +15,16 @@
/* XXX U-BOOT XXX */
#include <common.h>
-#include "asm/errno.h"
+#include <linux/errno.h>
#include "yportenv.h"
#include "yaffs_trace.h"
#include "yaffs_mtdif2.h"
-#include "linux/mtd/mtd.h"
-#include "linux/types.h"
-#include "linux/time.h"
+#include <linux/mtd/mtd.h>
+#include <linux/types.h>
+#include <linux/time.h>
#include "yaffs_trace.h"
#include "yaffs_packedtags2.h"
diff --git a/fs/yaffs2/ydirectenv.h b/fs/yaffs2/ydirectenv.h
index 2b3e84f..d274f22 100644
--- a/fs/yaffs2/ydirectenv.h
+++ b/fs/yaffs2/ydirectenv.h
@@ -75,7 +75,7 @@
#define YAFFS_ROOT_MODE 0666
#define YAFFS_LOSTNFOUND_MODE 0666
-#include "linux/list.h"
+#include <linux/list.h>
#include "yaffsfs.h"
diff --git a/include/_exports.h b/include/_exports.h
index 11beeb2..6ff4364 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -13,7 +13,7 @@
EXPORT_FUNC(putc, void, putc, const char)
EXPORT_FUNC(puts, void, puts, const char *)
EXPORT_FUNC(printf, int, printf, const char*, ...)
-#if defined(CONFIG_X86) || defined(CONFIG_PPC)
+#if (defined(CONFIG_X86) && !defined(CONFIG_X86_64)) || defined(CONFIG_PPC)
EXPORT_FUNC(irq_install_handler, void, install_hdlr,
int, interrupt_handler_t, void*)
@@ -75,6 +75,7 @@
const char *, char **, unsigned int)
EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src)
EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec)
+ EXPORT_FUNC(memset, void *, memset, void *, int, size_t)
#ifdef CONFIG_PHY_AQUANTIA
EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
mdio_get_current_dev, void)
diff --git a/include/ahci.h b/include/ahci.h
index a956c6f..4876b41 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -145,7 +145,7 @@
};
struct ahci_probe_ent {
-#ifdef CONFIG_DM_PCI
+#if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
struct udevice *dev;
#else
pci_dev_t dev;
diff --git a/include/asm-generic/errno.h b/include/asm-generic/errno.h
deleted file mode 100644
index 464cfb7..0000000
--- a/include/asm-generic/errno.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * U-Boot - errno.h Error number defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _GENERIC_ERRNO_H
-#define _GENERIC_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Argument list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-
-#define EDEADLOCK EDEADLK
-
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-#endif
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index dc4cbdb..e02863d 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -45,7 +45,7 @@
unsigned long board_type;
#endif
unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
+#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
unsigned long precon_buf_idx; /* Pre-Console buffer index */
#endif
unsigned long env_addr; /* Address of Environment struct */
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 328bc62..daf021b 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -22,6 +22,8 @@
extern char __entry_text_start[], __entry_text_end[];
extern char __initdata_begin[], __initdata_end[];
extern char __start_rodata[], __end_rodata[];
+extern char __efi_hello_world_begin[];
+extern char __efi_hello_world_end[];
/* Start and end of .ctors section - used for constructor calls. */
extern char __ctors_start[], __ctors_end[];
@@ -82,6 +84,7 @@
extern ulong __rel_dyn_start;
extern ulong __rel_dyn_end;
extern ulong __bss_end;
+extern ulong _image_binary_end;
extern ulong _TEXT_BASE; /* code start */
diff --git a/include/clk.h b/include/clk.h
index dc18b03..5a5c2ff 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -9,6 +9,7 @@
#ifndef _CLK_H_
#define _CLK_H_
+#include <linux/errno.h>
#include <linux/types.h>
/**
@@ -59,7 +60,7 @@
unsigned long id;
};
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
struct phandle_2_cell;
int clk_get_by_index_platdata(struct udevice *dev, int index,
struct phandle_2_cell *cells, struct clk *clk);
diff --git a/include/common.h b/include/common.h
index e9f0dea..a8d833b 100644
--- a/include/common.h
+++ b/include/common.h
@@ -866,17 +866,20 @@
int tstc(void);
/* stdout */
-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SERIAL_SUPPORT)
-#define putc(...) do { } while (0)
-#define puts(...) do { } while (0)
-#define printf(...) do { } while (0)
-#define vprintf(...) do { } while (0)
-#else
+#if !defined(CONFIG_SPL_BUILD) || \
+ (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL_SUPPORT)) || \
+ (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && \
+ defined(CONFIG_SPL_SERIAL_SUPPORT))
void putc(const char c);
void puts(const char *s);
int printf(const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2)));
int vprintf(const char *fmt, va_list args);
+#else
+#define putc(...) do { } while (0)
+#define puts(...) do { } while (0)
+#define printf(...) do { } while (0)
+#define vprintf(...) do { } while (0)
#endif
/* stderr */
diff --git a/include/compiler.h b/include/compiler.h
index 65b826e..a43fb6a 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -52,6 +52,9 @@
# include <sys/endian.h> /* htole32 and friends */
#elif defined(__OpenBSD__)
# include <endian.h>
+# define __BYTE_ORDER BYTE_ORDER
+# define __LITTLE_ENDIAN LITTLE_ENDIAN
+# define __BIG_ENDIAN BIG_ENDIAN
#endif
#include <time.h>
@@ -84,20 +87,7 @@
# define uswap_64(x) _uswap_64(x, )
#endif
-#if defined(__OpenBSD__)
-#define cpu_to_le16(x) htole16(x)
-#define cpu_to_le32(x) htole32(x)
-#define cpu_to_le64(x) htole64(x)
-#define le16_to_cpu(x) letoh16(x)
-#define le32_to_cpu(x) letoh32(x)
-#define le64_to_cpu(x) letoh64(x)
-#define cpu_to_be16(x) htobe16(x)
-#define cpu_to_be32(x) htobe32(x)
-#define cpu_to_be64(x) htobe64(x)
-#define be16_to_cpu(x) betoh16(x)
-#define be32_to_cpu(x) betoh32(x)
-#define be64_to_cpu(x) betoh64(x)
-#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#if __BYTE_ORDER == __LITTLE_ENDIAN
# define cpu_to_le16(x) (x)
# define cpu_to_le32(x) (x)
# define cpu_to_le64(x) (x)
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index b5fd6c6..0c4f645 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -48,7 +48,6 @@
#define CONFIG_SCSI /* SCSI Support */
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
#define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */
-#define CONFIG_CMD_UBI /* UBI Support */
#define CONFIG_CMD_UBIFS /* UBIFS Support */
#define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */
#define CONFIG_CMD_UNZIP /* unzip from memory to memory */
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index b5efab5..f2e87ee 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -20,12 +20,9 @@
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_CMD_PXE
-
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
-#define CONFIG_MENU
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_ISO_PARTITION
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index 2ad54b7..3800932 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -96,7 +96,6 @@
#ifndef CONFIG_CMDLINE
#undef CONFIG_CMDLINE_EDITING
#undef CONFIG_SYS_LONGHELP
-#undef CONFIG_MENU
#endif
#endif /* __CONFIG_FALLBACKS_H */
diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index ebe018a..2cb8f5a 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -12,14 +12,12 @@
/*
* BOARD/CPU
*/
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* SERIAL
*/
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */
#define CONFIG_SYS_NS16550_MEM32
/*
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index b2126a6..b9f5439 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -12,14 +12,12 @@
/*
* BOARD/CPU
*/
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* SERIAL
*/
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */
/*
* CFI Flash
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2a8aeee..3ad9f80 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -7,13 +7,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* B4860 QDS board configuration file
*/
-#define CONFIG_B4860QDS
-
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
@@ -21,23 +17,14 @@
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
@@ -63,9 +50,6 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
@@ -78,23 +62,20 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#ifndef CONFIG_PPC_B4420
+#ifndef CONFIG_ARCH_B4420
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x77
@@ -241,13 +222,11 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_FSL_DDR3
#ifndef CONFIG_SPL_BUILD
#define CONFIG_FSL_DDR_INTERACTIVE
#endif
@@ -493,9 +472,6 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-#endif
/* I2C */
#define CONFIG_SYS_I2C
@@ -697,7 +673,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
@@ -805,7 +780,7 @@
#define __USB_PHY_TYPE ulpi
-#ifdef CONFIG_PPC_B4860
+#ifdef CONFIG_ARCH_B4860
#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
"bank_intlv=cs0_cs1;" \
"en_cpc:cpc2;"
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index a0ca0db..a6f73f2 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -11,12 +11,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-#ifdef CONFIG_BSC9131RDB
-#define CONFIG_BSC9131
#define CONFIG_NAND_FSL_IFC
-#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
@@ -28,8 +23,6 @@
#ifdef CONFIG_NAND
#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
@@ -53,12 +46,9 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
@@ -80,7 +70,6 @@
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_SYS_DDR_RAW_TIMING
#undef CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
@@ -95,7 +84,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
@@ -233,8 +221,6 @@
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -371,13 +357,6 @@
#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
"8m(kernel),512k(dtb),-(fs)"
-/*
- * Override partitions in device tree using info
- * in "mtdparts" environment variable
- */
-#ifdef CONFIG_CMD_MTDPARTS
-#define CONFIG_FDT_FIXUP_PARTITIONS
-#endif
/*
* Environment Configuration
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index eb6ddae..8aec315 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -11,12 +11,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-#ifdef CONFIG_BSC9132QDS
-#define CONFIG_BSC9132
-#endif
-
#define CONFIG_MISC_INIT_R
#ifdef CONFIG_SDCARD
@@ -26,7 +20,6 @@
#define CONFIG_SYS_TEXT_BASE 0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_RAMBOOT
@@ -44,8 +37,6 @@
#ifdef CONFIG_NAND
#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
@@ -77,13 +68,10 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
@@ -108,13 +96,10 @@
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_TSEC_ENET /* ethernet */
@@ -139,7 +124,6 @@
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
@@ -413,8 +397,6 @@
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -496,7 +478,6 @@
#endif /* CONFIG_TSEC_ENET */
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_FSL_ESDHC
@@ -609,14 +590,6 @@
"8m(kernel),512k(dtb),-(fs)"
#endif
/*
- * Override partitions in device tree using info
- * in "mtdparts" environment variable
- */
-#ifdef CONFIG_CMD_MTDPARTS
-#define CONFIG_FDT_FIXUP_PARTITIONS
-#endif
-
-/*
* Environment Configuration
*/
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index f75919d..53ee98c 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -11,12 +11,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-#ifdef CONFIG_C29XPCIE
-#define CONFIG_PPC_C29X
-#endif
-
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE 0x11000000
@@ -27,15 +21,8 @@
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE (128 << 10)
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
@@ -46,8 +33,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TEXT_BASE 0xff800000
@@ -83,13 +68,10 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#ifdef CONFIG_PCI
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
@@ -114,13 +96,10 @@
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
@@ -147,7 +126,6 @@
#define CONFIG_PANIC_HANG
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x50
@@ -383,8 +361,6 @@
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 603de33..55e48e2 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -20,7 +20,6 @@
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
@@ -75,8 +74,6 @@
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
@@ -108,10 +105,8 @@
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 06c5d3b..fb6e0ef 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -23,7 +23,6 @@
#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
@@ -98,8 +97,6 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
@@ -111,11 +108,6 @@
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
@@ -131,10 +123,8 @@
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 898ed7d..6230948 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -84,7 +84,6 @@
/* LCD */
#ifdef CONFIG_CMD_BMP
-#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_LCD_LOGO
#define CONFIG_SHARP_LQ035Q7DH06
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 735c4da..d61c68f 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -52,7 +52,6 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index 63b0a1e..9754bbd 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -40,7 +40,6 @@
/* Command line configuration */
#undef CONFIG_CMD_DATE
#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_UBI
#undef CONFIG_CMD_NAND
#define CONFIG_CMD_REGINFO
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 599ffc7..6a55e57 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -20,8 +20,6 @@
*/
#define CONFIG_M54451EVB /* M54451EVB board */
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 8301c46..abec373 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -20,8 +20,6 @@
*/
#define CONFIG_M54455EVB /* M54455EVB board */
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
@@ -174,8 +172,6 @@
/* PCI */
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index a3834f0..3b40cd0 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -19,8 +19,6 @@
* (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
@@ -96,8 +94,6 @@
/* PCI */
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index c94580e..2c18e98 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -19,8 +19,6 @@
* (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
@@ -93,8 +91,6 @@
/* PCI */
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 5da0005..f7fc652 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -17,7 +17,6 @@
* (easy to change)
***********************************************************/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_MIP405 1 /* ...on a MIP405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
@@ -57,9 +56,6 @@
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP
-#if !defined(CONFIG_MIP405T)
-#endif
-
/**************************************************************
* I2C Stuff:
* the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
@@ -107,19 +103,12 @@
#define CONFIG_SERVERIP 10.0.0.1
#define CONFIG_PREBOOT
/***************************************************************
- * defines if the console is stored in the environment
- ***************************************************************/
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
-/***************************************************************
* defines if an overwrite_console function exists
*************************************************************/
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
/***************************************************************
* defines if the overwrite_console should be stored in the
* environment
**************************************************************/
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
/**************************************************************
* loads config
@@ -168,10 +157,8 @@
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
/* resource configuration */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
@@ -312,7 +299,7 @@
/************************************************************
* IDE/ATA stuff
************************************************************/
-#if defined(CONFIG_MIP405T)
+#if defined(CONFIG_TARGET_MIP405T)
#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
#else
#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
@@ -347,23 +334,15 @@
/************************************************************
* Video support
************************************************************/
-#define CONFIG_VIDEO /*To enable video controller support */
-#define CONFIG_VIDEO_CT69000
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
#undef CONFIG_VIDEO_ONBOARD
/************************************************************
* USB support EXPERIMENTAL
************************************************************/
-#if !defined(CONFIG_MIP405T)
+#if !defined(CONFIG_TARGET_MIP405T)
#define CONFIG_USB_UHCI
-#define CONFIG_USB_KEYBOARD
/* Enable needed helper functions */
-#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
#endif
/************************************************************
* Debug support
@@ -377,21 +356,4 @@
************************************************************/
#define CONFIG_BZIP2 1
-/************************************************************
- * Ident
- ************************************************************/
-
-#define VERSION_TAG "released"
-#if !defined(CONFIG_MIP405T)
-#define CONFIG_ISO_STRING "MEV-10072-001"
-#else
-#define CONFIG_ISO_STRING "MEV-10082-001"
-#endif
-
-#if !defined(CONFIG_BOOT_PCI)
-#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
-#else
-#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 5b80464..7107a47 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -23,12 +21,9 @@
#define CONFIG_MISC_INIT_R
-#define CONFIG_MMC 1
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_USE_PIO
#define CONFIG_GENERIC_MMC
@@ -368,12 +363,9 @@
/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM 1
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 1c4e082..4b0b352 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -10,8 +10,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -22,8 +20,6 @@
#ifdef CONFIG_NAND
#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
@@ -58,7 +54,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_ELBC 1
@@ -398,7 +393,6 @@
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
/*
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 9f3dc49..bd25c0b 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
@@ -359,12 +357,9 @@
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 095c0d8..53f8a66 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -20,8 +18,6 @@
#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#define CONFIG_PCI 1
-
/*
* System Clock Setup
*/
@@ -258,7 +254,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SKIP_HOST_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 18418e3..12a47b2 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -340,7 +338,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index a2fa783..3d3eeb5 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -13,8 +13,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -33,7 +31,6 @@
#endif
#ifdef CONFIG_PCISLAVE
-#define CONFIG_PCI
#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
#endif /* CONFIG_PCISLAVE */
@@ -63,21 +60,16 @@
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
- * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
- * undefine it to use old spd_sdram.c
+ * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
+ * unselect it to use old spd_sdram.c
*/
-#define CONFIG_SYS_FSL_DDR2
-#ifdef CONFIG_SYS_FSL_DDR2
-#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x52
#define SPD_EEPROM_ADDRESS2 0x51
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#endif
/*
* 32-bit data path mode.
@@ -393,7 +385,6 @@
#undef PCI_ONE_PCI1
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 177718e..5f7eca0 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -40,8 +40,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
#define CONFIG_SYS_LOWBOOT
#endif
@@ -73,7 +71,6 @@
#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
#endif
-#define CONFIG_PCI
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C
#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
@@ -358,7 +355,7 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CONFIG_CONSOLE ttyS0
+#define CONSOLE ttyS0
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
@@ -402,8 +399,6 @@
#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR 0x00000000
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
@@ -740,10 +735,10 @@
__stringify(CONFIG_GATEWAYIP) ":" \
__stringify(CONFIG_NETMASK) ":" \
CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
- " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
+ " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=" __stringify(CONFIG_CONSOLE) "\0" \
+ "console=" __stringify(CONSOLE) "\0" \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index dd2aa04..f86b008 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -8,8 +8,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -383,8 +381,6 @@
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
@@ -487,8 +483,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_MMC 1
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index e010bd6..d843bd1 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -15,12 +15,9 @@
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XERDB 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#define CONFIG_PCI 1
-
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
@@ -398,7 +395,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
@@ -499,8 +495,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_MMC 1
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 3918160..ce33405 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -11,7 +11,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_SDCARD
@@ -38,14 +37,7 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8536 1
-#define CONFIG_MPC8536DS 1
-
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
@@ -55,7 +47,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -104,7 +95,6 @@
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
@@ -115,7 +105,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
@@ -494,9 +483,6 @@
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
/*PCIE video card used*/
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
@@ -504,13 +490,9 @@
/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
/* video */
-#define CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_BIOSEMU
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
@@ -621,8 +603,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_MMC 1
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index fae4b0c..3389a77 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -18,14 +18,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8540 1 /* MPC8540 specific */
-#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
-
/*
* default CCARBAR is at 0xff700000
* assume U-Boot is less than 0.5MB
@@ -36,12 +28,10 @@
#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
#endif
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx
@@ -78,7 +68,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -88,7 +77,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -258,9 +246,6 @@
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 0c2afb5..00a18b5 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -13,25 +13,16 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_CPM2 1 /* has CPM2 */
-#define CONFIG_MPC8541 1 /* MPC8541 specific */
-#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
#define CONFIG_SYS_TEXT_BASE 0xfff80000
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
#define CONFIG_FSL_VIA
#ifndef __ASSEMBLY__
@@ -52,7 +43,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -62,7 +52,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -303,7 +292,6 @@
#if defined(CONFIG_PCI)
#define CONFIG_MPC85XX_PCI2
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index d8dda87..b9c62e1 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -11,19 +11,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8544 1
-#define CONFIG_MPC8544DS 1
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
@@ -33,8 +24,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
@@ -63,7 +52,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
@@ -75,7 +63,6 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
@@ -277,20 +264,14 @@
/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
/* video */
-#define CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_BIOSEMU
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 789c62b..c241b51 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -13,14 +13,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8548 1 /* MPC8548 specific */
-#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
@@ -28,7 +20,6 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_PCI /* enable any pci type devices */
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2
@@ -40,7 +31,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
@@ -72,7 +62,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
@@ -84,7 +73,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -406,9 +394,6 @@
#endif
#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index fcd55c7..6faa230 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -13,23 +13,15 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_CPM2 1 /* has CPM2 */
-#define CONFIG_MPC8555 1 /* MPC8555 specific */
-#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
#define CONFIG_SYS_TEXT_BASE 0xfff80000
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
@@ -51,7 +43,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -61,7 +52,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -299,7 +289,6 @@
#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_MPC85XX_PCI2
#undef CONFIG_EEPRO100
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 4ed06c9..e0d010a 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -18,14 +18,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_CPM2 1 /* has CPM2 */
-#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
-#define CONFIG_MPC8560 1
/*
* default CCARBAR is at 0xff700000
@@ -33,13 +27,11 @@
*/
#define CONFIG_SYS_TEXT_BASE 0xfff80000
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
/*
@@ -75,7 +67,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
@@ -85,7 +76,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -253,9 +243,6 @@
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 39459de..0d3707f 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -10,20 +10,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8568 1 /* MPC8568 specific */
-#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
-
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* PCI controller */
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
@@ -33,7 +24,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
@@ -60,7 +50,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
@@ -71,7 +60,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -317,9 +305,6 @@
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 192cc2c..3e00f69 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -10,20 +10,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8569 1 /* MPC8569 specific */
-#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */
-
#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_PCI 1 /* Disable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
@@ -31,7 +22,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
@@ -87,7 +77,6 @@
#endif
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
@@ -99,7 +88,6 @@
/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -427,9 +415,6 @@
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -475,8 +460,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_MMC 1
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index e063c7a..5ca01e8 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -11,8 +11,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#include "../board/freescale/common/ics307_clk.h"
#ifndef CONFIG_SYS_TEXT_BASE
@@ -28,14 +26,9 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8572 1
-#define CONFIG_MPC8572DS 1
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
@@ -44,8 +37,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -91,7 +82,6 @@
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
@@ -103,7 +93,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
@@ -464,20 +453,14 @@
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
/* video */
-#define CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_BIOSEMU
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index c1b9b6e..c5f3634 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -11,11 +11,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
-#define CONFIG_MPC8610 1 /* MPC8610 specific */
-#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_SYS_TEXT_BASE 0xfff00000
@@ -25,11 +21,7 @@
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
-#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
@@ -44,14 +36,12 @@
*/
#define CONFIG_SYS_SCRATCH_VA 0xc0000000
-#define CONFIG_PCI 1 /* Enable PCI/PCIE*/
#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
@@ -81,7 +71,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
@@ -90,7 +79,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
#define CONFIG_DDR_SPD
@@ -103,7 +91,6 @@
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -277,7 +264,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_CMD_REGINFO
#define CONFIG_ULI526X
@@ -289,8 +275,6 @@
************************************************************/
#define CONFIG_PCI_OHCI 1
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL 1
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 1885124..fb66bb6 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -16,11 +16,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* High Level Configuration Options */
-#define CONFIG_MPC8641 1 /* MPC8641 specific */
-#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_ADDR_MAP 1 /* Use addr map */
@@ -44,12 +40,10 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -92,7 +86,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
@@ -108,7 +101,6 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
@@ -121,7 +113,6 @@
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -353,8 +344,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -363,8 +352,6 @@
************************************************************/
#define CONFIG_PCI_OHCI 1
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL 1
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
@@ -377,13 +364,9 @@
/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
/* video */
-#define CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_BIOSEMU
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index a4eabe5..75c5af6 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -9,7 +9,6 @@
#ifndef __MIGO_R_H
#define __MIGO_R_H
-#undef DEBUG
#define CONFIG_CPU_SH7722 1
#define CONFIG_MIGO_R 1
@@ -18,6 +17,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
@@ -40,10 +40,6 @@
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console
- information at boot */
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 0c84622..cd9cd9a 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -11,26 +11,13 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_P1010
-#define CONFIG_E500 /* BOOKE e500 family */
#include <asm/config_mpc85xx.h>
#define CONFIG_NAND_FSL_IFC
#ifdef CONFIG_SDCARD
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xD0001000
#define CONFIG_SPL_PAD_TO 0x18000
@@ -53,19 +40,9 @@
#define CONFIG_SYS_TEXT_BASE 0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xD0001000
#define CONFIG_SPL_PAD_TO 0x18000
@@ -86,8 +63,6 @@
#ifdef CONFIG_NAND
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
@@ -106,15 +81,7 @@
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE (128 << 10)
#define CONFIG_SPL_TEXT_BASE 0xD0001000
@@ -125,8 +92,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TEXT_BASE 0xff800000
@@ -165,13 +130,10 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
@@ -207,9 +169,9 @@
#endif
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
#endif
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
@@ -230,13 +192,10 @@
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
@@ -265,7 +224,6 @@
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
@@ -413,7 +371,7 @@
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
@@ -423,7 +381,7 @@
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
@@ -439,7 +397,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
/* NAND Flash Timing Params */
#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
FTIM0_NAND_TWP(0x0C) | \
@@ -454,7 +412,7 @@
FTIM2_NAND_TWHRE(0x0f)
#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
@@ -607,8 +565,6 @@
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -629,7 +585,7 @@
#define I2C_PCA9557_BUS_NUM 0
/* I2C EEPROM */
-#if defined(CONFIG_P1010RDB_PB)
+#if defined(CONFIG_TARGET_P1010RDB_PB)
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
@@ -713,7 +669,6 @@
#define CONFIG_LBA48
#endif /* #ifdef CONFIG_FSL_SATA */
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_FSL_ESDHC
@@ -755,10 +710,10 @@
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
#endif
@@ -879,7 +834,7 @@
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
CONFIG_BOOTMODE
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
#define CONFIG_BOOTMODE \
"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
"mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
@@ -888,7 +843,7 @@
"boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
"mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
#define CONFIG_BOOTMODE \
"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
"i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 9fbc128..505b417 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -11,20 +11,10 @@
#include "../board/freescale/common/ics307_clk.h"
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_SDCARD
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@@ -42,18 +32,9 @@
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@@ -78,14 +59,7 @@
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE (128 << 10)
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
@@ -96,8 +70,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TEXT_BASE 0xff800000
#define CONFIG_SPL_MAX_SIZE 4096
@@ -114,10 +86,6 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_P1022
-#define CONFIG_P1022DS
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
@@ -129,7 +97,6 @@
#endif
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
@@ -144,8 +111,6 @@
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
@@ -171,7 +136,6 @@
/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_FSL_DDR3
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
@@ -181,7 +145,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -404,11 +367,7 @@
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
-#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
@@ -424,14 +383,10 @@
#ifdef CONFIG_ATI
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
-#define CONFIG_VIDEO
#define CONFIG_BIOSEMU
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#endif
/* I2C */
@@ -527,7 +482,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
@@ -550,7 +504,6 @@
#define CONFIG_DOS_PARTITION
#endif
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index c01e72d..d8ff10e 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -10,8 +10,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
@@ -25,13 +23,9 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_P1023
#define CONFIG_MP /* support multiple processors */
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
@@ -39,7 +33,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
@@ -75,7 +68,6 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
#define CONFIG_SYS_SPD_BUS_NUM 0
@@ -232,7 +224,6 @@
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 3c3504b..3cd5c3c 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -11,10 +11,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_P2041RDB
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_PPC_P2041
-
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
@@ -32,9 +28,6 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
@@ -47,10 +40,9 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
@@ -63,8 +55,6 @@
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_DPAA_RMAN /* RMan */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
@@ -175,7 +165,6 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x52
@@ -543,7 +532,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
@@ -617,8 +605,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
-#define CONFIG_MMC
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index c901fe2..e32cdde 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -8,12 +8,8 @@
* P3041 DS board configuration file
*
*/
-#define CONFIG_P3041DS
-#define CONFIG_PPC_P3041
-
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 0d44c00..a6fa6a8 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -8,12 +8,8 @@
* P4080 DS board configuration file
* Also supports P4040 DS
*/
-#define CONFIG_P4080DS
-#define CONFIG_PPC_P4080
-
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_MMC
#define CONFIG_PCIE3
#define CONFIG_CMD_SATA
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index d2cedfe..0a8c387 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -8,12 +8,8 @@
* P5020 DS board configuration file
* Also supports P5010 DS
*/
-#define CONFIG_P5020DS
-#define CONFIG_PPC_P5020
-
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
index dc82721..5933fc0 100644
--- a/include/configs/P5040DS.h
+++ b/include/configs/P5040DS.h
@@ -8,12 +8,8 @@
* P5040 DS board configuration file
*
*/
-#define CONFIG_P5040DS
-#define CONFIG_PPC_P5040
-
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_PCIE3
#define CONFIG_FSL_SATA_V2
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index e96fbc5..c8d0a58 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -57,7 +57,6 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
#define CONFIG_PREBOOT
#define CONFIG_SYS_LONGHELP /* undef to save memory */
@@ -252,9 +251,4 @@
*/
#define CONFIG_SYS_DER 0x00000000
-#define VERSION_TAG "released"
-#define CONFIG_ISO_STRING "MEV-10084-001"
-
-#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
-
#endif /* __CONFIG_H */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index ecb126b..3dcb6ac 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -99,19 +99,12 @@
#define CONFIG_SERVERIP 10.0.0.1
#define CONFIG_PREBOOT
/***************************************************************
- * defines if the console is stored in the environment
- ***************************************************************/
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
-/***************************************************************
* defines if an overwrite_console function exists
*************************************************************/
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
/***************************************************************
* defines if the overwrite_console should be stored in the
* environment
**************************************************************/
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
/**************************************************************
* loads config
@@ -160,10 +153,8 @@
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
/* resource configuration */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
@@ -303,23 +294,15 @@
/************************************************************
* Video support
************************************************************/
-#define CONFIG_VIDEO /*To enable video controller support */
-#define CONFIG_VIDEO_CT69000
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
/************************************************************
* USB support
************************************************************/
#define CONFIG_USB_UHCI
-#define CONFIG_USB_KEYBOARD
/* Enable needed helper functions */
-#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
/************************************************************
* Debug support
@@ -333,11 +316,4 @@
************************************************************/
#define CONFIG_BZIP2 1
-/************************************************************
- * Ident
- ************************************************************/
-#define VERSION_TAG "released"
-#define CONFIG_ISO_STRING "MEV-10066-001"
-#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
-
#endif /* __CONFIG_H */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 391a697..0967577 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -21,7 +21,6 @@
#define CONFIG_PLU405 1 /* ...on a PLU405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
@@ -93,8 +92,6 @@
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
@@ -142,10 +139,8 @@
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
@@ -374,7 +369,6 @@
/*
* UBI
*/
-#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index 0b0db20..d7af4e0 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -12,7 +12,6 @@
#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
@@ -74,7 +73,6 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
@@ -100,10 +98,8 @@
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 956c787..2e7f6e4 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -29,8 +29,6 @@
#define CONFIG_SYS_TEXT_BASE 0xFFF90000
#endif
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_CLK_FREQ 33333400
#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
@@ -286,8 +284,6 @@
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
#define CONFIG_SUPPORT_VFAT
/*-----------------------------------------------------------------------
@@ -316,9 +312,7 @@
* PCI stuff
*----------------------------------------------------------------------*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 2218907..c9a1334 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -12,10 +12,6 @@
#define __T1024QDS_H
/* High Level Configuration Options */
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
@@ -26,15 +22,13 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
-#define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#endif
@@ -42,17 +36,8 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -67,19 +52,17 @@
#endif
#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
@@ -89,12 +72,12 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
#define CONFIG_SPL_SPI_BOOT
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
@@ -104,6 +87,7 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
#define CONFIG_SPL_MMC_BOOT
#endif
@@ -264,9 +248,6 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3
-#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
@@ -506,19 +487,14 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
/* Video */
-#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */
+#ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */
#define CONFIG_FSL_DIU_FB
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
@@ -575,7 +551,6 @@
* General PCIe
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
@@ -647,7 +622,6 @@
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
@@ -682,7 +656,6 @@
/*
* SDHC
*/
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index d5fd3e9..36eba4e 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -12,10 +12,6 @@
#define __T1024RDB_H
/* High Level Configuration Options */
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
@@ -26,40 +22,25 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
/* support deep sleep */
-#ifdef CONFIG_PPC_T1024
+#ifdef CONFIG_ARCH_T1024
#define CONFIG_DEEP_SLEEP
#endif
#if defined(CONFIG_DEEP_SLEEP)
-#define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
-#if defined(CONFIG_T1024RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
-#elif defined(CONFIG_T1023RDB)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
-#endif
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -74,19 +55,21 @@
#endif
#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
+#endif
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
@@ -96,12 +79,16 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
+#endif
#define CONFIG_SPL_SPI_BOOT
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
@@ -111,6 +98,11 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
+#endif
#define CONFIG_SPL_MMC_BOOT
#endif
@@ -183,9 +175,9 @@
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
#elif defined(CONFIG_SDCARD)
@@ -198,9 +190,9 @@
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#endif
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -279,14 +271,12 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_FSL_DDR_INTERACTIVE
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-#elif defined(CONFIG_T1023RDB)
-#define CONFIG_SYS_FSL_DDR4
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_SDRAM_SIZE 2048
#endif
@@ -309,9 +299,9 @@
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
#endif
@@ -338,7 +328,7 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
@@ -377,7 +367,7 @@
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
@@ -386,7 +376,7 @@
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
@@ -506,17 +496,12 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
/* Video */
#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
@@ -561,11 +546,10 @@
* General PCIe
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
-#ifdef CONFIG_PPC_T1040
+#ifdef CONFIG_ARCH_T1040
#define CONFIG_PCIE4 /* PCIE controller 4 */
#endif
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
@@ -657,7 +641,6 @@
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
@@ -676,7 +659,6 @@
/*
* SDHC
*/
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
@@ -722,7 +704,7 @@
#define CONFIG_SYS_DPAA_FMAN
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
#define CONFIG_QE
#define CONFIG_U_QE
#endif
@@ -746,10 +728,10 @@
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
#endif
@@ -777,12 +759,12 @@
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define RGMII_PHY1_ADDR 0x2
#define RGMII_PHY2_ADDR 0x6
#define SGMII_AQR_PHY_ADDR 0x2
#define FM1_10GEC1_PHY_ADDR 0x1
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define RGMII_PHY1_ADDR 0x1
#define SGMII_RTK_PHY_ADDR 0x3
#define SGMII_AQR_PHY_ADDR 0x2
@@ -868,7 +850,7 @@
#define CONFIG_BAUDRATE 115200
#define __USB_PHY_TYPE utmi
-#ifdef CONFIG_PPC_T1024
+#ifdef CONFIG_ARCH_T1024
#define CONFIG_BOARDNAME t1024rdb
#define BANK_INTLV cs0_cs1
#else
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 9488db2..8d6d986 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -26,8 +26,6 @@
/*
* T1040 QDS board configuration file
*/
-#define CONFIG_T1040QDS
-#define CONFIG_DISPLAY_BOARDINFO
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
@@ -37,16 +35,12 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
/* support deep sleep */
#define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
-#define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#endif
@@ -59,10 +53,9 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
@@ -72,8 +65,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
@@ -172,14 +163,10 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3
-#endif
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
@@ -408,18 +395,13 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
/* Video */
#define CONFIG_FSL_DIU_FB
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
@@ -524,8 +506,6 @@
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
@@ -563,8 +543,6 @@
#endif
#endif
-#define CONFIG_MMC
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 07c511f..d574bbb 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -10,10 +10,6 @@
/*
* T104x RDB board configuration file
*/
-#define CONFIG_T104xRDB
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_E500 /* BOOKE e500 family */
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_RAMBOOT_PBL
@@ -25,34 +21,8 @@
$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
#endif
-#ifdef CONFIG_T1040RDB
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
-#endif
-#ifdef CONFIG_T1042RDB_PI
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
-#endif
-#ifdef CONFIG_T1042RDB
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
-#endif
-#ifdef CONFIG_T1040D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
-#endif
-#ifdef CONFIG_T1042D4RDB
-#define CONFIG_SYS_FSL_PBL_RCW \
-$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
-#endif
-
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -67,7 +37,6 @@
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_SUPPORT
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
/*
@@ -83,13 +52,31 @@
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#ifdef CONFIG_TARGET_T1040RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1040D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
+#endif
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
@@ -99,12 +86,31 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#ifdef CONFIG_TARGET_T1040RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1040D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
+#endif
#define CONFIG_SPL_SPI_BOOT
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
@@ -114,14 +120,32 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#ifdef CONFIG_TARGET_T1040RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1040D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
+#endif
#define CONFIG_SPL_MMC_BOOT
#endif
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
@@ -129,7 +153,6 @@
#define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SILENT_CONSOLE
#endif
#ifndef CONFIG_SYS_TEXT_BASE
@@ -141,10 +164,9 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
@@ -154,8 +176,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_SYS_NO_FLASH
@@ -248,14 +268,10 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3
-#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
@@ -314,13 +330,13 @@
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
-#if defined(CONFIG_T1042RDB_PI)
+#if defined(CONFIG_TARGET_T1042RDB_PI)
#define CPLD_DIU_SEL_DFP 0x80
-#elif defined(CONFIG_T1042D4RDB)
+#elif defined(CONFIG_TARGET_T1042D4RDB)
#define CPLD_DIU_SEL_DFP 0xc0
#endif
-#if defined(CONFIG_T1040D4RDB)
+#if defined(CONFIG_TARGET_T1040D4RDB)
#define CPLD_INT_MASK_ALL 0xFF
#define CPLD_INT_MASK_THERM 0x80
#define CPLD_INT_MASK_DVI_DFP 0x40
@@ -487,23 +503,15 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-#endif
-#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
/* Video */
#define CONFIG_FSL_DIU_FB
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_CFB_CONSOLE_ANSI
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
@@ -527,11 +535,11 @@
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
-#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
#define I2C_MUX_CH_DEFAULT 0x8
-#endif
-#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
+#if defined(CONFIG_TARGET_T1042RDB_PI) || \
+ defined(CONFIG_TARGET_T1040D4RDB) || \
+ defined(CONFIG_TARGET_T1042D4RDB)
/* LDI/DVI Encoder for display */
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
@@ -612,8 +620,6 @@
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
@@ -648,8 +654,6 @@
#endif
#endif
-#define CONFIG_MMC
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
@@ -688,10 +692,8 @@
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
#define CONFIG_QE
#define CONFIG_U_QE
-#endif
/* Default address of microcode for the Linux Fman driver */
#if defined(CONFIG_SPIFLASH)
@@ -717,7 +719,6 @@
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
-#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_QE_FW_ADDR 0x130000
#elif defined(CONFIG_SDCARD)
@@ -727,7 +728,6 @@
#else
#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
#endif
-#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
@@ -740,17 +740,17 @@
#endif
#ifdef CONFIG_FMAN_ENET
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
-#elif defined(CONFIG_T1040D4RDB)
+#elif defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
-#elif defined(CONFIG_T1042D4RDB)
+#elif defined(CONFIG_TARGET_T1042D4RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
#endif
-#ifdef CONFIG_T104XD4RDB
+#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
#else
@@ -759,10 +759,10 @@
#endif
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
+#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_VSC9953
#define CONFIG_CMD_ETHSW
-#ifdef CONFIG_T1040RDB
+#ifdef CONFIG_TARGET_T1040RDB
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
#else
@@ -785,7 +785,7 @@
/*
* Command line configuration.
*/
-#ifdef CONFIG_T1042RDB_PI
+#ifdef CONFIG_TARGET_T1042RDB_PI
#define CONFIG_CMD_DATE
#endif
#define CONFIG_CMD_ERRATA
@@ -863,15 +863,15 @@
#define __USB_PHY_TYPE utmi
#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
-#ifdef CONFIG_T1040RDB
+#ifdef CONFIG_TARGET_T1040RDB
#define FDTFILE "t1040rdb/t1040rdb.dtb"
-#elif defined(CONFIG_T1042RDB_PI)
+#elif defined(CONFIG_TARGET_T1042RDB_PI)
#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
-#elif defined(CONFIG_T1042RDB)
+#elif defined(CONFIG_TARGET_T1042RDB)
#define FDTFILE "t1042rdb/t1042rdb.dtb"
-#elif defined(CONFIG_T1040D4RDB)
+#elif defined(CONFIG_TARGET_T1040D4RDB)
#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
-#elif defined(CONFIG_T1042D4RDB)
+#elif defined(CONFIG_TARGET_T1042D4RDB)
#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
#endif
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 065ffcd..210d8d8 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -11,24 +11,17 @@
#ifndef __T208xQDS_H
#define __T208xQDS_H
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#define CONFIG_MMC
#define CONFIG_USB_EHCI
-#if defined(CONFIG_PPC_T2080)
-#define CONFIG_T2080QDS
+#if defined(CONFIG_ARCH_T2080)
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-#elif defined(CONFIG_PPC_T2081)
-#define CONFIG_T2081QDS
+#elif defined(CONFIG_ARCH_T2081)
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
@@ -39,30 +32,16 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
-#if defined(CONFIG_PPC_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
-#elif defined(CONFIG_PPC_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
-#endif
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -77,19 +56,21 @@
#endif
#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
+#endif
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
@@ -99,12 +80,16 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
+#endif
#define CONFIG_SPL_SPI_BOOT
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
@@ -114,6 +99,11 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
+#endif
#define CONFIG_SPL_MMC_BOOT
#endif
@@ -230,7 +220,6 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
@@ -552,7 +541,6 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
@@ -602,7 +590,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 1a8c62e..1941188 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -11,17 +11,11 @@
#ifndef __T2080RDB_H
#define __T2080RDB_H
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_T2080RDB
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#define CONFIG_MMC
#define CONFIG_USB_EHCI
#define CONFIG_FSL_SATA_V2
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
@@ -32,26 +26,16 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -66,19 +50,17 @@
#endif
#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
@@ -88,12 +70,12 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
#define CONFIG_SPL_SPI_BOOT
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
@@ -103,6 +85,7 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
#define CONFIG_SPL_MMC_BOOT
#endif
@@ -222,7 +205,6 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
@@ -498,7 +480,6 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
@@ -547,7 +528,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 06f03aa..78ad86c 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -10,8 +10,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_T4240QDS
-
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
@@ -20,21 +18,12 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -43,18 +32,17 @@
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
@@ -64,6 +52,7 @@
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
#define CONFIG_SPL_MMC_BOOT
#endif
@@ -527,8 +516,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_MMC
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
@@ -552,7 +539,7 @@
* interleaving. It can be cacheline, page, bank, superbank.
* See doc/README.fsl-ddr for details.
*/
-#ifdef CONFIG_PPC_T4240
+#ifdef CONFIG_ARCH_T4240
#define CTRL_INTLV_PREFERED 3way_4KB
#else
#define CTRL_INTLV_PREFERED cacheline
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 38ad503..e15b0ea 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -10,9 +10,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_T4240RDB
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
@@ -20,21 +17,12 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
#ifndef CONFIG_SDCARD
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@@ -44,7 +32,6 @@
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
@@ -54,6 +41,7 @@
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
#define CONFIG_SPL_MMC_BOOT
#endif
@@ -72,9 +60,6 @@
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
@@ -87,18 +72,15 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
/*
@@ -145,13 +127,11 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
/*
* IFC Definitions
@@ -259,7 +239,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
@@ -719,8 +698,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_MMC
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
@@ -745,7 +722,7 @@
* interleaving. It can be cacheline, page, bank, superbank.
* See doc/README.fsl-ddr for details.
*/
-#ifdef CONFIG_PPC_T4240
+#ifdef CONFIG_ARCH_T4240
#define CTRL_INTLV_PREFERED 3way_4KB
#else
#define CTRL_INTLV_PREFERED cacheline
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 14e06fb..708eb76 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
@@ -52,7 +51,6 @@
#ifdef CONFIG_FO300
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
-#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
#if 0
@@ -78,8 +76,6 @@
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCI_MEM_BUS 0x40000000
@@ -99,22 +95,16 @@
* Video console
*/
#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#ifndef CONFIG_FO300
-#define CONFIG_CONSOLE_EXTRA_INFO
#else
#define CONFIG_VIDEO_BMP_LOGO
#endif
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif /* #ifndef CONFIG_TQM5200S */
/* Partitions */
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index c557ba1..2fd5fa3 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 814740b..11bba09 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 90e8dd9..68e5990 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -12,8 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -227,11 +225,9 @@
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_PCI
#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* PCI1 host bridge */
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 58fd8a4..548f1bc 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 3a4f94c..582b934 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 134076c..814290f 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index ad6f8f4..4a657ff 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index b935f31..bdfe509 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 79248de..ce6b404 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index d360644..66dbcb6 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -20,7 +20,6 @@
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 5c6013b..478f16b 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -20,7 +20,6 @@
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index c098f72..5501622 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 9d8a607..b246926 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -22,7 +22,6 @@
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 57748b4..f32fb4d 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -14,10 +14,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_FSL_ELBC
-#define CONFIG_PCI
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
@@ -30,7 +27,6 @@
#define CONFIG_UCP1020_REV_1_3
#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
-#define CONFIG_P1020
#define CONFIG_TSEC_ENET
#define CONFIG_TSEC1
@@ -49,15 +45,10 @@
#endif
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_MMC
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_LAST_STAGE_INIT
-#if !defined(CONFIG_DONGLE)
-#define CONFIG_SILENT_CONSOLE
-#endif
-
#endif
#if defined(CONFIG_TARGET_UCP1020)
@@ -66,7 +57,6 @@
#define CONFIG_UCP1020_REV_1_3
#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
-#define CONFIG_P1020
#define CONFIG_TSEC_ENET
#define CONFIG_TSEC1
@@ -90,7 +80,6 @@
#endif
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_MMC
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_LAST_STAGE_INIT
@@ -126,15 +115,8 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500
-/* #define CONFIG_MPC85xx */
-
#define CONFIG_MP
-#define CONFIG_FSL_LAW
-
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CMD_SATA
@@ -194,7 +176,6 @@
/* DDR Setup */
#define CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_FSL_DDR3
#ifndef CONFIG_DDR_ECC_ENABLE
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
@@ -208,7 +189,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
@@ -397,7 +377,6 @@
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
deleted file mode 100644
index c5a7d68..0000000
--- a/include/configs/VCMA9.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * (C) Copyright 2002, 2003
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <garyj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * Configuation settings for the MPL VCMA9 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define MACH_TYPE_MPL_VCMA9 227
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_THUMB_BUILD
-
-#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
-#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
-#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
-#define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */
-
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-
-/* input clock of PLL (VCMA9 has 12MHz input clock) */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_NAND
-
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * I2C stuff:
- * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
- * address 0x50 with 16bit addressing
- */
-#define CONFIG_SYS_I2C
-
-/* we use the built-in I2C controller */
-#define CONFIG_SYS_I2C_S3C24X0
-#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-/* use EEPROM for environment vars */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-/* environment starts at offset 0 */
-#define CONFIG_ENV_OFFSET 0x000
-/* 2KB should be more than enough */
-#define CONFIG_ENV_SIZE 0x800
-
-#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-/* 64 bytes page write mode on 24C256 */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * Hardware drivers
- */
-#define CONFIG_CS8900 /* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE 0x20000300
-#define CONFIG_CS8900_BUS16
-
-/*
- * select serial console configuration
- */
-#define CONFIG_S3C24X0_SERIAL
-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
-
-/* USB support (currently only works with D-cache off) */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_OHCI_S3C24XX
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_DOS_PARTITION
-
-/* Enable needed helper functions */
-#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
-
-/* RTC */
-#define CONFIG_RTC_S3C24X0
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_RESET_TO_RETRY
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.0.0.110
-#define CONFIG_SERVERIP 10.0.0.1
-
-#if defined(CONFIG_CMD_KGDB)
-/* speed to run kgdb serial port */
-#define CONFIG_KGDB_BAUDRATE 115200
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_DISPLAY_BOARDINFO /* Display board info */
-
-#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
-
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_LOAD_ADDR 0x30800000
-
-/* we configure PWM Timer 4 to 1ms 1000Hz */
-
-/* support additional compression methods */
-#define CONFIG_BZIP2
-#define CONFIG_LZO
-#define CONFIG_LZMA
-
-/* Ident */
-/*#define VERSION_TAG "released"*/
-#define VERSION_TAG "unstable"
-#define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \
- "MEV-10080-001 " VERSION_TAG
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/* FLASH and environment organization */
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT (19)
-
-/*
- * Size of malloc() pool
- * BZIP2 / LZO / LZMA need a lot of RAM
- */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-/* NAND configuration */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_S3C2410
-#define CONFIG_SYS_S3C2410_NAND_HWECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x4E000000
-#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
-#define CONFIG_S3C24XX_TACLS 1
-#define CONFIG_S3C24XX_TWRPH0 5
-#define CONFIG_S3C24XX_TWRPH1 3
-#endif
-
-#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-
-/* File system */
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_JFFS2
-#define CONFIG_YAFFS2
-#define CONFIG_RBTREE
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index 5e30511..50d2405 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -19,7 +19,6 @@
#define CONFIG_VOM405 1 /* ...on a VOM405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
@@ -83,8 +82,6 @@
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index ab2477c..a0306ca 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -14,7 +14,6 @@
#define CONFIG_MPC5200
#define CONFIG_A3M071 /* A3M071 board */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
@@ -54,7 +53,6 @@
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_NET_RETRY_COUNT 3
#define CONFIG_NETCONSOLE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS /* needed for UBI */
#define CONFIG_FLASH_CFI_MTD
@@ -75,7 +73,6 @@
#define CONFIG_LZO /* needed for UBI */
#define CONFIG_RBTREE /* needed for UBI */
#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
/*
@@ -249,8 +246,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x00100000
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
-
/*
* Various low-level settings
*/
@@ -332,7 +327,6 @@
#undef CONFIG_BOOTARGS
-#define CONFIG_SYS_OS_BASE 0xfc200000
#define CONFIG_SYS_FDT_BASE 0xfc1e0000
#define CONFIG_SYS_FDT_SIZE (16<<10)
@@ -397,18 +391,12 @@
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0xfc000000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
-#define CONFIG_SPL_SERIAL_SUPPORT
/* Place BSS for SPL near end of SDRAM */
#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_ENV_SUPPORT
/* Place patched DT blob (fdt) at this address */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index bdc81ff..b41ebe0 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -19,7 +19,6 @@
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_A4M072 1 /* ... on A4M072 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xFE000000
@@ -36,7 +35,6 @@
#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* define to enable silent console */
-#define CONFIG_SILENT_CONSOLE
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
/*
@@ -44,10 +42,8 @@
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-#define CONFIG_PCI
#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index 699ac41..2d1c099 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -13,7 +13,6 @@
#define __CONFIG_H
#define CONFIG_AC14XX 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the ifm AC14xx board:
@@ -32,11 +31,6 @@
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#if defined(CONFIG_VIDEO)
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#endif
-
#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */
#define SCFR1_IPS_DIV 2
#define SCFR1_LPC_DIV 2
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index c4e0a21..93fa614 100644
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -28,7 +28,6 @@
#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
#define CONFIG_INITRD_TAG /* send initrd params */
-#define CONFIG_NEEDS_MANUAL_RELOC
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_MEM_REMAP
@@ -101,7 +100,6 @@
/*
* SD (MMC) controller
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_FTSDC010
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index 992948a..99f9ef7 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -13,10 +13,9 @@
#include <asm/imx-common/gpio.h>
#define CONFIG_BOARD_NAME "Advantech DMS-BA16"
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-dms-ba16.dtb"
#define CONFIG_MXC_UART_BASE UART4_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc3"
+#define CONSOLE_DEV "ttymxc3"
#define CONFIG_EXTRA_BOOTARGS "panic=10"
#define CONFIG_BOOT_DIR ""
@@ -28,9 +27,6 @@
#include "mx6_common.h"
#include <linux/sizes.h>
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -59,7 +55,6 @@
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_DOS_PARTITION
@@ -72,7 +67,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
#define CONFIG_USBD_HS
@@ -117,7 +111,7 @@
"fdt_addr=0x18000000\0" \
"boot_fdt=yes\0" \
"ip_dyn=yes\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV "\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"sddev=0\0" \
@@ -275,12 +269,7 @@
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* Framebuffer */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
@@ -296,8 +285,6 @@
#undef CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
diff --git a/include/configs/alt.h b/include/configs/alt.h
index 7d6ec78..726e6d6 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -87,7 +87,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* MMCIF */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SH_MMCIF
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index f12ee04..49c14df 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -17,6 +17,7 @@
#define __CONFIG_AM335X_EVM_H
#include <configs/ti_am335x_common.h>
+#include <environment/ti/dfu.h>
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
@@ -90,6 +91,9 @@
func(DHCP, dhcp, na)
#define CONFIG_BOOTCOMMAND \
+ "if test ${boot_fit} -eq 1; then " \
+ "run update_to_fit;" \
+ "fi;" \
"run findfdt; " \
"run init_console; " \
"run envboot; " \
@@ -101,7 +105,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
- "boot_fdt=try\0" \
+ DEFAULT_FIT_TI_ARGS \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
@@ -127,30 +131,6 @@
"root=${ramroot} " \
"rootfstype=${ramrootfstype}\0" \
"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcloados=run args_mmc; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "run envboot; " \
- "if run loadimage; then " \
- "run mmcloados;" \
- "fi;" \
- "fi;\0" \
"spiboot=echo Booting from spi ...; " \
"run spiargs; " \
"sf probe ${spibusno}:0; " \
@@ -206,18 +186,14 @@
/* SPL */
#ifndef CONFIG_NOR_BOOT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-
/* Bootcount using the RTC block */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_AM33XX
#define CONFIG_SYS_BOOTCOUNT_BE
/* USB gadget RNDIS */
-#define CONFIG_SPL_MUSB_NEW_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#endif
#ifdef CONFIG_NAND
@@ -301,8 +277,6 @@
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
-/* To support eMMC booting */
-#define CONFIG_STORAGE_EMMC
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#endif
@@ -322,63 +296,21 @@
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
#undef CONFIG_TIMER
+#undef CONFIG_DM_USB
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* Remove other SPL modes. */
-#undef CONFIG_SPL_YMODEM_SUPPORT
-#undef CONFIG_SPL_NAND_SUPPORT
-#undef CONFIG_SPL_MMC_SUPPORT
#define CONFIG_ENV_IS_NOWHERE
#undef CONFIG_ENV_IS_IN_NAND
/* disable host part of MUSB in SPL */
/* disable EFI partitions and partition UUID support */
#undef CONFIG_PARTITION_UUIDS
#undef CONFIG_EFI_PARTITION
-/* General network SPL */
-#define CONFIG_SPL_NET_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
#endif
/* USB Device Firmware Update support */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
-#define DFU_ALT_INFO_MMC \
- "dfu_alt_info_mmc=" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1\0"
-#ifdef CONFIG_NAND
-#define CONFIG_DFU_NAND
-#define DFU_ALT_INFO_NAND \
- "dfu_alt_info_nand=" \
- "SPL part 0 1;" \
- "SPL.backup1 part 0 2;" \
- "SPL.backup2 part 0 3;" \
- "SPL.backup3 part 0 4;" \
- "u-boot part 0 5;" \
- "u-boot-spl-os part 0 6;" \
- "kernel part 0 8;" \
- "rootfs part 0 9\0"
-#else
-#define DFU_ALT_INFO_NAND ""
-#endif
-#define CONFIG_DFU_RAM
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0xD80000;" \
- "fdt ram 0x80F80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
#define DFUARGS \
"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
DFU_ALT_INFO_MMC \
@@ -397,9 +329,6 @@
*/
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
-#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
@@ -416,7 +345,6 @@
"-(rootfs)"
#elif defined(CONFIG_EMMC_BOOT)
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x0
@@ -452,6 +380,8 @@
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
+/* Enable Atheros phy driver */
+#define CONFIG_PHY_ATHEROS
/*
* NOR Size = 16 MiB
diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h
index a14310a..16fb1ae 100644
--- a/include/configs/am335x_igep0033.h
+++ b/include/configs/am335x_igep0033.h
@@ -123,9 +123,7 @@
#undef CONFIG_USE_IRQ
/* SPL */
-#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
-#define CONFIG_SPL_YMODEM_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index 9327c3d..32f93d2 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -21,7 +21,6 @@
#undef CONFIG_CMD_EXT4_WRITE
#undef CONFIG_CMD_MMC_SPI
#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_PXE
#define CONFIG_CMD_CACHE
@@ -279,14 +278,10 @@
#define CONFIG_POWER_TPS65217
/* SPL */
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#ifndef CONFIG_SPL_USBETH_SUPPORT
-/* To support eMMC booting */
-#define CONFIG_STORAGE_EMMC
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#endif
@@ -326,11 +321,6 @@
#if defined CONFIG_SHC_NETBOOT
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_NET_SUPPORT
-#define CONFIG_SPL_ETH_SUPPORT
-#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_ENV_IS_NOWHERE
#undef CONFIG_ENV_IS_IN_MMC
#endif
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index 8454872..ca5bb1a 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -80,27 +80,20 @@
#define CONFIG_POWER_TPS65910
/* SPL */
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
/* Bootcount using the RTC block */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_AM33XX
#define CONFIG_SYS_BOOTCOUNT_BE
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#ifndef CONFIG_SPL_USBETH_SUPPORT
-/* To support eMMC booting */
-#define CONFIG_STORAGE_EMMC
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* Remove other SPL modes. */
-#undef CONFIG_SPL_YMODEM_SUPPORT
-#undef CONFIG_SPL_NAND_SUPPORT
-#undef CONFIG_SPL_MMC_SUPPORT
#define CONFIG_ENV_IS_NOWHERE
#undef CONFIG_ENV_IS_IN_NAND
/* disable host part of MUSB in SPL */
@@ -108,16 +101,11 @@
/* disable EFI partitions and partition UUID support */
#undef CONFIG_PARTITION_UUIDS
#undef CONFIG_EFI_PARTITION
-/* General network SPL */
-#define CONFIG_SPL_NET_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
#endif
#if defined(CONFIG_EMMC_BOOT)
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x0
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 0055803..ad0de2c8 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -18,7 +18,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
-#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
@@ -29,12 +28,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -83,7 +76,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
@@ -112,7 +104,6 @@
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID 0x0451
#define CONFIG_USBD_PRODUCTID 0x5678
@@ -282,24 +273,13 @@
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 98c29b0..3247a4a 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -16,7 +16,6 @@
/* High Level Configuration Options */
#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_NO_FLASH
@@ -42,9 +41,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
@@ -81,7 +77,6 @@
115200}
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
@@ -140,7 +135,6 @@
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_BCH
-#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
@@ -339,24 +333,12 @@
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_MTD_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#endif /* __CONFIG_H */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 495dd8a..b47acb2 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -14,6 +14,7 @@
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#include <environment/ti/dfu.h>
#include <asm/arch/omap.h>
/* NS16550 Configuration */
@@ -39,8 +40,6 @@
#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
/* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
@@ -84,12 +83,9 @@
#define FAT_ENV_FILE "uboot.env"
#define CONFIG_FAT_WRITE
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* SPL USB Support */
-#ifdef CONFIG_SPL_USB_HOST_SUPPORT
-#define CONFIG_SPL_USB_SUPPORT
-#endif
#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
@@ -127,48 +123,12 @@
#ifndef CONFIG_SPL_BUILD
/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_RAM
-
-#define CONFIG_DFU_MMC
-#define DFU_ALT_INFO_MMC \
- "dfu_alt_info_mmc=" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
- "dfu_alt_info_emmc=" \
- "MLO raw 0x100 0x100 mmcpart 0;" \
- "u-boot.img raw 0x300 0x1000 mmcpart 0\0"
-
-#define CONFIG_DFU_RAM
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0x4000000;" \
- "fdt ram 0x80f80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
-
-#define CONFIG_DFU_SF
-#define DFU_ALT_INFO_QSPI \
- "dfu_alt_info_qspi=" \
- "u-boot.bin raw 0x0 0x080000;" \
- "u-boot.backup raw 0x080000 0x080000;" \
- "u-boot-spl-os raw 0x100000 0x010000;" \
- "u-boot-env raw 0x110000 0x010000;" \
- "u-boot-env.backup raw 0x120000 0x010000;" \
- "kernel raw 0x130000 0x800000\0"
-
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
DFU_ALT_INFO_RAM \
- DFU_ALT_INFO_QSPI
+ DFU_ALT_INFO_QSPI_XIP
#else
#define DFUARGS
#endif
@@ -216,6 +176,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
@@ -239,20 +200,6 @@
"root=${ramroot} " \
"rootfstype=${ramrootfstype}\0" \
"loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
- "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "setenv devnum ${mmcdev}; " \
- "setenv devtype mmc; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${devnum};" \
- "if run loadimage; then " \
- "run loadfdt; " \
- "echo Booting from mmc${mmcdev} ...; " \
- "run args_mmc; " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi;" \
- "fi;\0" \
"usbboot=" \
"setenv devnum ${usbdev}; " \
"setenv devtype usb; " \
@@ -293,6 +240,9 @@
DFUARGS \
#define CONFIG_BOOTCOMMAND \
+ "if test ${boot_fit} -eq 1; then " \
+ "run update_to_fit;" \
+ "fi;" \
"run findfdt; " \
"run envboot;" \
"run mmcboot;" \
@@ -318,13 +268,9 @@
#define CONFIG_PHYLIB
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL"
-
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT)
#undef CONFIG_ENV_IS_IN_FAT
#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SPL_NET_SUPPORT
#endif
#define CONFIG_SYS_RX_ETH_BUFFER 64
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 3479de4..cfd1f14 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -12,7 +12,9 @@
#ifndef __CONFIG_AM57XX_EVM_H
#define __CONFIG_AM57XX_EVM_H
-#define CONFIG_AM57XX
+#include <environment/ti/dfu.h>
+
+#define CONFIG_DRA7XX
#ifdef CONFIG_SPL_BUILD
#define CONFIG_IODELAY_RECALIBRATION
@@ -38,14 +40,40 @@
/* Define the default GPT table for eMMC */
#define PARTS_DEFAULT \
+ /* Linux partitions */ \
"uuid_disk=${uuid_gpt_disk};" \
- "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+ /* Android partitions */ \
+ "partitions_android=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
+ "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \
+ "name=environment,size=128K,uuid=${uuid_gpt_environment};" \
+ "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
+ "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
+ "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
+ "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
+ "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \
+ "name=boot,size=10M,uuid=${uuid_gpt_boot};" \
+ "name=system,size=768M,uuid=${uuid_gpt_system};" \
+ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
+ "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \
+ "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
+ "name=userdata,size=-,uuid=${uuid_gpt_userdata}"
+
+#define DFUARGS \
+ "dfu_bufsiz=0x10000\0" \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_EMMC \
+ DFU_ALT_INFO_RAM \
#include <configs/ti_omap5_common.h>
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
+#define CONFIG_RANDOM_UUID
+#define CONFIG_HSMMC2_8BIT
/* CPSW Ethernet */
#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
@@ -104,11 +132,8 @@
#endif
/* SPI SPL */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_DMA_SUPPORT
#define CONFIG_TI_EDMA3
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* SPI */
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index f4261e9..7974c53 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -78,7 +78,6 @@
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 5667680..4a54cb6 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -1,7 +1,7 @@
/*
* Sysam AMCORE board configuration
*
- * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -19,6 +19,17 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_BOOTCOMMAND "bootm ffc20000"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "upgrade_uboot=loady; " \
+ "protect off 0xffc00000 0xffc1ffff; " \
+ "erase 0xffc00000 0xffc1ffff; " \
+ "cp.b 0x20000 0xffc00000 ${filesize}\0" \
+ "upgrade_kernel=loady; " \
+ "erase 0xffc20000 0xffefffff; " \
+ "cp.b 0x20000 0xffc20000 ${filesize}\0" \
+ "upgrade_jffs2=loady; " \
+ "erase 0xfff00000 0xffffffff; " \
+ "cp.b 0x20000 0xfff00000 ${filesize}\0"
#undef CONFIG_CMD_AES
#define CONFIG_CMD_DIAG
@@ -40,7 +51,6 @@
/* Boot argument buffer size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index bf5746f..2da520e 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_HZ 1000
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 5d7e49e..ce64c94 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_HZ 1000
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index 32acb08..c86ce05 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -10,7 +10,6 @@
#ifndef __AP325RXA_H
#define __AP325RXA_H
-#undef DEBUG
#define CONFIG_CPU_SH7723 1
#define CONFIG_AP325RXA 1
@@ -21,6 +20,7 @@
#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTARGS "console=ttySC2,38400"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9118 */
@@ -55,9 +55,6 @@
#define CONFIG_CONS_SCIF5 1
/* Suppress display of console information at boot */
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
index d41b624..4b07f06 100644
--- a/include/configs/ap_sh4a_4a.h
+++ b/include/configs/ap_sh4a_4a.h
@@ -9,7 +9,6 @@
#ifndef __AP_SH4A_4A_H
#define __AP_SH4A_4A_H
-#undef DEBUG
#define CONFIG_CPU_SH7734 1
#define CONFIG_AP_SH4A_4A 1
#define CONFIG_400MHZ_MODE 1
@@ -24,6 +23,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC4,115200"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Ether */
@@ -71,9 +71,6 @@
#define CONFIG_CONS_SCIF4 1
/* Suppress display of console information at boot */
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE (0x88000000)
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
new file mode 100644
index 0000000..fdf9ed0
--- /dev/null
+++ b/include/configs/apalis_imx6.h
@@ -0,0 +1,336 @@
+/*
+ * Copyright 2013-2015 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex Apalis iMX6
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_SYS_THUMB_BUILD
+
+#undef CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
+
+#define CONFIG_MACH_TYPE 4886
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#define CONFIG_SPL_PAD_TO 0x11000 /* 4k IVT/DCD, 64k SPL */
+#endif
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* Make the HW version stuff available in U-Boot env */
+#define CONFIG_VERSION_VARIABLE /* ver environment variable */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* OCOTP Configs */
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+
+#ifdef CONFIG_MX6Q
+#define CONFIG_CMD_SATA
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE 4096
+#define CONFIG_TFTP_TSIZE
+
+/* USB Configs */
+/* Host */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_KEYBOARD
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#endif /* CONFIG_USB_KEYBOARD */
+/* Client */
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_G_DNL_MANUFACTURER "Toradex"
+/* USB DFU */
+#define CONFIG_DFU_MMC
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_MXC_GPIO
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_CMD_BMP
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FLASH
+
+#undef CONFIG_IPADDR
+#define CONFIG_IPADDR 192.168.10.2
+#define CONFIG_NETMASK 255.255.255.0
+#undef CONFIG_SERVERIP
+#define CONFIG_SERVERIP 192.168.10.1
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DRIVE_SATA "sata "
+#else
+#define CONFIG_DRIVE_SATA
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_DRIVE_MMC "mmc "
+#else
+#define CONFIG_DRIVE_MMC
+#endif
+
+#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
+
+#define DFU_ALT_EMMC_INFO \
+ "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "uImage fat 0 1;" \
+ "imx6q-colibri-eval-v3.dtb fat 0 1;" \
+ "imx6q-colibri-cam-eval-v3.dtb fat 0 1"
+
+#define EMMC_BOOTCMD \
+ "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "emmcboot=run setup; " \
+ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
+ "${vidargs}; echo Booting from internal eMMC chip...; " \
+ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x12000000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "kernel_addr_r=0x11000000\0" \
+ "ramdisk_addr_r=0x12100000\0"
+
+#define NFS_BOOTCMD \
+ "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
+ "nfsboot=run setup; " \
+ "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
+ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
+ "run nfsdtbload; dhcp ${kernel_addr_r} " \
+ "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
+ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define SD_BOOTCMD \
+ "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "sdboot=run setup; " \
+ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
+ "${vidargs}; echo Booting from SD card; " \
+ "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define USB_BOOTCMD \
+ "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
+ "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
+ "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+#define FDT_FILE "imx6q-apalis-eval.dtb"
+#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb"
+#else
+#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb"
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
+ "run nfsboot ; echo ; echo nfsboot failed ; " \
+ "usb start ;" \
+ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
+ "boot_file=uImage\0" \
+ "console=ttymxc0\0" \
+ "defargs=enable_wait_mode=off vmalloc=400M\0" \
+ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
+ EMMC_BOOTCMD \
+ "fdt_file=" FDT_FILE "\0" \
+ "fdt_fixup=;\0" \
+ MEM_LAYOUT_ENV_SETTINGS \
+ NFS_BOOTCMD \
+ SD_BOOTCMD \
+ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
+ "flash_eth.img && source ${loadaddr}\0" \
+ "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
+ "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+ "source ${loadaddr}\0" \
+ "setup=setenv setupargs fec_mac=${ethaddr} " \
+ "consoleblank=0 no_console_suspend=1 console=tty1 " \
+ "console=${console},${baudrate}n8\0 " \
+ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+ "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
+ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+ "source ${loadaddr}\0" \
+ "splashpos=m,m\0" \
+ "vidargs=mxc_hdmi.only_cea=1 " \
+ "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \
+ "video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
+ "fbmem=32M\0 "
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE 1024
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 48
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
+ CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 1
+#endif
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#define CONFIG_CMD_TIME
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_CRC32_VERIFY
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 8c76605..12a2877 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2015 Marcel Ziswiler
+ * Copyright (c) 2014-2016 Marcel Ziswiler
*
* Configuration settings for the Toradex Apalis T30 modules.
*
@@ -16,7 +16,7 @@
#define CONFIG_ARCH_MISC_INIT
/* High-level configuration options */
-#define CONFIG_TEGRA_BOARD_STRING "Toradex Apalis T30"
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
@@ -28,23 +28,21 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC support */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
-/* Environment in eMMC, at the end of 2nd "boot sector" */
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
+ CONFIG_TDX_CFG_BLOCK_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_SYS_MMC_ENV_PART 1
/* USB host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* PCI host support */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
/* PCI networking support */
@@ -52,7 +50,7 @@
/* General networking support */
#define CONFIG_IP_DEFRAG
-#define CONFIG_TFTP_BLOCKSIZE 16384
+#define CONFIG_TFTP_BLOCKSIZE 16352
#define CONFIG_TFTP_TSIZE
/* Miscellaneous commands */
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index e84cfb5..e9d8232 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -11,7 +11,6 @@
#define __CONFIG_H
#define CONFIG_ENV_VERSION 10
-#define CONFIG_IDENT_STRING " apf27 patch 3.10"
#define CONFIG_BOARD_NAME apf27
/*
@@ -26,22 +25,14 @@
#define CONFIG_SYS_NO_FLASH
/*
- * Board display option
- */
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_CPUINFO
-
-/*
* SPL
*/
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 2048
#define CONFIG_SPL_TEXT_BASE 0xA0000000
-#define CONFIG_SPL_SERIAL_SUPPORT
/* NAND boot config */
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
@@ -72,7 +63,6 @@
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
/*
@@ -318,7 +308,6 @@
* SD/MMC
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MXC_MMC
#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
index 92fea87..babaf26 100644
--- a/include/configs/apx4devkit.h
+++ b/include/configs/apx4devkit.h
@@ -21,7 +21,6 @@
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_DATE
@@ -57,7 +56,6 @@
/* UBI and NAND partitioning */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_RBTREE
diff --git a/include/configs/aria.h b/include/configs/aria.h
index cb50658..f385852 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -13,7 +13,6 @@
#define __CONFIG_H
#define CONFIG_ARIA 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the ARIA board:
@@ -38,12 +37,6 @@
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
/* video */
-#undef CONFIG_VIDEO
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#endif
/* CONFIG_PCI is defined at config time */
@@ -344,8 +337,6 @@
#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index 6dc419e..56530fd 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -57,7 +57,7 @@
"rescue_sys_length=f10000\0" \
"panel=lb07wv8\0" \
"splashpos=m,m\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV "\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
@@ -223,23 +223,14 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_RBTREE
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_FASTMAP
-#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1
-
#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG
/* Framebuffer */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
/* check this console not needed, after test remove it */
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h
index be93deb..1799cc1 100644
--- a/include/configs/aristainetos.h
+++ b/include/configs/aristainetos.h
@@ -18,7 +18,7 @@
#define CONFIG_BOARDNAME "aristainetos"
#define CONFIG_MXC_UART_BASE UART5_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc4"
+#define CONSOLE_DEV "ttymxc4"
#define CONFIG_FEC_XCV_TYPE RMII
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 152f5e9..8fa3eb5 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -19,7 +19,7 @@
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc1"
+#define CONSOLE_DEV "ttymxc1"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_PHY_MICREL_KSZ9031
diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h
index 78791db..df9b5c9 100644
--- a/include/configs/aristainetos2b.h
+++ b/include/configs/aristainetos2b.h
@@ -19,7 +19,7 @@
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc1"
+#define CONSOLE_DEV "ttymxc1"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_PHY_MICREL_KSZ9031
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index e3f4a7b..3775a49 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -27,11 +27,7 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_DCACHE_OFF
@@ -60,9 +56,6 @@
#define SCIF2_BASE 0xe6c60000
#define SCIF4_BASE 0xe6c80000
#define CONFIG_SCIF_A
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index b08f341..74fd9c4 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -27,8 +27,6 @@
/* Miscellaneous configurable options */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
-#define CONFIG_IDENT_STRING " for ARNDALE"
-
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h
index c468484..0cc72ca 100644
--- a/include/configs/aspenite.h
+++ b/include/configs/aspenite.h
@@ -11,11 +11,6 @@
#define __CONFIG_ASPENITE_H
/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-Aspenite DB"
-
-/*
* High Level Configuration Options
*/
#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 051186d..13140ba 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -25,7 +25,6 @@
#endif
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_ENV_VARS_UBOOT_CONFIG
@@ -75,7 +74,7 @@
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 earlyprintk " \
"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
- "256K(env),256k(env_redundent),256k(spare)," \
+ "256K(env),256k(env_redundant),256k(spare)," \
"512k(dtb),6M(kernel)ro,-(rootfs) " \
"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 3cc8d89..ed0daf5 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -144,7 +144,6 @@
#define CONFIG_USB_ATMEL 1
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_KEYBOARD 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index fab0374..f07366e 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -43,7 +43,6 @@
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
@@ -147,7 +146,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 867bd69..cc37236 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -29,8 +29,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_ATMEL_LEGACY
#define CONFIG_SYS_TEXT_BASE 0x21f00000
@@ -49,7 +47,6 @@
#define CONFIG_BAUDRATE 115200
/* LCD */
-#define CONFIG_LCD
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO
#undef LCD_TEST_PATTERN
@@ -61,8 +58,6 @@
#define CONFIG_ATMEL_LCD_BGR555
#endif
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
/* LED */
#define CONFIG_AT91_LED
#define CONFIG_RED_LED AT91_PIN_PA23 /* this is the power led */
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 854caf3..6806cc7 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -43,8 +43,6 @@
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
-
/*
* Hardware drivers
*/
@@ -59,7 +57,6 @@
#define CONFIG_BAUDRATE 115200
/* LCD */
-#define CONFIG_LCD 1
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO 1
#undef LCD_TEST_PATTERN
@@ -68,7 +65,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK 1
#define CONFIG_ATMEL_LCD 1
#define CONFIG_ATMEL_LCD_BGR555 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* LED */
#define CONFIG_AT91_LED
@@ -109,7 +105,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 37fa3ec..12a92c2 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -28,7 +28,6 @@
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
@@ -41,7 +40,6 @@
#define CONFIG_USART_ID ATMEL_ID_SYS
/* LCD */
-#define CONFIG_LCD
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO
#undef LCD_TEST_PATTERN
@@ -50,7 +48,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_LCD
#define CONFIG_ATMEL_LCD_RGB565
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* board specific(not enough SRAM) */
#define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
@@ -102,7 +99,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
@@ -186,11 +182,6 @@
#define CONFIG_SPL_MAX_SIZE 0x010000
#define CONFIG_SPL_STACK 0x310000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-
#define CONFIG_SYS_MONITOR_LEN 0x80000
#ifdef CONFIG_SYS_USE_MMC
@@ -201,16 +192,10 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_ECC
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 5fdda1a..9c9e809 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -28,7 +28,6 @@
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_AT91_GPIO
@@ -40,7 +39,6 @@
#define CONFIG_BAUDRATE 115200
/* LCD */
-#define CONFIG_LCD
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 24
#define CONFIG_LCD_LOGO
@@ -49,7 +47,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
@@ -126,7 +123,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
@@ -230,11 +226,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
@@ -245,16 +236,10 @@
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
@@ -267,8 +252,6 @@
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SPIFLASH
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index a383de6..b5aebe6 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -29,8 +29,6 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_ATMEL_LEGACY
#define CONFIG_AT91_GPIO 1
#define CONFIG_AT91_GPIO_PULLUP 1
@@ -46,7 +44,6 @@
#define CONFIG_BAUDRATE 115200
/* LCD */
-#define CONFIG_LCD 1
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO 1
#undef LCD_TEST_PATTERN
@@ -57,7 +54,6 @@
#define CONFIG_ATMEL_LCD_RGB565 1
/* Let board_init_f handle the framebuffer allocation */
#undef CONFIG_FB_ADDR
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* LED */
#define CONFIG_AT91_LED
@@ -110,7 +106,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_DOS_PARTITION
@@ -152,7 +147,7 @@
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 earlyprintk " \
"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
- "256K(env),256k(env_redundent),256k(spare)," \
+ "256K(env),256k(env_redundant),256k(spare)," \
"512k(dtb),6M(kernel)ro,-(rootfs) " \
"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 637c403..6dee45a 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -24,7 +24,6 @@
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
@@ -36,7 +35,6 @@
#define CONFIG_USART_ID ATMEL_ID_SYS
/* LCD */
-#define CONFIG_LCD
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 24
#define CONFIG_LCD_LOGO
@@ -45,7 +43,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
@@ -109,13 +106,11 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_LZO
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#endif
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
@@ -230,11 +225,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
@@ -245,16 +235,10 @@
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
@@ -267,8 +251,6 @@
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SPIFLASH
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index a0f451b..00a8c79 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -86,7 +86,6 @@
#define CONFIG_PORTMUX_PIO
#define CONFIG_SYS_NR_PIOS 5
#define CONFIG_SYS_HSDRAMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index 4d9282a..d1f61b3 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -105,7 +105,6 @@
#define CONFIG_PORTMUX_PIO
#define CONFIG_SYS_NR_PIOS 5
#define CONFIG_SYS_HSDRAMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 9ddfff2..3d17ae1 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -107,7 +107,6 @@
#define CONFIG_PORTMUX_PIO
#define CONFIG_SYS_NR_PIOS 5
#define CONFIG_SYS_HSDRAMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_GENERIC_MMC
diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h
index b99248e..296fbd1 100644
--- a/include/configs/axs10x.h
+++ b/include/configs/axs10x.h
@@ -85,7 +85,6 @@
/*
* SD/MMC configuration
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index fc56c82..06f5ceb 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -48,14 +48,12 @@
#define CONFIG_MTD_DEVICE
#define CONFIG_RBTREE
#define CONFIG_LZO
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
/* I2C configuration */
#undef CONFIG_SYS_OMAP24_I2C_SPEED
#define CONFIG_SYS_OMAP24_I2C_SPEED 1000
-#undef CONFIG_SPL_OS_BOOT
#ifdef CONFIG_NAND
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00080000
#ifdef CONFIG_SPL_OS_BOOT
@@ -104,7 +102,9 @@
"optargs=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 ro\0" \
+ "usbroot=/dev/sda2 ro\0" \
"mmcrootfstype=ext4 rootwait\0" \
+ "usbrootfstype=ext4 rootwait\0" \
"rootpath=/export/rootfs\0" \
"nfsopts=nolock\0" \
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
@@ -116,6 +116,11 @@
"${mtdparts} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
+ "usbargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "${mtdparts} " \
+ "root=${usbroot} " \
+ "rootfstype=${usbrootfstype}\0" \
"spiroot=/dev/mtdblock4 rw\0" \
"spirootfstype=jffs2\0" \
"spisrcaddr=0xe0000\0" \
@@ -132,15 +137,25 @@
"ip=dhcp\0" \
"bootenv=uEnv.txt\0" \
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "usbloadbootenv=load usb 0:1 ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t $loadaddr $filesize\0" \
+ "usbimportbootenv=echo Importing environment from USB ...; " \
+ "env import -t $loadaddr $filesize\0" \
"ramargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${ramroot} " \
"rootfstype=${ramrootfstype}\0" \
"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "usbloadimage=load usb 0:1 ${loadaddr} kernel-fit.itb\0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "usbloados=run usbargs; " \
+ "bootm ${loadaddr}#conf${board_name}; " \
+ "if test $? -ne 0; then " \
+ "echo Using default FIT configuration; " \
+ "bootm ${loadaddr}; " \
+ "fi;\0" \
"mmcloados=run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
@@ -155,6 +170,21 @@
"else " \
"bootz; " \
"fi;\0" \
+ "usbboot=usb reset; " \
+ "if usb storage; then " \
+ "echo USB drive found;" \
+ "if run usbloadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run usbimportbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run usbloadimage; then " \
+ "run usbloados;" \
+ "fi;" \
+ "fi;\0" \
"mmcboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
@@ -192,6 +222,7 @@
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
+ "run usbboot;" \
"run mmcboot;" \
"setenv mmcdev 1; " \
"setenv bootpart 1:2; " \
@@ -217,22 +248,16 @@
/* SPL */
#ifndef CONFIG_NOR_BOOT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-
/* Bootcount using the RTC block */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_AM33XX
/* USB gadget RNDIS */
-/*#define CONFIG_SPL_MUSB_NEW_SUPPORT*/
/* General network SPL, both CPSW and USB gadget RNDIS */
-/*#define CONFIG_SPL_NET_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
@@ -291,7 +316,6 @@
/*
* Disable CPSW SPL support so we fit within the 101KiB limit.
*/
-#undef CONFIG_SPL_ETH_SUPPORT
#endif
/* Network. */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 6d97755..1b22a37 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -203,9 +203,7 @@
*-----------------------------------------------------------------------
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index d8a8c0c..2f51e2c 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -350,18 +350,14 @@
/* SPL */
#ifndef CONFIG_NOR_BOOT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-
/* Bootcount using the RTC block */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_AM33XX
#define CONFIG_SYS_BOOTCOUNT_BE
/* USB gadget RNDIS */
-#define CONFIG_SPL_MUSB_NEW_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#endif
#ifdef CONFIG_NAND
@@ -451,8 +447,6 @@
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
-/* To support eMMC booting */
-#define CONFIG_STORAGE_EMMC
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#endif
@@ -465,16 +459,10 @@
/* disable EFI partitions and partition UUID support */
#undef CONFIG_PARTITION_UUIDS
#undef CONFIG_EFI_PARTITION
-/* General network SPL */
-#define CONFIG_SPL_NET_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_NET_VCI_STRING "BAV335x U-Boot SPL"
#endif
/* USB Device Firmware Update support */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
#define DFU_ALT_INFO_MMC \
"dfu_alt_info_mmc=" \
"boot part 0 1;" \
@@ -489,7 +477,6 @@
"u-boot.img fat 0 1;" \
"uEnv.txt fat 0 1\0"
#ifdef CONFIG_NAND
-#define CONFIG_DFU_NAND
#define DFU_ALT_INFO_NAND \
"dfu_alt_info_nand=" \
"SPL part 0 1;" \
@@ -503,7 +490,6 @@
#else
#define DFU_ALT_INFO_NAND ""
#endif
-#define CONFIG_DFU_RAM
#define DFU_ALT_INFO_RAM \
"dfu_alt_info_ram=" \
"kernel ram 0x80200000 0xD80000;" \
@@ -527,9 +513,6 @@
*/
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
-#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
@@ -547,7 +530,6 @@
#elif defined(CONFIG_EMMC_BOOT)
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x0
diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h
index 8f31436..8926047 100644
--- a/include/configs/bayleybay.h
+++ b/include/configs/bayleybay.h
@@ -16,20 +16,15 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_PCI_PNP
-
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_MMC
-#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SDMA
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
index eb4c497..8f062e2 100644
--- a/include/configs/bcm23550_w1d.h
+++ b/include/configs/bcm23550_w1d.h
@@ -31,10 +31,6 @@
#define CONFIG_KONA_GPIO
/* MMC/SD Driver */
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-#define CONFIG_KONA_SDHCI
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index 7a75fdb..0882531 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -30,10 +30,6 @@
#define CONFIG_KONA_GPIO
/* MMC/SD Driver */
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-#define CONFIG_KONA_SDHCI
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index e5fda5c..2e43a09 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -28,7 +28,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -53,8 +52,6 @@
#define CONFIG_USB_ETHER_ASIX
/* PCI host support */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
/* General networking support */
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 510cd47..43e4971 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -129,7 +129,6 @@
*/
#if !defined(__ADSPBF512__)
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
#define CONFIG_BFIN_SDH
#endif
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index 258115a..40ca18d 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -115,7 +115,6 @@
/*
* SPI_MMC Settings
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index ddc4a25..d945b8d 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -134,9 +134,6 @@
#endif
/* Don't waste time transferring a logo over the UART */
-#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-/*# define CONFIG_VIDEO*/
-#endif
/*
* Video Settings
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index c2466ca..ec4d93c 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -204,7 +204,6 @@
#endif
/* define to enable splash screen support */
-/* #define CONFIG_VIDEO */
/*
* Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 4f861aa..6517705 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -125,7 +125,6 @@
*/
#define CONFIG_MMC_SPI
#ifdef CONFIG_MMC_SPI
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#endif
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 811dae8..b79aa2b 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -143,7 +143,6 @@
*/
#if !defined(__ADSPBF544__)
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
#define CONFIG_BFIN_SDH
#endif
@@ -167,7 +166,6 @@
#define CONFIG_ADI_GPIO2
-#undef CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
#define CONFIG_DEB_DMA_URGENT
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 4deb2d2..337bb0a 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -127,7 +127,6 @@
* SDH Settings
*/
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
#define CONFIG_BFIN_SDH
/*
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 502ddad..c401b73 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -78,7 +78,6 @@
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_LOADS_ECHO 1
#define CONFIG_JTAG_CONSOLE
-#define CONFIG_SILENT_CONSOLE
#ifndef CONFIG_BAUDRATE
# define CONFIG_BAUDRATE 57600
#endif
diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h
index e13f736..57a6985 100644
--- a/include/configs/bg0900.h
+++ b/include/configs/bg0900.h
@@ -11,7 +11,6 @@
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_NAND
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
new file mode 100644
index 0000000..5861eeb
--- /dev/null
+++ b/include/configs/bk4r1.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2016 3ADEV <http://3adev.com>
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Configuration settings for the phytec PCM-052 SoM-based BK4R1.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Define the BK4r1-specific env commands */
+#define PCM052_EXTRA_ENV_SETTINGS \
+ "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \
+ "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"
+
+/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/
+#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; "
+
+/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */
+#define PCM052_NET_INIT "run set_gpio122; "
+
+/* add NOR to MTD env */
+#define MTDIDS_DEFAULT "nand0=NAND,nor0=NOR"
+#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\
+ ",128k(env1)"\
+ ",128k(env2)"\
+ ",128k(dtb)"\
+ ",6144k(kernel)"\
+ ",-(root);"\
+ "NOR:-(nor)"
+
+/* now include standard PCM052 config */
+
+#include "configs/pcm052.h"
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
index f094bbe..0deb350 100755
--- a/include/configs/blanche.h
+++ b/include/configs/blanche.h
@@ -16,9 +16,6 @@
#include "rcar-gen2-common.h"
-#define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_USE_ARCH_MEMCPY
-
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC
#define STACK_AREA_SIZE 0xC000
diff --git a/include/configs/boston.h b/include/configs/boston.h
new file mode 100644
index 0000000..aad87c6
--- /dev/null
+++ b/include/configs/boston.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __CONFIGS_BOSTON_H__
+#define __CONFIGS_BOSTON_H__
+
+/*
+ * CPU
+ */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 30000000
+
+/*
+ * PCI
+ */
+#define CONFIG_CMD_PCI
+
+/*
+ * Memory map
+ */
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+#else
+# define CONFIG_SYS_SDRAM_BASE 0x80000000
+#endif
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000)
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
+
+/*
+ * Console
+ */
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Flash
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#ifdef CONFIG_64BIT
+# define CONFIG_ENV_ADDR \
+ (0xffffffffb8000000 + (128 << 20) - CONFIG_ENV_SIZE)
+#else
+# define CONFIG_ENV_ADDR \
+ (0xb8000000 + (128 << 20) - CONFIG_ENV_SIZE)
+#endif
+
+#endif /* __CONFIGS_BOSTON_H__ */
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
index 6a239b5..eb2419c 100644
--- a/include/configs/brppt1.h
+++ b/include/configs/brppt1.h
@@ -16,7 +16,6 @@
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
#define CONFIG_AM335X_LCD
-#define CONFIG_LCD
#define CONFIG_LCD_ROTATION
#define CONFIG_LCD_DT_SIMPLEFB
#define CONFIG_SYS_WHITE_ON_BLACK
@@ -24,9 +23,7 @@
#define CONFIG_HW_WATCHDOG
#define CONFIG_OMAP_WATCHDOG
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
/* Bootcount using the RTC block */
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
#define CONFIG_BOOTCOUNT_LIMIT
@@ -51,14 +48,9 @@
/* MMC/SD IP block */
#if defined(CONFIG_EMMC_BOOT)
- #define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_SUPPORT_EMMC_BOOT
-/* RAW SD card / eMMC locations. */
- #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
- #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
- #define CONFIG_SPL_MMC_SUPPORT
#endif /* CONFIG_EMMC_BOOT */
/*
@@ -71,7 +63,6 @@
#define CONFIG_CMD_MTDPARTS
#endif /* CONFIG_SPI_BOOT, ... */
-#undef CONFIG_SPL_OS_BOOT
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
@@ -90,7 +81,6 @@
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
@@ -257,8 +247,6 @@
#define CONFIG_OMAP3_SPI
#define CONFIG_SF_DEFAULT_SPEED 24000000
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#undef CONFIG_ENV_IS_NOWHERE
diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h
index 11f56bf..ac338c4 100644
--- a/include/configs/brxre1.h
+++ b/include/configs/brxre1.h
@@ -16,7 +16,6 @@
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
#define CONFIG_AM335X_LCD
-#define CONFIG_LCD
#define CONFIG_LCD_NOSTDOUT
#define CONFIG_SYS_WHITE_ON_BLACK
#define LCD_BPP LCD_COLOR32
@@ -42,17 +41,11 @@
#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000
/* GPIO */
-#define CONFIG_SPL_GPIO_SUPPORT
/* MMC/SD IP block */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_SUPPORT_EMMC_BOOT
-/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SPL_MMC_SUPPORT
/* Always 64 KiB env size */
#define CONFIG_ENV_SIZE (64 << 10)
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 51d4624..c989023 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -134,10 +134,8 @@
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 1de5edc..7afffa2 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -14,14 +14,12 @@
/* ------------------------------------------------------------------------- */
#define CONFIG_AM33XX
#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */
-#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_POWER_TPS65217
#define CONFIG_SYS_NO_FLASH /* have no NOR-flash */
@@ -113,12 +111,7 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
/* General parts of the framework, required. */
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_YMODEM_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#endif /* ! __BUR_AM335X_COMMON_H__ */
diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h
index 85510f0..5c99860 100644
--- a/include/configs/bur_cfg_common.h
+++ b/include/configs/bur_cfg_common.h
@@ -39,10 +39,7 @@
#define CONFIG_NETCONSOLE 1
#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
/* As stated above, the following choices are optional. */
#define CONFIG_SYS_LONGHELP
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index bf173ff..dab4ec2 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -32,8 +32,6 @@
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_DA850_LOWLEVEL
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_HW_WATCHDOG
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index b416660..684695f 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -15,7 +15,6 @@
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* allowed and functional CONFIG_SYS_TEXT_BASE values:
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index aac36b1..1d189d2 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -404,9 +404,7 @@
* PCI stuff
*----------------------------------------------------------------------*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 5943b04..b7df2bc 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -31,7 +31,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -56,8 +55,6 @@
#define CONFIG_USB_ETHER_ASIX
/* PCI host support */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
/* General networking support */
diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h
index aebb10a..6eed4bc 100644
--- a/include/configs/cei-tk1-som.h
+++ b/include/configs/cei-tk1-som.h
@@ -30,7 +30,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -54,8 +53,6 @@
#define CONFIG_USB_ETHER_ASIX
/* PCI host support */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
/* General networking support */
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 9a0469d..bccfedf 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -18,10 +18,6 @@
#define CONFIG_MACH_TYPE 4122
#ifdef CONFIG_SPL
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#define CONFIG_SPL_SPI_LOAD
#include "imx6_spl.h"
@@ -78,18 +74,12 @@
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
-#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
#define CONFIG_USBD_HS
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
-#define CONFIG_DFU_SF
-
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
@@ -97,12 +87,7 @@
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
/* Framebuffer */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
@@ -138,7 +123,7 @@
/* Command definition */
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc1"
+#define CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define CONFIG_SYS_MMC_ENV_DEV 0
@@ -150,7 +135,7 @@
"fdt_addr_r=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV "\0" \
"dfuspi=dfu 0 sf 0:0:10000000:0\0" \
"dfu_alt_info_spl=spl raw 0x400\0" \
"dfu_alt_info_img=u-boot raw 0x10000\0" \
diff --git a/include/configs/chromebook_jerry.h b/include/configs/chromebook_jerry.h
deleted file mode 100644
index d1f5b46..0000000
--- a/include/configs/chromebook_jerry.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define ROCKCHIP_DEVICE_SETTINGS \
- "stdin=serial,cros-ec-keyb\0" \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
-
-#include <configs/rk3288_common.h>
-
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPI_FLASH_GIGADEVICE
-
-#define CONFIG_CMD_SF_TEST
-
-#undef CONFIG_SPL_GPIO_SUPPORT
-
-#define CONFIG_KEYBOARD
-
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-
-#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
-
-#endif
diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h
index b89ba41..1234bff 100644
--- a/include/configs/chromebook_samus.h
+++ b/include/configs/chromebook_samus.h
@@ -16,8 +16,6 @@
#include <configs/x86-common.h>
#include <configs/x86-chromebook.h>
-#undef CONFIG_CFB_CONSOLE
-
#undef CONFIG_STD_DEVICES_SETTINGS
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
"stdout=vidconsole,serial\0" \
diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h
new file mode 100644
index 0000000..8297182
--- /dev/null
+++ b/include/configs/cl-som-am57x.h
@@ -0,0 +1,197 @@
+/*
+ * Configuration settings for CompuLab CL-SOM-AM57x board
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_CL_SOM_AM57X_H
+#define __CONFIG_CL_SOM_AM57X_H
+
+#define CONFIG_DRA7XX
+
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONSOLEDEV "ttyO2"
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+
+#include <configs/ti_omap5_common.h>
+
+/* misc */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_REVISION_TAG
+
+/* Status LED */
+#define CONFIG_STATUS_LED /* Status LED enabled */
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define GREEN_LED_DEV 0
+ /* cl_som_am57x Green LED is GPIO2_5 */
+#define GREEN_LED_GPIO 37
+#define STATUS_LED_BIT GREEN_LED_GPIO
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+
+/* PMIC I2C bus number */
+#define CONFIG_SYS_SPD_BUS_NUM 3
+
+/* SPI Flash support */
+#undef CONFIG_OMAP3_SPI
+
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_SF_DEFAULT_SPEED 48000000
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
+
+/* SPI SPL defines */
+/* Offsets: 0K - SPL1, 64K - SPL2, 128K - SPL3, 192K - SPL4, 256K - U-Boot */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+
+/* SD/MMC RAW boot */
+#undef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+#undef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
+
+/* Environment */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB env size */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_OFFSET (768 * 1024)
+#define CONFIG_ENV_SPI_MAX_HZ 48000000
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_BUS 3
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_EEPROM_SIZE 256
+
+#ifndef CONFIG_SPL_BUILD
+/* SATA */
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+/* PCA9555 GPIO expander support */
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
+#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
+
+/* GPT */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
+/* USB xHCI HOST */
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB3PHY1_HOST
+
+/* USB Networking options */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_RNDIS
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+
+/* CPSW Ethernet */
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_PHYLIB
+#define CONFIG_SYS_RX_ETH_BUFFER 64
+#define PHY_ANEG_TIMEOUT 8000
+
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+
+#endif /* !CONFIG_SPL_BUILD */
+
+/* Default environment */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ "autoload=no\0" \
+ "baudrate=115200\0" \
+ "console=ttyO2,115200n8\0" \
+ "bootdelay=3\0" \
+ "fdtfile=am57xx-sbc-am57x.dtb\0" \
+ "kernel=zImage-cl-som-am57x\0" \
+ "bootscr=bootscr.img\0" \
+ "displaytype=hdmi\0" \
+ "bootkernel=bootz ${loadaddr} - ${fdtaddr}\0" \
+ "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+ "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
+ "load_mmc=mmc dev ${mmcdev} && mmc rescan && " \
+ "run mmcloadkernel run mmcloadfdt\0" \
+ "mmcroot=/dev/mmcblk1p2\0" \
+ "mmcrootfstype=ext4 rw rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "mmcbootscript=setenv mmcdev 0; mmc dev ${mmcdev} && mmc rescan && " \
+ "load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \
+ "echo Running bootscript from MMC/SD Card ... && " \
+ "source ${loadaddr}\0" \
+ "mmcboot=setenv mmcdev 0 && run load_mmc && " \
+ "run mmcargs && echo Booting from MMC/SD Card ... && " \
+ "run bootkernel\0" \
+ "emmcroot=/dev/mmcblk0p2\0" \
+ "emmcrootfstype=ext4 rw rootwait\0" \
+ "emmcargs=setenv bootargs console=${console} " \
+ "root=${emmcroot} " \
+ "rootfstype=${emmcrootfstype}\0" \
+ "emmcbootscript=setenv mmcdev 1; mmc dev ${mmcdev} && mmc rescan && " \
+ "load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \
+ "echo Running bootscript from eMMC ... && " \
+ "source ${loadaddr}\0" \
+ "emmcboot=setenv mmcdev 1 && run load_mmc && " \
+ "run emmcargs && echo Booting from eMMC ... && " \
+ "run bootkernel\0" \
+ "sataroot=/dev/sda2\0" \
+ "satarootfstype=ext4 rw rootwait\0" \
+ "load_sata=load scsi 0 ${loadaddr} ${kernel} && " \
+ "load scsi 0 ${fdtaddr} ${fdtfile}\0" \
+ "sataargs=setenv bootargs console=${console} " \
+ "root=${sataroot} " \
+ "rootfstype=${satarootfstype}\0" \
+ "satabootscript=load scsi 0 ${loadaddr} ${bootscr} && " \
+ "echo Running bootscript from SATA ... && " \
+ "source ${loadaddr}\0" \
+ "sataboot=run load_sata && run sataargs && " \
+ "echo Booting from SATA ... && " \
+ "run bootkernel\0" \
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+ "run mmcbootscript || run mmcboot || " \
+ "run satabootscript || run sataboot || " \
+ "run emmcbootscript || run emmcboot"
+
+
+#endif /* __CONFIG_CL_SOM_AM57X_H */
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
index 6cbdee2..e520b1a 100644
--- a/include/configs/clearfog.h
+++ b/include/configs/clearfog.h
@@ -43,11 +43,7 @@
/*
* SDIO/MMC Card Configuration
*/
-#define CONFIG_MMC
-#define CONFIG_MMC_SDMA
#define CONFIG_GENERIC_MMC
-#define CONFIG_SDHCI
-#define CONFIG_MV_SDHCI
#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
/* Partition support */
@@ -81,13 +77,10 @@
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
/* Keep device tree and initrd in lower memory so the kernel can access them */
@@ -123,15 +116,8 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
@@ -139,13 +125,8 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR ((CONFIG_SYS_U_BOOT_OFFS / 512)\
- + 1)
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 78841cd..32229d2 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -118,7 +118,6 @@
/*
* SPI_MMC Settings
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 5785ebd..dc2eabd 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -116,7 +116,6 @@
/*
* SPI_MMC Settings
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index d1aa262..c5b82f7 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -113,7 +113,6 @@
#ifndef __ADSPBF542__
/* Don't waste time transferring a logo over the UART */
# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-# define CONFIG_VIDEO
# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
# endif
# define CONFIG_DEB_DMA_URGENT
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 065e700..b65ca3e 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -8,8 +8,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -35,7 +33,6 @@
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
/*
* Ethernet configuration
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index c839b03..0dad9c3 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -56,7 +56,6 @@
/* MTD support */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_FDT_FIXUP_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SPI_FLASH_MTD
@@ -211,7 +210,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_SYS_STDIO_DEREGISTER
/* I2C */
#define CONFIG_SYS_I2C
@@ -242,29 +240,17 @@
/* misc */
#define CONFIG_STACKSIZE (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
#define CONFIG_MISC_INIT_R
/* SPL */
#include "imx6_spl.h"
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */
-#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#define CONFIG_SPL_SPI_LOAD
/* Display */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SOURCE
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index 6dbc9e9..8f24174 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -19,15 +19,12 @@
#undef CONFIG_BOARD_LATE_INIT
#undef CONFIG_SPI
#undef CONFIG_OMAP3_SPI
-#undef CONFIG_SPL_OS_BOOT
#undef CONFIG_BOOTCOUNT_LIMIT
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#undef CONFIG_MAX_RAM_BANK_SIZE
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
-#define CONFIG_OMAP_COMMON
-
#define MACH_TYPE_CM_T335 4586 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335
@@ -105,7 +102,7 @@
#define CONFIG_SYS_I2C_EEPROM_BUS 0
/* SPL */
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
/* Network. */
#define CONFIG_PHY_GIGE
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 562ba56..1ce27e3 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -25,7 +25,6 @@
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
-#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
@@ -36,12 +35,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -88,7 +81,6 @@
115200}
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
@@ -102,7 +94,6 @@
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* commands to include */
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
@@ -287,7 +278,6 @@
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP LCD_COLOR16
-#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SOURCE
#define CONFIG_CMD_BMP
@@ -300,27 +290,15 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index a408fbf..bae9697 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -15,7 +15,6 @@
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_CM_T3517 /* working with CM-T3517 */
-#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
@@ -36,12 +35,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -85,7 +78,6 @@
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -96,7 +88,6 @@
#define CONFIG_OMAP_GPIO
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
@@ -288,7 +279,6 @@
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP LCD_COLOR16
-#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASHIMAGE_GUARD
#define CONFIG_CMD_BMP
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 45fa37a..9c24ba9 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -90,11 +90,7 @@
#define CONFIG_HSMMC2_8BIT
#include <configs/ti_armv7_omap.h>
-#undef CONFIG_SPL_OS_BOOT
-#undef CONFIG_SPL_GPIO_SUPPORT
-#undef CONFIG_SPL_NAND_SUPPORT
#undef CONFIG_SYS_MONITOR_LEN
-#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -107,7 +103,7 @@
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SPI_MAX_HZ 48000000
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
@@ -153,15 +149,9 @@
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
-#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x480
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
/* EEPROM */
#define CONFIG_CMD_EEPROM
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index 6b51b43..952538d 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -16,8 +16,6 @@
#include <configs/ti_omap5_common.h>
-#undef CONFIG_SPL_OS_BOOT
-
/* EEPROM related defines */
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
@@ -32,13 +30,6 @@
#define CONFIG_SYS_NS16550_COM4 UART4_BASE
#define CONFIG_BAUDRATE 115200
-/* SD/MMC RAW boot */
-#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
-#undef CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* 0x40000 - 256 KB */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 /* 384 KB */
-
/* MMC ENV related defines */
#undef CONFIG_ENV_OFFSET
#undef CONFIG_ENV_SIZE
@@ -56,7 +47,6 @@
#define CONFIG_SUPPORT_EMMC_BOOT
/* SATA Boot related defines */
-#define CONFIG_SPL_SATA_SUPPORT
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
new file mode 100644
index 0000000..b05fca6
--- /dev/null
+++ b/include/configs/colibri_imx6.h
@@ -0,0 +1,304 @@
+/*
+ * Copyright 2013-2015 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex Colibri iMX6
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_SYS_THUMB_BUILD
+
+#undef CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#define CONFIG_SPL_PAD_TO 0x11000 /* 4k IVT/DCD, 64k SPL */
+#endif
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* Make the HW version stuff available in U-Boot env */
+#define CONFIG_VERSION_VARIABLE /* ver environment variable */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* OCOTP Configs */
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE 16352
+#define CONFIG_TFTP_TSIZE
+
+/* USB Configs */
+/* Host */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_KEYBOARD
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#endif /* CONFIG_USB_KEYBOARD */
+/* Client */
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_G_DNL_MANUFACTURER "Toradex"
+/* USB DFU */
+#define CONFIG_DFU_MMC
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_MXC_GPIO
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_CMD_BMP
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FLASH
+
+#undef CONFIG_IPADDR
+#define CONFIG_IPADDR 192.168.10.2
+#define CONFIG_NETMASK 255.255.255.0
+#undef CONFIG_SERVERIP
+#define CONFIG_SERVERIP 192.168.10.1
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_DRIVE_MMC "mmc "
+#else
+#define CONFIG_DRIVE_MMC
+#endif
+
+#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC
+
+#define DFU_ALT_EMMC_INFO \
+ "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "uImage fat 0 1;" \
+ "imx6q-colibri-eval-v3.dtb fat 0 1;" \
+ "imx6q-colibri-cam-eval-v3.dtb fat 0 1"
+
+#define EMMC_BOOTCMD \
+ "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "emmcboot=run setup; " \
+ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
+ "${vidargs}; echo Booting from internal eMMC chip...; " \
+ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x12000000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "kernel_addr_r=0x11000000\0" \
+ "ramdisk_addr_r=0x12100000\0"
+
+#define NFS_BOOTCMD \
+ "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
+ "nfsboot=run setup; " \
+ "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
+ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
+ "run nfsdtbload; dhcp ${kernel_addr_r} " \
+ "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
+ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define SD_BOOTCMD \
+ "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "sdboot=run setup; " \
+ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
+ "${vidargs}; echo Booting from SD card; " \
+ "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define USB_BOOTCMD \
+ "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
+ "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
+ "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
+ "run nfsboot ; echo ; echo nfsboot failed ; " \
+ "usb start ;" \
+ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
+ "boot_file=uImage\0" \
+ "console=ttymxc0\0" \
+ "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \
+ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
+ EMMC_BOOTCMD \
+ "fdt_file=" FDT_FILE "\0" \
+ "fdt_fixup=;\0" \
+ MEM_LAYOUT_ENV_SETTINGS \
+ NFS_BOOTCMD \
+ SD_BOOTCMD \
+ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
+ "flash_eth.img && source ${loadaddr}\0" \
+ "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
+ "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+ "source ${loadaddr}\0" \
+ "setup=setenv setupargs fec_mac=${ethaddr} " \
+ "consoleblank=0 no_console_suspend=1 console=tty1 " \
+ "console=${console},${baudrate}n8\0 " \
+ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+ "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
+ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+ "source ${loadaddr}\0" \
+ "splashpos=m,m\0" \
+ "vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \
+ "video=mxcfb1:off fbmem=8M\0 "
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE 1024
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 48
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
+ CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 1
+#endif
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#define CONFIG_CMD_TIME
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_CRC32_VERIFY
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 2ec392e..bc3b53b 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -15,24 +15,22 @@
#include "mx7_common.h"
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
/*#define CONFIG_DBG_MONITOR*/
#define PHYS_SDRAM_SIZE SZ_512M
+#define CONFIG_ARCH_MISC_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-/* Uncomment to enable secure boot support */
-/* #define CONFIG_SECURE_BOOT */
-#define CONFIG_CSF_SIZE 0x4000
-
#define CONFIG_CMD_BMODE
/* Network */
@@ -44,9 +42,9 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
-#define CONFIG_TFTP_TSIZE
#define CONFIG_IP_DEFRAG
-#define CONFIG_TFTP_BLOCKSIZE 16384
+#define CONFIG_TFTP_BLOCKSIZE 16352
+#define CONFIG_TFTP_TSIZE
/* ENET1 */
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
@@ -59,9 +57,7 @@
#undef CONFIG_BOOTM_RTEMS
/* I2C configs */
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_IPADDR 192.168.10.2
@@ -188,8 +184,6 @@
/* UBI stuff */
#define CONFIG_RBTREE
#define CONFIG_LZO
-#define CONFIG_CMD_UBI
-#define CONFIG_MTD_UBI_FASTMAP
#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */
/* Dynamic MTD partition support */
@@ -222,19 +216,12 @@
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_CMD_BMP
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index ba8d93c..51f7877 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -2,7 +2,7 @@
* Toradex Colibri PXA270 configuration file
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
+ * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -21,10 +21,14 @@
/* We will never enable dcache because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
+
/*
* Environment settings
*/
#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
@@ -39,14 +43,10 @@
#define CONFIG_TIMESTAMP
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_LZMA /* LZMA compression support */
/*
* Serial Console Configuration
*/
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
/*
@@ -67,7 +67,6 @@
#define CONFIG_PXA_LCD
#define CONFIG_PXA_VGA
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#define CONFIG_CMD_BMP
#define CONFIG_LCD_LOGO
#endif
@@ -96,8 +95,8 @@
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_DEVICE_NULLDEV 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE 1
+#undef CONFIG_CMDLINE_EDITING /* Saves 2.5 KB */
+#undef CONFIG_AUTO_COMPLETE /* Saves 2.5 KB */
/*
* Clock Configuration
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index d9954c1..e9db97f 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -14,7 +14,7 @@
#define CONFIG_ARCH_MISC_INIT
/* High-level configuration options */
-#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20"
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
@@ -27,7 +27,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC support */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -47,7 +46,6 @@
/* LCD support */
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#define CONFIG_CMD_BMP
#define CONFIG_LCD_LOGO
@@ -74,10 +72,8 @@
#define CONFIG_ENV_SIZE (SZ_64K)
/* UBI */
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */
#define CONFIG_LZO
-#define CONFIG_MTD_UBI_FASTMAP
#define CONFIG_RBTREE
/* Debug commands */
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index fbb235d..4d13856 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015 Stefan Agner
+ * Copyright (c) 2013-2016 Stefan Agner
*
* Configuration settings for the Toradex Colibri T30 modules.
*
@@ -16,7 +16,7 @@
#define CONFIG_ARCH_MISC_INIT
/* High-level configuration options */
-#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30"
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
@@ -28,15 +28,15 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC support */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
-/* Environment in eMMC, at the end of 2nd "boot sector" */
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
+ CONFIG_TDX_CFG_BLOCK_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_SYS_MMC_ENV_PART 1
/* USB host support */
#define CONFIG_USB_EHCI
@@ -48,7 +48,7 @@
/* General networking support */
#define CONFIG_IP_DEFRAG
-#define CONFIG_TFTP_BLOCKSIZE 16384
+#define CONFIG_TFTP_BLOCKSIZE 16352
#define CONFIG_TFTP_TSIZE
/* Miscellaneous commands */
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index d3e4523..4cfd5b9 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -1,7 +1,7 @@
/*
- * Copyright 2015 Toradex, Inc.
+ * Copyright 2015-2016 Toradex, Inc.
*
- * Configuration settings for the Toradex VF50/VF61 module.
+ * Configuration settings for the Toradex VF50/VF61 modules.
*
* Based on vf610twr.h:
* Copyright 2013 Freescale Semiconductor, Inc.
@@ -16,13 +16,10 @@
#define CONFIG_VF610
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_SYS_FSL_CLK
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
#define CONFIG_SKIP_LOWLEVEL_INIT
@@ -38,6 +35,7 @@
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_BAUDRATE 115200
@@ -58,20 +56,15 @@
"512k(u-boot-env)," \
"-(ubi)"
-#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_RBTREE
#define CONFIG_LZO
-#define CONFIG_CMD_UBI
-#define CONFIG_MTD_UBI_FASTMAP
#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */
#define CONFIG_FEC_MXC
@@ -101,7 +94,7 @@
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
@@ -110,7 +103,7 @@
"${setupargs} ${vidargs}; echo Booting from NFS...;" \
"dhcp ${kernel_addr_r} && " \
"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
@@ -118,10 +111,10 @@
"ubiboot=run setup; " \
"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \
"${setupargs} ${vidargs}; echo Booting from NAND...; " \
- "ubi part ubi && ubifsmount ubi0:rootfs && " \
- "ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \
- "ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "ubi part ubi && " \
+ "ubi read ${kernel_addr_r} kernel && " \
+ "ubi read ${fdt_addr_r} dtb && " \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
@@ -133,6 +126,7 @@
"kernel_file=zImage\0" \
"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
"fdt_board=eval-v3\0" \
+ "fdt_fixup=;\0" \
"defargs=\0" \
"console=ttyLP0\0" \
"setup=setenv setupargs " \
@@ -210,17 +204,7 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-/* USB Client Support */
-#define CONFIG_TRDX_VID 0x1B67
-#define CONFIG_TRDX_PID_COLIBRI_VF50 0x0016
-#define CONFIG_TRDX_PID_COLIBRI_VF61 0x0017
-#define CONFIG_TRDX_PID_COLIBRI_VF61IT 0x0018
-#define CONFIG_TRDX_PID_COLIBRI_VF50IT 0x0019
-
/* USB DFU */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_NAND
-#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024)
/* USB Storage */
diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h
index 652e073..b28a1f2 100644
--- a/include/configs/conga-qeval20-qa3-e3845.h
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -19,8 +19,6 @@
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_PCI_PNP
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
@@ -29,10 +27,7 @@
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_MMC
-#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SDMA
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 29189a4..1736097 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -35,21 +35,11 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_P1022
#define CONFIG_CONTROLCENTERD
#define CONFIG_MP /* support multiple processors */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
-#ifdef CONFIG_TRAILBLAZER
-#define CONFIG_IDENT_STRING " controlcenterd trailblazer 0.01"
-#else
-#define CONFIG_IDENT_STRING " controlcenterd 0.01"
-#endif
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP
@@ -132,8 +122,6 @@
#define CONFIG_SYS_SDRAM_SIZE 1024
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_FSL_DDR3
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -218,7 +206,6 @@
/*
* MMC
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
@@ -231,19 +218,14 @@
*/
#define CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CMD_BMP
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_CMD_PCI
@@ -346,8 +328,6 @@
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
/*
* Command line configuration.
*/
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c598300..c9c00c5 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -10,8 +10,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_RAMBOOT_PBL
@@ -26,13 +24,13 @@
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
-#if defined(CONFIG_P3041DS)
+#if defined(CONFIG_TARGET_P3041DS)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
-#elif defined(CONFIG_P4080DS)
+#elif defined(CONFIG_TARGET_P4080DS)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
-#elif defined(CONFIG_P5020DS)
+#elif defined(CONFIG_TARGET_P5020DS)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
-#elif defined(CONFIG_P5040DS)
+#elif defined(CONFIG_TARGET_P5040DS)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
#endif
#endif
@@ -48,9 +46,6 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
@@ -63,17 +58,14 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
@@ -184,7 +176,6 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
@@ -557,7 +548,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
@@ -684,7 +674,7 @@
#define CONFIG_BAUDRATE 115200
-#ifdef CONFIG_P4080DS
+#ifdef CONFIG_TARGET_P4080DS
#define __USB_PHY_TYPE ulpi
#else
#define __USB_PHY_TYPE utmi
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index db90f92..e6a52d8 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -37,7 +37,6 @@
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
@@ -112,8 +111,6 @@
#define CONFIG_MTD_PARTITIONS
/* DFU class support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
@@ -160,13 +157,7 @@
#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_ECC
diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
index 88845dc..2e9fa07 100644
--- a/include/configs/cougarcanyon2.h
+++ b/include/configs/cougarcanyon2.h
@@ -14,8 +14,6 @@
#define CONFIG_SMSC_SIO1007
-#define CONFIG_PCI_PNP
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
@@ -27,8 +25,4 @@
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x5ff000
-/* Video is not supported for now */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-
#endif /* __CONFIG_H */
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 49ed3ef..cef2fd7 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -19,19 +19,14 @@
#define CONFIG_SMSC_LPC47M
-#define CONFIG_PCI_PNP
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
-#define CONFIG_MMC
-#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SDMA
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index c1abcb6..14e207e 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -7,20 +7,17 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CYRUS
-#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040)
+#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
#error Must call Cyrus CONFIG with a specific CPU enabled.
#endif
-#define CONFIG_MMC
#define CONFIG_SDCARD
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
-#ifdef CONFIG_PPC_P5020
+#ifdef CONFIG_ARCH_P5020
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_SYS_DPAA_RMAN
#endif
@@ -32,18 +29,15 @@
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
-#if defined(CONFIG_PPC_P5020)
+#if defined(CONFIG_ARCH_P5020)
#define CONFIG_SYS_CLK_FREQ 133000000
#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
-#elif defined(CONFIG_PPC_P5040)
+#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
@@ -54,16 +48,13 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_NO_FLASH
@@ -132,7 +123,6 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
@@ -388,7 +378,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -448,12 +437,8 @@
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL
/* _VIA_CONTROL_EP */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif
#ifdef CONFIG_MMC
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index ef0fd59..ceb9cea 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -31,8 +31,6 @@
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
#ifdef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_ARCH_CPU_INIT
@@ -147,8 +145,6 @@
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
@@ -205,7 +201,6 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 10
#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
@@ -301,7 +296,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_LZO
#define CONFIG_RBTREE
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#endif
@@ -319,7 +313,6 @@
/* SD/MMC configuration */
#ifndef CONFIG_USE_NOR
-#define CONFIG_MMC
#define CONFIG_DAVINCI_MMC_SD1
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
@@ -340,12 +333,7 @@
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
@@ -355,10 +343,6 @@
/* Load U-Boot Image From MMC */
#ifdef CONFIG_SPL_MMC_LOAD
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75
-#undef CONFIG_SPL_SPI_SUPPORT
#undef CONFIG_SPL_SPI_LOAD
#endif
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index b0311bf..04ab48d 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -24,7 +24,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
index 4e00812..282d5e8 100644
--- a/include/configs/db-88f6720.h
+++ b/include/configs/db-88f6720.h
@@ -50,7 +50,6 @@
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
/* Additional FS support/configuration */
@@ -91,14 +90,7 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
new file mode 100644
index 0000000..4834828
--- /dev/null
+++ b/include/configs/db-88f6820-amc.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_DB_88F6820_AMC_H
+#define _CONFIG_DB_88F6820_AMC_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_PCI
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+/* Partition support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 1
+#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* NAND */
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
+ *
+ * MMC is not populated on this board.
+ * NAND support may be added in the future.
+ */
+#define SPL_BOOT_SPI_NOR_FLASH 1
+#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE (140 << 10)
+#define CONFIG_SPL_TEXT_BASE 0x40000030
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 96
+
+#endif /* _CONFIG_DB_88F6820_AMC_H */
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 88614b3..519f2d3 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -43,11 +43,7 @@
/*
* SDIO/MMC Card Configuration
*/
-#define CONFIG_MMC
-#define CONFIG_MMC_SDMA
#define CONFIG_GENERIC_MMC
-#define CONFIG_SDHCI
-#define CONFIG_MV_SDHCI
#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
/*
@@ -82,13 +78,10 @@
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
/* Keep device tree and initrd in lower memory so the kernel can access them */
@@ -124,15 +117,8 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
@@ -140,13 +126,9 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512)
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 5cdfd1c..26508c2 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -55,7 +55,6 @@
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
/* SATA support */
@@ -71,9 +70,7 @@
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#endif
@@ -116,14 +113,7 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index dbd2bb3..182e8ab 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -15,8 +15,6 @@
#define CONFIG_DBAU1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
#define CONFIG_SOC_AU1000 1
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index abf1394..a71f67c 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -137,7 +137,6 @@
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
/*
@@ -193,16 +192,12 @@
/* Use the framework and generic lib */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
/* SPL will use serial */
-#define CONFIG_SPL_SERIAL_SUPPORT
/* SPL loads an image from NAND */
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_RAW_ONLY
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 5112ef3..e72cee0 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -40,10 +40,6 @@
#include <configs/ti_omap3_common.h>
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
@@ -199,7 +195,6 @@
#define CONFIG_SYS_SRAM_SIZE 0x10000
/* Defines for SPL */
-#undef CONFIG_SPL_MTD_SUPPORT
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h
index 23d8a0a..727baae 100644
--- a/include/configs/dfi-bt700.h
+++ b/include/configs/dfi-bt700.h
@@ -21,8 +21,6 @@
#undef CONFIG_SYS_NS16550_PORT_MAPPED
#endif
-#define CONFIG_PCI_PNP
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
@@ -31,10 +29,7 @@
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_MMC
-#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SDMA
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 8cf0283..ae0d3d4 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -22,7 +22,6 @@
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
@@ -51,8 +50,6 @@
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCI_BOOTDELAY 250
@@ -73,18 +70,13 @@
/*
* Video
*/
-#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
#define CONFIG_VIDEO_MB862xx_ACCEL
#define CONFIG_VIDEO_CORALP
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
@@ -224,12 +216,6 @@
#define CONFIG_BOOTCOMMAND "run mtcb_start"
/*
- * SPI configuration
- */
-#define CONFIG_HARD_SPI 1
-#define CONFIG_MPC52XX_SPI 1
-
-/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 521604e..a5384a2 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -17,7 +17,6 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvsion-10g
-#define CONFIG_IDENT_STRING " dlvision-10g 0.06"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
index 4dda319..57640da 100644
--- a/include/configs/dlvision.h
+++ b/include/configs/dlvision.h
@@ -17,7 +17,6 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvision
-#define CONFIG_IDENT_STRING " dlvision 0.02"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
diff --git a/include/configs/dns325.h b/include/configs/dns325.h
index 7ee274e..1b61afd 100644
--- a/include/configs/dns325.h
+++ b/include/configs/dns325.h
@@ -18,7 +18,6 @@
*/
#define MACH_TYPE_DNS325 3800
#define CONFIG_MACH_TYPE MACH_TYPE_DNS325
-#define CONFIG_IDENT_STRING "\nD-Link DNS-325"
/*
* High Level Configuration Options (easy to change)
@@ -76,17 +75,6 @@
#define CONFIG_KIRKWOOD_GPIO
/*
- * Console configuration
- */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/*
- * Display cpu info at boot
- */
-#define CONFIG_DISPLAY_CPUINFO
-
-/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h
index cd05857..781a8b5 100644
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -13,11 +13,6 @@
#define _CONFIG_DOCKSTAR_H
/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nSeagate FreeAgent DockStar"
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
@@ -87,7 +82,6 @@
* File system
*/
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8d5dbc0..980ab40 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -12,6 +12,8 @@
#ifndef __CONFIG_DRA7XX_EVM_H
#define __CONFIG_DRA7XX_EVM_H
+#include <environment/ti/dfu.h>
+
#define CONFIG_DRA7XX
#define CONFIG_BOARD_EARLY_INIT_F
@@ -54,11 +56,12 @@
/* Android partitions */ \
"partitions_android=" \
"uuid_disk=${uuid_gpt_disk};" \
- "name=xloader,start=128K,size=128K,uuid=${uuid_gpt_xloader};" \
- "name=bootloader,size=384K,uuid=${uuid_gpt_bootloader};" \
+ "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
+ "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \
"name=environment,size=128K,uuid=${uuid_gpt_environment};" \
"name=misc,size=128K,uuid=${uuid_gpt_misc};" \
- "name=efs,start=1280K,size=16M,uuid=${uuid_gpt_efs};" \
+ "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
+ "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
"name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
"name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \
"name=boot,size=10M,uuid=${uuid_gpt_boot};" \
@@ -68,68 +71,31 @@
"name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
"name=userdata,size=-,uuid=${uuid_gpt_userdata}"
-#define DFU_ALT_INFO_MMC \
- "dfu_alt_info_mmc=" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
- "dfu_alt_info_emmc=" \
- "rawemmc raw 0 3751936;" \
- "boot part 1 1;" \
- "rootfs part 1 2;" \
- "MLO fat 1 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 1 1;" \
- "spl-os-image fat 1 1;" \
- "u-boot.img fat 1 1;" \
- "uEnv.txt fat 1 1\0"
-
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0x4000000;" \
- "fdt ram 0x80f80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
-
-#define DFU_ALT_INFO_QSPI \
- "dfu_alt_info_qspi=" \
- "MLO raw 0x0 0x010000;" \
- "MLO.backup1 raw 0x010000 0x010000;" \
- "MLO.backup2 raw 0x020000 0x010000;" \
- "MLO.backup3 raw 0x030000 0x010000;" \
- "u-boot.img raw 0x040000 0x0100000;" \
- "u-boot-spl-os raw 0x140000 0x080000;" \
- "u-boot-env raw 0x1C0000 0x010000;" \
- "u-boot-env.backup raw 0x1D0000 0x010000;" \
- "kernel raw 0x1E0000 0x800000\0"
-
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_QSPI
+#else
+/* Discard fastboot in SPL build, to spare some space */
+#undef CONFIG_FASTBOOT
+#undef CONFIG_USB_FUNCTION_FASTBOOT
+#undef CONFIG_CMD_FASTBOOT
+#undef CONFIG_ANDROID_BOOT_IMAGE
+#undef CONFIG_FASTBOOT_BUF_ADDR
+#undef CONFIG_FASTBOOT_BUF_SIZE
+#undef CONFIG_FASTBOOT_FLASH
+#endif
-/* Fastboot */
-#define CONFIG_USB_FUNCTION_FASTBOOT
-#define CONFIG_CMD_FASTBOOT
-#define CONFIG_ANDROID_BOOT_IMAGE
-#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
-#define CONFIG_FASTBOOT_BUF_SIZE 0x2F000000
-#define CONFIG_FASTBOOT_FLASH
-#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_CMD_BOOTD
+#ifdef CONFIG_SPL_DFU_SUPPORT
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
+#define DFUARGS \
+ "dfu_bufsiz=0x10000\0" \
+ DFU_ALT_INFO_RAM
+#endif
#endif
#include <configs/ti_omap5_common.h>
@@ -167,10 +133,7 @@
/*
* Default to using SPI for environment, etc.
- * 0x000000 - 0x010000 : QSPI.SPL (64KiB)
- * 0x010000 - 0x020000 : QSPI.SPL.backup1 (64KiB)
- * 0x020000 - 0x030000 : QSPI.SPL.backup2 (64KiB)
- * 0x030000 - 0x040000 : QSPI.SPL.backup3 (64KiB)
+ * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
* 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
* 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
* 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
@@ -182,11 +145,6 @@
#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
#if defined(CONFIG_QSPI_BOOT)
-/* In SPL, use the environment and discard MMC support for space. */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_SPL_MMC_SUPPORT
-#endif
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
@@ -197,11 +155,8 @@
#endif
/* SPI SPL */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_DMA_SUPPORT
#define CONFIG_TI_EDMA3
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#define CONFIG_SUPPORT_EMMC_BOOT
@@ -213,14 +168,6 @@
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB2PHY2_HOST
-/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_RAM
-
-#define CONFIG_DFU_MMC
-#define CONFIG_DFU_RAM
-#define CONFIG_DFU_SF
-
/* SATA */
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SCSI
diff --git a/include/configs/draco.h b/include/configs/draco.h
index 889178c..7c4179d 100644
--- a/include/configs/draco.h
+++ b/include/configs/draco.h
@@ -19,7 +19,6 @@
#include "siemens-am33x-common.h"
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MPUCLK 300
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
@@ -46,12 +45,6 @@
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
-
-#undef CONFIG_SPL_NET_SUPPORT
-#undef CONFIG_SPL_NET_VCI_STRING
-#undef CONFIG_SPL_ETH_SUPPORT
-
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
#define CONFIG_PHY_SMSC
diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index cc7ab83..e6bb919 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -12,8 +12,6 @@
#include <linux/sizes.h>
#include <asm/arch/sysmap-apq8016.h>
-#define CONFIG_IDENT_STRING "\nQualcomm-DragonBoard 410C"
-
#define CONFIG_MISC_INIT_R /* To stop autoboot */
/* Physical Memory Map */
@@ -34,9 +32,7 @@
#define COUNTER_FREQUENCY 19000000
/* This are needed to have proper mmc support */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_SDHCI
#define CONFIG_SYS_LDSCRIPT "board/qualcomm/dragonboard410c/u-boot.lds"
diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h
index c78c949..252e5f5 100644
--- a/include/configs/dreamplug.h
+++ b/include/configs/dreamplug.h
@@ -26,11 +26,6 @@
#endif
/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-DreamPlug"
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
diff --git a/include/configs/ds109.h b/include/configs/ds109.h
new file mode 100644
index 0000000..222a510
--- /dev/null
+++ b/include/configs/ds109.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_DS109_H
+#define _CONFIG_DS109_H
+
+/*
+ * FIXME: This belongs in mach-types.h. However, we only pull mach-types
+ * from Linus' kernel.org tree. This hasn't been updated primarily due to
+ * the recent arch/arm reshuffling. So, in the meantime, we'll place it
+ * here.
+ */
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_SYNOLOGY
+#error "MACH_TYPE_SYNOLOGY has been defined properly, please remove this."
+#else
+#define MACH_TYPE_SYNOLOGY 527
+#endif
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
+#define CONFIG_MACH_TYPE MACH_TYPE_SYNOLOGY
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/*
+ * mv-plug-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-plug-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI 1
+#define CONFIG_KIRKWOOD_SPI 1
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
+#endif
+
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_ADDR 0x3d0000
+#define CONFIG_ENV_OFFSET 0x3d0000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
+ "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "bootm 0x6400000;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "x_bootcmd_ethernet=ping 192.168.1.2\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
+ "x_bootargs=console=ttyS0,115200\0" \
+ "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \
+ "ipaddr=192.168.1.5\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */
+#define CONFIG_PHY_BASE_ADR 8
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#endif /* _CONFIG_DS109_H */
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index 11c1ec4..0be8800 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -51,7 +51,6 @@
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_PCI_MVEBU
@@ -122,14 +121,7 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
diff --git a/include/configs/duovero.h b/include/configs/duovero.h
index 868158b..b5bd3ba 100644
--- a/include/configs/duovero.h
+++ b/include/configs/duovero.h
@@ -21,7 +21,6 @@
#include <configs/ti_omap4_common.h>
-#undef CONFIG_SPL_OS_BOOT
#undef CONFIG_EFI_PARTITION
#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h
index c9e8c8e..d4aca55 100644
--- a/include/configs/e2220-1170.h
+++ b/include/configs/e2220-1170.h
@@ -22,7 +22,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 910bcd4..f897145 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -21,7 +21,6 @@
#define CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_VIDEO
#define CONFIG_PREBOOT
/*
@@ -103,16 +102,11 @@
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CMD_BMP
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#endif
/*
@@ -160,7 +154,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_LZO
#define CONFIG_RBTREE
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_NAND_DAVINCI
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 6d469a38..4a868c5 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -251,8 +251,6 @@
* VIDEO configuration
*/
-#define CONFIG_VIDEO
-
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_VCXK 1
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index c8508ff..6470327 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -22,7 +22,6 @@
* 0x1800_0000 MFI 16bit
*/
-#undef DEBUG
#define CONFIG_CPU_SH7724 1
#define CONFIG_BOARD_LATE_INIT 1
#define CONFIG_ECOVEC 1
@@ -38,6 +37,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* I2C */
@@ -91,9 +91,6 @@
#define CONFIG_CONS_SCIF0 1
/* Suppress display of console information at boot */
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE (0x88000000)
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 7053795..a83c617 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -234,7 +234,6 @@
#ifdef CONFIG_EP93XX_SPI_MMC
#define CONFIG_EP93XX_SPI
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
#define CONFIG_MMC_SPI_NPOWER_EGPIO 9
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index c30b63b..af7b470 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -17,10 +17,6 @@
*/
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0xffff0000
#define CONFIG_SPL_MAX_SIZE 0x0000fff0
#define CONFIG_SPL_STACK 0x00020000
@@ -35,12 +31,6 @@
#define CONFIG_SYS_TEXT_BASE 0x00800000
/*
- * Version number information
- */
-
-#define CONFIG_IDENT_STRING " EDMiniV2"
-
-/*
* High Level Configuration Options (easy to change)
*/
@@ -218,10 +208,8 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_LOAD_ADDR 0x00800000
diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h
index 95e46c5..5626061 100644
--- a/include/configs/efi-x86.h
+++ b/include/configs/efi-x86.h
@@ -15,8 +15,6 @@
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
#undef CONFIG_SCSI_AHCI
#undef CONFIG_SCSI
#undef CONFIG_INTEL_ICH6_GPIO
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index 55ef612..8a0b3d2 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h
@@ -25,10 +25,6 @@
#define CONFIG_MXC_UART
#ifdef CONFIG_SPL
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#define CONFIG_SPL_SPI_LOAD
#include "imx6_spl.h"
@@ -67,7 +63,6 @@
/* Command definition */
#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
#define CONFIG_BOARD_NAME EL6Q
@@ -77,7 +72,7 @@
"board="__stringify(CONFIG_BOARD_NAME)"\0" \
"cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \
"chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV "\0" \
"fdtfile=undefined\0" \
"fdt_high=0xffffffff\0" \
"fdt_addr_r=0x18000000\0" \
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 809ec21..2106e86 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -14,7 +14,7 @@
#define __RIOTBOARD_CONFIG_H
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc1"
+#define CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk1p2"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
@@ -117,12 +117,7 @@
#endif
/* Framebuffer */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
index c6a756d..0a50154 100644
--- a/include/configs/espresso7420.h
+++ b/include/configs/espresso7420.h
@@ -24,7 +24,6 @@
/* select serial console configuration */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-#define CONFIG_IDENT_STRING " for ESPRESSO7420"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
/* DRAM Memory Banks */
diff --git a/include/configs/espt.h b/include/configs/espt.h
index e76a4ee..9475740 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -23,6 +23,7 @@
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SCIF */
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index 4919cfe..eb17d68 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h
@@ -69,7 +69,6 @@
CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MPUCLK 300
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
@@ -104,12 +103,6 @@
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
-
-#undef CONFIG_SPL_NET_SUPPORT
-#undef CONFIG_SPL_NET_VCI_STRING
-#undef CONFIG_SPL_ETH_SUPPORT
-
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
#define CONFIG_PHY_SMSC
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index ce254b3..c78eebf 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -23,7 +23,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
/* CPU information */
-#define CONFIG_DISPLAY_CPUINFO /* Display at console. */
#define CONFIG_ARCH_CPU_INIT
/* ARM asynchronous clock */
@@ -96,7 +95,6 @@
#define CONFIG_CMD_DATE
#define CONFIG_CMD_REISER
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_UNZIP
#endif
@@ -129,7 +127,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
diff --git a/include/configs/evb_rk3288.h b/include/configs/evb_rk3288.h
index 342557f..77b647e 100644
--- a/include/configs/evb_rk3288.h
+++ b/include/configs/evb_rk3288.h
@@ -10,8 +10,6 @@
#define ROCKCHIP_DEVICE_SETTINGS
#include <configs/rk3288_common.h>
-#define CONFIG_SPL_MMC_SUPPORT
-
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
/* SPL @ 32k for ~36k
@@ -21,6 +19,5 @@
#define CONFIG_ENV_OFFSET (96 * 1024)
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
index 047850a..8fdefa2 100644
--- a/include/configs/evb_rk3399.h
+++ b/include/configs/evb_rk3399.h
@@ -10,7 +10,7 @@
#include <configs/rk3399_common.h>
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_DEV 1
/*
* SPL @ 32k for ~36k
* ENV @ 96k
@@ -21,6 +21,5 @@
#define SDRAM_BANK_SIZE (2UL << 30)
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 38298a2..9328a22 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -17,14 +17,9 @@
#include <linux/sizes.h>
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
-
/* Keep L2 Cache Disabled */
/* input clock of PLL: 24MHz input clock */
@@ -44,9 +39,6 @@
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_S5P_SDHCI
-#define CONFIG_SDHCI
#define CONFIG_DWMMC
#define CONFIG_EXYNOS_DWMMC
#define CONFIG_BOUNCE_BUFFER
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index fdbaf02..ec45640 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -18,7 +18,6 @@
#define CONFIG_REVISION_TAG
/* SD/MMC configuration */
-#define CONFIG_MMC_SDMA
#define CONFIG_MMC_DEFAULT_DEV 0
#undef CONFIG_CMD_ONENAND
@@ -29,8 +28,6 @@
#define CONFIG_CMD_THOR_DOWNLOAD
#define CONFIG_USB_FUNCTION_THOR
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define DFU_DEFAULT_POLL_TIMEOUT 300
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 421002d..12ceb2c 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -42,9 +42,6 @@
/* select serial console configuration */
#define CONFIG_BAUDRATE 115200
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
-#define CONFIG_SILENT_CONSOLE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_CONSOLE_MUX
#define CONFIG_CMD_HASH
@@ -57,10 +54,6 @@
#define COPY_BL2_FNPTR_ADDR 0x02020030
#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-
/* specific .lds file */
#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h
index 3d81f94..7cb3a29 100644
--- a/include/configs/exynos5-dt-common.h
+++ b/include/configs/exynos5-dt-common.h
@@ -27,7 +27,6 @@
#define CONFIG_BOARD_COMMON
/* Display */
-#define CONFIG_LCD
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
index 9e03962..1cea74e 100644
--- a/include/configs/exynos7420-common.h
+++ b/include/configs/exynos7420-common.h
@@ -18,7 +18,6 @@
#include <linux/sizes.h>
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
/* Size of malloc() pool before and after relocation */
@@ -48,15 +47,13 @@
#define CONFIG_IRAM_BASE 0x02100000
#define CONFIG_IRAM_SIZE 0x58000
#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
+#define CPU_RELEASE_ADDR secondary_boot_addr
/* Number of CPUs available */
#define CONFIG_CORE_COUNT 0x8
/* select serial console configuration */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SILENT_CONSOLE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h
index 342557f..77b647e 100644
--- a/include/configs/fennec_rk3288.h
+++ b/include/configs/fennec_rk3288.h
@@ -10,8 +10,6 @@
#define ROCKCHIP_DEVICE_SETTINGS
#include <configs/rk3288_common.h>
-#define CONFIG_SPL_MMC_SUPPORT
-
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
/* SPL @ 32k for ~36k
@@ -21,6 +19,5 @@
#define CONFIG_ENV_OFFSET (96 * 1024)
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h
index a29f557..14fdead 100644
--- a/include/configs/firefly-rk3288.h
+++ b/include/configs/firefly-rk3288.h
@@ -14,8 +14,6 @@
#include <configs/rk3288_common.h>
-#define CONFIG_SPL_MMC_SUPPORT
-
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
/* SPL @ 32k for ~36k
@@ -25,6 +23,5 @@
#define CONFIG_ENV_OFFSET (96 * 1024)
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index e84803d..0f7b3c8 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -20,8 +20,6 @@
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_DISPLAY_CPUINFO
-
/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
#define MACH_TYPE_FLEA3 3668
@@ -103,10 +101,9 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
@@ -229,8 +226,8 @@
"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
- "update=protect off ${uboot_addr} +40000;" \
- "erase ${uboot_addr} +40000;" \
+ "update=protect off ${uboot_addr} +80000;" \
+ "erase ${uboot_addr} +80000;" \
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
"upd=if run load;then echo Updating u-boot;if run update;" \
"then echo U-Boot updated;" \
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 40f7fba..26eb127 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -21,8 +21,6 @@
/* ns16550 UART is memory-mapped in Quark SoC */
#undef CONFIG_SYS_NS16550_PORT_MAPPED
-#define CONFIG_PCI_PNP
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
@@ -31,15 +29,8 @@
#undef CONFIG_SCSI_AHCI
#undef CONFIG_SCSI
-/* Video is not supported in Quark SoC */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-
/* SD/MMC support */
-#define CONFIG_MMC
-#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SDMA
/* 10/100M Ethernet support */
#define CONFIG_DESIGNWARE_ETH
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
index 2845a80..12bf95f 100644
--- a/include/configs/gdppc440etx.h
+++ b/include/configs/gdppc440etx.h
@@ -155,9 +155,7 @@
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \
CONFIG_SYS_PCI_MEMBASE*/
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 52f096e..0039c8c 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -15,22 +15,22 @@
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
+#define BX50V3_BOOTARGS_EXTRA
#if defined(CONFIG_TARGET_GE_B450V3)
#define CONFIG_BOARD_NAME "General Electric B450v3"
-#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb"
#elif defined(CONFIG_TARGET_GE_B650V3)
#define CONFIG_BOARD_NAME "General Electric B650v3"
-#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b650v3.dtb"
#elif defined(CONFIG_TARGET_GE_B850V3)
#define CONFIG_BOARD_NAME "General Electric B850v3"
-#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb"
+#undef BX50V3_BOOTARGS_EXTRA
+#define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \
+ "video=HDMI-A-1:1024x768@60 "
#else
#define CONFIG_BOARD_NAME "General Electric BA16 Generic"
-#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb"
#endif
#define CONFIG_MXC_UART_BASE UART3_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc2"
+#define CONSOLE_DEV "ttymxc2"
#define CONFIG_SUPPORT_EMMC_BOOT
@@ -38,9 +38,6 @@
#include "mx6_common.h"
#include <linux/sizes.h>
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -70,7 +67,6 @@
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_DOS_PARTITION
@@ -83,7 +79,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
#define CONFIG_CI_UDC
@@ -139,7 +134,7 @@
"fdt_addr=0x18000000\0" \
"boot_fdt=yes\0" \
"ip_dyn=yes\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV "\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"sddev=0\0" \
@@ -166,7 +161,8 @@
"echo 'U-Boot upgraded. Please reset'; " \
"fi\0" \
"setargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/${rootdev} rw rootwait cma=128M\0" \
+ "root=/dev/${rootdev} rw rootwait cma=128M " \
+ BX50V3_BOOTARGS_EXTRA "\0" \
"loadbootscript=" \
"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
@@ -302,14 +298,9 @@
#define CONFIG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-
/* Framebuffer */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
@@ -326,8 +317,6 @@
#undef CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
index ffbe660..c17c5e9 100644
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -16,11 +16,6 @@
#define _CONFIG_GOFLEXHOME_H
/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nSeagate GoFlex Home"
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
@@ -48,8 +43,6 @@
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_CMD_ENV
#define CONFIG_CMD_NAND
diff --git a/include/configs/gose.h b/include/configs/gose.h
index 23707ed..45395cd 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -94,7 +94,6 @@
#define CONFIG_SMSTP7_ENA 0x00200000
/* SDHI */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SH_SDHI_FREQ 97500000
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 82b1830..37b0a8c 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* Based on Aspenite:
* (C) Copyright 2010
@@ -26,11 +26,6 @@
#endif
/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-gplugD"
-
-/*
* High Level Configuration Options
*/
#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
@@ -77,11 +72,6 @@
/* GPIO Configuration for PHY */
#define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */
-/* SPI Support */
-#define CONFIG_ARMADA100_SPI
-#define CONFIG_ENV_SPI_CS 110
-#define CONFIG_SYS_SSP_PORT 2
-
/* Flash Support */
/*
@@ -100,10 +90,8 @@
/*
* Environment variables configurations
*/
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x4000
+#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x4000
-#define CONFIG_ENV_OFFSET 0x07C000
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index 8b57354..211dc38 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -14,8 +14,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
@@ -340,9 +338,6 @@
/* no DDR2 Controller */
#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-/* Identification string */
-#define CONFIG_IDENT_STRING " Gaisler LEON3 GR-CPCI-AX2000"
-
/* default kernel command line */
#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 265f03c..ad0c126 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -15,8 +15,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
@@ -60,7 +58,6 @@
#if USE_GRUSB
#define CONFIG_USB_UHCI
/* Enable needed helper functions */
-#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
#endif
/*
@@ -306,9 +303,6 @@
/* no DDR2 Controller */
#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-/* Identification string */
-#define CONFIG_IDENT_STRING " Gaisler LEON3 EP2S60"
-
/* default kernel command line */
#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index 36acf01..b0e9001 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -13,8 +13,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
@@ -272,9 +270,6 @@
/* no DDR2 Controller */
#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-/* Identification string */
-#define CONFIG_IDENT_STRING " Gaisler LEON3 GR-XC3S-1500"
-
/* default kernel command line */
#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index c2656fb..17cac5a 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -13,8 +13,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
@@ -292,8 +290,6 @@
/* default kernel command line */
#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-#define CONFIG_IDENT_STRING " Gaisler GRSIM"
-
/* TSIM command:
* $ ./tsim-leon3 -mmu -cas
*
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 59adbdc..1642793 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -12,8 +12,6 @@
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
* (easy to change)
@@ -287,6 +285,4 @@
/* default kernel command line */
#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-#define CONFIG_IDENT_STRING " Gaisler GRSIM LEON2"
-
#endif /* __CONFIG_H */
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 5907e98..5ac29db 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -11,11 +11,6 @@
#define _CONFIG_GURUPLUG_H
/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-GuruPlug"
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 92d64a9..8f6d9bb 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -9,15 +9,11 @@
/* SPL */
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
/* Location in NAND to read U-Boot from */
#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M)
/* Falcon Mode */
#define CONFIG_CMD_SPL
-#define CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
@@ -32,8 +28,6 @@
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
-#undef CONFIG_SPL_EXT_SUPPORT
-#undef CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
@@ -130,8 +124,6 @@
*/
#define CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCI_FIXUP_DEV
#define CONFIG_PCIE_IMX
@@ -152,7 +144,6 @@
#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */
#define CONFIG_CMD_GSC
#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */
-#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
/* Ethernet support */
@@ -174,7 +165,6 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_KEYBOARD
#define CONFIG_USBD_HS
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_CDC
@@ -185,15 +175,10 @@
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* Framebuffer and LCD */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_VIDEO_LOGO
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_CMD_HDMIDETECT
-#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_VIDEO_BMP_LOGO
@@ -427,7 +412,4 @@
"if run ${btype}_boot; then; fi; " \
"done"
-/* Device Tree Support */
-#define CONFIG_FDT_FIXUP_PARTITIONS
-
#endif /* __CONFIG_H */
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 3e419c6..18b5488 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -107,8 +107,6 @@
/*
* Serial port
*/
-
-#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART
#define CONFIG_CONS_INDEX 3
@@ -131,7 +129,6 @@
#define CONFIG_BOOTARGS "root=/dev/ram0 ro console=ttyS0,115200n8"
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_USB_DEV_PULLUP_GPIO 33
/* USB VBUS GPIO 3 */
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 2ecae65..cf3c493 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -27,7 +27,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -54,7 +53,6 @@
/* LCD support */
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#include "tegra-common-post.h"
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 5e5aa19..c725833 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -21,8 +21,6 @@
#define CONFIG_SUPPORT_RAW_INITRD
-#define CONFIG_IDENT_STRING "hikey"
-
#define CONFIG_BOARD_EARLY_INIT_F
/* Physical Memory Map */
@@ -74,7 +72,6 @@
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
#define CONFIG_DWMMC
#define CONFIG_HIKEY_DWMMC
#define CONFIG_BOUNCE_BUFFER
@@ -82,7 +79,6 @@
#define CONFIG_FS_EXT4
/* Command line configuration */
-#define CONFIG_MENU
#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_ENV
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index c5e6828..b224706 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -20,20 +20,12 @@
#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#ifdef CONFIG_HRCON_DH
-#define CONFIG_IDENT_STRING " hrcon dh 0.01"
-#else
-#define CONFIG_IDENT_STRING " hrcon 0.01"
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
@@ -480,12 +472,9 @@
/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM 1
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
@@ -545,8 +534,6 @@
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
index ab23607..f686c7f 100644
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -10,11 +10,6 @@
#define _CONFIG_IB62x0_H
/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS62x0"
-
-/*
* High level configuration options
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
diff --git a/include/configs/icon.h b/include/configs/icon.h
index 7e9e7e6..b15016b 100644
--- a/include/configs/icon.h
+++ b/include/configs/icon.h
@@ -126,18 +126,13 @@
/*
* Video options
*/
-#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#define CONFIG_VIDEO_SM501_32BPP
#define CONFIG_VIDEO_SM501_PCI
#define VIDEO_FB_LITTLE_ENDIAN
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CFG_CONSOLE_IS_IN_ENV
@@ -211,9 +206,7 @@
* PCI stuff
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
#define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/
diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h
index f0d4250..633941b 100644
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -10,11 +10,6 @@
#define _CONFIG_ICONNECT_H
/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING " Iomega iConnect"
-
-/*
* High level configuration options
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
@@ -95,7 +90,6 @@
* File system
*/
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index c9d3b93..112e885 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -533,7 +533,6 @@
/* UBI Support */
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h
new file mode 100644
index 0000000..0a7fe60
--- /dev/null
+++ b/include/configs/imgtec_xilfpga.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Imagination Technologies Ltd. MIPSfpga
+ */
+
+#ifndef __XILFPGA_CONFIG_H
+#define __XILFPGA_CONFIG_H
+
+/* BootROM + MIG is pretty smart. DDR and Cache initialized */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*--------------------------------------------
+ * CPU configuration
+ */
+/* CPU Timer rate */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
+
+/* Cache Configuration */
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+
+/*----------------------------------------------------------------------
+ * Memory Layout
+ */
+
+/* SDRAM Configuration (for final code, data, stack, heap) */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
+
+#define CONFIG_SYS_MALLOC_LEN (256 << 10)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */
+
+/*----------------------------------------------------------------------
+ * Commands
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+/*-------------------------------------------------
+ * FLASH configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*------------------------------------------------------------
+ * Console Configuration
+ */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
+#define CONFIG_BAUDRATE 115200
+
+/* -------------------------------------------------
+ * Environment
+ */
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x4000
+
+/* ---------------------------------------------------------------------
+ * Board boot configuration
+ */
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+#endif /* __XILFPGA_CONFIG_H */
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 80628dd..30168bc 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -16,9 +16,6 @@
#define CONFIG_MX27
#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_SYS_TEXT_BASE 0xc0000000
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
@@ -140,7 +137,6 @@
/*
* SD/MMC
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MXC_MMC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 50dfc11..4910b51 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -18,9 +18,6 @@
#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_MX31_CLK32 32000
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -181,13 +178,8 @@
#define CONFIG_S6E63D6
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MX3
#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 9bd9f6e..c5a035f 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -25,31 +25,27 @@
* or 64KB
*/
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x00908000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_STACK 0x0091FFB8
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
+/*
+ * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO 0x11000
/* NAND support */
#if defined(CONFIG_SPL_NAND_SUPPORT)
#define CONFIG_SPL_NAND_MXS
-#define CONFIG_SPL_DMA_SUPPORT
#endif
/* MMC support */
#if defined(CONFIG_SPL_MMC_SUPPORT)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
+#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-#define CONFIG_SPL_EXT_SUPPORT
#endif
/* SATA support */
@@ -57,13 +53,11 @@
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-#define CONFIG_SPL_EXT_SUPPORT
#endif
/* Define the payload for FAT/EXT support */
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_LIBDISK_SUPPORT
#endif
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
new file mode 100644
index 0000000..eb83d23
--- /dev/null
+++ b/include/configs/imx6qdl_icore.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam i.CoreM6 QDL Starter Kits.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX6QLD_ICORE_CONFIG_H
+#define __IMX6QLD_ICORE_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+# define CONFIG_ENV_OFFSET 0x100000
+/* Environment in NAND */
+# elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET 0x400000
+# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "splashpos=m,m\0" \
+ "image=uImage\0" \
+ "fit_image=fit.itb\0" \
+ "console=ttymxc3\0" \
+ "fdt_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x18000000\0" \
+ "boot_fdt=try\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "nandroot=ubi0:rootfs rootfstype=ubifs\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "ubiargs=setenv bootargs console=${console},${baudrate} " \
+ "ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \
+ "fitboot=echo Booting FIT image from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "if mtdparts; then " \
+ "echo Starting nand boot ...; " \
+ "else " \
+ "mtdparts default; " \
+ "fi; " \
+ "run ubiargs; " \
+ "nand read ${loadaddr} kernel 0x800000; " \
+ "nand read ${fdt_addr} dtb 0x100000; " \
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+#ifdef CONFIG_NAND_MXS
+# define CONFIG_BOOTCOMMAND "run nandboot"
+#else
+# define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadfit; then " \
+ "run fitboot; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FIT */
+#ifdef CONFIG_FIT
+# define CONFIG_HASH_VERIFY
+# define CONFIG_SHA1
+# define CONFIG_SHA256
+# define CONFIG_IMAGE_FORMAT_LEGACY
+#endif
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# define CONFIG_MXC_UART_BASE UART4_BASE
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV 0
+# define CONFIG_SYS_FSL_USDHC_NUM 1
+# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#endif
+
+/* NAND */
+#ifdef CONFIG_NAND_MXS
+# define CONFIG_SYS_MAX_NAND_DEVICE 1
+# define CONFIG_SYS_NAND_BASE 0x40000000
+# define CONFIG_SYS_NAND_5_ADDR_CYCLE
+# define CONFIG_SYS_NAND_ONFI_DETECTION
+# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
+
+/* MTD device */
+# define CONFIG_MTD_DEVICE
+# define CONFIG_CMD_MTDPARTS
+# define CONFIG_MTD_PARTITIONS
+# define MTDIDS_DEFAULT "nand0=gpmi-nand"
+# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:2m(spl),2m(uboot)," \
+ "1m(env),8m(kernel),1m(dtb),-(rootfs)"
+
+/* UBI */
+# define CONFIG_CMD_UBIFS
+# define CONFIG_RBTREE
+# define CONFIG_LZO
+
+# define CONFIG_APBH_DMA
+# define CONFIG_APBH_DMA_BURST
+# define CONFIG_APBH_DMA_BURST8
+#endif
+
+/* Ethernet */
+#ifdef CONFIG_FEC_MXC
+# define IMX_FEC_BASE ENET_BASE_ADDR
+# define CONFIG_FEC_MXC_PHYADDR 0
+# define CONFIG_FEC_XCV_TYPE RMII
+# define CONFIG_ETHPRIME "FEC"
+
+# define CONFIG_MII
+# define CONFIG_PHYLIB
+# define CONFIG_PHY_SMSC
+#endif
+
+/* Framebuffer */
+#ifdef CONFIG_VIDEO_IPUV3
+# define CONFIG_IPUV3_CLK 260000000
+# define CONFIG_IMX_VIDEO_SKIP
+
+# define CONFIG_SPLASH_SCREEN
+# define CONFIG_SPLASH_SCREEN_ALIGN
+# define CONFIG_BMP_16BPP
+# define CONFIG_VIDEO_BMP_RLE8
+# define CONFIG_VIDEO_LOGO
+# define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# ifdef CONFIG_NAND_MXS
+# define CONFIG_SPL_NAND_SUPPORT
+# else
+# define CONFIG_SPL_MMC_SUPPORT
+# endif
+
+# include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+# undef CONFIG_DM_GPIO
+# undef CONFIG_DM_MMC
+# endif
+#endif
+
+#endif /* __IMX6QLD_ICORE_CONFIG_H */
diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h
new file mode 100644
index 0000000..6f7195d
--- /dev/null
+++ b/include/configs/imx6qdl_icore_rqs.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam i.CoreM6 QDL RQS Starter Kits.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX6QLD_ICORE_RQS_CONFIG_H
+#define __IMX6QLD_ICORE_RQS_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+# define CONFIG_ENV_OFFSET 0x100000
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=uImage\0" \
+ "fit_image=fit.itb\0" \
+ "console=ttymxc3\0" \
+ "fdt_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x18000000\0" \
+ "boot_fdt=try\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \
+ "fitboot=echo Booting FIT image from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadfit; then " \
+ "run fitboot; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FIT */
+#ifdef CONFIG_FIT
+# define CONFIG_HASH_VERIFY
+# define CONFIG_SHA1
+# define CONFIG_SHA256
+# define CONFIG_IMAGE_FORMAT_LEGACY
+#endif
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# define CONFIG_MXC_UART_BASE UART4_BASE
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV 0
+# define CONFIG_SYS_FSL_USDHC_NUM 1
+# define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#endif
+
+/* Ethernet */
+#ifdef CONFIG_FEC_MXC
+# define CONFIG_FEC_MXC_PHYADDR 3
+# define CONFIG_FEC_XCV_TYPE RGMII
+
+# define CONFIG_MII
+# define CONFIG_PHYLIB
+# define CONFIG_PHY_MICREL
+# define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# define CONFIG_SPL_MMC_SUPPORT
+# include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+# undef CONFIG_DM_GPIO
+# undef CONFIG_DM_MMC
+# endif
+#endif
+
+#endif /* __IMX6QLD_ICORE_RQS_CONFIG_H */
diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h
new file mode 100644
index 0000000..23fa3ee
--- /dev/null
+++ b/include/configs/imx6ul_geam.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam GEAM6UL Starter Kits.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX6UL_GEAM_CONFIG_H
+#define __IMX6UL_GEAM_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+# define CONFIG_ENV_OFFSET 0x100000
+/* Environment in NAND */
+# elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET 0x400000
+# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=uImage\0" \
+ "fit_image=fit.itb\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x87800000\0" \
+ "boot_fdt=try\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "nandroot=ubi0:rootfs rootfstype=ubifs\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "ubiargs=setenv bootargs console=${console},${baudrate} " \
+ "ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \
+ "fitboot=echo Booting FIT image from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "if mtdparts; then " \
+ "echo Starting nand boot ...; " \
+ "else " \
+ "mtdparts default; " \
+ "fi; " \
+ "run ubiargs; " \
+ "nand read ${loadaddr} kernel 0x800000; " \
+ "nand read ${fdt_addr} dtb 0x100000; " \
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+#ifdef CONFIG_NAND_MXS
+# define CONFIG_BOOTCOMMAND "run nandboot"
+#else
+# define CONFIG_BOOTCOMMAND \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadfit; then " \
+ "run fitboot; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FIT */
+#ifdef CONFIG_FIT
+# define CONFIG_HASH_VERIFY
+# define CONFIG_SHA1
+# define CONFIG_SHA256
+# define CONFIG_IMAGE_FORMAT_LEGACY
+#endif
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# define CONFIG_MXC_UART_BASE UART1_BASE
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV 0
+# define CONFIG_SYS_FSL_USDHC_NUM 1
+# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#endif
+
+/* NAND */
+#ifdef CONFIG_NAND_MXS
+# define CONFIG_SYS_MAX_NAND_DEVICE 1
+# define CONFIG_SYS_NAND_BASE 0x40000000
+# define CONFIG_SYS_NAND_5_ADDR_CYCLE
+# define CONFIG_SYS_NAND_ONFI_DETECTION
+# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
+
+/* MTD device */
+# define CONFIG_MTD_DEVICE
+# define CONFIG_CMD_MTDPARTS
+# define CONFIG_MTD_PARTITIONS
+# define MTDIDS_DEFAULT "nand0=gpmi-nand"
+# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:2m(spl),2m(uboot)," \
+ "1m(env),8m(kernel),1m(dtb),-(rootfs)"
+
+/* UBI */
+# define CONFIG_CMD_UBIFS
+# define CONFIG_RBTREE
+# define CONFIG_LZO
+
+# define CONFIG_APBH_DMA
+# define CONFIG_APBH_DMA_BURST
+# define CONFIG_APBH_DMA_BURST8
+#endif
+
+/* Ethernet */
+#ifdef CONFIG_FEC_MXC
+# define CONFIG_FEC_MXC_PHYADDR 0
+# define CONFIG_FEC_XCV_TYPE RMII
+
+# define CONFIG_MII
+# define CONFIG_PHYLIB
+# define CONFIG_PHY_SMSC
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# ifdef CONFIG_NAND_MXS
+# define CONFIG_SPL_NAND_SUPPORT
+# else
+# define CONFIG_SPL_MMC_SUPPORT
+# endif
+
+# include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+# undef CONFIG_DM_GPIO
+# undef CONFIG_DM_MMC
+# endif
+#endif
+
+#endif /* __IMX6UL_GEAM_CONFIG_H */
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 56c7ca9..79a716e 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -18,7 +18,6 @@
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_INKA4X0 1 /* INKA4x0 board */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
@@ -48,8 +47,6 @@
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index e7d058f..1d1b8b3 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -44,9 +44,7 @@
* PCI definitions
*/
-#define CONFIG_PCI
#define CONFIG_CMD_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_TULIP
#define CONFIG_EEPRO100
diff --git a/include/configs/intip.h b/include/configs/intip.h
index c5af365..e61005b 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -24,10 +24,8 @@
#define CONFIG_460EX 1 /* Specific PPC460EX */
#ifdef CONFIG_DEVCONCENTER
#define CONFIG_HOSTNAME devconcenter
-#define CONFIG_IDENT_STRING " devconcenter 0.06"
#else
#define CONFIG_HOSTNAME intip
-#define CONFIG_IDENT_STRING " intip 0.06"
#endif
#define CONFIG_440 1
@@ -290,9 +288,7 @@
* PCI stuff
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
#define CONFIG_PCI_DISABLE_PCIE
diff --git a/include/configs/io.h b/include/configs/io.h
index 544d044..8c9ee0e 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -17,7 +17,6 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io
-#define CONFIG_IDENT_STRING " io 0.06"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/io64.h b/include/configs/io64.h
index 14ffb33..7f2cbd5 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -36,7 +36,6 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io64
-#define CONFIG_IDENT_STRING " io64 0.02"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
@@ -395,8 +394,6 @@
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index d85a76c..87f56f1 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -17,7 +17,6 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME iocon
-#define CONFIG_IDENT_STRING " iocon 0.06"
#include "amcc-common.h"
/* Reclaim some space. */
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 37a5fa4..991dad1 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -32,8 +32,6 @@
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
/*
@@ -178,7 +176,6 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 10
#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
@@ -266,7 +263,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_LZO
#define CONFIG_RBTREE
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define MTDIDS_NAME_STR "davinci_nand.0"
@@ -285,9 +281,6 @@
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
@@ -302,14 +295,12 @@
/* add FALCON boot mode */
#define CONFIG_CMD_SPL
-#define CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
#define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
#define CONFIG_CMD_SPL_NAND_OFS 0x00180000
#define CONFIG_CMD_SPL_WRITE_SIZE 0x400
/* GPIO support */
-#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_DA8XX_GPIO
#define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index 126e02e..3bd938e 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -19,7 +19,6 @@
#define CONFIG_MPX5200 1 /* MPX5200 board */
#define CONFIG_MPC5200_DDR 1 /* use DDR RAM */
#define CONFIG_IPEK01 /* Motherboard is ipek01 */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xfc000000
@@ -44,18 +43,12 @@
/*
* Video configuration for LIME GDC
*/
-#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
#define CONFIG_VIDEO_MB862xx_ACCEL
#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
@@ -70,8 +63,6 @@
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCI_MEM_BUS 0x40000000
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index 26c629f..c1fa2c6 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -26,7 +26,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -50,8 +49,6 @@
#define CONFIG_USB_ETHER_ASIX
/* PCI host support */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
/* General networking support */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 65f53b7..e073528 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -15,7 +15,6 @@
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_JUPITER 1 /* ... on Jupiter board */
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
@@ -45,10 +44,8 @@
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-/*#define CONFIG_PCI */
#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 7eaab87..777f225 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -12,13 +12,11 @@
/* Platform type */
#define CONFIG_SOC_K2E
-#define CONFIG_K2E_EVM
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
"boot=ubi\0" \
- "addr_mon=0x0c140000\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
"name_fdt=keystone-k2e-evm.dtb\0" \
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 71b0037..fb8fbe4 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -12,18 +12,17 @@
/* Platform type */
#define CONFIG_SOC_K2G
-#define CONFIG_K2G_EVM
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_MMC_TI_ARGS \
DEFAULT_PMMC_BOOT_ENV \
+ DEFAULT_FW_INITRAMFS_BOOT_ENV \
"boot=mmc\0" \
"console=ttyS0,115200n8\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"rd_spec=-\0" \
- "addr_mon=0x0c040000\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
"name_fdt=keystone-k2g-evm.dtb\0" \
@@ -31,6 +30,8 @@
"name_ubi=k2g-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2g-evm.gph\0" \
"init_mmc=run args_all args_mmc\0" \
+ "init_fw_rd_mmc=load mmc ${bootpart} ${rdaddr} " \
+ "${bootdir}/${name_fw_rd}; run set_rd_spec\0" \
"soc_variant=k2g\0" \
"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0"\
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
@@ -40,9 +41,9 @@
#define CONFIG_BOOTCOMMAND \
"run envboot; " \
- "run set_name_pmmc init_${boot} get_pmmc_${boot} run_pmmc " \
- "get_fdt_${boot} get_mon_${boot} get_kern_${boot} " \
- "run_mon run_kern"
+ "run set_name_pmmc init_${boot} init_fw_rd_${boot} " \
+ "get_pmmc_${boot} run_pmmc get_mon_${boot} run_mon " \
+ "get_fdt_${boot} get_kern_${boot} run_kern"
#include <configs/ti_armv7_keystone2.h>
@@ -60,7 +61,6 @@
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
/* MMC/SD */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
@@ -77,6 +77,7 @@
#define CONFIG_CADENCE_QSPI
#define CONFIG_CQSPI_REF_CLK 384000000
#define CONFIG_CQSPI_DECODER 0x0
+#define CONFIG_BOUNCE_BUFFER
#endif
#endif /* __CONFIG_K2G_EVM_H */
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 0256f0e..4adb119 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -12,13 +12,11 @@
/* Platform type */
#define CONFIG_SOC_K2HK
-#define CONFIG_K2HK_EVM
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
"boot=ubi\0" \
- "addr_mon=0x0c5f0000\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
"name_fdt=keystone-k2hk-evm.dtb\0" \
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 2322ab2..9bdd565 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -12,13 +12,11 @@
/* Platform type */
#define CONFIG_SOC_K2L
-#define CONFIG_K2L_EVM
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
"boot=ubi\0" \
- "addr_mon=0x0c140000\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0" \
"name_fdt=keystone-k2l-evm.dtb\0" \
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index e3fede5..a41c127 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -214,9 +214,7 @@
*-----------------------------------------------------------------------
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index c1a9e64..7a4ba09 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -31,7 +31,6 @@
#define CONFIG_OMAP
#define CONFIG_OMAP4430
-#define CONFIG_OMAP_COMMON
/*
* Board
@@ -89,7 +88,6 @@
* MMC
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
@@ -126,29 +124,15 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024)
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2
/*
* Console
*/
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 227504f..2254eca 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -387,14 +387,10 @@
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 8e1de7c..4ab96bf 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -65,7 +65,6 @@
#define CONFIG_BOOTP_HOSTNAME
/* UBI Support for all Keymile boards */
-#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h
index d21b500..0fe89af 100644
--- a/include/configs/km/km8309-common.h
+++ b/include/configs/km/km8309-common.h
@@ -10,8 +10,6 @@
#ifndef __CONFIG_KM8309_COMMON_H
#define __CONFIG_KM8309_COMMON_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h
index ef83263..5bc546c 100644
--- a/include/configs/km/km8321-common.h
+++ b/include/configs/km/km8321-common.h
@@ -23,8 +23,6 @@
#ifndef __CONFIG_KM8321_COMMON_H
#define __CONFIG_KM8321_COMMON_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 6a9d739..d824b1b 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -8,8 +8,6 @@
#ifndef __CONFIG_KM83XX_H
#define __CONFIG_KM83XX_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#include "km-powerpc.h"
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 25db704..98aec7c 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -146,10 +146,8 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 8166c86..b4cdb67 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -8,8 +8,6 @@
#ifndef _CONFIG_KMP204X_H
#define _CONFIG_KMP204X_H
-#define CONFIG_PPC_P2041
-
#define CONFIG_SYS_TEXT_BASE 0xfff40000
#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
@@ -20,8 +18,6 @@
#define CONFIG_NAND_ECC_BCH
-#define CONFIG_DISPLAY_BOARDINFO
-
/* common KM defines */
#include "keymile-common.h"
@@ -33,17 +29,13 @@
#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
@@ -51,8 +43,6 @@
#define CONFIG_SYS_DPAA_RMAN /* RMan */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
/* Environment in SPI Flash */
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -111,7 +101,6 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
@@ -355,7 +344,6 @@
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h
index 1f9c720..aeece20 100644
--- a/include/configs/km82xx.h
+++ b/include/configs/km82xx.h
@@ -29,8 +29,6 @@
#error ("Board unsupported")
#endif
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/km8360.h b/include/configs/km8360.h
index c8039e1..6fa4e63 100644
--- a/include/configs/km8360.h
+++ b/include/configs/km8360.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/* KMBEC FPGA (PRIO) */
#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index b377c41..0d78cfa 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -23,14 +23,12 @@
/* KM_KIRKWOOD */
#if defined(CONFIG_KM_KIRKWOOD)
-#define CONFIG_IDENT_STRING "\nKeymile Kirkwood"
#define CONFIG_HOSTNAME km_kirkwood
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
/* KM_KIRKWOOD_PCI */
#elif defined(CONFIG_KM_KIRKWOOD_PCI)
-#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI"
#define CONFIG_HOSTNAME km_kirkwood_pci
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_FPGA_CONFIG
@@ -39,7 +37,6 @@
/* KM_KIRKWOOD_128M16 */
#elif defined(CONFIG_KM_KIRKWOOD_128M16)
-#define CONFIG_IDENT_STRING "\nKeymile Kirkwood 128M16"
#define CONFIG_HOSTNAME km_kirkwood_128m16
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
@@ -51,10 +48,8 @@
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
# if defined(CONFIG_KM_NUSA)
-#define CONFIG_IDENT_STRING "\nKeymile NUSA"
#define CONFIG_HOSTNAME kmnusa
# elif defined(CONFIG_KM_SUGP1)
-#define CONFIG_IDENT_STRING "\nKeymile SUGP1"
#define CONFIG_HOSTNAME kmsugp1
#define KM_PCIE_RESET_MPP7
#endif
@@ -69,7 +64,6 @@
/* KM_MGCOGE3UN */
#elif defined(CONFIG_KM_MGCOGE3UN)
-#define CONFIG_IDENT_STRING "\nKeymile COGE3UN"
#define CONFIG_HOSTNAME mgcoge3un
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
@@ -81,7 +75,6 @@
/* KMCOGE5UN */
#elif defined(CONFIG_KM_COGE5UN)
-#define CONFIG_IDENT_STRING "\nKeymile COGE5UN"
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
@@ -93,7 +86,6 @@
/* KM_PORTL2 */
#elif defined(CONFIG_KM_PORTL2)
-#define CONFIG_IDENT_STRING "\nKeymile Port-L2"
#define CONFIG_HOSTNAME portl2
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_PIGGY4_88E6061
@@ -101,7 +93,6 @@
/* KM_SUV31 */
#elif defined(CONFIG_KM_SUV31)
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
-#define CONFIG_IDENT_STRING "\nKeymile SUV31"
#define CONFIG_HOSTNAME kmsuv31
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index a1d96ff..c7aa7cc0 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -94,7 +94,6 @@
#define CONFIG_SMSTP7_ENA 0x00200000
/* SD */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SH_SDHI_FREQ 97500000
diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h
index e8ca76d..4f0bd84 100644
--- a/include/configs/kylin_rk3036.h
+++ b/include/configs/kylin_rk3036.h
@@ -23,33 +23,6 @@
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-/* Enable gpt partition table */
-#define CONFIG_CMD_GPT
-#define CONFIG_RANDOM_UUID
-#define PARTS_DEFAULT \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=loader,start=32K,size=4000K,uuid=${uuid_gpt_loader};" \
- "name=reserved,size=64K,uuid=${uuid_gpt_reserved};" \
- "name=misc,size=4M,uuid=${uuid_gpt_misc};" \
- "name=recovery,size=32M,uuid=${uuid_gpt_recovery};" \
- "name=boot_a,size=32M,uuid=${uuid_gpt_boot_a};" \
- "name=boot_b,size=32M,uuid=${uuid_gpt_boot_b};" \
- "name=system_a,size=818M,uuid=${uuid_gpt_system_a};" \
- "name=system_b,size=818M,uuid=${uuid_gpt_system_b};" \
- "name=vendor_a,size=50M,uuid=${uuid_gpt_vendor_a};" \
- "name=vendor_b,size=50M,uuid=${uuid_gpt_vendor_b};" \
- "name=cache,size=100M,uuid=${uuid_gpt_cache};" \
- "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \
- "name=persist,size=4M,uuid=${uuid_gpt_persist};" \
- "name=userdata,size=-,uuid=${uuid_gpt_userdata};\0" \
-
-#undef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "partitions=" PARTS_DEFAULT \
-
#endif
-#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_PREBOOT
-
#endif
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 409c30d..9402aca 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -18,8 +18,6 @@
#include <asm/arch/rmobile.h>
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_CMDLINE_TAG
@@ -56,9 +54,6 @@
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF4
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END \
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 9b2c575..4804fe0 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -12,27 +12,20 @@
*/
#if defined(CONFIG_INETSPACE_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2
-#define CONFIG_IDENT_STRING " IS v2"
#elif defined(CONFIG_NETSPACE_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
-#define CONFIG_IDENT_STRING " NS v2"
#elif defined(CONFIG_NETSPACE_LITE_V2)
#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2
-#define CONFIG_IDENT_STRING " NS v2 Lite"
#elif defined(CONFIG_NETSPACE_MINI_V2)
#define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2
-#define CONFIG_IDENT_STRING " NS v2 Mini"
#elif defined(CONFIG_NETSPACE_MAX_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
-#define CONFIG_IDENT_STRING " NS Max v2"
#elif defined(CONFIG_D2NET_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
-#define CONFIG_IDENT_STRING " D2 v2"
#elif defined(CONFIG_NET2BIG_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2
-#define CONFIG_IDENT_STRING " 2Big v2"
#else
#error "Unknown board"
#endif
@@ -150,12 +143,6 @@
*/
/*
- * Console configuration
- */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/*
* Environment variables configurations
*/
#define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 664999c..a7894ca 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -86,7 +86,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SH_MMCIF
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index d91e75d..3b118bb 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -26,8 +26,6 @@
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
@@ -217,7 +215,6 @@
#define CONFIG_ENV_SIZE (16 << 10)
/* SD/MMC configuration */
-#define CONFIG_MMC
#define CONFIG_DAVINCI_MMC_SD1
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
new file mode 100644
index 0000000..a55d767
--- /dev/null
+++ b/include/configs/liteboard.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ *
+ * Configuration settings for the Grinn liteBoard (i.MX6UL).
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __LITEBOARD_CONFIG_H
+#define __LITEBOARD_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT
+#endif
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 0
+#define CONFIG_MMCROOT "/dev/mmcblk0p2"
+
+#define CONFIG_CMD_BMODE
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_ENET_DEV 0
+
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#endif
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index fba2fac..20f0c61 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -8,12 +8,8 @@
#define __LS1012A_COMMON_H
#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_FSL_LSCH2
-#define CONFIG_LS1012A
#define CONFIG_GICV2
-#define CONFIG_SYS_HAS_SERDES
-
#include <asm/arch/config.h>
#define CONFIG_SYS_NO_FLASH
@@ -102,26 +98,19 @@
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
-#define CONFIG_DISPLAY_CPUINFO
-
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "initrd_high=0xffffffff\0" \
"verify=no\0" \
- "hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x80100000\0" \
"kernel_addr=0x100000\0" \
- "ramdisk_addr=0x800000\0" \
- "ramdisk_size=0x2000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0xa00000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
- "console=ttyAMA0,38400n8\0"
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
- "earlycon=uart8250,mmio,0x21c0500"
+ "earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
"$kernel_start $kernel_size && "\
"bootm $kernel_load"
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index 19ad194..f6f88e8 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -9,19 +9,28 @@
#include "ls1012a_common.h"
+/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
-
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000
-
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0xa00000\0" \
+ "kernel_load=0x96000000\0" \
+ "kernel_size=0x2800000\0"
+
/*
* USB
*/
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 75b60fa..b5b4d7e 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -9,14 +9,15 @@
#include "ls1012a_common.h"
-
+/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
/*
* QIXIS Definitions
@@ -130,7 +131,6 @@
#endif
/* MMC */
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
@@ -153,7 +153,6 @@
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
@@ -174,7 +173,6 @@
#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index d3117e7..f35fd31 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -9,15 +9,11 @@
#include "ls1012a_common.h"
-
+/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
-
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
@@ -48,7 +44,6 @@
#define __SW_REV_B 0xF0
/* MMC */
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
@@ -71,7 +66,6 @@
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
@@ -92,7 +86,6 @@
#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
new file mode 100644
index 0000000..ae8ee24
--- /dev/null
+++ b/include/configs/ls1021aiot.h
@@ -0,0 +1,365 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_LS102XA
+
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
+
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+
+/* XHCI Support - enabled by default */
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * Generic Timer Definitions
+ */
+#define GENERIC_TIMER_CLK 12500000
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+
+/*
+ * DDR: 800 MHz ( 1600 MT/s data rate )
+ */
+
+#define DDR_SDRAM_CFG 0x470c0008
+#define DDR_CS0_BNDS 0x008000bf
+#define DDR_CS0_CONFIG 0x80014302
+#define DDR_TIMING_CFG_0 0x50550004
+#define DDR_TIMING_CFG_1 0xbcb38c56
+#define DDR_TIMING_CFG_2 0x0040d120
+#define DDR_TIMING_CFG_3 0x010e1000
+#define DDR_TIMING_CFG_4 0x00000001
+#define DDR_TIMING_CFG_5 0x03401400
+#define DDR_SDRAM_CFG_2 0x00401010
+#define DDR_SDRAM_MODE 0x00061c60
+#define DDR_SDRAM_MODE_2 0x00180000
+#define DDR_SDRAM_INTERVAL 0x18600618
+#define DDR_DDR_WRLVL_CNTL 0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2 0x05060607
+#define DDR_DDR_WRLVL_CNTL_3 0x05050505
+#define DDR_DDR_CDR1 0x80040000
+#define DDR_DDR_CDR2 0x00000001
+#define DDR_SDRAM_CLK_CNTL 0x02000000
+#define DDR_DDR_ZQ_CNTL 0x89080600
+#define DDR_CS0_CONFIG_2 0
+#define DDR_SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG2_D_INIT 0x00000010
+#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
+#define SDRAM_CFG2_FRC_SR 0x80000000
+#define SDRAM_CFG_BI 0x00000001
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI \
+ board/freescale/ls1021aiot/ls102xa_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
+
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1a000
+#define CONFIG_SPL_STACK 0x1001d000
+#define CONFIG_SPL_PAD_TO 0x1c000
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x40010000
+#endif
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_FSL_CAAM /* Enable CAAM */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * I2C
+ */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * MMC
+ */
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+
+/* SATA */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
+#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
+#endif
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
+ PCI_DEVICE_ID_FREESCALE_AHCI}
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* SPI */
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SPI_FLASH_SPANSION
+
+/* QSPI */
+#define QSPI0_AMBA_BASE 0x40000000
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_SPANSION
+#endif
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
+#define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
+#endif
+
+/*
+ * eTSEC
+ */
+#define CONFIG_TSEC_ENET
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_MII
+#define CONFIG_MII_DEFAULT_TSEC 1
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+
+#define TSEC1_PHY_ADDR 1
+#define TSEC2_PHY_ADDR 3
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC2"
+
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+/* PCIe */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+
+/* Use common FSL Layerscape PCIe code */
+#define CONFIG_PCIE_LAYERSCAPE
+#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#endif
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_CMDLINE_EDITING
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT)
+#undef CONFIG_CMD_IMLS
+#endif
+
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ 12500000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 256
+
+#define CONFIG_FSL_DEVICE_DISABLE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
+"initrd_high=0xffffffff\0" \
+"fdt_high=0xffffffff\0"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MEMINFO
+
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+
+#define CONFIG_LS102XA_STREAM_ID
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (30 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
+
+/*
+ * Environment
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#endif
+
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+
+#ifdef CONFIG_FSL_CAAM
+
+#define CONFIG_CMD_HASH
+
+#define CONFIG_SHA_HW_ACCEL
+
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 105702d..6f857a7 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -15,16 +15,10 @@
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DEEP_SLEEP
-#if defined(CONFIG_DEEP_SLEEP)
-#define CONFIG_SILENT_CONSOLE
-#endif
/*
* Size of malloc() pool
@@ -67,17 +61,6 @@
#endif
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
@@ -105,15 +88,6 @@
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
@@ -146,7 +120,6 @@
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
@@ -161,8 +134,6 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_SYS_HAS_SERDES
-
#define CONFIG_FSL_CAAM /* Enable CAAM */
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
@@ -287,6 +258,13 @@
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_CTL_SYS 0x5
+#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
+#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
+#define QIXIS_RST_FORCE_3 0x45
+#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
+#define QIXIS_PWR_CTL2 0x21
+#define QIXIS_PWR_CTL2_PCTL 0x2
#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
@@ -415,7 +393,6 @@
/*
* MMC
*/
-#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC
@@ -464,13 +441,9 @@
#define CONFIG_FSL_DCU_FB
#ifdef CONFIG_FSL_DCU_FB
-#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
@@ -525,7 +498,6 @@
#endif
/* PCIe */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
@@ -547,7 +519,6 @@
#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif
@@ -555,8 +526,6 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_ARMV7_NONSEC
-#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 90ae770..b48cd00 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -15,15 +15,9 @@
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DEEP_SLEEP
-#ifdef CONFIG_DEEP_SLEEP
-#define CONFIG_SILENT_CONSOLE
-#endif
/*
* Size of malloc() pool
@@ -112,26 +106,13 @@
#endif
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
/*
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image.
*/
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \
- (CONFIG_U_BOOT_HDR_SIZE / 512)
-#else
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */
#define CONFIG_SPL_TEXT_BASE 0x10000000
@@ -178,8 +159,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_HAS_SERDES
-
#define CONFIG_FSL_CAAM /* Enable CAAM */
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
@@ -315,7 +294,6 @@
/*
* MMC
*/
-#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC
@@ -342,13 +320,9 @@
#define CONFIG_FSL_DCU_FB
#ifdef CONFIG_FSL_DCU_FB
-#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
@@ -394,7 +368,6 @@
#endif
/* PCIe */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
@@ -416,7 +389,6 @@
#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif
@@ -424,8 +396,6 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_ARMV7_NONSEC
-#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e55fcb2..3e70464 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -9,16 +9,12 @@
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_FSL_LSCH2
#define CONFIG_LS1043A
#define CONFIG_MP
#define CONFIG_SYS_FSL_CLK
#define CONFIG_GICV2
#include <asm/arch/config.h>
-#ifdef CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_HAS_SERDES
-#endif
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
@@ -28,10 +24,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F 1
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
-#endif
-
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
@@ -60,17 +52,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1d000
@@ -91,15 +72,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
@@ -143,7 +115,6 @@
#define CONFIG_SYS_I2C_MXC_I2C4
/* PCIe */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
@@ -167,7 +138,6 @@
#ifdef CONFIG_PCI
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP
#define CONFIG_E1000
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
@@ -175,11 +145,8 @@
/* Command line configuration */
#define CONFIG_CMD_ENV
-#define CONFIG_MENU
-#define CONFIG_CMD_PXE
/* MMC */
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index a80e33d..561a05a 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -9,9 +9,6 @@
#include "ls1043a_common.h"
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE 0x82000000
#elif defined(CONFIG_QSPI_BOOT)
@@ -42,9 +39,6 @@
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
-#endif
#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
@@ -52,8 +46,6 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_SYS_HAS_SERDES
-
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 70ee046..71c26bd 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -12,7 +12,6 @@
#if defined(CONFIG_FSL_LS_PPA)
#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#define SEC_FIRMWARE_ERET_ADDR_REVERT
-#define CONFIG_ARMV8_PSCI
#define CONFIG_SYS_LS_PPA_FW_IN_XIP
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
@@ -20,9 +19,6 @@
#endif
#endif
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE 0x82000000
#else
@@ -313,7 +309,6 @@
#define SCSI_VEND_ID 0x1b4b
#define SCSI_DEV_ID 0x9170
#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#define CONFIG_PCI
#include <asm/fsl_secure_boot.h>
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
new file mode 100644
index 0000000..40e6af8
--- /dev/null
+++ b/include/configs/ls1046a_common.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1046A_COMMON_H
+#define __LS1046A_COMMON_H
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_MP
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_GICV2
+
+#include <asm/arch/config.h>
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
+
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* SD boot SPL */
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
+#define CONFIG_SPL_STACK 0x10020000
+#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
+#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SYS_MONITOR_LEN 0xa0000
+#endif
+
+/* NAND SPL */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PBL_PAD
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */
+#define CONFIG_SPL_STACK 0x1001f000
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SYS_MONITOR_LEN 0xa0000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_MXC_I2C3
+#define CONFIG_SYS_I2C_MXC_I2C4
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
+
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+
+/* FMan ucode */
+#define CONFIG_SYS_DPAA_FMAN
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+
+#ifdef CONFIG_SD_BOOT
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x40300000
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000000
+#define CONFIG_ENV_SPI_MODE 0x03
+#elif defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x1000000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "console=ttyS0,115200\0" \
+ MTDPARTS_DEFAULT "\0"
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0500 " \
+ MTDPARTS_DEFAULT
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
+#endif /* __LS1046A_COMMON_H */
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
new file mode 100644
index 0000000..29e0aa5
--- /dev/null
+++ b/include/configs/ls1046aqds.h
@@ -0,0 +1,490 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1046AQDS_H__
+#define __LS1046AQDS_H__
+
+#include "ls1046a_common.h"
+
+#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x40010000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x60100000
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_DDR_SPD
+#define SPD_EEPROM_ADDRESS 0x51
+#define CONFIG_SYS_SPD_BUS_NUM 0
+
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+/* DSPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+#define CONFIG_SPI_FLASH_EON /* cs2 */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_CS 0
+#endif
+#endif
+
+/* QSPI */
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHYLIB_10G
+#define RGMII_PHY1_ADDR 0x1
+#define RGMII_PHY2_ADDR 0x2
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+/* PHY address on QSGMII riser card on slot 2 */
+#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
+#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
+#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
+#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI \
+ board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
+#endif
+#endif
+
+/* IFC */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_FSL_IFC
+/*
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
+ */
+#define CONFIG_SYS_FLASH_BASE 0x60000000
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+#endif
+#endif
+
+/* LPUART */
+#ifdef CONFIG_LPUART
+#define CONFIG_LPUART_32B_REG
+#define CFG_UART_MUX_MASK 0x6
+#define CFG_UART_MUX_SHIFT 1
+#define CFG_LPUART_EN 0x2
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+/*
+ * IFC Definitions
+ */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1a) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0xe) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE 0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_NAND \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x7) | \
+ FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0xe) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+ FTIM2_NAND_TREH(0xa) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#endif
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE 0x7fb00000
+#define QIXIS_BASE_PHYS QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_LBMAP_NAND 0x09
+#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_SD_QSPI 0xff
+#define QIXIS_LBMAP_QSPI 0xff
+#define QIXIS_RCW_SRC_NAND 0x110
+#define QIXIS_RCW_SRC_SD 0x040
+#define QIXIS_RCW_SRC_QSPI 0x045
+#define QIXIS_RST_CTL_RESET 0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+
+#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
+#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_MSEL_GPCM | \
+ CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_NOR_MODE_AVD_NOR | \
+ CSOR_NOR_TRHZ_80)
+
+/*
+ * QIXIS Timing parameters for IFC GPCM
+ */
+#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
+ FTIM0_GPCM_TEADC(0x20) | \
+ FTIM0_GPCM_TEAHC(0x10))
+#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
+ FTIM2_GPCM_TCH(0x8) | \
+ FTIM2_GPCM_TWP(0xf0))
+#define CONFIG_SYS_FPGA_FTIM3 0x0
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI 0x77
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR 0x18
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_CH7301 0xC
+#define I2C_MUX_CH5 0xD
+#define I2C_MUX_CH6 0xE
+#define I2C_MUX_CH7 0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_INA220
+/* The lowest and highest voltage allowed for LS1046AQDS */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (30 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x20000
+#endif
+
+#define CONFIG_CMDLINE_TAG
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
+ "e0000 f00000 && bootm $kernel_load"
+#else
+#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
+ "$kernel_size && bootm $kernel_load"
+#endif
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
+ "14m(free)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
+ "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
+ "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
+ "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
+ "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
+ "40m(nor_bank4_fit);7e800000.flash:" \
+ "4m(nand_uboot),36m(nand_kernel)," \
+ "472m(nand_free);spi0.0:2m(uboot)," \
+ "14m(free)"
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1046AQDS_H__ */
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
new file mode 100644
index 0000000..2fe8fc1
--- /dev/null
+++ b/include/configs/ls1046ardb.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1046ARDB_H__
+#define __LS1046ARDB_H__
+
+#include "ls1046a_common.h"
+
+#if defined(CONFIG_FSL_LS_PPA)
+#define CONFIG_ARMV8_PSCI
+#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
+
+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
+#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000
+#endif
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x40100000
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_DDR_SPD
+#define SPD_EEPROM_ADDRESS 0x51
+#define CONFIG_SYS_SPD_BUS_NUM 0
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_EMMC_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
+#endif
+#endif
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* IFC */
+#define CONFIG_FSL_IFC
+
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE 0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_NAND \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x7) | \
+ FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0xe) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+ FTIM2_NAND_TREH(0xa) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/*
+ * CPLD
+ */
+#define CONFIG_SYS_CPLD_BASE 0x7fb00000
+#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+
+#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
+#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_MSEL_GPCM | \
+ CSPR_V)
+#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
+
+/* CPLD Timing parameters for IFC GPCM */
+#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+ FTIM2_GPCM_TCH(0xf) | \
+ FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CPLD_FTIM3 0x0
+
+/* IFC Timing Params */
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define I2C_RETIMER_ADDR 0x18
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
+#endif
+
+/* FMan */
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_AQUANTIA
+#define AQR105_IRQ_MASK 0x80000000
+
+#define RGMII_PHY1_ADDR 0x1
+#define RGMII_PHY2_ADDR 0x2
+
+#define SGMII_PHY1_ADDR 0x3
+#define SGMII_PHY2_ADDR 0x4
+
+#define FM1_10GEC1_PHY_ADDR 0x0
+
+#define CONFIG_ETHPRIME "FM1@DTSEC3"
+#endif
+
+/* QSPI device */
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE (1 << 26)
+#define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_SPI_FLASH_BAR
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \
+ "$kernel_start $kernel_size;" \
+ "bootm $kernel_load"
+
+#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \
+ "15m(u-boot),48m(kernel.itb);" \
+ "7e800000.flash:16m(nand_uboot)," \
+ "48m(nand_kernel),448m(nand_free)"
+
+#endif /* __LS1046ARDB_H__ */
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index ebe1415..2cae966 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -9,16 +9,12 @@
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_FSL_LSCH3
#define CONFIG_MP
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#include <asm/arch/ls2080a_stream_id.h>
#include <asm/arch/config.h>
-#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
-#define CONFIG_SYS_HAS_SERDES
-#endif
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
@@ -50,7 +46,6 @@
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
@@ -153,11 +148,6 @@
#define CONFIG_SYS_NAND_BASE 0x530000000ULL
#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
-/* Debug Server firmware */
-#define CONFIG_FSL_DEBUG_SERVER
-/* 2 sec timeout */
-#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
-
/* MC firmware */
#define CONFIG_FSL_MC_ENET
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
@@ -175,8 +165,7 @@
* It will be used by MC and Debug Server. The MC region must be
* 512MB aligned, so the min size to hide is 512MB.
*/
-#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
-#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024)
+#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024)
#endif
@@ -222,8 +211,6 @@
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
-#define CONFIG_DISPLAY_CPUINFO
-
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -265,17 +252,9 @@
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MAX_SIZE 0x16000
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h
index 16e37bf..cec12ad 100644
--- a/include/configs/ls2080a_emu.h
+++ b/include/configs/ls2080a_emu.h
@@ -9,8 +9,6 @@
#include "ls2080a_common.h"
-#define CONFIG_IDENT_STRING " LS2080A-EMU"
-
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 7f245b5..07be30c 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -9,8 +9,6 @@
#include "ls2080a_common.h"
-#define CONFIG_IDENT_STRING " LS2080A-SIMU"
-
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
@@ -135,7 +133,6 @@
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
/* MMC */
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
@@ -148,9 +145,6 @@
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
/* MC firmware */
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
-
#define CONFIG_SYS_LS_MC_DPL_IN_NOR
#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 5e36ca7..37d5704 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -9,8 +9,6 @@
#include "ls2080a_common.h"
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
@@ -349,17 +347,14 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
-#define CONFIG_PCI /* Enable PCIE */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif
/* MMC */
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b93e919..713e86b 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -12,8 +12,6 @@
#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 2
-#define CONFIG_DISPLAY_BOARDINFO
-
#define I2C_MUX_CH_VOL_MONITOR 0xa
#define I2C_VOL_MONITOR_ADDR 0x38
#define CONFIG_VOL_MONITOR_IR36021_READ
@@ -271,6 +269,7 @@
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_STMICRO
#endif
/*
@@ -292,17 +291,14 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
-#define CONFIG_PCI /* Enable PCIE */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif
/* MMC */
-#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
@@ -320,10 +316,25 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#undef CONFIG_CMDLINE_EDITING
+#include <config_distro_defaults.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(SCSI, scsi, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "scriptaddr=0x80800000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "pxefile_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "ramdisk_addr_r=0x89000000\0" \
"loadaddr=0x80100000\0" \
"kernel_addr=0x100000\0" \
"ramdisk_addr=0x800000\0" \
@@ -333,8 +344,10 @@
"kernel_start=0x581100000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
+ "fdtfile=fsl-ls2080a-rdb.dtb\0" \
"mcinitcmd=fsl_mc start mc 0x580300000" \
- " 0x580800000 \0"
+ " 0x580800000 \0" \
+ BOOTENV
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
@@ -342,6 +355,13 @@
"ramdisk_size=0x2000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=256"
+#undef CONFIG_BOOTCOMMAND
+/* Try to boot an on-NOR kernel first, then do normal distro boot */
+#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \
+ " && cp.b $kernel_start $kernel_load $kernel_size" \
+ " && bootm $kernel_load" \
+ " || run distro_bootcmd"
+
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_PHYLIB_10G
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index e878cbe..0caca4c 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -12,12 +12,10 @@
* Version number information
*/
#if defined(CONFIG_LSCHLV2)
-#define CONFIG_IDENT_STRING " LS-CHLv2"
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
#define CONFIG_MACH_TYPE 3006
#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
#elif defined(CONFIG_LSXHL)
-#define CONFIG_IDENT_STRING " LS-XHL"
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
#define CONFIG_MACH_TYPE 2663
/* CONFIG_SYS_TCLK is 200000000 by default */
@@ -38,8 +36,6 @@
#define CONFIG_KIRKWOOD_GPIO
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
/*
* Enable u-boot API for standalone programs.
diff --git a/include/configs/luan.h b/include/configs/luan.h
index e22d0e8..2ab6f58 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -159,9 +159,7 @@
#if defined(CONFIG_CMD_PCI)
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* Board-specific PCI */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index da63842..638682f 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -12,11 +12,6 @@
#define __CONFIG_H
/*
- * Liebherr extra version info
- */
-#define CONFIG_IDENT_STRING " - v2.0"
-
-/*
* High Level Configuration Options
*/
#define CONFIG_LWMON5 1 /* Board is lwmon5 */
@@ -260,7 +255,6 @@
/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
/*
* I2C
@@ -359,17 +353,12 @@
#define CONFIG_PHY1_ADDR 1
/* Video console */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
#define CONFIG_VIDEO_MB862xx_ACCEL
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
#define VIDEO_FB_16BPP_PIXEL_SWAP
#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
/*
@@ -437,8 +426,6 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
-
#ifndef DEBUG
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
#endif
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index cdd24cd..25884b4 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -16,7 +16,6 @@
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
@@ -25,7 +24,6 @@
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_VIDEO
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
@@ -46,7 +44,6 @@
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_RBTREE
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index fd47a72..8ec98fd 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -13,7 +13,6 @@
#include <asm/arch/imx-regs.h>
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_NO_FLASH
@@ -24,7 +23,6 @@
/*
* U-Boot Commands
*/
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
@@ -33,7 +31,6 @@
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_CMD_SATA
-#define CONFIG_VIDEO
/*
* Memory configurations
@@ -85,7 +82,6 @@
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
@@ -115,7 +111,6 @@
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_RBTREE
@@ -203,9 +198,6 @@
*/
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SPLASH_SCREEN
@@ -239,11 +231,6 @@
#define CONFIG_SPL_TEXT_BASE 0x70008000
#define CONFIG_SPL_PAD_TO 0x8000
#define CONFIG_SPL_STACK 0x70004000
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index a696c1a..de83d6c 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -21,7 +21,6 @@
*/
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
-/*#define CONFIG_LCD*/
/*
* Memory configurations
@@ -82,14 +81,12 @@
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 24
#define CONFIG_ATMEL_HLCD
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif
/*
* SD/MMC
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
@@ -216,16 +213,9 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index dcfe3d7..7c358bc 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -252,14 +252,10 @@
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/malta.h b/include/configs/malta.h
index fc4baba..65cd321 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -12,14 +12,11 @@
*/
#define CONFIG_MALTA
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MEMSIZE_IN_BYTES
-#define CONFIG_PCI
#define CONFIG_PCI_GT64120
#define CONFIG_PCI_MSC01
-#define CONFIG_PCI_PNP
#define CONFIG_PCNET
#define CONFIG_PCNET_79C973
#define PCNET_HAS_PROM
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 47d2948..9f4308f 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -46,7 +46,6 @@
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
/*
@@ -84,14 +83,7 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 22a54c7..f15abd3 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -15,7 +15,6 @@
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP3_MCX /* working with mcx */
#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
@@ -36,12 +35,6 @@
*/
#define CONFIG_SYS_TEXT_BASE 0x80008000
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -88,7 +81,6 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
@@ -109,7 +101,6 @@
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
@@ -320,19 +311,10 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
@@ -344,7 +326,6 @@
#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
@@ -381,13 +362,9 @@
#define CONFIG_NET_RETRY_COUNT 10
#endif
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_CMD_BMP
#define CONFIG_VIDEO_OMAP3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif /* __CONFIG_H */
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 4211e72..4f90c34 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -15,7 +15,6 @@
#define __CONFIG_H
#define CONFIG_MECP5123 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the MECP5123 board:
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index ae7ca3b..d42976b 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h
@@ -20,7 +20,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index df76a20..6b9bb6a 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -52,8 +52,6 @@
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */
-#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */
#define CONFIG_PREBOOT /* enable preboot variable */
/*
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index e5bf700..7abffdb 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -177,7 +177,6 @@
#if defined(FLASH)
# define CONFIG_CMD_JFFS2
-# define CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
# if !defined(RAMENV)
@@ -192,7 +191,6 @@
# endif
#else
# undef CONFIG_CMD_JFFS2
-# undef CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
#endif
#endif
@@ -202,7 +200,6 @@
#endif
#if defined(CONFIG_CMD_UBIFS)
-# define CONFIG_CMD_UBI
# define CONFIG_LZO
#endif
@@ -259,8 +256,6 @@
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
/* Enable flat device tree support */
#define CONFIG_LMB 1
@@ -285,24 +280,17 @@
/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
#define CONFIG_SPL_RAM_DEVICE
#ifdef CONFIG_SYS_FLASH_BASE
-# define CONFIG_SPL_NOR_SUPPORT
# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
#endif
/* for booting directly linux */
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
- 0x60000)
#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
0x40000)
#define CONFIG_SYS_FDT_SIZE (16<<10)
diff --git a/include/configs/miniarm_rk3288.h b/include/configs/miniarm_rk3288.h
index 342557f..9451365 100644
--- a/include/configs/miniarm_rk3288.h
+++ b/include/configs/miniarm_rk3288.h
@@ -10,10 +10,13 @@
#define ROCKCHIP_DEVICE_SETTINGS
#include <configs/rk3288_common.h>
-#define CONFIG_SPL_MMC_SUPPORT
+#undef BOOT_TARGET_DEVICES
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
/* SPL @ 32k for ~36k
* ENV @ 96k
* u-boot @ 128K
@@ -21,6 +24,5 @@
#define CONFIG_ENV_OFFSET (96 * 1024)
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 95ad128..5b17fd7 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -19,19 +19,15 @@
#define CONFIG_SMSC_LPC47M
-#define CONFIG_PCI_PNP
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
- "stdout=vga,serial\0" \
- "stderr=vga,serial\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
+ "stdout=vidconsole,serial\0" \
+ "stderr=vidconsole,serial\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_MMC
-#define CONFIG_SDHCI
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SDMA
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index bad85ba..917350f 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -17,7 +17,6 @@
/* CPU and board */
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index e329105..c36141a 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -12,7 +12,6 @@
#define __CONFIG_H
#define CONFIG_MPC5121ADS 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the MPC5121ADS board:
@@ -37,11 +36,7 @@
/* video */
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
-#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
@@ -52,7 +47,6 @@
#define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
#else
#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
-#define CONFIG_PCI
#endif
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
@@ -332,8 +326,6 @@
#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 57cb795..76667d7 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -329,12 +327,9 @@
/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM 1
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
index 1a8909a..0d37912 100644
--- a/include/configs/mpr2.h
+++ b/include/configs/mpr2.h
@@ -22,6 +22,8 @@
#define CONFIG_CPU_SH7720 1
#define CONFIG_MPR2 1
+#define CONFIG_DISPLAY_BOARDINFO
+
/* U-Boot internals */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index d136726..87f8712 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -21,6 +21,7 @@
#define CONFIG_BOOTFILE "/boot/zImage"
#define CONFIG_LOADADDR 0x8E000000
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 9b0c166..181d021 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -18,6 +18,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
@@ -40,9 +41,6 @@
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index c0fb16d..6268d73 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -15,6 +15,8 @@
#define CONFIG_MS7750SE 1
#define __LITTLE_ENDIAN__ 1
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* Command line configuration.
*/
diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h
index 29564d7..2420612 100644
--- a/include/configs/mt_ventoux.h
+++ b/include/configs/mt_ventoux.h
@@ -51,14 +51,10 @@
#define CONFIG_FPGA_DELAY() udelay(1)
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_CMD_BMP
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
"bootcmd=run net_nfs\0"
diff --git a/include/configs/munices.h b/include/configs/munices.h
index 3e4c062..5a6d004 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -168,7 +168,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
-#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_CMDLINE_EDITING 1
/*
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index dd223be..b28030c 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -83,11 +83,9 @@
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
@@ -137,7 +135,6 @@
*/
#ifdef CONFIG_SYS_MVFS
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
new file mode 100644
index 0000000..8ab5bbe
--- /dev/null
+++ b/include/configs/mvebu_armada-8k.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_MVEBU_ARMADA_8K_H
+#define _CONFIG_MVEBU_ARMADA_8K_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/* auto boot */
+#define CONFIG_PREBOOT
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200, 230400, 460800, 921600 }
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
+
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
+#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* End of 16M scrubbed by training in bootrom */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
+
+/*
+ * SPI Flash configuration
+ */
+#define CONFIG_KIRKWOOD_SPI
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+
+/* Environment in SPI NOR flash */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
+
+/* USB 2.0 */
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
+/* USB 3.0 */
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS + \
+ CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS)
+
+/* USB ethernet */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_RTL8152
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+#define CONFIG_SUPPORT_VFAT
+
+/* DISK Partition support */
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+/*
+ * PCI configuration
+ */
+#ifdef CONFIG_PCIE_DW_MVEBU
+#define CONFIG_E1000
+#define CONFIG_CMD_PCI
+#endif
+
+#endif /* _CONFIG_MVEBU_ARMADA_8K_H */
diff --git a/include/configs/mvebu_db-88f3720.h b/include/configs/mvebu_db-88f3720.h
new file mode 100644
index 0000000..7ddde8c
--- /dev/null
+++ b/include/configs/mvebu_db-88f3720.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_MVEBU_DB_88F3720_H
+#define _CONFIG_MVEBU_DB_88F3720_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/* auto boot */
+#define CONFIG_PREBOOT
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200, 230400, 460800, 921600 }
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
+
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
+#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* End of 16M scrubbed by training in bootrom */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
+
+/*
+ * I2C
+ */
+#define CONFIG_I2C_MV
+#define CONFIG_SYS_I2C_SLAVE 0x0
+
+/*
+ * SPI Flash configuration
+ */
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+
+/* Environment in SPI NOR flash */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
+
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT 200
+#define CONFIG_NET_RETRY_COUNT 50
+
+/* USB 2.0 */
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
+/* USB 3.0 */
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS + \
+ CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS)
+
+/* USB ethernet */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_RTL8152
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+#define CONFIG_SUPPORT_VFAT
+
+/* DISK Partition support */
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+#endif /* _CONFIG_MVEBU_DB_88F3720_H */
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index 9971c81..36ff7ce 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -12,7 +12,6 @@
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_LED
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index 0de5737..ecb6e4d 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -15,11 +15,8 @@
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
-#define CONFIG_VIDEO
-
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index ea0d605..3853c05 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -20,9 +20,6 @@
#define CONFIG_SYS_TIMER_COUNTER \
(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -90,7 +87,6 @@
#define CONFIG_ENV_OVERWRITE
/* ESDHC driver */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
@@ -121,8 +117,6 @@
#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_DEFAULT_FDT_FILE "imx25-pdk.dtb"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index b2bf599..5963d39 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -17,13 +17,11 @@
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_VIDEO
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
@@ -69,7 +67,6 @@
/* UBI and NAND partitioning */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_RBTREE
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 8de9dec..28fa513 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -14,9 +14,6 @@
/* High Level Configuration Options */
#define CONFIG_MX31 1 /* This is a mx31 */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_TEXT_BASE 0xA0000000
#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index a81dd78..1401760 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -19,9 +19,6 @@
/* High Level Configuration Options */
#define CONFIG_MX31 /* This is a mx31 */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -31,9 +28,6 @@
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 2048
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x87dc0000
#define CONFIG_SYS_TEXT_BASE 0x87e00000
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index e57912a..c0fb8d1 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -18,7 +18,6 @@
/* High Level Configuration Options */
#define CONFIG_MX35
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_FSL_CLK
/* Set TEXT at the beginning of the NOR flash */
@@ -220,7 +219,6 @@
#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
/* mmc driver */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 072aafd..b62360b 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -15,9 +15,6 @@
#define CONFIG_MX51 /* in a mx51 */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_TEXT_BASE 0x97800000
@@ -70,8 +67,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#define CONFIG_MMC
-
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
@@ -96,12 +91,7 @@
/* Framebuffer and LCD */
#define CONFIG_PREBOOT
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 0419050..d84d524 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -11,9 +11,6 @@
#define CONFIG_MX53
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
#include <asm/arch/imx-regs.h>
@@ -56,7 +53,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
@@ -81,8 +77,6 @@
#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
-#define CONFIG_DEFAULT_FDT_FILE "imx53-ard.dtb"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=zImage\0" \
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
new file mode 100644
index 0000000..8fec94e
--- /dev/null
+++ b/include/configs/mx53cx9020.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Configuration settings for Beckhoff CX9020.
+ *
+ * Based on Freescale's Linux i.MX mx53loco.h file:
+ * Copyright (C) 2010-2011 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_MXC_UART_BASE UART2_BASE
+
+#define CONFIG_FPGA_COUNT 1
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+#define CONFIG_GENERIC_MMC
+
+/* bootz: zImage/initrd.img support */
+#define CONFIG_DOS_PARTITION
+
+/* Eth Configs */
+#define CONFIG_MII
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_FEC_MXC_PHYADDR 0x1F
+
+/* USB Configs */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE 0x77800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr=0x71ff0000\0" \
+ "rdaddr=0x72000000\0" \
+ "console=ttymxc1,115200\0" \
+ "uenv=/boot/uEnv.txt\0" \
+ "optargs=\0" \
+ "cmdline=\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcrootfstype=ext4 rootwait fixrtc\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline}\0" \
+ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadrd=load mmc ${bootpart} ${rdaddr} ${bootdir}/${rdfile};" \
+ "setenv rdsize ${filesize}\0" \
+ "loadfdt=echo loading ${fdt_path} ...;" \
+ "load mmc ${bootpart} ${fdt_addr} ${fdt_path}\0" \
+ "mmcboot=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "echo Checking for: ${uenv} ...;" \
+ "setenv bootpart ${mmcdev}:${mmcpart};" \
+ "if test -e mmc ${bootpart} ${uenv}; then " \
+ "load mmc ${bootpart} ${loadaddr} ${uenv};" \
+ "env import -t ${loadaddr} ${filesize};" \
+ "echo Loaded environment from ${uenv};" \
+ "if test -n ${dtb}; then " \
+ "setenv fdt_file ${dtb};" \
+ "echo Using: dtb=${fdt_file} ...;" \
+ "fi;" \
+ "echo Checking for uname_r in ${uenv}...;" \
+ "if test -n ${uname_r}; then " \
+ "echo Running uname_boot ...;" \
+ "run uname_boot;" \
+ "fi;" \
+ "fi;" \
+ "fi;\0" \
+ "uname_boot="\
+ "setenv bootdir /boot; " \
+ "setenv bootfile vmlinuz-${uname_r}; " \
+ "setenv ccatfile /boot/ccat.rbf; " \
+ "echo loading CCAT firmware from ${ccatfile}; " \
+ "load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
+ "echo loading ${bootdir}/${bootfile} ...; " \
+ "run loadimage;" \
+ "setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \
+ "if test -e mmc ${bootpart} ${fdt_path}; then " \
+ "run loadfdt;" \
+ "else " \
+ "echo; echo unable to find ${fdt_file} ...;" \
+ "echo booting legacy ...;"\
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr}] ... ;" \
+ "bootz ${loadaddr}; " \
+ "fi;" \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} - ${fdt_addr}] ... ;" \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "run mmcboot;"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x70000000
+#define CONFIG_SYS_MEMTEST_END 0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2 CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE (gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* Framebuffer and LCD */
+#define CONFIG_PREBOOT
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 200000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 5e1c597..aa82928 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -11,9 +11,6 @@
#define CONFIG_MX53
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK
#include <asm/arch/imx-regs.h>
@@ -55,7 +52,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index d259f53..6cc5f0f 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -12,8 +12,6 @@
#define CONFIG_MX53
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
#include <asm/arch/imx-regs.h>
@@ -40,7 +38,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
@@ -215,12 +212,7 @@
/* Framebuffer and LCD */
#define CONFIG_PREBOOT
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 632ebba..ad4964c 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -11,9 +11,6 @@
#define CONFIG_MX53
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
#include <asm/arch/imx-regs.h>
@@ -46,7 +43,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index fb49322..0a1563c 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -35,8 +35,6 @@
#define CONFIG_MX6
#endif
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_FSL_CLK
/* ATAGs */
@@ -46,7 +44,8 @@
#define CONFIG_REVISION_TAG
/* Boot options */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL))
#define CONFIG_LOADADDR 0x82000000
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x87800000
@@ -83,7 +82,6 @@
#define CONFIG_MXC_GPIO
/* MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FSL_ESDHC
@@ -93,4 +91,14 @@
#define CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
+/* Secure boot (HAB) support */
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE 0x2000
+#define CONFIG_FSL_CAAM
+#define CONFIG_CMD_DEKBLOB
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#endif
+#endif
+
#endif
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 366b5b9..446b3bc 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -11,8 +11,6 @@
#include <config_distro_defaults.h>
#include "mx6_common.h"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
#define CONFIG_IMX_THERMAL
@@ -35,12 +33,8 @@
#define CONFIG_PHY_ATHEROS
/* Framebuffer */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IPUV3_CLK 260000000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
@@ -50,7 +44,6 @@
#define CONFIG_IMX_HDMI
#define CONFIG_CMD_HDMIDETECT
#define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_CONSOLE_MUX
/* USB */
#define CONFIG_USB_EHCI
@@ -59,7 +52,6 @@
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT \
"if hdmidet; then " \
@@ -76,7 +68,7 @@
/* Command definition */
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc0"
+#define CONSOLE_DEV "ttymxc0"
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */
@@ -94,7 +86,7 @@
"initrd_high=0xffffffff\0" \
"fdt_high=0xffffffff\0" \
"ip_dyn=yes\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV "\0" \
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"update_sd_firmware=" \
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 9cf3c2c..f849f34 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -11,7 +11,7 @@
#define CONFIG_MACH_TYPE 3529
#define CONFIG_MXC_UART_BASE UART4_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc3"
+#define CONSOLE_DEV "ttymxc3"
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
/* USB Configs */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 1ee880d..e404d5b 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -74,7 +74,7 @@
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV "\0" \
"dfuspi=dfu 0 sf 0:0:10000000:0\0" \
"dfu_alt_info_spl=spl raw 0x400\0" \
"dfu_alt_info_img=u-boot raw 0x10000\0" \
@@ -208,12 +208,7 @@
#endif
/* Framebuffer */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
@@ -238,11 +233,6 @@
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
-
-/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
-#define CONFIG_DFU_SF
#endif
#endif /* __MX6QSABRE_COMMON_CONFIG_H */
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index d3b10e0..10c229d 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -10,20 +10,30 @@
#define __MX6QSABRESD_CONFIG_H
#ifdef CONFIG_SPL
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
+#undef CONFIG_SPL_EXT_SUPPORT
#endif
#define CONFIG_MACH_TYPE 3980
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc0"
+#define CONSOLE_DEV "ttymxc0"
#define CONFIG_MMCROOT "/dev/mmcblk1p2"
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#include "mx6sabre_common.h"
+/* Falcon Mode */
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
+#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
+
#define CONFIG_SYS_FSL_USDHC_NUM 3
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
@@ -31,8 +41,6 @@
#define CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 13589df..501d7de 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -12,8 +12,6 @@
#include "mx6_common.h"
#ifdef CONFIG_SPL
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
#endif
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
new file mode 100644
index 0000000..b9f25cf
--- /dev/null
+++ b/include/configs/mx6sllevk.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* I2C Configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "epdc_waveform=epdc_splash.bin\0" \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6sll-evk.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=1\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "usb start; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE SZ_2G
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */
+#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
+
+#define CONFIG_ENV_OFFSET (12 * SZ_64K)
+#define CONFIG_ENV_IS_IN_MMC
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IOMUX_LPSR
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 274cb36..c30e3dd 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -173,7 +173,6 @@
#define CONFIG_IMX_THERMAL
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SYS_FSL_QSPI_AHB
#define CONFIG_SF_DEFAULT_BUS 0
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 86987df..d423880 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -12,8 +12,6 @@
#include "mx6_common.h"
#ifdef CONFIG_SPL
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
#endif
@@ -185,8 +183,6 @@
#define CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
@@ -207,14 +203,9 @@
#endif
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_CMD_BMP
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 614de5f..c08294c 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -16,15 +16,10 @@
#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
/* SPL options */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
@@ -188,15 +183,11 @@
#ifndef CONFIG_SYS_DCACHE_OFF
#endif
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SPI_FLASH_STMICRO
#define FSL_QSPI_FLASH_NUM 1
#define FSL_QSPI_FLASH_SIZE SZ_32M
#endif
@@ -234,14 +225,9 @@
#define CONFIG_IMX_THERMAL
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_CMD_BMP
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
new file mode 100644
index 0000000..f06d889
--- /dev/null
+++ b/include/configs/mx6ullevk.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __MX6ULLEVK_CONFIG_H
+#define __MX6ULLEVK_CONFIG_H
+
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/imx-common/gpio.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+#define PHYS_SDRAM_SIZE SZ_512M
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+
+/* NAND pin conflicts with usdhc2 */
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#endif
+#endif
+
+/* I2C configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6ull-14x14-evk.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_OFFSET (12 * SZ_64K)
+
+#define CONFIG_CMD_BMODE
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IOMUX_LPSR
+
+#define CONFIG_SOFT_SPI
+
+#endif
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 4b1077c..16fedfb 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -31,8 +31,6 @@
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_LOADADDR 0x80800000
#define CONFIG_SYS_TEXT_BASE 0x87800000
@@ -62,7 +60,6 @@
#define CONFIG_MXC_UART
/* MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FSL_ESDHC
@@ -74,4 +71,11 @@
#define CONFIG_ARMV7_SECURE_BASE 0x00900000
+/* Secure boot (HAB) support */
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE 0x2000
+#define CONFIG_FSL_CAAM
+#define CONFIG_CMD_DEKBLOB
+#endif
+
#endif
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index f6a636d..ca5f9db 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -22,12 +22,6 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Uncomment to enable secure boot support */
-/* #define CONFIG_SECURE_BOOT */
-#define CONFIG_CSF_SIZE 0x4000
-
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_MII
@@ -207,6 +201,9 @@
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
+/* MXC SPI driver support */
+#define CONFIG_MXC_SPI
+
/*
* If want to use nand, define CONFIG_NAND_MXS and rework board
* to support nand, since emmc has pin conflicts with nand
@@ -252,19 +249,9 @@
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
-#define CONFIG_DFU_RAM
-
-#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_CMD_BMP
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index d80dc5e..04c3ce9 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -49,10 +49,6 @@
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
/* Memory sizes */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
@@ -147,16 +143,11 @@
/* LCD */
#ifdef CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
index cca2324..7cfdacd 100644
--- a/include/configs/nas220.h
+++ b/include/configs/nas220.h
@@ -17,7 +17,6 @@
*/
#define MACH_TYPE_NAS220 MACH_TYPE_RD88F6192_NAS
#define CONFIG_MACH_TYPE MACH_TYPE_NAS220
-#define CONFIG_IDENT_STRING "\nNAS 220"
/*
* High Level Configuration Options (easy to change)
@@ -111,7 +110,6 @@
#define CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_LZO
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 4f244a9..8b6ee92 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -17,7 +17,6 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME neo
-#define CONFIG_IDENT_STRING " neo 0.02"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 6ad4a3e..c22fed7 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -85,19 +85,13 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
/* Miscellaneous commands */
#define CONFIG_CMD_BMODE
/* Framebuffer and LCD */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
@@ -106,7 +100,6 @@
#define CONFIG_BMP_16BPP
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_CMD_HDMIDETECT
-#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
@@ -312,8 +305,6 @@
* PCI express
*/
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#endif
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index cdae544..99ce60f 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -27,7 +27,6 @@
#define CONFIG_OMAP3430 /* which is in a 3430 */
#define CONFIG_OMAP3_RX51 /* working with RX51 */
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
-#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
@@ -49,12 +48,6 @@
#include <asm/arch/mem.h>
#include <linux/stringify.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -100,7 +93,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
@@ -118,7 +110,6 @@
#define CONFIG_USBD_MANUFACTURER "Nokia"
#define CONFIG_USBD_PRODUCT_NAME "N900"
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_NO_FLASH
/* commands to include */
@@ -126,7 +117,6 @@
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_CMD_BOOTMENU /* ANSI terminal Boot Menu */
#define CONFIG_CMD_CLEAR /* ANSI terminal clear screen command */
#ifdef ONENAND_SUPPORT
@@ -135,7 +125,6 @@
#define CONFIG_CMD_MTDPARTS /* mtd parts support */
#ifdef UBIFS_SUPPORT
-#define CONFIG_CMD_UBI /* UBI Support */
#define CONFIG_CMD_UBIFS /* UBIFS Support */
#endif
@@ -232,13 +221,9 @@
* Framebuffer
*/
/* Video console */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_CFB_CONSOLE_ANSI /* Enable ANSI escape codes in framebuffer */
#define CONFIG_VIDEO_LOGO
#define VIDEO_FB_16BPP_PIXEL_SWAP
#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
/* functions for cfb_console */
@@ -377,7 +362,6 @@
"run attachboot;" \
"echo"
-#define CONFIG_MENU
#define CONFIG_MENU_SHOW
/*
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 13a7074..51b6687 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -24,7 +24,6 @@
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SATA
-#define CONFIG_VIDEO
/* U-Boot general configurations */
@@ -72,8 +71,6 @@
#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
/* SPL */
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h" /* common IMX6 SPL configuration */
/* Ethernet Configuration */
@@ -113,8 +110,6 @@
/* PCI express */
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29)
@@ -145,8 +140,6 @@
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
@@ -164,16 +157,12 @@
/* Video output */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_CMD_HDMIDETECT
-#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#endif
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index c548ee1..ae49054 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -25,7 +25,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 8913784..c51ea3d 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -17,7 +17,6 @@
* High Level Configuration Options
*/
#define CONFIG_MPC5200
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
@@ -50,8 +49,6 @@
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-#undef CONFIG_PCI
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
@@ -95,8 +92,8 @@
#undef CONFIG_BOOTARGS
-#if !defined(CONFIG_CONSOLE_DEV)
-#define CONFIG_CONSOLE_DEV "ttyPSC1"
+#if !defined(CONSOLE_DEV)
+#define CONSOLE_DEV "ttyPSC1"
#endif
/*
@@ -131,7 +128,7 @@
"addmem=setenv bootargs ${bootargs} ${memlimit}\0" \
"addmisc=sete bootargs ${bootargs} ${miscargs}\0" \
"addtty=sete bootargs ${bootargs} console=" \
- CONFIG_CONSOLE_DEV ",${baudrate}\0" \
+ CONSOLE_DEV ",${baudrate}\0" \
"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
"kernel_addr_r=600000\0" \
"initrd_high=0x03e00000\0" \
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
index bf5df9c..1d5b3d5 100644
--- a/include/configs/odroid-c2.h
+++ b/include/configs/odroid-c2.h
@@ -8,8 +8,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_IDENT_STRING " odroid-c2"
-
/* Serial setup */
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index a28244d..2828f07 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -43,8 +43,6 @@
#define CONFIG_BAUDRATE 115200
/* Console configuration */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run autoboot"
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 5196d58..40b48f7 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -12,7 +12,6 @@
#include <configs/exynos5-common.h>
#undef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_IDENT_STRING " for ODROID-XU3"
#define CONFIG_BOARD_COMMON
@@ -46,8 +45,6 @@
#define CONFIG_USB_EHCI_EXYNOS
/* DFU */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define DFU_MANIFEST_POLL_TIMEOUT 25000
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index c17dcf5..9850aa6 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -29,12 +29,6 @@
#include <configs/ti_omap3_common.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
@@ -110,11 +104,52 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run distro_bootcmd; " \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run userbutton; then " \
+ "setenv bootenv uEnv.txt;" \
+ "else " \
+ "setenv bootenv user.txt;" \
+ "fi;" \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot;" \
+ "fi;" \
+ "fi; " \
+ "fi;" \
+ "run nandboot;" \
+ "setenv bootfile zImage;" \
+ "if run loadimage; then " \
+ "run loadfdt;" \
+ "run mmcbootz; " \
+ "fi; " \
+
+#include <config_distro_bootcmd.h>
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
+ "kernel_addr_r=0x80200000\0" \
"rdaddr=0x81000000\0" \
+ "initrd_addr_r=0x81000000\0" \
"fdt_high=0xffffffff\0" \
"fdtaddr=0x80f80000\0" \
+ "fdt_addr_r=0x80f80000\0" \
"usbtty=cdc_acm\0" \
"bootfile=uImage\0" \
"ramdisk=ramdisk.gz\0" \
@@ -209,39 +244,8 @@
"userbutton=if gpio input 173; then run userbutton_xm; " \
"else run userbutton_nonxm; fi;\0" \
"userbutton_xm=gpio input 4;\0" \
- "userbutton_nonxm=gpio input 7;\0"
-/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run userbutton; then " \
- "setenv bootenv uEnv.txt;" \
- "else " \
- "setenv bootenv user.txt;" \
- "fi;" \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot;" \
- "fi;" \
- "fi; " \
- "fi;" \
- "run nandboot;" \
- "setenv bootfile zImage;" \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcbootz; " \
- "fi; " \
+ "userbutton_nonxm=gpio input 7;\0" \
+ BOOTENV
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index 4310bad..09f4ec0 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -40,12 +40,6 @@
#include <configs/ti_omap3_common.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index b134ac9..1a67584 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -35,10 +35,6 @@
*/
#define CONFIG_SYS_LONGHELP
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -51,15 +47,10 @@
*/
/* MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
/* SPL */
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
@@ -78,7 +69,6 @@
/* NAND SPL */
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
@@ -101,7 +91,6 @@
*/
#define CONFIG_OMAP /* This is TI OMAP core */
#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
@@ -247,7 +236,6 @@
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID 0x0451
@@ -349,14 +337,8 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 3389bf3..30d3aa8 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -23,12 +23,6 @@
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
@@ -65,7 +59,6 @@
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID 0x0451
@@ -75,7 +68,6 @@
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_UBI
#ifndef CONFIG_SPL_BUILD
@@ -116,13 +108,11 @@
#define CONFIG_SYS_MTDPARTS_RUNTIME
/* OneNAND config */
-#define CONFIG_SPL_ONENAND_SUPPORT
#define CONFIG_USE_ONENAND_BOARD_INIT
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
/* NAND config */
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
@@ -167,6 +157,4 @@
#define CONFIG_UBIFS_SILENCE_MSG 1
#define CONFIG_ENV_SIZE (32*1024)
-#undef CONFIG_SPL_EXT_SUPPORT
-
#endif /* __IGEP00X0_H */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 496da17..b38811e 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -15,19 +15,6 @@
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs. We use this rather than the inherited defines from
- * ti_armv7_common.h for backwards compatibility.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80100000
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-
#include <configs/ti_omap3_common.h>
/*
@@ -38,10 +25,6 @@
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
-/* Display CPU and Board information */
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
@@ -93,7 +76,6 @@
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
@@ -126,34 +108,17 @@
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO),"\
- "1920k(u-boot),128k(u-boot-env),"\
- "4m(kernel),-(fs)"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:"\
+ "512k(MLO),"\
+ "1792k(u-boot),"\
+ "128k(spl-os)," \
+ "128k(u-boot-env),"\
+ "6m(kernel),-(fs)"
#endif
/* Environment information */
-/*
- * PREBOOT assumes the 4.3" display is attached. User can interrupt
- * and modify display variable to suit their needs.
- */
#define CONFIG_PREBOOT \
- "echo ======================NOTICE============================;"\
- "echo \"The u-boot environment is not set.\";" \
- "echo \"If using a display a valid display variable for your panel\";" \
- "echo \"needs to be set.\";" \
- "echo \"Valid display options are:\";" \
- "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
- "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
- "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
- "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
- "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
- "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
- "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
- "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
- "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
- "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
- "setenv display 15;" \
"setenv preboot;" \
"nand unlock;" \
"saveenv;"
@@ -178,7 +143,6 @@
"else run defaultboot; fi\0" \
"defaultboot=run mmcramboot\0" \
"consoledevice=ttyO0\0" \
- "display=15\0" \
"setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
"dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
"rotation=0\0" \
@@ -188,7 +152,7 @@
"fi\0" \
"optargs=ignore_loglevel early_printk no_console_suspend\0" \
"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
+ "common_bootargs=setenv bootargs ${bootargs} " \
"${optargs};" \
"run addmtdparts; " \
"run vrfb_arg\0" \
@@ -214,6 +178,12 @@
"${optargs} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
+ "nfsargs=run setconsole; setenv serverip ${tftpserver}; " \
+ "setenv bootargs console=${console} root=/dev/nfs " \
+ "nfsroot=${nfsrootpath} " \
+ "ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \
+ "nfsrootpath=/opt/nfs-exports/omap\0" \
+ "autoload=no\0" \
"fdtaddr=0x86000000\0" \
"loadfdtimage=mmc rescan; " \
"fatload mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
@@ -238,14 +208,21 @@
"run loadzimage; " \
"run loadramdisk; " \
"run loadfdtimage; " \
- "bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr}\0; " \
+ "bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr};\0" \
"tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
"run ramargs; " \
"run common_bootargs; " \
"run dump_bootargs; " \
- "tftpboot ${loadaddr} ${uimage}; " \
+ "tftpboot ${loadaddr} ${zimage}; " \
"tftpboot ${ramdiskaddr} ${ramdiskimage}; " \
- "bootm ${loadaddr} ${ramdiskaddr}\0"
+ "bootm ${loadaddr} ${ramdiskaddr}\0" \
+ "tftpbootz=echo 'Booting kernel NFS rootfs...'; " \
+ "dhcp;" \
+ "run nfsargs;" \
+ "run common_bootargs;" \
+ "run dump_bootargs;" \
+ "tftpboot $loadaddr zImage;" \
+ "bootz $loadaddr\0"
#define CONFIG_BOOTCOMMAND \
"run autoboot"
@@ -263,8 +240,6 @@
/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
#endif
/* Monitor at start of flash */
@@ -272,7 +247,6 @@
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 8dffa89..ebf7dd0 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -20,10 +20,6 @@
#define CONFIG_BCH
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* call misc_init_r */
#define CONFIG_MISC_INIT_R
@@ -59,7 +55,6 @@
/* commands to include */
#ifdef CONFIG_NAND
-#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index b664319..ba7d3cd 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -18,18 +18,11 @@
#include <configs/ti_omap3_common.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
#define CONFIG_SYS_DEVICE_NULLDEV 1
/*
@@ -69,7 +62,6 @@
#define CONFIG_SYS_NAND_OOBSIZE 64
#ifdef CONFIG_NAND
-#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 6397051..aa27a9e 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -26,17 +26,10 @@
/* Remove SPL boot option - we do not support that on LDP yet */
#undef CONFIG_SPL_FRAMEWORK
-#undef CONFIG_SPL_OS_BOOT
/* Generic NAND definition conflicts with debug_base */
#undef CONFIG_SYS_NAND_BASE
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
#define CONFIG_MISC_INIT_R
#define CONFIG_REVISION_TAG 1
@@ -55,7 +48,6 @@
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID 0x0451
#define CONFIG_USBD_PRODUCTID 0x5678
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index c126990..736d804 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -12,6 +12,8 @@
#ifndef __CONFIG_OMAP5_EVM_H
#define __CONFIG_OMAP5_EVM_H
+#include <environment/ti/dfu.h>
+
#ifndef CONFIG_SPL_BUILD
/* Define the default GPT table for eMMC */
#define PARTS_DEFAULT \
@@ -19,41 +21,6 @@
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
#endif
-#define DFU_ALT_INFO_MMC \
- "dfu_alt_info_mmc=" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
- "dfu_alt_info_emmc=" \
- "rawemmc raw 0 3751936;" \
- "boot part 1 1;" \
- "rootfs part 1 2;" \
- "MLO fat 1 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 1 1;" \
- "spl-os-image fat 1 1;" \
- "u-boot.img fat 1 1;" \
- "uEnv.txt fat 1 1\0"
-
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0x4000000;" \
- "fdt ram 0x80f80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
-
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_MMC \
@@ -96,12 +63,6 @@
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
-/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_RAM
-
-#define CONFIG_DFU_MMC
-
/* Enabled commands */
/* USB Networking options */
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 43afecd..cdc93c3 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -75,10 +75,51 @@
#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLM 24
+#define CONFIG_SYS_DA850_PLL0_PLLM 37
#define CONFIG_SYS_DA850_PLL1_PLLM 21
/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+ DV_DDR_PHY_EXT_STRBEN | \
+ (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
+ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
+ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
+ (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
+ (4 << DV_DDR_SDCR_CL_SHIFT) | \
+ (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
+ (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
+ (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
+ (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
+ (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
+ (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
+ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
+ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
+ (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
+ (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
+ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
+#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
+
+/*
* Serial Driver info
*/
#define CONFIG_SYS_NS16550_SERIAL
@@ -97,8 +138,6 @@
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
@@ -126,14 +165,40 @@
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_BUSWIDTH_16_BIT
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_CLE_MASK 0x10
-#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_MASK_CLE 0x10
+#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
+ CONFIG_SYS_NAND_U_BOOT_SIZE - \
+ CONFIG_SYS_MALLOC_LEN - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
#endif
#ifdef CONFIG_SYS_USE_NOR
@@ -182,7 +247,7 @@
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_BOOTFILE "zImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
@@ -202,7 +267,29 @@
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
-#define CONFIG_BOOTCOMMAND "if mmc rescan; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi"
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan; then " \
+ "run mmcboot; " \
+ "else " \
+ "run spiboot; " \
+ "fi"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdtaddr=0xc0600000\0" \
+ "fdtfile=da850-lcdk.dtb\0" \
+ "fdtboot=bootz 0xc0700000 - ${fdtaddr};\0" \
+ "mmcboot=" \
+ "if fatload mmc 0 0xc0600000 boot.scr; then " \
+ "source 0xc0600000; " \
+ "else " \
+ "fatload mmc 0 0xc0700000 " \
+ __stringify(CONFIG_BOOTFILE) "; " \
+ "fatload mmc 0 ${fdtaddr} ${fdtfile}; " \
+ "run fdtboot; " \
+ "fi;\0" \
+ "spiboot=" \
+ "sf probe 0; " \
+ "sf read 0xc0700000 0x80000 0x220000; " \
+ "bootz 0xc0700000;\0"
/*
* U-Boot commands
@@ -225,7 +312,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_LZO
#define CONFIG_RBTREE
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#endif
@@ -242,7 +328,6 @@
#endif
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
@@ -268,9 +353,6 @@
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
diff --git a/include/configs/openrd.h b/include/configs/openrd.h
index 4defa7e..c21b849 100644
--- a/include/configs/openrd.h
+++ b/include/configs/openrd.h
@@ -15,23 +15,6 @@
#define _CONFIG_OPENRD_H
/*
- * Version number information
- */
-#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
-# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate"
-#else
-# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
-# define CONFIG_IDENT_STRING "\nOpenRD-Client"
-# else
-# ifdef CONFIG_BOARD_IS_OPENRD_BASE
-# define CONFIG_IDENT_STRING "\nOpenRD-Base"
-# else
-# error Unknown OpenRD board specified
-# endif
-# endif
-#endif
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
@@ -124,7 +107,6 @@
#endif /*CONFIG_MVSATA_IDE*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MVEBU_MMC
#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index 227c0ca..9decae7 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -38,7 +38,6 @@
#define CONFIG_BAUDRATE CONFIG_SYS_UART_BAUD
#define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE}
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */
#define CONSOLE_ARG "console=console=ttyS0,115200\0"
/*
diff --git a/include/configs/origen.h b/include/configs/origen.h
index 1fa2f4d..26fe402 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -37,8 +37,6 @@
#define CONFIG_BAUDRATE 115200
/* Console configuration */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
@@ -87,8 +85,6 @@
"fi;" \
"load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
-#define CONFIG_IDENT_STRING " for ORIGEN"
-
#define CONFIG_CLK_1000_400_200
/* MIU (Memory Interleaving Unit) */
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 9be9d8b..f4b3e06 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -80,9 +80,6 @@
/* SPL */
#ifdef CONFIG_SPL
#include "imx6_spl.h"
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#define CONFIG_SPL_SPI_LOAD
#endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index ae0f6a5..f91a762 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -10,11 +10,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
-#if defined(CONFIG_P1020MBG)
+#if defined(CONFIG_TARGET_P1020MBG)
#define CONFIG_BOARDNAME "P1020MBG-PC"
-#define CONFIG_P1020
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
@@ -23,19 +20,17 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
-#if defined(CONFIG_P1020UTM)
+#if defined(CONFIG_TARGET_P1020UTM)
#define CONFIG_BOARDNAME "P1020UTM-PC"
-#define CONFIG_P1020
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xe0
#define __SW_BOOT_SD 0x50
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
-#if defined(CONFIG_P1020RDB_PC)
+#if defined(CONFIG_TARGET_P1020RDB_PC)
#define CONFIG_BOARDNAME "P1020RDB-PC"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1020
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
@@ -60,10 +55,9 @@
* 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
* 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
*/
-#if defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_BOARDNAME "P1020RDB-PD"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1020
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
@@ -85,10 +79,9 @@
"57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
#endif
-#if defined(CONFIG_P1021RDB)
+#if defined(CONFIG_TARGET_P1021RDB)
#define CONFIG_BOARDNAME "P1021RDB-PC"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1021
#define CONFIG_QE
#define CONFIG_VSC7385_ENET
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
@@ -120,10 +113,9 @@
#endif
#endif
-#if defined(CONFIG_P1024RDB)
+#if defined(CONFIG_TARGET_P1024RDB)
#define CONFIG_BOARDNAME "P1024RDB"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1024
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0xf3
#define __SW_BOOT_NOR 0x00
@@ -133,10 +125,9 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
-#if defined(CONFIG_P1025RDB)
+#if defined(CONFIG_TARGET_P1025RDB)
#define CONFIG_BOARDNAME "P1025RDB"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1025
#define CONFIG_QE
#define CONFIG_SLIC
@@ -150,10 +141,9 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
-#if defined(CONFIG_P2020RDB)
-#define CONFIG_BOARDNAME "P2020RDB-PCA"
+#if defined(CONFIG_TARGET_P2020RDB)
+#define CONFIG_BOARDNAME "P2020RDB-PC"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P2020
#define CONFIG_VSC7385_ENET
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8
@@ -181,17 +171,9 @@
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@@ -209,18 +191,9 @@
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@@ -241,14 +214,7 @@
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE (128 << 10)
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
@@ -259,8 +225,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xff800000
@@ -294,14 +258,9 @@
#endif
#endif
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500
-
#define CONFIG_MP
#define CONFIG_FSL_ELBC
-#define CONFIG_PCI
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
@@ -309,7 +268,6 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -319,7 +277,7 @@
#define CONFIG_LIBATA
#define CONFIG_LBA48
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_TARGET_P2020RDB)
#define CONFIG_SYS_CLK_FREQ 100000000
#else
#define CONFIG_SYS_CLK_FREQ 66666666
@@ -356,14 +314,13 @@
#endif
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
#undef CONFIG_FSL_DDR_INTERACTIVE
-#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#else
@@ -374,11 +331,10 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
-#ifndef CONFIG_P2020RDB
+#ifndef CONFIG_TARGET_P2020RDB
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
@@ -433,10 +389,10 @@
/*
* Local Bus Definitions
*/
-#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
#define CONFIG_SYS_FLASH_BASE 0xec000000
-#elif defined(CONFIG_P1020UTM)
+#elif defined(CONFIG_TARGET_P1020UTM)
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
#define CONFIG_SYS_FLASH_BASE 0xee000000
#else
@@ -482,7 +438,7 @@
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
-#if defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#else
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
@@ -493,7 +449,7 @@
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#if defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
@@ -611,7 +567,7 @@
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_TARGET_P2020RDB)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
#else
#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
@@ -739,7 +695,6 @@
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -783,7 +738,7 @@
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_QE */
-#ifdef CONFIG_P1025RDB
+#ifdef CONFIG_TARGET_P1025RDB
/*
* QE UEC ethernet configuration
*/
@@ -817,7 +772,7 @@
#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
#endif /* CONFIG_UEC_ETH5 */
-#endif /* CONFIG_P1025RDB */
+#endif /* CONFIG_TARGET_P1025RDB */
/*
* Environment
@@ -881,12 +836,10 @@
#endif
#endif
-#if defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
-#define CONFIG_MMC
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 6de9acd..63825b0 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -10,10 +10,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
-#define CONFIG_P1025
#define CONFIG_PHY_ATHEROS
#define CONFIG_QE
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
@@ -40,14 +38,9 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500
-
#define CONFIG_MP
#define CONFIG_FSL_ELBC
-#define CONFIG_PCI
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
@@ -55,7 +48,6 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -89,7 +81,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
@@ -98,7 +89,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
@@ -281,7 +271,6 @@
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -417,8 +406,6 @@
#endif
#endif
-#define CONFIG_MMC
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h
index 968b89e..cd981b9 100644
--- a/include/configs/p2371-0000.h
+++ b/include/configs/p2371-0000.h
@@ -22,7 +22,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h
index ffd26db..7ff545c 100644
--- a/include/configs/p2371-2180.h
+++ b/include/configs/p2371-2180.h
@@ -22,7 +22,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -46,8 +45,6 @@
#define CONFIG_USB_ETHER_ASIX
/* PCI host support */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
/* General networking support */
diff --git a/include/configs/p2571.h b/include/configs/p2571.h
index 4fa345d..7daaf8e 100644
--- a/include/configs/p2571.h
+++ b/include/configs/p2571.h
@@ -23,7 +23,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
index 1f64405..0864e4d 100644
--- a/include/configs/p2771-0000.h
+++ b/include/configs/p2771-0000.h
@@ -18,7 +18,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -29,8 +28,6 @@
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* PCI host support */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
#include "tegra-common-post.h"
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 5e59ccb..0cefee3 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -23,7 +23,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -45,7 +44,6 @@
/* LCD support */
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#include "tegra-common-post.h"
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index fb5278f..c92948f 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -15,8 +15,6 @@
#define CONFIG_PB1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_PB1000
#define CONFIG_SOC_AU1000 1
#else
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index 9babe6a..4fb9966 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -113,8 +113,6 @@
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
* -----------------------------------------------------------------------*/
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
@@ -350,8 +348,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_DISPLAY_BOARDINFO 1
-
/*-----------------------------------------------------------------------------
Various low-level settings
-----------------------------------------------------------------------------*/
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index e24dcb9..aff4635 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -120,16 +120,9 @@
/* CPU */
#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SPL_YMODEM_SUPPORT
-#define CONFIG_SPL_NET_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL"
-#define CONFIG_SPL_ETH_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#ifdef CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 57a7630..f3cf954 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -13,8 +13,6 @@
#define CONFIG_VF610
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
@@ -37,14 +35,12 @@
#define CONFIG_SYS_NAND_ONFI_DETECTION
#ifdef CONFIG_CMD_NAND
-#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
#define CONFIG_JFFS2_NAND
/* UBI */
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
@@ -53,26 +49,27 @@
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
+
+#ifndef MTDIDS_DEFAULT
#define MTDIDS_DEFAULT "nand0=NAND"
-#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
- ",384k(bootloader)"\
+#endif
+
+#ifndef MTDPARTS_DEFAULT
+#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\
",128k(env1)"\
",128k(env2)"\
",128k(dtb)"\
",6144k(kernel)"\
- ",65536k(ramdisk)"\
- ",450944k(root)"
+ ",-(root)"
#endif
-#define CONFIG_MMC
+#endif
+
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
@@ -88,7 +85,6 @@
/* QSPI Configs*/
#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SYS_FSL_QSPI_LE
@@ -118,16 +114,38 @@
#define CONFIG_SYS_TEXT_BASE 0x3f408000
#define CONFIG_BOARD_SIZE_LIMIT 524288
-#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
+/* if no target-specific extra environment settings were defined by the
+ target, define an empty one */
+#ifndef PCM052_EXTRA_ENV_SETTINGS
+#define PCM052_EXTRA_ENV_SETTINGS
+#endif
+
+/* if no target-specific boot command was defined by the target,
+ define an empty one */
+#ifndef PCM052_BOOTCOMMAND
+#define PCM052_BOOTCOMMAND
+#endif
+
+/* if no target-specific extra environment settings were defined by the
+ target, define an empty one */
+#ifndef PCM052_NET_INIT
+#define PCM052_NET_INIT
+#endif
+
+/* boot command, including the target-defined one if any */
+#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand"
+
+/* Extra env settings (including the target-defined ones if any) */
#define CONFIG_EXTRA_ENV_SETTINGS \
+ PCM052_EXTRA_ENV_SETTINGS \
+ "autoload=no\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
- "blimg_file=u-boot.imx\0" \
- "blsec_addr=0x81000000\0" \
- "blimg_addr=0x81000400\0" \
+ "blimg_file=u-boot.vyb\0" \
+ "blimg_addr=0x81000000\0" \
"kernel_file=zImage\0" \
"kernel_addr=0x82000000\0" \
- "fdt_file=vf610-pcm052.dtb\0" \
+ "fdt_file=zImage.dtb\0" \
"fdt_addr=0x81000000\0" \
"ram_file=uRamdisk\0" \
"ram_addr=0x83000000\0" \
@@ -138,14 +156,15 @@
"tftptimeout=1000\0" \
"tftptimeoutcountmax=1000000\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
- "bootargs_base=setenv bootargs rw mem=256M " \
+ "bootargs_base=setenv bootargs rw " \
+ " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \
"console=ttyLP1,115200n8\0" \
"bootargs_sd=setenv bootargs ${bootargs} " \
"root=/dev/mmcblk0p2 rootwait\0" \
"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
"bootargs_nand=setenv bootargs ${bootargs} " \
- "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \
+ "ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
"bootargs_ram=setenv bootargs ${bootargs} " \
"root=/dev/ram rw initrd=${ram_addr}\0" \
"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
@@ -164,14 +183,14 @@
"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
"nand read ${fdt_addr} dtb; " \
"nand read ${kernel_addr} kernel; " \
- "nand read ${ram_addr} ramdisk; " \
+ "nand read ${ram_addr} root; " \
"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
- "update_bootloader_from_tftp=mtdparts default; " \
- "nand read ${blsec_addr} bootloader; " \
- "mw.b ${blimg_addr} 0xff 0x5FC00; " \
- "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \
+ "update_bootloader_from_tftp=" PCM052_NET_INIT \
+ "if tftp ${blimg_addr} "\
+ "${tftpdir}${blimg_file}; then " \
+ "mtdparts default; " \
"nand erase.part bootloader; " \
- "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \
+ "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
"${kernel_file}; " \
"then mtdparts default; " \
@@ -180,7 +199,8 @@
"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
"nand erase.part dtb; " \
"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
- "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
+ "update_kernel_from_tftp=" PCM052_NET_INIT \
+ "if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
"then setenv fdtsize ${filesize}; " \
"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
"mtdparts default; " \
@@ -188,16 +208,18 @@
"nand write ${fdt_addr} dtb ${fdtsize}; " \
"nand erase.part kernel; " \
"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
- "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
+ "update_rootfs_from_tftp=" PCM052_NET_INIT \
+ "if tftp ${sys_addr} ${tftpdir}${filesys}; " \
"then mtdparts default; " \
"nand erase.part root; " \
"ubi part root; " \
"ubi create rootfs; " \
"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
- "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
+ "update_ramdisk_from_tftp=" PCM052_NET_INIT \
+ "if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
"then mtdparts default; " \
- "nand erase.part ramdisk; " \
- "nand write ${ram_addr} ramdisk ${filesize}; fi\0"
+ "nand erase.part root; " \
+ "nand write ${ram_addr} root ${filesize}; fi\0"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
@@ -223,7 +245,7 @@
/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM (0x80000000)
-#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
index 97cbeba..2869c4e 100644
--- a/include/configs/pcm058.h
+++ b/include/configs/pcm058.h
@@ -11,12 +11,6 @@
#include <config_distro_defaults.h>
#ifdef CONFIG_SPL
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_DMA_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#include "imx6_spl.h"
@@ -30,7 +24,7 @@
/* Serial */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc1"
+#define CONSOLE_DEV "ttymxc1"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
@@ -98,7 +92,6 @@
#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */
#define CONFIG_CMD_GSC
#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */
-#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
/* Physical Memory Map */
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index 6d03d69..eca984a 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -13,7 +13,6 @@
#define __CONFIG_H
#define CONFIG_PDM360NG 1
-#define CONFIG_DISPLAY_BOARDINFO
/*
* Memory map for the PDM360NG board:
@@ -37,14 +36,10 @@
/* Used for silent command in environment */
#define CONFIG_SYS_DEVICE_NULLDEV
-#define CONFIG_SILENT_CONSOLE
/* Video */
-#define CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_RLE8
@@ -250,14 +245,6 @@
"f8000000.flash:-(unused);" \
"MPC5121 NAND:1024m(extended-userfs)"
-/*
- * Override partitions in device tree using info
- * in "mtdparts" environment variable
- */
-#ifdef CONFIG_CMD_MTDPARTS
-#define CONFIG_FDT_FIXUP_PARTITIONS
-#endif
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */
#ifdef CONFIG_FSL_DIU_FB
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h
index 6c42aaa..296d77a 100644
--- a/include/configs/peach-pi.h
+++ b/include/configs/peach-pi.h
@@ -29,10 +29,7 @@
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-#define CONFIG_IDENT_STRING " for Peach-Pi"
-
/* Display */
-#define CONFIG_LCD
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 6c68dd2..c4ae0e2 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -29,8 +29,6 @@
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-#define CONFIG_IDENT_STRING " for Peach-Pit"
-
/* DRAM Memory Banks */
#define CONFIG_NR_DRAM_BANKS 4
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 909ed9d..f1db204 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -114,13 +114,6 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* SPL */
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-
-/* General network SPL */
-#define CONFIG_SPL_NET_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
/* NAND support */
#define CONFIG_CMD_NAND
@@ -201,7 +194,6 @@
#if defined(CONFIG_SPL_BUILD)
/* disable host part of MUSB in SPL */
/* Disable CPSW SPL support so we fit within the 101KiB limit. */
-#undef CONFIG_SPL_ETH_SUPPORT
#endif
/* CPSW ethernet */
@@ -214,8 +206,7 @@
#define CONFIG_PHY_REALTEK
/* CPSW support */
-#define CONFIG_SPL_ETH_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#endif /* ! __CONFIG_PENGWYN_H */
diff --git a/include/configs/pepper.h b/include/configs/pepper.h
index 1bc8c4b..2aa63fc 100644
--- a/include/configs/pepper.h
+++ b/include/configs/pepper.h
@@ -7,11 +7,9 @@
#ifndef __CONFIG_PEPPER_H
#define __CONFIG_PEPPER_H
-#define CONFIG_MMC
#include <configs/ti_am335x_common.h>
#undef CONFIG_BOARD_LATE_INIT
-#undef CONFIG_SPL_OS_BOOT
/* Clock defines */
#define V_OSCK 24000000 /* Clock output from T2 */
@@ -25,8 +23,6 @@
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_IS_NOWHERE
-/* Display cpuinfo */
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -93,6 +89,6 @@
#define CONFIG_PHY_RESET_DELAY 1000
/* SPL */
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#endif /* __CONFIG_PEPPER_H */
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 49c98d8..e6fd249 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -10,7 +10,6 @@
#define __PIC32MZDASK_CONFIG_H
/* System Configuration */
-#define CONFIG_DISPLAY_BOARDINFO
/*--------------------------------------------
* CPU configuration
@@ -92,8 +91,6 @@
/*-----------------------------------------------------------------------
* SDHC Configuration
*/
-#define CONFIG_SDHCI
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/*--------------------------------------------------
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 1c46ec3..2bd7076 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -14,9 +14,6 @@
#include "mx6_common.h"
#include <asm/imx-common/gpio.h>
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Network support */
#define CONFIG_FEC_MXC
@@ -40,7 +37,6 @@
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_EMMC_BOOT
@@ -58,13 +54,9 @@
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_DEFAULT_FDT_FILE "imx6ul-pico-hobbit.dtb"
-
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
index c2e2c43..20fb036 100644
--- a/include/configs/picosam9g45.h
+++ b/include/configs/picosam9g45.h
@@ -31,7 +31,6 @@
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
@@ -44,7 +43,6 @@
#define CONFIG_USART_ID ATMEL_ID_SYS
/* LCD */
-#define CONFIG_LCD
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO
#undef LCD_TEST_PATTERN
@@ -53,7 +51,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_LCD
#define CONFIG_ATMEL_LCD_RGB565
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* board specific(not enough SRAM) */
#define CONFIG_AT91SAM9G45_LCD_BASE 0x23E00000
@@ -95,7 +92,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#endif
@@ -163,12 +159,6 @@
#define CONFIG_SPL_MAX_SIZE 0x010000
#define CONFIG_SPL_STACK 0x310000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-
#define CONFIG_SYS_MONITOR_LEN 0x80000
#ifdef CONFIG_SYS_USE_MMC
@@ -179,13 +169,8 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_ATMEL_SIZE
#define CONFIG_SYS_MASTER_CLOCK 132096000
diff --git a/include/configs/platinum.h b/include/configs/platinum.h
index 34ce086..f3ac458 100644
--- a/include/configs/platinum.h
+++ b/include/configs/platinum.h
@@ -8,8 +8,6 @@
#define __PLATINUM_CONFIG_H__
/* SPL */
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
/* Location in NAND to read U-Boot from */
#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024)
@@ -25,7 +23,6 @@
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
/*
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 635e439..8ad5af1 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -20,7 +20,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 537a6d8..c19e7dc 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -20,8 +20,6 @@
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_DISPLAY_BOARDINFO
-
#define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162
#define MAIN_PLL_DIV 2
@@ -151,7 +149,6 @@
#define CONFIG_USART_ID ATMEL_ID_SYS
/* LCD */
-#define CONFIG_LCD 1
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO 1
#undef LCD_TEST_PATTERN
@@ -160,7 +157,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK 1
#define CONFIG_ATMEL_LCD 1
#define CONFIG_ATMEL_LCD_BGR555 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* LED */
#define CONFIG_AT91_LED
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 9993248..eddc81a 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -19,8 +19,6 @@
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65
@@ -164,7 +162,6 @@
#define CONFIG_USART_ID ATMEL_ID_SYS
/* LCD */
-#define CONFIG_LCD 1
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO 1
#undef LCD_TEST_PATTERN
@@ -173,7 +170,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK 1
#define CONFIG_ATMEL_LCD 1
#define CONFIG_ATMEL_LCD_BGR555 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
#define CONFIG_LCD_IN_PSRAM 1
diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h
index 6393ff3..fb1339c 100644
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -18,7 +18,6 @@
*/
#define MACH_TYPE_POGO_E02 3542
#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02
-#define CONFIG_IDENT_STRING "\nPogo E02"
/*
* High Level Configuration Options (easy to change)
@@ -82,7 +81,6 @@
* File system
*/
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
diff --git a/include/configs/popmetal_rk3288.h b/include/configs/popmetal_rk3288.h
index 342557f..77b647e 100644
--- a/include/configs/popmetal_rk3288.h
+++ b/include/configs/popmetal_rk3288.h
@@ -10,8 +10,6 @@
#define ROCKCHIP_DEVICE_SETTINGS
#include <configs/rk3288_common.h>
-#define CONFIG_SPL_MMC_SUPPORT
-
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
/* SPL @ 32k for ~36k
@@ -21,6 +19,5 @@
#define CONFIG_ENV_OFFSET (96 * 1024)
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
diff --git a/include/configs/porter.h b/include/configs/porter.h
index 7d8a095..ccaa796 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -88,7 +88,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* SD */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SH_SDHI_FREQ 97500000
diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h
index 21bf088..4598bd9 100644
--- a/include/configs/pxa-common.h
+++ b/include/configs/pxa-common.h
@@ -9,7 +9,6 @@
#ifndef __CONFIG_PXA_COMMON_H__
#define __CONFIG_PXA_COMMON_H__
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/*
@@ -23,7 +22,6 @@
* MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 990fd84..d797a2c 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -40,12 +40,6 @@
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
-
-#undef CONFIG_SPL_NET_SUPPORT
-#undef CONFIG_SPL_NET_VCI_STRING
-#undef CONFIG_SPL_ETH_SUPPORT
-
#define CONFIG_PHY_ATHEROS
#define CONFIG_FACTORYSET
@@ -128,11 +122,8 @@
#endif
#endif /* CONFIG_SPL_BUILD */
-#define CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_LOGO
@@ -142,8 +133,6 @@
#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
#define PWM_TICKS 0x1388
#define PWM_DUTY 0x200
-#define CONFIG_SYS_CONSOLE_BG_COL 0xff
-#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
#endif /* ! __CONFIG_PXM2_H */
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 546c508..a6abba7 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -14,7 +14,6 @@
#define CONFIG_QEMU_MIPS
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 6cab719..7297a81 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -14,7 +14,6 @@
#define CONFIG_QEMU_MIPS
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 072859e..9517674 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -12,11 +12,6 @@
#define CONFIG_CMD_REGINFO
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_QEMU_E500
-
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
@@ -24,7 +19,6 @@
#define CONFIG_SYS_RAMBOOT
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
@@ -118,7 +112,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index 476d37d..4783563 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -16,11 +16,9 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_ARCH_EARLY_INIT_R
-#define CONFIG_PCI_PNP
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
/*
* ATA/SATA support for QEMU x86 targets
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index 2d7e326..f7412f0 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -9,7 +9,6 @@
#ifndef __R0P7734_H
#define __R0P7734_H
-#undef DEBUG
#define CONFIG_CPU_SH7734 1
#define CONFIG_R0P7734 1
#define CONFIG_400MHZ_MODE 1
@@ -24,6 +23,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC3,115200"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Ether */
@@ -76,9 +76,6 @@
#define CONFIG_CONS_SCIF3 1
/* Suppress display of console information at boot */
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE (0x88000000)
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 1fc919b..0e954af 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -1,13 +1,13 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
#define CONFIG_CPU_SH7751 1
#define CONFIG_CPU_SH_TYPE_R 1
#define CONFIG_R2DPLUS 1
#define __LITTLE_ENDIAN__ 1
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* Command line configuration.
*/
@@ -26,10 +26,10 @@
#define CONFIG_ENV_OVERWRITE 1
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
-#define CONFIG_SYS_SDRAM_SIZE (0x04000000)
+#define CONFIG_SYS_SDRAM_BASE 0x8C000000
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
+#define CONFIG_SYS_TEXT_BASE 0x8FE00000
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE 256
@@ -88,12 +88,9 @@
/*
* SuperH PCI Bridge Configration
*/
-#define CONFIG_PCI
#define CONFIG_SH4_PCI
#define CONFIG_SH7751_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW 1
-#define __io
#define __mem_pci
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
@@ -102,8 +99,8 @@
#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
-#define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
-#define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
+#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
#endif /* __CONFIG_H */
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index bc01ae9..baadd87 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -10,12 +10,13 @@
#ifndef __R7780RP_H
#define __R7780RP_H
-#undef DEBUG
#define CONFIG_CPU_SH7780 1
#define CONFIG_R7780MP 1
#define CONFIG_SYS_R7780MP_OLD_FLASH 1
#define __LITTLE_ENDIAN__ 1
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* Command line configuration.
*/
@@ -94,15 +95,12 @@
/* PCI Controller */
#if defined(CONFIG_CMD_PCI)
-#define CONFIG_PCI
#define CONFIG_SH4_PCI
#define CONFIG_SH7780_PCI
#define CONFIG_SH7780_PCI_LSR 0x07f00001
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW 1
-#define __io
#define __mem_pci
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
index 55be46b..d6fead2 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/rastaban.h
@@ -15,7 +15,6 @@
#include "siemens-am33x-common.h"
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MPUCLK 300
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
@@ -49,12 +48,6 @@
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
-
-#undef CONFIG_SPL_NET_SUPPORT
-#undef CONFIG_SPL_NET_VCI_STRING
-#undef CONFIG_SPL_ETH_SUPPORT
-
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
#define CONFIG_PHY_SMSC
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 5733da6..459b077 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -34,17 +34,12 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_TMU_TIMER
#define CONFIG_SH_GPIO_PFC
/* console */
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE 256
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 7655417..ec4d54e 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -43,16 +43,11 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SH_GPIO_PFC
/* console */
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE 256
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 101a3ed..27dfbce 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -7,6 +7,7 @@
#define __CONFIG_RK3036_COMMON_H
#include <asm/arch/hardware.h>
+#include "rockchip-common.h"
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
@@ -18,14 +19,11 @@
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
@@ -39,7 +37,6 @@
#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
/* MMC/SD IP block */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
#define CONFIG_BOUNCE_BUFFER
@@ -72,13 +69,22 @@
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
#define CONFIG_G_DNL_VENDOR_NUM 0x2207
#define CONFIG_G_DNL_PRODUCT_NUM 0x310a
-#include <config_distro_defaults.h>
-
+/* usb host */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+#endif
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x60000000\0" \
"pxefile_addr_r=0x60100000\0" \
@@ -86,19 +92,18 @@
"kernel_addr_r=0x62000000\0" \
"ramdisk_addr_r=0x64000000\0"
-/* First try to boot from SD (index 0), then eMMC (index 1 */
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1)
-
#include <config_distro_bootcmd.h>
/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
* so limit the fdt reallocation to that */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x7fffffff\0" \
+ "partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
#endif
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_PREBOOT
+
#endif
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 601186c..535797a 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -8,7 +8,9 @@
#define __CONFIG_RK3288_COMMON_H
#include <asm/arch/hardware.h>
+#include "rockchip-common.h"
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_SIZE 0x2000
@@ -17,17 +19,12 @@
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SPL_BOARD_INIT
@@ -42,14 +39,7 @@
#define CONFIG_SPL_STACK 0xff718000
#define CONFIG_SPL_TEXT_BASE 0xff704004
-#define CONFIG_SILENT_CONSOLE
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_SYS_CONSOLE_IS_IN_ENV
-# define CONFIG_CONSOLE_MUX
-#endif
-
/* MMC/SD IP block */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
#define CONFIG_BOUNCE_BUFFER
@@ -59,17 +49,12 @@
#define CONFIG_CMD_PART
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
/* FAT sd card locations. */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_PINCTRL_SUPPORT
-#define CONFIG_SPL_RAM_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-
#define CONFIG_SYS_SDRAM_BASE 0
#define CONFIG_NR_DRAM_BANKS 1
#define SDRAM_BANK_SIZE (2UL << 30)
@@ -103,11 +88,6 @@
#define CONFIG_G_DNL_VENDOR_NUM 0x2207
#define CONFIG_G_DNL_PRODUCT_NUM 0x320a
-/* Enable gpt partition table */
-#define CONFIG_CMD_GPT
-
-#include <config_distro_defaults.h>
-
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
"pxefile_addr_r=0x00100000\0" \
@@ -115,28 +95,20 @@
"kernel_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x04000000\0"
-#define CONFIG_RANDOM_UUID
-#define PARTS_DEFAULT \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \
- "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
-
-/* First try to boot from SD (index 0), then eMMC (index 1 */
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1)
-
#include <config_distro_bootcmd.h>
-/* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so
+/* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so
* limit the fdt reallocation to that */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "fdt_high=0x1fffffff\0" \
- "initrd_high=0x1fffffff\0" \
+ "fdt_high=0x0fffffff\0" \
+ "initrd_high=0x0fffffff\0" \
"partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \
BOOTENV
#endif
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_PREBOOT
+
#endif
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index e9626a5..eab3f04 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -7,6 +7,8 @@
#ifndef __CONFIG_RK3399_COMMON_H
#define __CONFIG_RK3399_COMMON_H
+#include "rockchip-common.h"
+
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_SIZE 0x2000
@@ -15,7 +17,6 @@
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_NS16550_MEM32
@@ -26,10 +27,8 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
/* MMC/SD IP block */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
-#define CONFIG_SDHCI
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
@@ -40,7 +39,6 @@
#define CONFIG_CMD_PART
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
/* FAT sd card locations. */
@@ -53,7 +51,6 @@
#define CONFIG_SF_DEFAULT_SPEED 20000000
#ifndef CONFIG_SPL_BUILD
-#include <config_distro_defaults.h>
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
@@ -62,19 +59,6 @@
"kernel_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x04000000\0"
-#define CONFIG_CMD_GPT
-#define CONFIG_RANDOM_UUID
-#define CONFIG_PARTITION_UUIDS
-#define PARTS_DEFAULT \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=boot,start=16M,size=32M,bootable;" \
- "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
-
-/* First try to boot from SD (index 0), then eMMC (index 1) */
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1)
-
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
@@ -83,4 +67,16 @@
#endif
+/* enable usb config for usb ether */
+#define CONFIG_USB_HOST_ETHER
+
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_ASIX88179
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_RTL8152
+
+/* rockchip xhci host driver */
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
#endif
diff --git a/include/configs/rock2.h b/include/configs/rock2.h
index a29f557..b9c2290 100644
--- a/include/configs/rock2.h
+++ b/include/configs/rock2.h
@@ -14,17 +14,23 @@
#include <configs/rk3288_common.h>
-#define CONFIG_SPL_MMC_SUPPORT
-
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* SPL @ 32k for 34k
+ * u-boot directly after @ 68k for 400k or so
+ * ENV @ 992k
+ */
+#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
+#else
/* SPL @ 32k for ~36k
* ENV @ 96k
* u-boot @ 128K
*/
#define CONFIG_ENV_OFFSET (96 * 1024)
+#endif
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#endif
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
new file mode 100644
index 0000000..9ec71c4
--- /dev/null
+++ b/include/configs/rockchip-common.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ROCKCHIP_COMMON_H_
+#define _ROCKCHIP_COMMON_H_
+#include <linux/sizes.h>
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+
+/* First try to boot from SD (index 0), then eMMC (index 1 */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1)
+
+ /* Enable gpt partition table */
+#define CONFIG_CMD_GPT
+#define CONFIG_RANDOM_UUID
+#define CONFIG_PARTITION_UUIDS
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \
+ "name=reserved1,size=64K,uuid=${uuid_gpt_reserved1};" \
+ "name=reserved2,size=4M,uuid=${uuid_gpt_reserved2};" \
+ "name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \
+ "name=atf,size=4M,uuid=${uuid_gpt_atf};" \
+ "name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \
+ "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
+
+#endif
+
+#endif /* _ROCKCHIP_COMMON_H_ */
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 8d4ad5d..45d8824 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -16,7 +16,6 @@
/* Architecture, CPU, etc.*/
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
/* Use SoC timer for AArch32, but architected timer for AArch64 */
#ifndef CONFIG_ARM64
@@ -71,9 +70,8 @@
/* GPIO */
#define CONFIG_BCM2835_GPIO
/* LCD */
-#define CONFIG_LCD
#define CONFIG_LCD_DT_SIMPLEFB
-#define LCD_BPP LCD_COLOR16
+#define LCD_BPP LCD_COLOR32
/*
* Prevent allocation of RAM for FB; the real FB address is queried
* dynamically from the VideoCore co-processor, and comes from RAM
@@ -82,14 +80,9 @@
#define CONFIG_FB_ADDR 0
#define CONFIG_VIDEO_BCM2835
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS
-#define CONFIG_BCM2835_SDHCI
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2
@@ -102,9 +95,7 @@
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_TFTP_TSIZE
#define CONFIG_MISC_INIT_R
-#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_SYS_STDIO_DEREGISTER
#endif
/* Console UART */
@@ -130,8 +121,6 @@
#define CONFIG_FAT_WRITE
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_SYS_LOAD_ADDR 0x1000000
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_PREBOOT "usb start"
/* Shell */
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index 9db73d3..913cbc2 100644
--- a/include/configs/rsk7203.h
+++ b/include/configs/rsk7203.h
@@ -10,7 +10,6 @@
#ifndef __RSK7203_H
#define __RSK7203_H
-#undef DEBUG
#define CONFIG_CPU_SH7203 1
#define CONFIG_RSK7203 1
@@ -20,6 +19,7 @@
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
index 3f9fb7b..ea60014 100644
--- a/include/configs/rsk7264.h
+++ b/include/configs/rsk7264.h
@@ -11,10 +11,11 @@
#ifndef __RSK7264_H
#define __RSK7264_H
-#undef DEBUG
#define CONFIG_CPU_SH7264 1
#define CONFIG_RSK7264 1
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC3,115200"
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h
index b7f361b..f470954 100644
--- a/include/configs/rsk7269.h
+++ b/include/configs/rsk7269.h
@@ -10,10 +10,11 @@
#ifndef __RSK7269_H
#define __RSK7269_H
-#undef DEBUG
#define CONFIG_CPU_SH7269 1
#define CONFIG_RSK7269 1
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC7,115200"
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
diff --git a/include/configs/rut.h b/include/configs/rut.h
index aea8e21..e5933b8 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -35,12 +35,6 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200
-
-#undef CONFIG_SPL_NET_SUPPORT
-#undef CONFIG_SPL_NET_VCI_STRING
-#undef CONFIG_SPL_ETH_SUPPORT
-
#define CONFIG_PHY_NATSEMI
#define CONFIG_FACTORYSET
@@ -122,11 +116,8 @@
#undef CONFIG_HW_WATCHDOG
#endif
-#define CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_LOGO
@@ -142,8 +133,6 @@
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_FORMIKE
#define DISPL_PLL_SPREAD_SPECTRUM
-#define CONFIG_SYS_CONSOLE_BG_COL 0xff
-#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
#endif /* ! __CONFIG_RUT_H */
diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
index 13eac75..9ee68dd 100644
--- a/include/configs/s32v234evb.h
+++ b/include/configs/s32v234evb.h
@@ -18,9 +18,6 @@
#define CONFIG_S32V234
#define CONFIG_DM
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Config GIC */
#define CONFIG_GICV2
#define GICD_BASE 0x7D001000
@@ -80,25 +77,20 @@
#undef CONFIG_CMD_IMLS
-#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
/* #define CONFIG_CMD_EXT2 EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_DOS_PARTITION
#if 0
/* Ethernet config */
#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_MII
@@ -136,8 +128,6 @@
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
-#define CONFIG_CMD_DHCP
-
#define CONFIG_LOADADDR 0xC307FFC0
#define CONFIG_BOOTARGS "console=ttyLF0 root=/dev/ram rw"
@@ -221,7 +211,6 @@
#if 0
/* Configure PXE */
-#define CONFIG_CMD_PXE
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
#endif
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 61c5663..6a61e5c 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -21,8 +21,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
/* input clock of PLL: has 24MHz input clock at S5PC110 */
#define CONFIG_SYS_CLK_FREQ_C110 24000000
@@ -50,9 +48,6 @@
/* MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
#define SDHCI_MAX_HOSTS 4
/* PWM */
@@ -65,8 +60,6 @@
#define CONFIG_CMD_GPT
/* USB Composite download gadget - g_dnl */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define DFU_DEFAULT_POLL_TIMEOUT 300
@@ -137,7 +130,6 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -234,25 +226,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_MAX8998
-
-#include <asm/arch/gpio.h>
-/*
- * I2C Settings
- */
-#define CONFIG_SOFT_I2C_GPIO_SCL S5PC110_GPIO_J43
-#define CONFIG_SOFT_I2C_GPIO_SDA S5PC110_GPIO_J40
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_INIT_BOARD
-
-#define CONFIG_SYS_MAX_I2C_BUS 7
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
#define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 9915306..1bfefe9 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -29,8 +29,6 @@
#define CONFIG_BAUDRATE 115200
/* Console configuration */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run mmcboot"
@@ -155,25 +153,6 @@
#define CONFIG_SAMSUNG_ONENAND
#define CONFIG_SYS_ONENAND_BASE 0x0C000000
-#include <asm/arch/gpio.h>
-/*
- * I2C Settings
- */
-#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_B7
-#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_B6
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0
-#define CONFIG_SOFT_I2C_READ_REPEATED_START
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS 7
-
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_MAX8998
-
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
/*
diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h
index c1c01bd..7a049d4 100644
--- a/include/configs/sama5d2_ptc.h
+++ b/include/configs/sama5d2_ptc.h
@@ -121,22 +121,14 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_SERIALFLASH
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#elif CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_PMECC_CAP 8
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index 563c045..4f72c83 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -15,10 +15,9 @@
#include "at91-sama5_common.h"
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_UART1
-#define CONFIG_USART_ID ATMEL_ID_UART1
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_MISC_INIT_R
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
@@ -34,14 +33,8 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-#undef CONFIG_AT91_GPIO
-#define CONFIG_ATMEL_PIO4
-
/* SerialFlash */
#ifdef CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI
-#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 30000000
@@ -51,23 +44,8 @@
#undef CONFIG_CMD_NAND
/* MMC */
-
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_SDHCI
-#define CONFIG_ATMEL_SDHCI
-#define CONFIG_ATMEL_SDHCI0
-#define CONFIG_ATMEL_SDHCI1
-#define CONFIG_SUPPORT_EMMC_BOOT
-#endif
-
-/* USB */
-
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_ATMEL
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#endif
/* USB device */
@@ -79,6 +57,10 @@
#define CONFIG_DOS_PARTITION
#endif
+/* I2C */
+#define AT24MAC_ADDR 0x5c
+#define AT24MAC_REG 0x9a
+
/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_RMII
@@ -86,7 +68,6 @@
#define CONFIG_MACB_SEARCH_PHY
/* LCD */
-/* #define CONFIG_LCD */
#ifdef CONFIG_LCD
#define LCD_BPP LCD_COLOR16
@@ -97,7 +78,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif
#ifdef CONFIG_SYS_USE_MMC
@@ -125,27 +105,15 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_SERIALFLASH
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index fef925f..b840315 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -67,7 +67,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_LZO
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#endif
@@ -82,7 +81,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_ATMEL_MCI_8BIT
@@ -124,26 +122,15 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 248de8d..831a45c 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -39,7 +39,6 @@
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
/* LCD */
-#define CONFIG_LCD
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 24
#define CONFIG_LCD_LOGO
@@ -48,7 +47,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* board specific (not enough SRAM) */
#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
@@ -115,7 +113,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
@@ -164,26 +161,15 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
@@ -196,8 +182,6 @@
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SERIALFLASH
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index d874ab5..bcd5c37 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -64,7 +64,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
@@ -94,7 +93,6 @@
#define CONFIG_MACB_SEARCH_PHY
/* LCD */
-/* #define CONFIG_LCD */
#ifdef CONFIG_LCD
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 24
@@ -104,7 +102,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif
#ifdef CONFIG_SYS_USE_SERIALFLASH
@@ -124,26 +121,15 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_PMECC_CAP 8
@@ -158,8 +144,6 @@
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SERIALFLASH
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index 61c3f85..9009730 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -64,7 +64,6 @@
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
@@ -94,7 +93,6 @@
#define CONFIG_MACB_SEARCH_PHY
/* LCD */
-#define CONFIG_LCD
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 18
#define CONFIG_LCD_LOGO
@@ -103,7 +101,6 @@
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#ifdef CONFIG_SYS_USE_SERIALFLASH
/* override the bootcmd, bootargs and other configuration for spi flash env*/
@@ -122,26 +119,15 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#elif CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_PMECC_CAP 8
@@ -156,8 +142,6 @@
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#elif CONFIG_SYS_USE_SERIALFLASH
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 94e024b..2daf02d 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -25,8 +25,6 @@
#define CONFIG_SYS_TIMER_RATE 1000000
#endif
-#define CONFIG_SYS_STDIO_DEREGISTER
-
/*
* Number of bits in a C 'long' on this architecture. Set this to 32 when
* building on a 32-bit machine.
@@ -37,7 +35,6 @@
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_CMD_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_CMD_IO
#define CONFIG_FS_FAT
@@ -67,7 +64,6 @@
#define CONFIG_SYS_LONGHELP /* #undef to save memory */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SILENT_CONSOLE
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -150,8 +146,6 @@
/* LCD and keyboard require SDL support */
#ifdef CONFIG_SANDBOX_SDL
#define CONFIG_CMD_BMP
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define LCD_BPP LCD_COLOR16
#define CONFIG_LCD_BMP_RLE8
#define CONFIG_VIDEO_BMP_RLE8
diff --git a/include/configs/sandbox_spl.h b/include/configs/sandbox_spl.h
index ffc3098..2aaa3ab 100644
--- a/include/configs/sandbox_spl.h
+++ b/include/configs/sandbox_spl.h
@@ -10,11 +10,6 @@
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#endif
diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
index d58b963..0b2821d 100644
--- a/include/configs/sansa_fuze_plus.h
+++ b/include/configs/sansa_fuze_plus.h
@@ -11,11 +11,8 @@
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
-#define CONFIG_VIDEO
-
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 567c4d5..ca1797d 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -15,8 +15,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -332,8 +330,6 @@
#undef PCI_ONE_PCI1
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index ec9ad45..281a993 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -36,9 +36,6 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
/*
@@ -70,8 +67,6 @@
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
/*
* Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
*/
@@ -101,7 +96,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
/*
@@ -122,7 +116,6 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
@@ -461,9 +454,6 @@
#endif
#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 248785d..f02634b 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -21,7 +21,6 @@
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
@@ -43,12 +42,10 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_PCI 1 /* Enable PCIE */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -60,7 +57,6 @@
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CACHE_LINE_INTERLEAVING 0x20000000
#define PAGE_INTERLEAVING 0x21000000
#define BANK_INTERLEAVING 0x22000000
@@ -89,7 +85,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
@@ -107,7 +102,6 @@
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -297,8 +291,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index 0a8a637..56a23a6 100644
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -16,7 +16,6 @@
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
/* Memory configuration */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 3076ef4..3ee6555 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -32,7 +32,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -57,11 +56,9 @@
#define CONFIG_KEYBOARD
/* USB keyboard */
-#define CONFIG_USB_KEYBOARD
/* LCD support */
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
/* NAND support */
#define CONFIG_CMD_NAND
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index ac783d3..ed8a51c 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -45,7 +45,6 @@
* Define this if you want support for video console with radeon 9200 pci card
* Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
*/
-#undef CONFIG_VIDEO
#ifdef CONFIG_VIDEO
/*
@@ -266,17 +265,13 @@
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
#define CONFIG_SUPPORT_VFAT
/*
* PCI stuff
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
@@ -411,11 +406,8 @@
#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
#define VIDEO_IO_OFFSET 0xe8000000
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_LOGO
-#define CONFIG_CFB_CONSOLE
#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CMD_BMP
#endif
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index cfcde81..e2af82d 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -9,12 +9,10 @@
#ifndef __SH7752EVB_H
#define __SH7752EVB_H
-#undef DEBUG
#define CONFIG_CPU_SH7752 1
#define CONFIG_SH7752EVB 1
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
-#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7752evb/u-boot.lds"
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
@@ -26,6 +24,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
@@ -44,9 +43,6 @@
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF2 1
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
@@ -92,7 +88,6 @@
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_MMC 1
#define CONFIG_GENERIC_MMC 1
#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
index fefdbb4..0859109 100644
--- a/include/configs/sh7753evb.h
+++ b/include/configs/sh7753evb.h
@@ -9,12 +9,10 @@
#ifndef __SH7753EVB_H
#define __SH7753EVB_H
-#undef DEBUG
#define CONFIG_CPU_SH7753 1
#define CONFIG_SH7753EVB 1
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
-#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7753evb/u-boot.lds"
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
@@ -26,6 +24,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
@@ -44,9 +43,6 @@
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF2 1
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
@@ -92,7 +88,6 @@
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_MMC 1
#define CONFIG_GENERIC_MMC 1
#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 262d390..05b5faa 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -9,13 +9,11 @@
#ifndef __SH7757LCR_H
#define __SH7757LCR_H
-#undef DEBUG
#define CONFIG_CPU_SH7757 1
#define CONFIG_SH7757LCR 1
#define CONFIG_SH7757LCR_DDR_ECC 1
#define CONFIG_SYS_TEXT_BASE 0x8ef80000
-#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds"
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MD5SUM
@@ -26,6 +24,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
@@ -44,9 +43,6 @@
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF2 1
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
@@ -93,7 +89,6 @@
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_MMC 1
#define CONFIG_GENERIC_MMC 1
#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 2e45699..6124826 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -23,6 +23,7 @@
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SCIF */
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index 80e61a4..a74fd60 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -9,7 +9,6 @@
#ifndef __SH7785LCR_H
#define __SH7785LCR_H
-#undef DEBUG
#define CONFIG_CPU_SH7785 1
#define CONFIG_SH7785LCR 1
@@ -27,6 +26,7 @@
"bootdevice=0:1\0" \
"usbload=usb reset;usbboot;usb stop;bootm\0"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
@@ -60,9 +60,6 @@
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF1 1
#define CONFIG_SCIF_EXT_CLOCK 1
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET
-#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
@@ -109,7 +106,6 @@
#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
/* PCI Controller */
-#define CONFIG_PCI
#define CONFIG_SH4_PCI
#define CONFIG_SH7780_PCI
#if defined(CONFIG_SH_32BIT)
@@ -121,7 +117,6 @@
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
#endif
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index fa76a25..9f22d4c 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -11,11 +11,6 @@
#define _CONFIG_SHEEVAPLUG_H
/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-Sheevaplug"
-
-/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
@@ -88,7 +83,6 @@
* SDIO/MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MVEBU_MMC
#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
diff --git a/include/configs/shmin.h b/include/configs/shmin.h
index e0fc3a2..dde6625 100644
--- a/include/configs/shmin.h
+++ b/include/configs/shmin.h
@@ -26,6 +26,7 @@
* you should set undef.
*/
#undef CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_DISPLAY_BOARDINFO
/* system */
#define SHMIN_SDRAM_BASE (0x8C000000)
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 3eca93b..e4d0ad9 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -16,7 +16,6 @@
#define CONFIG_AM33XX
#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
#include <asm/arch/omap.h>
@@ -78,7 +77,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
@@ -110,7 +108,6 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SERIAL1 1
#define CONFIG_CONS_INDEX 1
@@ -130,33 +127,17 @@
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_FS_FAT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_AM33XX_BCH
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
@@ -231,8 +212,6 @@
#define CONFIG_USBD_HS
/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
@@ -285,10 +264,7 @@
#define CONFIG_MTD_DEVICE
#define CONFIG_RBTREE
#define CONFIG_LZO
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_FASTMAP
-#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1
#endif
/* Commen environment */
diff --git a/include/configs/silk.h b/include/configs/silk.h
index 19c6297..a343cd1 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -88,7 +88,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* MMCIF */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR 0xee200000
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 8ad8f24..df5fe21 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -47,7 +47,6 @@
#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
-#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 32
@@ -166,8 +165,6 @@
#define CONFIG_USB_GADGET_AT91
/* DFU class support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#endif
@@ -239,13 +236,8 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_USE_NANDFLASH 1
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
@@ -283,6 +275,5 @@
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
deleted file mode 100644
index c8148bb..0000000
--- a/include/configs/smdk2410.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <garyj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * Configuation settings for the SAMSUNG SMDK2410 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
-#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
-#define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */
-
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-
-/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Hardware drivers
- */
-#define CONFIG_CS8900 /* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE 0x19000300
-#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_S3C24X0_SERIAL
-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
-
-/************************************************************
- * USB support (currently only works with D-cache off)
- ************************************************************/
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_OHCI_S3C24XX
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_DOS_PARTITION
-
-/************************************************************
- * RTC
- ************************************************************/
-#define CONFIG_RTC_S3C24X0
-
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_REGINFO
-
-#define CONFIG_CMDLINE_EDITING
-
-/* autoboot */
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_RESET_TO_RETRY
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.0.0.110
-#define CONFIG_SERVERIP 10.0.0.1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-
-#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x30800000
-
-/* support additional compression methods */
-#define CONFIG_BZIP2
-#define CONFIG_LZO
-#define CONFIG_LZMA
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT (19)
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 0x10000
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Size of malloc() pool
- * BZIP2 / LZO / LZMA need a lot of RAM
- */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_LEN (448 * 1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-/*
- * NAND configuration
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_S3C2410
-#define CONFIG_SYS_S3C2410_NAND_HWECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x4E000000
-#endif
-
-/*
- * File system
- */
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_YAFFS2
-#define CONFIG_RBTREE
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 92a0833..c152459 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -13,14 +13,12 @@
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
-#undef CONFIG_LCD
#undef CONFIG_EXYNOS_FB
#undef CONFIG_EXYNOS_DP
#undef CONFIG_KEYBOARD
#define CONFIG_BOARD_COMMON
-#define CONFIG_IDENT_STRING " for SMDK5250"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
#endif /* __CONFIG_SMDK_H */
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index a46ca74..502772c 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -13,7 +13,6 @@
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
-#undef CONFIG_LCD
#undef CONFIG_EXYNOS_FB
#undef CONFIG_EXYNOS_DP
@@ -31,7 +30,6 @@
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-#define CONFIG_IDENT_STRING " for SMDK5420"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
/* USB */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 9d52689..4292566 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -25,9 +25,6 @@
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* input clock of PLL: SMDKC100 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
@@ -167,7 +164,6 @@
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
-#define CONFIG_IDENT_STRING " for SMDKC100"
#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
#define CONFIG_ENABLE_MMU
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index efb18ff..ccb8921 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -67,7 +67,6 @@
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
/* FLASH and environment organization */
-#define CONFIG_IDENT_STRING " for SMDKC210/V310"
#define CONFIG_CLK_1000_400_200
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 978c627..8bd5806 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -28,7 +28,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_DISPLAY_CPUINFO
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index aab286f..a19a38b 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -26,7 +26,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
@@ -72,14 +71,11 @@
#define CONFIG_PARTITION_UUIDS
/* MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
/* LCD */
#define CONFIG_ATMEL_LCD
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_GURNARD_SPLASH
#define CONFIG_ATMEL_SPI
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 5062cd0..0a3d242 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -26,7 +26,6 @@
*/
#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
/*
* Board
@@ -96,7 +95,6 @@
* MMC
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
@@ -134,33 +132,14 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024)
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-/*
- * Console
- */
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
diff --git a/include/configs/snow.h b/include/configs/snow.h
index 1d8d8da..01d9db8 100644
--- a/include/configs/snow.h
+++ b/include/configs/snow.h
@@ -15,7 +15,6 @@
#define CONFIG_BOARD_COMMON
-#define CONFIG_IDENT_STRING " for snow"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
#endif /* __CONFIG_SNOW_H */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index b3fb245..31f1338 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -14,7 +14,6 @@
/*
* High level configuration
*/
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_ARCH_EARLY_INIT_R
@@ -143,7 +142,6 @@
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
@@ -209,6 +207,7 @@
#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
#endif
#define CONFIG_CQSPI_DECODER 0
+#define CONFIG_BOUNCE_BUFFER
/*
* Designware SPI support
@@ -241,10 +240,6 @@
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_FUNCTION_DFU
-#ifdef CONFIG_DM_MMC
-#define CONFIG_DFU_MMC
-#endif
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300
@@ -256,9 +251,6 @@
/*
* U-Boot environment
*/
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#if !defined(CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE 4096
#endif
@@ -300,7 +292,6 @@
/* UBI and UBIFS support */
#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
@@ -322,36 +313,18 @@
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE (64 * 1024)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#ifdef CONFIG_DM_MMC
-#define CONFIG_SPL_MMC_SUPPORT
-#endif
-#ifdef CONFIG_DM_SPI
-#define CONFIG_SPL_SPI_SUPPORT
-#endif
-#ifdef CONFIG_SPL_NAND_DENALI
-#define CONFIG_SPL_NAND_SUPPORT
-#endif
-
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
-#define CONFIG_SPL_LIBDISK_SUPPORT
#else
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */
-#define CONFIG_SPL_LIBDISK_SUPPORT
#endif
#endif
/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#endif
diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h
new file mode 100644
index 0000000..deec647
--- /dev/null
+++ b/include/configs/socfpga_de1_soc.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_TERASIC_DE1_SOC_H__
+#define __CONFIG_TERASIC_DE1_SOC_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE "fitImage"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdtaddr}\0" \
+ "bootimage=zImage\0" \
+ "fdtaddr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "bootm ${loadaddr} - ${fdtaddr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdtaddr} ${fdtimage}\0" \
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif /* __CONFIG_TERASIC_DE1_SOC_H__ */
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index 286e746..0407f03 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -25,7 +25,6 @@
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
/* Ethernet on SoC (EMAC) */
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
index 1c7d45e..c5555e6 100644
--- a/include/configs/socfpga_vining_fpga.h
+++ b/include/configs/socfpga_vining_fpga.h
@@ -192,9 +192,7 @@
"else echo \"Unsupported boot mode: \"${bootmode} ; " \
"fi\0" \
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_FASTMAP
#define CONFIG_RBTREE
#define CONFIG_LZO
#define MTDPARTS_DEFAULT \
@@ -217,10 +215,6 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_LATE_INIT
-/* Enable DFU to SF and RAM */
-#define CONFIG_DFU_RAM
-#define CONFIG_DFU_SF
-
/* Support changing the prompt string */
#define CONFIG_CMDLINE_PS_SUPPORT
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 29f9522..6480116 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -18,15 +18,10 @@
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8544 1
#define CONFIG_SOCRATES 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xfff80000
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_TSEC_ENET /* tsec ethernet support */
@@ -34,8 +29,6 @@
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
/*
* Only possible on E500 Version 2 or newer cores.
*/
@@ -75,7 +68,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
@@ -87,7 +79,6 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
@@ -169,18 +160,12 @@
#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
#define CONFIG_VIDEO_MB862xx_ACCEL
-#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
#define VIDEO_FB_16BPP_PIXEL_SWAP
#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
@@ -252,7 +237,6 @@
#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h
index 43a9623..b4a4fb0 100644
--- a/include/configs/som-6896.h
+++ b/include/configs/som-6896.h
@@ -20,16 +20,14 @@
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
-#define CONFIG_PCI_PNP
-
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_ARCH_EARLY_INIT_R
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x00ff0000
diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h
index a4b343e..6235518 100644
--- a/include/configs/som-db5800-som-6867.h
+++ b/include/configs/som-db5800-som-6867.h
@@ -18,10 +18,9 @@
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_PCI_PNP
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 7f6cb93..912b776 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -173,7 +173,6 @@
/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@@ -182,7 +181,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00800000
#define CONFIG_SYS_MEMTEST_END 0x04000000
#define CONFIG_SYS_MALLOC_LEN (1024*1024)
-#define CONFIG_IDENT_STRING "-SPEAr"
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE 256
@@ -191,7 +189,6 @@
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x00800000
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_FLASH_EMPTY_INFO
diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h
index 8090bc8..dd73a4d 100644
--- a/include/configs/spear3xx_evb.h
+++ b/include/configs/spear3xx_evb.h
@@ -12,22 +12,19 @@
* High Level Configuration Options
* (easy to change)
*/
-#if defined(CONFIG_spear300)
+#if defined(CONFIG_SPEAR300)
#define CONFIG_SPEAR3XX
-#define CONFIG_SPEAR300
-#elif defined(CONFIG_spear310)
+#elif defined(CONFIG_SPEAR310)
#define CONFIG_SPEAR3XX
-#define CONFIG_SPEAR310
-#elif defined(CONFIG_spear320)
+#elif defined(CONFIG_SPEAR320)
#define CONFIG_SPEAR3XX
-#define CONFIG_SPEAR320
#endif
-#if defined(CONFIG_usbtty)
+#if defined(CONFIG_USBTTY)
#define CONFIG_SPEAR_USBTTY
#endif
-#if defined(CONFIG_nand)
+#if defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#else
#define CONFIG_ENV_IS_IN_FLASH
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h
index 28dddcc..7745247 100644
--- a/include/configs/spear6xx_evb.h
+++ b/include/configs/spear6xx_evb.h
@@ -12,13 +12,11 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_SPEAR600
-
-#if defined(CONFIG_usbtty)
+#if defined(CONFIG_USBTTY)
#define CONFIG_SPEAR_USBTTY
#endif
-#if defined(CONFIG_nand)
+#if defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#else
#define CONFIG_ENV_IS_IN_FLASH
diff --git a/include/configs/spring.h b/include/configs/spring.h
index 8940123..d8c9b4a 100644
--- a/include/configs/spring.h
+++ b/include/configs/spring.h
@@ -13,7 +13,6 @@
#define CONFIG_BOARD_COMMON
-#define CONFIG_IDENT_STRING " for spring"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
#endif /* __CONFIG_SPRING_H */
diff --git a/include/configs/stout.h b/include/configs/stout.h
index e3b9325..0d9e4aa 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -92,7 +92,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/* Module stop status bits */
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 5fabbad..3be2597 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -20,24 +20,12 @@
#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#ifdef CONFIG_STRIDER_CPU_DP
-#define CONFIG_IDENT_STRING " strider cpu dp 0.01"
-#elif defined(CONFIG_STRIDER_CPU)
-#define CONFIG_IDENT_STRING " strider cpu 0.01"
-#elif defined(CONFIG_STRIDER_CON_DP)
-#define CONFIG_IDENT_STRING " strider con dp 0.01"
-#else
-#define CONFIG_IDENT_STRING " strider con 0.01"
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
@@ -518,12 +506,9 @@
/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM 1
-#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
@@ -583,8 +568,6 @@
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index bfd1bd7..09a3064 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -74,6 +74,7 @@
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
+#define CONFIG_BOUNCE_BUFFER
#endif
diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
index ea079eb..3dfd95a 100644
--- a/include/configs/sun4i.h
+++ b/include/configs/sun4i.h
@@ -14,7 +14,6 @@
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#define CONFIG_SUNXI_USB_PHYS 3
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
index 0fdb4c7..3e5708b 100644
--- a/include/configs/sun50i.h
+++ b/include/configs/sun50i.h
@@ -11,6 +11,11 @@
* A64 specific configuration
*/
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_SUNXI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
#define CONFIG_SUNXI_USB_PHYS 1
#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
index d257659..ec8f319 100644
--- a/include/configs/sun5i.h
+++ b/include/configs/sun5i.h
@@ -14,7 +14,6 @@
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
#define CONFIG_SUNXI_USB_PHYS 2
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
index 67a26c2..6c1eca4 100644
--- a/include/configs/sun6i.h
+++ b/include/configs/sun6i.h
@@ -17,7 +17,6 @@
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#define CONFIG_SUNXI_USB_PHYS 3
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index d8e6e20..5455901 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -15,7 +15,6 @@
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#define CONFIG_SUNXI_USB_PHYS 3
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index 011d70f..a4c3fb6 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -15,7 +15,6 @@
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
#ifdef CONFIG_MACH_SUN8I_H3
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 708ab17..b0bfc0d 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -35,7 +35,6 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_SUNXI /* sunxi family */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
#endif
@@ -54,7 +53,6 @@
#endif
/* CPU */
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_TIMER_CLK_FREQ 24000000
/*
@@ -69,7 +67,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */
#define CONFIG_SYS_TEXT_BASE 0x2a000000
-#define CONFIG_PRE_CON_BUF_ADDR 0x2f000000
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
@@ -80,7 +77,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
#define CONFIG_SYS_TEXT_BASE 0x4a000000
-#define CONFIG_PRE_CON_BUF_ADDR 0x4f000000
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
@@ -134,13 +130,11 @@
#ifdef CONFIG_NAND_SUNXI
#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
-#define CONFIG_SPL_NAND_SUPPORT 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 8
#endif
#ifdef CONFIG_SPL_SPI_SUNXI
-#define CONFIG_SPL_SPI_FLASH_SUPPORT 1
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#endif
@@ -151,6 +145,7 @@
#define CONFIG_MMC_SUNXI_SLOT 0
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
+#define CONFIG_SYS_MMC_MAX_DEVICE 4
#endif
/* 64MB of malloc() pool */
@@ -180,8 +175,6 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
-#define CONFIG_IDENT_STRING " Allwinner Technology"
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
@@ -189,9 +182,6 @@
#define CONFIG_FAT_WRITE /* enable write access */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_BOARD_LOAD_IMAGE
@@ -206,17 +196,10 @@
#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */
#endif
-#define CONFIG_SPL_LIBDISK_SUPPORT
-
-#ifdef CONFIG_MMC
-#define CONFIG_SPL_MMC_SUPPORT
-#endif
-
#ifndef CONFIG_ARM64
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
#endif
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
@@ -232,7 +215,6 @@
/* I2C */
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
defined CONFIG_SY8106A_POWER
-#define CONFIG_SPL_I2C_SUPPORT
#endif
#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
@@ -266,7 +248,6 @@
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \
defined CONFIG_SY8106A_POWER
-#define CONFIG_SPL_POWER_SUPPORT
#endif
#ifndef CONFIG_CONS_INDEX
@@ -293,7 +274,6 @@
/* GPIO */
#define CONFIG_SUNXI_GPIO
-#define CONFIG_SPL_GPIO_SUPPORT
#ifdef CONFIG_VIDEO
/*
@@ -307,17 +287,13 @@
#define CONFIG_VIDEO_SUNXI
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_STD_TIMINGS
#define CONFIG_I2C_EDID
#define VIDEO_LINE_LEN (pGD->plnSizeX)
/* allow both serial and cfb console. */
-#define CONFIG_CONSOLE_MUX
/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#endif /* CONFIG_VIDEO */
@@ -347,15 +323,10 @@
#endif
#ifdef CONFIG_USB_MUSB_GADGET
-#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#endif
-#ifdef CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_RAM
-#endif
-
#ifdef CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
@@ -374,9 +345,7 @@
#endif
#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_CONSOLE_MUX
#define CONFIG_PREBOOT
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
#endif
@@ -388,15 +357,10 @@
#endif
#define CONFIG_MISC_INIT_R
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
-/* Enable pre-console buffer to get complete log on the VGA console */
-#define CONFIG_PRE_CONSOLE_BUFFER
-#define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */
-
#ifdef CONFIG_ARM64
/*
* Boards seem to come with at least 512MB of DRAM.
diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
index 64e200e..e0c7674 100644
--- a/include/configs/t3corp.h
+++ b/include/configs/t3corp.h
@@ -359,9 +359,7 @@
* PCI stuff
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 8ce337e..0f59eb1 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -10,13 +10,9 @@
#ifndef __T4QDS_H
#define __T4QDS_H
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
@@ -29,9 +25,8 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
@@ -42,8 +37,6 @@
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
#define CONFIG_ENV_OVERWRITE
/*
@@ -90,13 +83,11 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
/*
* IFC Definitions
@@ -215,7 +206,6 @@
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index a63db65..44201a2 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -15,7 +15,6 @@
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
@@ -28,12 +27,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -80,7 +73,6 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
@@ -201,20 +193,10 @@
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
@@ -226,7 +208,6 @@
#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
@@ -260,7 +241,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 696ca32..03fc42c 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -19,7 +19,6 @@
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
@@ -32,12 +31,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -78,7 +71,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
@@ -282,27 +274,15 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 2c41dd8..ab457da 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -47,7 +47,6 @@
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
@@ -128,8 +127,6 @@
#define CONFIG_USB_GADGET_AT91
/* DFU class support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#endif
@@ -142,9 +139,6 @@
#if defined(CONFIG_SPL_BUILD)
/* SPL related */
-#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
@@ -258,14 +252,8 @@
#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_USE_NANDFLASH 1
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 85501bc..0dc4a28 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -39,26 +39,22 @@
#define CONFIG_SYS_MEMTEST_END \
(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ 0x6C000000
+#define CONFIG_SYS_BOOTMAPSZ 0x10000000
/* Serial console */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_CONSOLE_MUX
#define CONFIG_CONS_INDEX 1
-#define CONFIG_PRE_CONSOLE_BUFFER
-#define CONFIG_PRE_CON_BUF_SZ 4096
-#define CONFIG_PRE_CON_BUF_ADDR 0x7C000000
-
/* *** Command definition *** */
#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_PART
/* Filesystems / image support */
#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
@@ -77,14 +73,9 @@
#define CONFIG_PHY_ATHEROS
/* Framebuffer */
-#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IPUV3_CLK 260000000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_CFB_CONSOLE_ANSI
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
@@ -94,8 +85,6 @@
/* PCI */
#define CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
@@ -123,10 +112,8 @@
#define CONFIG_USBD_HS
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#endif /* CONFIG_CMD_USB_MASS_STORAGE */
-#define CONFIG_USB_KEYBOARD
#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_PREBOOT \
"usb start; " \
"if hdmidet; then " \
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index c294f70..97aa046 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -118,7 +118,6 @@
/*
* SPI_MMC Settings
*/
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
index 0e9d98c..067e171 100644
--- a/include/configs/tec-ng.h
+++ b/include/configs/tec-ng.h
@@ -21,7 +21,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 7b14299..c03dabf 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -20,7 +20,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index a9990b7..5144d5a 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -115,9 +115,6 @@
#endif
/* remove MMC support */
-#ifdef CONFIG_MMC
-#undef CONFIG_MMC
-#endif
#ifdef CONFIG_GENERIC_MMC
#undef CONFIG_GENERIC_MMC
#endif
diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h
index 3e3eeea..58a5a30 100644
--- a/include/configs/tegra-common-usb-gadget.h
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -10,20 +10,14 @@
#ifndef CONFIG_SPL_BUILD
/* USB gadget mode support*/
+#ifndef CONFIG_TEGRA20
#define CONFIG_CI_UDC_HAS_HOSTPC
+#endif
/* USB mass storage protocol */
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* DFU protocol */
-#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M
-#ifdef CONFIG_MMC
-#define CONFIG_DFU_MMC
-#endif
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_DFU_SF
-#endif
-#define CONFIG_DFU_RAM
#endif
#endif /* _TEGRA_COMMON_USB_GADGET_H_ */
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 7b0940a..23a0e78 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -24,12 +24,6 @@
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
#endif
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
/* Environment */
@@ -66,33 +60,22 @@
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_STDIO_DEREGISTER
-#endif
-
/*
* Increasing the size of the IO buffer as default nfsargs size is more
* than 256 and so it is not possible to edit it
*/
-#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
+
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
-#ifndef CONFIG_ARM64
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_USE_ARCH_MEMCPY
-#endif
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
@@ -122,11 +105,6 @@
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 8bbf879..281593a 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -63,7 +63,6 @@
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PREBOOT
@@ -86,9 +85,7 @@
/* PCIe support */
#ifdef CONFIG_CMD_PCI
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
-#define CONFIG_PCI_PNP
#define CONFIG_BOARD_LATE_INIT /* for PEX switch test */
#endif
#endif
@@ -96,9 +93,6 @@
/* Enable LCD and reserve 512KB from top of memory*/
#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CMD_BMP
/* FPGA programming support */
@@ -149,14 +143,7 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
index 25ac2cb..a235253 100644
--- a/include/configs/thuban.h
+++ b/include/configs/thuban.h
@@ -15,7 +15,6 @@
#include "siemens-am33x-common.h"
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_MPUCLK 300
#define DDR_PLL_FREQ 303
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
@@ -42,12 +41,6 @@
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
-
-#undef CONFIG_SPL_NET_SUPPORT
-#undef CONFIG_SPL_NET_VCI_STRING
-#undef CONFIG_SPL_ETH_SUPPORT
-
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
#define CONFIG_PHY_SMSC
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 5c3b3da..a546db2 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -15,9 +15,6 @@
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_IDENT_STRING \
- " for Cavium Thunder CN88XX ARM v8 Multi-Core"
-
#define MEM_BASE 0x00500000
#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
@@ -52,9 +49,6 @@
#define CONFIG_BAUDRATE 115200
-/* Command line configuration */
-#define CONFIG_MENU
-
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 82ab479..86ab1e0 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -20,7 +20,6 @@
#define CONFIG_TI814X
#define CONFIG_SYS_NO_FLASH
#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
#include <asm/arch/omap.h>
@@ -114,7 +113,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */
#define CONFIG_OMAP_GPIO
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
@@ -149,7 +147,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_ENV_IS_NOWHERE
@@ -162,22 +159,12 @@
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index e3cd647..d909f25 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -14,7 +14,6 @@
#define CONFIG_TI816X
#define CONFIG_SYS_NO_FLASH
#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
#define CONFIG_ARCH_CPU_INIT
@@ -29,8 +28,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG /* required for ramdisk support */
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x81000000\0" \
@@ -55,7 +52,6 @@
#define CONFIG_CMD_ASKEN
#define CONFIG_OMAP_GPIO
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
@@ -114,7 +110,6 @@
#define CONFIG_SERIAL2
#define CONFIG_SERIAL3
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_ENV_IS_NOWHERE
@@ -128,22 +123,12 @@
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 9a671de..809d015 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -12,7 +12,6 @@
#ifndef __CONFIG_TI_AM335X_COMMON_H__
#define __CONFIG_TI_AM335X_COMMON_H__
-#define CONFIG_AM33XX
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
@@ -57,12 +56,11 @@
* supports X-MODEM loading via UART, and we leverage this and then use
* Y-MODEM to load u-boot.img, when booted over UART.
*/
-#define CONFIG_SPL_TEXT_BASE 0x402F0400
+#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
/* Enable the watchdog inside of SPL */
-#define CONFIG_SPL_WATCHDOG_SUPPORT
/*
* Since SPL did pll and ddr initialization for us,
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 32cb202..dbe494a 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -54,7 +54,8 @@
"ramdisk_addr_r=0x88080000\0" \
"scriptaddr=0x80000000\0" \
"pxefile_addr_r=0x80100000\0" \
- "bootm_size=0x10000000\0"
+ "bootm_size=0x10000000\0" \
+ "boot_fdt=try\0"
#define DEFAULT_MMC_TI_ARGS \
"mmcdev=0\0" \
@@ -71,6 +72,8 @@
"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
+ "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"envboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
@@ -87,6 +90,42 @@
"fi;" \
"fi;" \
"fi;\0" \
+ "mmcloados=run args_mmc; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "mmcboot=mmc dev ${mmcdev}; " \
+ "setenv devnum ${mmcdev}; " \
+ "setenv devtype mmc; " \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadimage; then " \
+ "if test ${boot_fit} -eq 1; then " \
+ "run loadfit; " \
+ "else " \
+ "run mmcloados;" \
+ "fi;" \
+ "fi;" \
+ "fi;\0" \
+
+#define DEFAULT_FIT_TI_ARGS \
+ "boot_fit=0\0" \
+ "fit_loadaddr=0x88000000\0" \
+ "fit_bootfile=fitImage.itb\0" \
+ "update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \
+ "args_fit=setenv bootargs console=${console} \0" \
+ "loadfit=run args_fit; bootm ${loadaddr}:kernel@1 " \
+ "${loadaddr}:ramdisk@1 ${loadaddr}:${fdtfile};\0" \
/*
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
@@ -129,7 +168,6 @@
#endif
/* MMC/SD IP block */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/* McSPI IP block */
@@ -146,12 +184,7 @@
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
-#ifdef CONFIG_DFU_MMC
-#define CONFIG_SYS_MALLOC_LEN ((16 << 20) + CONFIG_SYS_DFU_DATA_BUF_SIZE)
-#else
-#define CONFIG_SYS_MALLOC_LEN (16 << 20)
-#endif
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_BAUDRATE 115200
#define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */
#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
@@ -165,7 +198,7 @@
#define CONFIG_SYS_MAXARGS 64
/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_CBSIZE 1024
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -197,16 +230,18 @@
/*
* Our platforms make use of SPL to initalize the hardware (primarily
- * memory) enough for full U-Boot to be loaded. We also support Falcon
- * Mode so that the Linux kernel can be booted directly from SPL
- * instead, if desired. We make use of the general SPL framework found
- * under common/spl/. Given our generally common memory map, we set a
- * number of related defaults and sizes here.
+ * memory) enough for full U-Boot to be loaded. We make use of the general
+ * SPL framework found under common/spl/. Given our generally common memory
+ * map, we set a number of related defaults and sizes here.
*/
#if !defined(CONFIG_NOR_BOOT) && \
!(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_OS_BOOT
+
+/*
+ * We also support Falcon Mode so that the Linux kernel can be booted
+ * directly from SPL. This is not currently available on HS devices.
+ */
/*
* Place the image at the start of the ROM defined image space (per
@@ -230,7 +265,7 @@
#ifndef CONFIG_SYS_SPL_MALLOC_START
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_8M
#endif
#ifndef CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
@@ -238,10 +273,6 @@
#endif
-/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-
/* FAT sd card locations. */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
@@ -260,30 +291,15 @@
#define CONFIG_CMD_SPL
#endif
-#ifdef CONFIG_MMC
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_EXT_SUPPORT
-#endif
-
#define CONFIG_SYS_THUMB_BUILD
/* General parts of the framework, required. */
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_MTD_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#endif
#endif /* !CONFIG_NOR_BOOT */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index c8df48a..28a80f5 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -15,7 +15,6 @@
/* U-Boot Build Configuration */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
@@ -54,8 +53,6 @@
CONFIG_SYS_SPL_MALLOC_SIZE + \
SPL_MALLOC_F_SIZE + \
CONFIG_SPL_STACK_SIZE - 4)
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
@@ -70,14 +67,14 @@
#define CONFIG_CONS_INDEX 1
#ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
#else
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2
+#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2
#endif
/* SPI Configuration */
#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SYS_SPI0
@@ -206,7 +203,6 @@
/* U-Boot command configuration */
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_EEPROM
@@ -224,6 +220,8 @@
"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \
"init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; " \
"run set_rd_spec\0" \
+ "init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; " \
+ "run set_rd_spec\0" \
"init_fw_rd_ramfs=setenv rd_spec -\0" \
"init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \
"run set_rd_spec\0" \
@@ -232,6 +230,7 @@
"set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \
"dev_pmmc=0\0" \
"get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \
+ "get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0" \
"get_pmmc_ramfs=run get_pmmc_net\0" \
"get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \
"${bootdir}/${name_pmmc}\0" \
@@ -250,6 +249,7 @@
"addr_ubi=0x82000000\0" \
"addr_secdb_key=0xc000000\0" \
"name_kern=zImage\0" \
+ "addr_mon=0x87000000\0" \
"run_mon=mon_install ${addr_mon}\0" \
"run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \
"init_net=run args_all args_net\0" \
@@ -294,8 +294,8 @@
#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
- "run init_${boot} init_fw_rd_${boot} get_fdt_${boot} " \
- "get_mon_${boot} get_kern_${boot} run_mon run_kern"
+ "run init_${boot} get_mon_${boot} run_mon init_fw_rd_${boot} " \
+ "get_fdt_${boot} get_kern_${boot} run_kern"
#endif
#define CONFIG_BOOTARGS \
@@ -304,24 +304,17 @@
#include <configs/ti_armv7_common.h>
/* We wont be loading up OS from SPL for now.. */
-#undef CONFIG_SPL_OS_BOOT
/* We do not have MMC support.. yet.. */
-#undef CONFIG_SPL_LIBDISK_SUPPORT
-#undef CONFIG_SPL_MMC_SUPPORT
-#undef CONFIG_SPL_FAT_SUPPORT
-#undef CONFIG_SPL_EXT_SUPPORT
-#undef CONFIG_MMC
#undef CONFIG_GENERIC_MMC
/* And no support for GPIO, yet.. */
-#undef CONFIG_SPL_GPIO_SUPPORT
/* we may include files below only after all above definitions */
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
#else
#define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk]
#endif
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
index 7548170..6d9d4b2 100644
--- a/include/configs/ti_armv7_omap.h
+++ b/include/configs/ti_armv7_omap.h
@@ -14,7 +14,6 @@
/* Common defines for all OMAP architecture based SoCs */
#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
/* I2C IP block */
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 33426c8..0ad3235 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -68,8 +68,7 @@
/* SPL */
#define CONFIG_SPL_TEXT_BASE 0x40200800
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(64 << 20))
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 8c88ebf..8e0f9eb 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -17,8 +17,6 @@
*/
#define CONFIG_OMAP4430 1 /* which is in a 4430 */
#define CONFIG_MISC_INIT_R
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_SYS_THUMB_BUILD
@@ -75,7 +73,6 @@
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/*
* Environment setup
@@ -101,6 +98,9 @@
func(DHCP, dhcp, na)
#define CONFIG_BOOTCOMMAND \
+ "if test ${boot_fit} -eq 1; then " \
+ "run update_to_fit;" \
+ "fi;" \
"run findfdt; " \
"run envboot; " \
"run distro_bootcmd"
@@ -110,6 +110,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
"console=ttyO2,115200n8\0" \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
@@ -117,14 +118,7 @@
"bootfile=zImage\0" \
"usbtty=cdc_acm\0" \
"vram=16M\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run args_mmc; " \
- "if run loadimage; then " \
- "run loadfdt; " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi;\0" \
"uimageboot=echo Booting from mmc${mmcdev} ...; " \
"run args_mmc; " \
"bootm ${loadaddr}\0" \
@@ -141,7 +135,6 @@
"setenv fdtfile omap4-duovero-parlor.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
BOOTENV
/*
@@ -151,8 +144,7 @@
* So moving TEXT_BASE down to non-HS limit.
*/
#define CONFIG_SPL_TEXT_BASE 0x40300000
-#define CONFIG_SPL_DISPLAY_PRINT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
@@ -164,7 +156,6 @@
/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
#undef CONFIG_SYS_I2C
#undef CONFIG_SYS_I2C_OMAP24XX
-#undef CONFIG_SPL_I2C_SUPPORT
#endif
#endif /* __CONFIG_TI_OMAP4_COMMON_H */
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index cbdf0bc..37d6565 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -17,9 +17,6 @@
#ifndef __CONFIG_TI_OMAP5_COMMON_H
#define __CONFIG_TI_OMAP5_COMMON_H
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_798870
@@ -64,11 +61,11 @@
#define DFUARGS
#endif
-#ifndef CONFIG_SPL_BUILD
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
"console=" CONSOLEDEV ",115200n8\0" \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
@@ -79,20 +76,6 @@
"partitions=" PARTS_DEFAULT "\0" \
"optargs=\0" \
"dofastboot=0\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadimage; then " \
- "run loadfdt; " \
- "echo Booting from mmc${mmcdev} ...; " \
- "run args_mmc; " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi;" \
- "fi;\0" \
"findfdt="\
"if test $board_name = omap5_uevm; then " \
"setenv fdtfile omap5-uevm.dtb; fi; " \
@@ -102,15 +85,22 @@
"setenv fdtfile dra72-evm-revc.dtb; fi;" \
"if test $board_name = dra72x; then " \
"setenv fdtfile dra72-evm.dtb; fi;" \
+ "if test $board_name = dra71x; then " \
+ "setenv fdtfile dra71-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \
"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+ "if test $board_name = beagle_x15_revb1; then " \
+ "setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \
"if test $board_name = am572x_idk; then " \
"setenv fdtfile am572x-idk.dtb; fi;" \
"if test $board_name = am57xx_evm; then " \
"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+ "if test $board_name = am57xx_evm_reva3; then " \
+ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+ "if test $board_name = am571x_idk; then " \
+ "setenv fdtfile am571x-idk.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
DFUARGS \
NETARGS \
@@ -118,8 +108,12 @@
"if test ${dofastboot} -eq 1; then " \
"echo Boot fastboot requested, resetting dofastboot ...;" \
"setenv dofastboot 0; saveenv;" \
- "echo Booting into fastboot ...; fastboot 0;" \
+ "echo Booting into fastboot ...; " \
+ "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \
"fi;" \
+ "if test ${boot_fit} -eq 1; then " \
+ "run update_to_fit;" \
+ "fi;" \
"run findfdt; " \
"run envboot; " \
"run mmcboot;" \
@@ -128,7 +122,6 @@
"setenv mmcroot /dev/mmcblk0p2 rw; " \
"run mmcboot;" \
""
-#endif
/*
* SPL related defines. The Public RAM memory map the ROM defines the
@@ -146,6 +139,14 @@
*/
#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
#define CONFIG_SPL_TEXT_BASE 0x40301350
+/* If no specific start address is specified then the secure EMIF
+ * region will be placed at the end of the DDR space. In order to prevent
+ * the main u-boot relocation from clobbering that memory and causing a
+ * firewall violation, we tell u-boot that memory is protected RAM (PRAM)
+ */
+#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
+#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
+#endif
#else
/*
* For all booting on GP parts, the flash loader image is
@@ -154,8 +155,7 @@
#define CONFIG_SPL_TEXT_BASE 0x40300000
#endif
-#define CONFIG_SPL_DISPLAY_PRINT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
index f550aab..bbdaf04 100644
--- a/include/configs/titanium.h
+++ b/include/configs/titanium.h
@@ -197,7 +197,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#endif /* __CONFIG_H */
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
new file mode 100644
index 0000000..3b0fa29
--- /dev/null
+++ b/include/configs/topic_miami.h
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2014 Topic Embedded Products
+ *
+ * Configuration for Zynq Evaluation and Development Board - Miami
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_TOPIC_MIAMI_H
+#define __CONFIG_TOPIC_MIAMI_H
+
+#define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL
+
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_I2C1
+
+/* Speed up boot time by ignoring the environment which we never used */
+#define CONFIG_ENV_IS_NOWHERE
+
+#include "zynq-common.h"
+
+/* Fixup settings */
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE 0x8000
+#undef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x80000
+
+/* SPL settings */
+#undef CONFIG_SPL_ETH_SUPPORT
+#undef CONFIG_SYS_SPI_U_BOOT_OFFS
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#undef CONFIG_SPL_MAX_FOOTPRINT
+#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+
+/* sspi command isn't useful */
+#undef CONFIG_CMD_SPI
+
+/* No useful gpio */
+#undef CONFIG_ZYNQ_GPIO
+#undef CONFIG_CMD_GPIO
+
+/* No falcon support */
+#undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_SPL_FPGA_SUPPORT
+
+/* FPGA commands that we don't use */
+#undef CONFIG_CMD_FPGA_LOADMK
+#undef CONFIG_CMD_FPGA_LOADP
+#undef CONFIG_CMD_FPGA_LOADBP
+#undef CONFIG_CMD_FPGA_LOADFS
+
+/* Extras */
+#define CONFIG_CMD_MEMTEST
+#undef CONFIG_SYS_MEMTEST_START
+#define CONFIG_SYS_MEMTEST_START 0
+#undef CONFIG_SYS_MEMTEST_END
+#define CONFIG_SYS_MEMTEST_END 0x18000000
+
+/* Faster flash, ours may run at 108 MHz */
+#undef CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SF_DEFAULT_SPEED 108000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#undef CONFIG_SF_DUAL_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#undef CONFIG_SPI_FLASH_WINBOND
+#undef CONFIG_SPI_FLASH_ISSI
+
+/* Setup proper boot sequences for Miami boards */
+
+#if defined(CONFIG_USB)
+# define EXTRA_ENV_USB \
+ "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
+ "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
+ "usbboot=run usbreset && if usb start; then " \
+ "echo Booting from USB... && " \
+ "if load usb 0 0x1900000 ${bootscript}; then "\
+ "source 0x1900000; fi; " \
+ "load usb 0 ${kernel_addr} ${kernel_image} && " \
+ "load usb 0 ${devicetree_addr} ${devicetree_image} && " \
+ "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \
+ "bootm ${kernel_addr} ${ramdisk_load_address} "\
+ "${devicetree_addr}; " \
+ "fi\0"
+ /* Note that addresses here should match the addresses in the env */
+# undef DFU_ALT_INFO
+# define DFU_ALT_INFO \
+ "dfu_alt_info=" \
+ "uImage ram 0x2080000 0x500000;" \
+ "devicetree.dtb ram 0x2000000 0x20000;" \
+ "uramdisk.image.gz ram 0x4000000 0x10000000\0" \
+ "dfu_ram=run usbreset && dfu 0 ram 0\0" \
+ "thor_ram=run usbreset && thordown 0 ram 0\0"
+#else
+# define EXTRA_ENV_USB
+#endif
+
+#undef CONFIG_PREBOOT
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_image=uImage\0" \
+ "kernel_addr=0x2080000\0" \
+ "ramdisk_image=uramdisk.image.gz\0" \
+ "ramdisk_load_address=0x4000000\0" \
+ "devicetree_image=devicetree.dtb\0" \
+ "devicetree_addr=0x2000000\0" \
+ "bitstream_image=fpga.bin\0" \
+ "bootscript=autorun.scr\0" \
+ "loadbit_addr=0x100000\0" \
+ "loadbootenv_addr=0x2000000\0" \
+ "kernel_size=0x400000\0" \
+ "devicetree_size=0x10000\0" \
+ "boot_size=0xF00000\0" \
+ "fdt_high=0x20000000\0" \
+ "initrd_high=0x20000000\0" \
+ "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
+ "mmcinfo && " \
+ "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+ "fpga load 0 ${loadbit_addr} ${filesize}\0" \
+ "qspiboot=echo Booting from QSPI flash... && " \
+ "sf probe && " \
+ "sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \
+ "sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \
+ "bootm ${kernel_addr} - ${devicetree_addr}\0" \
+ "sdboot=if mmcinfo; then " \
+ "setenv bootargs console=ttyPS0,115200 " \
+ "root=/dev/mmcblk0p2 rw rootfstype=ext4 " \
+ "rootwait quiet ; " \
+ "load mmc 0 ${kernel_addr} ${kernel_image}&& " \
+ "load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \
+ "bootm ${kernel_addr} - ${devicetree_addr}; " \
+ "fi\0" \
+ EXTRA_ENV_USB \
+ DFU_ALT_INFO
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND "if mmcinfo; then " \
+ "if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; " \
+ "fi; fi; run $modeboot"
+#undef CONFIG_DISPLAY_BOARDINFO
+
+/* Further tweaks to reduce image size */
+#undef CONFIG_CMD_BOOTZ
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_AES
+
+#endif /* __CONFIG_TOPIC_MIAMI_H */
diff --git a/include/configs/topic_miamiplus.h b/include/configs/topic_miamiplus.h
new file mode 100644
index 0000000..46ca6bd
--- /dev/null
+++ b/include/configs/topic_miamiplus.h
@@ -0,0 +1,2 @@
+#include "topic_miami.h"
+#define CONFIG_SF_DUAL_FLASH
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 7bf8e4c..fefc902 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_HZ 1000
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 3173dc0..983153f 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -12,11 +12,6 @@
#include <linux/kconfig.h>
/* SPL */
/* #if defined(CONFIG_SPL_BUILD) */
-
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-
/* common IMX6 SPL configuration */
#include "imx6_spl.h"
@@ -300,7 +295,7 @@
"uboot=u-boot.imx\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV "\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h
index 2f52598..265aa4a 100644
--- a/include/configs/tqma6_mba6.h
+++ b/include/configs/tqma6_mba6.h
@@ -9,12 +9,6 @@
#ifndef __CONFIG_TQMA6_MBA6_H
#define __CONFIG_TQMA6_MBA6_H
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
-#define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb"
-#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb"
-#endif
-
#define CONFIG_DTT_SENSORS { 0, 1 }
#define CONFIG_FEC_XCV_TYPE RGMII
@@ -25,6 +19,6 @@
#define CONFIG_PHY_KSZ9031
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc1"
+#define CONSOLE_DEV "ttymxc1"
#endif /* __CONFIG_TQMA6_MBA6_H */
diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
index 8896bc3..96f15cd 100644
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_TQMA6_WRU4_H
#define __CONFIG_TQMA6_WRU4_H
-#define CONFIG_DEFAULT_FDT_FILE "imx6s-wru4.dtb"
-
/* DTT sensors */
#define CONFIG_DTT_SENSORS { 0, 1 }
#define CONFIG_SYS_DTT_BUS_NUM 2
@@ -21,7 +19,7 @@
/* UART */
#define CONFIG_MXC_UART_BASE UART4_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc3"
+#define CONSOLE_DEV "ttymxc3"
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 22b0c90..a771ddb 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -41,8 +41,6 @@
#define CONFIG_BAUDRATE 115200
/* Console configuration */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
#define MACH_TYPE_TRATS 3928
@@ -180,36 +178,6 @@
/* GPT */
#define CONFIG_RANDOM_UUID
-/* I2C */
-#include <asm/arch/gpio.h>
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_S3C24X0
-#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
-#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE
-#define CONFIG_MAX_I2C_NUM 8
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-#define CONFIG_SOFT_I2C_READ_REPEATED_START
-#define CONFIG_SYS_I2C_INIT_BOARD
-
-/* I2C FG */
-#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41
-#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40
-
-/* POWER */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_MAX8997
-
-#define CONFIG_POWER_FG
-#define CONFIG_POWER_FG_MAX17042
-#define CONFIG_POWER_MUIC
-#define CONFIG_POWER_MUIC_MAX8997
-#define CONFIG_POWER_BATTERY
-#define CONFIG_POWER_BATTERY_TRATS
-
/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_LIB_HW_RAND
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 1febaae..1cd3e14 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -38,8 +38,6 @@
#define CONFIG_BAUDRATE 115200
/* Console configuration */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run autoboot"
@@ -157,39 +155,6 @@
/* GPT */
#define CONFIG_RANDOM_UUID
-/* I2C */
-#include <asm/arch/gpio.h>
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_S3C24X0
-#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
-#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
-#define CONFIG_MAX_I2C_NUM 8
-#define CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
-#define I2C_SOFT_DECLARATIONS2
-#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00
-#define CONFIG_SOFT_I2C_READ_REPEATED_START
-#define CONFIG_SYS_I2C_INIT_BOARD
-
-#ifndef __ASSEMBLY__
-int get_soft_i2c_scl_pin(void);
-int get_soft_i2c_sda_pin(void);
-#endif
-#define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin()
-#define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin()
-
-/* POWER */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_MAX77686
-#define CONFIG_POWER_PMIC_MAX77693
-#define CONFIG_POWER_MUIC_MAX77693
-#define CONFIG_POWER_FG_MAX77693
-#define CONFIG_POWER_BATTERY_TRATS2
-
/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_LIB_HW_RAND
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index e5d321a..1c36d07 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -19,7 +19,6 @@
/* High Level Configuration Options */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
@@ -39,12 +38,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SILENT_CONSOLE
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
@@ -96,7 +89,6 @@
/* MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
@@ -146,7 +138,6 @@
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
-#define CONFIG_CMD_UBI /* UBI commands */
#define CONFIG_CMD_UBIFS /* UBIFS commands */
#define CONFIG_LZO /* LZO is needed for UBIFS */
@@ -319,23 +310,12 @@
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index a4ca7c7..ff00614 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -28,7 +28,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -49,8 +48,6 @@
#define CONFIG_USB_ETHER_ASIX
/* PCI host support */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
/* General networking support */
diff --git a/include/configs/ts4600.h b/include/configs/ts4600.h
new file mode 100644
index 0000000..9b7bd1b
--- /dev/null
+++ b/include/configs/ts4600.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Derived from MX28EVK code by
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ * Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the TS4600 Board
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIGS_TS4600_H__
+#define __CONFIGS_TS4600_H__
+
+/* System configurations */
+#define CONFIG_MX28 /* i.MX28 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH /* No NOR Flash */
+#define CONFIG_DOS_PARTITION
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+/* Boot Linux */
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr=0x41000000\0" \
+ "loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \
+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} imx28-ts4600.dtb\0" \
+ "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ub\0" \
+ "bootscript=echo Running bootscript from mmc...; " \
+ "setenv mmcdev 0; " \
+ "setenv mmcpart 2; " \
+ "run loadbootscript && source ${loadaddr}; \0" \
+ "sdboot=echo Booting from SD card ...; " \
+ "setenv mmcdev 0; " \
+ "setenv mmcpart 2; " \
+ "setenv root /dev/mmcblk0p3; " \
+ "run loadkernel && run loadfdt; \0" \
+ "startbootsequence=run bootscript || run sdboot \0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc rescan; " \
+ "run startbootsequence; " \
+ "setenv cmdline_append console=ttyAMA0,115200; " \
+ "setenv bootargs root=${root} rootwait rw ${cmdline_append}; " \
+ "bootz ${loadaddr} - ${fdt_addr}; "
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_TS4600_H__ */
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index 252b3fc..a451acf 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -16,9 +16,6 @@
/* High Level Configuration Options */
#define CONFIG_MX51
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_SYS_NO_FLASH /* No NOR Flash */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */
@@ -62,10 +59,6 @@
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
-
-#define CONFIG_MMC
-
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/twister.h b/include/configs/twister.h
index 66f4680..fd117b8 100644
--- a/include/configs/twister.h
+++ b/include/configs/twister.h
@@ -42,7 +42,6 @@
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
0x600000)
-#define CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_SPL_BOARD_INIT
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index fba78d0..0a7767c 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -11,8 +11,6 @@
#include "mx6_common.h"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
#define MACH_TYPE_UDOO 4800
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
new file mode 100644
index 0000000..915d0f0
--- /dev/null
+++ b/include/configs/udoo_neo.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright Jasbir Matharu
+ * Copyright 2015 UDOO Team
+ *
+ * Configuration settings for the UDOO NEO board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_UART
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+
+/* Command definition */
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/
+
+/* Linux only */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdtfile=undefined\0" \
+ "fdt_addr=0x83000000\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=0\0" \
+ "mmcrootfstype=ext4\0" \
+ "findfdt="\
+ "if test $board_name = BASIC; then " \
+ "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \
+ "if test $board_name = BASICKS; then " \
+ "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \
+ "if test $board_name = FULL; then " \
+ "setenv fdtfile imx6sx-udoo-neo-full.dtb; fi; " \
+ "if test $board_name = EXTENDED; then " \
+ "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \
+ "if test $fdtfile = UNDEFINED; then " \
+ "echo WARNING: Could not determine dtb to use; fi; \0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "ramdisk_addr_r=0x83000000\0" \
+ "ramdiskaddr=0x83000000\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(DHCP, dhcp, na)
+
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_IMX_THERMAL
+
+/* I2C configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
+#define PFUZE3000_I2C_BUS 0
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+
+#define CONFIG_FEC_ENET_DEV 0
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC0"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index b3ca46b..74f1373 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -15,12 +15,6 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_SMC911X
-
-/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
-#define CONFIG_SMC911X_BASE 0
-#define CONFIG_SMC911X_32_BIT
-
/*-----------------------------------------------------------------------
* MMU and Cache Setting
*----------------------------------------------------------------------*/
@@ -29,11 +23,6 @@
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_MISC_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
@@ -43,10 +32,15 @@
/* FLASH related */
#define CONFIG_MTD_DEVICE
-/*
- * uncomment the following to disable FLASH related code.
- */
-/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_SMC911X_32_BIT
+/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
+#define CONFIG_SMC911X_BASE 0
+
+#ifdef CONFIG_MICRO_SUPPORT_CARD
+#define CONFIG_SMC911X
+#else
+#define CONFIG_SYS_NO_FLASH
+#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
@@ -57,7 +51,7 @@
#define CONFIG_SYS_FLASH_BASE 0
/*
- * flash_toggle does not work for out supoort card.
+ * flash_toggle does not work for our support card.
* We need to use flash_status_poll.
*/
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
@@ -69,11 +63,6 @@
/* serial console configuration */
#define CONFIG_BAUDRATE 115200
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
-#define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_USE_ARCH_MEMCPY
-#endif
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* add command line history */
@@ -132,7 +121,6 @@
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* USB */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION
@@ -277,25 +265,16 @@
#define CONFIG_PANIC_HANG
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NOR_SUPPORT
#ifdef CONFIG_ARM64
#define CONFIG_SPL_BOARD_LOAD_IMAGE
-#else
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#endif
-#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
/* subtract sizeof(struct image_header) */
#define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 39ac189..075d9c9 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -31,8 +31,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_DISPLAY_CPUINFO
-
#define CONFIG_SYS_TEXT_BASE 0x23f00000
/*
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 23092db..904b772 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -12,8 +12,6 @@
#define __CONFIG_H
#define CONFIG_MX53
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_FSL_CLK
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO
@@ -45,7 +43,6 @@
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/* USB */
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 03ff0c6..229c242 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -14,7 +14,6 @@
*/
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_V38B 1 /* ...on V38B board */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xFF000000
@@ -57,7 +56,6 @@
/*
* PCI - no support
*/
-#undef CONFIG_PCI
/*
* Partitions
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 168902c..6ff22c2 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -25,8 +25,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
@@ -142,7 +140,6 @@
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
/*
* FLASH and environment organization
@@ -246,7 +243,6 @@
#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_SYS_USE_UBI
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 83d0004..e293f12 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -13,8 +13,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
@@ -27,7 +25,6 @@
#define CONFIG_SYS_TEXT_BASE 0xfe000000
#endif
-#define CONFIG_PCI 1
#define CONFIG_PCI_INDIRECT_BRIDGE 1
#define CONFIG_FSL_ELBC 1
@@ -271,7 +268,6 @@
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index 72fa973..7c7b200 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h
@@ -23,7 +23,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index b282467..f5459a8 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -21,7 +21,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
@@ -42,11 +41,9 @@
/* General networking support */
/* USB keyboard */
-#define CONFIG_USB_KEYBOARD
/* LCD support */
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
#include "tegra-common-post.h"
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 71c4a1f..f026f35 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -19,8 +19,6 @@
#define CONFIG_SUPPORT_RAW_INITRD
-#define CONFIG_IDENT_STRING " vexpress_aemv8a"
-
/* Link Definitions */
#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
@@ -127,11 +125,8 @@
#define CONFIG_PL011_CLOCK 24000000
#endif
-/* Command line configuration */
-#define CONFIG_MENU
/*#define CONFIG_MENU_SHOW*/
#define CONFIG_CMD_UNZIP
-#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index a8eba31..0bc4ea5 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -150,7 +150,6 @@
#define CONFIG_SYS_SERIAL0 V2M_UART0
#define CONFIG_SYS_SERIAL1 V2M_UART1
-#define CONFIG_MMC 1
#define CONFIG_GENERIC_MMC
#define CONFIG_ARM_PL180_MMCI
#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
diff --git a/include/configs/veyron.h b/include/configs/veyron.h
new file mode 100644
index 0000000..b15cc26
--- /dev/null
+++ b/include/configs/veyron.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,cros-ec-keyb\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3288_common.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPI_FLASH_GIGADEVICE
+
+#define CONFIG_CMD_SF_TEST
+
+#define CONFIG_KEYBOARD
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+#endif
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 33f966a..f122c98 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -13,8 +13,6 @@
#define CONFIG_VF610
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_FSL_CLK
#define CONFIG_MACH_TYPE 4146
@@ -44,12 +42,10 @@
#define CONFIG_SYS_NAND_ONFI_DETECTION
#ifdef CONFIG_CMD_NAND
-#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
/* UBI */
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
@@ -68,13 +64,10 @@
"-(rootfs)"
#endif
-#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index 0f3fc8f..07fe616 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -57,7 +57,6 @@
#ifdef CONFIG_CMD_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
new file mode 100644
index 0000000..235574d
--- /dev/null
+++ b/include/configs/vining_2000.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * Configuration settings for the Samtec VIN|ING 2000 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6)
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_PWM_IMX
+#define CONFIG_IMX6_PWM_PER_CLK 66000000
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_OFFSET_REDUND (9 * SZ_64K)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_IS_IN_MMC
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */
+/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */
+#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 60513df..f1bd313 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -18,8 +18,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* Top level Makefile configuration choices
*/
@@ -39,7 +37,6 @@
#define CONFIG_MISC_INIT_R
-#define CONFIG_PCI
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
@@ -269,7 +266,6 @@
#ifndef VME_CADDY2
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index d07b74f..2edc0b0 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -92,10 +92,8 @@
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 295f834..406591c 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -12,8 +12,6 @@
#include <config_distro_defaults.h>
#include "mx6_common.h"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
#define MACH_TYPE_WANDBOARD 4412
@@ -76,12 +74,8 @@
#define CONFIG_PHY_ATHEROS
/* Framebuffer */
-#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
@@ -92,6 +86,7 @@
#define CONFIG_CMD_HDMIDETECT
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
+#endif
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -118,32 +113,6 @@
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
"fi; " \
"fi\0" \
- "videoargs=" \
- "setenv nextcon 0; " \
- "if hdmidet; then " \
- "setenv bootargs ${bootargs} " \
- "video=mxcfb${nextcon}:dev=hdmi,1280x720M@60," \
- "if=RGB24; " \
- "setenv fbmen fbmem=28M; " \
- "setexpr nextcon ${nextcon} + 1; " \
- "else " \
- "echo - no HDMI monitor;" \
- "fi; " \
- "i2c dev 1; " \
- "if i2c probe 0x10; then " \
- "setenv bootargs ${bootargs} " \
- "video=mxcfb${nextcon}:dev=lcd,800x480@60," \
- "if=RGB666,bpp=32; " \
- "if test 0 -eq ${nextcon}; then " \
- "setenv fbmem fbmem=10M; " \
- "else " \
- "setenv fbmem ${fbmem},10M; " \
- "fi; " \
- "setexpr nextcon ${nextcon} + 1; " \
- "else " \
- "echo '- no FWBADAPT-7WVGA-LCD-F07A-0102 display';" \
- "fi; " \
- "setenv bootargs ${bootargs} ${fbmem}\0" \
"findfdt="\
"if test $board_name = C1 && test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-wandboard.dtb; fi; " \
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 6665184..b35b795 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -75,8 +75,6 @@
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 89a6fcc..f4a9231 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -21,8 +21,6 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_DISPLAY_BOARDINFO
-
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_SUPPORT_EMMC_BOOT
@@ -40,6 +38,7 @@
"script=boot.scr\0" \
"image=zImage\0" \
"console=ttymxc0\0" \
+ "ethact=usb_ether\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=imx7s-warp.dtb\0" \
@@ -144,9 +143,13 @@
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* USB Device Firmware Update support */
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
+#define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01"
+
#endif
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 0cd892e..ffd9a2c 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -25,7 +25,6 @@
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index de6b183..4aaeea9 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -20,8 +20,6 @@
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_DISPLAY_CPUINFO
-
/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
#define MACH_TYPE_FLEA3 3668
@@ -62,7 +60,6 @@
#define CONFIG_RTC_MC13XXX
/* mmc driver */
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h
index 25bfeef..eb42d8c 100644
--- a/include/configs/woodburn_sd.h
+++ b/include/configs/woodburn_sd.h
@@ -22,15 +22,7 @@
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x100 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 /* 512 KB */
-#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x10002300
#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index b2103b4..b08641f 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -108,7 +108,6 @@
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
/*
@@ -188,12 +187,8 @@
#define CONFIG_SPL_BOARD_INIT
/* Use the framework and generic lib */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
/* SPL will use serial */
-#define CONFIG_SPL_SERIAL_SUPPORT
/* SPL will load U-Boot from NAND offset 0x40000 */
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_BOOT
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 4af6b67..5e51f65 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -115,7 +115,6 @@
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_LZO
@@ -137,7 +136,6 @@
/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@@ -148,7 +146,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00800000
#define CONFIG_SYS_MEMTEST_END 0x04000000
#define CONFIG_SYS_MALLOC_LEN (8 << 20)
-#define CONFIG_IDENT_STRING "-SPEAr"
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
@@ -158,7 +155,6 @@
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x00800000
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* Use last 2 lwords in internal SRAM for bootcounter */
#define CONFIG_BOOTCOUNT_LIMIT
@@ -267,10 +263,6 @@
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NOR_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
/*
* Please select/define only one of the following
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index 312987e..46a11ef 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -36,8 +36,6 @@
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xefff
-#define CONFIG_PCI_PNP
-
#define CONFIG_BIOSEMU
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
@@ -53,8 +51,8 @@
#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
- "stdout=vga,serial\0" \
- "stderr=vga,serial\0"
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
+ "stdout=vidconsole,serial\0" \
+ "stderr=vidconsole,serial\0"
#endif
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 74b2522..04d151b 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -19,7 +19,6 @@
#define CONFIG_ZBOOT_32
#define CONFIG_PHYSMEM
#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_NR_DRAM_BANKS 8
@@ -62,10 +61,6 @@
9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_PORT_MAPPED
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_STDIO_DEREGISTER
-
#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
#define CONFIG_AUTO_COMPLETE
@@ -86,8 +81,6 @@
#endif
#define CONFIG_PARTITION_UUIDS
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
/* x86 GPIOs are accessed through a PCI device */
#define CONFIG_INTEL_ICH6_GPIO
@@ -129,16 +122,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x20000000
/*-----------------------------------------------------------------------
- * Video Configuration
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SW_CURSOR
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_CONSOLE_SCROLL_LINES 5
-
-/*-----------------------------------------------------------------------
* CPU Features
*/
@@ -165,7 +148,6 @@
/*-----------------------------------------------------------------------
* PCI configuration
*/
-#define CONFIG_PCI
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/*-----------------------------------------------------------------------
@@ -175,7 +157,6 @@
#define CONFIG_USB_EHCI_PCI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_USB_HOST_ETHER
diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
index 69558fd..ae9ab71 100644
--- a/include/configs/xfi3.h
+++ b/include/configs/xfi3.h
@@ -11,11 +11,8 @@
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
-#define CONFIG_VIDEO
-
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index 6c52582..47c1ddf 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -57,7 +57,6 @@
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 02f0e4c..74cbfcf 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -34,10 +34,6 @@
/* Have release address at the end of 256MB for now */
#define CPU_RELEASE_ADDR 0xFFFFFF0
-#if !defined(CONFIG_IDENT_STRING)
-# define CONFIG_IDENT_STRING " Xilinx ZynqMP"
-#endif
-
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
@@ -79,18 +75,14 @@
/* Diff from config_distro_defaults.h */
#define CONFIG_SUPPORT_RAW_INITRD
+#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#endif
#define CONFIG_AUTO_COMPLETE
-/* PXE */
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-
#if defined(CONFIG_ZYNQ_SDHCI)
-# define CONFIG_MMC
# define CONFIG_GENERIC_MMC
# define CONFIG_SUPPORT_EMMC_BOOT
-# define CONFIG_SDHCI
# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
# endif
@@ -112,14 +104,11 @@
#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_XHCI_ZYNQMP
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_DFU_RAM
#define CONFIG_USB_CABLE_CHECK
#define CONFIG_CMD_THOR_DOWNLOAD
#define CONFIG_USB_FUNCTION_THOR
@@ -140,7 +129,6 @@
# define DFU_ALT_INFO
#endif
-
#define CONFIG_BOARD_LATE_INIT
/* Do not preserve environment */
@@ -189,10 +177,8 @@
#endif
#ifdef CONFIG_SATA_CEVA
-#define CONFIG_AHCI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
-#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
@@ -251,42 +237,60 @@
DFU_ALT_INFO
#endif
+/* SPL can't handle all huge variables - define just DFU */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT)
+#undef CONFIG_EXTRA_ENV_SETTINGS
+# define CONFIG_EXTRA_ENV_SETTINGS \
+ "dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \
+ "atf-uboot.ub ram 0x10000000 0x1000000;" \
+ "Image ram 0x80000 0x3f80000;" \
+ "system.dtb ram 0x4000000 0x100000\0" \
+ "dfu_bufsiz=0x1000\0"
+#endif
+
#define CONFIG_SPL_TEXT_BASE 0xfffc0000
#define CONFIG_SPL_STACK 0xfffffffc
-#define CONFIG_SPL_MAX_SIZE 0x20000
+#define CONFIG_SPL_MAX_SIZE 0x40000
/* Just random location in OCM */
-#define CONFIG_SPL_BSS_START_ADDR 0x1000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x2000000
+#define CONFIG_SPL_BSS_START_ADDR 0x0
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_OS_BOOT
/* u-boot is like dtb */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin"
#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000
/* ATF is my kernel image */
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf.ub"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub"
/* FIT load address for RAM boot */
#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000
/* MMC support */
#ifdef CONFIG_ZYNQ_SDHCI
-# define CONFIG_SPL_MMC_SUPPORT
# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */
# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */
# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* unused */
-# define CONFIG_SPL_LIBDISK_SUPPORT
-# define CONFIG_SPL_FAT_SUPPORT
# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU_SUPPORT)
+# undef CONFIG_CMD_BOOTD
+# define CONFIG_SPL_ENV_SUPPORT
+# define CONFIG_SPL_HASH_SUPPORT
+# define CONFIG_ENV_MAX_ENTRIES 10
+
+# define CONFIG_SYS_SPL_MALLOC_START 0x20000000
+# define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000000
+
+#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
+# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
+#endif
+#endif
+
#endif /* __XILINX_ZYNQMP_H */
diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index 44434aa..3a572b7 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -14,10 +14,8 @@
#define __CONFIG_ZYNQMP_EP_H
#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
-#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
+#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
#define CONFIG_ZYNQ_EEPROM
-#define CONFIG_AHCI
-#define CONFIG_SATA_CEVA
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
ZYNQMP_USB1_XHCI_BASEADDR}
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
index c9f4432..b19a552 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -15,8 +15,6 @@
#define CONFIG_AHCI
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1"
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
index 526d0bb..0714d72 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
@@ -12,8 +12,6 @@
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR}
-#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2"
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
deleted file mode 100644
index 65277a6..0000000
--- a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Configuration for Xilinx ZynqMP zc1751 XM018 DC4
- *
- * (C) Copyright 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H
-#define __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H
-
-#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm018 dc4"
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
index 76350d9..6a0e397 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
@@ -13,8 +13,6 @@
#define CONFIG_ZYNQ_SDHCI0
-#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5"
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */
diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index 7ceab32..8d018da 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -41,12 +41,8 @@
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
-#define CONFIG_SATA_CEVA
-
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102"
-
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS 5
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index bc91714..bfe68f0 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -22,7 +22,6 @@
#define CONFIG_440GX 1 /* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
@@ -144,9 +143,7 @@
* PCI
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index eaea33b..0d5b1ff 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -14,7 +14,6 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
#define CONFIG_SYS_FORM_3U_VPX 1
@@ -23,31 +22,25 @@
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_ALTIVEC 1
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xfff00000
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCIE1 1 /* PCIE controller 1 */
#define CONFIG_PCIE2 1 /* PCIE controller 2 */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* DDR config
*/
-#define CONFIG_SYS_FSL_DDR2
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_ECC
@@ -80,7 +73,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index f7cfc9e..b88aeb4 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -14,38 +14,29 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8548 1
#define CONFIG_XPEDITE5200 1
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
-#define CONFIG_DISPLAY_BOARDINFO
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* DDR config
*/
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_DDR_ECC
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 3306e44a..5d78560 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -14,21 +14,14 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8572 1
-#define CONFIG_XPEDITE5370 1
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
-#define CONFIG_DISPLAY_BOARDINFO
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCIE1 1 /* PCIE controller 1 */
#define CONFIG_PCIE2 1 /* PCIE controller 2 */
@@ -36,7 +29,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_ELBC 1
/*
@@ -49,7 +41,6 @@
/*
* DDR config
*/
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
@@ -57,7 +48,6 @@
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_ECC
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index ded6bbf..35e6350 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -14,29 +14,22 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_P2020 1
#define CONFIG_XPEDITE550X 1
#define CONFIG_SYS_BOARD_NAME "XPedite5500"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
-#define CONFIG_DISPLAY_BOARDINFO
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_ELBC 1
/*
@@ -49,13 +42,11 @@
/*
* DDR config
*/
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x54
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_DDR_ECC
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index 26be337..41d4c07 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -12,13 +12,8 @@
#include <asm/imx-common/gpio.h>
/* SPL options */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 << 20)
@@ -47,7 +42,6 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index 3e5d310..c7862be 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h
@@ -112,8 +112,6 @@
#undef CONFIG_USE_IRQ /* Keep it simple, poll only */
#define CONFIG_BOARD_POSTCLK_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTFILE "uImage"
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 0707768..a355112 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -199,9 +199,7 @@
*-----------------------------------------------------------------------
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 76717e4..0a3e4b3 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -181,9 +181,7 @@
*-----------------------------------------------------------------------
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h
index 073a42c..a7988e0 100644
--- a/include/configs/zc5202.h
+++ b/include/configs/zc5202.h
@@ -10,11 +10,9 @@
#define __EL_ZC5202_H
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc1"
+#define CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-zc5202.dtb"
-
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#include "el6x_common.h"
@@ -29,8 +27,6 @@
#define CONFIG_MV88E6352_SWITCH
#define CONFIG_CMD_PCI
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h
index 28b9c6b..61c6a60 100644
--- a/include/configs/zc5601.h
+++ b/include/configs/zc5601.h
@@ -11,11 +11,9 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc1"
+#define CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk0p1"
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-zc5601.dtb"
-
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#include "el6x_common.h"
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 6e83cc9..a30aefb 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -49,7 +49,6 @@
* Serial Console Configuration
* STUART - the lower serial port on Colibri board
*/
-#define CONFIG_PXA_SERIAL
#define CONFIG_STUART 1
#define CONFIG_CONS_INDEX 2
#define CONFIG_BAUDRATE 115200
@@ -63,7 +62,6 @@
* MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_SYS_MMC_BASE 0xF0000000
@@ -75,7 +73,6 @@
*/
#ifdef CONFIG_CMD_SPI
#define CONFIG_SOFT_SPI
-#define CONFIG_LCD
#define CONFIG_LCD_ROTATION
#define CONFIG_PXA_LCD
#define CONFIG_LMS283GF05
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 5f7fefd..2fe6897 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -76,22 +76,24 @@
# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#endif
+#ifdef CONFIG_NAND_ZYNQ
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_MTD_DEVICE
+#endif
+
/* MMC */
#if defined(CONFIG_ZYNQ_SDHCI)
-# define CONFIG_MMC
# define CONFIG_GENERIC_MMC
-# define CONFIG_SDHCI
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#endif
#ifdef CONFIG_USB_EHCI_ZYNQ
# define CONFIG_EHCI_IS_TDI
-# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define DFU_DEFAULT_POLL_TIMEOUT 300
-# define CONFIG_USB_FUNCTION_DFU
-# define CONFIG_DFU_RAM
# define CONFIG_USB_CABLE_CHECK
# define CONFIG_CMD_THOR_DOWNLOAD
# define CONFIG_THOR_RESET_OFF
@@ -106,7 +108,6 @@
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
# if defined(CONFIG_ZYNQ_SDHCI)
-# define CONFIG_DFU_MMC
# define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
"set dfu_alt_info " \
@@ -238,7 +239,6 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_LONGHELP
#define CONFIG_CLOCKS
#define CONFIG_CMD_CLK
@@ -293,9 +293,6 @@
/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_RAM_DEVICE
@@ -303,12 +300,7 @@
/* MMC support */
#ifdef CONFIG_ZYNQ_SDHCI
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
@@ -331,9 +323,7 @@
/* qspi mode is working fine */
#ifdef CONFIG_ZYNQ_QSPI
-#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
@@ -342,7 +332,6 @@
#endif
/* for booting directly linux */
-#define CONFIG_SPL_OS_BOOT
/* SP location before relocation, must use scratch RAM */
#define CONFIG_SPL_TEXT_BASE 0x0
diff --git a/include/cpsw.h b/include/cpsw.h
index 257d12a..f135e7b 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -48,6 +48,7 @@
void (*control)(int enabled);
u32 host_port_num;
u32 active_slave;
+ bool rmii_clock_external;
u8 version;
};
diff --git a/include/cpu.h b/include/cpu.h
index bda5315..9542577 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -21,6 +21,8 @@
int cpu_id;
int ucode_version;
ulong device_id;
+ u16 family; /* DMTF CPU Family */
+ u32 id[2]; /* DMTF CPU Processor IDs */
};
/* CPU features - mostly just a placeholder for now */
@@ -71,6 +73,16 @@
* @return CPU count if OK, -ve on error
*/
int (*get_count)(struct udevice *dev);
+
+ /**
+ * get_vendor() - Get vendor name of a CPU
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @buf: Buffer to place string
+ * @size: Size of string space
+ * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+ int (*get_vendor)(struct udevice *dev, char *buf, int size);
};
#define cpu_get_ops(dev) ((struct cpu_ops *)(dev)->driver->ops)
@@ -102,4 +114,14 @@
*/
int cpu_get_count(struct udevice *dev);
+/**
+ * cpu_get_vendor() - Get vendor name of a CPU
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @buf: Buffer to place string
+ * @size: Size of string space
+ * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int cpu_get_vendor(struct udevice *dev, char *buf, int size);
+
#endif
diff --git a/include/cros_ec.h b/include/cros_ec.h
index 5fa5f6f..0271f2b 100644
--- a/include/cros_ec.h
+++ b/include/cros_ec.h
@@ -250,15 +250,6 @@
*/
int cros_ec_calc_checksum(const uint8_t *data, int size);
-/**
- * Decode a flash region parameter
- *
- * @param argc Number of params remaining
- * @param argv List of remaining parameters
- * @return flash region (EC_FLASH_REGION_...) or -1 on error
- */
-int cros_ec_decode_region(int argc, char * const argv[]);
-
int cros_ec_flash_erase(struct cros_ec_dev *dev, uint32_t offset,
uint32_t size);
@@ -281,6 +272,17 @@
uint32_t size);
/**
+ * Read back flash parameters
+ *
+ * This function reads back parameters of the flash as reported by the EC
+ *
+ * @param dev Pointer to device
+ * @param info Pointer to output flash info struct
+ */
+int cros_ec_read_flashinfo(struct cros_ec_dev *dev,
+ struct ec_response_flash_info *info);
+
+/**
* Write data to the flash
*
* Write an arbitrary amount of data to the EC flash, by repeatedly writing
@@ -395,9 +397,11 @@
* Tunnel an I2C transfer to the EC
*
* @param dev CROS-EC device
+ * @param port The remote port on EC to use
* @param msg List of messages to transfer
* @param nmsgs Number of messages to transfer
*/
-int cros_ec_i2c_tunnel(struct udevice *dev, struct i2c_msg *msg, int nmsgs);
+int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *msg,
+ int nmsgs);
#endif
diff --git a/include/display.h b/include/display.h
index b1c4766..d0a08d4 100644
--- a/include/display.h
+++ b/include/display.h
@@ -16,10 +16,12 @@
* @source_id: ID for the source of the display data, typically a video
* controller
* @src_dev: Source device providing the video
+ * @in_use: Display is being used
*/
struct display_plat {
int source_id;
struct udevice *src_dev;
+ bool in_use;
};
/**
@@ -41,6 +43,14 @@
int display_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *timing);
+/**
+ * display_in_use() - Check if a display is in use by any device
+ *
+ * @return true if the device is in use (display_enable() has been called
+ * successfully), else false
+ */
+bool display_in_use(struct udevice *dev);
+
struct dm_display_ops {
/**
* read_timing() - Read information directly
diff --git a/include/dm/device.h b/include/dm/device.h
index babf8ac..9948bd4 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -497,6 +497,22 @@
fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);
/**
+ * dev_get_addr_size_index() - Get the indexed reg property of a device
+ *
+ * Returns the address and size specified in the 'reg' property of a device.
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ * @size: Pointer to size varible - this function returns the size
+ * specified in the 'reg' property here
+ *
+ * @return addr
+ */
+fdt_addr_t dev_get_addr_size_index(struct udevice *dev, int index,
+ fdt_size_t *size);
+
+/**
* dev_get_addr_name() - Get the reg property of a device, indexed by name
*
* @dev: Pointer to a device
diff --git a/include/dm/platform_data/serial_pxa.h b/include/dm/platform_data/serial_pxa.h
new file mode 100644
index 0000000..b19a4a6
--- /dev/null
+++ b/include/dm/platform_data/serial_pxa.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SERIAL_PXA_H
+#define __SERIAL_PXA_H
+
+/*
+ * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
+ * easily handle enabling of clock.
+ */
+#ifdef CONFIG_CPU_MONAHANS
+#define UART_CLK_BASE CKENA_21_BTUART
+#define UART_CLK_REG CKENA
+#define BTUART_INDEX 0
+#define FFUART_INDEX 1
+#define STUART_INDEX 2
+#elif CONFIG_CPU_PXA25X
+#define UART_CLK_BASE (1 << 4) /* HWUART */
+#define UART_CLK_REG CKEN
+#define HWUART_INDEX 0
+#define STUART_INDEX 1
+#define FFUART_INDEX 2
+#define BTUART_INDEX 3
+#else /* PXA27x */
+#define UART_CLK_BASE CKEN5_STUART
+#define UART_CLK_REG CKEN
+#define STUART_INDEX 0
+#define FFUART_INDEX 1
+#define BTUART_INDEX 2
+#endif
+
+/*
+ * Only PXA250 has HWUART, to avoid poluting the code with more macros,
+ * artificially introduce this.
+ */
+#ifndef CONFIG_CPU_PXA25X
+#define HWUART_INDEX 0xff
+#endif
+
+/*
+ * struct pxa_serial_platdata - information about a PXA port
+ *
+ * @base: Uart port base register address
+ * @port: Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre: Uart port baudrate
+ */
+struct pxa_serial_platdata {
+ struct pxa_uart_regs *base;
+ int port;
+ int baudrate;
+};
+
+#endif /* __SERIAL_PXA_H */
diff --git a/include/dm/root.h b/include/dm/root.h
index c7f0c1d..3cf730d 100644
--- a/include/dm/root.h
+++ b/include/dm/root.h
@@ -21,6 +21,16 @@
*/
struct udevice *dm_root(void);
+struct global_data;
+/**
+ * dm_fixup_for_gd_move() - Handle global_data moving to a new place
+ *
+ * The uclass list is part of global_data. Due to the way lists work, moving
+ * the list will cause it to become invalid. This function fixes that up so
+ * that the uclass list will work correctly.
+ */
+void dm_fixup_for_gd_move(struct global_data *new_gd);
+
/**
* dm_scan_platdata() - Scan all platform data and bind drivers
*
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index eb78c4d..8c92d0b 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -66,6 +66,7 @@
UCLASS_REMOTEPROC, /* Remote Processor device */
UCLASS_RESET, /* Reset controller device */
UCLASS_RTC, /* Real time clock device */
+ UCLASS_SCSI, /* SCSI device */
UCLASS_SERIAL, /* Serial UART */
UCLASS_SPI, /* SPI bus */
UCLASS_SPMI, /* System Power Management Interface bus */
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 84f05bc..b583aa8 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -119,6 +119,14 @@
int uclass_get(enum uclass_id key, struct uclass **ucp);
/**
+ * uclass_get_name() - Get the name of a uclass driver
+ *
+ * @id: ID to look up
+ * @returns the name of the uclass driver for that ID, or NULL if none
+ */
+const char *uclass_get_name(enum uclass_id id);
+
+/**
* uclass_get_device() - Get a uclass device based on an ID and index
*
* The device is probed to activate it ready for use.
diff --git a/include/dt-bindings/clk/ti-dra7-atl.h b/include/dt-bindings/clk/ti-dra7-atl.h
new file mode 100644
index 0000000..42dd416
--- /dev/null
+++ b/include/dt-bindings/clk/ti-dra7-atl.h
@@ -0,0 +1,40 @@
+/*
+ * This header provides constants for DRA7 ATL (Audio Tracking Logic)
+ *
+ * The constants defined in this header are used in dts files
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
+#define _DT_BINDINGS_CLK_DRA7_ATL_H
+
+#define DRA7_ATL_WS_MCASP1_FSR 0
+#define DRA7_ATL_WS_MCASP1_FSX 1
+#define DRA7_ATL_WS_MCASP2_FSR 2
+#define DRA7_ATL_WS_MCASP2_FSX 3
+#define DRA7_ATL_WS_MCASP3_FSX 4
+#define DRA7_ATL_WS_MCASP4_FSX 5
+#define DRA7_ATL_WS_MCASP5_FSX 6
+#define DRA7_ATL_WS_MCASP6_FSX 7
+#define DRA7_ATL_WS_MCASP7_FSX 8
+#define DRA7_ATL_WS_MCASP8_FSX 9
+#define DRA7_ATL_WS_MCASP8_AHCLKX 10
+#define DRA7_ATL_WS_XREF_CLK3 11
+#define DRA7_ATL_WS_XREF_CLK0 12
+#define DRA7_ATL_WS_XREF_CLK1 13
+#define DRA7_ATL_WS_XREF_CLK2 14
+#define DRA7_ATL_WS_OSC1_X1 15
+
+#endif
diff --git a/include/dt-bindings/clock/bcm2835-aux.h b/include/dt-bindings/clock/bcm2835-aux.h
new file mode 100644
index 0000000..d91156e
--- /dev/null
+++ b/include/dt-bindings/clock/bcm2835-aux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BCM2835_AUX_CLOCK_UART 0
+#define BCM2835_AUX_CLOCK_SPI1 1
+#define BCM2835_AUX_CLOCK_SPI2 2
+#define BCM2835_AUX_CLOCK_COUNT 3
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
new file mode 100644
index 0000000..360e00c
--- /dev/null
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BCM2835_PLLA 0
+#define BCM2835_PLLB 1
+#define BCM2835_PLLC 2
+#define BCM2835_PLLD 3
+#define BCM2835_PLLH 4
+
+#define BCM2835_PLLA_CORE 5
+#define BCM2835_PLLA_PER 6
+#define BCM2835_PLLB_ARM 7
+#define BCM2835_PLLC_CORE0 8
+#define BCM2835_PLLC_CORE1 9
+#define BCM2835_PLLC_CORE2 10
+#define BCM2835_PLLC_PER 11
+#define BCM2835_PLLD_CORE 12
+#define BCM2835_PLLD_PER 13
+#define BCM2835_PLLH_RCAL 14
+#define BCM2835_PLLH_AUX 15
+#define BCM2835_PLLH_PIX 16
+
+#define BCM2835_CLOCK_TIMER 17
+#define BCM2835_CLOCK_OTP 18
+#define BCM2835_CLOCK_UART 19
+#define BCM2835_CLOCK_VPU 20
+#define BCM2835_CLOCK_V3D 21
+#define BCM2835_CLOCK_ISP 22
+#define BCM2835_CLOCK_H264 23
+#define BCM2835_CLOCK_VEC 24
+#define BCM2835_CLOCK_HSM 25
+#define BCM2835_CLOCK_SDRAM 26
+#define BCM2835_CLOCK_TSENS 27
+#define BCM2835_CLOCK_EMMC 28
+#define BCM2835_CLOCK_PERI_IMAGE 29
+#define BCM2835_CLOCK_PWM 30
+#define BCM2835_CLOCK_PCM 31
+
+#define BCM2835_PLLA_DSI0 32
+#define BCM2835_PLLA_CCP2 33
+#define BCM2835_PLLD_DSI0 34
+#define BCM2835_PLLD_DSI1 35
+
+#define BCM2835_CLOCK_AVEO 36
+#define BCM2835_CLOCK_DFT 37
+#define BCM2835_CLOCK_GP0 38
+#define BCM2835_CLOCK_GP1 39
+#define BCM2835_CLOCK_GP2 40
+#define BCM2835_CLOCK_SLIM 41
+#define BCM2835_CLOCK_SMI 42
+#define BCM2835_CLOCK_TEC 43
+#define BCM2835_CLOCK_DPI 44
+#define BCM2835_CLOCK_CAM0 45
+#define BCM2835_CLOCK_CAM1 46
+#define BCM2835_CLOCK_DSI0E 47
+#define BCM2835_CLOCK_DSI1E 48
diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h
new file mode 100644
index 0000000..25f9cd2
--- /dev/null
+++ b/include/dt-bindings/clock/boston-clock.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+
+#define BOSTON_CLK_SYS 0
+#define BOSTON_CLK_CPU 1
+
+#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
new file mode 100644
index 0000000..d382fc7
--- /dev/null
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX5_H
+#define __DT_BINDINGS_CLOCK_IMX5_H
+
+#define IMX5_CLK_DUMMY 0
+#define IMX5_CLK_CKIL 1
+#define IMX5_CLK_OSC 2
+#define IMX5_CLK_CKIH1 3
+#define IMX5_CLK_CKIH2 4
+#define IMX5_CLK_AHB 5
+#define IMX5_CLK_IPG 6
+#define IMX5_CLK_AXI_A 7
+#define IMX5_CLK_AXI_B 8
+#define IMX5_CLK_UART_PRED 9
+#define IMX5_CLK_UART_ROOT 10
+#define IMX5_CLK_ESDHC_A_PRED 11
+#define IMX5_CLK_ESDHC_B_PRED 12
+#define IMX5_CLK_ESDHC_C_SEL 13
+#define IMX5_CLK_ESDHC_D_SEL 14
+#define IMX5_CLK_EMI_SEL 15
+#define IMX5_CLK_EMI_SLOW_PODF 16
+#define IMX5_CLK_NFC_PODF 17
+#define IMX5_CLK_ECSPI_PRED 18
+#define IMX5_CLK_ECSPI_PODF 19
+#define IMX5_CLK_USBOH3_PRED 20
+#define IMX5_CLK_USBOH3_PODF 21
+#define IMX5_CLK_USB_PHY_PRED 22
+#define IMX5_CLK_USB_PHY_PODF 23
+#define IMX5_CLK_CPU_PODF 24
+#define IMX5_CLK_DI_PRED 25
+#define IMX5_CLK_TVE_SEL 27
+#define IMX5_CLK_UART1_IPG_GATE 28
+#define IMX5_CLK_UART1_PER_GATE 29
+#define IMX5_CLK_UART2_IPG_GATE 30
+#define IMX5_CLK_UART2_PER_GATE 31
+#define IMX5_CLK_UART3_IPG_GATE 32
+#define IMX5_CLK_UART3_PER_GATE 33
+#define IMX5_CLK_I2C1_GATE 34
+#define IMX5_CLK_I2C2_GATE 35
+#define IMX5_CLK_GPT_IPG_GATE 36
+#define IMX5_CLK_PWM1_IPG_GATE 37
+#define IMX5_CLK_PWM1_HF_GATE 38
+#define IMX5_CLK_PWM2_IPG_GATE 39
+#define IMX5_CLK_PWM2_HF_GATE 40
+#define IMX5_CLK_GPT_HF_GATE 41
+#define IMX5_CLK_FEC_GATE 42
+#define IMX5_CLK_USBOH3_PER_GATE 43
+#define IMX5_CLK_ESDHC1_IPG_GATE 44
+#define IMX5_CLK_ESDHC2_IPG_GATE 45
+#define IMX5_CLK_ESDHC3_IPG_GATE 46
+#define IMX5_CLK_ESDHC4_IPG_GATE 47
+#define IMX5_CLK_SSI1_IPG_GATE 48
+#define IMX5_CLK_SSI2_IPG_GATE 49
+#define IMX5_CLK_SSI3_IPG_GATE 50
+#define IMX5_CLK_ECSPI1_IPG_GATE 51
+#define IMX5_CLK_ECSPI1_PER_GATE 52
+#define IMX5_CLK_ECSPI2_IPG_GATE 53
+#define IMX5_CLK_ECSPI2_PER_GATE 54
+#define IMX5_CLK_CSPI_IPG_GATE 55
+#define IMX5_CLK_SDMA_GATE 56
+#define IMX5_CLK_EMI_SLOW_GATE 57
+#define IMX5_CLK_IPU_SEL 58
+#define IMX5_CLK_IPU_GATE 59
+#define IMX5_CLK_NFC_GATE 60
+#define IMX5_CLK_IPU_DI1_GATE 61
+#define IMX5_CLK_VPU_SEL 62
+#define IMX5_CLK_VPU_GATE 63
+#define IMX5_CLK_VPU_REFERENCE_GATE 64
+#define IMX5_CLK_UART4_IPG_GATE 65
+#define IMX5_CLK_UART4_PER_GATE 66
+#define IMX5_CLK_UART5_IPG_GATE 67
+#define IMX5_CLK_UART5_PER_GATE 68
+#define IMX5_CLK_TVE_GATE 69
+#define IMX5_CLK_TVE_PRED 70
+#define IMX5_CLK_ESDHC1_PER_GATE 71
+#define IMX5_CLK_ESDHC2_PER_GATE 72
+#define IMX5_CLK_ESDHC3_PER_GATE 73
+#define IMX5_CLK_ESDHC4_PER_GATE 74
+#define IMX5_CLK_USB_PHY_GATE 75
+#define IMX5_CLK_HSI2C_GATE 76
+#define IMX5_CLK_MIPI_HSC1_GATE 77
+#define IMX5_CLK_MIPI_HSC2_GATE 78
+#define IMX5_CLK_MIPI_ESC_GATE 79
+#define IMX5_CLK_MIPI_HSP_GATE 80
+#define IMX5_CLK_LDB_DI1_DIV_3_5 81
+#define IMX5_CLK_LDB_DI1_DIV 82
+#define IMX5_CLK_LDB_DI0_DIV_3_5 83
+#define IMX5_CLK_LDB_DI0_DIV 84
+#define IMX5_CLK_LDB_DI1_GATE 85
+#define IMX5_CLK_CAN2_SERIAL_GATE 86
+#define IMX5_CLK_CAN2_IPG_GATE 87
+#define IMX5_CLK_I2C3_GATE 88
+#define IMX5_CLK_LP_APM 89
+#define IMX5_CLK_PERIPH_APM 90
+#define IMX5_CLK_MAIN_BUS 91
+#define IMX5_CLK_AHB_MAX 92
+#define IMX5_CLK_AIPS_TZ1 93
+#define IMX5_CLK_AIPS_TZ2 94
+#define IMX5_CLK_TMAX1 95
+#define IMX5_CLK_TMAX2 96
+#define IMX5_CLK_TMAX3 97
+#define IMX5_CLK_SPBA 98
+#define IMX5_CLK_UART_SEL 99
+#define IMX5_CLK_ESDHC_A_SEL 100
+#define IMX5_CLK_ESDHC_B_SEL 101
+#define IMX5_CLK_ESDHC_A_PODF 102
+#define IMX5_CLK_ESDHC_B_PODF 103
+#define IMX5_CLK_ECSPI_SEL 104
+#define IMX5_CLK_USBOH3_SEL 105
+#define IMX5_CLK_USB_PHY_SEL 106
+#define IMX5_CLK_IIM_GATE 107
+#define IMX5_CLK_USBOH3_GATE 108
+#define IMX5_CLK_EMI_FAST_GATE 109
+#define IMX5_CLK_IPU_DI0_GATE 110
+#define IMX5_CLK_GPC_DVFS 111
+#define IMX5_CLK_PLL1_SW 112
+#define IMX5_CLK_PLL2_SW 113
+#define IMX5_CLK_PLL3_SW 114
+#define IMX5_CLK_IPU_DI0_SEL 115
+#define IMX5_CLK_IPU_DI1_SEL 116
+#define IMX5_CLK_TVE_EXT_SEL 117
+#define IMX5_CLK_MX51_MIPI 118
+#define IMX5_CLK_PLL4_SW 119
+#define IMX5_CLK_LDB_DI1_SEL 120
+#define IMX5_CLK_DI_PLL4_PODF 121
+#define IMX5_CLK_LDB_DI0_SEL 122
+#define IMX5_CLK_LDB_DI0_GATE 123
+#define IMX5_CLK_USB_PHY1_GATE 124
+#define IMX5_CLK_USB_PHY2_GATE 125
+#define IMX5_CLK_PER_LP_APM 126
+#define IMX5_CLK_PER_PRED1 127
+#define IMX5_CLK_PER_PRED2 128
+#define IMX5_CLK_PER_PODF 129
+#define IMX5_CLK_PER_ROOT 130
+#define IMX5_CLK_SSI_APM 131
+#define IMX5_CLK_SSI1_ROOT_SEL 132
+#define IMX5_CLK_SSI2_ROOT_SEL 133
+#define IMX5_CLK_SSI3_ROOT_SEL 134
+#define IMX5_CLK_SSI_EXT1_SEL 135
+#define IMX5_CLK_SSI_EXT2_SEL 136
+#define IMX5_CLK_SSI_EXT1_COM_SEL 137
+#define IMX5_CLK_SSI_EXT2_COM_SEL 138
+#define IMX5_CLK_SSI1_ROOT_PRED 139
+#define IMX5_CLK_SSI1_ROOT_PODF 140
+#define IMX5_CLK_SSI2_ROOT_PRED 141
+#define IMX5_CLK_SSI2_ROOT_PODF 142
+#define IMX5_CLK_SSI_EXT1_PRED 143
+#define IMX5_CLK_SSI_EXT1_PODF 144
+#define IMX5_CLK_SSI_EXT2_PRED 145
+#define IMX5_CLK_SSI_EXT2_PODF 146
+#define IMX5_CLK_SSI1_ROOT_GATE 147
+#define IMX5_CLK_SSI2_ROOT_GATE 148
+#define IMX5_CLK_SSI3_ROOT_GATE 149
+#define IMX5_CLK_SSI_EXT1_GATE 150
+#define IMX5_CLK_SSI_EXT2_GATE 151
+#define IMX5_CLK_EPIT1_IPG_GATE 152
+#define IMX5_CLK_EPIT1_HF_GATE 153
+#define IMX5_CLK_EPIT2_IPG_GATE 154
+#define IMX5_CLK_EPIT2_HF_GATE 155
+#define IMX5_CLK_CAN_SEL 156
+#define IMX5_CLK_CAN1_SERIAL_GATE 157
+#define IMX5_CLK_CAN1_IPG_GATE 158
+#define IMX5_CLK_OWIRE_GATE 159
+#define IMX5_CLK_GPU3D_SEL 160
+#define IMX5_CLK_GPU2D_SEL 161
+#define IMX5_CLK_GPU3D_GATE 162
+#define IMX5_CLK_GPU2D_GATE 163
+#define IMX5_CLK_GARB_GATE 164
+#define IMX5_CLK_CKO1_SEL 165
+#define IMX5_CLK_CKO1_PODF 166
+#define IMX5_CLK_CKO1 167
+#define IMX5_CLK_CKO2_SEL 168
+#define IMX5_CLK_CKO2_PODF 169
+#define IMX5_CLK_CKO2 170
+#define IMX5_CLK_SRTC_GATE 171
+#define IMX5_CLK_PATA_GATE 172
+#define IMX5_CLK_SATA_GATE 173
+#define IMX5_CLK_SPDIF_XTAL_SEL 174
+#define IMX5_CLK_SPDIF0_SEL 175
+#define IMX5_CLK_SPDIF1_SEL 176
+#define IMX5_CLK_SPDIF0_PRED 177
+#define IMX5_CLK_SPDIF0_PODF 178
+#define IMX5_CLK_SPDIF1_PRED 179
+#define IMX5_CLK_SPDIF1_PODF 180
+#define IMX5_CLK_SPDIF0_COM_SEL 181
+#define IMX5_CLK_SPDIF1_COM_SEL 182
+#define IMX5_CLK_SPDIF0_GATE 183
+#define IMX5_CLK_SPDIF1_GATE 184
+#define IMX5_CLK_SPDIF_IPG_GATE 185
+#define IMX5_CLK_OCRAM 186
+#define IMX5_CLK_SAHARA_IPG_GATE 187
+#define IMX5_CLK_SATA_REF 188
+#define IMX5_CLK_STEP_SEL 189
+#define IMX5_CLK_CPU_PODF_SEL 190
+#define IMX5_CLK_ARM 191
+#define IMX5_CLK_FIRI_PRED 192
+#define IMX5_CLK_FIRI_SEL 193
+#define IMX5_CLK_FIRI_PODF 194
+#define IMX5_CLK_FIRI_SERIAL_GATE 195
+#define IMX5_CLK_FIRI_IPG_GATE 196
+#define IMX5_CLK_CSI0_MCLK1_PRED 197
+#define IMX5_CLK_CSI0_MCLK1_SEL 198
+#define IMX5_CLK_CSI0_MCLK1_PODF 199
+#define IMX5_CLK_CSI0_MCLK1_GATE 200
+#define IMX5_CLK_IEEE1588_PRED 201
+#define IMX5_CLK_IEEE1588_SEL 202
+#define IMX5_CLK_IEEE1588_PODF 203
+#define IMX5_CLK_IEEE1588_GATE 204
+#define IMX5_CLK_END 205
+
+#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
new file mode 100644
index 0000000..2905033
--- /dev/null
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define __DT_BINDINGS_CLOCK_IMX6QDL_H
+
+#define IMX6QDL_CLK_DUMMY 0
+#define IMX6QDL_CLK_CKIL 1
+#define IMX6QDL_CLK_CKIH 2
+#define IMX6QDL_CLK_OSC 3
+#define IMX6QDL_CLK_PLL2_PFD0_352M 4
+#define IMX6QDL_CLK_PLL2_PFD1_594M 5
+#define IMX6QDL_CLK_PLL2_PFD2_396M 6
+#define IMX6QDL_CLK_PLL3_PFD0_720M 7
+#define IMX6QDL_CLK_PLL3_PFD1_540M 8
+#define IMX6QDL_CLK_PLL3_PFD2_508M 9
+#define IMX6QDL_CLK_PLL3_PFD3_454M 10
+#define IMX6QDL_CLK_PLL2_198M 11
+#define IMX6QDL_CLK_PLL3_120M 12
+#define IMX6QDL_CLK_PLL3_80M 13
+#define IMX6QDL_CLK_PLL3_60M 14
+#define IMX6QDL_CLK_TWD 15
+#define IMX6QDL_CLK_STEP 16
+#define IMX6QDL_CLK_PLL1_SW 17
+#define IMX6QDL_CLK_PERIPH_PRE 18
+#define IMX6QDL_CLK_PERIPH2_PRE 19
+#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
+#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
+#define IMX6QDL_CLK_AXI_SEL 22
+#define IMX6QDL_CLK_ESAI_SEL 23
+#define IMX6QDL_CLK_ASRC_SEL 24
+#define IMX6QDL_CLK_SPDIF_SEL 25
+#define IMX6QDL_CLK_GPU2D_AXI 26
+#define IMX6QDL_CLK_GPU3D_AXI 27
+#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
+#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
+#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
+#define IMX6QDL_CLK_IPU1_SEL 31
+#define IMX6QDL_CLK_IPU2_SEL 32
+#define IMX6QDL_CLK_LDB_DI0_SEL 33
+#define IMX6QDL_CLK_LDB_DI1_SEL 34
+#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
+#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
+#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
+#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
+#define IMX6QDL_CLK_IPU1_DI0_SEL 39
+#define IMX6QDL_CLK_IPU1_DI1_SEL 40
+#define IMX6QDL_CLK_IPU2_DI0_SEL 41
+#define IMX6QDL_CLK_IPU2_DI1_SEL 42
+#define IMX6QDL_CLK_HSI_TX_SEL 43
+#define IMX6QDL_CLK_PCIE_AXI_SEL 44
+#define IMX6QDL_CLK_SSI1_SEL 45
+#define IMX6QDL_CLK_SSI2_SEL 46
+#define IMX6QDL_CLK_SSI3_SEL 47
+#define IMX6QDL_CLK_USDHC1_SEL 48
+#define IMX6QDL_CLK_USDHC2_SEL 49
+#define IMX6QDL_CLK_USDHC3_SEL 50
+#define IMX6QDL_CLK_USDHC4_SEL 51
+#define IMX6QDL_CLK_ENFC_SEL 52
+#define IMX6QDL_CLK_EIM_SEL 53
+#define IMX6QDL_CLK_EIM_SLOW_SEL 54
+#define IMX6QDL_CLK_VDO_AXI_SEL 55
+#define IMX6QDL_CLK_VPU_AXI_SEL 56
+#define IMX6QDL_CLK_CKO1_SEL 57
+#define IMX6QDL_CLK_PERIPH 58
+#define IMX6QDL_CLK_PERIPH2 59
+#define IMX6QDL_CLK_PERIPH_CLK2 60
+#define IMX6QDL_CLK_PERIPH2_CLK2 61
+#define IMX6QDL_CLK_IPG 62
+#define IMX6QDL_CLK_IPG_PER 63
+#define IMX6QDL_CLK_ESAI_PRED 64
+#define IMX6QDL_CLK_ESAI_PODF 65
+#define IMX6QDL_CLK_ASRC_PRED 66
+#define IMX6QDL_CLK_ASRC_PODF 67
+#define IMX6QDL_CLK_SPDIF_PRED 68
+#define IMX6QDL_CLK_SPDIF_PODF 69
+#define IMX6QDL_CLK_CAN_ROOT 70
+#define IMX6QDL_CLK_ECSPI_ROOT 71
+#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
+#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
+#define IMX6QDL_CLK_GPU3D_SHADER 74
+#define IMX6QDL_CLK_IPU1_PODF 75
+#define IMX6QDL_CLK_IPU2_PODF 76
+#define IMX6QDL_CLK_LDB_DI0_PODF 77
+#define IMX6QDL_CLK_LDB_DI1_PODF 78
+#define IMX6QDL_CLK_IPU1_DI0_PRE 79
+#define IMX6QDL_CLK_IPU1_DI1_PRE 80
+#define IMX6QDL_CLK_IPU2_DI0_PRE 81
+#define IMX6QDL_CLK_IPU2_DI1_PRE 82
+#define IMX6QDL_CLK_HSI_TX_PODF 83
+#define IMX6QDL_CLK_SSI1_PRED 84
+#define IMX6QDL_CLK_SSI1_PODF 85
+#define IMX6QDL_CLK_SSI2_PRED 86
+#define IMX6QDL_CLK_SSI2_PODF 87
+#define IMX6QDL_CLK_SSI3_PRED 88
+#define IMX6QDL_CLK_SSI3_PODF 89
+#define IMX6QDL_CLK_UART_SERIAL_PODF 90
+#define IMX6QDL_CLK_USDHC1_PODF 91
+#define IMX6QDL_CLK_USDHC2_PODF 92
+#define IMX6QDL_CLK_USDHC3_PODF 93
+#define IMX6QDL_CLK_USDHC4_PODF 94
+#define IMX6QDL_CLK_ENFC_PRED 95
+#define IMX6QDL_CLK_ENFC_PODF 96
+#define IMX6QDL_CLK_EIM_PODF 97
+#define IMX6QDL_CLK_EIM_SLOW_PODF 98
+#define IMX6QDL_CLK_VPU_AXI_PODF 99
+#define IMX6QDL_CLK_CKO1_PODF 100
+#define IMX6QDL_CLK_AXI 101
+#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
+#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
+#define IMX6QDL_CLK_ARM 104
+#define IMX6QDL_CLK_AHB 105
+#define IMX6QDL_CLK_APBH_DMA 106
+#define IMX6QDL_CLK_ASRC 107
+#define IMX6QDL_CLK_CAN1_IPG 108
+#define IMX6QDL_CLK_CAN1_SERIAL 109
+#define IMX6QDL_CLK_CAN2_IPG 110
+#define IMX6QDL_CLK_CAN2_SERIAL 111
+#define IMX6QDL_CLK_ECSPI1 112
+#define IMX6QDL_CLK_ECSPI2 113
+#define IMX6QDL_CLK_ECSPI3 114
+#define IMX6QDL_CLK_ECSPI4 115
+#define IMX6Q_CLK_ECSPI5 116
+#define IMX6DL_CLK_I2C4 116
+#define IMX6QDL_CLK_ENET 117
+#define IMX6QDL_CLK_ESAI_EXTAL 118
+#define IMX6QDL_CLK_GPT_IPG 119
+#define IMX6QDL_CLK_GPT_IPG_PER 120
+#define IMX6QDL_CLK_GPU2D_CORE 121
+#define IMX6QDL_CLK_GPU3D_CORE 122
+#define IMX6QDL_CLK_HDMI_IAHB 123
+#define IMX6QDL_CLK_HDMI_ISFR 124
+#define IMX6QDL_CLK_I2C1 125
+#define IMX6QDL_CLK_I2C2 126
+#define IMX6QDL_CLK_I2C3 127
+#define IMX6QDL_CLK_IIM 128
+#define IMX6QDL_CLK_ENFC 129
+#define IMX6QDL_CLK_IPU1 130
+#define IMX6QDL_CLK_IPU1_DI0 131
+#define IMX6QDL_CLK_IPU1_DI1 132
+#define IMX6QDL_CLK_IPU2 133
+#define IMX6QDL_CLK_IPU2_DI0 134
+#define IMX6QDL_CLK_LDB_DI0 135
+#define IMX6QDL_CLK_LDB_DI1 136
+#define IMX6QDL_CLK_IPU2_DI1 137
+#define IMX6QDL_CLK_HSI_TX 138
+#define IMX6QDL_CLK_MLB 139
+#define IMX6QDL_CLK_MMDC_CH0_AXI 140
+#define IMX6QDL_CLK_MMDC_CH1_AXI 141
+#define IMX6QDL_CLK_OCRAM 142
+#define IMX6QDL_CLK_OPENVG_AXI 143
+#define IMX6QDL_CLK_PCIE_AXI 144
+#define IMX6QDL_CLK_PWM1 145
+#define IMX6QDL_CLK_PWM2 146
+#define IMX6QDL_CLK_PWM3 147
+#define IMX6QDL_CLK_PWM4 148
+#define IMX6QDL_CLK_PER1_BCH 149
+#define IMX6QDL_CLK_GPMI_BCH_APB 150
+#define IMX6QDL_CLK_GPMI_BCH 151
+#define IMX6QDL_CLK_GPMI_IO 152
+#define IMX6QDL_CLK_GPMI_APB 153
+#define IMX6QDL_CLK_SATA 154
+#define IMX6QDL_CLK_SDMA 155
+#define IMX6QDL_CLK_SPBA 156
+#define IMX6QDL_CLK_SSI1 157
+#define IMX6QDL_CLK_SSI2 158
+#define IMX6QDL_CLK_SSI3 159
+#define IMX6QDL_CLK_UART_IPG 160
+#define IMX6QDL_CLK_UART_SERIAL 161
+#define IMX6QDL_CLK_USBOH3 162
+#define IMX6QDL_CLK_USDHC1 163
+#define IMX6QDL_CLK_USDHC2 164
+#define IMX6QDL_CLK_USDHC3 165
+#define IMX6QDL_CLK_USDHC4 166
+#define IMX6QDL_CLK_VDO_AXI 167
+#define IMX6QDL_CLK_VPU_AXI 168
+#define IMX6QDL_CLK_CKO1 169
+#define IMX6QDL_CLK_PLL1_SYS 170
+#define IMX6QDL_CLK_PLL2_BUS 171
+#define IMX6QDL_CLK_PLL3_USB_OTG 172
+#define IMX6QDL_CLK_PLL4_AUDIO 173
+#define IMX6QDL_CLK_PLL5_VIDEO 174
+#define IMX6QDL_CLK_PLL8_MLB 175
+#define IMX6QDL_CLK_PLL7_USB_HOST 176
+#define IMX6QDL_CLK_PLL6_ENET 177
+#define IMX6QDL_CLK_SSI1_IPG 178
+#define IMX6QDL_CLK_SSI2_IPG 179
+#define IMX6QDL_CLK_SSI3_IPG 180
+#define IMX6QDL_CLK_ROM 181
+#define IMX6QDL_CLK_USBPHY1 182
+#define IMX6QDL_CLK_USBPHY2 183
+#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
+#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
+#define IMX6QDL_CLK_SATA_REF 186
+#define IMX6QDL_CLK_SATA_REF_100M 187
+#define IMX6QDL_CLK_PCIE_REF 188
+#define IMX6QDL_CLK_PCIE_REF_125M 189
+#define IMX6QDL_CLK_ENET_REF 190
+#define IMX6QDL_CLK_USBPHY1_GATE 191
+#define IMX6QDL_CLK_USBPHY2_GATE 192
+#define IMX6QDL_CLK_PLL4_POST_DIV 193
+#define IMX6QDL_CLK_PLL5_POST_DIV 194
+#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
+#define IMX6QDL_CLK_EIM_SLOW 196
+#define IMX6QDL_CLK_SPDIF 197
+#define IMX6QDL_CLK_CKO2_SEL 198
+#define IMX6QDL_CLK_CKO2_PODF 199
+#define IMX6QDL_CLK_CKO2 200
+#define IMX6QDL_CLK_CKO 201
+#define IMX6QDL_CLK_VDOA 202
+#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
+#define IMX6QDL_CLK_LVDS1_SEL 204
+#define IMX6QDL_CLK_LVDS2_SEL 205
+#define IMX6QDL_CLK_LVDS1_GATE 206
+#define IMX6QDL_CLK_LVDS2_GATE 207
+#define IMX6QDL_CLK_ESAI_IPG 208
+#define IMX6QDL_CLK_ESAI_MEM 209
+#define IMX6QDL_CLK_ASRC_IPG 210
+#define IMX6QDL_CLK_ASRC_MEM 211
+#define IMX6QDL_CLK_LVDS1_IN 212
+#define IMX6QDL_CLK_LVDS2_IN 213
+#define IMX6QDL_CLK_ANACLK1 214
+#define IMX6QDL_CLK_ANACLK2 215
+#define IMX6QDL_PLL1_BYPASS_SRC 216
+#define IMX6QDL_PLL2_BYPASS_SRC 217
+#define IMX6QDL_PLL3_BYPASS_SRC 218
+#define IMX6QDL_PLL4_BYPASS_SRC 219
+#define IMX6QDL_PLL5_BYPASS_SRC 220
+#define IMX6QDL_PLL6_BYPASS_SRC 221
+#define IMX6QDL_PLL7_BYPASS_SRC 222
+#define IMX6QDL_CLK_PLL1 223
+#define IMX6QDL_CLK_PLL2 224
+#define IMX6QDL_CLK_PLL3 225
+#define IMX6QDL_CLK_PLL4 226
+#define IMX6QDL_CLK_PLL5 227
+#define IMX6QDL_CLK_PLL6 228
+#define IMX6QDL_CLK_PLL7 229
+#define IMX6QDL_PLL1_BYPASS 230
+#define IMX6QDL_PLL2_BYPASS 231
+#define IMX6QDL_PLL3_BYPASS 232
+#define IMX6QDL_PLL4_BYPASS 233
+#define IMX6QDL_PLL5_BYPASS 234
+#define IMX6QDL_PLL6_BYPASS 235
+#define IMX6QDL_PLL7_BYPASS 236
+#define IMX6QDL_CLK_GPT_3M 237
+#define IMX6QDL_CLK_VIDEO_27M 238
+#define IMX6QDL_CLK_MIPI_CORE_CFG 239
+#define IMX6QDL_CLK_MIPI_IPG 240
+#define IMX6QDL_CLK_CAAM_MEM 241
+#define IMX6QDL_CLK_CAAM_ACLK 242
+#define IMX6QDL_CLK_CAAM_IPG 243
+#define IMX6QDL_CLK_SPDIF_GCLK 244
+#define IMX6QDL_CLK_UART_SEL 245
+#define IMX6QDL_CLK_IPG_PER_SEL 246
+#define IMX6QDL_CLK_ECSPI_SEL 247
+#define IMX6QDL_CLK_CAN_SEL 248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249
+#define IMX6QDL_CLK_PRE0 250
+#define IMX6QDL_CLK_PRE1 251
+#define IMX6QDL_CLK_PRE2 252
+#define IMX6QDL_CLK_PRE3 253
+#define IMX6QDL_CLK_PRG0_AXI 254
+#define IMX6QDL_CLK_PRG1_AXI 255
+#define IMX6QDL_CLK_PRG0_APB 256
+#define IMX6QDL_CLK_PRG1_APB 257
+#define IMX6QDL_CLK_PRE_AXI 258
+#define IMX6QDL_CLK_END 259
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
new file mode 100644
index 0000000..39c2567
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
+#define __DT_BINDINGS_CLOCK_IMX6SLL_H
+
+#define IMX6SLL_CLK_DUMMY 0
+#define IMX6SLL_CLK_CKIL 1
+#define IMX6SLL_CLK_OSC 2
+#define IMX6SLL_PLL1_BYPASS_SRC 3
+#define IMX6SLL_PLL2_BYPASS_SRC 4
+#define IMX6SLL_PLL3_BYPASS_SRC 5
+#define IMX6SLL_PLL4_BYPASS_SRC 6
+#define IMX6SLL_PLL5_BYPASS_SRC 7
+#define IMX6SLL_PLL6_BYPASS_SRC 8
+#define IMX6SLL_PLL7_BYPASS_SRC 9
+#define IMX6SLL_CLK_PLL1 10
+#define IMX6SLL_CLK_PLL2 11
+#define IMX6SLL_CLK_PLL3 12
+#define IMX6SLL_CLK_PLL4 13
+#define IMX6SLL_CLK_PLL5 14
+#define IMX6SLL_CLK_PLL6 15
+#define IMX6SLL_CLK_PLL7 16
+#define IMX6SLL_PLL1_BYPASS 17
+#define IMX6SLL_PLL2_BYPASS 18
+#define IMX6SLL_PLL3_BYPASS 19
+#define IMX6SLL_PLL4_BYPASS 20
+#define IMX6SLL_PLL5_BYPASS 21
+#define IMX6SLL_PLL6_BYPASS 22
+#define IMX6SLL_PLL7_BYPASS 23
+#define IMX6SLL_CLK_PLL1_SYS 24
+#define IMX6SLL_CLK_PLL2_BUS 25
+#define IMX6SLL_CLK_PLL3_USB_OTG 26
+#define IMX6SLL_CLK_PLL4_AUDIO 27
+#define IMX6SLL_CLK_PLL5_VIDEO 28
+#define IMX6SLL_CLK_PLL6_ENET 29
+#define IMX6SLL_CLK_PLL7_USB_HOST 30
+#define IMX6SLL_CLK_USBPHY1 31
+#define IMX6SLL_CLK_USBPHY2 32
+#define IMX6SLL_CLK_USBPHY1_GATE 33
+#define IMX6SLL_CLK_USBPHY2_GATE 34
+#define IMX6SLL_CLK_PLL2_PFD0 35
+#define IMX6SLL_CLK_PLL2_PFD1 36
+#define IMX6SLL_CLK_PLL2_PFD2 37
+#define IMX6SLL_CLK_PLL2_PFD3 38
+#define IMX6SLL_CLK_PLL3_PFD0 39
+#define IMX6SLL_CLK_PLL3_PFD1 40
+#define IMX6SLL_CLK_PLL3_PFD2 41
+#define IMX6SLL_CLK_PLL3_PFD3 42
+#define IMX6SLL_CLK_PLL4_POST_DIV 43
+#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
+#define IMX6SLL_CLK_PLL5_POST_DIV 45
+#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
+#define IMX6SLL_CLK_PLL2_198M 47
+#define IMX6SLL_CLK_PLL3_120M 48
+#define IMX6SLL_CLK_PLL3_80M 49
+#define IMX6SLL_CLK_PLL3_60M 50
+#define IMX6SLL_CLK_STEP 51
+#define IMX6SLL_CLK_PLL1_SW 52
+#define IMX6SLL_CLK_AXI_ALT_SEL 53
+#define IMX6SLL_CLK_AXI_SEL 54
+#define IMX6SLL_CLK_PERIPH_PRE 55
+#define IMX6SLL_CLK_PERIPH2_PRE 56
+#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
+#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
+#define IMX6SLL_CLK_PERCLK_SEL 59
+#define IMX6SLL_CLK_USDHC1_SEL 60
+#define IMX6SLL_CLK_USDHC2_SEL 61
+#define IMX6SLL_CLK_USDHC3_SEL 62
+#define IMX6SLL_CLK_SSI1_SEL 63
+#define IMX6SLL_CLK_SSI2_SEL 64
+#define IMX6SLL_CLK_SSI3_SEL 65
+#define IMX6SLL_CLK_PXP_SEL 66
+#define IMX6SLL_CLK_LCDIF_PRE_SEL 67
+#define IMX6SLL_CLK_LCDIF_SEL 68
+#define IMX6SLL_CLK_EPDC_PRE_SEL 69
+#define IMX6SLL_CLK_SPDIF_SEL 70
+#define IMX6SLL_CLK_ECSPI_SEL 71
+#define IMX6SLL_CLK_UART_SEL 72
+#define IMX6SLL_CLK_ARM 73
+#define IMX6SLL_CLK_PERIPH 74
+#define IMX6SLL_CLK_PERIPH2 75
+#define IMX6SLL_CLK_PERIPH2_CLK2 76
+#define IMX6SLL_CLK_PERIPH_CLK2 77
+#define IMX6SLL_CLK_MMDC_PODF 78
+#define IMX6SLL_CLK_AXI_PODF 79
+#define IMX6SLL_CLK_AHB 80
+#define IMX6SLL_CLK_IPG 81
+#define IMX6SLL_CLK_PERCLK 82
+#define IMX6SLL_CLK_USDHC1_PODF 83
+#define IMX6SLL_CLK_USDHC2_PODF 84
+#define IMX6SLL_CLK_USDHC3_PODF 85
+#define IMX6SLL_CLK_SSI1_PRED 86
+#define IMX6SLL_CLK_SSI2_PRED 87
+#define IMX6SLL_CLK_SSI3_PRED 88
+#define IMX6SLL_CLK_SSI1_PODF 89
+#define IMX6SLL_CLK_SSI2_PODF 90
+#define IMX6SLL_CLK_SSI3_PODF 91
+#define IMX6SLL_CLK_PXP_PODF 92
+#define IMX6SLL_CLK_LCDIF_PRED 93
+#define IMX6SLL_CLK_LCDIF_PODF 94
+#define IMX6SLL_CLK_EPDC_SEL 95
+#define IMX6SLL_CLK_EPDC_PODF 96
+#define IMX6SLL_CLK_SPDIF_PRED 97
+#define IMX6SLL_CLK_SPDIF_PODF 98
+#define IMX6SLL_CLK_ECSPI_PODF 99
+#define IMX6SLL_CLK_UART_PODF 100
+
+/* CCGR 0 */
+#define IMX6SLL_CLK_AIPSTZ1 101
+#define IMX6SLL_CLK_AIPSTZ2 102
+#define IMX6SLL_CLK_DCP 103
+#define IMX6SLL_CLK_UART2_IPG 104
+#define IMX6SLL_CLK_UART2_SERIAL 105
+
+/* CCGR 1 */
+#define IMX6SLL_CLK_ECSPI1 106
+#define IMX6SLL_CLK_ECSPI2 107
+#define IMX6SLL_CLK_ECSPI3 108
+#define IMX6SLL_CLK_ECSPI4 109
+#define IMX6SLL_CLK_UART3_IPG 110
+#define IMX6SLL_CLK_UART3_SERIAL 111
+#define IMX6SLL_CLK_UART4_IPG 112
+#define IMX6SLL_CLK_UART4_SERIAL 113
+#define IMX6SLL_CLK_EPIT1 114
+#define IMX6SLL_CLK_EPIT2 115
+#define IMX6SLL_CLK_GPT_BUS 116
+#define IMX6SLL_CLK_GPT_SERIAL 117
+
+/* CCGR2 */
+#define IMX6SLL_CLK_CSI 118
+#define IMX6SLL_CLK_I2C1 119
+#define IMX6SLL_CLK_I2C2 120
+#define IMX6SLL_CLK_I2C3 121
+#define IMX6SLL_CLK_OCOTP 122
+#define IMX6SLL_CLK_LCDIF_APB 123
+#define IMX6SLL_CLK_PXP 124
+
+/* CCGR3 */
+#define IMX6SLL_CLK_UART5_IPG 125
+#define IMX6SLL_CLK_UART5_SERIAL 126
+#define IMX6SLL_CLK_EPDC_AXI 127
+#define IMX6SLL_CLK_EPDC_PIX 128
+#define IMX6SLL_CLK_LCDIF_PIX 129
+#define IMX6SLL_CLK_WDOG1 130
+#define IMX6SLL_CLK_MMDC_P0_FAST 131
+#define IMX6SLL_CLK_MMDC_P0_IPG 132
+#define IMX6SLL_CLK_OCRAM 133
+
+/* CCGR4 */
+#define IMX6SLL_CLK_PWM1 134
+#define IMX6SLL_CLK_PWM2 135
+#define IMX6SLL_CLK_PWM3 136
+#define IMX6SLL_CLK_PWM4 137
+
+/* CCGR 5 */
+#define IMX6SLL_CLK_ROM 138
+#define IMX6SLL_CLK_SDMA 139
+#define IMX6SLL_CLK_KPP 140
+#define IMX6SLL_CLK_WDOG2 141
+#define IMX6SLL_CLK_SPBA 142
+#define IMX6SLL_CLK_SPDIF 143
+#define IMX6SLL_CLK_SPDIF_GCLK 144
+#define IMX6SLL_CLK_SSI1 145
+#define IMX6SLL_CLK_SSI1_IPG 146
+#define IMX6SLL_CLK_SSI2 147
+#define IMX6SLL_CLK_SSI2_IPG 148
+#define IMX6SLL_CLK_SSI3 149
+#define IMX6SLL_CLK_SSI3_IPG 150
+#define IMX6SLL_CLK_UART1_IPG 151
+#define IMX6SLL_CLK_UART1_SERIAL 152
+
+/* CCGR 6 */
+#define IMX6SLL_CLK_USBOH3 153
+#define IMX6SLL_CLK_USDHC1 154
+#define IMX6SLL_CLK_USDHC2 155
+#define IMX6SLL_CLK_USDHC3 156
+
+#define IMX6SLL_CLK_IPP_DI0 157
+#define IMX6SLL_CLK_IPP_DI1 158
+#define IMX6SLL_CLK_LDB_DI0_SEL 159
+#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
+#define IMX6SLL_CLK_LDB_DI0_DIV_7 161
+#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
+#define IMX6SLL_CLK_LDB_DI0 163
+#define IMX6SLL_CLK_LDB_DI1_SEL 164
+#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
+#define IMX6SLL_CLK_LDB_DI1_DIV_7 166
+#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
+#define IMX6SLL_CLK_LDB_DI1 168
+#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
+#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
+#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
+#define IMX6SLL_CLK_EXTERN_AUDIO 172
+
+#define IMX6SLL_CLK_END 173
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
new file mode 100644
index 0000000..4623f17
--- /dev/null
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
+#define __DT_BINDINGS_CLOCK_IMX6UL_H
+
+#define IMX6UL_CLK_DUMMY 0
+#define IMX6UL_CLK_CKIL 1
+#define IMX6UL_CLK_CKIH 2
+#define IMX6UL_CLK_OSC 3
+#define IMX6UL_PLL1_BYPASS_SRC 4
+#define IMX6UL_PLL2_BYPASS_SRC 5
+#define IMX6UL_PLL3_BYPASS_SRC 6
+#define IMX6UL_PLL4_BYPASS_SRC 7
+#define IMX6UL_PLL5_BYPASS_SRC 8
+#define IMX6UL_PLL6_BYPASS_SRC 9
+#define IMX6UL_PLL7_BYPASS_SRC 10
+#define IMX6UL_CLK_PLL1 11
+#define IMX6UL_CLK_PLL2 12
+#define IMX6UL_CLK_PLL3 13
+#define IMX6UL_CLK_PLL4 14
+#define IMX6UL_CLK_PLL5 15
+#define IMX6UL_CLK_PLL6 16
+#define IMX6UL_CLK_PLL7 17
+#define IMX6UL_PLL1_BYPASS 18
+#define IMX6UL_PLL2_BYPASS 19
+#define IMX6UL_PLL3_BYPASS 20
+#define IMX6UL_PLL4_BYPASS 21
+#define IMX6UL_PLL5_BYPASS 22
+#define IMX6UL_PLL6_BYPASS 23
+#define IMX6UL_PLL7_BYPASS 24
+#define IMX6UL_CLK_PLL1_SYS 25
+#define IMX6UL_CLK_PLL2_BUS 26
+#define IMX6UL_CLK_PLL3_USB_OTG 27
+#define IMX6UL_CLK_PLL4_AUDIO 28
+#define IMX6UL_CLK_PLL5_VIDEO 29
+#define IMX6UL_CLK_PLL6_ENET 30
+#define IMX6UL_CLK_PLL7_USB_HOST 31
+#define IMX6UL_CLK_USBPHY1 32
+#define IMX6UL_CLK_USBPHY2 33
+#define IMX6UL_CLK_USBPHY1_GATE 34
+#define IMX6UL_CLK_USBPHY2_GATE 35
+#define IMX6UL_CLK_PLL2_PFD0 36
+#define IMX6UL_CLK_PLL2_PFD1 37
+#define IMX6UL_CLK_PLL2_PFD2 38
+#define IMX6UL_CLK_PLL2_PFD3 39
+#define IMX6UL_CLK_PLL3_PFD0 40
+#define IMX6UL_CLK_PLL3_PFD1 41
+#define IMX6UL_CLK_PLL3_PFD2 42
+#define IMX6UL_CLK_PLL3_PFD3 43
+#define IMX6UL_CLK_ENET_REF 44
+#define IMX6UL_CLK_ENET2_REF 45
+#define IMX6UL_CLK_ENET2_REF_125M 46
+#define IMX6UL_CLK_ENET_PTP_REF 47
+#define IMX6UL_CLK_ENET_PTP 48
+#define IMX6UL_CLK_PLL4_POST_DIV 49
+#define IMX6UL_CLK_PLL4_AUDIO_DIV 50
+#define IMX6UL_CLK_PLL5_POST_DIV 51
+#define IMX6UL_CLK_PLL5_VIDEO_DIV 52
+#define IMX6UL_CLK_PLL2_198M 53
+#define IMX6UL_CLK_PLL3_80M 54
+#define IMX6UL_CLK_PLL3_60M 55
+#define IMX6UL_CLK_STEP 56
+#define IMX6UL_CLK_PLL1_SW 57
+#define IMX6UL_CLK_AXI_ALT_SEL 58
+#define IMX6UL_CLK_AXI_SEL 59
+#define IMX6UL_CLK_PERIPH_PRE 60
+#define IMX6UL_CLK_PERIPH2_PRE 61
+#define IMX6UL_CLK_PERIPH_CLK2_SEL 62
+#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63
+#define IMX6UL_CLK_USDHC1_SEL 64
+#define IMX6UL_CLK_USDHC2_SEL 65
+#define IMX6UL_CLK_BCH_SEL 66
+#define IMX6UL_CLK_GPMI_SEL 67
+#define IMX6UL_CLK_EIM_SLOW_SEL 68
+#define IMX6UL_CLK_SPDIF_SEL 69
+#define IMX6UL_CLK_SAI1_SEL 70
+#define IMX6UL_CLK_SAI2_SEL 71
+#define IMX6UL_CLK_SAI3_SEL 72
+#define IMX6UL_CLK_LCDIF_PRE_SEL 73
+#define IMX6UL_CLK_SIM_PRE_SEL 74
+#define IMX6UL_CLK_LDB_DI0_SEL 75
+#define IMX6UL_CLK_LDB_DI1_SEL 76
+#define IMX6UL_CLK_ENFC_SEL 77
+#define IMX6UL_CLK_CAN_SEL 78
+#define IMX6UL_CLK_ECSPI_SEL 79
+#define IMX6UL_CLK_UART_SEL 80
+#define IMX6UL_CLK_QSPI1_SEL 81
+#define IMX6UL_CLK_PERCLK_SEL 82
+#define IMX6UL_CLK_LCDIF_SEL 83
+#define IMX6UL_CLK_SIM_SEL 84
+#define IMX6UL_CLK_PERIPH 85
+#define IMX6UL_CLK_PERIPH2 86
+#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87
+#define IMX6UL_CLK_LDB_DI0_DIV_7 88
+#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89
+#define IMX6UL_CLK_LDB_DI1_DIV_7 90
+#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91
+#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92
+#define IMX6UL_CLK_ARM 93
+#define IMX6UL_CLK_PERIPH_CLK2 94
+#define IMX6UL_CLK_PERIPH2_CLK2 95
+#define IMX6UL_CLK_AHB 96
+#define IMX6UL_CLK_MMDC_PODF 97
+#define IMX6UL_CLK_AXI_PODF 98
+#define IMX6UL_CLK_PERCLK 99
+#define IMX6UL_CLK_IPG 100
+#define IMX6UL_CLK_USDHC1_PODF 101
+#define IMX6UL_CLK_USDHC2_PODF 102
+#define IMX6UL_CLK_BCH_PODF 103
+#define IMX6UL_CLK_GPMI_PODF 104
+#define IMX6UL_CLK_EIM_SLOW_PODF 105
+#define IMX6UL_CLK_SPDIF_PRED 106
+#define IMX6UL_CLK_SPDIF_PODF 107
+#define IMX6UL_CLK_SAI1_PRED 108
+#define IMX6UL_CLK_SAI1_PODF 109
+#define IMX6UL_CLK_SAI2_PRED 110
+#define IMX6UL_CLK_SAI2_PODF 111
+#define IMX6UL_CLK_SAI3_PRED 112
+#define IMX6UL_CLK_SAI3_PODF 113
+#define IMX6UL_CLK_LCDIF_PRED 114
+#define IMX6UL_CLK_LCDIF_PODF 115
+#define IMX6UL_CLK_SIM_PODF 116
+#define IMX6UL_CLK_QSPI1_PDOF 117
+#define IMX6UL_CLK_ENFC_PRED 118
+#define IMX6UL_CLK_ENFC_PODF 119
+#define IMX6UL_CLK_CAN_PODF 120
+#define IMX6UL_CLK_ECSPI_PODF 121
+#define IMX6UL_CLK_UART_PODF 122
+#define IMX6UL_CLK_ADC1 123
+#define IMX6UL_CLK_ADC2 124
+#define IMX6UL_CLK_AIPSTZ1 125
+#define IMX6UL_CLK_AIPSTZ2 126
+#define IMX6UL_CLK_AIPSTZ3 127
+#define IMX6UL_CLK_APBHDMA 128
+#define IMX6UL_CLK_ASRC_IPG 129
+#define IMX6UL_CLK_ASRC_MEM 130
+#define IMX6UL_CLK_GPMI_BCH_APB 131
+#define IMX6UL_CLK_GPMI_BCH 132
+#define IMX6UL_CLK_GPMI_IO 133
+#define IMX6UL_CLK_GPMI_APB 134
+#define IMX6UL_CLK_CAAM_MEM 135
+#define IMX6UL_CLK_CAAM_ACLK 136
+#define IMX6UL_CLK_CAAM_IPG 137
+#define IMX6UL_CLK_CSI 138
+#define IMX6UL_CLK_ECSPI1 139
+#define IMX6UL_CLK_ECSPI2 140
+#define IMX6UL_CLK_ECSPI3 141
+#define IMX6UL_CLK_ECSPI4 142
+#define IMX6UL_CLK_EIM 143
+#define IMX6UL_CLK_ENET 144
+#define IMX6UL_CLK_ENET_AHB 145
+#define IMX6UL_CLK_EPIT1 146
+#define IMX6UL_CLK_EPIT2 147
+#define IMX6UL_CLK_CAN1_IPG 148
+#define IMX6UL_CLK_CAN1_SERIAL 149
+#define IMX6UL_CLK_CAN2_IPG 150
+#define IMX6UL_CLK_CAN2_SERIAL 151
+#define IMX6UL_CLK_GPT1_BUS 152
+#define IMX6UL_CLK_GPT1_SERIAL 153
+#define IMX6UL_CLK_GPT2_BUS 154
+#define IMX6UL_CLK_GPT2_SERIAL 155
+#define IMX6UL_CLK_I2C1 156
+#define IMX6UL_CLK_I2C2 157
+#define IMX6UL_CLK_I2C3 158
+#define IMX6UL_CLK_I2C4 159
+#define IMX6UL_CLK_IOMUXC 160
+#define IMX6UL_CLK_LCDIF_APB 161
+#define IMX6UL_CLK_LCDIF_PIX 162
+#define IMX6UL_CLK_MMDC_P0_FAST 163
+#define IMX6UL_CLK_MMDC_P0_IPG 164
+#define IMX6UL_CLK_OCOTP 165
+#define IMX6UL_CLK_OCRAM 166
+#define IMX6UL_CLK_PWM1 167
+#define IMX6UL_CLK_PWM2 168
+#define IMX6UL_CLK_PWM3 169
+#define IMX6UL_CLK_PWM4 170
+#define IMX6UL_CLK_PWM5 171
+#define IMX6UL_CLK_PWM6 172
+#define IMX6UL_CLK_PWM7 173
+#define IMX6UL_CLK_PWM8 174
+#define IMX6UL_CLK_PXP 175
+#define IMX6UL_CLK_QSPI 176
+#define IMX6UL_CLK_ROM 177
+#define IMX6UL_CLK_SAI1 178
+#define IMX6UL_CLK_SAI1_IPG 179
+#define IMX6UL_CLK_SAI2 180
+#define IMX6UL_CLK_SAI2_IPG 181
+#define IMX6UL_CLK_SAI3 182
+#define IMX6UL_CLK_SAI3_IPG 183
+#define IMX6UL_CLK_SDMA 184
+#define IMX6UL_CLK_SIM 185
+#define IMX6UL_CLK_SIM_S 186
+#define IMX6UL_CLK_SPBA 187
+#define IMX6UL_CLK_SPDIF 188
+#define IMX6UL_CLK_UART1_IPG 189
+#define IMX6UL_CLK_UART1_SERIAL 190
+#define IMX6UL_CLK_UART2_IPG 191
+#define IMX6UL_CLK_UART2_SERIAL 192
+#define IMX6UL_CLK_UART3_IPG 193
+#define IMX6UL_CLK_UART3_SERIAL 194
+#define IMX6UL_CLK_UART4_IPG 195
+#define IMX6UL_CLK_UART4_SERIAL 196
+#define IMX6UL_CLK_UART5_IPG 197
+#define IMX6UL_CLK_UART5_SERIAL 198
+#define IMX6UL_CLK_UART6_IPG 199
+#define IMX6UL_CLK_UART6_SERIAL 200
+#define IMX6UL_CLK_UART7_IPG 201
+#define IMX6UL_CLK_UART7_SERIAL 202
+#define IMX6UL_CLK_UART8_IPG 203
+#define IMX6UL_CLK_UART8_SERIAL 204
+#define IMX6UL_CLK_USBOH3 205
+#define IMX6UL_CLK_USDHC1 206
+#define IMX6UL_CLK_USDHC2 207
+#define IMX6UL_CLK_WDOG1 208
+#define IMX6UL_CLK_WDOG2 209
+#define IMX6UL_CLK_WDOG3 210
+#define IMX6UL_CLK_LDB_DI0 211
+#define IMX6UL_CLK_AXI 212
+#define IMX6UL_CLK_SPDIF_GCLK 213
+#define IMX6UL_CLK_GPT_3M 214
+#define IMX6UL_CLK_SIM2 215
+#define IMX6UL_CLK_SIM1 216
+#define IMX6UL_CLK_IPP_DI0 217
+#define IMX6UL_CLK_IPP_DI1 218
+#define IMX6UL_CA7_SECONDARY_SEL 219
+#define IMX6UL_CLK_PER_BCH 220
+#define IMX6UL_CLK_CSI_SEL 221
+#define IMX6UL_CLK_CSI_PODF 222
+#define IMX6UL_CLK_PLL3_120M 223
+#define IMX6UL_CLK_KPP 224
+/* For i.MX6ULL */
+#define IMX6UL_CLK_ESAI_SEL 224
+#define IMX6UL_CLK_ESAI_PRED 225
+#define IMX6UL_CLK_ESAI_PODF 226
+#define IMX6UL_CLK_ESAI_EXTAL 227
+#define IMX6UL_CLK_ESAI_MEM 228
+#define IMX6UL_CLK_ESAI_IPG 229
+#define IMX6UL_CLK_DCP_CLK 230
+#define IMX6UL_CLK_EPDC_PRE_SEL 231
+#define IMX6UL_CLK_EPDC_SEL 232
+#define IMX6UL_CLK_EPDC_PODF 233
+#define IMX6UL_CLK_EPDC_ACLK 234
+#define IMX6UL_CLK_EPDC_PIX 235
+
+#define IMX6UL_CLK_END 236
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index 6d0d8d8..534c03f 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -49,7 +49,7 @@
#define TEGRA114_CLK_I2S0 30
/* 31 */
-/* 32 */
+#define TEGRA114_CLK_MC 32
/* 33 */
#define TEGRA114_CLK_APBDMA 34
/* 35 */
@@ -337,6 +337,7 @@
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
-#define TEGRA114_CLK_CLK_MAX 311
+#define TEGRA114_CLK_XUSB_SS_DIV2 311
+#define TEGRA114_CLK_CLK_MAX 312
#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index a1ae9a8..04500b2 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -49,7 +49,7 @@
/* 30 */
#define TEGRA20_CLK_CACHE2 31
-#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_MC 32
#define TEGRA20_CLK_AHBDMA 33
#define TEGRA20_CLK_APBDMA 34
/* 35 */
@@ -92,7 +92,7 @@
#define TEGRA20_CLK_OWR 71
#define TEGRA20_CLK_AFI 72
#define TEGRA20_CLK_CSITE 73
-#define TEGRA20_CLK_PCIE_XCLK 74
+/* 74 */
#define TEGRA20_CLK_AVPUCQ 75
#define TEGRA20_CLK_LA 76
/* 77 */
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index d134741..bd3530e 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -1,6 +1,16 @@
/*
- * This header provides Tegra210-specific constants for binding
- * nvidia,tegra210-car.
+ * This header provides constants for binding nvidia,tegra210-car.
+ *
+ * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 224 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
+ * above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
@@ -14,7 +24,7 @@
#define TEGRA210_CLK_TIMER 5
#define TEGRA210_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
-/* 8 */
+#define TEGRA210_CLK_GPIO 8
#define TEGRA210_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA210_CLK_I2S1 11
@@ -25,30 +35,31 @@
/* 16 */
#define TEGRA210_CLK_PWM 17
#define TEGRA210_CLK_I2S2 18
+/* 19 */
/* 20 (register bit affects vi and vi_sensor) */
/* 21 */
#define TEGRA210_CLK_USBD 22
#define TEGRA210_CLK_ISP 23
-/* 26 */
+/* 24 */
/* 25 */
#define TEGRA210_CLK_DISP2 26
#define TEGRA210_CLK_DISP1 27
#define TEGRA210_CLK_HOST1X 28
-#define TEGRA210_CLK_VCP 29
+/* 29 */
#define TEGRA210_CLK_I2S0 30
/* 31 */
#define TEGRA210_CLK_MC 32
-/* 33 */
+#define TEGRA210_CLK_AHBDMA 33
#define TEGRA210_CLK_APBDMA 34
/* 35 */
-#define TEGRA210_CLK_KBC 36
+/* 36 */
/* 37 */
-/* 38 */
+#define TEGRA210_CLK_PMC 38
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA210_CLK_KFUSE 40
#define TEGRA210_CLK_SBC1 41
-#define TEGRA210_CLK_NOR 42
+/* 42 */
/* 43 */
#define TEGRA210_CLK_SBC2 44
/* 45 */
@@ -56,8 +67,8 @@
#define TEGRA210_CLK_I2C5 47
#define TEGRA210_CLK_DSIA 48
/* 49 */
-#define TEGRA210_CLK_MIPI 50
-#define TEGRA210_CLK_HDMI 51
+/* 50 */
+/* 51 */
#define TEGRA210_CLK_CSI 52
/* 53 */
#define TEGRA210_CLK_I2C2 54
@@ -65,10 +76,10 @@
#define TEGRA210_CLK_MIPI_CAL 56
#define TEGRA210_CLK_EMC 57
#define TEGRA210_CLK_USB2 58
-#define TEGRA210_CLK_USB3 59
+/* 59 */
/* 60 */
-#define TEGRA210_CLK_VDE 61
-#define TEGRA210_CLK_BSEA 62
+/* 61 */
+/* 62 */
#define TEGRA210_CLK_BSEV 63
/* 64 */
@@ -83,8 +94,8 @@
#define TEGRA210_CLK_CSITE 73
/* 74 */
/* 75 */
-#define TEGRA210_CLK_LA 76
-#define TEGRA210_CLK_TRACE 77
+/* 76 */
+/* 77 */
#define TEGRA210_CLK_SOC_THERM 78
#define TEGRA210_CLK_DTV 79
/* 80 */
@@ -98,7 +109,7 @@
/* 88 */
#define TEGRA210_CLK_XUSB_HOST 89
/* 90 */
-#define TEGRA210_CLK_MSENC 91
+/* 91 */
#define TEGRA210_CLK_CSUS 92
/* 93 */
/* 94 */
@@ -112,20 +123,20 @@
#define TEGRA210_CLK_I2S3 101
#define TEGRA210_CLK_I2S4 102
#define TEGRA210_CLK_I2C4 103
-#define TEGRA210_CLK_SBC5 104
-#define TEGRA210_CLK_SBC6 105
+/* 104 */
+/* 105 */
#define TEGRA210_CLK_D_AUDIO 106
-#define TEGRA210_CLK_APBIF 107
-#define TEGRA210_CLK_DAM0 108
-#define TEGRA210_CLK_DAM1 109
-#define TEGRA210_CLK_DAM2 110
+#define TEGRA210_CLK_APB2APE 107
+/* 108 */
+/* 109 */
+/* 110 */
#define TEGRA210_CLK_HDA2CODEC_2X 111
/* 112 */
-#define TEGRA210_CLK_AUDIO0_2X 113
-#define TEGRA210_CLK_AUDIO1_2X 114
-#define TEGRA210_CLK_AUDIO2_2X 115
-#define TEGRA210_CLK_AUDIO3_2X 116
-#define TEGRA210_CLK_AUDIO4_2X 117
+/* 113 */
+/* 114 */
+/* 115 */
+/* 116 */
+/* 117 */
#define TEGRA210_CLK_SPDIF_2X 118
#define TEGRA210_CLK_ACTMON 119
#define TEGRA210_CLK_EXTERN1 120
@@ -135,10 +146,10 @@
#define TEGRA210_CLK_SATA 124
#define TEGRA210_CLK_HDA 125
/* 126 */
-#define TEGRA210_CLK_SE 127
+/* 127 */
#define TEGRA210_CLK_HDA2HDMI 128
-#define TEGRA210_CLK_SATA_COLD 129
+/* 129 */
/* 130 */
/* 131 */
/* 132 */
@@ -152,19 +163,19 @@
/* 140 */
/* 141 */
/* 142 */
-/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
-/* xusb_host_src and xusb_ss_src) */
+/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
+#define TEGRA210_CLK_XUSB_GATE 143
#define TEGRA210_CLK_CILAB 144
#define TEGRA210_CLK_CILCD 145
#define TEGRA210_CLK_CILE 146
#define TEGRA210_CLK_DSIALP 147
#define TEGRA210_CLK_DSIBLP 148
#define TEGRA210_CLK_ENTROPY 149
-#define TEGRA210_CLK_DDS 150
+/* 150 */
/* 151 */
-#define TEGRA210_CLK_DP2 152
-#define TEGRA210_CLK_AMX 153
-#define TEGRA210_CLK_ADX 154
+/* 152 */
+/* 153 */
+/* 154 */
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA210_CLK_XUSB_SS 156
/* 157 */
@@ -172,8 +183,8 @@
/* 159 */
/* 160 */
-/* 161 */
-/* 162 */
+#define TEGRA210_CLK_DMIC1 161
+#define TEGRA210_CLK_DMIC2 162
/* 163 */
/* 164 */
/* 165 */
@@ -184,159 +195,207 @@
/* 170 */
#define TEGRA210_CLK_VIM2_CLK 171
/* 172 */
-/* 173 */
+#define TEGRA210_CLK_MIPIBIF 173
/* 174 */
/* 175 */
-#define TEGRA210_CLK_HDMI_AUDIO 176
+/* 176 */
#define TEGRA210_CLK_CLK72MHZ 177
#define TEGRA210_CLK_VIC03 178
/* 179 */
-#define TEGRA210_CLK_ADX1 180
+/* 180 */
#define TEGRA210_CLK_DPAUX 181
#define TEGRA210_CLK_SOR0 182
-/* 183 */
+#define TEGRA210_CLK_SOR1 183
#define TEGRA210_CLK_GPU 184
-#define TEGRA210_CLK_AMX1 185
+#define TEGRA210_CLK_DBGAPB 185
/* 186 */
-/* 187 */
+#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
/* 188 */
-/* 189 */
+#define TEGRA210_CLK_PLL_G_REF 189
/* 190 */
/* 191 */
-#define TEGRA210_CLK_UARTB 192
-#define TEGRA210_CLK_VFIR 193
-#define TEGRA210_CLK_SPDIF_IN 194
-#define TEGRA210_CLK_SPDIF_OUT 195
-#define TEGRA210_CLK_VI 196
-#define TEGRA210_CLK_VI_SENSOR 197
-#define TEGRA210_CLK_FUSE 198
-#define TEGRA210_CLK_FUSE_BURN 199
-#define TEGRA210_CLK_CLK_32K 200
-#define TEGRA210_CLK_CLK_M 201
-#define TEGRA210_CLK_CLK_M_DIV2 202
-#define TEGRA210_CLK_CLK_M_DIV4 203
-#define TEGRA210_CLK_PLL_REF 204
-#define TEGRA210_CLK_PLL_C 205
-#define TEGRA210_CLK_PLL_C_OUT1 206
-#define TEGRA210_CLK_PLL_C2 207
-#define TEGRA210_CLK_PLL_C3 208
-#define TEGRA210_CLK_PLL_M 209
-#define TEGRA210_CLK_PLL_M_OUT1 210
-#define TEGRA210_CLK_PLL_P 211
-#define TEGRA210_CLK_PLL_P_OUT1 212
-#define TEGRA210_CLK_PLL_P_OUT2 213
-#define TEGRA210_CLK_PLL_P_OUT3 214
-#define TEGRA210_CLK_PLL_P_OUT4 215
-#define TEGRA210_CLK_PLL_A 216
-#define TEGRA210_CLK_PLL_A_OUT0 217
-#define TEGRA210_CLK_PLL_D 218
-#define TEGRA210_CLK_PLL_D_OUT0 219
-#define TEGRA210_CLK_PLL_D2 220
-#define TEGRA210_CLK_PLL_D2_OUT0 221
-#define TEGRA210_CLK_PLL_U 222
-#define TEGRA210_CLK_PLL_U_480M 223
-#define TEGRA210_CLK_PLL_U_60M 224
-#define TEGRA210_CLK_PLL_U_48M 225
-#define TEGRA210_CLK_PLL_U_12M 226
-/* 227 */
-/* 228 */
-#define TEGRA210_CLK_PLL_RE_VCO 229
-#define TEGRA210_CLK_PLL_RE_OUT 230
-#define TEGRA210_CLK_PLL_E 231
-#define TEGRA210_CLK_SPDIF_IN_SYNC 232
-#define TEGRA210_CLK_I2S0_SYNC 233
-#define TEGRA210_CLK_I2S1_SYNC 234
-#define TEGRA210_CLK_I2S2_SYNC 235
-#define TEGRA210_CLK_I2S3_SYNC 236
-#define TEGRA210_CLK_I2S4_SYNC 237
-#define TEGRA210_CLK_VIMCLK_SYNC 238
-#define TEGRA210_CLK_AUDIO0 239
-#define TEGRA210_CLK_AUDIO1 240
-#define TEGRA210_CLK_AUDIO2 241
-#define TEGRA210_CLK_AUDIO3 242
-#define TEGRA210_CLK_AUDIO4 243
-#define TEGRA210_CLK_SPDIF 244
-#define TEGRA210_CLK_CLK_OUT_1 245
-#define TEGRA210_CLK_CLK_OUT_2 246
-#define TEGRA210_CLK_CLK_OUT_3 247
-#define TEGRA210_CLK_BLINK 248
-/* 249 */
-/* 250 */
-/* 251 */
-#define TEGRA210_CLK_XUSB_HOST_SRC 252
-#define TEGRA210_CLK_XUSB_FALCON_SRC 253
-#define TEGRA210_CLK_XUSB_FS_SRC 254
-#define TEGRA210_CLK_XUSB_SS_SRC 255
+/* 192 */
+#define TEGRA210_CLK_SDMMC_LEGACY 193
+#define TEGRA210_CLK_NVDEC 194
+#define TEGRA210_CLK_NVJPG 195
+/* 196 */
+#define TEGRA210_CLK_DMIC3 197
+#define TEGRA210_CLK_APE 198
+/* 199 */
+/* 200 */
+/* 201 */
+#define TEGRA210_CLK_MAUD 202
+/* 203 */
+/* 204 */
+/* 205 */
+#define TEGRA210_CLK_TSECB 206
+#define TEGRA210_CLK_DPAUX1 207
+#define TEGRA210_CLK_VI_I2C 208
+#define TEGRA210_CLK_HSIC_TRK 209
+#define TEGRA210_CLK_USB2_TRK 210
+#define TEGRA210_CLK_QSPI 211
+#define TEGRA210_CLK_UARTAPE 212
+/* 213 */
+/* 214 */
+/* 215 */
+/* 216 */
+/* 217 */
+/* 218 */
+#define TEGRA210_CLK_NVENC 219
+/* 220 */
+/* 221 */
+#define TEGRA210_CLK_SOR_SAFE 222
+#define TEGRA210_CLK_PLL_P_OUT_CPU 223
-#define TEGRA210_CLK_XUSB_DEV_SRC 256
-#define TEGRA210_CLK_XUSB_DEV 257
-#define TEGRA210_CLK_XUSB_HS_SRC 258
-#define TEGRA210_CLK_SCLK 259
-#define TEGRA210_CLK_HCLK 260
-#define TEGRA210_CLK_PCLK 261
-/* 262 */
-/* 263 */
-#define TEGRA210_CLK_DFLL_REF 264
-#define TEGRA210_CLK_DFLL_SOC 265
-#define TEGRA210_CLK_VI_SENSOR2 266
-#define TEGRA210_CLK_PLL_P_OUT5 267
-#define TEGRA210_CLK_CML0 268
-#define TEGRA210_CLK_CML1 269
-#define TEGRA210_CLK_PLL_C4 270
-#define TEGRA210_CLK_PLL_DP 271
-#define TEGRA210_CLK_PLL_E_MUX 272
-#define TEGRA210_CLK_PLLD_DSI 273
-/* 274 */
-/* 275 */
-/* 276 */
-/* 277 */
-/* 278 */
-/* 279 */
-/* 280 */
+
+#define TEGRA210_CLK_UARTB 224
+#define TEGRA210_CLK_VFIR 225
+#define TEGRA210_CLK_SPDIF_IN 226
+#define TEGRA210_CLK_SPDIF_OUT 227
+#define TEGRA210_CLK_VI 228
+#define TEGRA210_CLK_VI_SENSOR 229
+#define TEGRA210_CLK_FUSE 230
+#define TEGRA210_CLK_FUSE_BURN 231
+#define TEGRA210_CLK_CLK_32K 232
+#define TEGRA210_CLK_CLK_M 233
+#define TEGRA210_CLK_CLK_M_DIV2 234
+#define TEGRA210_CLK_CLK_M_DIV4 235
+#define TEGRA210_CLK_PLL_REF 236
+#define TEGRA210_CLK_PLL_C 237
+#define TEGRA210_CLK_PLL_C_OUT1 238
+#define TEGRA210_CLK_PLL_C2 239
+#define TEGRA210_CLK_PLL_C3 240
+#define TEGRA210_CLK_PLL_M 241
+#define TEGRA210_CLK_PLL_M_OUT1 242
+#define TEGRA210_CLK_PLL_P 243
+#define TEGRA210_CLK_PLL_P_OUT1 244
+#define TEGRA210_CLK_PLL_P_OUT2 245
+#define TEGRA210_CLK_PLL_P_OUT3 246
+#define TEGRA210_CLK_PLL_P_OUT4 247
+#define TEGRA210_CLK_PLL_A 248
+#define TEGRA210_CLK_PLL_A_OUT0 249
+#define TEGRA210_CLK_PLL_D 250
+#define TEGRA210_CLK_PLL_D_OUT0 251
+#define TEGRA210_CLK_PLL_D2 252
+#define TEGRA210_CLK_PLL_D2_OUT0 253
+#define TEGRA210_CLK_PLL_U 254
+#define TEGRA210_CLK_PLL_U_480M 255
+
+#define TEGRA210_CLK_PLL_U_60M 256
+#define TEGRA210_CLK_PLL_U_48M 257
+/* 258 */
+#define TEGRA210_CLK_PLL_X 259
+#define TEGRA210_CLK_PLL_X_OUT0 260
+#define TEGRA210_CLK_PLL_RE_VCO 261
+#define TEGRA210_CLK_PLL_RE_OUT 262
+#define TEGRA210_CLK_PLL_E 263
+#define TEGRA210_CLK_SPDIF_IN_SYNC 264
+#define TEGRA210_CLK_I2S0_SYNC 265
+#define TEGRA210_CLK_I2S1_SYNC 266
+#define TEGRA210_CLK_I2S2_SYNC 267
+#define TEGRA210_CLK_I2S3_SYNC 268
+#define TEGRA210_CLK_I2S4_SYNC 269
+#define TEGRA210_CLK_VIMCLK_SYNC 270
+#define TEGRA210_CLK_AUDIO0 271
+#define TEGRA210_CLK_AUDIO1 272
+#define TEGRA210_CLK_AUDIO2 273
+#define TEGRA210_CLK_AUDIO3 274
+#define TEGRA210_CLK_AUDIO4 275
+#define TEGRA210_CLK_SPDIF 276
+#define TEGRA210_CLK_CLK_OUT_1 277
+#define TEGRA210_CLK_CLK_OUT_2 278
+#define TEGRA210_CLK_CLK_OUT_3 279
+#define TEGRA210_CLK_BLINK 280
/* 281 */
/* 282 */
/* 283 */
-/* 284 */
-/* 285 */
-/* 286 */
-/* 287 */
+#define TEGRA210_CLK_XUSB_HOST_SRC 284
+#define TEGRA210_CLK_XUSB_FALCON_SRC 285
+#define TEGRA210_CLK_XUSB_FS_SRC 286
+#define TEGRA210_CLK_XUSB_SS_SRC 287
-/* 288 */
-/* 289 */
-/* 290 */
-/* 291 */
-/* 292 */
-/* 293 */
-/* 294 */
-/* 295 */
-/* 296 */
-/* 297 */
-/* 298 */
-/* 299 */
-#define TEGRA210_CLK_AUDIO0_MUX 300
-#define TEGRA210_CLK_AUDIO1_MUX 301
-#define TEGRA210_CLK_AUDIO2_MUX 302
-#define TEGRA210_CLK_AUDIO3_MUX 303
-#define TEGRA210_CLK_AUDIO4_MUX 304
-#define TEGRA210_CLK_SPDIF_MUX 305
-#define TEGRA210_CLK_CLK_OUT_1_MUX 306
-#define TEGRA210_CLK_CLK_OUT_2_MUX 307
-#define TEGRA210_CLK_CLK_OUT_3_MUX 308
-/* 309 */
-/* 310 */
-#define TEGRA210_CLK_SOR0_LVDS 311
-#define TEGRA210_CLK_XUSB_SS_DIV2 312
+#define TEGRA210_CLK_XUSB_DEV_SRC 288
+#define TEGRA210_CLK_XUSB_DEV 289
+#define TEGRA210_CLK_XUSB_HS_SRC 290
+#define TEGRA210_CLK_SCLK 291
+#define TEGRA210_CLK_HCLK 292
+#define TEGRA210_CLK_PCLK 293
+#define TEGRA210_CLK_CCLK_G 294
+#define TEGRA210_CLK_CCLK_LP 295
+#define TEGRA210_CLK_DFLL_REF 296
+#define TEGRA210_CLK_DFLL_SOC 297
+#define TEGRA210_CLK_VI_SENSOR2 298
+#define TEGRA210_CLK_PLL_P_OUT5 299
+#define TEGRA210_CLK_CML0 300
+#define TEGRA210_CLK_CML1 301
+#define TEGRA210_CLK_PLL_C4 302
+#define TEGRA210_CLK_PLL_DP 303
+#define TEGRA210_CLK_PLL_E_MUX 304
+#define TEGRA210_CLK_PLL_MB 305
+#define TEGRA210_CLK_PLL_A1 306
+#define TEGRA210_CLK_PLL_D_DSI_OUT 307
+#define TEGRA210_CLK_PLL_C4_OUT0 308
+#define TEGRA210_CLK_PLL_C4_OUT1 309
+#define TEGRA210_CLK_PLL_C4_OUT2 310
+#define TEGRA210_CLK_PLL_C4_OUT3 311
+#define TEGRA210_CLK_PLL_U_OUT 312
+#define TEGRA210_CLK_PLL_U_OUT1 313
+#define TEGRA210_CLK_PLL_U_OUT2 314
+#define TEGRA210_CLK_USB2_HSIC_TRK 315
+#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
+#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
+#define TEGRA210_CLK_XUSB_SSP_SRC 318
+#define TEGRA210_CLK_PLL_RE_OUT1 319
+/* 320 */
+/* 321 */
+/* 322 */
+/* 323 */
+/* 324 */
+/* 325 */
+/* 326 */
+/* 327 */
+/* 328 */
+/* 329 */
+/* 330 */
+/* 331 */
+/* 332 */
+/* 333 */
+/* 334 */
+/* 335 */
+/* 336 */
+/* 337 */
+/* 338 */
+/* 339 */
+/* 340 */
+/* 341 */
+/* 342 */
+/* 343 */
+/* 344 */
+/* 345 */
+/* 346 */
+/* 347 */
+/* 348 */
+/* 349 */
-#define TEGRA210_CLK_PLL_M_UD 313
-#define TEGRA210_CLK_PLL_C_UD 314
+#define TEGRA210_CLK_AUDIO0_MUX 350
+#define TEGRA210_CLK_AUDIO1_MUX 351
+#define TEGRA210_CLK_AUDIO2_MUX 352
+#define TEGRA210_CLK_AUDIO3_MUX 353
+#define TEGRA210_CLK_AUDIO4_MUX 354
+#define TEGRA210_CLK_SPDIF_MUX 355
+#define TEGRA210_CLK_CLK_OUT_1_MUX 356
+#define TEGRA210_CLK_CLK_OUT_2_MUX 357
+#define TEGRA210_CLK_CLK_OUT_3_MUX 358
+#define TEGRA210_CLK_DSIA_MUX 359
+#define TEGRA210_CLK_DSIB_MUX 360
+#define TEGRA210_CLK_SOR0_LVDS 361
+#define TEGRA210_CLK_XUSB_SS_DIV2 362
-#define TEGRA210_CLK_PLL_X 227
-#define TEGRA210_CLK_PLL_X_OUT0 228
+#define TEGRA210_CLK_PLL_M_UD 363
+#define TEGRA210_CLK_PLL_C_UD 364
+#define TEGRA210_CLK_SCLK_MUX 365
-#define TEGRA210_CLK_CCLK_G 262
-#define TEGRA210_CLK_CCLK_LP 263
+#define TEGRA210_CLK_CLK_MAX 366
-#define TEGRA210_CLK_CLK_MAX 315
-
-#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
+#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 2244582..889e49b 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -92,7 +92,7 @@
#define TEGRA30_CLK_OWR 71
#define TEGRA30_CLK_AFI 72
#define TEGRA30_CLK_CSITE 73
-#define TEGRA30_CLK_PCIEX 74
+/* 74 */
#define TEGRA30_CLK_AVPUCQ 75
#define TEGRA30_CLK_LA 76
/* 77 */
diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
new file mode 100644
index 0000000..a3a6b40
--- /dev/null
+++ b/include/dt-bindings/comphy/comphy_data.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _COMPHY_DATA_H_
+#define _COMPHY_DATA_H_
+
+#define PHY_SPEED_1_25G 0
+#define PHY_SPEED_1_5G 1
+#define PHY_SPEED_2_5G 2
+#define PHY_SPEED_3G 3
+#define PHY_SPEED_3_125G 4
+#define PHY_SPEED_5G 5
+#define PHY_SPEED_6G 6
+#define PHY_SPEED_6_25G 7
+#define PHY_SPEED_10_3125G 8
+#define PHY_SPEED_MAX 9
+#define PHY_SPEED_INVALID 0xff
+
+#define PHY_TYPE_UNCONNECTED 0
+#define PHY_TYPE_PEX0 1
+#define PHY_TYPE_PEX1 2
+#define PHY_TYPE_PEX2 3
+#define PHY_TYPE_PEX3 4
+#define PHY_TYPE_SATA0 5
+#define PHY_TYPE_SATA1 6
+#define PHY_TYPE_SATA2 7
+#define PHY_TYPE_SATA3 8
+#define PHY_TYPE_SGMII0 9
+#define PHY_TYPE_SGMII1 10
+#define PHY_TYPE_SGMII2 11
+#define PHY_TYPE_SGMII3 12
+#define PHY_TYPE_QSGMII 13
+#define PHY_TYPE_USB3_HOST0 14
+#define PHY_TYPE_USB3_HOST1 15
+#define PHY_TYPE_USB3_DEVICE 16
+#define PHY_TYPE_XAUI0 17
+#define PHY_TYPE_XAUI1 18
+#define PHY_TYPE_XAUI2 19
+#define PHY_TYPE_XAUI3 20
+#define PHY_TYPE_RXAUI0 21
+#define PHY_TYPE_RXAUI1 22
+#define PHY_TYPE_KR 23
+#define PHY_TYPE_MAX 24
+#define PHY_TYPE_INVALID 0xff
+
+#define PHY_POLARITY_NO_INVERT 0
+#define PHY_POLARITY_TXD_INVERT 1
+#define PHY_POLARITY_RXD_INVERT 2
+#define PHY_POLARITY_ALL_INVERT \
+ (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
+
+#define UTMI_PHY_TO_USB_HOST0 0
+#define UTMI_PHY_TO_USB_HOST1 1
+#define UTMI_PHY_TO_USB_DEVICE0 2
+#define UTMI_PHY_INVALID 0xff
+
+#endif /* _COMPHY_DATA_H_ */
+
diff --git a/include/dt-bindings/interrupt-controller/mips-gic.h b/include/dt-bindings/interrupt-controller/mips-gic.h
new file mode 100644
index 0000000..cf35a57
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/mips-gic.h
@@ -0,0 +1,9 @@
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define GIC_SHARED 0
+#define GIC_LOCAL 1
+
+#endif
diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h
new file mode 100644
index 0000000..8f48985
--- /dev/null
+++ b/include/dt-bindings/memory/tegra114-mc.h
@@ -0,0 +1,25 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
+
+#define TEGRA_SWGROUP_PTC 0
+#define TEGRA_SWGROUP_DC 1
+#define TEGRA_SWGROUP_DCB 2
+#define TEGRA_SWGROUP_EPP 3
+#define TEGRA_SWGROUP_G2 4
+#define TEGRA_SWGROUP_AVPC 5
+#define TEGRA_SWGROUP_NV 6
+#define TEGRA_SWGROUP_HDA 7
+#define TEGRA_SWGROUP_HC 8
+#define TEGRA_SWGROUP_MSENC 9
+#define TEGRA_SWGROUP_PPCS 10
+#define TEGRA_SWGROUP_VDE 11
+#define TEGRA_SWGROUP_MPCORELP 12
+#define TEGRA_SWGROUP_MPCORE 13
+#define TEGRA_SWGROUP_VI 14
+#define TEGRA_SWGROUP_ISP 15
+#define TEGRA_SWGROUP_XUSB_HOST 16
+#define TEGRA_SWGROUP_XUSB_DEV 17
+#define TEGRA_SWGROUP_EMUCIF 18
+#define TEGRA_SWGROUP_TSEC 19
+
+#endif
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
new file mode 100644
index 0000000..d1731bc
--- /dev/null
+++ b/include/dt-bindings/memory/tegra210-mc.h
@@ -0,0 +1,36 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
+
+#define TEGRA_SWGROUP_PTC 0
+#define TEGRA_SWGROUP_DC 1
+#define TEGRA_SWGROUP_DCB 2
+#define TEGRA_SWGROUP_AFI 3
+#define TEGRA_SWGROUP_AVPC 4
+#define TEGRA_SWGROUP_HDA 5
+#define TEGRA_SWGROUP_HC 6
+#define TEGRA_SWGROUP_NVENC 7
+#define TEGRA_SWGROUP_PPCS 8
+#define TEGRA_SWGROUP_SATA 9
+#define TEGRA_SWGROUP_MPCORE 10
+#define TEGRA_SWGROUP_ISP2 11
+#define TEGRA_SWGROUP_XUSB_HOST 12
+#define TEGRA_SWGROUP_XUSB_DEV 13
+#define TEGRA_SWGROUP_ISP2B 14
+#define TEGRA_SWGROUP_TSEC 15
+#define TEGRA_SWGROUP_A9AVP 16
+#define TEGRA_SWGROUP_GPU 17
+#define TEGRA_SWGROUP_SDMMC1A 18
+#define TEGRA_SWGROUP_SDMMC2A 19
+#define TEGRA_SWGROUP_SDMMC3A 20
+#define TEGRA_SWGROUP_SDMMC4A 21
+#define TEGRA_SWGROUP_VIC 22
+#define TEGRA_SWGROUP_VI 23
+#define TEGRA_SWGROUP_NVDEC 24
+#define TEGRA_SWGROUP_APE 25
+#define TEGRA_SWGROUP_NVJPG 26
+#define TEGRA_SWGROUP_SE 27
+#define TEGRA_SWGROUP_AXIAP 28
+#define TEGRA_SWGROUP_ETR 29
+#define TEGRA_SWGROUP_TSECB 30
+
+#endif
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
new file mode 100644
index 0000000..502beb0
--- /dev/null
+++ b/include/dt-bindings/memory/tegra30-mc.h
@@ -0,0 +1,24 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
+
+#define TEGRA_SWGROUP_PTC 0
+#define TEGRA_SWGROUP_DC 1
+#define TEGRA_SWGROUP_DCB 2
+#define TEGRA_SWGROUP_EPP 3
+#define TEGRA_SWGROUP_G2 4
+#define TEGRA_SWGROUP_MPE 5
+#define TEGRA_SWGROUP_VI 6
+#define TEGRA_SWGROUP_AFI 7
+#define TEGRA_SWGROUP_AVPC 8
+#define TEGRA_SWGROUP_NV 9
+#define TEGRA_SWGROUP_NV2 10
+#define TEGRA_SWGROUP_HDA 11
+#define TEGRA_SWGROUP_HC 12
+#define TEGRA_SWGROUP_PPCS 13
+#define TEGRA_SWGROUP_SATA 14
+#define TEGRA_SWGROUP_VDE 15
+#define TEGRA_SWGROUP_MPCORELP 16
+#define TEGRA_SWGROUP_MPCORE 17
+#define TEGRA_SWGROUP_ISP 18
+
+#endif
diff --git a/include/dt-bindings/pinctrl/bcm2835.h b/include/dt-bindings/pinctrl/bcm2835.h
new file mode 100644
index 0000000..6f0bc37
--- /dev/null
+++ b/include/dt-bindings/pinctrl/bcm2835.h
@@ -0,0 +1,27 @@
+/*
+ * Header providing constants for bcm2835 pinctrl bindings.
+ *
+ * Copyright (C) 2015 Stefan Wahren <stefan.wahren@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__
+#define __DT_BINDINGS_PINCTRL_BCM2835_H__
+
+/* brcm,function property */
+#define BCM2835_FSEL_GPIO_IN 0
+#define BCM2835_FSEL_GPIO_OUT 1
+#define BCM2835_FSEL_ALT5 2
+#define BCM2835_FSEL_ALT4 3
+#define BCM2835_FSEL_ALT0 4
+#define BCM2835_FSEL_ALT1 5
+#define BCM2835_FSEL_ALT2 6
+#define BCM2835_FSEL_ALT3 7
+
+#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
index 7448edf..5c75e80 100644
--- a/include/dt-bindings/pinctrl/dra.h
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -30,6 +30,26 @@
#define MUX_MODE14 0xe
#define MUX_MODE15 0xf
+/* Certain pins need virtual mode, but note: they may glitch */
+#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4))
+#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4))
+#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
+#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4))
+#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4))
+#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4))
+#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4))
+#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4))
+#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4))
+#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4))
+#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4))
+#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4))
+#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4))
+#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4))
+#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4))
+#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4))
+
+#define MODE_SELECT (1 << 8)
+
#define PULL_ENA (0 << 16)
#define PULL_DIS (1 << 16)
#define PULL_UP (1 << 17)
@@ -47,5 +67,11 @@
#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
+
#endif
diff --git a/include/dt-bindings/power/raspberrypi-power.h b/include/dt-bindings/power/raspberrypi-power.h
new file mode 100644
index 0000000..b3ff8e0
--- /dev/null
+++ b/include/dt-bindings/power/raspberrypi-power.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright © 2015 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
+#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
+
+/* These power domain indices are the firmware interface's indices
+ * minus one.
+ */
+#define RPI_POWER_DOMAIN_I2C0 0
+#define RPI_POWER_DOMAIN_I2C1 1
+#define RPI_POWER_DOMAIN_I2C2 2
+#define RPI_POWER_DOMAIN_VIDEO_SCALER 3
+#define RPI_POWER_DOMAIN_VPU1 4
+#define RPI_POWER_DOMAIN_HDMI 5
+#define RPI_POWER_DOMAIN_USB 6
+#define RPI_POWER_DOMAIN_VEC 7
+#define RPI_POWER_DOMAIN_JPEG 8
+#define RPI_POWER_DOMAIN_H264 9
+#define RPI_POWER_DOMAIN_V3D 10
+#define RPI_POWER_DOMAIN_ISP 11
+#define RPI_POWER_DOMAIN_UNICAM0 12
+#define RPI_POWER_DOMAIN_UNICAM1 13
+#define RPI_POWER_DOMAIN_CCP2RX 14
+#define RPI_POWER_DOMAIN_CSI2 15
+#define RPI_POWER_DOMAIN_CPI 16
+#define RPI_POWER_DOMAIN_DSI0 17
+#define RPI_POWER_DOMAIN_DSI1 18
+#define RPI_POWER_DOMAIN_TRANSPOSER 19
+#define RPI_POWER_DOMAIN_CCP2TX 20
+#define RPI_POWER_DOMAIN_CDP 21
+#define RPI_POWER_DOMAIN_ARM 22
+
+#define RPI_POWER_DOMAIN_COUNT 23
+
+#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
index 85aaf66..729ab9f 100644
--- a/include/dt-bindings/thermal/tegra124-soctherm.h
+++ b/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -9,5 +9,6 @@
#define TEGRA124_SOCTHERM_SENSOR_MEM 1
#define TEGRA124_SOCTHERM_SENSOR_GPU 2
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
+#define TEGRA124_SOCTHERM_SENSOR_NUM 4
#endif
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 5b9602c..4dda009 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -253,14 +253,12 @@
* See rockchip_dw_mmc.c for an example.
*
* @cfg: Configuration structure to fill in (generally &plat->mmc)
- * @name: Device name (normally dev->name)
- * @buswidth: Bus width (in bits, such as 4 or 8)
- * @caps: Host capabilities (MMC_MODE_...)
+ * @host: DWMMC host
* @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
* @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
*/
-void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
- uint caps, u32 max_clk, u32 min_clk);
+void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
+ u32 max_clk, u32 min_clk);
/**
* dwmci_bind() - Set up a new MMC block device
diff --git a/include/efi.h b/include/efi.h
index 5a3b8cf..3d58780 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -15,6 +15,7 @@
#ifndef _EFI_H
#define _EFI_H
+#include <linux/linkage.h>
#include <linux/string.h>
#include <linux/types.h>
@@ -22,15 +23,18 @@
/* EFI uses the Microsoft ABI which is not the default for GCC */
#define EFIAPI __attribute__((ms_abi))
#else
-#define EFIAPI
+#define EFIAPI asmlinkage
#endif
struct efi_device_path;
#define EFI_BITS_PER_LONG BITS_PER_LONG
-/* With 64-bit EFI stub, EFI_BITS_PER_LONG has to be 64 */
-#ifdef CONFIG_EFI_STUB_64BIT
+/*
+ * With 64-bit EFI stub, EFI_BITS_PER_LONG has to be 64. EFI_STUB is set
+ * in lib/efi/Makefile, when building the stub.
+ */
+#if defined(CONFIG_EFI_STUB_64BIT) && defined(EFI_STUB)
#undef EFI_BITS_PER_LONG
#define EFI_BITS_PER_LONG 64
#endif
diff --git a/include/efi_api.h b/include/efi_api.h
index f572b88..5c3836a 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -201,6 +201,10 @@
EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, \
0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0)
+#define SMBIOS_TABLE_GUID \
+ EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3, \
+ 0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
struct efi_configuration_table
{
efi_guid_t guid;
@@ -264,6 +268,19 @@
u16 length;
};
+struct efi_mac_addr {
+ u8 addr[32];
+};
+
+#define DEVICE_PATH_TYPE_MESSAGING_DEVICE 0x03
+# define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b
+
+struct efi_device_path_mac_addr {
+ struct efi_device_path dp;
+ struct efi_mac_addr mac;
+ u8 if_type;
+};
+
#define DEVICE_PATH_TYPE_MEDIA_DEVICE 0x04
# define DEVICE_PATH_SUB_TYPE_FILE_PATH 0x04
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 9738835..99619f5 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -85,6 +85,8 @@
int efi_gop_register(void);
/* Called by bootefi to make the network interface available */
int efi_net_register(void **handle);
+/* Called by bootefi to make SMBIOS tables available */
+void efi_smbios_register(void);
/* Called by networking code to memorize the dhcp ack package */
void efi_net_set_dhcp_ack(void *pkt, int len);
@@ -93,7 +95,7 @@
* Stub implementation for a protocol opener that just returns the handle as
* interface
*/
-efi_status_t efi_return_handle(void *handle,
+efi_status_t EFIAPI efi_return_handle(void *handle,
efi_guid_t *protocol, void **protocol_interface,
void *agent_handle, void *controller_handle,
uint32_t attributes);
@@ -117,8 +119,13 @@
/* More specific EFI memory allocator, called by EFI payloads */
efi_status_t efi_allocate_pages(int type, int memory_type, unsigned long pages,
uint64_t *memory);
-/* EFI memory free function. Not implemented today */
+/* EFI memory free function. */
efi_status_t efi_free_pages(uint64_t memory, unsigned long pages);
+/* EFI memory allocator for small allocations */
+efi_status_t efi_allocate_pool(int pool_type, unsigned long size,
+ void **buffer);
+/* EFI pool memory free function. */
+efi_status_t efi_free_pool(void *buffer);
/* Returns the EFI memory map */
efi_status_t efi_get_memory_map(unsigned long *memory_map_size,
struct efi_mem_desc *memory_map,
@@ -130,6 +137,8 @@
bool overlap_only_ram);
/* Called by board init to initialize the EFI memory map */
int efi_memory_init(void);
+/* Adds new or overrides configuration table entry to the system table */
+efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table);
#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
extern void *efi_bounce_buffer;
@@ -147,14 +156,32 @@
* Use these to indicate that your code / data should go into the EFI runtime
* section and thus still be available when the OS is running
*/
-#define EFI_RUNTIME_DATA __attribute__ ((section ("efi_runtime_data")))
-#define EFI_RUNTIME_TEXT __attribute__ ((section ("efi_runtime_text")))
+#define __efi_runtime_data __attribute__ ((section ("efi_runtime_data")))
+#define __efi_runtime __attribute__ ((section ("efi_runtime_text")))
+
+/* Call this with mmio_ptr as the _pointer_ to a pointer to an MMIO region
+ * to make it available at runtime */
+void efi_add_runtime_mmio(void *mmio_ptr, u64 len);
+
+/* Boards may provide the functions below to implement RTS functionality */
+
+void __efi_runtime EFIAPI efi_reset_system(
+ enum efi_reset_type reset_type,
+ efi_status_t reset_status,
+ unsigned long data_size, void *reset_data);
+void efi_reset_system_init(void);
+
+efi_status_t __efi_runtime EFIAPI efi_get_time(
+ struct efi_time *time,
+ struct efi_time_cap *capabilities);
+void efi_get_time_init(void);
#else /* defined(EFI_LOADER) && !defined(CONFIG_SPL_BUILD) */
/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
-#define EFI_RUNTIME_DATA
-#define EFI_RUNTIME_TEXT
+#define __efi_runtime_data
+#define __efi_runtime
+static inline void efi_add_runtime_mmio(void *mmio_ptr, u64 len) { }
/* No loader configured, stub out EFI_ENTRY */
static inline void efi_restore_gd(void) { }
diff --git a/include/elf.h b/include/elf.h
index a35e085..aaecac7 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -13,6 +13,7 @@
#ifndef _ELF_H
#define _ELF_H
+#ifndef __ASSEMBLER__
#include "compiler.h"
/*
@@ -394,6 +395,12 @@
Elf64_Xword r_info; /* index and type of relocation */
} Elf64_Rel;
+typedef struct {
+ Elf64_Addr r_offset; /* Location at which to apply the action */
+ Elf64_Xword r_info; /* index and type of relocation */
+ Elf64_Sxword r_addend; /* Constant addend used to compute value */
+} Elf64_Rela;
+
/* Extract relocation info - r_info */
#define ELF32_R_SYM(i) ((i) >> 8)
#define ELF32_R_TYPE(i) ((unsigned char) (i))
@@ -511,6 +518,8 @@
#define ELF_TARG_VER 1 /* The ver for which this code is intended */
+#endif /* __ASSEMBLER */
+
/*
* XXX - PowerPC defines really don't belong in here,
* but we'll put them in for simplicity.
@@ -596,6 +605,16 @@
that may still be in object files. */
#define R_PPC_TOC16 255
+ /* ARM relocs */
+#define R_ARM_NONE 0 /* No reloc */
+#define R_ARM_RELATIVE 23 /* Adjust by program base */
+
+/* AArch64 relocs */
+#define R_AARCH64_NONE 0 /* No relocation. */
+#define R_AARCH64_RELATIVE 1027 /* Adjust by program base. */
+
+#ifndef __ASSEMBLER__
int valid_elf_image(unsigned long addr);
+#endif
#endif /* _ELF_H */
diff --git a/include/environment.h b/include/environment.h
index 1fdbdad..b602e8a 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -16,10 +16,9 @@
* shifts the remaining entries to the front. Replacing an entry is a
* combination of deleting the old value and adding the new one.
*
- * The environment is preceeded by a 32 bit CRC over the data part.
+ * The environment is preceded by a 32 bit CRC over the data part.
*
- **************************************************************************
- */
+ *************************************************************************/
#if defined(CONFIG_ENV_IS_IN_FLASH)
# ifndef CONFIG_ENV_ADDR
diff --git a/include/environment/ti/dfu.h b/include/environment/ti/dfu.h
new file mode 100644
index 0000000..caf71a3
--- /dev/null
+++ b/include/environment/ti/dfu.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for DFU on TI boards.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define DFU_ALT_INFO_MMC \
+ "dfu_alt_info_mmc=" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "MLO fat 0 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x400;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 0 1;" \
+ "spl-os-image fat 0 1;" \
+ "u-boot.img fat 0 1;" \
+ "uEnv.txt fat 0 1\0"
+
+#define DFU_ALT_INFO_EMMC \
+ "dfu_alt_info_emmc=" \
+ "rawemmc raw 0 3751936;" \
+ "boot part 1 1;" \
+ "rootfs part 1 2;" \
+ "MLO fat 1 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x1000;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 1 1;" \
+ "spl-os-image fat 1 1;" \
+ "u-boot.img fat 1 1;" \
+ "uEnv.txt fat 1 1\0"
+
+#ifdef CONFIG_NAND
+#define DFU_ALT_INFO_NAND \
+ "dfu_alt_info_nand=" \
+ "SPL part 0 1;" \
+ "SPL.backup1 part 0 2;" \
+ "SPL.backup2 part 0 3;" \
+ "SPL.backup3 part 0 4;" \
+ "u-boot part 0 5;" \
+ "u-boot-spl-os part 0 6;" \
+ "kernel part 0 8;" \
+ "rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "kernel ram 0x80200000 0x4000000;" \
+ "fdt ram 0x80f80000 0x80000;" \
+ "ramdisk ram 0x81000000 0x4000000\0"
+
+#define DFU_ALT_INFO_QSPI_XIP \
+ "dfu_alt_info_qspi=" \
+ "u-boot.bin raw 0x0 0x080000;" \
+ "u-boot.backup raw 0x080000 0x080000;" \
+ "u-boot-spl-os raw 0x100000 0x010000;" \
+ "u-boot-env raw 0x110000 0x010000;" \
+ "u-boot-env.backup raw 0x120000 0x010000;" \
+ "kernel raw 0x130000 0x800000\0"
+
+#define DFU_ALT_INFO_QSPI \
+ "dfu_alt_info_qspi=" \
+ "MLO raw 0x0 0x040000;" \
+ "u-boot.img raw 0x040000 0x0100000;" \
+ "u-boot-spl-os raw 0x140000 0x080000;" \
+ "u-boot-env raw 0x1C0000 0x010000;" \
+ "u-boot-env.backup raw 0x1D0000 0x010000;" \
+ "kernel raw 0x1E0000 0x800000\0"
diff --git a/include/errno.h b/include/errno.h
index 15ece2f..e0c670a 100644
--- a/include/errno.h
+++ b/include/errno.h
@@ -7,7 +7,7 @@
#ifndef _ERRNO_H
#define _ERRNO_H
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
extern int errno;
diff --git a/include/exports.h b/include/exports.h
index deef8fb..1d81bc4 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -57,7 +57,7 @@
};
-#define XF_VERSION 8
+#define XF_VERSION 9
#if defined(CONFIG_X86)
extern gd_t *global_data;
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 13d2c56..bb55639 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -28,6 +28,7 @@
#define __EXT4__
#include <ext_common.h>
+#define EXT4_INDEX_FL 0x00001000 /* Inode uses hash tree index */
#define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */
#define EXT4_EXT_MAGIC 0xf30a
#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010
@@ -86,6 +87,8 @@
uint32_t inodesz;
/* Sectors per Block */
uint32_t sect_perblk;
+ /* Group Descriptor size */
+ uint16_t gdsize;
/* Group Descriptor Block Number */
uint32_t gdtable_blkno;
/* Total block groups of partition */
@@ -95,7 +98,6 @@
/* Superblock */
struct ext2_sblock *sb;
/* Block group descritpor table */
- struct ext2_block_group *bgd;
char *gdtable;
/* Block Bitmap Related */
@@ -124,7 +126,7 @@
int ext4fs_init(void);
void ext4fs_deinit(void);
-int ext4fs_filename_check(char *filename);
+int ext4fs_filename_unlink(char *filename);
int ext4fs_write(const char *fname, unsigned char *buffer,
unsigned long sizebytes);
int ext4_write_file(const char *filename, void *buf, loff_t offset, loff_t len,
@@ -133,7 +135,7 @@
struct ext_filesystem *get_fs(void);
int ext4fs_open(const char *filename, loff_t *len);
-int ext4fs_read(char *buf, loff_t len, loff_t *actread);
+int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread);
int ext4fs_mount(unsigned part_length);
void ext4fs_close(void);
void ext4fs_reinit_global(void);
diff --git a/include/ext_common.h b/include/ext_common.h
index 6cddf16..07b61fa 100644
--- a/include/ext_common.h
+++ b/include/ext_common.h
@@ -49,11 +49,9 @@
#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data))
/* Log2 size of ext2 block in bytes. */
-#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu \
+#define LOG2_BLOCK_SIZE(data) (le32_to_cpu \
(data->sblock.log2_block_size) \
+ EXT2_MIN_BLOCK_LOG_SIZE)
-#define INODE_SIZE_FILESYSTEM(data) (__le32_to_cpu \
- (data->sblock.inode_size))
#define EXT2_FT_DIR 2
#define SUCCESS 1
@@ -66,92 +64,134 @@
/* The ext2 superblock. */
struct ext2_sblock {
- uint32_t total_inodes;
- uint32_t total_blocks;
- uint32_t reserved_blocks;
- uint32_t free_blocks;
- uint32_t free_inodes;
- uint32_t first_data_block;
- uint32_t log2_block_size;
- uint32_t log2_fragment_size;
- uint32_t blocks_per_group;
- uint32_t fragments_per_group;
- uint32_t inodes_per_group;
- uint32_t mtime;
- uint32_t utime;
- uint16_t mnt_count;
- uint16_t max_mnt_count;
- uint16_t magic;
- uint16_t fs_state;
- uint16_t error_handling;
- uint16_t minor_revision_level;
- uint32_t lastcheck;
- uint32_t checkinterval;
- uint32_t creator_os;
- uint32_t revision_level;
- uint16_t uid_reserved;
- uint16_t gid_reserved;
- uint32_t first_inode;
- uint16_t inode_size;
- uint16_t block_group_number;
- uint32_t feature_compatibility;
- uint32_t feature_incompat;
- uint32_t feature_ro_compat;
- uint32_t unique_id[4];
+ __le32 total_inodes;
+ __le32 total_blocks;
+ __le32 reserved_blocks;
+ __le32 free_blocks;
+ __le32 free_inodes;
+ __le32 first_data_block;
+ __le32 log2_block_size;
+ __le32 log2_fragment_size;
+ __le32 blocks_per_group;
+ __le32 fragments_per_group;
+ __le32 inodes_per_group;
+ __le32 mtime;
+ __le32 utime;
+ __le16 mnt_count;
+ __le16 max_mnt_count;
+ __le16 magic;
+ __le16 fs_state;
+ __le16 error_handling;
+ __le16 minor_revision_level;
+ __le32 lastcheck;
+ __le32 checkinterval;
+ __le32 creator_os;
+ __le32 revision_level;
+ __le16 uid_reserved;
+ __le16 gid_reserved;
+ __le32 first_inode;
+ __le16 inode_size;
+ __le16 block_group_number;
+ __le32 feature_compatibility;
+ __le32 feature_incompat;
+ __le32 feature_ro_compat;
+ __le32 unique_id[4];
char volume_name[16];
char last_mounted_on[64];
- uint32_t compression_info;
+ __le32 compression_info;
+ uint8_t prealloc_blocks;
+ uint8_t prealloc_dir_blocks;
+ __le16 reserved_gdt_blocks;
+ uint8_t journal_uuid[16];
+ __le32 journal_inode;
+ __le32 journal_dev;
+ __le32 last_orphan;
+ __le32 hash_seed[4];
+ uint8_t default_hash_version;
+ uint8_t journal_backup_type;
+ __le16 descriptor_size;
+ __le32 default_mount_options;
+ __le32 first_meta_block_group;
+ __le32 mkfs_time;
+ __le32 journal_blocks[17];
+ __le32 total_blocks_high;
+ __le32 reserved_blocks_high;
+ __le32 free_blocks_high;
+ __le16 min_extra_inode_size;
+ __le16 want_extra_inode_size;
+ __le32 flags;
+ __le16 raid_stride;
+ __le16 mmp_interval;
+ __le64 mmp_block;
+ __le32 raid_stripe_width;
+ uint8_t log2_groups_per_flex;
+ uint8_t checksum_type;
};
struct ext2_block_group {
- __u32 block_id; /* Blocks bitmap block */
- __u32 inode_id; /* Inodes bitmap block */
- __u32 inode_table_id; /* Inodes table block */
- __u16 free_blocks; /* Free blocks count */
- __u16 free_inodes; /* Free inodes count */
- __u16 used_dir_cnt; /* Directories count */
- __u16 bg_flags;
- __u32 bg_reserved[2];
- __u16 bg_itable_unused; /* Unused inodes count */
- __u16 bg_checksum; /* crc16(s_uuid+grouo_num+group_desc)*/
+ __le32 block_id; /* Blocks bitmap block */
+ __le32 inode_id; /* Inodes bitmap block */
+ __le32 inode_table_id; /* Inodes table block */
+ __le16 free_blocks; /* Free blocks count */
+ __le16 free_inodes; /* Free inodes count */
+ __le16 used_dir_cnt; /* Directories count */
+ __le16 bg_flags;
+ __le32 bg_exclude_bitmap;
+ __le16 bg_block_id_csum;
+ __le16 bg_inode_id_csum;
+ __le16 bg_itable_unused; /* Unused inodes count */
+ __le16 bg_checksum; /* crc16(s_uuid+group_num+group_desc)*/
+ /* following fields only exist if descriptor size is 64 */
+ __le32 block_id_high;
+ __le32 inode_id_high;
+ __le32 inode_table_id_high;
+ __le16 free_blocks_high;
+ __le16 free_inodes_high;
+ __le16 used_dir_cnt_high;
+ __le16 bg_itable_unused_high;
+ __le32 bg_exclude_bitmap_high;
+ __le16 bg_block_id_csum_high;
+ __le16 bg_inode_id_csum_high;
+ __le32 bg_reserved;
};
/* The ext2 inode. */
struct ext2_inode {
- uint16_t mode;
- uint16_t uid;
- uint32_t size;
- uint32_t atime;
- uint32_t ctime;
- uint32_t mtime;
- uint32_t dtime;
- uint16_t gid;
- uint16_t nlinks;
- uint32_t blockcnt; /* Blocks of 512 bytes!! */
- uint32_t flags;
- uint32_t osd1;
+ __le16 mode;
+ __le16 uid;
+ __le32 size;
+ __le32 atime;
+ __le32 ctime;
+ __le32 mtime;
+ __le32 dtime;
+ __le16 gid;
+ __le16 nlinks;
+ __le32 blockcnt; /* Blocks of either 512 or block_size bytes */
+ __le32 flags;
+ __le32 osd1;
union {
struct datablocks {
- uint32_t dir_blocks[INDIRECT_BLOCKS];
- uint32_t indir_block;
- uint32_t double_indir_block;
- uint32_t triple_indir_block;
+ __le32 dir_blocks[INDIRECT_BLOCKS];
+ __le32 indir_block;
+ __le32 double_indir_block;
+ __le32 triple_indir_block;
} blocks;
char symlink[60];
+ char inline_data[60];
} b;
- uint32_t version;
- uint32_t acl;
- uint32_t dir_acl;
- uint32_t fragment_addr;
- uint32_t osd2[3];
+ __le32 version;
+ __le32 acl;
+ __le32 size_high; /* previously dir_acl, but never used */
+ __le32 fragment_addr;
+ __le32 osd2[3];
};
/* The header of an ext2 directory entry. */
struct ext2_dirent {
- uint32_t inode;
- uint16_t direntlen;
- uint8_t namelen;
- uint8_t filetype;
+ __le32 inode;
+ __le16 direntlen;
+ __u8 namelen;
+ __u8 filetype;
};
struct ext2fs_node {
diff --git a/include/fat.h b/include/fat.h
index 9d053e6..e38f380 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -33,6 +33,8 @@
#define FAT16BUFSIZE (FATBUFSIZE/2)
#define FAT32BUFSIZE (FATBUFSIZE/4)
+/* Maximum number of entry for long file name according to spec */
+#define MAX_LFN_SLOT 20
/* Filesystem identifiers */
#define FAT12_SIGN "FAT12 "
@@ -169,6 +171,7 @@
int fatsize; /* Size of FAT in bits */
__u32 fatlength; /* Length of FAT in sectors */
__u16 fat_sect; /* Starting sector of the FAT */
+ __u8 fat_dirty; /* Set if fatbuf has been modified */
__u32 rootdir_sect; /* Start sector of root directory */
__u16 sect_size; /* Size of sectors in bytes */
__u16 clust_size; /* Size of clusters in sectors */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index e9f3497..955c121 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -93,7 +93,15 @@
* property will be left untouched.
* @return 0 if ok, or -1 or -FDT_ERR_... on error
*/
+#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
+#else
+static inline int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[],
+ int banks)
+{
+ return 0;
+}
+#endif
void fdt_fixup_ethernet(void *fdt);
int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
@@ -114,9 +122,9 @@
int fdt_fixup_display(void *blob, const char *path, const char *display);
#if defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL)
-void fdt_fixup_dr_usb(void *blob, bd_t *bd);
+void fsl_fdt_fixup_dr_usb(void *blob, bd_t *bd);
#else
-static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
+static inline void fsl_fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
#endif /* defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL) */
#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
@@ -167,7 +175,15 @@
int ft_system_setup(void *blob, bd_t *bd);
void set_working_fdt_addr(ulong addr);
-int fdt_shrink_to_minimum(void *blob);
+
+/**
+ * shrink down the given blob to minimum size + some extrasize if required
+ *
+ * @param blob FDT blob to update
+ * @param extrasize additional bytes needed
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int fdt_shrink_to_minimum(void *blob, uint extrasize);
int fdt_increase_size(void *fdt, int add_len);
int fdt_fixup_nor_flash_size(void *blob);
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 71c02a0..5c54f71 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -148,7 +148,6 @@
COMPAT_INTEL_MICROCODE, /* Intel microcode update */
COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
- COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */
COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
@@ -977,6 +976,40 @@
*/
int fdtdec_decode_display_timing(const void *blob, int node, int index,
struct display_timing *config);
+
+/**
+ * fdtdec_setup_memory_size() - decode and setup gd->ram_size
+ *
+ * Decode the /memory 'reg' property to determine the size of the first memory
+ * bank, populate the global data with the size of the first bank of memory.
+ *
+ * This function should be called from a boards dram_init(). This helper
+ * function allows for boards to query the device tree for DRAM size instead of
+ * hard coding the value in the case where the memory size cannot be detected
+ * automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_memory_size(void);
+
+/**
+ * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
+ *
+ * Decode the /memory 'reg' property to determine the address and size of the
+ * memory banks. Use this data to populate the global data board info with the
+ * phys address and size of memory banks.
+ *
+ * This function should be called from a boards dram_init_banksize(). This
+ * helper function allows for boards to query the device tree for memory bank
+ * information instead of hard coding the information in cases where it cannot
+ * be detected automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_memory_banksize(void);
+
/**
* Set up the device tree ready for use
*/
diff --git a/include/fsl_csu.h b/include/fsl_csu.h
index f4d97fb..8582ac0 100644
--- a/include/fsl_csu.h
+++ b/include/fsl_csu.h
@@ -30,5 +30,7 @@
};
void enable_layerscape_ns_access(void);
+void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
+void set_pcie_ns_access(int pcie, u16 val);
#endif
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 3351acd..261b94e 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -15,7 +15,7 @@
#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
/* All controllers are for main memory */
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
#endif
#ifdef CONFIG_SYS_FSL_DDR_LE
@@ -54,7 +54,6 @@
*
* All data structures have to be on the stack
*/
-#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
typedef struct {
@@ -138,4 +137,6 @@
void update_spd_address(unsigned int ctrl_num,
unsigned int slot,
unsigned int *addr);
+
+void erratum_a009942_check_cpo(void);
#endif
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 486e47e..1404c57 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -299,7 +299,7 @@
unsigned int ddr_cdr2;
unsigned int err_disable;
unsigned int err_int_en;
- unsigned int debug[32];
+ unsigned int debug[64];
} fsl_ddr_cfg_regs_t;
typedef struct memctl_options_partial_s {
@@ -374,7 +374,8 @@
unsigned int additive_latency_override_value;
unsigned int clk_adjust; /* */
- unsigned int cpo_override;
+ unsigned int cpo_override; /* override timing_cfg_2[CPO]*/
+ unsigned int cpo_sample; /* optimize debug_29[24:31] */
unsigned int write_data_delay; /* DQS adjust */
unsigned int cswl_override;
diff --git a/include/fsl_debug_server.h b/include/fsl_debug_server.h
deleted file mode 100644
index 28d8adb..0000000
--- a/include/fsl_debug_server.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FSL_DBG_SERVER_H__
-#define __FSL_DBG_SERVER_H__
-
-#include <asm/io.h>
-#include <common.h>
-
-/*
- * Define Debug Server firmware version information
- */
-
-/* Major version number: incremented on API compatibility changes */
-#define DEBUG_SERVER_VER_MAJOR 0
-
-/* Minor version number: incremented on API additions (backward
- * compatible); reset when major version is incremented.
- */
-#define DEBUG_SERVER_VER_MINOR 1
-
-#define DEBUG_SERVER_INIT_STATUS (1 << 0)
-#define DEBUG_SERVER_INIT_STATUS_MASK (0x00000001)
-
-int debug_server_init(void);
-unsigned long debug_server_get_dram_block_size(void);
-
-#endif /* __FSL_DBG_SERVER_H__ */
-
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index c6f4666..e15d3ae 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -10,7 +10,7 @@
#ifndef __FSL_ESDHC_H__
#define __FSL_ESDHC_H__
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/byteorder.h>
/* needed for the mmc_cfg definition */
diff --git a/include/fsl_immap.h b/include/fsl_immap.h
index e4addad..b1c4fe7 100644
--- a/include/fsl_immap.h
+++ b/include/fsl_immap.h
@@ -131,7 +131,6 @@
u32 capture_ext_address; /* Error Extended Addr Capture */
u32 err_sbe; /* Single-Bit ECC Error Management */
u8 res_e5c[164];
- u32 debug[32]; /* debug_1 to debug_32 */
- u8 res_f80[128];
+ u32 debug[64]; /* debug_1 to debug_64 */
};
#endif /* __FSL_IMMAP_H */
diff --git a/include/fsl_memac.h b/include/fsl_memac.h
index bed2a40..431c2a0 100644
--- a/include/fsl_memac.h
+++ b/include/fsl_memac.h
@@ -226,6 +226,7 @@
#define PHY_SGMII_CR_PHY_RESET 0x8000
#define PHY_SGMII_CR_RESET_AN 0x0200
#define PHY_SGMII_CR_DEF_VAL 0x1140
+#define PHY_SGMII_IF_SPEED_GIGABIT 0x0008
#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
#define PHY_SGMII_IF_MODE_AN 0x0002
#define PHY_SGMII_IF_MODE_SGMII 0x0001
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
index a939d89..d5c4f8d 100644
--- a/include/fsl_mmdc.h
+++ b/include/fsl_mmdc.h
@@ -7,63 +7,39 @@
#ifndef FSL_MMDC_H
#define FSL_MMDC_H
-#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000
-#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954
-#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
-#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
-
-#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680
-#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
-#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
-#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
-
-#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
-
-#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f
-
-#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003
-
-#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16)
-
-/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
-#define WR_LVL_HW_EN 0x00000001
+/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
+#define MPWLGCR_HW_WL_EN (1 << 0)
/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
-#define MPR_COMPARE_EN 0x00000001
+#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
-#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
-#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
-#define AUTO_RD_CALIBRATION_EN 0x00000010
+#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
-#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035
+/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
+#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
-#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
-
-#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000
-
-#define START_REFRESH 0x00000001
+/* MMDC Core Refresh Control Register (MMDC_MDREF) */
+#define MDREF_START_REFRESH (1 << 0)
/* MMDC Core Special Command Register (MDSCR) */
-#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
-
-#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
-
-#define DISABLE_CFG_REQ 0x0
-#define CONFIGURATION_REQ (0x1 << 15)
-#define WL_EN (0x1 << 9)
-
-#define CMD_NORMAL (0x0 << 4)
-#define CMD_PRECHARGE (0x1 << 4)
-#define CMD_AUTO_REFRESH (0x2 << 4)
-#define CMD_LOAD_MODE_REG (0x3 << 4)
-#define CMD_ZQ_CALIBRATION (0x4 << 4)
-#define CMD_PRECHARGE_BANK_OPEN (0x5 << 4)
-#define CMD_MRR (0x6 << 4)
-
+#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
+#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
+#define MDSCR_DISABLE_CFG_REQ (0 << 15)
+#define MDSCR_ENABLE_CON_REQ (1 << 15)
+#define MDSCR_CON_ACK (1 << 14)
+#define MDSCR_WL_EN (1 << 9)
+#define CMD_NORMAL (0 << 4)
+#define CMD_PRECHARGE (1 << 4)
+#define CMD_AUTO_REFRESH (2 << 4)
+#define CMD_LOAD_MODE_REG (3 << 4)
+#define CMD_ZQ_CALIBRATION (4 << 4)
+#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
+#define CMD_MRR (6 << 4)
#define CMD_BANK_ADDR_0 0x0
#define CMD_BANK_ADDR_1 0x1
#define CMD_BANK_ADDR_2 0x2
@@ -73,8 +49,22 @@
#define CMD_BANK_ADDR_6 0x6
#define CMD_BANK_ADDR_7 0x7
+/* MMDC Core Control Register (MDCTL) */
+#define MDCTL_SDE0 (1 << 31)
+#define MDCTL_SDE1 (1 << 30)
+
+/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
+#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
+
+/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
+#define MMDC_MPMUR0_FRC_MSR (1 << 11)
+
+/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
+/* default 64 for a quarter cycle delay */
+#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040
+
/* MMDC Registers */
-struct mmdc_p_regs {
+struct mmdc_regs {
u32 mdctl;
u32 mdpdc;
u32 mdotc;
@@ -120,7 +110,10 @@
u32 mprddqby1dl;
u32 mprddqby2dl;
u32 mprddqby3dl;
- u32 res5[4];
+ u32 mpwrdqby0dl;
+ u32 mpwrdqby1dl;
+ u32 mpwrdqby2dl;
+ u32 mpwrdqby3dl;
u32 mpdgctrl0;
u32 mpdgctrl1;
u32 mpdgdlst0;
@@ -157,4 +150,23 @@
u32 mpdccr;
};
+struct fsl_mmdc_info {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
+ u32 mdref;
+ u32 mdrwd;
+ u32 mdor;
+ u32 mdasp;
+ u32 mpodtctrl;
+ u32 mpzqhwctrl;
+ u32 mprddlctl;
+};
+
+void mmdc_init(const struct fsl_mmdc_info *);
+
#endif /* FSL_MMDC_H */
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index bffabc8..61c671d 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -24,7 +24,7 @@
#define sec_in16(a) in_be16(a)
#define sec_clrbits32 clrbits_be32
#define sec_setbits32 setbits_be32
-#else
+#elif defined(CONFIG_SYS_FSL_HAS_SEC)
#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
#endif
@@ -303,7 +303,7 @@
*/
int blob_dek(const u8 *src, u8 *dst, u8 len);
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
int sec_init_idx(uint8_t);
#endif
int sec_init(void);
diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h
index b6794ce..1f31f88 100644
--- a/include/fsl_sec_mon.h
+++ b/include/fsl_sec_mon.h
@@ -34,13 +34,16 @@
u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
};
-#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
-#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
-#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
+#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
+#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
+#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
+#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
+#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */
#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */
#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */
+#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */
#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */
/*
@@ -53,6 +56,7 @@
SEC_MON_SW_SV,
};
-int change_sec_mon_state(uint32_t initial_state, uint32_t final_state);
+/* Transition SEC_MON state */
+int set_sec_mon_state(u32 state);
#endif /* __FSL_SEC_MON_H */
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
index 2976a2c..d3a2813 100644
--- a/include/fsl_sfp.h
+++ b/include/fsl_sfp.h
@@ -78,9 +78,16 @@
u32 fsl_uid; /* 0xB0 FSL Unique ID */
};
#endif
+
#define ITS_MASK 0x00000004
#define ITS_BIT 2
-#define OSPR_KEY_REVOC_SHIFT 13
-#define OSPR_KEY_REVOC_MASK 0x0000e000
+
+#if defined(CONFIG_SYS_FSL_SFP_VER_3_4)
+#define OSPR_KEY_REVOC_SHIFT 9
+#define OSPR_KEY_REVOC_MASK 0x0000fe00
+#else
+#define OSPR_KEY_REVOC_SHIFT 13
+#define OSPR_KEY_REVOC_MASK 0x0000e000
+#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */
#endif
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index fc72fb9..73235b8 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -95,5 +95,6 @@
bool has_erratum_a005697(void);
bool has_erratum_a004477(void);
bool has_erratum_a008751(void);
+bool has_erratum_a010151(void);
#endif
#endif /*_ASM_FSL_USB_H_ */
diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h
index f698d4d..683c3f3 100644
--- a/include/fsl_wdog.h
+++ b/include/fsl_wdog.h
@@ -15,5 +15,6 @@
#define WCR_WDE 0x04
#define WCR_WDT 0x08
#define WCR_SRS 0x10
+#define WCR_WDA 0x20
#define SET_WCR_WT(x) (x << 8)
#define WCR_WT_MSK SET_WCR_WT(0xFF)
diff --git a/include/g_dnl.h b/include/g_dnl.h
index ba49f1f..bd29a9f 100644
--- a/include/g_dnl.h
+++ b/include/g_dnl.h
@@ -43,5 +43,6 @@
bool g_dnl_detach(void);
void g_dnl_trigger_detach(void);
void g_dnl_clear_detach(void);
+int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget);
#endif /* __G_DOWNLOAD_H_ */
diff --git a/include/hwconfig.h b/include/hwconfig.h
index def7ad0..d30421d 100644
--- a/include/hwconfig.h
+++ b/include/hwconfig.h
@@ -13,7 +13,7 @@
#define _HWCONFIG_H
#include <linux/types.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#ifdef CONFIG_HWCONFIG
diff --git a/include/image.h b/include/image.h
index 64da722..0537678 100644
--- a/include/image.h
+++ b/include/image.h
@@ -278,6 +278,9 @@
IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */
IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */
IH_TYPE_FPGA, /* FPGA Image */
+ IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */
+ IH_TYPE_TEE, /* Trusted Execution Environment OS Image */
+ IH_TYPE_FIRMWARE_IVT, /* Firmware Image with HABv4 IVT */
IH_TYPE_COUNT, /* Number of image types */
};
@@ -1048,7 +1051,9 @@
const char *keyname; /* Name of key to use */
void *fit; /* Pointer to FIT blob */
int node_offset; /* Offset of signature node */
- struct image_sig_algo *algo; /* Algorithm information */
+ const char *name; /* Algorithm name */
+ struct checksum_algo *checksum; /* Checksum algorithm information */
+ struct crypto_algo *crypto; /* Crypto algorithm information */
const void *fdt_blob; /* FDT containing public keys */
int required_keynode; /* Node offset of key to use: -1=any */
const char *require_keys; /* Value for 'required' property */
@@ -1069,18 +1074,19 @@
struct checksum_algo {
const char *name;
const int checksum_len;
- const int pad_len;
+ const int der_len;
+ const uint8_t *der_prefix;
#if IMAGE_ENABLE_SIGN
const EVP_MD *(*calculate_sign)(void);
#endif
int (*calculate)(const char *name,
const struct image_region region[],
int region_count, uint8_t *checksum);
- const uint8_t *rsa_padding;
};
-struct image_sig_algo {
+struct crypto_algo {
const char *name; /* Name of algorithm */
+ const int key_len;
/**
* sign() - calculate and return signature for given input data
@@ -1129,18 +1135,23 @@
int (*verify)(struct image_sign_info *info,
const struct image_region region[], int region_count,
uint8_t *sig, uint sig_len);
-
- /* pointer to checksum algorithm */
- struct checksum_algo *checksum;
};
/**
- * image_get_sig_algo() - Look up a signature algortihm
+ * image_get_checksum_algo() - Look up a checksum algorithm
*
- * @param name Name of algorithm
+ * @param full_name Name of algorithm in the form "checksum,crypto"
* @return pointer to algorithm information, or NULL if not found
*/
-struct image_sig_algo *image_get_sig_algo(const char *name);
+struct checksum_algo *image_get_checksum_algo(const char *full_name);
+
+/**
+ * image_get_crypto_algo() - Look up a cryptosystem algorithm
+ *
+ * @param full_name Name of algorithm in the form "checksum,crypto"
+ * @return pointer to algorithm information, or NULL if not found
+ */
+struct crypto_algo *image_get_crypto_algo(const char *full_name);
/**
* fit_image_verify_required_sigs() - Verify signatures marked as 'required'
@@ -1262,4 +1273,34 @@
void board_fit_image_post_process(void **p_image, size_t *p_size);
#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */
+/**
+ * Mapping of image types to function handlers to be invoked on the associated
+ * loaded images
+ *
+ * @type: Type of image, I.E. IH_TYPE_*
+ * @handler: Function to call on loaded image
+ */
+struct fit_loadable_tbl {
+ int type;
+ /**
+ * handler() - Process a loaded image
+ *
+ * @data: Pointer to start of loaded image data
+ * @size: Size of loaded image data
+ */
+ void (*handler)(ulong data, size_t size);
+};
+
+/*
+ * Define a FIT loadable image type handler
+ *
+ * _type is a valid uimage_type ID as defined in the "Image Type" enum above
+ * _handler is the handler function to call after this image type is loaded
+ */
+#define U_BOOT_FIT_LOADABLE_HANDLER(_type, _handler) \
+ ll_entry_declare(struct fit_loadable_tbl, _function, fit_loadable) = { \
+ .type = _type, \
+ .handler = _handler, \
+ }
+
#endif /* __IMAGE_H__ */
diff --git a/include/keyboard.h b/include/keyboard.h
index 6725e48..5cbd9f8 100644
--- a/include/keyboard.h
+++ b/include/keyboard.h
@@ -98,8 +98,8 @@
extern void pckbd_leds(unsigned char leds);
#endif /* !CONFIG_DM_KEYBOARD */
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || \
- defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
int ps2ser_check(void);
#endif
diff --git a/include/lcd_console.h b/include/lcd_console.h
index 2e0f56f..eac227f 100644
--- a/include/lcd_console.h
+++ b/include/lcd_console.h
@@ -5,9 +5,6 @@
*/
/* By default we scroll by a single line */
-#ifndef CONFIG_CONSOLE_SCROLL_LINES
-#define CONFIG_CONSOLE_SCROLL_LINES 1
-#endif
struct console_t {
short curr_col, curr_row;
diff --git a/include/libfdt.h b/include/libfdt.h
index b6a400a..e2bc2e0 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -61,7 +61,7 @@
#define FDT_ERR_NOTFOUND 1
/* FDT_ERR_NOTFOUND: The requested node or property does not exist */
#define FDT_ERR_EXISTS 2
- /* FDT_ERR_EXISTS: Attemped to create a node or property which
+ /* FDT_ERR_EXISTS: Attempted to create a node or property which
* already exists */
#define FDT_ERR_NOSPACE 3
/* FDT_ERR_NOSPACE: Operation needed to expand the device
@@ -79,8 +79,10 @@
* (e.g. missing a leading / for a function which requires an
* absolute path) */
#define FDT_ERR_BADPHANDLE 6
- /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle
- * value. phandle values of 0 and -1 are not permitted. */
+ /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle.
+ * This can be caused either by an invalid phandle property
+ * length, or the phandle value was either 0 or -1, which are
+ * not permitted. */
#define FDT_ERR_BADSTATE 7
/* FDT_ERR_BADSTATE: Function was passed an incomplete device
* tree created by the sequential-write functions, which is
@@ -121,12 +123,26 @@
/* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells
* or similar property with a bad format or value */
-#define FDT_ERR_TOODEEP 15
+#define FDT_ERR_BADVALUE 15
+ /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected
+ * value. For example: a property expected to contain a string list
+ * is not NUL-terminated within the length of its value. */
+
+#define FDT_ERR_BADOVERLAY 16
+ /* FDT_ERR_BADOVERLAY: The device tree overlay, while
+ * correctly structured, cannot be applied due to some
+ * unexpected or missing value, property or node. */
+
+#define FDT_ERR_NOPHANDLES 17
+ /* FDT_ERR_NOPHANDLES: The device tree doesn't have any
+ * phandle available anymore without causing an overflow */
+
+#define FDT_ERR_TOODEEP 18
/* FDT_ERR_TOODEEP: The depth of a node has exceeded the internal
* libfdt limit. This can happen if you have more than
* FDT_MAX_DEPTH nested nodes. */
-#define FDT_ERR_MAX 15
+#define FDT_ERR_MAX 18
/**********************************************************************/
/* Low-level functions (you probably don't need these) */
@@ -171,24 +187,27 @@
/**
* fdt_for_each_subnode - iterate over all subnodes of a parent
*
+ * @node: child node (int, lvalue)
+ * @fdt: FDT blob (const void *)
+ * @parent: parent node (int)
+ *
* This is actually a wrapper around a for loop and would be used like so:
*
- * fdt_for_each_subnode(fdt, node, parent) {
- * ...
- * use node
+ * fdt_for_each_subnode(node, fdt, parent) {
+ * Use node
* ...
* }
*
- * Note that this is implemented as a macro and node is used as iterator in
- * the loop. It should therefore be a locally allocated variable. The parent
- * variable on the other hand is never modified, so it can be constant or
- * even a literal.
+ * if ((node < 0) && (node != -FDT_ERR_NOT_FOUND)) {
+ * Error handling
+ * }
*
- * @fdt: FDT blob (const void *)
- * @node: child node (int)
- * @parent: parent node (int)
+ * Note that this is implemented as a macro and @node is used as
+ * iterator in the loop. The parent variable be constant or even a
+ * literal.
+ *
*/
-#define fdt_for_each_subnode(fdt, node, parent) \
+#define fdt_for_each_subnode(node, fdt, parent) \
for (node = fdt_first_subnode(fdt, parent); \
node >= 0; \
node = fdt_next_subnode(fdt, node))
@@ -213,7 +232,7 @@
#define __fdt_set_hdr(name) \
static inline void fdt_set_##name(void *fdt, uint32_t val) \
{ \
- struct fdt_header *fdth = (struct fdt_header*)fdt; \
+ struct fdt_header *fdth = (struct fdt_header *)fdt; \
fdth->name = cpu_to_fdt32(val); \
}
__fdt_set_hdr(magic);
@@ -288,11 +307,13 @@
* @fdt: pointer to the device tree blob
*
* fdt_get_max_phandle retrieves the highest phandle in the given
- * device tree
+ * device tree. This will ignore badly formatted phandles, or phandles
+ * with a value of 0 or -1.
*
* returns:
* the highest phandle on success
- * 0, if an error occurred
+ * 0, if no phandle was found in the device tree
+ * -1, if an error occurred
*/
uint32_t fdt_get_max_phandle(const void *fdt);
@@ -356,8 +377,9 @@
* returns:
* structure block offset of the requested subnode (>=0), on success
* -FDT_ERR_NOTFOUND, if the requested subnode does not exist
- * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
- * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE
+ * tag
+ * -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
@@ -366,13 +388,13 @@
int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
/**
- * fdt_path_offset_namelen - find a tree node based on substring
+ * fdt_path_offset_namelen - find a tree node by its full path
* @fdt: pointer to the device tree blob
* @path: full path of the node to locate
- * @namelen: number of characters of name to consider
+ * @namelen: number of characters of path to consider
*
- * Identical to fdt_path_offset(), but only examine the first
- * namelen characters of path for matching the node path.
+ * Identical to fdt_path_offset(), but only consider the first namelen
+ * characters of path as the path name.
*/
int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen);
@@ -389,7 +411,8 @@
* address).
*
* returns:
- * structure block offset of the node with the requested path (>=0), on success
+ * structure block offset of the node with the requested path (>=0), on
+ * success
* -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
* -FDT_ERR_NOTFOUND, if the requested node does not exist
* -FDT_ERR_BADMAGIC,
@@ -398,10 +421,7 @@
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings.
*/
-static inline int fdt_path_offset(const void *fdt, const char *path)
-{
- return fdt_path_offset_namelen(fdt, path, strlen(path));
-}
+int fdt_path_offset(const void *fdt, const char *path);
/**
* fdt_get_name - retrieve the name of a given node
@@ -416,10 +436,12 @@
*
* returns:
* pointer to the node's name, on success
- * If lenp is non-NULL, *lenp contains the length of that name (>=0)
+ * If lenp is non-NULL, *lenp contains the length of that name
+ * (>=0)
* NULL, on error
* if lenp is non-NULL *lenp contains an error code (<0):
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
+ * tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE, standard meanings
@@ -468,23 +490,26 @@
int fdt_next_property_offset(const void *fdt, int offset);
/**
- * fdt_for_each_property - iterate over all properties of a node
- * @property_offset: property offset (int)
+ * fdt_for_each_property_offset - iterate over all properties of a node
+ *
+ * @property_offset: property offset (int, lvalue)
* @fdt: FDT blob (const void *)
* @node: node offset (int)
*
* This is actually a wrapper around a for loop and would be used like so:
*
- * fdt_for_each_property(fdt, node, property) {
- * ...
- * use property
+ * fdt_for_each_property_offset(property, fdt, node) {
+ * Use property
* ...
* }
*
+ * if ((property < 0) && (property != -FDT_ERR_NOT_FOUND)) {
+ * Error handling
+ * }
+ *
* Note that this is implemented as a macro and property is used as
- * iterator in the loop. It should therefore be a locally allocated
- * variable. The node variable on the other hand is never modified, so
- * it can be constant or even a literal.
+ * iterator in the loop. The node variable can be constant or even a
+ * literal.
*/
#define fdt_for_each_property_offset(property, fdt, node) \
for (property = fdt_first_property_offset(fdt, node); \
@@ -527,8 +552,8 @@
* @namelen: number of characters of name to consider
* @lenp: pointer to an integer variable (will be overwritten) or NULL
*
- * Identical to fdt_get_property_namelen(), but only examine the first
- * namelen characters of name for matching the property name.
+ * Identical to fdt_get_property(), but only examine the first namelen
+ * characters of name for matching the property name.
*/
const struct fdt_property *fdt_get_property_namelen(const void *fdt,
int nodeoffset,
@@ -555,7 +580,8 @@
* NULL, on error
* if lenp is non-NULL, *lenp contains an error code (<0):
* -FDT_ERR_NOTFOUND, node does not have named property
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
+ * tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
@@ -647,7 +673,8 @@
* NULL, on error
* if lenp is non-NULL, *lenp contains an error code (<0):
* -FDT_ERR_NOTFOUND, node does not have named property
- * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
+ * tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
@@ -689,7 +716,7 @@
const char *name, int namelen);
/**
- * fdt_get_alias - retreive the path referenced by a given alias
+ * fdt_get_alias - retrieve the path referenced by a given alias
* @fdt: pointer to the device tree blob
* @name: name of the alias th look up
*
@@ -749,11 +776,11 @@
* structure from the start to nodeoffset.
*
* returns:
-
* structure block offset of the node at node offset's ancestor
* of depth supernodedepth (>=0), on success
* -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
-* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset
+ * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of
+ * nodeoffset
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
@@ -946,51 +973,66 @@
int fdt_stringlist_contains(const char *strlist, int listlen, const char *str);
/**
- * fdt_count_strings - count the number of strings in a string list
+ * fdt_stringlist_count - count the number of strings in a string list
* @fdt: pointer to the device tree blob
- * @node: offset of the node
+ * @nodeoffset: offset of a tree node
* @property: name of the property containing the string list
- * @return: the number of strings in the given property
+ * @return:
+ * the number of strings in the given property
+ * -FDT_ERR_BADVALUE if the property value is not NUL-terminated
+ * -FDT_ERR_NOTFOUND if the property does not exist
*/
-int fdt_count_strings(const void *fdt, int node, const char *property);
+int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property);
/**
- * fdt_find_string - find a string in a string list and return its index
+ * fdt_stringlist_search - find a string in a string list and return its index
* @fdt: pointer to the device tree blob
- * @node: offset of the node
+ * @nodeoffset: offset of a tree node
* @property: name of the property containing the string list
* @string: string to look up in the string list
- * @return: the index of the string or negative on error
+ *
+ * Note that it is possible for this function to succeed on property values
+ * that are not NUL-terminated. That's because the function will stop after
+ * finding the first occurrence of @string. This can for example happen with
+ * small-valued cell properties, such as #address-cells, when searching for
+ * the empty string.
+ *
+ * @return:
+ * the index of the string in the list of strings
+ * -FDT_ERR_BADVALUE if the property value is not NUL-terminated
+ * -FDT_ERR_NOTFOUND if the property does not exist or does not contain
+ * the given string
*/
-int fdt_find_string(const void *fdt, int node, const char *property,
- const char *string);
+int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,
+ const char *string);
/**
- * fdt_get_string_index() - obtain the string at a given index in a string list
+ * fdt_stringlist_get() - obtain the string at a given index in a string list
* @fdt: pointer to the device tree blob
- * @node: offset of the node
+ * @nodeoffset: offset of a tree node
* @property: name of the property containing the string list
* @index: index of the string to return
- * @output: return location for the string
- * @return: 0 if the string was found or a negative error code otherwise
- */
-int fdt_get_string_index(const void *fdt, int node, const char *property,
- int index, const char **output);
-
-/**
- * fdt_get_string() - obtain the first string in a string list
- * @fdt: pointer to the device tree blob
- * @node: offset of the node
- * @property: name of the property containing the string list
- * @output: return location for the string
- * @return: 0 if the string was found or a negative error code otherwise
+ * @lenp: return location for the string length or an error code on failure
*
- * This is a shortcut for:
+ * Note that this will successfully extract strings from properties with
+ * non-NUL-terminated values. For example on small-valued cell properties
+ * this function will return the empty string.
*
- * fdt_get_string_index(fdt, node, property, 0, output).
+ * If non-NULL, the length of the string (on success) or a negative error-code
+ * (on failure) will be stored in the integer pointer to by lenp.
+ *
+ * @return:
+ * A pointer to the string at the given index in the string list or NULL on
+ * failure. On success the length of the string will be stored in the memory
+ * location pointed to by the lenp parameter, if non-NULL. On failure one of
+ * the following negative error codes will be returned in the lenp parameter
+ * (if non-NULL):
+ * -FDT_ERR_BADVALUE if the property value is not NUL-terminated
+ * -FDT_ERR_NOTFOUND if the property does not exist
*/
-int fdt_get_string(const void *fdt, int node, const char *property,
- const char **output);
+const char *fdt_stringlist_get(const void *fdt, int nodeoffset,
+ const char *property, int index,
+ int *lenp);
/**********************************************************************/
/* Read-only functions (addressing related) */
@@ -1060,7 +1102,7 @@
* @nodeoffset: offset of the node whose property to change
* @name: name of the property to change
* @namelen: number of characters of name to consider
- * @index: index of the property to change in the array
+ * @idx: index of the property to change in the array
* @val: pointer to data to replace the property value with
* @len: length of the property value
*
@@ -1071,7 +1113,7 @@
*/
int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,
const char *name, int namelen,
- uint32_t index, const void *val,
+ uint32_t idx, const void *val,
int len);
/**
@@ -1700,9 +1742,11 @@
* change the offsets of some existing nodes.
* returns:
- * structure block offset of the created nodeequested subnode (>=0), on success
+ * structure block offset of the created nodeequested subnode (>=0), on
+ * success
* -FDT_ERR_NOTFOUND, if the requested subnode does not exist
- * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE
+ * tag
* -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
* the given name
* -FDT_ERR_NOSPACE, if there is insufficient free space in the
@@ -1756,8 +1800,9 @@
* -FDT_ERR_NOSPACE, there's not enough space in the base device tree
* -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or
* properties in the base DT
- * -FDT_ERR_BADPHANDLE, the phandles in the overlay do not have the right
- * magic
+ * -FDT_ERR_BADPHANDLE,
+ * -FDT_ERR_BADOVERLAY,
+ * -FDT_ERR_NOPHANDLES,
* -FDT_ERR_INTERNAL,
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_BADMAGIC,
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 7236b8d..533983f 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -15,7 +15,7 @@
extern struct p_current *current;
-#define ndelay(x) udelay(1)
+#define ndelay(x) udelay((x) < 1000 ? 1 : (x)/1000)
#define dev_dbg(dev, fmt, args...) \
debug(fmt, ##args)
@@ -151,8 +151,6 @@
typedef unsigned long blkcnt_t;
#endif
-#define ENOTSUPP 524 /* Operation is not supported */
-
/* module */
#define THIS_MODULE 0
#define try_module_get(...) 1
diff --git a/include/linux/err.h b/include/linux/err.h
index 5b3c8bc..22e5756 100644
--- a/include/linux/err.h
+++ b/include/linux/err.h
@@ -4,7 +4,7 @@
#include <linux/compiler.h>
#include <linux/compat.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
/*
@@ -36,6 +36,11 @@
return IS_ERR_VALUE((unsigned long)ptr);
}
+static inline bool IS_ERR_OR_NULL(const void *ptr)
+{
+ return !ptr || IS_ERR_VALUE((unsigned long)ptr);
+}
+
/**
* ERR_CAST - Explicitly cast an error-valued pointer to another pointer type
* @ptr: The pointer to cast.
diff --git a/include/linux/errno.h b/include/linux/errno.h
new file mode 100644
index 0000000..3d94207
--- /dev/null
+++ b/include/linux/errno.h
@@ -0,0 +1,168 @@
+#ifndef _LINUX_ERRNO_H
+#define _LINUX_ERRNO_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Argument list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+
+#define ENOSYS 38 /* Invalid system call number */
+
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+
+#define EDEADLOCK EDEADLK
+
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+#define ECANCELED 125 /* Operation Canceled */
+#define ENOKEY 126 /* Required key not available */
+#define EKEYEXPIRED 127 /* Key has expired */
+#define EKEYREVOKED 128 /* Key has been revoked */
+#define EKEYREJECTED 129 /* Key was rejected by service */
+
+/* for robust mutexes */
+#define EOWNERDEAD 130 /* Owner died */
+#define ENOTRECOVERABLE 131 /* State not recoverable */
+
+#define ERFKILL 132 /* Operation not possible due to RF-kill */
+
+#define EHWPOISON 133 /* Memory page has hardware error */
+
+#define ERESTARTSYS 512
+#define ERESTARTNOINTR 513
+#define ERESTARTNOHAND 514 /* restart if no handler.. */
+#define ENOIOCTLCMD 515 /* No ioctl command */
+#define ERESTART_RESTARTBLOCK 516 /* restart by calling sys_restart_syscall */
+#define EPROBE_DEFER 517 /* Driver requests probe retry */
+#define EOPENSTALE 518 /* open found a stale dentry */
+
+/* Defined for the NFSv3 protocol */
+#define EBADHANDLE 521 /* Illegal NFS file handle */
+#define ENOTSYNC 522 /* Update synchronization mismatch */
+#define EBADCOOKIE 523 /* Cookie is stale */
+#define ENOTSUPP 524 /* Operation is not supported */
+#define ETOOSMALL 525 /* Buffer or request is too small */
+#define ESERVERFAULT 526 /* An untranslatable error occurred */
+#define EBADTYPE 527 /* Type not supported by server */
+#define EJUKEBOX 528 /* Request initiated, but will not complete before timeout */
+#define EIOCBQUEUED 529 /* iocb queued, will get completion event */
+#define ERECALLCONFLICT 530 /* conflict with recalled state */
+
+#endif
diff --git a/include/linux/list.h b/include/linux/list.h
index b78851c..5b8d1df 100644
--- a/include/linux/list.h
+++ b/include/linux/list.h
@@ -338,6 +338,17 @@
list_entry((ptr)->next, type, member)
/**
+ * list_last_entry - get the last element from a list
+ * @ptr: the list head to take the element from.
+ * @type: the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define list_last_entry(ptr, type, member) \
+ list_entry((ptr)->prev, type, member)
+
+/**
* list_for_each - iterate over a list
* @pos: the &struct list_head to use as a loop cursor.
* @head: the head for your list.
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 779eea0..1fd17c3 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -20,7 +20,7 @@
#else
#include <linux/compat.h>
#include <mtd/mtd-abi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <div64.h>
#define MAX_MTD_DEVICES 32
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 87d72db..d55807b 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -16,12 +16,12 @@
#ifndef __LINUX_MTD_NAND_H
#define __LINUX_MTD_NAND_H
-#include "config.h"
+#include <config.h>
-#include "linux/compat.h"
-#include "linux/mtd/mtd.h"
-#include "linux/mtd/flashchip.h"
-#include "linux/mtd/bbm.h"
+#include <linux/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/flashchip.h>
+#include <linux/mtd/bbm.h>
struct mtd_info;
struct nand_flash_dev;
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 6d1e365..c1b23b2 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -180,10 +180,25 @@
/* Global USB2 PHY Configuration Register */
#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
+#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
+#define DWC3_GUSB2PHYCFG_PHYIF (1 << 3)
+
+/* Global USB2 PHY Configuration Mask */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
+
+/* Global USB2 PHY Configuration Offset */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
+
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
+ DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
+ DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
/* Global USB3 PIPE Control Register */
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
+#define DWC3_GUSB3PIPECTL_DISRXDETP3 (1 << 28)
#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
/* Global TX Fifo Size Register */
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 199f366..15cac40 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -20,6 +20,9 @@
#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
#define USB3_PWRCTL_CLK_CMD_SHIFT 14
#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
+#define USB3_ENABLE_BEAT_BURST 0xF
+#define USB3_ENABLE_BEAT_BURST_MASK 0xFF
+#define USB3_SET_BEAT_BURST_LIMIT 0xF00
/* USBOTGSS_WRAPPER definitions */
#define USBOTGSS_WRAPRESET BIT(17)
@@ -51,7 +54,7 @@
struct dwc3 *dwc3_reg;
};
-#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
+#if defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
index cb166e6..9de80d7 100644
--- a/include/linux/usb/xhci-omap.h
+++ b/include/linux/usb/xhci-omap.h
@@ -10,11 +10,11 @@
#ifndef _ASM_ARCH_XHCI_OMAP_H_
#define _ASM_ARCH_XHCI_OMAP_H_
-#ifdef CONFIG_DRA7XX
+#ifdef CONFIG_TARGET_DRA7XX_EVM
#define OMAP_XHCI_BASE 0x488d0000
#define OMAP_OCP1_SCP_BASE 0x4A081000
#define OMAP_OTG_WRAPPER_BASE 0x488c0000
-#elif defined CONFIG_AM57XX
+#elif defined CONFIG_TARGET_AM57XX_EVM
#define OMAP_XHCI_BASE 0x48890000
#define OMAP_OCP1_SCP_BASE 0x4A084c00
#define OMAP_OTG_WRAPPER_BASE 0x48880000
diff --git a/include/micrel.h b/include/micrel.h
index e6d145d..3e6b531 100644
--- a/include/micrel.h
+++ b/include/micrel.h
@@ -20,6 +20,9 @@
#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
+#define MII_KSZ9031_FLP_BURST_TX_LO 0x3
+#define MII_KSZ9031_FLP_BURST_TX_HI 0x4
+
/* Registers */
#define MMD_ACCESS_CONTROL 0xd
#define MMD_ACCESS_REG_DATA 0xe
diff --git a/include/miiphy.h b/include/miiphy.h
index 83141b4..fe8928a 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -48,6 +48,15 @@
struct mii_dev *mdio_alloc(void);
void mdio_free(struct mii_dev *bus);
int mdio_register(struct mii_dev *bus);
+
+/**
+ * mdio_register_seq - Register mdio bus with sequence number
+ * @bus: mii device structure
+ * @seq: sequence number
+ *
+ * Return: 0 if success, negative value if error
+ */
+int mdio_register_seq(struct mii_dev *bus, int seq);
int mdio_unregister(struct mii_dev *bus);
void mdio_list_devices(void);
diff --git a/include/mmc.h b/include/mmc.h
index aa6d5d1..1720955 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -11,6 +11,7 @@
#define _MMC_H_
#include <linux/list.h>
+#include <linux/sizes.h>
#include <linux/compiler.h>
#include <part.h>
@@ -102,6 +103,7 @@
#define SD_CMD_SWITCH_UHS18V 11
#define SD_CMD_APP_SET_BUS_WIDTH 6
+#define SD_CMD_APP_SD_STATUS 13
#define SD_CMD_ERASE_WR_BLK_START 32
#define SD_CMD_ERASE_WR_BLK_END 33
#define SD_CMD_APP_SEND_OP_COND 41
@@ -172,6 +174,7 @@
#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
+#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
#define EXT_CSD_WR_REL_PARAM 166 /* R */
#define EXT_CSD_WR_REL_SET 167 /* R/W */
#define EXT_CSD_RPMB_MULT 168 /* RO */
@@ -186,6 +189,7 @@
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
+#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
/*
* EXT_CSD field definitions
@@ -392,6 +396,12 @@
unsigned char part_type;
};
+struct sd_ssr {
+ unsigned int au; /* In sectors */
+ unsigned int erase_timeout; /* In milliseconds */
+ unsigned int erase_offset; /* In milliseconds */
+};
+
/*
* With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
* with mmc_get_mmc_dev().
@@ -426,6 +436,7 @@
uint write_bl_len;
uint erase_grp_size; /* in 512-byte sectors */
uint hc_wp_grp_size; /* in 512-byte sectors */
+ struct sd_ssr ssr; /* SD status register */
u64 capacity;
u64 capacity_user;
u64 capacity_boot;
@@ -504,6 +515,7 @@
* @return 0 if there is no MMC device, else the number of devices
*/
int get_mmc_num(void);
+int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
enum mmc_hwpart_conf_mode mode);
@@ -531,6 +543,10 @@
unsigned short cnt, unsigned char *key);
int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
unsigned short cnt, unsigned char *key);
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+int mmc_set_bkops_enable(struct mmc *mmc);
+#endif
+
/**
* Start device initialization and return immediately; it does not block on
* polling OCR (operation condition register) status. Then you should call
diff --git a/include/ns16550.h b/include/ns16550.h
index 1311f4c..7c97036 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -57,6 +57,7 @@
int reg_shift;
int clock;
int reg_offset;
+ u32 fcr;
};
struct udevice;
@@ -117,6 +118,9 @@
#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME 0x10
+
/*
* These are the definitions for the Modem Control Register
*/
diff --git a/include/os.h b/include/os.h
index 1782e50..049b248 100644
--- a/include/os.h
+++ b/include/os.h
@@ -215,9 +215,18 @@
int os_dirent_ls(const char *dirname, struct os_dirent_node **headp);
/**
+ * Free directory list
+ *
+ * This frees a linked list containing a directory listing.
+ *
+ * @param node Pointer to head of linked list
+ */
+void os_dirent_free(struct os_dirent_node *node);
+
+/**
* Get the name of a directory entry type
*
- * @param type Type to cehck
+ * @param type Type to check
* @return string containing the name of that type, or "???" if none/invalid
*/
const char *os_dirent_get_typename(enum os_dirent_t type);
diff --git a/include/palmas.h b/include/palmas.h
index cca3f9a..d676617 100644
--- a/include/palmas.h
+++ b/include/palmas.h
@@ -24,6 +24,16 @@
#define LDO1_CTRL 0x50
#define LDO1_VOLTAGE 0x51
+/* LDO1 control/voltage for LP873x */
+#define LP873X_LDO1_ADDR 0x60
+#define LP873X_LDO1_CTRL 0x9
+#define LP873X_LDO1_VOLTAGE 0xa
+#define LP873X_LDO_VOLT_3V0 0x19
+#define LP873X_LDO_VOLT_1V8 0xa
+#define LP873X_LDO_CTRL_EN (0x1 << 0)
+#define LP873X_LDO_CTRL_EN_PINCTRL (0x1 << 1)
+#define LP873X_LDO_CTRL_RDIS_EN (0x1 << 2)
+
/* LDO2 control/voltage */
#define LDO2_CTRL 0x52
#define LDO2_VOLTAGE 0x53
@@ -119,7 +129,8 @@
}
void palmas_init_settings(void);
-int palmas_mmc1_poweron_ldo(void);
+int palmas_mmc1_poweron_ldo(uint voltage);
+int lp873x_mmc1_poweron_ldo(uint voltage);
int twl603x_mmc1_set_ldo9(u8 vsel);
int twl603x_audio_power(u8 on);
int twl603x_enable_bb_charge(u8 bb_fields);
diff --git a/include/part.h b/include/part.h
index 226b5be..0979005 100644
--- a/include/part.h
+++ b/include/part.h
@@ -28,6 +28,11 @@
#define PART_TYPE_AMIGA 0x04
#define PART_TYPE_EFI 0x05
+/* maximum number of partition entries supported by search */
+#define DOS_ENTRY_NUMBERS 8
+#define ISO_ENTRY_NUMBERS 64
+#define MAC_ENTRY_NUMBERS 64
+#define AMIGA_ENTRY_NUMBERS 8
/*
* Type string for U-Boot bootable partitions
*/
@@ -146,6 +151,34 @@
int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
struct blk_desc **dev_desc,
disk_partition_t *info, int allow_whole_dev);
+
+/**
+ * part_get_info_by_name() - Search for a partition by name
+ * among all available registered partitions
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_name - the specified table entry name
+ * @param info - returns the disk partition info
+ *
+ * @return - '0' on match, '-1' on no match, otherwise error
+ */
+int part_get_info_by_name(struct blk_desc *dev_desc,
+ const char *name, disk_partition_t *info);
+
+/**
+ * part_set_generic_name() - create generic partition like hda1 or sdb2
+ *
+ * Helper function for partition tables, which don't hold partition names
+ * (DOS, ISO). Generates partition name out of the device type and partition
+ * number.
+ *
+ * @dev_desc: pointer to the block device
+ * @part_num: partition number for which the name is generated
+ * @name: buffer where the name is written
+ */
+void part_set_generic_name(const struct blk_desc *dev_desc,
+ int part_num, char *name);
+
extern const struct block_drvr block_drvr[];
#else
static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
@@ -189,6 +222,7 @@
struct part_driver {
const char *name;
int part_type;
+ const int max_entries; /* maximum number of entries to search */
/**
* get_info() - Get information about a partition
@@ -225,18 +259,6 @@
#include <part_efi.h>
/* disk/part_efi.c */
/**
- * part_get_info_efi_by_name() - Find the specified GPT partition table entry
- *
- * @param dev_desc - block device descriptor
- * @param gpt_name - the specified table entry name
- * @param info - returns the disk partition info
- *
- * @return - '0' on match, '-1' on no match, otherwise error
- */
-int part_get_info_efi_by_name(struct blk_desc *dev_desc,
- const char *name, disk_partition_t *info);
-
-/**
* write_gpt_table() - Write the GUID Partition Table to disk
*
* @param dev_desc - block device descriptor
@@ -343,4 +365,27 @@
gpt_header *gpt_head, gpt_entry **gpt_pte);
#endif
+#ifdef CONFIG_DOS_PARTITION
+/**
+ * is_valid_dos_buf() - Ensure that a DOS MBR image is valid
+ *
+ * @param buf - buffer which contains the MBR
+ *
+ * @return - '0' on success, otherwise error
+ */
+int is_valid_dos_buf(void *buf);
+
+/**
+ * write_mbr_partition() - write DOS MBR
+ *
+ * @param dev_desc - block device descriptor
+ * @param buf - buffer which contains the MBR
+ *
+ * @return - '0' on success, otherwise error
+ */
+int write_mbr_partition(struct blk_desc *dev_desc, void *buf);
+
+#endif
+
+
#endif /* _PART_H */
diff --git a/include/part_efi.h b/include/part_efi.h
index c8fc873..317c044 100644
--- a/include/part_efi.h
+++ b/include/part_efi.h
@@ -27,7 +27,6 @@
#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL
#define GPT_HEADER_REVISION_V1 0x00010000
#define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL
-#define GPT_ENTRY_NAME "gpt"
#define GPT_ENTRY_NUMBERS 128
#define GPT_ENTRY_SIZE 128
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 17a01a0..ab6aa58 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2599,13 +2599,14 @@
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60
-#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO 0x0f15
-#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD 0x0f16
+#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
+#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC 0x0f1c
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IDE 0x0f20
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IDE_ALT 0x0f21
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA 0x0f22
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT 0x0f23
+#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
#define PCI_DEVICE_ID_INTEL_82542 0x1000
diff --git a/include/power/lp873x.h b/include/power/lp873x.h
new file mode 100644
index 0000000..e0c0711
--- /dev/null
+++ b/include/power/lp873x.h
@@ -0,0 +1,19 @@
+#define LP8732 0x0
+#define LP8733 0x1
+
+#define LP873X_LDO_NUM 2
+#define LP873X_BUCK_NUM 2
+
+/* Drivers name */
+#define LP873X_LDO_DRIVER "lp873x_ldo"
+#define LP873X_BUCK_DRIVER "lp873x_buck"
+
+#define LP873X_BUCK_VOLT_MASK 0xFF
+#define LP873X_BUCK_VOLT_MAX_HEX 0xFF
+#define LP873X_BUCK_VOLT_MAX 3360000
+#define LP873X_BUCK_MODE_MASK 0x1
+
+#define LP873X_LDO_VOLT_MASK 0x1F
+#define LP873X_LDO_VOLT_MAX_HEX 0x19
+#define LP873X_LDO_VOLT_MAX 3300000
+#define LP873X_LDO_MODE_MASK 0x1
diff --git a/include/power/palmas.h b/include/power/palmas.h
new file mode 100644
index 0000000..bad5a35
--- /dev/null
+++ b/include/power/palmas.h
@@ -0,0 +1,25 @@
+#define PALMAS 0x0
+#define TPS659038 0x1
+#define TPS65917 0x2
+
+/* I2C device address for pmic palmas */
+#define PALMAS_I2C_ADDR (0x12 >> 1)
+#define PALMAS_LDO_NUM 11
+#define PALMAS_SMPS_NUM 8
+
+/* Drivers name */
+#define PALMAS_LDO_DRIVER "palmas_ldo"
+#define PALMAS_SMPS_DRIVER "palmas_smps"
+
+#define PALMAS_SMPS_VOLT_MASK 0x7F
+#define PALMAS_SMPS_RANGE_MASK 0x80
+#define PALMAS_SMPS_VOLT_MAX_HEX 0x7F
+#define PALMAS_SMPS_VOLT_MAX 3300000
+#define PALMAS_SMPS_MODE_MASK 0x3
+#define PALMAS_SMPS_STATUS_MASK 0x30
+
+#define PALMAS_LDO_VOLT_MASK 0x3F
+#define PALMAS_LDO_VOLT_MAX_HEX 0x3F
+#define PALMAS_LDO_VOLT_MAX 3300000
+#define PALMAS_LDO_MODE_MASK 0x1
+#define PALMAS_LDO_STATUS_MASK 0x10
diff --git a/include/power/pfuze3000_pmic.h b/include/power/pfuze3000_pmic.h
index e8b892b..7d66ba4 100644
--- a/include/power/pfuze3000_pmic.h
+++ b/include/power/pfuze3000_pmic.h
@@ -75,4 +75,9 @@
int power_pfuze3000_init(unsigned char bus);
+/* Voltage Configuration */
+#define PFUZE3000_SW1AB_SETP(x) ((x - 7000) / 250)
+#define PFUZE3000_SW3_SETP(x) ((x - 9000) / 500)
+#define PFUZE3000_VLDO_SETP(x) ((x - 8000) / 500)
+
#endif
diff --git a/include/power/regulator.h b/include/power/regulator.h
index 9bcd728..1a8e575 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -108,6 +108,7 @@
REGULATOR_TYPE_BUCK,
REGULATOR_TYPE_DVS,
REGULATOR_TYPE_FIXED,
+ REGULATOR_TYPE_GPIO,
REGULATOR_TYPE_OTHER,
};
@@ -152,6 +153,8 @@
* TODO(sjg@chromium.org): Consider putting the above two into @flags
* @flags: - flags value (see REGULATOR_FLAG_...)
* @name** - fdt regulator name - should be taken from the device tree
+ * ctrl_reg: - Control register offset used to enable/disable regulator
+ * volt_reg: - register offset for writing voltage vsel values
*
* Note:
* * - set automatically on device probe by the uclass's '.pre_probe' method.
@@ -171,6 +174,8 @@
bool boot_on;
const char *name;
int flags;
+ u8 ctrl_reg;
+ u8 volt_reg;
};
/* Regulator device operations */
@@ -256,6 +261,16 @@
int regulator_set_value(struct udevice *dev, int uV);
/**
+ * regulator_set_value_force: set the microvoltage value of a given regulator
+ * without any min-,max condition check
+ *
+ * @dev - pointer to the regulator device
+ * @uV - the output value to set [micro Volts]
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_value_force(struct udevice *dev, int uV);
+
+/**
* regulator_get_current: get microampere value of a given regulator
*
* @dev - pointer to the regulator device
diff --git a/include/power/rn5t567_pmic.h b/include/power/rn5t567_pmic.h
new file mode 100644
index 0000000..9ce601f
--- /dev/null
+++ b/include/power/rn5t567_pmic.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2016 Toradex AG
+ * Stefan Agner <stefan.agner@toradex.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __RN5T567_PMIC_H_
+#define __RN5T567_PMIC_H_
+
+/* RN5T567 registers */
+enum {
+ RN5T567_LSIVER = 0x00,
+ RN5T567_OTPVER = 0x01,
+ RN5T567_IODAC = 0x02,
+ RN5T567_VINDAC = 0x03,
+ RN5T567_OUT32KEN = 0x05,
+
+ RN5T567_CPUCNT = 0x06,
+
+ RN5T567_PSWR = 0x07,
+ RN5T567_PONHIS = 0x09,
+ RN5T567_POFFHIS = 0x0A,
+ RN5T567_WATCHDOG = 0x0B,
+ RN5T567_WATCHDOGCNT = 0x0C,
+ RN5T567_PWRFUNC = 0x0D,
+ RN5T567_SLPCNT = 0x0E,
+ RN5T567_REPCNT = 0x0F,
+ RN5T567_PWRONTIMSET = 0x10,
+ RN5T567_NOETIMSETCNT = 0x11,
+ RN5T567_PWRIREN = 0x12,
+ RN5T567_PWRIRQ = 0x13,
+ RN5T567_PWRMON = 0x14,
+ RN5T567_PWRIRSEL = 0x15,
+
+ RN5T567_DC1_SLOT = 0x16,
+ RN5T567_DC2_SLOT = 0x17,
+ RN5T567_DC3_SLOT = 0x18,
+ RN5T567_DC4_SLOT = 0x19,
+
+ RN5T567_LDO1_SLOT = 0x1B,
+ RN5T567_LDO2_SLOT = 0x1C,
+ RN5T567_LDO3_SLOT = 0x1D,
+ RN5T567_LDO4_SLOT = 0x1E,
+ RN5T567_LDO5_SLOT = 0x1F,
+
+ RN5T567_PSO0_SLOT = 0x25,
+ RN5T567_PSO1_SLOT = 0x26,
+ RN5T567_PSO2_SLOT = 0x27,
+ RN5T567_PSO3_SLOT = 0x28,
+
+ RN5T567_LDORTC1_SLOT = 0x2A,
+
+ RN5T567_DC1CTL = 0x2C,
+ RN5T567_DC1CTL2 = 0x2D,
+ RN5T567_DC2CTL = 0x2E,
+ RN5T567_DC2CTL2 = 0x2F,
+ RN5T567_DC3CTL = 0x30,
+ RN5T567_DC3CTL2 = 0x31,
+ RN5T567_DC4CTL = 0x32,
+ RN5T567_DC4CTL2 = 0x33,
+
+ RN5T567_DC1DAC = 0x36,
+ RN5T567_DC2DAC = 0x37,
+ RN5T567_DC3DAC = 0x38,
+ RN5T567_DC4DAC = 0x39,
+
+ RN5T567_DC1DAC_SLP = 0x3B,
+ RN5T567_DC2DAC_SLP = 0x3C,
+ RN5T567_DC3DAC_SLP = 0x3D,
+ RN5T567_DC4DAC_SLP = 0x3E,
+
+ RN5T567_DCIREN = 0x40,
+ RN5T567_DCIRQ = 0x41,
+ RN5T567_DCIRMON = 0x42,
+
+ RN5T567_LDOEN1 = 0x44,
+ RN5T567_LDOEN2 = 0x45,
+ RN5T567_LDODIS1 = 0x46,
+
+ RN5T567_LDO1DAC = 0x4C,
+ RN5T567_LDO2DAC = 0x4D,
+ RN5T567_LDO3DAC = 0x4E,
+ RN5T567_LDO4DAC = 0x4F,
+ RN5T567_LDO5DAC = 0x50,
+
+ RN5T567_LDORTC1DAC = 0x56,
+ RN5T567_LDORTC2DAC = 0x57,
+
+ RN5T567_LDO1DAC_SLP = 0x58,
+ RN5T567_LDO2DAC_SLP = 0x59,
+ RN5T567_LDO3DAC_SLP = 0x5A,
+ RN5T567_LDO4DAC_SLP = 0x5B,
+ RN5T567_LDO5DAC_SLP = 0x5C,
+
+ RN5T567_IOSEL = 0x90,
+ RN5T567_IOOUT = 0x91,
+ RN5T567_GPEDGE1 = 0x92,
+ RN5T567_EN_GPIR = 0x94,
+ RN5T567_IR_GPR = 0x95,
+ RN5T567_IR_GPF = 0x96,
+ RN5T567_MON_IOIN = 0x97,
+ RN5T567_GPLED_FUNC = 0x98,
+ RN5T567_INTPOL = 0x9C,
+ RN5T567_INTEN = 0x9D,
+ RN5T567_INTMON = 0x9E,
+
+ RN5T567_PREVINDAC = 0xB0,
+ RN5T567_OVTEMP = 0xBC,
+
+ RN5T567_NUM_OF_REGS = 0xBF,
+};
+
+#endif
diff --git a/include/reset-uclass.h b/include/reset-uclass.h
index 50adeca..38c716ff 100644
--- a/include/reset-uclass.h
+++ b/include/reset-uclass.h
@@ -11,6 +11,7 @@
#include <reset.h>
+struct fdtdec_phandle_args;
struct udevice;
/**
diff --git a/include/reset.h b/include/reset.h
index dc0900f..f45fcf8 100644
--- a/include/reset.h
+++ b/include/reset.h
@@ -7,6 +7,8 @@
#ifndef _RESET_H
#define _RESET_H
+#include <linux/errno.h>
+
/**
* A reset is a hardware signal indicating that a HW module (or IP block, or
* sometimes an entire off-CPU chip) reset all of its internal state to some
@@ -58,6 +60,7 @@
unsigned long id;
};
+#ifdef CONFIG_DM_RESET
/**
* reset_get_by_index - Get/request a reset signal by integer index.
*
@@ -132,4 +135,33 @@
*/
int reset_deassert(struct reset_ctl *reset_ctl);
+#else
+static inline int reset_get_by_index(struct udevice *dev, int index,
+ struct reset_ctl *reset_ctl)
+{
+ return -ENOTSUPP;
+}
+
+static inline int reset_get_by_name(struct udevice *dev, const char *name,
+ struct reset_ctl *reset_ctl)
+{
+ return -ENOTSUPP;
+}
+
+static inline int reset_free(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static inline int reset_assert(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static inline int reset_deassert(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+#endif
+
#endif
diff --git a/include/s_record.h b/include/s_record.h
index 6db7174..81245ba 100644
--- a/include/s_record.h
+++ b/include/s_record.h
@@ -29,7 +29,7 @@
* 2 data record with 24-bit address
* 3 data record with 32-bit address
* 4 symbol record (LSI extension)
- * 5 number of data records in preceeding block
+ * 5 number of data records in preceding block
* 6 unused
* 7 ending record for S3 records
* 8 ending record for S2 records
diff --git a/include/sata.h b/include/sata.h
index b35359a..d18cc9a 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -2,6 +2,7 @@
#define __SATA_H__
#include <part.h>
+#if !defined(CONFIG_DM_SCSI)
int init_sata(int dev);
int reset_sata(int dev);
int scan_sata(int dev);
@@ -15,5 +16,6 @@
int sata_port_status(int dev, int port);
extern struct blk_desc sata_dev_desc[];
+#endif
#endif
diff --git a/include/scsi.h b/include/scsi.h
index 7e37591..190dacd 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -166,17 +166,32 @@
void scsi_print_error(ccb *pccb);
int scsi_exec(ccb *pccb);
void scsi_bus_reset(void);
+#if !defined(CONFIG_DM_SCSI)
void scsi_low_level_init(int busdevfunc);
-
+#else
+void scsi_low_level_init(int busdevfunc, struct udevice *dev);
+#endif
/***************************************************************************
* functions residing inside cmd_scsi.c
*/
void scsi_init(void);
-void scsi_scan(int mode);
+int scsi_scan(int mode);
-/** @return the number of scsi disks */
-int scsi_get_disk_count(void);
+#if defined(CONFIG_DM_SCSI)
+/**
+ * struct scsi_platdata - stores information about SCSI controller
+ *
+ * @base: Controller base address
+ * @max_lun: Maximum number of logical units
+ * @max_id: Maximum number of target ids
+ */
+struct scsi_platdata {
+ unsigned long base;
+ unsigned long max_lun;
+ unsigned long max_id;
+};
+#endif
#define SCSI_IDENTIFY 0xC0 /* not used */
diff --git a/include/sdhci.h b/include/sdhci.h
index 6844c73..144570f 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -97,6 +97,7 @@
#define SDHCI_DIV_MASK 0xFF
#define SDHCI_DIV_MASK_LEN 8
#define SDHCI_DIV_HI_MASK 0x300
+#define SDHCI_PROG_CLOCK_MODE 0x0020
#define SDHCI_CLOCK_CARD_EN 0x0004
#define SDHCI_CLOCK_INT_STABLE 0x0002
#define SDHCI_CLOCK_INT_EN 0x0001
@@ -242,6 +243,7 @@
unsigned int quirks;
unsigned int host_caps;
unsigned int version;
+ unsigned int clk_mul; /* Clock Multiplier value */
unsigned int clock;
struct mmc *mmc;
const struct sdhci_ops *ops;
diff --git a/include/search.h b/include/search.h
index 343dbc3..402dfd8 100644
--- a/include/search.h
+++ b/include/search.h
@@ -12,8 +12,8 @@
* Copyright (C) 2010-2013 Wolfgang Denk <wd@denx.de>
*/
-#ifndef _SEARCH_H
-#define _SEARCH_H 1
+#ifndef _SEARCH_H_
+#define _SEARCH_H_
#include <stddef.h>
@@ -25,7 +25,7 @@
env_op_overwrite,
};
-/* Action which shall be performed in the call the hsearch. */
+/* Action which shall be performed in the call to hsearch. */
typedef enum {
FIND,
ENTER
@@ -45,7 +45,7 @@
/*
* Family of hash table handling functions. The functions also
* have reentrant counterparts ending with _r. The non-reentrant
- * functions all work on a signle internal hashing table.
+ * functions all work on a single internal hash table.
*/
/* Data type for reentrant functions. */
@@ -55,38 +55,38 @@
unsigned int filled;
/*
* Callback function which will check whether the given change for variable
- * "item" to "newval" may be applied or not, and possibly apply such change.
+ * "__item" to "newval" may be applied or not, and possibly apply such change.
* When (flag & H_FORCE) is set, it shall not print out any error message and
* shall force overwriting of write-once variables.
-.* Must return 0 for approval, 1 for denial.
+ * Must return 0 for approval, 1 for denial.
*/
int (*change_ok)(const ENTRY *__item, const char *newval, enum env_op,
int flag);
};
-/* Create a new hashing table which will at most contain NEL elements. */
+/* Create a new hash table which will contain at most "__nel" elements. */
extern int hcreate_r(size_t __nel, struct hsearch_data *__htab);
-/* Destroy current internal hashing table. */
+/* Destroy current internal hash table. */
extern void hdestroy_r(struct hsearch_data *__htab);
/*
- * Search for entry matching ITEM.key in internal hash table. If
+ * Search for entry matching __item.key in internal hash table. If
* ACTION is `FIND' return found entry or signal error by returning
* NULL. If ACTION is `ENTER' replace existing data (if any) with
- * ITEM.data.
+ * __item.data.
* */
extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval,
struct hsearch_data *__htab, int __flag);
/*
- * Search for an entry matching `MATCH'. Otherwise, Same semantics
+ * Search for an entry matching "__match". Otherwise, Same semantics
* as hsearch_r().
*/
extern int hmatch_r(const char *__match, int __last_idx, ENTRY ** __retval,
struct hsearch_data *__htab);
-/* Search and delete entry matching ITEM.key in internal hash table. */
+/* Search and delete entry matching "__key" in internal hash table. */
extern int hdelete_r(const char *__key, struct hsearch_data *__htab,
int __flag);
@@ -97,8 +97,6 @@
/*
* nvars: length of vars array
* vars: array of strings (variable names) to import (nvars == 0 means all)
- * do_apply: whether to call callback function to check the new argument,
- * and possibly apply changes (false means accept everything)
*/
extern int himport_r(struct hsearch_data *__htab,
const char *__env, size_t __size, const char __sep,
@@ -123,4 +121,4 @@
#define H_PROGRAMMATIC (1 << 9) /* indicate that an import is from setenv() */
#define H_ORIGIN_FLAGS (H_INTERACTIVE | H_PROGRAMMATIC)
-#endif /* search.h */
+#endif /* _SEARCH_H_ */
diff --git a/include/sed13806.h b/include/sed13806.h
deleted file mode 100644
index 1cb0b86..0000000
--- a/include/sed13806.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* Video support for Epson SED13806 chipset */
-
-
-#ifndef _SED13806_H_
-#define _SED13806_H_
-
-
-/* General definitions */
-#define FRAME_BUFFER_OFFSET 0x200000 /* Frame buffer offset */
-#define TOTAL_SPACE_SIZE 0x400000
-
-#define DEFAULT_VIDEO_MEMORY_SIZE 0x140000 /* Video Memory Size */
-
-#define HWCURSORSIZE 1024 /* Size of memory reserved
- for HW cursor*/
-
-/* Offset of chipset registers */
-#define BLT_CTRL0 (0x0100)
-#define BLT_CTRL1 (0x0101)
-#define BLT_ROP (0x0102)
-#define BLT_OP (0x0103)
-#define BLT_SRC_ADDR0 (0x0104)
-#define BLT_SRC_ADDR1 (0x0105)
-#define BLT_SRC_ADDR2 (0x0106)
-#define BLT_DST_ADDR0 (0x0108)
-#define BLT_DST_ADDR1 (0x0109)
-#define BLT_DST_ADDR2 (0x010A)
-#define BLT_MEM_OFF0 (0x010C)
-#define BLT_MEM_OFF1 (0x010D)
-#define BLT_WIDTH0 (0x0110)
-#define BLT_WIDTH1 (0x0111)
-#define BLT_HEIGHT0 (0x0112)
-#define BLT_HEIGHT1 (0x0113)
-#define BLT_BGCOLOR0 (0x0114)
-#define BLT_BGCOLOR1 (0x0115)
-#define BLT_FGCOLOR0 (0x0118)
-#define BLT_FGCOLOR1 (0x0119)
-
-#define BLT_REG (0x100000)
-
-/* Lookup table registers */
-#define REG_LUT_ADDR 0x1e2
-#define REG_LUT_DATA 0x1e4
-
-/* Cursor/Ink registers */
-#define LCD_CURSOR_CNTL (0x0070)
-#define LCD_CURSOR_START (0x0071)
-#define LCD_CURSOR_XL (0x0072)
-#define LCD_CURSOR_XM (0x0073)
-#define LCD_CURSOR_YL (0x0074)
-#define LCD_CURSOR_YM (0x0075)
-#define LCD_CURSOR_COL0_B (0x0076)
-#define LCD_CURSOR_COL0_G (0x0077)
-#define LCD_CURSOR_COL0_R (0x0078)
-#define LCD_CURSOR_COL1_B (0x007A)
-#define LCD_CURSOR_COL1_G (0x007B)
-#define LCD_CURSOR_COL1_R (0x007C)
-#define LCD_CURSOR_FIFO (0x007E)
-
-typedef struct
-{
- unsigned short Index;
- unsigned char Value;
-} S1D_REGS;
-
-
-/* Board specific functions */
-unsigned int board_video_init (void);
-void board_validate_screen (unsigned int base);
-const S1D_REGS *board_get_regs (void);
-int board_get_width (void);
-int board_get_height (void);
-
-#endif /* _SED13806_H_ */
diff --git a/include/smbios.h b/include/smbios.h
new file mode 100644
index 0000000..d582d4f
--- /dev/null
+++ b/include/smbios.h
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Adapted from coreboot src/include/smbios.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SMBIOS_H_
+#define _SMBIOS_H_
+
+/* SMBIOS spec version implemented */
+#define SMBIOS_MAJOR_VER 3
+#define SMBIOS_MINOR_VER 0
+
+/* SMBIOS structure types */
+enum {
+ SMBIOS_BIOS_INFORMATION = 0,
+ SMBIOS_SYSTEM_INFORMATION = 1,
+ SMBIOS_BOARD_INFORMATION = 2,
+ SMBIOS_SYSTEM_ENCLOSURE = 3,
+ SMBIOS_PROCESSOR_INFORMATION = 4,
+ SMBIOS_CACHE_INFORMATION = 7,
+ SMBIOS_SYSTEM_SLOTS = 9,
+ SMBIOS_PHYS_MEMORY_ARRAY = 16,
+ SMBIOS_MEMORY_DEVICE = 17,
+ SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19,
+ SMBIOS_SYSTEM_BOOT_INFORMATION = 32,
+ SMBIOS_END_OF_TABLE = 127
+};
+
+#define SMBIOS_INTERMEDIATE_OFFSET 16
+#define SMBIOS_STRUCT_EOS_BYTES 2
+
+struct __packed smbios_entry {
+ u8 anchor[4];
+ u8 checksum;
+ u8 length;
+ u8 major_ver;
+ u8 minor_ver;
+ u16 max_struct_size;
+ u8 entry_point_rev;
+ u8 formatted_area[5];
+ u8 intermediate_anchor[5];
+ u8 intermediate_checksum;
+ u16 struct_table_length;
+ u32 struct_table_address;
+ u16 struct_count;
+ u8 bcd_rev;
+};
+
+/* BIOS characteristics */
+#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7)
+#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11)
+#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16)
+
+#define BIOS_CHARACTERISTICS_EXT1_ACPI (1 << 0)
+#define BIOS_CHARACTERISTICS_EXT1_UEFI (1 << 3)
+#define BIOS_CHARACTERISTICS_EXT2_TARGET (1 << 2)
+
+struct __packed smbios_type0 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 vendor;
+ u8 bios_ver;
+ u16 bios_start_segment;
+ u8 bios_release_date;
+ u8 bios_rom_size;
+ u64 bios_characteristics;
+ u8 bios_characteristics_ext1;
+ u8 bios_characteristics_ext2;
+ u8 bios_major_release;
+ u8 bios_minor_release;
+ u8 ec_major_release;
+ u8 ec_minor_release;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_type1 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 manufacturer;
+ u8 product_name;
+ u8 version;
+ u8 serial_number;
+ u8 uuid[16];
+ u8 wakeup_type;
+ u8 sku_number;
+ u8 family;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+#define SMBIOS_BOARD_FEATURE_HOSTING (1 << 0)
+#define SMBIOS_BOARD_MOTHERBOARD 10
+
+struct __packed smbios_type2 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 manufacturer;
+ u8 product_name;
+ u8 version;
+ u8 serial_number;
+ u8 asset_tag_number;
+ u8 feature_flags;
+ u8 chassis_location;
+ u16 chassis_handle;
+ u8 board_type;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+#define SMBIOS_ENCLOSURE_DESKTOP 3
+#define SMBIOS_STATE_SAFE 3
+#define SMBIOS_SECURITY_NONE 3
+
+struct __packed smbios_type3 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 manufacturer;
+ u8 chassis_type;
+ u8 version;
+ u8 serial_number;
+ u8 asset_tag_number;
+ u8 bootup_state;
+ u8 power_supply_state;
+ u8 thermal_state;
+ u8 security_status;
+ u32 oem_defined;
+ u8 height;
+ u8 number_of_power_cords;
+ u8 element_count;
+ u8 element_record_length;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+#define SMBIOS_PROCESSOR_TYPE_CENTRAL 3
+#define SMBIOS_PROCESSOR_STATUS_ENABLED 1
+#define SMBIOS_PROCESSOR_UPGRADE_NONE 6
+
+#define SMBIOS_PROCESSOR_FAMILY_OTHER 1
+#define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 2
+
+struct __packed smbios_type4 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 socket_designation;
+ u8 processor_type;
+ u8 processor_family;
+ u8 processor_manufacturer;
+ u32 processor_id[2];
+ u8 processor_version;
+ u8 voltage;
+ u16 external_clock;
+ u16 max_speed;
+ u16 current_speed;
+ u8 status;
+ u8 processor_upgrade;
+ u16 l1_cache_handle;
+ u16 l2_cache_handle;
+ u16 l3_cache_handle;
+ u8 serial_number;
+ u8 asset_tag;
+ u8 part_number;
+ u8 core_count;
+ u8 core_enabled;
+ u8 thread_count;
+ u16 processor_characteristics;
+ u16 processor_family2;
+ u16 core_count2;
+ u16 core_enabled2;
+ u16 thread_count2;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_type32 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 reserved[6];
+ u8 boot_status;
+ u8 eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_type127 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_header {
+ u8 type;
+ u8 length;
+ u16 handle;
+};
+
+/**
+ * fill_smbios_header() - Fill the header of an SMBIOS table
+ *
+ * This fills the header of an SMBIOS table structure.
+ *
+ * @table: start address of the structure
+ * @type: the type of structure
+ * @length: the length of the formatted area of the structure
+ * @handle: the structure's handle, a unique 16-bit number
+ */
+static inline void fill_smbios_header(void *table, int type,
+ int length, int handle)
+{
+ struct smbios_header *header = table;
+
+ header->type = type;
+ header->length = length - SMBIOS_STRUCT_EOS_BYTES;
+ header->handle = handle;
+}
+
+/**
+ * Function prototype to write a specific type of SMBIOS structure
+ *
+ * @addr: start address to write the structure
+ * @handle: the structure's handle, a unique 16-bit number
+ * @return: size of the structure
+ */
+typedef int (*smbios_write_type)(uintptr_t *addr, int handle);
+
+/**
+ * write_smbios_table() - Write SMBIOS table
+ *
+ * This writes SMBIOS table at a given address.
+ *
+ * @addr: start address to write SMBIOS table
+ * @return: end address of SMBIOS table
+ */
+uintptr_t write_smbios_table(uintptr_t addr);
+
+#endif /* _SMBIOS_H_ */
diff --git a/include/spi.h b/include/spi.h
index ca96fa4..deb65ef 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -26,16 +26,9 @@
#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */
#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */
#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */
-
-/* SPI mode_rx flags */
-#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */
-#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */
-#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */
-#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */
-
-/* SPI bus connection options - see enum spi_dual_flash */
-#define SPI_CONN_DUAL_SHARED (1 << 0)
-#define SPI_CONN_DUAL_SEPARATED (1 << 1)
+#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */
+#define SPI_RX_DUAL BIT(12) /* receive with 2 wires */
+#define SPI_RX_QUAD BIT(13) /* receive with 4 wires */
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -61,13 +54,11 @@
* @cs: Chip select number (0..n-1)
* @max_hz: Maximum bus speed that this slave can tolerate
* @mode: SPI mode to use for this device (see SPI mode flags)
- * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
*/
struct dm_spi_slave_platdata {
unsigned int cs;
uint max_hz;
uint mode;
- u8 mode_rx;
};
#endif /* CONFIG_DM_SPI */
@@ -94,12 +85,10 @@
* bus (bus->seq) so does not need to be stored
* @cs: ID of the chip select connected to the slave.
* @mode: SPI mode to use for this slave (see SPI mode flags)
- * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
* @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes.
* @memory_map: Address of read-only SPI flash access.
- * @option: Varies SPI bus options - separate, shared bus.
* @flags: Indication of SPI flags.
*/
struct spi_slave {
@@ -112,7 +101,6 @@
unsigned int cs;
#endif
uint mode;
- u8 mode_rx;
unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
@@ -124,7 +112,6 @@
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
#define SPI_XFER_MMAP BIT(2) /* Memory Mapped start */
#define SPI_XFER_MMAP_END BIT(3) /* Memory Mapped End */
-#define SPI_XFER_U_PAGE BIT(4)
};
/**
diff --git a/include/spi_flash.h b/include/spi_flash.h
index d0ce9e7..be2fe3f 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -239,7 +239,4 @@
return flash->flash_unlock(flash, ofs, len);
}
-void spi_boot(void) __noreturn;
-void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
-
#endif /* _SPI_FLASH_H_ */
diff --git a/include/spl.h b/include/spl.h
index 8afa085..6e746b2 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -49,6 +49,7 @@
/**
* spl_load_simple_fit() - Loads a fit image from a device.
+ * @spl_image: Image description to set up
* @info: Structure containing the information required to load data.
* @sector: Sector number where FIT image is located in the device
* @fdt: Pointer to the copied FIT header.
@@ -57,66 +58,159 @@
* specified load address and copies the dtb to end of u-boot image.
* Returns 0 on success.
*/
-int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fdt);
+int spl_load_simple_fit(struct spl_image_info *spl_image,
+ struct spl_load_info *info, ulong sector, void *fdt);
#define SPL_COPY_PAYLOAD_ONLY 1
-extern struct spl_image_info spl_image;
-
/* SPL common functions */
void preloader_console_init(void);
u32 spl_boot_device(void);
u32 spl_boot_mode(const u32 boot_device);
-void spl_set_header_raw_uboot(void);
-int spl_parse_image_header(const struct image_header *header);
+
+/**
+ * spl_set_header_raw_uboot() - Set up a standard SPL image structure
+ *
+ * This sets up the given spl_image which the standard values obtained from
+ * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START,
+ * CONFIG_SYS_TEXT_BASE.
+ *
+ * @spl_image: Image description to set up
+ */
+void spl_set_header_raw_uboot(struct spl_image_info *spl_image);
+
+/**
+ * spl_parse_image_header() - parse the image header and set up info
+ *
+ * This parses the legacy image header information at @header and sets up
+ * @spl_image according to what is found. If no image header is found, then
+ * a raw image or bootz is assumed. If CONFIG_SPL_PANIC_ON_RAW_IMAGE is
+ * enabled, then this causes a panic. If CONFIG_SPL_ABORT_ON_RAW_IMAGE is
+ * enabled then U-Boot gives up. Otherwise U-Boot sets up the image using
+ * spl_set_header_raw_uboot(), or possibly the bootz header.
+ *
+ * @spl_image: Image description to set up
+ * @header image header to parse
+ * @return 0 if a header was correctly parsed, -ve on error
+ */
+int spl_parse_image_header(struct spl_image_info *spl_image,
+ const struct image_header *header);
+
void spl_board_prepare_for_linux(void);
void spl_board_prepare_for_boot(void);
int spl_board_ubi_load_image(u32 boot_device);
-void __noreturn jump_to_image_linux(void *arg);
+
+/**
+ * jump_to_image_linux() - Jump to a Linux kernel from SPL
+ *
+ * This jumps into a Linux kernel using the information in @spl_image.
+ *
+ * @spl_image: Image description to set up
+ * @arg: Argument to pass to Linux (typically a device tree pointer)
+ */
+void __noreturn jump_to_image_linux(struct spl_image_info *spl_image,
+ void *arg);
+
+/**
+ * spl_start_uboot() - Check if SPL should start the kernel or U-Boot
+ *
+ * This is called by the various SPL loaders to determine whether the board
+ * wants to load the kernel or U-Boot. This function should be provided by
+ * the board.
+ *
+ * @return 0 if SPL should start the kernel, 1 if U-Boot must be started
+ */
int spl_start_uboot(void);
+
+/**
+ * spl_display_print() - Display a board-specific message in SPL
+ *
+ * If CONFIG_SPL_DISPLAY_PRINT is enabled, U-Boot will call this function
+ * immediately after displaying the SPL console banner ("U-Boot SPL ...").
+ * This function should be provided by the board.
+ */
void spl_display_print(void);
-/* NAND SPL functions */
-int spl_nand_load_image(void);
+/**
+ * struct spl_boot_device - Describes a boot device used by SPL
+ *
+ * @boot_device: A number indicating the BOOT_DEVICE type. There are various
+ * BOOT_DEVICE... #defines and enums in U-Boot and they are not consistently
+ * numbered.
+ * @boot_device_name: Named boot device, or NULL if none.
+ *
+ * Note: Additional fields can be added here, bearing in mind that SPL is
+ * size-sensitive and common fields will be present on all boards. This
+ * struct can also be used to return additional information about the load
+ * process if that becomes useful.
+ */
+struct spl_boot_device {
+ uint boot_device;
+ const char *boot_device_name;
+};
-/* OneNAND SPL functions */
-int spl_onenand_load_image(void);
+/**
+ * Holds information about a way of loading an SPL image
+ *
+ * @name: User-friendly name for this method (e.g. "MMC")
+ * @boot_device: Boot device that this loader supports
+ * @load_image: Function to call to load image
+ */
+struct spl_image_loader {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ const char *name;
+#endif
+ uint boot_device;
+ /**
+ * load_image() - Load an SPL image
+ *
+ * @spl_image: place to put image information
+ * @bootdev: describes the boot device to load from
+ */
+ int (*load_image)(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev);
+};
-/* NOR SPL functions */
-int spl_nor_load_image(void);
+/* Declare an SPL image loader */
+#define SPL_LOAD_IMAGE(__name) \
+ ll_entry_declare(struct spl_image_loader, __name, spl_image_loader)
-/* UBI SPL functions */
-int spl_ubi_load_image(u32 boot_device);
-
-/* MMC SPL functions */
-int spl_mmc_load_image(u32 boot_device);
-
-/* YMODEM SPL functions */
-int spl_ymodem_load_image(void);
-
-/* SPI SPL functions */
-int spl_spi_load_image(void);
-
-/* Ethernet SPL functions */
-int spl_net_load_image(const char *device);
-
-/* USB SPL functions */
-int spl_usb_load_image(void);
-
-/* SATA SPL functions */
-int spl_sata_load_image(void);
+/*
+ * _priority is the priority of this method, 0 meaning it will be the top
+ * choice for this device, 9 meaning it is the bottom choice.
+ * _boot_device is the BOOT_DEVICE_... value
+ * _method is the load_image function to call
+ */
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+#define SPL_LOAD_IMAGE_METHOD(_name, _priority, _boot_device, _method) \
+ SPL_LOAD_IMAGE(_method ## _priority ## _boot_device) = { \
+ .name = _name, \
+ .boot_device = _boot_device, \
+ .load_image = _method, \
+ }
+#else
+#define SPL_LOAD_IMAGE_METHOD(_name, _priority, _boot_device, _method) \
+ SPL_LOAD_IMAGE(_method ## _priority ## _boot_device) = { \
+ .boot_device = _boot_device, \
+ .load_image = _method, \
+ }
+#endif
/* SPL FAT image functions */
-int spl_load_image_fat(struct blk_desc *block_dev, int partition,
+int spl_load_image_fat(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition,
const char *filename);
-int spl_load_image_fat_os(struct blk_desc *block_dev, int partition);
+int spl_load_image_fat_os(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition);
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image);
/* SPL EXT image functions */
-int spl_load_image_ext(struct blk_desc *block_dev, int partition,
+int spl_load_image_ext(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition,
const char *filename);
-int spl_load_image_ext_os(struct blk_desc *block_dev, int partition);
+int spl_load_image_ext_os(struct spl_image_info *spl_image,
+ struct blk_desc *block_dev, int partition);
/**
* spl_init() - Set up device tree and driver model in SPL if enabled
@@ -144,4 +238,16 @@
*/
bool spl_was_boot_source(void);
+/**
+ * spl_dfu_cmd- run dfu command with chosen mmc device interface
+ * @param usb_index - usb controller number
+ * @param mmc_dev - mmc device nubmer
+ *
+ * @return 0 on success, otherwise error code
+ */
+int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr);
+
+int spl_mmc_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev);
+
#endif
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index 13f76be..e4fc8b1 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -100,7 +100,7 @@
int stdio_init(void);
void stdio_print_current_devices(void);
-#ifdef CONFIG_SYS_STDIO_DEREGISTER
+#if CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER)
int stdio_deregister(const char *devname, int force);
int stdio_deregister_dev(struct stdio_dev *dev, int force);
#endif
diff --git a/include/tables_csum.h b/include/tables_csum.h
new file mode 100644
index 0000000..27d147b
--- /dev/null
+++ b/include/tables_csum.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TABLES_CSUM_H_
+#define _TABLES_CSUM_H_
+
+static inline u8 table_compute_checksum(void *v, int len)
+{
+ u8 *bytes = v;
+ u8 checksum = 0;
+ int i;
+
+ for (i = 0; i < len; i++)
+ checksum -= bytes[i];
+
+ return checksum;
+}
+
+#endif
diff --git a/include/tee/optee.h b/include/tee/optee.h
new file mode 100644
index 0000000..9ab0d08
--- /dev/null
+++ b/include/tee/optee.h
@@ -0,0 +1,30 @@
+/*
+ * OP-TEE related definitions
+ *
+ * (C) Copyright 2016 Linaro Limited
+ * Andrew F. Davis <andrew.davis@linaro.org>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#ifndef _OPTEE_H
+#define _OPTEE_H
+
+#define OPTEE_MAGIC 0x4554504f
+#define OPTEE_VERSION 1
+#define OPTEE_ARCH_ARM32 0
+#define OPTEE_ARCH_ARM64 1
+
+struct optee_header {
+ uint32_t magic;
+ uint8_t version;
+ uint8_t arch;
+ uint16_t flags;
+ uint32_t init_size;
+ uint32_t init_load_addr_hi;
+ uint32_t init_load_addr_lo;
+ uint32_t init_mem_usage;
+ uint32_t paged_size;
+};
+
+#endif /* _OPTEE_H */
diff --git a/include/u-boot/rsa-checksum.h b/include/u-boot/rsa-checksum.h
index 3c69d85..c240720 100644
--- a/include/u-boot/rsa-checksum.h
+++ b/include/u-boot/rsa-checksum.h
@@ -12,10 +12,6 @@
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
-extern const uint8_t padding_sha256_rsa4096[];
-extern const uint8_t padding_sha256_rsa2048[];
-extern const uint8_t padding_sha1_rsa2048[];
-
/**
* hash_calculate() - Calculate hash over the data
*
diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h
index b0d9ce9..2634a29 100644
--- a/include/u-boot/sha1.h
+++ b/include/u-boot/sha1.h
@@ -21,6 +21,9 @@
#define SHA1_SUM_POS -0x20
#define SHA1_SUM_LEN 20
+#define SHA1_DER_LEN 15
+
+extern const uint8_t sha1_der_prefix[];
/**
* \brief SHA-1 context structure
diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h
index beadab3..9aa1251 100644
--- a/include/u-boot/sha256.h
+++ b/include/u-boot/sha256.h
@@ -2,6 +2,9 @@
#define _SHA256_H
#define SHA256_SUM_LEN 32
+#define SHA256_DER_LEN 19
+
+extern const uint8_t sha256_der_prefix[];
/* Reset watchdog each time we process this many bytes */
#define CHUNKSZ_SHA256 (64 * 1024)
diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h
index 324fe72..80acbcb 100644
--- a/include/ubi_uboot.h
+++ b/include/ubi_uboot.h
@@ -32,12 +32,9 @@
#include <onenand_uboot.h>
#endif
-#include <asm/errno.h>
+#include <linux/errno.h>
/* configurable */
-#if !defined(CONFIG_MTD_UBI_WL_THRESHOLD)
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#endif
#define CONFIG_MTD_UBI_BEB_RESERVE 1
/* debug options (Linux: drivers/mtd/ubi/Kconfig.debug) */
@@ -59,10 +56,6 @@
*/
#define CONFIG_MTD_UBI_MODULE
-#if !defined(CONFIG_MTD_UBI_BEB_LIMIT)
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#endif
-
/* build.c */
#define get_device(...)
#define put_device(...)
diff --git a/include/usb/lin_gadget_compat.h b/include/usb/lin_gadget_compat.h
index 29fb166..4a01585 100644
--- a/include/usb/lin_gadget_compat.h
+++ b/include/usb/lin_gadget_compat.h
@@ -13,8 +13,6 @@
#include <linux/compat.h>
/* common */
-#define ENOTSUPP 524 /* Operation is not supported */
-
#define BITS_PER_BYTE 8
#define BITS_TO_LONGS(nr) \
DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
diff --git a/include/vbe.h b/include/vbe.h
index 164ccae..16bb096 100644
--- a/include/vbe.h
+++ b/include/vbe.h
@@ -106,5 +106,11 @@
struct graphic_device;
int vbe_get_video_info(struct graphic_device *gdev);
+struct video_priv;
+struct video_uc_platdata;
+int vbe_setup_video_priv(struct vesa_mode_info *vesa,
+ struct video_priv *uc_priv,
+ struct video_uc_platdata *plat);
+int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void));
#endif
diff --git a/include/version.h b/include/version.h
index 777e9f6..0494309 100644
--- a/include/version.h
+++ b/include/version.h
@@ -14,10 +14,6 @@
#include "generated/version_autogenerated.h"
#endif
-#ifndef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING ""
-#endif
-
#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
diff --git a/include/video.h b/include/video.h
index 0d5bd21..5b4e78b 100644
--- a/include/video.h
+++ b/include/video.h
@@ -245,6 +245,17 @@
unsigned int max_hz, unsigned int spi_mode);
#endif
+/*
+ * video_get_info_str() - obtain a board string: type, speed, etc.
+ *
+ * This is called if CONFIG_CONSOLE_EXTRA_INFO is enabled.
+ *
+ * line_number: location to place info string beside logo
+ * info: buffer for info string (empty if nothing to display on this
+ * line)
+ */
+void video_get_info_str(int line_number, char *info);
+
#endif /* CONFIG_DM_VIDEO */
#endif
diff --git a/include/video_fb.h b/include/video_fb.h
index 55ec24d..b008853 100644
--- a/include/video_fb.h
+++ b/include/video_fb.h
@@ -18,14 +18,6 @@
#ifndef _VIDEO_FB_H_
#define _VIDEO_FB_H_
-#if defined(CONFIG_SYS_CONSOLE_FG_COL) && defined(CONFIG_SYS_CONSOLE_BG_COL)
-#define CONSOLE_BG_COL CONFIG_SYS_CONSOLE_BG_COL
-#define CONSOLE_FG_COL CONFIG_SYS_CONSOLE_FG_COL
-#else
-#define CONSOLE_BG_COL 0x00
-#define CONSOLE_FG_COL 0xa0
-#endif
-
/*
* Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
*/
@@ -96,9 +88,5 @@
unsigned char g, /* green */
unsigned char b /* blue */
);
-#ifdef CONFIG_VIDEO_HW_CURSOR
-void video_set_hw_cursor(int x, int y); /* x y in pixel */
-void video_init_hw_cursor(int font_width, int font_height);
-#endif
#endif /*_VIDEO_FB_H_ */
diff --git a/include/vsprintf.h b/include/vsprintf.h
index 60e91d1..e38076d 100644
--- a/include/vsprintf.h
+++ b/include/vsprintf.h
@@ -72,7 +72,7 @@
* panic() - Print a message and reset/hang
*
* Prints a message on the console(s) and then resets. If CONFIG_PANIC_HANG is
- * defined, then it will hang instead of reseting.
+ * defined, then it will hang instead of resetting.
*
* @param fmt: printf() format string for message, which should not include
* \n, followed by arguments
@@ -84,7 +84,7 @@
* panic_str() - Print a message and reset/hang
*
* Prints a message on the console(s) and then resets. If CONFIG_PANIC_HANG is
- * defined, then it will hang instead of reseting.
+ * defined, then it will hang instead of resetting.
*
* This function can be used instead of panic() when your board does not
* already use printf(), * to keep code size small.
diff --git a/include/wait_bit.h b/include/wait_bit.h
index 061a2db..066e30c 100644
--- a/include/wait_bit.h
+++ b/include/wait_bit.h
@@ -11,7 +11,7 @@
#include <common.h>
#include <console.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
/**
diff --git a/include/xilinx.h b/include/xilinx.h
index aebcb3b..d2a2ea7 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -21,6 +21,7 @@
master_selectmap, /* master SelectMap (virtex2) */
slave_selectmap, /* slave SelectMap (virtex2) */
devcfg, /* devcfg interface (zynq) */
+ csu_dma, /* csu_dma interface (zynqmp) */
max_xilinx_iface_type /* insert all new types before this */
} xilinx_iface; /* end, typedef xilinx_iface */
@@ -31,6 +32,7 @@
xilinx_virtex2, /* Virtex2 Family */
xilinx_spartan3, /* Spartan-III Family */
xilinx_zynq, /* Zynq Family */
+ xilinx_zynqmp, /* ZynqMP Family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */
diff --git a/include/zynqmppl.h b/include/zynqmppl.h
new file mode 100644
index 0000000..fb5200e
--- /dev/null
+++ b/include/zynqmppl.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2015 Xilinx, Inc,
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ZYNQMPPL_H_
+#define _ZYNQMPPL_H_
+
+#include <xilinx.h>
+
+#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018
+#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016
+#define ZYNQMP_FPGA_OP_INIT (1 << 0)
+#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
+#define ZYNQMP_FPGA_OP_DONE (1 << 2)
+
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
+ ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
+#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
+#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
+
+extern struct xilinx_fpga_op zynqmp_op;
+
+#define XILINX_ZYNQMP_DESC \
+{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
+
+#endif /* _ZYNQMPPL_H_ */
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 1d37a51..5a34a17 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -19,7 +19,10 @@
# define FPGA_ZYNQPL_OPS NULL
#endif
+#define XILINX_ZYNQ_7007S 0x3
#define XILINX_ZYNQ_7010 0x2
+#define XILINX_ZYNQ_7012S 0x1c
+#define XILINX_ZYNQ_7014S 0x8
#define XILINX_ZYNQ_7015 0x1b
#define XILINX_ZYNQ_7020 0x7
#define XILINX_ZYNQ_7030 0xc
@@ -28,7 +31,10 @@
#define XILINX_ZYNQ_7100 0x16
/* Device Image Sizes */
+#define XILINX_XC7Z007S_SIZE 16669920/8
#define XILINX_XC7Z010_SIZE 16669920/8
+#define XILINX_XC7Z012S_SIZE 28085344/8
+#define XILINX_XC7Z014S_SIZE 32364512/8
#define XILINX_XC7Z015_SIZE 28085344/8
#define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8
@@ -37,10 +43,22 @@
#define XILINX_XC7Z100_SIZE 139330784/8
/* Descriptor Macros */
+#define XILINX_XC7Z007S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z007s" }
+
#define XILINX_XC7Z010_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z010" }
+#define XILINX_XC7Z012S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z012s" }
+
+#define XILINX_XC7Z014S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z014s" }
+
#define XILINX_XC7Z015_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z015" }
diff --git a/lib/Kconfig b/lib/Kconfig
index 16ff01a..b16062f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -154,6 +154,48 @@
particular compatible nodes. The library operates on a flattened
version of the device tree.
+config FDT_FIXUP_PARTITIONS
+ bool "overwrite MTD partitions in DTS through defined in 'mtdparts'"
+ depends on OF_LIBFDT
+ default n
+ help
+ Allow overwriting defined partitions in the device tree blob
+ using partition info defined in the 'mtdparts' environment
+ variable.
+
+menu "System tables"
+ depends on (!EFI && !SYS_COREBOOT) || (ARM && EFI_LOADER)
+
+config GENERATE_SMBIOS_TABLE
+ bool "Generate an SMBIOS (System Management BIOS) table"
+ default y
+ depends on X86 || EFI_LOADER
+ help
+ The System Management BIOS (SMBIOS) specification addresses how
+ motherboard and system vendors present management information about
+ their products in a standard format by extending the BIOS interface
+ on Intel architecture systems.
+
+ Check http://www.dmtf.org/standards/smbios for details.
+
+config SMBIOS_MANUFACTURER
+ string "SMBIOS Manufacturer"
+ depends on GENERATE_SMBIOS_TABLE
+ default SYS_VENDOR
+ help
+ The board manufacturer to store in SMBIOS structures.
+ Change this to override the default one (CONFIG_SYS_VENDOR).
+
+config SMBIOS_PRODUCT_NAME
+ string "SMBIOS Product Name"
+ depends on GENERATE_SMBIOS_TABLE
+ default SYS_BOARD
+ help
+ The product name to store in SMBIOS structures.
+ Change this to override the default one (CONFIG_SYS_BOARD).
+
+endmenu
+
source lib/efi/Kconfig
source lib/efi_loader/Kconfig
diff --git a/lib/Makefile b/lib/Makefile
index f6a8ba1..23e9f1e 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -27,6 +27,7 @@
obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
obj-$(CONFIG_GZIP) += gunzip.o
obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o
+obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
obj-y += initcall.o
obj-$(CONFIG_LMB) += lmb.o
obj-y += ldiv.o
@@ -47,6 +48,7 @@
obj-$(CONFIG_$(SPL_)SHA1) += sha1.o
obj-$(CONFIG_$(SPL_)SHA256) += sha256.o
+obj-$(CONFIG_SPL_SAVEENV) += qsort.o
obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy)
obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o
@@ -72,17 +74,23 @@
obj-y += membuff.o
obj-$(CONFIG_REGEX) += slre.o
obj-y += string.o
+obj-y += tables_csum.o
obj-y += time.o
obj-$(CONFIG_TRACE) += trace.o
obj-$(CONFIG_LIB_UUID) += uuid.o
obj-$(CONFIG_LIB_RAND) += rand.o
ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_TPL_BUILD
+SERIAL_SUPPORT := $(CONFIG_TPL_SERIAL_SUPPORT)
+else
+SERIAL_SUPPORT := $(CONFIG_SPL_SERIAL_SUPPORT)
+endif
# SPL U-Boot may use full-printf, tiny-printf or none at all
ifdef CONFIG_USE_TINY_PRINTF
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += tiny-printf.o panic.o strto.o
+obj-$(SERIAL_SUPPORT) += tiny-printf.o panic.o strto.o
else
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o panic.o strto.o strmhz.o
+obj-$(SERIAL_SUPPORT) += vsprintf.o panic.o strto.o strmhz.o
endif
else
# Main U-Boot always uses the full printf support
diff --git a/lib/efi/Makefile b/lib/efi/Makefile
index e32dc14..9449600 100644
--- a/lib/efi/Makefile
+++ b/lib/efi/Makefile
@@ -9,9 +9,9 @@
CFLAGS_REMOVE_efi_stub.o := -mregparm=3 \
$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
-CFLAGS_efi_stub.o := -fpic -fshort-wchar
+CFLAGS_efi_stub.o := -fpic -fshort-wchar -DEFI_STUB
CFLAGS_REMOVE_efi.o := -mregparm=3 \
$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
-CFLAGS_efi.o := -fpic -fshort-wchar
+CFLAGS_efi.o := -fpic -fshort-wchar -DEFI_STUB
extra-$(CONFIG_EFI_STUB) += efi_stub.o efi.o
diff --git a/lib/efi_loader/.gitignore b/lib/efi_loader/.gitignore
new file mode 100644
index 0000000..634a600
--- /dev/null
+++ b/lib/efi_loader/.gitignore
@@ -0,0 +1,2 @@
+*.efi
+*.so
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 37a0dd6..d2b6327 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -1,6 +1,6 @@
config EFI_LOADER
bool "Support running EFI Applications in U-Boot"
- depends on (ARM64 || ARM) && OF_LIBFDT
+ depends on (ARM || X86) && OF_LIBFDT
default y
help
Select this option if you want to run EFI applications (like grub2)
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 2a3849e..fa8b91a 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -7,8 +7,16 @@
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
+CFLAGS_helloworld.o := $(CFLAGS_EFI)
+CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI)
+
+efiprogs-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += helloworld.efi
+always := $(efiprogs-y)
+
+obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
obj-y += efi_memory.o
obj-$(CONFIG_LCD) += efi_gop.o
obj-$(CONFIG_PARTITIONS) += efi_disk.o
obj-$(CONFIG_NET) += efi_net.o
+obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index be6f5e8..51080cb 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -37,8 +37,9 @@
* In most cases we want to pass an FDT to the payload, so reserve one slot of
* config table space for it. The pointer gets populated by do_bootefi_exec().
*/
-static struct efi_configuration_table EFI_RUNTIME_DATA efi_conf_table[1];
+static struct efi_configuration_table __efi_runtime_data efi_conf_table[2];
+#ifdef CONFIG_ARM
/*
* The "gd" pointer lives in a register on ARM and AArch64 that we declare
* fixed when compiling U-Boot. However, the payload does not know about that
@@ -46,16 +47,20 @@
* EFI callback entry/exit.
*/
static volatile void *efi_gd, *app_gd;
+#endif
/* Called from do_bootefi_exec() */
void efi_save_gd(void)
{
+#ifdef CONFIG_ARM
efi_gd = gd;
+#endif
}
/* Called on every callback entry */
void efi_restore_gd(void)
{
+#ifdef CONFIG_ARM
/* Only restore if we're already in EFI context */
if (!efi_gd)
return;
@@ -63,12 +68,16 @@
if (gd != efi_gd)
app_gd = gd;
gd = efi_gd;
+#endif
}
/* Called on every callback exit */
efi_status_t efi_exit_func(efi_status_t ret)
{
+#ifdef CONFIG_ARM
gd = app_gd;
+#endif
+
return ret;
}
@@ -130,22 +139,23 @@
return EFI_EXIT(r);
}
-static efi_status_t EFIAPI efi_allocate_pool(int pool_type, unsigned long size,
- void **buffer)
+static efi_status_t EFIAPI efi_allocate_pool_ext(int pool_type,
+ unsigned long size,
+ void **buffer)
{
efi_status_t r;
EFI_ENTRY("%d, %ld, %p", pool_type, size, buffer);
- r = efi_allocate_pages(0, pool_type, (size + 0xfff) >> 12, (void*)buffer);
+ r = efi_allocate_pool(pool_type, size, buffer);
return EFI_EXIT(r);
}
-static efi_status_t EFIAPI efi_free_pool(void *buffer)
+static efi_status_t EFIAPI efi_free_pool_ext(void *buffer)
{
efi_status_t r;
EFI_ENTRY("%p", buffer);
- r = efi_free_pages((ulong)buffer, 0);
+ r = efi_free_pool(buffer);
return EFI_EXIT(r);
}
@@ -159,7 +169,7 @@
u32 trigger_time;
u64 trigger_next;
unsigned long notify_tpl;
- void (*notify_function) (void *event, void *context);
+ void (EFIAPI *notify_function) (void *event, void *context);
void *notify_context;
} efi_event = {
/* Disable timers on bootup */
@@ -168,7 +178,8 @@
static efi_status_t EFIAPI efi_create_event(
enum efi_event_type type, ulong notify_tpl,
- void (*notify_function) (void *event, void *context),
+ void (EFIAPI *notify_function) (void *event,
+ void *context),
void *notify_context, void **event)
{
EFI_ENTRY("%d, 0x%lx, %p, %p", type, notify_tpl, notify_function,
@@ -375,31 +386,35 @@
return EFI_EXIT(EFI_NOT_FOUND);
}
-static efi_status_t EFIAPI efi_install_configuration_table(efi_guid_t *guid,
- void *table)
+efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table)
{
int i;
- EFI_ENTRY("%p, %p", guid, table);
-
/* Check for guid override */
for (i = 0; i < systab.nr_tables; i++) {
if (!guidcmp(guid, &efi_conf_table[i].guid)) {
efi_conf_table[i].table = table;
- return EFI_EXIT(EFI_SUCCESS);
+ return EFI_SUCCESS;
}
}
/* No override, check for overflow */
if (i >= ARRAY_SIZE(efi_conf_table))
- return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+ return EFI_OUT_OF_RESOURCES;
/* Add a new entry */
memcpy(&efi_conf_table[i].guid, guid, sizeof(*guid));
efi_conf_table[i].table = table;
- systab.nr_tables = i;
+ systab.nr_tables = i + 1;
- return EFI_EXIT(EFI_SUCCESS);
+ return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI efi_install_configuration_table_ext(efi_guid_t *guid,
+ void *table)
+{
+ EFI_ENTRY("%p, %p", guid, table);
+ return EFI_EXIT(efi_install_configuration_table(guid, table));
}
static efi_status_t EFIAPI efi_load_image(bool boot_policy,
@@ -475,7 +490,7 @@
exit_data_size, exit_data);
loaded_image_info->exit_status = exit_status;
- longjmp(&loaded_image_info->exit_jmp);
+ longjmp(&loaded_image_info->exit_jmp, 1);
panic("EFI application exited");
}
@@ -523,6 +538,8 @@
{
EFI_ENTRY("%p, %ld", image_handle, map_key);
+ board_quiesce_devices();
+
/* Fix up caches for EFI payloads if necessary */
efi_exit_caches();
@@ -734,8 +751,8 @@
.allocate_pages = efi_allocate_pages_ext,
.free_pages = efi_free_pages_ext,
.get_memory_map = efi_get_memory_map_ext,
- .allocate_pool = efi_allocate_pool,
- .free_pool = efi_free_pool,
+ .allocate_pool = efi_allocate_pool_ext,
+ .free_pool = efi_free_pool_ext,
.create_event = efi_create_event,
.set_timer = efi_set_timer,
.wait_for_event = efi_wait_for_event,
@@ -750,7 +767,7 @@
.register_protocol_notify = efi_register_protocol_notify,
.locate_handle = efi_locate_handle,
.locate_device_path = efi_locate_device_path,
- .install_configuration_table = efi_install_configuration_table,
+ .install_configuration_table = efi_install_configuration_table_ext,
.load_image = efi_load_image,
.start_image = efi_start_image,
.exit = efi_exit,
@@ -775,10 +792,10 @@
};
-static uint16_t EFI_RUNTIME_DATA firmware_vendor[] =
+static uint16_t __efi_runtime_data firmware_vendor[] =
{ 'D','a','s',' ','U','-','b','o','o','t',0 };
-struct efi_system_table EFI_RUNTIME_DATA systab = {
+struct efi_system_table __efi_runtime_data systab = {
.hdr = {
.signature = EFI_SYSTEM_TABLE_SIGNATURE,
.revision = 0x20005, /* 2.5 */
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 2e0228c..8ef7326 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -9,11 +9,38 @@
#include <common.h>
#include <efi_loader.h>
-/* If we can't determine the console size, default to 80x24 */
-static int console_columns = 80;
-static int console_rows = 24;
static bool console_size_queried;
+#define EFI_COUT_MODE_2 2
+#define EFI_MAX_COUT_MODE 3
+
+struct cout_mode {
+ unsigned long columns;
+ unsigned long rows;
+ int present;
+};
+
+static struct cout_mode efi_cout_modes[] = {
+ /* EFI Mode 0 is 80x25 and always present */
+ {
+ .columns = 80,
+ .rows = 25,
+ .present = 1,
+ },
+ /* EFI Mode 1 is always 80x50 */
+ {
+ .columns = 80,
+ .rows = 50,
+ .present = 0,
+ },
+ /* Value are unknown until we query the console */
+ {
+ .columns = 0,
+ .rows = 0,
+ .present = 0,
+ },
+};
+
const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID;
#define cESC '\x1b'
@@ -56,8 +83,9 @@
.lock_std_in = efi_cin_lock_std_in,
};
+/* Default to mode 0 */
static struct simple_text_output_mode efi_con_mode = {
- .max_mode = 0,
+ .max_mode = 1,
.mode = 0,
.attribute = 0,
.cursor_column = 0,
@@ -131,8 +159,10 @@
struct efi_simple_text_output_protocol *this,
const unsigned short *string)
{
+ struct cout_mode *mode;
u16 ch;
+ mode = &efi_cout_modes[efi_con_mode.mode];
EFI_ENTRY("%p, %p", this, string);
for (;(ch = *string); string++) {
print_unicode_in_utf8(ch);
@@ -140,13 +170,12 @@
if (ch == '\n') {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
- } else if (efi_con_mode.cursor_column > console_columns) {
+ } else if (efi_con_mode.cursor_column > mode->columns) {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
}
- if (efi_con_mode.cursor_row > console_rows) {
- efi_con_mode.cursor_row = console_rows;
- }
+ if (efi_con_mode.cursor_row > mode->rows)
+ efi_con_mode.cursor_row = mode->rows;
}
return EFI_EXIT(EFI_SUCCESS);
@@ -160,6 +189,14 @@
return EFI_EXIT(EFI_SUCCESS);
}
+static bool cout_mode_matches(struct cout_mode *mode, int rows, int cols)
+{
+ if (!mode->present)
+ return false;
+
+ return (mode->rows == rows) && (mode->columns == cols);
+}
+
static efi_status_t EFIAPI efi_cout_query_mode(
struct efi_simple_text_output_protocol *this,
unsigned long mode_number, unsigned long *columns,
@@ -170,6 +207,8 @@
if (!console_size_queried) {
/* Ask the terminal about its size */
int n[3];
+ int cols;
+ int rows;
u64 timeout;
console_size_queried = true;
@@ -191,15 +230,40 @@
goto out;
}
- console_columns = n[2];
- console_rows = n[1];
+ cols = n[2];
+ rows = n[1];
+
+ /* Test if we can have Mode 1 */
+ if (cols >= 80 && rows >= 50) {
+ efi_cout_modes[1].present = 1;
+ efi_con_mode.max_mode = 2;
+ }
+
+ /*
+ * Install our mode as mode 2 if it is different
+ * than mode 0 or 1 and set it as the currently selected mode
+ */
+ if (!cout_mode_matches(&efi_cout_modes[0], rows, cols) &&
+ !cout_mode_matches(&efi_cout_modes[1], rows, cols)) {
+ efi_cout_modes[EFI_COUT_MODE_2].columns = cols;
+ efi_cout_modes[EFI_COUT_MODE_2].rows = rows;
+ efi_cout_modes[EFI_COUT_MODE_2].present = 1;
+ efi_con_mode.max_mode = EFI_MAX_COUT_MODE;
+ efi_con_mode.mode = EFI_COUT_MODE_2;
+ }
}
+ if (mode_number >= efi_con_mode.max_mode)
+ return EFI_EXIT(EFI_UNSUPPORTED);
+
+ if (efi_cout_modes[mode_number].present != 1)
+ return EFI_EXIT(EFI_UNSUPPORTED);
+
out:
if (columns)
- *columns = console_columns;
+ *columns = efi_cout_modes[mode_number].columns;
if (rows)
- *rows = console_rows;
+ *rows = efi_cout_modes[mode_number].rows;
return EFI_EXIT(EFI_SUCCESS);
}
@@ -210,11 +274,15 @@
{
EFI_ENTRY("%p, %ld", this, mode_number);
- /* We only support text output for now */
- if (mode_number == EFI_CONSOLE_MODE_TEXT)
- return EFI_EXIT(EFI_SUCCESS);
- return EFI_EXIT(EFI_UNSUPPORTED);
+ if (mode_number > efi_con_mode.max_mode)
+ return EFI_EXIT(EFI_UNSUPPORTED);
+
+ efi_con_mode.mode = mode_number;
+ efi_con_mode.cursor_column = 0;
+ efi_con_mode.cursor_row = 0;
+
+ return EFI_EXIT(EFI_SUCCESS);
}
static efi_status_t EFIAPI efi_cout_set_attribute(
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index d8ddcc9..1e3dca4 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -35,9 +35,10 @@
const struct blk_desc *desc;
};
-static efi_status_t efi_disk_open_block(void *handle, efi_guid_t *protocol,
- void **protocol_interface, void *agent_handle,
- void *controller_handle, uint32_t attributes)
+static efi_status_t EFIAPI efi_disk_open_block(void *handle,
+ efi_guid_t *protocol, void **protocol_interface,
+ void *agent_handle, void *controller_handle,
+ uint32_t attributes)
{
struct efi_disk_obj *diskobj = handle;
@@ -46,7 +47,7 @@
return EFI_SUCCESS;
}
-static efi_status_t efi_disk_open_dp(void *handle, efi_guid_t *protocol,
+static efi_status_t EFIAPI efi_disk_open_dp(void *handle, efi_guid_t *protocol,
void **protocol_interface, void *agent_handle,
void *controller_handle, uint32_t attributes)
{
@@ -108,7 +109,7 @@
return EFI_EXIT(EFI_SUCCESS);
}
-static efi_status_t efi_disk_read_blocks(struct efi_block_io *this,
+static efi_status_t EFIAPI efi_disk_read_blocks(struct efi_block_io *this,
u32 media_id, u64 lba, unsigned long buffer_size,
void *buffer)
{
@@ -143,7 +144,7 @@
return EFI_EXIT(r);
}
-static efi_status_t efi_disk_write_blocks(struct efi_block_io *this,
+static efi_status_t EFIAPI efi_disk_write_blocks(struct efi_block_io *this,
u32 media_id, u64 lba, unsigned long buffer_size,
void *buffer)
{
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index 33a3d71..286ad83 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -129,6 +129,7 @@
{
struct efi_gop_obj *gopobj;
u32 bpix, col, row;
+ u64 fb_base, fb_size;
#ifdef CONFIG_DM_VIDEO
struct udevice *vdev;
@@ -141,11 +142,16 @@
bpix = priv->bpix;
col = video_get_xsize(vdev);
row = video_get_ysize(vdev);
+ fb_base = (uintptr_t)priv->fb;
+ fb_size = priv->fb_size;
#else
+ int line_len;
bpix = panel_info.vl_bpix;
col = panel_info.vl_col;
row = panel_info.vl_row;
+ fb_base = gd->fb_base;
+ fb_size = lcd_get_size(&line_len);
#endif
switch (bpix) {
@@ -177,6 +183,16 @@
gopobj->mode.info = &gopobj->info;
gopobj->mode.info_size = sizeof(gopobj->info);
+#ifdef CONFIG_DM_VIDEO
+ if (bpix == VIDEO_BPP32) {
+#else
+ if (bpix == LCD_COLOR32) {
+#endif
+ /* With 32bit color space we can directly expose the fb */
+ gopobj->mode.fb_base = fb_base;
+ gopobj->mode.fb_size = fb_size;
+ }
+
gopobj->info.version = 0;
gopobj->info.width = col;
gopobj->info.height = row;
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
index 5165377..3262d76 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -174,7 +174,8 @@
efi_loader_relocate(rel, rel_size, efi_reloc);
/* Flush cache */
- flush_cache((ulong)efi_reloc, virt_size);
+ flush_cache((ulong)efi_reloc,
+ ALIGN(virt_size, CONFIG_SYS_CACHELINE_SIZE));
invalidate_icache_all();
/* Populate the loaded image interface bits */
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 80e4e26..95aa590 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -34,6 +34,19 @@
#endif
/*
+ * U-Boot services each EFI AllocatePool request as a separate
+ * (multiple) page allocation. We have to track the number of pages
+ * to be able to free the correct amount later.
+ * EFI requires 8 byte alignment for pool allocations, so we can
+ * prepend each allocation with an 64 bit header tracking the
+ * allocation size, and hand out the remainder to the caller.
+ */
+struct efi_pool_allocation {
+ u64 num_pages;
+ char data[];
+};
+
+/*
* Sorts the memory list from highest address to lowest address
*
* When allocating memory we should always start from the highest
@@ -62,9 +75,17 @@
* Unmaps all memory occupied by the carve_desc region from the
* list entry pointed to by map.
*
- * Returns 1 if carving was performed or 0 if the regions don't overlap.
- * Returns -1 if it would affect non-RAM regions but overlap_only_ram is set.
- * Carving is only guaranteed to complete when all regions return 0.
+ * Returns EFI_CARVE_NO_OVERLAP if the regions don't overlap.
+ * Returns EFI_CARVE_OVERLAPS_NONRAM if the carve and map overlap,
+ * and the map contains anything but free ram.
+ * (only when overlap_only_ram is true)
+ * Returns EFI_CARVE_LOOP_AGAIN if the mapping list should be traversed
+ * again, as it has been altered
+ * Returns the number of overlapping pages. The pages are removed from
+ * the mapping list.
+ *
+ * In case of EFI_CARVE_OVERLAPS_NONRAM it is the callers responsibility
+ * to readd the already carved out pages to the mapping.
*/
static int efi_mem_carve_out(struct efi_mem_list *map,
struct efi_mem_desc *carve_desc,
@@ -95,10 +116,13 @@
if (map_end == carve_end) {
/* Full overlap, just remove map */
list_del(&map->link);
+ free(map);
+ } else {
+ map->desc.physical_start = carve_end;
+ map->desc.num_pages = (map_end - carve_end)
+ >> EFI_PAGE_SHIFT;
}
- map_desc->physical_start = carve_end;
- map_desc->num_pages = (map_end - carve_end) >> EFI_PAGE_SHIFT;
return (carve_end - carve_start) >> EFI_PAGE_SHIFT;
}
@@ -114,7 +138,8 @@
newmap->desc = map->desc;
newmap->desc.physical_start = carve_start;
newmap->desc.num_pages = (map_end - carve_start) >> EFI_PAGE_SHIFT;
- list_add_tail(&newmap->link, &efi_mem);
+ /* Insert before current entry (descending address order) */
+ list_add_tail(&newmap->link, &map->link);
/* Shrink the map to [ map_start ... carve_start ] */
map_desc->num_pages = (carve_start - map_start) >> EFI_PAGE_SHIFT;
@@ -315,8 +340,52 @@
efi_status_t efi_free_pages(uint64_t memory, unsigned long pages)
{
- /* We don't free, let's cross our fingers we have plenty RAM */
- return EFI_SUCCESS;
+ uint64_t r = 0;
+
+ r = efi_add_memory_map(memory, pages, EFI_CONVENTIONAL_MEMORY, false);
+ /* Merging of adjacent free regions is missing */
+
+ if (r == memory)
+ return EFI_SUCCESS;
+
+ return EFI_NOT_FOUND;
+}
+
+efi_status_t efi_allocate_pool(int pool_type, unsigned long size,
+ void **buffer)
+{
+ efi_status_t r;
+ efi_physical_addr_t t;
+ u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
+
+ if (size == 0) {
+ *buffer = NULL;
+ return EFI_SUCCESS;
+ }
+
+ r = efi_allocate_pages(0, pool_type, num_pages, &t);
+
+ if (r == EFI_SUCCESS) {
+ struct efi_pool_allocation *alloc = (void *)(uintptr_t)t;
+ alloc->num_pages = num_pages;
+ *buffer = alloc->data;
+ }
+
+ return r;
+}
+
+efi_status_t efi_free_pool(void *buffer)
+{
+ efi_status_t r;
+ struct efi_pool_allocation *alloc;
+
+ alloc = container_of(buffer, struct efi_pool_allocation, data);
+ /* Sanity check, was the supplied address returned by allocate_pool */
+ assert(((uintptr_t)alloc & EFI_PAGE_MASK) == 0);
+
+ r = efi_free_pages((uintptr_t)alloc, alloc->num_pages);
+
+ return r;
}
efi_status_t efi_get_memory_map(unsigned long *memory_map_size,
@@ -328,6 +397,7 @@
ulong map_size = 0;
int map_entries = 0;
struct list_head *lhandle;
+ unsigned long provided_map_size = *memory_map_size;
list_for_each(lhandle, &efi_mem)
map_entries++;
@@ -342,7 +412,7 @@
if (descriptor_version)
*descriptor_version = EFI_MEMORY_DESCRIPTOR_VERSION;
- if (*memory_map_size < map_size)
+ if (provided_map_size < map_size)
return EFI_BUFFER_TOO_SMALL;
/* Copy list into array */
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
index dd3b485..604ac6e 100644
--- a/lib/efi_loader/efi_net.c
+++ b/lib/efi_loader/efi_net.c
@@ -27,7 +27,8 @@
struct efi_simple_network net;
struct efi_simple_network_mode net_mode;
/* Device path to the network adapter */
- struct efi_device_path_file_path dp[2];
+ struct efi_device_path_mac_addr dp_mac;
+ struct efi_device_path_file_path dp_end;
/* PXE struct to transmit dhcp data */
struct efi_pxe pxe;
struct efi_pxe_mode pxe_mode;
@@ -152,7 +153,14 @@
return EFI_EXIT(EFI_INVALID_PARAMETER);
}
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+ /* Ethernet packets always fit, just bounce */
+ memcpy(efi_bounce_buffer, buffer, buffer_size);
+ net_send_packet(efi_bounce_buffer, buffer_size);
+#else
net_send_packet(buffer, buffer_size);
+#endif
+
new_tx_packet = buffer;
return EFI_EXIT(EFI_SUCCESS);
@@ -191,19 +199,19 @@
return EFI_EXIT(EFI_SUCCESS);
}
-static efi_status_t efi_net_open_dp(void *handle, efi_guid_t *protocol,
+static efi_status_t EFIAPI efi_net_open_dp(void *handle, efi_guid_t *protocol,
void **protocol_interface, void *agent_handle,
void *controller_handle, uint32_t attributes)
{
struct efi_simple_network *net = handle;
struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
- *protocol_interface = netobj->dp;
+ *protocol_interface = &netobj->dp_mac;
return EFI_SUCCESS;
}
-static efi_status_t efi_net_open_pxe(void *handle, efi_guid_t *protocol,
+static efi_status_t EFIAPI efi_net_open_pxe(void *handle, efi_guid_t *protocol,
void **protocol_interface, void *agent_handle,
void *controller_handle, uint32_t attributes)
{
@@ -229,11 +237,10 @@
int efi_net_register(void **handle)
{
struct efi_net_obj *netobj;
- struct efi_device_path_file_path dp_net = {
- .dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
- .dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+ struct efi_device_path_mac_addr dp_net = {
+ .dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE,
+ .dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR,
.dp.length = sizeof(dp_net),
- .str = { 'N', 'e', 't' },
};
struct efi_device_path_file_path dp_end = {
.dp.type = DEVICE_PATH_TYPE_END,
@@ -272,8 +279,9 @@
netobj->net.receive = efi_net_receive;
netobj->net.mode = &netobj->net_mode;
netobj->net_mode.state = EFI_NETWORK_STARTED;
- netobj->dp[0] = dp_net;
- netobj->dp[1] = dp_end;
+ netobj->dp_mac = dp_net;
+ netobj->dp_end = dp_end;
+ memcpy(netobj->dp_mac.mac.addr, eth_get_ethaddr(), 6);
memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
netobj->net_mode.max_packet_size = PKTSIZE;
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 99b5ef1..dd52755 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -16,9 +16,19 @@
/* For manual relocation support */
DECLARE_GLOBAL_DATA_PTR;
-static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_unimplemented(void);
-static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_device_error(void);
-static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_invalid_parameter(void);
+struct efi_runtime_mmio_list {
+ struct list_head link;
+ void **ptr;
+ u64 paddr;
+ u64 len;
+};
+
+/* This list contains all runtime available mmio regions */
+LIST_HEAD(efi_runtime_mmio);
+
+static efi_status_t __efi_runtime EFIAPI efi_unimplemented(void);
+static efi_status_t __efi_runtime EFIAPI efi_device_error(void);
+static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void);
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define EFI_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
@@ -34,6 +44,10 @@
#elif defined(CONFIG_ARM)
#define R_RELATIVE 23
#define R_MASK 0xffULL
+#elif defined(CONFIG_X86)
+#include <asm/elf.h>
+#define R_RELATIVE R_386_RELATIVE
+#define R_MASK 0xffULL
#else
#error Need to add relocation awareness
#endif
@@ -55,9 +69,10 @@
* handle a good number of runtime callbacks
*/
-static void EFIAPI efi_reset_system(enum efi_reset_type reset_type,
- efi_status_t reset_status,
- unsigned long data_size, void *reset_data)
+static void EFIAPI efi_reset_system_boottime(
+ enum efi_reset_type reset_type,
+ efi_status_t reset_status,
+ unsigned long data_size, void *reset_data)
{
EFI_ENTRY("%d %lx %lx %p", reset_type, reset_status, data_size,
reset_data);
@@ -72,11 +87,12 @@
break;
}
- EFI_EXIT(EFI_SUCCESS);
+ while (1) { }
}
-static efi_status_t EFIAPI efi_get_time(struct efi_time *time,
- struct efi_time_cap *capabilities)
+static efi_status_t EFIAPI efi_get_time_boottime(
+ struct efi_time *time,
+ struct efi_time_cap *capabilities)
{
#if defined(CONFIG_CMD_DATE) && defined(CONFIG_DM_RTC)
struct rtc_time tm;
@@ -107,6 +123,33 @@
#endif
}
+/* Boards may override the helpers below to implement RTS functionality */
+
+void __weak __efi_runtime EFIAPI efi_reset_system(
+ enum efi_reset_type reset_type,
+ efi_status_t reset_status,
+ unsigned long data_size, void *reset_data)
+{
+ /* Nothing we can do */
+ while (1) { }
+}
+
+void __weak efi_reset_system_init(void)
+{
+}
+
+efi_status_t __weak __efi_runtime EFIAPI efi_get_time(
+ struct efi_time *time,
+ struct efi_time_cap *capabilities)
+{
+ /* Nothing we can do */
+ return EFI_DEVICE_ERROR;
+}
+
+void __weak efi_get_time_init(void)
+{
+}
+
struct efi_runtime_detach_list_struct {
void *ptr;
void *patchto;
@@ -116,7 +159,7 @@
{
/* do_reset is gone */
.ptr = &efi_runtime_services.reset_system,
- .patchto = NULL,
+ .patchto = efi_reset_system,
}, {
/* invalidate_*cache_all are gone */
.ptr = &efi_runtime_services.set_virtual_address_map,
@@ -124,7 +167,7 @@
}, {
/* RTC accessors are gone */
.ptr = &efi_runtime_services.get_time,
- .patchto = &efi_device_error,
+ .patchto = &efi_get_time,
}, {
/* Clean up system table */
.ptr = &systab.con_in,
@@ -233,12 +276,39 @@
EFI_ENTRY("%lx %lx %x %p", memory_map_size, descriptor_size,
descriptor_version, virtmap);
+ /* Rebind mmio pointers */
+ for (i = 0; i < n; i++) {
+ struct efi_mem_desc *map = (void*)virtmap +
+ (descriptor_size * i);
+ struct list_head *lhandle;
+ efi_physical_addr_t map_start = map->physical_start;
+ efi_physical_addr_t map_len = map->num_pages << EFI_PAGE_SHIFT;
+ efi_physical_addr_t map_end = map_start + map_len;
+
+ /* Adjust all mmio pointers in this region */
+ list_for_each(lhandle, &efi_runtime_mmio) {
+ struct efi_runtime_mmio_list *lmmio;
+
+ lmmio = list_entry(lhandle,
+ struct efi_runtime_mmio_list,
+ link);
+ if ((map_start <= lmmio->paddr) &&
+ (map_end >= lmmio->paddr)) {
+ u64 off = map->virtual_start - map_start;
+ uintptr_t new_addr = lmmio->paddr + off;
+ *lmmio->ptr = (void *)new_addr;
+ }
+ }
+ }
+
+ /* Move the actual runtime code over */
for (i = 0; i < n; i++) {
struct efi_mem_desc *map;
map = (void*)virtmap + (descriptor_size * i);
if (map->type == EFI_RUNTIME_SERVICES_CODE) {
- ulong new_offset = map->virtual_start - (runtime_start - gd->relocaddr);
+ ulong new_offset = map->virtual_start -
+ (runtime_start - gd->relocaddr);
efi_runtime_relocate(new_offset, map);
/* Once we're virtual, we can no longer handle
@@ -251,6 +321,20 @@
return EFI_EXIT(EFI_INVALID_PARAMETER);
}
+void efi_add_runtime_mmio(void *mmio_ptr, u64 len)
+{
+ struct efi_runtime_mmio_list *newmmio;
+
+ u64 pages = (len + EFI_PAGE_SIZE - 1) >> EFI_PAGE_SHIFT;
+ efi_add_memory_map(*(uintptr_t *)mmio_ptr, pages, EFI_MMAP_IO, false);
+
+ newmmio = calloc(1, sizeof(*newmmio));
+ newmmio->ptr = mmio_ptr;
+ newmmio->paddr = *(uintptr_t *)mmio_ptr;
+ newmmio->len = len;
+ list_add_tail(&newmmio->link, &efi_runtime_mmio);
+}
+
/*
* In the second stage, U-Boot has disappeared. To isolate our runtime code
* that at this point still exists from the rest, we put it into a special
@@ -262,7 +346,7 @@
* function or variable below this line.
*
* Please keep everything fully self-contained and annotated with
- * EFI_RUNTIME_TEXT and EFI_RUNTIME_DATA markers.
+ * __efi_runtime and __efi_runtime_data markers.
*/
/*
@@ -271,28 +355,28 @@
* address map calls.
*/
-static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_unimplemented(void)
+static efi_status_t __efi_runtime EFIAPI efi_unimplemented(void)
{
return EFI_UNSUPPORTED;
}
-static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_device_error(void)
+static efi_status_t __efi_runtime EFIAPI efi_device_error(void)
{
return EFI_DEVICE_ERROR;
}
-static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_invalid_parameter(void)
+static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void)
{
return EFI_INVALID_PARAMETER;
}
-struct efi_runtime_services EFI_RUNTIME_DATA efi_runtime_services = {
+struct efi_runtime_services __efi_runtime_data efi_runtime_services = {
.hdr = {
.signature = EFI_RUNTIME_SERVICES_SIGNATURE,
.revision = EFI_RUNTIME_SERVICES_REVISION,
.headersize = sizeof(struct efi_table_hdr),
},
- .get_time = &efi_get_time,
+ .get_time = &efi_get_time_boottime,
.set_time = (void *)&efi_device_error,
.get_wakeup_time = (void *)&efi_unimplemented,
.set_wakeup_time = (void *)&efi_unimplemented,
@@ -302,5 +386,5 @@
.get_next_variable = (void *)&efi_device_error,
.set_variable = (void *)&efi_device_error,
.get_next_high_mono_count = (void *)&efi_device_error,
- .reset_system = &efi_reset_system,
+ .reset_system = &efi_reset_system_boottime,
};
diff --git a/lib/efi_loader/efi_smbios.c b/lib/efi_loader/efi_smbios.c
new file mode 100644
index 0000000..ac412e7
--- /dev/null
+++ b/lib/efi_loader/efi_smbios.c
@@ -0,0 +1,32 @@
+/*
+ * EFI application tables support
+ *
+ * Copyright (c) 2016 Alexander Graf
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <inttypes.h>
+#include <smbios.h>
+
+static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID;
+
+void efi_smbios_register(void)
+{
+ /* Map within the low 32 bits, to allow for 32bit SMBIOS tables */
+ uint64_t dmi = 0xffffffff;
+ /* Reserve 4kb for SMBIOS */
+ uint64_t pages = 1;
+ int memtype = EFI_RUNTIME_SERVICES_DATA;
+
+ if (efi_allocate_pages(1, memtype, pages, &dmi) != EFI_SUCCESS)
+ return;
+
+ /* Generate SMBIOS tables */
+ write_smbios_table(dmi);
+
+ /* And expose them to our EFI payload */
+ efi_install_configuration_table(&smbios_guid, (void*)(uintptr_t)dmi);
+}
diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c
new file mode 100644
index 0000000..03e65ab
--- /dev/null
+++ b/lib/efi_loader/helloworld.c
@@ -0,0 +1,24 @@
+/*
+ * EFI hello world
+ *
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <part_efi.h>
+#include <efi_api.h>
+
+efi_status_t EFIAPI efi_main(efi_handle_t handle,
+ struct efi_system_table *systable)
+{
+ struct efi_simple_text_output_protocol *con_out = systable->con_out;
+ struct efi_boot_services *boottime = systable->boottime;
+
+ con_out->output_string(con_out, L"Hello, world!\n");
+ boottime->exit(handle, 0, 0, NULL);
+
+ return EFI_SUCCESS;
+}
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index a1b844f..2e1beb5 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -59,7 +59,6 @@
COMPAT(INTEL_MICROCODE, "intel,microcode"),
COMPAT(AMS_AS3722, "ams,as3722"),
COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
- COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
@@ -837,7 +836,7 @@
int subnode;
int num = 0;
- fdt_for_each_subnode(blob, subnode, node)
+ fdt_for_each_subnode(subnode, blob, node)
num++;
return num;
@@ -1015,7 +1014,7 @@
{
int index;
- index = fdt_find_string(fdt, node, prop_names, name);
+ index = fdt_stringlist_search(fdt, node, prop_names, name);
if (index < 0)
return index;
@@ -1175,6 +1174,62 @@
return ret;
}
+int fdtdec_setup_memory_size(void)
+{
+ int ret, mem;
+ struct fdt_resource res;
+
+ mem = fdt_path_offset(gd->fdt_blob, "/memory");
+ if (mem < 0) {
+ debug("%s: Missing /memory node\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = fdt_get_resource(gd->fdt_blob, mem, "reg", 0, &res);
+ if (ret != 0) {
+ debug("%s: Unable to decode first memory bank\n", __func__);
+ return -EINVAL;
+ }
+
+ gd->ram_size = (phys_size_t)(res.end - res.start + 1);
+ debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+ return 0;
+}
+
+#if defined(CONFIG_NR_DRAM_BANKS)
+int fdtdec_setup_memory_banksize(void)
+{
+ int bank, ret, mem;
+ struct fdt_resource res;
+
+ mem = fdt_path_offset(gd->fdt_blob, "/memory");
+ if (mem < 0) {
+ debug("%s: Missing /memory node\n", __func__);
+ return -EINVAL;
+ }
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, &res);
+ if (ret == -FDT_ERR_NOTFOUND)
+ break;
+ if (ret != 0)
+ return -EINVAL;
+
+ gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
+ gd->bd->bi_dram[bank].size =
+ (phys_size_t)(res.end - res.start + 1);
+
+ debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
+ __func__, bank,
+ (unsigned long long)gd->bd->bi_dram[bank].start,
+ (unsigned long long)gd->bd->bi_dram[bank].size);
+ }
+
+ return 0;
+}
+#endif
+
int fdtdec_setup(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
diff --git a/lib/gunzip.c b/lib/gunzip.c
index bc746d6..832b306 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -11,6 +11,7 @@
#include <console.h>
#include <image.h>
#include <malloc.h>
+#include <memalign.h>
#include <u-boot/zlib.h>
#include <div64.h>
@@ -193,7 +194,7 @@
s.next_in = src + i;
s.avail_in = payload_size+8;
- writebuf = (unsigned char *)malloc(szwritebuf);
+ writebuf = (unsigned char *)malloc_cache_aligned(szwritebuf);
/* decompress until deflate stream ends or end of file */
do {
diff --git a/lib/hashtable.c b/lib/hashtable.c
index 4e52b36..f088477 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -477,11 +477,11 @@
return 1;
}
+#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV))
/*
* hexport()
*/
-#ifndef CONFIG_SPL_BUILD
/*
* Export the data stored in the hash table in linearized form.
*
@@ -499,7 +499,7 @@
*
* If the separator character is different from NUL, then any
* separator characters and backslash characters in the values will
- * be escaped by a preceeding backslash in output. This is needed for
+ * be escaped by a preceding backslash in output. This is needed for
* example to enable multi-line values, especially when the output
* shall later be parsed (for example, for re-import).
*
diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c
index 96017a1..2055734 100644
--- a/lib/libfdt/fdt.c
+++ b/lib/libfdt/fdt.c
@@ -35,18 +35,19 @@
const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)
{
- const char *p;
+ unsigned absoffset = offset + fdt_off_dt_struct(fdt);
+
+ if ((absoffset < offset)
+ || ((absoffset + len) < absoffset)
+ || (absoffset + len) > fdt_totalsize(fdt))
+ return NULL;
if (fdt_version(fdt) >= 0x11)
if (((offset + len) < offset)
|| ((offset + len) > fdt_size_dt_struct(fdt)))
return NULL;
- p = _fdt_offset_ptr(fdt, offset);
-
- if (p + len < p)
- return NULL;
- return p;
+ return _fdt_offset_ptr(fdt, offset);
}
uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
diff --git a/lib/libfdt/fdt_overlay.c b/lib/libfdt/fdt_overlay.c
index 40b6d27..bb41404 100644
--- a/lib/libfdt/fdt_overlay.c
+++ b/lib/libfdt/fdt_overlay.c
@@ -28,19 +28,19 @@
if (!val)
return 0;
- if ((*val == (uint32_t)-1) || (len != sizeof(*val)))
+ if ((len != sizeof(*val)) || (*val == (uint32_t)-1))
return (uint32_t)-1;
return fdt32_to_cpu(*val);
}
/**
- * overlay_get_target - retrieves the target phandle of a fragment
+ * overlay_get_target - retrieves the offset of a fragment's target
* @fdt: Base device tree blob
* @fdto: Device tree overlay blob
* @fragment: node offset of the fragment in the overlay
*
- * overlay_get_target() retrieves the target phandle in the base
+ * overlay_get_target() retrieves the target offset in the base
* device tree of a fragment, no matter how the actual targetting is
* done (through a phandle or a path)
*
@@ -53,6 +53,7 @@
{
uint32_t phandle;
const char *path;
+ int path_len;
/* Try first to do a phandle based lookup */
phandle = overlay_get_target_phandle(fdto, fragment);
@@ -63,9 +64,20 @@
return fdt_node_offset_by_phandle(fdt, phandle);
/* And then a path based lookup */
- path = fdt_getprop(fdto, fragment, "target-path", NULL);
- if (!path)
- return -FDT_ERR_NOTFOUND;
+ path = fdt_getprop(fdto, fragment, "target-path", &path_len);
+ if (!path) {
+ /*
+ * If we haven't found either a target or a
+ * target-path property in a node that contains a
+ * __overlay__ subnode (we wouldn't be called
+ * otherwise), consider it a improperly written
+ * overlay
+ */
+ if (path_len == -FDT_ERR_NOTFOUND)
+ return -FDT_ERR_BADOVERLAY;
+
+ return path_len;
+ }
return fdt_path_offset(fdt, path);
}
@@ -96,13 +108,16 @@
return len;
if (len != sizeof(*val))
- return -FDT_ERR_BADSTRUCTURE;
+ return -FDT_ERR_BADPHANDLE;
adj_val = fdt32_to_cpu(*val);
if ((adj_val + delta) < adj_val)
- return -FDT_ERR_BADPHANDLE;
+ return -FDT_ERR_NOPHANDLES;
adj_val += delta;
+ if (adj_val == (uint32_t)-1)
+ return -FDT_ERR_NOPHANDLES;
+
return fdt_setprop_inplace_u32(fdt, node, name, adj_val);
}
@@ -124,7 +139,6 @@
static int overlay_adjust_node_phandles(void *fdto, int node,
uint32_t delta)
{
- bool found = false;
int child;
int ret;
@@ -132,22 +146,15 @@
if (ret && ret != -FDT_ERR_NOTFOUND)
return ret;
- if (!ret)
- found = true;
-
ret = overlay_phandle_add_offset(fdto, node, "linux,phandle", delta);
if (ret && ret != -FDT_ERR_NOTFOUND)
return ret;
- /*
- * If neither phandle nor linux,phandle have been found return
- * an error.
- */
- if (!found && !ret)
- return ret;
-
- fdt_for_each_subnode(fdto, child, node)
- overlay_adjust_node_phandles(fdto, child, delta);
+ fdt_for_each_subnode(child, fdto, node) {
+ ret = overlay_adjust_node_phandles(fdto, child, delta);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -203,7 +210,8 @@
int ret;
fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) {
- const unsigned char *fixup_val, *tree_val;
+ const uint32_t *fixup_val;
+ const char *tree_val;
const char *name;
int fixup_len;
int tree_len;
@@ -214,15 +222,21 @@
if (!fixup_val)
return fixup_len;
+ if (fixup_len % sizeof(uint32_t))
+ return -FDT_ERR_BADOVERLAY;
+
tree_val = fdt_getprop(fdto, tree_node, name, &tree_len);
- if (!tree_val)
+ if (!tree_val) {
+ if (tree_len == -FDT_ERR_NOTFOUND)
+ return -FDT_ERR_BADOVERLAY;
+
return tree_len;
+ }
- for (i = 0; i < fixup_len; i += sizeof(uint32_t)) {
- uint32_t adj_val, index;
+ for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) {
+ uint32_t adj_val, poffset;
- index = *(uint32_t *)(fixup_val + i);
- index = fdt32_to_cpu(index);
+ poffset = fdt32_to_cpu(fixup_val[i]);
/*
* phandles to fixup can be unaligned.
@@ -230,7 +244,7 @@
* Use a memcpy for the architectures that do
* not support unaligned accesses.
*/
- memcpy(&adj_val, tree_val + index, sizeof(uint32_t));
+ memcpy(&adj_val, tree_val + poffset, sizeof(adj_val));
adj_val = fdt32_to_cpu(adj_val);
adj_val += delta;
@@ -240,21 +254,26 @@
tree_node,
name,
strlen(name),
- index,
+ poffset,
&adj_val,
sizeof(adj_val));
+ if (ret == -FDT_ERR_NOSPACE)
+ return -FDT_ERR_BADOVERLAY;
+
if (ret)
return ret;
}
}
- fdt_for_each_subnode(fdto, fixup_child, fixup_node) {
+ fdt_for_each_subnode(fixup_child, fdto, fixup_node) {
const char *fixup_child_name = fdt_get_name(fdto, fixup_child,
NULL);
int tree_child;
tree_child = fdt_subnode_offset(fdto, tree_node,
fixup_child_name);
+ if (ret == -FDT_ERR_NOTFOUND)
+ return -FDT_ERR_BADOVERLAY;
if (tree_child < 0)
return tree_child;
@@ -315,7 +334,7 @@
* @path_len: number of path characters to consider
* @name: Name of the property holding the phandle reference in the overlay
* @name_len: number of name characters to consider
- * @index: Index in the overlay property where the phandle is stored
+ * @poffset: Offset within the overlay property where the phandle is stored
* @label: Label of the node referenced by the phandle
*
* overlay_fixup_one_phandle() resolves an overlay phandle pointing to
@@ -333,7 +352,7 @@
int symbols_off,
const char *path, uint32_t path_len,
const char *name, uint32_t name_len,
- int index, const char *label)
+ int poffset, const char *label)
{
const char *symbol_path;
uint32_t phandle;
@@ -343,7 +362,7 @@
symbol_path = fdt_getprop(fdt, symbols_off, label,
&prop_len);
if (!symbol_path)
- return -FDT_ERR_NOTFOUND;
+ return prop_len;
symbol_off = fdt_path_offset(fdt, symbol_path);
if (symbol_off < 0)
@@ -354,12 +373,14 @@
return -FDT_ERR_NOTFOUND;
fixup_off = fdt_path_offset_namelen(fdto, path, path_len);
+ if (fixup_off == -FDT_ERR_NOTFOUND)
+ return -FDT_ERR_BADOVERLAY;
if (fixup_off < 0)
return fixup_off;
phandle = cpu_to_fdt32(phandle);
return fdt_setprop_inplace_namelen_partial(fdto, fixup_off,
- name, name_len, index,
+ name, name_len, poffset,
&phandle, sizeof(phandle));
};
@@ -371,8 +392,8 @@
* @property: Property offset in the overlay holding the list of fixups
*
* overlay_fixup_phandle() resolves all the overlay phandles pointed
- * to in a __local_fixup__ property, and updates them to match the
- * phandles in use in the base device tree.
+ * to in a __fixups__ property, and updates them to match the phandles
+ * in use in the base device tree.
*
* This is part of the device tree overlay application process, when
* you want all the phandles in the overlay to point to the actual
@@ -391,40 +412,55 @@
value = fdt_getprop_by_offset(fdto, property,
&label, &len);
- if (!value)
+ if (!value) {
+ if (len == -FDT_ERR_NOTFOUND)
+ return -FDT_ERR_INTERNAL;
+
return len;
+ }
do {
- const char *prop_string = value;
- const char *path, *name;
- uint32_t prop_len = strlen(value);
+ const char *path, *name, *fixup_end;
+ const char *fixup_str = value;
uint32_t path_len, name_len;
+ uint32_t fixup_len;
char *sep, *endptr;
- int index;
- int ret;
+ int poffset, ret;
- path = prop_string;
- sep = memchr(prop_string, ':', prop_len);
- if (*sep != ':')
- return -FDT_ERR_BADSTRUCTURE;
+ fixup_end = memchr(value, '\0', len);
+ if (!fixup_end)
+ return -FDT_ERR_BADOVERLAY;
+ fixup_len = fixup_end - fixup_str;
+
+ len -= fixup_len + 1;
+ value += fixup_len + 1;
+
+ path = fixup_str;
+ sep = memchr(fixup_str, ':', fixup_len);
+ if (!sep || *sep != ':')
+ return -FDT_ERR_BADOVERLAY;
+
path_len = sep - path;
+ if (path_len == (fixup_len - 1))
+ return -FDT_ERR_BADOVERLAY;
+ fixup_len -= path_len + 1;
name = sep + 1;
- sep = memchr(name, ':', prop_len);
- if (*sep != ':')
- return -FDT_ERR_BADSTRUCTURE;
+ sep = memchr(name, ':', fixup_len);
+ if (!sep || *sep != ':')
+ return -FDT_ERR_BADOVERLAY;
+
name_len = sep - name;
+ if (!name_len)
+ return -FDT_ERR_BADOVERLAY;
- index = strtoul(sep + 1, &endptr, 10);
+ poffset = strtoul(sep + 1, &endptr, 10);
if ((*endptr != '\0') || (endptr <= (sep + 1)))
- return -FDT_ERR_BADSTRUCTURE;
-
- len -= prop_len + 1;
- value += prop_len + 1;
+ return -FDT_ERR_BADOVERLAY;
ret = overlay_fixup_one_phandle(fdt, fdto, symbols_off,
path, path_len, name, name_len,
- index, label);
+ poffset, label);
if (ret)
return ret;
} while (len > 0);
@@ -454,8 +490,15 @@
int fixups_off, symbols_off;
int property;
- symbols_off = fdt_path_offset(fdt, "/__symbols__");
+ /* We can have overlays without any fixups */
fixups_off = fdt_path_offset(fdto, "/__fixups__");
+ if ((fixups_off < 0 && (fixups_off != -FDT_ERR_NOTFOUND)))
+ return fixups_off;
+
+ /* And base DTs without symbols */
+ symbols_off = fdt_path_offset(fdt, "/__symbols__");
+ if ((symbols_off < 0 && (symbols_off != -FDT_ERR_NOTFOUND)))
+ return symbols_off;
fdt_for_each_property_offset(property, fdto, fixups_off) {
int ret;
@@ -469,14 +512,14 @@
}
/**
- * overlay_apply_node - Merge an overlay fragment into the base device tree
+ * overlay_apply_node - Merges a node into the base device tree
* @fdt: Base Device Tree blob
* @target: Node offset in the base device tree to apply the fragment to
* @fdto: Device tree overlay blob
- * @fragment: Node offset in the overlay holding the changes to merge
+ * @node: Node offset in the overlay holding the changes to merge
*
- * overlay_apply_node() merges an overlay fragment into a target base
- * device tree node pointed.
+ * overlay_apply_node() merges a node into a target base device tree
+ * node pointed.
*
* This is part of the final step in the device tree overlay
* application process, when all the phandles have been adjusted and
@@ -488,12 +531,12 @@
* Negative error code on failure
*/
static int overlay_apply_node(void *fdt, int target,
- void *fdto, int fragment)
+ void *fdto, int node)
{
int property;
- int node;
+ int subnode;
- fdt_for_each_property_offset(property, fdto, fragment) {
+ fdt_for_each_property_offset(property, fdto, node) {
const char *name;
const void *prop;
int prop_len;
@@ -511,19 +554,22 @@
return ret;
}
- fdt_for_each_subnode(fdto, node, fragment) {
- const char *name = fdt_get_name(fdto, node, NULL);
+ fdt_for_each_subnode(subnode, fdto, node) {
+ const char *name = fdt_get_name(fdto, subnode, NULL);
int nnode;
int ret;
nnode = fdt_add_subnode(fdt, target, name);
- if (nnode == -FDT_ERR_EXISTS)
+ if (nnode == -FDT_ERR_EXISTS) {
nnode = fdt_subnode_offset(fdt, target, name);
+ if (nnode == -FDT_ERR_NOTFOUND)
+ return -FDT_ERR_INTERNAL;
+ }
if (nnode < 0)
return nnode;
- ret = overlay_apply_node(fdt, nnode, fdto, node);
+ ret = overlay_apply_node(fdt, nnode, fdto, subnode);
if (ret)
return ret;
}
@@ -546,24 +592,31 @@
* 0 on success
* Negative error code on failure
*/
-static int overlay_merge(void *dt, void *dto)
+static int overlay_merge(void *fdt, void *fdto)
{
int fragment;
- fdt_for_each_subnode(dto, fragment, 0) {
+ fdt_for_each_subnode(fragment, fdto, 0) {
int overlay;
int target;
int ret;
- target = overlay_get_target(dt, dto, fragment);
- if (target < 0)
+ /*
+ * Each fragments will have an __overlay__ node. If
+ * they don't, it's not supposed to be merged
+ */
+ overlay = fdt_subnode_offset(fdto, fragment, "__overlay__");
+ if (overlay == -FDT_ERR_NOTFOUND)
continue;
- overlay = fdt_subnode_offset(dto, fragment, "__overlay__");
if (overlay < 0)
return overlay;
- ret = overlay_apply_node(dt, target, dto, overlay);
+ target = overlay_get_target(fdt, fdto, fragment);
+ if (target < 0)
+ return target;
+
+ ret = overlay_apply_node(fdt, target, fdto, overlay);
if (ret)
return ret;
}
@@ -573,7 +626,7 @@
int fdt_overlay_apply(void *fdt, void *fdto)
{
- uint32_t delta = fdt_get_max_phandle(fdt) + 1;
+ uint32_t delta = fdt_get_max_phandle(fdt);
int ret;
FDT_CHECK_HEADER(fdt);
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 9cc98db..1be9538 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -60,11 +60,11 @@
return max_phandle;
if (offset < 0)
- return 0;
+ return (uint32_t)-1;
phandle = fdt_get_phandle(fdt, offset);
if (phandle == (uint32_t)-1)
- return 0;
+ continue;
if (phandle > max_phandle)
max_phandle = phandle;
@@ -204,6 +204,11 @@
return offset;
}
+int fdt_path_offset(const void *fdt, const char *path)
+{
+ return fdt_path_offset_namelen(fdt, path, strlen(path));
+}
+
const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
{
const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset);
@@ -538,80 +543,104 @@
return 0;
}
-int fdt_count_strings(const void *fdt, int node, const char *property)
+int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property)
{
- int length, i, count = 0;
- const char *list;
+ const char *list, *end;
+ int length, count = 0;
- list = fdt_getprop(fdt, node, property, &length);
+ list = fdt_getprop(fdt, nodeoffset, property, &length);
if (!list)
return length;
- for (i = 0; i < length; i++) {
- int len = strlen(list);
+ end = list + length;
- list += len + 1;
- i += len;
+ while (list < end) {
+ length = strnlen(list, end - list) + 1;
+
+ /* Abort if the last string isn't properly NUL-terminated. */
+ if (list + length > end)
+ return -FDT_ERR_BADVALUE;
+
+ list += length;
count++;
}
return count;
}
-int fdt_find_string(const void *fdt, int node, const char *property,
- const char *string)
+int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,
+ const char *string)
{
+ int length, len, idx = 0;
const char *list, *end;
- int len, index = 0;
- list = fdt_getprop(fdt, node, property, &len);
+ list = fdt_getprop(fdt, nodeoffset, property, &length);
if (!list)
- return len;
+ return length;
- end = list + len;
- len = strlen(string);
+ len = strlen(string) + 1;
+ end = list + length;
while (list < end) {
- int l = strlen(list);
+ length = strnlen(list, end - list) + 1;
- if (l == len && memcmp(list, string, len) == 0)
- return index;
+ /* Abort if the last string isn't properly NUL-terminated. */
+ if (list + length > end)
+ return -FDT_ERR_BADVALUE;
- list += l + 1;
- index++;
+ if (length == len && memcmp(list, string, length) == 0)
+ return idx;
+
+ list += length;
+ idx++;
}
return -FDT_ERR_NOTFOUND;
}
-int fdt_get_string_index(const void *fdt, int node, const char *property,
- int index, const char **output)
+const char *fdt_stringlist_get(const void *fdt, int nodeoffset,
+ const char *property, int idx,
+ int *lenp)
{
- const char *list;
- int length, i;
+ const char *list, *end;
+ int length;
- list = fdt_getprop(fdt, node, property, &length);
+ list = fdt_getprop(fdt, nodeoffset, property, &length);
+ if (!list) {
+ if (lenp)
+ *lenp = length;
- for (i = 0; i < length; i++) {
- int len = strlen(list);
+ return NULL;
+ }
- if (index == 0) {
- *output = list;
- return 0;
+ end = list + length;
+
+ while (list < end) {
+ length = strnlen(list, end - list) + 1;
+
+ /* Abort if the last string isn't properly NUL-terminated. */
+ if (list + length > end) {
+ if (lenp)
+ *lenp = -FDT_ERR_BADVALUE;
+
+ return NULL;
}
- list += len + 1;
- i += len;
- index--;
+ if (idx == 0) {
+ if (lenp)
+ *lenp = length - 1;
+
+ return list;
+ }
+
+ list += length;
+ idx--;
}
- return -FDT_ERR_NOTFOUND;
-}
+ if (lenp)
+ *lenp = -FDT_ERR_NOTFOUND;
-int fdt_get_string(const void *fdt, int node, const char *property,
- const char **output)
-{
- return fdt_get_string_index(fdt, node, property, 0, output);
+ return NULL;
}
int fdt_node_check_compatible(const void *fdt, int nodeoffset,
@@ -623,10 +652,8 @@
prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
if (!prop)
return len;
- if (fdt_stringlist_contains(prop, len, compatible))
- return 0;
- else
- return 1;
+
+ return !fdt_stringlist_contains(prop, len, compatible);
}
int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index e7321cc..87d4030 100644
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
@@ -60,6 +60,8 @@
if (((p + oldlen) < p) || ((p + oldlen) > end))
return -FDT_ERR_BADOFFSET;
+ if ((p < (char *)fdt) || ((end - oldlen + newlen) < (char *)fdt))
+ return -FDT_ERR_BADOFFSET;
if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt)))
return -FDT_ERR_NOSPACE;
memmove(p + newlen, p + oldlen, end - p - oldlen);
@@ -148,17 +150,13 @@
int fdt_del_mem_rsv(void *fdt, int n)
{
struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n);
- int err;
FDT_RW_CHECK_HEADER(fdt);
if (n >= fdt_num_mem_rsv(fdt))
return -FDT_ERR_NOTFOUND;
- err = _fdt_splice_mem_rsv(fdt, re, 1, 0);
- if (err)
- return err;
- return 0;
+ return _fdt_splice_mem_rsv(fdt, re, 1, 0);
}
static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name,
@@ -168,7 +166,7 @@
int err;
*prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
- if (!(*prop))
+ if (!*prop)
return oldlen;
if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
diff --git a/lib/libfdt/fdt_strerror.c b/lib/libfdt/fdt_strerror.c
index 3b7e168..7f8e02b 100644
--- a/lib/libfdt/fdt_strerror.c
+++ b/lib/libfdt/fdt_strerror.c
@@ -28,6 +28,7 @@
FDT_ERRTABENT(FDT_ERR_BADOFFSET),
FDT_ERRTABENT(FDT_ERR_BADPATH),
+ FDT_ERRTABENT(FDT_ERR_BADPHANDLE),
FDT_ERRTABENT(FDT_ERR_BADSTATE),
FDT_ERRTABENT(FDT_ERR_TRUNCATED),
@@ -35,6 +36,8 @@
FDT_ERRTABENT(FDT_ERR_BADVERSION),
FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE),
FDT_ERRTABENT(FDT_ERR_BADLAYOUT),
+ FDT_ERRTABENT(FDT_ERR_BADOVERLAY),
+ FDT_ERRTABENT(FDT_ERR_NOPHANDLES),
};
#define FDT_ERRTABSIZE (sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))
diff --git a/lib/libfdt/fdt_wip.c b/lib/libfdt/fdt_wip.c
index 216c512..45fb964 100644
--- a/lib/libfdt/fdt_wip.c
+++ b/lib/libfdt/fdt_wip.c
@@ -16,7 +16,7 @@
int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,
const char *name, int namelen,
- uint32_t index, const void *val,
+ uint32_t idx, const void *val,
int len)
{
void *propval;
@@ -27,10 +27,10 @@
if (!propval)
return proplen;
- if (proplen < (len + index))
+ if (proplen < (len + idx))
return -FDT_ERR_NOSPACE;
- memcpy(propval + index, val, len);
+ memcpy((char *)propval + idx, val, len);
return 0;
}
diff --git a/lib/libfdt/libfdt.swig b/lib/libfdt/libfdt.swig
index 14f583d..b24c72b 100644
--- a/lib/libfdt/libfdt.swig
+++ b/lib/libfdt/libfdt.swig
@@ -75,6 +75,14 @@
}
%}
+%typemap(in) (const void *) {
+ if (!PyByteArray_Check($input)) {
+ SWIG_exception_fail(SWIG_TypeError, "in method '" "$symname" "', argument "
+ "$argnum"" of type '" "$type""'");
+ }
+ $1 = (void *) PyByteArray_AsString($input);
+}
+
const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
int fdt_path_offset(const void *fdt, const char *path);
int fdt_first_property_offset(const void *fdt, int nodeoffset);
@@ -87,3 +95,19 @@
const char *fdt_string(const void *fdt, int stroffset);
int fdt_first_subnode(const void *fdt, int offset);
int fdt_next_subnode(const void *fdt, int offset);
+
+%typemap(in) (void *) {
+ if (!PyByteArray_Check($input)) {
+ SWIG_exception_fail(SWIG_TypeError, "in method '" "$symname" "', argument "
+ "$argnum"" of type '" "$type""'");
+ }
+ $1 = PyByteArray_AsString($input);
+}
+
+int fdt_delprop(void *fdt, int nodeoffset, const char *name);
+
+const char *fdt_strerror(int errval);
+int fdt_pack(void *fdt);
+
+int fdt_totalsize(const void *fdt);
+int fdt_off_dt_struct(const void *fdt);
diff --git a/lib/rsa/rsa-checksum.c b/lib/rsa/rsa-checksum.c
index 68d9d65..2bf28e2 100644
--- a/lib/rsa/rsa-checksum.c
+++ b/lib/rsa/rsa-checksum.c
@@ -8,135 +8,14 @@
#include <common.h>
#include <fdtdec.h>
#include <asm/byteorder.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/unaligned.h>
#include <hash.h>
#else
#include "fdt_host.h"
-#include <u-boot/sha1.h>
-#include <u-boot/sha256.h>
#endif
#include <u-boot/rsa.h>
-/* PKCS 1.5 paddings as described in the RSA PKCS#1 v2.1 standard. */
-
-const uint8_t padding_sha256_rsa2048[RSA2048_BYTES - SHA256_SUM_LEN] = {
-0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30,
-0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05,
-0x00, 0x04, 0x20
-};
-
-const uint8_t padding_sha1_rsa2048[RSA2048_BYTES - SHA1_SUM_LEN] = {
- 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x21, 0x30,
- 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, 0x02, 0x1a,
- 0x05, 0x00, 0x04, 0x14
-};
-
-const uint8_t padding_sha256_rsa4096[RSA4096_BYTES - SHA256_SUM_LEN] = {
- 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30,
- 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65,
- 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
-};
-
int hash_calculate(const char *name,
const struct image_region region[],
int region_count, uint8_t *checksum)
diff --git a/lib/rsa/rsa-mod-exp.c b/lib/rsa/rsa-mod-exp.c
index 4a6de2b..9d78aa1 100644
--- a/lib/rsa/rsa-mod-exp.c
+++ b/lib/rsa/rsa-mod-exp.c
@@ -9,7 +9,7 @@
#include <fdtdec.h>
#include <asm/types.h>
#include <asm/byteorder.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/types.h>
#include <asm/unaligned.h>
#else
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index c26f741..9a09280 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -244,7 +244,7 @@
ret = rsa_get_priv_key(info->keydir, info->keyname, &rsa);
if (ret)
goto err_priv;
- ret = rsa_sign_with_key(rsa, info->algo->checksum, region,
+ ret = rsa_sign_with_key(rsa, info->checksum, region,
region_count, sigp, sig_len);
if (ret)
goto err_sign;
@@ -508,7 +508,7 @@
}
if (!ret) {
ret = fdt_setprop_string(keydest, node, FIT_ALGO_PROP,
- info->algo->name);
+ info->name);
}
if (!ret && info->require_keys) {
ret = fdt_setprop_string(keydest, node, "required",
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index 60126d2..0d548f8 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -9,7 +9,7 @@
#include <fdtdec.h>
#include <asm/types.h>
#include <asm/byteorder.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/types.h>
#include <asm/unaligned.h>
#include <dm.h>
@@ -25,6 +25,40 @@
#define RSA_DEFAULT_PUBEXP 65537
/**
+ * rsa_verify_padding() - Verify RSA message padding is valid
+ *
+ * Verify a RSA message's padding is consistent with PKCS1.5
+ * padding as described in the RSA PKCS#1 v2.1 standard.
+ *
+ * @msg: Padded message
+ * @pad_len: Number of expected padding bytes
+ * @algo: Checksum algo structure having information on DER encoding etc.
+ * @return 0 on success, != 0 on failure
+ */
+static int rsa_verify_padding(const uint8_t *msg, const int pad_len,
+ struct checksum_algo *algo)
+{
+ int ff_len;
+ int ret;
+
+ /* first byte must be 0x00 */
+ ret = *msg++;
+ /* second byte must be 0x01 */
+ ret |= *msg++ ^ 0x01;
+ /* next ff_len bytes must be 0xff */
+ ff_len = pad_len - algo->der_len - 3;
+ ret |= *msg ^ 0xff;
+ ret |= memcmp(msg, msg+1, ff_len-1);
+ msg += ff_len;
+ /* next byte must be 0x00 */
+ ret |= *msg++;
+ /* next der_len bytes must match der_prefix */
+ ret |= memcmp(msg, algo->der_prefix, algo->der_len);
+
+ return ret;
+}
+
+/**
* rsa_verify_key() - Verify a signature against some data using RSA Key
*
* Verify a RSA PKCS1.5 signature against an expected hash using
@@ -34,14 +68,14 @@
* @sig: Signature
* @sig_len: Number of bytes in signature
* @hash: Pointer to the expected hash
- * @algo: Checksum algo structure having information on RSA padding etc.
+ * @key_len: Number of bytes in rsa key
+ * @algo: Checksum algo structure having information on DER encoding etc.
* @return 0 if verified, -ve on error
*/
static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig,
const uint32_t sig_len, const uint8_t *hash,
- struct checksum_algo *algo)
+ const uint32_t key_len, struct checksum_algo *algo)
{
- const uint8_t *padding;
int pad_len;
int ret;
#if !defined(USE_HOSTCC)
@@ -83,11 +117,11 @@
return ret;
}
- padding = algo->rsa_padding;
- pad_len = algo->pad_len - algo->checksum_len;
+ pad_len = key_len - algo->checksum_len;
/* Check pkcs1.5 padding bytes. */
- if (memcmp(buf, padding, pad_len)) {
+ ret = rsa_verify_padding(buf, pad_len, algo);
+ if (ret) {
debug("In RSAVerify(): Padding check failed!\n");
return -EINVAL;
}
@@ -149,7 +183,8 @@
return -EFAULT;
}
- ret = rsa_verify_key(&prop, sig, sig_len, hash, info->algo->checksum);
+ ret = rsa_verify_key(&prop, sig, sig_len, hash,
+ info->crypto->key_len, info->checksum);
return ret;
}
@@ -160,7 +195,7 @@
{
const void *blob = info->fdt_blob;
/* Reserve memory for maximum checksum-length */
- uint8_t hash[info->algo->checksum->pad_len];
+ uint8_t hash[info->crypto->key_len];
int ndepth, noffset;
int sig_node, node;
char name[100];
@@ -170,10 +205,10 @@
* Verify that the checksum-length does not exceed the
* rsa-signature-length
*/
- if (info->algo->checksum->checksum_len >
- info->algo->checksum->pad_len) {
+ if (info->checksum->checksum_len >
+ info->crypto->key_len) {
debug("%s: invlaid checksum-algorithm %s for %s\n",
- __func__, info->algo->checksum->name, info->algo->name);
+ __func__, info->checksum->name, info->crypto->name);
return -EINVAL;
}
@@ -184,7 +219,7 @@
}
/* Calculate checksum with checksum-algorithm */
- ret = info->algo->checksum->calculate(info->algo->checksum->name,
+ ret = info->checksum->calculate(info->checksum->name,
region, region_count, hash);
if (ret < 0) {
debug("%s: Error in checksum calculation\n", __func__);
diff --git a/lib/sha1.c b/lib/sha1.c
index 72c5dea..f54bb5b 100644
--- a/lib/sha1.c
+++ b/lib/sha1.c
@@ -26,6 +26,11 @@
#include <watchdog.h>
#include <u-boot/sha1.h>
+const uint8_t sha1_der_prefix[SHA1_DER_LEN] = {
+ 0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e,
+ 0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14
+};
+
/*
* 32-bit integer manipulation macros (big endian)
*/
diff --git a/lib/sha256.c b/lib/sha256.c
index bb338ba..7f5a361 100644
--- a/lib/sha256.c
+++ b/lib/sha256.c
@@ -15,6 +15,12 @@
#include <watchdog.h>
#include <u-boot/sha256.h>
+const uint8_t sha256_der_prefix[SHA256_DER_LEN] = {
+ 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
+ 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05,
+ 0x00, 0x04, 0x20
+};
+
/*
* 32-bit integer manipulation macros (big endian)
*/
diff --git a/lib/smbios.c b/lib/smbios.c
new file mode 100644
index 0000000..ce1974d
--- /dev/null
+++ b/lib/smbios.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Adapted from coreboot src/arch/x86/smbios.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <smbios.h>
+#include <tables_csum.h>
+#include <version.h>
+#ifdef CONFIG_CPU
+#include <cpu.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * smbios_add_string() - add a string to the string area
+ *
+ * This adds a string to the string area which is appended directly after
+ * the formatted portion of an SMBIOS structure.
+ *
+ * @start: string area start address
+ * @str: string to add
+ * @return: string number in the string area
+ */
+static int smbios_add_string(char *start, const char *str)
+{
+ int i = 1;
+ char *p = start;
+
+ for (;;) {
+ if (!*p) {
+ strcpy(p, str);
+ p += strlen(str);
+ *p++ = '\0';
+ *p++ = '\0';
+
+ return i;
+ }
+
+ if (!strcmp(p, str))
+ return i;
+
+ p += strlen(p) + 1;
+ i++;
+ }
+}
+
+/**
+ * smbios_string_table_len() - compute the string area size
+ *
+ * This computes the size of the string area including the string terminator.
+ *
+ * @start: string area start address
+ * @return: string area size
+ */
+static int smbios_string_table_len(char *start)
+{
+ char *p = start;
+ int i, len = 0;
+
+ while (*p) {
+ i = strlen(p) + 1;
+ p += i;
+ len += i;
+ }
+
+ return len + 1;
+}
+
+static int smbios_write_type0(uintptr_t *current, int handle)
+{
+ struct smbios_type0 *t = (struct smbios_type0 *)*current;
+ int len = sizeof(struct smbios_type0);
+
+ memset(t, 0, sizeof(struct smbios_type0));
+ fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, handle);
+ t->vendor = smbios_add_string(t->eos, "U-Boot");
+ t->bios_ver = smbios_add_string(t->eos, PLAIN_VERSION);
+ t->bios_release_date = smbios_add_string(t->eos, U_BOOT_DMI_DATE);
+#ifdef CONFIG_ROM_SIZE
+ t->bios_rom_size = (CONFIG_ROM_SIZE / 65536) - 1;
+#endif
+ t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED |
+ BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
+ BIOS_CHARACTERISTICS_UPGRADEABLE;
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+ t->bios_characteristics_ext1 = BIOS_CHARACTERISTICS_EXT1_ACPI;
+#endif
+#ifdef CONFIG_EFI_LOADER
+ t->bios_characteristics_ext1 |= BIOS_CHARACTERISTICS_EXT1_UEFI;
+#endif
+ t->bios_characteristics_ext2 = BIOS_CHARACTERISTICS_EXT2_TARGET;
+
+ t->bios_major_release = 0xff;
+ t->bios_minor_release = 0xff;
+ t->ec_major_release = 0xff;
+ t->ec_minor_release = 0xff;
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+
+ return len;
+}
+
+static int smbios_write_type1(uintptr_t *current, int handle)
+{
+ struct smbios_type1 *t = (struct smbios_type1 *)*current;
+ int len = sizeof(struct smbios_type1);
+ char *serial_str = getenv("serial#");
+
+ memset(t, 0, sizeof(struct smbios_type1));
+ fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
+ t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+ t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
+ if (serial_str) {
+ strncpy((char*)t->uuid, serial_str, sizeof(t->uuid));
+ t->serial_number = smbios_add_string(t->eos, serial_str);
+ }
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+
+ return len;
+}
+
+static int smbios_write_type2(uintptr_t *current, int handle)
+{
+ struct smbios_type2 *t = (struct smbios_type2 *)*current;
+ int len = sizeof(struct smbios_type2);
+
+ memset(t, 0, sizeof(struct smbios_type2));
+ fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
+ t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+ t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
+ t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
+ t->board_type = SMBIOS_BOARD_MOTHERBOARD;
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+
+ return len;
+}
+
+static int smbios_write_type3(uintptr_t *current, int handle)
+{
+ struct smbios_type3 *t = (struct smbios_type3 *)*current;
+ int len = sizeof(struct smbios_type3);
+
+ memset(t, 0, sizeof(struct smbios_type3));
+ fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle);
+ t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+ t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP;
+ t->bootup_state = SMBIOS_STATE_SAFE;
+ t->power_supply_state = SMBIOS_STATE_SAFE;
+ t->thermal_state = SMBIOS_STATE_SAFE;
+ t->security_status = SMBIOS_SECURITY_NONE;
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+
+ return len;
+}
+
+static void smbios_write_type4_dm(struct smbios_type4 *t)
+{
+ u16 processor_family = SMBIOS_PROCESSOR_FAMILY_UNKNOWN;
+ const char *vendor = "Unknown";
+ const char *name = "Unknown";
+
+#ifdef CONFIG_CPU
+ char processor_name[49];
+ char vendor_name[49];
+ struct udevice *dev = NULL;
+
+ uclass_find_first_device(UCLASS_CPU, &dev);
+ if (dev) {
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+ if (plat->family)
+ processor_family = plat->family;
+ t->processor_id[0] = plat->id[0];
+ t->processor_id[1] = plat->id[1];
+
+ if (!cpu_get_vendor(dev, vendor_name, sizeof(vendor_name)))
+ vendor = vendor_name;
+ if (!cpu_get_desc(dev, processor_name, sizeof(processor_name)))
+ name = processor_name;
+ }
+#endif
+
+ t->processor_family = processor_family;
+ t->processor_manufacturer = smbios_add_string(t->eos, vendor);
+ t->processor_version = smbios_add_string(t->eos, name);
+}
+
+static int smbios_write_type4(uintptr_t *current, int handle)
+{
+ struct smbios_type4 *t = (struct smbios_type4 *)*current;
+ int len = sizeof(struct smbios_type4);
+
+ memset(t, 0, sizeof(struct smbios_type4));
+ fill_smbios_header(t, SMBIOS_PROCESSOR_INFORMATION, len, handle);
+ t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
+ smbios_write_type4_dm(t);
+ t->status = SMBIOS_PROCESSOR_STATUS_ENABLED;
+ t->processor_upgrade = SMBIOS_PROCESSOR_UPGRADE_NONE;
+ t->l1_cache_handle = 0xffff;
+ t->l2_cache_handle = 0xffff;
+ t->l3_cache_handle = 0xffff;
+ t->processor_family2 = t->processor_family;
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+
+ return len;
+}
+
+static int smbios_write_type32(uintptr_t *current, int handle)
+{
+ struct smbios_type32 *t = (struct smbios_type32 *)*current;
+ int len = sizeof(struct smbios_type32);
+
+ memset(t, 0, sizeof(struct smbios_type32));
+ fill_smbios_header(t, SMBIOS_SYSTEM_BOOT_INFORMATION, len, handle);
+
+ *current += len;
+
+ return len;
+}
+
+static int smbios_write_type127(uintptr_t *current, int handle)
+{
+ struct smbios_type127 *t = (struct smbios_type127 *)*current;
+ int len = sizeof(struct smbios_type127);
+
+ memset(t, 0, sizeof(struct smbios_type127));
+ fill_smbios_header(t, SMBIOS_END_OF_TABLE, len, handle);
+
+ *current += len;
+
+ return len;
+}
+
+static smbios_write_type smbios_write_funcs[] = {
+ smbios_write_type0,
+ smbios_write_type1,
+ smbios_write_type2,
+ smbios_write_type3,
+ smbios_write_type4,
+ smbios_write_type32,
+ smbios_write_type127
+};
+
+uintptr_t write_smbios_table(uintptr_t addr)
+{
+ struct smbios_entry *se;
+ u32 tables;
+ int len = 0;
+ int max_struct_size = 0;
+ int handle = 0;
+ char *istart;
+ int isize;
+ int i;
+
+ /* 16 byte align the table address */
+ addr = ALIGN(addr, 16);
+
+ se = (struct smbios_entry *)addr;
+ memset(se, 0, sizeof(struct smbios_entry));
+
+ addr += sizeof(struct smbios_entry);
+ addr = ALIGN(addr, 16);
+ tables = addr;
+
+ /* populate minimum required tables */
+ for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) {
+ int tmp = smbios_write_funcs[i](&addr, handle++);
+ max_struct_size = max(max_struct_size, tmp);
+ len += tmp;
+ }
+
+ memcpy(se->anchor, "_SM_", 4);
+ se->length = sizeof(struct smbios_entry);
+ se->major_ver = SMBIOS_MAJOR_VER;
+ se->minor_ver = SMBIOS_MINOR_VER;
+ se->max_struct_size = max_struct_size;
+ memcpy(se->intermediate_anchor, "_DMI_", 5);
+ se->struct_table_length = len;
+ se->struct_table_address = tables;
+ se->struct_count = handle;
+
+ /* calculate checksums */
+ istart = (char *)se + SMBIOS_INTERMEDIATE_OFFSET;
+ isize = sizeof(struct smbios_entry) - SMBIOS_INTERMEDIATE_OFFSET;
+ se->intermediate_checksum = table_compute_checksum(istart, isize);
+ se->checksum = table_compute_checksum(se, sizeof(struct smbios_entry));
+
+ return addr;
+}
diff --git a/lib/strto.c b/lib/strto.c
index a6c0157..e93a4f5 100644
--- a/lib/strto.c
+++ b/lib/strto.c
@@ -160,9 +160,11 @@
if (!end)
end = str + strlen(str);
- for (p = end - 1; p > str; p--) {
- if (!isdigit(*p))
- return simple_strtoul(p + 1, NULL, 10);
+ if (isdigit(end[-1])) {
+ for (p = end - 1; p > str; p--) {
+ if (!isdigit(*p))
+ return simple_strtoul(p + 1, NULL, 10);
+ }
}
return -1;
diff --git a/lib/tables_csum.c b/lib/tables_csum.c
new file mode 100644
index 0000000..340d7b3
--- /dev/null
+++ b/lib/tables_csum.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/ctype.h>
+
+u8 table_compute_checksum(void *v, int len)
+{
+ u8 *bytes = v;
+ u8 checksum = 0;
+ int i;
+
+ for (i = 0; i < len; i++)
+ checksum -= bytes[i];
+
+ return checksum;
+}
diff --git a/net/Kconfig b/net/Kconfig
index c393269..414c549 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -45,7 +45,4 @@
default "U-Boot.arm" if ARM
default "U-Boot"
-config SPL_NET_VCI_STRING
- string
-
endif # if NET
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index c15cc4d..1d13011 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -227,6 +227,7 @@
case env_op_create:
case env_op_overwrite:
eth_parse_enetaddr(value, pdata->enetaddr);
+ eth_write_hwaddr(dev);
break;
case env_op_delete:
memset(pdata->enetaddr, 0, 6);
@@ -511,7 +512,8 @@
eth_setenv_enetaddr_by_index("eth", dev->seq, pdata->enetaddr);
printf("\nWarning: %s using MAC address from ROM\n",
dev->name);
- } else if (is_zero_ethaddr(pdata->enetaddr)) {
+ } else if (is_zero_ethaddr(pdata->enetaddr) ||
+ !is_valid_ethaddr(pdata->enetaddr)) {
#ifdef CONFIG_NET_RANDOM_ETHADDR
net_random_ethaddr(pdata->enetaddr);
printf("\nWarning: %s (eth%d) using random MAC address - %pM\n",
diff --git a/net/eth_legacy.c b/net/eth_legacy.c
index bdcd6ea..1354f49 100644
--- a/net/eth_legacy.c
+++ b/net/eth_legacy.c
@@ -11,7 +11,7 @@
#include <environment.h>
#include <net.h>
#include <phy.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "eth_internal.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -118,6 +118,7 @@
case env_op_create:
case env_op_overwrite:
eth_parse_enetaddr(value, dev->enetaddr);
+ eth_write_hwaddr(dev, "eth", dev->index);
break;
case env_op_delete:
memset(dev->enetaddr, 0, 6);
diff --git a/net/fastboot.c b/net/fastboot.c
index a5d059b..aff7fd7 100644
--- a/net/fastboot.c
+++ b/net/fastboot.c
@@ -289,7 +289,7 @@
dev_desc = blk_get_dev("mmc", 0);
if (dev_desc == NULL) {
write_fb_response("FAIL", "block device not found", response);
- } else if (part_get_info_efi_by_name(dev_desc, part_name, &part_info) < 0) {
+ } else if (part_get_info_by_name(dev_desc, part_name, &part_info) < 0) {
write_fb_response("FAIL", "partition not found", response);
} else {
write_fb_response("OKAY", (char*)part_info.type, response);
diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index d512fa5..89725fa 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -234,7 +234,7 @@
hi = (temp64>>32) & 0xffffffff;
lo = temp64 & 0xffffffff;
- post_log("Memory (date line) error at %08x, "
+ post_log("Memory (data line) error at %08x, "
"wrote %08x%08x, read %08x%08x !\n",
pmem, pathi, patlo, hi, lo);
ret = -1;
diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf
index 01a739d..2f85eb9 100644
--- a/scripts/Makefile.autoconf
+++ b/scripts/Makefile.autoconf
@@ -46,7 +46,7 @@
-MQ include/config/auto.conf $(srctree)/include/common.h > $@ || { \
rm $@; false; \
}
-include/autoconf.mk.dep: FORCE
+include/autoconf.mk.dep: include/config.h FORCE
$(call cmd,autoconf_dep)
# We are migrating from board headers to Kconfig little by little.
@@ -58,32 +58,44 @@
# same CONFIG macros
quiet_cmd_autoconf = GEN $@
cmd_autoconf = \
- $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \
- sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp | \
+ sed -n -f $(srctree)/tools/scripts/define2mk.sed $< | \
while read line; do \
if [ -n "${KCONFIG_IGNORE_DUPLICATES}" ] || \
! grep -q "$${line%=*}=" include/config/auto.conf; then \
echo "$$line"; \
fi \
- done > $@; \
- rm $@.tmp; \
- } || { \
- rm $@.tmp; false; \
+ done > $@
+
+quiet_cmd_u_boot_cfg = CFG $@
+ cmd_u_boot_cfg = \
+ $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \
+ grep 'define CONFIG_' $@.tmp > $@; \
+ rm $@.tmp; \
+ } || { \
+ rm $@.tmp; false; \
}
-include/autoconf.mk: FORCE
+u-boot.cfg: include/config.h FORCE
+ $(call cmd,u_boot_cfg)
+
+spl/u-boot.cfg: include/config.h FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call cmd,u_boot_cfg,-DCONFIG_SPL_BUILD)
+
+tpl/u-boot.cfg: include/config.h FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call cmd,u_boot_cfg,-DCONFIG_SPL_BUILD -DCONFIG_TPL_BUILD)
+
+include/autoconf.mk: u-boot.cfg
$(call cmd,autoconf)
-spl/include/autoconf.mk: FORCE
+spl/include/autoconf.mk: spl/u-boot.cfg
$(Q)mkdir -p $(dir $@)
- $(call cmd,autoconf,-DCONFIG_SPL_BUILD)
+ $(call cmd,autoconf)
-tpl/include/autoconf.mk: FORCE
+tpl/include/autoconf.mk: tpl/u-boot.cfg
$(Q)mkdir -p $(dir $@)
- $(call cmd,autoconf,-DCONFIG_SPL_BUILD -DCONFIG_TPL_BUILD)
-
-include/autoconf.mk include/autoconf.mk.dep \
- spl/include/autoconf.mk tpl/include/autoconf.mk: include/config.h
+ $(call cmd,autoconf)
# include/config.h
# Prior to Kconfig, it was generated by mkconfig. Now it is created here.
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 45a0e1d..13c975b 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -164,10 +164,30 @@
ld_flags = $(LDFLAGS) $(ldflags-y)
+dts_dir = $(srctree)/arch/$(ARCH)/dts
+
+# Try these files in order to find the U-Boot-specific .dtsi include file
+u_boot_dtsi_options = $(wildcard $(dts_dir)/$(basename $(notdir $<))-u-boot.dtsi) \
+ $(wildcard $(dts_dir)/$(subst $\",,$(CONFIG_SYS_SOC))-u-boot.dtsi) \
+ $(wildcard $(dts_dir)/$(subst $\",,$(CONFIG_SYS_CPU))-u-boot.dtsi) \
+ $(wildcard $(dts_dir)/$(subst $\",,$(CONFIG_SYS_VENDOR))-u-boot.dtsi) \
+ $(wildcard $(dts_dir)/u-boot.dtsi)
+
+# Uncomment for debugging
+# $(warning u_boot_dtsi_options: $(u_boot_dtsi_options))
+
+# We use the first match
+u_boot_dtsi = $(firstword $(u_boot_dtsi_options))
+
# Modified for U-Boot
dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \
-I$(srctree)/arch/$(ARCH)/dts \
-I$(srctree)/arch/$(ARCH)/dts/include \
+ -Iinclude \
+ -I$(srctree)/include \
+ -I$(srctree)/arch/$(ARCH)/include \
+ -include $(srctree)/include/linux/kconfig.h \
+ -D__ASSEMBLY__ \
-undef -D__DTS__
# Finds the multi-part object the current object will be linked into
@@ -288,8 +308,11 @@
quiet_cmd_dtc = DTC $@
# Modified for U-Boot
+# Bring in any U-Boot-specific include after the '/dts-v1/;' header
cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
- $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+ cat $< $(if $(u_boot_dtsi),\
+ | sed 's%^/ {$$%\#include \"$(u_boot_dtsi)\"\n&%') | \
+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; \
$(DTC) -O dtb -o $@ -b 0 \
-i $(dir $<) $(DTC_FLAGS) \
-d $(depfile).dtc.tmp $(dtc-tmp) ; \
@@ -321,6 +344,39 @@
$(obj)/%.S: $(src)/%.ttf
$(call cmd,S_ttf)
+# EFI Hello World application
+# ---------------------------------------------------------------------------
+
+# Generate an assembly file to wrap the EFI app
+cmd_S_efi= \
+( \
+ echo '.section .rodata.efi.init,"a"'; \
+ echo '.balign 16'; \
+ echo '.global __efi_hello_world_begin'; \
+ echo '__efi_hello_world_begin:'; \
+ echo '.incbin "$<" '; \
+ echo '__efi_hello_world_end:'; \
+ echo '.global __efi_hello_world_end'; \
+ echo '.balign 16'; \
+) > $@
+
+$(obj)/%_efi.S: $(obj)/%.efi
+ $(call cmd,S_efi)
+
+$(obj)/%.efi: $(obj)/%.so
+ $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j .dynamic \
+ -j .dynsym -j .rel* -j .rela* -j .reloc \
+ $(if $(EFI_TARGET),$(EFI_TARGET),-O binary) $^ $@
+
+EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS)
+
+$(obj)/helloworld.so: $(EFI_LDS_PATH)
+
+$(obj)/helloworld.so: $(obj)/helloworld.o arch/$(ARCH)/lib/$(EFI_CRT0) \
+ arch/$(ARCH)/lib/$(EFI_RELOC)
+ $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared -Bsymbolic \
+ $^ -o $@
+
# ACPI
# ---------------------------------------------------------------------------
quiet_cmd_acpi_c_asl= ASL $<
@@ -431,6 +487,7 @@
#
# mkimage
# ---------------------------------------------------------------------------
+MKIMAGEOUTPUT ?= /dev/null
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+ $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 3ba9742..c962bbc 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -54,12 +54,21 @@
libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/
libs-y += common/init/
+
+# Special handling for a few options which support SPL/TPL
+ifeq ($(CONFIG_TPL_BUILD),y)
+libs-$(CONFIG_TPL_LIBCOMMON_SUPPORT) += common/ cmd/
+libs-$(CONFIG_TPL_LIBGENERIC_SUPPORT) += lib/
+else
libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ cmd/
+libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
+endif
+
libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/
libs-y += drivers/
+libs-$(CONFIG_SPL_USB_GADGET_SUPPORT) += drivers/usb/dwc3/
libs-y += dts/
libs-y += fs/
-libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
libs-$(CONFIG_SPL_NET_SUPPORT) += net/
@@ -110,9 +119,11 @@
$(shell $(LD) --version | \
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
+MKIMAGEOUTPUT ?= /dev/null
+
quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+ $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
MKIMAGEFLAGS_MLO = -T omapimage -a $(CONFIG_SPL_TEXT_BASE)
@@ -134,17 +145,17 @@
$(call if_changed,mkimage)
else
ifdef CONFIG_ARCH_ZYNQ
-MKIMAGEFLAGS_boot.bin = -T zynqimage
+MKIMAGEFLAGS_boot.bin = -T zynqimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
endif
ifdef CONFIG_ARCH_ZYNQMP
-MKIMAGEFLAGS_boot.bin = -T zynqmpimage
+MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
endif
spl/boot.bin: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
endif
-ALL-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).cfg
+ALL-y += $(obj)/$(SPL_BIN).bin
ifdef CONFIG_SAMSUNG
ALL-y += $(obj)/$(BOARD)-spl.bin
@@ -154,7 +165,7 @@
ALL-y += $(obj)/$(SPL_BIN).sfp
endif
-ifdef CONFIG_SUNXI
+ifdef CONFIG_ARCH_SUNXI
ALL-y += $(obj)/sunxi-spl.bin
endif
@@ -204,13 +215,6 @@
$(obj)/$(SPL_BIN).dtb: dts/dt.dtb $(objtree)/tools/fdtgrep FORCE
$(call if_changed,fdtgrep)
-quiet_cmd_cpp_cfg = CFG $@
-cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
- -DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $<
-
-$(obj)/$(SPL_BIN).cfg: include/config.h FORCE
- $(call if_changed,cpp_cfg)
-
pythonpath = PYTHONPATH=tools
quiet_cmd_dtocc = DTOC C $@
diff --git a/scripts/build-whitelist.sh b/scripts/build-whitelist.sh
new file mode 100755
index 0000000..f169eaa
--- /dev/null
+++ b/scripts/build-whitelist.sh
@@ -0,0 +1,62 @@
+#!/bin/sh
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+# This script creates the configuration whitelist file. This file contains
+# all the config options which are allowed to be used outside Kconfig.
+# Please do not add things to the whitelist. Instead, add your new option
+# to Kconfig.
+#
+export LC_ALL=C LC_COLLATE=C
+
+# There are two independent greps. The first pulls out the component parts
+# of CONFIG_SYS_EXTRA_OPTIONS. An example is:
+#
+# SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)
+#
+# We want this to produce:
+# CONFIG_SUNXI_GMAC
+# CONFIG_AHCI
+# CONFIG_SATAPWR
+#
+# The second looks for the rest of the CONFIG options, but excludes those in
+# Kconfig and defconfig files.
+#
+(
+git grep CONFIG_SYS_EXTRA_OPTIONS |sed -n \
+ 's/.*CONFIG_SYS_EXTRA_OPTIONS="\(.*\)"/\1/ p' \
+ | tr , '\n' \
+ | sed 's/ *\([A-Za-z0-9_]*\).*/CONFIG_\1/'
+
+git grep CONFIG_ | \
+ egrep -vi "(Kconfig:|defconfig:|README|\.py|\.pl:)" \
+ | tr ' \t' '\n\n' \
+ | sed -n 's/^\(CONFIG_[A-Za-z0-9_]*\).*/\1/p'
+) \
+ |sort |uniq >scripts/config_whitelist.txt.tmp1;
+
+# Finally, we need a list of the valid Kconfig options to exclude these from
+# the whitelist.
+cat `find . -name "Kconfig*"` |sed -n \
+ -e 's/^config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
+ -e 's/^menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
+ |sort |uniq >scripts/config_whitelist.txt.tmp2
+
+# Use only the options that are present in the first file but not the second.
+comm -23 scripts/config_whitelist.txt.tmp1 scripts/config_whitelist.txt.tmp2 \
+ |sort |uniq >scripts/config_whitelist.txt.tmp3
+
+# If scripts/config_whitelist.txt already exists, take the intersection of the
+# current list and the new one. We do not want to increase whitelist options.
+if [ -r scripts/config_whitelist.txt ]; then
+ comm -12 scripts/config_whitelist.txt.tmp3 scripts/config_whitelist.txt \
+ > scripts/config_whitelist.txt.tmp4
+ mv scripts/config_whitelist.txt.tmp4 scripts/config_whitelist.txt
+else
+ mv scripts/config_whitelist.txt.tmp3 scripts/config_whitelist.txt
+fi
+
+rm scripts/config_whitelist.txt.tmp*
+
+unset LC_ALL LC_COLLATE
diff --git a/scripts/check-config.sh b/scripts/check-config.sh
new file mode 100755
index 0000000..6618dfb
--- /dev/null
+++ b/scripts/check-config.sh
@@ -0,0 +1,50 @@
+#!/bin/sh
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Check that the u-boot.cfg file provided does not introduce any new
+# ad-hoc CONFIG options
+#
+# Use scripts/build-whitelist.sh to generate the list of current ad-hoc
+# CONFIG options (those which are not in Kconfig).
+
+# Usage
+# check-config.sh <path to u-boot.cfg> <path to whitelist file> <source dir>
+#
+# For example:
+# scripts/check-config.sh b/chromebook_link/u-boot.cfg kconfig_whitelist.txt .
+
+path="$1"
+whitelist="$2"
+srctree="$3"
+
+# Temporary files
+configs="${path}.configs"
+suspects="${path}.suspects"
+ok="${path}.ok"
+new_adhoc="${path}.adhoc"
+
+export LC_ALL=C
+export LC_COLLATE=C
+
+cat ${path} |sed -n 's/^#define \(CONFIG_[A-Za-z0-9_]*\).*/\1/p' |sort |uniq \
+ >${configs}
+
+comm -23 ${configs} ${whitelist} > ${suspects}
+
+cat `find ${srctree} -name "Kconfig*"` |sed -n \
+ -e 's/^config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
+ -e 's/^menuconfig \([A-Za-z0-9_]*\).*$/CONFIG_\1/p' |sort |uniq > ${ok}
+comm -23 ${suspects} ${ok} >${new_adhoc}
+if [ -s ${new_adhoc} ]; then
+ echo "Error: You must add new CONFIG options using Kconfig"
+ echo "The following new ad-hoc CONFIG options were detected:"
+ cat ${new_adhoc}
+ echo
+ echo "Please add these via Kconfig instead. Find a suitable Kconfig"
+ echo "file and add a 'config' or 'menuconfig' option."
+ # Don't delete the temporary files in case they are useful
+ exit 1
+else
+ rm ${suspects} ${ok} ${new_adhoc}
+fi
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 24831b3..84f5756 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -4263,7 +4263,7 @@
}
}
-# check for case / default statements not preceeded by break/fallthrough/switch
+# check for case / default statements not preceded by break/fallthrough/switch
if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) {
my $has_break = 0;
my $has_statement = 0;
@@ -4284,7 +4284,7 @@
}
if (!$has_break && $has_statement) {
WARN("MISSING_BREAK",
- "Possible switch case/default not preceeded by break or fallthrough comment\n" . $herecurr);
+ "Possible switch case/default not preceded by break or fallthrough comment\n" . $herecurr);
}
}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
new file mode 100644
index 0000000..00ee3f1
--- /dev/null
+++ b/scripts/config_whitelist.txt
@@ -0,0 +1,8047 @@
+CONFIG_16BIT
+CONFIG_33
+CONFIG_400MHZ_MODE
+CONFIG_405
+CONFIG_405EP
+CONFIG_405EX
+CONFIG_405EX_CHIP21_ECID3_REV_D
+CONFIG_405EX_CHIP21_PVR_REV_C
+CONFIG_405EX_CHIP21_PVR_REV_D
+CONFIG_405EZ
+CONFIG_405GP
+CONFIG_440
+CONFIG_440EP
+CONFIG_440EPX
+CONFIG_440GP
+CONFIG_440GR
+CONFIG_440GRX
+CONFIG_440GX
+CONFIG_440SP
+CONFIG_440SPE
+CONFIG_440SPE_REVA
+CONFIG_440_GX
+CONFIG_4430SDP
+CONFIG_460EX
+CONFIG_460GT
+CONFIG_460SX
+CONFIG_4xx_CONFIG_BLOCKSIZE
+CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR
+CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET
+CONFIG_4xx_DCACHE
+CONFIG_521X
+CONFIG_533MHZ_MODE
+CONFIG_5xx_CONS_SCI1
+CONFIG_5xx_CONS_SCI2
+CONFIG_5xx_GCLK_FREQ
+CONFIG_64BIT_PHYS_ADDR
+CONFIG_66
+CONFIG_8260_CLKIN
+CONFIG_8349_CLKIN
+CONFIG_83XX
+CONFIG_83XX_CLKIN
+CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
+CONFIG_83XX_PCICLK
+CONFIG_83XX_PCI_STREAMING
+CONFIG_88F5182
+CONFIG_8xx_CONS_NONE
+CONFIG_8xx_CONS_SCCx
+CONFIG_8xx_CONS_SMC1
+CONFIG_8xx_CONS_SMC2
+CONFIG_8xx_CONS_SMCx
+CONFIG_8xx_CPUCLK_DEFAULT
+CONFIG_8xx_GCLK_FREQ
+CONFIG_8xx_OSCLK
+CONFIG_A003399_NOR_WORKAROUND
+CONFIG_A008044_WORKAROUND
+CONFIG_A3M071
+CONFIG_A4M072
+CONFIG_A4M2K
+CONFIG_AC14XX
+CONFIG_ACADIA
+CONFIG_ACX517AKN
+CONFIG_ACX544AKN
+CONFIG_ADCIOP
+CONFIG_ADDMISC
+CONFIG_ADDRESS
+CONFIG_ADDR_AUTO_INCR_BIT
+CONFIG_ADDR_MAP
+CONFIG_ADDR_STREAMING
+CONFIG_ADI_GPIO1
+CONFIG_ADI_GPIO2
+CONFIG_ADNPESC1
+CONFIG_ADP_AG101P
+CONFIG_AEABI
+CONFIG_AEMIF_CNTRL_BASE
+CONFIG_AES
+CONFIG_ALTERA_SDRAM
+CONFIG_ALTERA_SPI_IDLE_VAL
+CONFIG_ALTIVEC
+CONFIG_ALT_LB_ADDR
+CONFIG_ALT_LH_ADDR
+CONFIG_ALU
+CONFIG_AM335X_LCD
+CONFIG_AM335X_USB0
+CONFIG_AM335X_USB0_MODE
+CONFIG_AM335X_USB1
+CONFIG_AM335X_USB1_MODE
+CONFIG_AM437X_USB2PHY2_HOST
+CONFIG_AMBAPP_IOAREA
+CONFIG_AMCC_DEF_ENV
+CONFIG_AMCC_DEF_ENV_NOR_UPD
+CONFIG_AMCC_DEF_ENV_POWERPC
+CONFIG_AMCC_DEF_ENV_PPC
+CONFIG_AMCC_DEF_ENV_PPC_OLD
+CONFIG_AMCC_DEF_ENV_ROOTPATH
+CONFIG_AMCORE
+CONFIG_AMIGA_PARTITION
+CONFIG_ANDES_PCU
+CONFIG_ANDES_PCU_BASE
+CONFIG_AP325RXA
+CONFIG_APBH_DMA
+CONFIG_APBH_DMA_BURST
+CONFIG_APBH_DMA_BURST8
+CONFIG_APER_0_BASE
+CONFIG_APER_1_BASE
+CONFIG_APER_SIZE
+CONFIG_API
+CONFIG_APUS_FAST_EXCEPT
+CONFIG_AP_SH4A_4A
+CONFIG_ARCH_AAED2000
+CONFIG_ARCH_ADI_COYOTE
+CONFIG_ARCH_ADPAG101P
+CONFIG_ARCH_AT91RM9200DK
+CONFIG_ARCH_AUTCPU12
+CONFIG_ARCH_BAST
+CONFIG_ARCH_CATS
+CONFIG_ARCH_CDB89712
+CONFIG_ARCH_CEIVA
+CONFIG_ARCH_CLEP7212
+CONFIG_ARCH_CPU_INIT
+CONFIG_ARCH_CSB226
+CONFIG_ARCH_DMA_PIO_WORDS
+CONFIG_ARCH_EARLY_INIT_R
+CONFIG_ARCH_EBSA110
+CONFIG_ARCH_EBSA285
+CONFIG_ARCH_EDB7211
+CONFIG_ARCH_ENP2611
+CONFIG_ARCH_FORTUNET
+CONFIG_ARCH_GUMSTIX
+CONFIG_ARCH_H1940
+CONFIG_ARCH_H5400
+CONFIG_ARCH_H7201
+CONFIG_ARCH_H7202
+CONFIG_ARCH_HAS_ILOG2_U32
+CONFIG_ARCH_HAS_ILOG2_U64
+CONFIG_ARCH_INNOKOM
+CONFIG_ARCH_IQ31244
+CONFIG_ARCH_IQ80321
+CONFIG_ARCH_IQ80331
+CONFIG_ARCH_IXCDP1100
+CONFIG_ARCH_IXDP2400
+CONFIG_ARCH_IXDP2401
+CONFIG_ARCH_IXDP2800
+CONFIG_ARCH_IXDP2801
+CONFIG_ARCH_IXDP425
+CONFIG_ARCH_KIRKWOOD
+CONFIG_ARCH_KS8695
+CONFIG_ARCH_L7200
+CONFIG_ARCH_LUBBOCK
+CONFIG_ARCH_MAP_SYSMEM
+CONFIG_ARCH_MISC_INIT
+CONFIG_ARCH_MX1ADS
+CONFIG_ARCH_NETWINDER
+CONFIG_ARCH_OMAP4
+CONFIG_ARCH_ORION5X
+CONFIG_ARCH_P720T
+CONFIG_ARCH_PERSONAL_SERVER
+CONFIG_ARCH_PLEB
+CONFIG_ARCH_PXA_CERF
+CONFIG_ARCH_PXA_IDP
+CONFIG_ARCH_RMOBILE_BOARD_STRING
+CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
+CONFIG_ARCH_RPC
+CONFIG_ARCH_S3C2440
+CONFIG_ARCH_SHARK
+CONFIG_ARCH_TEGRA
+CONFIG_ARCH_USE_BUILTIN_BSWAP
+CONFIG_ARCH_VERSATILE_PB
+CONFIG_ARCH_VIPER
+CONFIG_ARC_MMU_VER
+CONFIG_ARC_SERIAL
+CONFIG_ARC_UART_BASE
+CONFIG_ARIA
+CONFIG_ARIA_FPGA
+CONFIG_ARM926EJS
+CONFIG_ARMADA100
+CONFIG_ARMADA100_FEC
+CONFIG_ARMADA168
+CONFIG_ARMADA_39X
+CONFIG_ARMCORTEXA9
+CONFIG_ARMV7_PSCI_1_0
+CONFIG_ARMV7_SECURE_BASE
+CONFIG_ARMV7_SECURE_MAX_SIZE
+CONFIG_ARMV7_SECURE_RESERVE_SIZE
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+CONFIG_ARMV8_SWITCH_TO_EL1
+CONFIG_ARM_ARCH_CP15_ERRATA
+CONFIG_ARM_ASM_UNIFIED
+CONFIG_ARM_DCC
+CONFIG_ARM_ERRATA_430973
+CONFIG_ARM_ERRATA_454179
+CONFIG_ARM_ERRATA_621766
+CONFIG_ARM_ERRATA_716044
+CONFIG_ARM_ERRATA_742230
+CONFIG_ARM_ERRATA_743622
+CONFIG_ARM_ERRATA_751472
+CONFIG_ARM_ERRATA_761320
+CONFIG_ARM_ERRATA_773022
+CONFIG_ARM_ERRATA_774769
+CONFIG_ARM_ERRATA_794072
+CONFIG_ARM_ERRATA_798870
+CONFIG_ARM_ERRATA_801819
+CONFIG_ARM_ERRATA_826974
+CONFIG_ARM_ERRATA_828024
+CONFIG_ARM_ERRATA_829520
+CONFIG_ARM_ERRATA_833069
+CONFIG_ARM_ERRATA_833471
+CONFIG_ARM_FREQ
+CONFIG_ARM_GIC_BASE_ADDRESS
+CONFIG_ARM_PL180_MMCI
+CONFIG_ARM_PL180_MMCI_BASE
+CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
+CONFIG_ARM_THUMB
+CONFIG_ARP_TIMEOUT
+CONFIG_AS3722_POWER
+CONFIG_ASTRO5373L
+CONFIG_ASTRO_COFDMDUOS2
+CONFIG_ASTRO_TWIN7S2
+CONFIG_ASTRO_V512
+CONFIG_ASTRO_V532
+CONFIG_ASTRO_V912
+CONFIG_AT32AP
+CONFIG_AT32AP7000
+CONFIG_AT32UC3A0xxx
+CONFIG_AT91C_PQFP_UHPBUG
+CONFIG_AT91FAMILY
+CONFIG_AT91RESET_EXTRST
+CONFIG_AT91RM9200
+CONFIG_AT91RM9200EK
+CONFIG_AT91SAM9260
+CONFIG_AT91SAM9260EK
+CONFIG_AT91SAM9261
+CONFIG_AT91SAM9261EK
+CONFIG_AT91SAM9263
+CONFIG_AT91SAM9263EK
+CONFIG_AT91SAM9G10
+CONFIG_AT91SAM9G10EK
+CONFIG_AT91SAM9G20
+CONFIG_AT91SAM9G20EK
+CONFIG_AT91SAM9G20EK_2MMC
+CONFIG_AT91SAM9G45
+CONFIG_AT91SAM9G45EKES
+CONFIG_AT91SAM9G45_LCD_BASE
+CONFIG_AT91SAM9M10G45
+CONFIG_AT91SAM9M10G45EK
+CONFIG_AT91SAM9N12
+CONFIG_AT91SAM9RL
+CONFIG_AT91SAM9RLEK
+CONFIG_AT91SAM9X5
+CONFIG_AT91SAM9X5EK
+CONFIG_AT91SAM9XE
+CONFIG_AT91SAM9_WATCHDOG
+CONFIG_AT91_CAN
+CONFIG_AT91_EFLASH
+CONFIG_AT91_GPIO
+CONFIG_AT91_GPIO_PULLUP
+CONFIG_AT91_HW_WDT_TIMEOUT
+CONFIG_AT91_LED
+CONFIG_AT91_WANTS_COMMON_PHY
+CONFIG_ATAPI
+CONFIG_ATA_ACPI
+CONFIG_ATI
+CONFIG_ATI_RADEON_FB
+CONFIG_ATM
+CONFIG_ATMEL_DATAFLASH_SPI
+CONFIG_ATMEL_HLCD
+CONFIG_ATMEL_LCD
+CONFIG_ATMEL_LCD_BGR555
+CONFIG_ATMEL_LCD_RGB565
+CONFIG_ATMEL_LEGACY
+CONFIG_ATMEL_MCI_8BIT
+CONFIG_ATMEL_NAND_HWECC
+CONFIG_ATMEL_NAND_HW_PMECC
+CONFIG_ATMEL_SPI0
+CONFIG_ATNGW100
+CONFIG_ATNGW100MKII
+CONFIG_ATSTK1000
+CONFIG_ATSTK1000_16MB_SDRAM
+CONFIG_ATSTK1002
+CONFIG_AT_TRANS
+CONFIG_AUTOCALIB
+CONFIG_AUTONEG_TIMEOUT
+CONFIG_AUTO_COMPLETE
+CONFIG_AUTO_ZRELADDR
+CONFIG_BACKSIDE_L2_CACHE
+CONFIG_BAMBOO
+CONFIG_BAMBOO_NAND
+CONFIG_BARIX_IPAM390
+CONFIG_BAT_CMD
+CONFIG_BAT_PAIR
+CONFIG_BAT_RW
+CONFIG_BAUDRATE
+CONFIG_BCH
+CONFIG_BCH_CONST_M
+CONFIG_BCH_CONST_PARAMS
+CONFIG_BCH_CONST_T
+CONFIG_BCM2835_GPIO
+CONFIG_BCM283X_MU_SERIAL
+CONFIG_BCM_SF2_ETH
+CONFIG_BCM_SF2_ETH_DEFAULT_PORT
+CONFIG_BCM_SF2_ETH_GMAC
+CONFIG_BD_NUM_CPUS
+CONFIG_BF506_UART0_PORTF
+CONFIG_BF506_UART1_PORTG
+CONFIG_BF50x
+CONFIG_BF51x
+CONFIG_BF527_EZKIT_REV_2_1
+CONFIG_BF52x
+CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
+CONFIG_BF54x
+CONFIG_BF60x
+CONFIG_BFIN_ATAPI_BASE_ADDR
+CONFIG_BFIN_ATA_MODE
+CONFIG_BFIN_BOARD_VERSION_1_0
+CONFIG_BFIN_BOOTROM_USES_EVT1
+CONFIG_BFIN_BOOT_MODE
+CONFIG_BFIN_CF_IDE
+CONFIG_BFIN_CPU
+CONFIG_BFIN_GET_DCLK_M
+CONFIG_BFIN_GPIO_TRACK
+CONFIG_BFIN_HDD_IDE
+CONFIG_BFIN_IDE
+CONFIG_BFIN_INS_LOWOVERHEAD
+CONFIG_BFIN_LINKPORT
+CONFIG_BFIN_MAC
+CONFIG_BFIN_MAC_PINS
+CONFIG_BFIN_NFC
+CONFIG_BFIN_NFC_BOOTROM_ECC
+CONFIG_BFIN_NFC_CTL_VAL
+CONFIG_BFIN_NFC_NO_HW_ECC
+CONFIG_BFIN_SCRATCH_REG
+CONFIG_BFIN_SDH
+CONFIG_BFIN_SERIAL
+CONFIG_BFIN_SOFT_SWITCH
+CONFIG_BFIN_SPI
+CONFIG_BFIN_SPI6XX
+CONFIG_BFIN_SPI_GPIO_CS
+CONFIG_BFIN_SPI_IDLE_VAL
+CONFIG_BFIN_SPI_IMG_SIZE
+CONFIG_BFIN_TRUE_IDE
+CONFIG_BFIN_WATCHDOG
+CONFIG_BIOSEMU
+CONFIG_BITBANGMII
+CONFIG_BITBANGMII_MULTI
+CONFIG_BKUP_FLASH
+CONFIG_BL1_OFFSET
+CONFIG_BL1_SIZE
+CONFIG_BL2_OFFSET
+CONFIG_BL2_SIZE
+CONFIG_BMP_16BPP
+CONFIG_BMP_24BMP
+CONFIG_BMP_24BPP
+CONFIG_BMP_32BPP
+CONFIG_BOARDDIR
+CONFIG_BOARDINFO
+CONFIG_BOARDNAME
+CONFIG_BOARDNAME_LOCAL
+CONFIG_BOARD_AXM
+CONFIG_BOARD_BOOTCMD
+CONFIG_BOARD_COMMON
+CONFIG_BOARD_EARLY_INIT_F
+CONFIG_BOARD_EARLY_INIT_R
+CONFIG_BOARD_ECC_SUPPORT
+CONFIG_BOARD_EMAC_COUNT
+CONFIG_BOARD_H2200
+CONFIG_BOARD_IS_OPENRD_BASE
+CONFIG_BOARD_IS_OPENRD_CLIENT
+CONFIG_BOARD_IS_OPENRD_ULTIMATE
+CONFIG_BOARD_LATE_INIT
+CONFIG_BOARD_MEM_LIMIT
+CONFIG_BOARD_NAME
+CONFIG_BOARD_POSTCLK_INIT
+CONFIG_BOARD_RESET
+CONFIG_BOARD_REVISION_TAG
+CONFIG_BOARD_SIZE_LIMIT
+CONFIG_BOARD_SPECIFIC_LED
+CONFIG_BOARD_TAURUS
+CONFIG_BOARD_TYPES
+CONFIG_BOOGER
+CONFIG_BOOM
+CONFIG_BOOTARGS
+CONFIG_BOOTARGS_AXM
+CONFIG_BOOTARGS_ROOT
+CONFIG_BOOTARGS_TAURUS
+CONFIG_BOOTARGS_VIDEO
+CONFIG_BOOTBLOCK
+CONFIG_BOOTCOMMAND
+CONFIG_BOOTCOUNT_ALEN
+CONFIG_BOOTCOUNT_AM33XX
+CONFIG_BOOTCOUNT_ENV
+CONFIG_BOOTCOUNT_I2C
+CONFIG_BOOTCOUNT_LIMIT
+CONFIG_BOOTCOUNT_RAM
+CONFIG_BOOTFILE
+CONFIG_BOOTMAPSZ
+CONFIG_BOOTMODE
+CONFIG_BOOTM_LINUX
+CONFIG_BOOTM_NETBSD
+CONFIG_BOOTM_OPENRTOS
+CONFIG_BOOTM_OSE
+CONFIG_BOOTM_PLAN9
+CONFIG_BOOTM_RTEMS
+CONFIG_BOOTM_VXWORKS
+CONFIG_BOOTP_
+CONFIG_BOOTP_BOOTFILE
+CONFIG_BOOTP_BOOTFILESIZE
+CONFIG_BOOTP_BOOTPATH
+CONFIG_BOOTP_DEFAULT
+CONFIG_BOOTP_DHCP_REQUEST_DELAY
+CONFIG_BOOTP_DNS
+CONFIG_BOOTP_DNS2
+CONFIG_BOOTP_GATEWAY
+CONFIG_BOOTP_HOSTNAME
+CONFIG_BOOTP_ID_CACHE_SIZE
+CONFIG_BOOTP_MAY_FAIL
+CONFIG_BOOTP_NISDOMAIN
+CONFIG_BOOTP_NTPSERVER
+CONFIG_BOOTP_PXE
+CONFIG_BOOTP_RANDOM_DELAY
+CONFIG_BOOTP_SEND_HOSTNAME
+CONFIG_BOOTP_SERVERIP
+CONFIG_BOOTP_SUBNETMASK
+CONFIG_BOOTP_TIMEOFFSET
+CONFIG_BOOTP_VENDOREX
+CONFIG_BOOTROM_ERR_REG
+CONFIG_BOOTSCRIPT_ADDR
+CONFIG_BOOTSCRIPT_COPY_RAM
+CONFIG_BOOTSCRIPT_HDR_ADDR
+CONFIG_BOOTSCRIPT_KEY_HASH
+CONFIG_BOOT_DIR
+CONFIG_BOOT_FROM_XMD
+CONFIG_BOOT_MODE_BIT
+CONFIG_BOOT_OS_NET
+CONFIG_BOOT_PARAMS_ADDR
+CONFIG_BOOT_PCI
+CONFIG_BOOT_RETRY_MIN
+CONFIG_BOOT_RETRY_TIME
+CONFIG_BOUNCE_BUFFER
+CONFIG_BPTR_VIRT_ADDR
+CONFIG_BSEIP
+CONFIG_BS_ADDR_DEVICE
+CONFIG_BS_ADDR_RAM
+CONFIG_BS_COPY_CMD
+CONFIG_BS_COPY_ENV
+CONFIG_BS_HDR_ADDR_DEVICE
+CONFIG_BS_HDR_ADDR_RAM
+CONFIG_BS_HDR_SIZE
+CONFIG_BS_SIZE
+CONFIG_BTB
+CONFIG_BUBINGA
+CONFIG_BUFNO_AUTO_INCR_BIT
+CONFIG_BUILD_ENVCRC
+CONFIG_BUILD_TARGET
+CONFIG_BUS_WIDTH
+CONFIG_BZIP2
+CONFIG_CACHELINE_ALIGNED_L1
+CONFIG_CADDY2
+CONFIG_CALXEDA_XGMAC
+CONFIG_CAM5200
+CONFIG_CAM5200_NIOSFLASH
+CONFIG_CANMB
+CONFIG_CAN_DRIVER
+CONFIG_CCLK_ACT_DIV
+CONFIG_CCLK_DIV
+CONFIG_CCLK_DIV_not_defined_properly
+CONFIG_CCLK_HZ
+CONFIG_CDP_APPLIANCE_VLAN_TYPE
+CONFIG_CDP_CAPABILITIES
+CONFIG_CDP_DEVICE_ID
+CONFIG_CDP_DEVICE_ID_PREFIX
+CONFIG_CDP_PLATFORM
+CONFIG_CDP_PORT_ID
+CONFIG_CDP_POWER_CONSUMPTION
+CONFIG_CDP_TRIGGER
+CONFIG_CDP_VERSION
+CONFIG_CFG_DATA_SECTOR
+CONFIG_CFG_FAT
+CONFIG_CFG_USB
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+CONFIG_CF_ATASEL_DIS
+CONFIG_CF_ATASEL_ENA
+CONFIG_CF_DSPI
+CONFIG_CF_QSPI
+CONFIG_CF_SBF
+CONFIG_CF_SPI
+CONFIG_CF_V2
+CONFIG_CF_V3
+CONFIG_CF_V4
+CONFIG_CF_V4E
+CONFIG_CGU_CTL_VAL
+CONFIG_CGU_DIV_VAL
+CONFIG_CHAIN_BOOT_CMD
+CONFIG_CHAIN_OF_TRUST
+CONFIG_CHARON
+CONFIG_CHIP_SELECTS_PER_CTRL
+CONFIG_CHIP_SELECT_QUAD_CAPABLE
+CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
+CONFIG_CIS8201_PHY
+CONFIG_CI_UDC_HAS_HOSTPC
+CONFIG_CLK0_DIV
+CONFIG_CLK0_EN
+CONFIG_CLKIN_HALF
+CONFIG_CLKIN_HZ
+CONFIG_CLK_1000_200_200
+CONFIG_CLK_1000_330_165
+CONFIG_CLK_1000_400_200
+CONFIG_CLK_800_330_165
+CONFIG_CLK_DEBUG
+CONFIG_CLOCKS
+CONFIG_CLOCKS_IN_MHZ
+CONFIG_CLOCK_SYNTHESIZER
+CONFIG_CM5200
+CONFIG_CM922T_XA10
+CONFIG_CMDLINE_EDITING
+CONFIG_CMDLINE_PS_SUPPORT
+CONFIG_CMDLINE_TAG
+CONFIG_CMD_AES
+CONFIG_CMD_ASKEN
+CONFIG_CMD_BAT
+CONFIG_CMD_BEDBUG
+CONFIG_CMD_BLOB
+CONFIG_CMD_BMODE
+CONFIG_CMD_BMP
+CONFIG_CMD_BOOTLDR
+CONFIG_CMD_BSP
+CONFIG_CMD_CBFS
+CONFIG_CMD_CHIP_CONFIG
+CONFIG_CMD_CLEAR
+CONFIG_CMD_CLK
+CONFIG_CMD_CPLBINFO
+CONFIG_CMD_CRAMFS
+CONFIG_CMD_DATE
+CONFIG_CMD_DEFAULTENV_VARS
+CONFIG_CMD_DEKBLOB
+CONFIG_CMD_DFL
+CONFIG_CMD_DIAG
+CONFIG_CMD_DISPLAY
+CONFIG_CMD_DOC
+CONFIG_CMD_DS4510
+CONFIG_CMD_DS4510_INFO
+CONFIG_CMD_DS4510_MEM
+CONFIG_CMD_DS4510_RST
+CONFIG_CMD_DTT
+CONFIG_CMD_ECCTEST
+CONFIG_CMD_EECONFIG
+CONFIG_CMD_EEPROM
+CONFIG_CMD_EEPROM_LAYOUT
+CONFIG_CMD_ENTERRCM
+CONFIG_CMD_ENV
+CONFIG_CMD_ENV_CALLBACK
+CONFIG_CMD_ENV_FLAGS
+CONFIG_CMD_ERRATA
+CONFIG_CMD_ESBC_VALIDATE
+CONFIG_CMD_ETHSW
+CONFIG_CMD_FDC
+CONFIG_CMD_FDT_MAX_DUMP
+CONFIG_CMD_FPGAD
+CONFIG_CMD_FPGA_LOADBP
+CONFIG_CMD_FPGA_LOADFS
+CONFIG_CMD_FPGA_LOADMK
+CONFIG_CMD_FPGA_LOADP
+CONFIG_CMD_FUSE
+CONFIG_CMD_GETTIME
+CONFIG_CMD_GPT
+CONFIG_CMD_GSC
+CONFIG_CMD_HASH
+CONFIG_CMD_HD44760
+CONFIG_CMD_HD44780
+CONFIG_CMD_HDMIDETECT
+CONFIG_CMD_IDE
+CONFIG_CMD_IMMAP
+CONFIG_CMD_IMXOTP
+CONFIG_CMD_IMX_FUSE
+CONFIG_CMD_IO
+CONFIG_CMD_IOLOOP
+CONFIG_CMD_IOTRACE
+CONFIG_CMD_IRQ
+CONFIG_CMD_JFFS2
+CONFIG_CMD_KGDB
+CONFIG_CMD_LDRINFO
+CONFIG_CMD_LED
+CONFIG_CMD_LOADY
+CONFIG_CMD_LZMADEC
+CONFIG_CMD_MAX6957
+CONFIG_CMD_MD5SUM
+CONFIG_CMD_MEM
+CONFIG_CMD_MFSL
+CONFIG_CMD_MMC_SPI
+CONFIG_CMD_MTDPARTS
+CONFIG_CMD_MTDPARTS_SPREAD
+CONFIG_CMD_NAND_LOCK_UNLOCK
+CONFIG_CMD_NAND_TORTURE
+CONFIG_CMD_NAND_TRIMFFS
+CONFIG_CMD_ONENAND
+CONFIG_CMD_OTP
+CONFIG_CMD_PART
+CONFIG_CMD_PCA953X
+CONFIG_CMD_PCA953X_INFO
+CONFIG_CMD_PCI
+CONFIG_CMD_PCI_ENUM
+CONFIG_CMD_PCMCIA
+CONFIG_CMD_PORTIO
+CONFIG_CMD_READ
+CONFIG_CMD_REGINFO
+CONFIG_CMD_REISER
+CONFIG_CMD_SANDBOX
+CONFIG_CMD_SATA
+CONFIG_CMD_SAVES
+CONFIG_CMD_SCSI
+CONFIG_CMD_SDRAM
+CONFIG_CMD_SF_TEST
+CONFIG_CMD_SH_ZIMAGEBOOT
+CONFIG_CMD_SOFTSWITCH
+CONFIG_CMD_SPIBOOTLDR
+CONFIG_CMD_SPL
+CONFIG_CMD_SPL_NAND_OFS
+CONFIG_CMD_SPL_WRITE_SIZE
+CONFIG_CMD_STRINGS
+CONFIG_CMD_SX151X
+CONFIG_CMD_TCA642X
+CONFIG_CMD_TERMINAL
+CONFIG_CMD_TFTP
+CONFIG_CMD_THOR_DOWNLOAD
+CONFIG_CMD_TRACE
+CONFIG_CMD_TSI148
+CONFIG_CMD_UBIFS
+CONFIG_CMD_UNIVERSE
+CONFIG_CMD_UNZIP
+CONFIG_CMD_USB_STORAGE
+CONFIG_CMD_UUID
+CONFIG_CMD_ZBOOT
+CONFIG_CMD_ZFS
+CONFIG_CM_INIT
+CONFIG_CM_MULTIPLE_SSRAM
+CONFIG_CM_REMAP
+CONFIG_CM_SPD_DETECT
+CONFIG_CM_T335
+CONFIG_CM_T3517
+CONFIG_CM_T3X
+CONFIG_CM_T43
+CONFIG_CM_T54
+CONFIG_CM_TCRAM
+CONFIG_CNTL
+CONFIG_COLDFIRE
+CONFIG_COMMANDS
+CONFIG_COMMAND_HISTORY
+CONFIG_COMMON_BOOT
+CONFIG_COMMON_ENV_MISC
+CONFIG_COMMON_ENV_SETTINGS
+CONFIG_COMMON_ENV_UBI
+CONFIG_COMPACT_FLASH
+CONFIG_COMPAT
+CONFIG_CONS_EXTC_PINSEL
+CONFIG_CONS_EXTC_RATE
+CONFIG_CONS_NONE
+CONFIG_CONS_ON_SCC
+CONFIG_CONS_ON_SMC
+CONFIG_CONS_SCIF0
+CONFIG_CONS_SCIF1
+CONFIG_CONS_SCIF2
+CONFIG_CONS_SCIF3
+CONFIG_CONS_SCIF4
+CONFIG_CONS_SCIF5
+CONFIG_CONS_SCIF7
+CONFIG_CONTROL
+CONFIG_CONTROLCENTERD
+CONFIG_CON_ROT
+CONFIG_CORE1_RUN
+CONFIG_CORE_COUNT
+CONFIG_CORTINA_FW_ADDR
+CONFIG_CORTINA_FW_LENGTH
+CONFIG_CPCI405
+CONFIG_CPCI405_6U
+CONFIG_CPCI405_VER2
+CONFIG_CPCI_AX2000
+CONFIG_CPLD_BR_PRELIM
+CONFIG_CPLD_OR_PRELIM
+CONFIG_CPM2
+CONFIG_CPUAT91
+CONFIG_CPU_ARCHS34
+CONFIG_CPU_ARMV8
+CONFIG_CPU_CAVIUM_OCTEON
+CONFIG_CPU_FREQ_HZ
+CONFIG_CPU_HAS_LLSC
+CONFIG_CPU_HAS_PREFETCH
+CONFIG_CPU_HAS_SMARTMIPS
+CONFIG_CPU_HAS_SR_RB
+CONFIG_CPU_HAS_WB
+CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+CONFIG_CPU_LITTLE_ENDIAN
+CONFIG_CPU_MICROMIPS
+CONFIG_CPU_MIPSR2
+CONFIG_CPU_MONAHANS
+CONFIG_CPU_PXA25X
+CONFIG_CPU_PXA26X
+CONFIG_CPU_PXA27X
+CONFIG_CPU_PXA300
+CONFIG_CPU_R8000
+CONFIG_CPU_SH7203
+CONFIG_CPU_SH7264
+CONFIG_CPU_SH7269
+CONFIG_CPU_SH7706
+CONFIG_CPU_SH7720
+CONFIG_CPU_SH7722
+CONFIG_CPU_SH7723
+CONFIG_CPU_SH7724
+CONFIG_CPU_SH7734
+CONFIG_CPU_SH7750
+CONFIG_CPU_SH7751
+CONFIG_CPU_SH7752
+CONFIG_CPU_SH7753
+CONFIG_CPU_SH7757
+CONFIG_CPU_SH7763
+CONFIG_CPU_SH7780
+CONFIG_CPU_SH7785
+CONFIG_CPU_SH_TYPE_R
+CONFIG_CPU_TYPE_R
+CONFIG_CPU_VR41XX
+CONFIG_CP_CLK_FREQ
+CONFIG_CQSPI_DECODER
+CONFIG_CQSPI_REF_CLK
+CONFIG_CRC32
+CONFIG_CRC32_VERIFY
+CONFIG_CS8900
+CONFIG_CS8900_BASE
+CONFIG_CS8900_BUS16
+CONFIG_CS8900_BUS32
+CONFIG_CSF_SIZE
+CONFIG_CTL_JTAG
+CONFIG_CTL_TBE
+CONFIG_CTRD1_PROBE_T1
+CONFIG_CTRD1_PROBE_T2
+CONFIG_CUSTOMER_BOARD_SUPPORT
+CONFIG_CYRUS
+CONFIG_D2NET_V2
+CONFIG_DA850_AM18X_EVM
+CONFIG_DA850_EVM_MAX_CPU_CLK
+CONFIG_DA850_LOWLEVEL
+CONFIG_DA8XX_GPIO
+CONFIG_DASA_SIM
+CONFIG_DATA
+CONFIG_DAVINCI_MMC
+CONFIG_DAVINCI_MMC_SD1
+CONFIG_DAVINCI_SPI
+CONFIG_DBAU1000
+CONFIG_DBAU1X00
+CONFIG_DBGU
+CONFIG_DBG_MONITOR
+CONFIG_DB_784MP_GP
+CONFIG_DCACHE
+CONFIG_DCACHE_OFF
+CONFIG_DCACHE_WB
+CONFIG_DCFG_ADDR
+CONFIG_DCLK_DIV
+CONFIG_DDR_
+CONFIG_DDR_2HCLK
+CONFIG_DDR_2T_TIMING
+CONFIG_DDR_32BIT
+CONFIG_DDR_64BIT
+CONFIG_DDR_CLK_FREQ
+CONFIG_DDR_DATA_EYE
+CONFIG_DDR_DEFAULT_CL
+CONFIG_DDR_ECC
+CONFIG_DDR_ECC_CMD
+CONFIG_DDR_ECC_ENABLE
+CONFIG_DDR_ECC_INIT_VIA_DMA
+CONFIG_DDR_FIXED_SIZE
+CONFIG_DDR_HCLK
+CONFIG_DDR_HYB25D512160BF
+CONFIG_DDR_II
+CONFIG_DDR_K4H511638C
+CONFIG_DDR_LOG_LEVEL
+CONFIG_DDR_MB
+CONFIG_DDR_MT46V16M16
+CONFIG_DDR_MT46V32M16
+CONFIG_DDR_MT47H128M8
+CONFIG_DDR_MT47H32M16
+CONFIG_DDR_MT47H64M16
+CONFIG_DDR_PLL2
+CONFIG_DDR_RFDC_FIXED
+CONFIG_DDR_RQDC_FIXED
+CONFIG_DDR_SPD
+CONFIG_DEBUG
+CONFIG_DEBUG_DUMP
+CONFIG_DEBUG_DUMP_SYMS
+CONFIG_DEBUG_EARLY_SERIAL
+CONFIG_DEBUG_FS
+CONFIG_DEBUG_LED
+CONFIG_DEBUG_LOCK_ALLOC
+CONFIG_DEBUG_NULL_PTR
+CONFIG_DEBUG_SECTION_MISMATCH
+CONFIG_DEBUG_SEMIHOSTING
+CONFIG_DEBUG_SERIAL
+CONFIG_DEBUG_UART_LINFLEXUART
+CONFIG_DEBUG_WRITECOUNT
+CONFIG_DEB_DMA_URGENT
+CONFIG_DEEP_SLEEP
+CONFIG_DEFAULT
+CONFIG_DEFAULT_CONSOLE
+CONFIG_DEFAULT_IMMR
+CONFIG_DEFAULT_KERNEL_COMMAND_LINE
+CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
+CONFIG_DEFAULT_SPI_BUS
+CONFIG_DEFAULT_SPI_CS
+CONFIG_DEFAULT_SPI_MODE
+CONFIG_DEF_HWCONFIG
+CONFIG_DELAY_ENVIRONMENT
+CONFIG_DENX_M28_V10
+CONFIG_DESIGNWARE_ETH
+CONFIG_DESIGNWARE_WATCHDOG
+CONFIG_DEVCONCENTER
+CONFIG_DEVELOP
+CONFIG_DEVICE_TREE_LIST
+CONFIG_DEV_USB_PHY_BASE
+CONFIG_DFU_ALT
+CONFIG_DFU_ALT_BOOT_EMMC
+CONFIG_DFU_ALT_BOOT_SD
+CONFIG_DFU_ALT_SYSTEM
+CONFIG_DFU_ENV_SETTINGS
+CONFIG_DFU_MTD
+CONFIG_DHCP_MIN_EXT_LEN
+CONFIG_DIALOG_POWER
+CONFIG_DIGSY_MTC
+CONFIG_DIGSY_REV5
+CONFIG_DIMM_SLOTS_PER_CTLR
+CONFIG_DIRECT_NOR_BOOT
+CONFIG_DISABLE_CONSOLE
+CONFIG_DISABLE_IMAGE_LEGACY
+CONFIG_DISABLE_PISE_TEST
+CONFIG_DISCONTIGMEM
+CONFIG_DISCOVER_PHY
+CONFIG_DISPLAY_AER_xxxx
+CONFIG_DISPLAY_BOARDINFO_LATE
+CONFIG_DLVISION
+CONFIG_DLVISION_10G
+CONFIG_DM9000_BASE
+CONFIG_DM9000_BYTE_SWAPPED
+CONFIG_DM9000_DEBUG
+CONFIG_DM9000_NO_SROM
+CONFIG_DM9000_USE_16BIT
+CONFIG_DMA_COHERENT
+CONFIG_DMA_COHERENT_SIZE
+CONFIG_DMA_LPC32XX
+CONFIG_DMA_NONCOHERENT
+CONFIG_DMA_REQ_BIT
+CONFIG_DMC_DDRCFG
+CONFIG_DMC_DDRCTL
+CONFIG_DMC_DDREMR1
+CONFIG_DMC_DDRMR
+CONFIG_DMC_DDRTR0
+CONFIG_DMC_DDRTR1
+CONFIG_DMC_DDRTR2
+CONFIG_DNET_AUTONEG_TIMEOUT
+CONFIG_DNP5370_EXT_WD_DISABLE
+CONFIG_DOS_PARTITION
+CONFIG_DP_DDR_CTRL
+CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
+CONFIG_DP_DDR_NUM_CTRLS
+CONFIG_DRA7XX
+CONFIG_DRAM_2G
+CONFIG_DRAM_TIMINGS_
+CONFIG_DRIVER_AT91EMAC
+CONFIG_DRIVER_AT91EMAC_PHYADDR
+CONFIG_DRIVER_AT91EMAC_QUIET
+CONFIG_DRIVER_AX88180
+CONFIG_DRIVER_AX88796L
+CONFIG_DRIVER_DM9000
+CONFIG_DRIVER_EP93XX_MAC
+CONFIG_DRIVER_ETHER
+CONFIG_DRIVER_NAND_BFIN
+CONFIG_DRIVER_NE2000
+CONFIG_DRIVER_NE2000_BASE
+CONFIG_DRIVER_NE2000_CCR
+CONFIG_DRIVER_NE2000_VAL
+CONFIG_DRIVER_SMC911X_BASE
+CONFIG_DRIVER_TI_CPSW
+CONFIG_DRIVER_TI_EMAC
+CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
+CONFIG_DRIVER_TI_EMAC_USE_RMII
+CONFIG_DRIVER_TI_KEYSTONE_NET
+CONFIG_DRIVE_MMC
+CONFIG_DRIVE_SATA
+CONFIG_DRIVE_TYPES
+CONFIG_DRIVE_USB
+CONFIG_DS4510
+CONFIG_DSP_CLUSTER_START
+CONFIG_DTT
+CONFIG_DTT_AD7414
+CONFIG_DTT_ADM1021
+CONFIG_DTT_DS1621
+CONFIG_DTT_DS1775
+CONFIG_DTT_DS620
+CONFIG_DTT_HYSTERESIS
+CONFIG_DTT_LM63
+CONFIG_DTT_LM75
+CONFIG_DTT_LM81
+CONFIG_DTT_MAX_TEMP
+CONFIG_DTT_MIN_TEMP
+CONFIG_DTT_PWM_LOOKUPTABLE
+CONFIG_DTT_SENSORS
+CONFIG_DTT_TACH_LIMIT
+CONFIG_DUOVERO
+CONFIG_DV_USBPHY_CTL
+CONFIG_DWC2_DFLT_SPEED_FULL
+CONFIG_DWC2_DMA_BURST_SIZE
+CONFIG_DWC2_DMA_ENABLE
+CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE
+CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE
+CONFIG_DWC2_HOST_RX_FIFO_SIZE
+CONFIG_DWC2_I2C_ENABLE
+CONFIG_DWC2_IC_USB_CAP
+CONFIG_DWC2_MAX_CHANNELS
+CONFIG_DWC2_MAX_PACKET_COUNT
+CONFIG_DWC2_MAX_TRANSFER_SIZE
+CONFIG_DWC2_PHY_TYPE
+CONFIG_DWC2_PHY_ULPI_DDR
+CONFIG_DWC2_PHY_ULPI_EXT_VBUS
+CONFIG_DWC2_THR_CTL
+CONFIG_DWC2_TS_DLINE
+CONFIG_DWC2_TX_THR_LENGTH
+CONFIG_DWC2_ULPI_FS_LS
+CONFIG_DWC2_UTMI_WIDTH
+CONFIG_DWCDDR21MCTL
+CONFIG_DWCDDR21MCTL_BASE
+CONFIG_DWC_AHSATA
+CONFIG_DWC_AHSATA_BASE_ADDR
+CONFIG_DWC_AHSATA_PORT_ID
+CONFIG_DWMMC
+CONFIG_DW_ALTDESCRIPTOR
+CONFIG_DW_AXI_BURST_LEN
+CONFIG_DW_GMAC_DEFAULT_DMA_PBL
+CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
+CONFIG_DW_PORTS
+CONFIG_DW_SERIAL
+CONFIG_DW_UDC
+CONFIG_DW_WDT_BASE
+CONFIG_DW_WDT_CLOCK_KHZ
+CONFIG_DYNAMIC_MMC_DEVNO
+CONFIG_E1000_NO_NVM
+CONFIG_E300
+CONFIG_E5500
+CONFIG_EBCAW_VAL
+CONFIG_EBC_PPC4xx_IBM_VER1
+CONFIG_EBIU_AMBCTL0_VAL
+CONFIG_EBIU_AMBCTL1_VAL
+CONFIG_EBIU_AMGCTL_VAL
+CONFIG_EBIU_DDRCTL0_VAL
+CONFIG_EBIU_DDRCTL1_VAL
+CONFIG_EBIU_DDRCTL2_VAL
+CONFIG_EBIU_DDRCTL3_VAL
+CONFIG_EBIU_DDRQUE_VAL
+CONFIG_EBIU_FCTL_VAL
+CONFIG_EBIU_MBSCTL_VAL
+CONFIG_EBIU_MODE_VAL
+CONFIG_EBIU_RSTCTL_VAL
+CONFIG_EBIU_SDBCTL_VAL
+CONFIG_EBIU_SDGCTL_VAL
+CONFIG_EBIU_SDRRC_VAL
+CONFIG_EBSZ_VAL
+CONFIG_ECC
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+CONFIG_ECC_MODE_MASK
+CONFIG_ECC_MODE_SHIFT
+CONFIG_ECC_SRAM_ADDR_MASK
+CONFIG_ECC_SRAM_ADDR_SHIFT
+CONFIG_ECC_SRAM_REQ_BIT
+CONFIG_ECOVEC
+CONFIG_ECOVEC_ROMIMAGE_ADDR
+CONFIG_EDB9301
+CONFIG_EDB9302
+CONFIG_EDB9302A
+CONFIG_EDB9307
+CONFIG_EDB9307A
+CONFIG_EDB9312
+CONFIG_EDB9315
+CONFIG_EDB9315A
+CONFIG_EDB93XX_INDUSTRIAL
+CONFIG_EDB93XX_SDCS0
+CONFIG_EDB93XX_SDCS1
+CONFIG_EDB93XX_SDCS2
+CONFIG_EDB93XX_SDCS3
+CONFIG_EEPRO100
+CONFIG_EEPRO100_SROM_WRITE
+CONFIG_EEPROM_BUS_ADDRESS
+CONFIG_EEPROM_CHIP_ADDRESS
+CONFIG_EEPROM_LAYOUT_HELP_STRING
+CONFIG_EFI_PARTITION
+CONFIG_EFLASH_PROTSECTORS
+CONFIG_EHCI_DESC_BIG_ENDIAN
+CONFIG_EHCI_HCD_INIT_AFTER_RESET
+CONFIG_EHCI_IS_TDI
+CONFIG_EHCI_MMIO_BIG_ENDIAN
+CONFIG_EHCI_MXS_PORT0
+CONFIG_EHCI_MXS_PORT1
+CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
+CONFIG_EMAC_MDIO_PHY_NUM
+CONFIG_EMAC_NR_START
+CONFIG_EMAC_PHY_MODE
+CONFIG_EMIF4
+CONFIG_EMMC_BOOT
+CONFIG_EMU
+CONFIG_ENABLE_36BIT_PHYS
+CONFIG_ENABLE_MMU
+CONFIG_ENABLE_MUST_CHECK
+CONFIG_ENABLE_VBOOT
+CONFIG_ENABLE_WARN_DEPRECATED
+CONFIG_ENC_SILENTLINK
+CONFIG_ENV_ACCESS_IGNORE_FORCE
+CONFIG_ENV_ADDR
+CONFIG_ENV_ADDR_FLEX
+CONFIG_ENV_ADDR_REDUND
+CONFIG_ENV_AES
+CONFIG_ENV_BASE
+CONFIG_ENV_CALLBACK_LIST_DEFAULT
+CONFIG_ENV_CALLBACK_LIST_STATIC
+CONFIG_ENV_COMMON_BOOT
+CONFIG_ENV_EEPROM_IS_ON_I2C
+CONFIG_ENV_FIT_UCBOOT
+CONFIG_ENV_FLAGS_LIST_DEFAULT
+CONFIG_ENV_FLAGS_LIST_STATIC
+CONFIG_ENV_FLASHBOOT
+CONFIG_ENV_IS_EMBEDDED
+CONFIG_ENV_IS_EMBEDDED_IN_LDR
+CONFIG_ENV_IS_IN_
+CONFIG_ENV_IS_IN_DATAFLASH
+CONFIG_ENV_IS_IN_EEPROM
+CONFIG_ENV_IS_IN_FAT
+CONFIG_ENV_IS_IN_FLASH
+CONFIG_ENV_IS_IN_MMC
+CONFIG_ENV_IS_IN_MRAM
+CONFIG_ENV_IS_IN_NAND
+CONFIG_ENV_IS_IN_NVRAM
+CONFIG_ENV_IS_IN_ONENAND
+CONFIG_ENV_IS_IN_REMOTE
+CONFIG_ENV_IS_IN_SPI_FLASH
+CONFIG_ENV_IS_IN_UBI
+CONFIG_ENV_IS_NOWHERE
+CONFIG_ENV_MAX_ENTRIES
+CONFIG_ENV_MIN_ENTRIES
+CONFIG_ENV_OFFSET
+CONFIG_ENV_OFFSET_OOB
+CONFIG_ENV_OFFSET_REDUND
+CONFIG_ENV_OVERWRITE
+CONFIG_ENV_RANGE
+CONFIG_ENV_RDADDR
+CONFIG_ENV_REFLASH
+CONFIG_ENV_SECT_SIZE
+CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS
+CONFIG_ENV_SETTINGS_NAND_V1
+CONFIG_ENV_SETTINGS_NAND_V2
+CONFIG_ENV_SETTINGS_V1
+CONFIG_ENV_SETTINGS_V2
+CONFIG_ENV_SIZE
+CONFIG_ENV_SIZE_FLEX
+CONFIG_ENV_SIZE_REDUND
+CONFIG_ENV_SPI_BASE
+CONFIG_ENV_SPI_BUS
+CONFIG_ENV_SPI_CS
+CONFIG_ENV_SPI_MAX_HZ
+CONFIG_ENV_SPI_MODE
+CONFIG_ENV_SROM_BANK
+CONFIG_ENV_TOTAL_SIZE
+CONFIG_ENV_UBIFS_OPTION
+CONFIG_ENV_UBI_MTD
+CONFIG_ENV_UBI_PART
+CONFIG_ENV_UBI_VOLUME
+CONFIG_ENV_UBI_VOLUME_REDUND
+CONFIG_ENV_VARS_UBOOT_CONFIG
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+CONFIG_ENV_VERSION
+CONFIG_ENV_xxx
+CONFIG_EP9301
+CONFIG_EP9302
+CONFIG_EP9307
+CONFIG_EP9312
+CONFIG_EP9315
+CONFIG_EP93XX
+CONFIG_EP93XX_NO_FLASH_CFG
+CONFIG_EP93XX_SPI
+CONFIG_EP93XX_SPI_MMC
+CONFIG_EPH_POWER_EN
+CONFIG_EPOLL
+CONFIG_ESBC_ADDR_64BIT
+CONFIG_ESBC_HDR_LS
+CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+CONFIG_ESDHC_DETECT_QUIRK
+CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1
+CONFIG_ESDHC_HC_BLK_ADDR
+CONFIG_ESPRESSO7420
+CONFIG_ESPT
+CONFIG_ET1100_BASE
+CONFIG_ETH1ADDR
+CONFIG_ETH2ADDR
+CONFIG_ETHADDR
+CONFIG_ETHBASE
+CONFIG_ETHER_INDEX
+CONFIG_ETHER_LOOPBACK_TEST
+CONFIG_ETHER_NONE
+CONFIG_ETHER_ON_FCC
+CONFIG_ETHER_ON_FCC1
+CONFIG_ETHER_ON_FCC2
+CONFIG_ETHER_ON_FCC3
+CONFIG_ETHER_ON_FEC1
+CONFIG_ETHER_ON_FEC2
+CONFIG_ETHER_ON_SCC
+CONFIG_ETHPRIME
+CONFIG_ETH_BUFSIZE
+CONFIG_ETH_RXSIZE
+CONFIG_EXCEPTION_DEFER
+CONFIG_EXT4_WRITE
+CONFIG_EXTRA_BOOTARGS
+CONFIG_EXTRA_CLOCK
+CONFIG_EXTRA_ENV
+CONFIG_EXTRA_ENV_BOARD_SETTINGS
+CONFIG_EXTRA_ENV_ITB
+CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS
+CONFIG_EXTRA_ENV_SETTINGS
+CONFIG_EXTRA_ENV_SETTINGS_BASE
+CONFIG_EXTRA_ENV_SETTINGS_COMMON
+CONFIG_EXTRA_ENV_SETTINGS_DEVEL
+CONFIG_EXTRA_ENV_SETTINGS_SELECT
+CONFIG_EXTRA_ENV_UNLOCK
+CONFIG_EXTRA_ENV_USBTTY
+CONFIG_EXT_AHB2AHB_BASE
+CONFIG_EXT_AHBAPBBRG_BASE
+CONFIG_EXT_AHBPCIBRG_BASE
+CONFIG_EXT_AHBSLAVE01_BASE
+CONFIG_EXT_AHBSLAVE02_BASE
+CONFIG_EXT_PHY
+CONFIG_EXT_USB_HOST_BASE
+CONFIG_EXYNOS4
+CONFIG_EXYNOS4210
+CONFIG_EXYNOS5
+CONFIG_EXYNOS5250
+CONFIG_EXYNOS5420
+CONFIG_EXYNOS5800
+CONFIG_EXYNOS5_DT
+CONFIG_EXYNOS7420
+CONFIG_EXYNOS_ACE_SHA
+CONFIG_EXYNOS_DP
+CONFIG_EXYNOS_DWMMC
+CONFIG_EXYNOS_FB
+CONFIG_EXYNOS_MIPI_DSIM
+CONFIG_EXYNOS_RELOCATE_CODE_BASE
+CONFIG_EXYNOS_SPL
+CONFIG_EXYNOS_TMU
+CONFIG_FACTORYSET
+CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE
+CONFIG_FASTBOOT_FLASH_NAND_DEV
+CONFIG_FASTBOOT_FLASH_NAND_TRIMFFS
+CONFIG_FAST_FLASH_BIT
+CONFIG_FAT_WRITE
+CONFIG_FB_ADDR
+CONFIG_FB_BACKLIGHT
+CONFIG_FB_DEFERRED_IO
+CONFIG_FDT1_ENV_ADDR
+CONFIG_FDT2_ENV_ADDR
+CONFIG_FDTADDR
+CONFIG_FDTFILE
+CONFIG_FDT_ENV_ADDR
+CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+CONFIG_FDT_FIXUP_PCI_IRQ
+CONFIG_FEATURE_CLEAN_UP
+CONFIG_FEATURE_COMMAND_EDITING
+CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN
+CONFIG_FEATURE_SH_EXTRA_QUIET
+CONFIG_FEATURE_SH_FANCY_PROMPT
+CONFIG_FEATURE_SH_STANDALONE_SHELL
+CONFIG_FEC1_PHY
+CONFIG_FEC2_PHY
+CONFIG_FEC_10MBIT
+CONFIG_FEC_AN_TIMEOUT
+CONFIG_FEC_ENET
+CONFIG_FEC_ENET_DEV
+CONFIG_FEC_FIXED_SPEED
+CONFIG_FEC_MXC_25M_REF_CLK
+CONFIG_FEC_MXC_PHYADDR
+CONFIG_FEC_MXC_SWAP_PACKET
+CONFIG_FEC_XCV_TYPE
+CONFIG_FEROCEON
+CONFIG_FEROCEON_88FR131
+CONFIG_FFUART
+CONFIG_FILE
+CONFIG_FIRMWARE_OFFSET
+CONFIG_FIRMWARE_SIZE
+CONFIG_FIT_DISABLE_SHA256
+CONFIG_FIXED_PHY
+CONFIG_FIXED_PHY_ADDR
+CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
+CONFIG_FLASHBOOTCOMMAND
+CONFIG_FLASHCARD
+CONFIG_FLASH_16BIT
+CONFIG_FLASH_8BIT
+CONFIG_FLASH_BASE
+CONFIG_FLASH_BR_PRELIM
+CONFIG_FLASH_CFI_DRIVER
+CONFIG_FLASH_CFI_LEGACY
+CONFIG_FLASH_CFI_MTD
+CONFIG_FLASH_END
+CONFIG_FLASH_NOT_MEM_MAPPED
+CONFIG_FLASH_OR_PRELIM
+CONFIG_FLASH_PNOR
+CONFIG_FLASH_SECTOR_SIZE
+CONFIG_FLASH_SHOW_PROGRESS
+CONFIG_FLASH_SPANSION_S29WS_N
+CONFIG_FLASH_VERIFY
+CONFIG_FMAN_ENET
+CONFIG_FM_PLAT_CLK_DIV
+CONFIG_FO300
+CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
+CONFIG_FORMIKE
+CONFIG_FPGA_COUNT
+CONFIG_FPGA_DELAY
+CONFIG_FPGA_SOCFPGA
+CONFIG_FPGA_SPARTAN2
+CONFIG_FPGA_SPARTAN3
+CONFIG_FPGA_STRATIX_V
+CONFIG_FPGA_ZYNQPL
+CONFIG_FSLDMAFEC
+CONFIG_FSL_CADMUS
+CONFIG_FSL_CORENET
+CONFIG_FSL_CPLD
+CONFIG_FSL_DCU_FB
+CONFIG_FSL_DCU_SII9022A
+CONFIG_FSL_DDR_BIST
+CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+CONFIG_FSL_DDR_INTERACTIVE
+CONFIG_FSL_DDR_SYNC_REFRESH
+CONFIG_FSL_DEEP_SLEEP
+CONFIG_FSL_DEVICE_DISABLE
+CONFIG_FSL_DIU_CH7301
+CONFIG_FSL_DIU_FB
+CONFIG_FSL_DMA
+CONFIG_FSL_DSPI1
+CONFIG_FSL_ELBC
+CONFIG_FSL_ESDHC
+CONFIG_FSL_ESDHC_ADAPTER_IDENT
+CONFIG_FSL_ESDHC_PIN_MUX
+CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+CONFIG_FSL_FIXED_MMC_LOCATION
+CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+CONFIG_FSL_I2C_CUSTOM_DFSR
+CONFIG_FSL_I2C_CUSTOM_FDR
+CONFIG_FSL_IFC
+CONFIG_FSL_IIM
+CONFIG_FSL_ISBC_KEY_EXT
+CONFIG_FSL_LAYERSCAPE
+CONFIG_FSL_LBC
+CONFIG_FSL_LINFLEXUART
+CONFIG_FSL_MC9SDZ60
+CONFIG_FSL_MC_ENET
+CONFIG_FSL_MEMAC
+CONFIG_FSL_NFC_CHIPS
+CONFIG_FSL_NFC_SPARE_SIZE
+CONFIG_FSL_NFC_WIDTH
+CONFIG_FSL_NFC_WRITE_SIZE
+CONFIG_FSL_NGPIXIS
+CONFIG_FSL_PCIE_DISABLE_ASPM
+CONFIG_FSL_PCIE_RESET
+CONFIG_FSL_PCI_INIT
+CONFIG_FSL_PIXIS
+CONFIG_FSL_PMIC_BITLEN
+CONFIG_FSL_PMIC_BUS
+CONFIG_FSL_PMIC_CLK
+CONFIG_FSL_PMIC_CS
+CONFIG_FSL_PMIC_MODE
+CONFIG_FSL_QIXIS
+CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+CONFIG_FSL_QIXIS_V2
+CONFIG_FSL_SATA
+CONFIG_FSL_SATA_V2
+CONFIG_FSL_SDHC_V2_3
+CONFIG_FSL_SDRAM_TYPE
+CONFIG_FSL_SERDES
+CONFIG_FSL_SERDES1
+CONFIG_FSL_SERDES2
+CONFIG_FSL_SGMII_RISER
+CONFIG_FSL_SPI_INTERFACE
+CONFIG_FSL_TBCLK_EXTRA_DIV
+CONFIG_FSL_TRUST_ARCH_v1
+CONFIG_FSL_TZASC_400
+CONFIG_FSL_TZPC_BP147
+CONFIG_FSL_USDHC
+CONFIG_FSL_VIA
+CONFIG_FSMC_NAND_BASE
+CONFIG_FSMTDBLK
+CONFIG_FSNOTIFY
+CONFIG_FS_EXT4
+CONFIG_FS_FAT
+CONFIG_FS_FAT_MAX_CLUSTSIZE
+CONFIG_FS_POSIX_ACL
+CONFIG_FTAHBC020S
+CONFIG_FTAHBC020S_BASE
+CONFIG_FTAPBBRG020S_01_BASE
+CONFIG_FTCFC010_BASE
+CONFIG_FTDMAC020_BASE
+CONFIG_FTGMAC100_BASE
+CONFIG_FTGMAC100_EGIGA
+CONFIG_FTGPIO010_BASE
+CONFIG_FTI2C010_BASE1
+CONFIG_FTI2C010_BASE2
+CONFIG_FTI2C010_BASE3
+CONFIG_FTI2C010_CLOCK
+CONFIG_FTI2C010_TIMEOUT
+CONFIG_FTIDE020S_BASE
+CONFIG_FTIIC010_BASE
+CONFIG_FTINTC010_BASE
+CONFIG_FTLCDC100_BASE
+CONFIG_FTMAC100
+CONFIG_FTMAC100_BASE
+CONFIG_FTMAC110_BASE
+CONFIG_FTPCI100_BASE
+CONFIG_FTPCI100_IO_SIZE
+CONFIG_FTPCI100_MEM_BASE
+CONFIG_FTPCI100_MEM_SIZE
+CONFIG_FTPMU010
+CONFIG_FTPMU010_BASE
+CONFIG_FTPMU010_POWER
+CONFIG_FTPWM010_BASE
+CONFIG_FTRACE_MCOUNT_RECORD
+CONFIG_FTRTC010_BASE
+CONFIG_FTRTC010_EXTCLK
+CONFIG_FTRTC010_PCLK
+CONFIG_FTSDC010
+CONFIG_FTSDC010_BASE
+CONFIG_FTSDC010_BASE_LIST
+CONFIG_FTSDC010_NUMBER
+CONFIG_FTSDC010_SDIO
+CONFIG_FTSDC021_CLOCK
+CONFIG_FTSDMC021
+CONFIG_FTSDMC021_BASE
+CONFIG_FTSMC020
+CONFIG_FTSMC020_BASE
+CONFIG_FTSSP010_01_BASE
+CONFIG_FTSSP010_02_BASE
+CONFIG_FTTMR010_BASE
+CONFIG_FTTMR010_EXT_CLK
+CONFIG_FTUART010_01_BASE
+CONFIG_FTUART010_02_BASE
+CONFIG_FTUART010_03_BASE
+CONFIG_FTWDT010_BASE
+CONFIG_FTWDT010_WATCHDOG
+CONFIG_FUNC_ISRAM_ADDR
+CONFIG_FWUPDATE_DEBUG
+CONFIG_FZOTG266HD0A_BASE
+CONFIG_GATEWAYIP
+CONFIG_GCOV_KERNEL
+CONFIG_GCOV_PROFILE_ALL
+CONFIG_GENERIC_ATMEL_MCI
+CONFIG_GENERIC_MMC
+CONFIG_GICV2
+CONFIG_GICV3
+CONFIG_GLOBAL_DATA_NOT_REG10
+CONFIG_GLOBAL_TIMER
+CONFIG_GMII
+CONFIG_GOOD_SESH4
+CONFIG_GPCNTRL
+CONFIG_GPCS_PHY1_ADDR
+CONFIG_GPCS_PHY2_ADDR
+CONFIG_GPCS_PHY3_ADDR
+CONFIG_GPCS_PHY_ADDR
+CONFIG_GPIO
+CONFIG_GPIO_ENABLE_SPI_FLASH
+CONFIG_GPIO_LED
+CONFIG_GPIO_LED_INVERTED_TABLE
+CONFIG_GPIO_LED_STUBS
+CONFIG_GREEN_LED
+CONFIG_GRETH
+CONFIG_GRETH_10MBIT
+CONFIG_GRSIM
+CONFIG_GRXC3S1500
+CONFIG_GR_EP2S60
+CONFIG_GURNARD_FPGA
+CONFIG_GURNARD_SPLASH
+CONFIG_GZIP
+CONFIG_GZIP_COMPRESSED
+CONFIG_GZIP_COMPRESS_DEF_SZ
+CONFIG_G_DNL_THOR_PRODUCT_NUM
+CONFIG_G_DNL_THOR_VENDOR_NUM
+CONFIG_G_DNL_UMS_PRODUCT_NUM
+CONFIG_G_DNL_UMS_VENDOR_NUM
+CONFIG_H264_FREQ
+CONFIG_H8300
+CONFIG_HALEAKALA
+CONFIG_HARD_I2C
+CONFIG_HARD_SPI
+CONFIG_HASH_VERIFY
+CONFIG_HAS_DATAFLASH
+CONFIG_HAS_ETH0
+CONFIG_HAS_ETH1
+CONFIG_HAS_ETH2
+CONFIG_HAS_ETH3
+CONFIG_HAS_ETH4
+CONFIG_HAS_ETH5
+CONFIG_HAS_ETH7
+CONFIG_HAS_FEC
+CONFIG_HAS_FSL_DR_USB
+CONFIG_HAS_FSL_MPH_USB
+CONFIG_HAS_FSL_XHCI_USB
+CONFIG_HAS_POST
+CONFIG_HAS_VR
+CONFIG_HAVE_ACPI_RESUME
+CONFIG_HAVE_OWN_RESET
+CONFIG_HCLK_FREQ
+CONFIG_HDBOOT
+CONFIG_HDMI_ENCODER_I2C_ADDR
+CONFIG_HETROGENOUS_CLUSTERS
+CONFIG_HIDE_LOGO_VERSION
+CONFIG_HIGH_BATS
+CONFIG_HIKEY_DWMMC
+CONFIG_HIKEY_GPIO
+CONFIG_HIS_DRIVER
+CONFIG_HITACHI_SP19X001_Z1A
+CONFIG_HITACHI_SX14
+CONFIG_HLD1045
+CONFIG_HOSTNAME
+CONFIG_HOST_MAX_DEVICES
+CONFIG_HOTPLUG
+CONFIG_HPS_ALTERAGRP_DBGATCLK
+CONFIG_HPS_ALTERAGRP_MAINCLK
+CONFIG_HPS_ALTERAGRP_MPUCLK
+CONFIG_HPS_CLK_CAN0_HZ
+CONFIG_HPS_CLK_CAN1_HZ
+CONFIG_HPS_CLK_EMAC0_HZ
+CONFIG_HPS_CLK_EMAC1_HZ
+CONFIG_HPS_CLK_F2S_PER_REF_HZ
+CONFIG_HPS_CLK_F2S_SDR_REF_HZ
+CONFIG_HPS_CLK_GPIODB_HZ
+CONFIG_HPS_CLK_L4_MP_HZ
+CONFIG_HPS_CLK_L4_SP_HZ
+CONFIG_HPS_CLK_MAINVCO_HZ
+CONFIG_HPS_CLK_NAND_HZ
+CONFIG_HPS_CLK_OSC1_HZ
+CONFIG_HPS_CLK_OSC2_HZ
+CONFIG_HPS_CLK_PERVCO_HZ
+CONFIG_HPS_CLK_QSPI_HZ
+CONFIG_HPS_CLK_SDMMC_HZ
+CONFIG_HPS_CLK_SDRVCO_HZ
+CONFIG_HPS_CLK_SPIM_HZ
+CONFIG_HPS_CLK_USBCLK_HZ
+CONFIG_HPS_DBCTRL_STAYOSC1
+CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
+CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH
+CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH
+CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
+CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT
+CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT
+CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK
+CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK
+CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP
+CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP
+CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT
+CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK
+CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK
+CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK
+CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK
+CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT
+CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
+CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT
+CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK
+CONFIG_HPS_MAINPLLGRP_VCO_DENOM
+CONFIG_HPS_MAINPLLGRP_VCO_NUMER
+CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK
+CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK
+CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK
+CONFIG_HPS_PERPLLGRP_DIV_USBCLK
+CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT
+CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT
+CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK
+CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT
+CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT
+CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT
+CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT
+CONFIG_HPS_PERPLLGRP_SRC_NAND
+CONFIG_HPS_PERPLLGRP_SRC_QSPI
+CONFIG_HPS_PERPLLGRP_SRC_SDMMC
+CONFIG_HPS_PERPLLGRP_VCO_DENOM
+CONFIG_HPS_PERPLLGRP_VCO_NUMER
+CONFIG_HPS_PERPLLGRP_VCO_PSRC
+CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT
+CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE
+CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT
+CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE
+CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT
+CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE
+CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT
+CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE
+CONFIG_HPS_SDRPLLGRP_VCO_DENOM
+CONFIG_HPS_SDRPLLGRP_VCO_NUMER
+CONFIG_HPS_SDRPLLGRP_VCO_SSRC
+CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR
+CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP
+CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH
+CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP
+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER
+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN
+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN
+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN
+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL
+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE
+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS
+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN
+CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT
+CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH
+CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS
+CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS
+CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS
+CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS
+CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH
+CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH
+CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN
+CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ
+CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
+CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
+CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
+CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
+CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
+CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED
+CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED
+CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED
+CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
+CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES
+CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES
+CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0
+CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32
+CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0
+CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4
+CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36
+CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
+CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0
+CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32
+CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64
+CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0
+CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32
+CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0
+CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14
+CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46
+CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0
+CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN
+CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP
+CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
+CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
+CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
+CONFIG_HP_CLK_FREQ
+CONFIG_HRCON
+CONFIG_HRCON_DH
+CONFIG_HRCON_FANS
+CONFIG_HSMMC2_8BIT
+CONFIG_HUSH_INIT_VAR
+CONFIG_HVBOOT
+CONFIG_HWCONFIG
+CONFIG_HW_ENV_SETTINGS
+CONFIG_HW_WATCHDOG
+CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
+CONFIG_HW_WATCHDOG_TIMEOUT_MS
+CONFIG_I2C
+CONFIG_I2CFAST
+CONFIG_I2C_CHIPADDRESS
+CONFIG_I2C_CMD_TREE
+CONFIG_I2C_ENV_EEPROM_BUS
+CONFIG_I2C_FPGA
+CONFIG_I2C_GSC
+CONFIG_I2C_MAC_OFFSET
+CONFIG_I2C_MBB_TIMEOUT
+CONFIG_I2C_MULTI_BUS
+CONFIG_I2C_MV
+CONFIG_I2C_MVTWSI
+CONFIG_I2C_MVTWSI_BASE
+CONFIG_I2C_MVTWSI_BASE0
+CONFIG_I2C_MVTWSI_BASE1
+CONFIG_I2C_MVTWSI_BASE2
+CONFIG_I2C_MVTWSI_BASE3
+CONFIG_I2C_MVTWSI_BASE4
+CONFIG_I2C_MVTWSI_BASE5
+CONFIG_I2C_MXC
+CONFIG_I2C_PMIC
+CONFIG_I2C_REPEATED_START
+CONFIG_I2C_RTC_ADDR
+CONFIG_I2C_TIMEOUT
+CONFIG_IBM_EMAC4_V4
+CONFIG_ICACHE
+CONFIG_ICACHE_OFF
+CONFIG_ICON
+CONFIG_ICS307_REFCLK_HZ
+CONFIG_IDE_8xx_DIRECT
+CONFIG_IDE_8xx_PCCARD
+CONFIG_IDE_INIT_POSTRESET
+CONFIG_IDE_LED
+CONFIG_IDE_PCMCIA
+CONFIG_IDE_PREINIT
+CONFIG_IDE_REG_CS
+CONFIG_IDE_RESET
+CONFIG_IDE_RESET_ROUTINE
+CONFIG_IDE_SIL680
+CONFIG_IDE_SWAP_IO
+CONFIG_IDS8313
+CONFIG_IDT8T49N222A
+CONFIG_ID_EEPROM
+CONFIG_IFM_DEFAULT_ENV_NEW
+CONFIG_IFM_DEFAULT_ENV_OLD
+CONFIG_IFM_DEFAULT_ENV_SETTINGS
+CONFIG_IFM_SENSOR_TYPE
+CONFIG_IMA
+CONFIG_IMAGE_FORMAT_LEGACY
+CONFIG_IMX
+CONFIG_IMX31_PHYCORE_EET
+CONFIG_IMX6_PWM_PER_CLK
+CONFIG_IMX_HDMI
+CONFIG_IMX_NAND
+CONFIG_IMX_OTP
+CONFIG_IMX_VIDEO_SKIP
+CONFIG_IMX_WATCHDOG
+CONFIG_INETSPACE_V2
+CONFIG_INITRD_TAG
+CONFIG_INIT_CRITICAL
+CONFIG_INIT_IGNORE_ERROR
+CONFIG_INIT_TLB
+CONFIG_INI_ALLOW_MULTILINE
+CONFIG_INI_CASE_INSENSITIVE
+CONFIG_INI_MAX_LINE
+CONFIG_INI_MAX_NAME
+CONFIG_INI_MAX_SECTION
+CONFIG_INKA4X0
+CONFIG_INTEGRITY
+CONFIG_INTEL_ICH6_GPIO
+CONFIG_INTERRUPTS
+CONFIG_INTIB
+CONFIG_IO
+CONFIG_IO64
+CONFIG_IOCON
+CONFIG_IODELAY_RECALIBRATION
+CONFIG_IOMUX_LPSR
+CONFIG_IOMUX_SHARE_CONF_REG
+CONFIG_IOS
+CONFIG_IO_TRACE
+CONFIG_IP86x
+CONFIG_IPADDR
+CONFIG_IPADDR1
+CONFIG_IPADDR2
+CONFIG_IPAM390_GPIO_BOOTMODE
+CONFIG_IPAM390_GPIO_LED_GREEN
+CONFIG_IPAM390_GPIO_LED_RED
+CONFIG_IPEK01
+CONFIG_IPIPE
+CONFIG_IPROC
+CONFIG_IPUV3_CLK
+CONFIG_IP_DEFRAG
+CONFIG_IRAM_BASE
+CONFIG_IRAM_END
+CONFIG_IRAM_SIZE
+CONFIG_IRAM_STACK
+CONFIG_IRAM_TOP
+CONFIG_IRDA_BASE
+CONFIG_ISO_PARTITION
+CONFIG_ISP1362_USB
+CONFIG_IS_BUILTIN
+CONFIG_IS_ENABLED
+CONFIG_IS_INVALID
+CONFIG_IS_MODULE
+CONFIG_IS_VALID
+CONFIG_IVMS8
+CONFIG_JFFS2_CMDLINE
+CONFIG_JFFS2_DEV
+CONFIG_JFFS2_LZO
+CONFIG_JFFS2_NAND
+CONFIG_JFFS2_PART_OFFSET
+CONFIG_JFFS2_PART_SIZE
+CONFIG_JFFS2_SUMMARY
+CONFIG_JRSTARTR_JR0
+CONFIG_JTAG_CONSOLE
+CONFIG_JTAG_CONSOLE_TIMEOUT
+CONFIG_JUPITER
+CONFIG_KALLSYMS
+CONFIG_KASAN
+CONFIG_KATMAI
+CONFIG_KCLK_DIS
+CONFIG_KEEP_SERVERADDR
+CONFIG_KERNEL_OFFSET
+CONFIG_KEYBOARD
+CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE
+CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE
+CONFIG_KEYSTONE_RBL_NAND
+CONFIG_KEY_REVOCATION
+CONFIG_KGDB_BAUDRATE
+CONFIG_KGDB_EXTC_PINSEL
+CONFIG_KGDB_EXTC_RATE
+CONFIG_KGDB_INDEX
+CONFIG_KGDB_ON_SCC
+CONFIG_KGDB_ON_SMC
+CONFIG_KGDB_SER_INDEX
+CONFIG_KILAUEA
+CONFIG_KIRKWOOD_EGIGA_INIT
+CONFIG_KIRKWOOD_GPIO
+CONFIG_KIRKWOOD_PCIE_INIT
+CONFIG_KIRKWOOD_RGMII_PAD_1V8
+CONFIG_KIRKWOOD_SPI
+CONFIG_KIRQ_EN
+CONFIG_KM8321
+CONFIG_KM8XX
+CONFIG_KMCOGE4
+CONFIG_KMCOGE5NE
+CONFIG_KMETER1
+CONFIG_KMLION1
+CONFIG_KMOPTI2
+CONFIG_KMP204X
+CONFIG_KMSUPX5
+CONFIG_KMTEGR1
+CONFIG_KMTEPR2
+CONFIG_KMVECT1
+CONFIG_KM_82XX
+CONFIG_KM_BOARD_EXTRA_ENV
+CONFIG_KM_BOARD_NAME
+CONFIG_KM_COGE5UN
+CONFIG_KM_COMMON_ETH_INIT
+CONFIG_KM_CONSOLE_TTY
+CONFIG_KM_CRAMFS_ADDR
+CONFIG_KM_DEF_ARCH
+CONFIG_KM_DEF_BOOT_ARGS_CPU
+CONFIG_KM_DEF_ENV
+CONFIG_KM_DEF_ENV_BOOTARGS
+CONFIG_KM_DEF_ENV_BOOTPARAMS
+CONFIG_KM_DEF_ENV_BOOTTARGETS
+CONFIG_KM_DEF_ENV_CONSTANTS
+CONFIG_KM_DEF_ENV_CPU
+CONFIG_KM_DEF_ENV_FLASH_BOOT
+CONFIG_KM_DEF_NETDEV
+CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
+CONFIG_KM_DISABLE_PCI
+CONFIG_KM_DISABLE_PCIE
+CONFIG_KM_ECC_MODE
+CONFIG_KM_ENV_IS_IN_SPI_NOR
+CONFIG_KM_FDT_ADDR
+CONFIG_KM_FPGA_CONFIG
+CONFIG_KM_I2C_ABORT
+CONFIG_KM_IVM_BUS
+CONFIG_KM_KERNEL_ADDR
+CONFIG_KM_KIRKWOOD
+CONFIG_KM_KIRKWOOD_128M16
+CONFIG_KM_KIRKWOOD_PCI
+CONFIG_KM_MGCOGE3UN
+CONFIG_KM_MVEXTSW_ADDR
+CONFIG_KM_NEW_ENV
+CONFIG_KM_NUSA
+CONFIG_KM_PHRAM
+CONFIG_KM_PIGGY4_88E6061
+CONFIG_KM_PIGGY4_88E6352
+CONFIG_KM_PNVRAM
+CONFIG_KM_PORTL2
+CONFIG_KM_RESERVED_PRAM
+CONFIG_KM_ROOTFSSIZE
+CONFIG_KM_SUGP1
+CONFIG_KM_SUV31
+CONFIG_KM_UBI_LINUX_MTD
+CONFIG_KM_UBI_PARTITION_NAME_APP
+CONFIG_KM_UBI_PARTITION_NAME_BOOT
+CONFIG_KM_UBI_PART_BOOT_OPTS
+CONFIG_KM_UIMAGE_NAME
+CONFIG_KM_UPDATE_UBOOT
+CONFIG_KONA
+CONFIG_KONA_GPIO
+CONFIG_KONA_RESET_S
+CONFIG_KPROBES
+CONFIG_KS8851_MLL
+CONFIG_KS8851_MLL_BASEADDR
+CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE
+CONFIG_KSNAV_NETCP_PDMA_RX_BASE
+CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM
+CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE
+CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM
+CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE
+CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE
+CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE
+CONFIG_KSNAV_NETCP_PDMA_TX_BASE
+CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM
+CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE
+CONFIG_KSNAV_PKTDMA_NETCP
+CONFIG_KSNAV_QM_BASE_ADDRESS
+CONFIG_KSNAV_QM_CONF_BASE
+CONFIG_KSNAV_QM_DESC_SETUP_BASE
+CONFIG_KSNAV_QM_INTD_CONF_BASE
+CONFIG_KSNAV_QM_LINK_RAM_BASE
+CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE
+CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE
+CONFIG_KSNAV_QM_PDSP1_CMD_BASE
+CONFIG_KSNAV_QM_PDSP1_CTRL_BASE
+CONFIG_KSNAV_QM_PDSP1_IRAM_BASE
+CONFIG_KSNAV_QM_QPOOL_NUM
+CONFIG_KSNAV_QM_QUEUE_STATUS_BASE
+CONFIG_KSNAV_QM_REGION_NUM
+CONFIG_KSNAV_QM_STATUS_RAM_BASE
+CONFIG_KSNET_CPSW_NUM_PORTS
+CONFIG_KSNET_MAC_ID_BASE
+CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+CONFIG_KSNET_NETCP_BASE
+CONFIG_KSNET_NETCP_V1_0
+CONFIG_KSNET_NETCP_V1_5
+CONFIG_KSNET_SERDES_LANES_PER_SGMII
+CONFIG_KSNET_SERDES_SGMII2_BASE
+CONFIG_KSNET_SERDES_SGMII_BASE
+CONFIG_KVM_GUEST
+CONFIG_KW88F6192
+CONFIG_KW88F6281
+CONFIG_KW88F6702
+CONFIG_KYOCERA_KCS057QV1AJ
+CONFIG_KZM_A9_GT
+CONFIG_L1_INIT_RAM
+CONFIG_L2_CACHE
+CONFIG_LAN91C96_USE_32_BIT
+CONFIG_LAST_STAGE_INIT
+CONFIG_LAYERSCAPE_NS_ACCESS
+CONFIG_LBA48
+CONFIG_LBD
+CONFIG_LBDAF
+CONFIG_LCD_ALIGNMENT
+CONFIG_LCD_BMP_RLE8
+CONFIG_LCD_DT_SIMPLEFB
+CONFIG_LCD_INFO
+CONFIG_LCD_INFO_BELOW_LOGO
+CONFIG_LCD_IN_PSRAM
+CONFIG_LCD_LOGO
+CONFIG_LCD_MENU
+CONFIG_LCD_MENU_BOARD
+CONFIG_LCD_NOSTDOUT
+CONFIG_LCD_ROTATION
+CONFIG_LD9040
+CONFIG_LEGACY
+CONFIG_LEGACY_BOOTCMD_ENV
+CONFIG_LEON_RAM_SDRAM
+CONFIG_LEON_RAM_SDRAM_NOSRAM
+CONFIG_LEON_RAM_SELECT
+CONFIG_LEON_RAM_SRAM
+CONFIG_LG4573
+CONFIG_LG4573_BUS
+CONFIG_LG4573_CS
+CONFIG_LIBATA
+CONFIG_LIB_HW_RAND
+CONFIG_LIB_UUID
+CONFIG_LINUX
+CONFIG_LINUX_CMDLINE_ADDR
+CONFIG_LINUX_CMDLINE_SIZE
+CONFIG_LINUX_RESET_VEC
+CONFIG_LITTLETON_LCD
+CONFIG_LMB
+CONFIG_LMS283GF05
+CONFIG_LOADADDR
+CONFIG_LOADCMD
+CONFIG_LOADS_ECHO
+CONFIG_LOGBUFFER
+CONFIG_LOWBOOT
+CONFIG_LOWPOWER_ADDR
+CONFIG_LOWPOWER_FLAG
+CONFIG_LOW_MCFCLK
+CONFIG_LPC32XX_ETH
+CONFIG_LPC32XX_ETH_BUFS_BASE
+CONFIG_LPC32XX_HSUART
+CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY
+CONFIG_LPC32XX_NAND_MLC_NAND_TA
+CONFIG_LPC32XX_NAND_MLC_RD_HIGH
+CONFIG_LPC32XX_NAND_MLC_RD_LOW
+CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY
+CONFIG_LPC32XX_NAND_MLC_WR_HIGH
+CONFIG_LPC32XX_NAND_MLC_WR_LOW
+CONFIG_LPC32XX_NAND_SLC_RDR_CLKS
+CONFIG_LPC32XX_NAND_SLC_RHOLD
+CONFIG_LPC32XX_NAND_SLC_RSETUP
+CONFIG_LPC32XX_NAND_SLC_RWIDTH
+CONFIG_LPC32XX_NAND_SLC_WDR_CLKS
+CONFIG_LPC32XX_NAND_SLC_WHOLD
+CONFIG_LPC32XX_NAND_SLC_WSETUP
+CONFIG_LPC32XX_NAND_SLC_WWIDTH
+CONFIG_LPC32XX_SDRAM_
+CONFIG_LPC32XX_SPL
+CONFIG_LPC32XX_SSP
+CONFIG_LPC32XX_SSP_TIMEOUT
+CONFIG_LPC_BASE
+CONFIG_LPC_IO_BASE
+CONFIG_LPUART
+CONFIG_LPUART_32B_REG
+CONFIG_LQ035Q1_LCD_MODE
+CONFIG_LQ035Q1_SPI_BUS
+CONFIG_LQ035Q1_SPI_CS
+CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
+CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
+CONFIG_LQ038J7DH53
+CONFIG_LS102XA
+CONFIG_LS102XA_STREAM_ID
+CONFIG_LS1043A
+CONFIG_LS2080A
+CONFIG_LSCHLV2
+CONFIG_LSXHL
+CONFIG_LUAN
+CONFIG_LWMON5
+CONFIG_LXT971_NO_SLEEP
+CONFIG_LYNXKDI
+CONFIG_LZMA
+CONFIG_LZO
+CONFIG_M41T94_SPI_CS
+CONFIG_M520x
+CONFIG_M52277EVB
+CONFIG_M5253DEMO
+CONFIG_M5253EVBE
+CONFIG_M5275EVB
+CONFIG_M5301x
+CONFIG_M54418TWR
+CONFIG_M54451EVB
+CONFIG_M54455EVB
+CONFIG_M88E1111_DISABLE_FIBER
+CONFIG_M88E1111_PHY
+CONFIG_M88E1112_PHY
+CONFIG_M88E1141_PHY
+CONFIG_MACB
+CONFIG_MACB0_PHY
+CONFIG_MACB1_PHY
+CONFIG_MACB2_PHY
+CONFIG_MACB3_PHY
+CONFIG_MACB_SEARCH_PHY
+CONFIG_MACH_A0
+CONFIG_MACH_A2F
+CONFIG_MACH_ABACUS
+CONFIG_MACH_ABB_GMA_1_1
+CONFIG_MACH_ABILENE
+CONFIG_MACH_ABLE
+CONFIG_MACH_ACER_A5
+CONFIG_MACH_ACER_A8
+CONFIG_MACH_ACER_GAUGUIN
+CONFIG_MACH_ACER_MAYA
+CONFIG_MACH_ACMENETUSFOXG20
+CONFIG_MACH_ACMEROVER1
+CONFIG_MACH_ACRO37XBRD
+CONFIG_MACH_ACS5K
+CONFIG_MACH_ACSX106
+CONFIG_MACH_ADSSPHERE
+CONFIG_MACH_AEBL
+CONFIG_MACH_AF4000
+CONFIG_MACH_AFEB9260
+CONFIG_MACH_AG11005
+CONFIG_MACH_AG5EVM
+CONFIG_MACH_AKITA
+CONFIG_MACH_AMK_A4
+CONFIG_MACH_AML_M5900
+CONFIG_MACH_AMS_DELTA
+CONFIG_MACH_ANCHOVY
+CONFIG_MACH_ANTARES
+CONFIG_MACH_ANTERO
+CONFIG_MACH_ANUBIS
+CONFIG_MACH_ANW6410
+CONFIG_MACH_AP4EVB
+CONFIG_MACH_APALIS_T30
+CONFIG_MACH_APP3K_ROBIN
+CONFIG_MACH_AQUARIUS
+CONFIG_MACH_AQUILA
+CONFIG_MACH_ARCOM_VULCAN
+CONFIG_MACH_ARCOM_ZEUS
+CONFIG_MACH_ARK9431
+CONFIG_MACH_ARMADA_XP_DB
+CONFIG_MACH_ARMADILLO460
+CONFIG_MACH_ARMADILLO5X0
+CONFIG_MACH_ARMADILLO800EVA
+CONFIG_MACH_ARMCORE
+CONFIG_MACH_ARMLEX4210
+CONFIG_MACH_ARMLGUEST
+CONFIG_MACH_AROWANA
+CONFIG_MACH_ARTHUR
+CONFIG_MACH_ARUBA
+CONFIG_MACH_AS1167
+CONFIG_MACH_ASL_PHOENIX
+CONFIG_MACH_ASPEN
+CONFIG_MACH_ASPENITE
+CONFIG_MACH_AST2200
+CONFIG_MACH_AT2440EVB
+CONFIG_MACH_AT572D940HFEB
+CONFIG_MACH_AT91CAP7STK
+CONFIG_MACH_AT91CAP7XDK
+CONFIG_MACH_AT91CAP9ADK
+CONFIG_MACH_AT91EB01
+CONFIG_MACH_AT91RM9200EK
+CONFIG_MACH_AT91SAM9260EK
+CONFIG_MACH_AT91SAM9261EK
+CONFIG_MACH_AT91SAM9263DESK16L
+CONFIG_MACH_AT91SAM9263EK
+CONFIG_MACH_AT91SAM9263OTLITE
+CONFIG_MACH_AT91SAM9G10EK
+CONFIG_MACH_AT91SAM9G20EK
+CONFIG_MACH_AT91SAM9G20EK_2MMC
+CONFIG_MACH_AT91SAM9G45EKES
+CONFIG_MACH_AT91SAM9M10G45EK
+CONFIG_MACH_AT91SAM9RLEK
+CONFIG_MACH_AT91SAM9X5EK
+CONFIG_MACH_ATDGP318
+CONFIG_MACH_ATEB9200
+CONFIG_MACH_ATHENE
+CONFIG_MACH_ATLAS5_C1
+CONFIG_MACH_AUTOBOT
+CONFIG_MACH_AVENGERS_LITE
+CONFIG_MACH_AVILA
+CONFIG_MACH_AWM2
+CONFIG_MACH_AX502
+CONFIG_MACH_AX8008
+CONFIG_MACH_B5500
+CONFIG_MACH_BASI
+CONFIG_MACH_BCM2708
+CONFIG_MACH_BCM589X
+CONFIG_MACH_BCMHANA_SV
+CONFIG_MACH_BCMHANA_TABLET
+CONFIG_MACH_BCMRING
+CONFIG_MACH_BEECT
+CONFIG_MACH_BIGDISK
+CONFIG_MACH_BIO3K
+CONFIG_MACH_BIPNET
+CONFIG_MACH_BLISS
+CONFIG_MACH_BLISSC
+CONFIG_MACH_BLUECHEESE
+CONFIG_MACH_BLUEPOINT
+CONFIG_MACH_BLUESHARK
+CONFIG_MACH_BOCKW
+CONFIG_MACH_BONAIRE
+CONFIG_MACH_BORABORA
+CONFIG_MACH_BORZOI
+CONFIG_MACH_BROWNSTONE
+CONFIG_MACH_BSTBRD
+CONFIG_MACH_BTMAVB101
+CONFIG_MACH_BTMAWB101
+CONFIG_MACH_BUBBA3
+CONFIG_MACH_BUG
+CONFIG_MACH_BUG20
+CONFIG_MACH_BURY_BL7582
+CONFIG_MACH_BURY_BPS5270
+CONFIG_MACH_BV07
+CONFIG_MACH_C2MMI
+CONFIG_MACH_CALLISTO
+CONFIG_MACH_CAM60
+CONFIG_MACH_CAPC7117
+CONFIG_MACH_CARDHU
+CONFIG_MACH_CARMEVA
+CONFIG_MACH_CAYENNE
+CONFIG_MACH_CC9P9360DEV
+CONFIG_MACH_CC9P9360JS
+CONFIG_MACH_CCMX53
+CONFIG_MACH_CCMX53JS
+CONFIG_MACH_CCWMX51MUT
+CONFIG_MACH_CCWMX53
+CONFIG_MACH_CCWMX53JS
+CONFIG_MACH_CENTRO
+CONFIG_MACH_CETUS9263
+CONFIG_MACH_CHACHA
+CONFIG_MACH_CHALTEN_XA1
+CONFIG_MACH_CHARON
+CONFIG_MACH_CLOD
+CONFIG_MACH_CM4745
+CONFIG_MACH_CM_A510
+CONFIG_MACH_CM_T35
+CONFIG_MACH_CM_T3517
+CONFIG_MACH_CM_T3730
+CONFIG_MACH_CM_X300
+CONFIG_MACH_CNS2133EVB
+CONFIG_MACH_CNS21XX
+CONFIG_MACH_CNS3420VB
+CONFIG_MACH_COBRAL138
+CONFIG_MACH_COCONUT
+CONFIG_MACH_COLIBRI
+CONFIG_MACH_COLIBRI300
+CONFIG_MACH_COLIBRI320
+CONFIG_MACH_COLIBRI_T20
+CONFIG_MACH_COLIBRI_T30
+CONFIG_MACH_CONTROLTEK9G20
+CONFIG_MACH_CORETEC_VCX7400
+CONFIG_MACH_CORGI
+CONFIG_MACH_CPUAT9G20
+CONFIG_MACH_CPX2
+CONFIG_MACH_CRANEBOARD
+CONFIG_MACH_CRUX
+CONFIG_MACH_CSB337
+CONFIG_MACH_CSB637
+CONFIG_MACH_CSB726
+CONFIG_MACH_CSC
+CONFIG_MACH_CTBU_GEN2
+CONFIG_MACH_CTERA_PLUG_C2
+CONFIG_MACH_CURACAO
+CONFIG_MACH_CV2201
+CONFIG_MACH_CV2202
+CONFIG_MACH_CV2203
+CONFIG_MACH_CWAM1808
+CONFIG_MACH_CWDM365
+CONFIG_MACH_CWME9210
+CONFIG_MACH_CWME9210JS
+CONFIG_MACH_CWMX233
+CONFIG_MACH_D2NET
+CONFIG_MACH_D2NET_V2
+CONFIG_MACH_D2PLUG
+CONFIG_MACH_DA850_K5
+CONFIG_MACH_DAINTREE_CWAC
+CONFIG_MACH_DATAWAY
+CONFIG_MACH_DAVINCI_CALIMAIN
+CONFIG_MACH_DAVINCI_DA830_EVM
+CONFIG_MACH_DAVINCI_DA850_EVM
+CONFIG_MACH_DAVINCI_DM355_EVM
+CONFIG_MACH_DAVINCI_DM355_MMM
+CONFIG_MACH_DAVINCI_DM365_BV
+CONFIG_MACH_DAVINCI_DM365_DVR
+CONFIG_MACH_DAVINCI_DM365_EVM
+CONFIG_MACH_DAVINCI_DM6467TEVM
+CONFIG_MACH_DAVINCI_DM6467_EVM
+CONFIG_MACH_DAVINCI_EVM
+CONFIG_MACH_DAVINCI_PICTO
+CONFIG_MACH_DAWAD7
+CONFIG_MACH_DB78X00_BP
+CONFIG_MACH_DB88F5281
+CONFIG_MACH_DB88F6281_BP
+CONFIG_MACH_DDNAS
+CONFIG_MACH_DDPLUG
+CONFIG_MACH_DDS
+CONFIG_MACH_DEEP_R_EK_1
+CONFIG_MACH_DEVIXP
+CONFIG_MACH_DEVKIT8000
+CONFIG_MACH_DGM3240
+CONFIG_MACH_DIMMSAM9G20
+CONFIG_MACH_DIMM_IMX28
+CONFIG_MACH_DIMM_MX257
+CONFIG_MACH_DINGO
+CONFIG_MACH_DIR665
+CONFIG_MACH_DM355_LEOPARD
+CONFIG_MACH_DM365_CV100
+CONFIG_MACH_DM368_LEOPARD
+CONFIG_MACH_DM3730_SOM_LV
+CONFIG_MACH_DM3730_TORPEDO
+CONFIG_MACH_DM6441_ESP
+CONFIG_MACH_DM6446_ADBOX
+CONFIG_MACH_DMA6410
+CONFIG_MACH_DMA_THUNDERBUG
+CONFIG_MACH_DMW96
+CONFIG_MACH_DNS323
+CONFIG_MACH_DOCKSTAR
+CONFIG_MACH_DOORBOY
+CONFIG_MACH_DOUBLESHOT
+CONFIG_MACH_DOVE_AVNG_V3
+CONFIG_MACH_DOVE_DB
+CONFIG_MACH_DP6XX
+CONFIG_MACH_DRAGONET
+CONFIG_MACH_DSM320
+CONFIG_MACH_DSMG600
+CONFIG_MACH_DURIAN
+CONFIG_MACH_DYNASTY
+CONFIG_MACH_E10
+CONFIG_MACH_E330
+CONFIG_MACH_E350
+CONFIG_MACH_E400
+CONFIG_MACH_E740
+CONFIG_MACH_E750
+CONFIG_MACH_E800
+CONFIG_MACH_EA20
+CONFIG_MACH_EA2478DEVKIT
+CONFIG_MACH_EAG_CI4000
+CONFIG_MACH_EASYCRRH
+CONFIG_MACH_EC4350SDB
+CONFIG_MACH_EC4350TBM
+CONFIG_MACH_ECBAT91
+CONFIG_MACH_ECO920
+CONFIG_MACH_ECUV5
+CONFIG_MACH_EDB9301
+CONFIG_MACH_EDB9302
+CONFIG_MACH_EDB9302A
+CONFIG_MACH_EDB9307
+CONFIG_MACH_EDB9307A
+CONFIG_MACH_EDB9312
+CONFIG_MACH_EDB9315
+CONFIG_MACH_EDB9315A
+CONFIG_MACH_EDISON
+CONFIG_MACH_EDMINIV2
+CONFIG_MACH_EDMINI_V2
+CONFIG_MACH_EELX2
+CONFIG_MACH_EIGEN_TTR
+CONFIG_MACH_ELEPHANT
+CONFIG_MACH_ELKE
+CONFIG_MACH_ELOG
+CONFIG_MACH_EM1SY
+CONFIG_MACH_EM7210
+CONFIG_MACH_EMERALD
+CONFIG_MACH_EM_X270
+CONFIG_MACH_ENCORE
+CONFIG_MACH_ENDIAN_MINI
+CONFIG_MACH_EP80219
+CONFIG_MACH_EPC10
+CONFIG_MACH_EPIPHAN
+CONFIG_MACH_ES2440
+CONFIG_MACH_ESATA_SHEEVAPLUG
+CONFIG_MACH_ESL_MOBILIS_A
+CONFIG_MACH_ESL_MOBILIS_B
+CONFIG_MACH_ESL_WAVE_A
+CONFIG_MACH_ESL_WAVE_B
+CONFIG_MACH_ESPRESSO
+CONFIG_MACH_ETHERPRO_ISP
+CONFIG_MACH_ETNA
+CONFIG_MACH_EUKREA_CPUIMX25SD
+CONFIG_MACH_EUKREA_CPUIMX35SD
+CONFIG_MACH_EUKREA_CPUIMX51
+CONFIG_MACH_EUKREA_CPUIMX51SD
+CONFIG_MACH_EVA2000
+CONFIG_MACH_EVSY
+CONFIG_MACH_EXEDA
+CONFIG_MACH_EXPRESS
+CONFIG_MACH_EXPRESSCT
+CONFIG_MACH_EXPRESSH
+CONFIG_MACH_EXPRESS_KT
+CONFIG_MACH_EZX_A1200
+CONFIG_MACH_EZX_A780
+CONFIG_MACH_EZX_A910
+CONFIG_MACH_EZX_E2
+CONFIG_MACH_EZX_E6
+CONFIG_MACH_EZX_E680
+CONFIG_MACH_FA9X27
+CONFIG_MACH_FFCORE
+CONFIG_MACH_FLEXIBITY
+CONFIG_MACH_FLINT
+CONFIG_MACH_FLYER
+CONFIG_MACH_FRISMS
+CONFIG_MACH_FRRHWCDMA60W
+CONFIG_MACH_FSG
+CONFIG_MACH_FSM9XXX_FFA
+CONFIG_MACH_FSM9XXX_SURF
+CONFIG_MACH_FS_S5PC100
+CONFIG_MACH_FUJI
+CONFIG_MACH_FWBD_0404
+CONFIG_MACH_G3EVM
+CONFIG_MACH_G4EVM
+CONFIG_MACH_GATEWAY7001
+CONFIG_MACH_GENEVA_B5
+CONFIG_MACH_GESBC9312
+CONFIG_MACH_GFS_SPM
+CONFIG_MACH_GINGER
+CONFIG_MACH_GIRA_KNXIP_ROUTER
+CONFIG_MACH_GLANTANK
+CONFIG_MACH_GNET_SGCE
+CONFIG_MACH_GNET_SGME
+CONFIG_MACH_GNET_SLC
+CONFIG_MACH_GOFLEXHOME
+CONFIG_MACH_GOFLEXNET
+CONFIG_MACH_GOLDENGATE
+CONFIG_MACH_GONI
+CONFIG_MACH_GORAMO_MLR
+CONFIG_MACH_GPSDISPLAY
+CONFIG_MACH_GREECO
+CONFIG_MACH_GSIA18S
+CONFIG_MACH_GSL_DIAMOND
+CONFIG_MACH_GSNCOMM
+CONFIG_MACH_GTA04
+CONFIG_MACH_GTIB
+CONFIG_MACH_GTL_IT5100
+CONFIG_MACH_GTWX5715
+CONFIG_MACH_GT_I5700
+CONFIG_MACH_GUPPY
+CONFIG_MACH_GURNARD
+CONFIG_MACH_GURUPLUG
+CONFIG_MACH_GW2361
+CONFIG_MACH_H1600
+CONFIG_MACH_H4700
+CONFIG_MACH_HABA_KNX_EXPLORER
+CONFIG_MACH_HALIBUT
+CONFIG_MACH_HAMMERHEAD
+CONFIG_MACH_HARMONY
+CONFIG_MACH_HARVEST_DESOTO
+CONFIG_MACH_HAWKS
+CONFIG_MACH_HDGU
+CONFIG_MACH_HDMINI
+CONFIG_MACH_HDNVP
+CONFIG_MACH_HELIOS_V1
+CONFIG_MACH_HELIOS_V2
+CONFIG_MACH_HERALD
+CONFIG_MACH_HERRING
+CONFIG_MACH_HIMALAYA
+CONFIG_MACH_HJSDU
+CONFIG_MACH_HKDKC100
+CONFIG_MACH_HMT
+CONFIG_MACH_HOLIDAY
+CONFIG_MACH_HREFV60
+CONFIG_MACH_HSGX6D
+CONFIG_MACH_HTCMEGA
+CONFIG_MACH_HTCTORNADO
+CONFIG_MACH_HTC_HD_MINI
+CONFIG_MACH_HTC_SPV_M700
+CONFIG_MACH_HUASHAN
+CONFIG_MACH_HUSKY
+CONFIG_MACH_HWGW6410
+CONFIG_MACH_IAM28
+CONFIG_MACH_ICON
+CONFIG_MACH_ICONG
+CONFIG_MACH_ICONNECT
+CONFIG_MACH_ICONTROL
+CONFIG_MACH_ICON_G
+CONFIG_MACH_ICS_IF_VOIP
+CONFIG_MACH_IDEA6410
+CONFIG_MACH_IGEP0020
+CONFIG_MACH_IGEP0030
+CONFIG_MACH_IGEP0032
+CONFIG_MACH_IJ3K_2440
+CONFIG_MACH_IMATE8502
+CONFIG_MACH_IMX27IPCAM
+CONFIG_MACH_IMX27LITE
+CONFIG_MACH_IMX27_VISSTRIM_M10
+CONFIG_MACH_INCOME
+CONFIG_MACH_INETSPACE_V2
+CONFIG_MACH_INHAND_APEIRON
+CONFIG_MACH_INHAND_FURY
+CONFIG_MACH_INHAND_SIREN
+CONFIG_MACH_INTELMOTE2
+CONFIG_MACH_IOMEGA_IX2_200
+CONFIG_MACH_IQ80332
+CONFIG_MACH_IQ81340MC
+CONFIG_MACH_IQ81340SC
+CONFIG_MACH_ISC3
+CONFIG_MACH_IXDP2351
+CONFIG_MACH_IXDP28X5
+CONFIG_MACH_IXDP465
+CONFIG_MACH_IXDPG425
+CONFIG_MACH_JANUS
+CONFIG_MACH_JIGEN
+CONFIG_MACH_JIVE
+CONFIG_MACH_JOCPU550
+CONFIG_MACH_KAEN
+CONFIG_MACH_KAFA
+CONFIG_MACH_KB9200
+CONFIG_MACH_KEV7A400
+CONFIG_MACH_KINGDOM
+CONFIG_MACH_KIXRP435
+CONFIG_MACH_KMM2M01
+CONFIG_MACH_KMP_AM17_01
+CONFIG_MACH_KM_KIRKWOOD
+CONFIG_MACH_KOI
+CONFIG_MACH_KRONOS
+CONFIG_MACH_KT_SBC_SAM9_1
+CONFIG_MACH_KUROBOX_PRO
+CONFIG_MACH_KX33XX
+CONFIG_MACH_KZM9D
+CONFIG_MACH_KZM9G
+CONFIG_MACH_KZM_ARM11_01
+CONFIG_MACH_LANREADYFN511
+CONFIG_MACH_LAUSANNE
+CONFIG_MACH_LB88RC8480
+CONFIG_MACH_LEAD
+CONFIG_MACH_LEGACY
+CONFIG_MACH_LEMON
+CONFIG_MACH_LIBRA
+CONFIG_MACH_LIGHTNING
+CONFIG_MACH_LILLY1131
+CONFIG_MACH_LINKSTATION_CHLV2
+CONFIG_MACH_LINKSTATION_LSCHL
+CONFIG_MACH_LINKSTATION_LS_HGL
+CONFIG_MACH_LINKSTATION_MINI
+CONFIG_MACH_LINKSTATION_PRO
+CONFIG_MACH_LITTLETON
+CONFIG_MACH_LOFT
+CONFIG_MACH_LOGICPD_PXA270
+CONFIG_MACH_LPC24XX
+CONFIG_MACH_LPD7A400
+CONFIG_MACH_LPD7A404
+CONFIG_MACH_LQ2
+CONFIG_MACH_LS9G20
+CONFIG_MACH_LSWXL
+CONFIG_MACH_M502
+CONFIG_MACH_MACH_SDH001
+CONFIG_MACH_MACKEREL
+CONFIG_MACH_MAGICIAN
+CONFIG_MACH_MAGX_ZN5
+CONFIG_MACH_MAHIMAHI
+CONFIG_MACH_MAINSTONE
+CONFIG_MACH_MANUAE
+CONFIG_MACH_MAPLE1
+CONFIG_MACH_MARVEL
+CONFIG_MACH_MARVELC
+CONFIG_MACH_MARVELCT
+CONFIG_MACH_MARVELL_JASPER
+CONFIG_MACH_MATRIX505
+CONFIG_MACH_MATRIX518
+CONFIG_MACH_MAXIMASP
+CONFIG_MACH_MB3
+CONFIG_MACH_MECHA
+CONFIG_MACH_MENO_QNG
+CONFIG_MACH_MESON
+CONFIG_MACH_MESON_6236M
+CONFIG_MACH_MESON_8626M
+CONFIG_MACH_MESSINA
+CONFIG_MACH_MIC256
+CONFIG_MACH_MICCPT
+CONFIG_MACH_MICRO9
+CONFIG_MACH_MICRO9L
+CONFIG_MACH_MICRO9M
+CONFIG_MACH_MICRO9S
+CONFIG_MACH_MIF10P
+CONFIG_MACH_MIMAS
+CONFIG_MACH_MINI210
+CONFIG_MACH_MINI2440
+CONFIG_MACH_MINI6410
+CONFIG_MACH_MINI8168
+CONFIG_MACH_MIOA502
+CONFIG_MACH_MIOA701
+CONFIG_MACH_MIONE
+CONFIG_MACH_MIOS_V1
+CONFIG_MACH_MITYOMAPL138
+CONFIG_MACH_MMM
+CONFIG_MACH_MONCH
+CONFIG_MACH_MONE
+CONFIG_MACH_MOON
+CONFIG_MACH_MORA
+CONFIG_MACH_MR301A
+CONFIG_MACH_MSM7X25_FFA
+CONFIG_MACH_MSM7X25_SURF
+CONFIG_MACH_MSM7X27A_FFA
+CONFIG_MACH_MSM7X27A_RUMI3
+CONFIG_MACH_MSM7X27A_SURF
+CONFIG_MACH_MSM7X27_FFA
+CONFIG_MACH_MSM7X27_SURF
+CONFIG_MACH_MSM7X30_FFA
+CONFIG_MACH_MSM7X30_FLUID
+CONFIG_MACH_MSM7X30_SURF
+CONFIG_MACH_MSM8960_APQ
+CONFIG_MACH_MSM8960_CDP
+CONFIG_MACH_MSM8960_FLUID
+CONFIG_MACH_MSM8960_MDP
+CONFIG_MACH_MSM8960_RUMI3
+CONFIG_MACH_MSM8960_SIM
+CONFIG_MACH_MSM8X55_SVLTE_FFA
+CONFIG_MACH_MSM8X55_SVLTE_SURF
+CONFIG_MACH_MSM8X60_FFA
+CONFIG_MACH_MSM8X60_FLUID
+CONFIG_MACH_MSM8X60_QRDC
+CONFIG_MACH_MSM8X60_QT
+CONFIG_MACH_MSM8X60_RUMI3
+CONFIG_MACH_MSM8X60_SIM
+CONFIG_MACH_MSM8X60_SURF
+CONFIG_MACH_MSS2
+CONFIG_MACH_MULTHSU
+CONFIG_MACH_MV2120
+CONFIG_MACH_MV88F6281GTW_GE
+CONFIG_MACH_MVBLX
+CONFIG_MACH_MX21ADS
+CONFIG_MACH_MX23EVK
+CONFIG_MACH_MX257SOL
+CONFIG_MACH_MX257SX
+CONFIG_MACH_MX25_3DS
+CONFIG_MACH_MX25_E2S_UC
+CONFIG_MACH_MX27ADS
+CONFIG_MACH_MX27SU2
+CONFIG_MACH_MX27_3DS
+CONFIG_MACH_MX27_WMULTRA
+CONFIG_MACH_MX28EVK
+CONFIG_MACH_MX31ADS
+CONFIG_MACH_MX31LITE
+CONFIG_MACH_MX31MOBOARD
+CONFIG_MACH_MX31_3DS
+CONFIG_MACH_MX35_3DS
+CONFIG_MACH_MX50_ARM2
+CONFIG_MACH_MX50_RDP
+CONFIG_MACH_MX51EREBUS
+CONFIG_MACH_MX51_3DS
+CONFIG_MACH_MX51_ASTER7
+CONFIG_MACH_MX51_BABBAGE
+CONFIG_MACH_MX51_BRAVO
+CONFIG_MACH_MX51_EFIKAMX
+CONFIG_MACH_MX51_EFIKASB
+CONFIG_MACH_MX51_GGC
+CONFIG_MACH_MX51_MORAY
+CONFIG_MACH_MX51_TULIP
+CONFIG_MACH_MX53_ARD
+CONFIG_MACH_MX53_EVK
+CONFIG_MACH_MX53_LOCO
+CONFIG_MACH_MX53_SMD
+CONFIG_MACH_MX61_ARD
+CONFIG_MACH_MXC25_TOPAZ
+CONFIG_MACH_MXLADS
+CONFIG_MACH_MXT_TD60
+CONFIG_MACH_MXT_TD61
+CONFIG_MACH_N2100
+CONFIG_MACH_N30
+CONFIG_MACH_N35
+CONFIG_MACH_NAJAY_A9263
+CONFIG_MACH_NANOS
+CONFIG_MACH_NANOZOOM
+CONFIG_MACH_NAS100D
+CONFIG_MACH_NAS4220B
+CONFIG_MACH_NAS6210
+CONFIG_MACH_NAVEFIHID
+CONFIG_MACH_NAXY1200
+CONFIG_MACH_NAXY400
+CONFIG_MACH_NB31
+CONFIG_MACH_NCP
+CONFIG_MACH_NDA_EVM
+CONFIG_MACH_NEC_MP900
+CONFIG_MACH_NEO1973_GTA02
+CONFIG_MACH_NEOCORE926
+CONFIG_MACH_NERY_1000
+CONFIG_MACH_NET2BIG
+CONFIG_MACH_NET2BIG_NAND_V2
+CONFIG_MACH_NET2BIG_V2
+CONFIG_MACH_NET5BIG_NAND_V2
+CONFIG_MACH_NET5BIG_V2
+CONFIG_MACH_NETSPACE_LITE_V2
+CONFIG_MACH_NETSPACE_MAX_V2
+CONFIG_MACH_NETSPACE_V2
+CONFIG_MACH_NETVIZ
+CONFIG_MACH_NETWALKER
+CONFIG_MACH_NEUROS_OSD2
+CONFIG_MACH_NEXCODER_2440
+CONFIG_MACH_NITROGEN_IMX51
+CONFIG_MACH_NITROGEN_IMX53
+CONFIG_MACH_NITROGEN_VM_IMX51
+CONFIG_MACH_NMH
+CONFIG_MACH_NOKIA770
+CONFIG_MACH_NOKIA_N800
+CONFIG_MACH_NOKIA_N810
+CONFIG_MACH_NOKIA_N810_WIMAX
+CONFIG_MACH_NOKIA_RM680
+CONFIG_MACH_NOKIA_RX51
+CONFIG_MACH_NOMADIK
+CONFIG_MACH_NOTLE
+CONFIG_MACH_NS2416
+CONFIG_MACH_NS2816TB
+CONFIG_MACH_NS2816_NTNB
+CONFIG_MACH_NS2816_NTPAD
+CONFIG_MACH_NSB3AST
+CONFIG_MACH_NSK330
+CONFIG_MACH_NSLU2
+CONFIG_MACH_NSSLSBOARD
+CONFIG_MACH_NS_K330
+CONFIG_MACH_NUC700EVB
+CONFIG_MACH_NUC710EVB
+CONFIG_MACH_NUC740EVB
+CONFIG_MACH_NUC745EVB
+CONFIG_MACH_NUC932EVB
+CONFIG_MACH_NUC950TS
+CONFIG_MACH_NURI
+CONFIG_MACH_NV1000
+CONFIG_MACH_NXDB500
+CONFIG_MACH_NXDKN
+CONFIG_MACH_NXEB500HMI
+CONFIG_MACH_OCE_NIGMA
+CONFIG_MACH_OMAP2EVM
+CONFIG_MACH_OMAP3505NOVA8
+CONFIG_MACH_OMAP3517EVM
+CONFIG_MACH_OMAP3530_LV_SOM
+CONFIG_MACH_OMAP3621_EDP1
+CONFIG_MACH_OMAP3EVM
+CONFIG_MACH_OMAP3SMARTDISPLAY
+CONFIG_MACH_OMAP3_BAIA
+CONFIG_MACH_OMAP3_BC10
+CONFIG_MACH_OMAP3_BEAGLE
+CONFIG_MACH_OMAP3_BRAILLO
+CONFIG_MACH_OMAP3_IBIZA
+CONFIG_MACH_OMAP3_PANDORA
+CONFIG_MACH_OMAP3_RFS200
+CONFIG_MACH_OMAP3_TDM3730
+CONFIG_MACH_OMAP3_TORPEDO
+CONFIG_MACH_OMAP3_WALDO1
+CONFIG_MACH_OMAP4_PANDA
+CONFIG_MACH_OMAP5_SEVM
+CONFIG_MACH_OMAPL138_CASE_A3
+CONFIG_MACH_OMAPL138_EUROPALC
+CONFIG_MACH_OMAPL138_HAWKBOARD
+CONFIG_MACH_OMAPL138_LCDK
+CONFIG_MACH_OMAP_2430SDP
+CONFIG_MACH_OMAP_3430SDP
+CONFIG_MACH_OMAP_3630SDP
+CONFIG_MACH_OMAP_4430SDP
+CONFIG_MACH_OMAP_APOLLON
+CONFIG_MACH_OMAP_BENDER
+CONFIG_MACH_OMAP_FSAMPLE
+CONFIG_MACH_OMAP_GENERIC
+CONFIG_MACH_OMAP_H2
+CONFIG_MACH_OMAP_H3
+CONFIG_MACH_OMAP_H4
+CONFIG_MACH_OMAP_INNOVATOR
+CONFIG_MACH_OMAP_LDP
+CONFIG_MACH_OMAP_MCOP
+CONFIG_MACH_OMAP_OSK
+CONFIG_MACH_OMAP_PALMTE
+CONFIG_MACH_OMAP_PALMTT
+CONFIG_MACH_OMAP_PALMZ71
+CONFIG_MACH_OMAP_PERSEUS2
+CONFIG_MACH_OMAP_ZOOM2
+CONFIG_MACH_OMAP_ZOOM3
+CONFIG_MACH_OMN_AT91SAM9G20
+CONFIG_MACH_ONEARM
+CONFIG_MACH_OPENRD_BASE
+CONFIG_MACH_OPENRD_CLIENT
+CONFIG_MACH_OPENRD_ULTIMATE
+CONFIG_MACH_ORATISAES
+CONFIG_MACH_ORATISLINK
+CONFIG_MACH_ORIGEN
+CONFIG_MACH_OSIRIS
+CONFIG_MACH_OSLO_AMUNDSEN
+CONFIG_MACH_OTOM
+CONFIG_MACH_OVERO
+CONFIG_MACH_OVERO_CTU_INERTIAL
+CONFIG_MACH_P87_SMARTSIM
+CONFIG_MACH_PALMLD
+CONFIG_MACH_PALMT5
+CONFIG_MACH_PALMTC
+CONFIG_MACH_PALMTE2
+CONFIG_MACH_PALMTX
+CONFIG_MACH_PALMZ72
+CONFIG_MACH_PAZ00
+CONFIG_MACH_PC7302
+CONFIG_MACH_PC7308
+CONFIG_MACH_PC9260_V2
+CONFIG_MACH_PCA100
+CONFIG_MACH_PCA102
+CONFIG_MACH_PCATS_OVERLAY
+CONFIG_MACH_PCM027
+CONFIG_MACH_PCM037
+CONFIG_MACH_PCM038
+CONFIG_MACH_PCM043
+CONFIG_MACH_PCM048
+CONFIG_MACH_PCM049
+CONFIG_MACH_PCONTROL_G20
+CONFIG_MACH_PEC_HC2
+CONFIG_MACH_PEC_TC
+CONFIG_MACH_PEMP_OMAP3_APOLLO
+CONFIG_MACH_PGS_SITARA
+CONFIG_MACH_PHILHWANI
+CONFIG_MACH_PHY3250
+CONFIG_MACH_PICASSO
+CONFIG_MACH_PICO
+CONFIG_MACH_PICOCOM3
+CONFIG_MACH_PICOCOM4
+CONFIG_MACH_PICOTUX2XX
+CONFIG_MACH_PIVICC
+CONFIG_MACH_PNX4008
+CONFIG_MACH_POLYSAT1
+CONFIG_MACH_POODLE
+CONFIG_MACH_PORTUXG20
+CONFIG_MACH_POV15HD
+CONFIG_MACH_PREMIERWAVE_EN
+CONFIG_MACH_PRIMA2_EVB
+CONFIG_MACH_PTX7510
+CONFIG_MACH_PTX7545
+CONFIG_MACH_PUNICA
+CONFIG_MACH_PUPITRE
+CONFIG_MACH_PVM2030
+CONFIG_MACH_PWB3090
+CONFIG_MACH_PXWNAS_500_1000
+CONFIG_MACH_PYRAMID
+CONFIG_MACH_QBC9263
+CONFIG_MACH_QIL_A9260
+CONFIG_MACH_QONG
+CONFIG_MACH_QSD8X50A_ST1_5
+CONFIG_MACH_QSD8X50_SURF
+CONFIG_MACH_QSD8X72_FFA
+CONFIG_MACH_QSD8X72_SURF
+CONFIG_MACH_QT2410
+CONFIG_MACH_QUAD_SALSA
+CONFIG_MACH_QUICKSTEP
+CONFIG_MACH_R1801E
+CONFIG_MACH_RASCAL
+CONFIG_MACH_RAUMFELD_CONNECTOR
+CONFIG_MACH_RAUMFELD_RC
+CONFIG_MACH_RAUMFELD_SPEAKER
+CONFIG_MACH_RD78X00_MASA
+CONFIG_MACH_RD88F5181L_FXO
+CONFIG_MACH_RD88F5181L_GE
+CONFIG_MACH_RD88F5182
+CONFIG_MACH_RD88F6183AP_GE
+CONFIG_MACH_RD88F6192_NAS
+CONFIG_MACH_RD88F6281
+CONFIG_MACH_RDSTOR
+CONFIG_MACH_RE2REV20
+CONFIG_MACH_RE2REV21
+CONFIG_MACH_REAL6410
+CONFIG_MACH_REALVIEW_EB
+CONFIG_MACH_REALVIEW_PB1176
+CONFIG_MACH_REALVIEW_PB11MP
+CONFIG_MACH_REALVIEW_PBA8
+CONFIG_MACH_REALVIEW_PBX
+CONFIG_MACH_REMUS
+CONFIG_MACH_REXMAS
+CONFIG_MACH_RFL109145_SSRV
+CONFIG_MACH_RHINO
+CONFIG_MACH_RIB
+CONFIG_MACH_RIDER
+CONFIG_MACH_RIOT_BEI2
+CONFIG_MACH_RIOT_X37
+CONFIG_MACH_ROADRUNNER
+CONFIG_MACH_ROCKHOPPER
+CONFIG_MACH_ROVERPCS8
+CONFIG_MACH_ROVERX7
+CONFIG_MACH_ROVER_G8
+CONFIG_MACH_RPC353
+CONFIG_MACH_RUBY
+CONFIG_MACH_RUBYS
+CONFIG_MACH_RUMP
+CONFIG_MACH_RUT100
+CONFIG_MACH_RV082
+CONFIG_MACH_RX1950
+CONFIG_MACH_RX3715
+CONFIG_MACH_S3C2413
+CONFIG_MACH_S5500
+CONFIG_MACH_S5PC110_CRESPO
+CONFIG_MACH_SAAR
+CONFIG_MACH_SAARB
+CONFIG_MACH_SAARB_MG1
+CONFIG_MACH_SAGA
+CONFIG_MACH_SALUDA
+CONFIG_MACH_SAM9REPEATER
+CONFIG_MACH_SAM9_L9260
+CONFIG_MACH_SANTIAGO
+CONFIG_MACH_SAPPHIRE
+CONFIG_MACH_SBC3530
+CONFIG_MACH_SBC6000X
+CONFIG_MACH_SBCA11
+CONFIG_MACH_SC575IPC
+CONFIG_MACH_SC575PLC
+CONFIG_MACH_SCB9328
+CONFIG_MACH_SCIPHONE_G2
+CONFIG_MACH_SDI_ESS_9263
+CONFIG_MACH_SDVR
+CONFIG_MACH_SEABOARD
+CONFIG_MACH_SERRANO
+CONFIG_MACH_SFFSDR
+CONFIG_MACH_SGH_I740
+CONFIG_MACH_SHARESPACE
+CONFIG_MACH_SHEEVAPLUG
+CONFIG_MACH_SHENZHOU
+CONFIG_MACH_SHEPHERD
+CONFIG_MACH_SHOOTER
+CONFIG_MACH_SHOOTER_CT
+CONFIG_MACH_SHOOTER_U
+CONFIG_MACH_SHORTLOIN
+CONFIG_MACH_SIEMENS_L0
+CONFIG_MACH_SIMPLENET
+CONFIG_MACH_SIMTEC_KIRKMOD
+CONFIG_MACH_SIM_ONE
+CONFIG_MACH_SKY25
+CONFIG_MACH_SKY6410
+CONFIG_MACH_SM1K
+CONFIG_MACH_SMARTQ5
+CONFIG_MACH_SMARTQ7
+CONFIG_MACH_SMARTQV3
+CONFIG_MACH_SMARTQV5
+CONFIG_MACH_SMARTQV7
+CONFIG_MACH_SMDK2412
+CONFIG_MACH_SMDK2413
+CONFIG_MACH_SMDK2416
+CONFIG_MACH_SMDK2443
+CONFIG_MACH_SMDK6410
+CONFIG_MACH_SMDK6440
+CONFIG_MACH_SMDK6442
+CONFIG_MACH_SMDK6450
+CONFIG_MACH_SMDKC100
+CONFIG_MACH_SMDKC110
+CONFIG_MACH_SMDKC210
+CONFIG_MACH_SMDKV210
+CONFIG_MACH_SMDKV310
+CONFIG_MACH_SNAPPER_9260
+CONFIG_MACH_SNAPPER_CL15
+CONFIG_MACH_SOFTWINNER
+CONFIG_MACH_SOLI_01
+CONFIG_MACH_SPADE
+CONFIG_MACH_SPADE_LTE
+CONFIG_MACH_SPDM
+CONFIG_MACH_SPEAR1310
+CONFIG_MACH_SPEAR1340
+CONFIG_MACH_SPEAR300
+CONFIG_MACH_SPEAR310
+CONFIG_MACH_SPEAR320
+CONFIG_MACH_SPEAR600
+CONFIG_MACH_SPEAR900
+CONFIG_MACH_SPECIFIC
+CONFIG_MACH_SPICA
+CONFIG_MACH_SPITZ
+CONFIG_MACH_SPLENDOR
+CONFIG_MACH_SPX_SAKURA
+CONFIG_MACH_SPYPLUG
+CONFIG_MACH_SSC
+CONFIG_MACH_STAMP9G20
+CONFIG_MACH_STAMP9G45
+CONFIG_MACH_STARGATE2
+CONFIG_MACH_STEELYARD
+CONFIG_MACH_STELLA
+CONFIG_MACH_STMP378X
+CONFIG_MACH_STMP37XX
+CONFIG_MACH_STRASBOURG
+CONFIG_MACH_STRASBOURG_A2
+CONFIG_MACH_STRETCHS7000
+CONFIG_MACH_SUNFIRE
+CONFIG_MACH_SUNFLOWER
+CONFIG_MACH_SVCID
+CONFIG_MACH_SVP5500
+CONFIG_MACH_SVP8500V1
+CONFIG_MACH_SVP8500V2
+CONFIG_MACH_SWARCOEXTMODEM
+CONFIG_MACH_SWEDA_TMS2
+CONFIG_MACH_SX1
+CONFIG_MACH_SYNERGY
+CONFIG_MACH_SYNOLOGY_6282
+CONFIG_MACH_T20
+CONFIG_MACH_T5325
+CONFIG_MACH_T5388P
+CONFIG_MACH_T55
+CONFIG_MACH_TAG
+CONFIG_MACH_TAGW
+CONFIG_MACH_TANNA
+CONFIG_MACH_TAVOREVB
+CONFIG_MACH_TAVOREVB3
+CONFIG_MACH_TCC8000_SDK
+CONFIG_MACH_TCT_HAMMER
+CONFIG_MACH_TD3_REV1
+CONFIG_MACH_TEENOTE
+CONFIG_MACH_TEGRA_DAYTONA
+CONFIG_MACH_TEGRA_E1165
+CONFIG_MACH_TEGRA_SWORDFISH
+CONFIG_MACH_TEGRA_VOGUE
+CONFIG_MACH_TEM3X30
+CONFIG_MACH_TENDERLOIN
+CONFIG_MACH_TERASTATION_PRO2
+CONFIG_MACH_TERASTATION_WXL
+CONFIG_MACH_TERA_PRO2_RACK
+CONFIG_MACH_TETON_BGA
+CONFIG_MACH_THALES_ADC
+CONFIG_MACH_THALES_CBC
+CONFIG_MACH_THEBE
+CONFIG_MACH_TI8148EVM
+CONFIG_MACH_TI8168EVM
+CONFIG_MACH_TIMU
+CONFIG_MACH_TIN307
+CONFIG_MACH_TIN510
+CONFIG_MACH_TINY_GURNARD
+CONFIG_MACH_TITAN
+CONFIG_MACH_TJINC1000
+CONFIG_MACH_TM_EFDC
+CONFIG_MACH_TN200
+CONFIG_MACH_TNETV107X
+CONFIG_MACH_TNY_T3530
+CONFIG_MACH_TONGA2_TFTTIMER
+CONFIG_MACH_TOP9000
+CONFIG_MACH_TOP9000_BSL
+CONFIG_MACH_TOP9000_EVAL
+CONFIG_MACH_TOP9000_SU
+CONFIG_MACH_TOP9000_TCU
+CONFIG_MACH_TORBRECK
+CONFIG_MACH_TORNADO3240
+CONFIG_MACH_TOSA
+CONFIG_MACH_TOUCHBOOK
+CONFIG_MACH_TPT_2_0
+CONFIG_MACH_TQ6410
+CONFIG_MACH_TQMA35
+CONFIG_MACH_TQMA9263
+CONFIG_MACH_TRANSCEDE
+CONFIG_MACH_TREO680
+CONFIG_MACH_TRICORDER
+CONFIG_MACH_TRIDENT
+CONFIG_MACH_TRIMSLICE
+CONFIG_MACH_TRIPEL
+CONFIG_MACH_TRITIP
+CONFIG_MACH_TRIZEPS4
+CONFIG_MACH_TRIZEPS4WL
+CONFIG_MACH_TROUT
+CONFIG_MACH_TS209
+CONFIG_MACH_TS219
+CONFIG_MACH_TS3
+CONFIG_MACH_TS409
+CONFIG_MACH_TS41X
+CONFIG_MACH_TS42XX
+CONFIG_MACH_TS47XX
+CONFIG_MACH_TS4800
+CONFIG_MACH_TS48XX
+CONFIG_MACH_TS72XX
+CONFIG_MACH_TS75XX
+CONFIG_MACH_TS78XX
+CONFIG_MACH_TSOPLOADER
+CONFIG_MACH_TSUNAGI
+CONFIG_MACH_TTC_DKB
+CONFIG_MACH_TUBE
+CONFIG_MACH_TULIP
+CONFIG_MACH_TUNA
+CONFIG_MACH_TUXRAIL
+CONFIG_MACH_TX28
+CONFIG_MACH_TX53
+CONFIG_MACH_TYPE
+CONFIG_MACH_TYPE_COMPAT_REV
+CONFIG_MACH_U300
+CONFIG_MACH_U5500
+CONFIG_MACH_UBISYS_P9D_EVP
+CONFIG_MACH_UEMD
+CONFIG_MACH_UNINO1
+CONFIG_MACH_UNISDEV
+CONFIG_MACH_UNISENSE_MMM
+CONFIG_MACH_UNIT2S
+CONFIG_MACH_UNIVERSAL_C210
+CONFIG_MACH_USB_A9260
+CONFIG_MACH_USB_A9263
+CONFIG_MACH_USDLOADER
+CONFIG_MACH_UTM300
+CONFIG_MACH_VALDEZ
+CONFIG_MACH_VANGOGH
+CONFIG_MACH_VC0718
+CONFIG_MACH_VENTANA
+CONFIG_MACH_VERDI
+CONFIG_MACH_VERDI_LTE
+CONFIG_MACH_VERIDIS_A300
+CONFIG_MACH_VERSATILE_AB
+CONFIG_MACH_VEXPRESS
+CONFIG_MACH_VIGOR
+CONFIG_MACH_VIPRINET
+CONFIG_MACH_VIT_IBOX
+CONFIG_MACH_VIVO
+CONFIG_MACH_VIVOW_CT
+CONFIG_MACH_VMX25
+CONFIG_MACH_VMX51
+CONFIG_MACH_VMX53
+CONFIG_MACH_VOICEBLUE
+CONFIG_MACH_VPAC270
+CONFIG_MACH_VPR200
+CONFIG_MACH_VR1000
+CONFIG_MACH_VSTMS
+CONFIG_MACH_VVBOX_SDLITE2
+CONFIG_MACH_VVBOX_SDORIG2
+CONFIG_MACH_VVBOX_SDPRO4
+CONFIG_MACH_W21
+CONFIG_MACH_W90N960EVB
+CONFIG_MACH_W90P910EVB
+CONFIG_MACH_W90P950EVB
+CONFIG_MACH_WARIO
+CONFIG_MACH_WASABI
+CONFIG_MACH_WATSON_EFM_PLUGIN
+CONFIG_MACH_WB40N
+CONFIG_MACH_WBD111
+CONFIG_MACH_WBD222
+CONFIG_MACH_WG302V2
+CONFIG_MACH_WHISTLER
+CONFIG_MACH_WLAN_COMPUTER
+CONFIG_MACH_WLF_CRAGG_6410
+CONFIG_MACH_WM8505_7IN_NETBOOK
+CONFIG_MACH_WM8650REFBOARD
+CONFIG_MACH_WN802T
+CONFIG_MACH_WNR854T
+CONFIG_MACH_WRT350N_V2
+CONFIG_MACH_WTPLUG
+CONFIG_MACH_XARINA
+CONFIG_MACH_XCEP
+CONFIG_MACH_XILINX
+CONFIG_MACH_XILINX_EP107
+CONFIG_MACH_XSBASE255
+CONFIG_MACH_YANOMAMI
+CONFIG_MACH_YL9200
+CONFIG_MACH_Z3_814X_MOD
+CONFIG_MACH_Z3_816X_MOD
+CONFIG_MACH_ZIPIT2
+CONFIG_MACH_ZMX25
+CONFIG_MACH_ZYLONITE
+CONFIG_MACH_ZYLONITE2
+CONFIG_MACPWR
+CONFIG_MACRESET_TIMEOUT
+CONFIG_MAC_ADDR_IN_EEPROM
+CONFIG_MAC_ADDR_IN_SPIFLASH
+CONFIG_MAC_OFFSET
+CONFIG_MAC_PARTITION
+CONFIG_MAKALU
+CONFIG_MALLOC_F_ADDR
+CONFIG_MALTA
+CONFIG_MARCO_MEMSET
+CONFIG_MARUBUN_PCCARD
+CONFIG_MARVELL
+CONFIG_MARVELL_GPIO
+CONFIG_MARVELL_MFP
+CONFIG_MASK_AER_AO
+CONFIG_MAX_DSP_CPUS
+CONFIG_MAX_FPGA_DEVICES
+CONFIG_MAX_MEM_MAPPED
+CONFIG_MAX_PKT
+CONFIG_MAX_RAM_BANK_SIZE
+CONFIG_MCAST_TFTP
+CONFIG_MCF5249
+CONFIG_MCF5253
+CONFIG_MCFFEC
+CONFIG_MCFPIT
+CONFIG_MCFRTC
+CONFIG_MCFTMR
+CONFIG_MCFUART
+CONFIG_MCLK_DIS
+CONFIG_MD5
+CONFIG_MD5SUM_VERIFY
+CONFIG_MDIO_TIMEOUT
+CONFIG_MECP5123
+CONFIG_MEMSIZE
+CONFIG_MEMSIZE_IN_BYTES
+CONFIG_MEMSIZE_MASK
+CONFIG_MEM_ADD_WDTH
+CONFIG_MEM_HOLE_16M
+CONFIG_MEM_INIT_VALUE
+CONFIG_MEM_REMAP
+CONFIG_MEM_SIZE
+CONFIG_MENUKEY
+CONFIG_MENUPROMPT
+CONFIG_MENU_SHOW
+CONFIG_MFG_ENV_SETTINGS
+CONFIG_MGCOGE
+CONFIG_MGCOGE3NE
+CONFIG_MIGO_R
+CONFIG_MII
+CONFIG_MIIM_ADDRESS
+CONFIG_MII_DEFAULT_TSEC
+CONFIG_MII_INIT
+CONFIG_MII_SUPPRESS_PREAMBLE
+CONFIG_MINIFAP
+CONFIG_MIPS_HUGE_TLB_SUPPORT
+CONFIG_MIPS_MT_FPAFF
+CONFIG_MIRQ_EN
+CONFIG_MISC_COMMON
+CONFIG_MISC_INIT_F
+CONFIG_MISC_INIT_R
+CONFIG_MIU_1BIT_INTERLEAVED
+CONFIG_MIU_2BIT_21_7_INTERLEAVED
+CONFIG_MIU_2BIT_INTERLEAVED
+CONFIG_MIU_LINEAR
+CONFIG_MK_edb9301
+CONFIG_MK_edb9315a
+CONFIG_MMCBOOTCOMMAND
+CONFIG_MMCROOT
+CONFIG_MMC_DEFAULT_DEV
+CONFIG_MMC_RPMB_TRACE
+CONFIG_MMC_SPI
+CONFIG_MMC_SPI_BUS
+CONFIG_MMC_SPI_CRC_ON
+CONFIG_MMC_SPI_CS
+CONFIG_MMC_SPI_CS_EPGIO
+CONFIG_MMC_SPI_MODE
+CONFIG_MMC_SPI_NPOWER_EGPIO
+CONFIG_MMC_SPI_POWER_EGPIO
+CONFIG_MMC_SPI_SPEED
+CONFIG_MMC_SUNXI
+CONFIG_MMC_SUNXI_SLOT
+CONFIG_MMC_TRACE
+CONFIG_MMU
+CONFIG_MODVERSIONS
+CONFIG_MONITOR_IS_IN_RAM
+CONFIG_MOTIONPRO
+CONFIG_MP
+CONFIG_MPC5121ADS
+CONFIG_MPC5121ADS_REV2
+CONFIG_MPC512x_FEC
+CONFIG_MPC5200
+CONFIG_MPC5200_DDR
+CONFIG_MPC555
+CONFIG_MPC5xxx_FEC
+CONFIG_MPC5xxx_FEC_MII10
+CONFIG_MPC5xxx_FEC_MII100
+CONFIG_MPC823
+CONFIG_MPC8247
+CONFIG_MPC8255
+CONFIG_MPC8272_FAMILY
+CONFIG_MPC8308
+CONFIG_MPC8308RDB
+CONFIG_MPC8308_P1M
+CONFIG_MPC8309
+CONFIG_MPC830x
+CONFIG_MPC8313
+CONFIG_MPC8313ERDB
+CONFIG_MPC8315
+CONFIG_MPC8315ERDB
+CONFIG_MPC831x
+CONFIG_MPC832XEMDS
+CONFIG_MPC832x
+CONFIG_MPC8349
+CONFIG_MPC8349EMDS
+CONFIG_MPC8349ITX
+CONFIG_MPC8349ITXGP
+CONFIG_MPC834x
+CONFIG_MPC8360
+CONFIG_MPC837XEMDS
+CONFIG_MPC837XERDB
+CONFIG_MPC837x
+CONFIG_MPC83XX_GPIO
+CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
+CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
+CONFIG_MPC83XX_GPIO_0_INIT_VALUE
+CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION
+CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN
+CONFIG_MPC83XX_GPIO_1_INIT_VALUE
+CONFIG_MPC83XX_PCI2
+CONFIG_MPC850
+CONFIG_MPC855
+CONFIG_MPC857
+CONFIG_MPC85XX_FEC
+CONFIG_MPC85XX_FEC_NAME
+CONFIG_MPC85XX_PCI2
+CONFIG_MPC860
+CONFIG_MPC860T
+CONFIG_MPC862
+CONFIG_MPC866
+CONFIG_MPC866_FAMILY
+CONFIG_MPC86x
+CONFIG_MPC885
+CONFIG_MPC885_FAMILY
+CONFIG_MPC8XXX_SPI
+CONFIG_MPC8XX_LCD
+CONFIG_MPC8xxx_DISABLE_BPTR
+CONFIG_MPLL_FREQ
+CONFIG_MPR2
+CONFIG_MPX5200
+CONFIG_MP_CLK_FREQ
+CONFIG_MS7720SE
+CONFIG_MS7722SE
+CONFIG_MS7750SE
+CONFIG_MSHC_FREQ
+CONFIG_MTDMAP
+CONFIG_MTDPARTS
+CONFIG_MTD_CONCAT
+CONFIG_MTD_DEBUG
+CONFIG_MTD_DEBUG_VERBOSE
+CONFIG_MTD_DEVICE
+CONFIG_MTD_ECC_SOFT
+CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
+CONFIG_MTD_NAND_ECC_SMC
+CONFIG_MTD_NAND_MUSEUM_IDS
+CONFIG_MTD_NAND_VERIFY_WRITE
+CONFIG_MTD_ONENAND_VERIFY_WRITE
+CONFIG_MTD_PARTITION
+CONFIG_MTD_PARTITIONS
+CONFIG_MTD_UBI_BEB_RESERVE
+CONFIG_MTD_UBI_BLOCK
+CONFIG_MTD_UBI_DEBUG
+CONFIG_MTD_UBI_DEBUG_MSG
+CONFIG_MTD_UBI_DEBUG_MSG_BLD
+CONFIG_MTD_UBI_DEBUG_MSG_EBA
+CONFIG_MTD_UBI_DEBUG_MSG_IO
+CONFIG_MTD_UBI_DEBUG_MSG_WL
+CONFIG_MTD_UBI_DEBUG_PARANOID
+CONFIG_MTD_UBI_GLUEBI
+CONFIG_MTD_UBI_MODULE
+CONFIG_MULTI_CS
+CONFIG_MUNICES
+CONFIG_MUSB_HOST
+CONFIG_MV88E61XX_CPU_PORT
+CONFIG_MV88E61XX_PHY_PORTS
+CONFIG_MV88E61XX_SWITCH
+CONFIG_MV88E6352_SWITCH
+CONFIG_MVEBU_MMC
+CONFIG_MVGBE
+CONFIG_MVGBE_PORTS
+CONFIG_MVMFP_V2
+CONFIG_MVNETA
+CONFIG_MVS
+CONFIG_MVSATA_IDE
+CONFIG_MVSATA_IDE_USE_PORT0
+CONFIG_MVSATA_IDE_USE_PORT1
+CONFIG_MV_ETH_RXQ
+CONFIG_MV_I2C_NUM
+CONFIG_MV_I2C_REG
+CONFIG_MX23
+CONFIG_MX25
+CONFIG_MX25_CLK32
+CONFIG_MX25_HCLK_FREQ
+CONFIG_MX27
+CONFIG_MX27_CLK32
+CONFIG_MX27_TIMER_HIGH_PRECISION
+CONFIG_MX28
+CONFIG_MX28_FEC_MAC_IN_OCOTP
+CONFIG_MX31
+CONFIG_MX31_CLK32
+CONFIG_MX31_HCLK_FREQ
+CONFIG_MX35
+CONFIG_MX35_CLK32
+CONFIG_MX35_HCLK_FREQ
+CONFIG_MX6DL_LPDDR2
+CONFIG_MX6DQ_LPDDR2
+CONFIG_MX6SX_SABRESD_REVA
+CONFIG_MX6UL_14X14_EVK_EMMC_REWORK
+CONFIG_MXC_EPDC
+CONFIG_MXC_GPIO
+CONFIG_MXC_GPT_HCLK
+CONFIG_MXC_MCI_REGS_BASE
+CONFIG_MXC_MMC
+CONFIG_MXC_NAND_HWECC
+CONFIG_MXC_NAND_IP_REGS_BASE
+CONFIG_MXC_NAND_REGS_BASE
+CONFIG_MXC_SPI
+CONFIG_MXC_UART_BASE
+CONFIG_MXC_USB_FLAGS
+CONFIG_MXC_USB_PORT
+CONFIG_MXC_USB_PORTSC
+CONFIG_MXS
+CONFIG_MXS_AUART
+CONFIG_MXS_AUART_BASE
+CONFIG_MXS_GPIO
+CONFIG_MXS_MMC
+CONFIG_MXS_OCOTP
+CONFIG_MXS_SPI
+CONFIG_MX_CYCLIC
+CONFIG_MY_OPTION
+CONFIG_NAND
+CONFIG_NANDFLASH_SIZE
+CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
+CONFIG_NAND_ACTL
+CONFIG_NAND_ATMEL
+CONFIG_NAND_CS_INIT
+CONFIG_NAND_DATA_REG
+CONFIG_NAND_DAVINCI
+CONFIG_NAND_DENALI_ECC_SIZE
+CONFIG_NAND_ECC_BCH
+CONFIG_NAND_ENV_DST
+CONFIG_NAND_FSL_ELBC
+CONFIG_NAND_FSL_IFC
+CONFIG_NAND_FSL_NFC
+CONFIG_NAND_FSMC
+CONFIG_NAND_KIRKWOOD
+CONFIG_NAND_KMETER1
+CONFIG_NAND_LPC32XX_MLC
+CONFIG_NAND_LPC32XX_SLC
+CONFIG_NAND_MODE_REG
+CONFIG_NAND_MPC5121_NFC
+CONFIG_NAND_MXC
+CONFIG_NAND_MXC_V1_1
+CONFIG_NAND_NDFC
+CONFIG_NAND_OMAP_ECCSCHEME
+CONFIG_NAND_OMAP_ELM
+CONFIG_NAND_OMAP_GPMC
+CONFIG_NAND_OMAP_GPMC_PREFETCH
+CONFIG_NAND_OMAP_GPMC_WSCFG
+CONFIG_NAND_PLAT
+CONFIG_NAND_SECBOOT
+CONFIG_NAND_SPL
+CONFIG_NAND_U_BOOT
+CONFIG_NATSEMI
+CONFIG_NB
+CONFIG_NCEL2C100_BASE
+CONFIG_NCEMIC100_BASE
+CONFIG_NDS_DLM1_BASE
+CONFIG_NDS_DLM2_BASE
+CONFIG_NEC_NL6448AC33
+CONFIG_NEC_NL6448BC20
+CONFIG_NEC_NL6448BC33_54
+CONFIG_NEEDS_MANUAL_RELOC
+CONFIG_NEO
+CONFIG_NET2BIG_V2
+CONFIG_NETCONSOLE_BUFFER_SIZE
+CONFIG_NETDEV
+CONFIG_NETMASK
+CONFIG_NETSPACE_LITE_V2
+CONFIG_NETSPACE_MAX_V2
+CONFIG_NETSPACE_MINI_V2
+CONFIG_NETSPACE_V2
+CONFIG_NET_MAXDEFRAG
+CONFIG_NET_MULTI
+CONFIG_NET_RETRY_COUNT
+CONFIG_NEVER_ASSERT_ODT_TO_CPU
+CONFIG_NFC_FREQ
+CONFIG_NFSBOOTCOMMAND
+CONFIG_NFS_READ_SIZE
+CONFIG_NFS_TIMEOUT
+CONFIG_NOBQFMAN
+CONFIG_NON_SECURE
+CONFIG_NORBOOT
+CONFIG_NORFLASH_PS32BIT
+CONFIG_NOT_SELECTED
+CONFIG_NO_ETH
+CONFIG_NO_RELOCATION
+CONFIG_NO_SERIAL_EEPROM
+CONFIG_NO_WAIT
+CONFIG_NR_CPUS
+CONFIG_NR_DRAM_BANKS
+CONFIG_NR_DRAM_BANKS_MAX
+CONFIG_NR_DRAM_POPULATED
+CONFIG_NS16550_MIN_FUNCTIONS
+CONFIG_NS8382X
+CONFIG_NS87308
+CONFIG_NUM_DSP_CPUS
+CONFIG_NUM_PAMU
+CONFIG_OCLK_DIV
+CONFIG_ODROID_REV_AIN
+CONFIG_OFF_PADCONF
+CONFIG_OF_
+CONFIG_OF_IDE_FIXUP
+CONFIG_OF_PLATDATA
+CONFIG_OF_SPI
+CONFIG_OF_SPI_FLASH
+CONFIG_OF_STDOUT_PATH
+CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
+CONFIG_OMAP
+CONFIG_OMAP3430
+CONFIG_OMAP3_AM3517CRANE
+CONFIG_OMAP3_DEVKIT8000
+CONFIG_OMAP3_EVM
+CONFIG_OMAP3_GPIO_2
+CONFIG_OMAP3_GPIO_3
+CONFIG_OMAP3_GPIO_4
+CONFIG_OMAP3_GPIO_5
+CONFIG_OMAP3_GPIO_6
+CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID
+CONFIG_OMAP3_MCX
+CONFIG_OMAP3_MICRON_DDR
+CONFIG_OMAP3_RX51
+CONFIG_OMAP3_SPI_D0_D1_SWAPPED
+CONFIG_OMAP3_ZOOM1
+CONFIG_OMAP4430
+CONFIG_OMAP54X
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
+CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
+CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
+CONFIG_OMAP_GPIO
+CONFIG_OMAP_HSMMC
+CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+CONFIG_OMAP_USB2PHY2_HOST
+CONFIG_OMAP_USB3PHY1_HOST
+CONFIG_OMAP_USB_PHY
+CONFIG_OMAP_VC_I2C_HS_MCODE
+CONFIG_OMAP_WATCHDOG
+CONFIG_OPTREX_BW
+CONFIG_ORIGEN
+CONFIG_OS1_ENV_ADDR
+CONFIG_OS2_ENV_ADDR
+CONFIG_OS_ENV_ADDR
+CONFIG_OTHBOOTARGS
+CONFIG_OVERWRITE_ETHADDR_ONCE
+CONFIG_PAGE_CNT_MASK
+CONFIG_PAGE_CNT_SHIFT
+CONFIG_PALMAS_AUDPWR
+CONFIG_PALMAS_POWER
+CONFIG_PALMAS_SMPS7_FPWM
+CONFIG_PALMAS_USB_SS_PWR
+CONFIG_PANIC_HANG
+CONFIG_PARAVIRT
+CONFIG_PARTITIONS
+CONFIG_PARTITION_TYPE_GUID
+CONFIG_PARTITION_UUIDS
+CONFIG_PATA_BFIN
+CONFIG_PATI
+CONFIG_PB1000
+CONFIG_PB1100
+CONFIG_PB1500
+CONFIG_PB1X00
+CONFIG_PCA953X
+CONFIG_PCA9564_BASE
+CONFIG_PCA9564_I2C
+CONFIG_PCA9698
+CONFIG_PCI1
+CONFIG_PCI2
+CONFIG_PCIAUTO_SKIP_HOST_BRIDGE
+CONFIG_PCIE
+CONFIG_PCIE1
+CONFIG_PCIE2
+CONFIG_PCIE3
+CONFIG_PCIE4
+CONFIG_PCIE_IMX
+CONFIG_PCIE_IMX_PERST_GPIO
+CONFIG_PCIE_IMX_POWER_GPIO
+CONFIG_PCIE_LAYERSCAPE
+CONFIG_PCISLAVE
+CONFIG_PCIX_CHECK
+CONFIG_PCI_33M
+CONFIG_PCI_4xx_PTM_OVERWRITE
+CONFIG_PCI_66M
+CONFIG_PCI_BOOTDELAY
+CONFIG_PCI_CLK_FREQ
+CONFIG_PCI_CONFIG_HOST_BRIDGE
+CONFIG_PCI_DISABLE_PCIE
+CONFIG_PCI_EHCI_DEVICE
+CONFIG_PCI_EHCI_DEVNO
+CONFIG_PCI_ENUM_ONLY
+CONFIG_PCI_FIXUP_DEV
+CONFIG_PCI_GT64120
+CONFIG_PCI_HOST
+CONFIG_PCI_INDIRECT_BRIDGE
+CONFIG_PCI_IO_BUS
+CONFIG_PCI_IO_PHYS
+CONFIG_PCI_IO_SIZE
+CONFIG_PCI_MEMORY_BUS
+CONFIG_PCI_MEMORY_PHYS
+CONFIG_PCI_MEMORY_SIZE
+CONFIG_PCI_MEM_BUS
+CONFIG_PCI_MEM_PHYS
+CONFIG_PCI_MEM_SIZE
+CONFIG_PCI_MSC01
+CONFIG_PCI_MVEBU
+CONFIG_PCI_NOSCAN
+CONFIG_PCI_OHCI
+CONFIG_PCI_OHCI_DEVNO
+CONFIG_PCI_PREF_BUS
+CONFIG_PCI_PREF_PHYS
+CONFIG_PCI_PREF_SIZE
+CONFIG_PCI_SCAN_SHOW
+CONFIG_PCI_SKIP_HOST_BRIDGE
+CONFIG_PCI_SYS_BUS
+CONFIG_PCI_SYS_MEM_BUS
+CONFIG_PCI_SYS_MEM_PHYS
+CONFIG_PCI_SYS_MEM_SIZE
+CONFIG_PCI_SYS_PHYS
+CONFIG_PCI_SYS_SIZE
+CONFIG_PCMCIA
+CONFIG_PCMCIA_SLOT_A
+CONFIG_PCMCIA_SLOT_B
+CONFIG_PCNET
+CONFIG_PCNET_79C973
+CONFIG_PCNET_79C975
+CONFIG_PDM360NG
+CONFIG_PDSP188x
+CONFIG_PEN_ADDR_BIG_ENDIAN
+CONFIG_PERIF1_FREQ
+CONFIG_PERIF2_FREQ
+CONFIG_PERIF3_FREQ
+CONFIG_PERIF4_FREQ
+CONFIG_PHY1_ADDR
+CONFIG_PHY2_ADDR
+CONFIG_PHY3_ADDR
+CONFIG_PHYCORE_MPC5200B_TINY
+CONFIG_PHYLIB_10G
+CONFIG_PHYSMEM
+CONFIG_PHY_ADDR
+CONFIG_PHY_AQUANTIA
+CONFIG_PHY_ATHEROS
+CONFIG_PHY_BASE_ADR
+CONFIG_PHY_BCM5421S
+CONFIG_PHY_BROADCOM
+CONFIG_PHY_CLK_FREQ
+CONFIG_PHY_CLOCK_FREQ
+CONFIG_PHY_CMD_DELAY
+CONFIG_PHY_CORTINA
+CONFIG_PHY_DAVICOM
+CONFIG_PHY_DYNAMIC_ANEG
+CONFIG_PHY_ET1011C
+CONFIG_PHY_ET1011C_TX_CLK_FIX
+CONFIG_PHY_GIGE
+CONFIG_PHY_ID
+CONFIG_PHY_INTERFACE_MODE
+CONFIG_PHY_IRAM_BASE
+CONFIG_PHY_KSZ9031
+CONFIG_PHY_LXT
+CONFIG_PHY_M88E1111
+CONFIG_PHY_MARVELL
+CONFIG_PHY_MAX_ADDR
+CONFIG_PHY_MICREL
+CONFIG_PHY_MICREL_KSZ9021
+CONFIG_PHY_MICREL_KSZ9031
+CONFIG_PHY_MODE_NEED_CHANGE
+CONFIG_PHY_NATSEMI
+CONFIG_PHY_REALTEK
+CONFIG_PHY_RESET
+CONFIG_PHY_RESET_DELAY
+CONFIG_PHY_SMSC
+CONFIG_PHY_TERANETICS
+CONFIG_PHY_TI
+CONFIG_PHY_TYPE
+CONFIG_PHY_VITESSE
+CONFIG_PHY_XILINX
+CONFIG_PHYx_ADDR
+CONFIG_PICOSAM
+CONFIG_PIGGY_MAC_ADRESS_OFFSET
+CONFIG_PIP405
+CONFIG_PIXIS_BRDCFG0_SPI
+CONFIG_PIXIS_BRDCFG0_USB2
+CONFIG_PIXIS_BRDCFG1_AUDCLK_11
+CONFIG_PIXIS_BRDCFG1_AUDCLK_12
+CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK
+CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK
+CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI
+CONFIG_PIXIS_BRDCFG1_TDM
+CONFIG_PIXIS_SGMII_CMD
+CONFIG_PL010_SERIAL
+CONFIG_PL011_CLOCK
+CONFIG_PL011_SERIAL
+CONFIG_PL011_SERIAL_RLCR
+CONFIG_PL01X_SERIAL
+CONFIG_PL01x_PORTS
+CONFIG_PLATFORM_ENV_SETTINGS
+CONFIG_PLATINUM_BOARD
+CONFIG_PLATINUM_CPU
+CONFIG_PLATINUM_PICON
+CONFIG_PLATINUM_PROJECT
+CONFIG_PLATINUM_TITANIUM
+CONFIG_PLL
+CONFIG_PLL1_CLK_FREQ
+CONFIG_PLL1_DIV2_CLK_FREQ
+CONFIG_PLL_BYPASS
+CONFIG_PLL_CTL_VAL
+CONFIG_PLL_DIV_VAL
+CONFIG_PLL_LOCKCNT_VAL
+CONFIG_PLU405
+CONFIG_PM
+CONFIG_PM9261
+CONFIG_PM9263
+CONFIG_PM9G45
+CONFIG_PMC405DE
+CONFIG_PMC_BR_PRELIM
+CONFIG_PMC_OR_PRELIM
+CONFIG_PMECC_CAP
+CONFIG_PMECC_INDEX_TABLE_OFFSET
+CONFIG_PMECC_SECTOR_SIZE
+CONFIG_PME_PLAT_CLK_DIV
+CONFIG_PMIC
+CONFIG_PMU
+CONFIG_PMW_BASE
+CONFIG_PM_SLEEP
+CONFIG_PORTMUX_PIO
+CONFIG_PORT_ADDR
+CONFIG_PORT_AP
+CONFIG_PORT_BEM
+CONFIG_PORT_BME
+CONFIG_PORT_BS
+CONFIG_PORT_BU
+CONFIG_PORT_BW
+CONFIG_PORT_CR
+CONFIG_PORT_CSN
+CONFIG_PORT_OEN
+CONFIG_PORT_PEN
+CONFIG_PORT_RE
+CONFIG_PORT_SOR
+CONFIG_PORT_TH
+CONFIG_PORT_TWE
+CONFIG_PORT_WBF
+CONFIG_PORT_WBN
+CONFIG_POST
+CONFIG_POSTBOOTMENU
+CONFIG_POST_ALT_LIST
+CONFIG_POST_BSPEC1
+CONFIG_POST_BSPEC1_GPIO_LEDS
+CONFIG_POST_BSPEC2
+CONFIG_POST_BSPEC2_GPIO_BUTTONS
+CONFIG_POST_BSPEC2_GPIO_NAMES
+CONFIG_POST_BSPEC3
+CONFIG_POST_BSPEC4
+CONFIG_POST_BSPEC5
+CONFIG_POST_EXTERNAL_WORD_FUNCS
+CONFIG_POST_KEY_MAGIC
+CONFIG_POST_SKIP_ENV_FLAGS
+CONFIG_POST_STD_LIST
+CONFIG_POST_UART
+CONFIG_POST_WATCHDOG
+CONFIG_POWER
+CONFIG_POWER_FSL
+CONFIG_POWER_FSL_MC13892
+CONFIG_POWER_FSL_MC34704
+CONFIG_POWER_HI6553
+CONFIG_POWER_I2C
+CONFIG_POWER_LTC3676
+CONFIG_POWER_LTC3676_I2C_ADDR
+CONFIG_POWER_MAX77696
+CONFIG_POWER_MAX77696_I2C_ADDR
+CONFIG_POWER_PFUZE100
+CONFIG_POWER_PFUZE100_I2C_ADDR
+CONFIG_POWER_PFUZE3000
+CONFIG_POWER_PFUZE3000_I2C_ADDR
+CONFIG_POWER_SPI
+CONFIG_POWER_TPS62362
+CONFIG_POWER_TPS65090_EC
+CONFIG_POWER_TPS65217
+CONFIG_POWER_TPS65218
+CONFIG_POWER_TPS65910
+CONFIG_PPC4XX_RAPIDIO_DEBUG
+CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
+CONFIG_PPC4XX_RAPIDIO_LOOPBACK
+CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
+CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
+CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+CONFIG_PPC4xx_DDR_METHOD_A
+CONFIG_PPC4xx_EMAC
+CONFIG_PPC64BRIDGE
+CONFIG_PPC_CLUSTER_START
+CONFIG_PPC_SPINTABLE_COMPATIBLE
+CONFIG_PQ_MDS_PIB
+CONFIG_PQ_MDS_PIB_ATM
+CONFIG_PRAM
+CONFIG_PREBOOT
+CONFIG_PRIMEVIEW_V16C6448AC
+CONFIG_PRINTK
+CONFIG_PROC_FS
+CONFIG_PROFILE_ALL_BRANCHES
+CONFIG_PROFILING
+CONFIG_PROG_FDT
+CONFIG_PROG_FDT1
+CONFIG_PROG_FDT2
+CONFIG_PROG_OS
+CONFIG_PROG_OS1
+CONFIG_PROG_OS2
+CONFIG_PROG_SDRAM_TLB
+CONFIG_PROG_UBOOT
+CONFIG_PROG_UBOOT1
+CONFIG_PROG_UBOOT2
+CONFIG_PROOF_POINTS
+CONFIG_PRPMC_PCI_ALIAS
+CONFIG_PS2KBD
+CONFIG_PS2MULT
+CONFIG_PS2MULT_DELAY
+CONFIG_PS2SERIAL
+CONFIG_PSC3_USB
+CONFIG_PSC_CONSOLE
+CONFIG_PSC_CONSOLE2
+CONFIG_PSRAM_SCFG
+CONFIG_PWM
+CONFIG_PWM_IMX
+CONFIG_PXA_LCD
+CONFIG_PXA_MMC_GENERIC
+CONFIG_PXA_PWR_I2C
+CONFIG_PXA_STD_I2C
+CONFIG_PXA_VGA
+CONFIG_PXA_VIDEO
+CONFIG_P_CLK_FREQ
+CONFIG_QBMAN_CLK_DIV
+CONFIG_QE
+CONFIG_QEMU_MIPS
+CONFIG_QIXIS_I2C_ACCESS
+CONFIG_QSPI
+CONFIG_QSPI_QUAD_SUPPORT
+CONFIG_QSPI_SEL_GPIO
+CONFIG_QUOTA
+CONFIG_R0P7734
+CONFIG_R2DPLUS
+CONFIG_R7780MP
+CONFIG_R8A66597_BASE_ADDR
+CONFIG_R8A66597_ENDIAN
+CONFIG_R8A66597_LDRV
+CONFIG_R8A66597_XTAL
+CONFIG_R8A7740
+CONFIG_R8A7790
+CONFIG_R8A7791
+CONFIG_R8A7792
+CONFIG_R8A7793
+CONFIG_R8A7794
+CONFIG_RAINIER
+CONFIG_RAMBOOT
+CONFIG_RAMBOOTCOMMAND
+CONFIG_RAMBOOTCOMMAND_TFTP
+CONFIG_RAMBOOT_NAND
+CONFIG_RAMBOOT_PBL
+CONFIG_RAMBOOT_SDCARD
+CONFIG_RAMBOOT_SPIFLASH
+CONFIG_RAMBOOT_TEXT_BASE
+CONFIG_RAMDISKFILE
+CONFIG_RAMDISK_ADDR
+CONFIG_RAMDISK_BOOT
+CONFIG_RAM_BOOT
+CONFIG_RAM_BOOT_PHYS
+CONFIG_RANDOM_UUID
+CONFIG_RAPIDIO
+CONFIG_RBTREE
+CONFIG_RCAR_BOARD_STRING
+CONFIG_RD_LVL
+CONFIG_REALMODE_DEBUG
+CONFIG_RED_LED
+CONFIG_REFCLK_FREQ
+CONFIG_REG
+CONFIG_REG_0
+CONFIG_REG_1_BASE
+CONFIG_REG_2
+CONFIG_REG_3
+CONFIG_REG_8
+CONFIG_REG_APER_SIZE
+CONFIG_RELOC_GOT_SKIP_NULL
+CONFIG_REMAKE_ELF
+CONFIG_REQ
+CONFIG_RESERVED_01_BASE
+CONFIG_RESERVED_02_BASE
+CONFIG_RESERVED_03_BASE
+CONFIG_RESERVED_04_BASE
+CONFIG_RESET
+CONFIG_RESET_PHY_R
+CONFIG_RESET_TO_RETRY
+CONFIG_RESET_VECTOR_ADDRESS
+CONFIG_RESTORE_FLASH
+CONFIG_RES_BLOCK_SIZE
+CONFIG_REV1
+CONFIG_REV3
+CONFIG_REVISION_TAG
+CONFIG_RFSPART
+CONFIG_RGMII
+CONFIG_RIO
+CONFIG_RMII
+CONFIG_RMOBILE_BOARD_STRING
+CONFIG_RMSTP0_ENA
+CONFIG_RMSTP10_ENA
+CONFIG_RMSTP11_ENA
+CONFIG_RMSTP1_ENA
+CONFIG_RMSTP2_ENA
+CONFIG_RMSTP3_ENA
+CONFIG_RMSTP4_ENA
+CONFIG_RMSTP5_ENA
+CONFIG_RMSTP6_ENA
+CONFIG_RMSTP7_ENA
+CONFIG_RMSTP8_ENA
+CONFIG_RMSTP9_ENA
+CONFIG_ROCKCHIP_CHIP_TAG
+CONFIG_ROCKCHIP_MAX_INIT_SIZE
+CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
+CONFIG_ROCKCHIP_USB2_PHY
+CONFIG_ROM_STUBS
+CONFIG_ROOTFS_OFFSET
+CONFIG_ROOTPATH
+CONFIG_RSK7203
+CONFIG_RSK7264
+CONFIG_RSK7269
+CONFIG_RTC_BFIN
+CONFIG_RTC_DS1307
+CONFIG_RTC_DS1337
+CONFIG_RTC_DS1338
+CONFIG_RTC_DS1374
+CONFIG_RTC_DS1388
+CONFIG_RTC_DS1556
+CONFIG_RTC_DS174x
+CONFIG_RTC_DS3231
+CONFIG_RTC_FTRTC010
+CONFIG_RTC_IMXDI
+CONFIG_RTC_INTERNAL
+CONFIG_RTC_M41T11
+CONFIG_RTC_M41T60
+CONFIG_RTC_M41T62
+CONFIG_RTC_M48T35A
+CONFIG_RTC_MC13XXX
+CONFIG_RTC_MC146818
+CONFIG_RTC_MCFRRTC
+CONFIG_RTC_MCP79411
+CONFIG_RTC_MPC5200
+CONFIG_RTC_MPC8xx
+CONFIG_RTC_MV
+CONFIG_RTC_MXS
+CONFIG_RTC_PCF8563
+CONFIG_RTC_PT7C4338
+CONFIG_RTC_RTC4543
+CONFIG_RTC_RV3029
+CONFIG_RTC_RX8025
+CONFIG_RTC_X1205
+CONFIG_RUN_FROM_DDR0
+CONFIG_RUN_FROM_DDR1
+CONFIG_RUN_FROM_IRAM_ONLY
+CONFIG_RX_DESCR_NUM
+CONFIG_S32V234
+CONFIG_S3C2400
+CONFIG_S3C2410
+CONFIG_S3C2410_NAND_BBT
+CONFIG_S3C2410_NAND_HWECC
+CONFIG_S3C2440
+CONFIG_S3C24X0
+CONFIG_S3C24XX_TACLS
+CONFIG_S3C24XX_TWRPH0
+CONFIG_S3C24XX_TWRPH1
+CONFIG_S3D2_CLK_FREQ
+CONFIG_S5P
+CONFIG_S5PC100
+CONFIG_S5PC110
+CONFIG_S5P_PA_SYSRAM
+CONFIG_S6E63D6
+CONFIG_S6E8AX0
+CONFIG_SA1100_ADSBITSY
+CONFIG_SA1100_ASSABET
+CONFIG_SA1100_BADGE4
+CONFIG_SA1100_BRUTUS
+CONFIG_SA1100_CERF
+CONFIG_SA1100_COLLIE
+CONFIG_SA1100_CONSUS
+CONFIG_SA1100_FLEXANET
+CONFIG_SA1100_GRAPHICSCLIENT
+CONFIG_SA1100_GRAPHICSMASTER
+CONFIG_SA1100_H3100
+CONFIG_SA1100_H3600
+CONFIG_SA1100_HACKKIT
+CONFIG_SA1100_JORNADA720
+CONFIG_SA1100_LART
+CONFIG_SA1100_NANOENGINE
+CONFIG_SA1100_PFS168
+CONFIG_SA1100_PLEB
+CONFIG_SA1100_PT_SYSTEM3
+CONFIG_SA1100_SHANNON
+CONFIG_SA1100_SIMPAD
+CONFIG_SA1100_XP860
+CONFIG_SABRELITE
+CONFIG_SAMA5D2
+CONFIG_SAMA5D3
+CONFIG_SAMA5D3_LCD_BASE
+CONFIG_SAMA5D4
+CONFIG_SAMSUNG
+CONFIG_SAMSUNG_ONENAND
+CONFIG_SANDBOX_ARCH
+CONFIG_SANDBOX_BIG_ENDIAN
+CONFIG_SANDBOX_BITS_PER_LONG
+CONFIG_SANDBOX_SDL
+CONFIG_SANDBOX_SPI_MAX_BUS
+CONFIG_SANDBOX_SPI_MAX_CS
+CONFIG_SAR2_REG
+CONFIG_SAR_REG
+CONFIG_SATA1
+CONFIG_SATA2
+CONFIG_SATAPWR
+CONFIG_SATA_DWC
+CONFIG_SATA_MV
+CONFIG_SATA_SIL
+CONFIG_SATA_SIL3114
+CONFIG_SATA_ULI5288
+CONFIG_SBC8349
+CONFIG_SBC8548
+CONFIG_SBC8641D
+CONFIG_SCC1_ENET
+CONFIG_SCC2_ENET
+CONFIG_SCF0403_LCD
+CONFIG_SCIF
+CONFIG_SCIF_A
+CONFIG_SCIF_CONSOLE
+CONFIG_SCIF_EXT_CLOCK
+CONFIG_SCIF_USE_EXT_CLK
+CONFIG_SCLK0_DIV
+CONFIG_SCLK1_DIV
+CONFIG_SCLK_DIV
+CONFIG_SCLK_HZ
+CONFIG_SCSI
+CONFIG_SCSI_AHCI
+CONFIG_SCSI_AHCI_PLAT
+CONFIG_SCSI_DEV_ID
+CONFIG_SCSI_DEV_LIST
+CONFIG_SCSI_SYM53C8XX
+CONFIG_SC_TIMER_CLK
+CONFIG_SDCARD
+CONFIG_SDRAM_BANK0
+CONFIG_SDRAM_BANK1
+CONFIG_SDRAM_ECC
+CONFIG_SDRAM_OFFSET_FOR_RT
+CONFIG_SDRAM_PPC4xx_DENALI_DDR2
+CONFIG_SDRAM_PPC4xx_IBM_DDR
+CONFIG_SDRAM_PPC4xx_IBM_DDR2
+CONFIG_SDRAM_PPC4xx_IBM_SDRAM
+CONFIG_SDRC
+CONFIG_SDR_MT48LC16M16A2
+CONFIG_SD_BOOT_QSPI
+CONFIG_SECBOOT
+CONFIG_SECURE_BL1_ONLY
+CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
+CONFIG_SECURITY
+CONFIG_SEC_DEQ_TIMEOUT
+CONFIG_SEC_FW_SIZE
+CONFIG_SELECTED
+CONFIG_SEQUOIA
+CONFIG_SERIAL0
+CONFIG_SERIAL1
+CONFIG_SERIAL2
+CONFIG_SERIAL3
+CONFIG_SERIAL_BOOT
+CONFIG_SERIAL_FLASH
+CONFIG_SERIAL_HW_FLOW_CONTROL
+CONFIG_SERIAL_MULTI
+CONFIG_SERIAL_SOFTWARE_FIFO
+CONFIG_SERIAL_TAG
+CONFIG_SERIRQ_CONTINUOUS_MODE
+CONFIG_SERVERIP
+CONFIG_SETUP_INITRD_TAG
+CONFIG_SETUP_MEMORY_TAGS
+CONFIG_SET_BIST
+CONFIG_SET_BOOTARGS
+CONFIG_SET_DFU_ALT_BUF_LEN
+CONFIG_SET_DFU_ALT_INFO
+CONFIG_SFIO
+CONFIG_SF_DATAFLASH
+CONFIG_SF_DEFAULT_BUS
+CONFIG_SF_DEFAULT_CS
+CONFIG_SF_DEFAULT_HZ
+CONFIG_SF_DEFAULT_MODE
+CONFIG_SF_DEFAULT_SPEED
+CONFIG_SF_DUAL_FLASH
+CONFIG_SGI_IP28
+CONFIG_SH4_PCI
+CONFIG_SH73A0
+CONFIG_SH7751_PCI
+CONFIG_SH7752EVB
+CONFIG_SH7753EVB
+CONFIG_SH7757LCR
+CONFIG_SH7757LCR_DDR_ECC
+CONFIG_SH7763RDP
+CONFIG_SH7780_PCI
+CONFIG_SH7780_PCI_BAR
+CONFIG_SH7780_PCI_LAR
+CONFIG_SH7780_PCI_LSR
+CONFIG_SH7785LCR
+CONFIG_SHA1SUM_VERIFY
+CONFIG_SHARP_16x9
+CONFIG_SHARP_LM8V31
+CONFIG_SHARP_LQ035Q7DH06
+CONFIG_SHARP_LQ057Q3DC02
+CONFIG_SHARP_LQ065T9DR51U
+CONFIG_SHARP_LQ084V1DG21
+CONFIG_SHARP_LQ104V7DS01
+CONFIG_SHARP_LQ64D341
+CONFIG_SHEEVA_88SV131
+CONFIG_SHEEVA_88SV331xV5
+CONFIG_SHELL
+CONFIG_SHMIN
+CONFIG_SHOW_ACTIVITY
+CONFIG_SHOW_BOOT_PROGRESS
+CONFIG_SH_CMT_CLK_FREQ
+CONFIG_SH_DSP
+CONFIG_SH_ETHER
+CONFIG_SH_ETHER_ALIGNE_SIZE
+CONFIG_SH_ETHER_BASE_ADDR
+CONFIG_SH_ETHER_CACHE_INVALIDATE
+CONFIG_SH_ETHER_CACHE_WRITEBACK
+CONFIG_SH_ETHER_PHY_ADDR
+CONFIG_SH_ETHER_PHY_MODE
+CONFIG_SH_ETHER_SH7734_MII
+CONFIG_SH_ETHER_USE_GETHER
+CONFIG_SH_ETHER_USE_PORT
+CONFIG_SH_GPIO_PFC
+CONFIG_SH_I2C_8BIT
+CONFIG_SH_I2C_BASE0
+CONFIG_SH_I2C_BASE1
+CONFIG_SH_I2C_CLOCK
+CONFIG_SH_I2C_DATA_HIGH
+CONFIG_SH_I2C_DATA_LOW
+CONFIG_SH_MMCIF
+CONFIG_SH_MMCIF_ADDR
+CONFIG_SH_MMCIF_CLK
+CONFIG_SH_QSPI
+CONFIG_SH_QSPI_BASE
+CONFIG_SH_SCIF_CLK_FREQ
+CONFIG_SH_SDHI_FREQ
+CONFIG_SH_SDRAM_OFFSET
+CONFIG_SH_SH7734_I2C
+CONFIG_SH_SPI
+CONFIG_SH_SPI_BASE
+CONFIG_SH_TMU_CLK_FREQ
+CONFIG_SIEMENS_DRACO
+CONFIG_SIEMENS_MACH_TYPE
+CONFIG_SIEMENS_PXM2
+CONFIG_SIEMENS_RUT
+CONFIG_SIMU
+CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
+CONFIG_SKIP_LOWLEVEL_INIT
+CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+CONFIG_SKIP_TRUNOFF_WATCHDOG
+CONFIG_SLIC
+CONFIG_SLTTMR
+CONFIG_SMC91111
+CONFIG_SMC91111_BASE
+CONFIG_SMC91111_EXT_PHY
+CONFIG_SMC911X
+CONFIG_SMC911X_16_BIT
+CONFIG_SMC911X_32_BIT
+CONFIG_SMC911X_BASE
+CONFIG_SMC911X_NO_EEPROM
+CONFIG_SMC_91111_EXT_PHY
+CONFIG_SMC_AUTONEG_TIMEOUT
+CONFIG_SMC_B0CTL_VAL
+CONFIG_SMC_B0ETIM_VAL
+CONFIG_SMC_B0TIM_VAL
+CONFIG_SMC_B1CTL_VAL
+CONFIG_SMC_B1ETIM_VAL
+CONFIG_SMC_B1TIM_VAL
+CONFIG_SMC_B2CTL_VAL
+CONFIG_SMC_B2ETIM_VAL
+CONFIG_SMC_B2TIM_VAL
+CONFIG_SMC_B3CTL_VAL
+CONFIG_SMC_B3ETIM_VAL
+CONFIG_SMC_B3TIM_VAL
+CONFIG_SMC_GCTL_VAL
+CONFIG_SMC_USE_32_BIT
+CONFIG_SMC_USE_IOFUNCS
+CONFIG_SMDK5420
+CONFIG_SMDKC100
+CONFIG_SMDKV310
+CONFIG_SMP_PEN_ADDR
+CONFIG_SMSC_LPC47M
+CONFIG_SMSC_SIO1007
+CONFIG_SMSTP0_ENA
+CONFIG_SMSTP10_ENA
+CONFIG_SMSTP11_ENA
+CONFIG_SMSTP1_ENA
+CONFIG_SMSTP2_ENA
+CONFIG_SMSTP3_ENA
+CONFIG_SMSTP4_ENA
+CONFIG_SMSTP5_ENA
+CONFIG_SMSTP6_ENA
+CONFIG_SMSTP7_ENA
+CONFIG_SMSTP8_ENA
+CONFIG_SMSTP9_ENA
+CONFIG_SOCFPGA_DWMMC
+CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH
+CONFIG_SOCFPGA_VIRTUAL_TARGET
+CONFIG_SOCRATES
+CONFIG_SOC_AU1000
+CONFIG_SOC_AU1100
+CONFIG_SOC_AU1500
+CONFIG_SOC_AU1550
+CONFIG_SOC_AU1X00
+CONFIG_SOC_DA850
+CONFIG_SOC_DA8XX
+CONFIG_SOC_DM355
+CONFIG_SOC_DM365
+CONFIG_SOC_DM644X
+CONFIG_SOC_DM646X
+CONFIG_SOC_K2E
+CONFIG_SOC_K2G
+CONFIG_SOC_K2HK
+CONFIG_SOC_K2L
+CONFIG_SOC_KEYSTONE
+CONFIG_SOC_OMAP3430
+CONFIG_SOFT_I2C_GPIO_SCL
+CONFIG_SOFT_I2C_GPIO_SDA
+CONFIG_SOFT_I2C_I2C10_SCL
+CONFIG_SOFT_I2C_I2C10_SDA
+CONFIG_SOFT_I2C_I2C5_SCL
+CONFIG_SOFT_I2C_I2C5_SDA
+CONFIG_SOFT_I2C_I2C9_SCL
+CONFIG_SOFT_I2C_I2C9_SDA
+CONFIG_SOFT_I2C_MULTI_BUS
+CONFIG_SOFT_I2C_READ_REPEATED_START
+CONFIG_SOFT_SPI
+CONFIG_SOFT_TWS
+CONFIG_SOURCE
+CONFIG_SPARSE_RCU_POINTER
+CONFIG_SPDDRAM_SILENT
+CONFIG_SPD_EEPROM
+CONFIG_SPEAR300
+CONFIG_SPEAR310
+CONFIG_SPEAR320
+CONFIG_SPEAR3XX
+CONFIG_SPEAR600
+CONFIG_SPEAR_BOOTSTRAPCFG
+CONFIG_SPEAR_BOOTSTRAPMASK
+CONFIG_SPEAR_BOOTSTRAPSHFT
+CONFIG_SPEAR_EMI
+CONFIG_SPEAR_EMIBASE
+CONFIG_SPEAR_ETHBASE
+CONFIG_SPEAR_GPIO
+CONFIG_SPEAR_HZ
+CONFIG_SPEAR_HZ_CLOCK
+CONFIG_SPEAR_MISCBASE
+CONFIG_SPEAR_MPMCBASE
+CONFIG_SPEAR_MPMCREGS
+CONFIG_SPEAR_NORNAND16BOOT
+CONFIG_SPEAR_NORNAND8BOOT
+CONFIG_SPEAR_NORNANDBOOT
+CONFIG_SPEAR_ONLYSNORBOOT
+CONFIG_SPEAR_RASBASE
+CONFIG_SPEAR_SYSCNTLBASE
+CONFIG_SPEAR_TIMERBASE
+CONFIG_SPEAR_UART48M
+CONFIG_SPEAR_UARTCLKMSK
+CONFIG_SPEAR_USBBOOT
+CONFIG_SPEAR_USBTTY
+CONFIG_SPI
+CONFIG_SPI_ADDR
+CONFIG_SPI_BAUD_INITBLOCK
+CONFIG_SPI_BOOTING
+CONFIG_SPI_CS_IS_VALID
+CONFIG_SPI_DATAFLASH_WRITE_VERIFY
+CONFIG_SPI_FLASH_ALL
+CONFIG_SPI_FLASH_ISSI
+CONFIG_SPI_FLASH_QUAD
+CONFIG_SPI_FLASH_SIZE
+CONFIG_SPI_HALF_DUPLEX
+CONFIG_SPI_IDLE_VAL
+CONFIG_SPI_LENGTH
+CONFIG_SPI_N25Q256A_RESET
+CONFIG_SPLASHIMAGE_GUARD
+CONFIG_SPLASH_SCREEN
+CONFIG_SPLASH_SCREEN_ALIGN
+CONFIG_SPLASH_SOURCE
+CONFIG_SPLL_FREQ
+CONFIG_SPL_
+CONFIG_SPL_ABORT_ON_RAW_IMAGE
+CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+CONFIG_SPL_ATMEL_SIZE
+CONFIG_SPL_BOARD_INIT
+CONFIG_SPL_BOARD_LOAD_IMAGE
+CONFIG_SPL_BOOTROM_SAVE
+CONFIG_SPL_BOOT_DEVICE
+CONFIG_SPL_BSS_MAX_SIZE
+CONFIG_SPL_BSS_START_ADDR
+CONFIG_SPL_CMT
+CONFIG_SPL_CMT_DEBUG
+CONFIG_SPL_COMMON_INIT_DDR
+CONFIG_SPL_CONSOLE
+CONFIG_SPL_ETH_DEVICE
+CONFIG_SPL_FLUSH_IMAGE
+CONFIG_SPL_FRAMEWORK
+CONFIG_SPL_FSL_PBL
+CONFIG_SPL_FS_LOAD_ARGS_NAME
+CONFIG_SPL_FS_LOAD_KERNEL_NAME
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+CONFIG_SPL_GD_ADDR
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+CONFIG_SPL_INIT_MINIMAL
+CONFIG_SPL_JR0_LIODN_NS
+CONFIG_SPL_JR0_LIODN_S
+CONFIG_SPL_LDSCRIPT
+CONFIG_SPL_LOAD_FIT_ADDRESS
+CONFIG_SPL_MAX_FOOTPRINT
+CONFIG_SPL_MAX_PEB_SIZE
+CONFIG_SPL_MAX_SIZE
+CONFIG_SPL_MMC_BOOT
+CONFIG_SPL_MMC_LOAD
+CONFIG_SPL_MMC_MINIMAL
+CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
+CONFIG_SPL_MXS_PSWITCH_WAIT
+CONFIG_SPL_NAND_AM33XX_BCH
+CONFIG_SPL_NAND_BASE
+CONFIG_SPL_NAND_BOOT
+CONFIG_SPL_NAND_DRIVERS
+CONFIG_SPL_NAND_ECC
+CONFIG_SPL_NAND_INIT
+CONFIG_SPL_NAND_LOAD
+CONFIG_SPL_NAND_MINIMAL
+CONFIG_SPL_NAND_MXS
+CONFIG_SPL_NAND_RAW_ONLY
+CONFIG_SPL_NAND_SIMPLE
+CONFIG_SPL_NAND_SOFTECC
+CONFIG_SPL_NAND_WORKSPACE
+CONFIG_SPL_NO_CPU_SUPPORT_CODE
+CONFIG_SPL_OMAP3_ID_NAND
+CONFIG_SPL_PAD_TO
+CONFIG_SPL_PANIC_ON_RAW_IMAGE
+CONFIG_SPL_PBL_PAD
+CONFIG_SPL_PPAACT_ADDR
+CONFIG_SPL_RAM_DEVICE
+CONFIG_SPL_RELOC_MALLOC_ADDR
+CONFIG_SPL_RELOC_MALLOC_SIZE
+CONFIG_SPL_RELOC_STACK
+CONFIG_SPL_RELOC_STACK_SIZE
+CONFIG_SPL_RELOC_TEXT_BASE
+CONFIG_SPL_SATA_BOOT_DEVICE
+CONFIG_SPL_SIZE
+CONFIG_SPL_SKIP_RELOCATE
+CONFIG_SPL_SPAACT_ADDR
+CONFIG_SPL_SPI_BOOT
+CONFIG_SPL_SPI_FLASH_MINIMAL
+CONFIG_SPL_SPI_LOAD
+CONFIG_SPL_STACK
+CONFIG_SPL_STACK_ADDR
+CONFIG_SPL_STACK_SIZE
+CONFIG_SPL_START_S_PATH
+CONFIG_SPL_TARGET
+CONFIG_SPL_TEXT_BASE
+CONFIG_SPL_UBI
+CONFIG_SPL_UBI_INFO_ADDR
+CONFIG_SPL_UBI_LEB_START
+CONFIG_SPL_UBI_LOAD_ARGS_ID
+CONFIG_SPL_UBI_LOAD_KERNEL_ID
+CONFIG_SPL_UBI_LOAD_MONITOR_ID
+CONFIG_SPL_UBI_MAX_PEBS
+CONFIG_SPL_UBI_MAX_PEB_SIZE
+CONFIG_SPL_UBI_MAX_VOL_LEBS
+CONFIG_SPL_UBI_PEB_OFFSET
+CONFIG_SPL_UBI_VID_OFFSET
+CONFIG_SPL_UBI_VOL_IDS
+CONFIG_SPL_UBOOT_KEY_HASH
+CONFIG_SRAM_BASE
+CONFIG_SRAM_SIZE
+CONFIG_SRIO1
+CONFIG_SRIO2
+CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
+CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1
+CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2
+CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
+CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
+CONFIG_SRIO_PCIE_BOOT_MASTER
+CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK
+CONFIG_SRIO_PCIE_BOOT_SLAVE
+CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
+CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
+CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
+CONFIG_SSD_BR_PRELIM
+CONFIG_SSD_OR_PRELIM
+CONFIG_SSE2
+CONFIG_SSI1_FREQ
+CONFIG_SSI2_FREQ
+CONFIG_SSP1_BASE
+CONFIG_SSP2_BASE
+CONFIG_SSP3_BASE
+CONFIG_STACKBASE
+CONFIG_STACKSIZE
+CONFIG_STACKSIZE_FIQ
+CONFIG_STACKSIZE_IRQ
+CONFIG_STAMP_CF
+CONFIG_STANDALONE_LOAD_ADDR
+CONFIG_STATIC_BOARD_REV
+CONFIG_STATIC_RELA
+CONFIG_STATUS_LED
+CONFIG_STD_DEVICES_SETTINGS
+CONFIG_STK52XX
+CONFIG_STK52XX_REV100
+CONFIG_STM32F4DISCOVERY
+CONFIG_STM32X7_SERIAL
+CONFIG_STM32_FLASH
+CONFIG_STM32_GPIO
+CONFIG_STM32_HSE_HZ
+CONFIG_STM32_HZ
+CONFIG_STM32_SERIAL
+CONFIG_STRESS
+CONFIG_STRIDER
+CONFIG_STRIDER_CON
+CONFIG_STRIDER_CON_DP
+CONFIG_STRIDER_CPU
+CONFIG_STRIDER_CPU_DP
+CONFIG_STRIDER_FANS
+CONFIG_STUART
+CONFIG_STV0991
+CONFIG_STV0991_HZ
+CONFIG_STV0991_HZ_CLOCK
+CONFIG_ST_SMI
+CONFIG_SUN4
+CONFIG_SUNXI_AHCI
+CONFIG_SUNXI_EMAC
+CONFIG_SUNXI_GMAC
+CONFIG_SUNXI_GPIO
+CONFIG_SUNXI_MAX_FB_SIZE
+CONFIG_SUNXI_USB_PHYS
+CONFIG_SUPERH_ON_CHIP_R8A66597
+CONFIG_SUPPORT_EMMC_BOOT
+CONFIG_SUPPORT_EMMC_RPMB
+CONFIG_SUPPORT_RAW_INITRD
+CONFIG_SUPPORT_VFAT
+CONFIG_SUVD3
+CONFIG_SX151X_GPIO_COUNT_8
+CONFIG_SX151X_SPI_BUS
+CONFIG_SXNI855T
+CONFIG_SYSCOUNTER_TIMER
+CONFIG_SYSFLAGS_ADDR
+CONFIG_SYSFS
+CONFIG_SYSMGR_ISWGRP_HANDOFF
+CONFIG_SYSTEMACE
+CONFIG_SYS_33MHZ
+CONFIG_SYS_405_UART_ERRATA_59
+CONFIG_SYS_460GT_SRIO_ERRATA_1
+CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
+CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
+CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
+CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
+CONFIG_SYS_4xx_CHIP_21_ERRATA
+CONFIG_SYS_4xx_GPIO_TABLE
+CONFIG_SYS_4xx_RESET_TYPE
+CONFIG_SYS_64BIT
+CONFIG_SYS_64BIT_LBA
+CONFIG_SYS_64BIT_VSPRINTF
+CONFIG_SYS_66MHZ
+CONFIG_SYS_8313ERDB_BROKEN_PMC
+CONFIG_SYS_83XX_DDR_USES_CS0
+CONFIG_SYS_8XX_XIN
+CONFIG_SYS_8xx_CPUCLK_MAX
+CONFIG_SYS_8xx_CPUCLK_MIN
+CONFIG_SYS_ACE_BASE
+CONFIG_SYS_ACE_BASE_PHYS_H
+CONFIG_SYS_ACE_BASE_PHYS_L
+CONFIG_SYS_ACR_APARK
+CONFIG_SYS_ACR_PARKM
+CONFIG_SYS_ACR_PIPE_DEP
+CONFIG_SYS_ACR_RPTCNT
+CONFIG_SYS_ADDRESS_MAP_A
+CONFIG_SYS_ADV7611_I2C
+CONFIG_SYS_AHB_BASE
+CONFIG_SYS_ALLOC_DPRAM
+CONFIG_SYS_ALT_BOOT
+CONFIG_SYS_ALT_FLASH
+CONFIG_SYS_ALT_MEMTEST
+CONFIG_SYS_AMASK0
+CONFIG_SYS_AMASK0_FINAL
+CONFIG_SYS_AMASK1
+CONFIG_SYS_AMASK1_FINAL
+CONFIG_SYS_AMASK2
+CONFIG_SYS_AMASK2_FINAL
+CONFIG_SYS_AMASK3
+CONFIG_SYS_AMASK3_FINAL
+CONFIG_SYS_AMASK4
+CONFIG_SYS_AMASK5
+CONFIG_SYS_AMASK6
+CONFIG_SYS_AMASK7
+CONFIG_SYS_APP1_BASE
+CONFIG_SYS_APP1_SIZE
+CONFIG_SYS_APP2_BASE
+CONFIG_SYS_APP2_SIZE
+CONFIG_SYS_ARCH_TIMER
+CONFIG_SYS_ARIA_FPGA_BASE
+CONFIG_SYS_ARIA_FPGA_SIZE
+CONFIG_SYS_ARIA_SRAM_BASE
+CONFIG_SYS_ARIA_SRAM_SIZE
+CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+CONFIG_SYS_AT91_CPU_NAME
+CONFIG_SYS_AT91_MAIN_CLOCK
+CONFIG_SYS_AT91_PLLA
+CONFIG_SYS_AT91_PLLB
+CONFIG_SYS_AT91_SLOW_CLOCK
+CONFIG_SYS_ATA_ALT_OFFSET
+CONFIG_SYS_ATA_BASE_ADDR
+CONFIG_SYS_ATA_CS_ON_I2C2
+CONFIG_SYS_ATA_CS_ON_TIMER01
+CONFIG_SYS_ATA_DATA_OFFSET
+CONFIG_SYS_ATA_IDE0_OFFSET
+CONFIG_SYS_ATA_IDE1_OFFSET
+CONFIG_SYS_ATA_PORT_ADDR
+CONFIG_SYS_ATA_REG_OFFSET
+CONFIG_SYS_ATA_STRIDE
+CONFIG_SYS_ATI_REV_A11
+CONFIG_SYS_ATI_REV_A12
+CONFIG_SYS_ATI_REV_A13
+CONFIG_SYS_ATI_REV_ID_MASK
+CONFIG_SYS_ATMEL_BASE
+CONFIG_SYS_ATMEL_BOOT
+CONFIG_SYS_ATMEL_CPU_NAME
+CONFIG_SYS_ATMEL_REGION
+CONFIG_SYS_ATMEL_SECT
+CONFIG_SYS_ATMEL_SECTSZ
+CONFIG_SYS_ATMEL_TOTALSECT
+CONFIG_SYS_AUTOLOAD
+CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+CONFIG_SYS_AUXCORE_BOOTDATA
+CONFIG_SYS_BARGSIZE
+CONFIG_SYS_BASE_BAUD
+CONFIG_SYS_BAUDRATE_TABLE
+CONFIG_SYS_BCR
+CONFIG_SYS_BCR_60x
+CONFIG_SYS_BCR_SINGLE
+CONFIG_SYS_BCSR
+CONFIG_SYS_BCSR3_PCIE
+CONFIG_SYS_BCSR5_PCI66EN
+CONFIG_SYS_BCSR_ADDR
+CONFIG_SYS_BCSR_BASE
+CONFIG_SYS_BCSR_BASE_PHYS
+CONFIG_SYS_BCSR_SIZE
+CONFIG_SYS_BD_INFO_ADDR
+CONFIG_SYS_BD_REV
+CONFIG_SYS_BFTIC3_BASE
+CONFIG_SYS_BFTIC3_SIZE
+CONFIG_SYS_BITBANG_PHY_PORT
+CONFIG_SYS_BITBANG_PHY_PORTS
+CONFIG_SYS_BLACK_IN_WRITE
+CONFIG_SYS_BMAN_CENA_BASE
+CONFIG_SYS_BMAN_CENA_SIZE
+CONFIG_SYS_BMAN_CINH_BASE
+CONFIG_SYS_BMAN_CINH_SIZE
+CONFIG_SYS_BMAN_MEM_BASE
+CONFIG_SYS_BMAN_MEM_PHYS
+CONFIG_SYS_BMAN_MEM_SIZE
+CONFIG_SYS_BMAN_NUM_PORTALS
+CONFIG_SYS_BMAN_SP_CENA_SIZE
+CONFIG_SYS_BMAN_SP_CINH_SIZE
+CONFIG_SYS_BMAN_SWP_ISDR_REG
+CONFIG_SYS_BOARD_NAME
+CONFIG_SYS_BOARD_OMAP3_HA
+CONFIG_SYS_BOARD_VERSION
+CONFIG_SYS_BOOK3E_HV
+CONFIG_SYS_BOOTCOUNT_ADDR
+CONFIG_SYS_BOOTCOUNT_BE
+CONFIG_SYS_BOOTCOUNT_LE
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD
+CONFIG_SYS_BOOTCS_CFG
+CONFIG_SYS_BOOTCS_SIZE
+CONFIG_SYS_BOOTCS_START
+CONFIG_SYS_BOOTFILE
+CONFIG_SYS_BOOTFILE_PREFIX
+CONFIG_SYS_BOOTMAPSZ
+CONFIG_SYS_BOOTM_LEN
+CONFIG_SYS_BOOTPARAMS_LEN
+CONFIG_SYS_BOOTSZ
+CONFIG_SYS_BOOT_BASE_ADDR
+CONFIG_SYS_BOOT_BLOCK
+CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS
+CONFIG_SYS_BOOT_GET_CMDLINE
+CONFIG_SYS_BOOT_GET_KBD
+CONFIG_SYS_BOOT_RAMDISK_HIGH
+CONFIG_SYS_BOOT_SPINOR
+CONFIG_SYS_BR0_64M
+CONFIG_SYS_BR0_8M
+CONFIG_SYS_BR0_PRELIM
+CONFIG_SYS_BR10_PRELIM
+CONFIG_SYS_BR11_PRELIM
+CONFIG_SYS_BR1_PRELIM
+CONFIG_SYS_BR2_PRELIM
+CONFIG_SYS_BR3_CAN
+CONFIG_SYS_BR3_PRELIM
+CONFIG_SYS_BR4_PRELIM
+CONFIG_SYS_BR5_ISP1362
+CONFIG_SYS_BR5_PRELIM
+CONFIG_SYS_BR6_64M
+CONFIG_SYS_BR6_8M
+CONFIG_SYS_BR6_PRELIM
+CONFIG_SYS_BR7_PRELIM
+CONFIG_SYS_BR8_PRELIM
+CONFIG_SYS_BR9_PRELIM
+CONFIG_SYS_BRGCLK_PRESCALE
+CONFIG_SYS_BRIGHTNESS
+CONFIG_SYS_BUSCLK
+CONFIG_SYS_CACHELINE_SHIFT
+CONFIG_SYS_CACHE_ACR0
+CONFIG_SYS_CACHE_ACR1
+CONFIG_SYS_CACHE_ACR2
+CONFIG_SYS_CACHE_ACR3
+CONFIG_SYS_CACHE_ACR4
+CONFIG_SYS_CACHE_ACR5
+CONFIG_SYS_CACHE_ACR6
+CONFIG_SYS_CACHE_ACR7
+CONFIG_SYS_CACHE_DCACR
+CONFIG_SYS_CACHE_ICACR
+CONFIG_SYS_CACHE_STASHING
+CONFIG_SYS_CADMUS_BASE_REG
+CONFIG_SYS_CAN_BASE
+CONFIG_SYS_CAN_OR_AM
+CONFIG_SYS_CBSIZE
+CONFIG_SYS_CCCR
+CONFIG_SYS_CCI400_ADDR
+CONFIG_SYS_CCSRBAR
+CONFIG_SYS_CCSRBAR_PHYS
+CONFIG_SYS_CCSRBAR_PHYS_HIGH
+CONFIG_SYS_CCSRBAR_PHYS_LOW
+CONFIG_SYS_CCSR_DEFAULT_DBATL
+CONFIG_SYS_CCSR_DEFAULT_DBATU
+CONFIG_SYS_CCSR_DEFAULT_IBATL
+CONFIG_SYS_CCSR_DEFAULT_IBATU
+CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+CONFIG_SYS_CFI_FLASH_CONFIG_REGS
+CONFIG_SYS_CFI_FLASH_STATUS_POLL
+CONFIG_SYS_CF_BASE
+CONFIG_SYS_CF_INTC_REG1
+CONFIG_SYS_CF_SIZE
+CONFIG_SYS_CH7301_I2C
+CONFIG_SYS_CKEN
+CONFIG_SYS_CLK
+CONFIG_SYS_CLKDIV_CPU
+CONFIG_SYS_CLKDIV_HSB
+CONFIG_SYS_CLKDIV_PBA
+CONFIG_SYS_CLKDIV_PBB
+CONFIG_SYS_CLKTL_CBCDR
+CONFIG_SYS_CLK_100
+CONFIG_SYS_CLK_100_DDR_100
+CONFIG_SYS_CLK_100_DDR_133
+CONFIG_SYS_CLK_DIV
+CONFIG_SYS_CLK_FREQ_C100
+CONFIG_SYS_CLK_FREQ_C110
+CONFIG_SYS_CMD_CONFIGURE
+CONFIG_SYS_CMD_EL
+CONFIG_SYS_CMD_IAS
+CONFIG_SYS_CMD_INT
+CONFIG_SYS_CMD_SUSPEND
+CONFIG_SYS_CMXFCR_MASK1
+CONFIG_SYS_CMXFCR_MASK2
+CONFIG_SYS_CMXFCR_MASK3
+CONFIG_SYS_CMXFCR_VALUE1
+CONFIG_SYS_CMXFCR_VALUE2
+CONFIG_SYS_CMXFCR_VALUE3
+CONFIG_SYS_CMXSCR_VALUE
+CONFIG_SYS_CORE_SRAM
+CONFIG_SYS_CORE_SRAM_SIZE
+CONFIG_SYS_CORTEX_R4
+CONFIG_SYS_CORTINA_FW_IN_MMC
+CONFIG_SYS_CORTINA_FW_IN_NAND
+CONFIG_SYS_CORTINA_FW_IN_NOR
+CONFIG_SYS_CORTINA_FW_IN_REMOTE
+CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
+CONFIG_SYS_CPC_REINIT_F
+CONFIG_SYS_CPLD
+CONFIG_SYS_CPLD_ADDR
+CONFIG_SYS_CPLD_AMASK
+CONFIG_SYS_CPLD_BASE
+CONFIG_SYS_CPLD_BASE_PHYS
+CONFIG_SYS_CPLD_CSOR
+CONFIG_SYS_CPLD_CSPR
+CONFIG_SYS_CPLD_CSPR_EXT
+CONFIG_SYS_CPLD_DATA
+CONFIG_SYS_CPLD_FTIM0
+CONFIG_SYS_CPLD_FTIM1
+CONFIG_SYS_CPLD_FTIM2
+CONFIG_SYS_CPLD_FTIM3
+CONFIG_SYS_CPLD_SIZE
+CONFIG_SYS_CPMFCR_RAMTYPE
+CONFIG_SYS_CPM_BOOTCOUNT_ADDR
+CONFIG_SYS_CPM_INTERRUPT
+CONFIG_SYS_CPM_POST_WORD_ADDR
+CONFIG_SYS_CPRI
+CONFIG_SYS_CPRI_CLK
+CONFIG_SYS_CPUSPEED
+CONFIG_SYS_CPU_CLK
+CONFIG_SYS_CPU_PCI_IO_START
+CONFIG_SYS_CPU_PCI_MEMIO_START
+CONFIG_SYS_CPU_PCI_MEM_START
+CONFIG_SYS_CS0_BASE
+CONFIG_SYS_CS0_CFG
+CONFIG_SYS_CS0_CTRL
+CONFIG_SYS_CS0_FTIM0
+CONFIG_SYS_CS0_FTIM1
+CONFIG_SYS_CS0_FTIM2
+CONFIG_SYS_CS0_FTIM3
+CONFIG_SYS_CS0_MASK
+CONFIG_SYS_CS0_SIZE
+CONFIG_SYS_CS0_START
+CONFIG_SYS_CS1_BASE
+CONFIG_SYS_CS1_CFG
+CONFIG_SYS_CS1_CTRL
+CONFIG_SYS_CS1_FLASH_BASE
+CONFIG_SYS_CS1_FTIM0
+CONFIG_SYS_CS1_FTIM1
+CONFIG_SYS_CS1_FTIM2
+CONFIG_SYS_CS1_FTIM3
+CONFIG_SYS_CS1_MASK
+CONFIG_SYS_CS1_SIZE
+CONFIG_SYS_CS1_START
+CONFIG_SYS_CS2_BASE
+CONFIG_SYS_CS2_CFG
+CONFIG_SYS_CS2_CTRL
+CONFIG_SYS_CS2_FLASH_BASE
+CONFIG_SYS_CS2_FTIM0
+CONFIG_SYS_CS2_FTIM1
+CONFIG_SYS_CS2_FTIM2
+CONFIG_SYS_CS2_FTIM3
+CONFIG_SYS_CS2_MASK
+CONFIG_SYS_CS2_SIZE
+CONFIG_SYS_CS2_START
+CONFIG_SYS_CS3_BASE
+CONFIG_SYS_CS3_CFG
+CONFIG_SYS_CS3_CTRL
+CONFIG_SYS_CS3_FLASH_BASE
+CONFIG_SYS_CS3_FTIM0
+CONFIG_SYS_CS3_FTIM1
+CONFIG_SYS_CS3_FTIM2
+CONFIG_SYS_CS3_FTIM3
+CONFIG_SYS_CS3_MASK
+CONFIG_SYS_CS3_SIZE
+CONFIG_SYS_CS3_START
+CONFIG_SYS_CS4_BASE
+CONFIG_SYS_CS4_CFG
+CONFIG_SYS_CS4_CTRL
+CONFIG_SYS_CS4_FLASH_BASE
+CONFIG_SYS_CS4_FTIM0
+CONFIG_SYS_CS4_FTIM1
+CONFIG_SYS_CS4_FTIM2
+CONFIG_SYS_CS4_FTIM3
+CONFIG_SYS_CS4_MASK
+CONFIG_SYS_CS4_SIZE
+CONFIG_SYS_CS4_START
+CONFIG_SYS_CS5_BASE
+CONFIG_SYS_CS5_CFG
+CONFIG_SYS_CS5_CTRL
+CONFIG_SYS_CS5_FLASH_BASE
+CONFIG_SYS_CS5_FTIM0
+CONFIG_SYS_CS5_FTIM1
+CONFIG_SYS_CS5_FTIM2
+CONFIG_SYS_CS5_FTIM3
+CONFIG_SYS_CS5_MASK
+CONFIG_SYS_CS5_SIZE
+CONFIG_SYS_CS5_START
+CONFIG_SYS_CS6_BASE
+CONFIG_SYS_CS6_CFG
+CONFIG_SYS_CS6_CTRL
+CONFIG_SYS_CS6_FTIM0
+CONFIG_SYS_CS6_FTIM1
+CONFIG_SYS_CS6_FTIM2
+CONFIG_SYS_CS6_FTIM3
+CONFIG_SYS_CS6_MASK
+CONFIG_SYS_CS6_SIZE
+CONFIG_SYS_CS6_START
+CONFIG_SYS_CS7_BASE
+CONFIG_SYS_CS7_CFG
+CONFIG_SYS_CS7_CTRL
+CONFIG_SYS_CS7_FTIM0
+CONFIG_SYS_CS7_FTIM1
+CONFIG_SYS_CS7_FTIM2
+CONFIG_SYS_CS7_FTIM3
+CONFIG_SYS_CS7_MASK
+CONFIG_SYS_CS7_SIZE
+CONFIG_SYS_CS7_START
+CONFIG_SYS_CSOR0
+CONFIG_SYS_CSOR0_EXT
+CONFIG_SYS_CSOR1
+CONFIG_SYS_CSOR1_EXT
+CONFIG_SYS_CSOR2
+CONFIG_SYS_CSOR2_EXT
+CONFIG_SYS_CSOR3
+CONFIG_SYS_CSOR3_EXT
+CONFIG_SYS_CSOR4
+CONFIG_SYS_CSOR4_EXT
+CONFIG_SYS_CSOR5
+CONFIG_SYS_CSOR5_EXT
+CONFIG_SYS_CSOR6
+CONFIG_SYS_CSOR6_EXT
+CONFIG_SYS_CSOR7
+CONFIG_SYS_CSOR7_EXT
+CONFIG_SYS_CSPR0
+CONFIG_SYS_CSPR0_EXT
+CONFIG_SYS_CSPR0_FINAL
+CONFIG_SYS_CSPR1
+CONFIG_SYS_CSPR1_EXT
+CONFIG_SYS_CSPR1_FINAL
+CONFIG_SYS_CSPR2
+CONFIG_SYS_CSPR2_EXT
+CONFIG_SYS_CSPR2_FINAL
+CONFIG_SYS_CSPR3
+CONFIG_SYS_CSPR3_EXT
+CONFIG_SYS_CSPR3_FINAL
+CONFIG_SYS_CSPR4
+CONFIG_SYS_CSPR4_EXT
+CONFIG_SYS_CSPR5
+CONFIG_SYS_CSPR5_EXT
+CONFIG_SYS_CSPR6
+CONFIG_SYS_CSPR6_EXT
+CONFIG_SYS_CSPR7
+CONFIG_SYS_CSPR7_EXT
+CONFIG_SYS_CS_ALETIMING
+CONFIG_SYS_CS_BURST
+CONFIG_SYS_CS_DEADCYCLE
+CONFIG_SYS_CS_HOLDCYCLE
+CONFIG_SYS_DA850_CS2CFG
+CONFIG_SYS_DA850_CS3CFG
+CONFIG_SYS_DA850_DDR2_DDRPHYCR
+CONFIG_SYS_DA850_DDR2_PBBPR
+CONFIG_SYS_DA850_DDR2_SDBCR
+CONFIG_SYS_DA850_DDR2_SDBCR2
+CONFIG_SYS_DA850_DDR2_SDRCR
+CONFIG_SYS_DA850_DDR2_SDTIMR
+CONFIG_SYS_DA850_DDR2_SDTIMR2
+CONFIG_SYS_DA850_PLL0_PLLDIV1
+CONFIG_SYS_DA850_PLL0_PLLDIV2
+CONFIG_SYS_DA850_PLL0_PLLDIV3
+CONFIG_SYS_DA850_PLL0_PLLDIV4
+CONFIG_SYS_DA850_PLL0_PLLDIV5
+CONFIG_SYS_DA850_PLL0_PLLDIV6
+CONFIG_SYS_DA850_PLL0_PLLDIV7
+CONFIG_SYS_DA850_PLL0_PLLM
+CONFIG_SYS_DA850_PLL0_POSTDIV
+CONFIG_SYS_DA850_PLL0_PREDIV
+CONFIG_SYS_DA850_PLL1_PLLDIV1
+CONFIG_SYS_DA850_PLL1_PLLDIV2
+CONFIG_SYS_DA850_PLL1_PLLDIV3
+CONFIG_SYS_DA850_PLL1_PLLM
+CONFIG_SYS_DA850_PLL1_POSTDIV
+CONFIG_SYS_DA850_SYSCFG_SUSPSRC
+CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0
+CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
+CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
+CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
+CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
+CONFIG_SYS_DAVINCI_I2C_SLAVE
+CONFIG_SYS_DAVINCI_I2C_SLAVE1
+CONFIG_SYS_DAVINCI_I2C_SLAVE2
+CONFIG_SYS_DAVINCI_I2C_SPEED
+CONFIG_SYS_DAVINCI_I2C_SPEED1
+CONFIG_SYS_DAVINCI_I2C_SPEED2
+CONFIG_SYS_DBAT
+CONFIG_SYS_DBAT0L
+CONFIG_SYS_DBAT0U
+CONFIG_SYS_DBAT1L
+CONFIG_SYS_DBAT1U
+CONFIG_SYS_DBAT2L
+CONFIG_SYS_DBAT2U
+CONFIG_SYS_DBAT3L
+CONFIG_SYS_DBAT3U
+CONFIG_SYS_DBAT4L
+CONFIG_SYS_DBAT4U
+CONFIG_SYS_DBAT5L
+CONFIG_SYS_DBAT5U
+CONFIG_SYS_DBAT6L
+CONFIG_SYS_DBAT6L_EARLY
+CONFIG_SYS_DBAT6U
+CONFIG_SYS_DBAT6U_EARLY
+CONFIG_SYS_DBAT7L
+CONFIG_SYS_DBAT7U
+CONFIG_SYS_DCACHE_INV
+CONFIG_SYS_DCACHE_LINESZ
+CONFIG_SYS_DCACHE_SACR_VALUE
+CONFIG_SYS_DCSRBAR
+CONFIG_SYS_DCSRBAR_PHYS
+CONFIG_SYS_DCSR_COP_CCP_ADDR
+CONFIG_SYS_DCSR_DCFG_ADDR
+CONFIG_SYS_DCSR_DCFG_OFFSET
+CONFIG_SYS_DCU_ADDR
+CONFIG_SYS_DDR1_CS0_BNDS
+CONFIG_SYS_DDR2_CFG_1A
+CONFIG_SYS_DDR2_CFG_1B
+CONFIG_SYS_DDR2_CFG_2
+CONFIG_SYS_DDR2_CLK_CTRL
+CONFIG_SYS_DDR2_CS0_BNDS
+CONFIG_SYS_DDR2_CS0_CONFIG
+CONFIG_SYS_DDR2_CS1_BNDS
+CONFIG_SYS_DDR2_CS1_CONFIG
+CONFIG_SYS_DDR2_CS2_BNDS
+CONFIG_SYS_DDR2_CS2_CONFIG
+CONFIG_SYS_DDR2_CS3_BNDS
+CONFIG_SYS_DDR2_CS3_CONFIG
+CONFIG_SYS_DDR2_DATA_INIT
+CONFIG_SYS_DDR2_EXT_REFRESH
+CONFIG_SYS_DDR2_INTERVAL
+CONFIG_SYS_DDR2_MODE_1
+CONFIG_SYS_DDR2_MODE_2
+CONFIG_SYS_DDR2_MODE_CTL
+CONFIG_SYS_DDR2_TIMING_0
+CONFIG_SYS_DDR2_TIMING_1
+CONFIG_SYS_DDR2_TIMING_2
+CONFIG_SYS_DDRCDR
+CONFIG_SYS_DDRCDR_VALUE
+CONFIG_SYS_DDRCMD_EM2
+CONFIG_SYS_DDRCMD_EM3
+CONFIG_SYS_DDRCMD_EN_DLL
+CONFIG_SYS_DDRCMD_NOP
+CONFIG_SYS_DDRCMD_OCD_DEFAULT
+CONFIG_SYS_DDRCMD_OCD_EXIT
+CONFIG_SYS_DDRCMD_PCHG_ALL
+CONFIG_SYS_DDRCMD_RES_DLL
+CONFIG_SYS_DDRCMD_RFSH
+CONFIG_SYS_DDRD
+CONFIG_SYS_DDRTC
+CONFIG_SYS_DDRUA
+CONFIG_SYS_DDR_BASE
+CONFIG_SYS_DDR_BLOCK1_SIZE
+CONFIG_SYS_DDR_BLOCK2_BASE
+CONFIG_SYS_DDR_CACHED_ADDR
+CONFIG_SYS_DDR_CDR_1
+CONFIG_SYS_DDR_CDR_2
+CONFIG_SYS_DDR_CFG_1A
+CONFIG_SYS_DDR_CFG_1B
+CONFIG_SYS_DDR_CFG_2
+CONFIG_SYS_DDR_CLKSEL
+CONFIG_SYS_DDR_CLK_CNTL
+CONFIG_SYS_DDR_CLK_CONTROL
+CONFIG_SYS_DDR_CLK_CTRL
+CONFIG_SYS_DDR_CLK_CTRL_1000
+CONFIG_SYS_DDR_CLK_CTRL_1200
+CONFIG_SYS_DDR_CLK_CTRL_1333
+CONFIG_SYS_DDR_CLK_CTRL_667
+CONFIG_SYS_DDR_CLK_CTRL_800
+CONFIG_SYS_DDR_CLK_CTRL_900
+CONFIG_SYS_DDR_CONFIG
+CONFIG_SYS_DDR_CONFIG_2
+CONFIG_SYS_DDR_CONFIG_256
+CONFIG_SYS_DDR_CONTROL
+CONFIG_SYS_DDR_CONTROL2
+CONFIG_SYS_DDR_CONTROL_1333
+CONFIG_SYS_DDR_CONTROL_2
+CONFIG_SYS_DDR_CONTROL_2_1333
+CONFIG_SYS_DDR_CONTROL_2_800
+CONFIG_SYS_DDR_CONTROL_800
+CONFIG_SYS_DDR_CPO
+CONFIG_SYS_DDR_CS0_BNDS
+CONFIG_SYS_DDR_CS0_CONFIG
+CONFIG_SYS_DDR_CS0_CONFIG_1333
+CONFIG_SYS_DDR_CS0_CONFIG_2
+CONFIG_SYS_DDR_CS0_CONFIG_800
+CONFIG_SYS_DDR_CS1_BNDS
+CONFIG_SYS_DDR_CS1_CONFIG
+CONFIG_SYS_DDR_CS1_CONFIG_2
+CONFIG_SYS_DDR_CS2_BNDS
+CONFIG_SYS_DDR_CS2_CONFIG
+CONFIG_SYS_DDR_CS3_BNDS
+CONFIG_SYS_DDR_CS3_CONFIG
+CONFIG_SYS_DDR_DATA_INIT
+CONFIG_SYS_DDR_ERR_DIS
+CONFIG_SYS_DDR_ERR_INT_EN
+CONFIG_SYS_DDR_INIT_ADDR
+CONFIG_SYS_DDR_INIT_EXT_ADDR
+CONFIG_SYS_DDR_INTERVAL
+CONFIG_SYS_DDR_INTERVAL_1000
+CONFIG_SYS_DDR_INTERVAL_1200
+CONFIG_SYS_DDR_INTERVAL_1333
+CONFIG_SYS_DDR_INTERVAL_667
+CONFIG_SYS_DDR_INTERVAL_800
+CONFIG_SYS_DDR_INTERVAL_900
+CONFIG_SYS_DDR_MODE
+CONFIG_SYS_DDR_MODE2
+CONFIG_SYS_DDR_MODE_1
+CONFIG_SYS_DDR_MODE_1_1000
+CONFIG_SYS_DDR_MODE_1_1200
+CONFIG_SYS_DDR_MODE_1_1333
+CONFIG_SYS_DDR_MODE_1_667
+CONFIG_SYS_DDR_MODE_1_800
+CONFIG_SYS_DDR_MODE_1_900
+CONFIG_SYS_DDR_MODE_2
+CONFIG_SYS_DDR_MODE_2_1000
+CONFIG_SYS_DDR_MODE_2_1200
+CONFIG_SYS_DDR_MODE_2_1333
+CONFIG_SYS_DDR_MODE_2_667
+CONFIG_SYS_DDR_MODE_2_800
+CONFIG_SYS_DDR_MODE_2_900
+CONFIG_SYS_DDR_MODE_CONTROL
+CONFIG_SYS_DDR_MODE_CTL
+CONFIG_SYS_DDR_MODE_WEAK
+CONFIG_SYS_DDR_OCD_CTRL
+CONFIG_SYS_DDR_OCD_STATUS
+CONFIG_SYS_DDR_RAW_TIMING
+CONFIG_SYS_DDR_RCW_1
+CONFIG_SYS_DDR_RCW_2
+CONFIG_SYS_DDR_SBE
+CONFIG_SYS_DDR_SDRAM_BASE
+CONFIG_SYS_DDR_SDRAM_BASE2
+CONFIG_SYS_DDR_SDRAM_CFG
+CONFIG_SYS_DDR_SDRAM_CFG2
+CONFIG_SYS_DDR_SDRAM_CFG_2
+CONFIG_SYS_DDR_SDRAM_CLK_CNTL
+CONFIG_SYS_DDR_SDRAM_INTERVAL
+CONFIG_SYS_DDR_SDRAM_MODE
+CONFIG_SYS_DDR_SDRAM_MODE_2
+CONFIG_SYS_DDR_SIZE
+CONFIG_SYS_DDR_SR_CNTR
+CONFIG_SYS_DDR_TIMING_0
+CONFIG_SYS_DDR_TIMING_0_1000
+CONFIG_SYS_DDR_TIMING_0_1200
+CONFIG_SYS_DDR_TIMING_0_1333
+CONFIG_SYS_DDR_TIMING_0_667
+CONFIG_SYS_DDR_TIMING_0_800
+CONFIG_SYS_DDR_TIMING_0_900
+CONFIG_SYS_DDR_TIMING_1
+CONFIG_SYS_DDR_TIMING_1_1000
+CONFIG_SYS_DDR_TIMING_1_1200
+CONFIG_SYS_DDR_TIMING_1_1333
+CONFIG_SYS_DDR_TIMING_1_667
+CONFIG_SYS_DDR_TIMING_1_800
+CONFIG_SYS_DDR_TIMING_1_900
+CONFIG_SYS_DDR_TIMING_2
+CONFIG_SYS_DDR_TIMING_2_1000
+CONFIG_SYS_DDR_TIMING_2_1200
+CONFIG_SYS_DDR_TIMING_2_1333
+CONFIG_SYS_DDR_TIMING_2_667
+CONFIG_SYS_DDR_TIMING_2_800
+CONFIG_SYS_DDR_TIMING_2_900
+CONFIG_SYS_DDR_TIMING_3
+CONFIG_SYS_DDR_TIMING_3_1000
+CONFIG_SYS_DDR_TIMING_3_1200
+CONFIG_SYS_DDR_TIMING_3_1333
+CONFIG_SYS_DDR_TIMING_3_667
+CONFIG_SYS_DDR_TIMING_3_800
+CONFIG_SYS_DDR_TIMING_3_900
+CONFIG_SYS_DDR_TIMING_4
+CONFIG_SYS_DDR_TIMING_4_1333
+CONFIG_SYS_DDR_TIMING_4_800
+CONFIG_SYS_DDR_TIMING_5
+CONFIG_SYS_DDR_TIMING_5_1333
+CONFIG_SYS_DDR_TIMING_5_800
+CONFIG_SYS_DDR_WRITE_DATA_DELAY
+CONFIG_SYS_DDR_WRLVL_CNTL
+CONFIG_SYS_DDR_WRLVL_CONTROL
+CONFIG_SYS_DDR_WRLVL_CONTROL_1333
+CONFIG_SYS_DDR_WRLVL_CONTROL_667
+CONFIG_SYS_DDR_WRLVL_CONTROL_800
+CONFIG_SYS_DDR_ZQ_CNTL
+CONFIG_SYS_DDR_ZQ_CONTROL
+CONFIG_SYS_DEBUG
+CONFIG_SYS_DEBUG_SERVER_FW_ADDR
+CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+CONFIG_SYS_DECREMENT_PATTERNS
+CONFIG_SYS_DEFAULT_IMMR
+CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+CONFIG_SYS_DEFAULT_MBAR
+CONFIG_SYS_DEFAULT_VIDEO_MODE
+CONFIG_SYS_DEF_EEPROM_ADDR
+CONFIG_SYS_DELAYED_ICACHE
+CONFIG_SYS_DER
+CONFIG_SYS_DEVICE_NULLDEV
+CONFIG_SYS_DFU_DATA_BUF_SIZE
+CONFIG_SYS_DFU_MAX_FILE_SIZE
+CONFIG_SYS_DIAG_ADDR
+CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
+CONFIG_SYS_DIMM_SLOTS_PER_CTLR
+CONFIG_SYS_DIRECT_FLASH_NFS
+CONFIG_SYS_DIRECT_FLASH_TFTP
+CONFIG_SYS_DISCOVER_PHY
+CONFIG_SYS_DISPLAY_BASE
+CONFIG_SYS_DISP_CHR_RAM
+CONFIG_SYS_DIU_ADDR
+CONFIG_SYS_DM36x_PINMUX0
+CONFIG_SYS_DM36x_PINMUX1
+CONFIG_SYS_DM36x_PINMUX2
+CONFIG_SYS_DM36x_PINMUX3
+CONFIG_SYS_DM36x_PINMUX4
+CONFIG_SYS_DM36x_PLL1_PREDIV
+CONFIG_SYS_DM36x_PLL2_PREDIV
+CONFIG_SYS_DMA_USE_INTSRAM
+CONFIG_SYS_DOC_SHORT_TIMEOUT
+CONFIG_SYS_DOC_SUPPORT_2000
+CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
+CONFIG_SYS_DP501_BASE
+CONFIG_SYS_DP501_DIFFERENTIAL
+CONFIG_SYS_DP501_I2C
+CONFIG_SYS_DP501_VCAPCTRL0
+CONFIG_SYS_DPAA_DCE
+CONFIG_SYS_DPAA_FMAN
+CONFIG_SYS_DPAA_PME
+CONFIG_SYS_DPAA_QBMAN
+CONFIG_SYS_DPAA_RMAN
+CONFIG_SYS_DP_DDR_BASE
+CONFIG_SYS_DP_DDR_BASE_PHY
+CONFIG_SYS_DRAMSZ
+CONFIG_SYS_DRAMSZ1
+CONFIG_SYS_DRAM_BASE
+CONFIG_SYS_DRAM_SIZE
+CONFIG_SYS_DRAM_TEST
+CONFIG_SYS_DS1339_TCR_VAL
+CONFIG_SYS_DS1388_TCR_VAL
+CONFIG_SYS_DSPIC_TEST_ADDR
+CONFIG_SYS_DSPIC_TEST_MASK
+CONFIG_SYS_DSPI_CS0
+CONFIG_SYS_DSPI_CS2
+CONFIG_SYS_DSPI_CTAR0
+CONFIG_SYS_DSPI_CTAR1
+CONFIG_SYS_DSPI_CTAR2
+CONFIG_SYS_DSPI_CTAR3
+CONFIG_SYS_DSPI_CTAR4
+CONFIG_SYS_DSPI_CTAR5
+CONFIG_SYS_DSPI_CTAR6
+CONFIG_SYS_DSPI_CTAR7
+CONFIG_SYS_DTT_ADM1021
+CONFIG_SYS_DTT_BUS_NUM
+CONFIG_SYS_DTT_HYSTERESIS
+CONFIG_SYS_DTT_LOW_TEMP
+CONFIG_SYS_DTT_MAX_TEMP
+CONFIG_SYS_DTT_MIN_TEMP
+CONFIG_SYS_DUART_RST
+CONFIG_SYS_DV_CLKMODE
+CONFIG_SYS_DV_NOR_BOOT_CFG
+CONFIG_SYS_EBC_CFG
+CONFIG_SYS_EBC_PB0AP
+CONFIG_SYS_EBC_PB0CR
+CONFIG_SYS_EBC_PB1AP
+CONFIG_SYS_EBC_PB1CR
+CONFIG_SYS_EBC_PB2AP
+CONFIG_SYS_EBC_PB2CR
+CONFIG_SYS_EBC_PB3AP
+CONFIG_SYS_EBC_PB3CR
+CONFIG_SYS_EBC_PB4AP
+CONFIG_SYS_EBC_PB4CR
+CONFIG_SYS_EBC_PB5AP
+CONFIG_SYS_EBC_PB5CR
+CONFIG_SYS_EBC_PB6AP
+CONFIG_SYS_EBC_PB6CR
+CONFIG_SYS_EBC_PB7AP
+CONFIG_SYS_EBC_PB7CR
+CONFIG_SYS_EBI_CFGR_VAL
+CONFIG_SYS_EBI_CSA_VAL
+CONFIG_SYS_EEPROM_BASE
+CONFIG_SYS_EEPROM_BUS_NUM
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
+CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+CONFIG_SYS_EEPROM_SIZE
+CONFIG_SYS_EEPROM_WP
+CONFIG_SYS_EEPROM_WREN
+CONFIG_SYS_EHCI_USB1_ADDR
+CONFIG_SYS_ELBC_BASE
+CONFIG_SYS_ELBC_BASE_PHYS
+CONFIG_SYS_ELO3_DMA3
+CONFIG_SYS_ELPIDA_INIT_DEV_OP
+CONFIG_SYS_ELPIDA_OCD_EXIT
+CONFIG_SYS_ELPIDA_RES_DLL
+CONFIG_SYS_EMAC_TI_CLKDIV
+CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+CONFIG_SYS_ENABLE_PADS_ALL
+CONFIG_SYS_ENET_BD_BASE
+CONFIG_SYS_ENV_ADDR
+CONFIG_SYS_ENV_OFFSET
+CONFIG_SYS_ENV_SECT_SIZE
+CONFIG_SYS_EPLD_BASE
+CONFIG_SYS_ETHOC_BASE
+CONFIG_SYS_ETHOC_BUFFER_ADDR
+CONFIG_SYS_ETH_IOBASE
+CONFIG_SYS_ETVPE_CLK
+CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+CONFIG_SYS_EXTBDINFO
+CONFIG_SYS_EXTRA_ENV_RELOC
+CONFIG_SYS_EXT_SERIAL_CLOCK
+CONFIG_SYS_FAST_CLK
+CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+CONFIG_SYS_FAULT_MII_ADDR
+CONFIG_SYS_FCC_PSMR
+CONFIG_SYS_FCPU133MHZ
+CONFIG_SYS_FCPU266MHZ
+CONFIG_SYS_FCPU333MHZ
+CONFIG_SYS_FDC_DRIVE_NUMBER
+CONFIG_SYS_FDC_HW_INIT
+CONFIG_SYS_FDT_ADDR
+CONFIG_SYS_FDT_BASE
+CONFIG_SYS_FDT_LOAD_ADDR
+CONFIG_SYS_FDT_PAD
+CONFIG_SYS_FDT_SIZE
+CONFIG_SYS_FEC0_IOBASE
+CONFIG_SYS_FEC0_MIIBASE
+CONFIG_SYS_FEC0_PHYADDR
+CONFIG_SYS_FEC0_PINMUX
+CONFIG_SYS_FEC1_IOBASE
+CONFIG_SYS_FEC1_MIIBASE
+CONFIG_SYS_FEC1_PHYADDR
+CONFIG_SYS_FEC1_PINMUX
+CONFIG_SYS_FECI2C
+CONFIG_SYS_FEC_BUF_USE_SRAM
+CONFIG_SYS_FEC_FULL_MII
+CONFIG_SYS_FEC_NO_SHARED_PHY
+CONFIG_SYS_FIFO_BASE
+CONFIG_SYS_FIXED_PHY_ADDR
+CONFIG_SYS_FIXED_PHY_PORT
+CONFIG_SYS_FIXED_PHY_PORTS
+CONFIG_SYS_FLASH
+CONFIG_SYS_FLASH0
+CONFIG_SYS_FLASH0_BASE
+CONFIG_SYS_FLASH1
+CONFIG_SYS_FLASH1_BASE
+CONFIG_SYS_FLASH1_BASE_PHYS
+CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
+CONFIG_SYS_FLASH2_BASE
+CONFIG_SYS_FLASHBOOT
+CONFIG_SYS_FLASH_2ND_16BIT_DEV
+CONFIG_SYS_FLASH_2ND_ADDR
+CONFIG_SYS_FLASH_ADDR0
+CONFIG_SYS_FLASH_ADDR1
+CONFIG_SYS_FLASH_ADDR_BASE
+CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+CONFIG_SYS_FLASH_AUTOPROTECT_LIST
+CONFIG_SYS_FLASH_BANKS_LIST
+CONFIG_SYS_FLASH_BANKS_SIZES
+CONFIG_SYS_FLASH_BANK_SIZE
+CONFIG_SYS_FLASH_BASE
+CONFIG_SYS_FLASH_BASE0
+CONFIG_SYS_FLASH_BASE1
+CONFIG_SYS_FLASH_BASE2
+CONFIG_SYS_FLASH_BASE_1
+CONFIG_SYS_FLASH_BASE_2
+CONFIG_SYS_FLASH_BASE_CS1
+CONFIG_SYS_FLASH_BASE_PHYS
+CONFIG_SYS_FLASH_BASE_PHYS_EARLY
+CONFIG_SYS_FLASH_BASE_PHYS_H
+CONFIG_SYS_FLASH_BASE_PHYS_L
+CONFIG_SYS_FLASH_BASE_PHYS_LOW
+CONFIG_SYS_FLASH_BR_PRELIM
+CONFIG_SYS_FLASH_CFI
+CONFIG_SYS_FLASH_CFI_AMD_RESET
+CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
+CONFIG_SYS_FLASH_CFI_BYPASS_READ
+CONFIG_SYS_FLASH_CFI_NONBLOCK
+CONFIG_SYS_FLASH_CFI_WIDTH
+CONFIG_SYS_FLASH_CHECKSUM
+CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE
+CONFIG_SYS_FLASH_EMPTY_INFO
+CONFIG_SYS_FLASH_ERASE_TOUT
+CONFIG_SYS_FLASH_LEGACY_256Kx8
+CONFIG_SYS_FLASH_LEGACY_512Kx16
+CONFIG_SYS_FLASH_LEGACY_512Kx8
+CONFIG_SYS_FLASH_LOCK_TOUT
+CONFIG_SYS_FLASH_OR_PRELIM
+CONFIG_SYS_FLASH_PARMSECT_SZ
+CONFIG_SYS_FLASH_PROTECTION
+CONFIG_SYS_FLASH_QUIET_TEST
+CONFIG_SYS_FLASH_READ0
+CONFIG_SYS_FLASH_READ1
+CONFIG_SYS_FLASH_READ2
+CONFIG_SYS_FLASH_SECT_SIZE
+CONFIG_SYS_FLASH_SECT_SZ
+CONFIG_SYS_FLASH_SIZE
+CONFIG_SYS_FLASH_SIZE_1
+CONFIG_SYS_FLASH_SIZE_2
+CONFIG_SYS_FLASH_UNLOCK_TOUT
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE
+CONFIG_SYS_FLASH_WORD_SIZE
+CONFIG_SYS_FLASH_WRITE_TOUT
+CONFIG_SYS_FLYCNFG_VAL
+CONFIG_SYS_FM1_10GEC1_PHY_ADDR
+CONFIG_SYS_FM1_10GEC2_PHY_ADDR
+CONFIG_SYS_FM1_CLK
+CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR
+CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
+CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+CONFIG_SYS_FM1_DTSEC2_PHY_ADDR
+CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR
+CONFIG_SYS_FM1_DTSEC3_PHY_ADDR
+CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR
+CONFIG_SYS_FM1_DTSEC4_PHY_ADDR
+CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR
+CONFIG_SYS_FM1_DTSEC5_PHY_ADDR
+CONFIG_SYS_FM1_DTSEC_MDIO_ADDR
+CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR
+CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR
+CONFIG_SYS_FM1_QSGMII11_PHY_ADDR
+CONFIG_SYS_FM1_QSGMII21_PHY_ADDR
+CONFIG_SYS_FM1_TGEC_MDIO_ADDR
+CONFIG_SYS_FM2_10GEC1_PHY_ADDR
+CONFIG_SYS_FM2_CLK
+CONFIG_SYS_FM2_DTSEC1_PHY_ADDR
+CONFIG_SYS_FM2_DTSEC2_PHY_ADDR
+CONFIG_SYS_FM2_DTSEC3_PHY_ADDR
+CONFIG_SYS_FM2_DTSEC4_PHY_ADDR
+CONFIG_SYS_FM2_DTSEC_MDIO_ADDR
+CONFIG_SYS_FM2_TGEC_MDIO_ADDR
+CONFIG_SYS_FMAN_FW_ADDR
+CONFIG_SYS_FMAN_V3
+CONFIG_SYS_FM_MURAM_SIZE
+CONFIG_SYS_FORM_3U_CPCI
+CONFIG_SYS_FORM_3U_VPX
+CONFIG_SYS_FORM_6U_CPCI
+CONFIG_SYS_FORM_6U_VPX
+CONFIG_SYS_FORM_AMC
+CONFIG_SYS_FORM_ATCA_AMC
+CONFIG_SYS_FORM_ATCA_PMC
+CONFIG_SYS_FORM_CUSTOM
+CONFIG_SYS_FORM_PCI
+CONFIG_SYS_FORM_PCI_EXPRESS
+CONFIG_SYS_FORM_PMC
+CONFIG_SYS_FORM_PMC_XMC
+CONFIG_SYS_FORM_VME
+CONFIG_SYS_FORM_XMC
+CONFIG_SYS_FPGA0_BASE
+CONFIG_SYS_FPGA0_SIZE
+CONFIG_SYS_FPGA1_BASE
+CONFIG_SYS_FPGA2_BASE
+CONFIG_SYS_FPGA3_BASE
+CONFIG_SYS_FPGAREG_DATE
+CONFIG_SYS_FPGAREG_DIPSW
+CONFIG_SYS_FPGAREG_FREQ
+CONFIG_SYS_FPGAREG_RESET
+CONFIG_SYS_FPGAREG_RESET_CODE
+CONFIG_SYS_FPGA_AMASK
+CONFIG_SYS_FPGA_BASE
+CONFIG_SYS_FPGA_BASE0
+CONFIG_SYS_FPGA_BASE1
+CONFIG_SYS_FPGA_BASE_0
+CONFIG_SYS_FPGA_BASE_1
+CONFIG_SYS_FPGA_BASE_ADDR
+CONFIG_SYS_FPGA_BASE_PHYS
+CONFIG_SYS_FPGA_CHECK_BUSY
+CONFIG_SYS_FPGA_CHECK_CTRLC
+CONFIG_SYS_FPGA_CHECK_ERROR
+CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK
+CONFIG_SYS_FPGA_CLK
+CONFIG_SYS_FPGA_COMMON
+CONFIG_SYS_FPGA_COUNT
+CONFIG_SYS_FPGA_CSOR
+CONFIG_SYS_FPGA_CSPR
+CONFIG_SYS_FPGA_CSPR_EXT
+CONFIG_SYS_FPGA_CTRL
+CONFIG_SYS_FPGA_CTRL_CF_RESET
+CONFIG_SYS_FPGA_CTRL_PS2_RESET
+CONFIG_SYS_FPGA_CTRL_WDI
+CONFIG_SYS_FPGA_DATA
+CONFIG_SYS_FPGA_DONE
+CONFIG_SYS_FPGA_DPRAM_RST
+CONFIG_SYS_FPGA_DPRAM_RW_TYPE
+CONFIG_SYS_FPGA_DPRAM_R_INT_LINE
+CONFIG_SYS_FPGA_DPRAM_W_INT_LINE
+CONFIG_SYS_FPGA_FIFO_BASE
+CONFIG_SYS_FPGA_FTIM0
+CONFIG_SYS_FPGA_FTIM1
+CONFIG_SYS_FPGA_FTIM2
+CONFIG_SYS_FPGA_FTIM3
+CONFIG_SYS_FPGA_INIT
+CONFIG_SYS_FPGA_IS_PROTO
+CONFIG_SYS_FPGA_LINESIDE_LOOPBACK
+CONFIG_SYS_FPGA_MAGIC
+CONFIG_SYS_FPGA_MAGIC_MASK
+CONFIG_SYS_FPGA_MAX_SIZE
+CONFIG_SYS_FPGA_MODE
+CONFIG_SYS_FPGA_MODE_CF_RESET
+CONFIG_SYS_FPGA_MODE_DUART_RESET
+CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT
+CONFIG_SYS_FPGA_MODE_TS_CLEAR
+CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR
+CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE
+CONFIG_SYS_FPGA_NO_RFL_HI
+CONFIG_SYS_FPGA_PHY0_INT
+CONFIG_SYS_FPGA_PHY1_INT
+CONFIG_SYS_FPGA_PRG
+CONFIG_SYS_FPGA_PROG
+CONFIG_SYS_FPGA_PROG_FEEDBACK
+CONFIG_SYS_FPGA_PROG_TIME
+CONFIG_SYS_FPGA_PTR
+CONFIG_SYS_FPGA_REG_BASE
+CONFIG_SYS_FPGA_REG_BASE_ADDR
+CONFIG_SYS_FPGA_SIZE
+CONFIG_SYS_FPGA_SLIC0_CS
+CONFIG_SYS_FPGA_SLIC0_ENABLE
+CONFIG_SYS_FPGA_SLIC0_INT
+CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT
+CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT
+CONFIG_SYS_FPGA_SLIC1_CS
+CONFIG_SYS_FPGA_SLIC1_ENABLE
+CONFIG_SYS_FPGA_SLIC1_INT
+CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT
+CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT
+CONFIG_SYS_FPGA_SPARTAN2
+CONFIG_SYS_FPGA_STATUS
+CONFIG_SYS_FPGA_STATUS_DIP0
+CONFIG_SYS_FPGA_STATUS_DIP1
+CONFIG_SYS_FPGA_STATUS_DIP2
+CONFIG_SYS_FPGA_STATUS_FLASH
+CONFIG_SYS_FPGA_STATUS_TS_IRQ
+CONFIG_SYS_FPGA_TS
+CONFIG_SYS_FPGA_TS_CAP0
+CONFIG_SYS_FPGA_TS_CAP0_LOW
+CONFIG_SYS_FPGA_TS_CAP1
+CONFIG_SYS_FPGA_TS_CAP1_LOW
+CONFIG_SYS_FPGA_TS_CAP2
+CONFIG_SYS_FPGA_TS_CAP2_LOW
+CONFIG_SYS_FPGA_TS_CAP3
+CONFIG_SYS_FPGA_TS_CAP3_LOW
+CONFIG_SYS_FPGA_TS_LOW
+CONFIG_SYS_FPGA_UART0_FO
+CONFIG_SYS_FPGA_UART1_FO
+CONFIG_SYS_FPGA_USER_LED0
+CONFIG_SYS_FPGA_USER_LED1
+CONFIG_SYS_FPGA_VER_MASK
+CONFIG_SYS_FPGA_WAIT
+CONFIG_SYS_FPGA_WAIT_BUSY
+CONFIG_SYS_FPGA_WAIT_CONFIG
+CONFIG_SYS_FPGA_WAIT_INIT
+CONFIG_SYS_FPGA_xxx
+CONFIG_SYS_FSL_AIOP1_BASE
+CONFIG_SYS_FSL_AIOP1_SIZE
+CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+CONFIG_SYS_FSL_BMAN_ADDR
+CONFIG_SYS_FSL_BMAN_OFFSET
+CONFIG_SYS_FSL_BOOTROM_BASE
+CONFIG_SYS_FSL_BOOTROM_SIZE
+CONFIG_SYS_FSL_CCSR_BASE
+CONFIG_SYS_FSL_CCSR_GUR_BE
+CONFIG_SYS_FSL_CCSR_GUR_LE
+CONFIG_SYS_FSL_CCSR_SCFG_BE
+CONFIG_SYS_FSL_CCSR_SCFG_LE
+CONFIG_SYS_FSL_CCSR_SIZE
+CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR
+CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR
+CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR
+CONFIG_SYS_FSL_CLK
+CONFIG_SYS_FSL_CLK_ADDR
+CONFIG_SYS_FSL_CLUSTER_1_L2
+CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET
+CONFIG_SYS_FSL_CLUSTER_CLOCKS
+CONFIG_SYS_FSL_CORENET_CCM_ADDR
+CONFIG_SYS_FSL_CORENET_CCM_OFFSET
+CONFIG_SYS_FSL_CORENET_CLK_ADDR
+CONFIG_SYS_FSL_CORENET_CLK_OFFSET
+CONFIG_SYS_FSL_CORENET_PMAN
+CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET
+CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET
+CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET
+CONFIG_SYS_FSL_CORENET_PME_ADDR
+CONFIG_SYS_FSL_CORENET_PME_OFFSET
+CONFIG_SYS_FSL_CORENET_RCPM_ADDR
+CONFIG_SYS_FSL_CORENET_RCPM_OFFSET
+CONFIG_SYS_FSL_CORENET_RMAN_ADDR
+CONFIG_SYS_FSL_CORENET_RMAN_OFFSET
+CONFIG_SYS_FSL_CORENET_SERDES2_ADDR
+CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET
+CONFIG_SYS_FSL_CORENET_SERDES3_ADDR
+CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET
+CONFIG_SYS_FSL_CORENET_SERDES4_ADDR
+CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET
+CONFIG_SYS_FSL_CORENET_SERDES_ADDR
+CONFIG_SYS_FSL_CORENET_SERDES_OFFSET
+CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+CONFIG_SYS_FSL_CORES_PER_CLUSTER
+CONFIG_SYS_FSL_CPC
+CONFIG_SYS_FSL_CPC_ADDR
+CONFIG_SYS_FSL_CPC_OFFSET
+CONFIG_SYS_FSL_CSU_ADDR
+CONFIG_SYS_FSL_DCFG_ADDR
+CONFIG_SYS_FSL_DCSR_BASE
+CONFIG_SYS_FSL_DCSR_DDR2_ADDR
+CONFIG_SYS_FSL_DCSR_DDR3_ADDR
+CONFIG_SYS_FSL_DCSR_DDR4_ADDR
+CONFIG_SYS_FSL_DCSR_DDR_ADDR
+CONFIG_SYS_FSL_DCSR_SIZE
+CONFIG_SYS_FSL_DCU_BE
+CONFIG_SYS_FSL_DCU_LE
+CONFIG_SYS_FSL_DDR2_ADDR
+CONFIG_SYS_FSL_DDR3L
+CONFIG_SYS_FSL_DDR3_ADDR
+CONFIG_SYS_FSL_DDR_ADDR
+CONFIG_SYS_FSL_DDR_EMU
+CONFIG_SYS_FSL_DDR_INTLV_256B
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
+CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+CONFIG_SYS_FSL_DRAM_BASE1
+CONFIG_SYS_FSL_DRAM_BASE2
+CONFIG_SYS_FSL_DRAM_BASE3
+CONFIG_SYS_FSL_DRAM_SIZE1
+CONFIG_SYS_FSL_DRAM_SIZE2
+CONFIG_SYS_FSL_DRAM_SIZE3
+CONFIG_SYS_FSL_DSPI_BE
+CONFIG_SYS_FSL_DSP_CCSRBAR
+CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS
+CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
+CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
+CONFIG_SYS_FSL_DSP_DDR_ADDR
+CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
+CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
+CONFIG_SYS_FSL_ERRATUM_A008751
+CONFIG_SYS_FSL_ERRATUM_A_004934
+CONFIG_SYS_FSL_ESDHC_ADDR
+CONFIG_SYS_FSL_ESDHC_BE
+CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
+CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+CONFIG_SYS_FSL_ESDHC_LE
+CONFIG_SYS_FSL_ESDHC_NUM
+CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
+CONFIG_SYS_FSL_ESDHC_USE_PIO
+CONFIG_SYS_FSL_FM
+CONFIG_SYS_FSL_FM1_ADDR
+CONFIG_SYS_FSL_FM1_DTSEC1_ADDR
+CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
+CONFIG_SYS_FSL_FM1_OFFSET
+CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET
+CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
+CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET
+CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
+CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
+CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
+CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
+CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
+CONFIG_SYS_FSL_FM2_ADDR
+CONFIG_SYS_FSL_FM2_OFFSET
+CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET
+CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET
+CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET
+CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET
+CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET
+CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET
+CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET
+CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
+CONFIG_SYS_FSL_FMAN_ADDR
+CONFIG_SYS_FSL_GUTS_ADDR
+CONFIG_SYS_FSL_I2C
+CONFIG_SYS_FSL_I2C2_OFFSET
+CONFIG_SYS_FSL_I2C2_SLAVE
+CONFIG_SYS_FSL_I2C2_SPEED
+CONFIG_SYS_FSL_I2C3_OFFSET
+CONFIG_SYS_FSL_I2C3_SLAVE
+CONFIG_SYS_FSL_I2C3_SPEED
+CONFIG_SYS_FSL_I2C4_OFFSET
+CONFIG_SYS_FSL_I2C4_SLAVE
+CONFIG_SYS_FSL_I2C4_SPEED
+CONFIG_SYS_FSL_I2C_OFFSET
+CONFIG_SYS_FSL_I2C_SLAVE
+CONFIG_SYS_FSL_I2C_SPEED
+CONFIG_SYS_FSL_IFC_BASE
+CONFIG_SYS_FSL_IFC_BASE1
+CONFIG_SYS_FSL_IFC_BASE2
+CONFIG_SYS_FSL_IFC_BE
+CONFIG_SYS_FSL_IFC_LE
+CONFIG_SYS_FSL_IFC_SIZE
+CONFIG_SYS_FSL_IFC_SIZE1
+CONFIG_SYS_FSL_IFC_SIZE1_1
+CONFIG_SYS_FSL_IFC_SIZE2
+CONFIG_SYS_FSL_ISBC_VER
+CONFIG_SYS_FSL_JR0_ADDR
+CONFIG_SYS_FSL_JR0_OFFSET
+CONFIG_SYS_FSL_LS1_CLK_ADDR
+CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
+CONFIG_SYS_FSL_MAX_NUM_OF_SEC
+CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
+CONFIG_SYS_FSL_MC_BASE
+CONFIG_SYS_FSL_MC_SIZE
+CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+CONFIG_SYS_FSL_NI_BASE
+CONFIG_SYS_FSL_NI_SIZE
+CONFIG_SYS_FSL_NO_SERDES
+CONFIG_SYS_FSL_NUM_CC_PLL
+CONFIG_SYS_FSL_NUM_CC_PLLS
+CONFIG_SYS_FSL_OCRAM_BASE
+CONFIG_SYS_FSL_OCRAM_SIZE
+CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+CONFIG_SYS_FSL_PAMU_OFFSET
+CONFIG_SYS_FSL_PBL_PBI
+CONFIG_SYS_FSL_PBL_RCW
+CONFIG_SYS_FSL_PCIE_COMPAT
+CONFIG_SYS_FSL_PCI_VER_3_X
+CONFIG_SYS_FSL_PEBUF_BASE
+CONFIG_SYS_FSL_PEBUF_SIZE
+CONFIG_SYS_FSL_PEX_LUT_BE
+CONFIG_SYS_FSL_PEX_LUT_LE
+CONFIG_SYS_FSL_PMIC_I2C_ADDR
+CONFIG_SYS_FSL_PMU_ADDR
+CONFIG_SYS_FSL_PMU_CLTBENR
+CONFIG_SYS_FSL_QBMAN_BASE
+CONFIG_SYS_FSL_QBMAN_SIZE
+CONFIG_SYS_FSL_QBMAN_SIZE_1
+CONFIG_SYS_FSL_QMAN_ADDR
+CONFIG_SYS_FSL_QMAN_OFFSET
+CONFIG_SYS_FSL_QMAN_V3
+CONFIG_SYS_FSL_QSPI_AHB
+CONFIG_SYS_FSL_QSPI_BASE
+CONFIG_SYS_FSL_QSPI_BASE1
+CONFIG_SYS_FSL_QSPI_BASE2
+CONFIG_SYS_FSL_QSPI_BE
+CONFIG_SYS_FSL_QSPI_LE
+CONFIG_SYS_FSL_QSPI_SIZE
+CONFIG_SYS_FSL_QSPI_SIZE1
+CONFIG_SYS_FSL_QSPI_SIZE2
+CONFIG_SYS_FSL_RAID_ENGINE
+CONFIG_SYS_FSL_RAID_ENGINE_ADDR
+CONFIG_SYS_FSL_RAID_ENGINE_OFFSET
+CONFIG_SYS_FSL_RCPM_ADDR
+CONFIG_SYS_FSL_RMU
+CONFIG_SYS_FSL_RST_ADDR
+CONFIG_SYS_FSL_SCFG_ADDR
+CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
+CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET
+CONFIG_SYS_FSL_SCFG_OFFSET
+CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
+CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
+CONFIG_SYS_FSL_SEC_ADDR
+CONFIG_SYS_FSL_SEC_IDX_OFFSET
+CONFIG_SYS_FSL_SEC_MON_BE
+CONFIG_SYS_FSL_SEC_MON_LE
+CONFIG_SYS_FSL_SEC_OFFSET
+CONFIG_SYS_FSL_SERDES
+CONFIG_SYS_FSL_SERDES_ADDR
+CONFIG_SYS_FSL_SFP_BE
+CONFIG_SYS_FSL_SFP_LE
+CONFIG_SYS_FSL_SFP_VER_3_0
+CONFIG_SYS_FSL_SFP_VER_3_2
+CONFIG_SYS_FSL_SFP_VER_3_4
+CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+CONFIG_SYS_FSL_SNVS_LE
+CONFIG_SYS_FSL_SRDS_3
+CONFIG_SYS_FSL_SRDS_4
+CONFIG_SYS_FSL_SRDS_NUM_PLLS
+CONFIG_SYS_FSL_SRIO_ADDR
+CONFIG_SYS_FSL_SRIO_IB_WIN_NUM
+CONFIG_SYS_FSL_SRIO_LIODN
+CONFIG_SYS_FSL_SRIO_MAX_PORTS
+CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM
+CONFIG_SYS_FSL_SRIO_OB_WIN_NUM
+CONFIG_SYS_FSL_SRIO_OFFSET
+CONFIG_SYS_FSL_SRK_LE
+CONFIG_SYS_FSL_TBCLK_DIV
+CONFIG_SYS_FSL_TIMER_ADDR
+CONFIG_SYS_FSL_USB1_ADDR
+CONFIG_SYS_FSL_USB1_PHY_ENABLE
+CONFIG_SYS_FSL_USB2_ADDR
+CONFIG_SYS_FSL_USB2_PHY_ENABLE
+CONFIG_SYS_FSL_USB_CTRL_PHY_EN
+CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN
+CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE
+CONFIG_SYS_FSL_USB_HS_DISCNCT_INC
+CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN
+CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV
+CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN
+CONFIG_SYS_FSL_USB_PLLPRG2_MFI
+CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK
+CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN
+CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN
+CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN
+CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV
+CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK
+CONFIG_SYS_FSL_USB_PWRFLT_CR_EN
+CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3
+CONFIG_SYS_FSL_USB_SYS_CLK_VALID
+CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN
+CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK
+CONFIG_SYS_FSL_USDHC_NUM
+CONFIG_SYS_FSL_WDOG_BE
+CONFIG_SYS_FSL_WRIOP1_ADDR
+CONFIG_SYS_FSL_WRIOP1_BASE
+CONFIG_SYS_FSL_WRIOP1_MDIO1
+CONFIG_SYS_FSL_WRIOP1_MDIO2
+CONFIG_SYS_FSL_WRIOP1_SIZE
+CONFIG_SYS_FSL_XHCI_USB1_ADDR
+CONFIG_SYS_FSL_XHCI_USB2_ADDR
+CONFIG_SYS_FSL_XHCI_USB3_ADDR
+CONFIG_SYS_FSMC_BASE
+CONFIG_SYS_FSMC_NAND_16BIT
+CONFIG_SYS_FSMC_NAND_8BIT
+CONFIG_SYS_FSMC_NAND_SP
+CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS
+CONFIG_SYS_FTPMU010_SDRAMHTC
+CONFIG_SYS_FTSDMC021_BANK0_BASE
+CONFIG_SYS_FTSDMC021_BANK0_BSR
+CONFIG_SYS_FTSDMC021_BANK1_BASE
+CONFIG_SYS_FTSDMC021_BANK1_BSR
+CONFIG_SYS_FTSDMC021_CR1
+CONFIG_SYS_FTSDMC021_CR2
+CONFIG_SYS_FTSDMC021_TP1
+CONFIG_SYS_FTSDMC021_TP2
+CONFIG_SYS_FTSMC020_CONFIGS
+CONFIG_SYS_FULL_VA
+CONFIG_SYS_GAFR0_L_VAL
+CONFIG_SYS_GAFR0_U_VAL
+CONFIG_SYS_GAFR1_L_VAL
+CONFIG_SYS_GAFR1_U_VAL
+CONFIG_SYS_GAFR2_L_VAL
+CONFIG_SYS_GAFR2_U_VAL
+CONFIG_SYS_GAFR3_L_VAL
+CONFIG_SYS_GAFR3_U_VAL
+CONFIG_SYS_GBIT_MII1_BUSNAME
+CONFIG_SYS_GBIT_MII_BUSNAME
+CONFIG_SYS_GBL_DATA_ADDR
+CONFIG_SYS_GBL_DATA_OFFSET
+CONFIG_SYS_GBL_DATA_SIZE
+CONFIG_SYS_GENERIC_BOARD
+CONFIG_SYS_GENERIC_GLOBAL_DATA
+CONFIG_SYS_GIC400_ADDR
+CONFIG_SYS_GLOBAL_SDRAM_LIMIT
+CONFIG_SYS_GP1DIR
+CONFIG_SYS_GP1ODR
+CONFIG_SYS_GP2DIR
+CONFIG_SYS_GP2ODR
+CONFIG_SYS_GPCR0_VAL
+CONFIG_SYS_GPCR1_VAL
+CONFIG_SYS_GPCR2_VAL
+CONFIG_SYS_GPCR3_VAL
+CONFIG_SYS_GPDR0_VAL
+CONFIG_SYS_GPDR1_VAL
+CONFIG_SYS_GPDR2_VAL
+CONFIG_SYS_GPDR3_VAL
+CONFIG_SYS_GPIO0_ISR1H
+CONFIG_SYS_GPIO0_ISR1L
+CONFIG_SYS_GPIO0_ISR2H
+CONFIG_SYS_GPIO0_ISR2L
+CONFIG_SYS_GPIO0_ODR
+CONFIG_SYS_GPIO0_OR
+CONFIG_SYS_GPIO0_OSRH
+CONFIG_SYS_GPIO0_OSRL
+CONFIG_SYS_GPIO0_TCR
+CONFIG_SYS_GPIO0_TSRH
+CONFIG_SYS_GPIO0_TSRL
+CONFIG_SYS_GPIO1_DAT
+CONFIG_SYS_GPIO1_DIR
+CONFIG_SYS_GPIO1_EN
+CONFIG_SYS_GPIO1_FUNC
+CONFIG_SYS_GPIO1_ISR1H
+CONFIG_SYS_GPIO1_ISR1L
+CONFIG_SYS_GPIO1_LED
+CONFIG_SYS_GPIO1_OSRH
+CONFIG_SYS_GPIO1_OSRL
+CONFIG_SYS_GPIO1_OUT
+CONFIG_SYS_GPIO1_PRELIM
+CONFIG_SYS_GPIO1_TCR
+CONFIG_SYS_GPIO1_TSRH
+CONFIG_SYS_GPIO1_TSRL
+CONFIG_SYS_GPIO2_DAT
+CONFIG_SYS_GPIO2_DIR
+CONFIG_SYS_GPIO2_PRELIM
+CONFIG_SYS_GPIO_0_ADDR
+CONFIG_SYS_GPIO_BASE
+CONFIG_SYS_GPIO_BOARD_RESET
+CONFIG_SYS_GPIO_CAN_ENABLE
+CONFIG_SYS_GPIO_CRAM_ADV
+CONFIG_SYS_GPIO_CRAM_CLK
+CONFIG_SYS_GPIO_CRAM_CRE
+CONFIG_SYS_GPIO_CRAM_WAIT
+CONFIG_SYS_GPIO_DATADIR
+CONFIG_SYS_GPIO_DATAVALUE
+CONFIG_SYS_GPIO_DSPIC_READY
+CONFIG_SYS_GPIO_EEPROM_EXT_WP
+CONFIG_SYS_GPIO_EEPROM_INT_WP
+CONFIG_SYS_GPIO_EEPROM_WP
+CONFIG_SYS_GPIO_EN
+CONFIG_SYS_GPIO_ENABLE
+CONFIG_SYS_GPIO_EREADY
+CONFIG_SYS_GPIO_FLASH_WP
+CONFIG_SYS_GPIO_FUNC
+CONFIG_SYS_GPIO_HIGHSIDE
+CONFIG_SYS_GPIO_HWREV_MASK
+CONFIG_SYS_GPIO_HWREV_SHIFT
+CONFIG_SYS_GPIO_I2C_SCL
+CONFIG_SYS_GPIO_I2C_SDA
+CONFIG_SYS_GPIO_LEDA_N
+CONFIG_SYS_GPIO_LEDB_N
+CONFIG_SYS_GPIO_LEDRUN_N
+CONFIG_SYS_GPIO_LIME_RST
+CONFIG_SYS_GPIO_LIME_S
+CONFIG_SYS_GPIO_LSB_ENABLE
+CONFIG_SYS_GPIO_M66EN
+CONFIG_SYS_GPIO_MONARCH_N
+CONFIG_SYS_GPIO_ODR
+CONFIG_SYS_GPIO_OPENDRAIN
+CONFIG_SYS_GPIO_OR
+CONFIG_SYS_GPIO_OUT
+CONFIG_SYS_GPIO_PCIE_CLKREQ
+CONFIG_SYS_GPIO_PCIE_PRESENT0
+CONFIG_SYS_GPIO_PCIE_PRESENT1
+CONFIG_SYS_GPIO_PCIE_PRESENT2
+CONFIG_SYS_GPIO_PCIE_RST
+CONFIG_SYS_GPIO_PCIE_WAKE
+CONFIG_SYS_GPIO_PERM_VOLT_FEED
+CONFIG_SYS_GPIO_PHY0_RST
+CONFIG_SYS_GPIO_PHY1_RST
+CONFIG_SYS_GPIO_PHY_RST
+CONFIG_SYS_GPIO_RS232_FORCEOFF
+CONFIG_SYS_GPIO_SELFRST_N
+CONFIG_SYS_GPIO_STARTUP_FINISHED
+CONFIG_SYS_GPIO_STARTUP_FINISHED_N
+CONFIG_SYS_GPIO_SYSMON_STATUS
+CONFIG_SYS_GPIO_TCR
+CONFIG_SYS_GPIO_WATCHDOG
+CONFIG_SYS_GPIO_WIDTH
+CONFIG_SYS_GPR1
+CONFIG_SYS_GPSR0_VAL
+CONFIG_SYS_GPSR1_VAL
+CONFIG_SYS_GPSR2_VAL
+CONFIG_SYS_GPSR3_VAL
+CONFIG_SYS_GPS_PORT_CONFIG
+CONFIG_SYS_GPS_PORT_CONFIG_1
+CONFIG_SYS_GPS_PORT_CONFIG_2
+CONFIG_SYS_GRLIB_APBUART_INDEX
+CONFIG_SYS_GRLIB_ESA_MCTRL1
+CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1
+CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2
+CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3
+CONFIG_SYS_GRLIB_ESA_MCTRL2
+CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG1
+CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG2
+CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG3
+CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
+CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG1
+CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG3
+CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG4
+CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
+CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG1
+CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG3
+CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG4
+CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
+CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL
+CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
+CONFIG_SYS_GRLIB_GAISLER_DDRSPA2_CTRL
+CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
+CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1
+CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2
+CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3
+CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
+CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG1
+CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG2
+CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG3
+CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
+CONFIG_SYS_GRLIB_GAISLER_SDCTRL1_CTRL
+CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
+CONFIG_SYS_GRLIB_GAISLER_SDCTRL2_CTRL
+CONFIG_SYS_GRLIB_GPTIMER_INDEX
+CONFIG_SYS_GRLIB_GRETH_INDEX
+CONFIG_SYS_GRLIB_GRETH_PHYADDR
+CONFIG_SYS_GRLIB_GRUSB_INDEX
+CONFIG_SYS_GRLIB_MEMCFG1
+CONFIG_SYS_GRLIB_MEMCFG2
+CONFIG_SYS_GRLIB_MEMCFG3
+CONFIG_SYS_GRLIB_SDRAM
+CONFIG_SYS_GRLIB_SINGLE_BUS
+CONFIG_SYS_HALT_BEFOR_RAM_JUMP
+CONFIG_SYS_HAS_NO_CACHE
+CONFIG_SYS_HELP_CMD_WIDTH
+CONFIG_SYS_HID0_FINAL
+CONFIG_SYS_HID0_INIT
+CONFIG_SYS_HID2
+CONFIG_SYS_HIGH
+CONFIG_SYS_HMI_BASE
+CONFIG_SYS_HOSTNAME
+CONFIG_SYS_HRCW_HIGH
+CONFIG_SYS_HRCW_HIGH_BASE
+CONFIG_SYS_HRCW_LOW
+CONFIG_SYS_HRCW_MASTER
+CONFIG_SYS_HRCW_SLAVE1
+CONFIG_SYS_HRCW_SLAVE2
+CONFIG_SYS_HRCW_SLAVE3
+CONFIG_SYS_HRCW_SLAVE4
+CONFIG_SYS_HRCW_SLAVE5
+CONFIG_SYS_HRCW_SLAVE6
+CONFIG_SYS_HRCW_SLAVE7
+CONFIG_SYS_HSDRAMC
+CONFIG_SYS_HWINFO_MAGIC
+CONFIG_SYS_HWINFO_OFFSET
+CONFIG_SYS_HWINFO_SIZE
+CONFIG_SYS_HZ_CLOCK
+CONFIG_SYS_I2C
+CONFIG_SYS_I2C2_FSL_OFFSET
+CONFIG_SYS_I2C2_OFFSET
+CONFIG_SYS_I2C2_PINMUX_CLR
+CONFIG_SYS_I2C2_PINMUX_REG
+CONFIG_SYS_I2C2_PINMUX_SET
+CONFIG_SYS_I2C_0
+CONFIG_SYS_I2C_2
+CONFIG_SYS_I2C_5
+CONFIG_SYS_I2C_8574A_ADDR1
+CONFIG_SYS_I2C_8574A_ADDR2
+CONFIG_SYS_I2C_8574_ADDR1
+CONFIG_SYS_I2C_8574_ADDR2
+CONFIG_SYS_I2C_ADI
+CONFIG_SYS_I2C_BASE
+CONFIG_SYS_I2C_BASE0
+CONFIG_SYS_I2C_BASE1
+CONFIG_SYS_I2C_BASE2
+CONFIG_SYS_I2C_BASE3
+CONFIG_SYS_I2C_BASE4
+CONFIG_SYS_I2C_BASE5
+CONFIG_SYS_I2C_BOARD_LATE_INIT
+CONFIG_SYS_I2C_BOOT_EEPROM_ADDR
+CONFIG_SYS_I2C_BUSES
+CONFIG_SYS_I2C_BUS_MAX
+CONFIG_SYS_I2C_CLK_OFFSET
+CONFIG_SYS_I2C_DAVINCI
+CONFIG_SYS_I2C_DIRECT_BUS
+CONFIG_SYS_I2C_DPMEM_OFFSET
+CONFIG_SYS_I2C_DS1621_ADDR
+CONFIG_SYS_I2C_DS4510_ADDR
+CONFIG_SYS_I2C_DSPIC_2_ADDR
+CONFIG_SYS_I2C_DSPIC_ADDR
+CONFIG_SYS_I2C_DSPIC_IO_ADDR
+CONFIG_SYS_I2C_DSPIC_KEYB_ADDR
+CONFIG_SYS_I2C_DTT_ADDR
+CONFIG_SYS_I2C_DVI_ADDR
+CONFIG_SYS_I2C_DVI_BUS_NUM
+CONFIG_SYS_I2C_EARLY_INIT
+CONFIG_SYS_I2C_EEPROM
+CONFIG_SYS_I2C_EEPROM_ADDR
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+CONFIG_SYS_I2C_EEPROM_BUS
+CONFIG_SYS_I2C_EEPROM_BUS_NUM
+CONFIG_SYS_I2C_EEPROM_CCID
+CONFIG_SYS_I2C_EEPROM_CPU_ADDR
+CONFIG_SYS_I2C_EEPROM_MAC_OFFSET
+CONFIG_SYS_I2C_EEPROM_MB_ADDR
+CONFIG_SYS_I2C_EEPROM_NXID
+CONFIG_SYS_I2C_EEPROM_NXID_MAC
+CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS
+CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS
+CONFIG_SYS_I2C_EXPANDER_ADDR
+CONFIG_SYS_I2C_FACT_ADDR
+CONFIG_SYS_I2C_FPGA_ADDR
+CONFIG_SYS_I2C_FRAM
+CONFIG_SYS_I2C_G762_ADDR
+CONFIG_SYS_I2C_GENERIC_MAC
+CONFIG_SYS_I2C_HWMON_ADDR
+CONFIG_SYS_I2C_IDT6V49205B
+CONFIG_SYS_I2C_IFDR_DIV
+CONFIG_SYS_I2C_IHS
+CONFIG_SYS_I2C_IHS_CH0
+CONFIG_SYS_I2C_IHS_CH0_1
+CONFIG_SYS_I2C_IHS_CH1
+CONFIG_SYS_I2C_IHS_CH1_1
+CONFIG_SYS_I2C_IHS_CH2
+CONFIG_SYS_I2C_IHS_CH2_1
+CONFIG_SYS_I2C_IHS_CH3
+CONFIG_SYS_I2C_IHS_CH3_1
+CONFIG_SYS_I2C_IHS_DUAL
+CONFIG_SYS_I2C_IHS_SLAVE_0
+CONFIG_SYS_I2C_IHS_SLAVE_0_1
+CONFIG_SYS_I2C_IHS_SLAVE_1
+CONFIG_SYS_I2C_IHS_SLAVE_1_1
+CONFIG_SYS_I2C_IHS_SLAVE_2
+CONFIG_SYS_I2C_IHS_SLAVE_2_1
+CONFIG_SYS_I2C_IHS_SLAVE_3
+CONFIG_SYS_I2C_IHS_SLAVE_3_1
+CONFIG_SYS_I2C_IHS_SPEED_0
+CONFIG_SYS_I2C_IHS_SPEED_0_1
+CONFIG_SYS_I2C_IHS_SPEED_1
+CONFIG_SYS_I2C_IHS_SPEED_1_1
+CONFIG_SYS_I2C_IHS_SPEED_2
+CONFIG_SYS_I2C_IHS_SPEED_2_1
+CONFIG_SYS_I2C_IHS_SPEED_3
+CONFIG_SYS_I2C_IHS_SPEED_3_1
+CONFIG_SYS_I2C_INIT_BOARD
+CONFIG_SYS_I2C_IO
+CONFIG_SYS_I2C_KEYBD_ADDR
+CONFIG_SYS_I2C_KONA
+CONFIG_SYS_I2C_LDI_ADDR
+CONFIG_SYS_I2C_LM75_ADDR
+CONFIG_SYS_I2C_LM90_ADDR
+CONFIG_SYS_I2C_LPC32XX
+CONFIG_SYS_I2C_LPC32XX_SLAVE
+CONFIG_SYS_I2C_LPC32XX_SPEED
+CONFIG_SYS_I2C_MAC1_BUS
+CONFIG_SYS_I2C_MAC1_CHIP_ADDR
+CONFIG_SYS_I2C_MAC1_DATA_ADDR
+CONFIG_SYS_I2C_MAC2_BUS
+CONFIG_SYS_I2C_MAC2_CHIP_ADDR
+CONFIG_SYS_I2C_MAC2_DATA_ADDR
+CONFIG_SYS_I2C_MAC_OFFSET
+CONFIG_SYS_I2C_MAX1237_ADDR
+CONFIG_SYS_I2C_MAX_HOPS
+CONFIG_SYS_I2C_MODULE
+CONFIG_SYS_I2C_MXC_I2C1
+CONFIG_SYS_I2C_MXC_I2C2
+CONFIG_SYS_I2C_MXC_I2C3
+CONFIG_SYS_I2C_MXC_I2C4
+CONFIG_SYS_I2C_MXS
+CONFIG_SYS_I2C_NCT72_ADDR
+CONFIG_SYS_I2C_NOPROBES
+CONFIG_SYS_I2C_OFFSET
+CONFIG_SYS_I2C_OMAP24XX
+CONFIG_SYS_I2C_OMAP34XX
+CONFIG_SYS_I2C_PCA953X_ADDR
+CONFIG_SYS_I2C_PCA953X_ADDR0
+CONFIG_SYS_I2C_PCA953X_ADDR1
+CONFIG_SYS_I2C_PCA953X_ADDR2
+CONFIG_SYS_I2C_PCA953X_ADDR3
+CONFIG_SYS_I2C_PCA953X_WIDTH
+CONFIG_SYS_I2C_PCA9553_ADDR
+CONFIG_SYS_I2C_PCA9555_ADDR
+CONFIG_SYS_I2C_PCA9557_ADDR
+CONFIG_SYS_I2C_PCF8574A_ADDR
+CONFIG_SYS_I2C_PEX8518_ADDR
+CONFIG_SYS_I2C_PINMUX_CLR
+CONFIG_SYS_I2C_PINMUX_REG
+CONFIG_SYS_I2C_PINMUX_SET
+CONFIG_SYS_I2C_POWERIC_ADDR
+CONFIG_SYS_I2C_PPC4XX
+CONFIG_SYS_I2C_PPC4XX_CH0
+CONFIG_SYS_I2C_PPC4XX_CH1
+CONFIG_SYS_I2C_PPC4XX_SLAVE_0
+CONFIG_SYS_I2C_PPC4XX_SLAVE_1
+CONFIG_SYS_I2C_PPC4XX_SPEED_0
+CONFIG_SYS_I2C_PPC4XX_SPEED_1
+CONFIG_SYS_I2C_PXA
+CONFIG_SYS_I2C_QIXIS_ADDR
+CONFIG_SYS_I2C_RCAR
+CONFIG_SYS_I2C_RTC_ADDR
+CONFIG_SYS_I2C_S3C24X0
+CONFIG_SYS_I2C_S3C24X0_SLAVE
+CONFIG_SYS_I2C_S3C24X0_SPEED
+CONFIG_SYS_I2C_SH
+CONFIG_SYS_I2C_SH_BASE0
+CONFIG_SYS_I2C_SH_BASE1
+CONFIG_SYS_I2C_SH_BASE2
+CONFIG_SYS_I2C_SH_BASE3
+CONFIG_SYS_I2C_SH_BASE4
+CONFIG_SYS_I2C_SH_NUM_CONTROLLERS
+CONFIG_SYS_I2C_SH_SPEED0
+CONFIG_SYS_I2C_SH_SPEED1
+CONFIG_SYS_I2C_SH_SPEED2
+CONFIG_SYS_I2C_SH_SPEED3
+CONFIG_SYS_I2C_SH_SPEED4
+CONFIG_SYS_I2C_SLAVE
+CONFIG_SYS_I2C_SLAVE1
+CONFIG_SYS_I2C_SLAVE2
+CONFIG_SYS_I2C_SLAVE3
+CONFIG_SYS_I2C_SOFT
+CONFIG_SYS_I2C_SOFT_SLAVE
+CONFIG_SYS_I2C_SOFT_SLAVE_10
+CONFIG_SYS_I2C_SOFT_SLAVE_11
+CONFIG_SYS_I2C_SOFT_SLAVE_12
+CONFIG_SYS_I2C_SOFT_SLAVE_2
+CONFIG_SYS_I2C_SOFT_SLAVE_3
+CONFIG_SYS_I2C_SOFT_SLAVE_4
+CONFIG_SYS_I2C_SOFT_SLAVE_5
+CONFIG_SYS_I2C_SOFT_SLAVE_6
+CONFIG_SYS_I2C_SOFT_SLAVE_7
+CONFIG_SYS_I2C_SOFT_SLAVE_8
+CONFIG_SYS_I2C_SOFT_SLAVE_9
+CONFIG_SYS_I2C_SOFT_SPEED
+CONFIG_SYS_I2C_SOFT_SPEED_10
+CONFIG_SYS_I2C_SOFT_SPEED_11
+CONFIG_SYS_I2C_SOFT_SPEED_12
+CONFIG_SYS_I2C_SOFT_SPEED_2
+CONFIG_SYS_I2C_SOFT_SPEED_3
+CONFIG_SYS_I2C_SOFT_SPEED_4
+CONFIG_SYS_I2C_SOFT_SPEED_5
+CONFIG_SYS_I2C_SOFT_SPEED_6
+CONFIG_SYS_I2C_SOFT_SPEED_7
+CONFIG_SYS_I2C_SOFT_SPEED_8
+CONFIG_SYS_I2C_SOFT_SPEED_9
+CONFIG_SYS_I2C_SPEED
+CONFIG_SYS_I2C_SPEED1
+CONFIG_SYS_I2C_SPEED2
+CONFIG_SYS_I2C_SPEED3
+CONFIG_SYS_I2C_TCA642X_ADDR
+CONFIG_SYS_I2C_TCA642X_BUS_NUM
+CONFIG_SYS_I2C_TEGRA
+CONFIG_SYS_I2C_UCODE_PATCH
+CONFIG_SYS_I2C_W83782G_ADDR
+CONFIG_SYS_I2C_ZYNQ
+CONFIG_SYS_I2C_ZYNQ_SLAVE
+CONFIG_SYS_I2C_ZYNQ_SPEED
+CONFIG_SYS_I2ODMA_BASE
+CONFIG_SYS_I2ODMA_PHYS_ADDR
+CONFIG_SYS_I2c_INIT_MPC5XXX
+CONFIG_SYS_IBAT
+CONFIG_SYS_IBAT0L
+CONFIG_SYS_IBAT0U
+CONFIG_SYS_IBAT1L
+CONFIG_SYS_IBAT1U
+CONFIG_SYS_IBAT2L
+CONFIG_SYS_IBAT2U
+CONFIG_SYS_IBAT3L
+CONFIG_SYS_IBAT3U
+CONFIG_SYS_IBAT4L
+CONFIG_SYS_IBAT4U
+CONFIG_SYS_IBAT5L
+CONFIG_SYS_IBAT5U
+CONFIG_SYS_IBAT6L
+CONFIG_SYS_IBAT6L_EARLY
+CONFIG_SYS_IBAT6U
+CONFIG_SYS_IBAT6U_EARLY
+CONFIG_SYS_IBAT7L
+CONFIG_SYS_IBAT7U
+CONFIG_SYS_ICACHE_INV
+CONFIG_SYS_ICACHE_LINESZ
+CONFIG_SYS_ICACHE_SACR_VALUE
+CONFIG_SYS_ICS8N3QV01_I2C
+CONFIG_SYS_ICTRL
+CONFIG_SYS_IDE_MAXBUS
+CONFIG_SYS_IDE_MAXDEVICE
+CONFIG_SYS_ID_EEPROM
+CONFIG_SYS_IFC_ADDR
+CONFIG_SYS_IFC_CCR
+CONFIG_SYS_IMMR
+CONFIG_SYS_INIT_DBCR
+CONFIG_SYS_INIT_DCACHE_CS
+CONFIG_SYS_INIT_DCACHE_PBxAR
+CONFIG_SYS_INIT_DCACHE_PBxCR
+CONFIG_SYS_INIT_EXTRA_SIZE
+CONFIG_SYS_INIT_L2CSR0
+CONFIG_SYS_INIT_L2_ADDR
+CONFIG_SYS_INIT_L2_ADDR_PHYS
+CONFIG_SYS_INIT_L2_END
+CONFIG_SYS_INIT_L3_ADDR
+CONFIG_SYS_INIT_L3_ADDR_PHYS
+CONFIG_SYS_INIT_L3_END
+CONFIG_SYS_INIT_L3_VADDR
+CONFIG_SYS_INIT_RAM1_ADDR
+CONFIG_SYS_INIT_RAM1_CTRL
+CONFIG_SYS_INIT_RAM1_END
+CONFIG_SYS_INIT_RAM_ADDR
+CONFIG_SYS_INIT_RAM_ADDR_PHYS
+CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
+CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW
+CONFIG_SYS_INIT_RAM_CTRL
+CONFIG_SYS_INIT_RAM_DCACHE
+CONFIG_SYS_INIT_RAM_LOCK
+CONFIG_SYS_INIT_RAM_PATTERN
+CONFIG_SYS_INIT_RAM_SIZE
+CONFIG_SYS_INIT_SP_ADDR
+CONFIG_SYS_INIT_SP_OFFSET
+CONFIG_SYS_INPUT_CLKSRC
+CONFIG_SYS_INTA_FAKE
+CONFIG_SYS_INTEL_BOOT
+CONFIG_SYS_INTERLAKEN
+CONFIG_SYS_INTRAM_BASE
+CONFIG_SYS_INTRAM_SIZE
+CONFIG_SYS_INTR_BASE
+CONFIG_SYS_INTSRAM
+CONFIG_SYS_INTSRAMSZ
+CONFIG_SYS_INT_FLASH_BASE
+CONFIG_SYS_INT_FLASH_ENABLE
+CONFIG_SYS_IOCTRL_MUX_DDR
+CONFIG_SYS_IO_BASE
+CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
+CONFIG_SYS_IPBSPEED_133
+CONFIG_SYS_IR_REG_BASE_ADDR
+CONFIG_SYS_ISA_BASE
+CONFIG_SYS_ISA_IO
+CONFIG_SYS_ISA_IO_BASE_ADDRESS
+CONFIG_SYS_ISA_IO_OFFSET
+CONFIG_SYS_ISA_IO_STRIDE
+CONFIG_SYS_ISA_MEM
+CONFIG_SYS_ISB
+CONFIG_SYS_ISRAM_BASE
+CONFIG_SYS_IVM_EEPROM_ADR
+CONFIG_SYS_IVM_EEPROM_MAX_LEN
+CONFIG_SYS_IVM_EEPROM_PAGE_LEN
+CONFIG_SYS_JFFS2_FIRST_BANK
+CONFIG_SYS_JFFS2_FIRST_SECTOR
+CONFIG_SYS_JFFS2_MEM_NAND
+CONFIG_SYS_JFFS2_NUM_BANKS
+CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+CONFIG_SYS_KBYTES_SDRAM
+CONFIG_SYS_KEY_REG_BASE_ADDR
+CONFIG_SYS_KMBEC_FPGA_BASE
+CONFIG_SYS_KMBEC_FPGA_SIZE
+CONFIG_SYS_KWD_CONFIG
+CONFIG_SYS_KW_SPI_MPP
+CONFIG_SYS_L2
+CONFIG_SYS_L2_PL310
+CONFIG_SYS_L2_SIZE
+CONFIG_SYS_L3_SIZE
+CONFIG_SYS_LARGE_FLASH
+CONFIG_SYS_LATCH0_BOOT
+CONFIG_SYS_LATCH0_RESET
+CONFIG_SYS_LATCH1_BOOT
+CONFIG_SYS_LATCH1_RESET
+CONFIG_SYS_LATCH_ADDR
+CONFIG_SYS_LATCH_BASE
+CONFIG_SYS_LBAPP1_BASE
+CONFIG_SYS_LBAPP1_BASE_PHYS
+CONFIG_SYS_LBAPP1_BR_PRELIM
+CONFIG_SYS_LBAPP1_OR_PRELIM
+CONFIG_SYS_LBAPP2_BASE
+CONFIG_SYS_LBAPP2_BASE_PHYS
+CONFIG_SYS_LBAPP2_BR_PRELIM
+CONFIG_SYS_LBAPP2_OR_PRELIM
+CONFIG_SYS_LBC0_BASE
+CONFIG_SYS_LBC0_BASE_PHYS
+CONFIG_SYS_LBC1_BASE
+CONFIG_SYS_LBC1_BASE_PHYS
+CONFIG_SYS_LBCR_ADDR
+CONFIG_SYS_LBC_ADDR
+CONFIG_SYS_LBC_BASE
+CONFIG_SYS_LBC_BASE_PHYS_LOW
+CONFIG_SYS_LBC_CACHE_BASE
+CONFIG_SYS_LBC_FLASH_BASE
+CONFIG_SYS_LBC_LBCR
+CONFIG_SYS_LBC_LCRR
+CONFIG_SYS_LBC_LSDMR_1
+CONFIG_SYS_LBC_LSDMR_2
+CONFIG_SYS_LBC_LSDMR_3
+CONFIG_SYS_LBC_LSDMR_4
+CONFIG_SYS_LBC_LSDMR_5
+CONFIG_SYS_LBC_LSDMR_ARFRSH
+CONFIG_SYS_LBC_LSDMR_COMMON
+CONFIG_SYS_LBC_LSDMR_MRW
+CONFIG_SYS_LBC_LSDMR_PCHALL
+CONFIG_SYS_LBC_LSDMR_RFEN
+CONFIG_SYS_LBC_LSRT
+CONFIG_SYS_LBC_MRTPR
+CONFIG_SYS_LBC_NONCACHE_BASE
+CONFIG_SYS_LBC_SDRAM_BASE
+CONFIG_SYS_LBC_SDRAM_BASE_PHYS
+CONFIG_SYS_LBC_SDRAM_SIZE
+CONFIG_SYS_LBLAWAR0_PRELIM
+CONFIG_SYS_LBLAWAR1_PRELIM
+CONFIG_SYS_LBLAWAR2_PRELIM
+CONFIG_SYS_LBLAWAR3_PRELIM
+CONFIG_SYS_LBLAWAR4_PRELIM
+CONFIG_SYS_LBLAWAR5_PRELIM
+CONFIG_SYS_LBLAWAR6_PRELIM
+CONFIG_SYS_LBLAWAR7_PRELIM
+CONFIG_SYS_LBLAWBAR0_PRELIM
+CONFIG_SYS_LBLAWBAR1_PRELIM
+CONFIG_SYS_LBLAWBAR2_PRELIM
+CONFIG_SYS_LBLAWBAR3_PRELIM
+CONFIG_SYS_LBLAWBAR4_PRELIM
+CONFIG_SYS_LBLAWBAR5_PRELIM
+CONFIG_SYS_LBLAWBAR6_PRELIM
+CONFIG_SYS_LBLAWBAR7_PRELIM
+CONFIG_SYS_LB_SDRAM
+CONFIG_SYS_LCD0_RST
+CONFIG_SYS_LCD1_RST
+CONFIG_SYS_LCD_BASE
+CONFIG_SYS_LCD_ENDIAN
+CONFIG_SYS_LCRR_CLKDIV
+CONFIG_SYS_LCRR_DBYP
+CONFIG_SYS_LCRR_EADC
+CONFIG_SYS_LDB_CLOCK
+CONFIG_SYS_LDSCRIPT
+CONFIG_SYS_LED_ADDR
+CONFIG_SYS_LED_BASE
+CONFIG_SYS_LED_DISP_BASE
+CONFIG_SYS_LIME_BASE
+CONFIG_SYS_LIME_BASE_0
+CONFIG_SYS_LIME_BASE_1
+CONFIG_SYS_LIME_BASE_2
+CONFIG_SYS_LIME_BASE_3
+CONFIG_SYS_LIME_CLOCK_100MHZ
+CONFIG_SYS_LIME_CLOCK_133MHZ
+CONFIG_SYS_LIME_MMR
+CONFIG_SYS_LIME_SDRAM_CLOCK
+CONFIG_SYS_LIME_SIZE
+CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
+CONFIG_SYS_LOADS_BAUD_CHANGE
+CONFIG_SYS_LOAD_ADDR
+CONFIG_SYS_LOAD_ADDR2
+CONFIG_SYS_LOCAL_CONF_REGS
+CONFIG_SYS_LONGHELP
+CONFIG_SYS_LOW
+CONFIG_SYS_LOWBOOT
+CONFIG_SYS_LOWBOOT16
+CONFIG_SYS_LOWBOOT32
+CONFIG_SYS_LOWMEM_BASE
+CONFIG_SYS_LOW_RES_TIMER
+CONFIG_SYS_LPAE_SDRAM_BASE
+CONFIG_SYS_LPC32XX_UART
+CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
+CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
+CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
+CONFIG_SYS_LS_MC_DPC_ADDR
+CONFIG_SYS_LS_MC_DPC_IN_DDR
+CONFIG_SYS_LS_MC_DPC_IN_NOR
+CONFIG_SYS_LS_MC_DPC_MAX_LENGTH
+CONFIG_SYS_LS_MC_DPL_ADDR
+CONFIG_SYS_LS_MC_DPL_IN_DDR
+CONFIG_SYS_LS_MC_DPL_IN_NOR
+CONFIG_SYS_LS_MC_DPL_MAX_LENGTH
+CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
+CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
+CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
+CONFIG_SYS_LS_MC_FW_IN_DDR
+CONFIG_SYS_LS_PPA_FW_ADDR
+CONFIG_SYS_LS_PPA_FW_IN_XIP
+CONFIG_SYS_LS_PPA_FW_IN_xxx
+CONFIG_SYS_M41T11_BASE_YEAR
+CONFIG_SYS_M41T11_EXT_CENTURY_DATA
+CONFIG_SYS_MACB0_BASE
+CONFIG_SYS_MACB1_BASE
+CONFIG_SYS_MACB2_BASE
+CONFIG_SYS_MACB3_BASE
+CONFIG_SYS_MAIN_PWR_ON
+CONFIG_SYS_MALLOC_BASE
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT
+CONFIG_SYS_MALLOC_END
+CONFIG_SYS_MALLOC_LEN
+CONFIG_SYS_MALLOC_SIMPLE
+CONFIG_SYS_MAMR
+CONFIG_SYS_MAMR_10COL
+CONFIG_SYS_MAMR_8COL
+CONFIG_SYS_MAMR_9COL
+CONFIG_SYS_MAMR_PTA
+CONFIG_SYS_MAPLE
+CONFIG_SYS_MAPLE_MEM_PHYS
+CONFIG_SYS_MAPPED_RAM_BASE
+CONFIG_SYS_MARUBUN_IO
+CONFIG_SYS_MARUBUN_MRSHPC
+CONFIG_SYS_MARUBUN_MW1
+CONFIG_SYS_MARUBUN_MW2
+CONFIG_SYS_MASK
+CONFIG_SYS_MASTER_CLOCK
+CONFIG_SYS_MATRIX_EBI0CSA_VAL
+CONFIG_SYS_MATRIX_EBICSA_VAL
+CONFIG_SYS_MATRIX_MCFG_REMAP
+CONFIG_SYS_MAXARGS
+CONFIG_SYS_MAXIDLE
+CONFIG_SYS_MAX_DATAFLASH_BANKS
+CONFIG_SYS_MAX_DDR_BAT_SIZE
+CONFIG_SYS_MAX_DOC_DEVICE
+CONFIG_SYS_MAX_FLASH_BANKS
+CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+CONFIG_SYS_MAX_FLASH_SECT
+CONFIG_SYS_MAX_I2C_BUS
+CONFIG_SYS_MAX_MTD_BANKS
+CONFIG_SYS_MAX_NAND_CHIPS
+CONFIG_SYS_MAX_NAND_DEVICE
+CONFIG_SYS_MAX_PCI_EPS
+CONFIG_SYS_MAX_RAM_SIZE
+CONFIG_SYS_MB862xx_CCF
+CONFIG_SYS_MB862xx_MMR
+CONFIG_SYS_MBAR
+CONFIG_SYS_MBAR2
+CONFIG_SYS_MBYTES_RAM
+CONFIG_SYS_MBYTES_SDRAM
+CONFIG_SYS_MCATT0_VAL
+CONFIG_SYS_MCATT1_VAL
+CONFIG_SYS_MCFRRTC_BASE
+CONFIG_SYS_MCFRTC_BASE
+CONFIG_SYS_MCF_SYNCR
+CONFIG_SYS_MCIO0_VAL
+CONFIG_SYS_MCIO1_VAL
+CONFIG_SYS_MCKR
+CONFIG_SYS_MCKR1_VAL
+CONFIG_SYS_MCKR2_VAL
+CONFIG_SYS_MCKR_CSS
+CONFIG_SYS_MCKR_VAL
+CONFIG_SYS_MCLINK_MAX
+CONFIG_SYS_MCMEM0_VAL
+CONFIG_SYS_MCMEM1_VAL
+CONFIG_SYS_MC_RSV_MEM_ALIGN
+CONFIG_SYS_MDC1_PIN
+CONFIG_SYS_MDCNFG_VAL
+CONFIG_SYS_MDC_PIN
+CONFIG_SYS_MDDRCGRP_HIPRIO_CFG
+CONFIG_SYS_MDDRCGRP_LUT0_AL
+CONFIG_SYS_MDDRCGRP_LUT0_AU
+CONFIG_SYS_MDDRCGRP_LUT0_ML
+CONFIG_SYS_MDDRCGRP_LUT0_MU
+CONFIG_SYS_MDDRCGRP_LUT1_AL
+CONFIG_SYS_MDDRCGRP_LUT1_AU
+CONFIG_SYS_MDDRCGRP_LUT1_ML
+CONFIG_SYS_MDDRCGRP_LUT1_MU
+CONFIG_SYS_MDDRCGRP_LUT2_AL
+CONFIG_SYS_MDDRCGRP_LUT2_AU
+CONFIG_SYS_MDDRCGRP_LUT2_ML
+CONFIG_SYS_MDDRCGRP_LUT2_MU
+CONFIG_SYS_MDDRCGRP_LUT3_AL
+CONFIG_SYS_MDDRCGRP_LUT3_AU
+CONFIG_SYS_MDDRCGRP_LUT3_ML
+CONFIG_SYS_MDDRCGRP_LUT3_MU
+CONFIG_SYS_MDDRCGRP_LUT4_AL
+CONFIG_SYS_MDDRCGRP_LUT4_AU
+CONFIG_SYS_MDDRCGRP_LUT4_ML
+CONFIG_SYS_MDDRCGRP_LUT4_MU
+CONFIG_SYS_MDDRCGRP_PM_CFG1
+CONFIG_SYS_MDDRCGRP_PM_CFG2
+CONFIG_SYS_MDDRC_SYS_CFG
+CONFIG_SYS_MDDRC_SYS_CFG_ALT1
+CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA
+CONFIG_SYS_MDDRC_SYS_CFG_EN
+CONFIG_SYS_MDDRC_TIME_CFG0
+CONFIG_SYS_MDDRC_TIME_CFG0_ALT1
+CONFIG_SYS_MDDRC_TIME_CFG1
+CONFIG_SYS_MDDRC_TIME_CFG1_ALT1
+CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA
+CONFIG_SYS_MDDRC_TIME_CFG2
+CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
+CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA
+CONFIG_SYS_MDIO1_OFFSET
+CONFIG_SYS_MDIO1_PIN
+CONFIG_SYS_MDIO_BASE_ADDR
+CONFIG_SYS_MDIO_PIN
+CONFIG_SYS_MDMRS_VAL
+CONFIG_SYS_MDREFR_VAL
+CONFIG_SYS_MEASURE_CPUCLK
+CONFIG_SYS_MECR_VAL
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+CONFIG_SYS_MEMORY_BASE
+CONFIG_SYS_MEMORY_SIZE
+CONFIG_SYS_MEMORY_TOP
+CONFIG_SYS_MEMTEST_END
+CONFIG_SYS_MEMTEST_SCRATCH
+CONFIG_SYS_MEMTEST_START
+CONFIG_SYS_MEM_MAP
+CONFIG_SYS_MEM_RESERVE_SECURE
+CONFIG_SYS_MEM_SIZE
+CONFIG_SYS_MEM_TOP_HIDE
+CONFIG_SYS_MFD
+CONFIG_SYS_MHZ
+CONFIG_SYS_MICRON_BMODE
+CONFIG_SYS_MICRON_BMODE_PARAM
+CONFIG_SYS_MICRON_BMODE_RSTDLL
+CONFIG_SYS_MICRON_EMODE
+CONFIG_SYS_MICRON_EMODE2
+CONFIG_SYS_MICRON_EMODE3
+CONFIG_SYS_MICRON_EMODE_PARAM
+CONFIG_SYS_MICRON_EMR
+CONFIG_SYS_MICRON_EMR2
+CONFIG_SYS_MICRON_EMR3
+CONFIG_SYS_MICRON_EMR_OCD
+CONFIG_SYS_MICRON_INIT_DEV_OP
+CONFIG_SYS_MII_MODE
+CONFIG_SYS_MIPS_CACHE_MODE
+CONFIG_SYS_MIPS_TIMER_FREQ
+CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
+CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
+CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
+CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+CONFIG_SYS_MMC_BASE
+CONFIG_SYS_MMC_CD_PIN
+CONFIG_SYS_MMC_CLK_OD
+CONFIG_SYS_MMC_ENV_DEV
+CONFIG_SYS_MMC_ENV_PART
+CONFIG_SYS_MMC_IMG_LOAD_PART
+CONFIG_SYS_MMC_MAX_BLK_COUNT
+CONFIG_SYS_MMC_MAX_DEVICE
+CONFIG_SYS_MMC_U_BOOT_DST
+CONFIG_SYS_MMC_U_BOOT_OFFS
+CONFIG_SYS_MMC_U_BOOT_SIZE
+CONFIG_SYS_MMC_U_BOOT_START
+CONFIG_SYS_MM_TOP_HIDE
+CONFIG_SYS_MONITOR_
+CONFIG_SYS_MONITOR_BASE
+CONFIG_SYS_MONITOR_BASE_EARLY
+CONFIG_SYS_MONITOR_LEN
+CONFIG_SYS_MONITOR_SEC
+CONFIG_SYS_MOR_VAL
+CONFIG_SYS_MPC512X_CLKIN
+CONFIG_SYS_MPC512x_USB1_ADDR
+CONFIG_SYS_MPC512x_USB1_OFFSET
+CONFIG_SYS_MPC5XXX_CLKIN
+CONFIG_SYS_MPC83xx_DMA_ADDR
+CONFIG_SYS_MPC83xx_DMA_OFFSET
+CONFIG_SYS_MPC83xx_ESDHC_ADDR
+CONFIG_SYS_MPC83xx_ESDHC_OFFSET
+CONFIG_SYS_MPC83xx_USB1_ADDR
+CONFIG_SYS_MPC83xx_USB1_OFFSET
+CONFIG_SYS_MPC83xx_USB2_ADDR
+CONFIG_SYS_MPC83xx_USB2_OFFSET
+CONFIG_SYS_MPC85XX_NO_RESETVEC
+CONFIG_SYS_MPC85xx_CPM_ADDR
+CONFIG_SYS_MPC85xx_CPM_OFFSET
+CONFIG_SYS_MPC85xx_DMA
+CONFIG_SYS_MPC85xx_DMA1_OFFSET
+CONFIG_SYS_MPC85xx_DMA2_OFFSET
+CONFIG_SYS_MPC85xx_DMA3_OFFSET
+CONFIG_SYS_MPC85xx_DMA_ADDR
+CONFIG_SYS_MPC85xx_DMA_OFFSET
+CONFIG_SYS_MPC85xx_ECM_ADDR
+CONFIG_SYS_MPC85xx_ECM_OFFSET
+CONFIG_SYS_MPC85xx_ESDHC_ADDR
+CONFIG_SYS_MPC85xx_ESDHC_OFFSET
+CONFIG_SYS_MPC85xx_ESPI_ADDR
+CONFIG_SYS_MPC85xx_ESPI_OFFSET
+CONFIG_SYS_MPC85xx_GPIO3_ADDR
+CONFIG_SYS_MPC85xx_GPIO_ADDR
+CONFIG_SYS_MPC85xx_GPIO_OFFSET
+CONFIG_SYS_MPC85xx_GUTS_ADDR
+CONFIG_SYS_MPC85xx_GUTS_OFFSET
+CONFIG_SYS_MPC85xx_IFC_OFFSET
+CONFIG_SYS_MPC85xx_L2_ADDR
+CONFIG_SYS_MPC85xx_L2_OFFSET
+CONFIG_SYS_MPC85xx_LBC_OFFSET
+CONFIG_SYS_MPC85xx_PCI1_OFFSET
+CONFIG_SYS_MPC85xx_PCI2_OFFSET
+CONFIG_SYS_MPC85xx_PCIE
+CONFIG_SYS_MPC85xx_PCIE1_OFFSET
+CONFIG_SYS_MPC85xx_PCIE2_OFFSET
+CONFIG_SYS_MPC85xx_PCIE3_OFFSET
+CONFIG_SYS_MPC85xx_PCIE4_OFFSET
+CONFIG_SYS_MPC85xx_PCIX2_ADDR
+CONFIG_SYS_MPC85xx_PCIX2_OFFSET
+CONFIG_SYS_MPC85xx_PCIX_ADDR
+CONFIG_SYS_MPC85xx_PCIX_OFFSET
+CONFIG_SYS_MPC85xx_PIC_OFFSET
+CONFIG_SYS_MPC85xx_QE_OFFSET
+CONFIG_SYS_MPC85xx_SATA
+CONFIG_SYS_MPC85xx_SATA1_ADDR
+CONFIG_SYS_MPC85xx_SATA1_OFFSET
+CONFIG_SYS_MPC85xx_SATA2_ADDR
+CONFIG_SYS_MPC85xx_SATA2_OFFSET
+CONFIG_SYS_MPC85xx_SCFG
+CONFIG_SYS_MPC85xx_SCFG_OFFSET
+CONFIG_SYS_MPC85xx_SERDES1_ADDR
+CONFIG_SYS_MPC85xx_SERDES1_OFFSET
+CONFIG_SYS_MPC85xx_SERDES2_ADDR
+CONFIG_SYS_MPC85xx_SERDES2_OFFSET
+CONFIG_SYS_MPC85xx_TDM_OFFSET
+CONFIG_SYS_MPC85xx_USB
+CONFIG_SYS_MPC85xx_USB1_ADDR
+CONFIG_SYS_MPC85xx_USB1_OFFSET
+CONFIG_SYS_MPC85xx_USB1_PHY_ADDR
+CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET
+CONFIG_SYS_MPC85xx_USB2_ADDR
+CONFIG_SYS_MPC85xx_USB2_OFFSET
+CONFIG_SYS_MPC85xx_USB2_PHY_ADDR
+CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET
+CONFIG_SYS_MPC86xx_DMA_ADDR
+CONFIG_SYS_MPC86xx_DMA_OFFSET
+CONFIG_SYS_MPC86xx_PCI1_OFFSET
+CONFIG_SYS_MPC86xx_PCI2_OFFSET
+CONFIG_SYS_MPC86xx_PCIE1_OFFSET
+CONFIG_SYS_MPC86xx_PCIE2_OFFSET
+CONFIG_SYS_MPC86xx_PIC_OFFSET
+CONFIG_SYS_MPC8xxx_DDR2_OFFSET
+CONFIG_SYS_MPC8xxx_DDR3_OFFSET
+CONFIG_SYS_MPC8xxx_DDR_OFFSET
+CONFIG_SYS_MPC8xxx_GUTS_ADDR
+CONFIG_SYS_MPC8xxx_PIC_ADDR
+CONFIG_SYS_MPC92469AC
+CONFIG_SYS_MPEG_BASE
+CONFIG_SYS_MPEG_SIZE
+CONFIG_SYS_MPTPR
+CONFIG_SYS_MPTPR_1BK_2K
+CONFIG_SYS_MPTPR_1BK_4K
+CONFIG_SYS_MPTPR_1BK_8K
+CONFIG_SYS_MPTPR_2BK_2K
+CONFIG_SYS_MPTPR_2BK_4K
+CONFIG_SYS_MPTPR_2BK_8K
+CONFIG_SYS_MPUCLK
+CONFIG_SYS_MRAM_BASE
+CONFIG_SYS_MRAM_SIZE
+CONFIG_SYS_MRS_OFFS
+CONFIG_SYS_MSC0_VAL
+CONFIG_SYS_MSC1_VAL
+CONFIG_SYS_MSC2_VAL
+CONFIG_SYS_MTDPARTS_RUNTIME
+CONFIG_SYS_MVFS
+CONFIG_SYS_MX5_CLK32
+CONFIG_SYS_MX5_HCLK
+CONFIG_SYS_MX6_CLK32
+CONFIG_SYS_MX6_HCLK
+CONFIG_SYS_MX7_CLK32
+CONFIG_SYS_MX7_HCLK
+CONFIG_SYS_MXC_I2C1_SLAVE
+CONFIG_SYS_MXC_I2C1_SPEED
+CONFIG_SYS_MXC_I2C2_SLAVE
+CONFIG_SYS_MXC_I2C2_SPEED
+CONFIG_SYS_MXC_I2C3_SLAVE
+CONFIG_SYS_MXC_I2C3_SPEED
+CONFIG_SYS_MXC_I2C4_SLAVE
+CONFIG_SYS_MXC_I2C4_SPEED
+CONFIG_SYS_MXS_VDD5V_ONLY
+CONFIG_SYS_NAND2_ADDR
+CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+CONFIG_SYS_NAND_4_ADDR_CYCLE
+CONFIG_SYS_NAND_5_ADDR_CYCLE
+CONFIG_SYS_NAND_ACTL_ALE
+CONFIG_SYS_NAND_ACTL_CLE
+CONFIG_SYS_NAND_ACTL_DELAY
+CONFIG_SYS_NAND_ACTL_NCE
+CONFIG_SYS_NAND_ADDR
+CONFIG_SYS_NAND_ALE
+CONFIG_SYS_NAND_AMASK
+CONFIG_SYS_NAND_BAD_BLOCK_POS
+CONFIG_SYS_NAND_BASE
+CONFIG_SYS_NAND_BASE2
+CONFIG_SYS_NAND_BASE_LIST
+CONFIG_SYS_NAND_BASE_PHYS
+CONFIG_SYS_NAND_BCR
+CONFIG_SYS_NAND_BLOCK_SIZE
+CONFIG_SYS_NAND_BOOT
+CONFIG_SYS_NAND_BR_PRELIM
+CONFIG_SYS_NAND_BUSWIDTH_16
+CONFIG_SYS_NAND_CE
+CONFIG_SYS_NAND_CLE
+CONFIG_SYS_NAND_CS
+CONFIG_SYS_NAND_CSOR
+CONFIG_SYS_NAND_CSPR
+CONFIG_SYS_NAND_CSPR_EXT
+CONFIG_SYS_NAND_DATA_BASE
+CONFIG_SYS_NAND_DBW_16
+CONFIG_SYS_NAND_DBW_8
+CONFIG_SYS_NAND_DDR_LAW
+CONFIG_SYS_NAND_ECCBYTES
+CONFIG_SYS_NAND_ECCPOS
+CONFIG_SYS_NAND_ECCSIZE
+CONFIG_SYS_NAND_ECCSTEPS
+CONFIG_SYS_NAND_ECCTOTAL
+CONFIG_SYS_NAND_ECC_BASE
+CONFIG_SYS_NAND_ENABLE_PIN
+CONFIG_SYS_NAND_ENABLE_PIN_SPL
+CONFIG_SYS_NAND_FTIM0
+CONFIG_SYS_NAND_FTIM1
+CONFIG_SYS_NAND_FTIM2
+CONFIG_SYS_NAND_FTIM3
+CONFIG_SYS_NAND_HW_ECC
+CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+CONFIG_SYS_NAND_LARGEPAGE
+CONFIG_SYS_NAND_LBLAWAR_PRELIM
+CONFIG_SYS_NAND_LBLAWBAR_PRELIM
+CONFIG_SYS_NAND_MASK_ALE
+CONFIG_SYS_NAND_MASK_CLE
+CONFIG_SYS_NAND_MAX_CHIPS
+CONFIG_SYS_NAND_MAX_ECCPOS
+CONFIG_SYS_NAND_MAX_OOBFREE
+CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
+CONFIG_SYS_NAND_NO_SUBPAGE
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+CONFIG_SYS_NAND_ONFI_DETECTION
+CONFIG_SYS_NAND_OOBSIZE
+CONFIG_SYS_NAND_OR_PRELIM
+CONFIG_SYS_NAND_PAGE_2K
+CONFIG_SYS_NAND_PAGE_4K
+CONFIG_SYS_NAND_PAGE_COUNT
+CONFIG_SYS_NAND_PAGE_SIZE
+CONFIG_SYS_NAND_QUIET
+CONFIG_SYS_NAND_RDY
+CONFIG_SYS_NAND_READY_PIN
+CONFIG_SYS_NAND_REGS_BASE
+CONFIG_SYS_NAND_SELECT_DEVICE
+CONFIG_SYS_NAND_SIZE
+CONFIG_SYS_NAND_SKIP_BAD_DOT_I
+CONFIG_SYS_NAND_SPL_KERNEL_OFFS
+CONFIG_SYS_NAND_SPL_SIZE
+CONFIG_SYS_NAND_USE_FLASH_BBT
+CONFIG_SYS_NAND_U_BOOT_DST
+CONFIG_SYS_NAND_U_BOOT_RELOC
+CONFIG_SYS_NAND_U_BOOT_RELOC_SP
+CONFIG_SYS_NAND_U_BOOT_SIZE
+CONFIG_SYS_NAND_U_BOOT_START
+CONFIG_SYS_NAND_WINDOW_SIZE
+CONFIG_SYS_NDFC_EBC0_CFG
+CONFIG_SYS_NETA_INTERFACE_TYPE
+CONFIG_SYS_NONCACHED_MEMORY
+CONFIG_SYS_NOR0_CSPR
+CONFIG_SYS_NOR0_CSPR_EARLY
+CONFIG_SYS_NOR0_CSPR_EXT
+CONFIG_SYS_NOR1SZ
+CONFIG_SYS_NOR1_CSPR
+CONFIG_SYS_NOR1_CSPR_EARLY
+CONFIG_SYS_NOR1_CSPR_EXT
+CONFIG_SYS_NOR_AMASK
+CONFIG_SYS_NOR_AMASK_EARLY
+CONFIG_SYS_NOR_BR_PRELIM
+CONFIG_SYS_NOR_CS
+CONFIG_SYS_NOR_CSOR
+CONFIG_SYS_NOR_CSPR
+CONFIG_SYS_NOR_CSPR_EXT
+CONFIG_SYS_NOR_FTIM0
+CONFIG_SYS_NOR_FTIM1
+CONFIG_SYS_NOR_FTIM2
+CONFIG_SYS_NOR_FTIM3
+CONFIG_SYS_NOR_OR_PRELIM
+CONFIG_SYS_NO_DCACHE
+CONFIG_SYS_NR_PIOS
+CONFIG_SYS_NR_VM_REGIONS
+CONFIG_SYS_NS16550_CLK
+CONFIG_SYS_NS16550_CLK_DIV
+CONFIG_SYS_NS16550_COM1
+CONFIG_SYS_NS16550_COM2
+CONFIG_SYS_NS16550_COM3
+CONFIG_SYS_NS16550_COM4
+CONFIG_SYS_NS16550_COM5
+CONFIG_SYS_NS16550_COM6
+CONFIG_SYS_NS16550_IER
+CONFIG_SYS_NS16550_MEM32
+CONFIG_SYS_NS16550_PORT_MAPPED
+CONFIG_SYS_NS16550_REG_SIZE
+CONFIG_SYS_NS16550_SERIAL
+CONFIG_SYS_NS87308_CS0_BASE
+CONFIG_SYS_NS87308_CS0_CONF
+CONFIG_SYS_NS87308_CS1_BASE
+CONFIG_SYS_NS87308_CS1_CONF
+CONFIG_SYS_NS87308_CS2_BASE
+CONFIG_SYS_NS87308_CS2_CONF
+CONFIG_SYS_NS87308_FDC
+CONFIG_SYS_NS87308_FDC_BASE
+CONFIG_SYS_NS87308_GPIO
+CONFIG_SYS_NS87308_GPIO_BASE
+CONFIG_SYS_NS87308_KBC1
+CONFIG_SYS_NS87308_KBC1_BASE
+CONFIG_SYS_NS87308_KBC2
+CONFIG_SYS_NS87308_LPT_BASE
+CONFIG_SYS_NS87308_MOUSE
+CONFIG_SYS_NS87308_PARP
+CONFIG_SYS_NS87308_PMC1
+CONFIG_SYS_NS87308_PMC2
+CONFIG_SYS_NS87308_PMC3
+CONFIG_SYS_NS87308_POWRMAN
+CONFIG_SYS_NS87308_PS2MOD
+CONFIG_SYS_NS87308_PWMAN_BASE
+CONFIG_SYS_NS87308_RARP
+CONFIG_SYS_NS87308_RTC_APC
+CONFIG_SYS_NS87308_RTC_BASE
+CONFIG_SYS_NS87308_UART1
+CONFIG_SYS_NS87308_UART1_BASE
+CONFIG_SYS_NS87308_UART2
+CONFIG_SYS_NS87308_UART2_BASE
+CONFIG_SYS_NUM_ADDR_MAP
+CONFIG_SYS_NUM_CPC
+CONFIG_SYS_NUM_FM1_10GEC
+CONFIG_SYS_NUM_FM1_DTSEC
+CONFIG_SYS_NUM_FM2_10GEC
+CONFIG_SYS_NUM_FM2_DTSEC
+CONFIG_SYS_NUM_FMAN
+CONFIG_SYS_NUM_I2C_BUSES
+CONFIG_SYS_NUM_IRQS
+CONFIG_SYS_NVRAM_ACCESS_ROUTINE
+CONFIG_SYS_NVRAM_BASE
+CONFIG_SYS_NVRAM_BASE_ADDR
+CONFIG_SYS_NVRAM_SIZE
+CONFIG_SYS_OBIR
+CONFIG_SYS_OCM_BASE
+CONFIG_SYS_OCM_DATA_ADDR
+CONFIG_SYS_OCM_DATA_SIZE
+CONFIG_SYS_OCM_SIZE
+CONFIG_SYS_OCM_STATUS_ADDR
+CONFIG_SYS_OCM_STATUS_FAIL
+CONFIG_SYS_OCM_STATUS_MASK
+CONFIG_SYS_OCM_STATUS_OK
+CONFIG_SYS_OHCI_BE_CONTROLLER
+CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+CONFIG_SYS_OHCI_USE_NPS
+CONFIG_SYS_OMAP24_I2C_SLAVE
+CONFIG_SYS_OMAP24_I2C_SLAVE1
+CONFIG_SYS_OMAP24_I2C_SLAVE2
+CONFIG_SYS_OMAP24_I2C_SLAVE3
+CONFIG_SYS_OMAP24_I2C_SLAVE4
+CONFIG_SYS_OMAP24_I2C_SPEED
+CONFIG_SYS_OMAP24_I2C_SPEED1
+CONFIG_SYS_OMAP24_I2C_SPEED2
+CONFIG_SYS_OMAP24_I2C_SPEED3
+CONFIG_SYS_OMAP24_I2C_SPEED4
+CONFIG_SYS_OMAP24_I2C_SPEED_PSOC
+CONFIG_SYS_OMAP_ABE_SYSCK
+CONFIG_SYS_ONENAND_BASE
+CONFIG_SYS_ONENAND_BLOCK_SIZE
+CONFIG_SYS_ONENAND_PAGE_SIZE
+CONFIG_SYS_OPENRISC_TMR_HZ
+CONFIG_SYS_OPER_FLASH
+CONFIG_SYS_OR0_64M
+CONFIG_SYS_OR0_8M
+CONFIG_SYS_OR0_PRELIM
+CONFIG_SYS_OR0_REMAP
+CONFIG_SYS_OR1
+CONFIG_SYS_OR10_PRELIM
+CONFIG_SYS_OR11_PRELIM
+CONFIG_SYS_OR1_PRELIM
+CONFIG_SYS_OR1_REMAP
+CONFIG_SYS_OR2_PRELIM
+CONFIG_SYS_OR3_CAN
+CONFIG_SYS_OR3_PRELIM
+CONFIG_SYS_OR4_PRELIM
+CONFIG_SYS_OR5_ISP1362
+CONFIG_SYS_OR5_PRELIM
+CONFIG_SYS_OR5_REMAP
+CONFIG_SYS_OR6_64M
+CONFIG_SYS_OR6_8M
+CONFIG_SYS_OR6_PRELIM
+CONFIG_SYS_OR7_PRELIM
+CONFIG_SYS_OR8_PRELIM
+CONFIG_SYS_OR9_PRELIM
+CONFIG_SYS_OR_TIMING_FLASH
+CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
+CONFIG_SYS_OR_TIMING_MRAM
+CONFIG_SYS_OR_TIMING_SDRAM
+CONFIG_SYS_OSC0_HZ
+CONFIG_SYS_OSC1_HZ
+CONFIG_SYS_OSCIN_FREQ
+CONFIG_SYS_OSC_CLK
+CONFIG_SYS_OSD_DH
+CONFIG_SYS_OSD_SCREENS
+CONFIG_SYS_OSPR_OFFSET
+CONFIG_SYS_PACNT
+CONFIG_SYS_PADAT
+CONFIG_SYS_PADDR
+CONFIG_SYS_PAGE_SIZE
+CONFIG_SYS_PAMU_ADDR
+CONFIG_SYS_PASPAR
+CONFIG_SYS_PAXE_BASE
+CONFIG_SYS_PAXE_SIZE
+CONFIG_SYS_PBCNT
+CONFIG_SYS_PBDAT
+CONFIG_SYS_PBDDR
+CONFIG_SYS_PBI_FLASH_BASE
+CONFIG_SYS_PBI_FLASH_WINDOW
+CONFIG_SYS_PBSIZE
+CONFIG_SYS_PB_LED
+CONFIG_SYS_PCA953X_BRD_CFG0
+CONFIG_SYS_PCA953X_BRD_CFG1
+CONFIG_SYS_PCA953X_BRD_CFG2
+CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS
+CONFIG_SYS_PCA953X_C0_SER0_EN
+CONFIG_SYS_PCA953X_C0_SER0_MODE
+CONFIG_SYS_PCA953X_C0_SER1_EN
+CONFIG_SYS_PCA953X_C0_SER1_MODE
+CONFIG_SYS_PCA953X_C0_VCORE_VID2
+CONFIG_SYS_PCA953X_C0_VCORE_VID3
+CONFIG_SYS_PCA953X_EREADY
+CONFIG_SYS_PCA953X_FLASH_PASS_CS
+CONFIG_SYS_PCA953X_GPIO_VPX0
+CONFIG_SYS_PCA953X_GPIO_VPX1
+CONFIG_SYS_PCA953X_GPIO_VPX2
+CONFIG_SYS_PCA953X_GPIO_VPX3
+CONFIG_SYS_PCA953X_MC_GPIO0
+CONFIG_SYS_PCA953X_MC_GPIO1
+CONFIG_SYS_PCA953X_MC_GPIO2
+CONFIG_SYS_PCA953X_MC_GPIO3
+CONFIG_SYS_PCA953X_MC_GPIO4
+CONFIG_SYS_PCA953X_MC_GPIO5
+CONFIG_SYS_PCA953X_MC_GPIO6
+CONFIG_SYS_PCA953X_MC_GPIO7
+CONFIG_SYS_PCA953X_MONARCH
+CONFIG_SYS_PCA953X_NVM_WP
+CONFIG_SYS_PCA953X_P0_GA0
+CONFIG_SYS_PCA953X_P0_GA1
+CONFIG_SYS_PCA953X_P0_GA2
+CONFIG_SYS_PCA953X_P0_GA3
+CONFIG_SYS_PCA953X_P0_GA4
+CONFIG_SYS_PCA953X_P0_GAP
+CONFIG_SYS_PCA953X_P14_IO0
+CONFIG_SYS_PCA953X_P14_IO1
+CONFIG_SYS_PCA953X_P14_IO2
+CONFIG_SYS_PCA953X_P14_IO3
+CONFIG_SYS_PCA953X_P14_IO4
+CONFIG_SYS_PCA953X_P14_IO5
+CONFIG_SYS_PCA953X_P14_IO6
+CONFIG_SYS_PCA953X_P14_IO7
+CONFIG_SYS_PCA953X_P1_SYSEN
+CONFIG_SYS_PCA953X_PLUG_GPIO0
+CONFIG_SYS_PCA953X_PMC0_EREADY
+CONFIG_SYS_PCA953X_PMC0_MONARCH
+CONFIG_SYS_PCA953X_PMC_EREADY
+CONFIG_SYS_PCA953X_PMC_MONARCH
+CONFIG_SYS_PCA953X_PMC_PRESENT
+CONFIG_SYS_PCA953X_VPX_FRU_WRCTL
+CONFIG_SYS_PCA953X_VPX_GPIO0
+CONFIG_SYS_PCA953X_VPX_GPIO1
+CONFIG_SYS_PCA953X_VPX_GPIO2
+CONFIG_SYS_PCA953X_VPX_GPIO3
+CONFIG_SYS_PCA953X_XMC0_BIST
+CONFIG_SYS_PCA953X_XMC0_MVMR0
+CONFIG_SYS_PCA953X_XMC0_ROOT0
+CONFIG_SYS_PCA953X_XMC0_WAKE
+CONFIG_SYS_PCA953X_XMC_BIST
+CONFIG_SYS_PCA953X_XMC_GA0
+CONFIG_SYS_PCA953X_XMC_GA1
+CONFIG_SYS_PCA953X_XMC_GA2
+CONFIG_SYS_PCA953X_XMC_PRESENT
+CONFIG_SYS_PCA953X_XMC_ROOT0
+CONFIG_SYS_PCA953X_XMC_WAKE
+CONFIG_SYS_PCCNT
+CONFIG_SYS_PCDAT
+CONFIG_SYS_PCDDR
+CONFIG_SYS_PCI
+CONFIG_SYS_PCI0_IO_SPACE
+CONFIG_SYS_PCI1_ADDR
+CONFIG_SYS_PCI1_IO_BASE
+CONFIG_SYS_PCI1_IO_BUS
+CONFIG_SYS_PCI1_IO_PHYS
+CONFIG_SYS_PCI1_IO_SIZE
+CONFIG_SYS_PCI1_IO_VIRT
+CONFIG_SYS_PCI1_MEM_BASE
+CONFIG_SYS_PCI1_MEM_BUS
+CONFIG_SYS_PCI1_MEM_PHYS
+CONFIG_SYS_PCI1_MEM_SIZE
+CONFIG_SYS_PCI1_MEM_VIRT
+CONFIG_SYS_PCI1_MMIO_BASE
+CONFIG_SYS_PCI1_MMIO_PHYS
+CONFIG_SYS_PCI1_MMIO_SIZE
+CONFIG_SYS_PCI2_ADDR
+CONFIG_SYS_PCI2_IO_BASE
+CONFIG_SYS_PCI2_IO_BUS
+CONFIG_SYS_PCI2_IO_PHYS
+CONFIG_SYS_PCI2_IO_SIZE
+CONFIG_SYS_PCI2_IO_VIRT
+CONFIG_SYS_PCI2_MEM_BASE
+CONFIG_SYS_PCI2_MEM_BUS
+CONFIG_SYS_PCI2_MEM_PHYS
+CONFIG_SYS_PCI2_MEM_SIZE
+CONFIG_SYS_PCI2_MEM_VIRT
+CONFIG_SYS_PCI2_MMIO_BASE
+CONFIG_SYS_PCI2_MMIO_PHYS
+CONFIG_SYS_PCI2_MMIO_SIZE
+CONFIG_SYS_PCI64_MEMORY_BUS
+CONFIG_SYS_PCI9054_IOBASE
+CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+CONFIG_SYS_PCIE
+CONFIG_SYS_PCIE0_CFGBASE
+CONFIG_SYS_PCIE0_CFGMASK
+CONFIG_SYS_PCIE0_MEMBASE
+CONFIG_SYS_PCIE0_REGBASE
+CONFIG_SYS_PCIE0_UTLBASE
+CONFIG_SYS_PCIE0_XCFGBASE
+CONFIG_SYS_PCIE1_ADDR
+CONFIG_SYS_PCIE1_BASE
+CONFIG_SYS_PCIE1_CFGBASE
+CONFIG_SYS_PCIE1_CFGMASK
+CONFIG_SYS_PCIE1_CFG_BASE
+CONFIG_SYS_PCIE1_CFG_SIZE
+CONFIG_SYS_PCIE1_IO_BASE
+CONFIG_SYS_PCIE1_IO_BUS
+CONFIG_SYS_PCIE1_IO_PHYS
+CONFIG_SYS_PCIE1_IO_PHYS_LOW
+CONFIG_SYS_PCIE1_IO_SIZE
+CONFIG_SYS_PCIE1_IO_VIRT
+CONFIG_SYS_PCIE1_MEMBASE
+CONFIG_SYS_PCIE1_MEM_BASE
+CONFIG_SYS_PCIE1_MEM_BUS
+CONFIG_SYS_PCIE1_MEM_PHYS
+CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
+CONFIG_SYS_PCIE1_MEM_PHYS_LOW
+CONFIG_SYS_PCIE1_MEM_SIZE
+CONFIG_SYS_PCIE1_MEM_VIRT
+CONFIG_SYS_PCIE1_NAME
+CONFIG_SYS_PCIE1_PHYS_ADDR
+CONFIG_SYS_PCIE1_PHYS_BASE
+CONFIG_SYS_PCIE1_PHYS_SIZE
+CONFIG_SYS_PCIE1_REGBASE
+CONFIG_SYS_PCIE1_UTLBASE
+CONFIG_SYS_PCIE1_VIRT_ADDR
+CONFIG_SYS_PCIE1_XCFGBASE
+CONFIG_SYS_PCIE2_ADDR
+CONFIG_SYS_PCIE2_BASE
+CONFIG_SYS_PCIE2_CFGBASE
+CONFIG_SYS_PCIE2_CFG_BASE
+CONFIG_SYS_PCIE2_CFG_SIZE
+CONFIG_SYS_PCIE2_IO_BASE
+CONFIG_SYS_PCIE2_IO_BUS
+CONFIG_SYS_PCIE2_IO_PHYS
+CONFIG_SYS_PCIE2_IO_PHYS_LOW
+CONFIG_SYS_PCIE2_IO_SIZE
+CONFIG_SYS_PCIE2_IO_VIRT
+CONFIG_SYS_PCIE2_MEM_BASE
+CONFIG_SYS_PCIE2_MEM_BUS
+CONFIG_SYS_PCIE2_MEM_PHYS
+CONFIG_SYS_PCIE2_MEM_PHYS_HIGH
+CONFIG_SYS_PCIE2_MEM_PHYS_LOW
+CONFIG_SYS_PCIE2_MEM_SIZE
+CONFIG_SYS_PCIE2_MEM_VIRT
+CONFIG_SYS_PCIE2_NAME
+CONFIG_SYS_PCIE2_PHYS_ADDR
+CONFIG_SYS_PCIE2_PHYS_BASE
+CONFIG_SYS_PCIE2_PHYS_SIZE
+CONFIG_SYS_PCIE2_REGBASE
+CONFIG_SYS_PCIE2_VIRT_ADDR
+CONFIG_SYS_PCIE2_XCFGBASE
+CONFIG_SYS_PCIE3_ADDR
+CONFIG_SYS_PCIE3_IO_BUS
+CONFIG_SYS_PCIE3_IO_PHYS
+CONFIG_SYS_PCIE3_IO_SIZE
+CONFIG_SYS_PCIE3_IO_VIRT
+CONFIG_SYS_PCIE3_MEM_BUS
+CONFIG_SYS_PCIE3_MEM_BUS2
+CONFIG_SYS_PCIE3_MEM_PHYS
+CONFIG_SYS_PCIE3_MEM_PHYS2
+CONFIG_SYS_PCIE3_MEM_SIZE
+CONFIG_SYS_PCIE3_MEM_SIZE2
+CONFIG_SYS_PCIE3_MEM_VIRT
+CONFIG_SYS_PCIE3_MEM_VIRT2
+CONFIG_SYS_PCIE3_NAME
+CONFIG_SYS_PCIE3_PHYS_ADDR
+CONFIG_SYS_PCIE3_PHYS_SIZE
+CONFIG_SYS_PCIE4_ADDR
+CONFIG_SYS_PCIE4_IO_BUS
+CONFIG_SYS_PCIE4_IO_PHYS
+CONFIG_SYS_PCIE4_IO_SIZE
+CONFIG_SYS_PCIE4_IO_VIRT
+CONFIG_SYS_PCIE4_MEM_BUS
+CONFIG_SYS_PCIE4_MEM_PHYS
+CONFIG_SYS_PCIE4_MEM_SIZE
+CONFIG_SYS_PCIE4_MEM_VIRT
+CONFIG_SYS_PCIE4_NAME
+CONFIG_SYS_PCIE4_PHYS_ADDR
+CONFIG_SYS_PCIE4_PHYS_SIZE
+CONFIG_SYS_PCIE_ADDR_HIGH
+CONFIG_SYS_PCIE_BASE
+CONFIG_SYS_PCIE_CFG0_PHYS_OFF
+CONFIG_SYS_PCIE_CFG0_SIZE
+CONFIG_SYS_PCIE_CFG1_PHYS_OFF
+CONFIG_SYS_PCIE_CFG1_SIZE
+CONFIG_SYS_PCIE_INBOUND_BASE
+CONFIG_SYS_PCIE_IO_BUS
+CONFIG_SYS_PCIE_IO_PHYS_OFF
+CONFIG_SYS_PCIE_IO_SIZE
+CONFIG_SYS_PCIE_MEMBASE
+CONFIG_SYS_PCIE_MEMSIZE
+CONFIG_SYS_PCIE_MEM_BUS
+CONFIG_SYS_PCIE_MEM_PHYS_OFF
+CONFIG_SYS_PCIE_MEM_SIZE
+CONFIG_SYS_PCIE_MMAP_SIZE
+CONFIG_SYS_PCIE_NR_PORTS
+CONFIG_SYS_PCIE_PHYS
+CONFIG_SYS_PCIE_VIRT
+CONFIG_SYS_PCIMSK0_MASK
+CONFIG_SYS_PCIMSK1_MASK
+CONFIG_SYS_PCISPEED_66
+CONFIG_SYS_PCI_64BIT
+CONFIG_SYS_PCI_BAR0
+CONFIG_SYS_PCI_BAR1
+CONFIG_SYS_PCI_BAR2
+CONFIG_SYS_PCI_BAR3
+CONFIG_SYS_PCI_BAR4
+CONFIG_SYS_PCI_BAR5
+CONFIG_SYS_PCI_BASE
+CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
+CONFIG_SYS_PCI_CACHE_LINE_SIZE
+CONFIG_SYS_PCI_CFG_BASE
+CONFIG_SYS_PCI_CFG_BUS
+CONFIG_SYS_PCI_CFG_PHYS
+CONFIG_SYS_PCI_CFG_SIZE
+CONFIG_SYS_PCI_CLASSCODE
+CONFIG_SYS_PCI_CLASSCODE_MONARCH
+CONFIG_SYS_PCI_CLASSCODE_NONMONARCH
+CONFIG_SYS_PCI_CON_DEVICE
+CONFIG_SYS_PCI_EP_MEMORY_BASE
+CONFIG_SYS_PCI_FORCE_PCI_CONV
+CONFIG_SYS_PCI_IO_BASE
+CONFIG_SYS_PCI_IO_BUS
+CONFIG_SYS_PCI_IO_PHYS
+CONFIG_SYS_PCI_IO_SIZE
+CONFIG_SYS_PCI_MAP_END
+CONFIG_SYS_PCI_MAP_START
+CONFIG_SYS_PCI_MASTER_INIT
+CONFIG_SYS_PCI_MEMBASE
+CONFIG_SYS_PCI_MEMBASE1
+CONFIG_SYS_PCI_MEMBASE2
+CONFIG_SYS_PCI_MEMBASE3
+CONFIG_SYS_PCI_MEMORY_BUS
+CONFIG_SYS_PCI_MEMORY_PHYS
+CONFIG_SYS_PCI_MEMORY_SIZE
+CONFIG_SYS_PCI_MEMSIZE
+CONFIG_SYS_PCI_MEM_BASE
+CONFIG_SYS_PCI_MEM_BUS
+CONFIG_SYS_PCI_MEM_PHYS
+CONFIG_SYS_PCI_MEM_SIZE
+CONFIG_SYS_PCI_MMIO_BASE
+CONFIG_SYS_PCI_MMIO_PHYS
+CONFIG_SYS_PCI_MMIO_SIZE
+CONFIG_SYS_PCI_MSTR0_LOCAL
+CONFIG_SYS_PCI_MSTR1_LOCAL
+CONFIG_SYS_PCI_MSTR_IO_BUS
+CONFIG_SYS_PCI_MSTR_IO_LOCAL
+CONFIG_SYS_PCI_MSTR_IO_SIZE
+CONFIG_SYS_PCI_MSTR_MEMIO_BUS
+CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
+CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
+CONFIG_SYS_PCI_MSTR_MEM_BUS
+CONFIG_SYS_PCI_MSTR_MEM_LOCAL
+CONFIG_SYS_PCI_MSTR_MEM_SIZE
+CONFIG_SYS_PCI_NR_INBOUND_WIN
+CONFIG_SYS_PCI_PHYS
+CONFIG_SYS_PCI_PTM1LA
+CONFIG_SYS_PCI_PTM1MS
+CONFIG_SYS_PCI_PTM1PCI
+CONFIG_SYS_PCI_PTM2LA
+CONFIG_SYS_PCI_PTM2MS
+CONFIG_SYS_PCI_PTM2PCI
+CONFIG_SYS_PCI_SLV_MEM_BUS
+CONFIG_SYS_PCI_SLV_MEM_LOCAL
+CONFIG_SYS_PCI_SLV_MEM_SIZE
+CONFIG_SYS_PCI_SUBSYS_DEVICEID
+CONFIG_SYS_PCI_SUBSYS_DEVICEID2
+CONFIG_SYS_PCI_SUBSYS_ID
+CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
+CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH
+CONFIG_SYS_PCI_SUBSYS_VENDORID
+CONFIG_SYS_PCI_SYS_MEM_BUS
+CONFIG_SYS_PCI_SYS_MEM_PHYS
+CONFIG_SYS_PCI_SYS_MEM_SIZE
+CONFIG_SYS_PCI_TARGBASE
+CONFIG_SYS_PCI_TARGET_INIT
+CONFIG_SYS_PCI_TBATR0
+CONFIG_SYS_PCI_TBATR1
+CONFIG_SYS_PCI_TBATR2
+CONFIG_SYS_PCI_TBATR3
+CONFIG_SYS_PCI_TBATR4
+CONFIG_SYS_PCI_TBATR5
+CONFIG_SYS_PCI_VIRT
+CONFIG_SYS_PCMCIA_ATTRB_ADDR
+CONFIG_SYS_PCMCIA_ATTRB_SIZE
+CONFIG_SYS_PCMCIA_ATTR_BASE
+CONFIG_SYS_PCMCIA_CIS_WIN
+CONFIG_SYS_PCMCIA_CIS_WIN_SIZE
+CONFIG_SYS_PCMCIA_DMA_ADDR
+CONFIG_SYS_PCMCIA_DMA_SIZE
+CONFIG_SYS_PCMCIA_IO_ADDR
+CONFIG_SYS_PCMCIA_IO_BASE
+CONFIG_SYS_PCMCIA_IO_SIZE
+CONFIG_SYS_PCMCIA_IO_WIN
+CONFIG_SYS_PCMCIA_IO_WIN_SIZE
+CONFIG_SYS_PCMCIA_MEM_ADDR
+CONFIG_SYS_PCMCIA_MEM_SIZE
+CONFIG_SYS_PCMCIA_PBR0
+CONFIG_SYS_PCMCIA_PBR1
+CONFIG_SYS_PCMCIA_PBR2
+CONFIG_SYS_PCMCIA_PBR3
+CONFIG_SYS_PCMCIA_PBR4
+CONFIG_SYS_PCMCIA_PBR5
+CONFIG_SYS_PCMCIA_PBR6
+CONFIG_SYS_PCMCIA_PBR7
+CONFIG_SYS_PCMCIA_POR0
+CONFIG_SYS_PCMCIA_POR1
+CONFIG_SYS_PCMCIA_POR2
+CONFIG_SYS_PCMCIA_POR3
+CONFIG_SYS_PCMCIA_POR4
+CONFIG_SYS_PCMCIA_POR5
+CONFIG_SYS_PCMCIA_POR6
+CONFIG_SYS_PCMCIA_POR7
+CONFIG_SYS_PCMCIA_TIMING
+CONFIG_SYS_PDCNT
+CONFIG_SYS_PDM360NG_COPROC_BAUDRATE
+CONFIG_SYS_PDM360NG_COPROC_READ_DELAY
+CONFIG_SYS_PEHLPAR
+CONFIG_SYS_PEPAR
+CONFIG_SYS_PERIPHERAL_BASE
+CONFIG_SYS_PFC0
+CONFIG_SYS_PFPAR
+CONFIG_SYS_PHYS_ADDR_HIGH
+CONFIG_SYS_PHY_UBOOT_BASE
+CONFIG_SYS_PIB_BASE
+CONFIG_SYS_PIB_WINDOW_SIZE
+CONFIG_SYS_PICMR0_MASK_ATTRIB
+CONFIG_SYS_PIOC_ASR_VAL
+CONFIG_SYS_PIOC_BSR_VAL
+CONFIG_SYS_PIOC_PDR_VAL
+CONFIG_SYS_PIOC_PDR_VAL1
+CONFIG_SYS_PIOC_PPUDR_VAL
+CONFIG_SYS_PIOD_PDR_VAL1
+CONFIG_SYS_PIOD_PPUDR_VAL
+CONFIG_SYS_PIO_MODE
+CONFIG_SYS_PISCR
+CONFIG_SYS_PIT_BASE
+CONFIG_SYS_PIT_PRESCALE
+CONFIG_SYS_PIXIS_VBOOT_ENABLE
+CONFIG_SYS_PIXIS_VBOOT_MASK
+CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
+CONFIG_SYS_PJPAR
+CONFIG_SYS_PL310_BASE
+CONFIG_SYS_PLATFORM_SRAM_BASE
+CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS
+CONFIG_SYS_PLATFORM_SRAM_SIZE
+CONFIG_SYS_PLL0_DIV
+CONFIG_SYS_PLL0_MUL
+CONFIG_SYS_PLL0_OPT
+CONFIG_SYS_PLL0_SUPPRESS_CYCLES
+CONFIG_SYS_PLLAR_VAL
+CONFIG_SYS_PLLBR_VAL
+CONFIG_SYS_PLLCR
+CONFIG_SYS_PLL_BYPASS
+CONFIG_SYS_PLL_FDR
+CONFIG_SYS_PLL_ODR
+CONFIG_SYS_PLL_RECONFIG
+CONFIG_SYS_PLL_SETTLING_TIME
+CONFIG_SYS_PLPRCR
+CONFIG_SYS_PLUG_BASE
+CONFIG_SYS_PMAN
+CONFIG_SYS_PMC_BASE
+CONFIG_SYS_PMC_BASE_PHYS
+CONFIG_SYS_PME_CLK
+CONFIG_SYS_POCMR0_MASK_ATTRIB
+CONFIG_SYS_POCMR1_MASK_ATTRIB
+CONFIG_SYS_POCMR2_MASK_ATTRIB
+CONFIG_SYS_PORTTC
+CONFIG_SYS_POST_BSPEC1
+CONFIG_SYS_POST_BSPEC2
+CONFIG_SYS_POST_BSPEC3
+CONFIG_SYS_POST_BSPEC4
+CONFIG_SYS_POST_BSPEC5
+CONFIG_SYS_POST_CACHE
+CONFIG_SYS_POST_CACHE_ADDR
+CONFIG_SYS_POST_CODEC
+CONFIG_SYS_POST_COPROC
+CONFIG_SYS_POST_CPU
+CONFIG_SYS_POST_DSP
+CONFIG_SYS_POST_ECC
+CONFIG_SYS_POST_ETHER
+CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
+CONFIG_SYS_POST_ETH_LOOPS
+CONFIG_SYS_POST_FLASH
+CONFIG_SYS_POST_FLASH_END
+CONFIG_SYS_POST_FLASH_NUM
+CONFIG_SYS_POST_FLASH_START
+CONFIG_SYS_POST_FPU
+CONFIG_SYS_POST_FPU_ON
+CONFIG_SYS_POST_HOTKEYS_GPIO
+CONFIG_SYS_POST_I2C
+CONFIG_SYS_POST_I2C_ADDRS
+CONFIG_SYS_POST_I2C_IGNORES
+CONFIG_SYS_POST_MEMORY
+CONFIG_SYS_POST_MEMORY_ON
+CONFIG_SYS_POST_MEM_REGIONS
+CONFIG_SYS_POST_OCM
+CONFIG_SYS_POST_PREREL
+CONFIG_SYS_POST_RTC
+CONFIG_SYS_POST_SPI
+CONFIG_SYS_POST_SPR
+CONFIG_SYS_POST_SYSMON
+CONFIG_SYS_POST_UART
+CONFIG_SYS_POST_UART_TABLE
+CONFIG_SYS_POST_USB
+CONFIG_SYS_POST_WATCHDOG
+CONFIG_SYS_POST_WORD_ADDR
+CONFIG_SYS_POWER_MANAGER
+CONFIG_SYS_PPC4XX_USB_ADDR
+CONFIG_SYS_PPC_DDR_WIMGE
+CONFIG_SYS_PQSPAR
+CONFIG_SYS_PRELIM_OR_AM
+CONFIG_SYS_PROMPT_HUSH_PS2
+CONFIG_SYS_PROM_OFFSET
+CONFIG_SYS_PROM_SIZE
+CONFIG_SYS_PSC1
+CONFIG_SYS_PSC3
+CONFIG_SYS_PSC4
+CONFIG_SYS_PSC6
+CONFIG_SYS_PSDMR
+CONFIG_SYS_PSDPAR
+CONFIG_SYS_PSRT
+CONFIG_SYS_PSSR_VAL
+CONFIG_SYS_PTA_PER_CLK
+CONFIG_SYS_PTCPAR
+CONFIG_SYS_PTDPAR
+CONFIG_SYS_PTL2_BITS
+CONFIG_SYS_PTV
+CONFIG_SYS_PUAPAR
+CONFIG_SYS_QE_FMAN_FW_IN_MMC
+CONFIG_SYS_QE_FMAN_FW_IN_NAND
+CONFIG_SYS_QE_FMAN_FW_IN_NOR
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+CONFIG_SYS_QE_FMAN_FW_LENGTH
+CONFIG_SYS_QE_FW_ADDR
+CONFIG_SYS_QE_FW_IN_SPIFLASH
+CONFIG_SYS_QMAN_CENA_BASE
+CONFIG_SYS_QMAN_CENA_SIZE
+CONFIG_SYS_QMAN_CINH_BASE
+CONFIG_SYS_QMAN_CINH_SIZE
+CONFIG_SYS_QMAN_MEM_BASE
+CONFIG_SYS_QMAN_MEM_PHYS
+CONFIG_SYS_QMAN_MEM_SIZE
+CONFIG_SYS_QMAN_NUM_PORTALS
+CONFIG_SYS_QMAN_SP_CENA_SIZE
+CONFIG_SYS_QMAN_SP_CINH_SIZE
+CONFIG_SYS_QMAN_SWP_ISDR_REG
+CONFIG_SYS_QRIO_BASE
+CONFIG_SYS_QRIO_BASE_PHYS
+CONFIG_SYS_QRIO_BR_PRELIM
+CONFIG_SYS_QRIO_OR_PRELIM
+CONFIG_SYS_R7780MP_OLD_FLASH
+CONFIG_SYS_RAMBOOT
+CONFIG_SYS_RAM_BASE
+CONFIG_SYS_RAM_CS
+CONFIG_SYS_RAM_END
+CONFIG_SYS_RAM_FREQ_DIV
+CONFIG_SYS_RAM_SIZE
+CONFIG_SYS_RCAR_I2C0_BASE
+CONFIG_SYS_RCAR_I2C0_SPEED
+CONFIG_SYS_RCAR_I2C1_BASE
+CONFIG_SYS_RCAR_I2C1_SPEED
+CONFIG_SYS_RCAR_I2C2_BASE
+CONFIG_SYS_RCAR_I2C2_SPEED
+CONFIG_SYS_RCAR_I2C3_BASE
+CONFIG_SYS_RCAR_I2C3_SPEED
+CONFIG_SYS_RCCR
+CONFIG_SYS_RCWH_PCIHOST
+CONFIG_SYS_READ_SPD
+CONFIG_SYS_REDUNDAND_ENVIRONMENT
+CONFIG_SYS_RELOC_MONITOR_BASE
+CONFIG_SYS_RELOC_MONITOR_MAX_END
+CONFIG_SYS_REMAP_OR_AM
+CONFIG_SYS_RESET_ADDR
+CONFIG_SYS_RESET_ADDRESS
+CONFIG_SYS_RESET_BASE
+CONFIG_SYS_RESET_SCTRL
+CONFIG_SYS_RFD
+CONFIG_SYS_RGMII1_PHY_ADDR
+CONFIG_SYS_RGMII2_PHY_ADDR
+CONFIG_SYS_RIO_MEM_BASE
+CONFIG_SYS_RIO_MEM_BUS
+CONFIG_SYS_RIO_MEM_PHYS
+CONFIG_SYS_RIO_MEM_SIZE
+CONFIG_SYS_RIO_MEM_VIRT
+CONFIG_SYS_RMDS
+CONFIG_SYS_RMR
+CONFIG_SYS_ROM_BASE
+CONFIG_SYS_ROOTPATH
+CONFIG_SYS_RSTC_RMR_VAL
+CONFIG_SYS_RTCSC
+CONFIG_SYS_RTC_BUS_NUM
+CONFIG_SYS_RTC_CNT
+CONFIG_SYS_RTC_DS1337
+CONFIG_SYS_RTC_DS1337_NOOSC
+CONFIG_SYS_RTC_DS1388
+CONFIG_SYS_RTC_OSCILLATOR
+CONFIG_SYS_RTC_PL031_BASE
+CONFIG_SYS_RTC_REG_BASE_ADDR
+CONFIG_SYS_RTC_SETUP
+CONFIG_SYS_RV3029_TCR
+CONFIG_SYS_RX_ETH_BUFFER
+CONFIG_SYS_SATA
+CONFIG_SYS_SATA1
+CONFIG_SYS_SATA1_FLAGS
+CONFIG_SYS_SATA1_OFFSET
+CONFIG_SYS_SATA2
+CONFIG_SYS_SATA2_FLAGS
+CONFIG_SYS_SATA2_OFFSET
+CONFIG_SYS_SATA_ENV_DEV
+CONFIG_SYS_SATA_FAT_BOOT_PARTITION
+CONFIG_SYS_SATA_MAX_DEVICE
+CONFIG_SYS_SBFHDR_DATA_OFFSET
+CONFIG_SYS_SBFHDR_SIZE
+CONFIG_SYS_SCCR
+CONFIG_SYS_SCCR_ENCCM
+CONFIG_SYS_SCCR_PCICM
+CONFIG_SYS_SCCR_PCIEXP1CM
+CONFIG_SYS_SCCR_PCIEXP2CM
+CONFIG_SYS_SCCR_SATACM
+CONFIG_SYS_SCCR_TSEC1CM
+CONFIG_SYS_SCCR_TSEC1ON
+CONFIG_SYS_SCCR_TSEC2CM
+CONFIG_SYS_SCCR_TSEC2ON
+CONFIG_SYS_SCCR_TSECCM
+CONFIG_SYS_SCCR_USBDRCM
+CONFIG_SYS_SCCR_USBMPHCM
+CONFIG_SYS_SCC_TOUT_LOOP
+CONFIG_SYS_SCR
+CONFIG_SYS_SCRATCH_VA
+CONFIG_SYS_SCSI_MAXDEVICE
+CONFIG_SYS_SCSI_MAX_DEVICE
+CONFIG_SYS_SCSI_MAX_LUN
+CONFIG_SYS_SCSI_MAX_SCSI_ID
+CONFIG_SYS_SCSI_SPIN_UP_TIME
+CONFIG_SYS_SCSI_SYM53C8XX_CCF
+CONFIG_SYS_SDHC_CLK
+CONFIG_SYS_SDHC_CLK_2_PLL
+CONFIG_SYS_SDIO0
+CONFIG_SYS_SDIO0_MAX_CLK
+CONFIG_SYS_SDIO1
+CONFIG_SYS_SDIO1_MAX_CLK
+CONFIG_SYS_SDIO2
+CONFIG_SYS_SDIO2_MAX_CLK
+CONFIG_SYS_SDIO3
+CONFIG_SYS_SDIO3_MAX_CLK
+CONFIG_SYS_SDIO_BASE0
+CONFIG_SYS_SDIO_BASE1
+CONFIG_SYS_SDIO_BASE2
+CONFIG_SYS_SDIO_BASE3
+CONFIG_SYS_SDMR
+CONFIG_SYS_SDRAM
+CONFIG_SYS_SDRAM0_CFG0
+CONFIG_SYS_SDRAM0_CLKTR
+CONFIG_SYS_SDRAM0_CODT
+CONFIG_SYS_SDRAM0_DLCR
+CONFIG_SYS_SDRAM0_INITPLR0
+CONFIG_SYS_SDRAM0_INITPLR1
+CONFIG_SYS_SDRAM0_INITPLR10
+CONFIG_SYS_SDRAM0_INITPLR11
+CONFIG_SYS_SDRAM0_INITPLR12
+CONFIG_SYS_SDRAM0_INITPLR13
+CONFIG_SYS_SDRAM0_INITPLR14
+CONFIG_SYS_SDRAM0_INITPLR15
+CONFIG_SYS_SDRAM0_INITPLR2
+CONFIG_SYS_SDRAM0_INITPLR3
+CONFIG_SYS_SDRAM0_INITPLR4
+CONFIG_SYS_SDRAM0_INITPLR5
+CONFIG_SYS_SDRAM0_INITPLR6
+CONFIG_SYS_SDRAM0_INITPLR7
+CONFIG_SYS_SDRAM0_INITPLR8
+CONFIG_SYS_SDRAM0_INITPLR9
+CONFIG_SYS_SDRAM0_MB0CF
+CONFIG_SYS_SDRAM0_MB0CF_BASE
+CONFIG_SYS_SDRAM0_MB1CF
+CONFIG_SYS_SDRAM0_MB1CF_BASE
+CONFIG_SYS_SDRAM0_MB2CF
+CONFIG_SYS_SDRAM0_MB3CF
+CONFIG_SYS_SDRAM0_MCOPT1
+CONFIG_SYS_SDRAM0_MCOPT2
+CONFIG_SYS_SDRAM0_MEMODE
+CONFIG_SYS_SDRAM0_MMODE
+CONFIG_SYS_SDRAM0_MODT0
+CONFIG_SYS_SDRAM0_MODT1
+CONFIG_SYS_SDRAM0_MODT2
+CONFIG_SYS_SDRAM0_MODT3
+CONFIG_SYS_SDRAM0_RDCC
+CONFIG_SYS_SDRAM0_RFDC
+CONFIG_SYS_SDRAM0_RQDC
+CONFIG_SYS_SDRAM0_RTR
+CONFIG_SYS_SDRAM0_SDTR1
+CONFIG_SYS_SDRAM0_SDTR2
+CONFIG_SYS_SDRAM0_SDTR3
+CONFIG_SYS_SDRAM0_TR0
+CONFIG_SYS_SDRAM0_WDDCTR
+CONFIG_SYS_SDRAM0_WRDTR
+CONFIG_SYS_SDRAM1
+CONFIG_SYS_SDRAM_BANKS
+CONFIG_SYS_SDRAM_BASE
+CONFIG_SYS_SDRAM_BASE0
+CONFIG_SYS_SDRAM_BASE1
+CONFIG_SYS_SDRAM_BASE1xx
+CONFIG_SYS_SDRAM_BASE2
+CONFIG_SYS_SDRAM_CASL
+CONFIG_SYS_SDRAM_CFG
+CONFIG_SYS_SDRAM_CFG1
+CONFIG_SYS_SDRAM_CFG2
+CONFIG_SYS_SDRAM_CL
+CONFIG_SYS_SDRAM_CONF1HB
+CONFIG_SYS_SDRAM_CONF1LL
+CONFIG_SYS_SDRAM_CONFPATHB
+CONFIG_SYS_SDRAM_CS1
+CONFIG_SYS_SDRAM_CTP
+CONFIG_SYS_SDRAM_CTRL
+CONFIG_SYS_SDRAM_DRVSTRENGTH
+CONFIG_SYS_SDRAM_DRV_STRENGTH
+CONFIG_SYS_SDRAM_EMOD
+CONFIG_SYS_SDRAM_END
+CONFIG_SYS_SDRAM_LDF
+CONFIG_SYS_SDRAM_LIST
+CONFIG_SYS_SDRAM_LOWER
+CONFIG_SYS_SDRAM_MODE
+CONFIG_SYS_SDRAM_PLBADDUHB
+CONFIG_SYS_SDRAM_PLBADDULL
+CONFIG_SYS_SDRAM_PTA
+CONFIG_SYS_SDRAM_R0BAS
+CONFIG_SYS_SDRAM_R1BAS
+CONFIG_SYS_SDRAM_R2BAS
+CONFIG_SYS_SDRAM_R3BAS
+CONFIG_SYS_SDRAM_RCD
+CONFIG_SYS_SDRAM_RFTA
+CONFIG_SYS_SDRAM_SIZE
+CONFIG_SYS_SDRAM_SIZE0
+CONFIG_SYS_SDRAM_SIZE1
+CONFIG_SYS_SDRAM_SIZE_LAW
+CONFIG_SYS_SDRAM_SIZE_MB
+CONFIG_SYS_SDRAM_TABLE
+CONFIG_SYS_SDRAM_UPPER
+CONFIG_SYS_SDRAM_VAL
+CONFIG_SYS_SDRAM_VAL1
+CONFIG_SYS_SDRAM_VAL10
+CONFIG_SYS_SDRAM_VAL11
+CONFIG_SYS_SDRAM_VAL12
+CONFIG_SYS_SDRAM_VAL2
+CONFIG_SYS_SDRAM_VAL3
+CONFIG_SYS_SDRAM_VAL4
+CONFIG_SYS_SDRAM_VAL5
+CONFIG_SYS_SDRAM_VAL6
+CONFIG_SYS_SDRAM_VAL7
+CONFIG_SYS_SDRAM_VAL8
+CONFIG_SYS_SDRAM_VAL9
+CONFIG_SYS_SDRAM_tRC
+CONFIG_SYS_SDRAM_tRCD
+CONFIG_SYS_SDRAM_tRFC
+CONFIG_SYS_SDRAM_tRP
+CONFIG_SYS_SDRC_CR_VAL
+CONFIG_SYS_SDRC_MDR_VAL
+CONFIG_SYS_SDRC_MR_VAL
+CONFIG_SYS_SDRC_MR_VAL1
+CONFIG_SYS_SDRC_MR_VAL2
+CONFIG_SYS_SDRC_MR_VAL3
+CONFIG_SYS_SDRC_MR_VAL4
+CONFIG_SYS_SDRC_MR_VAL5
+CONFIG_SYS_SDRC_TR_VAL
+CONFIG_SYS_SDRC_TR_VAL1
+CONFIG_SYS_SDRC_TR_VAL2
+CONFIG_SYS_SDSR
+CONFIG_SYS_SD_VOLTAGE
+CONFIG_SYS_SEC_MON_ADDR
+CONFIG_SYS_SEC_MON_OFFSET
+CONFIG_SYS_SELF_RST
+CONFIG_SYS_SERIAL0
+CONFIG_SYS_SERIAL1
+CONFIG_SYS_SERIAL2
+CONFIG_SYS_SERIAL3
+CONFIG_SYS_SERIAL4
+CONFIG_SYS_SERIAL5
+CONFIG_SYS_SERIAL_BOOT
+CONFIG_SYS_SFP_ADDR
+CONFIG_SYS_SFP_OFFSET
+CONFIG_SYS_SGMII1_PHY_ADDR
+CONFIG_SYS_SGMII2_PHY_ADDR
+CONFIG_SYS_SGMII3_PHY_ADDR
+CONFIG_SYS_SGMII_LINERATE_MHZ
+CONFIG_SYS_SGMII_RATESCALE
+CONFIG_SYS_SGMII_REFCLK_MHZ
+CONFIG_SYS_SH_SDHI0_BASE
+CONFIG_SYS_SH_SDHI1_BASE
+CONFIG_SYS_SH_SDHI2_BASE
+CONFIG_SYS_SH_SDHI3_BASE
+CONFIG_SYS_SH_SDHI_NR_CHANNEL
+CONFIG_SYS_SICRH
+CONFIG_SYS_SICRL
+CONFIG_SYS_SIL1178_I2C
+CONFIG_SYS_SIMULATE_SPD_EEPROM
+CONFIG_SYS_SIUMCR
+CONFIG_SYS_SIUMCR_HIGH
+CONFIG_SYS_SIUMCR_LOW
+CONFIG_SYS_SJA1000_BASE
+CONFIG_SYS_SMALL_FLASH
+CONFIG_SYS_SMC0_CYCLE0_VAL
+CONFIG_SYS_SMC0_MODE0_VAL
+CONFIG_SYS_SMC0_PULSE0_VAL
+CONFIG_SYS_SMC0_SETUP0_VAL
+CONFIG_SYS_SMC_CSR0_VAL
+CONFIG_SYS_SMC_DPMEM_OFFSET
+CONFIG_SYS_SMC_RXBUFLEN
+CONFIG_SYS_SMC_UCODE_PATCH
+CONFIG_SYS_SMI_BASE
+CONFIG_SYS_SPANSION_BASE
+CONFIG_SYS_SPANSION_BOOT
+CONFIG_SYS_SPC1920_PLD_BASE
+CONFIG_SYS_SPC1920_SMC1_CLK4
+CONFIG_SYS_SPCR_OPT
+CONFIG_SYS_SPCR_TSEC1EP
+CONFIG_SYS_SPCR_TSEC2EP
+CONFIG_SYS_SPCR_TSECEP
+CONFIG_SYS_SPD_BUS_NUM
+CONFIG_SYS_SPD_MAX_DIMMS
+CONFIG_SYS_SPI0
+CONFIG_SYS_SPI0_NUM_CS
+CONFIG_SYS_SPI1
+CONFIG_SYS_SPI1_BASE
+CONFIG_SYS_SPI1_NUM_CS
+CONFIG_SYS_SPI2
+CONFIG_SYS_SPI2_BASE
+CONFIG_SYS_SPI2_NUM_CS
+CONFIG_SYS_SPI_ARGS_OFFS
+CONFIG_SYS_SPI_ARGS_SIZE
+CONFIG_SYS_SPI_BASE
+CONFIG_SYS_SPI_CLK
+CONFIG_SYS_SPI_CS_ACT
+CONFIG_SYS_SPI_CS_BASE
+CONFIG_SYS_SPI_CS_USED
+CONFIG_SYS_SPI_DPMEM_OFFSET
+CONFIG_SYS_SPI_FLASH_U_BOOT_DST
+CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS
+CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE
+CONFIG_SYS_SPI_FLASH_U_BOOT_START
+CONFIG_SYS_SPI_INIT_OFFSET
+CONFIG_SYS_SPI_KERNEL_OFFS
+CONFIG_SYS_SPI_MXC_WAIT
+CONFIG_SYS_SPI_RTC_DEVID
+CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
+CONFIG_SYS_SPI_UCODE_PATCH
+CONFIG_SYS_SPI_U_BOOT_OFFS
+CONFIG_SYS_SPI_U_BOOT_SIZE
+CONFIG_SYS_SPI_WRITE_TOUT
+CONFIG_SYS_SPL_ARGS_ADDR
+CONFIG_SYS_SPL_LEN
+CONFIG_SYS_SPL_MALLOC_SIZE
+CONFIG_SYS_SPL_MALLOC_START
+CONFIG_SYS_SPL_MAX_LEN
+CONFIG_SYS_SPR
+CONFIG_SYS_SRAM_BASE
+CONFIG_SYS_SRAM_END
+CONFIG_SYS_SRAM_SIZE
+CONFIG_SYS_SRAM_START
+CONFIG_SYS_SRGPL0_CFG_BAR
+CONFIG_SYS_SRGPL0_MNT_BAR
+CONFIG_SYS_SRGPL0_MSG_BAR
+CONFIG_SYS_SRGPL0_REG_BAR
+CONFIG_SYS_SRIO
+CONFIG_SYS_SRIO1_MEM_BASE
+CONFIG_SYS_SRIO1_MEM_BUS
+CONFIG_SYS_SRIO1_MEM_PHYS
+CONFIG_SYS_SRIO1_MEM_PHYS_HIGH
+CONFIG_SYS_SRIO1_MEM_PHYS_LOW
+CONFIG_SYS_SRIO1_MEM_SIZE
+CONFIG_SYS_SRIO1_MEM_VIRT
+CONFIG_SYS_SRIO2_MEM_PHYS
+CONFIG_SYS_SRIO2_MEM_SIZE
+CONFIG_SYS_SRIO2_MEM_VIRT
+CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
+CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS
+CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR
+CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS
+CONFIG_SYS_SSD_BASE
+CONFIG_SYS_SSD_BASE_PHYS
+CONFIG_SYS_SST_SECT
+CONFIG_SYS_SST_SECTSZ
+CONFIG_SYS_STACKSIZE
+CONFIG_SYS_STACK_LENGTH
+CONFIG_SYS_STACK_SIZE
+CONFIG_SYS_STATUS_C
+CONFIG_SYS_STATUS_OK
+CONFIG_SYS_STMICRO_BOOT
+CONFIG_SYS_SUPPORT_64BIT_DATA
+CONFIG_SYS_SXCNFG_VAL
+CONFIG_SYS_SYPCR
+CONFIG_SYS_SYSTEMACE_BASE
+CONFIG_SYS_SYSTEMACE_WIDTH
+CONFIG_SYS_TBIPA_VALUE
+CONFIG_SYS_TBSCR
+CONFIG_SYS_TCLK
+CONFIG_SYS_TEMP_STACK_OCM
+CONFIG_SYS_TEXT_ADDR
+CONFIG_SYS_TEXT_BASE_NOR
+CONFIG_SYS_TEXT_BASE_SPL
+CONFIG_SYS_TFP410_ADDR
+CONFIG_SYS_TFP410_BUS
+CONFIG_SYS_THUMB_BUILD
+CONFIG_SYS_TIMERBASE
+CONFIG_SYS_TIMER_BASE
+CONFIG_SYS_TIMER_COUNTER
+CONFIG_SYS_TIMER_COUNTS_DOWN
+CONFIG_SYS_TIMER_PRESCALER
+CONFIG_SYS_TIMER_RATE
+CONFIG_SYS_TLB_FOR_BOOT_FLASH
+CONFIG_SYS_TMCNTSC
+CONFIG_SYS_TMPVIRT
+CONFIG_SYS_TMRINTR_MASK
+CONFIG_SYS_TMRINTR_NO
+CONFIG_SYS_TMRINTR_PEND
+CONFIG_SYS_TMRINTR_PRI
+CONFIG_SYS_TMRPND_REG
+CONFIG_SYS_TMR_BASE
+CONFIG_SYS_TMU_CLK_DIV
+CONFIG_SYS_TSEC1
+CONFIG_SYS_TSEC1_OFFSET
+CONFIG_SYS_TSEC2
+CONFIG_SYS_TSEC2_OFFSET
+CONFIG_SYS_TSEC3_OFFSET
+CONFIG_SYS_TX_ETH_BUFFER
+CONFIG_SYS_UART1_ALT1_GPIO
+CONFIG_SYS_UART1_PRI_GPIO
+CONFIG_SYS_UART2_ALT1_GPIO
+CONFIG_SYS_UART2_ALT3_GPIO
+CONFIG_SYS_UART2_PRI_GPIO
+CONFIG_SYS_UART_BASE
+CONFIG_SYS_UART_BAUD
+CONFIG_SYS_UART_FREQ
+CONFIG_SYS_UART_PORT
+CONFIG_SYS_UBOOT_BASE
+CONFIG_SYS_UBOOT_END
+CONFIG_SYS_UBOOT_START
+CONFIG_SYS_UCC_RGMII_MODE
+CONFIG_SYS_UCC_RMII_MODE
+CONFIG_SYS_UDELAY_BASE
+CONFIG_SYS_UEC
+CONFIG_SYS_UEC1_ETH_TYPE
+CONFIG_SYS_UEC1_INTERFACE_SPEED
+CONFIG_SYS_UEC1_INTERFACE_TYPE
+CONFIG_SYS_UEC1_PHY_ADDR
+CONFIG_SYS_UEC1_RX_CLK
+CONFIG_SYS_UEC1_TX_CLK
+CONFIG_SYS_UEC1_UCC_NUM
+CONFIG_SYS_UEC2_ETH_TYPE
+CONFIG_SYS_UEC2_INTERFACE_SPEED
+CONFIG_SYS_UEC2_INTERFACE_TYPE
+CONFIG_SYS_UEC2_PHY_ADDR
+CONFIG_SYS_UEC2_RX_CLK
+CONFIG_SYS_UEC2_TX_CLK
+CONFIG_SYS_UEC2_UCC_NUM
+CONFIG_SYS_UEC3_ETH_TYPE
+CONFIG_SYS_UEC3_INTERFACE_SPEED
+CONFIG_SYS_UEC3_INTERFACE_TYPE
+CONFIG_SYS_UEC3_PHY_ADDR
+CONFIG_SYS_UEC3_RX_CLK
+CONFIG_SYS_UEC3_TX_CLK
+CONFIG_SYS_UEC3_UCC_NUM
+CONFIG_SYS_UEC4_ETH_TYPE
+CONFIG_SYS_UEC4_INTERFACE_SPEED
+CONFIG_SYS_UEC4_INTERFACE_TYPE
+CONFIG_SYS_UEC4_PHY_ADDR
+CONFIG_SYS_UEC4_RX_CLK
+CONFIG_SYS_UEC4_TX_CLK
+CONFIG_SYS_UEC4_UCC_NUM
+CONFIG_SYS_UEC5_ETH_TYPE
+CONFIG_SYS_UEC5_INTERFACE_SPEED
+CONFIG_SYS_UEC5_INTERFACE_TYPE
+CONFIG_SYS_UEC5_PHY_ADDR
+CONFIG_SYS_UEC5_RX_CLK
+CONFIG_SYS_UEC5_TX_CLK
+CONFIG_SYS_UEC5_UCC_NUM
+CONFIG_SYS_UEC6_ETH_TYPE
+CONFIG_SYS_UEC6_INTERFACE_SPEED
+CONFIG_SYS_UEC6_INTERFACE_TYPE
+CONFIG_SYS_UEC6_PHY_ADDR
+CONFIG_SYS_UEC6_RX_CLK
+CONFIG_SYS_UEC6_TX_CLK
+CONFIG_SYS_UEC6_UCC_NUM
+CONFIG_SYS_UEC8_ETH_TYPE
+CONFIG_SYS_UEC8_INTERFACE_SPEED
+CONFIG_SYS_UEC8_INTERFACE_TYPE
+CONFIG_SYS_UEC8_PHY_ADDR
+CONFIG_SYS_UEC8_RX_CLK
+CONFIG_SYS_UEC8_TX_CLK
+CONFIG_SYS_UEC8_UCC_NUM
+CONFIG_SYS_UECx_PHY_ADDR
+CONFIG_SYS_UHC0_EHCI_BASE
+CONFIG_SYS_UHC1_EHCI_BASE
+CONFIG_SYS_ULB_CLK
+CONFIG_SYS_UMCR
+CONFIG_SYS_UNIFY_CACHE
+CONFIG_SYS_UNSPEC_PHYID
+CONFIG_SYS_UNSPEC_STRID
+CONFIG_SYS_UPDATE_FLASH_SIZE
+CONFIG_SYS_USB2D0_BASE
+CONFIG_SYS_USBCTRL
+CONFIG_SYS_USBD_BASE
+CONFIG_SYS_USB_BRGCLK
+CONFIG_SYS_USB_DEVICE
+CONFIG_SYS_USB_EHCI_CPU_INIT
+CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
+CONFIG_SYS_USB_EHCI_REGS_BASE
+CONFIG_SYS_USB_EVENT_POLL
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+CONFIG_SYS_USB_FAT_BOOT_PARTITION
+CONFIG_SYS_USB_HOST
+CONFIG_SYS_USB_OHCI_BOARD_INIT
+CONFIG_SYS_USB_OHCI_CPU_INIT
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
+CONFIG_SYS_USB_OHCI_REGS_BASE
+CONFIG_SYS_USB_OHCI_SLOT_NAME
+CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS
+CONFIG_SYS_USER_SWITCHES_BASE
+CONFIG_SYS_USE_BOOT_NORFLASH
+CONFIG_SYS_USE_DATAFLASH
+CONFIG_SYS_USE_DATAFLASH_CS0
+CONFIG_SYS_USE_DATAFLASH_CS1
+CONFIG_SYS_USE_DATAFLASH_CS3
+CONFIG_SYS_USE_DSPLINK
+CONFIG_SYS_USE_FLASH
+CONFIG_SYS_USE_MAIN_OSCILLATOR
+CONFIG_SYS_USE_MMC
+CONFIG_SYS_USE_MPC834XSYS_USB_PHY
+CONFIG_SYS_USE_NAND
+CONFIG_SYS_USE_NANDFLASH
+CONFIG_SYS_USE_NOR
+CONFIG_SYS_USE_NORFLASH
+CONFIG_SYS_USE_PPCENV
+CONFIG_SYS_USE_SERIALFLASH
+CONFIG_SYS_USE_SPIFLASH
+CONFIG_SYS_USE_UBI
+CONFIG_SYS_USR_EXCEP
+CONFIG_SYS_U_BOOT_OFFS
+CONFIG_SYS_VA_BITS
+CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
+CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
+CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
+CONFIG_SYS_VCXK_AUTODETECT
+CONFIG_SYS_VCXK_BASE
+CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
+CONFIG_SYS_VCXK_DOUBLEBUFFERED
+CONFIG_SYS_VCXK_ENABLE_DDR
+CONFIG_SYS_VCXK_ENABLE_PIN
+CONFIG_SYS_VCXK_ENABLE_PORT
+CONFIG_SYS_VCXK_INVERT_DDR
+CONFIG_SYS_VCXK_INVERT_PIN
+CONFIG_SYS_VCXK_INVERT_PORT
+CONFIG_SYS_VCXK_REQUEST_DDR
+CONFIG_SYS_VCXK_REQUEST_PIN
+CONFIG_SYS_VCXK_REQUEST_PORT
+CONFIG_SYS_VCXK_RESET_DDR
+CONFIG_SYS_VCXK_RESET_PIN
+CONFIG_SYS_VCXK_RESET_PORT
+CONFIG_SYS_VGA_RAM_EN
+CONFIG_SYS_VIDEO
+CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
+CONFIG_SYS_VPC3_BASE
+CONFIG_SYS_VPC3_SIZE
+CONFIG_SYS_VSC7385_BASE
+CONFIG_SYS_VSC7385_BASE_PHYS
+CONFIG_SYS_VSC7385_BR_PRELIM
+CONFIG_SYS_VSC7385_OR_PRELIM
+CONFIG_SYS_VSC7385_SIZE
+CONFIG_SYS_VXWORKS_MAC_PTR
+CONFIG_SYS_WATCHDOG_FLAGS_ADDR
+CONFIG_SYS_WATCHDOG_FREQ
+CONFIG_SYS_WATCHDOG_MAGIC
+CONFIG_SYS_WATCHDOG_MAGIC_MASK
+CONFIG_SYS_WATCHDOG_TIME_ADDR
+CONFIG_SYS_WATCHDOG_VALUE
+CONFIG_SYS_WDTC_WDMR_VAL
+CONFIG_SYS_WDTTIMERBASE
+CONFIG_SYS_WDT_PERIOD_HIGH
+CONFIG_SYS_WDT_PERIOD_LOW
+CONFIG_SYS_WHITE_ON_BLACK
+CONFIG_SYS_WINDOW1_BASE
+CONFIG_SYS_WRITE_SWAPPED_DATA
+CONFIG_SYS_XHCI_USB1_ADDR
+CONFIG_SYS_XHCI_USB2_ADDR
+CONFIG_SYS_XHCI_USB3_ADDR
+CONFIG_SYS_XILINX_SPI_LIST
+CONFIG_SYS_XIMG_LEN
+CONFIG_SYS_XLB_PIPELINING
+CONFIG_SYS_XSVF_DEFAULT_ADDR
+CONFIG_SYS_XWAY_EBU_BOOTCFG
+CONFIG_SYS_ZYNQ_QSPI_WAIT
+CONFIG_SYS_ZYNQ_SPI_WAIT
+CONFIG_SYS_i2C_FSL
+CONFIG_TAM3517_SETTINGS
+CONFIG_TAM3517_SW3_SETTINGS
+CONFIG_TCA642X
+CONFIG_TEGRA_BOARD_STRING
+CONFIG_TEGRA_CLOCK_SCALING
+CONFIG_TEGRA_ENABLE_UARTA
+CONFIG_TEGRA_ENABLE_UARTB
+CONFIG_TEGRA_ENABLE_UARTC
+CONFIG_TEGRA_ENABLE_UARTD
+CONFIG_TEGRA_ENABLE_UARTE
+CONFIG_TEGRA_GPU
+CONFIG_TEGRA_KEYBOARD
+CONFIG_TEGRA_LP0
+CONFIG_TEGRA_MMC
+CONFIG_TEGRA_NAND
+CONFIG_TEGRA_PMU
+CONFIG_TEGRA_SLINK_CTRLS
+CONFIG_TEGRA_SPI
+CONFIG_TEGRA_UARTA_GPU
+CONFIG_TEGRA_UARTA_SDIO1
+CONFIG_TEGRA_UARTA_UAA_UAB
+CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
+CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
+CONFIG_TESTPIN_MASK
+CONFIG_TESTPIN_REG
+CONFIG_TEST_LIST_SORT
+CONFIG_TFP410_I2C_ADDR
+CONFIG_TFTP_BLOCKSIZE
+CONFIG_TFTP_FILE_NAME_MAX_LEN
+CONFIG_TFTP_PORT
+CONFIG_TFTP_TSIZE
+CONFIG_THOR_RESET_OFF
+CONFIG_THUMB2_KERNEL
+CONFIG_THUNDERX
+CONFIG_TI814X
+CONFIG_TI816X
+CONFIG_TI816X_DDR_PLL_796
+CONFIG_TI816X_EVM_DDR2
+CONFIG_TI816X_EVM_DDR3
+CONFIG_TI816X_USE_EMIF0
+CONFIG_TI816X_USE_EMIF1
+CONFIG_TI81XX
+CONFIG_TIMER_CLK_FREQ
+CONFIG_TIMESTAMP
+CONFIG_TIZEN
+CONFIG_TI_KEYSTONE_SERDES
+CONFIG_TI_KSNAV
+CONFIG_TI_SPI_MMAP
+CONFIG_TMU_CMD_DTT
+CONFIG_TMU_TIMER
+CONFIG_TOTAL5200
+CONFIG_TPL_DRIVERS_MISC_SUPPORT
+CONFIG_TPL_PAD_TO
+CONFIG_TPM_TIS_BASE_ADDRESS
+CONFIG_TPS6586X_POWER
+CONFIG_TQM5200
+CONFIG_TQM5200S
+CONFIG_TQM5200_B
+CONFIG_TQM5200_REV100
+CONFIG_TQM823L
+CONFIG_TQM823M
+CONFIG_TQM834X
+CONFIG_TQM850L
+CONFIG_TQM850M
+CONFIG_TQM855L
+CONFIG_TQM855M
+CONFIG_TQM860L
+CONFIG_TQM860M
+CONFIG_TQM862L
+CONFIG_TQM862M
+CONFIG_TQM866M
+CONFIG_TQM885D
+CONFIG_TQM8xxL
+CONFIG_TQM8xxM
+CONFIG_TRACE
+CONFIG_TRACE_BUFFER_SIZE
+CONFIG_TRACE_EARLY
+CONFIG_TRACE_EARLY_ADDR
+CONFIG_TRACE_EARLY_SIZE
+CONFIG_TRAILBLAZER
+CONFIG_TRATS
+CONFIG_TSEC
+CONFIG_TSEC1
+CONFIG_TSEC1_NAME
+CONFIG_TSEC2
+CONFIG_TSEC2_NAME
+CONFIG_TSEC3
+CONFIG_TSEC3_NAME
+CONFIG_TSEC4
+CONFIG_TSEC4_NAME
+CONFIG_TSECV2
+CONFIG_TSECV2_1
+CONFIG_TSEC_ENET
+CONFIG_TSEC_TBI
+CONFIG_TSEC_TBICR_SETTINGS
+CONFIG_TSI108_ETH_NUM_PORTS
+CONFIG_TSIM
+CONFIG_TUGE1
+CONFIG_TULIP
+CONFIG_TULIP_FIX_DAVICOM
+CONFIG_TULIP_SELECT_MEDIA
+CONFIG_TULIP_USE_IO
+CONFIG_TUXX1
+CONFIG_TWL4030_INPUT
+CONFIG_TWL4030_KEYPAD
+CONFIG_TWL4030_LED
+CONFIG_TWL4030_POWER
+CONFIG_TWL4030_PWM
+CONFIG_TWL4030_USB
+CONFIG_TWL6030_INPUT
+CONFIG_TWL6030_POWER
+CONFIG_TWR
+CONFIG_TWR_P1025
+CONFIG_TX_DESCR_NUM
+CONFIG_TZSW_RESERVED_DRAM_SIZE
+CONFIG_T_SH7706LSR
+CONFIG_UART_BASE
+CONFIG_UART_BR_PRELIM
+CONFIG_UART_CONSOLE
+CONFIG_UART_CONSOLE_IS_JTAG
+CONFIG_UART_MEM
+CONFIG_UART_OR_PRELIM
+CONFIG_UBIBLOCK
+CONFIG_UBIFS_SILENCE_MSG
+CONFIG_UBIFS_VOLUME
+CONFIG_UBI_PART
+CONFIG_UBI_SILENCE_MSG
+CONFIG_UBI_SIZE
+CONFIG_UBOOT1_ENV_ADDR
+CONFIG_UBOOT2_ENV_ADDR
+CONFIG_UBOOTPATH
+CONFIG_UBOOT_ENABLE_PADS_ALL
+CONFIG_UBOOT_ENV_ADDR
+CONFIG_UBOOT_SECTOR_COUNT
+CONFIG_UBOOT_SECTOR_START
+CONFIG_UCP1020
+CONFIG_UCP1020_REV_1_3
+CONFIG_UDP_CHECKSUM
+CONFIG_UEC_ETH
+CONFIG_UEC_ETH1
+CONFIG_UEC_ETH2
+CONFIG_UEC_ETH3
+CONFIG_UEC_ETH4
+CONFIG_UEC_ETH5
+CONFIG_UEC_ETH6
+CONFIG_UEC_ETH7
+CONFIG_UEC_ETH8
+CONFIG_UID16
+CONFIG_ULI526X
+CONFIG_ULPI_REF_CLK
+CONFIG_UMSDEVS
+CONFIG_UNIPHIER_ETH
+CONFIG_UPDATEB
+CONFIG_UPDATE_LOAD_ADDR
+CONFIG_UPDATE_TFTP
+CONFIG_UPDATE_TFTP_CNT_MAX
+CONFIG_UPDATE_TFTP_MSEC_MAX
+CONFIG_USART1
+CONFIG_USART3
+CONFIG_USART_BASE
+CONFIG_USART_ID
+CONFIG_USBBOOTCOMMAND
+CONFIG_USBDEBUG
+CONFIG_USBD_CONFIGURATION_STR
+CONFIG_USBD_CTRL_INTERFACE_STR
+CONFIG_USBD_DATA_INTERFACE_STR
+CONFIG_USBD_HS
+CONFIG_USBD_MANUFACTURER
+CONFIG_USBD_PRODUCTID
+CONFIG_USBD_PRODUCTID_CDCACM
+CONFIG_USBD_PRODUCTID_GSERIAL
+CONFIG_USBD_PRODUCT_NAME
+CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE
+CONFIG_USBD_SERIAL_BULK_PKTSIZE
+CONFIG_USBD_SERIAL_INT_ENDPOINT
+CONFIG_USBD_SERIAL_INT_PKTSIZE
+CONFIG_USBD_SERIAL_IN_ENDPOINT
+CONFIG_USBD_SERIAL_IN_PKTSIZE
+CONFIG_USBD_SERIAL_OUT_ENDPOINT
+CONFIG_USBD_SERIAL_OUT_PKTSIZE
+CONFIG_USBD_VENDORID
+CONFIG_USBID_ADDR
+CONFIG_USBNET_DEV_ADDR
+CONFIG_USBNET_HOST_ADDR
+CONFIG_USBNET_MANUFACTURER
+CONFIG_USBTTY
+CONFIG_USB_AM35X
+CONFIG_USB_ATMEL
+CONFIG_USB_ATMEL_CLK_SEL_PLLB
+CONFIG_USB_ATMEL_CLK_SEL_UPLL
+CONFIG_USB_BIN_FIXUP
+CONFIG_USB_BLACKFIN
+CONFIG_USB_BLACKFIN_CLKIN
+CONFIG_USB_BOOTING
+CONFIG_USB_CABLE_CHECK
+CONFIG_USB_CLOCK
+CONFIG_USB_CONFIG
+CONFIG_USB_DEVICE
+CONFIG_USB_DEV_BASE
+CONFIG_USB_DEV_PULLUP_GPIO
+CONFIG_USB_DWC2
+CONFIG_USB_DWC2_REG_ADDR
+CONFIG_USB_EHCI_ARMADA100
+CONFIG_USB_EHCI_BASE
+CONFIG_USB_EHCI_BASE_LIST
+CONFIG_USB_EHCI_EXYNOS
+CONFIG_USB_EHCI_FARADAY
+CONFIG_USB_EHCI_FSL
+CONFIG_USB_EHCI_KIRKWOOD
+CONFIG_USB_EHCI_MX5
+CONFIG_USB_EHCI_MXC
+CONFIG_USB_EHCI_MXS
+CONFIG_USB_EHCI_OMAP
+CONFIG_USB_EHCI_PCI
+CONFIG_USB_EHCI_PPC4XX
+CONFIG_USB_EHCI_RMOBILE
+CONFIG_USB_EHCI_SPEAR
+CONFIG_USB_EHCI_SUNXI
+CONFIG_USB_EHCI_TEGRA
+CONFIG_USB_EHCI_TXFIFO_THRESH
+CONFIG_USB_EHCI_VCT
+CONFIG_USB_EHCI_VF
+CONFIG_USB_ETHER
+CONFIG_USB_ETHER_ASIX
+CONFIG_USB_ETHER_ASIX88179
+CONFIG_USB_ETHER_DM9601
+CONFIG_USB_ETHER_MCS7830
+CONFIG_USB_ETHER_RNDIS
+CONFIG_USB_ETHER_RTL8152
+CONFIG_USB_ETHER_SMSC95XX
+CONFIG_USB_ETHER_xxx
+CONFIG_USB_ETH_CDC
+CONFIG_USB_ETH_QMULT
+CONFIG_USB_ETH_RNDIS
+CONFIG_USB_ETH_SUBSET
+CONFIG_USB_EXT2_BOOT
+CONFIG_USB_FAT_BOOT
+CONFIG_USB_FREQ
+CONFIG_USB_FUNCTION_MASS_STORAGE
+CONFIG_USB_FUNCTION_THOR
+CONFIG_USB_GADGET_AMD5536UDC
+CONFIG_USB_GADGET_AT91
+CONFIG_USB_GADGET_AU1X00
+CONFIG_USB_GADGET_DUMMY_HCD
+CONFIG_USB_GADGET_DWC2_OTG_PHY
+CONFIG_USB_GADGET_FOTG210
+CONFIG_USB_GADGET_FSL_USB2
+CONFIG_USB_GADGET_GOKU
+CONFIG_USB_GADGET_IMX
+CONFIG_USB_GADGET_M66592
+CONFIG_USB_GADGET_MASS_STORAGE
+CONFIG_USB_GADGET_MPC8272
+CONFIG_USB_GADGET_MQ11XX
+CONFIG_USB_GADGET_MUSBHSFC
+CONFIG_USB_GADGET_N9604
+CONFIG_USB_GADGET_NET2280
+CONFIG_USB_GADGET_OMAP
+CONFIG_USB_GADGET_PXA27X
+CONFIG_USB_GADGET_PXA2XX
+CONFIG_USB_GADGET_S3C2410
+CONFIG_USB_GADGET_SA1100
+CONFIG_USB_GADGET_SUPERH
+CONFIG_USB_GADGET_SX2
+CONFIG_USB_HOST_ETHER
+CONFIG_USB_HOST_XHCI_BASE
+CONFIG_USB_INVENTRA_DMA
+CONFIG_USB_ISP1301_I2C_ADDR
+CONFIG_USB_MAX_CONTROLLER_COUNT
+CONFIG_USB_MUSB_AM35X
+CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+CONFIG_USB_MUSB_DSPS
+CONFIG_USB_MUSB_HCD
+CONFIG_USB_MUSB_OMAP2PLUS
+CONFIG_USB_MUSB_PIO_ONLY
+CONFIG_USB_MUSB_TIMEOUT
+CONFIG_USB_MUSB_TUSB6010
+CONFIG_USB_MUSB_UDC
+CONFIG_USB_MUSB_UDD
+CONFIG_USB_OHCI
+CONFIG_USB_OHCI_EP93XX
+CONFIG_USB_OHCI_LPC32XX
+CONFIG_USB_OHCI_NEW
+CONFIG_USB_OHCI_SUNXI
+CONFIG_USB_OMAP3
+CONFIG_USB_OTG
+CONFIG_USB_OTG_BLACKLIST_HUB
+CONFIG_USB_PHY_CFG_BASE
+CONFIG_USB_PHY_TYPE
+CONFIG_USB_PXA25X_SMALL
+CONFIG_USB_R8A66597_HCD
+CONFIG_USB_SERIALNO
+CONFIG_USB_SS_BASE
+CONFIG_USB_TI_CPPI_DMA
+CONFIG_USB_TTY
+CONFIG_USB_TUSB_OMAP_DMA
+CONFIG_USB_UHCI
+CONFIG_USB_ULPI_TIMEOUT
+CONFIG_USB_XHCI_EXYNOS
+CONFIG_USB_XHCI_FSL
+CONFIG_USB_XHCI_KEYSTONE
+CONFIG_USB_XHCI_OMAP
+CONFIG_USB_XHCI_PCI
+CONFIG_USB_XHCI_ZYNQMP
+CONFIG_USER_LOWLEVEL_INIT
+CONFIG_USE_FDT
+CONFIG_USE_INTERRUPT
+CONFIG_USE_IRQ
+CONFIG_USE_NAND
+CONFIG_USE_NETDEV
+CONFIG_USE_NOR
+CONFIG_USE_ONENAND_BOARD_INIT
+CONFIG_USE_SPIFLASH
+CONFIG_USE_STDINT
+CONFIG_USE_TTY
+CONFIG_UTBIPAR_INIT_TBIPA
+CONFIG_U_BOOT_HDR_ADDR
+CONFIG_U_BOOT_HDR_SIZE
+CONFIG_U_QE
+CONFIG_V38B
+CONFIG_VAL
+CONFIG_VAR_SIZE_SPL
+CONFIG_VCO_HZ
+CONFIG_VCO_MULT
+CONFIG_VCT_NOR
+CONFIG_VE8313
+CONFIG_VERY_BIG_RAM
+CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
+CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+CONFIG_VF610
+CONFIG_VID
+CONFIG_VIDEO_BCM2835
+CONFIG_VIDEO_BMP_GZIP
+CONFIG_VIDEO_BMP_LOGO
+CONFIG_VIDEO_BMP_RLE8
+CONFIG_VIDEO_CORALP
+CONFIG_VIDEO_DA8XX
+CONFIG_VIDEO_DT_SIMPLEFB
+CONFIG_VIDEO_FONT_4X6
+CONFIG_VIDEO_LCD_I2C_BUS
+CONFIG_VIDEO_LOGO
+CONFIG_VIDEO_MB862xx
+CONFIG_VIDEO_MB862xx_ACCEL
+CONFIG_VIDEO_MX3
+CONFIG_VIDEO_MXS
+CONFIG_VIDEO_MXS_MODE_SYSTEM
+CONFIG_VIDEO_OMAP3
+CONFIG_VIDEO_ONBOARD
+CONFIG_VIDEO_SM501
+CONFIG_VIDEO_SM501_16BPP
+CONFIG_VIDEO_SM501_32BPP
+CONFIG_VIDEO_SM501_8BPP
+CONFIG_VIDEO_SM501_PCI
+CONFIG_VIDEO_STD_TIMINGS
+CONFIG_VIDEO_SUNXI
+CONFIG_VIDEO_VCXK
+CONFIG_VID_FLS_ENV
+CONFIG_VM86
+CONFIG_VME8349
+CONFIG_VOIPAC_LCD
+CONFIG_VOL_MONITOR_INA220
+CONFIG_VOL_MONITOR_IR36021_READ
+CONFIG_VOL_MONITOR_IR36021_SET
+CONFIG_VOM405
+CONFIG_VR_CTL_CLKBUF
+CONFIG_VR_CTL_FREQ
+CONFIG_VR_CTL_VAL
+CONFIG_VR_CTL_VLEV
+CONFIG_VSC7385_ENET
+CONFIG_VSC7385_IMAGE
+CONFIG_VSC7385_IMAGE_SIZE
+CONFIG_VSC9953
+CONFIG_VSC_CROSSBAR
+CONFIG_WALNUT
+CONFIG_WATCHDOG
+CONFIG_WATCHDOG_BASEADDR
+CONFIG_WATCHDOG_IRQ
+CONFIG_WATCHDOG_NOWAYOUT
+CONFIG_WATCHDOG_PRESC
+CONFIG_WATCHDOG_RC
+CONFIG_WATCHDOG_TIMEOUT
+CONFIG_WATCHDOG_TIMEOUT_MSECS
+CONFIG_WDOG_GPIO_PIN
+CONFIG_WD_MAX_RATE
+CONFIG_WD_PERIOD
+CONFIG_WINBOND_83C553
+CONFIG_X600
+CONFIG_X86EMU_DEBUG
+CONFIG_X86EMU_RAW_IO
+CONFIG_X86_64
+CONFIG_X86_BSWAP
+CONFIG_X86_MRC_ADDR
+CONFIG_X86_REFCODE_ADDR
+CONFIG_X86_REFCODE_RUN_ADDR
+CONFIG_XGI_XG22_BASE
+CONFIG_XILINX_405
+CONFIG_XILINX_440
+CONFIG_XILINX_GPIO
+CONFIG_XILINX_LL_TEMAC
+CONFIG_XILINX_LL_TEMAC_CLK
+CONFIG_XILINX_PPC440_GENERIC
+CONFIG_XILINX_SPI_IDLE_VAL
+CONFIG_XILINX_TB_WATCHDOG
+CONFIG_XPEDITE1000
+CONFIG_XPEDITE5140
+CONFIG_XPEDITE5200
+CONFIG_XPEDITE550X
+CONFIG_XR16L2751
+CONFIG_XSENGINE
+CONFIG_XTFPGA
+CONFIG_YAFFSFS_PROVIDE_VALUES
+CONFIG_YAFFS_AUTO_UNICODE
+CONFIG_YAFFS_CASE_INSENSITIVE
+CONFIG_YAFFS_DEFINES_TYPES
+CONFIG_YAFFS_DIRECT
+CONFIG_YAFFS_PROVIDE_DEFS
+CONFIG_YAFFS_UNICODE
+CONFIG_YAFFS_UTIL
+CONFIG_YAFFS_WINCE
+CONFIG_YELLOWSTONE
+CONFIG_YELLOW_LED
+CONFIG_YOSEMITE
+CONFIG_ZBOOT_32
+CONFIG_ZC770_XM010
+CONFIG_ZC770_XM011
+CONFIG_ZC770_XM012
+CONFIG_ZC770_XM013
+CONFIG_ZLIB
+CONFIG_ZLT
+CONFIG_ZM7300
+CONFIG_ZYNQMP_EEPROM
+CONFIG_ZYNQMP_XHCI_LIST
+CONFIG_ZYNQ_EEPROM
+CONFIG_ZYNQ_EEPROM_BUS
+CONFIG_ZYNQ_GEM_EEPROM_ADDR
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET
+CONFIG_ZYNQ_HISPD_BROKEN
+CONFIG_ZYNQ_I2C0
+CONFIG_ZYNQ_I2C1
+CONFIG_ZYNQ_PS_CLK_FREQ
+CONFIG_ZYNQ_SDHCI0
+CONFIG_ZYNQ_SDHCI1
+CONFIG_ZYNQ_SDHCI_MAX_FREQ
+CONFIG_ZYNQ_SDHCI_MIN_FREQ
+CONFIG_ZYNQ_SERIAL
+CONFIG_eTSEC_MDIO_BUS
diff --git a/scripts/get_default_envs.sh b/scripts/get_default_envs.sh
new file mode 100755
index 0000000..7955db6
--- /dev/null
+++ b/scripts/get_default_envs.sh
@@ -0,0 +1,34 @@
+#! /bin/bash
+#
+# Copyright (C) 2016, Lukasz Majewski <l.majewski@majess.pl>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# This file extracts default envs from built u-boot
+# usage: get_default_envs.sh > u-boot-env-default.txt
+set -ue
+
+ENV_OBJ_FILE="env_common.o"
+ENV_OBJ_FILE_COPY="copy_${ENV_OBJ_FILE}"
+
+echoerr() { echo "$@" 1>&2; }
+
+path=$(readlink -f $0)
+env_obj_file_path=$(find ${path%/scripts*} -not -path "*/spl/*" \
+ -name "${ENV_OBJ_FILE}")
+[ -z "${env_obj_file_path}" ] && \
+ { echoerr "File '${ENV_OBJ_FILE}' not found!"; exit 1; }
+
+cp ${env_obj_file_path} ${ENV_OBJ_FILE_COPY}
+
+# NOTE: objcopy saves its output to file passed in
+# (copy_env_common.o in this case)
+objcopy -O binary -j ".rodata.default_environment" ${ENV_OBJ_FILE_COPY}
+
+# Replace default '\0' with '\n' and sort entries
+tr '\0' '\n' < ${ENV_OBJ_FILE_COPY} | sort -u
+
+rm ${ENV_OBJ_FILE_COPY}
+
+exit 0
diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
index 93679cb..b194864 100755
--- a/test/fs/fs-test.sh
+++ b/test/fs/fs-test.sh
@@ -9,14 +9,14 @@
# It currently tests the fs/sb and native commands for ext4 and fat partitions
# Expected results are as follows:
# EXT4 tests:
-# fs-test.sb.ext4.out: Summary: PASS: 17 FAIL: 2
-# fs-test.ext4.out: Summary: PASS: 10 FAIL: 9
-# fs-test.fs.ext4.out: Summary: PASS: 10 FAIL: 9
+# fs-test.sb.ext4.out: Summary: PASS: 23 FAIL: 0
+# fs-test.ext4.out: Summary: PASS: 23 FAIL: 0
+# fs-test.fs.ext4.out: Summary: PASS: 23 FAIL: 0
# FAT tests:
-# fs-test.sb.fat.out: Summary: PASS: 17 FAIL: 2
-# fs-test.fat.out: Summary: PASS: 19 FAIL: 0
-# fs-test.fs.fat.out: Summary: PASS: 19 FAIL: 0
-# Total Summary: TOTAL PASS: 92 TOTAL FAIL: 22
+# fs-test.sb.fat.out: Summary: PASS: 23 FAIL: 0
+# fs-test.fat.out: Summary: PASS: 20 FAIL: 3
+# fs-test.fs.fat.out: Summary: PASS: 20 FAIL: 3
+# Total Summary: TOTAL PASS: 132 TOTAL FAIL: 6
# pre-requisite binaries list.
PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir"
@@ -135,22 +135,6 @@
fi
}
-# 1st parameter is the FS type: fat/ext4
-# 2nd parameter is the name of small file
-# Returns filename which can be used for fat or ext4 for writing
-function fname_for_write() {
- case $1 in
- ext4)
- # ext4 needs absolute path name of file
- echo /${2}.w
- ;;
-
- *)
- echo ${2}.w
- ;;
- esac
-}
-
# 1st parameter is image file
# 2nd parameter is file system type - fat/ext4
# 3rd parameter is name of small file
@@ -166,11 +150,14 @@
case "$2" in
fat)
+ FPATH=""
PREFIX="fat"
WRITE="write"
;;
ext4)
+ # ext4 needs absolute path
+ FPATH="/"
PREFIX="ext4"
WRITE="write"
;;
@@ -205,16 +192,15 @@
esac
- if [ -z "$6" ]; then
- FILE_WRITE=`fname_for_write $2 $3`
- FILE_SMALL=$3
- FILE_BIG=$4
- else
- FILE_WRITE=$6/`fname_for_write $2 $3`
- FILE_SMALL=$6/$3
- FILE_BIG=$6/$4
+ # sb always uses full path to mointpoint, irrespective of filesystem
+ if [ "$5" = "sb" ]; then
+ FPATH=${6}/
fi
+ FILE_WRITE=${3}.w
+ FILE_SMALL=$3
+ FILE_BIG=$4
+
# In u-boot commands, <interface> stands for host or hostfs
# hostfs maps to the host fs.
# host maps to the "sb bind" that we do
@@ -230,13 +216,13 @@
# sb size hostfs - $3 for hostfs commands.
# 1MB is 0x0010 0000
# Test Case 2 - size of small file
-${PREFIX}size host${SUFFIX} $FILE_SMALL
+${PREFIX}size host${SUFFIX} ${FPATH}$FILE_SMALL
printenv filesize
setenv filesize
# 2.5GB (1024*1024*2500) is 0x9C40 0000
# Test Case 3 - size of big file
-${PREFIX}size host${SUFFIX} $FILE_BIG
+${PREFIX}size host${SUFFIX} ${FPATH}$FILE_BIG
printenv filesize
setenv filesize
@@ -245,14 +231,14 @@
# Last two parameters are size and offset.
# Test Case 4a - Read full 1MB of small file
-${PREFIX}load host${SUFFIX} $addr $FILE_SMALL
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_SMALL
printenv filesize
# Test Case 4b - Read full 1MB of small file
md5sum $addr \$filesize
setenv filesize
# Test Case 5a - First 1MB of big file
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x0
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x0
printenv filesize
# Test Case 5b - First 1MB of big file
md5sum $addr \$filesize
@@ -260,7 +246,7 @@
# fails for ext as no offset support
# Test Case 6a - Last 1MB of big file
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x9C300000
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x9C300000
printenv filesize
# Test Case 6b - Last 1MB of big file
md5sum $addr \$filesize
@@ -268,7 +254,7 @@
# fails for ext as no offset support
# Test Case 7a - One from the last 1MB chunk of 2GB
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF00000
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x7FF00000
printenv filesize
# Test Case 7b - One from the last 1MB chunk of 2GB
md5sum $addr \$filesize
@@ -276,7 +262,7 @@
# fails for ext as no offset support
# Test Case 8a - One from the start 1MB chunk from 2GB
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x80000000
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x80000000
printenv filesize
# Test Case 8b - One from the start 1MB chunk from 2GB
md5sum $addr \$filesize
@@ -284,7 +270,7 @@
# fails for ext as no offset support
# Test Case 9a - One 1MB chunk crossing the 2GB boundary
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF80000
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x7FF80000
printenv filesize
# Test Case 9b - One 1MB chunk crossing the 2GB boundary
md5sum $addr \$filesize
@@ -292,21 +278,44 @@
# Generic failure case
# Test Case 10 - 2MB chunk from the last 1MB of big file
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG 0x00200000 0x9C300000
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG 0x00200000 0x9C300000
printenv filesize
#
# Read 1MB from small file
-${PREFIX}load host${SUFFIX} $addr $FILE_SMALL
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_SMALL
# Write it back to test the writes
# Test Case 11a - Check that the write succeeded
-${PREFIX}${WRITE} host${SUFFIX} $addr $FILE_WRITE \$filesize
+${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}$FILE_WRITE \$filesize
mw.b $addr 00 100
-${PREFIX}load host${SUFFIX} $addr $FILE_WRITE
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_WRITE
# Test Case 11b - Check md5 of written to is same as the one read from
md5sum $addr \$filesize
setenv filesize
#
+
+# Next test case checks writing a file whose dirent
+# is the first in the block, which is always true for "."
+# The write should fail, but the lookup should work
+# Test Case 12 - Check directory traversal
+${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}. 0x10
+
+# Read 1MB from small file
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_SMALL
+# Write it via "same directory", i.e. "." dirent
+# Test Case 13a - Check directory traversal
+${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}./${FILE_WRITE}2 \$filesize
+mw.b $addr 00 100
+${PREFIX}load host${SUFFIX} $addr ${FPATH}./${FILE_WRITE}2
+# Test Case 13b - Check md5 of written to is same as the one read from
+md5sum $addr \$filesize
+setenv filesize
+mw.b $addr 00 100
+${PREFIX}load host${SUFFIX} $addr ${FPATH}${FILE_WRITE}2
+# Test Case 13c - Check md5 of written to is same as the one read from
+md5sum $addr \$filesize
+setenv filesize
+#
reset
EOF
@@ -343,9 +352,10 @@
&> /dev/null
fi
- # Delete the small file which possibly is written as part of a
+ # Delete the small file copies which possibly are written as part of a
# previous test.
sudo rm -f "${MB1}.w"
+ sudo rm -f "${MB1}.w2"
# Generate the md5sums of reads that we will test against small file
dd if="${MB1}" bs=1M skip=0 count=1 2> /dev/null | md5sum > "$2"
@@ -400,7 +410,7 @@
# md5sum in u-boot has output of form:
# md5 for 01000008 ... 01100007 ==> <md5>
# the 7th field is the actual md5
- md5_src=`grep -A3 "$1" "$2" | grep "md5 for" | tr -d '\r'`
+ md5_src=`grep -A2 "$1" "$2" | grep "md5 for" | tr -d '\r'`
md5_src=($md5_src)
md5_src=${md5_src[6]}
@@ -445,48 +455,60 @@
pass_fail "TC3: size of $4"
# Check read full mb of 1MB.file
- grep -A6 "Test Case 4a " "$1" | grep -q "filesize=100000"
+ grep -A4 "Test Case 4a " "$1" | grep -q "filesize=100000"
pass_fail "TC4: load of $3 size"
check_md5 "Test Case 4b " "$1" "$2" 1 "TC4: load from $3"
# Check first mb of 2.5GB.file
- grep -A6 "Test Case 5a " "$1" | grep -q "filesize=100000"
+ grep -A4 "Test Case 5a " "$1" | grep -q "filesize=100000"
pass_fail "TC5: load of 1st MB from $4 size"
check_md5 "Test Case 5b " "$1" "$2" 2 "TC5: load of 1st MB from $4"
# Check last mb of 2.5GB.file
- grep -A6 "Test Case 6a " "$1" | grep -q "filesize=100000"
+ grep -A4 "Test Case 6a " "$1" | grep -q "filesize=100000"
pass_fail "TC6: load of last MB from $4 size"
check_md5 "Test Case 6b " "$1" "$2" 3 "TC6: load of last MB from $4"
# Check last 1mb chunk of 2gb from 2.5GB file
- grep -A6 "Test Case 7a " "$1" | grep -q "filesize=100000"
+ grep -A4 "Test Case 7a " "$1" | grep -q "filesize=100000"
pass_fail "TC7: load of last 1mb chunk of 2GB from $4 size"
check_md5 "Test Case 7b " "$1" "$2" 4 \
"TC7: load of last 1mb chunk of 2GB from $4"
# Check first 1mb chunk after 2gb from 2.5GB file
- grep -A6 "Test Case 8a " "$1" | grep -q "filesize=100000"
+ grep -A4 "Test Case 8a " "$1" | grep -q "filesize=100000"
pass_fail "TC8: load 1st MB chunk after 2GB from $4 size"
check_md5 "Test Case 8b " "$1" "$2" 5 \
"TC8: load 1st MB chunk after 2GB from $4"
# Check 1mb chunk crossing the 2gb boundary from 2.5GB file
- grep -A6 "Test Case 9a " "$1" | grep -q "filesize=100000"
+ grep -A4 "Test Case 9a " "$1" | grep -q "filesize=100000"
pass_fail "TC9: load 1MB chunk crossing 2GB boundary from $4 size"
check_md5 "Test Case 9b " "$1" "$2" 6 \
"TC9: load 1MB chunk crossing 2GB boundary from $4"
# Check 2mb chunk from the last 1MB of 2.5GB file loads 1MB
- grep -A6 "Test Case 10 " "$1" | grep -q "filesize=100000"
+ grep -A5 "Test Case 10 " "$1" | grep -q "filesize=100000"
pass_fail "TC10: load 2MB from the last 1MB of $4 loads 1MB"
# Check 1mb chunk write
- grep -A3 "Test Case 11a " "$1" | \
- egrep -q '1048576 bytes written|update journal'
- pass_fail "TC11: 1MB write to $5 - write succeeded"
+ grep -A2 "Test Case 11a " "$1" | grep -q '1048576 bytes written'
+ pass_fail "TC11: 1MB write to $3.w - write succeeded"
check_md5 "Test Case 11b " "$1" "$2" 1 \
- "TC11: 1MB write to $5 - content verified"
+ "TC11: 1MB write to $3.w - content verified"
+
+ # Check lookup of 'dot' directory
+ grep -A4 "Test Case 12 " "$1" | grep -q 'Unable to write file'
+ pass_fail "TC12: 1MB write to . - write denied"
+
+ # Check directory traversal
+ grep -A2 "Test Case 13a " "$1" | grep -q '1048576 bytes written'
+ pass_fail "TC13: 1MB write to ./$3.w2 - write succeeded"
+ check_md5 "Test Case 13b " "$1" "$2" 1 \
+ "TC13: 1MB read from ./$3.w2 - content verified"
+ check_md5 "Test Case 13c " "$1" "$2" 1 \
+ "TC13: 1MB read from $3.w2 - content verified"
+
echo "** End $1"
}
@@ -500,8 +522,12 @@
OUT_FILE="${OUT}.$1.${fs}.out"
test_image $IMAGE $fs $SMALL_FILE $BIG_FILE $1 "" \
> ${OUT_FILE} 2>&1
- check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \
- $WRITE_FILE
+ # strip out noise from fs code
+ grep -v -e "File System is consistent\|update journal finished" \
+ -e "reading .*\.file\|writing .*\.file.w" \
+ < ${OUT_FILE} > ${OUT_FILE}_clean
+ check_results ${OUT_FILE}_clean $MD5_FILE_FS $SMALL_FILE \
+ $BIG_FILE
TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
TOTAL_PASS=$((TOTAL_PASS + PASS))
echo "Summary: PASS: $PASS FAIL: $FAIL"
@@ -551,8 +577,7 @@
sudo umount "$MOUNT_DIR"
rmdir "$MOUNT_DIR"
- check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \
- $WRITE_FILE
+ check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE
TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
TOTAL_PASS=$((TOTAL_PASS + PASS))
echo "Summary: PASS: $PASS FAIL: $FAIL"
diff --git a/test/overlay/cmd_ut_overlay.c b/test/overlay/cmd_ut_overlay.c
index 87dc932..cbef720 100644
--- a/test/overlay/cmd_ut_overlay.c
+++ b/test/overlay/cmd_ut_overlay.c
@@ -52,12 +52,15 @@
const char **out)
{
int node_off;
+ int len;
node_off = fdt_path_offset(fdt, path);
if (node_off < 0)
return node_off;
- return fdt_get_string(fdt, node_off, name, out);
+ *out = fdt_stringlist_get(fdt, node_off, name, 0, &len);
+
+ return len < 0 ? len : 0;
}
static int fdt_overlay_change_int_property(struct unit_test_state *uts)
diff --git a/test/py/conftest.py b/test/py/conftest.py
index 5b3a923..65e1d75 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -298,6 +298,32 @@
continue
generate_config(metafunc, fn)
+@pytest.fixture(scope='session')
+def u_boot_log(request):
+ """Generate the value of a test's log fixture.
+
+ Args:
+ request: The pytest request.
+
+ Returns:
+ The fixture value.
+ """
+
+ return console.log
+
+@pytest.fixture(scope='session')
+def u_boot_config(request):
+ """Generate the value of a test's u_boot_config fixture.
+
+ Args:
+ request: The pytest request.
+
+ Returns:
+ The fixture value.
+ """
+
+ return console.config
+
@pytest.fixture(scope='function')
def u_boot_console(request):
"""Generate the value of a test's u_boot_console fixture.
@@ -431,6 +457,9 @@
if not ubconfig.buildconfig.get('config_' + option.lower(), None):
pytest.skip('.config feature not enabled')
+def start_test_section(item):
+ anchors[item.name] = log.start_section(item.name)
+
def pytest_runtest_setup(item):
"""pytest hook: Configure (set up) a test item.
@@ -444,7 +473,7 @@
Nothing.
"""
- anchors[item.name] = log.start_section(item.name)
+ start_test_section(item)
setup_boardspec(item)
setup_buildconfigspec(item)
@@ -464,6 +493,14 @@
reports = runtestprotocol(item, nextitem=nextitem)
+ # In pytest 3, runtestprotocol() may not call pytest_runtest_setup() if
+ # the test is skipped. That call is required to create the test's section
+ # in the log file. The call to log.end_section() requires that the log
+ # contain a section for this test. Create a section for the test if it
+ # doesn't already exist.
+ if not item.name in anchors:
+ start_test_section(item)
+
failure_cleanup = False
test_list = tests_passed
msg = 'OK'
diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py
new file mode 100644
index 0000000..5d7f5db
--- /dev/null
+++ b/test/py/tests/test_efi_loader.py
@@ -0,0 +1,195 @@
+# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+# Copyright (c) 2016, Alexander Graf <agraf@suse.de>
+#
+# based on test_net.py.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+# Test efi loader implementation
+
+import pytest
+import u_boot_utils
+
+"""
+Note: This test relies on boardenv_* containing configuration values to define
+which the network environment available for testing. Without this, the parts
+that rely on network will be automatically skipped.
+
+For example:
+
+# Boolean indicating whether the Ethernet device is attached to USB, and hence
+# USB enumeration needs to be performed prior to network tests.
+# This variable may be omitted if its value is False.
+env__net_uses_usb = False
+
+# Boolean indicating whether the Ethernet device is attached to PCI, and hence
+# PCI enumeration needs to be performed prior to network tests.
+# This variable may be omitted if its value is False.
+env__net_uses_pci = True
+
+# True if a DHCP server is attached to the network, and should be tested.
+# If DHCP testing is not possible or desired, this variable may be omitted or
+# set to False.
+env__net_dhcp_server = True
+
+# A list of environment variables that should be set in order to configure a
+# static IP. If solely relying on DHCP, this variable may be omitted or set to
+# an empty list.
+env__net_static_env_vars = [
+ ("ipaddr", "10.0.0.100"),
+ ("netmask", "255.255.255.0"),
+ ("serverip", "10.0.0.1"),
+]
+
+# Details regarding a file that may be read from a TFTP server. This variable
+# may be omitted or set to None if TFTP testing is not possible or desired.
+env__efi_loader_helloworld_file = {
+ "fn": "lib/efi_loader/helloworld.efi",
+ "size": 5058624,
+ "crc32": "c2244b26",
+}
+"""
+
+net_set_up = False
+
+def test_efi_pre_commands(u_boot_console):
+ """Execute any commands required to enable network hardware.
+
+ These commands are provided by the boardenv_* file; see the comment at the
+ beginning of this file.
+ """
+
+ init_usb = u_boot_console.config.env.get('env__net_uses_usb', False)
+ if init_usb:
+ u_boot_console.run_command('usb start')
+
+ init_pci = u_boot_console.config.env.get('env__net_uses_pci', False)
+ if init_pci:
+ u_boot_console.run_command('pci enum')
+
+@pytest.mark.buildconfigspec('cmd_dhcp')
+def test_efi_dhcp(u_boot_console):
+ """Test the dhcp command.
+
+ The boardenv_* file may be used to enable/disable this test; see the
+ comment at the beginning of this file.
+ """
+
+ test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+ if not test_dhcp:
+ pytest.skip('No DHCP server available')
+
+ u_boot_console.run_command('setenv autoload no')
+ output = u_boot_console.run_command('dhcp')
+ assert 'DHCP client bound to address ' in output
+
+ global net_set_up
+ net_set_up = True
+
+@pytest.mark.buildconfigspec('net')
+def test_efi_setup_static(u_boot_console):
+ """Set up a static IP configuration.
+
+ The configuration is provided by the boardenv_* file; see the comment at
+ the beginning of this file.
+ """
+
+ env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None)
+ if not env_vars:
+ pytest.skip('No static network configuration is defined')
+
+ for (var, val) in env_vars:
+ u_boot_console.run_command('setenv %s %s' % (var, val))
+
+ global net_set_up
+ net_set_up = True
+
+def fetch_tftp_file(u_boot_console, env_conf):
+ """Grab an env described file via TFTP and return its address
+
+ A file as described by an env config <env_conf> is downloaded from the TFTP
+ server. The address to that file is returned.
+ """
+ if not net_set_up:
+ pytest.skip('Network not initialized')
+
+ f = u_boot_console.config.env.get(env_conf, None)
+ if not f:
+ pytest.skip('No %s binary specified in environment' % env_conf)
+
+ addr = f.get('addr', None)
+ if not addr:
+ addr = u_boot_utils.find_ram_base(u_boot_console) + (1024 * 1024 * 4)
+
+ fn = f['fn']
+ output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+ expected_text = 'Bytes transferred = '
+ sz = f.get('size', None)
+ if sz:
+ expected_text += '%d' % sz
+ assert expected_text in output
+
+ expected_crc = f.get('crc32', None)
+ if not expected_crc:
+ return addr
+
+ if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+ return addr
+
+ output = u_boot_console.run_command('crc32 %x $filesize' % addr)
+ assert expected_crc in output
+
+ return addr
+
+@pytest.mark.buildconfigspec('cmd_bootefi_hello_compile')
+def test_efi_helloworld_net(u_boot_console):
+ """Run the helloworld.efi binary via TFTP.
+
+ The helloworld.efi file is downloaded from the TFTP server and gets
+ executed.
+ """
+
+ addr = fetch_tftp_file(u_boot_console, 'env__efi_loader_helloworld_file')
+
+ output = u_boot_console.run_command('bootefi %x' % addr)
+ expected_text = 'Hello, world'
+ assert expected_text in output
+
+@pytest.mark.buildconfigspec('cmd_bootefi_hello')
+def test_efi_helloworld_builtin(u_boot_console):
+ """Run the builtin helloworld.efi binary.
+
+ The helloworld.efi file is included in U-Boot, execute it using the
+ special "bootefi hello" command.
+ """
+
+ output = u_boot_console.run_command('bootefi hello')
+ expected_text = 'Hello, world'
+ assert expected_text in output
+
+@pytest.mark.buildconfigspec('cmd_bootefi')
+def test_efi_grub_net(u_boot_console):
+ """Run the grub.efi binary via TFTP.
+
+ The grub.efi file is downloaded from the TFTP server and gets
+ executed.
+ """
+
+ addr = fetch_tftp_file(u_boot_console, 'env__efi_loader_grub_file')
+
+ u_boot_console.run_command('bootefi %x' % addr, wait_for_prompt=False)
+
+ # Verify that we have an SMBIOS table
+ check_smbios = u_boot_console.config.env.get('env__efi_loader_check_smbios', False)
+ if check_smbios:
+ u_boot_console.wait_for('grub>')
+ output = u_boot_console.run_command('lsefisystab', wait_for_prompt=False, wait_for_echo=False)
+ u_boot_console.wait_for('SMBIOS')
+
+ # Then exit cleanly
+ u_boot_console.wait_for('grub>')
+ output = u_boot_console.run_command('exit', wait_for_prompt=False, wait_for_echo=False)
+ u_boot_console.wait_for('r = 0')
+
+ # And give us our U-Boot prompt back
+ u_boot_console.run_command('')
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index 4ab58b4..293b73a 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -47,6 +47,15 @@
"size": 5058624,
"crc32": "c2244b26",
}
+
+# Details regarding a file that may be read from a NFS server. This variable
+# may be omitted or set to None if NFS testing is not possible or desired.
+env__net_nfs_readable_file = {
+ "fn": "ubtest-readable.bin",
+ "addr": 0x10000000,
+ "size": 5058624,
+ "crc32": "c2244b26",
+}
"""
net_set_up = False
@@ -138,7 +147,7 @@
addr = f.get('addr', None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = u_boot_utils.find_ram_base(u_boot_console) + (1024 * 1024 * 4)
fn = f['fn']
output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
@@ -157,3 +166,43 @@
output = u_boot_console.run_command('crc32 %x $filesize' % addr)
assert expected_crc in output
+
+@pytest.mark.buildconfigspec('cmd_nfs')
+def test_net_nfs(u_boot_console):
+ """Test the nfs command.
+
+ A file is downloaded from the NFS server, its size and optionally its
+ CRC32 are validated.
+
+ The details of the file to download are provided by the boardenv_* file;
+ see the comment at the beginning of this file.
+ """
+
+ if not net_set_up:
+ pytest.skip('Network not initialized')
+
+ f = u_boot_console.config.env.get('env__net_nfs_readable_file', None)
+ if not f:
+ pytest.skip('No NFS readable file to read')
+
+ addr = f.get('addr', None)
+ if not addr:
+ addr = u_boot_utils.find_ram_base(u_boot_console) + (1024 * 1024 * 4)
+
+ fn = f['fn']
+ output = u_boot_console.run_command('nfs %x %s' % (addr, fn))
+ expected_text = 'Bytes transferred = '
+ sz = f.get('size', None)
+ if sz:
+ expected_text += '%d' % sz
+ assert expected_text in output
+
+ expected_crc = f.get('crc32', None)
+ if not expected_crc:
+ return
+
+ if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+ return
+
+ output = u_boot_console.run_command('crc32 %x $filesize' % addr)
+ assert expected_crc in output
diff --git a/test/py/tests/test_sleep.py b/test/py/tests/test_sleep.py
index 5c1a262..b59a4cf 100644
--- a/test/py/tests/test_sleep.py
+++ b/test/py/tests/test_sleep.py
@@ -9,6 +9,8 @@
"""Test the sleep command, and validate that it sleeps for approximately
the correct amount of time."""
+ if u_boot_console.config.buildconfig.get('config_cmd_misc', 'n') != 'y':
+ pytest.skip('sleep command not supported')
# 3s isn't too long, but is enough to cross a few second boundaries.
sleep_time = 3
tstart = time.time()
diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index 021892b..6e62820 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -53,7 +53,7 @@
util.run_and_log(cons, 'dtc %s %s%s -O dtb '
'-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
- def run_bootm(sha_algo, test_type, expect_string):
+ def run_bootm(sha_algo, test_type, expect_string, boots):
"""Run a 'bootm' command U-Boot.
This always starts a fresh U-Boot instance since the device tree may
@@ -64,6 +64,8 @@
expect_string: A string which is expected in the output.
sha_algo: Either 'sha1' or 'sha256', to select the algorithm to
use.
+ boots: A boolean that is True if Linux should boot and False if
+ we are expected to not boot
"""
cons.restart_uboot()
with cons.log.section('Verified boot %s %s' % (sha_algo, test_type)):
@@ -72,6 +74,8 @@
'fdt addr 100',
'bootm 100'])
assert(expect_string in ''.join(output))
+ if boots:
+ assert('sandbox: continuing, as we cannot run' in ''.join(output))
def make_fit(its):
"""Make a new FIT from the .its source file.
@@ -117,22 +121,22 @@
# Build the FIT, but don't sign anything yet
cons.log.action('%s: Test FIT with signed images' % sha_algo)
make_fit('sign-images-%s.its' % sha_algo)
- run_bootm(sha_algo, 'unsigned images', 'dev-')
+ run_bootm(sha_algo, 'unsigned images', 'dev-', True)
# Sign images with our dev keys
sign_fit(sha_algo)
- run_bootm(sha_algo, 'signed images', 'dev+')
+ run_bootm(sha_algo, 'signed images', 'dev+', True)
# Create a fresh .dtb without the public keys
dtc('sandbox-u-boot.dts')
cons.log.action('%s: Test FIT with signed configuration' % sha_algo)
make_fit('sign-configs-%s.its' % sha_algo)
- run_bootm(sha_algo, 'unsigned config', '%s+ OK' % sha_algo)
+ run_bootm(sha_algo, 'unsigned config', '%s+ OK' % sha_algo, True)
# Sign images with our dev keys
sign_fit(sha_algo)
- run_bootm(sha_algo, 'signed config', 'dev+')
+ run_bootm(sha_algo, 'signed config', 'dev+', True)
cons.log.action('%s: Check signed config on the host' % sha_algo)
@@ -149,7 +153,7 @@
util.run_and_log(cons, 'fdtput -t bx %s %s value %s' %
(fit, sig_node, sig))
- run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash')
+ run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash', False)
cons.log.action('%s: Check bad config on the host' % sha_algo)
util.run_and_log_expect_exception(cons, [fit_check_sign, '-f', fit,
diff --git a/tools/Makefile b/tools/Makefile
index 421414b..5b81dde 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -13,6 +13,7 @@
CONFIG_XWAY_SWAP_BYTES = y
CONFIG_NETCONSOLE = y
CONFIG_SHA1_CHECK_UB_IMG = y
+CONFIG_ARCH_SUNXI = y
endif
subdir-$(HOST_TOOLS_ALL) += easylogo
@@ -89,6 +90,7 @@
os_support.o \
pblimage.o \
pbl_crc32.o \
+ vybridimage.o \
$(ROCKCHIP_OBS) \
socfpgaimage.o \
lib/sha1.o \
@@ -110,7 +112,7 @@
# Build a libfdt Python module if swig is available
# Use 'sudo apt-get install swig libpython-dev' to enable this
hostprogs-$(CONFIG_SPL_OF_PLATDATA) += \
- $(if $(shell which swig),_libfdt.so)
+ $(if $(shell which swig 2> /dev/null),_libfdt.so)
_libfdt.so-sharedobjs += $(LIBFDT_OBJS)
libfdt:
@@ -168,7 +170,7 @@
hostprogs-$(CONFIG_MX28) += mxsboot
HOSTCFLAGS_mxsboot.o := -pedantic
-hostprogs-$(CONFIG_SUNXI) += mksunxiboot
+hostprogs-$(CONFIG_ARCH_SUNXI) += mksunxiboot
hostprogs-$(CONFIG_NETCONSOLE) += ncb
hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1
diff --git a/tools/binman/.gitignore b/tools/binman/.gitignore
new file mode 100644
index 0000000..0d20b64
--- /dev/null
+++ b/tools/binman/.gitignore
@@ -0,0 +1 @@
+*.pyc
diff --git a/tools/binman/README b/tools/binman/README
new file mode 100644
index 0000000..cb47e73
--- /dev/null
+++ b/tools/binman/README
@@ -0,0 +1,541 @@
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Introduction
+------------
+
+Firmware often consists of several components which must be packaged together.
+For example, we may have SPL, U-Boot, a device tree and an environment area
+grouped together and placed in MMC flash. When the system starts, it must be
+able to find these pieces.
+
+So far U-Boot has not provided a way to handle creating such images in a
+general way. Each SoC does what it needs to build an image, often packing or
+concatenating images in the U-Boot build system.
+
+Binman aims to provide a mechanism for building images, from simple
+SPL + U-Boot combinations, to more complex arrangements with many parts.
+
+
+What it does
+------------
+
+Binman reads your board's device tree and finds a node which describes the
+required image layout. It uses this to work out what to place where. The
+output file normally contains the device tree, so it is in principle possible
+to read an image and extract its constituent parts.
+
+
+Features
+--------
+
+So far binman is pretty simple. It supports binary blobs, such as 'u-boot',
+'spl' and 'fdt'. It supports empty entries (such as setting to 0xff). It can
+place entries at a fixed location in the image, or fit them together with
+suitable padding and alignment. It provides a way to process binaries before
+they are included, by adding a Python plug-in. The device tree is available
+to U-Boot at run-time so that the images can be interpreted.
+
+Binman does not yet update the device tree with the final location of
+everything when it is done. A simple C structure could be generated for
+constrained environments like SPL (using dtoc) but this is also not
+implemented.
+
+Binman can also support incorporating filesystems in the image if required.
+For example x86 platforms may use CBFS in some cases.
+
+Binman is intended for use with U-Boot but is designed to be general enough
+to be useful in other image-packaging situations.
+
+
+Motivation
+----------
+
+Packaging of firmware is quite a different task from building the various
+parts. In many cases the various binaries which go into the image come from
+separate build systems. For example, ARM Trusted Firmware is used on ARMv8
+devices but is not built in the U-Boot tree. If a Linux kernel is included
+in the firmware image, it is built elsewhere.
+
+It is of course possible to add more and more build rules to the U-Boot
+build system to cover these cases. It can shell out to other Makefiles and
+build scripts. But it seems better to create a clear divide between building
+software and packaging it.
+
+At present this is handled by manual instructions, different for each board,
+on how to create images that will boot. By turning these instructions into a
+standard format, we can support making valid images for any board without
+manual effort, lots of READMEs, etc.
+
+Benefits:
+- Each binary can have its own build system and tool chain without creating
+any dependencies between them
+- Avoids the need for a single-shot build: individual parts can be updated
+and brought in as needed
+- Provides for a standard image description available in the build and at
+run-time
+- SoC-specific image-signing tools can be accomodated
+- Avoids cluttering the U-Boot build system with image-building code
+- The image description is automatically available at run-time in U-Boot,
+SPL. It can be made available to other software also
+- The image description is easily readable (it's a text file in device-tree
+format) and permits flexible packing of binaries
+
+
+Terminology
+-----------
+
+Binman uses the following terms:
+
+- image - an output file containing a firmware image
+- binary - an input binary that goes into the image
+
+
+Relationship to FIT
+-------------------
+
+FIT is U-Boot's official image format. It supports multiple binaries with
+load / execution addresses, compression. It also supports verification
+through hashing and RSA signatures.
+
+FIT was originally designed to support booting a Linux kernel (with an
+optional ramdisk) and device tree chosen from various options in the FIT.
+Now that U-Boot supports configuration via device tree, it is possible to
+load U-Boot from a FIT, with the device tree chosen by SPL.
+
+Binman considers FIT to be one of the binaries it can place in the image.
+
+Where possible it is best to put as much as possible in the FIT, with binman
+used to deal with cases not covered by FIT. Examples include initial
+execution (since FIT itself does not have an executable header) and dealing
+with device boundaries, such as the read-only/read-write separation in SPI
+flash.
+
+For U-Boot, binman should not be used to create ad-hoc images in place of
+FIT.
+
+
+Relationship to mkimage
+-----------------------
+
+The mkimage tool provides a means to create a FIT. Traditionally it has
+needed an image description file: a device tree, like binman, but in a
+different format. More recently it has started to support a '-f auto' mode
+which can generate that automatically.
+
+More relevant to binman, mkimage also permits creation of many SoC-specific
+image types. These can be listed by running 'mkimage -T list'. Examples
+include 'rksd', the Rockchip SD/MMC boot format. The mkimage tool is often
+called from the U-Boot build system for this reason.
+
+Binman considers the output files created by mkimage to be binary blobs
+which it can place in an image. Binman does not replace the mkimage tool or
+this purpose. It would be possible in some situtions to create a new entry
+type for the images in mkimage, but this would not add functionality. It
+seems better to use the mkiamge tool to generate binaries and avoid blurring
+the boundaries between building input files (mkimage) and packaging then
+into a final image (binman).
+
+
+Example use of binman in U-Boot
+-------------------------------
+
+Binman aims to replace some of the ad-hoc image creation in the U-Boot
+build system.
+
+Consider sunxi. It has the following steps:
+
+1. It uses a custom mksunxiboot tool to build an SPL image called
+sunxi-spl.bin. This should probably move into mkimage.
+
+2. It uses mkimage to package U-Boot into a legacy image file (so that it can
+hold the load and execution address) called u-boot.img.
+
+3. It builds a final output image called u-boot-sunxi-with-spl.bin which
+consists of sunxi-spl.bin, some padding and u-boot.img.
+
+Binman is intended to replace the last step. The U-Boot build system builds
+u-boot.bin and sunxi-spl.bin. Binman can then take over creation of
+sunxi-spl.bin (by calling mksunxiboot, or hopefully one day mkimage). In any
+case, it would then create the image from the component parts.
+
+This simplifies the U-Boot Makefile somewhat, since various pieces of logic
+can be replaced by a call to binman.
+
+
+Example use of binman for x86
+-----------------------------
+
+In most cases x86 images have a lot of binary blobs, 'black-box' code
+provided by Intel which must be run for the platform to work. Typically
+these blobs are not relocatable and must be placed at fixed areas in the
+firmare image.
+
+Currently this is handled by ifdtool, which places microcode, FSP, MRC, VGA
+BIOS, reference code and Intel ME binaries into a u-boot.rom file.
+
+Binman is intended to replace all of this, with ifdtool left to handle only
+the configuration of the Intel-format descriptor.
+
+
+Running binman
+--------------
+
+Type:
+
+ binman -b <board_name>
+
+to build an image for a board. The board name is the same name used when
+configuring U-Boot (e.g. for sandbox_defconfig the board name is 'sandbox').
+Binman assumes that the input files for the build are in ../b/<board_name>.
+
+Or you can specify this explicitly:
+
+ binman -I <build_path>
+
+where <build_path> is the build directory containing the output of the U-Boot
+build.
+
+(Future work will make this more configurable)
+
+In either case, binman picks up the device tree file (u-boot.dtb) and looks
+for its instructions in the 'binman' node.
+
+Binman has a few other options which you can see by running 'binman -h'.
+
+
+Image description format
+------------------------
+
+The binman node is called 'binman'. An example image description is shown
+below:
+
+ binman {
+ filename = "u-boot-sunxi-with-spl.bin";
+ pad-byte = <0xff>;
+ blob {
+ filename = "spl/sunxi-spl.bin";
+ };
+ u-boot {
+ pos = <CONFIG_SPL_PAD_TO>;
+ };
+ };
+
+
+This requests binman to create an image file called u-boot-sunxi-with-spl.bin
+consisting of a specially formatted SPL (spl/sunxi-spl.bin, built by the
+normal U-Boot Makefile), some 0xff padding, and a U-Boot legacy image. The
+padding comes from the fact that the second binary is placed at
+CONFIG_SPL_PAD_TO. If that line were omitted then the U-Boot binary would
+immediately follow the SPL binary.
+
+The binman node describes an image. The sub-nodes describe entries in the
+image. Each entry represents a region within the overall image. The name of
+the entry (blob, u-boot) tells binman what to put there. For 'blob' we must
+provide a filename. For 'u-boot', binman knows that this means 'u-boot.bin'.
+
+Entries are normally placed into the image sequentially, one after the other.
+The image size is the total size of all entries. As you can see, you can
+specify the start position of an entry using the 'pos' property.
+
+Note that due to a device tree requirement, all entries must have a unique
+name. If you want to put the same binary in the image multiple times, you can
+use any unique name, with the 'type' property providing the type.
+
+The attributes supported for entries are described below.
+
+pos:
+ This sets the position of an entry within the image. The first byte
+ of the image is normally at position 0. If 'pos' is not provided,
+ binman sets it to the end of the previous region, or the start of
+ the image's entry area (normally 0) if there is no previous region.
+
+align:
+ This sets the alignment of the entry. The entry position is adjusted
+ so that the entry starts on an aligned boundary within the image. For
+ example 'align = <16>' means that the entry will start on a 16-byte
+ boundary. Alignment shold be a power of 2. If 'align' is not
+ provided, no alignment is performed.
+
+size:
+ This sets the size of the entry. The contents will be padded out to
+ this size. If this is not provided, it will be set to the size of the
+ contents.
+
+pad-before:
+ Padding before the contents of the entry. Normally this is 0, meaning
+ that the contents start at the beginning of the entry. This can be
+ offset the entry contents a little. Defaults to 0.
+
+pad-after:
+ Padding after the contents of the entry. Normally this is 0, meaning
+ that the entry ends at the last byte of content (unless adjusted by
+ other properties). This allows room to be created in the image for
+ this entry to expand later. Defaults to 0.
+
+align-size:
+ This sets the alignment of the entry size. For example, to ensure
+ that the size of an entry is a multiple of 64 bytes, set this to 64.
+ If 'align-size' is not provided, no alignment is performed.
+
+align-end:
+ This sets the alignment of the end of an entry. Some entries require
+ that they end on an alignment boundary, regardless of where they
+ start. If 'align-end' is not provided, no alignment is performed.
+
+ Note: This is not yet implemented in binman.
+
+filename:
+ For 'blob' types this provides the filename containing the binary to
+ put into the entry. If binman knows about the entry type (like
+ u-boot-bin), then there is no need to specify this.
+
+type:
+ Sets the type of an entry. This defaults to the entry name, but it is
+ possible to use any name, and then add (for example) 'type = "u-boot"'
+ to specify the type.
+
+
+The attributes supported for images are described below. Several are similar
+to those for entries.
+
+size:
+ Sets the image size in bytes, for example 'size = <0x100000>' for a
+ 1MB image.
+
+align-size:
+ This sets the alignment of the image size. For example, to ensure
+ that the image ends on a 512-byte boundary, use 'align-size = <512>'.
+ If 'align-size' is not provided, no alignment is performed.
+
+pad-before:
+ This sets the padding before the image entries. The first entry will
+ be positionad after the padding. This defaults to 0.
+
+pad-after:
+ This sets the padding after the image entries. The padding will be
+ placed after the last entry. This defaults to 0.
+
+pad-byte:
+ This specifies the pad byte to use when padding in the image. It
+ defaults to 0. To use 0xff, you would add 'pad-byte = <0xff>'.
+
+filename:
+ This specifies the image filename. It defaults to 'image.bin'.
+
+sort-by-pos:
+ This causes binman to reorder the entries as needed to make sure they
+ are in increasing positional order. This can be used when your entry
+ order may not match the positional order. A common situation is where
+ the 'pos' properties are set by CONFIG options, so their ordering is
+ not known a priori.
+
+ This is a boolean property so needs no value. To enable it, add a
+ line 'sort-by-pos;' to your description.
+
+multiple-images:
+ Normally only a single image is generated. To create more than one
+ image, put this property in the binman node. For example, this will
+ create image1.bin containing u-boot.bin, and image2.bin containing
+ both spl/u-boot-spl.bin and u-boot.bin:
+
+ binman {
+ multiple-images;
+ image1 {
+ u-boot {
+ };
+ };
+
+ image2 {
+ spl {
+ };
+ u-boot {
+ };
+ };
+ };
+
+end-at-4gb:
+ For x86 machines the ROM positions start just before 4GB and extend
+ up so that the image finished at the 4GB boundary. This boolean
+ option can be enabled to support this. The image size must be
+ provided so that binman knows when the image should start. For an
+ 8MB ROM, the position of the first entry would be 0xfff80000 with
+ this option, instead of 0 without this option.
+
+
+Examples of the above options can be found in the tests. See the
+tools/binman/test directory.
+
+
+Special properties
+------------------
+
+Some entries support special properties, documented here:
+
+u-boot-with-ucode-ptr:
+ optional-ucode: boolean property to make microcode optional. If the
+ u-boot.bin image does not include microcode, no error will
+ be generated.
+
+
+Order of image creation
+-----------------------
+
+Image creation proceeds in the following order, for each entry in the image.
+
+1. GetEntryContents() - the contents of each entry are obtained, normally by
+reading from a file. This calls the Entry.ObtainContents() to read the
+contents. The default version of Entry.ObtainContents() calls
+Entry.GetDefaultFilename() and then reads that file. So a common mechanism
+to select a file to read is to override that function in the subclass. The
+functions must return True when they have read the contents. Binman will
+retry calling the functions a few times if False is returned, allowing
+dependencies between the contents of different entries.
+
+2. GetEntryPositions() - calls Entry.GetPositions() for each entry. This can
+return a dict containing entries that need updating. The key should be the
+entry name and the value is a tuple (pos, size). This allows an entry to
+provide the position and size for other entries. The default implementation
+of GetEntryPositions() returns {}.
+
+3. PackEntries() - calls Entry.Pack() which figures out the position and
+size of an entry. The 'current' image position is passed in, and the function
+returns the position immediately after the entry being packed. The default
+implementation of Pack() is usually sufficient.
+
+4. CheckSize() - checks that the contents of all the entries fits within
+the image size. If the image does not have a defined size, the size is set
+large enough to hold all the entries.
+
+5. CheckEntries() - checks that the entries do not overlap, nor extend
+outside the image.
+
+6. ProcessEntryContents() - this calls Entry.ProcessContents() on each entry.
+The default implementatoin does nothing. This can be overriden to adjust the
+contents of an entry in some way. For example, it would be possible to create
+an entry containing a hash of the contents of some other entries. At this
+stage the position and size of entries should not be adjusted.
+
+7. BuildImage() - builds the image and writes it to a file. This is the final
+step.
+
+
+Automatic .dtsi inclusion
+-------------------------
+
+It is sometimes inconvenient to add a 'binman' node to the .dts file for each
+board. This can be done by using #include to bring in a common file. Another
+approach supported by the U-Boot build system is to automatically include
+a common header. You can then put the binman node (and anything else that is
+specific to U-Boot, such as u-boot,dm-pre-reloc properies) in that header
+file.
+
+Binman will search for the following files in arch/<arch>/dts:
+
+ <dts>-u-boot.dtsi where <dts> is the base name of the .dts file
+ <CONFIG_SYS_SOC>-u-boot.dtsi
+ <CONFIG_SYS_CPU>-u-boot.dtsi
+ <CONFIG_SYS_VENDOR>-u-boot.dtsi
+ u-boot.dtsi
+
+U-Boot will only use the first one that it finds. If you need to include a
+more general file you can do that from the more specific file using #include.
+If you are having trouble figuring out what is going on, you can uncomment
+the 'warning' line in scripts/Makefile.lib to see what it has found:
+
+ # Uncomment for debugging
+ # $(warning binman_dtsi_options: $(binman_dtsi_options))
+
+
+Code coverage
+-------------
+
+Binman is a critical tool and is designed to be very testable. Entry
+implementations target 100% test coverage. Run 'binman -T' to check this.
+
+To enable Python test coverage on Debian-type distributions (e.g. Ubuntu):
+
+ $ sudo apt-get install python-pip python-pytest
+ $ sudo pip install coverage
+
+
+Advanced Features / Technical docs
+----------------------------------
+
+The behaviour of entries is defined by the Entry class. All other entries are
+a subclass of this. An important subclass is Entry_blob which takes binary
+data from a file and places it in the entry. In fact most entry types are
+subclasses of Entry_blob.
+
+Each entry type is a separate file in the tools/binman/etype directory. Each
+file contains a class called Entry_<type> where <type> is the entry type.
+New entry types can be supported by adding new files in that directory.
+These will automatically be detected by binman when needed.
+
+Entry properties are documented in entry.py. The entry subclasses are free
+to change the values of properties to support special behaviour. For example,
+when Entry_blob loads a file, it sets content_size to the size of the file.
+Entry classes can adjust other entries. For example, an entry that knows
+where other entries should be positioned can set up those entries' positions
+so they don't need to be set in the binman decription. It can also adjust
+entry contents.
+
+Most of the time such essoteric behaviour is not needed, but it can be
+essential for complex images.
+
+
+History / Credits
+-----------------
+
+Binman takes a lot of inspiration from a Chrome OS tool called
+'cros_bundle_firmware', which I wrote some years ago. That tool was based on
+a reasonably simple and sound design but has expanded greatly over the
+years. In particular its handling of x86 images is convoluted.
+
+Quite a few lessons have been learned which are hopefully be applied here.
+
+
+Design notes
+------------
+
+On the face of it, a tool to create firmware images should be fairly simple:
+just find all the input binaries and place them at the right place in the
+image. The difficulty comes from the wide variety of input types (simple
+flat binaries containing code, packaged data with various headers), packing
+requirments (alignment, spacing, device boundaries) and other required
+features such as hierarchical images.
+
+The design challenge is to make it easy to create simple images, while
+allowing the more complex cases to be supported. For example, for most
+images we don't much care exactly where each binary ends up, so we should
+not have to specify that unnecessarily.
+
+New entry types should aim to provide simple usage where possible. If new
+core features are needed, they can be added in the Entry base class.
+
+
+To do
+-----
+
+Some ideas:
+- Fill out the device tree to include the final position and size of each
+ entry (since the input file may not always specify these)
+- Use of-platdata to make the information available to code that is unable
+ to use device tree (such as a very small SPL image)
+- Write an image map to a text file
+- Allow easy building of images by specifying just the board name
+- Produce a full Python binding for libfdt (for upstream)
+- Add an option to decode an image into the constituent binaries
+- Suppoort hierarchical images (packing of binaries into another binary
+ which is then placed in the image)
+- Support building an image for a board (-b) more completely, with a
+ configurable build directory
+- Consider making binman work with buildman, although if it is used in the
+ Makefile, this will be automatic
+- Implement align-end
+
+--
+Simon Glass <sjg@chromium.org>
+7/7/2016
diff --git a/tools/binman/binman b/tools/binman/binman
new file mode 120000
index 0000000..979b7e4
--- /dev/null
+++ b/tools/binman/binman
@@ -0,0 +1 @@
+binman.py
\ No newline at end of file
diff --git a/tools/binman/binman.py b/tools/binman/binman.py
new file mode 100755
index 0000000..4cc431f
--- /dev/null
+++ b/tools/binman/binman.py
@@ -0,0 +1,114 @@
+#!/usr/bin/env python
+
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Creates binary images from input files controlled by a description
+#
+
+"""See README for more information"""
+
+import os
+import sys
+import traceback
+import unittest
+
+# Bring in the patman and dtoc libraries
+our_path = os.path.dirname(os.path.realpath(__file__))
+sys.path.append(os.path.join(our_path, '../patman'))
+sys.path.append(os.path.join(our_path, '../dtoc'))
+
+# Also allow entry-type modules to be brought in from the etype directory.
+sys.path.append(os.path.join(our_path, 'etype'))
+
+import cmdline
+import command
+import control
+
+def RunTests():
+ """Run the functional tests and any embedded doctests"""
+ import entry_test
+ import fdt_test
+ import func_test
+ import test
+ import doctest
+
+ result = unittest.TestResult()
+ for module in []:
+ suite = doctest.DocTestSuite(module)
+ suite.run(result)
+
+ sys.argv = [sys.argv[0]]
+ for module in (func_test.TestFunctional, fdt_test.TestFdt,
+ entry_test.TestEntry):
+ suite = unittest.TestLoader().loadTestsFromTestCase(module)
+ suite.run(result)
+
+ print result
+ for test, err in result.errors:
+ print test.id(), err
+ for test, err in result.failures:
+ print err
+
+def RunTestCoverage():
+ """Run the tests and check that we get 100% coverage"""
+ # This uses the build output from sandbox_spl to get _libfdt.so
+ cmd = ('PYTHONPATH=%s/sandbox_spl/tools coverage run '
+ '--include "tools/binman/*.py" --omit "*test*,*binman.py" '
+ 'tools/binman/binman.py -t' % options.build_dir)
+ os.system(cmd)
+ stdout = command.Output('coverage', 'report')
+ coverage = stdout.splitlines()[-1].split(' ')[-1]
+ if coverage != '100%':
+ print stdout
+ print "Type 'coverage html' to get a report in htmlcov/index.html"
+ raise ValueError('Coverage error: %s, but should be 100%%' % coverage)
+
+
+def RunBinman(options, args):
+ """Main entry point to binman once arguments are parsed
+
+ Args:
+ options: Command-line options
+ args: Non-option arguments
+ """
+ ret_code = 0
+
+ # For testing: This enables full exception traces.
+ #options.debug = True
+
+ if not options.debug:
+ sys.tracebacklimit = 0
+
+ if options.test:
+ RunTests()
+
+ elif options.test_coverage:
+ RunTestCoverage()
+
+ elif options.full_help:
+ pager = os.getenv('PAGER')
+ if not pager:
+ pager = 'more'
+ fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
+ 'README')
+ command.Run(pager, fname)
+
+ else:
+ try:
+ ret_code = control.Binman(options, args)
+ except Exception as e:
+ print 'binman: %s' % e
+ if options.debug:
+ print
+ traceback.print_exc()
+ ret_code = 1
+ return ret_code
+
+
+if __name__ == "__main__":
+ (options, args) = cmdline.ParseArgs(sys.argv)
+ ret_code = RunBinman(options, args)
+ sys.exit(ret_code)
diff --git a/tools/binman/cmdline.py b/tools/binman/cmdline.py
new file mode 100644
index 0000000..233d5e1
--- /dev/null
+++ b/tools/binman/cmdline.py
@@ -0,0 +1,53 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Command-line parser for binman
+#
+
+from optparse import OptionParser
+
+def ParseArgs(argv):
+ """Parse the binman command-line arguments
+
+ Args:
+ argv: List of string arguments
+ Returns:
+ Tuple (options, args) with the command-line options and arugments.
+ options provides access to the options (e.g. option.debug)
+ args is a list of string arguments
+ """
+ parser = OptionParser()
+ parser.add_option('-b', '--board', type='string',
+ help='Board name to build')
+ parser.add_option('-B', '--build-dir', type='string', default='b',
+ help='Directory containing the build output')
+ parser.add_option('-d', '--dt', type='string',
+ help='Configuration file (.dtb) to use')
+ parser.add_option('-D', '--debug', action='store_true',
+ help='Enabling debugging (provides a full traceback on error)')
+ parser.add_option('-I', '--indir', action='append',
+ help='Add a path to a directory to use for input files')
+ parser.add_option('-H', '--full-help', action='store_true',
+ default=False, help='Display the README file')
+ parser.add_option('-O', '--outdir', type='string',
+ action='store', help='Path to directory to use for intermediate and '
+ 'output files')
+ parser.add_option('-p', '--preserve', action='store_true',\
+ help='Preserve temporary output directory even if option -O is not '
+ 'given')
+ parser.add_option('-t', '--test', action='store_true',
+ default=False, help='run tests')
+ parser.add_option('-T', '--test-coverage', action='store_true',
+ default=False, help='run tests and check for 100% coverage')
+ parser.add_option('-v', '--verbosity', default=1,
+ type='int', help='Control verbosity: 0=silent, 1=progress, 3=full, '
+ '4=debug')
+
+ parser.usage += """
+
+Create images for a board from a set of binaries. It is controlled by a
+description in the board device tree."""
+
+ return parser.parse_args(argv)
diff --git a/tools/binman/control.py b/tools/binman/control.py
new file mode 100644
index 0000000..e909678
--- /dev/null
+++ b/tools/binman/control.py
@@ -0,0 +1,118 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Creates binary images from input files controlled by a description
+#
+
+from collections import OrderedDict
+import os
+import sys
+import tools
+
+import command
+import fdt_select
+import fdt_util
+from image import Image
+import tout
+
+# List of images we plan to create
+# Make this global so that it can be referenced from tests
+images = OrderedDict()
+
+def _ReadImageDesc(binman_node):
+ """Read the image descriptions from the /binman node
+
+ This normally produces a single Image object called 'image'. But if
+ multiple images are present, they will all be returned.
+
+ Args:
+ binman_node: Node object of the /binman node
+ Returns:
+ OrderedDict of Image objects, each of which describes an image
+ """
+ images = OrderedDict()
+ if 'multiple-images' in binman_node.props:
+ for node in binman_node.subnodes:
+ images[node.name] = Image(node.name, node)
+ else:
+ images['image'] = Image('image', binman_node)
+ return images
+
+def _FindBinmanNode(fdt):
+ """Find the 'binman' node in the device tree
+
+ Args:
+ fdt: Fdt object to scan
+ Returns:
+ Node object of /binman node, or None if not found
+ """
+ for node in fdt.GetRoot().subnodes:
+ if node.name == 'binman':
+ return node
+ return None
+
+def Binman(options, args):
+ """The main control code for binman
+
+ This assumes that help and test options have already been dealt with. It
+ deals with the core task of building images.
+
+ Args:
+ options: Command line options object
+ args: Command line arguments (list of strings)
+ """
+ global images
+
+ if options.full_help:
+ pager = os.getenv('PAGER')
+ if not pager:
+ pager = 'more'
+ fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
+ 'README')
+ command.Run(pager, fname)
+ return 0
+
+ # Try to figure out which device tree contains our image description
+ if options.dt:
+ dtb_fname = options.dt
+ else:
+ board = options.board
+ if not board:
+ raise ValueError('Must provide a board to process (use -b <board>)')
+ board_pathname = os.path.join(options.build_dir, board)
+ dtb_fname = os.path.join(board_pathname, 'u-boot.dtb')
+ if not options.indir:
+ options.indir = ['.']
+ options.indir.append(board_pathname)
+
+ try:
+ tout.Init(options.verbosity)
+ try:
+ tools.SetInputDirs(options.indir)
+ tools.PrepareOutputDir(options.outdir, options.preserve)
+ fdt = fdt_select.FdtScan(dtb_fname)
+ node = _FindBinmanNode(fdt)
+ if not node:
+ raise ValueError("Device tree '%s' does not have a 'binman' "
+ "node" % dtb_fname)
+ images = _ReadImageDesc(node)
+ for image in images.values():
+ # Perform all steps for this image, including checking and
+ # writing it. This means that errors found with a later
+ # image will be reported after earlier images are already
+ # completed and written, but that does not seem important.
+ image.GetEntryContents()
+ image.GetEntryPositions()
+ image.PackEntries()
+ image.CheckSize()
+ image.CheckEntries()
+ image.ProcessEntryContents()
+ image.BuildImage()
+ finally:
+ tools.FinaliseOutputDir()
+ finally:
+ tout.Uninit()
+
+ return 0
diff --git a/tools/binman/entry_test.py b/tools/binman/entry_test.py
new file mode 100644
index 0000000..8a9ae01
--- /dev/null
+++ b/tools/binman/entry_test.py
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Test for the Entry class
+
+import collections
+import unittest
+
+import entry
+
+class TestEntry(unittest.TestCase):
+ def testEntryContents(self):
+ """Test the Entry bass class"""
+ base_entry = entry.Entry(None, None, None, read_node=False)
+ self.assertEqual(True, base_entry.ObtainContents())
+
+ def testUnknownEntry(self):
+ """Test that unknown entry types are detected"""
+ Node = collections.namedtuple('Node', ['name', 'path'])
+ node = Node('invalid-name', 'invalid-path')
+ with self.assertRaises(ValueError) as e:
+ entry.Entry.Create(None, node, node.name)
+ self.assertIn("Unknown entry type 'invalid-name' in node "
+ "'invalid-path'", str(e.exception))
diff --git a/tools/binman/etype/_testing.py b/tools/binman/etype/_testing.py
new file mode 100644
index 0000000..1783098
--- /dev/null
+++ b/tools/binman/etype/_testing.py
@@ -0,0 +1,26 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for testing purposes. Not used in real images.
+#
+
+from entry import Entry
+import fdt_util
+import tools
+
+class Entry__testing(Entry):
+ def __init__(self, image, etype, node):
+ Entry.__init__(self, image, etype, node)
+
+ def ObtainContents(self):
+ self.data = 'a'
+ self.contents_size = len(self.data)
+ return True
+
+ def ReadContents(self):
+ return True
+
+ def GetPositions(self):
+ return {'invalid-entry': [1, 2]}
diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py
new file mode 100644
index 0000000..def2164
--- /dev/null
+++ b/tools/binman/etype/blob.py
@@ -0,0 +1,37 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for blobs, which are binary objects read from files
+#
+
+from entry import Entry
+import fdt_util
+import tools
+
+class Entry_blob(Entry):
+ def __init__(self, image, etype, node):
+ Entry.__init__(self, image, etype, node)
+ self._filename = fdt_util.GetString(self._node, "filename", self.etype)
+
+ def ObtainContents(self):
+ self._filename = self.GetDefaultFilename()
+ self._pathname = tools.GetInputFilename(self._filename)
+ self.ReadContents()
+ return True
+
+ def ReadContents(self):
+ with open(self._pathname) as fd:
+ # We assume the data is small enough to fit into memory. If this
+ # is used for large filesystem image that might not be true.
+ # In that case, Image.BuildImage() could be adjusted to use a
+ # new Entry method which can read in chunks. Then we could copy
+ # the data in chunks and avoid reading it all at once. For now
+ # this seems like an unnecessary complication.
+ self.data = fd.read()
+ self.contents_size = len(self.data)
+ return True
+
+ def GetDefaultFilename(self):
+ return self._filename
diff --git a/tools/binman/etype/entry.py b/tools/binman/etype/entry.py
new file mode 100644
index 0000000..67c5734
--- /dev/null
+++ b/tools/binman/etype/entry.py
@@ -0,0 +1,200 @@
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Base class for all entries
+#
+
+# importlib was introduced in Python 2.7 but there was a report of it not
+# working in 2.7.12, so we work around this:
+# http://lists.denx.de/pipermail/u-boot/2016-October/269729.html
+try:
+ import importlib
+ have_importlib = True
+except:
+ have_importlib = False
+
+import fdt_util
+import tools
+
+modules = {}
+
+class Entry(object):
+ """An Entry in the image
+
+ An entry corresponds to a single node in the device-tree description
+ of the image. Each entry ends up being a part of the final image.
+ Entries can be placed either right next to each other, or with padding
+ between them. The type of the entry determines the data that is in it.
+
+ This class is not used by itself. All entry objects are subclasses of
+ Entry.
+
+ Attributes:
+ image: The image containing this entry
+ node: The node that created this entry
+ pos: Absolute position of entry within the image, None if not known
+ size: Entry size in bytes, None if not known
+ contents_size: Size of contents in bytes, 0 by default
+ align: Entry start position alignment, or None
+ align_size: Entry size alignment, or None
+ align_end: Entry end position alignment, or None
+ pad_before: Number of pad bytes before the contents, 0 if none
+ pad_after: Number of pad bytes after the contents, 0 if none
+ data: Contents of entry (string of bytes)
+ """
+ def __init__(self, image, etype, node, read_node=True):
+ self.image = image
+ self.etype = etype
+ self._node = node
+ self.pos = None
+ self.size = None
+ self.contents_size = 0
+ self.align = None
+ self.align_size = None
+ self.align_end = None
+ self.pad_before = 0
+ self.pad_after = 0
+ self.pos_unset = False
+ if read_node:
+ self.ReadNode()
+
+ @staticmethod
+ def Create(image, node, etype=None):
+ """Create a new entry for a node.
+
+ Args:
+ image: Image object containing this node
+ node: Node object containing information about the entry to create
+ etype: Entry type to use, or None to work it out (used for tests)
+
+ Returns:
+ A new Entry object of the correct type (a subclass of Entry)
+ """
+ if not etype:
+ etype = fdt_util.GetString(node, 'type', node.name)
+ module_name = etype.replace('-', '_')
+ module = modules.get(module_name)
+
+ # Import the module if we have not already done so.
+ if not module:
+ try:
+ if have_importlib:
+ module = importlib.import_module(module_name)
+ else:
+ module = __import__(module_name)
+ except ImportError:
+ raise ValueError("Unknown entry type '%s' in node '%s'" %
+ (etype, node.path))
+ modules[module_name] = module
+
+ # Call its constructor to get the object we want.
+ obj = getattr(module, 'Entry_%s' % module_name)
+ return obj(image, etype, node)
+
+ def ReadNode(self):
+ """Read entry information from the node
+
+ This reads all the fields we recognise from the node, ready for use.
+ """
+ self.pos = fdt_util.GetInt(self._node, 'pos')
+ self.size = fdt_util.GetInt(self._node, 'size')
+ self.align = fdt_util.GetInt(self._node, 'align')
+ if tools.NotPowerOfTwo(self.align):
+ raise ValueError("Node '%s': Alignment %s must be a power of two" %
+ (self._node.path, self.align))
+ self.pad_before = fdt_util.GetInt(self._node, 'pad-before', 0)
+ self.pad_after = fdt_util.GetInt(self._node, 'pad-after', 0)
+ self.align_size = fdt_util.GetInt(self._node, 'align-size')
+ if tools.NotPowerOfTwo(self.align_size):
+ raise ValueError("Node '%s': Alignment size %s must be a power "
+ "of two" % (self._node.path, self.align_size))
+ self.align_end = fdt_util.GetInt(self._node, 'align-end')
+ self.pos_unset = fdt_util.GetBool(self._node, 'pos-unset')
+
+ def ObtainContents(self):
+ """Figure out the contents of an entry.
+
+ Returns:
+ True if the contents were found, False if another call is needed
+ after the other entries are processed.
+ """
+ # No contents by default: subclasses can implement this
+ return True
+
+ def Pack(self, pos):
+ """Figure out how to pack the entry into the image
+
+ Most of the time the entries are not fully specified. There may be
+ an alignment but no size. In that case we take the size from the
+ contents of the entry.
+
+ If an entry has no hard-coded position, it will be placed at @pos.
+
+ Once this function is complete, both the position and size of the
+ entry will be know.
+
+ Args:
+ Current image position pointer
+
+ Returns:
+ New image position pointer (after this entry)
+ """
+ if self.pos is None:
+ if self.pos_unset:
+ self.Raise('No position set with pos-unset: should another '
+ 'entry provide this correct position?')
+ self.pos = tools.Align(pos, self.align)
+ needed = self.pad_before + self.contents_size + self.pad_after
+ needed = tools.Align(needed, self.align_size)
+ size = self.size
+ if not size:
+ size = needed
+ new_pos = self.pos + size
+ aligned_pos = tools.Align(new_pos, self.align_end)
+ if aligned_pos != new_pos:
+ size = aligned_pos - self.pos
+ new_pos = aligned_pos
+
+ if not self.size:
+ self.size = size
+
+ if self.size < needed:
+ self.Raise("Entry contents size is %#x (%d) but entry size is "
+ "%#x (%d)" % (needed, needed, self.size, self.size))
+ # Check that the alignment is correct. It could be wrong if the
+ # and pos or size values were provided (i.e. not calculated), but
+ # conflict with the provided alignment values
+ if self.size != tools.Align(self.size, self.align_size):
+ self.Raise("Size %#x (%d) does not match align-size %#x (%d)" %
+ (self.size, self.size, self.align_size, self.align_size))
+ if self.pos != tools.Align(self.pos, self.align):
+ self.Raise("Position %#x (%d) does not match align %#x (%d)" %
+ (self.pos, self.pos, self.align, self.align))
+
+ return new_pos
+
+ def Raise(self, msg):
+ """Convenience function to raise an error referencing a node"""
+ raise ValueError("Node '%s': %s" % (self._node.path, msg))
+
+ def GetPath(self):
+ """Get the path of a node
+
+ Returns:
+ Full path of the node for this entry
+ """
+ return self._node.path
+
+ def GetData(self):
+ return self.data
+
+ def GetPositions(self):
+ return {}
+
+ def SetPositionSize(self, pos, size):
+ self.pos = pos
+ self.size = size
+
+ def ProcessContents(self):
+ pass
diff --git a/tools/binman/etype/intel_cmc.py b/tools/binman/etype/intel_cmc.py
new file mode 100644
index 0000000..30676c8
--- /dev/null
+++ b/tools/binman/etype/intel_cmc.py
@@ -0,0 +1,14 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for Intel Chip Microcode binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_cmc(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
diff --git a/tools/binman/etype/intel_descriptor.py b/tools/binman/etype/intel_descriptor.py
new file mode 100644
index 0000000..7f4ea0b
--- /dev/null
+++ b/tools/binman/etype/intel_descriptor.py
@@ -0,0 +1,55 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for 'u-boot'
+#
+
+import struct
+
+from entry import Entry
+from blob import Entry_blob
+
+FD_SIGNATURE = struct.pack('<L', 0x0ff0a55a)
+MAX_REGIONS = 5
+
+(REGION_DESCRIPTOR, REGION_BIOS, REGION_ME, REGION_GBE,
+ REGION_PDATA) = range(5)
+
+class Region:
+ def __init__(self, data, frba, region_num):
+ pos = frba + region_num * 4
+ val = struct.unpack('<L', data[pos:pos + 4])[0]
+ self.base = (val & 0xfff) << 12
+ self.limit = ((val & 0x0fff0000) >> 4) | 0xfff
+ self.size = self.limit - self.base + 1
+
+class Entry_intel_descriptor(Entry_blob):
+ """Intel flash descriptor block (4KB)
+
+ This is placed at the start of flash and provides information about
+ the SPI flash regions. In particular it provides the base address and
+ size of the ME region, allowing us to place the ME binary in the right
+ place.
+ """
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+ self._regions = []
+
+ def GetDefaultFilename(self):
+ return 'descriptor.bin'
+
+ def GetPositions(self):
+ pos = self.data.find(FD_SIGNATURE)
+ if pos == -1:
+ self.Raise('Cannot find FD signature')
+ flvalsig, flmap0, flmap1, flmap2 = struct.unpack('<LLLL',
+ self.data[pos:pos + 16])
+ frba = ((flmap0 >> 16) & 0xff) << 4
+ for i in range(MAX_REGIONS):
+ self._regions.append(Region(self.data, frba, i))
+
+ # Set the offset for ME only, for now, since the others are not used
+ return {'intel-me': [self._regions[REGION_ME].base,
+ self._regions[REGION_ME].size]}
diff --git a/tools/binman/etype/intel_fsp.py b/tools/binman/etype/intel_fsp.py
new file mode 100644
index 0000000..13c9f05
--- /dev/null
+++ b/tools/binman/etype/intel_fsp.py
@@ -0,0 +1,14 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for Intel Firmware Support Package binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_fsp(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
diff --git a/tools/binman/etype/intel_me.py b/tools/binman/etype/intel_me.py
new file mode 100644
index 0000000..45ab50c
--- /dev/null
+++ b/tools/binman/etype/intel_me.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for Intel Management Engine binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_me(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'me.bin'
diff --git a/tools/binman/etype/intel_mrc.py b/tools/binman/etype/intel_mrc.py
new file mode 100644
index 0000000..f6cedb7
--- /dev/null
+++ b/tools/binman/etype/intel_mrc.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for Intel Memory Reference Code binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_mrc(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'mrc.bin'
diff --git a/tools/binman/etype/intel_vga.py b/tools/binman/etype/intel_vga.py
new file mode 100644
index 0000000..6693607
--- /dev/null
+++ b/tools/binman/etype/intel_vga.py
@@ -0,0 +1,14 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for x86 VGA ROM binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_vga(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
diff --git a/tools/binman/etype/u_boot.py b/tools/binman/etype/u_boot.py
new file mode 100644
index 0000000..1fcff73
--- /dev/null
+++ b/tools/binman/etype/u_boot.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for U-Boot binary
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'u-boot.bin'
diff --git a/tools/binman/etype/u_boot_dtb.py b/tools/binman/etype/u_boot_dtb.py
new file mode 100644
index 0000000..1122c95
--- /dev/null
+++ b/tools/binman/etype/u_boot_dtb.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for U-Boot device tree
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_dtb(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'u-boot.dtb'
diff --git a/tools/binman/etype/u_boot_dtb_with_ucode.py b/tools/binman/etype/u_boot_dtb_with_ucode.py
new file mode 100644
index 0000000..fc02c67
--- /dev/null
+++ b/tools/binman/etype/u_boot_dtb_with_ucode.py
@@ -0,0 +1,78 @@
+# Copyright (c) 2016 Google, Inc
+## Written by Simon Glass <sjg@chromium.org>
+
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for U-Boot device tree with the microcode removed
+#
+
+import fdt_select
+from entry import Entry
+from blob import Entry_blob
+import tools
+
+class Entry_u_boot_dtb_with_ucode(Entry_blob):
+ """A U-Boot device tree file, with the microcode removed
+
+ See Entry_u_boot_ucode for full details of the 3 entries involved in this
+ process.
+ """
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+ self.ucode_data = ''
+ self.collate = False
+ self.ucode_offset = None
+ self.ucode_size = None
+
+ def GetDefaultFilename(self):
+ return 'u-boot.dtb'
+
+ def ObtainContents(self):
+ Entry_blob.ObtainContents(self)
+
+ # If the image does not need microcode, there is nothing to do
+ ucode_dest_entry = self.image.FindEntryType('u-boot-spl-with-ucode-ptr')
+ if not ucode_dest_entry or not ucode_dest_entry.target_pos:
+ ucode_dest_entry = self.image.FindEntryType('u-boot-with-ucode-ptr')
+ if not ucode_dest_entry or not ucode_dest_entry.target_pos:
+ return True
+
+ # Create a new file to hold the copied device tree
+ dtb_name = 'u-boot-dtb-with-ucode.dtb'
+ fname = tools.GetOutputFilename(dtb_name)
+ with open(fname, 'wb') as fd:
+ fd.write(self.data)
+
+ # Remove the microcode
+ fdt = fdt_select.FdtScan(fname)
+ fdt.Scan()
+ ucode = fdt.GetNode('/microcode')
+ if not ucode:
+ raise self.Raise("No /microcode node found in '%s'" % fname)
+
+ # There's no need to collate it (move all microcode into one place)
+ # if we only have one chunk of microcode.
+ self.collate = len(ucode.subnodes) > 1
+ for node in ucode.subnodes:
+ data_prop = node.props.get('data')
+ if data_prop:
+ self.ucode_data += ''.join(data_prop.bytes)
+ if not self.collate:
+ poffset = data_prop.GetOffset()
+ if poffset is None:
+ # We cannot obtain a property offset. Collate instead.
+ self.collate = True
+ else:
+ # Find the offset in the device tree of the ucode data
+ self.ucode_offset = poffset + 12
+ self.ucode_size = len(data_prop.bytes)
+ if self.collate:
+ prop = node.DeleteProp('data')
+ if self.collate:
+ fdt.Pack()
+ fdt.Flush()
+
+ # Make this file the contents of this entry
+ self._pathname = fname
+ self.ReadContents()
+ return True
diff --git a/tools/binman/etype/u_boot_img.py b/tools/binman/etype/u_boot_img.py
new file mode 100644
index 0000000..744f1b4
--- /dev/null
+++ b/tools/binman/etype/u_boot_img.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for U-Boot binary
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_img(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'u-boot.img'
diff --git a/tools/binman/etype/u_boot_nodtb.py b/tools/binman/etype/u_boot_nodtb.py
new file mode 100644
index 0000000..3721c3b
--- /dev/null
+++ b/tools/binman/etype/u_boot_nodtb.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for 'u-boot-nodtb.bin'
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_nodtb(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'u-boot-nodtb.bin'
diff --git a/tools/binman/etype/u_boot_spl.py b/tools/binman/etype/u_boot_spl.py
new file mode 100644
index 0000000..68b0148
--- /dev/null
+++ b/tools/binman/etype/u_boot_spl.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for spl/u-boot-spl.bin
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_spl(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'spl/u-boot-spl.bin'
diff --git a/tools/binman/etype/u_boot_spl_bss_pad.py b/tools/binman/etype/u_boot_spl_bss_pad.py
new file mode 100644
index 0000000..c005f28
--- /dev/null
+++ b/tools/binman/etype/u_boot_spl_bss_pad.py
@@ -0,0 +1,26 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for BSS padding for spl/u-boot-spl.bin. This padding
+# can be added after the SPL binary to ensure that anything concatenated
+# to it will appear to SPL to be at the end of BSS rather than the start.
+#
+
+import command
+from entry import Entry
+from blob import Entry_blob
+import tools
+
+class Entry_u_boot_spl_bss_pad(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def ObtainContents(self):
+ fname = tools.GetInputFilename('spl/u-boot-spl')
+ args = [['nm', fname], ['grep', '__bss_size']]
+ out = command.RunPipe(args, capture=True).stdout.splitlines()
+ bss_size = int(out[0].split()[0], 16)
+ self.data = chr(0) * bss_size
+ self.contents_size = bss_size
diff --git a/tools/binman/etype/u_boot_spl_with_ucode_ptr.py b/tools/binman/etype/u_boot_spl_with_ucode_ptr.py
new file mode 100644
index 0000000..764c282
--- /dev/null
+++ b/tools/binman/etype/u_boot_spl_with_ucode_ptr.py
@@ -0,0 +1,28 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for an SPL binary with an embedded microcode pointer
+#
+
+import struct
+
+import command
+from entry import Entry
+from blob import Entry_blob
+from u_boot_with_ucode_ptr import Entry_u_boot_with_ucode_ptr
+import tools
+
+class Entry_u_boot_spl_with_ucode_ptr(Entry_u_boot_with_ucode_ptr):
+ """U-Boot SPL with embedded microcode pointer
+
+ See Entry_u_boot_ucode for full details of the entries involved in this
+ process.
+ """
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+ self.elf_fname = 'spl/u-boot-spl'
+
+ def GetDefaultFilename(self):
+ return 'spl/u-boot-spl.bin'
diff --git a/tools/binman/etype/u_boot_ucode.py b/tools/binman/etype/u_boot_ucode.py
new file mode 100644
index 0000000..8fe27ac
--- /dev/null
+++ b/tools/binman/etype/u_boot_ucode.py
@@ -0,0 +1,84 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for a U-Boot binary with an embedded microcode pointer
+#
+
+from entry import Entry
+from blob import Entry_blob
+import tools
+
+class Entry_u_boot_ucode(Entry_blob):
+ """U-Boot microcode block
+
+ U-Boot on x86 needs a single block of microcode. This is collected from
+ the various microcode update nodes in the device tree. It is also unable
+ to read the microcode from the device tree on platforms that use FSP
+ (Firmware Support Package) binaries, because the API requires that the
+ microcode is supplied before there is any SRAM available to use (i.e.
+ the FSP sets up the SRAM / cache-as-RAM but does so in the call that
+ requires the microcode!). To keep things simple, all x86 platforms handle
+ microcode the same way in U-Boot (even non-FSP platforms). This is that
+ a table is placed at _dt_ucode_base_size containing the base address and
+ size of the microcode. This is either passed to the FSP (for FSP
+ platforms), or used to set up the microcode (for non-FSP platforms).
+ This all happens in the build system since it is the only way to get
+ the microcode into a single blob and accessible without SRAM.
+
+ There are two cases to handle. If there is only one microcode blob in
+ the device tree, then the ucode pointer it set to point to that. This
+ entry (u-boot-ucode) is empty. If there is more than one update, then
+ this entry holds the concatenation of all updates, and the device tree
+ entry (u-boot-dtb-with-ucode) is updated to remove the microcode. This
+ last step ensures that that the microcode appears in one contiguous
+ block in the image and is not unnecessarily duplicated in the device
+ tree. It is referred to as 'collation' here.
+
+ Entry types that have a part to play in handling microcode:
+
+ Entry_u_boot_with_ucode_ptr:
+ Contains u-boot-nodtb.bin (i.e. U-Boot without the device tree).
+ It updates it with the address and size of the microcode so that
+ U-Boot can find it early on start-up.
+ Entry_u_boot_dtb_with_ucode:
+ Contains u-boot.dtb. It stores the microcode in a
+ 'self.ucode_data' property, which is then read by this class to
+ obtain the microcode if needed. If collation is performed, it
+ removes the microcode from the device tree.
+ Entry_u_boot_ucode:
+ This class. If collation is enabled it reads the microcode from
+ the Entry_u_boot_dtb_with_ucode entry, and uses it as the
+ contents of this entry.
+ """
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def ObtainContents(self):
+ # If the image does not need microcode, there is nothing to do
+ ucode_dest_entry = self.image.FindEntryType('u-boot-with-ucode-ptr')
+ if ucode_dest_entry and not ucode_dest_entry.target_pos:
+ self.data = ''
+ return True
+
+ # Get the microcode from the device tree entry
+ fdt_entry = self.image.FindEntryType('u-boot-dtb-with-ucode')
+ if not fdt_entry or not fdt_entry.ucode_data:
+ return False
+
+ if not fdt_entry.collate:
+ # This section can be empty
+ self.data = ''
+ return True
+
+ # Write it out to a file
+ dtb_name = 'u-boot-ucode.bin'
+ fname = tools.GetOutputFilename(dtb_name)
+ with open(fname, 'wb') as fd:
+ fd.write(fdt_entry.ucode_data)
+
+ self._pathname = fname
+ self.ReadContents()
+
+ return True
diff --git a/tools/binman/etype/u_boot_with_ucode_ptr.py b/tools/binman/etype/u_boot_with_ucode_ptr.py
new file mode 100644
index 0000000..6f01adb
--- /dev/null
+++ b/tools/binman/etype/u_boot_with_ucode_ptr.py
@@ -0,0 +1,87 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for a U-Boot binary with an embedded microcode pointer
+#
+
+import struct
+
+import command
+from entry import Entry
+from blob import Entry_blob
+import fdt_util
+import tools
+
+class Entry_u_boot_with_ucode_ptr(Entry_blob):
+ """U-Boot with embedded microcode pointer
+
+ See Entry_u_boot_ucode for full details of the 3 entries involved in this
+ process.
+ """
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+ self.elf_fname = 'u-boot'
+ self.target_pos = None
+
+ def GetDefaultFilename(self):
+ return 'u-boot-nodtb.bin'
+
+ def ObtainContents(self):
+ # Figure out where to put the microcode pointer
+ fname = tools.GetInputFilename(self.elf_fname)
+ args = [['nm', fname], ['grep', '-w', '_dt_ucode_base_size']]
+ out = (command.RunPipe(args, capture=True, raise_on_error=False).
+ stdout.splitlines())
+ if len(out) == 1:
+ self.target_pos = int(out[0].split()[0], 16)
+ elif not fdt_util.GetBool(self._node, 'optional-ucode'):
+ self.Raise('Cannot locate _dt_ucode_base_size symbol in u-boot')
+
+ return Entry_blob.ObtainContents(self)
+
+ def ProcessContents(self):
+ # If the image does not need microcode, there is nothing to do
+ if not self.target_pos:
+ return
+
+ # Get the position of the microcode
+ ucode_entry = self.image.FindEntryType('u-boot-ucode')
+ if not ucode_entry:
+ self.Raise('Cannot find microcode region u-boot-ucode')
+
+ # Check the target pos is in the image. If it is not, then U-Boot is
+ # being linked incorrectly, or is being placed at the wrong position
+ # in the image.
+ #
+ # The image must be set up so that U-Boot is placed at the
+ # flash address to which it is linked. For example, if
+ # CONFIG_SYS_TEXT_BASE is 0xfff00000, and the ROM is 8MB, then
+ # the U-Boot region must start at position 7MB in the image. In this
+ # case the ROM starts at 0xff800000, so the position of the first
+ # entry in the image corresponds to that.
+ if (self.target_pos < self.pos or
+ self.target_pos >= self.pos + self.size):
+ self.Raise('Microcode pointer _dt_ucode_base_size at %08x is '
+ 'outside the image ranging from %08x to %08x' %
+ (self.target_pos, self.pos, self.pos + self.size))
+
+ # Get the microcode, either from u-boot-ucode or u-boot-dtb-with-ucode.
+ # If we have left the microcode in the device tree, then it will be
+ # in the former. If we extracted the microcode from the device tree
+ # and collated it in one place, it will be in the latter.
+ if ucode_entry.size:
+ pos, size = ucode_entry.pos, ucode_entry.size
+ else:
+ dtb_entry = self.image.FindEntryType('u-boot-dtb-with-ucode')
+ if not dtb_entry:
+ self.Raise('Cannot find microcode region u-boot-dtb-with-ucode')
+ pos = dtb_entry.pos + dtb_entry.ucode_offset
+ size = dtb_entry.ucode_size
+
+ # Write the microcode position and size into the entry
+ pos_and_size = struct.pack('<2L', pos, size)
+ self.target_pos -= self.pos
+ self.data = (self.data[:self.target_pos] + pos_and_size +
+ self.data[self.target_pos + 8:])
diff --git a/tools/binman/etype/x86_start16.py b/tools/binman/etype/x86_start16.py
new file mode 100644
index 0000000..a44ea68
--- /dev/null
+++ b/tools/binman/etype/x86_start16.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for the 16-bit x86 start-up code for U-Boot
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_x86_start16(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'u-boot-x86-16bit.bin'
diff --git a/tools/binman/etype/x86_start16_spl.py b/tools/binman/etype/x86_start16_spl.py
new file mode 100644
index 0000000..3679a43
--- /dev/null
+++ b/tools/binman/etype/x86_start16_spl.py
@@ -0,0 +1,17 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for the 16-bit x86 start-up code for U-Boot SPL
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_x86_start16_spl(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'spl/u-boot-x86-16bit-spl.bin'
diff --git a/tools/binman/fdt_test.py b/tools/binman/fdt_test.py
new file mode 100644
index 0000000..1d9494e
--- /dev/null
+++ b/tools/binman/fdt_test.py
@@ -0,0 +1,48 @@
+#
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Test for the fdt modules
+
+import os
+import sys
+import tempfile
+import unittest
+
+from fdt_select import FdtScan
+import fdt_util
+import tools
+
+class TestFdt(unittest.TestCase):
+ @classmethod
+ def setUpClass(self):
+ self._binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
+ self._indir = tempfile.mkdtemp(prefix='binmant.')
+ tools.PrepareOutputDir(self._indir, True)
+
+ def TestFile(self, fname):
+ return os.path.join(self._binman_dir, 'test', fname)
+
+ def GetCompiled(self, fname):
+ return fdt_util.EnsureCompiled(self.TestFile(fname))
+
+ def _DeleteProp(self, fdt):
+ node = fdt.GetNode('/microcode/update@0')
+ node.DeleteProp('data')
+
+ def testFdtNormal(self):
+ fname = self.GetCompiled('34_x86_ucode.dts')
+ fdt = FdtScan(fname)
+ self._DeleteProp(fdt)
+
+ def testFdtFallback(self):
+ fname = self.GetCompiled('34_x86_ucode.dts')
+ fdt = FdtScan(fname, True)
+ fdt.GetProp('/microcode/update@0', 'data')
+ self.assertEqual('fred',
+ fdt.GetProp('/microcode/update@0', 'none', default='fred'))
+ self.assertEqual('12345678 12345679',
+ fdt.GetProp('/microcode/update@0', 'data', typespec='x'))
+ self._DeleteProp(fdt)
diff --git a/tools/binman/func_test.py b/tools/binman/func_test.py
new file mode 100644
index 0000000..740fa9e
--- /dev/null
+++ b/tools/binman/func_test.py
@@ -0,0 +1,822 @@
+#
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# To run a single test, change to this directory, and:
+#
+# python -m unittest func_test.TestFunctional.testHelp
+
+from optparse import OptionParser
+import os
+import shutil
+import struct
+import sys
+import tempfile
+import unittest
+
+import binman
+import cmdline
+import command
+import control
+import entry
+import fdt_select
+import fdt_util
+import tools
+import tout
+
+# Contents of test files, corresponding to different entry types
+U_BOOT_DATA = '1234'
+U_BOOT_IMG_DATA = 'img'
+U_BOOT_SPL_DATA = '567'
+BLOB_DATA = '89'
+ME_DATA = '0abcd'
+VGA_DATA = 'vga'
+U_BOOT_DTB_DATA = 'udtb'
+X86_START16_DATA = 'start16'
+U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here'
+FSP_DATA = 'fsp'
+CMC_DATA = 'cmc'
+
+class TestFunctional(unittest.TestCase):
+ """Functional tests for binman
+
+ Most of these use a sample .dts file to build an image and then check
+ that it looks correct. The sample files are in the test/ subdirectory
+ and are numbered.
+
+ For each entry type a very small test file is created using fixed
+ string contents. This makes it easy to test that things look right, and
+ debug problems.
+
+ In some cases a 'real' file must be used - these are also supplied in
+ the test/ diurectory.
+ """
+ @classmethod
+ def setUpClass(self):
+ # Handle the case where argv[0] is 'python'
+ self._binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
+ self._binman_pathname = os.path.join(self._binman_dir, 'binman')
+
+ # Create a temporary directory for input files
+ self._indir = tempfile.mkdtemp(prefix='binmant.')
+
+ # Create some test files
+ TestFunctional._MakeInputFile('u-boot.bin', U_BOOT_DATA)
+ TestFunctional._MakeInputFile('u-boot.img', U_BOOT_IMG_DATA)
+ TestFunctional._MakeInputFile('spl/u-boot-spl.bin', U_BOOT_SPL_DATA)
+ TestFunctional._MakeInputFile('blobfile', BLOB_DATA)
+ TestFunctional._MakeInputFile('me.bin', ME_DATA)
+ TestFunctional._MakeInputFile('vga.bin', VGA_DATA)
+ TestFunctional._MakeInputFile('u-boot.dtb', U_BOOT_DTB_DATA)
+ TestFunctional._MakeInputFile('u-boot-x86-16bit.bin', X86_START16_DATA)
+ TestFunctional._MakeInputFile('u-boot-nodtb.bin', U_BOOT_NODTB_DATA)
+ TestFunctional._MakeInputFile('fsp.bin', FSP_DATA)
+ TestFunctional._MakeInputFile('cmc.bin', CMC_DATA)
+ self._output_setup = False
+
+ # ELF file with a '_dt_ucode_base_size' symbol
+ with open(self.TestFile('u_boot_ucode_ptr')) as fd:
+ TestFunctional._MakeInputFile('u-boot', fd.read())
+
+ # Intel flash descriptor file
+ with open(self.TestFile('descriptor.bin')) as fd:
+ TestFunctional._MakeInputFile('descriptor.bin', fd.read())
+
+ @classmethod
+ def tearDownClass(self):
+ """Remove the temporary input directory and its contents"""
+ if self._indir:
+ shutil.rmtree(self._indir)
+ self._indir = None
+
+ def setUp(self):
+ # Enable this to turn on debugging output
+ # tout.Init(tout.DEBUG)
+ command.test_result = None
+
+ def tearDown(self):
+ """Remove the temporary output directory"""
+ tools._FinaliseForTest()
+
+ def _RunBinman(self, *args, **kwargs):
+ """Run binman using the command line
+
+ Args:
+ Arguments to pass, as a list of strings
+ kwargs: Arguments to pass to Command.RunPipe()
+ """
+ result = command.RunPipe([[self._binman_pathname] + list(args)],
+ capture=True, capture_stderr=True, raise_on_error=False)
+ if result.return_code and kwargs.get('raise_on_error', True):
+ raise Exception("Error running '%s': %s" % (' '.join(args),
+ result.stdout + result.stderr))
+ return result
+
+ def _DoBinman(self, *args):
+ """Run binman using directly (in the same process)
+
+ Args:
+ Arguments to pass, as a list of strings
+ Returns:
+ Return value (0 for success)
+ """
+ (options, args) = cmdline.ParseArgs(list(args))
+ options.pager = 'binman-invalid-pager'
+ options.build_dir = self._indir
+
+ # For testing, you can force an increase in verbosity here
+ # options.verbosity = tout.DEBUG
+ return control.Binman(options, args)
+
+ def _DoTestFile(self, fname):
+ """Run binman with a given test file
+
+ Args:
+ fname: Device tree source filename to use (e.g. 05_simple.dts)
+ """
+ return self._DoBinman('-p', '-I', self._indir,
+ '-d', self.TestFile(fname))
+
+ def _SetupDtb(self, fname, outfile='u-boot.dtb'):
+ """Set up a new test device-tree file
+
+ The given file is compiled and set up as the device tree to be used
+ for ths test.
+
+ Args:
+ fname: Filename of .dts file to read
+ outfile: Output filename for compiled device tree binary
+
+ Returns:
+ Contents of device tree binary
+ """
+ if not self._output_setup:
+ tools.PrepareOutputDir(self._indir, True)
+ self._output_setup = True
+ dtb = fdt_util.EnsureCompiled(self.TestFile(fname))
+ with open(dtb) as fd:
+ data = fd.read()
+ TestFunctional._MakeInputFile(outfile, data)
+ return data
+
+ def _DoReadFileDtb(self, fname, use_real_dtb=False):
+ """Run binman and return the resulting image
+
+ This runs binman with a given test file and then reads the resulting
+ output file. It is a shortcut function since most tests need to do
+ these steps.
+
+ Raises an assertion failure if binman returns a non-zero exit code.
+
+ Args:
+ fname: Device tree source filename to use (e.g. 05_simple.dts)
+ use_real_dtb: True to use the test file as the contents of
+ the u-boot-dtb entry. Normally this is not needed and the
+ test contents (the U_BOOT_DTB_DATA string) can be used.
+ But in some test we need the real contents.
+
+ Returns:
+ Tuple:
+ Resulting image contents
+ Device tree contents
+ """
+ dtb_data = None
+ # Use the compiled test file as the u-boot-dtb input
+ if use_real_dtb:
+ dtb_data = self._SetupDtb(fname)
+
+ try:
+ retcode = self._DoTestFile(fname)
+ self.assertEqual(0, retcode)
+
+ # Find the (only) image, read it and return its contents
+ image = control.images['image']
+ fname = tools.GetOutputFilename('image.bin')
+ self.assertTrue(os.path.exists(fname))
+ with open(fname) as fd:
+ return fd.read(), dtb_data
+ finally:
+ # Put the test file back
+ if use_real_dtb:
+ TestFunctional._MakeInputFile('u-boot.dtb', U_BOOT_DTB_DATA)
+
+ def _DoReadFile(self, fname, use_real_dtb=False):
+ """Helper function which discards the device-tree binary"""
+ return self._DoReadFileDtb(fname, use_real_dtb)[0]
+
+ @classmethod
+ def _MakeInputFile(self, fname, contents):
+ """Create a new test input file, creating directories as needed
+
+ Args:
+ fname: Filenaem to create
+ contents: File contents to write in to the file
+ Returns:
+ Full pathname of file created
+ """
+ pathname = os.path.join(self._indir, fname)
+ dirname = os.path.dirname(pathname)
+ if dirname and not os.path.exists(dirname):
+ os.makedirs(dirname)
+ with open(pathname, 'wb') as fd:
+ fd.write(contents)
+ return pathname
+
+ @classmethod
+ def TestFile(self, fname):
+ return os.path.join(self._binman_dir, 'test', fname)
+
+ def AssertInList(self, grep_list, target):
+ """Assert that at least one of a list of things is in a target
+
+ Args:
+ grep_list: List of strings to check
+ target: Target string
+ """
+ for grep in grep_list:
+ if grep in target:
+ return
+ self.fail("Error: '%' not found in '%s'" % (grep_list, target))
+
+ def CheckNoGaps(self, entries):
+ """Check that all entries fit together without gaps
+
+ Args:
+ entries: List of entries to check
+ """
+ pos = 0
+ for entry in entries.values():
+ self.assertEqual(pos, entry.pos)
+ pos += entry.size
+
+ def GetFdtLen(self, dtb):
+ """Get the totalsize field from a device tree binary
+
+ Args:
+ dtb: Device tree binary contents
+
+ Returns:
+ Total size of device tree binary, from the header
+ """
+ return struct.unpack('>L', dtb[4:8])[0]
+
+ def testRun(self):
+ """Test a basic run with valid args"""
+ result = self._RunBinman('-h')
+
+ def testFullHelp(self):
+ """Test that the full help is displayed with -H"""
+ result = self._RunBinman('-H')
+ help_file = os.path.join(self._binman_dir, 'README')
+ self.assertEqual(len(result.stdout), os.path.getsize(help_file))
+ self.assertEqual(0, len(result.stderr))
+ self.assertEqual(0, result.return_code)
+
+ def testFullHelpInternal(self):
+ """Test that the full help is displayed with -H"""
+ try:
+ command.test_result = command.CommandResult()
+ result = self._DoBinman('-H')
+ help_file = os.path.join(self._binman_dir, 'README')
+ finally:
+ command.test_result = None
+
+ def testHelp(self):
+ """Test that the basic help is displayed with -h"""
+ result = self._RunBinman('-h')
+ self.assertTrue(len(result.stdout) > 200)
+ self.assertEqual(0, len(result.stderr))
+ self.assertEqual(0, result.return_code)
+
+ # Not yet available.
+ def testBoard(self):
+ """Test that we can run it with a specific board"""
+ self._SetupDtb('05_simple.dts', 'sandbox/u-boot.dtb')
+ TestFunctional._MakeInputFile('sandbox/u-boot.bin', U_BOOT_DATA)
+ result = self._DoBinman('-b', 'sandbox')
+ self.assertEqual(0, result)
+
+ def testNeedBoard(self):
+ """Test that we get an error when no board ius supplied"""
+ with self.assertRaises(ValueError) as e:
+ result = self._DoBinman()
+ self.assertIn("Must provide a board to process (use -b <board>)",
+ str(e.exception))
+
+ def testMissingDt(self):
+ """Test that an invalid device tree file generates an error"""
+ with self.assertRaises(Exception) as e:
+ self._RunBinman('-d', 'missing_file')
+ # We get one error from libfdt, and a different one from fdtget.
+ self.AssertInList(["Couldn't open blob from 'missing_file'",
+ 'No such file or directory'], str(e.exception))
+
+ def testBrokenDt(self):
+ """Test that an invalid device tree source file generates an error
+
+ Since this is a source file it should be compiled and the error
+ will come from the device-tree compiler (dtc).
+ """
+ with self.assertRaises(Exception) as e:
+ self._RunBinman('-d', self.TestFile('01_invalid.dts'))
+ self.assertIn("FATAL ERROR: Unable to parse input tree",
+ str(e.exception))
+
+ def testMissingNode(self):
+ """Test that a device tree without a 'binman' node generates an error"""
+ with self.assertRaises(Exception) as e:
+ self._DoBinman('-d', self.TestFile('02_missing_node.dts'))
+ self.assertIn("does not have a 'binman' node", str(e.exception))
+
+ def testEmpty(self):
+ """Test that an empty binman node works OK (i.e. does nothing)"""
+ result = self._RunBinman('-d', self.TestFile('03_empty.dts'))
+ self.assertEqual(0, len(result.stderr))
+ self.assertEqual(0, result.return_code)
+
+ def testInvalidEntry(self):
+ """Test that an invalid entry is flagged"""
+ with self.assertRaises(Exception) as e:
+ result = self._RunBinman('-d',
+ self.TestFile('04_invalid_entry.dts'))
+ #print e.exception
+ self.assertIn("Unknown entry type 'not-a-valid-type' in node "
+ "'/binman/not-a-valid-type'", str(e.exception))
+
+ def testSimple(self):
+ """Test a simple binman with a single file"""
+ data = self._DoReadFile('05_simple.dts')
+ self.assertEqual(U_BOOT_DATA, data)
+
+ def testDual(self):
+ """Test that we can handle creating two images
+
+ This also tests image padding.
+ """
+ retcode = self._DoTestFile('06_dual_image.dts')
+ self.assertEqual(0, retcode)
+
+ image = control.images['image1']
+ self.assertEqual(len(U_BOOT_DATA), image._size)
+ fname = tools.GetOutputFilename('image1.bin')
+ self.assertTrue(os.path.exists(fname))
+ with open(fname) as fd:
+ data = fd.read()
+ self.assertEqual(U_BOOT_DATA, data)
+
+ image = control.images['image2']
+ self.assertEqual(3 + len(U_BOOT_DATA) + 5, image._size)
+ fname = tools.GetOutputFilename('image2.bin')
+ self.assertTrue(os.path.exists(fname))
+ with open(fname) as fd:
+ data = fd.read()
+ self.assertEqual(U_BOOT_DATA, data[3:7])
+ self.assertEqual(chr(0) * 3, data[:3])
+ self.assertEqual(chr(0) * 5, data[7:])
+
+ def testBadAlign(self):
+ """Test that an invalid alignment value is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('07_bad_align.dts')
+ self.assertIn("Node '/binman/u-boot': Alignment 23 must be a power "
+ "of two", str(e.exception))
+
+ def testPackSimple(self):
+ """Test that packing works as expected"""
+ retcode = self._DoTestFile('08_pack.dts')
+ self.assertEqual(0, retcode)
+ self.assertIn('image', control.images)
+ image = control.images['image']
+ entries = image._entries
+ self.assertEqual(5, len(entries))
+
+ # First u-boot
+ self.assertIn('u-boot', entries)
+ entry = entries['u-boot']
+ self.assertEqual(0, entry.pos)
+ self.assertEqual(len(U_BOOT_DATA), entry.size)
+
+ # Second u-boot, aligned to 16-byte boundary
+ self.assertIn('u-boot-align', entries)
+ entry = entries['u-boot-align']
+ self.assertEqual(16, entry.pos)
+ self.assertEqual(len(U_BOOT_DATA), entry.size)
+
+ # Third u-boot, size 23 bytes
+ self.assertIn('u-boot-size', entries)
+ entry = entries['u-boot-size']
+ self.assertEqual(20, entry.pos)
+ self.assertEqual(len(U_BOOT_DATA), entry.contents_size)
+ self.assertEqual(23, entry.size)
+
+ # Fourth u-boot, placed immediate after the above
+ self.assertIn('u-boot-next', entries)
+ entry = entries['u-boot-next']
+ self.assertEqual(43, entry.pos)
+ self.assertEqual(len(U_BOOT_DATA), entry.size)
+
+ # Fifth u-boot, placed at a fixed position
+ self.assertIn('u-boot-fixed', entries)
+ entry = entries['u-boot-fixed']
+ self.assertEqual(61, entry.pos)
+ self.assertEqual(len(U_BOOT_DATA), entry.size)
+
+ self.assertEqual(65, image._size)
+
+ def testPackExtra(self):
+ """Test that extra packing feature works as expected"""
+ retcode = self._DoTestFile('09_pack_extra.dts')
+
+ self.assertEqual(0, retcode)
+ self.assertIn('image', control.images)
+ image = control.images['image']
+ entries = image._entries
+ self.assertEqual(5, len(entries))
+
+ # First u-boot with padding before and after
+ self.assertIn('u-boot', entries)
+ entry = entries['u-boot']
+ self.assertEqual(0, entry.pos)
+ self.assertEqual(3, entry.pad_before)
+ self.assertEqual(3 + 5 + len(U_BOOT_DATA), entry.size)
+
+ # Second u-boot has an aligned size, but it has no effect
+ self.assertIn('u-boot-align-size-nop', entries)
+ entry = entries['u-boot-align-size-nop']
+ self.assertEqual(12, entry.pos)
+ self.assertEqual(4, entry.size)
+
+ # Third u-boot has an aligned size too
+ self.assertIn('u-boot-align-size', entries)
+ entry = entries['u-boot-align-size']
+ self.assertEqual(16, entry.pos)
+ self.assertEqual(32, entry.size)
+
+ # Fourth u-boot has an aligned end
+ self.assertIn('u-boot-align-end', entries)
+ entry = entries['u-boot-align-end']
+ self.assertEqual(48, entry.pos)
+ self.assertEqual(16, entry.size)
+
+ # Fifth u-boot immediately afterwards
+ self.assertIn('u-boot-align-both', entries)
+ entry = entries['u-boot-align-both']
+ self.assertEqual(64, entry.pos)
+ self.assertEqual(64, entry.size)
+
+ self.CheckNoGaps(entries)
+ self.assertEqual(128, image._size)
+
+ def testPackAlignPowerOf2(self):
+ """Test that invalid entry alignment is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('10_pack_align_power2.dts')
+ self.assertIn("Node '/binman/u-boot': Alignment 5 must be a power "
+ "of two", str(e.exception))
+
+ def testPackAlignSizePowerOf2(self):
+ """Test that invalid entry size alignment is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('11_pack_align_size_power2.dts')
+ self.assertIn("Node '/binman/u-boot': Alignment size 55 must be a "
+ "power of two", str(e.exception))
+
+ def testPackInvalidAlign(self):
+ """Test detection of an position that does not match its alignment"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('12_pack_inv_align.dts')
+ self.assertIn("Node '/binman/u-boot': Position 0x5 (5) does not match "
+ "align 0x4 (4)", str(e.exception))
+
+ def testPackInvalidSizeAlign(self):
+ """Test that invalid entry size alignment is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('13_pack_inv_size_align.dts')
+ self.assertIn("Node '/binman/u-boot': Size 0x5 (5) does not match "
+ "align-size 0x4 (4)", str(e.exception))
+
+ def testPackOverlap(self):
+ """Test that overlapping regions are detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('14_pack_overlap.dts')
+ self.assertIn("Node '/binman/u-boot-align': Position 0x3 (3) overlaps "
+ "with previous entry '/binman/u-boot' ending at 0x4 (4)",
+ str(e.exception))
+
+ def testPackEntryOverflow(self):
+ """Test that entries that overflow their size are detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('15_pack_overflow.dts')
+ self.assertIn("Node '/binman/u-boot': Entry contents size is 0x4 (4) "
+ "but entry size is 0x3 (3)", str(e.exception))
+
+ def testPackImageOverflow(self):
+ """Test that entries which overflow the image size are detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('16_pack_image_overflow.dts')
+ self.assertIn("Image '/binman': contents size 0x4 (4) exceeds image "
+ "size 0x3 (3)", str(e.exception))
+
+ def testPackImageSize(self):
+ """Test that the image size can be set"""
+ retcode = self._DoTestFile('17_pack_image_size.dts')
+ self.assertEqual(0, retcode)
+ self.assertIn('image', control.images)
+ image = control.images['image']
+ self.assertEqual(7, image._size)
+
+ def testPackImageSizeAlign(self):
+ """Test that image size alignemnt works as expected"""
+ retcode = self._DoTestFile('18_pack_image_align.dts')
+ self.assertEqual(0, retcode)
+ self.assertIn('image', control.images)
+ image = control.images['image']
+ self.assertEqual(16, image._size)
+
+ def testPackInvalidImageAlign(self):
+ """Test that invalid image alignment is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('19_pack_inv_image_align.dts')
+ self.assertIn("Image '/binman': Size 0x7 (7) does not match "
+ "align-size 0x8 (8)", str(e.exception))
+
+ def testPackAlignPowerOf2(self):
+ """Test that invalid image alignment is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('20_pack_inv_image_align_power2.dts')
+ self.assertIn("Image '/binman': Alignment size 131 must be a power of "
+ "two", str(e.exception))
+
+ def testImagePadByte(self):
+ """Test that the image pad byte can be specified"""
+ data = self._DoReadFile('21_image_pad.dts')
+ self.assertEqual(U_BOOT_SPL_DATA + (chr(0xff) * 9) + U_BOOT_DATA, data)
+
+ def testImageName(self):
+ """Test that image files can be named"""
+ retcode = self._DoTestFile('22_image_name.dts')
+ self.assertEqual(0, retcode)
+ image = control.images['image1']
+ fname = tools.GetOutputFilename('test-name')
+ self.assertTrue(os.path.exists(fname))
+
+ image = control.images['image2']
+ fname = tools.GetOutputFilename('test-name.xx')
+ self.assertTrue(os.path.exists(fname))
+
+ def testBlobFilename(self):
+ """Test that generic blobs can be provided by filename"""
+ data = self._DoReadFile('23_blob.dts')
+ self.assertEqual(BLOB_DATA, data)
+
+ def testPackSorted(self):
+ """Test that entries can be sorted"""
+ data = self._DoReadFile('24_sorted.dts')
+ self.assertEqual(chr(0) * 5 + U_BOOT_SPL_DATA + chr(0) * 2 +
+ U_BOOT_DATA, data)
+
+ def testPackZeroPosition(self):
+ """Test that an entry at position 0 is not given a new position"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('25_pack_zero_size.dts')
+ self.assertIn("Node '/binman/u-boot-spl': Position 0x0 (0) overlaps "
+ "with previous entry '/binman/u-boot' ending at 0x4 (4)",
+ str(e.exception))
+
+ def testPackUbootDtb(self):
+ """Test that a device tree can be added to U-Boot"""
+ data = self._DoReadFile('26_pack_u_boot_dtb.dts')
+ self.assertEqual(U_BOOT_NODTB_DATA + U_BOOT_DTB_DATA, data)
+
+ def testPackX86RomNoSize(self):
+ """Test that the end-at-4gb property requires a size property"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('27_pack_4gb_no_size.dts')
+ self.assertIn("Image '/binman': Image size must be provided when "
+ "using end-at-4gb", str(e.exception))
+
+ def testPackX86RomOutside(self):
+ """Test that the end-at-4gb property checks for position boundaries"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('28_pack_4gb_outside.dts')
+ self.assertIn("Node '/binman/u-boot': Position 0x0 (0) is outside "
+ "the image starting at 0xfffffff0 (4294967280)",
+ str(e.exception))
+
+ def testPackX86Rom(self):
+ """Test that a basic x86 ROM can be created"""
+ data = self._DoReadFile('29_x86-rom.dts')
+ self.assertEqual(U_BOOT_DATA + chr(0) * 3 + U_BOOT_SPL_DATA +
+ chr(0) * 6, data)
+
+ def testPackX86RomMeNoDesc(self):
+ """Test that an invalid Intel descriptor entry is detected"""
+ TestFunctional._MakeInputFile('descriptor.bin', '')
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('31_x86-rom-me.dts')
+ self.assertIn("Node '/binman/intel-descriptor': Cannot find FD "
+ "signature", str(e.exception))
+
+ def testPackX86RomBadDesc(self):
+ """Test that the Intel requires a descriptor entry"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('30_x86-rom-me-no-desc.dts')
+ self.assertIn("Node '/binman/intel-me': No position set with "
+ "pos-unset: should another entry provide this correct "
+ "position?", str(e.exception))
+
+ def testPackX86RomMe(self):
+ """Test that an x86 ROM with an ME region can be created"""
+ data = self._DoReadFile('31_x86-rom-me.dts')
+ self.assertEqual(ME_DATA, data[0x1000:0x1000 + len(ME_DATA)])
+
+ def testPackVga(self):
+ """Test that an image with a VGA binary can be created"""
+ data = self._DoReadFile('32_intel-vga.dts')
+ self.assertEqual(VGA_DATA, data[:len(VGA_DATA)])
+
+ def testPackStart16(self):
+ """Test that an image with an x86 start16 region can be created"""
+ data = self._DoReadFile('33_x86-start16.dts')
+ self.assertEqual(X86_START16_DATA, data[:len(X86_START16_DATA)])
+
+ def testPackUbootMicrocode(self):
+ """Test that x86 microcode can be handled correctly
+
+ We expect to see the following in the image, in order:
+ u-boot-nodtb.bin with a microcode pointer inserted at the correct
+ place
+ u-boot.dtb with the microcode removed
+ the microcode
+ """
+ data = self._DoReadFile('34_x86_ucode.dts', True)
+
+ # Now check the device tree has no microcode
+ second = data[len(U_BOOT_NODTB_DATA):]
+ fname = tools.GetOutputFilename('test.dtb')
+ with open(fname, 'wb') as fd:
+ fd.write(second)
+ fdt = fdt_select.FdtScan(fname)
+ ucode = fdt.GetNode('/microcode')
+ self.assertTrue(ucode)
+ for node in ucode.subnodes:
+ self.assertFalse(node.props.get('data'))
+
+ fdt_len = self.GetFdtLen(second)
+ third = second[fdt_len:]
+
+ # Check that the microcode appears immediately after the Fdt
+ # This matches the concatenation of the data properties in
+ # the /microcode/update@xxx nodes in x86_ucode.dts.
+ ucode_data = struct.pack('>4L', 0x12345678, 0x12345679, 0xabcd0000,
+ 0x78235609)
+ self.assertEqual(ucode_data, third[:len(ucode_data)])
+ ucode_pos = len(U_BOOT_NODTB_DATA) + fdt_len
+
+ # Check that the microcode pointer was inserted. It should match the
+ # expected position and size
+ pos_and_size = struct.pack('<2L', 0xfffffe00 + ucode_pos,
+ len(ucode_data))
+ first = data[:len(U_BOOT_NODTB_DATA)]
+ self.assertEqual('nodtb with microcode' + pos_and_size +
+ ' somewhere in here', first)
+
+ def _RunPackUbootSingleMicrocode(self, collate):
+ """Test that x86 microcode can be handled correctly
+
+ We expect to see the following in the image, in order:
+ u-boot-nodtb.bin with a microcode pointer inserted at the correct
+ place
+ u-boot.dtb with the microcode
+ an empty microcode region
+ """
+ # We need the libfdt library to run this test since only that allows
+ # finding the offset of a property. This is required by
+ # Entry_u_boot_dtb_with_ucode.ObtainContents().
+ if not fdt_select.have_libfdt:
+ return
+ data = self._DoReadFile('35_x86_single_ucode.dts', True)
+
+ second = data[len(U_BOOT_NODTB_DATA):]
+
+ fdt_len = self.GetFdtLen(second)
+ third = second[fdt_len:]
+ second = second[:fdt_len]
+
+ if not collate:
+ ucode_data = struct.pack('>2L', 0x12345678, 0x12345679)
+ self.assertIn(ucode_data, second)
+ ucode_pos = second.find(ucode_data) + len(U_BOOT_NODTB_DATA)
+
+ # Check that the microcode pointer was inserted. It should match the
+ # expected position and size
+ pos_and_size = struct.pack('<2L', 0xfffffe00 + ucode_pos,
+ len(ucode_data))
+ first = data[:len(U_BOOT_NODTB_DATA)]
+ self.assertEqual('nodtb with microcode' + pos_and_size +
+ ' somewhere in here', first)
+
+ def testPackUbootSingleMicrocode(self):
+ """Test that x86 microcode can be handled correctly with fdt_normal.
+ """
+ self._RunPackUbootSingleMicrocode(False)
+
+ def testPackUbootSingleMicrocodeFallback(self):
+ """Test that x86 microcode can be handled correctly with fdt_fallback.
+
+ This only supports collating the microcode.
+ """
+ try:
+ old_val = fdt_select.UseFallback(True)
+ self._RunPackUbootSingleMicrocode(True)
+ finally:
+ fdt_select.UseFallback(old_val)
+
+ def testUBootImg(self):
+ """Test that u-boot.img can be put in a file"""
+ data = self._DoReadFile('36_u_boot_img.dts')
+ self.assertEqual(U_BOOT_IMG_DATA, data)
+
+ def testNoMicrocode(self):
+ """Test that a missing microcode region is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('37_x86_no_ucode.dts', True)
+ self.assertIn("Node '/binman/u-boot-dtb-with-ucode': No /microcode "
+ "node found in ", str(e.exception))
+
+ def testMicrocodeWithoutNode(self):
+ """Test that a missing u-boot-dtb-with-ucode node is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('38_x86_ucode_missing_node.dts', True)
+ self.assertIn("Node '/binman/u-boot-with-ucode-ptr': Cannot find "
+ "microcode region u-boot-dtb-with-ucode", str(e.exception))
+
+ def testMicrocodeWithoutNode2(self):
+ """Test that a missing u-boot-ucode node is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('39_x86_ucode_missing_node2.dts', True)
+ self.assertIn("Node '/binman/u-boot-with-ucode-ptr': Cannot find "
+ "microcode region u-boot-ucode", str(e.exception))
+
+ def testMicrocodeWithoutPtrInElf(self):
+ """Test that a U-Boot binary without the microcode symbol is detected"""
+ # ELF file without a '_dt_ucode_base_size' symbol
+ if not fdt_select.have_libfdt:
+ return
+ try:
+ with open(self.TestFile('u_boot_no_ucode_ptr')) as fd:
+ TestFunctional._MakeInputFile('u-boot', fd.read())
+
+ with self.assertRaises(ValueError) as e:
+ self._RunPackUbootSingleMicrocode(False)
+ self.assertIn("Node '/binman/u-boot-with-ucode-ptr': Cannot locate "
+ "_dt_ucode_base_size symbol in u-boot", str(e.exception))
+
+ finally:
+ # Put the original file back
+ with open(self.TestFile('u_boot_ucode_ptr')) as fd:
+ TestFunctional._MakeInputFile('u-boot', fd.read())
+
+ def testMicrocodeNotInImage(self):
+ """Test that microcode must be placed within the image"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('40_x86_ucode_not_in_image.dts', True)
+ self.assertIn("Node '/binman/u-boot-with-ucode-ptr': Microcode "
+ "pointer _dt_ucode_base_size at fffffe14 is outside the "
+ "image ranging from 00000000 to 0000002e", str(e.exception))
+
+ def testWithoutMicrocode(self):
+ """Test that we can cope with an image without microcode (e.g. qemu)"""
+ with open(self.TestFile('u_boot_no_ucode_ptr')) as fd:
+ TestFunctional._MakeInputFile('u-boot', fd.read())
+ data, dtb = self._DoReadFileDtb('44_x86_optional_ucode.dts', True)
+
+ # Now check the device tree has no microcode
+ self.assertEqual(U_BOOT_NODTB_DATA, data[:len(U_BOOT_NODTB_DATA)])
+ second = data[len(U_BOOT_NODTB_DATA):]
+
+ fdt_len = self.GetFdtLen(second)
+ self.assertEqual(dtb, second[:fdt_len])
+
+ used_len = len(U_BOOT_NODTB_DATA) + fdt_len
+ third = data[used_len:]
+ self.assertEqual(chr(0) * (0x200 - used_len), third)
+
+ def testUnknownPosSize(self):
+ """Test that microcode must be placed within the image"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('41_unknown_pos_size.dts', True)
+ self.assertIn("Image '/binman': Unable to set pos/size for unknown "
+ "entry 'invalid-entry'", str(e.exception))
+
+ def testPackFsp(self):
+ """Test that an image with a FSP binary can be created"""
+ data = self._DoReadFile('42_intel-fsp.dts')
+ self.assertEqual(FSP_DATA, data[:len(FSP_DATA)])
+
+ def testPackCmc(self):
+ """Test that an image with a FSP binary can be created"""
+ data = self._DoReadFile('43_intel-cmc.dts')
+ self.assertEqual(CMC_DATA, data[:len(CMC_DATA)])
diff --git a/tools/binman/image.py b/tools/binman/image.py
new file mode 100644
index 0000000..07fc930
--- /dev/null
+++ b/tools/binman/image.py
@@ -0,0 +1,229 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Class for an image, the output of binman
+#
+
+from collections import OrderedDict
+from operator import attrgetter
+
+import entry
+from entry import Entry
+import fdt_util
+import tools
+
+class Image:
+ """A Image, representing an output from binman
+
+ An image is comprised of a collection of entries each containing binary
+ data. The image size must be large enough to hold all of this data.
+
+ This class implements the various operations needed for images.
+
+ Atrtributes:
+ _node: Node object that contains the image definition in device tree
+ _name: Image name
+ _size: Image size in bytes, or None if not known yet
+ _align_size: Image size alignment, or None
+ _pad_before: Number of bytes before the first entry starts. This
+ effectively changes the place where entry position 0 starts
+ _pad_after: Number of bytes after the last entry ends. The last
+ entry will finish on or before this boundary
+ _pad_byte: Byte to use to pad the image where there is no entry
+ _filename: Output filename for image
+ _sort: True if entries should be sorted by position, False if they
+ must be in-order in the device tree description
+ _skip_at_start: Number of bytes before the first entry starts. These
+ effecively adjust the starting position of entries. For example,
+ if _pad_before is 16, then the first entry would start at 16.
+ An entry with pos = 20 would in fact be written at position 4
+ in the image file.
+ _end_4gb: Indicates that the image ends at the 4GB boundary. This is
+ used for x86 images, which want to use positions such that a
+ memory address (like 0xff800000) is the first entry position.
+ This causes _skip_at_start to be set to the starting memory
+ address.
+ _entries: OrderedDict() of entries
+ """
+ def __init__(self, name, node):
+ self._node = node
+ self._name = name
+ self._size = None
+ self._align_size = None
+ self._pad_before = 0
+ self._pad_after = 0
+ self._pad_byte = 0
+ self._filename = '%s.bin' % self._name
+ self._sort = False
+ self._skip_at_start = 0
+ self._end_4gb = False
+ self._entries = OrderedDict()
+
+ self._ReadNode()
+ self._ReadEntries()
+
+ def _ReadNode(self):
+ """Read properties from the image node"""
+ self._size = fdt_util.GetInt(self._node, 'size')
+ self._align_size = fdt_util.GetInt(self._node, 'align-size')
+ if tools.NotPowerOfTwo(self._align_size):
+ self._Raise("Alignment size %s must be a power of two" %
+ self._align_size)
+ self._pad_before = fdt_util.GetInt(self._node, 'pad-before', 0)
+ self._pad_after = fdt_util.GetInt(self._node, 'pad-after', 0)
+ self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0)
+ filename = fdt_util.GetString(self._node, 'filename')
+ if filename:
+ self._filename = filename
+ self._sort = fdt_util.GetBool(self._node, 'sort-by-pos')
+ self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb')
+ if self._end_4gb and not self._size:
+ self._Raise("Image size must be provided when using end-at-4gb")
+ if self._end_4gb:
+ self._skip_at_start = 0x100000000 - self._size
+
+ def CheckSize(self):
+ """Check that the image contents does not exceed its size, etc."""
+ contents_size = 0
+ for entry in self._entries.values():
+ contents_size = max(contents_size, entry.pos + entry.size)
+
+ contents_size -= self._skip_at_start
+
+ size = self._size
+ if not size:
+ size = self._pad_before + contents_size + self._pad_after
+ size = tools.Align(size, self._align_size)
+
+ if self._size and contents_size > self._size:
+ self._Raise("contents size %#x (%d) exceeds image size %#x (%d)" %
+ (contents_size, contents_size, self._size, self._size))
+ if not self._size:
+ self._size = size
+ if self._size != tools.Align(self._size, self._align_size):
+ self._Raise("Size %#x (%d) does not match align-size %#x (%d)" %
+ (self._size, self._size, self._align_size, self._align_size))
+
+ def _Raise(self, msg):
+ """Raises an error for this image
+
+ Args:
+ msg: Error message to use in the raise string
+ Raises:
+ ValueError()
+ """
+ raise ValueError("Image '%s': %s" % (self._node.path, msg))
+
+ def _ReadEntries(self):
+ for node in self._node.subnodes:
+ self._entries[node.name] = Entry.Create(self, node)
+
+ def FindEntryType(self, etype):
+ """Find an entry type in the image
+
+ Args:
+ etype: Entry type to find
+ Returns:
+ entry matching that type, or None if not found
+ """
+ for entry in self._entries.values():
+ if entry.etype == etype:
+ return entry
+ return None
+
+ def GetEntryContents(self):
+ """Call ObtainContents() for each entry
+
+ This calls each entry's ObtainContents() a few times until they all
+ return True. We stop calling an entry's function once it returns
+ True. This allows the contents of one entry to depend on another.
+
+ After 3 rounds we give up since it's likely an error.
+ """
+ todo = self._entries.values()
+ for passnum in range(3):
+ next_todo = []
+ for entry in todo:
+ if not entry.ObtainContents():
+ next_todo.append(entry)
+ todo = next_todo
+ if not todo:
+ break
+
+ def _SetEntryPosSize(self, name, pos, size):
+ """Set the position and size of an entry
+
+ Args:
+ name: Entry name to update
+ pos: New position
+ size: New size
+ """
+ entry = self._entries.get(name)
+ if not entry:
+ self._Raise("Unable to set pos/size for unknown entry '%s'" % name)
+ entry.SetPositionSize(self._skip_at_start + pos, size)
+
+ def GetEntryPositions(self):
+ """Handle entries that want to set the position/size of other entries
+
+ This calls each entry's GetPositions() method. If it returns a list
+ of entries to update, it updates them.
+ """
+ for entry in self._entries.values():
+ pos_dict = entry.GetPositions()
+ for name, info in pos_dict.iteritems():
+ self._SetEntryPosSize(name, *info)
+
+ def PackEntries(self):
+ """Pack all entries into the image"""
+ pos = self._skip_at_start
+ for entry in self._entries.values():
+ pos = entry.Pack(pos)
+
+ def _SortEntries(self):
+ """Sort entries by position"""
+ entries = sorted(self._entries.values(), key=lambda entry: entry.pos)
+ self._entries.clear()
+ for entry in entries:
+ self._entries[entry._node.name] = entry
+
+ def CheckEntries(self):
+ """Check that entries do not overlap or extend outside the image"""
+ if self._sort:
+ self._SortEntries()
+ pos = 0
+ prev_name = 'None'
+ for entry in self._entries.values():
+ if (entry.pos < self._skip_at_start or
+ entry.pos >= self._skip_at_start + self._size):
+ entry.Raise("Position %#x (%d) is outside the image starting "
+ "at %#x (%d)" %
+ (entry.pos, entry.pos, self._skip_at_start,
+ self._skip_at_start))
+ if entry.pos < pos:
+ entry.Raise("Position %#x (%d) overlaps with previous entry '%s' "
+ "ending at %#x (%d)" %
+ (entry.pos, entry.pos, prev_name, pos, pos))
+ pos = entry.pos + entry.size
+ prev_name = entry.GetPath()
+
+ def ProcessEntryContents(self):
+ """Call the ProcessContents() method for each entry
+
+ This is intended to adjust the contents as needed by the entry type.
+ """
+ for entry in self._entries.values():
+ entry.ProcessContents()
+
+ def BuildImage(self):
+ """Write the image to a file"""
+ fname = tools.GetOutputFilename(self._filename)
+ with open(fname, 'wb') as fd:
+ fd.write(chr(self._pad_byte) * self._size)
+
+ for entry in self._entries.values():
+ data = entry.GetData()
+ fd.seek(self._pad_before + entry.pos - self._skip_at_start)
+ fd.write(data)
diff --git a/tools/binman/test/01_invalid.dts b/tools/binman/test/01_invalid.dts
new file mode 100644
index 0000000..7d00455
--- /dev/null
+++ b/tools/binman/test/01_invalid.dts
@@ -0,0 +1,5 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
diff --git a/tools/binman/test/02_missing_node.dts b/tools/binman/test/02_missing_node.dts
new file mode 100644
index 0000000..3a51ec2
--- /dev/null
+++ b/tools/binman/test/02_missing_node.dts
@@ -0,0 +1,6 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+};
diff --git a/tools/binman/test/03_empty.dts b/tools/binman/test/03_empty.dts
new file mode 100644
index 0000000..493c9a0
--- /dev/null
+++ b/tools/binman/test/03_empty.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ };
+};
diff --git a/tools/binman/test/04_invalid_entry.dts b/tools/binman/test/04_invalid_entry.dts
new file mode 100644
index 0000000..b043455
--- /dev/null
+++ b/tools/binman/test/04_invalid_entry.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ not-a-valid-type {
+ };
+ };
+};
diff --git a/tools/binman/test/05_simple.dts b/tools/binman/test/05_simple.dts
new file mode 100644
index 0000000..3771aa2
--- /dev/null
+++ b/tools/binman/test/05_simple.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ };
+};
diff --git a/tools/binman/test/06_dual_image.dts b/tools/binman/test/06_dual_image.dts
new file mode 100644
index 0000000..78be16f
--- /dev/null
+++ b/tools/binman/test/06_dual_image.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ multiple-images;
+ image1 {
+ u-boot {
+ };
+ };
+
+ image2 {
+ pad-before = <3>;
+ pad-after = <5>;
+
+ u-boot {
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/07_bad_align.dts b/tools/binman/test/07_bad_align.dts
new file mode 100644
index 0000000..123bb13
--- /dev/null
+++ b/tools/binman/test/07_bad_align.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ align = <23>;
+ };
+ };
+};
diff --git a/tools/binman/test/08_pack.dts b/tools/binman/test/08_pack.dts
new file mode 100644
index 0000000..dc63d99
--- /dev/null
+++ b/tools/binman/test/08_pack.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+
+ u-boot-align {
+ type = "u-boot";
+ align = <16>;
+ };
+
+ u-boot-size {
+ type = "u-boot";
+ size = <23>;
+ };
+
+ u-boot-next {
+ type = "u-boot";
+ };
+
+ u-boot-fixed {
+ type = "u-boot";
+ pos = <61>;
+ };
+ };
+};
diff --git a/tools/binman/test/09_pack_extra.dts b/tools/binman/test/09_pack_extra.dts
new file mode 100644
index 0000000..0765707
--- /dev/null
+++ b/tools/binman/test/09_pack_extra.dts
@@ -0,0 +1,35 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ pad-before = <3>;
+ pad-after = <5>;
+ };
+
+ u-boot-align-size-nop {
+ type = "u-boot";
+ align-size = <4>;
+ };
+
+ u-boot-align-size {
+ type = "u-boot";
+ align = <16>;
+ align-size = <32>;
+ };
+
+ u-boot-align-end {
+ type = "u-boot";
+ align-end = <64>;
+ };
+
+ u-boot-align-both {
+ type = "u-boot";
+ align= <64>;
+ align-end = <128>;
+ };
+ };
+};
diff --git a/tools/binman/test/10_pack_align_power2.dts b/tools/binman/test/10_pack_align_power2.dts
new file mode 100644
index 0000000..8f6253a
--- /dev/null
+++ b/tools/binman/test/10_pack_align_power2.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ align = <5>;
+ };
+ };
+};
diff --git a/tools/binman/test/11_pack_align_size_power2.dts b/tools/binman/test/11_pack_align_size_power2.dts
new file mode 100644
index 0000000..04f7672
--- /dev/null
+++ b/tools/binman/test/11_pack_align_size_power2.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ align-size = <55>;
+ };
+ };
+};
diff --git a/tools/binman/test/12_pack_inv_align.dts b/tools/binman/test/12_pack_inv_align.dts
new file mode 100644
index 0000000..1d9d80a
--- /dev/null
+++ b/tools/binman/test/12_pack_inv_align.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ pos = <5>;
+ align = <4>;
+ };
+ };
+};
diff --git a/tools/binman/test/13_pack_inv_size_align.dts b/tools/binman/test/13_pack_inv_size_align.dts
new file mode 100644
index 0000000..dfafa13
--- /dev/null
+++ b/tools/binman/test/13_pack_inv_size_align.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ size = <5>;
+ align-size = <4>;
+ };
+ };
+};
diff --git a/tools/binman/test/14_pack_overlap.dts b/tools/binman/test/14_pack_overlap.dts
new file mode 100644
index 0000000..611cfd9
--- /dev/null
+++ b/tools/binman/test/14_pack_overlap.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+
+ u-boot-align {
+ type = "u-boot";
+ pos = <3>;
+ };
+ };
+};
diff --git a/tools/binman/test/15_pack_overflow.dts b/tools/binman/test/15_pack_overflow.dts
new file mode 100644
index 0000000..6f65433
--- /dev/null
+++ b/tools/binman/test/15_pack_overflow.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ size = <3>;
+ };
+ };
+};
diff --git a/tools/binman/test/16_pack_image_overflow.dts b/tools/binman/test/16_pack_image_overflow.dts
new file mode 100644
index 0000000..6ae66f3
--- /dev/null
+++ b/tools/binman/test/16_pack_image_overflow.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <3>;
+
+ u-boot {
+ };
+ };
+};
diff --git a/tools/binman/test/17_pack_image_size.dts b/tools/binman/test/17_pack_image_size.dts
new file mode 100644
index 0000000..2360eb5
--- /dev/null
+++ b/tools/binman/test/17_pack_image_size.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <7>;
+
+ u-boot {
+ };
+ };
+};
diff --git a/tools/binman/test/18_pack_image_align.dts b/tools/binman/test/18_pack_image_align.dts
new file mode 100644
index 0000000..16cd2a4
--- /dev/null
+++ b/tools/binman/test/18_pack_image_align.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ align-size = <16>;
+
+ u-boot {
+ };
+ };
+};
diff --git a/tools/binman/test/19_pack_inv_image_align.dts b/tools/binman/test/19_pack_inv_image_align.dts
new file mode 100644
index 0000000..e5ee87b
--- /dev/null
+++ b/tools/binman/test/19_pack_inv_image_align.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <7>;
+ align-size = <8>;
+
+ u-boot {
+ };
+ };
+};
diff --git a/tools/binman/test/20_pack_inv_image_align_power2.dts b/tools/binman/test/20_pack_inv_image_align_power2.dts
new file mode 100644
index 0000000..a428c4b
--- /dev/null
+++ b/tools/binman/test/20_pack_inv_image_align_power2.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ align-size = <131>;
+
+ u-boot {
+ };
+ };
+};
diff --git a/tools/binman/test/21_image_pad.dts b/tools/binman/test/21_image_pad.dts
new file mode 100644
index 0000000..daf8385f
--- /dev/null
+++ b/tools/binman/test/21_image_pad.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+
+ u-boot {
+ pos = <12>;
+ };
+ };
+};
diff --git a/tools/binman/test/22_image_name.dts b/tools/binman/test/22_image_name.dts
new file mode 100644
index 0000000..94fc069
--- /dev/null
+++ b/tools/binman/test/22_image_name.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ multiple-images;
+ image1 {
+ filename = "test-name";
+ u-boot {
+ };
+ };
+
+ image2 {
+ filename = "test-name.xx";
+ u-boot {
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/23_blob.dts b/tools/binman/test/23_blob.dts
new file mode 100644
index 0000000..7dcff69
--- /dev/null
+++ b/tools/binman/test/23_blob.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ blob {
+ filename = "blobfile";
+ };
+ };
+};
diff --git a/tools/binman/test/24_sorted.dts b/tools/binman/test/24_sorted.dts
new file mode 100644
index 0000000..9f4151c
--- /dev/null
+++ b/tools/binman/test/24_sorted.dts
@@ -0,0 +1,17 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ u-boot {
+ pos = <10>;
+ };
+
+ u-boot-spl {
+ pos = <5>;
+ };
+ };
+};
diff --git a/tools/binman/test/25_pack_zero_size.dts b/tools/binman/test/25_pack_zero_size.dts
new file mode 100644
index 0000000..7d2baad
--- /dev/null
+++ b/tools/binman/test/25_pack_zero_size.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+
+ u-boot-spl {
+ pos = <0>;
+ };
+ };
+};
diff --git a/tools/binman/test/26_pack_u_boot_dtb.dts b/tools/binman/test/26_pack_u_boot_dtb.dts
new file mode 100644
index 0000000..2707a73
--- /dev/null
+++ b/tools/binman/test/26_pack_u_boot_dtb.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot-nodtb {
+ };
+
+ u-boot-dtb {
+ };
+ };
+};
diff --git a/tools/binman/test/27_pack_4gb_no_size.dts b/tools/binman/test/27_pack_4gb_no_size.dts
new file mode 100644
index 0000000..e0b6519
--- /dev/null
+++ b/tools/binman/test/27_pack_4gb_no_size.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ u-boot {
+ pos = <0xfffffff0>;
+ };
+
+ u-boot-spl {
+ pos = <0xfffffff7>;
+ };
+ };
+};
diff --git a/tools/binman/test/28_pack_4gb_outside.dts b/tools/binman/test/28_pack_4gb_outside.dts
new file mode 100644
index 0000000..ff468c7
--- /dev/null
+++ b/tools/binman/test/28_pack_4gb_outside.dts
@@ -0,0 +1,19 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <16>;
+ u-boot {
+ pos = <0>;
+ };
+
+ u-boot-spl {
+ pos = <0xfffffff7>;
+ };
+ };
+};
diff --git a/tools/binman/test/29_x86-rom.dts b/tools/binman/test/29_x86-rom.dts
new file mode 100644
index 0000000..075ede3
--- /dev/null
+++ b/tools/binman/test/29_x86-rom.dts
@@ -0,0 +1,19 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <16>;
+ u-boot {
+ pos = <0xfffffff0>;
+ };
+
+ u-boot-spl {
+ pos = <0xfffffff7>;
+ };
+ };
+};
diff --git a/tools/binman/test/30_x86-rom-me-no-desc.dts b/tools/binman/test/30_x86-rom-me-no-desc.dts
new file mode 100644
index 0000000..4578f66
--- /dev/null
+++ b/tools/binman/test/30_x86-rom-me-no-desc.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <16>;
+ intel-me {
+ pos-unset;
+ };
+ };
+};
diff --git a/tools/binman/test/31_x86-rom-me.dts b/tools/binman/test/31_x86-rom-me.dts
new file mode 100644
index 0000000..b484ab3
--- /dev/null
+++ b/tools/binman/test/31_x86-rom-me.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <0x800000>;
+ intel-descriptor {
+ };
+
+ intel-me {
+ pos-unset;
+ };
+ };
+};
diff --git a/tools/binman/test/32_intel-vga.dts b/tools/binman/test/32_intel-vga.dts
new file mode 100644
index 0000000..1790833
--- /dev/null
+++ b/tools/binman/test/32_intel-vga.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ intel-vga {
+ };
+ };
+};
diff --git a/tools/binman/test/33_x86-start16.dts b/tools/binman/test/33_x86-start16.dts
new file mode 100644
index 0000000..2e279de
--- /dev/null
+++ b/tools/binman/test/33_x86-start16.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ x86-start16 {
+ };
+ };
+};
diff --git a/tools/binman/test/34_x86_ucode.dts b/tools/binman/test/34_x86_ucode.dts
new file mode 100644
index 0000000..64a6c2c
--- /dev/null
+++ b/tools/binman/test/34_x86_ucode.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <0x200>;
+ u-boot-with-ucode-ptr {
+ };
+
+ u-boot-dtb-with-ucode {
+ };
+
+ u-boot-ucode {
+ };
+ };
+
+ microcode {
+ update@0 {
+ data = <0x12345678 0x12345679>;
+ };
+ update@1 {
+ data = <0xabcd0000 0x78235609>;
+ };
+ };
+};
diff --git a/tools/binman/test/35_x86_single_ucode.dts b/tools/binman/test/35_x86_single_ucode.dts
new file mode 100644
index 0000000..973e97f
--- /dev/null
+++ b/tools/binman/test/35_x86_single_ucode.dts
@@ -0,0 +1,26 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <0x200>;
+ u-boot-with-ucode-ptr {
+ };
+
+ u-boot-dtb-with-ucode {
+ };
+
+ u-boot-ucode {
+ };
+ };
+
+ microcode {
+ update@0 {
+ data = <0x12345678 0x12345679>;
+ };
+ };
+};
diff --git a/tools/binman/test/36_u_boot_img.dts b/tools/binman/test/36_u_boot_img.dts
new file mode 100644
index 0000000..aa5a3fe
--- /dev/null
+++ b/tools/binman/test/36_u_boot_img.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot-img {
+ };
+ };
+};
diff --git a/tools/binman/test/37_x86_no_ucode.dts b/tools/binman/test/37_x86_no_ucode.dts
new file mode 100644
index 0000000..9e12156
--- /dev/null
+++ b/tools/binman/test/37_x86_no_ucode.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <0x200>;
+ u-boot-with-ucode-ptr {
+ };
+
+ u-boot-dtb-with-ucode {
+ };
+
+ u-boot-ucode {
+ };
+ };
+};
diff --git a/tools/binman/test/38_x86_ucode_missing_node.dts b/tools/binman/test/38_x86_ucode_missing_node.dts
new file mode 100644
index 0000000..d6cf0d8
--- /dev/null
+++ b/tools/binman/test/38_x86_ucode_missing_node.dts
@@ -0,0 +1,26 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <0x200>;
+ u-boot-with-ucode-ptr {
+ };
+
+ u-boot-ucode {
+ };
+ };
+
+ microcode {
+ update@0 {
+ data = <0x12345678 0x12345679>;
+ };
+ update@1 {
+ data = <0xabcd0000 0x78235609>;
+ };
+ };
+};
diff --git a/tools/binman/test/39_x86_ucode_missing_node2.dts b/tools/binman/test/39_x86_ucode_missing_node2.dts
new file mode 100644
index 0000000..b7e26c5
--- /dev/null
+++ b/tools/binman/test/39_x86_ucode_missing_node2.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <0x200>;
+ u-boot-with-ucode-ptr {
+ };
+ };
+
+ microcode {
+ update@0 {
+ data = <0x12345678 0x12345679>;
+ };
+ update@1 {
+ data = <0xabcd0000 0x78235609>;
+ };
+ };
+};
diff --git a/tools/binman/test/40_x86_ucode_not_in_image.dts b/tools/binman/test/40_x86_ucode_not_in_image.dts
new file mode 100644
index 0000000..67d17d3
--- /dev/null
+++ b/tools/binman/test/40_x86_ucode_not_in_image.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ size = <0x200>;
+ u-boot-with-ucode-ptr {
+ };
+
+ u-boot-dtb-with-ucode {
+ };
+
+ u-boot-ucode {
+ };
+ };
+
+ microcode {
+ update@0 {
+ data = <0x12345678 0x12345679>;
+ };
+ update@1 {
+ data = <0xabcd0000 0x78235609>;
+ };
+ };
+};
diff --git a/tools/binman/test/41_unknown_pos_size.dts b/tools/binman/test/41_unknown_pos_size.dts
new file mode 100644
index 0000000..a8e7d8a
--- /dev/null
+++ b/tools/binman/test/41_unknown_pos_size.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ _testing {
+ };
+ };
+};
diff --git a/tools/binman/test/42_intel-fsp.dts b/tools/binman/test/42_intel-fsp.dts
new file mode 100644
index 0000000..e0a1e76
--- /dev/null
+++ b/tools/binman/test/42_intel-fsp.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ intel-fsp {
+ };
+ };
+};
diff --git a/tools/binman/test/43_intel-cmc.dts b/tools/binman/test/43_intel-cmc.dts
new file mode 100644
index 0000000..26c456d
--- /dev/null
+++ b/tools/binman/test/43_intel-cmc.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ intel-cmc {
+ };
+ };
+};
diff --git a/tools/binman/test/44_x86_optional_ucode.dts b/tools/binman/test/44_x86_optional_ucode.dts
new file mode 100644
index 0000000..abe1322
--- /dev/null
+++ b/tools/binman/test/44_x86_optional_ucode.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-pos;
+ end-at-4gb;
+ size = <0x200>;
+ u-boot-with-ucode-ptr {
+ optional-ucode;
+ };
+
+ u-boot-dtb-with-ucode {
+ };
+
+ u-boot-ucode {
+ };
+ };
+
+ microcode {
+ update@0 {
+ data = <0x12345678 0x12345679>;
+ };
+ update@1 {
+ data = <0xabcd0000 0x78235609>;
+ };
+ };
+};
diff --git a/tools/binman/test/descriptor.bin b/tools/binman/test/descriptor.bin
new file mode 100644
index 0000000..3d54943
--- /dev/null
+++ b/tools/binman/test/descriptor.bin
Binary files differ
diff --git a/tools/binman/test/u_boot_no_ucode_ptr b/tools/binman/test/u_boot_no_ucode_ptr
new file mode 100755
index 0000000..f72462f
--- /dev/null
+++ b/tools/binman/test/u_boot_no_ucode_ptr
Binary files differ
diff --git a/tools/binman/test/u_boot_no_ucode_ptr.c b/tools/binman/test/u_boot_no_ucode_ptr.c
new file mode 100644
index 0000000..a17bb4c
--- /dev/null
+++ b/tools/binman/test/u_boot_no_ucode_ptr.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Simple program to create a bad _dt_ucode_base_size symbol to create an
+ * error when it is used. This is used by binman tests.
+ *
+ * Build with:
+ * cc -march=i386 -m32 -o u_boot_no_ucode_ptr -T u_boot_ucode_ptr.lds \
+ -nostdlib u_boot_no_ucode_ptr.c
+ */
+
+static unsigned long not__dt_ucode_base_size[2]
+ __attribute__((section(".ucode"))) = {1, 2};
diff --git a/tools/binman/test/u_boot_ucode_ptr b/tools/binman/test/u_boot_ucode_ptr
new file mode 100755
index 0000000..dbfb184
--- /dev/null
+++ b/tools/binman/test/u_boot_ucode_ptr
Binary files differ
diff --git a/tools/binman/test/u_boot_ucode_ptr.c b/tools/binman/test/u_boot_ucode_ptr.c
new file mode 100644
index 0000000..434c9f4
--- /dev/null
+++ b/tools/binman/test/u_boot_ucode_ptr.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Simple program to create a _dt_ucode_base_size symbol which can be read
+ * by 'nm'. This is used by binman tests.
+ *
+ * Build with:
+ * cc -march=i386 -m32 -o u_boot_ucode_ptr -T u_boot_ucode_ptr.lds -nostdlib \
+ u_boot_ucode_ptr.c
+ */
+
+static unsigned long _dt_ucode_base_size[2]
+ __attribute__((section(".ucode"))) = {1, 2};
diff --git a/tools/binman/test/u_boot_ucode_ptr.lds b/tools/binman/test/u_boot_ucode_ptr.lds
new file mode 100644
index 0000000..167debf
--- /dev/null
+++ b/tools/binman/test/u_boot_ucode_ptr.lds
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0xfffffdf0;
+ _start = .;
+ .ucode : {
+ *(.ucode)
+ }
+}
diff --git a/tools/buildman/README b/tools/buildman/README
index 8c5f861..62ab7b7 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -211,6 +211,15 @@
and buildman will find arm-none-eabi-gcc in /usr/bin if you have it installed.
+[toolchain-wrapper]
+wrapper: ccache
+
+This tells buildman to use a compiler wrapper in front of CROSS_COMPILE. In
+this example, ccache. It doesn't affect the toolchain scan. The wrapper is
+added when CROSS_COMPILE environtal variable is set. The name in this
+section is ignored. If more than one line is provided, only the last one
+is taken.
+
3. Make sure you have the require Python pre-requisites
Buildman uses multiprocessing, Queue, shutil, StringIO, ConfigParser and
@@ -959,6 +968,55 @@
SOURCE_DATE_EPOCH=0 ./tools/buildman/buildman -I -P tegra
+Checking configuration
+======================
+
+A common requirement when converting CONFIG options to Kconfig is to check
+that the effective configuration has not changed due to the conversion.
+Buildman supports this with the -K option, used after a build. This shows
+differences in effective configuration between one commit and the next.
+
+For example:
+
+ $ buildman -b kc4 -sK
+ ...
+ 43: Convert CONFIG_SPL_USBETH_SUPPORT to Kconfig
+ arm:
+ + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1
+ + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ am335x_evm_usbspl :
+ + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1
+ + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ 44: Convert CONFIG_SPL_USB_HOST_SUPPORT to Kconfig
+ ...
+
+This shows that commit 44 enabled three new options for the board
+am335x_evm_usbspl which were not enabled in commit 43. There is also a
+summary for 'arm' showing all the changes detected for that architecture.
+In this case there is only one board with changes, so 'arm' output is the
+same as 'am335x_evm_usbspl'/
+
+The -K option uses the u-boot.cfg, spl/u-boot-spl.cfg and tpl/u-boot-tpl.cfg
+files which are produced by a build. If all you want is to check the
+configuration you can in fact avoid doing a full build, using -D. This tells
+buildman to configuration U-Boot and create the .cfg files, but not actually
+build the source. This is 5-10 times faster than doing a full build.
+
+By default buildman considers the follow two configuration methods
+equivalent:
+
+ #define CONFIG_SOME_OPTION
+
+ CONFIG_SOME_OPTION=y
+
+The former would appear in a header filer and the latter in a defconfig
+file. The achieve this, buildman considers 'y' to be '1' in configuration
+variables. This avoids lots of useless output when converting a CONFIG
+option to Kconfig. To disable this behaviour, use --squash-config-y.
+
+
Other options
=============
diff --git a/tools/buildman/board.py b/tools/buildman/board.py
index 5d536d5..ae0e0b8 100644
--- a/tools/buildman/board.py
+++ b/tools/buildman/board.py
@@ -92,9 +92,9 @@
self.board_name = board_name
self.vendor = vendor
self.soc = soc
- self.props = [self.target, self.arch, self.cpu, self.board_name,
- self.vendor, self.soc]
self.options = options
+ self.props = [self.target, self.arch, self.cpu, self.board_name,
+ self.vendor, self.soc, self.options]
self.build_it = False
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 8ec3551..236e061 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -12,8 +12,10 @@
import re
import Queue
import shutil
+import signal
import string
import sys
+import threading
import time
import builderthread
@@ -96,19 +98,22 @@
# Translate a commit subject into a valid filename
trans_valid_chars = string.maketrans("/: ", "---")
-CONFIG_FILENAMES = [
+BASE_CONFIG_FILENAMES = [
+ 'u-boot.cfg', 'u-boot-spl.cfg', 'u-boot-tpl.cfg'
+]
+
+EXTRA_CONFIG_FILENAMES = [
'.config', '.config-spl', '.config-tpl',
'autoconf.mk', 'autoconf-spl.mk', 'autoconf-tpl.mk',
'autoconf.h', 'autoconf-spl.h','autoconf-tpl.h',
- 'u-boot.cfg', 'u-boot-spl.cfg', 'u-boot-tpl.cfg'
]
class Config:
"""Holds information about configuration settings for a board."""
- def __init__(self, target):
+ def __init__(self, config_filename, target):
self.target = target
self.config = {}
- for fname in CONFIG_FILENAMES:
+ for fname in config_filename:
self.config[fname] = {}
def Add(self, fname, key, value):
@@ -126,7 +131,6 @@
"""Class for building U-Boot for a particular commit.
Public members: (many should ->private)
- active: True if the builder is active and has not been stopped
already_done: Number of builds already completed
base_dir: Base directory to use for builder
checkout: True to check out source, False to skip that step.
@@ -206,7 +210,8 @@
def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs,
gnu_make='make', checkout=True, show_unknown=True, step=1,
no_subdirs=False, full_path=False, verbose_build=False,
- incremental=False, per_board_out_dir=False):
+ incremental=False, per_board_out_dir=False,
+ config_only=False, squash_config_y=False):
"""Create a new Builder object
Args:
@@ -229,12 +234,13 @@
mrproper when configuring
per_board_out_dir: Build in a separate persistent directory per
board rather than a thread-specific directory
+ config_only: Only configure each build, don't build it
+ squash_config_y: Convert CONFIG options with the value 'y' to '1'
"""
self.toolchains = toolchains
self.base_dir = base_dir
self._working_dir = os.path.join(base_dir, '.bm-work')
self.threads = []
- self.active = True
self.do_make = self.Make
self.gnu_make = gnu_make
self.checkout = checkout
@@ -257,6 +263,11 @@
self.no_subdirs = no_subdirs
self.full_path = full_path
self.verbose_build = verbose_build
+ self.config_only = config_only
+ self.squash_config_y = squash_config_y
+ self.config_filenames = BASE_CONFIG_FILENAMES
+ if not self.squash_config_y:
+ self.config_filenames += EXTRA_CONFIG_FILENAMES
self.col = terminal.Color()
@@ -283,11 +294,17 @@
ignore_lines = ['(make.*Waiting for unfinished)', '(Segmentation fault)']
self.re_make_err = re.compile('|'.join(ignore_lines))
+ # Handle existing graceful with SIGINT / Ctrl-C
+ signal.signal(signal.SIGINT, self.signal_handler)
+
def __del__(self):
"""Get rid of all threads created by the builder"""
for t in self.threads:
del t
+ def signal_handler(self, signal, frame):
+ sys.exit(1)
+
def SetDisplayOptions(self, show_errors=False, show_sizes=False,
show_detail=False, show_bloat=False,
list_error_boards=False, show_config=False):
@@ -389,11 +406,6 @@
if result:
target = result.brd.target
- if result.return_code < 0:
- self.active = False
- command.StopAll()
- return
-
self.upto += 1
if result.return_code != 0:
self.fail += 1
@@ -431,7 +443,7 @@
name += target
Print(line + name, newline=False)
- length = 14 + len(name)
+ length = 16 + len(name)
self.ClearLine(length)
def _GetOutputDir(self, commit_upto):
@@ -582,13 +594,15 @@
key, value = values
else:
key = values[0]
- value = ''
+ value = '1' if self.squash_config_y else ''
if not key.startswith('CONFIG_'):
continue
elif not line or line[0] in ['#', '*', '/']:
continue
else:
key, value = line.split('=', 1)
+ if self.squash_config_y and value == 'y':
+ value = '1'
config[key] = value
return config
@@ -655,7 +669,7 @@
if read_config:
output_dir = self.GetBuildDir(commit_upto, target)
- for name in CONFIG_FILENAMES:
+ for name in self.config_filenames:
fname = os.path.join(output_dir, name)
config[name] = self._ProcessConfig(fname)
@@ -732,8 +746,8 @@
line, board)
last_was_warning = is_warning
last_func = None
- tconfig = Config(board.target)
- for fname in CONFIG_FILENAMES:
+ tconfig = Config(self.config_filenames, board.target)
+ for fname in self.config_filenames:
if outcome.config:
for key, value in outcome.config[fname].iteritems():
tconfig.Add(fname, key, value)
@@ -1189,7 +1203,7 @@
arch_config_plus[arch] = {}
arch_config_minus[arch] = {}
arch_config_change[arch] = {}
- for name in CONFIG_FILENAMES:
+ for name in self.config_filenames:
arch_config_plus[arch][name] = {}
arch_config_minus[arch][name] = {}
arch_config_change[arch][name] = {}
@@ -1206,7 +1220,7 @@
tbase = self._base_config[target]
tconfig = config[target]
lines = []
- for name in CONFIG_FILENAMES:
+ for name in self.config_filenames:
if not tconfig.config[name]:
continue
config_plus = {}
@@ -1250,7 +1264,7 @@
all_plus = {}
all_minus = {}
all_change = {}
- for name in CONFIG_FILENAMES:
+ for name in self.config_filenames:
all_plus.update(arch_config_plus[arch][name])
all_minus.update(arch_config_minus[arch][name])
all_change.update(arch_config_change[arch][name])
@@ -1366,8 +1380,10 @@
if os.path.exists(git_dir):
gitutil.Fetch(git_dir, thread_dir)
else:
- Print('Cloning repo for thread %d' % thread_num)
+ Print('\rCloning repo for thread %d' % thread_num,
+ newline=False)
gitutil.Clone(src_dir, thread_dir)
+ Print('\r%s\r' % (' ' * 30), newline=False)
def _PrepareWorkingSpace(self, max_threads, setup_git):
"""Prepare the working directory for use.
@@ -1395,8 +1411,14 @@
for commit_upto in range(self.commit_count):
dir_list.append(self._GetOutputDir(commit_upto))
+ to_remove = []
for dirname in glob.glob(os.path.join(self.base_dir, '*')):
if dirname not in dir_list:
+ to_remove.append(dirname)
+ if to_remove:
+ Print('Removing %d old build directories' % len(to_remove),
+ newline=False)
+ for dirname in to_remove:
shutil.rmtree(dirname)
def BuildBoards(self, commits, board_selected, keep_outputs, verbose):
@@ -1422,6 +1444,7 @@
self._PrepareWorkingSpace(min(self.num_threads, len(board_selected)),
commits is not None)
self._PrepareOutputSpace()
+ Print('\rStarting build...', newline=False)
self.SetupBuild(board_selected, commits)
self.ProcessResult(None)
@@ -1434,8 +1457,11 @@
job.step = self._step
self.queue.put(job)
- # Wait until all jobs are started
- self.queue.join()
+ term = threading.Thread(target=self.queue.join)
+ term.setDaemon(True)
+ term.start()
+ while term.isAlive():
+ term.join(100)
# Wait until we have processed all output
self.out_queue.join()
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index c512d3b..f2b2acd 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -110,8 +110,8 @@
return self.builder.do_make(commit, brd, stage, cwd, *args,
**kwargs)
- def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build,
- force_build_failures):
+ def RunCommit(self, commit_upto, brd, work_dir, do_config, config_only,
+ force_build, force_build_failures):
"""Build a particular commit.
If the build is already done, and we are not forcing a build, we skip
@@ -122,6 +122,7 @@
brd: Board object to build
work_dir: Directory to which the source will be checked out
do_config: True to run a make <board>_defconfig on the source
+ config_only: Only configure the source, do not build it
force_build: Force a build even if one was previously done
force_build_failures: Force a bulid if the previous result showed
failure
@@ -231,6 +232,8 @@
config_out += result.combined
do_config = False # No need to configure next time
if result.return_code == 0:
+ if config_only:
+ args.append('cfg')
result = self.Make(commit, brd, 'build', cwd, *args,
env=env)
result.stderr = result.stderr.replace(src_dir + '/', '')
@@ -304,10 +307,6 @@
print >>fd, 'arch', result.toolchain.arch
fd.write('%s' % result.return_code)
- with open(os.path.join(build_dir, 'toolchain'), 'w') as fd:
- print >>fd, 'gcc', result.toolchain.gcc
- print >>fd, 'path', result.toolchain.path
-
# Write out the image and function size information and an objdump
env = result.toolchain.MakeEnvironment(self.builder.full_path)
lines = []
@@ -405,7 +404,7 @@
force_build = False
for commit_upto in range(0, len(job.commits), job.step):
result, request_config = self.RunCommit(commit_upto, brd,
- work_dir, do_config,
+ work_dir, do_config, self.builder.config_only,
force_build or self.builder.force_build,
self.builder.force_build_failures)
failed = result.return_code or result.stderr
@@ -415,7 +414,7 @@
# with a reconfig.
if self.builder.force_config_on_failure:
result, request_config = self.RunCommit(commit_upto,
- brd, work_dir, True, True, False)
+ brd, work_dir, True, False, True, False)
did_config = True
if not self.builder.force_reconfig:
do_config = request_config
@@ -459,7 +458,8 @@
else:
# Just build the currently checked-out build
result, request_config = self.RunCommit(None, brd, work_dir, True,
- True, self.builder.force_build_failures)
+ self.builder.config_only, True,
+ self.builder.force_build_failures)
result.commit_upto = 0
self._WriteResult(result, job.keep_outputs)
self.builder.out_queue.put(result)
@@ -470,17 +470,7 @@
This thread picks a job from the queue, runs it, and then goes to the
next job.
"""
- alive = True
while True:
job = self.builder.queue.get()
- if self.builder.active and alive:
- self.RunJob(job)
- '''
- try:
- if self.builder.active and alive:
- self.RunJob(job)
- except Exception as err:
- alive = False
- print err
- '''
+ self.RunJob(job)
self.builder.queue.task_done()
diff --git a/tools/buildman/buildman.py b/tools/buildman/buildman.py
index d0afeda..607429d 100755
--- a/tools/buildman/buildman.py
+++ b/tools/buildman/buildman.py
@@ -15,7 +15,7 @@
# Bring in the patman libraries
our_path = os.path.dirname(os.path.realpath(__file__))
-sys.path.append(os.path.join(our_path, '../patman'))
+sys.path.insert(1, os.path.join(our_path, '../patman'))
# Our modules
import board
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 3e3bd63..0060e03 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -28,6 +28,8 @@
parser.add_option('-d', '--detail', dest='show_detail',
action='store_true', default=False,
help='Show detailed information for each board in summary')
+ parser.add_option('-D', '--config-only', action='store_true', default=False,
+ help="Don't build, just configure each commit")
parser.add_option('-e', '--show_errors', action='store_true',
default=False, help='Show errors and warnings')
parser.add_option('-f', '--force-build', dest='force_build',
@@ -57,6 +59,8 @@
default=False, help='Keep all build output files (e.g. binaries)')
parser.add_option('-K', '--show-config', action='store_true',
default=False, help='Show configuration changes in summary (both board config files and Kconfig)')
+ parser.add_option('--preserve-config-y', action='store_true',
+ default=False, help="Don't convert y to 1 in configs")
parser.add_option('-l', '--list-error-boards', action='store_true',
default=False, help='Show a list of boards next to each error/warning')
parser.add_option('--list-tool-chains', action='store_true', default=False,
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index b86d7b3..545c2cb 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -237,7 +237,7 @@
options.step = len(series.commits) - 1
gnu_make = command.Output(os.path.join(options.git,
- 'scripts/show-gnu-make')).rstrip()
+ 'scripts/show-gnu-make'), raise_on_error=False).rstrip()
if not gnu_make:
sys.exit('GNU Make not found')
@@ -258,7 +258,9 @@
no_subdirs=options.no_subdirs, full_path=options.full_path,
verbose_build=options.verbose_build,
incremental=options.incremental,
- per_board_out_dir=options.per_board_out_dir,)
+ per_board_out_dir=options.per_board_out_dir,
+ config_only=options.config_only,
+ squash_config_y=not options.preserve_config_y)
builder.force_config_on_failure = not options.quick
if make_func:
builder.do_make = make_func
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index d8f3c81..ed2a3a8 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -198,9 +198,9 @@
if line.text.strip():
count += 1
- # We should get one starting message, then an update for every commit
+ # We should get two starting messages, then an update for every commit
# built.
- self.assertEqual(count, len(commits) * len(boards) + 1)
+ self.assertEqual(count, len(commits) * len(boards) + 2)
build.SetDisplayOptions(show_errors=True);
build.ShowSummary(self.commits, board_selected)
#terminal.EchoPrintTestLines()
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 41e4e4c..4778876 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -127,6 +127,18 @@
return PRIORITY_CALC + prio
return PRIORITY_CALC + prio
+ def GetWrapper(self, show_warning=True):
+ """Get toolchain wrapper from the setting file.
+ """
+ value = ''
+ for name, value in bsettings.GetItems('toolchain-wrapper'):
+ if not value:
+ print "Warning: Wrapper not found"
+ if value:
+ value = value + ' '
+
+ return value
+
def MakeEnvironment(self, full_path):
"""Returns an environment for using the toolchain.
@@ -138,10 +150,12 @@
PATH
"""
env = dict(os.environ)
+ wrapper = self.GetWrapper()
+
if full_path:
- env['CROSS_COMPILE'] = os.path.join(self.path, self.cross)
+ env['CROSS_COMPILE'] = wrapper + os.path.join(self.path, self.cross)
else:
- env['CROSS_COMPILE'] = self.cross
+ env['CROSS_COMPILE'] = wrapper + self.cross
env['PATH'] = self.path + ':' + env['PATH']
return env
diff --git a/tools/default_image.c b/tools/default_image.c
index 6e4ae14..4e5568e 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -25,7 +25,7 @@
static int image_check_image_types(uint8_t type)
{
if (((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT)) ||
- (type == IH_TYPE_KERNEL_NOLOAD))
+ (type == IH_TYPE_KERNEL_NOLOAD) || (type == IH_TYPE_FIRMWARE_IVT))
return EXIT_SUCCESS;
else
return EXIT_FAILURE;
@@ -89,6 +89,7 @@
{
uint32_t checksum;
time_t time;
+ uint32_t imagesize;
image_header_t * hdr = (image_header_t *)ptr;
@@ -98,11 +99,16 @@
sbuf->st_size - sizeof(image_header_t));
time = imagetool_get_source_date(params, sbuf->st_mtime);
+ if (params->type == IH_TYPE_FIRMWARE_IVT)
+ /* Add size of CSF minus IVT */
+ imagesize = sbuf->st_size - sizeof(image_header_t) + 0x1FE0;
+ else
+ imagesize = sbuf->st_size - sizeof(image_header_t);
/* Build new header */
image_set_magic(hdr, IH_MAGIC);
image_set_time(hdr, time);
- image_set_size(hdr, sbuf->st_size - sizeof(image_header_t));
+ image_set_size(hdr, imagesize);
image_set_load(hdr, params->addr);
image_set_ep(hdr, params->ep);
image_set_dcrc(hdr, checksum);
diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py
index ec80abe..11050b6 100755
--- a/tools/dtoc/dtoc.py
+++ b/tools/dtoc/dtoc.py
@@ -9,27 +9,16 @@
import copy
from optparse import OptionError, OptionParser
import os
+import struct
import sys
-import fdt_util
-
# Bring in the patman libraries
our_path = os.path.dirname(os.path.realpath(__file__))
sys.path.append(os.path.join(our_path, '../patman'))
-# Bring in either the normal fdt library (which relies on libfdt) or the
-# fallback one (which uses fdtget and is slower). Both provide the same
-# interfface for this file to use.
-try:
- from fdt import Fdt
- import fdt
- have_libfdt = True
-except ImportError:
- have_libfdt = False
- from fdt_fallback import Fdt
- import fdt_fallback as fdt
-
-import struct
+import fdt
+import fdt_select
+import fdt_util
# When we see these properties we ignore them - i.e. do not create a structure member
PROP_IGNORE_LIST = [
@@ -45,10 +34,10 @@
# C type declarations for the tyues we support
TYPE_NAMES = {
- fdt_util.TYPE_INT: 'fdt32_t',
- fdt_util.TYPE_BYTE: 'unsigned char',
- fdt_util.TYPE_STRING: 'const char *',
- fdt_util.TYPE_BOOL: 'bool',
+ fdt.TYPE_INT: 'fdt32_t',
+ fdt.TYPE_BYTE: 'unsigned char',
+ fdt.TYPE_STRING: 'const char *',
+ fdt.TYPE_BOOL: 'bool',
};
STRUCT_PREFIX = 'dtd_'
@@ -71,7 +60,7 @@
def TabTo(num_tabs, str):
if len(str) >= num_tabs * 8:
return str + ' '
- return str + '\t' * (num_tabs - len(str) / 8)
+ return str + '\t' * (num_tabs - len(str) // 8)
class DtbPlatdata:
"""Provide a means to convert device tree binary data to platform data
@@ -150,13 +139,13 @@
type: Data type (fdt_util)
value: Data value, as a string of bytes
"""
- if type == fdt_util.TYPE_INT:
+ if type == fdt.TYPE_INT:
return '%#x' % fdt_util.fdt32_to_cpu(value)
- elif type == fdt_util.TYPE_BYTE:
+ elif type == fdt.TYPE_BYTE:
return '%#x' % ord(value[0])
- elif type == fdt_util.TYPE_STRING:
+ elif type == fdt.TYPE_STRING:
return '"%s"' % value
- elif type == fdt_util.TYPE_BOOL:
+ elif type == fdt.TYPE_BOOL:
return 'true'
def GetCompatName(self, node):
@@ -178,8 +167,7 @@
Once this is done, self.fdt.GetRoot() can be called to obtain the
device tree root node, and progress from there.
"""
- self.fdt = Fdt(self._dtb_fname)
- self.fdt.Scan()
+ self.fdt = fdt_select.FdtScan(self._dtb_fname)
def ScanTree(self):
"""Scan the device tree for useful information
@@ -236,14 +224,14 @@
fields = {}
# Get a list of all the valid properties in this node.
- for name, prop in node.props.iteritems():
+ for name, prop in node.props.items():
if name not in PROP_IGNORE_LIST and name[0] != '#':
fields[name] = copy.deepcopy(prop)
# If we've seen this node_name before, update the existing struct.
if node_name in structs:
struct = structs[node_name]
- for name, prop in fields.iteritems():
+ for name, prop in fields.items():
oldprop = struct.get(name)
if oldprop:
oldprop.Widen(prop)
@@ -258,7 +246,7 @@
for node in self._valid_nodes:
node_name = self.GetCompatName(node)
struct = structs[node_name]
- for name, prop in node.props.iteritems():
+ for name, prop in node.props.items():
if name not in PROP_IGNORE_LIST and name[0] != '#':
prop.Widen(struct[name])
upto += 1
@@ -310,7 +298,7 @@
var_name = Conv_name_to_c(node.name)
self.Buf('static struct %s%s %s%s = {\n' %
(STRUCT_PREFIX, struct_name, VAL_PREFIX, var_name))
- for pname, prop in node.props.iteritems():
+ for pname, prop in node.props.items():
if pname in PROP_IGNORE_LIST or pname[0] == '#':
continue
ptype = TYPE_NAMES[prop.type]
diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py
index 1d913a9..816fdbe 100644
--- a/tools/dtoc/fdt.py
+++ b/tools/dtoc/fdt.py
@@ -6,17 +6,26 @@
# SPDX-License-Identifier: GPL-2.0+
#
-import fdt_util
-import libfdt
+import struct
import sys
-# This deals with a device tree, presenting it as a list of Node and Prop
-# objects, representing nodes and properties, respectively.
-#
-# This implementation uses a libfdt Python library to access the device tree,
-# so it is fairly efficient.
+import fdt_util
-class Prop:
+# This deals with a device tree, presenting it as an assortment of Node and
+# Prop objects, representing nodes and properties, respectively. This file
+# contains the base classes and defines the high-level API. Most of the
+# implementation is in the FdtFallback and FdtNormal subclasses. See
+# fdt_select.py for how to create an Fdt object.
+
+# A list of types we support
+(TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL) = range(4)
+
+def CheckErr(errnum, msg):
+ if errnum:
+ raise ValueError('Error %d: %s: %s' %
+ (errnum, libfdt.fdt_strerror(errnum), msg))
+
+class PropBase:
"""A device tree property
Properties:
@@ -25,14 +34,11 @@
bytes
type: Value type
"""
- def __init__(self, name, bytes):
+ def __init__(self, node, offset, name):
+ self._node = node
+ self._offset = offset
self.name = name
self.value = None
- if not bytes:
- self.type = fdt_util.TYPE_BOOL
- self.value = True
- return
- self.type, self.value = fdt_util.BytesToValue(bytes)
def GetPhandle(self):
"""Get a (single) phandle value from a property
@@ -71,12 +77,85 @@
self.value = [self.value]
if type(self.value) == list and len(newprop.value) > len(self.value):
- val = fdt_util.GetEmpty(self.type)
+ val = self.GetEmpty(self.type)
while len(self.value) < len(newprop.value):
self.value.append(val)
+ def BytesToValue(self, bytes):
+ """Converts a string of bytes into a type and value
-class Node:
+ Args:
+ A string containing bytes
+
+ Return:
+ A tuple:
+ Type of data
+ Data, either a single element or a list of elements. Each element
+ is one of:
+ TYPE_STRING: string value from the property
+ TYPE_INT: a byte-swapped integer stored as a 4-byte string
+ TYPE_BYTE: a byte stored as a single-byte string
+ """
+ size = len(bytes)
+ strings = bytes.split('\0')
+ is_string = True
+ count = len(strings) - 1
+ if count > 0 and not strings[-1]:
+ for string in strings[:-1]:
+ if not string:
+ is_string = False
+ break
+ for ch in string:
+ if ch < ' ' or ch > '~':
+ is_string = False
+ break
+ else:
+ is_string = False
+ if is_string:
+ if count == 1:
+ return TYPE_STRING, strings[0]
+ else:
+ return TYPE_STRING, strings[:-1]
+ if size % 4:
+ if size == 1:
+ return TYPE_BYTE, bytes[0]
+ else:
+ return TYPE_BYTE, list(bytes)
+ val = []
+ for i in range(0, size, 4):
+ val.append(bytes[i:i + 4])
+ if size == 4:
+ return TYPE_INT, val[0]
+ else:
+ return TYPE_INT, val
+
+ def GetEmpty(self, type):
+ """Get an empty / zero value of the given type
+
+ Returns:
+ A single value of the given type
+ """
+ if type == TYPE_BYTE:
+ return chr(0)
+ elif type == TYPE_INT:
+ return struct.pack('<I', 0);
+ elif type == TYPE_STRING:
+ return ''
+ else:
+ return True
+
+ def GetOffset(self):
+ """Get the offset of a property
+
+ This can be implemented by subclasses.
+
+ Returns:
+ The offset of the property (struct fdt_property) within the
+ file, or None if not known.
+ """
+ return None
+
+class NodeBase:
"""A device tree node
Properties:
@@ -89,32 +168,42 @@
Keyed by property name
"""
def __init__(self, fdt, offset, name, path):
- self.offset = offset
+ self._fdt = fdt
+ self._offset = offset
self.name = name
self.path = path
- self._fdt = fdt
self.subnodes = []
self.props = {}
- def Scan(self):
- """Scan a node's properties and subnodes
+ def _FindNode(self, name):
+ """Find a node given its name
- This fills in the props and subnodes properties, recursively
- searching into subnodes so that the entire tree is built.
+ Args:
+ name: Node name to look for
+ Returns:
+ Node object if found, else None
"""
- self.props = self._fdt.GetProps(self.path)
+ for subnode in self.subnodes:
+ if subnode.name == name:
+ return subnode
+ return None
- offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self.offset)
- while offset >= 0:
- sep = '' if self.path[-1] == '/' else '/'
- name = libfdt.Name(self._fdt.GetFdt(), offset)
- path = self.path + sep + name
- node = Node(self._fdt, offset, name, path)
- self.subnodes.append(node)
+ def Scan(self):
+ """Scan the subnodes of a node
- node.Scan()
- offset = libfdt.fdt_next_subnode(self._fdt.GetFdt(), offset)
+ This should be implemented by subclasses
+ """
+ raise NotImplementedError()
+ def DeleteProp(self, prop_name):
+ """Delete a property of a node
+
+ This should be implemented by subclasses
+
+ Args:
+ prop_name: Name of the property to delete
+ """
+ raise NotImplementedError()
class Fdt:
"""Provides simple access to a flat device tree blob.
@@ -123,26 +212,20 @@
fname: Filename of fdt
_root: Root of device tree (a Node object)
"""
-
def __init__(self, fname):
- self.fname = fname
- with open(fname) as fd:
- self._fdt = fd.read()
+ self._fname = fname
- def GetFdt(self):
- """Get the contents of the FDT
-
- Returns:
- The FDT contents as a string of bytes
- """
- return self._fdt
-
- def Scan(self):
+ def Scan(self, root='/'):
"""Scan a device tree, building up a tree of Node objects
This fills in the self._root property
+
+ Args:
+ root: Ignored
+
+ TODO(sjg@chromium.org): Implement the 'root' parameter
"""
- self._root = Node(self, 0, '/', '/')
+ self._root = self.Node(self, 0, '/', '/')
self._root.Scan()
def GetRoot(self):
@@ -153,28 +236,34 @@
"""
return self._root
- def GetProps(self, node):
- """Get all properties from a node.
+ def GetNode(self, path):
+ """Look up a node from its path
Args:
- node: Full path to node name to look in.
-
+ path: Path to look up, e.g. '/microcode/update@0'
Returns:
- A dictionary containing all the properties, indexed by node name.
- The entries are Prop objects.
-
- Raises:
- ValueError: if the node does not exist.
+ Node object, or None if not found
"""
- offset = libfdt.fdt_path_offset(self._fdt, node)
- if offset < 0:
- libfdt.Raise(offset)
- props_dict = {}
- poffset = libfdt.fdt_first_property_offset(self._fdt, offset)
- while poffset >= 0:
- dprop, plen = libfdt.fdt_get_property_by_offset(self._fdt, poffset)
- prop = Prop(libfdt.String(self._fdt, dprop.nameoff), libfdt.Data(dprop))
- props_dict[prop.name] = prop
+ node = self._root
+ for part in path.split('/')[1:]:
+ node = node._FindNode(part)
+ if not node:
+ return None
+ return node
- poffset = libfdt.fdt_next_property_offset(self._fdt, poffset)
- return props_dict
+ def Flush(self):
+ """Flush device tree changes back to the file
+
+ If the device tree has changed in memory, write it back to the file.
+ Subclasses can implement this if needed.
+ """
+ pass
+
+ def Pack(self):
+ """Pack the device tree down to its minimum size
+
+ When nodes and properties shrink or are deleted, wasted space can
+ build up in the device tree binary. Subclasses can implement this
+ to remove that spare space.
+ """
+ pass
diff --git a/tools/dtoc/fdt_fallback.py b/tools/dtoc/fdt_fallback.py
index 9ed11e4..23e2679 100644
--- a/tools/dtoc/fdt_fallback.py
+++ b/tools/dtoc/fdt_fallback.py
@@ -7,6 +7,8 @@
#
import command
+import fdt
+from fdt import Fdt, NodeBase, PropBase
import fdt_util
import sys
@@ -17,7 +19,7 @@
# is not very efficient for larger trees. The tool is called once for each
# node and property in the tree.
-class Prop:
+class Prop(PropBase):
"""A device tree property
Properties:
@@ -26,58 +28,17 @@
bytes
type: Value type
"""
- def __init__(self, name, byte_list_str):
- self.name = name
- self.value = None
+ def __init__(self, node, name, byte_list_str):
+ PropBase.__init__(self, node, 0, name)
if not byte_list_str.strip():
- self.type = fdt_util.TYPE_BOOL
+ self.type = fdt.TYPE_BOOL
return
- bytes = [chr(int(byte, 16)) for byte in byte_list_str.strip().split(' ')]
- self.type, self.value = fdt_util.BytesToValue(''.join(bytes))
-
- def GetPhandle(self):
- """Get a (single) phandle value from a property
-
- Gets the phandle valuie from a property and returns it as an integer
- """
- return fdt_util.fdt32_to_cpu(self.value[:4])
-
- def Widen(self, newprop):
- """Figure out which property type is more general
-
- Given a current property and a new property, this function returns the
- one that is less specific as to type. The less specific property will
- be ble to represent the data in the more specific property. This is
- used for things like:
-
- node1 {
- compatible = "fred";
- value = <1>;
- };
- node1 {
- compatible = "fred";
- value = <1 2>;
- };
-
- He we want to use an int array for 'value'. The first property
- suggests that a single int is enough, but the second one shows that
- it is not. Calling this function with these two propertes would
- update the current property to be like the second, since it is less
- specific.
- """
- if newprop.type < self.type:
- self.type = newprop.type
-
- if type(newprop.value) == list and type(self.value) != list:
- self.value = newprop.value
-
- if type(self.value) == list and len(newprop.value) > len(self.value):
- val = fdt_util.GetEmpty(self.type)
- while len(self.value) < len(newprop.value):
- self.value.append(val)
+ self.bytes = [chr(int(byte, 16))
+ for byte in byte_list_str.strip().split(' ')]
+ self.type, self.value = self.BytesToValue(''.join(self.bytes))
-class Node:
+class Node(NodeBase):
"""A device tree node
Properties:
@@ -88,12 +49,8 @@
props: A dict of properties for this node, each a Prop object.
Keyed by property name
"""
- def __init__(self, fdt, name, path):
- self.name = name
- self.path = path
- self._fdt = fdt
- self.subnodes = []
- self.props = {}
+ def __init__(self, fdt, offset, name, path):
+ NodeBase.__init__(self, fdt, offset, name, path)
def Scan(self):
"""Scan a node's properties and subnodes
@@ -101,45 +58,43 @@
This fills in the props and subnodes properties, recursively
searching into subnodes so that the entire tree is built.
"""
- for name, byte_list_str in self._fdt.GetProps(self.path).iteritems():
- prop = Prop(name, byte_list_str)
+ for name, byte_list_str in self._fdt.GetProps(self.path).items():
+ prop = Prop(self, name, byte_list_str)
self.props[name] = prop
for name in self._fdt.GetSubNodes(self.path):
sep = '' if self.path[-1] == '/' else '/'
path = self.path + sep + name
- node = Node(self._fdt, name, path)
+ node = Node(self._fdt, 0, name, path)
self.subnodes.append(node)
node.Scan()
+ def DeleteProp(self, prop_name):
+ """Delete a property of a node
-class Fdt:
- """Provides simple access to a flat device tree blob.
+ The property is deleted using fdtput.
+
+ Args:
+ prop_name: Name of the property to delete
+ Raises:
+ CommandError if the property does not exist
+ """
+ args = [self._fdt._fname, '-d', self.path, prop_name]
+ command.Output('fdtput', *args)
+ del self.props[prop_name]
+
+class FdtFallback(Fdt):
+ """Provides simple access to a flat device tree blob using fdtget/fdtput
Properties:
- fname: Filename of fdt
- _root: Root of device tree (a Node object)
+ See superclass
"""
def __init__(self, fname):
- self.fname = fname
-
- def Scan(self):
- """Scan a device tree, building up a tree of Node objects
-
- This fills in the self._root property
- """
- self._root = Node(self, '/', '/')
- self._root.Scan()
-
- def GetRoot(self):
- """Get the root Node of the device tree
-
- Returns:
- The root Node object
- """
- return self._root
+ Fdt.__init__(self, fname)
+ if self._fname:
+ self._fname = fdt_util.EnsureCompiled(self._fname)
def GetSubNodes(self, node):
"""Returns a list of sub-nodes of a given node
@@ -153,15 +108,14 @@
Raises:
CmdError: if the node does not exist.
"""
- out = command.Output('fdtget', self.fname, '-l', node)
+ out = command.Output('fdtget', self._fname, '-l', node)
return out.strip().splitlines()
- def GetProps(self, node, convert_dashes=False):
+ def GetProps(self, node):
"""Get all properties from a node
Args:
node: full path to node name to look in
- convert_dashes: True to convert - to _ in node names
Returns:
A dictionary containing all the properties, indexed by node name.
@@ -171,13 +125,11 @@
Raises:
CmdError: if the node does not exist.
"""
- out = command.Output('fdtget', self.fname, node, '-p')
+ out = command.Output('fdtget', self._fname, node, '-p')
props = out.strip().splitlines()
props_dict = {}
for prop in props:
name = prop
- if convert_dashes:
- prop = re.sub('-', '_', prop)
props_dict[prop] = self.GetProp(node, name)
return props_dict
@@ -204,10 +156,26 @@
Raises:
CmdError: if the property does not exist and no default is provided.
"""
- args = [self.fname, node, prop, '-t', 'bx']
+ args = [self._fname, node, prop, '-t', 'bx']
if default is not None:
args += ['-d', str(default)]
if typespec is not None:
- args += ['-t%s' % typespec]
+ args += ['-t', typespec]
out = command.Output('fdtget', *args)
return out.strip()
+
+ @classmethod
+ def Node(self, fdt, offset, name, path):
+ """Create a new node
+
+ This is used by Fdt.Scan() to create a new node using the correct
+ class.
+
+ Args:
+ fdt: Fdt object
+ offset: Offset of node
+ name: Node name
+ path: Full path to node
+ """
+ node = Node(fdt, offset, name, path)
+ return node
diff --git a/tools/dtoc/fdt_normal.py b/tools/dtoc/fdt_normal.py
new file mode 100644
index 0000000..cce5c06
--- /dev/null
+++ b/tools/dtoc/fdt_normal.py
@@ -0,0 +1,225 @@
+#!/usr/bin/python
+#
+# Copyright (C) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+import struct
+import sys
+
+import fdt
+from fdt import Fdt, NodeBase, PropBase
+import fdt_util
+import libfdt
+
+# This deals with a device tree, presenting it as a list of Node and Prop
+# objects, representing nodes and properties, respectively.
+#
+# This implementation uses a libfdt Python library to access the device tree,
+# so it is fairly efficient.
+
+def CheckErr(errnum, msg):
+ if errnum:
+ raise ValueError('Error %d: %s: %s' %
+ (errnum, libfdt.fdt_strerror(errnum), msg))
+
+class Prop(PropBase):
+ """A device tree property
+
+ Properties:
+ name: Property name (as per the device tree)
+ value: Property value as a string of bytes, or a list of strings of
+ bytes
+ type: Value type
+ """
+ def __init__(self, node, offset, name, bytes):
+ PropBase.__init__(self, node, offset, name)
+ self.bytes = bytes
+ if not bytes:
+ self.type = fdt.TYPE_BOOL
+ self.value = True
+ return
+ self.type, self.value = self.BytesToValue(bytes)
+
+ def GetOffset(self):
+ """Get the offset of a property
+
+ Returns:
+ The offset of the property (struct fdt_property) within the file
+ """
+ return self._node._fdt.GetStructOffset(self._offset)
+
+class Node(NodeBase):
+ """A device tree node
+
+ Properties:
+ offset: Integer offset in the device tree
+ name: Device tree node tname
+ path: Full path to node, along with the node name itself
+ _fdt: Device tree object
+ subnodes: A list of subnodes for this node, each a Node object
+ props: A dict of properties for this node, each a Prop object.
+ Keyed by property name
+ """
+ def __init__(self, fdt, offset, name, path):
+ NodeBase.__init__(self, fdt, offset, name, path)
+
+ def Offset(self):
+ """Returns the offset of a node, after checking the cache
+
+ This should be used instead of self._offset directly, to ensure that
+ the cache does not contain invalid offsets.
+ """
+ self._fdt.CheckCache()
+ return self._offset
+
+ def Scan(self):
+ """Scan a node's properties and subnodes
+
+ This fills in the props and subnodes properties, recursively
+ searching into subnodes so that the entire tree is built.
+ """
+ self.props = self._fdt.GetProps(self)
+
+ offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self.Offset())
+ while offset >= 0:
+ sep = '' if self.path[-1] == '/' else '/'
+ name = libfdt.Name(self._fdt.GetFdt(), offset)
+ path = self.path + sep + name
+ node = Node(self._fdt, offset, name, path)
+ self.subnodes.append(node)
+
+ node.Scan()
+ offset = libfdt.fdt_next_subnode(self._fdt.GetFdt(), offset)
+
+ def Refresh(self, my_offset):
+ """Fix up the _offset for each node, recursively
+
+ Note: This does not take account of property offsets - these will not
+ be updated.
+ """
+ if self._offset != my_offset:
+ #print '%s: %d -> %d\n' % (self.path, self._offset, my_offset)
+ self._offset = my_offset
+ offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self._offset)
+ for subnode in self.subnodes:
+ subnode.Refresh(offset)
+ offset = libfdt.fdt_next_subnode(self._fdt.GetFdt(), offset)
+
+ def DeleteProp(self, prop_name):
+ """Delete a property of a node
+
+ The property is deleted and the offset cache is invalidated.
+
+ Args:
+ prop_name: Name of the property to delete
+ Raises:
+ ValueError if the property does not exist
+ """
+ CheckErr(libfdt.fdt_delprop(self._fdt.GetFdt(), self.Offset(), prop_name),
+ "Node '%s': delete property: '%s'" % (self.path, prop_name))
+ del self.props[prop_name]
+ self._fdt.Invalidate()
+
+class FdtNormal(Fdt):
+ """Provides simple access to a flat device tree blob using libfdt.
+
+ Properties:
+ _fdt: Device tree contents (bytearray)
+ _cached_offsets: True if all the nodes have a valid _offset property,
+ False if something has changed to invalidate the offsets
+ """
+ def __init__(self, fname):
+ Fdt.__init__(self, fname)
+ self._cached_offsets = False
+ if self._fname:
+ self._fname = fdt_util.EnsureCompiled(self._fname)
+
+ with open(self._fname) as fd:
+ self._fdt = bytearray(fd.read())
+
+ def GetFdt(self):
+ """Get the contents of the FDT
+
+ Returns:
+ The FDT contents as a string of bytes
+ """
+ return self._fdt
+
+ def Flush(self):
+ """Flush device tree changes back to the file"""
+ with open(self._fname, 'wb') as fd:
+ fd.write(self._fdt)
+
+ def Pack(self):
+ """Pack the device tree down to its minimum size"""
+ CheckErr(libfdt.fdt_pack(self._fdt), 'pack')
+ fdt_len = libfdt.fdt_totalsize(self._fdt)
+ del self._fdt[fdt_len:]
+
+ def GetProps(self, node):
+ """Get all properties from a node.
+
+ Args:
+ node: Full path to node name to look in.
+
+ Returns:
+ A dictionary containing all the properties, indexed by node name.
+ The entries are Prop objects.
+
+ Raises:
+ ValueError: if the node does not exist.
+ """
+ props_dict = {}
+ poffset = libfdt.fdt_first_property_offset(self._fdt, node._offset)
+ while poffset >= 0:
+ dprop, plen = libfdt.fdt_get_property_by_offset(self._fdt, poffset)
+ prop = Prop(node, poffset, libfdt.String(self._fdt, dprop.nameoff),
+ libfdt.Data(dprop))
+ props_dict[prop.name] = prop
+
+ poffset = libfdt.fdt_next_property_offset(self._fdt, poffset)
+ return props_dict
+
+ def Invalidate(self):
+ """Mark our offset cache as invalid"""
+ self._cached_offsets = False
+
+ def CheckCache(self):
+ """Refresh the offset cache if needed"""
+ if self._cached_offsets:
+ return
+ self.Refresh()
+ self._cached_offsets = True
+
+ def Refresh(self):
+ """Refresh the offset cache"""
+ self._root.Refresh(0)
+
+ def GetStructOffset(self, offset):
+ """Get the file offset of a given struct offset
+
+ Args:
+ offset: Offset within the 'struct' region of the device tree
+ Returns:
+ Position of @offset within the device tree binary
+ """
+ return libfdt.fdt_off_dt_struct(self._fdt) + offset
+
+ @classmethod
+ def Node(self, fdt, offset, name, path):
+ """Create a new node
+
+ This is used by Fdt.Scan() to create a new node using the correct
+ class.
+
+ Args:
+ fdt: Fdt object
+ offset: Offset of node
+ name: Node name
+ path: Full path to node
+ """
+ node = Node(fdt, offset, name, path)
+ return node
diff --git a/tools/dtoc/fdt_select.py b/tools/dtoc/fdt_select.py
new file mode 100644
index 0000000..ea78c52
--- /dev/null
+++ b/tools/dtoc/fdt_select.py
@@ -0,0 +1,36 @@
+#!/usr/bin/python
+#
+# Copyright (C) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+import fdt_fallback
+
+# Bring in either the normal fdt library (which relies on libfdt) or the
+# fallback one (which uses fdtget and is slower). Both provide the same
+# interface for this file to use.
+try:
+ import fdt_normal
+ have_libfdt = True
+except ImportError:
+ have_libfdt = False
+
+force_fallback = False
+
+def FdtScan(fname, _force_fallback=False):
+ """Returns a new Fdt object from the implementation we are using"""
+ if have_libfdt and not force_fallback and not _force_fallback:
+ dtb = fdt_normal.FdtNormal(fname)
+ else:
+ dtb = fdt_fallback.FdtFallback(fname)
+ dtb.Scan()
+ return dtb
+
+def UseFallback(fallback):
+ global force_fallback
+
+ old_val = force_fallback
+ force_fallback = fallback
+ return old_val
diff --git a/tools/dtoc/fdt_util.py b/tools/dtoc/fdt_util.py
index 929b524..e6d523b 100644
--- a/tools/dtoc/fdt_util.py
+++ b/tools/dtoc/fdt_util.py
@@ -6,73 +6,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
+import os
import struct
+import sys
+import tempfile
-# A list of types we support
-(TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL) = range(4)
-
-def BytesToValue(bytes):
- """Converts a string of bytes into a type and value
-
- Args:
- A string containing bytes
-
- Return:
- A tuple:
- Type of data
- Data, either a single element or a list of elements. Each element
- is one of:
- TYPE_STRING: string value from the property
- TYPE_INT: a byte-swapped integer stored as a 4-byte string
- TYPE_BYTE: a byte stored as a single-byte string
- """
- size = len(bytes)
- strings = bytes.split('\0')
- is_string = True
- count = len(strings) - 1
- if count > 0 and not strings[-1]:
- for string in strings[:-1]:
- if not string:
- is_string = False
- break
- for ch in string:
- if ch < ' ' or ch > '~':
- is_string = False
- break
- else:
- is_string = False
- if is_string:
- if count == 1:
- return TYPE_STRING, strings[0]
- else:
- return TYPE_STRING, strings[:-1]
- if size % 4:
- if size == 1:
- return TYPE_BYTE, bytes[0]
- else:
- return TYPE_BYTE, list(bytes)
- val = []
- for i in range(0, size, 4):
- val.append(bytes[i:i + 4])
- if size == 4:
- return TYPE_INT, val[0]
- else:
- return TYPE_INT, val
-
-def GetEmpty(type):
- """Get an empty / zero value of the given type
-
- Returns:
- A single value of the given type
- """
- if type == TYPE_BYTE:
- return chr(0)
- elif type == TYPE_INT:
- return struct.pack('<I', 0);
- elif type == TYPE_STRING:
- return ''
- else:
- return True
+import command
+import tools
def fdt32_to_cpu(val):
"""Convert a device tree cell to an integer
@@ -83,4 +23,67 @@
Return:
A native-endian integer value
"""
- return struct.unpack(">I", val)[0]
+ if sys.version_info > (3, 0):
+ val = val.encode('raw_unicode_escape')
+ return struct.unpack('>I', val)[0]
+
+def EnsureCompiled(fname):
+ """Compile an fdt .dts source file into a .dtb binary blob if needed.
+
+ Args:
+ fname: Filename (if .dts it will be compiled). It not it will be
+ left alone
+
+ Returns:
+ Filename of resulting .dtb file
+ """
+ _, ext = os.path.splitext(fname)
+ if ext != '.dts':
+ return fname
+
+ dts_input = tools.GetOutputFilename('source.dts')
+ dtb_output = tools.GetOutputFilename('source.dtb')
+
+ search_paths = [os.path.join(os.getcwd(), 'include')]
+ root, _ = os.path.splitext(fname)
+ args = ['-E', '-P', '-x', 'assembler-with-cpp', '-D__ASSEMBLY__']
+ args += ['-Ulinux']
+ for path in search_paths:
+ args.extend(['-I', path])
+ args += ['-o', dts_input, fname]
+ command.Run('cc', *args)
+
+ # If we don't have a directory, put it in the tools tempdir
+ search_list = []
+ for path in search_paths:
+ search_list.extend(['-i', path])
+ args = ['-I', 'dts', '-o', dtb_output, '-O', 'dtb']
+ args.extend(search_list)
+ args.append(dts_input)
+ command.Run('dtc', *args)
+ return dtb_output
+
+def GetInt(node, propname, default=None):
+ prop = node.props.get(propname)
+ if not prop:
+ return default
+ value = fdt32_to_cpu(prop.value)
+ if type(value) == type(list):
+ raise ValueError("Node '%s' property '%' has list value: expecting"
+ "a single integer" % (node.name, propname))
+ return value
+
+def GetString(node, propname, default=None):
+ prop = node.props.get(propname)
+ if not prop:
+ return default
+ value = prop.value
+ if type(value) == type(list):
+ raise ValueError("Node '%s' property '%' has list value: expecting"
+ "a single string" % (node.name, propname))
+ return value
+
+def GetBool(node, propname, default=False):
+ if propname in node.props:
+ return True
+ return default
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index d27f57e..862a0b1 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -643,16 +643,28 @@
return ret;
}
+/**
+ * environment_end() - compute offset of first byte right after environemnt
+ * @dev - index of enviroment buffer
+ * Return:
+ * device offset of first byte right after environemnt
+ */
+off_t environment_end(int dev)
+{
+ /* environment is block aligned */
+ return DEVOFFSET(dev) + ENVSECTORS(dev) * DEVESIZE(dev);
+}
+
/*
* Test for bad block on NAND, just returns 0 on NOR, on NAND:
* 0 - block is good
* > 0 - block is bad
* < 0 - failed to test
*/
-static int flash_bad_block (int fd, uint8_t mtd_type, loff_t *blockstart)
+static int flash_bad_block(int fd, uint8_t mtd_type, loff_t blockstart)
{
if (mtd_type == MTD_NANDFLASH) {
- int badblock = ioctl (fd, MEMGETBADBLOCK, blockstart);
+ int badblock = ioctl(fd, MEMGETBADBLOCK, &blockstart);
if (badblock < 0) {
perror ("Cannot read bad block mark");
@@ -662,7 +674,7 @@
if (badblock) {
#ifdef DEBUG
fprintf (stderr, "Bad block at 0x%llx, skipping\n",
- (unsigned long long) *blockstart);
+ (unsigned long long)blockstart);
#endif
return badblock;
}
@@ -677,13 +689,12 @@
* the DEVOFFSET (dev) block. On NOR the loop is only run once.
*/
static int flash_read_buf (int dev, int fd, void *buf, size_t count,
- off_t offset, uint8_t mtd_type)
+ off_t offset)
{
size_t blocklen; /* erase / write length - one block on NAND,
0 on NOR */
size_t processed = 0; /* progress counter */
size_t readlen = count; /* current read length */
- off_t top_of_range; /* end of the last block we may use */
off_t block_seek; /* offset inside the current block to the start
of the data */
loff_t blockstart; /* running start of the current block -
@@ -695,35 +706,27 @@
/* Offset inside a block */
block_seek = offset - blockstart;
- if (mtd_type == MTD_NANDFLASH) {
+ if (DEVTYPE(dev) == MTD_NANDFLASH) {
/*
* NAND: calculate which blocks we are reading. We have
* to read one block at a time to skip bad blocks.
*/
blocklen = DEVESIZE (dev);
- /*
- * To calculate the top of the range, we have to use the
- * global DEVOFFSET (dev), which can be different from offset
- */
- top_of_range = ((DEVOFFSET(dev) / blocklen) +
- ENVSECTORS (dev)) * blocklen;
-
/* Limit to one block for the first read */
if (readlen > blocklen - block_seek)
readlen = blocklen - block_seek;
} else {
blocklen = 0;
- top_of_range = offset + count;
}
/* This only runs once on NOR flash */
while (processed < count) {
- rc = flash_bad_block (fd, mtd_type, &blockstart);
+ rc = flash_bad_block(fd, DEVTYPE(dev), blockstart);
if (rc < 0) /* block test failed */
return -1;
- if (blockstart + block_seek + readlen > top_of_range) {
+ if (blockstart + block_seek + readlen > environment_end(dev)) {
/* End of range is reached */
fprintf (stderr,
"Too few good blocks within range\n");
@@ -762,12 +765,12 @@
}
/*
- * Write count bytes at offset, but stay within ENVSECTORS (dev) sectors of
+ * Write count bytes from begin of environment, but stay within
+ * ENVSECTORS(dev) sectors of
* DEVOFFSET (dev). Similar to the read case above, on NOR and dataflash we
* erase and write the whole data at once.
*/
-static int flash_write_buf (int dev, int fd, void *buf, size_t count,
- off_t offset, uint8_t mtd_type)
+static int flash_write_buf(int dev, int fd, void *buf, size_t count)
{
void *data;
struct erase_info_user erase;
@@ -783,7 +786,6 @@
below offset */
off_t block_seek; /* offset inside the erase block to the start
of the data */
- off_t top_of_range; /* end of the last block we may use */
loff_t blockstart; /* running start of the current block -
MEMGETBADBLOCK needs 64 bits */
int rc;
@@ -791,27 +793,24 @@
/*
* For mtd devices only offset and size of the environment do matter
*/
- if (mtd_type == MTD_ABSENT) {
+ if (DEVTYPE(dev) == MTD_ABSENT) {
blocklen = count;
- top_of_range = offset + count;
erase_len = blocklen;
- blockstart = offset;
+ blockstart = DEVOFFSET(dev);
block_seek = 0;
write_total = blocklen;
} else {
blocklen = DEVESIZE(dev);
- top_of_range = ((DEVOFFSET(dev) / blocklen) +
- ENVSECTORS(dev)) * blocklen;
-
- erase_offset = (offset / blocklen) * blocklen;
+ erase_offset = DEVOFFSET(dev);
/* Maximum area we may use */
- erase_len = top_of_range - erase_offset;
+ erase_len = environment_end(dev) - erase_offset;
blockstart = erase_offset;
+
/* Offset inside a block */
- block_seek = offset - erase_offset;
+ block_seek = DEVOFFSET(dev) - erase_offset;
/*
* Data size we actually write: from the start of the block
@@ -836,8 +835,7 @@
return -1;
}
- rc = flash_read_buf (dev, fd, data, write_total, erase_offset,
- mtd_type);
+ rc = flash_read_buf(dev, fd, data, write_total, erase_offset);
if (write_total != rc)
return -1;
@@ -864,7 +862,7 @@
data = buf;
}
- if (mtd_type == MTD_NANDFLASH) {
+ if (DEVTYPE(dev) == MTD_NANDFLASH) {
/*
* NAND: calculate which blocks we are writing. We have
* to write one block at a time to skip bad blocks.
@@ -878,11 +876,11 @@
/* This only runs once on NOR flash and SPI-dataflash */
while (processed < write_total) {
- rc = flash_bad_block (fd, mtd_type, &blockstart);
+ rc = flash_bad_block(fd, DEVTYPE(dev), blockstart);
if (rc < 0) /* block test failed */
return rc;
- if (blockstart + erasesize > top_of_range) {
+ if (blockstart + erasesize > environment_end(dev)) {
fprintf (stderr, "End of range reached, aborting\n");
return -1;
}
@@ -892,11 +890,11 @@
continue;
}
- if (mtd_type != MTD_ABSENT) {
+ if (DEVTYPE(dev) != MTD_ABSENT) {
erase.start = blockstart;
ioctl(fd, MEMUNLOCK, &erase);
/* These do not need an explicit erase cycle */
- if (mtd_type != MTD_DATAFLASH)
+ if (DEVTYPE(dev) != MTD_DATAFLASH)
if (ioctl(fd, MEMERASE, &erase) != 0) {
fprintf(stderr,
"MTD erase error on %s: %s\n",
@@ -923,7 +921,7 @@
return -1;
}
- if (mtd_type != MTD_ABSENT)
+ if (DEVTYPE(dev) != MTD_ABSENT)
ioctl(fd, MEMLOCK, &erase);
processed += erasesize;
@@ -1010,8 +1008,7 @@
#endif
rc = flash_write_buf(dev_target, fd_target, environment.image,
- CUR_ENVSIZE, DEVOFFSET(dev_target),
- DEVTYPE(dev_target));
+ CUR_ENVSIZE);
if (rc < 0)
return rc;
@@ -1035,7 +1032,7 @@
int rc;
rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
- DEVOFFSET(dev_current), DEVTYPE(dev_current));
+ DEVOFFSET(dev_current));
if (rc != CUR_ENVSIZE)
return -1;
@@ -1294,18 +1291,6 @@
struct stat st;
int fd, rc = 0;
- if (DEVOFFSET(dev) % DEVESIZE(dev) != 0) {
- fprintf(stderr, "Environment does not start on (erase) block boundary\n");
- errno = EINVAL;
- return -1;
- }
-
- if (ENVSIZE(dev) > ENVSECTORS(dev) * DEVESIZE(dev)) {
- fprintf(stderr, "Environment does not fit into available sectors\n");
- errno = EINVAL;
- return -1;
- }
-
fd = open(DEVNAME(dev), O_RDONLY);
if (fd < 0) {
fprintf(stderr,
@@ -1338,9 +1323,15 @@
goto err;
}
DEVTYPE(dev) = mtdinfo.type;
+ if (DEVESIZE(dev) == 0)
+ /* Assume the erase size is the same as the env-size */
+ DEVESIZE(dev) = ENVSIZE(dev);
} else {
uint64_t size;
DEVTYPE(dev) = MTD_ABSENT;
+ if (DEVESIZE(dev) == 0)
+ /* Assume the erase size to be 512 bytes */
+ DEVESIZE(dev) = 0x200;
/*
* Check for negative offsets, treat it as backwards offset
@@ -1362,6 +1353,22 @@
}
}
+ if (ENVSECTORS(dev) == 0)
+ /* Assume enough sectors to cover the environment */
+ ENVSECTORS(dev) = DIV_ROUND_UP(ENVSIZE(dev), DEVESIZE(dev));
+
+ if (DEVOFFSET(dev) % DEVESIZE(dev) != 0) {
+ fprintf(stderr, "Environment does not start on (erase) block boundary\n");
+ errno = EINVAL;
+ return -1;
+ }
+
+ if (ENVSIZE(dev) > ENVSECTORS(dev) * DEVESIZE(dev)) {
+ fprintf(stderr, "Environment does not fit into available sectors\n");
+ errno = EINVAL;
+ return -1;
+ }
+
err:
close(fd);
return rc;
@@ -1385,10 +1392,10 @@
DEVNAME (0) = DEVICE1_NAME;
DEVOFFSET (0) = DEVICE1_OFFSET;
ENVSIZE (0) = ENV1_SIZE;
- /* Default values are: erase-size=env-size */
- DEVESIZE (0) = ENVSIZE (0);
- /* #sectors=env-size/erase-size (rounded up) */
- ENVSECTORS (0) = (ENVSIZE(0) + DEVESIZE(0) - 1) / DEVESIZE(0);
+
+ /* Set defaults for DEVESIZE, ENVSECTORS later once we
+ * know DEVTYPE
+ */
#ifdef DEVICE1_ESIZE
DEVESIZE (0) = DEVICE1_ESIZE;
#endif
@@ -1400,10 +1407,10 @@
DEVNAME (1) = DEVICE2_NAME;
DEVOFFSET (1) = DEVICE2_OFFSET;
ENVSIZE (1) = ENV2_SIZE;
- /* Default values are: erase-size=env-size */
- DEVESIZE (1) = ENVSIZE (1);
- /* #sectors=env-size/erase-size (rounded up) */
- ENVSECTORS (1) = (ENVSIZE(1) + DEVESIZE(1) - 1) / DEVESIZE(1);
+
+ /* Set defaults for DEVESIZE, ENVSECTORS later once we
+ * know DEVTYPE
+ */
#ifdef DEVICE2_ESIZE
DEVESIZE (1) = DEVICE2_ESIZE;
#endif
@@ -1469,13 +1476,9 @@
DEVNAME(i) = devname;
- if (rc < 4)
- /* Assume the erase size is the same as the env-size */
- DEVESIZE(i) = ENVSIZE(i);
-
- if (rc < 5)
- /* Assume enough env sectors to cover the environment */
- ENVSECTORS (i) = (ENVSIZE(i) + DEVESIZE(i) - 1) / DEVESIZE(i);
+ /* Set defaults for DEVESIZE, ENVSECTORS later once we
+ * know DEVTYPE
+ */
i++;
}
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index 436eca9..05588ab 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -63,6 +63,7 @@
#endif
int aes_flag; /* Is AES encryption used? */
uint8_t aes_key[AES_KEY_LENGTH];
+ char *lockname;
};
int parse_aes_key(char *key, uint8_t *bin_key);
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 7a17b28..443de36 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -46,6 +46,7 @@
{"help", no_argument, NULL, 'h'},
{"script", required_argument, NULL, 's'},
{"noheader", required_argument, NULL, 'n'},
+ {"lock", required_argument, NULL, 'l'},
{NULL, 0, NULL, 0}
};
@@ -72,6 +73,7 @@
" -c, --config configuration file, default:" CONFIG_FILE "\n"
#endif
" -n, --noheader do not repeat variable name in output\n"
+ " -l, --lock lock node, default:/var/lock\n"
"\n");
}
@@ -88,6 +90,7 @@
#ifdef CONFIG_FILE
" -c, --config configuration file, default:" CONFIG_FILE "\n"
#endif
+ " -l, --lock lock node, default:/var/lock\n"
" -s, --script batch mode to minimize writes\n"
"\n"
"Examples:\n"
@@ -119,7 +122,7 @@
env_opts.config_file = CONFIG_FILE;
#endif
- while ((c = getopt_long(argc, argv, ":a:c:h", long_options, NULL)) !=
+ while ((c = getopt_long(argc, argv, ":a:c:l:h", long_options, NULL)) !=
EOF) {
switch (c) {
case 'a':
@@ -134,6 +137,9 @@
env_opts.config_file = optarg;
break;
#endif
+ case 'l':
+ env_opts.lockname = optarg;
+ break;
case 'h':
do_printenv ? usage_printenv() : usage_setenv();
exit(EXIT_SUCCESS);
@@ -155,8 +161,8 @@
parse_common_args(argc, argv);
- while ((c = getopt_long(argc, argv, "a:c:ns:h", long_options, NULL)) !=
- EOF) {
+ while ((c = getopt_long(argc, argv, "a:c:ns:l:h", long_options, NULL))
+ != EOF) {
switch (c) {
case 'n':
noheader = 1;
@@ -164,6 +170,7 @@
case 'a':
case 'c':
case 'h':
+ case 'l':
/* ignore common options */
break;
default: /* '?' */
@@ -181,8 +188,8 @@
parse_common_args(argc, argv);
- while ((c = getopt_long(argc, argv, "a:c:ns:h", long_options, NULL)) !=
- EOF) {
+ while ((c = getopt_long(argc, argv, "a:c:ns:l:h", long_options, NULL))
+ != EOF) {
switch (c) {
case 's':
script_file = optarg;
@@ -190,6 +197,7 @@
case 'a':
case 'c':
case 'h':
+ case 'l':
/* ignore common options */
break;
default: /* '?' */
@@ -203,7 +211,7 @@
int main(int argc, char *argv[])
{
- const char *lockname = "/var/lock/" CMD_PRINTENV ".lock";
+ char *lockname = "/var/lock/" CMD_PRINTENV ".lock";
int lockfd = -1;
int retval = EXIT_SUCCESS;
char *_cmdname;
@@ -235,6 +243,18 @@
argc -= optind;
argv += optind;
+ if (env_opts.lockname) {
+ lockname = malloc(sizeof(env_opts.lockname) +
+ sizeof(CMD_PRINTENV) + 10);
+ if (!lockname) {
+ fprintf(stderr, "Unable allocate memory");
+ exit(EXIT_FAILURE);
+ }
+
+ sprintf(lockname, "%s/%s.lock",
+ env_opts.lockname, CMD_PRINTENV);
+ }
+
lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC, 0666);
if (-1 == lockfd) {
fprintf(stderr, "Error opening lock file %s\n", lockname);
@@ -260,6 +280,9 @@
}
}
+ if (env_opts.lockname)
+ free(lockname);
+
flock(lockfd, LOCK_UN);
close(lockfd);
return retval;
diff --git a/tools/envcrc.c b/tools/envcrc.c
index a9d9b48..e9fd088 100644
--- a/tools/envcrc.c
+++ b/tools/envcrc.c
@@ -12,6 +12,8 @@
#include <string.h>
#include <unistd.h>
+#include <linux/kconfig.h>
+
#ifndef __ASSEMBLY__
#define __ASSEMBLY__ /* Dirty trick to get only #defines */
#endif
diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c
index 8d3fef4..b907827 100644
--- a/tools/fdtgrep.c
+++ b/tools/fdtgrep.c
@@ -405,7 +405,7 @@
* The output of this function may or may not be a valid FDT. To ensure it
* is, these disp->flags must be set:
*
- * FDT_REG_SUPERNODES: ensures that subnodes are preceeded by their
+ * FDT_REG_SUPERNODES: ensures that subnodes are preceded by their
* parents. Without this option, fragments of subnode data may be
* output without the supernodes above them. This is useful for
* hashing but cannot produce a valid FDT.
diff --git a/tools/fit_image.c b/tools/fit_image.c
index 10fd6d4..efd8a97 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -85,8 +85,15 @@
size = imagetool_get_filesize(params, params->datafile);
if (size < 0)
return -1;
-
total_size = size;
+
+ if (params->fit_ramdisk) {
+ size = imagetool_get_filesize(params, params->fit_ramdisk);
+ if (size < 0)
+ return -1;
+ total_size += size;
+ }
+
for (cont = params->content_head; cont; cont = cont->next) {
size = imagetool_get_filesize(params, cont->fname);
if (size < 0)
@@ -233,6 +240,20 @@
fdt_end_node(fdt);
}
+ /* And a ramdisk file if available */
+ if (params->fit_ramdisk) {
+ fdt_begin_node(fdt, FIT_RAMDISK_PROP "@1");
+
+ fdt_property_string(fdt, "type", FIT_RAMDISK_PROP);
+ fdt_property_string(fdt, "os", genimg_get_os_short_name(params->os));
+
+ ret = fdt_property_file(params, fdt, "data", params->fit_ramdisk);
+ if (ret)
+ return ret;
+
+ fdt_end_node(fdt);
+ }
+
fdt_end_node(fdt);
return 0;
@@ -272,15 +293,25 @@
snprintf(str, sizeof(str), "%s@1", typename);
fdt_property_string(fdt, typename, str);
+ if (params->fit_ramdisk)
+ fdt_property_string(fdt, FIT_RAMDISK_PROP,
+ FIT_RAMDISK_PROP "@1");
+
snprintf(str, sizeof(str), FIT_FDT_PROP "@%d", upto);
fdt_property_string(fdt, FIT_FDT_PROP, str);
fdt_end_node(fdt);
}
+
if (!upto) {
fdt_begin_node(fdt, "conf@1");
typename = genimg_get_type_short_name(params->fit_image_type);
snprintf(str, sizeof(str), "%s@1", typename);
fdt_property_string(fdt, typename, str);
+
+ if (params->fit_ramdisk)
+ fdt_property_string(fdt, FIT_RAMDISK_PROP,
+ FIT_RAMDISK_PROP "@1");
+
fdt_end_node(fdt);
}
diff --git a/tools/ifdtool.c b/tools/ifdtool.c
index 48059c0..195b153 100644
--- a/tools/ifdtool.c
+++ b/tools/ifdtool.c
@@ -33,16 +33,9 @@
#define FLREG_BASE(reg) ((reg & 0x00000fff) << 12);
#define FLREG_LIMIT(reg) (((reg & 0x0fff0000) >> 4) | 0xfff);
-enum input_file_type_t {
- IF_normal,
- IF_fdt,
- IF_uboot,
-};
-
struct input_file {
char *fname;
unsigned int addr;
- enum input_file_type_t type;
};
/**
@@ -760,219 +753,6 @@
return write_size;
}
-static int scan_ucode(const void *blob, char *ucode_base, int *countp,
- const char **datap, int *data_sizep)
-{
- const char *data = NULL;
- int node, count;
- int data_size;
- char *ucode;
-
- for (node = 0, count = 0, ucode = ucode_base; node >= 0; count++) {
- node = fdt_node_offset_by_compatible(blob, node,
- "intel,microcode");
- if (node < 0)
- break;
-
- data = fdt_getprop(blob, node, "data", &data_size);
- if (!data) {
- debug("Missing microcode data in FDT '%s': %s\n",
- fdt_get_name(blob, node, NULL),
- fdt_strerror(data_size));
- return -ENOENT;
- }
-
- if (ucode_base)
- memcpy(ucode, data, data_size);
- ucode += data_size;
- }
-
- if (countp)
- *countp = count;
- if (datap)
- *datap = data;
- if (data_sizep)
- *data_sizep = data_size;
-
- return ucode - ucode_base;
-}
-
-static int remove_ucode(char *blob)
-{
- int node, count;
- int ret;
-
- /* Keep going until we find no more microcode to remove */
- do {
- for (node = 0, count = 0; node >= 0;) {
- int ret;
-
- node = fdt_node_offset_by_compatible(blob, node,
- "intel,microcode");
- if (node < 0)
- break;
-
- ret = fdt_delprop(blob, node, "data");
-
- /*
- * -FDT_ERR_NOTFOUND means we already removed the
- * data for this one, so we just continue.
- * 0 means we did remove it, so offsets may have
- * changed and we need to restart our scan.
- * Anything else indicates an error we should report.
- */
- if (ret == -FDT_ERR_NOTFOUND)
- continue;
- else if (!ret)
- node = 0;
- else
- return ret;
- }
- } while (count);
-
- /* Pack down to remove excees space */
- ret = fdt_pack(blob);
- if (ret)
- return ret;
-
- return fdt_totalsize(blob);
-}
-
-static int write_ucode(char *image, int size, struct input_file *fdt,
- int fdt_size, unsigned int ucode_ptr,
- int collate_ucode)
-{
- const char *data = NULL;
- char *ucode_buf;
- const void *blob;
- char *ucode_base;
- uint32_t *ptr;
- int ucode_size;
- int data_size;
- int offset;
- int count;
- int ret;
-
- blob = (void *)image + (uint32_t)(fdt->addr + size);
-
- debug("DTB at %lx\n", (char *)blob - image);
-
- /* Find out about the micrcode we have */
- ucode_size = scan_ucode(blob, NULL, &count, &data, &data_size);
- if (ucode_size < 0)
- return ucode_size;
- if (!count) {
- debug("No microcode found in FDT\n");
- return -ENOENT;
- }
-
- if (count > 1 && !collate_ucode) {
- fprintf(stderr,
- "Cannot handle multiple microcode blocks - please use -C flag to collate them\n");
- return -EMLINK;
- }
-
- /*
- * Collect the microcode into a buffer, remove it from the device
- * tree and place it immediately above the (now smaller) device tree.
- */
- if (collate_ucode && count > 1) {
- ucode_buf = malloc(ucode_size);
- if (!ucode_buf) {
- fprintf(stderr,
- "Out of memory for microcode (%d bytes)\n",
- ucode_size);
- return -ENOMEM;
- }
- ret = scan_ucode(blob, ucode_buf, NULL, NULL, NULL);
- if (ret < 0)
- return ret;
-
- /* Remove the microcode from the device tree */
- ret = remove_ucode((char *)blob);
- if (ret < 0) {
- debug("Could not remove FDT microcode: %s\n",
- fdt_strerror(ret));
- return -EINVAL;
- }
- debug("Collated %d microcode block(s)\n", count);
- debug("Device tree reduced from %x to %x bytes\n",
- fdt_size, ret);
- fdt_size = ret;
-
- /*
- * Place microcode area immediately above the FDT, aligned
- * to a 16-byte boundary.
- */
- ucode_base = (char *)(((unsigned long)blob + fdt_size + 15) &
- ~15);
-
- data = ucode_base;
- data_size = ucode_size;
- memcpy(ucode_base, ucode_buf, ucode_size);
- free(ucode_buf);
- }
-
- offset = (uint32_t)(ucode_ptr + size);
- ptr = (void *)image + offset;
-
- ptr[0] = (data - image) - size;
- ptr[1] = data_size;
- debug("Wrote microcode pointer at %x: addr=%x, size=%x\n", ucode_ptr,
- ptr[0], ptr[1]);
-
- return (collate_ucode ? data + data_size : (char *)blob + fdt_size) -
- image;
-}
-
-/**
- * write_uboot() - Write U-Boot, device tree and microcode pointer
- *
- * This writes U-Boot into a place in the flash, followed by its device tree.
- * The microcode pointer is written so that U-Boot can find the microcode in
- * the device tree very early in boot.
- *
- * @image: Pointer to image
- * @size: Size of image in bytes
- * @uboot: Input file information for u-boot.bin
- * @fdt: Input file information for u-boot.dtb
- * @ucode_ptr: Address in U-Boot where the microcode pointer should be placed
- * @return 0 if OK, -ve on error
- */
-static int write_uboot(char *image, int size, struct input_file *uboot,
- struct input_file *fdt, unsigned int ucode_ptr,
- int collate_ucode, int *offset_uboot_top,
- int *offset_uboot_start)
-{
- int uboot_size, fdt_size;
- int uboot_top;
-
- uboot_size = write_data(image, size, uboot->addr, uboot->fname, 0, 0);
- if (uboot_size < 0)
- return uboot_size;
- fdt->addr = uboot->addr + uboot_size;
- debug("U-Boot size %#x, FDT at %#x\n", uboot_size, fdt->addr);
- fdt_size = write_data(image, size, fdt->addr, fdt->fname, 0, 0);
- if (fdt_size < 0)
- return fdt_size;
-
- uboot_top = (uint32_t)(fdt->addr + size) + fdt_size;
-
- if (ucode_ptr) {
- uboot_top = write_ucode(image, size, fdt, fdt_size, ucode_ptr,
- collate_ucode);
- if (uboot_top < 0)
- return uboot_top;
- }
-
- if (offset_uboot_top && offset_uboot_start) {
- *offset_uboot_top = uboot_top;
- *offset_uboot_start = (uint32_t)(uboot->addr + size);
- }
-
- return 0;
-}
-
static void print_version(void)
{
printf("ifdtool v%s -- ", IFDTOOL_VERSION);
@@ -1034,7 +814,7 @@
int mode_dump = 0, mode_extract = 0, mode_inject = 0;
int mode_spifreq = 0, mode_em100 = 0, mode_locked = 0;
int mode_unlocked = 0, mode_write = 0, mode_write_descriptor = 0;
- int create = 0, collate_ucode = 0;
+ int create = 0;
char *region_type_string = NULL, *inject_fname = NULL;
char *desc_fname = NULL, *addr_str = NULL;
int region_type = -1, inputfreq = 0;
@@ -1047,14 +827,12 @@
char *outfile = NULL;
struct stat buf;
int size = 0;
- unsigned int ucode_ptr = 0;
bool have_uboot = false;
int bios_fd;
char *image;
int ret;
static struct option long_options[] = {
{"create", 0, NULL, 'c'},
- {"collate-microcode", 0, NULL, 'C'},
{"dump", 0, NULL, 'd'},
{"descriptor", 1, NULL, 'D'},
{"em100", 0, NULL, 'e'},
@@ -1062,7 +840,6 @@
{"fdt", 1, NULL, 'f'},
{"inject", 1, NULL, 'i'},
{"lock", 0, NULL, 'l'},
- {"microcode", 1, NULL, 'm'},
{"romsize", 1, NULL, 'r'},
{"spifreq", 1, NULL, 's'},
{"unlock", 0, NULL, 'u'},
@@ -1073,15 +850,12 @@
{0, 0, 0, 0}
};
- while ((opt = getopt_long(argc, argv, "cCdD:ef:hi:lm:r:s:uU:vw:x?",
+ while ((opt = getopt_long(argc, argv, "cdD:ef:hi:lr:s:uU:vw:x?",
long_options, &option_index)) != EOF) {
switch (opt) {
case 'c':
create = 1;
break;
- case 'C':
- collate_ucode = 1;
- break;
case 'd':
mode_dump = 1;
break;
@@ -1119,9 +893,6 @@
case 'l':
mode_locked = 1;
break;
- case 'm':
- ucode_ptr = strtoul(optarg, NULL, 0);
- break;
case 'r':
rom_size = strtol(optarg, NULL, 0);
debug("ROM size %d\n", rom_size);
@@ -1166,12 +937,6 @@
exit(EXIT_FAILURE);
}
ifile->addr = strtoll(optarg, NULL, 0);
- ifile->type = opt == 'f' ? IF_fdt :
- opt == 'U' ? IF_uboot : IF_normal;
- if (ifile->type == IF_fdt)
- fdt = ifile;
- else if (ifile->type == IF_uboot)
- have_uboot = true;
wr_num++;
} else {
fprintf(stderr,
@@ -1302,18 +1067,9 @@
for (wr_idx = 0; wr_idx < wr_num; wr_idx++) {
ifile = &input_file[wr_idx];
- if (ifile->type == IF_fdt) {
- continue;
- } else if (ifile->type == IF_uboot) {
- ret = write_uboot(image, size, ifile, fdt,
- ucode_ptr, collate_ucode,
- &offset_uboot_top,
- &offset_uboot_start);
- } else {
- ret = write_data(image, size, ifile->addr,
- ifile->fname, offset_uboot_top,
- offset_uboot_start);
- }
+ ret = write_data(image, size, ifile->addr,
+ ifile->fname, offset_uboot_top,
+ offset_uboot_start);
if (ret < 0)
break;
}
diff --git a/tools/image-host.c b/tools/image-host.c
index 1104695..c1a0122 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -166,9 +166,11 @@
info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
info->fit = fit;
info->node_offset = noffset;
- info->algo = image_get_sig_algo(algo_name);
+ info->name = algo_name;
+ info->checksum = image_get_checksum_algo(algo_name);
+ info->crypto = image_get_crypto_algo(algo_name);
info->require_keys = require_keys;
- if (!info->algo) {
+ if (!info->checksum || !info->crypto) {
printf("Unsupported signature algorithm (%s) for '%s' signature node in '%s' image node\n",
algo_name, node_name, image_name);
return -1;
@@ -213,7 +215,7 @@
node_name = fit_get_name(fit, noffset, NULL);
region.data = data;
region.size = size;
- ret = info.algo->sign(&info, ®ion, 1, &value, &value_len);
+ ret = info.crypto->sign(&info, ®ion, 1, &value, &value_len);
if (ret) {
printf("Failed to sign '%s' signature node in '%s' image node: %d\n",
node_name, image_name, ret);
@@ -239,7 +241,7 @@
info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
if (keydest)
- ret = info.algo->add_verify_data(&info, keydest);
+ ret = info.crypto->add_verify_data(&info, keydest);
else
return -1;
@@ -588,7 +590,8 @@
require_keys ? "conf" : NULL))
return -1;
- ret = info.algo->sign(&info, region, region_count, &value, &value_len);
+ ret = info.crypto->sign(&info, region, region_count, &value,
+ &value_len);
free(region);
if (ret) {
printf("Failed to sign '%s' signature node in '%s' conf node\n",
@@ -617,7 +620,7 @@
/* Write the public key into the supplied FDT file */
if (keydest) {
- ret = info.algo->add_verify_data(&info, keydest);
+ ret = info.crypto->add_verify_data(&info, keydest);
if (ret == -ENOSPC)
return -ENOSPC;
if (ret) {
diff --git a/tools/imagetool.h b/tools/imagetool.h
index 6c1a9d3..15c2a0c 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -70,6 +70,7 @@
int orig_file_size; /* Original size for file before padding */
bool auto_its; /* Automatically create the .its file */
int fit_image_type; /* Image type to put into the FIT */
+ char *fit_ramdisk; /* Ramdisk file to include */
struct content_info *content_head; /* List of files to include */
struct content_info *content_tail;
bool external_data; /* Store data outside the FIT */
diff --git a/tools/imximage.c b/tools/imximage.c
index 092d550..2cd8d88 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -27,6 +27,7 @@
{CMD_CHECK_BITS_CLR, "CHECK_BITS_CLR", "Reg Check bits clr", },
{CMD_CSF, "CSF", "Command Sequence File", },
{CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
+ {CMD_PLUGIN, "PLUGIN", "file plugin_addr", },
{-1, "", "", },
};
@@ -80,6 +81,9 @@
static uint32_t imximage_csf_size = UNDEFINED;
/* Initial Load Region Size */
static uint32_t imximage_init_loadsize;
+static uint32_t imximage_iram_free_start;
+static uint32_t imximage_plugin_size;
+static uint32_t plugin_image;
static set_dcd_val_t set_dcd_val;
static set_dcd_param_t set_dcd_param;
@@ -118,7 +122,11 @@
/* Try to detect V2 */
if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
- (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
+ (hdr_v2->data.dcd_table.header.tag == DCD_HEADER_TAG))
+ return IMXIMAGE_V2;
+
+ if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
+ hdr_v2->boot_data.plugin)
return IMXIMAGE_V2;
return IMXIMAGE_VER_INVALID;
@@ -165,7 +173,7 @@
static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
int32_t cmd)
{
- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+ dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.data.dcd_table;
struct dcd_v2_cmd *d = gd_last_cmd;
struct dcd_v2_cmd *d2;
int len;
@@ -261,21 +269,22 @@
static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
char *name, int lineno)
{
- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
- struct dcd_v2_cmd *d = gd_last_cmd;
- int len;
+ if (!imxhdr->header.hdr_v2.boot_data.plugin) {
+ dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.data.dcd_table;
+ struct dcd_v2_cmd *d = gd_last_cmd;
+ int len;
- if (!d)
- d = &dcd_v2->dcd_cmd;
- len = be16_to_cpu(d->write_dcd_command.length);
- if (len > 4)
- d = (struct dcd_v2_cmd *)(((char *)d) + len);
+ if (!d)
+ d = &dcd_v2->dcd_cmd;
+ len = be16_to_cpu(d->write_dcd_command.length);
+ if (len > 4)
+ d = (struct dcd_v2_cmd *)(((char *)d) + len);
- len = (char *)d - (char *)&dcd_v2->header;
-
- dcd_v2->header.tag = DCD_HEADER_TAG;
- dcd_v2->header.length = cpu_to_be16(len);
- dcd_v2->header.version = DCD_VERSION;
+ len = (char *)d - (char *)&dcd_v2->header;
+ dcd_v2->header.tag = DCD_HEADER_TAG;
+ dcd_v2->header.length = cpu_to_be16(len);
+ dcd_v2->header.version = DCD_VERSION;
+ }
}
static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
@@ -317,24 +326,94 @@
fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
- fhdr_v2->entry = entry_point;
- fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
- hdr_base = entry_point - imximage_init_loadsize +
- flash_offset;
- fhdr_v2->self = hdr_base;
- if (dcd_len > 0)
- fhdr_v2->dcd_ptr = hdr_base
- + offsetof(imx_header_v2_t, dcd_table);
- else
+ if (!hdr_v2->boot_data.plugin) {
+ fhdr_v2->entry = entry_point;
+ fhdr_v2->reserved1 = 0;
+ fhdr_v2->reserved1 = 0;
+ hdr_base = entry_point - imximage_init_loadsize +
+ flash_offset;
+ fhdr_v2->self = hdr_base;
+ if (dcd_len > 0)
+ fhdr_v2->dcd_ptr = hdr_base +
+ offsetof(imx_header_v2_t, data);
+ else
+ fhdr_v2->dcd_ptr = 0;
+ fhdr_v2->boot_data_ptr = hdr_base
+ + offsetof(imx_header_v2_t, boot_data);
+ hdr_v2->boot_data.start = entry_point - imximage_init_loadsize;
+
+ fhdr_v2->csf = 0;
+
+ header_size_ptr = &hdr_v2->boot_data.size;
+ csf_ptr = &fhdr_v2->csf;
+ } else {
+ imx_header_v2_t *next_hdr_v2;
+ flash_header_v2_t *next_fhdr_v2;
+
+ if (imximage_csf_size != 0) {
+ fprintf(stderr, "Error: Header v2: SECURE_BOOT is only supported in DCD mode!");
+ exit(EXIT_FAILURE);
+ }
+
+ fhdr_v2->entry = imximage_iram_free_start +
+ flash_offset + sizeof(flash_header_v2_t) +
+ sizeof(boot_data_t);
+
+ fhdr_v2->reserved1 = 0;
+ fhdr_v2->reserved2 = 0;
+ fhdr_v2->self = imximage_iram_free_start + flash_offset;
+
fhdr_v2->dcd_ptr = 0;
- fhdr_v2->boot_data_ptr = hdr_base
- + offsetof(imx_header_v2_t, boot_data);
- hdr_v2->boot_data.start = entry_point - imximage_init_loadsize;
- fhdr_v2->csf = 0;
+ fhdr_v2->boot_data_ptr = fhdr_v2->self +
+ offsetof(imx_header_v2_t, boot_data);
- header_size_ptr = &hdr_v2->boot_data.size;
- csf_ptr = &fhdr_v2->csf;
+ hdr_v2->boot_data.start = imximage_iram_free_start;
+ /*
+ * The actural size of plugin image is "imximage_plugin_size +
+ * sizeof(flash_header_v2_t) + sizeof(boot_data_t)", plus the
+ * flash_offset space.The ROM code only need to copy this size
+ * to run the plugin code. However, later when copy the whole
+ * U-Boot image to DDR, the ROM code use memcpy to copy the
+ * first part of the image, and use the storage read function
+ * to get the remaining part. This requires the dividing point
+ * must be multiple of storage sector size. Here we set the
+ * first section to be MAX_PLUGIN_CODE_SIZE(64KB) for this
+ * purpose.
+ */
+ hdr_v2->boot_data.size = MAX_PLUGIN_CODE_SIZE;
+
+ /* Security feature are not supported */
+ fhdr_v2->csf = 0;
+
+ next_hdr_v2 = (imx_header_v2_t *)((char *)hdr_v2 +
+ imximage_plugin_size);
+
+ next_fhdr_v2 = &next_hdr_v2->fhdr;
+
+ next_fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
+ next_fhdr_v2->header.length =
+ cpu_to_be16(sizeof(flash_header_v2_t));
+ next_fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
+
+ next_fhdr_v2->entry = entry_point;
+ hdr_base = entry_point - sizeof(struct imx_header);
+ next_fhdr_v2->reserved1 = 0;
+ next_fhdr_v2->reserved2 = 0;
+ next_fhdr_v2->self = hdr_base + imximage_plugin_size;
+
+ next_fhdr_v2->dcd_ptr = 0;
+ next_fhdr_v2->boot_data_ptr = next_fhdr_v2->self +
+ offsetof(imx_header_v2_t, boot_data);
+
+ next_hdr_v2->boot_data.start = hdr_base - flash_offset;
+
+ header_size_ptr = &next_hdr_v2->boot_data.size;
+
+ next_hdr_v2->boot_data.plugin = 0;
+
+ next_fhdr_v2->csf = 0;
+ }
}
static void set_hdr_func(void)
@@ -393,16 +472,19 @@
{
imx_header_v2_t *hdr_v2 = &imx_hdr->header.hdr_v2;
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
- dcd_v2_t *dcd_v2 = &hdr_v2->dcd_table;
- uint32_t size, version;
+ dcd_v2_t *dcd_v2 = &hdr_v2->data.dcd_table;
+ uint32_t size, version, plugin;
- size = be16_to_cpu(dcd_v2->header.length);
- if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t)) + 8) {
- fprintf(stderr,
- "Error: Image corrupt DCD size %d exceed maximum %d\n",
- (uint32_t)(size / sizeof(dcd_addr_data_t)),
- MAX_HW_CFG_SIZE_V2);
- exit(EXIT_FAILURE);
+ plugin = hdr_v2->boot_data.plugin;
+ if (!plugin) {
+ size = be16_to_cpu(dcd_v2->header.length);
+ if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
+ fprintf(stderr,
+ "Error: Image corrupt DCD size %d exceed maximum %d\n",
+ (uint32_t)(size / sizeof(dcd_addr_data_t)),
+ MAX_HW_CFG_SIZE_V2);
+ exit(EXIT_FAILURE);
+ }
}
version = detect_imximage_version(imx_hdr);
@@ -410,19 +492,97 @@
printf("Image Type: Freescale IMX Boot Image\n");
printf("Image Ver: %x", version);
printf("%s\n", get_table_entry_name(imximage_versions, NULL, version));
- printf("Data Size: ");
- genimg_print_size(hdr_v2->boot_data.size);
- printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
- printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
- if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) &&
- (imximage_csf_size != UNDEFINED)) {
- printf("HAB Blocks: %08x %08x %08x\n",
- (uint32_t)fhdr_v2->self, 0,
- hdr_v2->boot_data.size - imximage_ivt_offset -
- imximage_csf_size);
+ printf("Mode: %s\n", plugin ? "PLUGIN" : "DCD");
+ if (!plugin) {
+ printf("Data Size: ");
+ genimg_print_size(hdr_v2->boot_data.size);
+ printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
+ printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
+ if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) &&
+ (imximage_csf_size != UNDEFINED)) {
+ uint16_t dcdlen;
+ int offs;
+
+ dcdlen = hdr_v2->data.dcd_table.header.length;
+ offs = (char *)&hdr_v2->data.dcd_table
+ - (char *)hdr_v2;
+
+ printf("HAB Blocks: %08x %08x %08x\n",
+ (uint32_t)fhdr_v2->self, 0,
+ hdr_v2->boot_data.size - imximage_ivt_offset -
+ imximage_csf_size);
+ printf("DCD Blocks: 00910000 %08x %08x\n",
+ offs, be16_to_cpu(dcdlen));
+ }
+ } else {
+ imx_header_v2_t *next_hdr_v2;
+ flash_header_v2_t *next_fhdr_v2;
+
+ /*First Header*/
+ printf("Plugin Data Size: ");
+ genimg_print_size(hdr_v2->boot_data.size);
+ printf("Plugin Code Size: ");
+ genimg_print_size(imximage_plugin_size);
+ printf("Plugin Load Address: %08x\n", hdr_v2->boot_data.start);
+ printf("Plugin Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
+
+ /*Second Header*/
+ next_hdr_v2 = (imx_header_v2_t *)((char *)hdr_v2 +
+ imximage_plugin_size);
+ next_fhdr_v2 = &next_hdr_v2->fhdr;
+ printf("U-Boot Data Size: ");
+ genimg_print_size(next_hdr_v2->boot_data.size);
+ printf("U-Boot Load Address: %08x\n",
+ next_hdr_v2->boot_data.start);
+ printf("U-Boot Entry Point: %08x\n",
+ (uint32_t)next_fhdr_v2->entry);
}
}
+static void copy_plugin_code(struct imx_header *imxhdr, char *plugin_file)
+{
+ int ifd;
+ struct stat sbuf;
+ char *plugin_buf = imxhdr->header.hdr_v2.data.plugin_code;
+ char *ptr;
+
+ ifd = open(plugin_file, O_RDONLY|O_BINARY);
+ if (ifd < 0) {
+ fprintf(stderr, "Can't open %s: %s\n",
+ plugin_file,
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ if (fstat(ifd, &sbuf) < 0) {
+ fprintf(stderr, "Can't stat %s: %s\n",
+ plugin_file,
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0);
+ if (ptr == MAP_FAILED) {
+ fprintf(stderr, "Can't read %s: %s\n",
+ plugin_file,
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ if (sbuf.st_size > MAX_PLUGIN_CODE_SIZE) {
+ printf("plugin binary size too large\n");
+ exit(EXIT_FAILURE);
+ }
+
+ memcpy(plugin_buf, ptr, sbuf.st_size);
+ imximage_plugin_size = sbuf.st_size;
+
+ (void) munmap((void *)ptr, sbuf.st_size);
+ (void) close(ifd);
+
+ imxhdr->header.hdr_v2.boot_data.plugin = 1;
+}
+
static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
char *name, int lineno, int fld, int dcd_len)
{
@@ -497,6 +657,10 @@
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
+ case CMD_PLUGIN:
+ plugin_image = 1;
+ copy_plugin_code(imxhdr, token);
+ break;
}
}
@@ -542,6 +706,10 @@
}
}
break;
+ case CMD_PLUGIN:
+ value = get_cfg_value(token, name, lineno);
+ imximage_iram_free_start = value;
+ break;
default:
break;
}
@@ -649,6 +817,7 @@
{
struct imx_header *imxhdr = (struct imx_header *)ptr;
uint32_t dcd_len;
+ uint32_t header_size;
/*
* In order to not change the old imx cfg file
@@ -665,10 +834,15 @@
dcd_len = parse_cfg_file(imxhdr, params->imagename);
if (imximage_version == IMXIMAGE_V2) {
- if (imximage_init_loadsize < imximage_ivt_offset +
- sizeof(imx_header_v2_t))
+ header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
+ if (!plugin_image)
+ header_size += sizeof(dcd_v2_t);
+ else
+ header_size += MAX_PLUGIN_CODE_SIZE;
+
+ if (imximage_init_loadsize < imximage_ivt_offset + header_size)
imximage_init_loadsize = imximage_ivt_offset +
- sizeof(imx_header_v2_t);
+ header_size;
}
/* Set the imx header */
@@ -721,7 +895,7 @@
size_t alloc_len;
struct stat sbuf;
char *datafile = params->datafile;
- uint32_t pad_len;
+ uint32_t pad_len, header_size;
memset(&imximage_header, 0, sizeof(imximage_header));
@@ -742,15 +916,21 @@
/* TODO: check i.MX image V1 handling, for now use 'old' style */
if (imximage_version == IMXIMAGE_V1) {
alloc_len = 4096;
+ header_size = 4096;
} else {
- if (imximage_init_loadsize < imximage_ivt_offset +
- sizeof(imx_header_v2_t))
+ header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
+ if (!plugin_image)
+ header_size += sizeof(dcd_v2_t);
+ else
+ header_size += MAX_PLUGIN_CODE_SIZE;
+
+ if (imximage_init_loadsize < imximage_ivt_offset + header_size)
imximage_init_loadsize = imximage_ivt_offset +
- sizeof(imx_header_v2_t);
+ header_size;
alloc_len = imximage_init_loadsize - imximage_ivt_offset;
}
- if (alloc_len < sizeof(struct imx_header)) {
+ if (alloc_len < header_size) {
fprintf(stderr, "%s: header error\n",
params->cmdname);
exit(EXIT_FAILURE);
diff --git a/tools/imximage.h b/tools/imximage.h
index c7b9b5c..db8b9a3 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -9,6 +9,7 @@
#define _IMXIMAGE_H_
#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
+#define MAX_PLUGIN_CODE_SIZE (64 * 1024)
#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
#define APP_CODE_BARKER 0xB1
#define DCD_BARKER 0xB17219E9
@@ -64,6 +65,7 @@
CMD_CHECK_BITS_SET,
CMD_CHECK_BITS_CLR,
CMD_CSF,
+ CMD_PLUGIN,
};
enum imximage_fld_types {
@@ -164,7 +166,10 @@
typedef struct {
flash_header_v2_t fhdr;
boot_data_t boot_data;
- dcd_v2_t dcd_table;
+ union {
+ dcd_v2_t dcd_table;
+ char plugin_code[MAX_PLUGIN_CODE_SIZE];
+ } data;
} imx_header_v2_t;
/* The header must be aligned to 4k on MX53 for NAND boot */
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 369aba7..69844d9 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -68,6 +68,8 @@
IMAGE_CFG_BINARY,
IMAGE_CFG_PAYLOAD,
IMAGE_CFG_DATA,
+ IMAGE_CFG_BAUDRATE,
+ IMAGE_CFG_DEBUG,
} type;
union {
unsigned int version;
@@ -85,6 +87,8 @@
unsigned int nandeccmode;
unsigned int nandpagesz;
struct ext_hdr_v0_reg regdata;
+ unsigned int baudrate;
+ unsigned int debug;
};
};
@@ -195,6 +199,28 @@
return csum;
}
+static uint8_t baudrate_to_option(unsigned int baudrate)
+{
+ switch (baudrate) {
+ case 2400:
+ return MAIN_HDR_V1_OPT_BAUD_2400;
+ case 4800:
+ return MAIN_HDR_V1_OPT_BAUD_4800;
+ case 9600:
+ return MAIN_HDR_V1_OPT_BAUD_9600;
+ case 19200:
+ return MAIN_HDR_V1_OPT_BAUD_19200;
+ case 38400:
+ return MAIN_HDR_V1_OPT_BAUD_38400;
+ case 57600:
+ return MAIN_HDR_V1_OPT_BAUD_57600;
+ case 115200:
+ return MAIN_HDR_V1_OPT_BAUD_115200;
+ default:
+ return MAIN_HDR_V1_OPT_BAUD_DEFAULT;
+ }
+}
+
static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
int payloadsz)
{
@@ -398,6 +424,12 @@
e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
if (e)
main_hdr->nandbadblklocation = e->nandbadblklocation;
+ e = image_find_option(IMAGE_CFG_BAUDRATE);
+ if (e)
+ main_hdr->options = baudrate_to_option(e->baudrate);
+ e = image_find_option(IMAGE_CFG_DEBUG);
+ if (e)
+ main_hdr->flags = e->debug ? 0x1 : 0;
binarye = image_find_option(IMAGE_CFG_BINARY);
if (binarye) {
@@ -548,6 +580,14 @@
el->type = IMAGE_CFG_DATA;
el->regdata.raddr = strtoul(value1, NULL, 16);
el->regdata.rdata = strtoul(value2, NULL, 16);
+ } else if (!strcmp(keyword, "BAUDRATE")) {
+ char *value = strtok_r(NULL, deliminiters, &saveptr);
+ el->type = IMAGE_CFG_BAUDRATE;
+ el->baudrate = strtoul(value, NULL, 10);
+ } else if (!strcmp(keyword, "DEBUG")) {
+ char *value = strtok_r(NULL, deliminiters, &saveptr);
+ el->type = IMAGE_CFG_DEBUG;
+ el->debug = strtoul(value, NULL, 10);
} else {
fprintf(stderr, "Ignoring unknown line '%s'\n", line);
}
diff --git a/tools/kwbimage.h b/tools/kwbimage.h
index e6e3d1d..01c2f1f 100644
--- a/tools/kwbimage.h
+++ b/tools/kwbimage.h
@@ -73,7 +73,7 @@
/* Structure of the main header, version 1 (Armada 370, Armada XP) */
struct main_hdr_v1 {
uint8_t blockid; /* 0 */
- uint8_t reserved1; /* 1 */
+ uint8_t flags; /* 1 */
uint16_t reserved2; /* 2-3 */
uint32_t blocksize; /* 4-7 */
uint8_t version; /* 8 */
@@ -82,7 +82,7 @@
uint32_t srcaddr; /* C-F */
uint32_t destaddr; /* 10-13 */
uint32_t execaddr; /* 14-17 */
- uint8_t reserved3; /* 18 */
+ uint8_t options; /* 18 */
uint8_t nandblocksize; /* 19 */
uint8_t nandbadblklocation; /* 1A */
uint8_t reserved4; /* 1B */
@@ -92,6 +92,18 @@
};
/*
+ * Main header options
+ */
+#define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
+#define MAIN_HDR_V1_OPT_BAUD_2400 0x1
+#define MAIN_HDR_V1_OPT_BAUD_4800 0x2
+#define MAIN_HDR_V1_OPT_BAUD_9600 0x3
+#define MAIN_HDR_V1_OPT_BAUD_19200 0x4
+#define MAIN_HDR_V1_OPT_BAUD_38400 0x5
+#define MAIN_HDR_V1_OPT_BAUD_57600 0x6
+#define MAIN_HDR_V1_OPT_BAUD_115200 0x7
+
+/*
* Header for the optional headers, version 1 (Armada 370, Armada XP)
*/
struct opt_hdr_v1 {
diff --git a/tools/logos/engicam.bmp b/tools/logos/engicam.bmp
new file mode 100755
index 0000000..f6c60fb
--- /dev/null
+++ b/tools/logos/engicam.bmp
Binary files differ
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 3c594a0..f48135f 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -9,6 +9,7 @@
*/
#include "mkimage.h"
+#include "imximage.h"
#include <image.h>
#include <version.h>
@@ -64,6 +65,7 @@
genimg_get_cat_name(category, item));
}
fprintf(stderr, "\n");
+ free(order);
return 0;
}
@@ -87,12 +89,13 @@
" -x ==> set XIP (execute in place)\n",
params.cmdname);
fprintf(stderr,
- " %s [-D dtc_options] [-f fit-image.its|-f auto|-F] [-b <dtb> [-b <dtb>]] fit-image\n"
- " <dtb> file is used with -f auto, it may occour multiple times.\n",
+ " %s [-D dtc_options] [-f fit-image.its|-f auto|-F] [-b <dtb> [-b <dtb>]] [-i <ramdisk.cpio.gz>] fit-image\n"
+ " <dtb> file is used with -f auto, it may occur multiple times.\n",
params.cmdname);
fprintf(stderr,
" -D => set all options for device tree compiler\n"
- " -f => input filename for FIT source\n");
+ " -f => input filename for FIT source\n"
+ " -i => input filename for ramdisk file\n");
#ifdef CONFIG_FIT_SIGNATURE
fprintf(stderr,
"Signing / verified boot options: [-E] [-k keydir] [-K dtb] [ -c <comment>] [-p addr] [-r]\n"
@@ -140,7 +143,7 @@
int opt;
while ((opt = getopt(argc, argv,
- "a:A:b:c:C:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != -1) {
+ "a:A:b:c:C:d:D:e:Ef:Fk:i:K:ln:p:O:rR:qsT:vVx")) != -1) {
switch (opt) {
case 'a':
params.addr = strtoull(optarg, &ptr, 16);
@@ -206,6 +209,9 @@
params.type = IH_TYPE_FLATDT;
params.fflag = 1;
break;
+ case 'i':
+ params.fit_ramdisk = optarg;
+ break;
case 'k':
params.keydir = optarg;
break;
@@ -503,6 +509,37 @@
} else {
copy_file(ifd, params.datafile, pad_len);
}
+ if (params.type == IH_TYPE_FIRMWARE_IVT) {
+ /* Add alignment and IVT */
+ uint32_t aligned_filesize = (params.file_size + 0x1000
+ - 1) & ~(0x1000 - 1);
+ flash_header_v2_t ivt_header = { { 0xd1, 0x2000, 0x40 },
+ params.addr, 0, 0, 0, params.addr
+ + aligned_filesize
+ - tparams->header_size,
+ params.addr + aligned_filesize
+ - tparams->header_size
+ + 0x20, 0 };
+ int i = params.file_size;
+ for (; i < aligned_filesize; i++) {
+ if (write(ifd, &i, 1) != 1) {
+ fprintf(stderr,
+ "%s: Write error on %s: %s\n",
+ params.cmdname,
+ params.imagefile,
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ }
+ if (write(ifd, &ivt_header, sizeof(flash_header_v2_t))
+ != sizeof(flash_header_v2_t)) {
+ fprintf(stderr, "%s: Write error on %s: %s\n",
+ params.cmdname,
+ params.imagefile,
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ }
}
/* We're a bit of paranoid */
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 9c1c5b7..0f0b003 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -15,7 +15,7 @@
#include <errno.h>
#include <sys/types.h>
#include <sys/stat.h>
-#include "asm/arch/spl.h"
+#include "../arch/arm/include/asm/arch-sunxi/spl.h"
#define STAMP_VALUE 0x5F0A6C39
diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 5576b57..228d098 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -122,8 +122,13 @@
Surround each portion of the log with escape sequences to display it
in color on the terminal.
+ -C, --commit
+ Create a git commit with the changes when the operation is complete. A
+ standard commit message is used which may need to be edited.
+
-d, --defconfigs
- Specify a file containing a list of defconfigs to move
+ Specify a file containing a list of defconfigs to move. The defconfig
+ files can be given with shell-style wildcards.
-n, --dry-run
Perform a trial run that does not make any changes. It is useful to
@@ -162,6 +167,10 @@
-v, --verbose
Show any build errors as boards are built
+ -y, --yes
+ Instead of prompting, automatically go ahead with all operations. This
+ includes cleaning up headers and CONFIG_SYS_EXTRA_OPTIONS.
+
To see the complete list of supported options, run
$ tools/moveconfig.py -h
@@ -172,6 +181,7 @@
import difflib
import filecmp
import fnmatch
+import glob
import multiprocessing
import optparse
import os
@@ -276,6 +286,24 @@
sys.exit('GNU Make not found')
return ret[0].rstrip()
+def get_matched_defconfigs(defconfigs_file):
+ """Get all the defconfig files that match the patterns in a file."""
+ defconfigs = []
+ for i, line in enumerate(open(defconfigs_file)):
+ line = line.strip()
+ if not line:
+ continue # skip blank lines silently
+ pattern = os.path.join('configs', line)
+ matched = glob.glob(pattern) + glob.glob(pattern + '_defconfig')
+ if not matched:
+ print >> sys.stderr, "warning: %s:%d: no defconfig matched '%s'" % \
+ (defconfigs_file, i + 1, line)
+
+ defconfigs += matched
+
+ # use set() to drop multiple matching
+ return [ defconfig[len('configs') + 1:] for defconfig in set(defconfigs) ]
+
def get_all_defconfigs():
"""Get all the defconfig files under the configs/ directory."""
defconfigs = []
@@ -481,14 +509,15 @@
configs: A list of CONFIGs to remove.
options: option flags.
"""
- while True:
- choice = raw_input('Clean up headers? [y/n]: ').lower()
- print choice
- if choice == 'y' or choice == 'n':
- break
+ if not options.yes:
+ while True:
+ choice = raw_input('Clean up headers? [y/n]: ').lower()
+ print choice
+ if choice == 'y' or choice == 'n':
+ break
- if choice == 'n':
- return
+ if choice == 'n':
+ return
patterns = []
for config in configs:
@@ -560,14 +589,16 @@
configs: A list of CONFIGs to remove.
options: option flags.
"""
- while True:
- choice = raw_input('Clean up CONFIG_SYS_EXTRA_OPTIONS? [y/n]: ').lower()
- print choice
- if choice == 'y' or choice == 'n':
- break
+ if not options.yes:
+ while True:
+ choice = (raw_input('Clean up CONFIG_SYS_EXTRA_OPTIONS? [y/n]: ').
+ lower())
+ print choice
+ if choice == 'y' or choice == 'n':
+ break
- if choice == 'n':
- return
+ if choice == 'n':
+ return
configs = [ config[len('CONFIG_'):] for config in configs ]
@@ -1193,13 +1224,7 @@
reference_src_dir = None
if options.defconfigs:
- defconfigs = [line.strip() for line in open(options.defconfigs)]
- for i, defconfig in enumerate(defconfigs):
- if not defconfig.endswith('_defconfig'):
- defconfigs[i] = defconfig + '_defconfig'
- if not os.path.exists(os.path.join('configs', defconfigs[i])):
- sys.exit('%s - defconfig does not exist. Stopping.' %
- defconfigs[i])
+ defconfigs = get_matched_defconfigs(options.defconfigs)
else:
defconfigs = get_all_defconfigs()
@@ -1233,6 +1258,8 @@
# Add options here
parser.add_option('-c', '--color', action='store_true', default=False,
help='display the log in color')
+ parser.add_option('-C', '--commit', action='store_true', default=False,
+ help='Create a git commit for the operation')
parser.add_option('-d', '--defconfigs', type='string',
help='a file containing a list of defconfigs to move')
parser.add_option('-n', '--dry-run', action='store_true', default=False,
@@ -1251,6 +1278,8 @@
help='the number of jobs to run simultaneously')
parser.add_option('-r', '--git-ref', type='string',
help='the git ref to clone for building the autoconf.mk')
+ parser.add_option('-y', '--yes', action='store_true', default=False,
+ help="respond 'yes' to any prompts")
parser.add_option('-v', '--verbose', action='store_true', default=False,
help='show any build errors as boards are built')
parser.usage += ' CONFIG ...'
@@ -1276,5 +1305,17 @@
cleanup_headers(configs, options)
cleanup_extra_options(configs, options)
+ if options.commit:
+ subprocess.call(['git', 'add', '-u'])
+ if configs:
+ msg = 'Convert %s %sto Kconfig' % (configs[0],
+ 'et al ' if len(configs) > 1 else '')
+ msg += ('\n\nThis converts the following to Kconfig:\n %s\n' %
+ '\n '.join(configs))
+ else:
+ msg = 'configs: Resync with savedefconfig'
+ msg += '\n\nRsync all defconfig files using moveconfig.py'
+ subprocess.call(['git', 'commit', '-s', '-m', msg])
+
if __name__ == '__main__':
main()
diff --git a/tools/mxsimage.c b/tools/mxsimage.c
index 98fc644..32a7978 100644
--- a/tools/mxsimage.c
+++ b/tools/mxsimage.c
@@ -22,6 +22,36 @@
#include "pbl_crc32.h"
#include <image.h>
+/*
+ * OpenSSL 1.1.0 and newer compatibility functions:
+ * https://wiki.openssl.org/index.php/1.1_API_Changes
+ */
+#if OPENSSL_VERSION_NUMBER < 0x10100000L
+static void *OPENSSL_zalloc(size_t num)
+{
+ void *ret = OPENSSL_malloc(num);
+
+ if (ret != NULL)
+ memset(ret, 0, num);
+ return ret;
+}
+
+EVP_MD_CTX *EVP_MD_CTX_new(void)
+{
+ return OPENSSL_zalloc(sizeof(EVP_MD_CTX));
+}
+
+void EVP_MD_CTX_free(EVP_MD_CTX *ctx)
+{
+ EVP_MD_CTX_cleanup(ctx);
+ OPENSSL_free(ctx);
+}
+
+int EVP_CIPHER_CTX_reset(EVP_CIPHER_CTX *ctx)
+{
+ return EVP_CIPHER_CTX_cleanup(ctx);
+}
+#endif
/*
* DCD block
@@ -144,8 +174,8 @@
struct sb_dcd_ctx *dcd_head;
struct sb_dcd_ctx *dcd_tail;
- EVP_CIPHER_CTX cipher_ctx;
- EVP_MD_CTX md_ctx;
+ EVP_CIPHER_CTX *cipher_ctx;
+ EVP_MD_CTX *md_ctx;
uint8_t digest[32];
struct sb_key_dictionary_key sb_dict_key;
@@ -173,24 +203,26 @@
*/
static int sb_aes_init(struct sb_image_ctx *ictx, uint8_t *iv, int enc)
{
- EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx;
+ EVP_CIPHER_CTX *ctx;
int ret;
/* If there is no init vector, init vector is all zeroes. */
if (!iv)
iv = ictx->image_key;
- EVP_CIPHER_CTX_init(ctx);
+ ctx = EVP_CIPHER_CTX_new();
ret = EVP_CipherInit(ctx, EVP_aes_128_cbc(), ictx->image_key, iv, enc);
- if (ret == 1)
+ if (ret == 1) {
EVP_CIPHER_CTX_set_padding(ctx, 0);
+ ictx->cipher_ctx = ctx;
+ }
return ret;
}
static int sb_aes_crypt(struct sb_image_ctx *ictx, uint8_t *in_data,
uint8_t *out_data, int in_len)
{
- EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx;
+ EVP_CIPHER_CTX *ctx = ictx->cipher_ctx;
int ret, outlen;
uint8_t *outbuf;
@@ -215,13 +247,13 @@
static int sb_aes_deinit(EVP_CIPHER_CTX *ctx)
{
- return EVP_CIPHER_CTX_cleanup(ctx);
+ return EVP_CIPHER_CTX_reset(ctx);
}
static int sb_aes_reinit(struct sb_image_ctx *ictx, int enc)
{
int ret;
- EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx;
+ EVP_CIPHER_CTX *ctx = ictx->cipher_ctx;
struct sb_boot_image_header *sb_header = &ictx->payload;
uint8_t *iv = sb_header->iv;
@@ -276,7 +308,7 @@
static void sb_encrypt_sb_header(struct sb_image_ctx *ictx)
{
- EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ EVP_MD_CTX *md_ctx = ictx->md_ctx;
struct sb_boot_image_header *sb_header = &ictx->payload;
uint8_t *sb_header_ptr = (uint8_t *)sb_header;
@@ -287,7 +319,7 @@
static void sb_encrypt_sb_sections_header(struct sb_image_ctx *ictx)
{
- EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ EVP_MD_CTX *md_ctx = ictx->md_ctx;
struct sb_section_ctx *sctx = ictx->sect_head;
struct sb_sections_header *shdr;
uint8_t *sb_sections_header_ptr;
@@ -307,7 +339,7 @@
static void sb_encrypt_key_dictionary_key(struct sb_image_ctx *ictx)
{
- EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ EVP_MD_CTX *md_ctx = ictx->md_ctx;
sb_aes_crypt(ictx, ictx->image_key, ictx->sb_dict_key.key,
sizeof(ictx->sb_dict_key.key));
@@ -316,7 +348,7 @@
static void sb_decrypt_key_dictionary_key(struct sb_image_ctx *ictx)
{
- EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ EVP_MD_CTX *md_ctx = ictx->md_ctx;
EVP_DigestUpdate(md_ctx, &ictx->sb_dict_key, sizeof(ictx->sb_dict_key));
sb_aes_crypt(ictx, ictx->sb_dict_key.key, ictx->image_key,
@@ -326,7 +358,7 @@
static void sb_encrypt_tag(struct sb_image_ctx *ictx,
struct sb_cmd_ctx *cctx)
{
- EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ EVP_MD_CTX *md_ctx = ictx->md_ctx;
struct sb_command *cmd = &cctx->payload;
sb_aes_crypt(ictx, (uint8_t *)cmd,
@@ -337,8 +369,8 @@
static int sb_encrypt_image(struct sb_image_ctx *ictx)
{
/* Start image-wide crypto. */
- EVP_MD_CTX_init(&ictx->md_ctx);
- EVP_DigestInit(&ictx->md_ctx, EVP_sha1());
+ ictx->md_ctx = EVP_MD_CTX_new();
+ EVP_DigestInit(ictx->md_ctx, EVP_sha1());
/*
* SB image header.
@@ -379,7 +411,7 @@
} else if (ccmd->header.tag == ROM_LOAD_CMD) {
sb_aes_crypt(ictx, cctx->data, cctx->data,
cctx->length);
- EVP_DigestUpdate(&ictx->md_ctx, cctx->data,
+ EVP_DigestUpdate(ictx->md_ctx, cctx->data,
cctx->length);
}
@@ -394,11 +426,12 @@
*/
sb_aes_reinit(ictx, 1);
- EVP_DigestFinal(&ictx->md_ctx, ictx->digest, NULL);
+ EVP_DigestFinal(ictx->md_ctx, ictx->digest, NULL);
+ EVP_MD_CTX_free(ictx->md_ctx);
sb_aes_crypt(ictx, ictx->digest, ictx->digest, sizeof(ictx->digest));
/* Stop the encryption session. */
- sb_aes_deinit(&ictx->cipher_ctx);
+ sb_aes_deinit(ictx->cipher_ctx);
return 0;
}
@@ -1322,7 +1355,7 @@
struct sb_boot_image_header *hdr = &ictx->payload;
struct sb_section_ctx *sctx = ictx->sect_head;
uint32_t kd_size, sections_blocks;
- EVP_MD_CTX md_ctx;
+ EVP_MD_CTX *md_ctx;
/* The main SB header size in blocks. */
hdr->image_blocks = hdr->header_blocks;
@@ -1359,13 +1392,14 @@
hdr->key_dictionary_block + kd_size / SB_BLOCK_SIZE;
/* Compute header digest. */
- EVP_MD_CTX_init(&md_ctx);
+ md_ctx = EVP_MD_CTX_new();
- EVP_DigestInit(&md_ctx, EVP_sha1());
- EVP_DigestUpdate(&md_ctx, hdr->signature1,
+ EVP_DigestInit(md_ctx, EVP_sha1());
+ EVP_DigestUpdate(md_ctx, hdr->signature1,
sizeof(struct sb_boot_image_header) -
sizeof(hdr->digest));
- EVP_DigestFinal(&md_ctx, hdr->digest, NULL);
+ EVP_DigestFinal(md_ctx, hdr->digest, NULL);
+ EVP_MD_CTX_free(md_ctx);
return 0;
}
@@ -1621,12 +1655,12 @@
struct tm tm;
int sz, ret = 0;
unsigned char digest[20];
- EVP_MD_CTX md_ctx;
+ EVP_MD_CTX *md_ctx;
unsigned long size;
/* Start image-wide crypto. */
- EVP_MD_CTX_init(&ictx->md_ctx);
- EVP_DigestInit(&ictx->md_ctx, EVP_sha1());
+ ictx->md_ctx = EVP_MD_CTX_new();
+ EVP_DigestInit(ictx->md_ctx, EVP_sha1());
soprintf(ictx, "---------- Verifying SB Image Header ----------\n");
@@ -1637,12 +1671,13 @@
}
/* Compute header digest. */
- EVP_MD_CTX_init(&md_ctx);
- EVP_DigestInit(&md_ctx, EVP_sha1());
- EVP_DigestUpdate(&md_ctx, hdr->signature1,
+ md_ctx = EVP_MD_CTX_new();
+ EVP_DigestInit(md_ctx, EVP_sha1());
+ EVP_DigestUpdate(md_ctx, hdr->signature1,
sizeof(struct sb_boot_image_header) -
sizeof(hdr->digest));
- EVP_DigestFinal(&md_ctx, digest, NULL);
+ EVP_DigestFinal(md_ctx, digest, NULL);
+ EVP_MD_CTX_free(md_ctx);
sb_aes_init(ictx, NULL, 1);
sb_encrypt_sb_header(ictx);
@@ -1761,7 +1796,7 @@
static void sb_decrypt_tag(struct sb_image_ctx *ictx,
struct sb_cmd_ctx *cctx)
{
- EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ EVP_MD_CTX *md_ctx = ictx->md_ctx;
struct sb_command *cmd = &cctx->payload;
sb_aes_crypt(ictx, (uint8_t *)&cctx->c_payload,
@@ -1818,7 +1853,7 @@
*tsize += size;
- EVP_DigestUpdate(&ictx->md_ctx, cctx->data, asize);
+ EVP_DigestUpdate(ictx->md_ctx, cctx->data, asize);
sb_aes_crypt(ictx, cctx->data, cctx->data, asize);
if (ccmd->load.crc32 != pbl_crc32(0,
@@ -2007,7 +2042,8 @@
}
/* Check the image digest. */
- EVP_DigestFinal(&ictx->md_ctx, ictx->digest, NULL);
+ EVP_DigestFinal(ictx->md_ctx, ictx->digest, NULL);
+ EVP_MD_CTX_free(ictx->md_ctx);
/* Decrypt the image digest from the input image. */
sb_aes_reinit(ictx, 0);
@@ -2083,7 +2119,7 @@
soprintf(ictx, "Verification %s\n", ret ? "FAILED" : "PASSED");
/* Stop the encryption session. */
- sb_aes_deinit(&ictx->cipher_ctx);
+ sb_aes_deinit(ictx->cipher_ctx);
fclose(fp);
return ret;
diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py
index 34a3bd2..be78fc5 100644
--- a/tools/patman/checkpatch.py
+++ b/tools/patman/checkpatch.py
@@ -63,7 +63,8 @@
result.problems = []
chk = FindCheckPatch()
item = {}
- result.stdout = command.Output(chk, '--no-tree', fname)
+ result.stdout = command.Output(chk, '--no-tree', fname,
+ raise_on_error=False)
#pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE)
#stdout, stderr = pipe.communicate()
@@ -82,7 +83,7 @@
for line in result.stdout.splitlines():
if verbose:
- print line
+ print(line)
# A blank line indicates the end of a message
if not line and item:
@@ -150,17 +151,17 @@
error_count += result.errors
warning_count += result.warnings
check_count += result.checks
- print '%d errors, %d warnings, %d checks for %s:' % (result.errors,
- result.warnings, result.checks, col.Color(col.BLUE, fname))
+ print('%d errors, %d warnings, %d checks for %s:' % (result.errors,
+ result.warnings, result.checks, col.Color(col.BLUE, fname)))
if (len(result.problems) != result.errors + result.warnings +
result.checks):
- print "Internal error: some problems lost"
+ print("Internal error: some problems lost")
for item in result.problems:
- print GetWarningMsg(col, item.get('type', '<unknown>'),
+ print(GetWarningMsg(col, item.get('type', '<unknown>'),
item.get('file', '<unknown>'),
- item.get('line', 0), item.get('msg', 'message'))
+ item.get('line', 0), item.get('msg', 'message')))
print
- #print stdout
+ #print(stdout)
if error_count or warning_count or check_count:
str = 'checkpatch.pl found %d error(s), %d warning(s), %d checks(s)'
color = col.GREEN
@@ -168,6 +169,6 @@
color = col.YELLOW
if error_count:
color = col.RED
- print col.Color(color, str % (error_count, warning_count, check_count))
+ print(col.Color(color, str % (error_count, warning_count, check_count)))
return False
return True
diff --git a/tools/patman/command.py b/tools/patman/command.py
index d586f11..bebc495 100644
--- a/tools/patman/command.py
+++ b/tools/patman/command.py
@@ -85,7 +85,7 @@
try:
last_pipe = cros_subprocess.Popen(cmd, cwd=cwd, **kwargs)
- except Exception, err:
+ except Exception as err:
result.exception = err
if raise_on_error:
raise Exception("Error running '%s': %s" % (user_pipestr, str))
@@ -104,8 +104,9 @@
raise Exception("Error running '%s'" % user_pipestr)
return result
-def Output(*cmd):
- return RunPipe([cmd], capture=True, raise_on_error=False).stdout
+def Output(*cmd, **kwargs):
+ raise_on_error = kwargs.get('raise_on_error', True)
+ return RunPipe([cmd], capture=True, raise_on_error=raise_on_error).stdout
def OutputOneLine(*cmd, **kwargs):
raise_on_error = kwargs.pop('raise_on_error', True)
diff --git a/tools/patman/cros_subprocess.py b/tools/patman/cros_subprocess.py
index 0fc4a06..ebd4300 100644
--- a/tools/patman/cros_subprocess.py
+++ b/tools/patman/cros_subprocess.py
@@ -166,7 +166,7 @@
while read_set or write_set:
try:
rlist, wlist, _ = select.select(read_set, write_set, [], 0.2)
- except select.error, e:
+ except select.error as e:
if e.args[0] == errno.EINTR:
continue
raise
diff --git a/tools/patman/get_maintainer.py b/tools/patman/get_maintainer.py
index 00b4939..2deb5db 100644
--- a/tools/patman/get_maintainer.py
+++ b/tools/patman/get_maintainer.py
@@ -40,7 +40,7 @@
get_maintainer = FindGetMaintainer()
if not get_maintainer:
if verbose:
- print "WARNING: Couldn't find get_maintainer.pl"
+ print("WARNING: Couldn't find get_maintainer.pl")
return []
stdout = command.Output(get_maintainer, '--norolestats', fname)
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index e088bae..0d23079 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -139,7 +139,7 @@
leaf = merge.split('/')[-1]
return '%s/%s' % (remote, leaf), None
else:
- raise ValueError, ("Cannot determine upstream branch for branch "
+ raise ValueError("Cannot determine upstream branch for branch "
"'%s' remote='%s', merge='%s'" % (branch, remote, merge))
@@ -224,7 +224,7 @@
result = command.RunPipe([pipe], capture=True, raise_on_error=False,
capture_stderr=True)
if result.return_code != 0:
- raise OSError, 'git checkout (%s): %s' % (pipe, result.stderr)
+ raise OSError('git checkout (%s): %s' % (pipe, result.stderr))
def Clone(git_dir, output_dir):
"""Checkout the selected commit for this build
@@ -236,7 +236,7 @@
result = command.RunPipe([pipe], capture=True, cwd=output_dir,
capture_stderr=True)
if result.return_code != 0:
- raise OSError, 'git clone: %s' % result.stderr
+ raise OSError('git clone: %s' % result.stderr)
def Fetch(git_dir=None, work_tree=None):
"""Fetch from the origin repo
@@ -252,7 +252,7 @@
pipe.append('fetch')
result = command.RunPipe([pipe], capture=True, capture_stderr=True)
if result.return_code != 0:
- raise OSError, 'git fetch: %s' % result.stderr
+ raise OSError('git fetch: %s' % result.stderr)
def CreatePatches(start, count, series):
"""Create a series of patches from the top of the current branch.
@@ -391,7 +391,8 @@
"""
to = BuildEmailList(series.get('to'), '--to', alias, raise_on_error)
if not to:
- git_config_to = command.Output('git', 'config', 'sendemail.to')
+ git_config_to = command.Output('git', 'config', 'sendemail.to',
+ raise_on_error=False)
if not git_config_to:
print ("No recipient.\n"
"Please add something like this to a commit\n"
@@ -488,18 +489,18 @@
if level > 10:
msg = "Recursive email alias at '%s'" % lookup_name
if raise_on_error:
- raise OSError, msg
+ raise OSError(msg)
else:
- print col.Color(col.RED, msg)
+ print(col.Color(col.RED, msg))
return out_list
if lookup_name:
if not lookup_name in alias:
msg = "Alias '%s' not found" % lookup_name
if raise_on_error:
- raise ValueError, msg
+ raise ValueError(msg)
else:
- print col.Color(col.RED, msg)
+ print(col.Color(col.RED, msg))
return out_list
for item in alias[lookup_name]:
todo = LookupEmail(item, alias, raise_on_error, level + 1)
@@ -507,7 +508,7 @@
if not new_item in out_list:
out_list.append(new_item)
- #print "No match for alias '%s'" % lookup_name
+ #print("No match for alias '%s'" % lookup_name)
return out_list
def GetTopLevel():
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 69d5cfb..cd4667f 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -480,12 +480,12 @@
commit.patch = fname
result = FixPatch(backup_dir, fname, series, commit)
if result:
- print '%d warnings for %s:' % (len(result), fname)
+ print('%d warnings for %s:' % (len(result), fname))
for warn in result:
- print '\t', warn
+ print('\t', warn)
print
count += 1
- print 'Cleaned %d patches' % count
+ print('Cleaned %d patches' % count)
return series
def InsertCoverLetter(fname, series, count):
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index fe50eb4..fdbee67 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -93,11 +93,11 @@
suite.run(result)
# TODO: Surely we can just 'print' result?
- print result
+ print(result)
for test, err in result.errors:
- print err
+ print(err)
for test, err in result.failures:
- print err
+ print(err)
# Called from git with a patch filename as argument
# Printout a list of additional CC recipients for this patch
@@ -110,7 +110,7 @@
for cc in match.group(2).split(', '):
cc = cc.strip()
if cc:
- print cc
+ print(cc)
fd.close()
elif options.full_help:
@@ -166,12 +166,12 @@
options.dry_run, not options.ignore_bad_tags, cc_file,
in_reply_to=options.in_reply_to, thread=options.thread)
else:
- print col.Color(col.RED, "Not sending emails due to errors/warnings")
+ print(col.Color(col.RED, "Not sending emails due to errors/warnings"))
# For a dry run, just show our actions as a sanity check
if options.dry_run:
series.ShowActions(args, cmd, options.process_tags)
if not its_a_go:
- print col.Color(col.RED, "Email would not be sent")
+ print(col.Color(col.RED, "Email would not be sent"))
os.remove(cc_file)
diff --git a/tools/patman/series.py b/tools/patman/series.py
index cc6f80b..38a452e 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -3,6 +3,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
+from __future__ import print_function
+
import itertools
import os
@@ -101,38 +103,38 @@
cc_set = set(gitutil.BuildEmailList(self.cc));
col = terminal.Color()
- print 'Dry run, so not doing much. But I would do this:'
- print
- print 'Send a total of %d patch%s with %scover letter.' % (
+ print('Dry run, so not doing much. But I would do this:')
+ print()
+ print('Send a total of %d patch%s with %scover letter.' % (
len(args), '' if len(args) == 1 else 'es',
- self.get('cover') and 'a ' or 'no ')
+ self.get('cover') and 'a ' or 'no '))
# TODO: Colour the patches according to whether they passed checks
for upto in range(len(args)):
commit = self.commits[upto]
- print col.Color(col.GREEN, ' %s' % args[upto])
+ print(col.Color(col.GREEN, ' %s' % args[upto]))
cc_list = list(self._generated_cc[commit.patch])
for email in set(cc_list) - to_set - cc_set:
if email == None:
email = col.Color(col.YELLOW, "<alias '%s' not found>"
% tag)
if email:
- print ' Cc: ',email
+ print(' Cc: ', email)
print
for item in to_set:
- print 'To:\t ', item
+ print('To:\t ', item)
for item in cc_set - to_set:
- print 'Cc:\t ', item
- print 'Version: ', self.get('version')
- print 'Prefix:\t ', self.get('prefix')
+ print('Cc:\t ', item)
+ print('Version: ', self.get('version'))
+ print('Prefix:\t ', self.get('prefix'))
if self.cover:
- print 'Cover: %d lines' % len(self.cover)
+ print('Cover: %d lines' % len(self.cover))
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
all_ccs = itertools.chain(cover_cc, *self._generated_cc.values())
for email in set(all_ccs) - to_set - cc_set:
- print ' Cc: ',email
+ print(' Cc: ', email)
if cmd:
- print 'Git command: %s' % cmd
+ print('Git command: %s' % cmd)
def MakeChangeLog(self, commit):
"""Create a list of changes for each version.
@@ -191,13 +193,13 @@
else:
if version > 1:
str = 'Change log missing for v%d' % version
- print col.Color(col.RED, str)
+ print(col.Color(col.RED, str))
for version in changes_copy:
str = 'Change log for unknown version v%d' % version
- print col.Color(col.RED, str)
+ print(col.Color(col.RED, str))
elif self.changes:
str = 'Change log exists, but no version is set'
- print col.Color(col.RED, str)
+ print(col.Color(col.RED, str))
def MakeCcFile(self, process_tags, cover_fname, raise_on_error,
add_maintainers):
@@ -225,15 +227,15 @@
raise_on_error=raise_on_error)
list += gitutil.BuildEmailList(commit.cc_list,
raise_on_error=raise_on_error)
- if add_maintainers:
+ if add_maintainers:
list += get_maintainer.GetMaintainer(commit.patch)
all_ccs += list
- print >>fd, commit.patch, ', '.join(set(list))
+ print(commit.patch, ', '.join(set(list)), file=fd)
self._generated_cc[commit.patch] = list
if cover_fname:
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
- print >>fd, cover_fname, ', '.join(set(cover_cc + all_ccs))
+ print(cover_fname, ', '.join(set(cover_cc + all_ccs)), file=fd)
fd.close()
return fname
@@ -259,7 +261,7 @@
"""
git_prefix = gitutil.GetDefaultSubjectPrefix()
if git_prefix:
- git_prefix = '%s][' % git_prefix
+ git_prefix = '%s][' % git_prefix
else:
git_prefix = ''
diff --git a/tools/patman/settings.py b/tools/patman/settings.py
index ba2a68f..5f207f5 100644
--- a/tools/patman/settings.py
+++ b/tools/patman/settings.py
@@ -3,7 +3,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
-import ConfigParser
+from __future__ import print_function
+
+try:
+ import configparser as ConfigParser
+except:
+ import ConfigParser
+
import os
import re
@@ -30,7 +36,10 @@
- Merge general default settings/aliases with project-specific ones.
# Sample config used for tests below...
- >>> import StringIO
+ >>> try:
+ ... from StringIO import StringIO
+ ... except ImportError:
+ ... from io import StringIO
>>> sample_config = '''
... [alias]
... me: Peter P. <likesspiders@example.com>
@@ -48,25 +57,25 @@
# Check to make sure that bogus project gets general alias.
>>> config = _ProjectConfigParser("zzz")
- >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.readfp(StringIO(sample_config))
>>> config.get("alias", "enemies")
'Evil <evil@example.com>'
# Check to make sure that alias gets overridden by project.
>>> config = _ProjectConfigParser("sm")
- >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.readfp(StringIO(sample_config))
>>> config.get("alias", "enemies")
'Green G. <ugly@example.com>'
# Check to make sure that settings get merged with project.
>>> config = _ProjectConfigParser("linux")
- >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.readfp(StringIO(sample_config))
>>> sorted(config.items("settings"))
[('am_hero', 'True'), ('process_tags', 'False')]
# Check to make sure that settings works with unknown project.
>>> config = _ProjectConfigParser("unknown")
- >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.readfp(StringIO(sample_config))
>>> sorted(config.items("settings"))
[('am_hero', 'True')]
"""
@@ -88,7 +97,7 @@
if not self.has_section(project_settings):
self.add_section(project_settings)
project_defaults = _default_settings.get(project_name, {})
- for setting_name, setting_value in project_defaults.iteritems():
+ for setting_name, setting_value in project_defaults.items():
self.set(project_settings, setting_name, setting_value)
def get(self, section, option, *args, **kwargs):
@@ -156,7 +165,7 @@
try:
fd = open(fname, 'r')
except IOError:
- print "Warning: Cannot find alias file '%s'" % fname
+ print("Warning: Cannot find alias file '%s'" % fname)
return
re_line = re.compile('alias\s+(\S+)\s+(.*)')
@@ -167,7 +176,7 @@
m = re_line.match(line)
if not m:
- print "Warning: Alias file line '%s' not understood" % line
+ print("Warning: Alias file line '%s' not understood" % line)
continue
list = alias.get(m.group(1), [])
@@ -200,10 +209,10 @@
try:
f = open(config_fname, 'w')
except IOError:
- print "Couldn't create patman config file\n"
+ print("Couldn't create patman config file\n")
raise
- print >>f, "[alias]\nme: %s <%s>" % (name, email)
+ print("[alias]\nme: %s <%s>" % (name, email), file=f)
f.close();
def _UpdateDefaults(parser, config):
@@ -233,7 +242,7 @@
val = config.getint('settings', name)
parser.set_default(name, val)
else:
- print "WARNING: Unknown setting %s" % name
+ print("WARNING: Unknown setting %s" % name)
def _ReadAliasFile(fname):
"""Read in the U-Boot git alias file if it exists.
@@ -258,7 +267,7 @@
continue
alias[words[1]] = [s.strip() for s in words[2].split(',')]
if bad_line:
- print bad_line
+ print(bad_line)
def Setup(parser, project_name, config_fname=''):
"""Set up the settings module by reading config files.
@@ -276,7 +285,7 @@
config_fname = '%s/.patman' % os.getenv('HOME')
if not os.path.exists(config_fname):
- print "No config file found ~/.patman\nCreating one...\n"
+ print("No config file found ~/.patman\nCreating one...\n")
CreatePatmanConfigFile(config_fname)
config.read(config_fname)
diff --git a/tools/patman/terminal.py b/tools/patman/terminal.py
index e78a7c1..137265f 100644
--- a/tools/patman/terminal.py
+++ b/tools/patman/terminal.py
@@ -8,6 +8,8 @@
This module handles terminal interaction including ANSI color codes.
"""
+from __future__ import print_function
+
import os
import sys
@@ -52,9 +54,11 @@
if colour:
col = Color()
text = col.Color(colour, text)
- print text,
+ print(text, end='')
if newline:
- print
+ print()
+ else:
+ sys.stdout.flush()
def SetPrintTestMode():
"""Go into test mode, where all printing is recorded"""
@@ -79,11 +83,11 @@
for line in print_test_list:
if line.colour:
col = Color()
- print col.Color(line.colour, line.text),
+ print(col.Color(line.colour, line.text), end='')
else:
- print line.text,
+ print(line.text, end='')
if line.newline:
- print
+ print()
class Color(object):
diff --git a/tools/patman/test.py b/tools/patman/test.py
index e8f7472..8c39f66 100644
--- a/tools/patman/test.py
+++ b/tools/patman/test.py
@@ -181,7 +181,7 @@
elif data_type == 'indent':
indent = tab
else:
- print 'not implemented'
+ print('not implemented')
return data % (signoff, tab, indent, tab)
def SetupData(self, data_type):
diff --git a/tools/patman/tools.py b/tools/patman/tools.py
new file mode 100644
index 0000000..ba24853
--- /dev/null
+++ b/tools/patman/tools.py
@@ -0,0 +1,120 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+import os
+import shutil
+import tempfile
+
+import tout
+
+outdir = None
+indirs = None
+preserve_outdir = False
+
+def PrepareOutputDir(dirname, preserve=False):
+ """Select an output directory, ensuring it exists.
+
+ This either creates a temporary directory or checks that the one supplied
+ by the user is valid. For a temporary directory, it makes a note to
+ remove it later if required.
+
+ Args:
+ dirname: a string, name of the output directory to use to store
+ intermediate and output files. If is None - create a temporary
+ directory.
+ preserve: a Boolean. If outdir above is None and preserve is False, the
+ created temporary directory will be destroyed on exit.
+
+ Raises:
+ OSError: If it cannot create the output directory.
+ """
+ global outdir, preserve_outdir
+
+ preserve_outdir = dirname or preserve
+ if dirname:
+ outdir = dirname
+ if not os.path.isdir(outdir):
+ try:
+ os.makedirs(outdir)
+ except OSError as err:
+ raise CmdError("Cannot make output directory '%s': '%s'" %
+ (outdir, err.strerror))
+ tout.Debug("Using output directory '%s'" % outdir)
+ else:
+ outdir = tempfile.mkdtemp(prefix='binman.')
+ tout.Debug("Using temporary directory '%s'" % outdir)
+
+def _RemoveOutputDir():
+ global outdir
+
+ shutil.rmtree(outdir)
+ tout.Debug("Deleted temporary directory '%s'" % outdir)
+ outdir = None
+
+def FinaliseOutputDir():
+ global outdir, preserve_outdir
+
+ """Tidy up: delete output directory if temporary and not preserved."""
+ if outdir and not preserve_outdir:
+ _RemoveOutputDir()
+
+def GetOutputFilename(fname):
+ """Return a filename within the output directory.
+
+ Args:
+ fname: Filename to use for new file
+
+ Returns:
+ The full path of the filename, within the output directory
+ """
+ return os.path.join(outdir, fname)
+
+def _FinaliseForTest():
+ """Remove the output directory (for use by tests)"""
+ global outdir
+
+ if outdir:
+ _RemoveOutputDir()
+
+def SetInputDirs(dirname):
+ """Add a list of input directories, where input files are kept.
+
+ Args:
+ dirname: a list of paths to input directories to use for obtaining
+ files needed by binman to place in the image.
+ """
+ global indir
+
+ indir = dirname
+ tout.Debug("Using input directories %s" % indir)
+
+def GetInputFilename(fname):
+ """Return a filename for use as input.
+
+ Args:
+ fname: Filename to use for new file
+
+ Returns:
+ The full path of the filename, within the input directory
+ """
+ if not indir:
+ return fname
+ for dirname in indir:
+ pathname = os.path.join(dirname, fname)
+ if os.path.exists(pathname):
+ return pathname
+
+ raise ValueError("Filename '%s' not found in input path (%s)" %
+ (fname, ','.join(indir)))
+
+def Align(pos, align):
+ if align:
+ mask = align - 1
+ pos = (pos + mask) & ~mask
+ return pos
+
+def NotPowerOfTwo(num):
+ return num and (num & (num - 1))
diff --git a/tools/patman/tout.py b/tools/patman/tout.py
new file mode 100644
index 0000000..c5fbd80
--- /dev/null
+++ b/tools/patman/tout.py
@@ -0,0 +1,166 @@
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Terminal output logging.
+#
+
+import sys
+
+import terminal
+
+# Output verbosity levels that we support
+ERROR = 0
+WARNING = 1
+NOTICE = 2
+INFO = 3
+DEBUG = 4
+
+"""
+This class handles output of progress and other useful information
+to the user. It provides for simple verbosity level control and can
+output nothing but errors at verbosity zero.
+
+The idea is that modules set up an Output object early in their years and pass
+it around to other modules that need it. This keeps the output under control
+of a single class.
+
+Public properties:
+ verbose: Verbosity level: 0=silent, 1=progress, 3=full, 4=debug
+"""
+def __enter__():
+ return
+
+def __exit__(unused1, unused2, unused3):
+ """Clean up and remove any progress message."""
+ ClearProgress()
+ return False
+
+def UserIsPresent():
+ """This returns True if it is likely that a user is present.
+
+ Sometimes we want to prompt the user, but if no one is there then this
+ is a waste of time, and may lock a script which should otherwise fail.
+
+ Returns:
+ True if it thinks the user is there, and False otherwise
+ """
+ return stdout_is_tty and verbose > 0
+
+def ClearProgress():
+ """Clear any active progress message on the terminal."""
+ if verbose > 0 and stdout_is_tty:
+ _stdout.write('\r%s\r' % (" " * len (_progress)))
+ _stdout.flush()
+
+def Progress(msg, warning=False, trailer='...'):
+ """Display progress information.
+
+ Args:
+ msg: Message to display.
+ warning: True if this is a warning."""
+ ClearProgress()
+ if verbose > 0:
+ _progress = msg + trailer
+ if stdout_is_tty:
+ col = _color.YELLOW if warning else _color.GREEN
+ _stdout.write('\r' + _color.Color(col, _progress))
+ _stdout.flush()
+ else:
+ _stdout.write(_progress + '\n')
+
+def _Output(level, msg, color=None):
+ """Output a message to the terminal.
+
+ Args:
+ level: Verbosity level for this message. It will only be displayed if
+ this as high as the currently selected level.
+ msg; Message to display.
+ error: True if this is an error message, else False.
+ """
+ if verbose >= level:
+ ClearProgress()
+ if color:
+ msg = _color.Color(color, msg)
+ _stdout.write(msg + '\n')
+
+def DoOutput(level, msg):
+ """Output a message to the terminal.
+
+ Args:
+ level: Verbosity level for this message. It will only be displayed if
+ this as high as the currently selected level.
+ msg; Message to display.
+ """
+ _Output(level, msg)
+
+def Error(msg):
+ """Display an error message
+
+ Args:
+ msg; Message to display.
+ """
+ _Output(0, msg, _color.RED)
+
+def Warning(msg):
+ """Display a warning message
+
+ Args:
+ msg; Message to display.
+ """
+ _Output(1, msg, _color.YELLOW)
+
+def Notice(msg):
+ """Display an important infomation message
+
+ Args:
+ msg; Message to display.
+ """
+ _Output(2, msg)
+
+def Info(msg):
+ """Display an infomation message
+
+ Args:
+ msg; Message to display.
+ """
+ _Output(3, msg)
+
+def Debug(msg):
+ """Display a debug message
+
+ Args:
+ msg; Message to display.
+ """
+ _Output(4, msg)
+
+def UserOutput(msg):
+ """Display a message regardless of the current output level.
+
+ This is used when the output was specifically requested by the user.
+ Args:
+ msg; Message to display.
+ """
+ _Output(0, msg)
+
+def Init(_verbose=WARNING, stdout=sys.stdout):
+ """Initialize a new output object.
+
+ Args:
+ verbose: Verbosity level (0-4).
+ stdout: File to use for stdout.
+ """
+ global verbose, _progress, _color, _stdout, stdout_is_tty
+
+ verbose = _verbose
+ _progress = '' # Our last progress message
+ _color = terminal.Color()
+ _stdout = stdout
+
+ # TODO(sjg): Move this into Chromite libraries when we have them
+ stdout_is_tty = hasattr(sys.stdout, 'isatty') and sys.stdout.isatty()
+
+def Uninit():
+ ClearProgress()
+
+Init()
diff --git a/tools/pblimage.c b/tools/pblimage.c
index d74fde9..16d94c98 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -297,7 +297,7 @@
pbi_crc_cmd1 = 0x13;
pbi_crc_cmd2 = 0x80;
pbl_cmd_initaddr = 0x82000000;
- pbl_end_cmd[0] = 0x09138000;
+ pbl_end_cmd[0] = 0x091380c0;
pbl_end_cmd[1] = 0x00000000;
pbl_end_cmd[2] = 0x091380c0;
pbl_end_cmd[3] = 0x00000000;
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 670b9fd..3c9d134 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -15,6 +15,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include "compiler.h"
#ifndef R_AARCH64_RELATIVE
#define R_AARCH64_RELATIVE 1027
@@ -50,40 +51,6 @@
}
}
-static inline uint64_t swap64(uint64_t val)
-{
- return ((val >> 56) & 0x00000000000000ffULL) |
- ((val >> 40) & 0x000000000000ff00ULL) |
- ((val >> 24) & 0x0000000000ff0000ULL) |
- ((val >> 8) & 0x00000000ff000000ULL) |
- ((val << 8) & 0x000000ff00000000ULL) |
- ((val << 24) & 0x0000ff0000000000ULL) |
- ((val << 40) & 0x00ff000000000000ULL) |
- ((val << 56) & 0xff00000000000000ULL);
-}
-
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-static inline uint64_t be64(uint64_t val)
-{
- return swap64(val);
-}
-
-static inline uint64_t le64(uint64_t val)
-{
- return val;
-}
-#else
-static inline uint64_t le64(uint64_t val)
-{
- return swap64(val);
-}
-
-static inline uint64_t be64(uint64_t val)
-{
- return val;
-}
-#endif
-
static bool read_num(const char *str, uint64_t *num)
{
char *endptr;
@@ -148,9 +115,9 @@
return 4;
}
- swrela.r_offset = le64(rela.r_offset);
- swrela.r_info = le64(rela.r_info);
- swrela.r_addend = le64(rela.r_addend);
+ swrela.r_offset = cpu_to_le64(rela.r_offset);
+ swrela.r_info = cpu_to_le64(rela.r_info);
+ swrela.r_addend = cpu_to_le64(rela.r_addend);
if (!supported_rela(&swrela))
continue;
diff --git a/tools/vybridimage.c b/tools/vybridimage.c
new file mode 100644
index 0000000..a31fc10
--- /dev/null
+++ b/tools/vybridimage.c
@@ -0,0 +1,164 @@
+/*
+ * Image manipulator for Vybrid SoCs
+ *
+ * Derived from vybridimage.c
+ *
+ * (C) Copyright 2016 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "imagetool.h"
+#include <compiler.h>
+#include <image.h>
+
+/*
+ * NAND page 0 boot header
+ */
+
+struct nand_page_0_boot_header {
+ union {
+ uint32_t fcb[128];
+ uint8_t fcb_bytes[512];
+ }; /* 0x00000000 - 0x000001ff */
+ uint8_t sw_ecc[512]; /* 0x00000200 - 0x000003ff */
+ uint32_t padding[65280]; /* 0x00000400 - 0x0003ffff */
+ uint8_t ivt_prefix[1024]; /* 0x00040000 - 0x000403ff */
+};
+
+/* signature byte for a readable block */
+
+static struct nand_page_0_boot_header vybridimage_header;
+
+static int vybridimage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_VYBRIDIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static uint8_t vybridimage_sw_ecc(uint8_t byte)
+{
+ uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0;
+ uint8_t bit1 = (byte & (1 << 1)) ? 1 : 0;
+ uint8_t bit2 = (byte & (1 << 2)) ? 1 : 0;
+ uint8_t bit3 = (byte & (1 << 3)) ? 1 : 0;
+ uint8_t bit4 = (byte & (1 << 4)) ? 1 : 0;
+ uint8_t bit5 = (byte & (1 << 5)) ? 1 : 0;
+ uint8_t bit6 = (byte & (1 << 6)) ? 1 : 0;
+ uint8_t bit7 = (byte & (1 << 7)) ? 1 : 0;
+ uint8_t res = 0;
+
+ res |= ((bit6 ^ bit5 ^ bit3 ^ bit2) << 0);
+ res |= ((bit7 ^ bit5 ^ bit4 ^ bit2 ^ bit1) << 1);
+ res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2);
+ res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3);
+ res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4);
+
+ return res;
+}
+
+static int vybridimage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+ int idx;
+
+ if (hdr->fcb[1] != 0x46434220)
+ return -1;
+ if (hdr->fcb[2] != 1)
+ return -1;
+ if (hdr->fcb[7] != 64)
+ return -1;
+ if (hdr->fcb[14] != 6)
+ return -1;
+ if (hdr->fcb[30] != 0x0001ff00)
+ return -1;
+ if (hdr->fcb[43] != 1)
+ return -1;
+ if (hdr->fcb[54] != 0)
+ return -1;
+ if (hdr->fcb[55] != 8)
+ return -1;
+
+ /* check software ECC */
+ for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++) {
+ uint8_t sw_ecc = vybridimage_sw_ecc(hdr->fcb_bytes[idx]);
+ if (sw_ecc != hdr->sw_ecc[idx])
+ return -1;
+ }
+
+ return 0;
+}
+
+static void vybridimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+ int idx;
+
+ /* fill header with 0x00 for first 56 entries then 0xff */
+ memset(&hdr->fcb[0], 0x0, 56*sizeof(uint32_t));
+ memset(&hdr->fcb[56], 0xff, 72*sizeof(uint32_t));
+ /* fill SW ecc and padding with 0xff */
+ memset(&hdr->sw_ecc[0], 0xff, sizeof(hdr->sw_ecc));
+ memset(&hdr->padding[0], 0xff, sizeof(hdr->padding));
+ /* fill IVT prefix with 0x00 */
+ memset(&hdr->ivt_prefix[0], 0x00, sizeof(hdr->ivt_prefix));
+
+ /* populate fcb */
+ hdr->fcb[1] = 0x46434220; /* signature */
+ hdr->fcb[2] = 0x00000001; /* version */
+ hdr->fcb[5] = 2048; /* page size */
+ hdr->fcb[6] = (2048+64); /* page + OOB size */
+ hdr->fcb[7] = 64; /* pages per block */
+ hdr->fcb[14] = 6; /* ECC mode 6 */
+ hdr->fcb[26] = 128; /* fw address (0x40000) in 2K pages */
+ hdr->fcb[27] = 128; /* fw address (0x40000) in 2K pages */
+ hdr->fcb[30] = 0x0001ff00; /* DBBT search area start address */
+ hdr->fcb[33] = 2048; /* BB marker physical offset */
+ hdr->fcb[43] = 1; /* DISBBM */
+ hdr->fcb[54] = 0; /* DISBB_Search */
+ hdr->fcb[55] = 8; /* Bad block search limit */
+
+ /* compute software ECC */
+ for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++)
+ hdr->sw_ecc[idx] = vybridimage_sw_ecc(hdr->fcb_bytes[idx]);
+}
+
+static void vybridimage_print_hdr_field(struct nand_page_0_boot_header *hdr,
+ int idx)
+{
+ printf("header.fcb[%d] = %08x\n", idx, hdr->fcb[idx]);
+}
+
+static void vybridimage_print_header(const void *ptr)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+ int idx;
+
+ for (idx = 0; idx < 56; idx++)
+ vybridimage_print_hdr_field(hdr, idx);
+}
+
+/*
+ * vybridimage parameters
+ */
+U_BOOT_IMAGE_TYPE(
+ vybridimage,
+ "Vybrid Boot Image",
+ sizeof(vybridimage_header),
+ (void *)&vybridimage_header,
+ NULL,
+ vybridimage_verify_header,
+ vybridimage_print_header,
+ vybridimage_set_header,
+ NULL,
+ vybridimage_check_image_types,
+ NULL,
+ NULL
+);
diff --git a/tools/zynqimage.c b/tools/zynqimage.c
index c43bd5d..021d2d3 100644
--- a/tools/zynqimage.c
+++ b/tools/zynqimage.c
@@ -222,6 +222,44 @@
return EXIT_FAILURE;
}
+static void zynqimage_parse_initparams(struct zynq_header *zynqhdr,
+ const char *filename)
+{
+ FILE *fp;
+ struct zynq_reginit reginit;
+ unsigned int reg_count = 0;
+ int r, err;
+ struct stat path_stat;
+
+ /* Expect a table of register-value pairs, e.g. "0x12345678 0x4321" */
+ fp = fopen(filename, "r");
+ if (!fp) {
+ fprintf(stderr, "Cannot open initparams file: %s\n", filename);
+ exit(1);
+ }
+
+ err = fstat(fileno(fp), &path_stat);
+ if (err) {
+ fclose(fp);
+ return;
+ }
+
+ if (!S_ISREG(path_stat.st_mode)) {
+ fclose(fp);
+ return;
+ }
+
+ do {
+ r = fscanf(fp, "%x %x", ®init.address, ®init.data);
+ if (r == 2) {
+ zynqhdr->register_init[reg_count] = reginit;
+ ++reg_count;
+ }
+ r = fscanf(fp, "%*[^\n]\n"); /* Skip to next line */
+ } while ((r != EOF) && (reg_count < HEADER_REGINITS));
+ fclose(fp);
+}
+
static void zynqimage_set_header(void *ptr, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
@@ -237,6 +275,10 @@
if (params->eflag)
zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
+ /* User can pass in text file with init list */
+ if (strlen(params->imagename2))
+ zynqimage_parse_initparams(zynqhdr, params->imagename2);
+
zynqhdr->checksum = zynqimage_checksum(zynqhdr);
}
diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
index 3f28eb4..0c9a3da 100644
--- a/tools/zynqmpimage.c
+++ b/tools/zynqmpimage.c
@@ -234,6 +234,44 @@
return EXIT_FAILURE;
}
+static void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr,
+ const char *filename)
+{
+ FILE *fp;
+ struct zynqmp_reginit reginit;
+ unsigned int reg_count = 0;
+ int r, err;
+ struct stat path_stat;
+
+ /* Expect a table of register-value pairs, e.g. "0x12345678 0x4321" */
+ fp = fopen(filename, "r");
+ if (!fp) {
+ fprintf(stderr, "Cannot open initparams file: %s\n", filename);
+ exit(1);
+ }
+
+ err = fstat(fileno(fp), &path_stat);
+ if (err) {
+ fclose(fp);
+ return;
+ }
+
+ if (!S_ISREG(path_stat.st_mode)) {
+ fclose(fp);
+ return;
+ }
+
+ do {
+ r = fscanf(fp, "%x %x", ®init.address, ®init.data);
+ if (r == 2) {
+ zynqhdr->register_init[reg_count] = reginit;
+ ++reg_count;
+ }
+ r = fscanf(fp, "%*[^\n]\n"); /* Skip to next line */
+ } while ((r != EOF) && (reg_count < HEADER_REGINITS));
+ fclose(fp);
+}
+
static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
@@ -250,6 +288,10 @@
if (params->eflag)
zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
+ /* User can pass in text file with init list */
+ if (strlen(params->imagename2))
+ zynqmpimage_parse_initparams(zynqhdr, params->imagename2);
+
zynqhdr->checksum = zynqmpimage_checksum(zynqhdr);
}
