commit 10be706778bd670197a66765c550cbb3a0cfda6d
author Marek Olšák <marek.olsak@amd.com> Wed Sep 16 01:11:31 2020 -0400
committer Marek Olšák <marek.olsak@amd.com> Fri Sep 25 02:29:30 2020 -0400
tree 33d431b4339c86cc2a751f7bfabffb1859eb5408
parent 3173367a478217d2cee3400805756393a02d3dd1

nir: gather indirect info from lowered IO intrinsics

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6758>

src/compiler/nir/nir_gather_info.c

diff --git a/src/compiler/nir/nir_gather_info.c b/src/compiler/nir/nir_gather_info.c
index 03f0d15..eacaed0 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -354,38 +354,47 @@
    }
 
    case nir_intrinsic_load_input:
-      if (shader->info.stage == MESA_SHADER_TESS_EVAL)
-         shader->info.patch_inputs_read |= slot_mask;
-      else
-         shader->info.inputs_read |= slot_mask;
-      break;
-
    case nir_intrinsic_load_per_vertex_input:
    case nir_intrinsic_load_input_vertex:
    case nir_intrinsic_load_interpolated_input:
-      shader->info.inputs_read |= slot_mask;
+      if (shader->info.stage == MESA_SHADER_TESS_EVAL &&
+          instr->intrinsic == nir_intrinsic_load_input) {
+         shader->info.patch_inputs_read |= slot_mask;
+         if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
+            shader->info.patch_inputs_read_indirectly |= slot_mask;
+      } else {
+         shader->info.inputs_read |= slot_mask;
+         if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
+            shader->info.inputs_read_indirectly |= slot_mask;
+      }
       break;
 
    case nir_intrinsic_load_output:
-      if (shader->info.stage == MESA_SHADER_TESS_CTRL)
-         shader->info.patch_outputs_read |= slot_mask;
-      else
-         shader->info.outputs_read |= slot_mask;
-      break;
-
    case nir_intrinsic_load_per_vertex_output:
-      shader->info.outputs_read |= slot_mask;
+      if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
+          instr->intrinsic == nir_intrinsic_load_output) {
+         shader->info.patch_outputs_read |= slot_mask;
+         if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
+            shader->info.patch_outputs_accessed_indirectly |= slot_mask;
+      } else {
+         shader->info.outputs_read |= slot_mask;
+         if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
+            shader->info.outputs_accessed_indirectly |= slot_mask;
+      }
       break;
 
    case nir_intrinsic_store_output:
-      if (shader->info.stage == MESA_SHADER_TESS_CTRL)
-         shader->info.patch_outputs_written |= slot_mask;
-      else
-         shader->info.outputs_written |= slot_mask;
-      break;
-
    case nir_intrinsic_store_per_vertex_output:
-      shader->info.outputs_written |= slot_mask;
+      if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
+          instr->intrinsic == nir_intrinsic_store_output) {
+         shader->info.patch_outputs_written |= slot_mask;
+         if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
+            shader->info.patch_outputs_accessed_indirectly |= slot_mask;
+      } else {
+         shader->info.outputs_written |= slot_mask;
+         if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
+            shader->info.outputs_accessed_indirectly |= slot_mask;
+      }
       break;
 
    case nir_intrinsic_load_draw_id: