Add .fpu directives to ARM unwind save & restore functions.
TODO: The iwmmx register save & restore functions still need the same treatment.
I didn't do that in this patch because the integrated assembler has a bug
where it refuses to build them on -march=armv6-m, even with
.march armv5t
.arm
in front of those functions.
This should fix PR22384.
http://reviews.llvm.org/D7258
git-svn-id: https://llvm.org/svn/llvm-project/libcxxabi/trunk@230360 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/src/Unwind/UnwindRegistersRestore.S b/src/Unwind/UnwindRegistersRestore.S
index 5e52ad7..00f2aeb 100644
--- a/src/Unwind/UnwindRegistersRestore.S
+++ b/src/Unwind/UnwindRegistersRestore.S
@@ -347,8 +347,8 @@
@ values pointer is in r0
@
.p2align 2
+ .fpu vfpv3-d16
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMDEPy)
-#if defined(__ARM_FP)
@ VFP and iwMMX instructions are only available when compiling with the flags
@ that enable them. We do not want to do that in the library (because we do not
@ want the compiler to generate instructions that access those) but this is
@@ -356,12 +356,7 @@
@ these registers implies they are, actually, available on the target, so
@ it's ok to execute.
@ So, generate the instruction using the corresponding coprocessor mnemonic.
-#if __ARM_ARCH < 7
- ldc p11, cr0, [r0], {0x20} @ fldmiad r0, {d0-d15}
-#else
vldmia r0, {d0-d15}
-#endif
-#endif
JMP(lr)
@
@@ -371,14 +366,9 @@
@ values pointer is in r0
@
.p2align 2
+ .fpu vfpv3-d16
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMXEPy)
-#if defined(__ARM_FP)
-#if __ARM_ARCH < 7
- ldc p11, cr0, [r0], {0x21} @ fldmiax r0, {d0-d15}
-#else
vldmia r0, {d0-d15} @ fldmiax is deprecated in ARMv7+ and now behaves like vldmia
-#endif
-#endif
JMP(lr)
@
@@ -388,14 +378,9 @@
@ values pointer is in r0
@
.p2align 2
+ .fpu vfpv3
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm12restoreVFPv3EPy)
-#if defined(__ARM_FP)
-#if !defined(__ARM_NEON)
- ldcl p11, cr0, [r0], {0x20} @ vldm r0, {d16-d31}
-#else
vldmia r0, {d16-d31}
-#endif
-#endif
JMP(lr)
@
diff --git a/src/Unwind/UnwindRegistersSave.S b/src/Unwind/UnwindRegistersSave.S
index 0a563e9..8c886a8 100644
--- a/src/Unwind/UnwindRegistersSave.S
+++ b/src/Unwind/UnwindRegistersSave.S
@@ -333,14 +333,9 @@
@ values pointer is in r0
@
.p2align 2
+ .fpu vfpv3-d16
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMDEPy)
-#if defined(__ARM_FP)
-#if __ARM_ARCH < 7
- stc p11, cr0, [r0], {0x20} @ fstmiad r0, {d0-d15}
-#else
vstmia r0, {d0-d15}
-#endif
-#endif
JMP(lr)
@
@@ -350,14 +345,9 @@
@ values pointer is in r0
@
.p2align 2
+ .fpu vfpv3-d16
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMXEPy)
-#if defined(__ARM_FP)
-#if __ARM_ARCH < 7
- stc p11, cr0, [r0], {0x21} @ fstmiax r0, {d0-d15}
-#else
vstmia r0, {d0-d15} @ fstmiax is deprecated in ARMv7+ and now behaves like vstmia
-#endif
-#endif
JMP(lr)
@
@@ -367,8 +357,8 @@
@ values pointer is in r0
@
.p2align 2
+ .fpu vfpv3
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm9saveVFPv3EPy)
-#if defined(__ARM_FP)
@ VFP and iwMMX instructions are only available when compiling with the flags
@ that enable them. We do not want to do that in the library (because we do not
@ want the compiler to generate instructions that access those) but this is
@@ -376,12 +366,7 @@
@ these registers implies they are, actually, available on the target, so
@ it's ok to execute.
@ So, generate the instructions using the corresponding coprocessor mnemonic.
-#if !defined(__ARM_NEON)
- stcl p11, cr0, [r0], {0x20} @ vstm r0, {d16-d31}
-#else
vstmia r0, {d16-d31}
-#endif
-#endif
JMP(lr)
@
