WW32 Driver Drop
Note this is an iterative drop on top of the previous driver drops.
Kernel Commit:
46c3d868f12209097c6cefaa2a49feaca494e4e1
Change-Id: I5ff24b54038b68a944acb7c8fb3abc552e91d517
Signed-off-by: Fabrizio Basso <basso@google.com>
diff --git a/drivers/misc/paintbox/Kconfig b/drivers/misc/paintbox/Kconfig
index 47bbfb2..9cb4630 100644
--- a/drivers/misc/paintbox/Kconfig
+++ b/drivers/misc/paintbox/Kconfig
@@ -57,28 +57,9 @@
---help---
This option sets the default state for Paintbox IOMMU to on.
-choice
- prompt "Paintbox Version"
- depends on PAINTBOX
- default PAINTBOX_V0
-
-config PAINTBOX_V0
- bool "Paintbox V0 functionality and errata"
- ---help---
- This option enables Paintbox V0 specific functionality and errata.
-
-config PAINTBOX_V1
- bool "Paintbox V1 functionality and errata"
- ---help---
- This option enables Paintbox V1 specific functionality and errata.
-
-endchoice
-
config PAINTBOX_VERSION_MAJOR
int
depends on PAINTBOX
- default 2 if PAINTBOX_V2
- default 1 if PAINTBOX_V1
default 0
endmenu
diff --git a/drivers/misc/paintbox/Makefile b/drivers/misc/paintbox/Makefile
index 2050ba4..7a7aa91 100644
--- a/drivers/misc/paintbox/Makefile
+++ b/drivers/misc/paintbox/Makefile
@@ -19,8 +19,7 @@
obj-$(CONFIG_PAINTBOX) += paintbox-lbp-debug.o
obj-$(CONFIG_PAINTBOX) += paintbox-mipi.o
obj-$(CONFIG_PAINTBOX) += paintbox-mipi-debug.o
-obj-$(CONFIG_PAINTBOX_V0) += paintbox-mipi-v0.o
-obj-$(CONFIG_PAINTBOX_V1) += paintbox-mipi-v1.o
+obj-$(CONFIG_PAINTBOX) += paintbox-mipi-v0.o
obj-$(CONFIG_PAINTBOX) += paintbox-mmu.o
obj-$(CONFIG_PAINTBOX) += paintbox-pmon.o
obj-$(CONFIG_PAINTBOX) += paintbox-power.o
diff --git a/drivers/misc/paintbox/paintbox-bif.c b/drivers/misc/paintbox/paintbox-bif.c
index 8a09193..21f86c3 100644
--- a/drivers/misc/paintbox/paintbox-bif.c
+++ b/drivers/misc/paintbox/paintbox-bif.c
@@ -161,7 +161,7 @@
*/
dma_report_error_all_channels(pb, -ENOTRECOVERABLE);
- /* TODO(ahampson): Initiate a reset of the IPU and block new operations
+ /* TODO: Initiate a reset of the IPU and block new operations
* until the IPU comes out of reset. Note it might be necessary to
* reset the whole Easel chip if the AXI bus is messed up. As part of
* the reset process any MIPI or STP waiters should be released.
@@ -189,7 +189,7 @@
*/
dma_report_error_all_channels(pb, -ENOTRECOVERABLE);
- /* TODO(ahampson): Initiate a reset of the IPU and block new operations
+ /* TODO: Initiate a reset of the IPU and block new operations
* until the IPU comes out of reset. Note it might be necessary to
* reset the whole Easel chip if the AXI bus is messed up. As part of
* the reset process any MIPI or STP waiters should be released.
@@ -224,7 +224,7 @@
*/
dma_report_error_all_channels(pb, -ENOTRECOVERABLE);
- /* TODO(ahampson): Initiate a reset of the IPU and block new operations
+ /* TODO: Initiate a reset of the IPU and block new operations
* until the IPU comes out of reset. As part of the reset process any
* MIPI or STP waiters should be released. b/34518459
*/
diff --git a/drivers/misc/paintbox/paintbox-debug.c b/drivers/misc/paintbox/paintbox-debug.c
index af87326..5ccdf22c 100644
--- a/drivers/misc/paintbox/paintbox-debug.c
+++ b/drivers/misc/paintbox/paintbox-debug.c
@@ -56,7 +56,7 @@
vaf.fmt = format;
vaf.va = &args;
- /* TODO(ahampson): Add support for levels */
+ /* TODO: Add support for levels */
pr_info("%pV", &vaf);
}
@@ -96,7 +96,7 @@
readl(group_base + reg_offset));
}
-/* TODO(ahampson): Remove the 32bit version and rename this one
+/* TODO: Remove the 32bit version and rename this one
* dump_ipu_register() when all the register groups have been converted.
* b/62373740
*/
@@ -122,7 +122,7 @@
reg_name ? reg_name : REG_UNUSED, reg_value);
}
-/* TODO(ahampson): Remove the 32bit version and rename this one
+/* TODO: Remove the 32bit version and rename this one
* dump_ipu_register_with_value() when all the register groups have been
* converted. b/62373740
*/
@@ -903,7 +903,7 @@
struct paintbox_data *pb = inode->i_private;
size_t len;
- /* TODO(showarth): Add V1 support for AON registers */
+ /* TODO: Add V1 support for AON registers */
len = IO_APB_NUM_REGS * REG_DEBUG_BUFFER_SIZE;
len += IO_AXI_NUM_REGS * REG_DEBUG_BUFFER_SIZE;
len += pb->io_ipu.num_mipi_input_streams * IO_IPU_NUM_REGS *
diff --git a/drivers/misc/paintbox/paintbox-dma-common.c b/drivers/misc/paintbox/paintbox-dma-common.c
index e32c933..35c75da 100644
--- a/drivers/misc/paintbox/paintbox-dma-common.c
+++ b/drivers/misc/paintbox/paintbox-dma-common.c
@@ -34,7 +34,7 @@
#include "paintbox-regs.h"
#include "paintbox-stp.h"
-/* TODO(ahampson): Temporarily make DMA configuration validation a debug
+/* TODO: Temporarily make DMA configuration validation a debug
* only operation.
*/
#ifdef DEBUG
@@ -137,7 +137,7 @@
struct paintbox_dma_transfer *transfer,
struct dma_image_config *config)
{
- /* TODO(ahampson): Temporarily make LBP DMA configuration validation a
+ /* TODO: Temporarily make LBP DMA configuration validation a
* debug only operation.
*/
#ifdef DEBUG
@@ -240,7 +240,7 @@
struct dma_transfer_config *config)
{
-/* TODO(ahampson): Temporarily make DMA configuration validation a debug
+/* TODO: Temporarily make DMA configuration validation a debug
* only operation.
*/
#ifdef DEBUG
@@ -307,7 +307,7 @@
DMA_CHAN_NOC_XFER_RETRY_INTERVAL_SHIFT;
#if CONFIG_PAINTBOX_VERSION_MAJOR == 0
- /* TODO(ahampson): DMA_CHAN_NOC_XFER_DYN_OUTSTANDING_MASK is currently
+ /* TODO: DMA_CHAN_NOC_XFER_DYN_OUTSTANDING_MASK is currently
* set for all DMA transfers at this time. This may change in the
* future to give priority to MIPI transfers.
*/
diff --git a/drivers/misc/paintbox/paintbox-dma-dram.c b/drivers/misc/paintbox/paintbox-dma-dram.c
index c8d5ab1..8088668 100644
--- a/drivers/misc/paintbox/paintbox-dma-dram.c
+++ b/drivers/misc/paintbox/paintbox-dma-dram.c
@@ -126,7 +126,7 @@
}
#endif
- /* TODO(ahampson): dma_buf_offset_bytes + config->len_bytes should be
+ /* TODO: dma_buf_offset_bytes + config->len_bytes should be
* less than or equal sg_dma_len(transfer->sg_table->sgl). Currently
* the config->len_bytes value supplied by the runtime is not the
* actual transfer boundary. b/35243756
@@ -164,7 +164,7 @@
}
#endif
- /* TODO(ahampson): The buffer offset should be factored in earlier so
+ /* TODO: The buffer offset should be factored in earlier so
* we don't map pages we don't need into the IOVA.
*/
transfer->dma_addr = sg_dma_address(transfer->sg_table->sgl) +
diff --git a/drivers/misc/paintbox/paintbox-dma-lbp.c b/drivers/misc/paintbox/paintbox-dma-lbp.c
index 7afdd8a..e79d8a0 100644
--- a/drivers/misc/paintbox/paintbox-dma-lbp.c
+++ b/drivers/misc/paintbox/paintbox-dma-lbp.c
@@ -43,7 +43,7 @@
struct paintbox_dma_transfer *transfer,
struct dma_lbp_config *config)
{
- /* TODO(ahampson): Temporarily make LBP DMA configuration validation a
+ /* TODO: Temporarily make LBP DMA configuration validation a
* debug only operation. b/62353362
*/
#ifdef DEBUG
@@ -109,7 +109,7 @@
{
int ret;
- /* TODO(ahampson): Temporarily make LBP DMA configuration validation a
+ /* TODO: Temporarily make LBP DMA configuration validation a
* debug only operation. b/62353362
*/
#ifdef DEBUG
@@ -171,7 +171,7 @@
{
int ret;
- /* TODO(ahampson): Temporarily make LBP DMA configuration validation a
+ /* TODO: Temporarily make LBP DMA configuration validation a
* debug only operation. b/62353362
*/
#ifdef DEBUG
@@ -236,7 +236,7 @@
if (channel->stats.time_stats_enabled)
channel->stats.non_dram_setup_start_time = ktime_get_boottime();
- /* TODO(ahampson): Temporarily make LBP DMA configuration validation a
+ /* TODO: Temporarily make LBP DMA configuration validation a
* debug only operation. b/62353362
*/
#ifdef DEBUG
@@ -296,7 +296,7 @@
if (channel->stats.time_stats_enabled)
channel->stats.non_dram_setup_start_time = ktime_get_boottime();
- /* TODO(ahampson): Temporarily make LBP DMA configuration validation a
+ /* TODO: Temporarily make LBP DMA configuration validation a
* debug only operation. b/62353362
*/
#ifdef DEBUG
diff --git a/drivers/misc/paintbox/paintbox-dma-mipi.c b/drivers/misc/paintbox/paintbox-dma-mipi.c
index 2380d40..a36cb06 100644
--- a/drivers/misc/paintbox/paintbox-dma-mipi.c
+++ b/drivers/misc/paintbox/paintbox-dma-mipi.c
@@ -37,7 +37,7 @@
{
int ret;
-/* TODO(ahampson): Temporarily make MIPI DMA configuration validation a debug
+/* TODO: Temporarily make MIPI DMA configuration validation a debug
* only operation. b/62353362
*/
#ifdef DEBUG
diff --git a/drivers/misc/paintbox/paintbox-dma-stp.c b/drivers/misc/paintbox/paintbox-dma-stp.c
index fc07fc2..a2f1514 100644
--- a/drivers/misc/paintbox/paintbox-dma-stp.c
+++ b/drivers/misc/paintbox/paintbox-dma-stp.c
@@ -35,7 +35,7 @@
#include "paintbox-regs.h"
#include "paintbox-stp.h"
-/* TODO(ahampson): Temporarily make stp dma configuration validation a debug
+/* TODO: Temporarily make stp dma configuration validation a debug
* only operation. b/62353362
*/
#ifdef DEBUG
@@ -147,7 +147,7 @@
*/
switch (stp_config->sram_target) {
case SRAM_TARGET_STP_INSTRUCTION_RAM:
- /* TODO(ahampson): Temporarily make stp dma configuration
+ /* TODO: Temporarily make stp dma configuration
* validation a debug only operation. b/62353362
*/
#ifdef DEBUG
@@ -161,7 +161,7 @@
DMA_CHAN_LB_START_Y_STP_IRAM);
break;
case SRAM_TARGET_STP_CONSTANT_RAM:
- /* TODO(ahampson): Temporarily make stp dma configuration
+ /* TODO: Temporarily make stp dma configuration
* validation a debug only operation. b/62353362
*/
#ifdef DEBUG
@@ -175,7 +175,7 @@
DMA_CHAN_LB_START_Y_STP_CRAM);
break;
case SRAM_TARGET_STP_SCALAR_RAM:
- /* TODO(ahampson): Temporarily make stp dma configuration
+ /* TODO: Temporarily make stp dma configuration
* validation a debug only operation. b/62353362
*/
#ifdef DEBUG
@@ -189,7 +189,7 @@
DMA_CHAN_LB_START_Y_STP_DRAM);
break;
case SRAM_TARGET_STP_VECTOR_RAM:
- /* TODO(ahampson): Add parameter checks for vector b/30969166
+ /* TODO: Add parameter checks for vector b/30969166
*/
paintbox_dma_set_lb_start(transfer,
(uint64_t)stp_config->sram_addr,
@@ -220,7 +220,7 @@
{
int ret;
- /* TODO(ahampson): Temporarily make stp dma configuration validation a
+ /* TODO: Temporarily make stp dma configuration validation a
* debug only operation. b/62353362
*/
#ifdef DEBUG
diff --git a/drivers/misc/paintbox/paintbox-dma.c b/drivers/misc/paintbox/paintbox-dma.c
index cde6ef3..84371a7 100644
--- a/drivers/misc/paintbox/paintbox-dma.c
+++ b/drivers/misc/paintbox/paintbox-dma.c
@@ -358,7 +358,7 @@
* read queue that is emptied by read_dma_transfer_ioctl(). All other
* transfers go on a discard queue and are cleaned up by a work queue.
*
- * TODO(ahampson): Remove the read queue support when b/62371806 is
+ * TODO: Remove the read queue support when b/62371806 is
* fixed.
*/
if (transfer->buffer_type == DMA_DRAM_BUFFER_USER &&
@@ -875,7 +875,7 @@
writel(transfer->chan_bif_xfer, dma_base + DMA_CHAN_BIF_XFER);
}
- /* TODO(ahampson): The trace_combiner used in register trace generation
+ /* TODO: The trace_combiner used in register trace generation
* relies on the DMA_CHAN_VA and DMA_CHAN_VA_BDRY registers being
* present in register traces for DMA transfers. When running on the
* Simulator the driver needs to always write these registers
@@ -1296,7 +1296,7 @@
writel(DMA_CTRL_DMA_RESET_MASK, pb->dma.dma_base + DMA_CTRL);
- /* TODO(ahampson): There should be no need to hold the DMA reset
+ /* TODO: There should be no need to hold the DMA reset
* register high for a minimum period but the FPGA will lockup if the
* reset register is cleared immediately following a VA Error Interrupt.
* This needs to be evaluated on the real hardware. b/35779292
diff --git a/drivers/misc/paintbox/paintbox-lbp.c b/drivers/misc/paintbox/paintbox-lbp.c
index dff4be4..7bed049 100644
--- a/drivers/misc/paintbox/paintbox-lbp.c
+++ b/drivers/misc/paintbox/paintbox-lbp.c
@@ -37,14 +37,14 @@
#define LB_BLOCK_TRANSFER_HEIGHT 4
#define LB_BLOCK_TRANSFER_WIDTH 4
-/* TODO(ahampson): Temporarily make the line buffer configuration validation a
+/* TODO: Temporarily make the line buffer configuration validation a
* debug only operation. b/62353362
*/
#ifdef DEBUG
static int validate_lb_config(struct paintbox_data *pb,
struct paintbox_lbp *lbp, struct line_buffer_config *lb_config)
{
- /* TODO(ahampson): Need to figure out how the broadcast id will be
+ /* TODO: Need to figure out how the broadcast id will be
* expressed.
*/
if (lb_config->lb_id < 0 || lb_config->lb_id >= pb->lbp.max_lbs) {
diff --git a/drivers/misc/paintbox/paintbox-mipi-v0.c b/drivers/misc/paintbox/paintbox-mipi-v0.c
index f3427f0..54a4658 100644
--- a/drivers/misc/paintbox/paintbox-mipi-v0.c
+++ b/drivers/misc/paintbox/paintbox-mipi-v0.c
@@ -347,7 +347,7 @@
/* On the V0 IPU it is also not possible to enable all streams at once, streams
* will be enabled sequentially.
*
- * TODO(ahampson): This function does not verify that the streams being enabled
+ * TODO: This function does not verify that the streams being enabled
* are all in the same state.
*/
void paintbox_mipi_enable_multiple_input(struct paintbox_data *pb,
@@ -377,7 +377,7 @@
req->free_running, req->frame_count,
req->input.disable_on_error);
- /* TODO(ahampson): A future performance optimization would be
+ /* TODO: A future performance optimization would be
* to construct an array of ctrl register masks here and then
* write that all at once in a second loop. This would reduce
* the amount of time between stream enables.
@@ -399,7 +399,7 @@
/* On the V0 IPU it is also not possible to enable all streams at once, streams
* will be enabled sequentially.
*
- * TODO(ahampson): This function does not verify that the streams being enabled
+ * TODO: This function does not verify that the streams being enabled
* are all in the same state.
*/
void paintbox_mipi_enable_multiple_output(struct paintbox_data *pb,
@@ -442,7 +442,7 @@
/* On the V0 IPU it is also not possible to disable all streams at once, streams
* will be disabled sequentially.
*
- * TODO(ahampson): This function does not verify that the streams being
+ * TODO: This function does not verify that the streams being
* disables are all in the same state.
*/
void paintbox_mipi_disable_multiple_input(struct paintbox_data *pb,
@@ -486,7 +486,7 @@
/* On the V0 IPU it is also not possible to disable all streams at once, streams
* will be disabled sequentially.
*
- * TODO(ahampson): This function does not verify that the streams being
+ * TODO: This function does not verify that the streams being
* disables are all in the same state.
*/
void paintbox_mipi_disable_multiple_output(struct paintbox_data *pb,
diff --git a/drivers/misc/paintbox/paintbox-mipi-v0.h b/drivers/misc/paintbox/paintbox-mipi-v0.h
index 0687022..e409713 100644
--- a/drivers/misc/paintbox/paintbox-mipi-v0.h
+++ b/drivers/misc/paintbox/paintbox-mipi-v0.h
@@ -44,7 +44,7 @@
#define MIPI_OUTPUT_EOF_IMR MPO_STRM_CTRL_EOF_IMR_MASK
#define MIPI_OUTPUT_EOF_ISR MPO_STRM_CTRL_EOF_ISR_MASK
-/* TODO(ahampson): The mapping here below applies to the V0 IPU but may not be
+/* TODO: The mapping here below applies to the V0 IPU but may not be
* the same in future versions of the hardware. This mapping should be moved
* into the device tree. b/32283059
*
diff --git a/drivers/misc/paintbox/paintbox-mipi-v1.c b/drivers/misc/paintbox/paintbox-mipi-v1.c
deleted file mode 100644
index bcda2e0..0000000
--- a/drivers/misc/paintbox/paintbox-mipi-v1.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Paintbox V1 specific MIPI Support for Paintbox programmable IPU
- *
- * Copyright (C) 2017 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/types.h>
-#include <uapi/paintbox.h>
-
-#include "paintbox-dma.h"
-#include "paintbox-io.h"
-#include "paintbox-mipi.h"
-#include "paintbox-mipi-debug.h"
-#include "paintbox-mipi-v1.h"
-#include "paintbox-regs.h"
-
-/* TODO(ahampson): This function will enable several streams simultaneously but
- * it does not verify that all the streams are ready to be enabled or are in the
- * same state. It also does not attempt to synchronize the stream update with
- * with any frame boundaries if the stream is already running.
- */
-void paintbox_mipi_enable_multiple_input(struct paintbox_data *pb,
- struct paintbox_session *session, uint32_t stream_id_mask,
- struct mipi_stream_enable_multiple *req)
-{
- struct paintbox_mipi_stream *stream, *stream_next;
- unsigned long irq_flags;
- uint64_t ctrl_set_mask = 0;
- uint32_t imr_set_mask = 0, imr_err_set_mask = 0;
-
- spin_lock_irqsave(&pb->io_ipu.mipi_lock, irq_flags);
-
- list_for_each_entry_safe(stream, stream_next,
- &session->mipi_input_list, session_entry) {
- if (!req->enable_all &&
- !(stream_id_mask & (1 << stream->stream_id)))
- continue;
-
- if (stream->enabled) {
- paintbox_mipi_update_stream_count(pb, stream,
- req->free_running, req->frame_count);
- continue;
- }
-
- paintbox_mipi_enable_input_stream_common(pb, stream,
- req->free_running, req->frame_count,
- req->input.disable_on_error);
-
- imr_set_mask |= 1 << (stream->stream_id + MPI_IMR_SOF0_SHIFT);
- imr_err_set_mask |= 1 << (stream->stream_id +
- MPI_ERR_IMR_OVF0_SHIFT);
- ctrl_set_mask |= MPI_CTRL_STRM_ENA_SET0_MASK <<
- stream->stream_id;
-
- /* TODO(ahampson, showarth): Implement support for single shot
- * mode. In the interim, continuous mode will always be used
- * with the stream disabled explicitly from the userspace or
- * when the requested number of frames has been met.
- */
- ctrl_set_mask |= MPI_CTRL_STRM_CONTINUOUS_SET0_MASK <<
- stream->stream_id;
- }
-
- mipi_input_set_imr(pb, imr_set_mask);
- mipi_input_set_err_imr(pb, imr_err_set_mask);
-
- writeq(ctrl_set_mask, pb->io_ipu.ipu_base + MPI_CTRL);
-
- spin_unlock_irqrestore(&pb->io_ipu.mipi_lock, irq_flags);
-}
-
-/* TODO(ahampson): This function will enable several streams simultaneously but
- * it does not verify that all the streams are ready to be enabled or are in the
- * same state. It also does not attempt to synchronize the stream update with
- * with any frame boundaries if the stream is already running.
- */
-void paintbox_mipi_enable_multiple_output(struct paintbox_data *pb,
- struct paintbox_session *session, uint32_t stream_id_mask,
- struct mipi_stream_enable_multiple *req)
-{
- struct paintbox_mipi_stream *stream, *stream_next;
- unsigned long irq_flags;
- uint64_t ctrl_set_mask = 0, ctrl_clear_mask = 0;
- uint32_t imr_set_mask = 0;
-
- spin_lock_irqsave(&pb->io_ipu.mipi_lock, irq_flags);
-
- list_for_each_entry_safe(stream, stream_next,
- &session->mipi_output_list, session_entry) {
- if (!req->enable_all &&
- !(stream_id_mask & (1 << stream->stream_id)))
- continue;
-
- if (stream->enabled) {
- paintbox_mipi_update_stream_count(pb, stream,
- req->free_running, req->frame_count);
- continue;
- }
-
- /* frame count is zero when in free running mode. */
- stream->free_running = req->free_running;
-
- /* set the frame count to the value passed in minus one
- * since the stream will start the output frame on
- * enable.
- */
- stream->frame_count = req->free_running ? 0 :
- req->frame_count - 1;
- stream->is_clean = false;
- stream->enabled = true;
-
- enable_mipi_interface(pb, stream);
-
- /* TODO(showarth): wait for last frame. b/38357562 */
-
- paintbox_mipi_select_output_stream(pb, stream->stream_id);
-
- /* {set,clear} RSYNC_EN in case previously {cleared,set} */
- mipi_output_clear_and_set_control(pb, stream,
- req->output.enable_row_sync ? 0 :
- MPO_STRM_CTRL_RSYNC_EN_MASK,
- req->output.enable_row_sync ?
- MPO_STRM_CTRL_RSYNC_EN_MASK : 0);
-
- imr_set_mask |= 1 << (stream->stream_id + MPO_IMR_EOF0_SHIFT);
-
- ctrl_set_mask |= MPO_CTRL_STRM_ENA_SET0_MASK <<
- stream->stream_id;
-
- /* TODO(ahampson, showarth): Implement support for single shot
- * mode. In the interim, continuous mode will always be used
- * with the stream disabled explicitly from the userspace or
- * when the requested number of frames has been met.
- */
- ctrl_set_mask |= MPO_CTRL_STRM_CONTINUOUS_SET0_MASK <<
- stream->stream_id;
-
- stream->last_frame = !req->free_running &&
- req->frame_count == 0;
-
- /* TODO(ahampson, showarth): Clear continuous mode for any
- * streams that are on their last frame. This should not be
- * necessary once single shot mode is fully supported.
- */
- if (stream->last_frame)
- ctrl_clear_mask |= MPO_CTRL_STRM_CONTINUOUS_CLR0_MASK;
- }
-
- mipi_output_set_imr(pb, imr_set_mask);
-
- writeq(ctrl_set_mask, pb->io_ipu.ipu_base + MPO_CTRL);
-
- if (!ctrl_clear_mask)
- writeq(ctrl_clear_mask, pb->io_ipu.ipu_base + MPO_CTRL);
-
- spin_unlock_irqrestore(&pb->io_ipu.mipi_lock, irq_flags);
-}
-
-void paintbox_mipi_disable_multiple_input(struct paintbox_data *pb,
- struct paintbox_session *session, uint32_t stream_id_mask,
- struct mipi_stream_disable_multiple *req)
-{
- struct paintbox_mipi_stream *stream, *stream_next;
- uint64_t ctrl_clear_mask = 0;
- uint32_t imr_clear_mask = 0;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&pb->io_ipu.mipi_lock, irq_flags);
-
- list_for_each_entry_safe(stream, stream_next, &session->mipi_input_list,
- session_entry) {
- if (!req->disable_all &&
- !(stream_id_mask & (1 << stream->stream_id)))
- continue;
-
- paintbox_mipi_disable_stream_common(pb, stream);
-
- /* Do not disable the overflow interrupt on disable. This
- * interrupt reports on the state of the current frame and needs
- * to be left enabled.
- */
- imr_clear_mask |= 1 << (stream->stream_id + MPI_IMR_SOF0_SHIFT);
-
- ctrl_clear_mask |= MPI_CTRL_STRM_CONTINUOUS_CLR0_MASK <<
- stream->stream_id;
- }
-
- mipi_input_clear_imr(pb, imr_clear_mask);
-
- writeq(ctrl_clear_mask, pb->io_ipu.ipu_base + MPI_CTRL);
-
- spin_unlock_irqrestore(&pb->io_ipu.mipi_lock, irq_flags);
-}
-
-void paintbox_mipi_disable_multiple_output(struct paintbox_data *pb,
- struct paintbox_session *session, uint32_t stream_id_mask,
- struct mipi_stream_disable_multiple *req)
-{
- struct paintbox_mipi_stream *stream, *stream_next;
- uint64_t ctrl_clear_mask = 0;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&pb->io_ipu.mipi_lock, irq_flags);
-
- list_for_each_entry_safe(stream, stream_next,
- &session->mipi_output_list, session_entry) {
- if (!req->disable_all &&
- !(stream_id_mask & (1 << stream->stream_id)))
- continue;
-
- paintbox_mipi_disable_stream_common(pb, stream);
-
- /* Do not disable the EOF interrupt on disable. This interrupt
- * reports on the state of the current frame and needs to be
- * left enabled.
- */
- ctrl_clear_mask |= MPO_CTRL_STRM_CONTINUOUS_CLR0_MASK <<
- stream->stream_id;
- }
-
- writeq(ctrl_clear_mask, pb->io_ipu.ipu_base + MPO_CTRL);
-
- spin_unlock_irqrestore(&pb->io_ipu.mipi_lock, irq_flags);
-}
diff --git a/drivers/misc/paintbox/paintbox-mipi-v1.h b/drivers/misc/paintbox/paintbox-mipi-v1.h
deleted file mode 100644
index ecb3b4f..0000000
--- a/drivers/misc/paintbox/paintbox-mipi-v1.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * Paintbox V1 specific MIPI support for Paintbox programmable IPU
- *
- * Copyright (C) 2017 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __PAINTBOX_MIPI_V1_H__
-#define __PAINTBOX_MIPI_V1_H__
-
-#include <linux/io.h>
-
-#include "paintbox-common.h"
-#include "paintbox-mipi.h"
-#include "paintbox-regs.h"
-
-#define MIPI_INVALID_FRAME_NUMBER -1
-
-#define MIPI_INPUT_SOF_IMR (1 << 0)
-#define MIPI_INPUT_SOF_ISR (1 << 0)
-#define MIPI_INPUT_OVF_IMR (1 << 1)
-#define MIPI_INPUT_OVF_ISR (1 << 1)
-
-#define MIPI_OUTPUT_EOF_IMR (1 << 0)
-#define MIPI_OUTPUT_EOF_ISR (1 << 0)
-
-/* MIPI input streams 0..11 have a fixed mapping to DMA channels 0..11.
- * MIPI output streams 0..3 and 4..7 share fixed mappings to DMA channels
- * 12..15.
- */
-#define MIPI_INPUT_DMA_CHANNEL_ID_START 0
-#define MIPI_INPUT_DMA_CHANNEL_ID_END 11
-#define MIPI_OUTPUT_DMA_CHANNEL_ID_START 12
-#define MIPI_OUTPUT_DMA_CHANNEL_ID_END 15
-
-static inline unsigned int mipi_stream_to_dma_channel_id(
- struct paintbox_mipi_stream *stream)
-{
- return stream->is_input
- ? MIPI_INPUT_DMA_CHANNEL_ID_START + stream->stream_id
- : MIPI_OUTPUT_DMA_CHANNEL_ID_START + (stream->stream_id % 4);
-}
-
-/* The caller to this function must hold pb->io_ipu.mipi_lock. */
-static inline int mipi_output_clear_and_set_control(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream, uint32_t ctrl_clear_mask,
- uint32_t ctrl_set_mask)
-{
- uint32_t ctrl;
-
- ctrl = readl(pb->io_ipu.ipu_base + MPO_STRM_CTRL);
- ctrl &= ~ctrl_clear_mask;
- ctrl |= ctrl_set_mask;
- writel(ctrl, pb->io_ipu.ipu_base + MPO_STRM_CTRL);
-
- return 0;
-}
-
-/* The caller to the mipi_{in,out}put_(ack|{en,dis}able)_xxx functions must hold
- * pb->io_ipu.mipi_lock.
- */
-static inline int mipi_input_enable_stream(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream)
-{
- writeq((MPI_CTRL_STRM_CONTINUOUS_SET0_MASK |
- MPI_CTRL_STRM_ENA_SET0_MASK) << stream->stream_id,
- pb->io_ipu.ipu_base + MPI_CTRL);
-
- return 0;
-}
-
-static inline void mipi_input_set_imr(struct paintbox_data *pb,
- uint32_t set_mask)
-{
- uint32_t val;
-
- val = readl(pb->io_ipu.ipu_base + MPI_IMR);
- val |= set_mask;
- writel(val, pb->io_ipu.ipu_base + MPI_IMR);
-
- /* With MIPI we enable and disable at the IER, as well as the IMR. */
- val = readl(pb->io_ipu.ipu_base + MPI_IER);
- val |= set_mask;
- writel(val, pb->io_ipu.ipu_base + MPI_IER);
-}
-
-static inline void mipi_input_set_err_imr(struct paintbox_data *pb,
- uint32_t set_mask)
-{
- uint32_t val;
-
- val = readl(pb->io_ipu.ipu_base + MPI_ERR_IMR);
- val |= set_mask;
- writel(val, pb->io_ipu.ipu_base + MPI_ERR_IMR);
-
- /* With MIPI we enable and disable at the IER, as well as the IMR. */
- val = readl(pb->io_ipu.ipu_base + MPI_ERR_IER);
- val |= set_mask;
- writel(val, pb->io_ipu.ipu_base + MPI_ERR_IER);
-}
-
-static inline void mipi_input_clear_imr(struct paintbox_data *pb,
- uint32_t clear_mask)
-{
- uint32_t val;
-
- /* With MIPI we enable and disable at the IER, as well as the IMR. */
- val = readl(pb->io_ipu.ipu_base + MPI_IER);
- val &= ~clear_mask;
- writel(val, pb->io_ipu.ipu_base + MPI_IER);
-
- val = readl(pb->io_ipu.ipu_base + MPI_IMR);
- val &= ~clear_mask;
- writel(val, pb->io_ipu.ipu_base + MPI_IMR);
-}
-
-static inline void mipi_input_clear_err_imr(struct paintbox_data *pb,
- uint32_t clear_mask)
-{
- uint32_t val;
-
- /* With MIPI we enable and disable at the IER, as well as the IMR. */
- val = readl(pb->io_ipu.ipu_base + MPI_ERR_IER);
- val &= ~clear_mask;
- writel(val, pb->io_ipu.ipu_base + MPI_ERR_IER);
-
- val = readl(pb->io_ipu.ipu_base + MPI_ERR_IMR);
- val &= ~clear_mask;
- writel(val, pb->io_ipu.ipu_base + MPI_ERR_IMR);
-}
-
-static inline void mipi_output_set_imr(struct paintbox_data *pb,
- uint32_t set_mask)
-{
- uint32_t val;
-
- val = readl(pb->io_ipu.ipu_base + MPO_IMR);
- val |= set_mask;
- writel(val, pb->io_ipu.ipu_base + MPO_IMR);
-
- /* With MIPI we enable and disable at the IER, as well as the IMR. */
- val = readl(pb->io_ipu.ipu_base + MPO_IER);
- val |= set_mask;
- writel(val, pb->io_ipu.ipu_base + MPO_IER);
-}
-
-static inline void mipi_output_clear_imr(struct paintbox_data *pb,
- uint32_t clear_mask)
-{
- uint32_t val;
-
- /* With MIPI we enable and disable at the IER, as well as the IMR. */
- val = readl(pb->io_ipu.ipu_base + MPO_IER);
- val &= ~clear_mask;
- writel(val, pb->io_ipu.ipu_base + MPO_IER);
-
- val = readl(pb->io_ipu.ipu_base + MPO_IMR);
- val &= ~clear_mask;
- writel(val, pb->io_ipu.ipu_base + MPO_IMR);
-}
-
-static inline int mipi_input_enable_irqs_and_stream(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream, uint32_t imr_mask)
-{
- if (imr_mask & MIPI_INPUT_SOF_IMR)
- mipi_input_set_imr(pb, 1 << (stream->stream_id +
- MPI_IMR_SOF0_SHIFT));
-
- if (imr_mask & MIPI_INPUT_OVF_IMR)
- mipi_input_set_err_imr(pb, 1 << (stream->stream_id +
- MPI_ERR_IMR_OVF0_SHIFT));
-
- mipi_input_enable_stream(pb, stream);
-
- return 0;
-}
-
-static inline int mipi_input_disable_stream(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream)
-{
- writeq(MPI_CTRL_STRM_CONTINUOUS_CLR0_MASK << stream->stream_id,
- pb->io_ipu.ipu_base + MPI_CTRL);
-
- return 0;
-}
-
-static inline int mipi_input_disable_irqs_and_stream(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream, uint32_t imr_mask)
-{
- if (imr_mask & MIPI_INPUT_SOF_IMR)
- mipi_input_clear_imr(pb, 1 << (stream->stream_id +
- MPI_IMR_SOF0_SHIFT));
-
- if (imr_mask & MIPI_INPUT_OVF_IMR)
- mipi_input_clear_err_imr(pb, 1 << (stream->stream_id +
- MPI_ERR_IMR_OVF0_SHIFT));
-
- mipi_input_disable_stream(pb, stream);
-
- return 0;
-}
-
-static inline int mipi_output_ack_irqs(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream, uint32_t isr_mask)
-{
- if (isr_mask & MIPI_OUTPUT_EOF_ISR)
- writel(1 << (stream->stream_id + MPO_ISR_EOF0_SHIFT),
- pb->io_ipu.ipu_base + MPO_ISR);
-
- return 0;
-}
-
-static inline int mipi_output_enable_stream(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream)
-{
- writeq((MPO_CTRL_STRM_CONTINUOUS_SET0_MASK |
- MPO_CTRL_STRM_ENA_SET0_MASK) << stream->stream_id,
- pb->io_ipu.ipu_base + MPO_CTRL);
-
- return 0;
-}
-
-static inline int mipi_output_enable_irqs_and_stream(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream, uint32_t imr_mask,
- bool row_sync)
-{
- uint32_t val;
-
- if (imr_mask & MIPI_OUTPUT_EOF_IMR) {
- val = readl(pb->io_ipu.ipu_base + MPO_IMR);
- val |= 1 << (stream->stream_id + MPO_IMR_EOF0_SHIFT);
- writel(val, pb->io_ipu.ipu_base + MPO_IMR);
- }
-
- paintbox_mipi_select_output_stream(pb, stream->stream_id);
-
- /* {set,clear} RSYNC_EN in case previously {cleared,set} */
- mipi_output_clear_and_set_control(pb, stream,
- row_sync ? 0 : MPO_STRM_CTRL_RSYNC_EN_MASK,
- row_sync ? MPO_STRM_CTRL_RSYNC_EN_MASK : 0);
-
- mipi_output_enable_stream(pb, stream);
-
- return 0;
-}
-
-static inline int mipi_output_disable_stream(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream)
-{
- writeq(MPO_CTRL_STRM_CONTINUOUS_CLR0_MASK << stream->stream_id,
- pb->io_ipu.ipu_base + MPO_CTRL);
-
- return 0;
-}
-
-static inline int mipi_output_disable_irqs(struct paintbox_data *pb,
- struct paintbox_mipi_stream *stream, uint32_t imr_mask)
-{
- uint32_t val;
-
- if (imr_mask & MIPI_OUTPUT_EOF_IMR) {
- val = readl(pb->io_ipu.ipu_base + MPO_IMR);
- val &= ~(1 << (stream->stream_id + MPO_IMR_EOF0_SHIFT));
- writel(val, pb->io_ipu.ipu_base + MPO_IMR);
- }
-
- return 0;
-}
-
-#endif /* __PAINTBOX_MIPI_V1_H__ */
diff --git a/drivers/misc/paintbox/paintbox-mipi.c b/drivers/misc/paintbox/paintbox-mipi.c
index 4cb2fe07..60aca6b 100644
--- a/drivers/misc/paintbox/paintbox-mipi.c
+++ b/drivers/misc/paintbox/paintbox-mipi.c
@@ -538,7 +538,7 @@
/* Enable the stream. This will copy the stream's pending configuration
* registers to the active set.
*/
- /* TODO(showarth): wait for last frame. b/38357562 */
+ /* TODO: wait for last frame. b/38357562 */
ret = mipi_output_enable_irqs_and_stream(pb, stream,
MIPI_OUTPUT_EOF_IMR, enable_row_sync);
@@ -548,7 +548,7 @@
if (!free_running && stream->frame_count == 0) {
stream->last_frame = true;
- /* TODO(ahampson): Remove Simulator check once MIPI double buffering is
+ /* TODO: Remove Simulator check once MIPI double buffering is
* implemented in the Simulator and QEMU. b/29508438, b/32769802
*
* With the current Simulator, the driver can not disable the stream at
@@ -1016,7 +1016,7 @@
spin_lock_irqsave(&pb->io_ipu.mipi_lock, irq_flags);
#if CONFIG_PAINTBOX_VERSION_MAJOR >= 1
- /* TODO(showarth): wait for ENA == 0 */
+ /* TODO: wait for ENA == 0 */
#else
/* Disable the stream while updating the stream configuration. This is
* to guarantee that the update is atomic if the update occurs over a
@@ -1111,7 +1111,7 @@
spin_lock_irqsave(&pb->io_ipu.mipi_lock, irq_flags);
#if CONFIG_PAINTBOX_VERSION_MAJOR >= 1
- /* TODO(showarth): wait for ENA == 0 */
+ /* TODO: wait for ENA == 0 */
#else
/* Disable the stream while updating the stream configuration. This is
* to guarantee that the update is atomic if the update occurs over a
@@ -1143,7 +1143,7 @@
writeq(cnfg0_val, pb->io_ipu.ipu_base + MPO_STRM_CNFG0);
#if CONFIG_PAINTBOX_VERSION_MAJOR >= 1
- /* TODO(showarth): support multiple virtual channels (b/36103832). */
+ /* TODO: support multiple virtual channels (b/36103832). */
cnfg1_val = 0;
#else
/* The MPO_SEG_END value in the MPO_STRM_CNFG1 register is subtracted
@@ -1300,7 +1300,7 @@
stream->cleanup_in_progress = false;
stream->is_clean = true;
- /* TODO(ahampson): This needs to be disabled for QEMU/Simulator for the
+ /* TODO: This needs to be disabled for QEMU/Simulator for the
* now. The RTL test bench can not currently handle the wait for 200us
* before reading the CLEANUP bit requirement. This will be fixed in
* QEMU and the RTL testbench. b/32338758
diff --git a/drivers/misc/paintbox/paintbox-mmu.c b/drivers/misc/paintbox/paintbox-mmu.c
index 5602b10..5f2971d 100644
--- a/drivers/misc/paintbox/paintbox-mmu.c
+++ b/drivers/misc/paintbox/paintbox-mmu.c
@@ -34,23 +34,23 @@
#include "paintbox-regs.h"
/* Paintbox IO virtual address space bounds
- * TODO(ahampson): These are place holder values. I need to figure out the
+ * TODO: These are place holder values. I need to figure out the
* correct value for these. This comes out to 512MB right now.
*/
#define PAINTBOX_IOVA_START 0x20000000
#define PAINTBOX_IOVA_SIZE 0x40000000
-/* TOOD(ahampson): The error base is specific to the platform and should
+/* TOOD: The error base is specific to the platform and should
* be passed in through the platform data.
*/
#define PAINTBOX_ERROR_BASE 0x8000000000
-/* TODO(ahampson): Figure out if there is a way to get this information from
+/* TODO: Figure out if there is a way to get this information from
* the system.
*/
#define PAINTBOX_INPUT_ADDR_SIZE 43 /* bits */
-/* TODO(ahampson): This will need to be configurable. The output address size
+/* TODO: This will need to be configurable. The output address size
* on Easel will be 32 bits but on a normal system it will be 40 bits.
*/
#define PAINTBOX_OUTPUT_ADDR_SIZE 32 /* bits */
@@ -175,7 +175,7 @@
*/
dma_report_error_all_channels(pb, -ENOTRECOVERABLE);
- /* TODO(ahampson): Initiate a reset of the IPU and block new operations
+ /* TODO: Initiate a reset of the IPU and block new operations
* until the IPU comes out of reset. As part of the reset process any
* MIPI or STP waiters should be released. b/34518459
*/
@@ -208,7 +208,7 @@
*/
dma_report_error_all_channels(pb, -ENOTRECOVERABLE);
- /* TODO(ahampson): Initiate a reset of the IPU and block new operations
+ /* TODO: Initiate a reset of the IPU and block new operations
* until the IPU comes out of reset. As part of the reset process any
* MIPI or STP waiters should be released. b/34518459
*/
@@ -241,7 +241,7 @@
*/
dma_report_error_all_channels(pb, -ENOTRECOVERABLE);
- /* TODO(ahampson): Initiate a reset of the IPU and block new operations
+ /* TODO: Initiate a reset of the IPU and block new operations
* until the IPU comes out of reset. As part of the reset process any
* MIPI or STP waiters should be released. b/34518459
*/
@@ -324,7 +324,7 @@
paintbox_disable_mmu_bif_idle_clock_gating(pb);
#endif
- /* TODO(ahampson): There is no field bit defined for MMU_SYNC so we
+ /* TODO: There is no field bit defined for MMU_SYNC so we
* just write a 1 into the register in the interim.
*/
writel(0x01, pb->io.axi_base + MMU_SYNC);
@@ -333,7 +333,7 @@
dev_err(&pb->pdev->dev,
"%s: timeout waiting for MMU sync\n",
__func__);
- /* TODO(ahampson): A proper recovery path for a sync
+ /* TODO: A proper recovery path for a sync
* timeout should be developed for this case.
* b/35470877
*/
@@ -366,7 +366,7 @@
dev_err(&pb->pdev->dev,
"%s: timeout waiting for flush "
"FIFO to clear\n", __func__);
- /* TODO(ahampson): A proper recovery path for a
+ /* TODO: A proper recovery path for a
* flush FIFO timeout should be developed for
* this case. b/35470877
*/
@@ -406,7 +406,7 @@
dev_err(&pb->pdev->dev,
"%s: timeout waiting for flush "
"FIFO to clear\n", __func__);
- /* TODO(ahampson): A proper recovery path for a
+ /* TODO: A proper recovery path for a
* flush FIFO timeout should be developed for
* this case. b/35470877
*/
@@ -526,7 +526,7 @@
iommu_dev->platform_data = pdata;
iommu_dev->bus = &paintbox_bus_type;
- /* TODO(ahampson): Look for a better way to do this. Normally it is
+ /* TODO: Look for a better way to do this. Normally it is
* done in OF but since we are manually constructing the IOMMU device we
* need to do it here.
*/
diff --git a/drivers/misc/paintbox/paintbox-pmon.c b/drivers/misc/paintbox/paintbox-pmon.c
index 2665a0d..b02e6cd 100644
--- a/drivers/misc/paintbox/paintbox-pmon.c
+++ b/drivers/misc/paintbox/paintbox-pmon.c
@@ -35,7 +35,7 @@
/* returns the number of counters for block type |block| */
static int pmon_num_counters_in_block(enum pmon_block_type block)
{
- /* TODO(vharron) query from hardware */
+ /* TODO query from hardware */
if (block == PMON_BLOCK_DMA)
return DMA_PMON_COUNTERS;
return DEFAULT_PMON_COUNTERS;
diff --git a/drivers/misc/paintbox/paintbox-power.c b/drivers/misc/paintbox/paintbox-power.c
index cd31fe4..a133919 100644
--- a/drivers/misc/paintbox/paintbox-power.c
+++ b/drivers/misc/paintbox/paintbox-power.c
@@ -630,7 +630,7 @@
spin_lock_init(&pb->power.power_lock);
- /* TODO(ahampson): Add support for debugfs entry that allows a user to
+ /* TODO: Add support for debugfs entry that allows a user to
* force a certain number of active cores. b/62352592
*/
diff --git a/drivers/misc/paintbox/paintbox-regs-v1-generated.h b/drivers/misc/paintbox/paintbox-regs-v1-generated.h
deleted file mode 100644
index 7f33e40..0000000
--- a/drivers/misc/paintbox/paintbox-regs-v1-generated.h
+++ /dev/null
@@ -1,3690 +0,0 @@
-
-/*
- * Register definitions for the Paintbox programmable IPU
- *
- * Copyright (C) 2017 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
- /* This file is generated from RTL, do not hand edit. */
-#ifndef __PAINTBOX_REGS_V1_GENERATED_H__
-#define __PAINTBOX_REGS_V1_GENERATED_H__
-
-/* Date created: Sun May 28 17:45:45 2017 */
-/* Git commit: b9570349f */
-/* Cfg: canvas.cfg */
-
-/* Register Group Offsets */
-#define IPU_CSR_AON_OFFSET 0x0
-#define IPU_CSR_APB_OFFSET 0x400
-#define IPU_CSR_AXI_OFFSET 0x800
-#define IPU_CSR_IO_OFFSET 0xc00
-#define IPU_CSR_DMA_OFFSET 0x1000
-#define IPU_CSR_STP_OFFSET 0x1400
-#define IPU_CSR_LBP_OFFSET 0x1800
-#define IPU_CSR_ADP_OFFSET 0x1c00
-
-
-/* Module : IPU_LIB_DREGFILE_AON*/
-#define IPU_VERSION 0x0
-#define IPU_VERSION_DEF 0x1000000
-#define IPU_VERSION_MINOR_M 0xffULL
-#define IPU_VERSION_MINOR_SHIFT 8
-#define IPU_VERSION_MINOR_MASK (IPU_VERSION_MINOR_M << IPU_VERSION_MINOR_SHIFT)
-#define IPU_VERSION_MAJOR_M 0xffULL
-#define IPU_VERSION_MAJOR_SHIFT 24
-#define IPU_VERSION_MAJOR_MASK (IPU_VERSION_MAJOR_M << IPU_VERSION_MAJOR_SHIFT)
-#define IPU_VERSION_INCR_M 0xffULL
-#define IPU_VERSION_INCR_SHIFT 0
-#define IPU_VERSION_INCR_MASK (IPU_VERSION_INCR_M << IPU_VERSION_INCR_SHIFT)
-#define IPU_VERSION_FPGA_BUILD_M 0x1ULL
-#define IPU_VERSION_FPGA_BUILD_SHIFT 23
-#define IPU_VERSION_FPGA_BUILD_MASK (IPU_VERSION_FPGA_BUILD_M << IPU_VERSION_FPGA_BUILD_SHIFT)
-#define IPU_CHECKSUM 0x8
-#define IPU_CHECKSUM_DEF 0x2e0a643b2a008ee8
-#define IPU_CHECKSUM_HIGH_M 0xffffffffULL
-#define IPU_CHECKSUM_HIGH_SHIFT 32
-#define IPU_CHECKSUM_HIGH_MASK (IPU_CHECKSUM_HIGH_M << IPU_CHECKSUM_HIGH_SHIFT)
-#define IPU_CHECKSUM_LOW_M 0xffffffffULL
-#define IPU_CHECKSUM_LOW_SHIFT 0
-#define IPU_CHECKSUM_LOW_MASK (IPU_CHECKSUM_LOW_M << IPU_CHECKSUM_LOW_SHIFT)
-#define IPU_CAP 0x10
-#define IPU_CAP_DEF 0x908
-#define IPU_CAP_NUM_LBP_M 0xffULL
-#define IPU_CAP_NUM_LBP_SHIFT 8
-#define IPU_CAP_NUM_LBP_MASK (IPU_CAP_NUM_LBP_M << IPU_CAP_NUM_LBP_SHIFT)
-#define IPU_CAP_NUM_STP_M 0xffULL
-#define IPU_CAP_NUM_STP_SHIFT 0
-#define IPU_CAP_NUM_STP_MASK (IPU_CAP_NUM_STP_M << IPU_CAP_NUM_STP_SHIFT)
-#define CLK_GATE_CONTROL_STP_IDLE_GATE_DIS 0x18
-#define CLK_GATE_CONTROL_STP_IDLE_GATE_DIS_DEF 0xff
-#define CLK_GATE_CONTROL_LBP_IDLE_GATE_DIS 0x20
-#define CLK_GATE_CONTROL_LBP_IDLE_GATE_DIS_DEF 0x1ff
-#define CLK_GATE_CONTROL 0x28
-#define CLK_GATE_CONTROL_DEF 0xf
-#define CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_M 0x1ULL
-#define CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_SHIFT 3
-#define CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_MASK (CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_M << CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_SHIFT)
-#define CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_M 0x1ULL
-#define CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_SHIFT 2
-#define CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_MASK (CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_M << CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_SHIFT)
-#define CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_M 0x1ULL
-#define CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_SHIFT 1
-#define CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_MASK (CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_M << CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_SHIFT)
-#define CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_M 0x1ULL
-#define CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_SHIFT 0
-#define CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_MASK (CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_M << CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_SHIFT)
-#define IDLE_CLK_COUNT 0x30
-#define IDLE_CLK_COUNT_DEF 0xf0f0f0f0f0f0f
-#define IDLE_CLK_COUNT_BIF_COUNT_M 0x3fULL
-#define IDLE_CLK_COUNT_BIF_COUNT_SHIFT 16
-#define IDLE_CLK_COUNT_BIF_COUNT_MASK (IDLE_CLK_COUNT_BIF_COUNT_M << IDLE_CLK_COUNT_BIF_COUNT_SHIFT)
-#define IDLE_CLK_COUNT_DMA_COUNT_M 0x3fULL
-#define IDLE_CLK_COUNT_DMA_COUNT_SHIFT 0
-#define IDLE_CLK_COUNT_DMA_COUNT_MASK (IDLE_CLK_COUNT_DMA_COUNT_M << IDLE_CLK_COUNT_DMA_COUNT_SHIFT)
-#define IDLE_CLK_COUNT_STP_COUNT_M 0x3fULL
-#define IDLE_CLK_COUNT_STP_COUNT_SHIFT 48
-#define IDLE_CLK_COUNT_STP_COUNT_MASK (IDLE_CLK_COUNT_STP_COUNT_M << IDLE_CLK_COUNT_STP_COUNT_SHIFT)
-#define IDLE_CLK_COUNT_LBP_COUNT_M 0x3fULL
-#define IDLE_CLK_COUNT_LBP_COUNT_SHIFT 40
-#define IDLE_CLK_COUNT_LBP_COUNT_MASK (IDLE_CLK_COUNT_LBP_COUNT_M << IDLE_CLK_COUNT_LBP_COUNT_SHIFT)
-#define IDLE_CLK_COUNT_MIF_COUNT_M 0x3fULL
-#define IDLE_CLK_COUNT_MIF_COUNT_SHIFT 32
-#define IDLE_CLK_COUNT_MIF_COUNT_MASK (IDLE_CLK_COUNT_MIF_COUNT_M << IDLE_CLK_COUNT_MIF_COUNT_SHIFT)
-#define IDLE_CLK_COUNT_MMU_COUNT_M 0x3fULL
-#define IDLE_CLK_COUNT_MMU_COUNT_SHIFT 8
-#define IDLE_CLK_COUNT_MMU_COUNT_MASK (IDLE_CLK_COUNT_MMU_COUNT_M << IDLE_CLK_COUNT_MMU_COUNT_SHIFT)
-#define IDLE_CLK_COUNT_SSP_COUNT_M 0x3fULL
-#define IDLE_CLK_COUNT_SSP_COUNT_SHIFT 24
-#define IDLE_CLK_COUNT_SSP_COUNT_MASK (IDLE_CLK_COUNT_SSP_COUNT_M << IDLE_CLK_COUNT_SSP_COUNT_SHIFT)
-#define IPU_CORE_PAIRS_EN 0x38
-#define IPU_CORE_PAIRS_EN_DEF 0x0
-#define IPU_DMA_CHAN_EN 0x40
-#define IPU_DMA_CHAN_EN_DEF 0x0
-#define IPU_MIF_CLK_EN 0x48
-#define IPU_MIF_CLK_EN_DEF 0x0
-#define IPU_MIF_CLK_EN_MPO_M 0x3ULL
-#define IPU_MIF_CLK_EN_MPO_SHIFT 3
-#define IPU_MIF_CLK_EN_MPO_MASK (IPU_MIF_CLK_EN_MPO_M << IPU_MIF_CLK_EN_MPO_SHIFT)
-#define IPU_MIF_CLK_EN_MPI_M 0x7ULL
-#define IPU_MIF_CLK_EN_MPI_SHIFT 0
-#define IPU_MIF_CLK_EN_MPI_MASK (IPU_MIF_CLK_EN_MPI_M << IPU_MIF_CLK_EN_MPI_SHIFT)
-#define CORE_POWER_ON_N 0x50
-#define CORE_POWER_ON_N_DEF 0xff
-#define CORE_ISO_ON 0x58
-#define CORE_ISO_ON_DEF 0xff
-#define CORE_RAM_ON_N 0x60
-#define CORE_RAM_ON_N_DEF 0xff
-#define IO_POWER_ON_N 0x68
-#define IO_POWER_ON_N_DEF 0x1
-#define IO_ISO_ON 0x70
-#define IO_ISO_ON_DEF 0x1
-#define IO_RAM_ON_N 0x78
-#define IO_RAM_ON_N_DEF 0x1
-#define SOFT_RESET 0x80
-#define SOFT_RESET_DEF 0x0
-#define SOFT_RESET_IPU_M 0x1ULL
-#define SOFT_RESET_IPU_SHIFT 0
-#define SOFT_RESET_IPU_MASK (SOFT_RESET_IPU_M << SOFT_RESET_IPU_SHIFT)
-#define AON_SPARE 0x88
-#define AON_SPARE_DEF 0x0
-#define AON_SPARE_SPARE15_M 0x1ULL
-#define AON_SPARE_SPARE15_SHIFT 15
-#define AON_SPARE_SPARE15_MASK (AON_SPARE_SPARE15_M << AON_SPARE_SPARE15_SHIFT)
-#define AON_SPARE_SPARE11_M 0x1ULL
-#define AON_SPARE_SPARE11_SHIFT 11
-#define AON_SPARE_SPARE11_MASK (AON_SPARE_SPARE11_M << AON_SPARE_SPARE11_SHIFT)
-#define AON_SPARE_SPARE12_M 0x1ULL
-#define AON_SPARE_SPARE12_SHIFT 12
-#define AON_SPARE_SPARE12_MASK (AON_SPARE_SPARE12_M << AON_SPARE_SPARE12_SHIFT)
-#define AON_SPARE_SPARE14_M 0x1ULL
-#define AON_SPARE_SPARE14_SHIFT 14
-#define AON_SPARE_SPARE14_MASK (AON_SPARE_SPARE14_M << AON_SPARE_SPARE14_SHIFT)
-#define AON_SPARE_SPARE13_M 0x1ULL
-#define AON_SPARE_SPARE13_SHIFT 13
-#define AON_SPARE_SPARE13_MASK (AON_SPARE_SPARE13_M << AON_SPARE_SPARE13_SHIFT)
-#define AON_SPARE_SPARE8_M 0x1ULL
-#define AON_SPARE_SPARE8_SHIFT 8
-#define AON_SPARE_SPARE8_MASK (AON_SPARE_SPARE8_M << AON_SPARE_SPARE8_SHIFT)
-#define AON_SPARE_SPARE9_M 0x1ULL
-#define AON_SPARE_SPARE9_SHIFT 9
-#define AON_SPARE_SPARE9_MASK (AON_SPARE_SPARE9_M << AON_SPARE_SPARE9_SHIFT)
-#define AON_SPARE_SPARE10_M 0x1ULL
-#define AON_SPARE_SPARE10_SHIFT 10
-#define AON_SPARE_SPARE10_MASK (AON_SPARE_SPARE10_M << AON_SPARE_SPARE10_SHIFT)
-#define AON_SPARE_SPARE4_M 0x1ULL
-#define AON_SPARE_SPARE4_SHIFT 4
-#define AON_SPARE_SPARE4_MASK (AON_SPARE_SPARE4_M << AON_SPARE_SPARE4_SHIFT)
-#define AON_SPARE_SPARE5_M 0x1ULL
-#define AON_SPARE_SPARE5_SHIFT 5
-#define AON_SPARE_SPARE5_MASK (AON_SPARE_SPARE5_M << AON_SPARE_SPARE5_SHIFT)
-#define AON_SPARE_SPARE6_M 0x1ULL
-#define AON_SPARE_SPARE6_SHIFT 6
-#define AON_SPARE_SPARE6_MASK (AON_SPARE_SPARE6_M << AON_SPARE_SPARE6_SHIFT)
-#define AON_SPARE_SPARE7_M 0x1ULL
-#define AON_SPARE_SPARE7_SHIFT 7
-#define AON_SPARE_SPARE7_MASK (AON_SPARE_SPARE7_M << AON_SPARE_SPARE7_SHIFT)
-#define AON_SPARE_SPARE0_M 0x1ULL
-#define AON_SPARE_SPARE0_SHIFT 0
-#define AON_SPARE_SPARE0_MASK (AON_SPARE_SPARE0_M << AON_SPARE_SPARE0_SHIFT)
-#define AON_SPARE_SPARE1_M 0x1ULL
-#define AON_SPARE_SPARE1_SHIFT 1
-#define AON_SPARE_SPARE1_MASK (AON_SPARE_SPARE1_M << AON_SPARE_SPARE1_SHIFT)
-#define AON_SPARE_SPARE2_M 0x1ULL
-#define AON_SPARE_SPARE2_SHIFT 2
-#define AON_SPARE_SPARE2_MASK (AON_SPARE_SPARE2_M << AON_SPARE_SPARE2_SHIFT)
-#define AON_SPARE_SPARE3_M 0x1ULL
-#define AON_SPARE_SPARE3_SHIFT 3
-#define AON_SPARE_SPARE3_MASK (AON_SPARE_SPARE3_M << AON_SPARE_SPARE3_SHIFT)
-
-/* Module : IPU_LIB_DREGFILE_APB*/
-#define IPU_ISR 0x0
-#define IPU_ISR_DEF 0x0
-#define IPU_ISR_DMA_ERR_INTR_M 0x1ULL
-#define IPU_ISR_DMA_ERR_INTR_SHIFT 16
-#define IPU_ISR_DMA_ERR_INTR_MASK (IPU_ISR_DMA_ERR_INTR_M << IPU_ISR_DMA_ERR_INTR_SHIFT)
-#define IPU_ISR_DMA_CHAN_INTR_M 0xffffULL
-#define IPU_ISR_DMA_CHAN_INTR_SHIFT 0
-#define IPU_ISR_DMA_CHAN_INTR_MASK (IPU_ISR_DMA_CHAN_INTR_M << IPU_ISR_DMA_CHAN_INTR_SHIFT)
-#define IPU_ISR_STP_INTR_M 0xffULL
-#define IPU_ISR_STP_INTR_SHIFT 32
-#define IPU_ISR_STP_INTR_MASK (IPU_ISR_STP_INTR_M << IPU_ISR_STP_INTR_SHIFT)
-#define IPU_ISR_MIF_INTR_M 0x1fULL
-#define IPU_ISR_MIF_INTR_SHIFT 50
-#define IPU_ISR_MIF_INTR_MASK (IPU_ISR_MIF_INTR_M << IPU_ISR_MIF_INTR_SHIFT)
-#define IPU_ISR_MMU_INTR_M 0x1ULL
-#define IPU_ISR_MMU_INTR_SHIFT 18
-#define IPU_ISR_MMU_INTR_MASK (IPU_ISR_MMU_INTR_M << IPU_ISR_MMU_INTR_SHIFT)
-#define IPU_ISR_STP_GRP_INTR_M 0x1ULL
-#define IPU_ISR_STP_GRP_INTR_SHIFT 49
-#define IPU_ISR_STP_GRP_INTR_MASK (IPU_ISR_STP_GRP_INTR_M << IPU_ISR_STP_GRP_INTR_SHIFT)
-#define IPU_ISR_BIF_INTR_M 0x1ULL
-#define IPU_ISR_BIF_INTR_SHIFT 17
-#define IPU_ISR_BIF_INTR_MASK (IPU_ISR_BIF_INTR_M << IPU_ISR_BIF_INTR_SHIFT)
-#define IPU_ISR_MIF_ERR_INTR_M 0x1ULL
-#define IPU_ISR_MIF_ERR_INTR_SHIFT 55
-#define IPU_ISR_MIF_ERR_INTR_MASK (IPU_ISR_MIF_ERR_INTR_M << IPU_ISR_MIF_ERR_INTR_SHIFT)
-#define IPU_ISR_STP_ERR_INTR_M 0x1ULL
-#define IPU_ISR_STP_ERR_INTR_SHIFT 48
-#define IPU_ISR_STP_ERR_INTR_MASK (IPU_ISR_STP_ERR_INTR_M << IPU_ISR_STP_ERR_INTR_SHIFT)
-#define IPU_ITR 0x8
-#define IPU_ITR_DEF 0x0
-#define IPU_ITR_STP_GRP_INTR_M 0x1ULL
-#define IPU_ITR_STP_GRP_INTR_SHIFT 49
-#define IPU_ITR_STP_GRP_INTR_MASK (IPU_ITR_STP_GRP_INTR_M << IPU_ITR_STP_GRP_INTR_SHIFT)
-#define IPU_ITR_DMA_ERR_INTR_M 0x1ULL
-#define IPU_ITR_DMA_ERR_INTR_SHIFT 16
-#define IPU_ITR_DMA_ERR_INTR_MASK (IPU_ITR_DMA_ERR_INTR_M << IPU_ITR_DMA_ERR_INTR_SHIFT)
-#define IPU_ITR_MIF_INTR_M 0x1fULL
-#define IPU_ITR_MIF_INTR_SHIFT 50
-#define IPU_ITR_MIF_INTR_MASK (IPU_ITR_MIF_INTR_M << IPU_ITR_MIF_INTR_SHIFT)
-#define IPU_ITR_MMU_INTR_M 0x1ULL
-#define IPU_ITR_MMU_INTR_SHIFT 18
-#define IPU_ITR_MMU_INTR_MASK (IPU_ITR_MMU_INTR_M << IPU_ITR_MMU_INTR_SHIFT)
-#define IPU_ITR_DMA_CHAN_INTR_M 0xffffULL
-#define IPU_ITR_DMA_CHAN_INTR_SHIFT 0
-#define IPU_ITR_DMA_CHAN_INTR_MASK (IPU_ITR_DMA_CHAN_INTR_M << IPU_ITR_DMA_CHAN_INTR_SHIFT)
-#define IPU_ITR_STP_ERR_INTR_M 0x1ULL
-#define IPU_ITR_STP_ERR_INTR_SHIFT 48
-#define IPU_ITR_STP_ERR_INTR_MASK (IPU_ITR_STP_ERR_INTR_M << IPU_ITR_STP_ERR_INTR_SHIFT)
-#define IPU_ITR_STP_INTR_M 0xffULL
-#define IPU_ITR_STP_INTR_SHIFT 32
-#define IPU_ITR_STP_INTR_MASK (IPU_ITR_STP_INTR_M << IPU_ITR_STP_INTR_SHIFT)
-#define IPU_ITR_BIF_INTR_M 0x1ULL
-#define IPU_ITR_BIF_INTR_SHIFT 17
-#define IPU_ITR_BIF_INTR_MASK (IPU_ITR_BIF_INTR_M << IPU_ITR_BIF_INTR_SHIFT)
-#define IPU_ITR_MIF_ERR_INTR_M 0x1ULL
-#define IPU_ITR_MIF_ERR_INTR_SHIFT 55
-#define IPU_ITR_MIF_ERR_INTR_MASK (IPU_ITR_MIF_ERR_INTR_M << IPU_ITR_MIF_ERR_INTR_SHIFT)
-#define IPU_IER 0x10
-#define IPU_IER_DEF 0xff00ff0007ffff
-#define IPU_IER_MIF_INTR_M 0x1fULL
-#define IPU_IER_MIF_INTR_SHIFT 50
-#define IPU_IER_MIF_INTR_MASK (IPU_IER_MIF_INTR_M << IPU_IER_MIF_INTR_SHIFT)
-#define IPU_IER_BIF_INTR_M 0x1ULL
-#define IPU_IER_BIF_INTR_SHIFT 17
-#define IPU_IER_BIF_INTR_MASK (IPU_IER_BIF_INTR_M << IPU_IER_BIF_INTR_SHIFT)
-#define IPU_IER_STP_INTR_M 0xffULL
-#define IPU_IER_STP_INTR_SHIFT 32
-#define IPU_IER_STP_INTR_MASK (IPU_IER_STP_INTR_M << IPU_IER_STP_INTR_SHIFT)
-#define IPU_IER_DMA_CHAN_INTR_M 0xffffULL
-#define IPU_IER_DMA_CHAN_INTR_SHIFT 0
-#define IPU_IER_DMA_CHAN_INTR_MASK (IPU_IER_DMA_CHAN_INTR_M << IPU_IER_DMA_CHAN_INTR_SHIFT)
-#define IPU_IER_MMU_INTR_M 0x1ULL
-#define IPU_IER_MMU_INTR_SHIFT 18
-#define IPU_IER_MMU_INTR_MASK (IPU_IER_MMU_INTR_M << IPU_IER_MMU_INTR_SHIFT)
-#define IPU_IER_STP_ERR_INTR_M 0x1ULL
-#define IPU_IER_STP_ERR_INTR_SHIFT 48
-#define IPU_IER_STP_ERR_INTR_MASK (IPU_IER_STP_ERR_INTR_M << IPU_IER_STP_ERR_INTR_SHIFT)
-#define IPU_IER_MIF_ERR_INTR_M 0x1ULL
-#define IPU_IER_MIF_ERR_INTR_SHIFT 55
-#define IPU_IER_MIF_ERR_INTR_MASK (IPU_IER_MIF_ERR_INTR_M << IPU_IER_MIF_ERR_INTR_SHIFT)
-#define IPU_IER_STP_GRP_INTR_M 0x1ULL
-#define IPU_IER_STP_GRP_INTR_SHIFT 49
-#define IPU_IER_STP_GRP_INTR_MASK (IPU_IER_STP_GRP_INTR_M << IPU_IER_STP_GRP_INTR_SHIFT)
-#define IPU_IER_DMA_ERR_INTR_M 0x1ULL
-#define IPU_IER_DMA_ERR_INTR_SHIFT 16
-#define IPU_IER_DMA_ERR_INTR_MASK (IPU_IER_DMA_ERR_INTR_M << IPU_IER_DMA_ERR_INTR_SHIFT)
-#define IPU_IMR 0x18
-#define IPU_IMR_DEF 0x0
-#define IPU_IMR_BIF_INTR_M 0x1ULL
-#define IPU_IMR_BIF_INTR_SHIFT 17
-#define IPU_IMR_BIF_INTR_MASK (IPU_IMR_BIF_INTR_M << IPU_IMR_BIF_INTR_SHIFT)
-#define IPU_IMR_MIF_ERR_INTR_M 0x1ULL
-#define IPU_IMR_MIF_ERR_INTR_SHIFT 55
-#define IPU_IMR_MIF_ERR_INTR_MASK (IPU_IMR_MIF_ERR_INTR_M << IPU_IMR_MIF_ERR_INTR_SHIFT)
-#define IPU_IMR_STP_GRP_INTR_M 0x1ULL
-#define IPU_IMR_STP_GRP_INTR_SHIFT 49
-#define IPU_IMR_STP_GRP_INTR_MASK (IPU_IMR_STP_GRP_INTR_M << IPU_IMR_STP_GRP_INTR_SHIFT)
-#define IPU_IMR_MMU_INTR_M 0x1ULL
-#define IPU_IMR_MMU_INTR_SHIFT 18
-#define IPU_IMR_MMU_INTR_MASK (IPU_IMR_MMU_INTR_M << IPU_IMR_MMU_INTR_SHIFT)
-#define IPU_IMR_DMA_ERR_INTR_M 0x1ULL
-#define IPU_IMR_DMA_ERR_INTR_SHIFT 16
-#define IPU_IMR_DMA_ERR_INTR_MASK (IPU_IMR_DMA_ERR_INTR_M << IPU_IMR_DMA_ERR_INTR_SHIFT)
-#define IPU_IMR_STP_INTR_M 0xffULL
-#define IPU_IMR_STP_INTR_SHIFT 32
-#define IPU_IMR_STP_INTR_MASK (IPU_IMR_STP_INTR_M << IPU_IMR_STP_INTR_SHIFT)
-#define IPU_IMR_DMA_CHAN_INTR_M 0xffffULL
-#define IPU_IMR_DMA_CHAN_INTR_SHIFT 0
-#define IPU_IMR_DMA_CHAN_INTR_MASK (IPU_IMR_DMA_CHAN_INTR_M << IPU_IMR_DMA_CHAN_INTR_SHIFT)
-#define IPU_IMR_MIF_INTR_M 0x1fULL
-#define IPU_IMR_MIF_INTR_SHIFT 50
-#define IPU_IMR_MIF_INTR_MASK (IPU_IMR_MIF_INTR_M << IPU_IMR_MIF_INTR_SHIFT)
-#define IPU_IMR_STP_ERR_INTR_M 0x1ULL
-#define IPU_IMR_STP_ERR_INTR_SHIFT 48
-#define IPU_IMR_STP_ERR_INTR_MASK (IPU_IMR_STP_ERR_INTR_M << IPU_IMR_STP_ERR_INTR_SHIFT)
-#define DMA_ERR_ISR 0x20
-#define DMA_ERR_ISR_DEF 0x0
-#define DMA_ERR_ISR_DMA_CHAN_ERR_M 0xffffULL
-#define DMA_ERR_ISR_DMA_CHAN_ERR_SHIFT 0
-#define DMA_ERR_ISR_DMA_CHAN_ERR_MASK (DMA_ERR_ISR_DMA_CHAN_ERR_M << DMA_ERR_ISR_DMA_CHAN_ERR_SHIFT)
-#define DMA_ERR_ITR 0x28
-#define DMA_ERR_ITR_DEF 0x0
-#define DMA_ERR_ITR_DMA_CHAN_ERR_M 0xffffULL
-#define DMA_ERR_ITR_DMA_CHAN_ERR_SHIFT 0
-#define DMA_ERR_ITR_DMA_CHAN_ERR_MASK (DMA_ERR_ITR_DMA_CHAN_ERR_M << DMA_ERR_ITR_DMA_CHAN_ERR_SHIFT)
-#define DMA_ERR_IER 0x30
-#define DMA_ERR_IER_DEF 0xffff
-#define DMA_ERR_IER_DMA_CHAN_ERR_M 0xffffULL
-#define DMA_ERR_IER_DMA_CHAN_ERR_SHIFT 0
-#define DMA_ERR_IER_DMA_CHAN_ERR_MASK (DMA_ERR_IER_DMA_CHAN_ERR_M << DMA_ERR_IER_DMA_CHAN_ERR_SHIFT)
-#define DMA_ERR_IMR 0x38
-#define DMA_ERR_IMR_DEF 0x0
-#define DMA_ERR_IMR_DMA_CHAN_ERR_M 0xffffULL
-#define DMA_ERR_IMR_DMA_CHAN_ERR_SHIFT 0
-#define DMA_ERR_IMR_DMA_CHAN_ERR_MASK (DMA_ERR_IMR_DMA_CHAN_ERR_M << DMA_ERR_IMR_DMA_CHAN_ERR_SHIFT)
-#define STP_ERR_ISR 0x40
-#define STP_ERR_ISR_DEF 0x0
-#define STP_ERR_ISR_STP_ERR_M 0xffULL
-#define STP_ERR_ISR_STP_ERR_SHIFT 0
-#define STP_ERR_ISR_STP_ERR_MASK (STP_ERR_ISR_STP_ERR_M << STP_ERR_ISR_STP_ERR_SHIFT)
-#define STP_ERR_ITR 0x48
-#define STP_ERR_ITR_DEF 0x0
-#define STP_ERR_ITR_STP_ERR_M 0xffULL
-#define STP_ERR_ITR_STP_ERR_SHIFT 0
-#define STP_ERR_ITR_STP_ERR_MASK (STP_ERR_ITR_STP_ERR_M << STP_ERR_ITR_STP_ERR_SHIFT)
-#define STP_ERR_IER 0x50
-#define STP_ERR_IER_DEF 0xff
-#define STP_ERR_IER_STP_ERR_M 0xffULL
-#define STP_ERR_IER_STP_ERR_SHIFT 0
-#define STP_ERR_IER_STP_ERR_MASK (STP_ERR_IER_STP_ERR_M << STP_ERR_IER_STP_ERR_SHIFT)
-#define STP_ERR_IMR 0x58
-#define STP_ERR_IMR_DEF 0x0
-#define STP_ERR_IMR_STP_ERR_M 0xffULL
-#define STP_ERR_IMR_STP_ERR_SHIFT 0
-#define STP_ERR_IMR_STP_ERR_MASK (STP_ERR_IMR_STP_ERR_M << STP_ERR_IMR_STP_ERR_SHIFT)
-#define MIF_ERR_ISR 0x60
-#define MIF_ERR_ISR_DEF 0x0
-#define MIF_ERR_ISR_MIF_ERR_M 0x7ULL
-#define MIF_ERR_ISR_MIF_ERR_SHIFT 0
-#define MIF_ERR_ISR_MIF_ERR_MASK (MIF_ERR_ISR_MIF_ERR_M << MIF_ERR_ISR_MIF_ERR_SHIFT)
-#define MIF_ERR_ITR 0x68
-#define MIF_ERR_ITR_DEF 0x0
-#define MIF_ERR_ITR_MIF_ERR_M 0x7ULL
-#define MIF_ERR_ITR_MIF_ERR_SHIFT 0
-#define MIF_ERR_ITR_MIF_ERR_MASK (MIF_ERR_ITR_MIF_ERR_M << MIF_ERR_ITR_MIF_ERR_SHIFT)
-#define MIF_ERR_IER 0x70
-#define MIF_ERR_IER_DEF 0x7
-#define MIF_ERR_IER_MIF_ERR_M 0x7ULL
-#define MIF_ERR_IER_MIF_ERR_SHIFT 0
-#define MIF_ERR_IER_MIF_ERR_MASK (MIF_ERR_IER_MIF_ERR_M << MIF_ERR_IER_MIF_ERR_SHIFT)
-#define MIF_ERR_IMR 0x78
-#define MIF_ERR_IMR_DEF 0x0
-#define MIF_ERR_IMR_MIF_ERR_M 0x7ULL
-#define MIF_ERR_IMR_MIF_ERR_SHIFT 0
-#define MIF_ERR_IMR_MIF_ERR_MASK (MIF_ERR_IMR_MIF_ERR_M << MIF_ERR_IMR_MIF_ERR_SHIFT)
-#define IPU_STP_GRP_SEL 0x80
-#define IPU_STP_GRP_SEL_DEF 0x0
-#define IPU_STP_GRP_SEL_MASK_M 0xffULL
-#define IPU_STP_GRP_SEL_MASK_SHIFT 0
-#define IPU_STP_GRP_SEL_MASK_MASK (IPU_STP_GRP_SEL_MASK_M << IPU_STP_GRP_SEL_MASK_SHIFT)
-#define APB_SPARE 0x88
-#define APB_SPARE_DEF 0x0
-#define APB_SPARE_SPARE0_M 0x1ULL
-#define APB_SPARE_SPARE0_SHIFT 0
-#define APB_SPARE_SPARE0_MASK (APB_SPARE_SPARE0_M << APB_SPARE_SPARE0_SHIFT)
-#define APB_SPARE_SPARE1_M 0x1ULL
-#define APB_SPARE_SPARE1_SHIFT 1
-#define APB_SPARE_SPARE1_MASK (APB_SPARE_SPARE1_M << APB_SPARE_SPARE1_SHIFT)
-#define APB_SPARE_SPARE2_M 0x1ULL
-#define APB_SPARE_SPARE2_SHIFT 2
-#define APB_SPARE_SPARE2_MASK (APB_SPARE_SPARE2_M << APB_SPARE_SPARE2_SHIFT)
-#define APB_SPARE_SPARE3_M 0x1ULL
-#define APB_SPARE_SPARE3_SHIFT 3
-#define APB_SPARE_SPARE3_MASK (APB_SPARE_SPARE3_M << APB_SPARE_SPARE3_SHIFT)
-#define APB_SPARE_SPARE4_M 0x1ULL
-#define APB_SPARE_SPARE4_SHIFT 4
-#define APB_SPARE_SPARE4_MASK (APB_SPARE_SPARE4_M << APB_SPARE_SPARE4_SHIFT)
-#define APB_SPARE_SPARE5_M 0x1ULL
-#define APB_SPARE_SPARE5_SHIFT 5
-#define APB_SPARE_SPARE5_MASK (APB_SPARE_SPARE5_M << APB_SPARE_SPARE5_SHIFT)
-#define APB_SPARE_SPARE6_M 0x1ULL
-#define APB_SPARE_SPARE6_SHIFT 6
-#define APB_SPARE_SPARE6_MASK (APB_SPARE_SPARE6_M << APB_SPARE_SPARE6_SHIFT)
-#define APB_SPARE_SPARE7_M 0x1ULL
-#define APB_SPARE_SPARE7_SHIFT 7
-#define APB_SPARE_SPARE7_MASK (APB_SPARE_SPARE7_M << APB_SPARE_SPARE7_SHIFT)
-#define APB_SPARE_SPARE8_M 0x1ULL
-#define APB_SPARE_SPARE8_SHIFT 8
-#define APB_SPARE_SPARE8_MASK (APB_SPARE_SPARE8_M << APB_SPARE_SPARE8_SHIFT)
-#define APB_SPARE_SPARE9_M 0x1ULL
-#define APB_SPARE_SPARE9_SHIFT 9
-#define APB_SPARE_SPARE9_MASK (APB_SPARE_SPARE9_M << APB_SPARE_SPARE9_SHIFT)
-#define APB_SPARE_SPARE12_M 0x1ULL
-#define APB_SPARE_SPARE12_SHIFT 12
-#define APB_SPARE_SPARE12_MASK (APB_SPARE_SPARE12_M << APB_SPARE_SPARE12_SHIFT)
-#define APB_SPARE_SPARE13_M 0x1ULL
-#define APB_SPARE_SPARE13_SHIFT 13
-#define APB_SPARE_SPARE13_MASK (APB_SPARE_SPARE13_M << APB_SPARE_SPARE13_SHIFT)
-#define APB_SPARE_SPARE10_M 0x1ULL
-#define APB_SPARE_SPARE10_SHIFT 10
-#define APB_SPARE_SPARE10_MASK (APB_SPARE_SPARE10_M << APB_SPARE_SPARE10_SHIFT)
-#define APB_SPARE_SPARE11_M 0x1ULL
-#define APB_SPARE_SPARE11_SHIFT 11
-#define APB_SPARE_SPARE11_MASK (APB_SPARE_SPARE11_M << APB_SPARE_SPARE11_SHIFT)
-#define APB_SPARE_SPARE14_M 0x1ULL
-#define APB_SPARE_SPARE14_SHIFT 14
-#define APB_SPARE_SPARE14_MASK (APB_SPARE_SPARE14_M << APB_SPARE_SPARE14_SHIFT)
-#define APB_SPARE_SPARE15_M 0x1ULL
-#define APB_SPARE_SPARE15_SHIFT 15
-#define APB_SPARE_SPARE15_MASK (APB_SPARE_SPARE15_M << APB_SPARE_SPARE15_SHIFT)
-
-/* Module : IPU_LIB_DREGFILE_AXI*/
-#define MMU_CTRL 0x0
-#define MMU_CTRL_DEF 0x2
-#define MMU_CTRL_MMU_ENABLE_M 0x1ULL
-#define MMU_CTRL_MMU_ENABLE_SHIFT 0
-#define MMU_CTRL_MMU_ENABLE_MASK (MMU_CTRL_MMU_ENABLE_M << MMU_CTRL_MMU_ENABLE_SHIFT)
-#define MMU_CTRL_PREFETCH_ENABLE_M 0x1ULL
-#define MMU_CTRL_PREFETCH_ENABLE_SHIFT 1
-#define MMU_CTRL_PREFETCH_ENABLE_MASK (MMU_CTRL_PREFETCH_ENABLE_M << MMU_CTRL_PREFETCH_ENABLE_SHIFT)
-#define MMU_CTRL_SINGLE_TWE_M 0x1ULL
-#define MMU_CTRL_SINGLE_TWE_SHIFT 2
-#define MMU_CTRL_SINGLE_TWE_MASK (MMU_CTRL_SINGLE_TWE_M << MMU_CTRL_SINGLE_TWE_SHIFT)
-#define MMU_TABLE_BASE 0x8
-#define MMU_TABLE_BASE_DEF 0x0
-#define MMU_TABLE_BASE_ADDR_M 0xffffULL
-#define MMU_TABLE_BASE_ADDR_SHIFT 4
-#define MMU_TABLE_BASE_ADDR_MASK (MMU_TABLE_BASE_ADDR_M << MMU_TABLE_BASE_ADDR_SHIFT)
-#define MMU_ERR_BASE 0x10
-#define MMU_ERR_BASE_DEF 0x0
-#define MMU_ERR_BASE_ADDR_M 0xfffffULL
-#define MMU_ERR_BASE_ADDR_SHIFT 0
-#define MMU_ERR_BASE_ADDR_MASK (MMU_ERR_BASE_ADDR_M << MMU_ERR_BASE_ADDR_SHIFT)
-#define MMU_SYNC 0x18
-#define MMU_SYNC_DEF 0x0
-#define MMU_FLUSH_CHANNEL 0x20
-#define MMU_FLUSH_CHANNEL_DEF 0x0
-#define MMU_FLUSH_ADDRESS 0x28
-#define MMU_FLUSH_ADDRESS_DEF 0x0
-#define MMU_FLUSH_FIFO_LEVEL 0x30
-#define MMU_FLUSH_FIFO_LEVEL_DEF 0x0
-#define MMU_FLUSH_FIFO_FULL 0x38
-#define MMU_FLUSH_FIFO_FULL_DEF 0x0
-#define MMU_ISR 0x40
-#define MMU_ISR_DEF 0x0
-#define MMU_ISR_FLUSH_MEMRD_ERR_M 0x1ULL
-#define MMU_ISR_FLUSH_MEMRD_ERR_SHIFT 4
-#define MMU_ISR_FLUSH_MEMRD_ERR_MASK (MMU_ISR_FLUSH_MEMRD_ERR_M << MMU_ISR_FLUSH_MEMRD_ERR_SHIFT)
-#define MMU_ISR_TWE_MEMRD_ERR_M 0x1ULL
-#define MMU_ISR_TWE_MEMRD_ERR_SHIFT 2
-#define MMU_ISR_TWE_MEMRD_ERR_MASK (MMU_ISR_TWE_MEMRD_ERR_M << MMU_ISR_TWE_MEMRD_ERR_SHIFT)
-#define MMU_ISR_FLUSH_FULL_ERR_M 0x1ULL
-#define MMU_ISR_FLUSH_FULL_ERR_SHIFT 6
-#define MMU_ISR_FLUSH_FULL_ERR_MASK (MMU_ISR_FLUSH_FULL_ERR_M << MMU_ISR_FLUSH_FULL_ERR_SHIFT)
-#define MMU_ISR_TWE_ACCESS_VIO_M 0x1ULL
-#define MMU_ISR_TWE_ACCESS_VIO_SHIFT 0
-#define MMU_ISR_TWE_ACCESS_VIO_MASK (MMU_ISR_TWE_ACCESS_VIO_M << MMU_ISR_TWE_ACCESS_VIO_SHIFT)
-#define MMU_ISR_PREFETCH_MEMRD_ERR_M 0x1ULL
-#define MMU_ISR_PREFETCH_MEMRD_ERR_SHIFT 5
-#define MMU_ISR_PREFETCH_MEMRD_ERR_MASK (MMU_ISR_PREFETCH_MEMRD_ERR_M << MMU_ISR_PREFETCH_MEMRD_ERR_SHIFT)
-#define MMU_ISR_TWE_INVALID_TABLE_M 0x1ULL
-#define MMU_ISR_TWE_INVALID_TABLE_SHIFT 1
-#define MMU_ISR_TWE_INVALID_TABLE_MASK (MMU_ISR_TWE_INVALID_TABLE_M << MMU_ISR_TWE_INVALID_TABLE_SHIFT)
-#define MMU_ISR_FLUSH_INVALID_TABLE_M 0x1ULL
-#define MMU_ISR_FLUSH_INVALID_TABLE_SHIFT 3
-#define MMU_ISR_FLUSH_INVALID_TABLE_MASK (MMU_ISR_FLUSH_INVALID_TABLE_M << MMU_ISR_FLUSH_INVALID_TABLE_SHIFT)
-#define MMU_ITR 0x48
-#define MMU_ITR_DEF 0x0
-#define MMU_ITR_TWE_ACCESS_VIO_M 0x1ULL
-#define MMU_ITR_TWE_ACCESS_VIO_SHIFT 0
-#define MMU_ITR_TWE_ACCESS_VIO_MASK (MMU_ITR_TWE_ACCESS_VIO_M << MMU_ITR_TWE_ACCESS_VIO_SHIFT)
-#define MMU_ITR_FLUSH_INVALID_TABLE_M 0x1ULL
-#define MMU_ITR_FLUSH_INVALID_TABLE_SHIFT 3
-#define MMU_ITR_FLUSH_INVALID_TABLE_MASK (MMU_ITR_FLUSH_INVALID_TABLE_M << MMU_ITR_FLUSH_INVALID_TABLE_SHIFT)
-#define MMU_ITR_TWE_MEMRD_ERR_M 0x1ULL
-#define MMU_ITR_TWE_MEMRD_ERR_SHIFT 2
-#define MMU_ITR_TWE_MEMRD_ERR_MASK (MMU_ITR_TWE_MEMRD_ERR_M << MMU_ITR_TWE_MEMRD_ERR_SHIFT)
-#define MMU_ITR_FLUSH_FULL_ERR_M 0x1ULL
-#define MMU_ITR_FLUSH_FULL_ERR_SHIFT 6
-#define MMU_ITR_FLUSH_FULL_ERR_MASK (MMU_ITR_FLUSH_FULL_ERR_M << MMU_ITR_FLUSH_FULL_ERR_SHIFT)
-#define MMU_ITR_PREFETCH_MEMRD_ERR_M 0x1ULL
-#define MMU_ITR_PREFETCH_MEMRD_ERR_SHIFT 5
-#define MMU_ITR_PREFETCH_MEMRD_ERR_MASK (MMU_ITR_PREFETCH_MEMRD_ERR_M << MMU_ITR_PREFETCH_MEMRD_ERR_SHIFT)
-#define MMU_ITR_FLUSH_MEMRD_ERR_M 0x1ULL
-#define MMU_ITR_FLUSH_MEMRD_ERR_SHIFT 4
-#define MMU_ITR_FLUSH_MEMRD_ERR_MASK (MMU_ITR_FLUSH_MEMRD_ERR_M << MMU_ITR_FLUSH_MEMRD_ERR_SHIFT)
-#define MMU_ITR_TWE_INVALID_TABLE_M 0x1ULL
-#define MMU_ITR_TWE_INVALID_TABLE_SHIFT 1
-#define MMU_ITR_TWE_INVALID_TABLE_MASK (MMU_ITR_TWE_INVALID_TABLE_M << MMU_ITR_TWE_INVALID_TABLE_SHIFT)
-#define MMU_IER 0x50
-#define MMU_IER_DEF 0x7f
-#define MMU_IER_TWE_INVALID_TABLE_M 0x1ULL
-#define MMU_IER_TWE_INVALID_TABLE_SHIFT 1
-#define MMU_IER_TWE_INVALID_TABLE_MASK (MMU_IER_TWE_INVALID_TABLE_M << MMU_IER_TWE_INVALID_TABLE_SHIFT)
-#define MMU_IER_FLUSH_FULL_ERR_M 0x1ULL
-#define MMU_IER_FLUSH_FULL_ERR_SHIFT 6
-#define MMU_IER_FLUSH_FULL_ERR_MASK (MMU_IER_FLUSH_FULL_ERR_M << MMU_IER_FLUSH_FULL_ERR_SHIFT)
-#define MMU_IER_TWE_MEMRD_ERR_M 0x1ULL
-#define MMU_IER_TWE_MEMRD_ERR_SHIFT 2
-#define MMU_IER_TWE_MEMRD_ERR_MASK (MMU_IER_TWE_MEMRD_ERR_M << MMU_IER_TWE_MEMRD_ERR_SHIFT)
-#define MMU_IER_TWE_ACCESS_VIO_M 0x1ULL
-#define MMU_IER_TWE_ACCESS_VIO_SHIFT 0
-#define MMU_IER_TWE_ACCESS_VIO_MASK (MMU_IER_TWE_ACCESS_VIO_M << MMU_IER_TWE_ACCESS_VIO_SHIFT)
-#define MMU_IER_FLUSH_MEMRD_ERR_M 0x1ULL
-#define MMU_IER_FLUSH_MEMRD_ERR_SHIFT 4
-#define MMU_IER_FLUSH_MEMRD_ERR_MASK (MMU_IER_FLUSH_MEMRD_ERR_M << MMU_IER_FLUSH_MEMRD_ERR_SHIFT)
-#define MMU_IER_FLUSH_INVALID_TABLE_M 0x1ULL
-#define MMU_IER_FLUSH_INVALID_TABLE_SHIFT 3
-#define MMU_IER_FLUSH_INVALID_TABLE_MASK (MMU_IER_FLUSH_INVALID_TABLE_M << MMU_IER_FLUSH_INVALID_TABLE_SHIFT)
-#define MMU_IER_PREFETCH_MEMRD_ERR_M 0x1ULL
-#define MMU_IER_PREFETCH_MEMRD_ERR_SHIFT 5
-#define MMU_IER_PREFETCH_MEMRD_ERR_MASK (MMU_IER_PREFETCH_MEMRD_ERR_M << MMU_IER_PREFETCH_MEMRD_ERR_SHIFT)
-#define MMU_IMR 0x58
-#define MMU_IMR_DEF 0x0
-#define MMU_IMR_PREFETCH_MEMRD_ERR_M 0x1ULL
-#define MMU_IMR_PREFETCH_MEMRD_ERR_SHIFT 5
-#define MMU_IMR_PREFETCH_MEMRD_ERR_MASK (MMU_IMR_PREFETCH_MEMRD_ERR_M << MMU_IMR_PREFETCH_MEMRD_ERR_SHIFT)
-#define MMU_IMR_TWE_ACCESS_VIO_M 0x1ULL
-#define MMU_IMR_TWE_ACCESS_VIO_SHIFT 0
-#define MMU_IMR_TWE_ACCESS_VIO_MASK (MMU_IMR_TWE_ACCESS_VIO_M << MMU_IMR_TWE_ACCESS_VIO_SHIFT)
-#define MMU_IMR_TWE_MEMRD_ERR_M 0x1ULL
-#define MMU_IMR_TWE_MEMRD_ERR_SHIFT 2
-#define MMU_IMR_TWE_MEMRD_ERR_MASK (MMU_IMR_TWE_MEMRD_ERR_M << MMU_IMR_TWE_MEMRD_ERR_SHIFT)
-#define MMU_IMR_FLUSH_MEMRD_ERR_M 0x1ULL
-#define MMU_IMR_FLUSH_MEMRD_ERR_SHIFT 4
-#define MMU_IMR_FLUSH_MEMRD_ERR_MASK (MMU_IMR_FLUSH_MEMRD_ERR_M << MMU_IMR_FLUSH_MEMRD_ERR_SHIFT)
-#define MMU_IMR_TWE_INVALID_TABLE_M 0x1ULL
-#define MMU_IMR_TWE_INVALID_TABLE_SHIFT 1
-#define MMU_IMR_TWE_INVALID_TABLE_MASK (MMU_IMR_TWE_INVALID_TABLE_M << MMU_IMR_TWE_INVALID_TABLE_SHIFT)
-#define MMU_IMR_FLUSH_FULL_ERR_M 0x1ULL
-#define MMU_IMR_FLUSH_FULL_ERR_SHIFT 6
-#define MMU_IMR_FLUSH_FULL_ERR_MASK (MMU_IMR_FLUSH_FULL_ERR_M << MMU_IMR_FLUSH_FULL_ERR_SHIFT)
-#define MMU_IMR_FLUSH_INVALID_TABLE_M 0x1ULL
-#define MMU_IMR_FLUSH_INVALID_TABLE_SHIFT 3
-#define MMU_IMR_FLUSH_INVALID_TABLE_MASK (MMU_IMR_FLUSH_INVALID_TABLE_M << MMU_IMR_FLUSH_INVALID_TABLE_SHIFT)
-#define MMU_ISR_OVF 0x60
-#define MMU_ISR_OVF_DEF 0x0
-#define MMU_ISR_OVF_FLUSH_MEMRD_ERR_M 0x1ULL
-#define MMU_ISR_OVF_FLUSH_MEMRD_ERR_SHIFT 4
-#define MMU_ISR_OVF_FLUSH_MEMRD_ERR_MASK (MMU_ISR_OVF_FLUSH_MEMRD_ERR_M << MMU_ISR_OVF_FLUSH_MEMRD_ERR_SHIFT)
-#define MMU_ISR_OVF_TWE_INVALID_TABLE_M 0x1ULL
-#define MMU_ISR_OVF_TWE_INVALID_TABLE_SHIFT 1
-#define MMU_ISR_OVF_TWE_INVALID_TABLE_MASK (MMU_ISR_OVF_TWE_INVALID_TABLE_M << MMU_ISR_OVF_TWE_INVALID_TABLE_SHIFT)
-#define MMU_ISR_OVF_TWE_MEMRD_ERR_M 0x1ULL
-#define MMU_ISR_OVF_TWE_MEMRD_ERR_SHIFT 2
-#define MMU_ISR_OVF_TWE_MEMRD_ERR_MASK (MMU_ISR_OVF_TWE_MEMRD_ERR_M << MMU_ISR_OVF_TWE_MEMRD_ERR_SHIFT)
-#define MMU_ISR_OVF_TWE_ACCESS_VIO_M 0x1ULL
-#define MMU_ISR_OVF_TWE_ACCESS_VIO_SHIFT 0
-#define MMU_ISR_OVF_TWE_ACCESS_VIO_MASK (MMU_ISR_OVF_TWE_ACCESS_VIO_M << MMU_ISR_OVF_TWE_ACCESS_VIO_SHIFT)
-#define MMU_ISR_OVF_FLUSH_FULL_ERR_M 0x1ULL
-#define MMU_ISR_OVF_FLUSH_FULL_ERR_SHIFT 6
-#define MMU_ISR_OVF_FLUSH_FULL_ERR_MASK (MMU_ISR_OVF_FLUSH_FULL_ERR_M << MMU_ISR_OVF_FLUSH_FULL_ERR_SHIFT)
-#define MMU_ISR_OVF_PREFETCH_MEMRD_ERR_M 0x1ULL
-#define MMU_ISR_OVF_PREFETCH_MEMRD_ERR_SHIFT 5
-#define MMU_ISR_OVF_PREFETCH_MEMRD_ERR_MASK (MMU_ISR_OVF_PREFETCH_MEMRD_ERR_M << MMU_ISR_OVF_PREFETCH_MEMRD_ERR_SHIFT)
-#define MMU_ISR_OVF_FLUSH_INVALID_TABLE_M 0x1ULL
-#define MMU_ISR_OVF_FLUSH_INVALID_TABLE_SHIFT 3
-#define MMU_ISR_OVF_FLUSH_INVALID_TABLE_MASK (MMU_ISR_OVF_FLUSH_INVALID_TABLE_M << MMU_ISR_OVF_FLUSH_INVALID_TABLE_SHIFT)
-#define MMU_ERR_LOG 0x68
-#define MMU_ERR_LOG_DEF 0x0
-#define MMU_ERR_LOG_ID_M 0x7fULL
-#define MMU_ERR_LOG_ID_SHIFT 32
-#define MMU_ERR_LOG_ID_MASK (MMU_ERR_LOG_ID_M << MMU_ERR_LOG_ID_SHIFT)
-#define MMU_ERR_LOG_VPAGEADDR_M 0x7fffffffULL
-#define MMU_ERR_LOG_VPAGEADDR_SHIFT 0
-#define MMU_ERR_LOG_VPAGEADDR_MASK (MMU_ERR_LOG_VPAGEADDR_M << MMU_ERR_LOG_VPAGEADDR_SHIFT)
-#define MMU_ERR_LOG_RD_WR_N_M 0x1ULL
-#define MMU_ERR_LOG_RD_WR_N_SHIFT 39
-#define MMU_ERR_LOG_RD_WR_N_MASK (MMU_ERR_LOG_RD_WR_N_M << MMU_ERR_LOG_RD_WR_N_SHIFT)
-#define BIF_AXI_CTRL_DMA0 0x80
-#define BIF_AXI_CTRL_DMA0_DEF 0x0
-#define BIF_AXI_CTRL_DMA0_CH0_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA0_CH0_AXQOS_SHIFT 7
-#define BIF_AXI_CTRL_DMA0_CH0_AXQOS_MASK (BIF_AXI_CTRL_DMA0_CH0_AXQOS_M << BIF_AXI_CTRL_DMA0_CH0_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH0_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA0_CH0_AXCACHE_SHIFT 0
-#define BIF_AXI_CTRL_DMA0_CH0_AXCACHE_MASK (BIF_AXI_CTRL_DMA0_CH0_AXCACHE_M << BIF_AXI_CTRL_DMA0_CH0_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH2_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA0_CH2_AXQOS_SHIFT 39
-#define BIF_AXI_CTRL_DMA0_CH2_AXQOS_MASK (BIF_AXI_CTRL_DMA0_CH2_AXQOS_M << BIF_AXI_CTRL_DMA0_CH2_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH3_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA0_CH3_AXCACHE_SHIFT 48
-#define BIF_AXI_CTRL_DMA0_CH3_AXCACHE_MASK (BIF_AXI_CTRL_DMA0_CH3_AXCACHE_M << BIF_AXI_CTRL_DMA0_CH3_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH1_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA0_CH1_AXQOS_SHIFT 23
-#define BIF_AXI_CTRL_DMA0_CH1_AXQOS_MASK (BIF_AXI_CTRL_DMA0_CH1_AXQOS_M << BIF_AXI_CTRL_DMA0_CH1_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH0_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA0_CH0_AXPROT_SHIFT 4
-#define BIF_AXI_CTRL_DMA0_CH0_AXPROT_MASK (BIF_AXI_CTRL_DMA0_CH0_AXPROT_M << BIF_AXI_CTRL_DMA0_CH0_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH1_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA0_CH1_AXPROT_SHIFT 20
-#define BIF_AXI_CTRL_DMA0_CH1_AXPROT_MASK (BIF_AXI_CTRL_DMA0_CH1_AXPROT_M << BIF_AXI_CTRL_DMA0_CH1_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH3_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA0_CH3_AXQOS_SHIFT 55
-#define BIF_AXI_CTRL_DMA0_CH3_AXQOS_MASK (BIF_AXI_CTRL_DMA0_CH3_AXQOS_M << BIF_AXI_CTRL_DMA0_CH3_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH2_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA0_CH2_AXCACHE_SHIFT 32
-#define BIF_AXI_CTRL_DMA0_CH2_AXCACHE_MASK (BIF_AXI_CTRL_DMA0_CH2_AXCACHE_M << BIF_AXI_CTRL_DMA0_CH2_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH2_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA0_CH2_AXPROT_SHIFT 36
-#define BIF_AXI_CTRL_DMA0_CH2_AXPROT_MASK (BIF_AXI_CTRL_DMA0_CH2_AXPROT_M << BIF_AXI_CTRL_DMA0_CH2_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH1_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA0_CH1_AXCACHE_SHIFT 16
-#define BIF_AXI_CTRL_DMA0_CH1_AXCACHE_MASK (BIF_AXI_CTRL_DMA0_CH1_AXCACHE_M << BIF_AXI_CTRL_DMA0_CH1_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA0_CH3_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA0_CH3_AXPROT_SHIFT 52
-#define BIF_AXI_CTRL_DMA0_CH3_AXPROT_MASK (BIF_AXI_CTRL_DMA0_CH3_AXPROT_M << BIF_AXI_CTRL_DMA0_CH3_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA1 0x88
-#define BIF_AXI_CTRL_DMA1_DEF 0x0
-#define BIF_AXI_CTRL_DMA1_CH5_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA1_CH5_AXPROT_SHIFT 20
-#define BIF_AXI_CTRL_DMA1_CH5_AXPROT_MASK (BIF_AXI_CTRL_DMA1_CH5_AXPROT_M << BIF_AXI_CTRL_DMA1_CH5_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH4_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA1_CH4_AXCACHE_SHIFT 0
-#define BIF_AXI_CTRL_DMA1_CH4_AXCACHE_MASK (BIF_AXI_CTRL_DMA1_CH4_AXCACHE_M << BIF_AXI_CTRL_DMA1_CH4_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH5_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA1_CH5_AXCACHE_SHIFT 16
-#define BIF_AXI_CTRL_DMA1_CH5_AXCACHE_MASK (BIF_AXI_CTRL_DMA1_CH5_AXCACHE_M << BIF_AXI_CTRL_DMA1_CH5_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH4_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA1_CH4_AXQOS_SHIFT 7
-#define BIF_AXI_CTRL_DMA1_CH4_AXQOS_MASK (BIF_AXI_CTRL_DMA1_CH4_AXQOS_M << BIF_AXI_CTRL_DMA1_CH4_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH6_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA1_CH6_AXQOS_SHIFT 39
-#define BIF_AXI_CTRL_DMA1_CH6_AXQOS_MASK (BIF_AXI_CTRL_DMA1_CH6_AXQOS_M << BIF_AXI_CTRL_DMA1_CH6_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH6_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA1_CH6_AXPROT_SHIFT 36
-#define BIF_AXI_CTRL_DMA1_CH6_AXPROT_MASK (BIF_AXI_CTRL_DMA1_CH6_AXPROT_M << BIF_AXI_CTRL_DMA1_CH6_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH4_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA1_CH4_AXPROT_SHIFT 4
-#define BIF_AXI_CTRL_DMA1_CH4_AXPROT_MASK (BIF_AXI_CTRL_DMA1_CH4_AXPROT_M << BIF_AXI_CTRL_DMA1_CH4_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH5_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA1_CH5_AXQOS_SHIFT 23
-#define BIF_AXI_CTRL_DMA1_CH5_AXQOS_MASK (BIF_AXI_CTRL_DMA1_CH5_AXQOS_M << BIF_AXI_CTRL_DMA1_CH5_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH7_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA1_CH7_AXQOS_SHIFT 55
-#define BIF_AXI_CTRL_DMA1_CH7_AXQOS_MASK (BIF_AXI_CTRL_DMA1_CH7_AXQOS_M << BIF_AXI_CTRL_DMA1_CH7_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH6_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA1_CH6_AXCACHE_SHIFT 32
-#define BIF_AXI_CTRL_DMA1_CH6_AXCACHE_MASK (BIF_AXI_CTRL_DMA1_CH6_AXCACHE_M << BIF_AXI_CTRL_DMA1_CH6_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH7_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA1_CH7_AXCACHE_SHIFT 48
-#define BIF_AXI_CTRL_DMA1_CH7_AXCACHE_MASK (BIF_AXI_CTRL_DMA1_CH7_AXCACHE_M << BIF_AXI_CTRL_DMA1_CH7_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA1_CH7_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA1_CH7_AXPROT_SHIFT 52
-#define BIF_AXI_CTRL_DMA1_CH7_AXPROT_MASK (BIF_AXI_CTRL_DMA1_CH7_AXPROT_M << BIF_AXI_CTRL_DMA1_CH7_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA2 0x90
-#define BIF_AXI_CTRL_DMA2_DEF 0x0
-#define BIF_AXI_CTRL_DMA2_CH9_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA2_CH9_AXPROT_SHIFT 20
-#define BIF_AXI_CTRL_DMA2_CH9_AXPROT_MASK (BIF_AXI_CTRL_DMA2_CH9_AXPROT_M << BIF_AXI_CTRL_DMA2_CH9_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH10_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA2_CH10_AXCACHE_SHIFT 32
-#define BIF_AXI_CTRL_DMA2_CH10_AXCACHE_MASK (BIF_AXI_CTRL_DMA2_CH10_AXCACHE_M << BIF_AXI_CTRL_DMA2_CH10_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH11_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA2_CH11_AXPROT_SHIFT 52
-#define BIF_AXI_CTRL_DMA2_CH11_AXPROT_MASK (BIF_AXI_CTRL_DMA2_CH11_AXPROT_M << BIF_AXI_CTRL_DMA2_CH11_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH8_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA2_CH8_AXQOS_SHIFT 7
-#define BIF_AXI_CTRL_DMA2_CH8_AXQOS_MASK (BIF_AXI_CTRL_DMA2_CH8_AXQOS_M << BIF_AXI_CTRL_DMA2_CH8_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH9_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA2_CH9_AXCACHE_SHIFT 16
-#define BIF_AXI_CTRL_DMA2_CH9_AXCACHE_MASK (BIF_AXI_CTRL_DMA2_CH9_AXCACHE_M << BIF_AXI_CTRL_DMA2_CH9_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH11_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA2_CH11_AXCACHE_SHIFT 48
-#define BIF_AXI_CTRL_DMA2_CH11_AXCACHE_MASK (BIF_AXI_CTRL_DMA2_CH11_AXCACHE_M << BIF_AXI_CTRL_DMA2_CH11_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH8_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA2_CH8_AXCACHE_SHIFT 0
-#define BIF_AXI_CTRL_DMA2_CH8_AXCACHE_MASK (BIF_AXI_CTRL_DMA2_CH8_AXCACHE_M << BIF_AXI_CTRL_DMA2_CH8_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH10_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA2_CH10_AXQOS_SHIFT 39
-#define BIF_AXI_CTRL_DMA2_CH10_AXQOS_MASK (BIF_AXI_CTRL_DMA2_CH10_AXQOS_M << BIF_AXI_CTRL_DMA2_CH10_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH8_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA2_CH8_AXPROT_SHIFT 4
-#define BIF_AXI_CTRL_DMA2_CH8_AXPROT_MASK (BIF_AXI_CTRL_DMA2_CH8_AXPROT_M << BIF_AXI_CTRL_DMA2_CH8_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH10_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA2_CH10_AXPROT_SHIFT 36
-#define BIF_AXI_CTRL_DMA2_CH10_AXPROT_MASK (BIF_AXI_CTRL_DMA2_CH10_AXPROT_M << BIF_AXI_CTRL_DMA2_CH10_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH11_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA2_CH11_AXQOS_SHIFT 55
-#define BIF_AXI_CTRL_DMA2_CH11_AXQOS_MASK (BIF_AXI_CTRL_DMA2_CH11_AXQOS_M << BIF_AXI_CTRL_DMA2_CH11_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA2_CH9_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA2_CH9_AXQOS_SHIFT 23
-#define BIF_AXI_CTRL_DMA2_CH9_AXQOS_MASK (BIF_AXI_CTRL_DMA2_CH9_AXQOS_M << BIF_AXI_CTRL_DMA2_CH9_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA3 0x98
-#define BIF_AXI_CTRL_DMA3_DEF 0x0
-#define BIF_AXI_CTRL_DMA3_CH13_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA3_CH13_AXPROT_SHIFT 20
-#define BIF_AXI_CTRL_DMA3_CH13_AXPROT_MASK (BIF_AXI_CTRL_DMA3_CH13_AXPROT_M << BIF_AXI_CTRL_DMA3_CH13_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH15_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA3_CH15_AXQOS_SHIFT 55
-#define BIF_AXI_CTRL_DMA3_CH15_AXQOS_MASK (BIF_AXI_CTRL_DMA3_CH15_AXQOS_M << BIF_AXI_CTRL_DMA3_CH15_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH12_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA3_CH12_AXQOS_SHIFT 7
-#define BIF_AXI_CTRL_DMA3_CH12_AXQOS_MASK (BIF_AXI_CTRL_DMA3_CH12_AXQOS_M << BIF_AXI_CTRL_DMA3_CH12_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH14_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA3_CH14_AXCACHE_SHIFT 32
-#define BIF_AXI_CTRL_DMA3_CH14_AXCACHE_MASK (BIF_AXI_CTRL_DMA3_CH14_AXCACHE_M << BIF_AXI_CTRL_DMA3_CH14_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH14_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA3_CH14_AXPROT_SHIFT 36
-#define BIF_AXI_CTRL_DMA3_CH14_AXPROT_MASK (BIF_AXI_CTRL_DMA3_CH14_AXPROT_M << BIF_AXI_CTRL_DMA3_CH14_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH14_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA3_CH14_AXQOS_SHIFT 39
-#define BIF_AXI_CTRL_DMA3_CH14_AXQOS_MASK (BIF_AXI_CTRL_DMA3_CH14_AXQOS_M << BIF_AXI_CTRL_DMA3_CH14_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH15_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA3_CH15_AXPROT_SHIFT 52
-#define BIF_AXI_CTRL_DMA3_CH15_AXPROT_MASK (BIF_AXI_CTRL_DMA3_CH15_AXPROT_M << BIF_AXI_CTRL_DMA3_CH15_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH13_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA3_CH13_AXCACHE_SHIFT 16
-#define BIF_AXI_CTRL_DMA3_CH13_AXCACHE_MASK (BIF_AXI_CTRL_DMA3_CH13_AXCACHE_M << BIF_AXI_CTRL_DMA3_CH13_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH12_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_DMA3_CH12_AXPROT_SHIFT 4
-#define BIF_AXI_CTRL_DMA3_CH12_AXPROT_MASK (BIF_AXI_CTRL_DMA3_CH12_AXPROT_M << BIF_AXI_CTRL_DMA3_CH12_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH15_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA3_CH15_AXCACHE_SHIFT 48
-#define BIF_AXI_CTRL_DMA3_CH15_AXCACHE_MASK (BIF_AXI_CTRL_DMA3_CH15_AXCACHE_M << BIF_AXI_CTRL_DMA3_CH15_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH12_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_DMA3_CH12_AXCACHE_SHIFT 0
-#define BIF_AXI_CTRL_DMA3_CH12_AXCACHE_MASK (BIF_AXI_CTRL_DMA3_CH12_AXCACHE_M << BIF_AXI_CTRL_DMA3_CH12_AXCACHE_SHIFT)
-#define BIF_AXI_CTRL_DMA3_CH13_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_DMA3_CH13_AXQOS_SHIFT 23
-#define BIF_AXI_CTRL_DMA3_CH13_AXQOS_MASK (BIF_AXI_CTRL_DMA3_CH13_AXQOS_M << BIF_AXI_CTRL_DMA3_CH13_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_MMU 0xb0
-#define BIF_AXI_CTRL_MMU_DEF 0x0
-#define BIF_AXI_CTRL_MMU_AXPROT_M 0x7ULL
-#define BIF_AXI_CTRL_MMU_AXPROT_SHIFT 4
-#define BIF_AXI_CTRL_MMU_AXPROT_MASK (BIF_AXI_CTRL_MMU_AXPROT_M << BIF_AXI_CTRL_MMU_AXPROT_SHIFT)
-#define BIF_AXI_CTRL_MMU_AXQOS_M 0xfULL
-#define BIF_AXI_CTRL_MMU_AXQOS_SHIFT 7
-#define BIF_AXI_CTRL_MMU_AXQOS_MASK (BIF_AXI_CTRL_MMU_AXQOS_M << BIF_AXI_CTRL_MMU_AXQOS_SHIFT)
-#define BIF_AXI_CTRL_MMU_AXCACHE_M 0xfULL
-#define BIF_AXI_CTRL_MMU_AXCACHE_SHIFT 0
-#define BIF_AXI_CTRL_MMU_AXCACHE_MASK (BIF_AXI_CTRL_MMU_AXCACHE_M << BIF_AXI_CTRL_MMU_AXCACHE_SHIFT)
-#define BIF_ISR 0xb8
-#define BIF_ISR_DEF 0x0
-#define BIF_ISR_TO_ERR_DMA_WR_M 0x1ULL
-#define BIF_ISR_TO_ERR_DMA_WR_SHIFT 3
-#define BIF_ISR_TO_ERR_DMA_WR_MASK (BIF_ISR_TO_ERR_DMA_WR_M << BIF_ISR_TO_ERR_DMA_WR_SHIFT)
-#define BIF_ISR_TO_ERR_DMA_RD_M 0x1ULL
-#define BIF_ISR_TO_ERR_DMA_RD_SHIFT 2
-#define BIF_ISR_TO_ERR_DMA_RD_MASK (BIF_ISR_TO_ERR_DMA_RD_M << BIF_ISR_TO_ERR_DMA_RD_SHIFT)
-#define BIF_ISR_TO_ERR_MMU_RD_M 0x1ULL
-#define BIF_ISR_TO_ERR_MMU_RD_SHIFT 4
-#define BIF_ISR_TO_ERR_MMU_RD_MASK (BIF_ISR_TO_ERR_MMU_RD_M << BIF_ISR_TO_ERR_MMU_RD_SHIFT)
-#define BIF_ISR_BUS_ERR_MMU_M 0x1ULL
-#define BIF_ISR_BUS_ERR_MMU_SHIFT 1
-#define BIF_ISR_BUS_ERR_MMU_MASK (BIF_ISR_BUS_ERR_MMU_M << BIF_ISR_BUS_ERR_MMU_SHIFT)
-#define BIF_ISR_BUS_ERR_DMA_M 0x1ULL
-#define BIF_ISR_BUS_ERR_DMA_SHIFT 0
-#define BIF_ISR_BUS_ERR_DMA_MASK (BIF_ISR_BUS_ERR_DMA_M << BIF_ISR_BUS_ERR_DMA_SHIFT)
-#define BIF_ITR 0xc0
-#define BIF_ITR_DEF 0x0
-#define BIF_ITR_TO_ERR_DMA_WR_M 0x1ULL
-#define BIF_ITR_TO_ERR_DMA_WR_SHIFT 3
-#define BIF_ITR_TO_ERR_DMA_WR_MASK (BIF_ITR_TO_ERR_DMA_WR_M << BIF_ITR_TO_ERR_DMA_WR_SHIFT)
-#define BIF_ITR_TO_ERR_MMU_RD_M 0x1ULL
-#define BIF_ITR_TO_ERR_MMU_RD_SHIFT 4
-#define BIF_ITR_TO_ERR_MMU_RD_MASK (BIF_ITR_TO_ERR_MMU_RD_M << BIF_ITR_TO_ERR_MMU_RD_SHIFT)
-#define BIF_ITR_TO_ERR_DMA_RD_M 0x1ULL
-#define BIF_ITR_TO_ERR_DMA_RD_SHIFT 2
-#define BIF_ITR_TO_ERR_DMA_RD_MASK (BIF_ITR_TO_ERR_DMA_RD_M << BIF_ITR_TO_ERR_DMA_RD_SHIFT)
-#define BIF_ITR_BUS_ERR_DMA_M 0x1ULL
-#define BIF_ITR_BUS_ERR_DMA_SHIFT 0
-#define BIF_ITR_BUS_ERR_DMA_MASK (BIF_ITR_BUS_ERR_DMA_M << BIF_ITR_BUS_ERR_DMA_SHIFT)
-#define BIF_ITR_BUS_ERR_MMU_M 0x1ULL
-#define BIF_ITR_BUS_ERR_MMU_SHIFT 1
-#define BIF_ITR_BUS_ERR_MMU_MASK (BIF_ITR_BUS_ERR_MMU_M << BIF_ITR_BUS_ERR_MMU_SHIFT)
-#define BIF_IER 0xc8
-#define BIF_IER_DEF 0x1f
-#define BIF_IER_TO_ERR_MMU_RD_M 0x1ULL
-#define BIF_IER_TO_ERR_MMU_RD_SHIFT 4
-#define BIF_IER_TO_ERR_MMU_RD_MASK (BIF_IER_TO_ERR_MMU_RD_M << BIF_IER_TO_ERR_MMU_RD_SHIFT)
-#define BIF_IER_TO_ERR_DMA_WR_M 0x1ULL
-#define BIF_IER_TO_ERR_DMA_WR_SHIFT 3
-#define BIF_IER_TO_ERR_DMA_WR_MASK (BIF_IER_TO_ERR_DMA_WR_M << BIF_IER_TO_ERR_DMA_WR_SHIFT)
-#define BIF_IER_BUS_ERR_MMU_M 0x1ULL
-#define BIF_IER_BUS_ERR_MMU_SHIFT 1
-#define BIF_IER_BUS_ERR_MMU_MASK (BIF_IER_BUS_ERR_MMU_M << BIF_IER_BUS_ERR_MMU_SHIFT)
-#define BIF_IER_BUS_ERR_DMA_M 0x1ULL
-#define BIF_IER_BUS_ERR_DMA_SHIFT 0
-#define BIF_IER_BUS_ERR_DMA_MASK (BIF_IER_BUS_ERR_DMA_M << BIF_IER_BUS_ERR_DMA_SHIFT)
-#define BIF_IER_TO_ERR_DMA_RD_M 0x1ULL
-#define BIF_IER_TO_ERR_DMA_RD_SHIFT 2
-#define BIF_IER_TO_ERR_DMA_RD_MASK (BIF_IER_TO_ERR_DMA_RD_M << BIF_IER_TO_ERR_DMA_RD_SHIFT)
-#define BIF_IMR 0xd0
-#define BIF_IMR_DEF 0x0
-#define BIF_IMR_TO_ERR_MMU_RD_M 0x1ULL
-#define BIF_IMR_TO_ERR_MMU_RD_SHIFT 4
-#define BIF_IMR_TO_ERR_MMU_RD_MASK (BIF_IMR_TO_ERR_MMU_RD_M << BIF_IMR_TO_ERR_MMU_RD_SHIFT)
-#define BIF_IMR_TO_ERR_DMA_WR_M 0x1ULL
-#define BIF_IMR_TO_ERR_DMA_WR_SHIFT 3
-#define BIF_IMR_TO_ERR_DMA_WR_MASK (BIF_IMR_TO_ERR_DMA_WR_M << BIF_IMR_TO_ERR_DMA_WR_SHIFT)
-#define BIF_IMR_BUS_ERR_MMU_M 0x1ULL
-#define BIF_IMR_BUS_ERR_MMU_SHIFT 1
-#define BIF_IMR_BUS_ERR_MMU_MASK (BIF_IMR_BUS_ERR_MMU_M << BIF_IMR_BUS_ERR_MMU_SHIFT)
-#define BIF_IMR_BUS_ERR_DMA_M 0x1ULL
-#define BIF_IMR_BUS_ERR_DMA_SHIFT 0
-#define BIF_IMR_BUS_ERR_DMA_MASK (BIF_IMR_BUS_ERR_DMA_M << BIF_IMR_BUS_ERR_DMA_SHIFT)
-#define BIF_IMR_TO_ERR_DMA_RD_M 0x1ULL
-#define BIF_IMR_TO_ERR_DMA_RD_SHIFT 2
-#define BIF_IMR_TO_ERR_DMA_RD_MASK (BIF_IMR_TO_ERR_DMA_RD_M << BIF_IMR_TO_ERR_DMA_RD_SHIFT)
-#define BIF_ISR_OVF 0xd8
-#define BIF_ISR_OVF_DEF 0x0
-#define BIF_ISR_OVF_BUS_ERR_MMU_M 0x1ULL
-#define BIF_ISR_OVF_BUS_ERR_MMU_SHIFT 1
-#define BIF_ISR_OVF_BUS_ERR_MMU_MASK (BIF_ISR_OVF_BUS_ERR_MMU_M << BIF_ISR_OVF_BUS_ERR_MMU_SHIFT)
-#define BIF_ISR_OVF_BUS_ERR_DMA_M 0x1ULL
-#define BIF_ISR_OVF_BUS_ERR_DMA_SHIFT 0
-#define BIF_ISR_OVF_BUS_ERR_DMA_MASK (BIF_ISR_OVF_BUS_ERR_DMA_M << BIF_ISR_OVF_BUS_ERR_DMA_SHIFT)
-#define BIF_ISR_OVF_TO_ERR_DMA_RD_M 0x1ULL
-#define BIF_ISR_OVF_TO_ERR_DMA_RD_SHIFT 2
-#define BIF_ISR_OVF_TO_ERR_DMA_RD_MASK (BIF_ISR_OVF_TO_ERR_DMA_RD_M << BIF_ISR_OVF_TO_ERR_DMA_RD_SHIFT)
-#define BIF_ISR_OVF_TO_ERR_MMU_RD_M 0x1ULL
-#define BIF_ISR_OVF_TO_ERR_MMU_RD_SHIFT 4
-#define BIF_ISR_OVF_TO_ERR_MMU_RD_MASK (BIF_ISR_OVF_TO_ERR_MMU_RD_M << BIF_ISR_OVF_TO_ERR_MMU_RD_SHIFT)
-#define BIF_ISR_OVF_TO_ERR_DMA_WR_M 0x1ULL
-#define BIF_ISR_OVF_TO_ERR_DMA_WR_SHIFT 3
-#define BIF_ISR_OVF_TO_ERR_DMA_WR_MASK (BIF_ISR_OVF_TO_ERR_DMA_WR_M << BIF_ISR_OVF_TO_ERR_DMA_WR_SHIFT)
-#define BIF_TO_ERR_CFG 0xe0
-#define BIF_TO_ERR_CFG_DEF 0x1f0000
-#define BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_M 0x1fULL
-#define BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_SHIFT 16
-#define BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_MASK (BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_M << BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_SHIFT)
-#define BIF_ERR_LOG 0xe8
-#define BIF_ERR_LOG_DEF 0x0
-#define BIF_ERR_LOG_BUS_ERR_DMA_WRITE_M 0x1ULL
-#define BIF_ERR_LOG_BUS_ERR_DMA_WRITE_SHIFT 0
-#define BIF_ERR_LOG_BUS_ERR_DMA_WRITE_MASK (BIF_ERR_LOG_BUS_ERR_DMA_WRITE_M << BIF_ERR_LOG_BUS_ERR_DMA_WRITE_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_TX_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_TX_EMPTY_SHIFT 40
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_TX_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_DMA_WR_TX_EMPTY_M << BIF_ERR_LOG_TO_ERR_DMA_WR_TX_EMPTY_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_EMPTY_SHIFT 37
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_EMPTY_M << BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_EMPTY_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_WID_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_WID_EMPTY_SHIFT 44
-#define BIF_ERR_LOG_TO_ERR_WID_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_WID_EMPTY_M << BIF_ERR_LOG_TO_ERR_WID_EMPTY_SHIFT)
-#define BIF_ERR_LOG_BUS_ERR_DMA_WR_ID_M 0x3fULL
-#define BIF_ERR_LOG_BUS_ERR_DMA_WR_ID_SHIFT 8
-#define BIF_ERR_LOG_BUS_ERR_DMA_WR_ID_MASK (BIF_ERR_LOG_BUS_ERR_DMA_WR_ID_M << BIF_ERR_LOG_BUS_ERR_DMA_WR_ID_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_RID_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_RID_EMPTY_SHIFT 43
-#define BIF_ERR_LOG_TO_ERR_RID_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_RID_EMPTY_M << BIF_ERR_LOG_TO_ERR_RID_EMPTY_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_EMPTY_SHIFT 42
-#define BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_EMPTY_M << BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_EMPTY_SHIFT)
-#define BIF_ERR_LOG_BUS_ERR_AXI_ID_M 0x7fULL
-#define BIF_ERR_LOG_BUS_ERR_AXI_ID_SHIFT 1
-#define BIF_ERR_LOG_BUS_ERR_AXI_ID_MASK (BIF_ERR_LOG_BUS_ERR_AXI_ID_M << BIF_ERR_LOG_BUS_ERR_AXI_ID_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_EMPTY_SHIFT 39
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_EMPTY_M << BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_EMPTY_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_TX_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_TX_EMPTY_SHIFT 32
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_TX_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_DMA_RD_TX_EMPTY_M << BIF_ERR_LOG_TO_ERR_DMA_RD_TX_EMPTY_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_EMPTY_SHIFT 38
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_EMPTY_M << BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_EMPTY_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_MMU_RD_RX_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_MMU_RD_RX_EMPTY_SHIFT 41
-#define BIF_ERR_LOG_TO_ERR_MMU_RD_RX_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_MMU_RD_RX_EMPTY_M << BIF_ERR_LOG_TO_ERR_MMU_RD_RX_EMPTY_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_RX_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_RX_EMPTY_SHIFT 33
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_RX_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_DMA_RD_RX_EMPTY_M << BIF_ERR_LOG_TO_ERR_DMA_RD_RX_EMPTY_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_IN_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_IN_EMPTY_SHIFT 34
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_IN_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_DMA_RD_IN_EMPTY_M << BIF_ERR_LOG_TO_ERR_DMA_RD_IN_EMPTY_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_EMPTY_SHIFT 35
-#define BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_EMPTY_M << BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_EMPTY_SHIFT)
-#define BIF_ERR_LOG_BUS_ERR_DMA_CHAN_M 0xfULL
-#define BIF_ERR_LOG_BUS_ERR_DMA_CHAN_SHIFT 14
-#define BIF_ERR_LOG_BUS_ERR_DMA_CHAN_MASK (BIF_ERR_LOG_BUS_ERR_DMA_CHAN_M << BIF_ERR_LOG_BUS_ERR_DMA_CHAN_SHIFT)
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_IN_EMPTY_M 0x1ULL
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_IN_EMPTY_SHIFT 36
-#define BIF_ERR_LOG_TO_ERR_DMA_WR_IN_EMPTY_MASK (BIF_ERR_LOG_TO_ERR_DMA_WR_IN_EMPTY_M << BIF_ERR_LOG_TO_ERR_DMA_WR_IN_EMPTY_SHIFT)
-#define BIF_ERR_LOG_BUS_ADDR 0xf0
-#define BIF_ERR_LOG_BUS_ADDR_DEF 0x0
-#define BIF_ERR_LOG_BUS_ADDR_PADDR_M 0xffffffffULL
-#define BIF_ERR_LOG_BUS_ADDR_PADDR_SHIFT 0
-#define BIF_ERR_LOG_BUS_ADDR_PADDR_MASK (BIF_ERR_LOG_BUS_ADDR_PADDR_M << BIF_ERR_LOG_BUS_ADDR_PADDR_SHIFT)
-#define BIF_PMON_CFG 0x100
-#define BIF_PMON_CFG_DEF 0x0
-#define BIF_PMON_CFG_ENABLE_M 0x1ULL
-#define BIF_PMON_CFG_ENABLE_SHIFT 0
-#define BIF_PMON_CFG_ENABLE_MASK (BIF_PMON_CFG_ENABLE_M << BIF_PMON_CFG_ENABLE_SHIFT)
-#define BIF_PMON_CNT_0_CFG 0x108
-#define BIF_PMON_CNT_0_CFG_DEF 0x0
-#define BIF_PMON_CNT_0_CFG_MODE_M 0x7ULL
-#define BIF_PMON_CNT_0_CFG_MODE_SHIFT 0
-#define BIF_PMON_CNT_0_CFG_MODE_MASK (BIF_PMON_CNT_0_CFG_MODE_M << BIF_PMON_CNT_0_CFG_MODE_SHIFT)
-#define BIF_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
-#define BIF_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
-#define BIF_PMON_CNT_0_CFG_DEC_MASK_MASK (BIF_PMON_CNT_0_CFG_DEC_MASK_M << BIF_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
-#define BIF_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
-#define BIF_PMON_CNT_0_CFG_INC_INV_SHIFT 47
-#define BIF_PMON_CNT_0_CFG_INC_INV_MASK (BIF_PMON_CNT_0_CFG_INC_INV_M << BIF_PMON_CNT_0_CFG_INC_INV_SHIFT)
-#define BIF_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
-#define BIF_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
-#define BIF_PMON_CNT_0_CFG_INC_MASK_MASK (BIF_PMON_CNT_0_CFG_INC_MASK_M << BIF_PMON_CNT_0_CFG_INC_MASK_SHIFT)
-#define BIF_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
-#define BIF_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
-#define BIF_PMON_CNT_0_CFG_INC_MATCH_MASK (BIF_PMON_CNT_0_CFG_INC_MATCH_M << BIF_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
-#define BIF_PMON_CNT_0_CFG_DEC_SEL_M 0xfULL
-#define BIF_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
-#define BIF_PMON_CNT_0_CFG_DEC_SEL_MASK (BIF_PMON_CNT_0_CFG_DEC_SEL_M << BIF_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
-#define BIF_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
-#define BIF_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
-#define BIF_PMON_CNT_0_CFG_DEC_INV_MASK (BIF_PMON_CNT_0_CFG_DEC_INV_M << BIF_PMON_CNT_0_CFG_DEC_INV_SHIFT)
-#define BIF_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
-#define BIF_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
-#define BIF_PMON_CNT_0_CFG_THRESHOLD_MASK (BIF_PMON_CNT_0_CFG_THRESHOLD_M << BIF_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
-#define BIF_PMON_CNT_0_CFG_INC_SEL_M 0xfULL
-#define BIF_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
-#define BIF_PMON_CNT_0_CFG_INC_SEL_MASK (BIF_PMON_CNT_0_CFG_INC_SEL_M << BIF_PMON_CNT_0_CFG_INC_SEL_SHIFT)
-#define BIF_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
-#define BIF_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
-#define BIF_PMON_CNT_0_CFG_DEC_MATCH_MASK (BIF_PMON_CNT_0_CFG_DEC_MATCH_M << BIF_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
-#define BIF_PMON_CNT_0 0x110
-#define BIF_PMON_CNT_0_DEF 0x0
-#define BIF_PMON_CNT_0_CNT_M 0xffffffffffULL
-#define BIF_PMON_CNT_0_CNT_SHIFT 0
-#define BIF_PMON_CNT_0_CNT_MASK (BIF_PMON_CNT_0_CNT_M << BIF_PMON_CNT_0_CNT_SHIFT)
-#define BIF_PMON_CNT_0_STS_ACC 0x118
-#define BIF_PMON_CNT_0_STS_ACC_DEF 0x0
-#define BIF_PMON_CNT_0_STS 0x120
-#define BIF_PMON_CNT_0_STS_DEF 0x0
-#define BIF_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
-#define BIF_PMON_CNT_0_STS_CNT_OF_SHIFT 2
-#define BIF_PMON_CNT_0_STS_CNT_OF_MASK (BIF_PMON_CNT_0_STS_CNT_OF_M << BIF_PMON_CNT_0_STS_CNT_OF_SHIFT)
-#define BIF_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
-#define BIF_PMON_CNT_0_STS_ACC_UF_SHIFT 1
-#define BIF_PMON_CNT_0_STS_ACC_UF_MASK (BIF_PMON_CNT_0_STS_ACC_UF_M << BIF_PMON_CNT_0_STS_ACC_UF_SHIFT)
-#define BIF_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
-#define BIF_PMON_CNT_0_STS_ACC_OF_SHIFT 0
-#define BIF_PMON_CNT_0_STS_ACC_OF_MASK (BIF_PMON_CNT_0_STS_ACC_OF_M << BIF_PMON_CNT_0_STS_ACC_OF_SHIFT)
-#define BIF_PMON_CNT_1_CFG 0x128
-#define BIF_PMON_CNT_1_CFG_DEF 0x0
-#define BIF_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
-#define BIF_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
-#define BIF_PMON_CNT_1_CFG_INC_MATCH_MASK (BIF_PMON_CNT_1_CFG_INC_MATCH_M << BIF_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
-#define BIF_PMON_CNT_1_CFG_INC_SEL_M 0xfULL
-#define BIF_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
-#define BIF_PMON_CNT_1_CFG_INC_SEL_MASK (BIF_PMON_CNT_1_CFG_INC_SEL_M << BIF_PMON_CNT_1_CFG_INC_SEL_SHIFT)
-#define BIF_PMON_CNT_1_CFG_DEC_SEL_M 0xfULL
-#define BIF_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
-#define BIF_PMON_CNT_1_CFG_DEC_SEL_MASK (BIF_PMON_CNT_1_CFG_DEC_SEL_M << BIF_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
-#define BIF_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
-#define BIF_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
-#define BIF_PMON_CNT_1_CFG_THRESHOLD_MASK (BIF_PMON_CNT_1_CFG_THRESHOLD_M << BIF_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
-#define BIF_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
-#define BIF_PMON_CNT_1_CFG_INC_INV_SHIFT 47
-#define BIF_PMON_CNT_1_CFG_INC_INV_MASK (BIF_PMON_CNT_1_CFG_INC_INV_M << BIF_PMON_CNT_1_CFG_INC_INV_SHIFT)
-#define BIF_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
-#define BIF_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
-#define BIF_PMON_CNT_1_CFG_DEC_MASK_MASK (BIF_PMON_CNT_1_CFG_DEC_MASK_M << BIF_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
-#define BIF_PMON_CNT_1_CFG_MODE_M 0x7ULL
-#define BIF_PMON_CNT_1_CFG_MODE_SHIFT 0
-#define BIF_PMON_CNT_1_CFG_MODE_MASK (BIF_PMON_CNT_1_CFG_MODE_M << BIF_PMON_CNT_1_CFG_MODE_SHIFT)
-#define BIF_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
-#define BIF_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
-#define BIF_PMON_CNT_1_CFG_DEC_INV_MASK (BIF_PMON_CNT_1_CFG_DEC_INV_M << BIF_PMON_CNT_1_CFG_DEC_INV_SHIFT)
-#define BIF_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
-#define BIF_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
-#define BIF_PMON_CNT_1_CFG_DEC_MATCH_MASK (BIF_PMON_CNT_1_CFG_DEC_MATCH_M << BIF_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
-#define BIF_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
-#define BIF_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
-#define BIF_PMON_CNT_1_CFG_INC_MASK_MASK (BIF_PMON_CNT_1_CFG_INC_MASK_M << BIF_PMON_CNT_1_CFG_INC_MASK_SHIFT)
-#define BIF_PMON_CNT_1 0x130
-#define BIF_PMON_CNT_1_DEF 0x0
-#define BIF_PMON_CNT_1_CNT_M 0xffffffffffULL
-#define BIF_PMON_CNT_1_CNT_SHIFT 0
-#define BIF_PMON_CNT_1_CNT_MASK (BIF_PMON_CNT_1_CNT_M << BIF_PMON_CNT_1_CNT_SHIFT)
-#define BIF_PMON_CNT_1_STS_ACC 0x138
-#define BIF_PMON_CNT_1_STS_ACC_DEF 0x0
-#define BIF_PMON_CNT_1_STS 0x140
-#define BIF_PMON_CNT_1_STS_DEF 0x0
-#define BIF_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
-#define BIF_PMON_CNT_1_STS_ACC_UF_SHIFT 1
-#define BIF_PMON_CNT_1_STS_ACC_UF_MASK (BIF_PMON_CNT_1_STS_ACC_UF_M << BIF_PMON_CNT_1_STS_ACC_UF_SHIFT)
-#define BIF_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
-#define BIF_PMON_CNT_1_STS_ACC_OF_SHIFT 0
-#define BIF_PMON_CNT_1_STS_ACC_OF_MASK (BIF_PMON_CNT_1_STS_ACC_OF_M << BIF_PMON_CNT_1_STS_ACC_OF_SHIFT)
-#define BIF_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
-#define BIF_PMON_CNT_1_STS_CNT_OF_SHIFT 2
-#define BIF_PMON_CNT_1_STS_CNT_OF_MASK (BIF_PMON_CNT_1_STS_CNT_OF_M << BIF_PMON_CNT_1_STS_CNT_OF_SHIFT)
-#define MMU_PMON_CFG 0x1c0
-#define MMU_PMON_CFG_DEF 0x0
-#define MMU_PMON_CFG_ENABLE_M 0x1ULL
-#define MMU_PMON_CFG_ENABLE_SHIFT 0
-#define MMU_PMON_CFG_ENABLE_MASK (MMU_PMON_CFG_ENABLE_M << MMU_PMON_CFG_ENABLE_SHIFT)
-#define MMU_PMON_CNT_0_CFG 0x1c8
-#define MMU_PMON_CNT_0_CFG_DEF 0x0
-#define MMU_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
-#define MMU_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
-#define MMU_PMON_CNT_0_CFG_THRESHOLD_MASK (MMU_PMON_CNT_0_CFG_THRESHOLD_M << MMU_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
-#define MMU_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
-#define MMU_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
-#define MMU_PMON_CNT_0_CFG_INC_MATCH_MASK (MMU_PMON_CNT_0_CFG_INC_MATCH_M << MMU_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
-#define MMU_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
-#define MMU_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
-#define MMU_PMON_CNT_0_CFG_DEC_INV_MASK (MMU_PMON_CNT_0_CFG_DEC_INV_M << MMU_PMON_CNT_0_CFG_DEC_INV_SHIFT)
-#define MMU_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
-#define MMU_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
-#define MMU_PMON_CNT_0_CFG_DEC_MATCH_MASK (MMU_PMON_CNT_0_CFG_DEC_MATCH_M << MMU_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
-#define MMU_PMON_CNT_0_CFG_MODE_M 0x7ULL
-#define MMU_PMON_CNT_0_CFG_MODE_SHIFT 0
-#define MMU_PMON_CNT_0_CFG_MODE_MASK (MMU_PMON_CNT_0_CFG_MODE_M << MMU_PMON_CNT_0_CFG_MODE_SHIFT)
-#define MMU_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
-#define MMU_PMON_CNT_0_CFG_INC_INV_SHIFT 47
-#define MMU_PMON_CNT_0_CFG_INC_INV_MASK (MMU_PMON_CNT_0_CFG_INC_INV_M << MMU_PMON_CNT_0_CFG_INC_INV_SHIFT)
-#define MMU_PMON_CNT_0_CFG_INC_SEL_M 0x1fULL
-#define MMU_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
-#define MMU_PMON_CNT_0_CFG_INC_SEL_MASK (MMU_PMON_CNT_0_CFG_INC_SEL_M << MMU_PMON_CNT_0_CFG_INC_SEL_SHIFT)
-#define MMU_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
-#define MMU_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
-#define MMU_PMON_CNT_0_CFG_INC_MASK_MASK (MMU_PMON_CNT_0_CFG_INC_MASK_M << MMU_PMON_CNT_0_CFG_INC_MASK_SHIFT)
-#define MMU_PMON_CNT_0_CFG_DEC_SEL_M 0x1fULL
-#define MMU_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
-#define MMU_PMON_CNT_0_CFG_DEC_SEL_MASK (MMU_PMON_CNT_0_CFG_DEC_SEL_M << MMU_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
-#define MMU_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
-#define MMU_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
-#define MMU_PMON_CNT_0_CFG_DEC_MASK_MASK (MMU_PMON_CNT_0_CFG_DEC_MASK_M << MMU_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
-#define MMU_PMON_CNT_0 0x1d0
-#define MMU_PMON_CNT_0_DEF 0x0
-#define MMU_PMON_CNT_0_CNT_M 0xffffffffffULL
-#define MMU_PMON_CNT_0_CNT_SHIFT 0
-#define MMU_PMON_CNT_0_CNT_MASK (MMU_PMON_CNT_0_CNT_M << MMU_PMON_CNT_0_CNT_SHIFT)
-#define MMU_PMON_CNT_0_STS_ACC 0x1d8
-#define MMU_PMON_CNT_0_STS_ACC_DEF 0x0
-#define MMU_PMON_CNT_0_STS 0x1e0
-#define MMU_PMON_CNT_0_STS_DEF 0x0
-#define MMU_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
-#define MMU_PMON_CNT_0_STS_CNT_OF_SHIFT 2
-#define MMU_PMON_CNT_0_STS_CNT_OF_MASK (MMU_PMON_CNT_0_STS_CNT_OF_M << MMU_PMON_CNT_0_STS_CNT_OF_SHIFT)
-#define MMU_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
-#define MMU_PMON_CNT_0_STS_ACC_UF_SHIFT 1
-#define MMU_PMON_CNT_0_STS_ACC_UF_MASK (MMU_PMON_CNT_0_STS_ACC_UF_M << MMU_PMON_CNT_0_STS_ACC_UF_SHIFT)
-#define MMU_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
-#define MMU_PMON_CNT_0_STS_ACC_OF_SHIFT 0
-#define MMU_PMON_CNT_0_STS_ACC_OF_MASK (MMU_PMON_CNT_0_STS_ACC_OF_M << MMU_PMON_CNT_0_STS_ACC_OF_SHIFT)
-#define MMU_PMON_CNT_1_CFG 0x1e8
-#define MMU_PMON_CNT_1_CFG_DEF 0x0
-#define MMU_PMON_CNT_1_CFG_MODE_M 0x7ULL
-#define MMU_PMON_CNT_1_CFG_MODE_SHIFT 0
-#define MMU_PMON_CNT_1_CFG_MODE_MASK (MMU_PMON_CNT_1_CFG_MODE_M << MMU_PMON_CNT_1_CFG_MODE_SHIFT)
-#define MMU_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
-#define MMU_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
-#define MMU_PMON_CNT_1_CFG_DEC_MASK_MASK (MMU_PMON_CNT_1_CFG_DEC_MASK_M << MMU_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
-#define MMU_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
-#define MMU_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
-#define MMU_PMON_CNT_1_CFG_INC_MASK_MASK (MMU_PMON_CNT_1_CFG_INC_MASK_M << MMU_PMON_CNT_1_CFG_INC_MASK_SHIFT)
-#define MMU_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
-#define MMU_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
-#define MMU_PMON_CNT_1_CFG_DEC_INV_MASK (MMU_PMON_CNT_1_CFG_DEC_INV_M << MMU_PMON_CNT_1_CFG_DEC_INV_SHIFT)
-#define MMU_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
-#define MMU_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
-#define MMU_PMON_CNT_1_CFG_DEC_MATCH_MASK (MMU_PMON_CNT_1_CFG_DEC_MATCH_M << MMU_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
-#define MMU_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
-#define MMU_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
-#define MMU_PMON_CNT_1_CFG_THRESHOLD_MASK (MMU_PMON_CNT_1_CFG_THRESHOLD_M << MMU_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
-#define MMU_PMON_CNT_1_CFG_DEC_SEL_M 0x1fULL
-#define MMU_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
-#define MMU_PMON_CNT_1_CFG_DEC_SEL_MASK (MMU_PMON_CNT_1_CFG_DEC_SEL_M << MMU_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
-#define MMU_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
-#define MMU_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
-#define MMU_PMON_CNT_1_CFG_INC_MATCH_MASK (MMU_PMON_CNT_1_CFG_INC_MATCH_M << MMU_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
-#define MMU_PMON_CNT_1_CFG_INC_SEL_M 0x1fULL
-#define MMU_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
-#define MMU_PMON_CNT_1_CFG_INC_SEL_MASK (MMU_PMON_CNT_1_CFG_INC_SEL_M << MMU_PMON_CNT_1_CFG_INC_SEL_SHIFT)
-#define MMU_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
-#define MMU_PMON_CNT_1_CFG_INC_INV_SHIFT 47
-#define MMU_PMON_CNT_1_CFG_INC_INV_MASK (MMU_PMON_CNT_1_CFG_INC_INV_M << MMU_PMON_CNT_1_CFG_INC_INV_SHIFT)
-#define MMU_PMON_CNT_1 0x1f0
-#define MMU_PMON_CNT_1_DEF 0x0
-#define MMU_PMON_CNT_1_CNT_M 0xffffffffffULL
-#define MMU_PMON_CNT_1_CNT_SHIFT 0
-#define MMU_PMON_CNT_1_CNT_MASK (MMU_PMON_CNT_1_CNT_M << MMU_PMON_CNT_1_CNT_SHIFT)
-#define MMU_PMON_CNT_1_STS_ACC 0x1f8
-#define MMU_PMON_CNT_1_STS_ACC_DEF 0x0
-#define MMU_PMON_CNT_1_STS 0x200
-#define MMU_PMON_CNT_1_STS_DEF 0x0
-#define MMU_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
-#define MMU_PMON_CNT_1_STS_ACC_UF_SHIFT 1
-#define MMU_PMON_CNT_1_STS_ACC_UF_MASK (MMU_PMON_CNT_1_STS_ACC_UF_M << MMU_PMON_CNT_1_STS_ACC_UF_SHIFT)
-#define MMU_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
-#define MMU_PMON_CNT_1_STS_ACC_OF_SHIFT 0
-#define MMU_PMON_CNT_1_STS_ACC_OF_MASK (MMU_PMON_CNT_1_STS_ACC_OF_M << MMU_PMON_CNT_1_STS_ACC_OF_SHIFT)
-#define MMU_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
-#define MMU_PMON_CNT_1_STS_CNT_OF_SHIFT 2
-#define MMU_PMON_CNT_1_STS_CNT_OF_MASK (MMU_PMON_CNT_1_STS_CNT_OF_M << MMU_PMON_CNT_1_STS_CNT_OF_SHIFT)
-#define AXI_SPARE 0x208
-#define AXI_SPARE_DEF 0x0
-#define AXI_SPARE_SPARE15_M 0x1ULL
-#define AXI_SPARE_SPARE15_SHIFT 15
-#define AXI_SPARE_SPARE15_MASK (AXI_SPARE_SPARE15_M << AXI_SPARE_SPARE15_SHIFT)
-#define AXI_SPARE_SPARE12_M 0x1ULL
-#define AXI_SPARE_SPARE12_SHIFT 12
-#define AXI_SPARE_SPARE12_MASK (AXI_SPARE_SPARE12_M << AXI_SPARE_SPARE12_SHIFT)
-#define AXI_SPARE_SPARE11_M 0x1ULL
-#define AXI_SPARE_SPARE11_SHIFT 11
-#define AXI_SPARE_SPARE11_MASK (AXI_SPARE_SPARE11_M << AXI_SPARE_SPARE11_SHIFT)
-#define AXI_SPARE_SPARE10_M 0x1ULL
-#define AXI_SPARE_SPARE10_SHIFT 10
-#define AXI_SPARE_SPARE10_MASK (AXI_SPARE_SPARE10_M << AXI_SPARE_SPARE10_SHIFT)
-#define AXI_SPARE_SPARE13_M 0x1ULL
-#define AXI_SPARE_SPARE13_SHIFT 13
-#define AXI_SPARE_SPARE13_MASK (AXI_SPARE_SPARE13_M << AXI_SPARE_SPARE13_SHIFT)
-#define AXI_SPARE_SPARE8_M 0x1ULL
-#define AXI_SPARE_SPARE8_SHIFT 8
-#define AXI_SPARE_SPARE8_MASK (AXI_SPARE_SPARE8_M << AXI_SPARE_SPARE8_SHIFT)
-#define AXI_SPARE_SPARE9_M 0x1ULL
-#define AXI_SPARE_SPARE9_SHIFT 9
-#define AXI_SPARE_SPARE9_MASK (AXI_SPARE_SPARE9_M << AXI_SPARE_SPARE9_SHIFT)
-#define AXI_SPARE_SPARE14_M 0x1ULL
-#define AXI_SPARE_SPARE14_SHIFT 14
-#define AXI_SPARE_SPARE14_MASK (AXI_SPARE_SPARE14_M << AXI_SPARE_SPARE14_SHIFT)
-#define AXI_SPARE_SPARE4_M 0x1ULL
-#define AXI_SPARE_SPARE4_SHIFT 4
-#define AXI_SPARE_SPARE4_MASK (AXI_SPARE_SPARE4_M << AXI_SPARE_SPARE4_SHIFT)
-#define AXI_SPARE_SPARE5_M 0x1ULL
-#define AXI_SPARE_SPARE5_SHIFT 5
-#define AXI_SPARE_SPARE5_MASK (AXI_SPARE_SPARE5_M << AXI_SPARE_SPARE5_SHIFT)
-#define AXI_SPARE_SPARE6_M 0x1ULL
-#define AXI_SPARE_SPARE6_SHIFT 6
-#define AXI_SPARE_SPARE6_MASK (AXI_SPARE_SPARE6_M << AXI_SPARE_SPARE6_SHIFT)
-#define AXI_SPARE_SPARE7_M 0x1ULL
-#define AXI_SPARE_SPARE7_SHIFT 7
-#define AXI_SPARE_SPARE7_MASK (AXI_SPARE_SPARE7_M << AXI_SPARE_SPARE7_SHIFT)
-#define AXI_SPARE_SPARE0_M 0x1ULL
-#define AXI_SPARE_SPARE0_SHIFT 0
-#define AXI_SPARE_SPARE0_MASK (AXI_SPARE_SPARE0_M << AXI_SPARE_SPARE0_SHIFT)
-#define AXI_SPARE_SPARE1_M 0x1ULL
-#define AXI_SPARE_SPARE1_SHIFT 1
-#define AXI_SPARE_SPARE1_MASK (AXI_SPARE_SPARE1_M << AXI_SPARE_SPARE1_SHIFT)
-#define AXI_SPARE_SPARE2_M 0x1ULL
-#define AXI_SPARE_SPARE2_SHIFT 2
-#define AXI_SPARE_SPARE2_MASK (AXI_SPARE_SPARE2_M << AXI_SPARE_SPARE2_SHIFT)
-#define AXI_SPARE_SPARE3_M 0x1ULL
-#define AXI_SPARE_SPARE3_SHIFT 3
-#define AXI_SPARE_SPARE3_MASK (AXI_SPARE_SPARE3_M << AXI_SPARE_SPARE3_SHIFT)
-
-/* Module : IPU_LIB_DREGFILE_DMA*/
-#define DMA_CTRL 0x0
-#define DMA_CTRL_DEF 0x1f00
-#define DMA_CTRL_DMA_RESET_M 0x1ULL
-#define DMA_CTRL_DMA_RESET_SHIFT 0
-#define DMA_CTRL_DMA_RESET_MASK (DMA_CTRL_DMA_RESET_M << DMA_CTRL_DMA_RESET_SHIFT)
-#define DMA_CTRL_DMA_CHAN_SEL_M 0x1fULL
-#define DMA_CTRL_DMA_CHAN_SEL_SHIFT 8
-#define DMA_CTRL_DMA_CHAN_SEL_MASK (DMA_CTRL_DMA_CHAN_SEL_M << DMA_CTRL_DMA_CHAN_SEL_SHIFT)
-#define DMA_CTRL_AXI_SWIZZLE_M 0x3ULL
-#define DMA_CTRL_AXI_SWIZZLE_SHIFT 16
-#define DMA_CTRL_AXI_SWIZZLE_MASK (DMA_CTRL_AXI_SWIZZLE_M << DMA_CTRL_AXI_SWIZZLE_SHIFT)
-#define DMA_CHAN_CTRL 0x8
-#define DMA_CHAN_CTRL_DEF 0x0
-#define DMA_CHAN_CTRL_CONTINUOUS_M 0xffffULL
-#define DMA_CHAN_CTRL_CONTINUOUS_SHIFT 16
-#define DMA_CHAN_CTRL_CONTINUOUS_MASK (DMA_CHAN_CTRL_CONTINUOUS_M << DMA_CHAN_CTRL_CONTINUOUS_SHIFT)
-#define DMA_CHAN_CTRL_STOP_M 0xffffULL
-#define DMA_CHAN_CTRL_STOP_SHIFT 32
-#define DMA_CHAN_CTRL_STOP_MASK (DMA_CHAN_CTRL_STOP_M << DMA_CHAN_CTRL_STOP_SHIFT)
-#define DMA_CHAN_CTRL_CHAN_RESET_M 0xffffULL
-#define DMA_CHAN_CTRL_CHAN_RESET_SHIFT 0
-#define DMA_CHAN_CTRL_CHAN_RESET_MASK (DMA_CHAN_CTRL_CHAN_RESET_M << DMA_CHAN_CTRL_CHAN_RESET_SHIFT)
-#define DMA_CAP0 0x10
-#define DMA_CAP0_DEF 0x10
-#define DMA_CAP0_MAX_DMA_CHAN_M 0x1fULL
-#define DMA_CAP0_MAX_DMA_CHAN_SHIFT 0
-#define DMA_CAP0_MAX_DMA_CHAN_MASK (DMA_CAP0_MAX_DMA_CHAN_M << DMA_CAP0_MAX_DMA_CHAN_SHIFT)
-#define DMA_IRQ_ISR 0x18
-#define DMA_IRQ_ISR_DEF 0x0
-#define DMA_IRQ_ISR_EOF_INTR_M 0xffffULL
-#define DMA_IRQ_ISR_EOF_INTR_SHIFT 0
-#define DMA_IRQ_ISR_EOF_INTR_MASK (DMA_IRQ_ISR_EOF_INTR_M << DMA_IRQ_ISR_EOF_INTR_SHIFT)
-#define DMA_IRQ_ERR_ISR 0x20
-#define DMA_IRQ_ERR_ISR_DEF 0x0
-#define DMA_IRQ_ERR_ISR_MS_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_ISR_MS_ERR_SHIFT 32
-#define DMA_IRQ_ERR_ISR_MS_ERR_MASK (DMA_IRQ_ERR_ISR_MS_ERR_M << DMA_IRQ_ERR_ISR_MS_ERR_SHIFT)
-#define DMA_IRQ_ERR_ISR_VA_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_ISR_VA_ERR_SHIFT 0
-#define DMA_IRQ_ERR_ISR_VA_ERR_MASK (DMA_IRQ_ERR_ISR_VA_ERR_M << DMA_IRQ_ERR_ISR_VA_ERR_SHIFT)
-#define DMA_IRQ_ITR 0x28
-#define DMA_IRQ_ITR_DEF 0x0
-#define DMA_IRQ_ITR_EOF_INTR_M 0xffffULL
-#define DMA_IRQ_ITR_EOF_INTR_SHIFT 0
-#define DMA_IRQ_ITR_EOF_INTR_MASK (DMA_IRQ_ITR_EOF_INTR_M << DMA_IRQ_ITR_EOF_INTR_SHIFT)
-#define DMA_IRQ_ERR_ITR 0x30
-#define DMA_IRQ_ERR_ITR_DEF 0x0
-#define DMA_IRQ_ERR_ITR_MS_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_ITR_MS_ERR_SHIFT 32
-#define DMA_IRQ_ERR_ITR_MS_ERR_MASK (DMA_IRQ_ERR_ITR_MS_ERR_M << DMA_IRQ_ERR_ITR_MS_ERR_SHIFT)
-#define DMA_IRQ_ERR_ITR_VA_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_ITR_VA_ERR_SHIFT 0
-#define DMA_IRQ_ERR_ITR_VA_ERR_MASK (DMA_IRQ_ERR_ITR_VA_ERR_M << DMA_IRQ_ERR_ITR_VA_ERR_SHIFT)
-#define DMA_IRQ_IER 0x38
-#define DMA_IRQ_IER_DEF 0xffff
-#define DMA_IRQ_IER_EOF_INTR_M 0xffffULL
-#define DMA_IRQ_IER_EOF_INTR_SHIFT 0
-#define DMA_IRQ_IER_EOF_INTR_MASK (DMA_IRQ_IER_EOF_INTR_M << DMA_IRQ_IER_EOF_INTR_SHIFT)
-#define DMA_IRQ_ERR_IER 0x40
-#define DMA_IRQ_ERR_IER_DEF 0xffff0000ffff
-#define DMA_IRQ_ERR_IER_VA_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_IER_VA_ERR_SHIFT 0
-#define DMA_IRQ_ERR_IER_VA_ERR_MASK (DMA_IRQ_ERR_IER_VA_ERR_M << DMA_IRQ_ERR_IER_VA_ERR_SHIFT)
-#define DMA_IRQ_ERR_IER_MS_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_IER_MS_ERR_SHIFT 32
-#define DMA_IRQ_ERR_IER_MS_ERR_MASK (DMA_IRQ_ERR_IER_MS_ERR_M << DMA_IRQ_ERR_IER_MS_ERR_SHIFT)
-#define DMA_IRQ_IMR 0x48
-#define DMA_IRQ_IMR_DEF 0x0
-#define DMA_IRQ_IMR_EOF_INTR_M 0xffffULL
-#define DMA_IRQ_IMR_EOF_INTR_SHIFT 0
-#define DMA_IRQ_IMR_EOF_INTR_MASK (DMA_IRQ_IMR_EOF_INTR_M << DMA_IRQ_IMR_EOF_INTR_SHIFT)
-#define DMA_IRQ_ERR_IMR 0x50
-#define DMA_IRQ_ERR_IMR_DEF 0x0
-#define DMA_IRQ_ERR_IMR_VA_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_IMR_VA_ERR_SHIFT 0
-#define DMA_IRQ_ERR_IMR_VA_ERR_MASK (DMA_IRQ_ERR_IMR_VA_ERR_M << DMA_IRQ_ERR_IMR_VA_ERR_SHIFT)
-#define DMA_IRQ_ERR_IMR_MS_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_IMR_MS_ERR_SHIFT 32
-#define DMA_IRQ_ERR_IMR_MS_ERR_MASK (DMA_IRQ_ERR_IMR_MS_ERR_M << DMA_IRQ_ERR_IMR_MS_ERR_SHIFT)
-#define DMA_IRQ_ISR_OVF 0x58
-#define DMA_IRQ_ISR_OVF_DEF 0x0
-#define DMA_IRQ_ISR_OVF_EOF_INTR_M 0xffffULL
-#define DMA_IRQ_ISR_OVF_EOF_INTR_SHIFT 0
-#define DMA_IRQ_ISR_OVF_EOF_INTR_MASK (DMA_IRQ_ISR_OVF_EOF_INTR_M << DMA_IRQ_ISR_OVF_EOF_INTR_SHIFT)
-#define DMA_IRQ_ERR_ISR_OVF 0x60
-#define DMA_IRQ_ERR_ISR_OVF_DEF 0x0
-#define DMA_IRQ_ERR_ISR_OVF_MS_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_ISR_OVF_MS_ERR_SHIFT 32
-#define DMA_IRQ_ERR_ISR_OVF_MS_ERR_MASK (DMA_IRQ_ERR_ISR_OVF_MS_ERR_M << DMA_IRQ_ERR_ISR_OVF_MS_ERR_SHIFT)
-#define DMA_IRQ_ERR_ISR_OVF_VA_ERR_M 0xffffULL
-#define DMA_IRQ_ERR_ISR_OVF_VA_ERR_SHIFT 0
-#define DMA_IRQ_ERR_ISR_OVF_VA_ERR_MASK (DMA_IRQ_ERR_ISR_OVF_VA_ERR_M << DMA_IRQ_ERR_ISR_OVF_VA_ERR_SHIFT)
-#define DMA_PMON_CFG 0x100
-#define DMA_PMON_CFG_DEF 0x0
-#define DMA_PMON_CFG_CNT_0_CHAN_M 0xfULL
-#define DMA_PMON_CFG_CNT_0_CHAN_SHIFT 4
-#define DMA_PMON_CFG_CNT_0_CHAN_MASK (DMA_PMON_CFG_CNT_0_CHAN_M << DMA_PMON_CFG_CNT_0_CHAN_SHIFT)
-#define DMA_PMON_CFG_CNT_1_CHAN_M 0xfULL
-#define DMA_PMON_CFG_CNT_1_CHAN_SHIFT 8
-#define DMA_PMON_CFG_CNT_1_CHAN_MASK (DMA_PMON_CFG_CNT_1_CHAN_M << DMA_PMON_CFG_CNT_1_CHAN_SHIFT)
-#define DMA_PMON_CFG_ENABLE_M 0x1ULL
-#define DMA_PMON_CFG_ENABLE_SHIFT 0
-#define DMA_PMON_CFG_ENABLE_MASK (DMA_PMON_CFG_ENABLE_M << DMA_PMON_CFG_ENABLE_SHIFT)
-#define DMA_PMON_CNT_0_CFG 0x108
-#define DMA_PMON_CNT_0_CFG_DEF 0x0
-#define DMA_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
-#define DMA_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
-#define DMA_PMON_CNT_0_CFG_INC_MATCH_MASK (DMA_PMON_CNT_0_CFG_INC_MATCH_M << DMA_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
-#define DMA_PMON_CNT_0_CFG_INC_SEL_M 0x3fULL
-#define DMA_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
-#define DMA_PMON_CNT_0_CFG_INC_SEL_MASK (DMA_PMON_CNT_0_CFG_INC_SEL_M << DMA_PMON_CNT_0_CFG_INC_SEL_SHIFT)
-#define DMA_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
-#define DMA_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
-#define DMA_PMON_CNT_0_CFG_DEC_MATCH_MASK (DMA_PMON_CNT_0_CFG_DEC_MATCH_M << DMA_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
-#define DMA_PMON_CNT_0_CFG_DEC_SEL_M 0x3fULL
-#define DMA_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
-#define DMA_PMON_CNT_0_CFG_DEC_SEL_MASK (DMA_PMON_CNT_0_CFG_DEC_SEL_M << DMA_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
-#define DMA_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
-#define DMA_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
-#define DMA_PMON_CNT_0_CFG_THRESHOLD_MASK (DMA_PMON_CNT_0_CFG_THRESHOLD_M << DMA_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
-#define DMA_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
-#define DMA_PMON_CNT_0_CFG_INC_INV_SHIFT 47
-#define DMA_PMON_CNT_0_CFG_INC_INV_MASK (DMA_PMON_CNT_0_CFG_INC_INV_M << DMA_PMON_CNT_0_CFG_INC_INV_SHIFT)
-#define DMA_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
-#define DMA_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
-#define DMA_PMON_CNT_0_CFG_DEC_MASK_MASK (DMA_PMON_CNT_0_CFG_DEC_MASK_M << DMA_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
-#define DMA_PMON_CNT_0_CFG_MODE_M 0x7ULL
-#define DMA_PMON_CNT_0_CFG_MODE_SHIFT 0
-#define DMA_PMON_CNT_0_CFG_MODE_MASK (DMA_PMON_CNT_0_CFG_MODE_M << DMA_PMON_CNT_0_CFG_MODE_SHIFT)
-#define DMA_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
-#define DMA_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
-#define DMA_PMON_CNT_0_CFG_DEC_INV_MASK (DMA_PMON_CNT_0_CFG_DEC_INV_M << DMA_PMON_CNT_0_CFG_DEC_INV_SHIFT)
-#define DMA_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
-#define DMA_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
-#define DMA_PMON_CNT_0_CFG_INC_MASK_MASK (DMA_PMON_CNT_0_CFG_INC_MASK_M << DMA_PMON_CNT_0_CFG_INC_MASK_SHIFT)
-#define DMA_PMON_CNT_0 0x110
-#define DMA_PMON_CNT_0_DEF 0x0
-#define DMA_PMON_CNT_0_CNT_M 0xffffffffffULL
-#define DMA_PMON_CNT_0_CNT_SHIFT 0
-#define DMA_PMON_CNT_0_CNT_MASK (DMA_PMON_CNT_0_CNT_M << DMA_PMON_CNT_0_CNT_SHIFT)
-#define DMA_PMON_CNT_0_STS_ACC 0x118
-#define DMA_PMON_CNT_0_STS_ACC_DEF 0x0
-#define DMA_PMON_CNT_0_STS 0x120
-#define DMA_PMON_CNT_0_STS_DEF 0x0
-#define DMA_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
-#define DMA_PMON_CNT_0_STS_ACC_UF_SHIFT 1
-#define DMA_PMON_CNT_0_STS_ACC_UF_MASK (DMA_PMON_CNT_0_STS_ACC_UF_M << DMA_PMON_CNT_0_STS_ACC_UF_SHIFT)
-#define DMA_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
-#define DMA_PMON_CNT_0_STS_ACC_OF_SHIFT 0
-#define DMA_PMON_CNT_0_STS_ACC_OF_MASK (DMA_PMON_CNT_0_STS_ACC_OF_M << DMA_PMON_CNT_0_STS_ACC_OF_SHIFT)
-#define DMA_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
-#define DMA_PMON_CNT_0_STS_CNT_OF_SHIFT 2
-#define DMA_PMON_CNT_0_STS_CNT_OF_MASK (DMA_PMON_CNT_0_STS_CNT_OF_M << DMA_PMON_CNT_0_STS_CNT_OF_SHIFT)
-#define DMA_PMON_CNT_1_CFG 0x128
-#define DMA_PMON_CNT_1_CFG_DEF 0x0
-#define DMA_PMON_CNT_1_CFG_MODE_M 0x7ULL
-#define DMA_PMON_CNT_1_CFG_MODE_SHIFT 0
-#define DMA_PMON_CNT_1_CFG_MODE_MASK (DMA_PMON_CNT_1_CFG_MODE_M << DMA_PMON_CNT_1_CFG_MODE_SHIFT)
-#define DMA_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
-#define DMA_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
-#define DMA_PMON_CNT_1_CFG_DEC_MATCH_MASK (DMA_PMON_CNT_1_CFG_DEC_MATCH_M << DMA_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
-#define DMA_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
-#define DMA_PMON_CNT_1_CFG_INC_INV_SHIFT 47
-#define DMA_PMON_CNT_1_CFG_INC_INV_MASK (DMA_PMON_CNT_1_CFG_INC_INV_M << DMA_PMON_CNT_1_CFG_INC_INV_SHIFT)
-#define DMA_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
-#define DMA_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
-#define DMA_PMON_CNT_1_CFG_INC_MASK_MASK (DMA_PMON_CNT_1_CFG_INC_MASK_M << DMA_PMON_CNT_1_CFG_INC_MASK_SHIFT)
-#define DMA_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
-#define DMA_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
-#define DMA_PMON_CNT_1_CFG_DEC_MASK_MASK (DMA_PMON_CNT_1_CFG_DEC_MASK_M << DMA_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
-#define DMA_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
-#define DMA_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
-#define DMA_PMON_CNT_1_CFG_INC_MATCH_MASK (DMA_PMON_CNT_1_CFG_INC_MATCH_M << DMA_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
-#define DMA_PMON_CNT_1_CFG_DEC_SEL_M 0x3fULL
-#define DMA_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
-#define DMA_PMON_CNT_1_CFG_DEC_SEL_MASK (DMA_PMON_CNT_1_CFG_DEC_SEL_M << DMA_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
-#define DMA_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
-#define DMA_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
-#define DMA_PMON_CNT_1_CFG_DEC_INV_MASK (DMA_PMON_CNT_1_CFG_DEC_INV_M << DMA_PMON_CNT_1_CFG_DEC_INV_SHIFT)
-#define DMA_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
-#define DMA_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
-#define DMA_PMON_CNT_1_CFG_THRESHOLD_MASK (DMA_PMON_CNT_1_CFG_THRESHOLD_M << DMA_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
-#define DMA_PMON_CNT_1_CFG_INC_SEL_M 0x3fULL
-#define DMA_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
-#define DMA_PMON_CNT_1_CFG_INC_SEL_MASK (DMA_PMON_CNT_1_CFG_INC_SEL_M << DMA_PMON_CNT_1_CFG_INC_SEL_SHIFT)
-#define DMA_PMON_CNT_1 0x130
-#define DMA_PMON_CNT_1_DEF 0x0
-#define DMA_PMON_CNT_1_CNT_M 0xffffffffffULL
-#define DMA_PMON_CNT_1_CNT_SHIFT 0
-#define DMA_PMON_CNT_1_CNT_MASK (DMA_PMON_CNT_1_CNT_M << DMA_PMON_CNT_1_CNT_SHIFT)
-#define DMA_PMON_CNT_1_STS_ACC 0x138
-#define DMA_PMON_CNT_1_STS_ACC_DEF 0x0
-#define DMA_PMON_CNT_1_STS 0x140
-#define DMA_PMON_CNT_1_STS_DEF 0x0
-#define DMA_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
-#define DMA_PMON_CNT_1_STS_CNT_OF_SHIFT 2
-#define DMA_PMON_CNT_1_STS_CNT_OF_MASK (DMA_PMON_CNT_1_STS_CNT_OF_M << DMA_PMON_CNT_1_STS_CNT_OF_SHIFT)
-#define DMA_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
-#define DMA_PMON_CNT_1_STS_ACC_UF_SHIFT 1
-#define DMA_PMON_CNT_1_STS_ACC_UF_MASK (DMA_PMON_CNT_1_STS_ACC_UF_M << DMA_PMON_CNT_1_STS_ACC_UF_SHIFT)
-#define DMA_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
-#define DMA_PMON_CNT_1_STS_ACC_OF_SHIFT 0
-#define DMA_PMON_CNT_1_STS_ACC_OF_MASK (DMA_PMON_CNT_1_STS_ACC_OF_M << DMA_PMON_CNT_1_STS_ACC_OF_SHIFT)
-#define DMA_PMON_CNT_2_CFG 0x148
-#define DMA_PMON_CNT_2_CFG_DEF 0x0
-#define DMA_PMON_CNT_2_CFG_INC_MASK_M 0xfULL
-#define DMA_PMON_CNT_2_CFG_INC_MASK_SHIFT 39
-#define DMA_PMON_CNT_2_CFG_INC_MASK_MASK (DMA_PMON_CNT_2_CFG_INC_MASK_M << DMA_PMON_CNT_2_CFG_INC_MASK_SHIFT)
-#define DMA_PMON_CNT_2_CFG_THRESHOLD_M 0xffULL
-#define DMA_PMON_CNT_2_CFG_THRESHOLD_SHIFT 3
-#define DMA_PMON_CNT_2_CFG_THRESHOLD_MASK (DMA_PMON_CNT_2_CFG_THRESHOLD_M << DMA_PMON_CNT_2_CFG_THRESHOLD_SHIFT)
-#define DMA_PMON_CNT_2_CFG_INC_MATCH_M 0xfULL
-#define DMA_PMON_CNT_2_CFG_INC_MATCH_SHIFT 43
-#define DMA_PMON_CNT_2_CFG_INC_MATCH_MASK (DMA_PMON_CNT_2_CFG_INC_MATCH_M << DMA_PMON_CNT_2_CFG_INC_MATCH_SHIFT)
-#define DMA_PMON_CNT_2_CFG_DEC_SEL_M 0x3fULL
-#define DMA_PMON_CNT_2_CFG_DEC_SEL_SHIFT 48
-#define DMA_PMON_CNT_2_CFG_DEC_SEL_MASK (DMA_PMON_CNT_2_CFG_DEC_SEL_M << DMA_PMON_CNT_2_CFG_DEC_SEL_SHIFT)
-#define DMA_PMON_CNT_2_CFG_DEC_MASK_M 0xfULL
-#define DMA_PMON_CNT_2_CFG_DEC_MASK_SHIFT 55
-#define DMA_PMON_CNT_2_CFG_DEC_MASK_MASK (DMA_PMON_CNT_2_CFG_DEC_MASK_M << DMA_PMON_CNT_2_CFG_DEC_MASK_SHIFT)
-#define DMA_PMON_CNT_2_CFG_INC_SEL_M 0x3fULL
-#define DMA_PMON_CNT_2_CFG_INC_SEL_SHIFT 32
-#define DMA_PMON_CNT_2_CFG_INC_SEL_MASK (DMA_PMON_CNT_2_CFG_INC_SEL_M << DMA_PMON_CNT_2_CFG_INC_SEL_SHIFT)
-#define DMA_PMON_CNT_2_CFG_MODE_M 0x7ULL
-#define DMA_PMON_CNT_2_CFG_MODE_SHIFT 0
-#define DMA_PMON_CNT_2_CFG_MODE_MASK (DMA_PMON_CNT_2_CFG_MODE_M << DMA_PMON_CNT_2_CFG_MODE_SHIFT)
-#define DMA_PMON_CNT_2_CFG_DEC_INV_M 0x1ULL
-#define DMA_PMON_CNT_2_CFG_DEC_INV_SHIFT 63
-#define DMA_PMON_CNT_2_CFG_DEC_INV_MASK (DMA_PMON_CNT_2_CFG_DEC_INV_M << DMA_PMON_CNT_2_CFG_DEC_INV_SHIFT)
-#define DMA_PMON_CNT_2_CFG_INC_INV_M 0x1ULL
-#define DMA_PMON_CNT_2_CFG_INC_INV_SHIFT 47
-#define DMA_PMON_CNT_2_CFG_INC_INV_MASK (DMA_PMON_CNT_2_CFG_INC_INV_M << DMA_PMON_CNT_2_CFG_INC_INV_SHIFT)
-#define DMA_PMON_CNT_2_CFG_DEC_MATCH_M 0xfULL
-#define DMA_PMON_CNT_2_CFG_DEC_MATCH_SHIFT 59
-#define DMA_PMON_CNT_2_CFG_DEC_MATCH_MASK (DMA_PMON_CNT_2_CFG_DEC_MATCH_M << DMA_PMON_CNT_2_CFG_DEC_MATCH_SHIFT)
-#define DMA_PMON_CNT_2 0x150
-#define DMA_PMON_CNT_2_DEF 0x0
-#define DMA_PMON_CNT_2_CNT_M 0xffffffffffULL
-#define DMA_PMON_CNT_2_CNT_SHIFT 0
-#define DMA_PMON_CNT_2_CNT_MASK (DMA_PMON_CNT_2_CNT_M << DMA_PMON_CNT_2_CNT_SHIFT)
-#define DMA_PMON_CNT_2_STS_ACC 0x158
-#define DMA_PMON_CNT_2_STS_ACC_DEF 0x0
-#define DMA_PMON_CNT_2_STS 0x160
-#define DMA_PMON_CNT_2_STS_DEF 0x0
-#define DMA_PMON_CNT_2_STS_CNT_OF_M 0x1ULL
-#define DMA_PMON_CNT_2_STS_CNT_OF_SHIFT 2
-#define DMA_PMON_CNT_2_STS_CNT_OF_MASK (DMA_PMON_CNT_2_STS_CNT_OF_M << DMA_PMON_CNT_2_STS_CNT_OF_SHIFT)
-#define DMA_PMON_CNT_2_STS_ACC_OF_M 0x1ULL
-#define DMA_PMON_CNT_2_STS_ACC_OF_SHIFT 0
-#define DMA_PMON_CNT_2_STS_ACC_OF_MASK (DMA_PMON_CNT_2_STS_ACC_OF_M << DMA_PMON_CNT_2_STS_ACC_OF_SHIFT)
-#define DMA_PMON_CNT_2_STS_ACC_UF_M 0x1ULL
-#define DMA_PMON_CNT_2_STS_ACC_UF_SHIFT 1
-#define DMA_PMON_CNT_2_STS_ACC_UF_MASK (DMA_PMON_CNT_2_STS_ACC_UF_M << DMA_PMON_CNT_2_STS_ACC_UF_SHIFT)
-#define DMA_PMON_CNT_3_CFG 0x168
-#define DMA_PMON_CNT_3_CFG_DEF 0x0
-#define DMA_PMON_CNT_3_CFG_INC_MASK_M 0xfULL
-#define DMA_PMON_CNT_3_CFG_INC_MASK_SHIFT 39
-#define DMA_PMON_CNT_3_CFG_INC_MASK_MASK (DMA_PMON_CNT_3_CFG_INC_MASK_M << DMA_PMON_CNT_3_CFG_INC_MASK_SHIFT)
-#define DMA_PMON_CNT_3_CFG_THRESHOLD_M 0xffULL
-#define DMA_PMON_CNT_3_CFG_THRESHOLD_SHIFT 3
-#define DMA_PMON_CNT_3_CFG_THRESHOLD_MASK (DMA_PMON_CNT_3_CFG_THRESHOLD_M << DMA_PMON_CNT_3_CFG_THRESHOLD_SHIFT)
-#define DMA_PMON_CNT_3_CFG_DEC_MATCH_M 0xfULL
-#define DMA_PMON_CNT_3_CFG_DEC_MATCH_SHIFT 59
-#define DMA_PMON_CNT_3_CFG_DEC_MATCH_MASK (DMA_PMON_CNT_3_CFG_DEC_MATCH_M << DMA_PMON_CNT_3_CFG_DEC_MATCH_SHIFT)
-#define DMA_PMON_CNT_3_CFG_INC_MATCH_M 0xfULL
-#define DMA_PMON_CNT_3_CFG_INC_MATCH_SHIFT 43
-#define DMA_PMON_CNT_3_CFG_INC_MATCH_MASK (DMA_PMON_CNT_3_CFG_INC_MATCH_M << DMA_PMON_CNT_3_CFG_INC_MATCH_SHIFT)
-#define DMA_PMON_CNT_3_CFG_DEC_SEL_M 0x3fULL
-#define DMA_PMON_CNT_3_CFG_DEC_SEL_SHIFT 48
-#define DMA_PMON_CNT_3_CFG_DEC_SEL_MASK (DMA_PMON_CNT_3_CFG_DEC_SEL_M << DMA_PMON_CNT_3_CFG_DEC_SEL_SHIFT)
-#define DMA_PMON_CNT_3_CFG_DEC_INV_M 0x1ULL
-#define DMA_PMON_CNT_3_CFG_DEC_INV_SHIFT 63
-#define DMA_PMON_CNT_3_CFG_DEC_INV_MASK (DMA_PMON_CNT_3_CFG_DEC_INV_M << DMA_PMON_CNT_3_CFG_DEC_INV_SHIFT)
-#define DMA_PMON_CNT_3_CFG_DEC_MASK_M 0xfULL
-#define DMA_PMON_CNT_3_CFG_DEC_MASK_SHIFT 55
-#define DMA_PMON_CNT_3_CFG_DEC_MASK_MASK (DMA_PMON_CNT_3_CFG_DEC_MASK_M << DMA_PMON_CNT_3_CFG_DEC_MASK_SHIFT)
-#define DMA_PMON_CNT_3_CFG_MODE_M 0x7ULL
-#define DMA_PMON_CNT_3_CFG_MODE_SHIFT 0
-#define DMA_PMON_CNT_3_CFG_MODE_MASK (DMA_PMON_CNT_3_CFG_MODE_M << DMA_PMON_CNT_3_CFG_MODE_SHIFT)
-#define DMA_PMON_CNT_3_CFG_INC_SEL_M 0x3fULL
-#define DMA_PMON_CNT_3_CFG_INC_SEL_SHIFT 32
-#define DMA_PMON_CNT_3_CFG_INC_SEL_MASK (DMA_PMON_CNT_3_CFG_INC_SEL_M << DMA_PMON_CNT_3_CFG_INC_SEL_SHIFT)
-#define DMA_PMON_CNT_3_CFG_INC_INV_M 0x1ULL
-#define DMA_PMON_CNT_3_CFG_INC_INV_SHIFT 47
-#define DMA_PMON_CNT_3_CFG_INC_INV_MASK (DMA_PMON_CNT_3_CFG_INC_INV_M << DMA_PMON_CNT_3_CFG_INC_INV_SHIFT)
-#define DMA_PMON_CNT_3 0x170
-#define DMA_PMON_CNT_3_DEF 0x0
-#define DMA_PMON_CNT_3_CNT_M 0xffffffffffULL
-#define DMA_PMON_CNT_3_CNT_SHIFT 0
-#define DMA_PMON_CNT_3_CNT_MASK (DMA_PMON_CNT_3_CNT_M << DMA_PMON_CNT_3_CNT_SHIFT)
-#define DMA_PMON_CNT_3_STS_ACC 0x178
-#define DMA_PMON_CNT_3_STS_ACC_DEF 0x0
-#define DMA_PMON_CNT_3_STS 0x180
-#define DMA_PMON_CNT_3_STS_DEF 0x0
-#define DMA_PMON_CNT_3_STS_CNT_OF_M 0x1ULL
-#define DMA_PMON_CNT_3_STS_CNT_OF_SHIFT 2
-#define DMA_PMON_CNT_3_STS_CNT_OF_MASK (DMA_PMON_CNT_3_STS_CNT_OF_M << DMA_PMON_CNT_3_STS_CNT_OF_SHIFT)
-#define DMA_PMON_CNT_3_STS_ACC_OF_M 0x1ULL
-#define DMA_PMON_CNT_3_STS_ACC_OF_SHIFT 0
-#define DMA_PMON_CNT_3_STS_ACC_OF_MASK (DMA_PMON_CNT_3_STS_ACC_OF_M << DMA_PMON_CNT_3_STS_ACC_OF_SHIFT)
-#define DMA_PMON_CNT_3_STS_ACC_UF_M 0x1ULL
-#define DMA_PMON_CNT_3_STS_ACC_UF_SHIFT 1
-#define DMA_PMON_CNT_3_STS_ACC_UF_MASK (DMA_PMON_CNT_3_STS_ACC_UF_M << DMA_PMON_CNT_3_STS_ACC_UF_SHIFT)
-#define DMA_CHAN_MODE 0x188
-#define DMA_CHAN_MODE_DEF 0x40
-#define DMA_CHAN_MODE_PRI_M 0x1ULL
-#define DMA_CHAN_MODE_PRI_SHIFT 11
-#define DMA_CHAN_MODE_PRI_MASK (DMA_CHAN_MODE_PRI_M << DMA_CHAN_MODE_PRI_SHIFT)
-#define DMA_CHAN_MODE_CHAN_ENA_M 0x1ULL
-#define DMA_CHAN_MODE_CHAN_ENA_SHIFT 0
-#define DMA_CHAN_MODE_CHAN_ENA_MASK (DMA_CHAN_MODE_CHAN_ENA_M << DMA_CHAN_MODE_CHAN_ENA_SHIFT)
-#define DMA_CHAN_MODE_DST_M 0x3ULL
-#define DMA_CHAN_MODE_DST_SHIFT 6
-#define DMA_CHAN_MODE_DST_MASK (DMA_CHAN_MODE_DST_M << DMA_CHAN_MODE_DST_SHIFT)
-#define DMA_CHAN_MODE_ADDR_MODE_M 0x1ULL
-#define DMA_CHAN_MODE_ADDR_MODE_SHIFT 8
-#define DMA_CHAN_MODE_ADDR_MODE_MASK (DMA_CHAN_MODE_ADDR_MODE_M << DMA_CHAN_MODE_ADDR_MODE_SHIFT)
-#define DMA_CHAN_MODE_SRC_M 0x3ULL
-#define DMA_CHAN_MODE_SRC_SHIFT 4
-#define DMA_CHAN_MODE_SRC_MASK (DMA_CHAN_MODE_SRC_M << DMA_CHAN_MODE_SRC_SHIFT)
-#define DMA_CHAN_MODE_SIGN_EXT_M 0x1ULL
-#define DMA_CHAN_MODE_SIGN_EXT_SHIFT 10
-#define DMA_CHAN_MODE_SIGN_EXT_MASK (DMA_CHAN_MODE_SIGN_EXT_M << DMA_CHAN_MODE_SIGN_EXT_SHIFT)
-#define DMA_CHAN_MODE_GATHER_M 0x1ULL
-#define DMA_CHAN_MODE_GATHER_SHIFT 9
-#define DMA_CHAN_MODE_GATHER_MASK (DMA_CHAN_MODE_GATHER_M << DMA_CHAN_MODE_GATHER_SHIFT)
-#define DMA_CHAN_IMG_FORMAT 0x190
-#define DMA_CHAN_IMG_FORMAT_DEF 0x0
-#define DMA_CHAN_IMG_FORMAT_COMPONENTS_M 0x3ULL
-#define DMA_CHAN_IMG_FORMAT_COMPONENTS_SHIFT 0
-#define DMA_CHAN_IMG_FORMAT_COMPONENTS_MASK (DMA_CHAN_IMG_FORMAT_COMPONENTS_M << DMA_CHAN_IMG_FORMAT_COMPONENTS_SHIFT)
-#define DMA_CHAN_IMG_FORMAT_PLANES_M 0x3fULL
-#define DMA_CHAN_IMG_FORMAT_PLANES_SHIFT 4
-#define DMA_CHAN_IMG_FORMAT_PLANES_MASK (DMA_CHAN_IMG_FORMAT_PLANES_M << DMA_CHAN_IMG_FORMAT_PLANES_SHIFT)
-#define DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_M 0x1ULL
-#define DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_SHIFT 20
-#define DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_MASK (DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_M << DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_SHIFT)
-#define DMA_CHAN_IMG_FORMAT_BIT_DEPTH_M 0x7ULL
-#define DMA_CHAN_IMG_FORMAT_BIT_DEPTH_SHIFT 12
-#define DMA_CHAN_IMG_FORMAT_BIT_DEPTH_MASK (DMA_CHAN_IMG_FORMAT_BIT_DEPTH_M << DMA_CHAN_IMG_FORMAT_BIT_DEPTH_SHIFT)
-#define DMA_CHAN_IMG_FORMAT_BLOCK_4X4_M 0x1ULL
-#define DMA_CHAN_IMG_FORMAT_BLOCK_4X4_SHIFT 26
-#define DMA_CHAN_IMG_FORMAT_BLOCK_4X4_MASK (DMA_CHAN_IMG_FORMAT_BLOCK_4X4_M << DMA_CHAN_IMG_FORMAT_BLOCK_4X4_SHIFT)
-#define DMA_CHAN_IMG_SIZE 0x198
-#define DMA_CHAN_IMG_SIZE_DEF 0x200080
-#define DMA_CHAN_IMG_SIZE_IMG_HEIGHT_M 0xffffULL
-#define DMA_CHAN_IMG_SIZE_IMG_HEIGHT_SHIFT 16
-#define DMA_CHAN_IMG_SIZE_IMG_HEIGHT_MASK (DMA_CHAN_IMG_SIZE_IMG_HEIGHT_M << DMA_CHAN_IMG_SIZE_IMG_HEIGHT_SHIFT)
-#define DMA_CHAN_IMG_SIZE_IMG_WIDTH_M 0xffffULL
-#define DMA_CHAN_IMG_SIZE_IMG_WIDTH_SHIFT 0
-#define DMA_CHAN_IMG_SIZE_IMG_WIDTH_MASK (DMA_CHAN_IMG_SIZE_IMG_WIDTH_M << DMA_CHAN_IMG_SIZE_IMG_WIDTH_SHIFT)
-#define DMA_CHAN_IMG_POS 0x1a0
-#define DMA_CHAN_IMG_POS_DEF 0x0
-#define DMA_CHAN_IMG_POS_START_X_M 0xffffULL
-#define DMA_CHAN_IMG_POS_START_X_SHIFT 0
-#define DMA_CHAN_IMG_POS_START_X_MASK (DMA_CHAN_IMG_POS_START_X_M << DMA_CHAN_IMG_POS_START_X_SHIFT)
-#define DMA_CHAN_IMG_POS_START_Y_M 0xffffULL
-#define DMA_CHAN_IMG_POS_START_Y_SHIFT 16
-#define DMA_CHAN_IMG_POS_START_Y_MASK (DMA_CHAN_IMG_POS_START_Y_M << DMA_CHAN_IMG_POS_START_Y_SHIFT)
-#define DMA_CHAN_IMG_POS_LB_START_X_M 0xffffULL
-#define DMA_CHAN_IMG_POS_LB_START_X_SHIFT 32
-#define DMA_CHAN_IMG_POS_LB_START_X_MASK (DMA_CHAN_IMG_POS_LB_START_X_M << DMA_CHAN_IMG_POS_LB_START_X_SHIFT)
-#define DMA_CHAN_IMG_POS_LB_START_Y_M 0xffffULL
-#define DMA_CHAN_IMG_POS_LB_START_Y_SHIFT 48
-#define DMA_CHAN_IMG_POS_LB_START_Y_MASK (DMA_CHAN_IMG_POS_LB_START_Y_M << DMA_CHAN_IMG_POS_LB_START_Y_SHIFT)
-#define DMA_CHAN_IMG_LAYOUT 0x1a8
-#define DMA_CHAN_IMG_LAYOUT_DEF 0x0
-#define DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_M 0x7ffffffffULL
-#define DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_SHIFT 0
-#define DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_MASK (DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_M << DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_SHIFT)
-#define DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_M 0xffffULL
-#define DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_SHIFT 35
-#define DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_MASK (DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_M << DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_SHIFT)
-#define DMA_CHAN_BIF_XFER 0x1b0
-#define DMA_CHAN_BIF_XFER_DEF 0x100004
-#define DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_M 0xffffULL
-#define DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_SHIFT 0
-#define DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_MASK (DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_M << DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_SHIFT)
-#define DMA_CHAN_BIF_XFER_OUTSTANDING_M 0x7fULL
-#define DMA_CHAN_BIF_XFER_OUTSTANDING_SHIFT 16
-#define DMA_CHAN_BIF_XFER_OUTSTANDING_MASK (DMA_CHAN_BIF_XFER_OUTSTANDING_M << DMA_CHAN_BIF_XFER_OUTSTANDING_SHIFT)
-#define DMA_CHAN_VA 0x1b8
-#define DMA_CHAN_VA_DEF 0x0
-#define DMA_CHAN_VA_BASE_M 0x7ffffffffffULL
-#define DMA_CHAN_VA_BASE_SHIFT 0
-#define DMA_CHAN_VA_BASE_MASK (DMA_CHAN_VA_BASE_M << DMA_CHAN_VA_BASE_SHIFT)
-#define DMA_CHAN_VA_BDRY 0x1c0
-#define DMA_CHAN_VA_BDRY_DEF 0x0
-#define DMA_CHAN_VA_BDRY_LEN_M 0x1ffffffffffULL
-#define DMA_CHAN_VA_BDRY_LEN_SHIFT 0
-#define DMA_CHAN_VA_BDRY_LEN_MASK (DMA_CHAN_VA_BDRY_LEN_M << DMA_CHAN_VA_BDRY_LEN_SHIFT)
-#define DMA_CHAN_NOC_XFER 0x1c8
-#define DMA_CHAN_NOC_XFER_DEF 0x6400804040
-#define DMA_CHAN_NOC_XFER_SHEET_WIDTH_M 0x1ffULL
-#define DMA_CHAN_NOC_XFER_SHEET_WIDTH_SHIFT 0
-#define DMA_CHAN_NOC_XFER_SHEET_WIDTH_MASK (DMA_CHAN_NOC_XFER_SHEET_WIDTH_M << DMA_CHAN_NOC_XFER_SHEET_WIDTH_SHIFT)
-#define DMA_CHAN_NOC_XFER_OUTSTANDING_M 0xfULL
-#define DMA_CHAN_NOC_XFER_OUTSTANDING_SHIFT 20
-#define DMA_CHAN_NOC_XFER_OUTSTANDING_MASK (DMA_CHAN_NOC_XFER_OUTSTANDING_M << DMA_CHAN_NOC_XFER_OUTSTANDING_SHIFT)
-#define DMA_CHAN_NOC_XFER_SHEET_HEIGHT_M 0x1fULL
-#define DMA_CHAN_NOC_XFER_SHEET_HEIGHT_SHIFT 12
-#define DMA_CHAN_NOC_XFER_SHEET_HEIGHT_MASK (DMA_CHAN_NOC_XFER_SHEET_HEIGHT_M << DMA_CHAN_NOC_XFER_SHEET_HEIGHT_SHIFT)
-#define DMA_CHAN_NOC_XFER_RETRY_INTERVAL_M 0x3ffULL
-#define DMA_CHAN_NOC_XFER_RETRY_INTERVAL_SHIFT 32
-#define DMA_CHAN_NOC_XFER_RETRY_INTERVAL_MASK (DMA_CHAN_NOC_XFER_RETRY_INTERVAL_M << DMA_CHAN_NOC_XFER_RETRY_INTERVAL_SHIFT)
-#define DMA_CHAN_NODE 0x1d0
-#define DMA_CHAN_NODE_DEF 0x0
-#define DMA_CHAN_NODE_CORE_ID_M 0xfULL
-#define DMA_CHAN_NODE_CORE_ID_SHIFT 0
-#define DMA_CHAN_NODE_CORE_ID_MASK (DMA_CHAN_NODE_CORE_ID_M << DMA_CHAN_NODE_CORE_ID_SHIFT)
-#define DMA_CHAN_NODE_LB_ID_M 0x7ULL
-#define DMA_CHAN_NODE_LB_ID_SHIFT 8
-#define DMA_CHAN_NODE_LB_ID_MASK (DMA_CHAN_NODE_LB_ID_M << DMA_CHAN_NODE_LB_ID_SHIFT)
-#define DMA_CHAN_NODE_RPTR_ID_M 0x7ULL
-#define DMA_CHAN_NODE_RPTR_ID_SHIFT 16
-#define DMA_CHAN_NODE_RPTR_ID_MASK (DMA_CHAN_NODE_RPTR_ID_M << DMA_CHAN_NODE_RPTR_ID_SHIFT)
-#define DMA_CHAN_MODE_RO 0x1d8
-#define DMA_CHAN_MODE_RO_DEF 0x40
-#define DMA_CHAN_MODE_RO_SIGN_EXT_M 0x1ULL
-#define DMA_CHAN_MODE_RO_SIGN_EXT_SHIFT 10
-#define DMA_CHAN_MODE_RO_SIGN_EXT_MASK (DMA_CHAN_MODE_RO_SIGN_EXT_M << DMA_CHAN_MODE_RO_SIGN_EXT_SHIFT)
-#define DMA_CHAN_MODE_RO_ADDR_MODE_M 0x1ULL
-#define DMA_CHAN_MODE_RO_ADDR_MODE_SHIFT 8
-#define DMA_CHAN_MODE_RO_ADDR_MODE_MASK (DMA_CHAN_MODE_RO_ADDR_MODE_M << DMA_CHAN_MODE_RO_ADDR_MODE_SHIFT)
-#define DMA_CHAN_MODE_RO_DST_M 0x3ULL
-#define DMA_CHAN_MODE_RO_DST_SHIFT 6
-#define DMA_CHAN_MODE_RO_DST_MASK (DMA_CHAN_MODE_RO_DST_M << DMA_CHAN_MODE_RO_DST_SHIFT)
-#define DMA_CHAN_MODE_RO_PRI_M 0x1ULL
-#define DMA_CHAN_MODE_RO_PRI_SHIFT 11
-#define DMA_CHAN_MODE_RO_PRI_MASK (DMA_CHAN_MODE_RO_PRI_M << DMA_CHAN_MODE_RO_PRI_SHIFT)
-#define DMA_CHAN_MODE_RO_GATHER_M 0x1ULL
-#define DMA_CHAN_MODE_RO_GATHER_SHIFT 9
-#define DMA_CHAN_MODE_RO_GATHER_MASK (DMA_CHAN_MODE_RO_GATHER_M << DMA_CHAN_MODE_RO_GATHER_SHIFT)
-#define DMA_CHAN_MODE_RO_SRC_M 0x3ULL
-#define DMA_CHAN_MODE_RO_SRC_SHIFT 4
-#define DMA_CHAN_MODE_RO_SRC_MASK (DMA_CHAN_MODE_RO_SRC_M << DMA_CHAN_MODE_RO_SRC_SHIFT)
-#define DMA_CHAN_MODE_RO_CHAN_ENA_M 0x1ULL
-#define DMA_CHAN_MODE_RO_CHAN_ENA_SHIFT 0
-#define DMA_CHAN_MODE_RO_CHAN_ENA_MASK (DMA_CHAN_MODE_RO_CHAN_ENA_M << DMA_CHAN_MODE_RO_CHAN_ENA_SHIFT)
-#define DMA_CHAN_IMG_FORMAT_RO 0x1e0
-#define DMA_CHAN_IMG_FORMAT_RO_DEF 0x0
-#define DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_M 0x7ULL
-#define DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_SHIFT 12
-#define DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_MASK (DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_M << DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_SHIFT)
-#define DMA_CHAN_IMG_FORMAT_RO_PLANES_M 0x3fULL
-#define DMA_CHAN_IMG_FORMAT_RO_PLANES_SHIFT 4
-#define DMA_CHAN_IMG_FORMAT_RO_PLANES_MASK (DMA_CHAN_IMG_FORMAT_RO_PLANES_M << DMA_CHAN_IMG_FORMAT_RO_PLANES_SHIFT)
-#define DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_M 0x3ULL
-#define DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_SHIFT 0
-#define DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_MASK (DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_M << DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_SHIFT)
-#define DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_M 0x1ULL
-#define DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_SHIFT 26
-#define DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_MASK (DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_M << DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_SHIFT)
-#define DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_M 0x1ULL
-#define DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_SHIFT 20
-#define DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_MASK (DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_M << DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_SHIFT)
-#define DMA_CHAN_IMG_SIZE_RO 0x1e8
-#define DMA_CHAN_IMG_SIZE_RO_DEF 0x200080
-#define DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_M 0xffffULL
-#define DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_SHIFT 16
-#define DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_MASK (DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_M << DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_SHIFT)
-#define DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_M 0xffffULL
-#define DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_SHIFT 0
-#define DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_MASK (DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_M << DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_SHIFT)
-#define DMA_CHAN_IMG_POS_RO 0x1f0
-#define DMA_CHAN_IMG_POS_RO_DEF 0x0
-#define DMA_CHAN_IMG_POS_RO_LB_START_Y_M 0xffffULL
-#define DMA_CHAN_IMG_POS_RO_LB_START_Y_SHIFT 48
-#define DMA_CHAN_IMG_POS_RO_LB_START_Y_MASK (DMA_CHAN_IMG_POS_RO_LB_START_Y_M << DMA_CHAN_IMG_POS_RO_LB_START_Y_SHIFT)
-#define DMA_CHAN_IMG_POS_RO_LB_START_X_M 0xffffULL
-#define DMA_CHAN_IMG_POS_RO_LB_START_X_SHIFT 32
-#define DMA_CHAN_IMG_POS_RO_LB_START_X_MASK (DMA_CHAN_IMG_POS_RO_LB_START_X_M << DMA_CHAN_IMG_POS_RO_LB_START_X_SHIFT)
-#define DMA_CHAN_IMG_POS_RO_START_Y_M 0xffffULL
-#define DMA_CHAN_IMG_POS_RO_START_Y_SHIFT 16
-#define DMA_CHAN_IMG_POS_RO_START_Y_MASK (DMA_CHAN_IMG_POS_RO_START_Y_M << DMA_CHAN_IMG_POS_RO_START_Y_SHIFT)
-#define DMA_CHAN_IMG_POS_RO_START_X_M 0xffffULL
-#define DMA_CHAN_IMG_POS_RO_START_X_SHIFT 0
-#define DMA_CHAN_IMG_POS_RO_START_X_MASK (DMA_CHAN_IMG_POS_RO_START_X_M << DMA_CHAN_IMG_POS_RO_START_X_SHIFT)
-#define DMA_CHAN_IMG_LAYOUT_RO 0x1f8
-#define DMA_CHAN_IMG_LAYOUT_RO_DEF 0x0
-#define DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_M 0xffffULL
-#define DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_SHIFT 35
-#define DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_MASK (DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_M << DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_SHIFT)
-#define DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_M 0x7ffffffffULL
-#define DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_SHIFT 0
-#define DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_MASK (DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_M << DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_SHIFT)
-#define DMA_CHAN_BIF_XFER_RO 0x200
-#define DMA_CHAN_BIF_XFER_RO_DEF 0x100004
-#define DMA_CHAN_BIF_XFER_RO_OUTSTANDING_M 0x7fULL
-#define DMA_CHAN_BIF_XFER_RO_OUTSTANDING_SHIFT 16
-#define DMA_CHAN_BIF_XFER_RO_OUTSTANDING_MASK (DMA_CHAN_BIF_XFER_RO_OUTSTANDING_M << DMA_CHAN_BIF_XFER_RO_OUTSTANDING_SHIFT)
-#define DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_M 0xffffULL
-#define DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_SHIFT 0
-#define DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_MASK (DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_M << DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_SHIFT)
-#define DMA_CHAN_VA_RO 0x208
-#define DMA_CHAN_VA_RO_DEF 0x0
-#define DMA_CHAN_VA_RO_BASE_M 0x7ffffffffffULL
-#define DMA_CHAN_VA_RO_BASE_SHIFT 0
-#define DMA_CHAN_VA_RO_BASE_MASK (DMA_CHAN_VA_RO_BASE_M << DMA_CHAN_VA_RO_BASE_SHIFT)
-#define DMA_CHAN_VA_BDRY_RO 0x210
-#define DMA_CHAN_VA_BDRY_RO_DEF 0x0
-#define DMA_CHAN_VA_BDRY_RO_LEN_M 0x1ffffffffffULL
-#define DMA_CHAN_VA_BDRY_RO_LEN_SHIFT 0
-#define DMA_CHAN_VA_BDRY_RO_LEN_MASK (DMA_CHAN_VA_BDRY_RO_LEN_M << DMA_CHAN_VA_BDRY_RO_LEN_SHIFT)
-#define DMA_CHAN_NOC_XFER_RO 0x218
-#define DMA_CHAN_NOC_XFER_RO_DEF 0x6400804040
-#define DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_M 0x1ffULL
-#define DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_SHIFT 0
-#define DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_MASK (DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_M << DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_SHIFT)
-#define DMA_CHAN_NOC_XFER_RO_OUTSTANDING_M 0xfULL
-#define DMA_CHAN_NOC_XFER_RO_OUTSTANDING_SHIFT 20
-#define DMA_CHAN_NOC_XFER_RO_OUTSTANDING_MASK (DMA_CHAN_NOC_XFER_RO_OUTSTANDING_M << DMA_CHAN_NOC_XFER_RO_OUTSTANDING_SHIFT)
-#define DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_M 0x3ffULL
-#define DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_SHIFT 32
-#define DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_MASK (DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_M << DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_SHIFT)
-#define DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_M 0x1fULL
-#define DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_SHIFT 12
-#define DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_MASK (DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_M << DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_SHIFT)
-#define DMA_CHAN_NODE_RO 0x220
-#define DMA_CHAN_NODE_RO_DEF 0x0
-#define DMA_CHAN_NODE_RO_CORE_ID_M 0xfULL
-#define DMA_CHAN_NODE_RO_CORE_ID_SHIFT 0
-#define DMA_CHAN_NODE_RO_CORE_ID_MASK (DMA_CHAN_NODE_RO_CORE_ID_M << DMA_CHAN_NODE_RO_CORE_ID_SHIFT)
-#define DMA_CHAN_NODE_RO_LB_ID_M 0x7ULL
-#define DMA_CHAN_NODE_RO_LB_ID_SHIFT 8
-#define DMA_CHAN_NODE_RO_LB_ID_MASK (DMA_CHAN_NODE_RO_LB_ID_M << DMA_CHAN_NODE_RO_LB_ID_SHIFT)
-#define DMA_CHAN_NODE_RO_RPTR_ID_M 0x7ULL
-#define DMA_CHAN_NODE_RO_RPTR_ID_SHIFT 16
-#define DMA_CHAN_NODE_RO_RPTR_ID_MASK (DMA_CHAN_NODE_RO_RPTR_ID_M << DMA_CHAN_NODE_RO_RPTR_ID_SHIFT)
-#define DMA_CHAN_DEPENDENCY 0x228
-#define DMA_CHAN_DEPENDENCY_DEF 0x0
-#define DMA_CHAN_DEPENDENCY_DEP_EN_M 0xffffULL
-#define DMA_CHAN_DEPENDENCY_DEP_EN_SHIFT 0
-#define DMA_CHAN_DEPENDENCY_DEP_EN_MASK (DMA_CHAN_DEPENDENCY_DEP_EN_M << DMA_CHAN_DEPENDENCY_DEP_EN_SHIFT)
-#define DMA_STAT_CTRL 0x230
-#define DMA_STAT_CTRL_DEF 0x0
-#define DMA_STAT_CTRL_ENABLE_M 0x1ULL
-#define DMA_STAT_CTRL_ENABLE_SHIFT 0
-#define DMA_STAT_CTRL_ENABLE_MASK (DMA_STAT_CTRL_ENABLE_M << DMA_STAT_CTRL_ENABLE_SHIFT)
-#define DMA_STAT_CTRL_ADDR_MODE_M 0x1ULL
-#define DMA_STAT_CTRL_ADDR_MODE_SHIFT 6
-#define DMA_STAT_CTRL_ADDR_MODE_MASK (DMA_STAT_CTRL_ADDR_MODE_M << DMA_STAT_CTRL_ADDR_MODE_SHIFT)
-#define DMA_STAT_CTRL_CHAN_SEL_M 0xfULL
-#define DMA_STAT_CTRL_CHAN_SEL_SHIFT 1
-#define DMA_STAT_CTRL_CHAN_SEL_MASK (DMA_STAT_CTRL_CHAN_SEL_M << DMA_STAT_CTRL_CHAN_SEL_SHIFT)
-#define DMA_STAT_CTRL_DST_BIF_SEL_SSP_M 0x1ULL
-#define DMA_STAT_CTRL_DST_BIF_SEL_SSP_SHIFT 5
-#define DMA_STAT_CTRL_DST_BIF_SEL_SSP_MASK (DMA_STAT_CTRL_DST_BIF_SEL_SSP_M << DMA_STAT_CTRL_DST_BIF_SEL_SSP_SHIFT)
-#define DMA_STAT_STATE 0x238
-#define DMA_STAT_STATE_DEF 0x0
-#define DMA_STAT_STATE_WR_MNGR_CHAN_MODE_M 0x1ULL
-#define DMA_STAT_STATE_WR_MNGR_CHAN_MODE_SHIFT 19
-#define DMA_STAT_STATE_WR_MNGR_CHAN_MODE_MASK (DMA_STAT_STATE_WR_MNGR_CHAN_MODE_M << DMA_STAT_STATE_WR_MNGR_CHAN_MODE_SHIFT)
-#define DMA_STAT_STATE_WR_MNGR_CHAN_M 0xfULL
-#define DMA_STAT_STATE_WR_MNGR_CHAN_SHIFT 12
-#define DMA_STAT_STATE_WR_MNGR_CHAN_MASK (DMA_STAT_STATE_WR_MNGR_CHAN_M << DMA_STAT_STATE_WR_MNGR_CHAN_SHIFT)
-#define DMA_STAT_STATE_SRC_MODE_M 0x1ULL
-#define DMA_STAT_STATE_SRC_MODE_SHIFT 16
-#define DMA_STAT_STATE_SRC_MODE_MASK (DMA_STAT_STATE_SRC_MODE_M << DMA_STAT_STATE_SRC_MODE_SHIFT)
-#define DMA_STAT_STATE_RD_MNGR_CHAN_M 0xfULL
-#define DMA_STAT_STATE_RD_MNGR_CHAN_SHIFT 8
-#define DMA_STAT_STATE_RD_MNGR_CHAN_MASK (DMA_STAT_STATE_RD_MNGR_CHAN_M << DMA_STAT_STATE_RD_MNGR_CHAN_SHIFT)
-#define DMA_STAT_STATE_SRC_M 0xfULL
-#define DMA_STAT_STATE_SRC_SHIFT 0
-#define DMA_STAT_STATE_SRC_MASK (DMA_STAT_STATE_SRC_M << DMA_STAT_STATE_SRC_SHIFT)
-#define DMA_STAT_STATE_RD_MNGR_CHAN_MODE_M 0x1ULL
-#define DMA_STAT_STATE_RD_MNGR_CHAN_MODE_SHIFT 18
-#define DMA_STAT_STATE_RD_MNGR_CHAN_MODE_MASK (DMA_STAT_STATE_RD_MNGR_CHAN_MODE_M << DMA_STAT_STATE_RD_MNGR_CHAN_MODE_SHIFT)
-#define DMA_STAT_STATE_DST_MODE_M 0x1ULL
-#define DMA_STAT_STATE_DST_MODE_SHIFT 17
-#define DMA_STAT_STATE_DST_MODE_MASK (DMA_STAT_STATE_DST_MODE_M << DMA_STAT_STATE_DST_MODE_SHIFT)
-#define DMA_STAT_STATE_DST_M 0xfULL
-#define DMA_STAT_STATE_DST_SHIFT 4
-#define DMA_STAT_STATE_DST_MASK (DMA_STAT_STATE_DST_M << DMA_STAT_STATE_DST_SHIFT)
-#define DMA_STAT_PTR 0x240
-#define DMA_STAT_PTR_DEF 0x0
-#define DMA_STAT_PTR_MODE_M 0x1ULL
-#define DMA_STAT_PTR_MODE_SHIFT 63
-#define DMA_STAT_PTR_MODE_MASK (DMA_STAT_PTR_MODE_M << DMA_STAT_PTR_MODE_SHIFT)
-#define DMA_STAT_PTR_Y_M 0xffffULL
-#define DMA_STAT_PTR_Y_SHIFT 16
-#define DMA_STAT_PTR_Y_MASK (DMA_STAT_PTR_Y_M << DMA_STAT_PTR_Y_SHIFT)
-#define DMA_STAT_PTR_X_M 0xffffULL
-#define DMA_STAT_PTR_X_SHIFT 0
-#define DMA_STAT_PTR_X_MASK (DMA_STAT_PTR_X_M << DMA_STAT_PTR_X_SHIFT)
-#define DMA_STAT_PTR_SHEET_HEIGHT_M 0x1fULL
-#define DMA_STAT_PTR_SHEET_HEIGHT_SHIFT 44
-#define DMA_STAT_PTR_SHEET_HEIGHT_MASK (DMA_STAT_PTR_SHEET_HEIGHT_M << DMA_STAT_PTR_SHEET_HEIGHT_SHIFT)
-#define DMA_STAT_PTR_SHEET_WIDTH_M 0x1ffULL
-#define DMA_STAT_PTR_SHEET_WIDTH_SHIFT 32
-#define DMA_STAT_PTR_SHEET_WIDTH_MASK (DMA_STAT_PTR_SHEET_WIDTH_M << DMA_STAT_PTR_SHEET_WIDTH_SHIFT)
-#define DMA_STAT_ADDR 0x248
-#define DMA_STAT_ADDR_DEF 0x0
-#define DMA_STAT_ADDR_ADDR_M 0x7ffffffffffULL
-#define DMA_STAT_ADDR_ADDR_SHIFT 0
-#define DMA_STAT_ADDR_ADDR_MASK (DMA_STAT_ADDR_ADDR_M << DMA_STAT_ADDR_ADDR_SHIFT)
-#define DMA_SPARE 0x250
-#define DMA_SPARE_DEF 0x0
-#define DMA_SPARE_SPARE0_M 0x1ULL
-#define DMA_SPARE_SPARE0_SHIFT 0
-#define DMA_SPARE_SPARE0_MASK (DMA_SPARE_SPARE0_M << DMA_SPARE_SPARE0_SHIFT)
-#define DMA_SPARE_SPARE1_M 0x1ULL
-#define DMA_SPARE_SPARE1_SHIFT 1
-#define DMA_SPARE_SPARE1_MASK (DMA_SPARE_SPARE1_M << DMA_SPARE_SPARE1_SHIFT)
-#define DMA_SPARE_SPARE2_M 0x1ULL
-#define DMA_SPARE_SPARE2_SHIFT 2
-#define DMA_SPARE_SPARE2_MASK (DMA_SPARE_SPARE2_M << DMA_SPARE_SPARE2_SHIFT)
-#define DMA_SPARE_SPARE3_M 0x1ULL
-#define DMA_SPARE_SPARE3_SHIFT 3
-#define DMA_SPARE_SPARE3_MASK (DMA_SPARE_SPARE3_M << DMA_SPARE_SPARE3_SHIFT)
-#define DMA_SPARE_SPARE4_M 0x1ULL
-#define DMA_SPARE_SPARE4_SHIFT 4
-#define DMA_SPARE_SPARE4_MASK (DMA_SPARE_SPARE4_M << DMA_SPARE_SPARE4_SHIFT)
-#define DMA_SPARE_SPARE5_M 0x1ULL
-#define DMA_SPARE_SPARE5_SHIFT 5
-#define DMA_SPARE_SPARE5_MASK (DMA_SPARE_SPARE5_M << DMA_SPARE_SPARE5_SHIFT)
-#define DMA_SPARE_SPARE6_M 0x1ULL
-#define DMA_SPARE_SPARE6_SHIFT 6
-#define DMA_SPARE_SPARE6_MASK (DMA_SPARE_SPARE6_M << DMA_SPARE_SPARE6_SHIFT)
-#define DMA_SPARE_SPARE7_M 0x1ULL
-#define DMA_SPARE_SPARE7_SHIFT 7
-#define DMA_SPARE_SPARE7_MASK (DMA_SPARE_SPARE7_M << DMA_SPARE_SPARE7_SHIFT)
-#define DMA_SPARE_SPARE8_M 0x1ULL
-#define DMA_SPARE_SPARE8_SHIFT 8
-#define DMA_SPARE_SPARE8_MASK (DMA_SPARE_SPARE8_M << DMA_SPARE_SPARE8_SHIFT)
-#define DMA_SPARE_SPARE9_M 0x1ULL
-#define DMA_SPARE_SPARE9_SHIFT 9
-#define DMA_SPARE_SPARE9_MASK (DMA_SPARE_SPARE9_M << DMA_SPARE_SPARE9_SHIFT)
-#define DMA_SPARE_SPARE55_M 0x1ULL
-#define DMA_SPARE_SPARE55_SHIFT 55
-#define DMA_SPARE_SPARE55_MASK (DMA_SPARE_SPARE55_M << DMA_SPARE_SPARE55_SHIFT)
-#define DMA_SPARE_SPARE61_M 0x1ULL
-#define DMA_SPARE_SPARE61_SHIFT 61
-#define DMA_SPARE_SPARE61_MASK (DMA_SPARE_SPARE61_M << DMA_SPARE_SPARE61_SHIFT)
-#define DMA_SPARE_SPARE23_M 0x1ULL
-#define DMA_SPARE_SPARE23_SHIFT 23
-#define DMA_SPARE_SPARE23_MASK (DMA_SPARE_SPARE23_M << DMA_SPARE_SPARE23_SHIFT)
-#define DMA_SPARE_SPARE22_M 0x1ULL
-#define DMA_SPARE_SPARE22_SHIFT 22
-#define DMA_SPARE_SPARE22_MASK (DMA_SPARE_SPARE22_M << DMA_SPARE_SPARE22_SHIFT)
-#define DMA_SPARE_SPARE21_M 0x1ULL
-#define DMA_SPARE_SPARE21_SHIFT 21
-#define DMA_SPARE_SPARE21_MASK (DMA_SPARE_SPARE21_M << DMA_SPARE_SPARE21_SHIFT)
-#define DMA_SPARE_SPARE20_M 0x1ULL
-#define DMA_SPARE_SPARE20_SHIFT 20
-#define DMA_SPARE_SPARE20_MASK (DMA_SPARE_SPARE20_M << DMA_SPARE_SPARE20_SHIFT)
-#define DMA_SPARE_SPARE27_M 0x1ULL
-#define DMA_SPARE_SPARE27_SHIFT 27
-#define DMA_SPARE_SPARE27_MASK (DMA_SPARE_SPARE27_M << DMA_SPARE_SPARE27_SHIFT)
-#define DMA_SPARE_SPARE26_M 0x1ULL
-#define DMA_SPARE_SPARE26_SHIFT 26
-#define DMA_SPARE_SPARE26_MASK (DMA_SPARE_SPARE26_M << DMA_SPARE_SPARE26_SHIFT)
-#define DMA_SPARE_SPARE25_M 0x1ULL
-#define DMA_SPARE_SPARE25_SHIFT 25
-#define DMA_SPARE_SPARE25_MASK (DMA_SPARE_SPARE25_M << DMA_SPARE_SPARE25_SHIFT)
-#define DMA_SPARE_SPARE24_M 0x1ULL
-#define DMA_SPARE_SPARE24_SHIFT 24
-#define DMA_SPARE_SPARE24_MASK (DMA_SPARE_SPARE24_M << DMA_SPARE_SPARE24_SHIFT)
-#define DMA_SPARE_SPARE29_M 0x1ULL
-#define DMA_SPARE_SPARE29_SHIFT 29
-#define DMA_SPARE_SPARE29_MASK (DMA_SPARE_SPARE29_M << DMA_SPARE_SPARE29_SHIFT)
-#define DMA_SPARE_SPARE28_M 0x1ULL
-#define DMA_SPARE_SPARE28_SHIFT 28
-#define DMA_SPARE_SPARE28_MASK (DMA_SPARE_SPARE28_M << DMA_SPARE_SPARE28_SHIFT)
-#define DMA_SPARE_SPARE59_M 0x1ULL
-#define DMA_SPARE_SPARE59_SHIFT 59
-#define DMA_SPARE_SPARE59_MASK (DMA_SPARE_SPARE59_M << DMA_SPARE_SPARE59_SHIFT)
-#define DMA_SPARE_SPARE54_M 0x1ULL
-#define DMA_SPARE_SPARE54_SHIFT 54
-#define DMA_SPARE_SPARE54_MASK (DMA_SPARE_SPARE54_M << DMA_SPARE_SPARE54_SHIFT)
-#define DMA_SPARE_SPARE45_M 0x1ULL
-#define DMA_SPARE_SPARE45_SHIFT 45
-#define DMA_SPARE_SPARE45_MASK (DMA_SPARE_SPARE45_M << DMA_SPARE_SPARE45_SHIFT)
-#define DMA_SPARE_SPARE44_M 0x1ULL
-#define DMA_SPARE_SPARE44_SHIFT 44
-#define DMA_SPARE_SPARE44_MASK (DMA_SPARE_SPARE44_M << DMA_SPARE_SPARE44_SHIFT)
-#define DMA_SPARE_SPARE47_M 0x1ULL
-#define DMA_SPARE_SPARE47_SHIFT 47
-#define DMA_SPARE_SPARE47_MASK (DMA_SPARE_SPARE47_M << DMA_SPARE_SPARE47_SHIFT)
-#define DMA_SPARE_SPARE46_M 0x1ULL
-#define DMA_SPARE_SPARE46_SHIFT 46
-#define DMA_SPARE_SPARE46_MASK (DMA_SPARE_SPARE46_M << DMA_SPARE_SPARE46_SHIFT)
-#define DMA_SPARE_SPARE41_M 0x1ULL
-#define DMA_SPARE_SPARE41_SHIFT 41
-#define DMA_SPARE_SPARE41_MASK (DMA_SPARE_SPARE41_M << DMA_SPARE_SPARE41_SHIFT)
-#define DMA_SPARE_SPARE40_M 0x1ULL
-#define DMA_SPARE_SPARE40_SHIFT 40
-#define DMA_SPARE_SPARE40_MASK (DMA_SPARE_SPARE40_M << DMA_SPARE_SPARE40_SHIFT)
-#define DMA_SPARE_SPARE43_M 0x1ULL
-#define DMA_SPARE_SPARE43_SHIFT 43
-#define DMA_SPARE_SPARE43_MASK (DMA_SPARE_SPARE43_M << DMA_SPARE_SPARE43_SHIFT)
-#define DMA_SPARE_SPARE42_M 0x1ULL
-#define DMA_SPARE_SPARE42_SHIFT 42
-#define DMA_SPARE_SPARE42_MASK (DMA_SPARE_SPARE42_M << DMA_SPARE_SPARE42_SHIFT)
-#define DMA_SPARE_SPARE49_M 0x1ULL
-#define DMA_SPARE_SPARE49_SHIFT 49
-#define DMA_SPARE_SPARE49_MASK (DMA_SPARE_SPARE49_M << DMA_SPARE_SPARE49_SHIFT)
-#define DMA_SPARE_SPARE48_M 0x1ULL
-#define DMA_SPARE_SPARE48_SHIFT 48
-#define DMA_SPARE_SPARE48_MASK (DMA_SPARE_SPARE48_M << DMA_SPARE_SPARE48_SHIFT)
-#define DMA_SPARE_SPARE58_M 0x1ULL
-#define DMA_SPARE_SPARE58_SHIFT 58
-#define DMA_SPARE_SPARE58_MASK (DMA_SPARE_SPARE58_M << DMA_SPARE_SPARE58_SHIFT)
-#define DMA_SPARE_SPARE60_M 0x1ULL
-#define DMA_SPARE_SPARE60_SHIFT 60
-#define DMA_SPARE_SPARE60_MASK (DMA_SPARE_SPARE60_M << DMA_SPARE_SPARE60_SHIFT)
-#define DMA_SPARE_SPARE34_M 0x1ULL
-#define DMA_SPARE_SPARE34_SHIFT 34
-#define DMA_SPARE_SPARE34_MASK (DMA_SPARE_SPARE34_M << DMA_SPARE_SPARE34_SHIFT)
-#define DMA_SPARE_SPARE35_M 0x1ULL
-#define DMA_SPARE_SPARE35_SHIFT 35
-#define DMA_SPARE_SPARE35_MASK (DMA_SPARE_SPARE35_M << DMA_SPARE_SPARE35_SHIFT)
-#define DMA_SPARE_SPARE36_M 0x1ULL
-#define DMA_SPARE_SPARE36_SHIFT 36
-#define DMA_SPARE_SPARE36_MASK (DMA_SPARE_SPARE36_M << DMA_SPARE_SPARE36_SHIFT)
-#define DMA_SPARE_SPARE37_M 0x1ULL
-#define DMA_SPARE_SPARE37_SHIFT 37
-#define DMA_SPARE_SPARE37_MASK (DMA_SPARE_SPARE37_M << DMA_SPARE_SPARE37_SHIFT)
-#define DMA_SPARE_SPARE30_M 0x1ULL
-#define DMA_SPARE_SPARE30_SHIFT 30
-#define DMA_SPARE_SPARE30_MASK (DMA_SPARE_SPARE30_M << DMA_SPARE_SPARE30_SHIFT)
-#define DMA_SPARE_SPARE31_M 0x1ULL
-#define DMA_SPARE_SPARE31_SHIFT 31
-#define DMA_SPARE_SPARE31_MASK (DMA_SPARE_SPARE31_M << DMA_SPARE_SPARE31_SHIFT)
-#define DMA_SPARE_SPARE32_M 0x1ULL
-#define DMA_SPARE_SPARE32_SHIFT 32
-#define DMA_SPARE_SPARE32_MASK (DMA_SPARE_SPARE32_M << DMA_SPARE_SPARE32_SHIFT)
-#define DMA_SPARE_SPARE33_M 0x1ULL
-#define DMA_SPARE_SPARE33_SHIFT 33
-#define DMA_SPARE_SPARE33_MASK (DMA_SPARE_SPARE33_M << DMA_SPARE_SPARE33_SHIFT)
-#define DMA_SPARE_SPARE63_M 0x1ULL
-#define DMA_SPARE_SPARE63_SHIFT 63
-#define DMA_SPARE_SPARE63_MASK (DMA_SPARE_SPARE63_M << DMA_SPARE_SPARE63_SHIFT)
-#define DMA_SPARE_SPARE38_M 0x1ULL
-#define DMA_SPARE_SPARE38_SHIFT 38
-#define DMA_SPARE_SPARE38_MASK (DMA_SPARE_SPARE38_M << DMA_SPARE_SPARE38_SHIFT)
-#define DMA_SPARE_SPARE39_M 0x1ULL
-#define DMA_SPARE_SPARE39_SHIFT 39
-#define DMA_SPARE_SPARE39_MASK (DMA_SPARE_SPARE39_M << DMA_SPARE_SPARE39_SHIFT)
-#define DMA_SPARE_SPARE62_M 0x1ULL
-#define DMA_SPARE_SPARE62_SHIFT 62
-#define DMA_SPARE_SPARE62_MASK (DMA_SPARE_SPARE62_M << DMA_SPARE_SPARE62_SHIFT)
-#define DMA_SPARE_SPARE56_M 0x1ULL
-#define DMA_SPARE_SPARE56_SHIFT 56
-#define DMA_SPARE_SPARE56_MASK (DMA_SPARE_SPARE56_M << DMA_SPARE_SPARE56_SHIFT)
-#define DMA_SPARE_SPARE57_M 0x1ULL
-#define DMA_SPARE_SPARE57_SHIFT 57
-#define DMA_SPARE_SPARE57_MASK (DMA_SPARE_SPARE57_M << DMA_SPARE_SPARE57_SHIFT)
-#define DMA_SPARE_SPARE18_M 0x1ULL
-#define DMA_SPARE_SPARE18_SHIFT 18
-#define DMA_SPARE_SPARE18_MASK (DMA_SPARE_SPARE18_M << DMA_SPARE_SPARE18_SHIFT)
-#define DMA_SPARE_SPARE19_M 0x1ULL
-#define DMA_SPARE_SPARE19_SHIFT 19
-#define DMA_SPARE_SPARE19_MASK (DMA_SPARE_SPARE19_M << DMA_SPARE_SPARE19_SHIFT)
-#define DMA_SPARE_SPARE52_M 0x1ULL
-#define DMA_SPARE_SPARE52_SHIFT 52
-#define DMA_SPARE_SPARE52_MASK (DMA_SPARE_SPARE52_M << DMA_SPARE_SPARE52_SHIFT)
-#define DMA_SPARE_SPARE53_M 0x1ULL
-#define DMA_SPARE_SPARE53_SHIFT 53
-#define DMA_SPARE_SPARE53_MASK (DMA_SPARE_SPARE53_M << DMA_SPARE_SPARE53_SHIFT)
-#define DMA_SPARE_SPARE50_M 0x1ULL
-#define DMA_SPARE_SPARE50_SHIFT 50
-#define DMA_SPARE_SPARE50_MASK (DMA_SPARE_SPARE50_M << DMA_SPARE_SPARE50_SHIFT)
-#define DMA_SPARE_SPARE51_M 0x1ULL
-#define DMA_SPARE_SPARE51_SHIFT 51
-#define DMA_SPARE_SPARE51_MASK (DMA_SPARE_SPARE51_M << DMA_SPARE_SPARE51_SHIFT)
-#define DMA_SPARE_SPARE12_M 0x1ULL
-#define DMA_SPARE_SPARE12_SHIFT 12
-#define DMA_SPARE_SPARE12_MASK (DMA_SPARE_SPARE12_M << DMA_SPARE_SPARE12_SHIFT)
-#define DMA_SPARE_SPARE13_M 0x1ULL
-#define DMA_SPARE_SPARE13_SHIFT 13
-#define DMA_SPARE_SPARE13_MASK (DMA_SPARE_SPARE13_M << DMA_SPARE_SPARE13_SHIFT)
-#define DMA_SPARE_SPARE10_M 0x1ULL
-#define DMA_SPARE_SPARE10_SHIFT 10
-#define DMA_SPARE_SPARE10_MASK (DMA_SPARE_SPARE10_M << DMA_SPARE_SPARE10_SHIFT)
-#define DMA_SPARE_SPARE11_M 0x1ULL
-#define DMA_SPARE_SPARE11_SHIFT 11
-#define DMA_SPARE_SPARE11_MASK (DMA_SPARE_SPARE11_M << DMA_SPARE_SPARE11_SHIFT)
-#define DMA_SPARE_SPARE16_M 0x1ULL
-#define DMA_SPARE_SPARE16_SHIFT 16
-#define DMA_SPARE_SPARE16_MASK (DMA_SPARE_SPARE16_M << DMA_SPARE_SPARE16_SHIFT)
-#define DMA_SPARE_SPARE17_M 0x1ULL
-#define DMA_SPARE_SPARE17_SHIFT 17
-#define DMA_SPARE_SPARE17_MASK (DMA_SPARE_SPARE17_M << DMA_SPARE_SPARE17_SHIFT)
-#define DMA_SPARE_SPARE14_M 0x1ULL
-#define DMA_SPARE_SPARE14_SHIFT 14
-#define DMA_SPARE_SPARE14_MASK (DMA_SPARE_SPARE14_M << DMA_SPARE_SPARE14_SHIFT)
-#define DMA_SPARE_SPARE15_M 0x1ULL
-#define DMA_SPARE_SPARE15_SHIFT 15
-#define DMA_SPARE_SPARE15_MASK (DMA_SPARE_SPARE15_M << DMA_SPARE_SPARE15_SHIFT)
-
-/* Module : IPU_LIB_DREGFILE_LBP*/
-#define LBP_SEL 0x0
-#define LBP_SEL_DEF 0xf0f
-#define LBP_SEL_LBP_SEL_M 0xfULL
-#define LBP_SEL_LBP_SEL_SHIFT 0
-#define LBP_SEL_LBP_SEL_MASK (LBP_SEL_LBP_SEL_M << LBP_SEL_LBP_SEL_SHIFT)
-#define LBP_SEL_LB_SEL_M 0xfULL
-#define LBP_SEL_LB_SEL_SHIFT 8
-#define LBP_SEL_LB_SEL_MASK (LBP_SEL_LB_SEL_M << LBP_SEL_LB_SEL_SHIFT)
-#define LBP_CTRL 0x8
-#define LBP_CTRL_DEF 0x1
-#define LBP_CTRL_LB_RESET_M 0xffULL
-#define LBP_CTRL_LB_RESET_SHIFT 16
-#define LBP_CTRL_LB_RESET_MASK (LBP_CTRL_LB_RESET_M << LBP_CTRL_LB_RESET_SHIFT)
-#define LBP_CTRL_LB_ENA_M 0xffULL
-#define LBP_CTRL_LB_ENA_SHIFT 0
-#define LBP_CTRL_LB_ENA_MASK (LBP_CTRL_LB_ENA_M << LBP_CTRL_LB_ENA_SHIFT)
-#define LBP_CTRL_LB_INIT_M 0xffULL
-#define LBP_CTRL_LB_INIT_SHIFT 32
-#define LBP_CTRL_LB_INIT_MASK (LBP_CTRL_LB_INIT_M << LBP_CTRL_LB_INIT_SHIFT)
-#define LBP_CTRL_PMON_RD_SEL_M 0xffULL
-#define LBP_CTRL_PMON_RD_SEL_SHIFT 48
-#define LBP_CTRL_PMON_RD_SEL_MASK (LBP_CTRL_PMON_RD_SEL_M << LBP_CTRL_PMON_RD_SEL_SHIFT)
-#define LBP_CTRL_LBP_RESET_M 0x1ULL
-#define LBP_CTRL_LBP_RESET_SHIFT 8
-#define LBP_CTRL_LBP_RESET_MASK (LBP_CTRL_LBP_RESET_M << LBP_CTRL_LBP_RESET_SHIFT)
-#define LBP_STAT 0x10
-#define LBP_STAT_DEF 0x0
-#define LBP_STAT_CRB_READY_M 0x1ULL
-#define LBP_STAT_CRB_READY_SHIFT 0
-#define LBP_STAT_CRB_READY_MASK (LBP_STAT_CRB_READY_M << LBP_STAT_CRB_READY_SHIFT)
-#define LBP_STAT_WDC_READY_M 0x1ULL
-#define LBP_STAT_WDC_READY_SHIFT 1
-#define LBP_STAT_WDC_READY_MASK (LBP_STAT_WDC_READY_M << LBP_STAT_WDC_READY_SHIFT)
-#define LBP_STAT_RD_READY_M 0x1ULL
-#define LBP_STAT_RD_READY_SHIFT 2
-#define LBP_STAT_RD_READY_MASK (LBP_STAT_RD_READY_M << LBP_STAT_RD_READY_SHIFT)
-#define LBP_CAP0 0x18
-#define LBP_CAP0_DEF 0x8fff1008
-#define LBP_CAP0_MAX_CHAN_M 0x1ffULL
-#define LBP_CAP0_MAX_CHAN_SHIFT 4
-#define LBP_CAP0_MAX_CHAN_MASK (LBP_CAP0_MAX_CHAN_M << LBP_CAP0_MAX_CHAN_SHIFT)
-#define LBP_CAP0_MAX_RPTR_M 0xfULL
-#define LBP_CAP0_MAX_RPTR_SHIFT 28
-#define LBP_CAP0_MAX_RPTR_MASK (LBP_CAP0_MAX_RPTR_M << LBP_CAP0_MAX_RPTR_SHIFT)
-#define LBP_CAP0_MAX_FB_ROWS_M 0xfffULL
-#define LBP_CAP0_MAX_FB_ROWS_SHIFT 16
-#define LBP_CAP0_MAX_FB_ROWS_MASK (LBP_CAP0_MAX_FB_ROWS_M << LBP_CAP0_MAX_FB_ROWS_SHIFT)
-#define LBP_CAP0_MAX_LB_M 0xfULL
-#define LBP_CAP0_MAX_LB_SHIFT 0
-#define LBP_CAP0_MAX_LB_MASK (LBP_CAP0_MAX_LB_M << LBP_CAP0_MAX_LB_SHIFT)
-#define LBP_CAP1 0x20
-#define LBP_CAP1_DEF 0x40000
-#define LBP_CAP1_MEM_SIZE_M 0xffffffffULL
-#define LBP_CAP1_MEM_SIZE_SHIFT 0
-#define LBP_CAP1_MEM_SIZE_MASK (LBP_CAP1_MEM_SIZE_M << LBP_CAP1_MEM_SIZE_SHIFT)
-#define LBP_RAM_CTRL 0x28
-#define LBP_RAM_CTRL_DEF 0x0
-#define LBP_RAM_CTRL_RUN_M 0x1ULL
-#define LBP_RAM_CTRL_RUN_SHIFT 0
-#define LBP_RAM_CTRL_RUN_MASK (LBP_RAM_CTRL_RUN_M << LBP_RAM_CTRL_RUN_SHIFT)
-#define LBP_RAM_CTRL_WRITE_M 0x1ULL
-#define LBP_RAM_CTRL_WRITE_SHIFT 1
-#define LBP_RAM_CTRL_WRITE_MASK (LBP_RAM_CTRL_WRITE_M << LBP_RAM_CTRL_WRITE_SHIFT)
-#define LBP_RAM_CTRL_RAM_ADDR_M 0x1fffULL
-#define LBP_RAM_CTRL_RAM_ADDR_SHIFT 16
-#define LBP_RAM_CTRL_RAM_ADDR_MASK (LBP_RAM_CTRL_RAM_ADDR_M << LBP_RAM_CTRL_RAM_ADDR_SHIFT)
-#define LBP_RAM_DATA0 0x30
-#define LBP_RAM_DATA0_DEF 0x0
-#define LBP_RAM_DATA1 0x38
-#define LBP_RAM_DATA1_DEF 0x0
-#define LBP_RAM_DATA2 0x40
-#define LBP_RAM_DATA2_DEF 0x0
-#define LBP_RAM_DATA3 0x48
-#define LBP_RAM_DATA3_DEF 0x0
-#define LBP_PMON_CFG 0x50
-#define LBP_PMON_CFG_DEF 0x0
-#define LBP_PMON_CFG_ENABLE_M 0x1ULL
-#define LBP_PMON_CFG_ENABLE_SHIFT 0
-#define LBP_PMON_CFG_ENABLE_MASK (LBP_PMON_CFG_ENABLE_M << LBP_PMON_CFG_ENABLE_SHIFT)
-#define LBP_PMON_CNT_0_CFG 0x58
-#define LBP_PMON_CNT_0_CFG_DEF 0x0
-#define LBP_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
-#define LBP_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
-#define LBP_PMON_CNT_0_CFG_DEC_INV_MASK (LBP_PMON_CNT_0_CFG_DEC_INV_M << LBP_PMON_CNT_0_CFG_DEC_INV_SHIFT)
-#define LBP_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
-#define LBP_PMON_CNT_0_CFG_INC_INV_SHIFT 47
-#define LBP_PMON_CNT_0_CFG_INC_INV_MASK (LBP_PMON_CNT_0_CFG_INC_INV_M << LBP_PMON_CNT_0_CFG_INC_INV_SHIFT)
-#define LBP_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
-#define LBP_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
-#define LBP_PMON_CNT_0_CFG_INC_MATCH_MASK (LBP_PMON_CNT_0_CFG_INC_MATCH_M << LBP_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
-#define LBP_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
-#define LBP_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
-#define LBP_PMON_CNT_0_CFG_THRESHOLD_MASK (LBP_PMON_CNT_0_CFG_THRESHOLD_M << LBP_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
-#define LBP_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
-#define LBP_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
-#define LBP_PMON_CNT_0_CFG_DEC_MASK_MASK (LBP_PMON_CNT_0_CFG_DEC_MASK_M << LBP_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
-#define LBP_PMON_CNT_0_CFG_MODE_M 0x7ULL
-#define LBP_PMON_CNT_0_CFG_MODE_SHIFT 0
-#define LBP_PMON_CNT_0_CFG_MODE_MASK (LBP_PMON_CNT_0_CFG_MODE_M << LBP_PMON_CNT_0_CFG_MODE_SHIFT)
-#define LBP_PMON_CNT_0_CFG_INC_SEL_M 0x3fULL
-#define LBP_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
-#define LBP_PMON_CNT_0_CFG_INC_SEL_MASK (LBP_PMON_CNT_0_CFG_INC_SEL_M << LBP_PMON_CNT_0_CFG_INC_SEL_SHIFT)
-#define LBP_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
-#define LBP_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
-#define LBP_PMON_CNT_0_CFG_DEC_MATCH_MASK (LBP_PMON_CNT_0_CFG_DEC_MATCH_M << LBP_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
-#define LBP_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
-#define LBP_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
-#define LBP_PMON_CNT_0_CFG_INC_MASK_MASK (LBP_PMON_CNT_0_CFG_INC_MASK_M << LBP_PMON_CNT_0_CFG_INC_MASK_SHIFT)
-#define LBP_PMON_CNT_0_CFG_DEC_SEL_M 0x3fULL
-#define LBP_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
-#define LBP_PMON_CNT_0_CFG_DEC_SEL_MASK (LBP_PMON_CNT_0_CFG_DEC_SEL_M << LBP_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
-#define LBP_PMON_CNT_0 0x60
-#define LBP_PMON_CNT_0_DEF 0x0
-#define LBP_PMON_CNT_0_CNT_M 0xffffffffffULL
-#define LBP_PMON_CNT_0_CNT_SHIFT 0
-#define LBP_PMON_CNT_0_CNT_MASK (LBP_PMON_CNT_0_CNT_M << LBP_PMON_CNT_0_CNT_SHIFT)
-#define LBP_PMON_CNT_0_STS_ACC 0x68
-#define LBP_PMON_CNT_0_STS_ACC_DEF 0x0
-#define LBP_PMON_CNT_0_STS 0x70
-#define LBP_PMON_CNT_0_STS_DEF 0x0
-#define LBP_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
-#define LBP_PMON_CNT_0_STS_ACC_OF_SHIFT 0
-#define LBP_PMON_CNT_0_STS_ACC_OF_MASK (LBP_PMON_CNT_0_STS_ACC_OF_M << LBP_PMON_CNT_0_STS_ACC_OF_SHIFT)
-#define LBP_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
-#define LBP_PMON_CNT_0_STS_CNT_OF_SHIFT 2
-#define LBP_PMON_CNT_0_STS_CNT_OF_MASK (LBP_PMON_CNT_0_STS_CNT_OF_M << LBP_PMON_CNT_0_STS_CNT_OF_SHIFT)
-#define LBP_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
-#define LBP_PMON_CNT_0_STS_ACC_UF_SHIFT 1
-#define LBP_PMON_CNT_0_STS_ACC_UF_MASK (LBP_PMON_CNT_0_STS_ACC_UF_M << LBP_PMON_CNT_0_STS_ACC_UF_SHIFT)
-#define LBP_PMON_CNT_1_CFG 0x78
-#define LBP_PMON_CNT_1_CFG_DEF 0x0
-#define LBP_PMON_CNT_1_CFG_INC_SEL_M 0x3fULL
-#define LBP_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
-#define LBP_PMON_CNT_1_CFG_INC_SEL_MASK (LBP_PMON_CNT_1_CFG_INC_SEL_M << LBP_PMON_CNT_1_CFG_INC_SEL_SHIFT)
-#define LBP_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
-#define LBP_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
-#define LBP_PMON_CNT_1_CFG_DEC_MATCH_MASK (LBP_PMON_CNT_1_CFG_DEC_MATCH_M << LBP_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
-#define LBP_PMON_CNT_1_CFG_DEC_SEL_M 0x3fULL
-#define LBP_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
-#define LBP_PMON_CNT_1_CFG_DEC_SEL_MASK (LBP_PMON_CNT_1_CFG_DEC_SEL_M << LBP_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
-#define LBP_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
-#define LBP_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
-#define LBP_PMON_CNT_1_CFG_INC_MATCH_MASK (LBP_PMON_CNT_1_CFG_INC_MATCH_M << LBP_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
-#define LBP_PMON_CNT_1_CFG_MODE_M 0x7ULL
-#define LBP_PMON_CNT_1_CFG_MODE_SHIFT 0
-#define LBP_PMON_CNT_1_CFG_MODE_MASK (LBP_PMON_CNT_1_CFG_MODE_M << LBP_PMON_CNT_1_CFG_MODE_SHIFT)
-#define LBP_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
-#define LBP_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
-#define LBP_PMON_CNT_1_CFG_DEC_MASK_MASK (LBP_PMON_CNT_1_CFG_DEC_MASK_M << LBP_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
-#define LBP_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
-#define LBP_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
-#define LBP_PMON_CNT_1_CFG_DEC_INV_MASK (LBP_PMON_CNT_1_CFG_DEC_INV_M << LBP_PMON_CNT_1_CFG_DEC_INV_SHIFT)
-#define LBP_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
-#define LBP_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
-#define LBP_PMON_CNT_1_CFG_INC_MASK_MASK (LBP_PMON_CNT_1_CFG_INC_MASK_M << LBP_PMON_CNT_1_CFG_INC_MASK_SHIFT)
-#define LBP_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
-#define LBP_PMON_CNT_1_CFG_INC_INV_SHIFT 47
-#define LBP_PMON_CNT_1_CFG_INC_INV_MASK (LBP_PMON_CNT_1_CFG_INC_INV_M << LBP_PMON_CNT_1_CFG_INC_INV_SHIFT)
-#define LBP_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
-#define LBP_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
-#define LBP_PMON_CNT_1_CFG_THRESHOLD_MASK (LBP_PMON_CNT_1_CFG_THRESHOLD_M << LBP_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
-#define LBP_PMON_CNT_1 0x80
-#define LBP_PMON_CNT_1_DEF 0x0
-#define LBP_PMON_CNT_1_CNT_M 0xffffffffffULL
-#define LBP_PMON_CNT_1_CNT_SHIFT 0
-#define LBP_PMON_CNT_1_CNT_MASK (LBP_PMON_CNT_1_CNT_M << LBP_PMON_CNT_1_CNT_SHIFT)
-#define LBP_PMON_CNT_1_STS_ACC 0x88
-#define LBP_PMON_CNT_1_STS_ACC_DEF 0x0
-#define LBP_PMON_CNT_1_STS 0x90
-#define LBP_PMON_CNT_1_STS_DEF 0x0
-#define LBP_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
-#define LBP_PMON_CNT_1_STS_ACC_UF_SHIFT 1
-#define LBP_PMON_CNT_1_STS_ACC_UF_MASK (LBP_PMON_CNT_1_STS_ACC_UF_M << LBP_PMON_CNT_1_STS_ACC_UF_SHIFT)
-#define LBP_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
-#define LBP_PMON_CNT_1_STS_ACC_OF_SHIFT 0
-#define LBP_PMON_CNT_1_STS_ACC_OF_MASK (LBP_PMON_CNT_1_STS_ACC_OF_M << LBP_PMON_CNT_1_STS_ACC_OF_SHIFT)
-#define LBP_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
-#define LBP_PMON_CNT_1_STS_CNT_OF_SHIFT 2
-#define LBP_PMON_CNT_1_STS_CNT_OF_MASK (LBP_PMON_CNT_1_STS_CNT_OF_M << LBP_PMON_CNT_1_STS_CNT_OF_SHIFT)
-#define LB_CTRL0 0xc0
-#define LB_CTRL0_DEF 0x280021
-#define LB_CTRL0_FB_ROWS_M 0xfffULL
-#define LB_CTRL0_FB_ROWS_SHIFT 16
-#define LB_CTRL0_FB_ROWS_MASK (LB_CTRL0_FB_ROWS_M << LB_CTRL0_FB_ROWS_SHIFT)
-#define LB_CTRL0_REUSE_ROWS_M 0x1fULL
-#define LB_CTRL0_REUSE_ROWS_SHIFT 32
-#define LB_CTRL0_REUSE_ROWS_MASK (LB_CTRL0_REUSE_ROWS_M << LB_CTRL0_REUSE_ROWS_SHIFT)
-#define LB_CTRL0_NUM_RPTR_M 0xfULL
-#define LB_CTRL0_NUM_RPTR_SHIFT 0
-#define LB_CTRL0_NUM_RPTR_MASK (LB_CTRL0_NUM_RPTR_M << LB_CTRL0_NUM_RPTR_SHIFT)
-#define LB_CTRL0_NUM_CHAN_M 0x1ffULL
-#define LB_CTRL0_NUM_CHAN_SHIFT 4
-#define LB_CTRL0_NUM_CHAN_MASK (LB_CTRL0_NUM_CHAN_M << LB_CTRL0_NUM_CHAN_SHIFT)
-#define LB_OFFSET 0xc8
-#define LB_OFFSET_DEF 0x0
-#define LB_OFFSET_OFFSET_Y_M 0xffffULL
-#define LB_OFFSET_OFFSET_Y_SHIFT 16
-#define LB_OFFSET_OFFSET_Y_MASK (LB_OFFSET_OFFSET_Y_M << LB_OFFSET_OFFSET_Y_SHIFT)
-#define LB_OFFSET_OFFSET_X_M 0xffffULL
-#define LB_OFFSET_OFFSET_X_SHIFT 0
-#define LB_OFFSET_OFFSET_X_MASK (LB_OFFSET_OFFSET_X_M << LB_OFFSET_OFFSET_X_SHIFT)
-#define LB_OFFSET_FB_OFFSET_M 0xffULL
-#define LB_OFFSET_FB_OFFSET_SHIFT 48
-#define LB_OFFSET_FB_OFFSET_MASK (LB_OFFSET_FB_OFFSET_M << LB_OFFSET_FB_OFFSET_SHIFT)
-#define LB_OFFSET_OFFSET_CHAN_M 0x1ffULL
-#define LB_OFFSET_OFFSET_CHAN_SHIFT 32
-#define LB_OFFSET_OFFSET_CHAN_MASK (LB_OFFSET_OFFSET_CHAN_M << LB_OFFSET_OFFSET_CHAN_SHIFT)
-#define LB_BDRY 0xd0
-#define LB_BDRY_DEF 0x0
-#define LB_BDRY_BDRY_M 0x3ULL
-#define LB_BDRY_BDRY_SHIFT 0
-#define LB_BDRY_BDRY_MASK (LB_BDRY_BDRY_M << LB_BDRY_BDRY_SHIFT)
-#define LB_BDRY_BDRY_VAL_M 0xffffULL
-#define LB_BDRY_BDRY_VAL_SHIFT 16
-#define LB_BDRY_BDRY_VAL_MASK (LB_BDRY_BDRY_VAL_M << LB_BDRY_BDRY_VAL_SHIFT)
-#define LB_IMG_SIZE 0xd8
-#define LB_IMG_SIZE_DEF 0x1e00280
-#define LB_IMG_SIZE_IMG_HEIGHT_M 0xffffULL
-#define LB_IMG_SIZE_IMG_HEIGHT_SHIFT 16
-#define LB_IMG_SIZE_IMG_HEIGHT_MASK (LB_IMG_SIZE_IMG_HEIGHT_M << LB_IMG_SIZE_IMG_HEIGHT_SHIFT)
-#define LB_IMG_SIZE_IMG_WIDTH_M 0xffffULL
-#define LB_IMG_SIZE_IMG_WIDTH_SHIFT 0
-#define LB_IMG_SIZE_IMG_WIDTH_MASK (LB_IMG_SIZE_IMG_WIDTH_M << LB_IMG_SIZE_IMG_WIDTH_SHIFT)
-#define LB_SB_SIZE 0xe0
-#define LB_SB_SIZE_DEF 0x0
-#define LB_SB_SIZE_SB_ROWS_M 0xfffULL
-#define LB_SB_SIZE_SB_ROWS_SHIFT 16
-#define LB_SB_SIZE_SB_ROWS_MASK (LB_SB_SIZE_SB_ROWS_M << LB_SB_SIZE_SB_ROWS_SHIFT)
-#define LB_SB_SIZE_SB_COLS_M 0xffffULL
-#define LB_SB_SIZE_SB_COLS_SHIFT 0
-#define LB_SB_SIZE_SB_COLS_MASK (LB_SB_SIZE_SB_COLS_M << LB_SB_SIZE_SB_COLS_SHIFT)
-#define LB_BASE 0xe8
-#define LB_BASE_DEF 0x0
-#define LB_BASE_FB_BASE_ADDR_M 0x1fffULL
-#define LB_BASE_FB_BASE_ADDR_SHIFT 0
-#define LB_BASE_FB_BASE_ADDR_MASK (LB_BASE_FB_BASE_ADDR_M << LB_BASE_FB_BASE_ADDR_SHIFT)
-#define LB_BASE_SB_BASE_ADDR_M 0x1fffULL
-#define LB_BASE_SB_BASE_ADDR_SHIFT 16
-#define LB_BASE_SB_BASE_ADDR_MASK (LB_BASE_SB_BASE_ADDR_M << LB_BASE_SB_BASE_ADDR_SHIFT)
-#define LB_STAT 0xf0
-#define LB_STAT_DEF 0x0
-#define LB_STAT_EMPTY_M 0xffULL
-#define LB_STAT_EMPTY_SHIFT 1
-#define LB_STAT_EMPTY_MASK (LB_STAT_EMPTY_M << LB_STAT_EMPTY_SHIFT)
-#define LB_STAT_FULL_M 0x1ULL
-#define LB_STAT_FULL_SHIFT 0
-#define LB_STAT_FULL_MASK (LB_STAT_FULL_M << LB_STAT_FULL_SHIFT)
-#define LB_L_PARAM 0xf8
-#define LB_L_PARAM_DEF 0x0
-#define LB_L_PARAM_L_INC_M 0x3fffULL
-#define LB_L_PARAM_L_INC_SHIFT 0
-#define LB_L_PARAM_L_INC_MASK (LB_L_PARAM_L_INC_M << LB_L_PARAM_L_INC_SHIFT)
-#define LB_L_PARAM_L_WIDTH_M 0x3fffULL
-#define LB_L_PARAM_L_WIDTH_SHIFT 16
-#define LB_L_PARAM_L_WIDTH_MASK (LB_L_PARAM_L_WIDTH_M << LB_L_PARAM_L_WIDTH_SHIFT)
-#define LB_SB_DELTA 0x100
-#define LB_SB_DELTA_DEF 0x0
-#define LB_SB_DELTA_SB_DELTA_M 0x3fffULL
-#define LB_SB_DELTA_SB_DELTA_SHIFT 0
-#define LB_SB_DELTA_SB_DELTA_MASK (LB_SB_DELTA_SB_DELTA_M << LB_SB_DELTA_SB_DELTA_SHIFT)
-#define LBP_SPARE 0x108
-#define LBP_SPARE_DEF 0x0
-#define LBP_SPARE_SPARE16_M 0x1ULL
-#define LBP_SPARE_SPARE16_SHIFT 16
-#define LBP_SPARE_SPARE16_MASK (LBP_SPARE_SPARE16_M << LBP_SPARE_SPARE16_SHIFT)
-#define LBP_SPARE_SPARE17_M 0x1ULL
-#define LBP_SPARE_SPARE17_SHIFT 17
-#define LBP_SPARE_SPARE17_MASK (LBP_SPARE_SPARE17_M << LBP_SPARE_SPARE17_SHIFT)
-#define LBP_SPARE_SPARE14_M 0x1ULL
-#define LBP_SPARE_SPARE14_SHIFT 14
-#define LBP_SPARE_SPARE14_MASK (LBP_SPARE_SPARE14_M << LBP_SPARE_SPARE14_SHIFT)
-#define LBP_SPARE_SPARE15_M 0x1ULL
-#define LBP_SPARE_SPARE15_SHIFT 15
-#define LBP_SPARE_SPARE15_MASK (LBP_SPARE_SPARE15_M << LBP_SPARE_SPARE15_SHIFT)
-#define LBP_SPARE_SPARE12_M 0x1ULL
-#define LBP_SPARE_SPARE12_SHIFT 12
-#define LBP_SPARE_SPARE12_MASK (LBP_SPARE_SPARE12_M << LBP_SPARE_SPARE12_SHIFT)
-#define LBP_SPARE_SPARE13_M 0x1ULL
-#define LBP_SPARE_SPARE13_SHIFT 13
-#define LBP_SPARE_SPARE13_MASK (LBP_SPARE_SPARE13_M << LBP_SPARE_SPARE13_SHIFT)
-#define LBP_SPARE_SPARE10_M 0x1ULL
-#define LBP_SPARE_SPARE10_SHIFT 10
-#define LBP_SPARE_SPARE10_MASK (LBP_SPARE_SPARE10_M << LBP_SPARE_SPARE10_SHIFT)
-#define LBP_SPARE_SPARE11_M 0x1ULL
-#define LBP_SPARE_SPARE11_SHIFT 11
-#define LBP_SPARE_SPARE11_MASK (LBP_SPARE_SPARE11_M << LBP_SPARE_SPARE11_SHIFT)
-#define LBP_SPARE_SPARE18_M 0x1ULL
-#define LBP_SPARE_SPARE18_SHIFT 18
-#define LBP_SPARE_SPARE18_MASK (LBP_SPARE_SPARE18_M << LBP_SPARE_SPARE18_SHIFT)
-#define LBP_SPARE_SPARE19_M 0x1ULL
-#define LBP_SPARE_SPARE19_SHIFT 19
-#define LBP_SPARE_SPARE19_MASK (LBP_SPARE_SPARE19_M << LBP_SPARE_SPARE19_SHIFT)
-#define LBP_SPARE_SPARE4_M 0x1ULL
-#define LBP_SPARE_SPARE4_SHIFT 4
-#define LBP_SPARE_SPARE4_MASK (LBP_SPARE_SPARE4_M << LBP_SPARE_SPARE4_SHIFT)
-#define LBP_SPARE_SPARE5_M 0x1ULL
-#define LBP_SPARE_SPARE5_SHIFT 5
-#define LBP_SPARE_SPARE5_MASK (LBP_SPARE_SPARE5_M << LBP_SPARE_SPARE5_SHIFT)
-#define LBP_SPARE_SPARE6_M 0x1ULL
-#define LBP_SPARE_SPARE6_SHIFT 6
-#define LBP_SPARE_SPARE6_MASK (LBP_SPARE_SPARE6_M << LBP_SPARE_SPARE6_SHIFT)
-#define LBP_SPARE_SPARE7_M 0x1ULL
-#define LBP_SPARE_SPARE7_SHIFT 7
-#define LBP_SPARE_SPARE7_MASK (LBP_SPARE_SPARE7_M << LBP_SPARE_SPARE7_SHIFT)
-#define LBP_SPARE_SPARE0_M 0x1ULL
-#define LBP_SPARE_SPARE0_SHIFT 0
-#define LBP_SPARE_SPARE0_MASK (LBP_SPARE_SPARE0_M << LBP_SPARE_SPARE0_SHIFT)
-#define LBP_SPARE_SPARE1_M 0x1ULL
-#define LBP_SPARE_SPARE1_SHIFT 1
-#define LBP_SPARE_SPARE1_MASK (LBP_SPARE_SPARE1_M << LBP_SPARE_SPARE1_SHIFT)
-#define LBP_SPARE_SPARE2_M 0x1ULL
-#define LBP_SPARE_SPARE2_SHIFT 2
-#define LBP_SPARE_SPARE2_MASK (LBP_SPARE_SPARE2_M << LBP_SPARE_SPARE2_SHIFT)
-#define LBP_SPARE_SPARE3_M 0x1ULL
-#define LBP_SPARE_SPARE3_SHIFT 3
-#define LBP_SPARE_SPARE3_MASK (LBP_SPARE_SPARE3_M << LBP_SPARE_SPARE3_SHIFT)
-#define LBP_SPARE_SPARE8_M 0x1ULL
-#define LBP_SPARE_SPARE8_SHIFT 8
-#define LBP_SPARE_SPARE8_MASK (LBP_SPARE_SPARE8_M << LBP_SPARE_SPARE8_SHIFT)
-#define LBP_SPARE_SPARE9_M 0x1ULL
-#define LBP_SPARE_SPARE9_SHIFT 9
-#define LBP_SPARE_SPARE9_MASK (LBP_SPARE_SPARE9_M << LBP_SPARE_SPARE9_SHIFT)
-#define LBP_SPARE_SPARE30_M 0x1ULL
-#define LBP_SPARE_SPARE30_SHIFT 30
-#define LBP_SPARE_SPARE30_MASK (LBP_SPARE_SPARE30_M << LBP_SPARE_SPARE30_SHIFT)
-#define LBP_SPARE_SPARE29_M 0x1ULL
-#define LBP_SPARE_SPARE29_SHIFT 29
-#define LBP_SPARE_SPARE29_MASK (LBP_SPARE_SPARE29_M << LBP_SPARE_SPARE29_SHIFT)
-#define LBP_SPARE_SPARE28_M 0x1ULL
-#define LBP_SPARE_SPARE28_SHIFT 28
-#define LBP_SPARE_SPARE28_MASK (LBP_SPARE_SPARE28_M << LBP_SPARE_SPARE28_SHIFT)
-#define LBP_SPARE_SPARE27_M 0x1ULL
-#define LBP_SPARE_SPARE27_SHIFT 27
-#define LBP_SPARE_SPARE27_MASK (LBP_SPARE_SPARE27_M << LBP_SPARE_SPARE27_SHIFT)
-#define LBP_SPARE_SPARE26_M 0x1ULL
-#define LBP_SPARE_SPARE26_SHIFT 26
-#define LBP_SPARE_SPARE26_MASK (LBP_SPARE_SPARE26_M << LBP_SPARE_SPARE26_SHIFT)
-#define LBP_SPARE_SPARE25_M 0x1ULL
-#define LBP_SPARE_SPARE25_SHIFT 25
-#define LBP_SPARE_SPARE25_MASK (LBP_SPARE_SPARE25_M << LBP_SPARE_SPARE25_SHIFT)
-#define LBP_SPARE_SPARE24_M 0x1ULL
-#define LBP_SPARE_SPARE24_SHIFT 24
-#define LBP_SPARE_SPARE24_MASK (LBP_SPARE_SPARE24_M << LBP_SPARE_SPARE24_SHIFT)
-#define LBP_SPARE_SPARE23_M 0x1ULL
-#define LBP_SPARE_SPARE23_SHIFT 23
-#define LBP_SPARE_SPARE23_MASK (LBP_SPARE_SPARE23_M << LBP_SPARE_SPARE23_SHIFT)
-#define LBP_SPARE_SPARE22_M 0x1ULL
-#define LBP_SPARE_SPARE22_SHIFT 22
-#define LBP_SPARE_SPARE22_MASK (LBP_SPARE_SPARE22_M << LBP_SPARE_SPARE22_SHIFT)
-#define LBP_SPARE_SPARE21_M 0x1ULL
-#define LBP_SPARE_SPARE21_SHIFT 21
-#define LBP_SPARE_SPARE21_MASK (LBP_SPARE_SPARE21_M << LBP_SPARE_SPARE21_SHIFT)
-#define LBP_SPARE_SPARE20_M 0x1ULL
-#define LBP_SPARE_SPARE20_SHIFT 20
-#define LBP_SPARE_SPARE20_MASK (LBP_SPARE_SPARE20_M << LBP_SPARE_SPARE20_SHIFT)
-#define LBP_SPARE_SPARE31_M 0x1ULL
-#define LBP_SPARE_SPARE31_SHIFT 31
-#define LBP_SPARE_SPARE31_MASK (LBP_SPARE_SPARE31_M << LBP_SPARE_SPARE31_SHIFT)
-
-/* Module : IPU_LIB_DREGFILE_MIF*/
-#define MPI_CAP 0x0
-#define MPI_CAP_DEF 0xc3
-#define MPI_CAP_MAX_STRM_M 0xfULL
-#define MPI_CAP_MAX_STRM_SHIFT 4
-#define MPI_CAP_MAX_STRM_MASK (MPI_CAP_MAX_STRM_M << MPI_CAP_MAX_STRM_SHIFT)
-#define MPI_CAP_MAX_IFC_M 0x3ULL
-#define MPI_CAP_MAX_IFC_SHIFT 0
-#define MPI_CAP_MAX_IFC_MASK (MPI_CAP_MAX_IFC_M << MPI_CAP_MAX_IFC_SHIFT)
-#define MPI_CTRL 0x8
-#define MPI_CTRL_DEF 0x0
-#define MPI_CTRL_STRM_CONTINUOUS_CLR4_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR4_SHIFT 40
-#define MPI_CTRL_STRM_CONTINUOUS_CLR4_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR4_M << MPI_CTRL_STRM_CONTINUOUS_CLR4_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET9_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET9_SHIFT 9
-#define MPI_CTRL_STRM_ENA_SET9_MASK (MPI_CTRL_STRM_ENA_SET9_M << MPI_CTRL_STRM_ENA_SET9_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET8_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET8_SHIFT 8
-#define MPI_CTRL_STRM_ENA_SET8_MASK (MPI_CTRL_STRM_ENA_SET8_M << MPI_CTRL_STRM_ENA_SET8_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET3_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET3_SHIFT 3
-#define MPI_CTRL_STRM_ENA_SET3_MASK (MPI_CTRL_STRM_ENA_SET3_M << MPI_CTRL_STRM_ENA_SET3_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET2_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET2_SHIFT 2
-#define MPI_CTRL_STRM_ENA_SET2_MASK (MPI_CTRL_STRM_ENA_SET2_M << MPI_CTRL_STRM_ENA_SET2_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET1_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET1_SHIFT 1
-#define MPI_CTRL_STRM_ENA_SET1_MASK (MPI_CTRL_STRM_ENA_SET1_M << MPI_CTRL_STRM_ENA_SET1_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET0_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET0_SHIFT 0
-#define MPI_CTRL_STRM_ENA_SET0_MASK (MPI_CTRL_STRM_ENA_SET0_M << MPI_CTRL_STRM_ENA_SET0_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET7_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET7_SHIFT 7
-#define MPI_CTRL_STRM_ENA_SET7_MASK (MPI_CTRL_STRM_ENA_SET7_M << MPI_CTRL_STRM_ENA_SET7_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET6_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET6_SHIFT 6
-#define MPI_CTRL_STRM_ENA_SET6_MASK (MPI_CTRL_STRM_ENA_SET6_M << MPI_CTRL_STRM_ENA_SET6_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET5_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET5_SHIFT 5
-#define MPI_CTRL_STRM_ENA_SET5_MASK (MPI_CTRL_STRM_ENA_SET5_M << MPI_CTRL_STRM_ENA_SET5_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET4_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET4_SHIFT 4
-#define MPI_CTRL_STRM_ENA_SET4_MASK (MPI_CTRL_STRM_ENA_SET4_M << MPI_CTRL_STRM_ENA_SET4_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS6_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS6_SHIFT 54
-#define MPI_CTRL_STRM_CONTINUOUS6_MASK (MPI_CTRL_STRM_CONTINUOUS6_M << MPI_CTRL_STRM_CONTINUOUS6_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS7_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS7_SHIFT 55
-#define MPI_CTRL_STRM_CONTINUOUS7_MASK (MPI_CTRL_STRM_CONTINUOUS7_M << MPI_CTRL_STRM_CONTINUOUS7_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS4_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS4_SHIFT 52
-#define MPI_CTRL_STRM_CONTINUOUS4_MASK (MPI_CTRL_STRM_CONTINUOUS4_M << MPI_CTRL_STRM_CONTINUOUS4_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS5_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS5_SHIFT 53
-#define MPI_CTRL_STRM_CONTINUOUS5_MASK (MPI_CTRL_STRM_CONTINUOUS5_M << MPI_CTRL_STRM_CONTINUOUS5_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET11_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET11_SHIFT 35
-#define MPI_CTRL_STRM_CONTINUOUS_SET11_MASK (MPI_CTRL_STRM_CONTINUOUS_SET11_M << MPI_CTRL_STRM_CONTINUOUS_SET11_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET10_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET10_SHIFT 34
-#define MPI_CTRL_STRM_CONTINUOUS_SET10_MASK (MPI_CTRL_STRM_CONTINUOUS_SET10_M << MPI_CTRL_STRM_CONTINUOUS_SET10_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS0_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS0_SHIFT 48
-#define MPI_CTRL_STRM_CONTINUOUS0_MASK (MPI_CTRL_STRM_CONTINUOUS0_M << MPI_CTRL_STRM_CONTINUOUS0_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS1_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS1_SHIFT 49
-#define MPI_CTRL_STRM_CONTINUOUS1_MASK (MPI_CTRL_STRM_CONTINUOUS1_M << MPI_CTRL_STRM_CONTINUOUS1_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR10_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR10_SHIFT 46
-#define MPI_CTRL_STRM_CONTINUOUS_CLR10_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR10_M << MPI_CTRL_STRM_CONTINUOUS_CLR10_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR11_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR11_SHIFT 47
-#define MPI_CTRL_STRM_CONTINUOUS_CLR11_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR11_M << MPI_CTRL_STRM_CONTINUOUS_CLR11_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS8_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS8_SHIFT 56
-#define MPI_CTRL_STRM_CONTINUOUS8_MASK (MPI_CTRL_STRM_CONTINUOUS8_M << MPI_CTRL_STRM_CONTINUOUS8_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS9_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS9_SHIFT 57
-#define MPI_CTRL_STRM_CONTINUOUS9_MASK (MPI_CTRL_STRM_CONTINUOUS9_M << MPI_CTRL_STRM_CONTINUOUS9_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR8_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR8_SHIFT 44
-#define MPI_CTRL_STRM_CONTINUOUS_CLR8_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR8_M << MPI_CTRL_STRM_CONTINUOUS_CLR8_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR9_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR9_SHIFT 45
-#define MPI_CTRL_STRM_CONTINUOUS_CLR9_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR9_M << MPI_CTRL_STRM_CONTINUOUS_CLR9_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS10_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS10_SHIFT 58
-#define MPI_CTRL_STRM_CONTINUOUS10_MASK (MPI_CTRL_STRM_CONTINUOUS10_M << MPI_CTRL_STRM_CONTINUOUS10_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS11_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS11_SHIFT 59
-#define MPI_CTRL_STRM_CONTINUOUS11_MASK (MPI_CTRL_STRM_CONTINUOUS11_M << MPI_CTRL_STRM_CONTINUOUS11_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR2_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR2_SHIFT 38
-#define MPI_CTRL_STRM_CONTINUOUS_CLR2_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR2_M << MPI_CTRL_STRM_CONTINUOUS_CLR2_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR3_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR3_SHIFT 39
-#define MPI_CTRL_STRM_CONTINUOUS_CLR3_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR3_M << MPI_CTRL_STRM_CONTINUOUS_CLR3_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR0_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR0_SHIFT 36
-#define MPI_CTRL_STRM_CONTINUOUS_CLR0_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR0_M << MPI_CTRL_STRM_CONTINUOUS_CLR0_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR1_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR1_SHIFT 37
-#define MPI_CTRL_STRM_CONTINUOUS_CLR1_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR1_M << MPI_CTRL_STRM_CONTINUOUS_CLR1_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR6_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR6_SHIFT 42
-#define MPI_CTRL_STRM_CONTINUOUS_CLR6_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR6_M << MPI_CTRL_STRM_CONTINUOUS_CLR6_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR7_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR7_SHIFT 43
-#define MPI_CTRL_STRM_CONTINUOUS_CLR7_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR7_M << MPI_CTRL_STRM_CONTINUOUS_CLR7_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET11_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET11_SHIFT 11
-#define MPI_CTRL_STRM_ENA_SET11_MASK (MPI_CTRL_STRM_ENA_SET11_M << MPI_CTRL_STRM_ENA_SET11_SHIFT)
-#define MPI_CTRL_STRM_ENA_SET10_M 0x1ULL
-#define MPI_CTRL_STRM_ENA_SET10_SHIFT 10
-#define MPI_CTRL_STRM_ENA_SET10_MASK (MPI_CTRL_STRM_ENA_SET10_M << MPI_CTRL_STRM_ENA_SET10_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET1_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET1_SHIFT 25
-#define MPI_CTRL_STRM_CONTINUOUS_SET1_MASK (MPI_CTRL_STRM_CONTINUOUS_SET1_M << MPI_CTRL_STRM_CONTINUOUS_SET1_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET0_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET0_SHIFT 24
-#define MPI_CTRL_STRM_CONTINUOUS_SET0_MASK (MPI_CTRL_STRM_CONTINUOUS_SET0_M << MPI_CTRL_STRM_CONTINUOUS_SET0_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET3_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET3_SHIFT 27
-#define MPI_CTRL_STRM_CONTINUOUS_SET3_MASK (MPI_CTRL_STRM_CONTINUOUS_SET3_M << MPI_CTRL_STRM_CONTINUOUS_SET3_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET2_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET2_SHIFT 26
-#define MPI_CTRL_STRM_CONTINUOUS_SET2_MASK (MPI_CTRL_STRM_CONTINUOUS_SET2_M << MPI_CTRL_STRM_CONTINUOUS_SET2_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET5_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET5_SHIFT 29
-#define MPI_CTRL_STRM_CONTINUOUS_SET5_MASK (MPI_CTRL_STRM_CONTINUOUS_SET5_M << MPI_CTRL_STRM_CONTINUOUS_SET5_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET4_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET4_SHIFT 28
-#define MPI_CTRL_STRM_CONTINUOUS_SET4_MASK (MPI_CTRL_STRM_CONTINUOUS_SET4_M << MPI_CTRL_STRM_CONTINUOUS_SET4_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET7_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET7_SHIFT 31
-#define MPI_CTRL_STRM_CONTINUOUS_SET7_MASK (MPI_CTRL_STRM_CONTINUOUS_SET7_M << MPI_CTRL_STRM_CONTINUOUS_SET7_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET6_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET6_SHIFT 30
-#define MPI_CTRL_STRM_CONTINUOUS_SET6_MASK (MPI_CTRL_STRM_CONTINUOUS_SET6_M << MPI_CTRL_STRM_CONTINUOUS_SET6_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET9_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET9_SHIFT 33
-#define MPI_CTRL_STRM_CONTINUOUS_SET9_MASK (MPI_CTRL_STRM_CONTINUOUS_SET9_M << MPI_CTRL_STRM_CONTINUOUS_SET9_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_SET8_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_SET8_SHIFT 32
-#define MPI_CTRL_STRM_CONTINUOUS_SET8_MASK (MPI_CTRL_STRM_CONTINUOUS_SET8_M << MPI_CTRL_STRM_CONTINUOUS_SET8_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS_CLR5_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS_CLR5_SHIFT 41
-#define MPI_CTRL_STRM_CONTINUOUS_CLR5_MASK (MPI_CTRL_STRM_CONTINUOUS_CLR5_M << MPI_CTRL_STRM_CONTINUOUS_CLR5_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS3_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS3_SHIFT 51
-#define MPI_CTRL_STRM_CONTINUOUS3_MASK (MPI_CTRL_STRM_CONTINUOUS3_M << MPI_CTRL_STRM_CONTINUOUS3_SHIFT)
-#define MPI_CTRL_STRM_ENA8_M 0x1ULL
-#define MPI_CTRL_STRM_ENA8_SHIFT 20
-#define MPI_CTRL_STRM_ENA8_MASK (MPI_CTRL_STRM_ENA8_M << MPI_CTRL_STRM_ENA8_SHIFT)
-#define MPI_CTRL_STRM_ENA9_M 0x1ULL
-#define MPI_CTRL_STRM_ENA9_SHIFT 21
-#define MPI_CTRL_STRM_ENA9_MASK (MPI_CTRL_STRM_ENA9_M << MPI_CTRL_STRM_ENA9_SHIFT)
-#define MPI_CTRL_STRM_CONTINUOUS2_M 0x1ULL
-#define MPI_CTRL_STRM_CONTINUOUS2_SHIFT 50
-#define MPI_CTRL_STRM_CONTINUOUS2_MASK (MPI_CTRL_STRM_CONTINUOUS2_M << MPI_CTRL_STRM_CONTINUOUS2_SHIFT)
-#define MPI_CTRL_STRM_ENA0_M 0x1ULL
-#define MPI_CTRL_STRM_ENA0_SHIFT 12
-#define MPI_CTRL_STRM_ENA0_MASK (MPI_CTRL_STRM_ENA0_M << MPI_CTRL_STRM_ENA0_SHIFT)
-#define MPI_CTRL_STRM_ENA1_M 0x1ULL
-#define MPI_CTRL_STRM_ENA1_SHIFT 13
-#define MPI_CTRL_STRM_ENA1_MASK (MPI_CTRL_STRM_ENA1_M << MPI_CTRL_STRM_ENA1_SHIFT)
-#define MPI_CTRL_STRM_ENA2_M 0x1ULL
-#define MPI_CTRL_STRM_ENA2_SHIFT 14
-#define MPI_CTRL_STRM_ENA2_MASK (MPI_CTRL_STRM_ENA2_M << MPI_CTRL_STRM_ENA2_SHIFT)
-#define MPI_CTRL_STRM_ENA3_M 0x1ULL
-#define MPI_CTRL_STRM_ENA3_SHIFT 15
-#define MPI_CTRL_STRM_ENA3_MASK (MPI_CTRL_STRM_ENA3_M << MPI_CTRL_STRM_ENA3_SHIFT)
-#define MPI_CTRL_STRM_ENA4_M 0x1ULL
-#define MPI_CTRL_STRM_ENA4_SHIFT 16
-#define MPI_CTRL_STRM_ENA4_MASK (MPI_CTRL_STRM_ENA4_M << MPI_CTRL_STRM_ENA4_SHIFT)
-#define MPI_CTRL_STRM_ENA5_M 0x1ULL
-#define MPI_CTRL_STRM_ENA5_SHIFT 17
-#define MPI_CTRL_STRM_ENA5_MASK (MPI_CTRL_STRM_ENA5_M << MPI_CTRL_STRM_ENA5_SHIFT)
-#define MPI_CTRL_STRM_ENA6_M 0x1ULL
-#define MPI_CTRL_STRM_ENA6_SHIFT 18
-#define MPI_CTRL_STRM_ENA6_MASK (MPI_CTRL_STRM_ENA6_M << MPI_CTRL_STRM_ENA6_SHIFT)
-#define MPI_CTRL_STRM_ENA7_M 0x1ULL
-#define MPI_CTRL_STRM_ENA7_SHIFT 19
-#define MPI_CTRL_STRM_ENA7_MASK (MPI_CTRL_STRM_ENA7_M << MPI_CTRL_STRM_ENA7_SHIFT)
-#define MPI_CTRL_STRM_ENA10_M 0x1ULL
-#define MPI_CTRL_STRM_ENA10_SHIFT 22
-#define MPI_CTRL_STRM_ENA10_MASK (MPI_CTRL_STRM_ENA10_M << MPI_CTRL_STRM_ENA10_SHIFT)
-#define MPI_CTRL_STRM_ENA11_M 0x1ULL
-#define MPI_CTRL_STRM_ENA11_SHIFT 23
-#define MPI_CTRL_STRM_ENA11_MASK (MPI_CTRL_STRM_ENA11_M << MPI_CTRL_STRM_ENA11_SHIFT)
-#define MPI_ISR 0x10
-#define MPI_ISR_DEF 0x0
-#define MPI_ISR_SOF10_M 0x1ULL
-#define MPI_ISR_SOF10_SHIFT 10
-#define MPI_ISR_SOF10_MASK (MPI_ISR_SOF10_M << MPI_ISR_SOF10_SHIFT)
-#define MPI_ISR_SOF11_M 0x1ULL
-#define MPI_ISR_SOF11_SHIFT 11
-#define MPI_ISR_SOF11_MASK (MPI_ISR_SOF11_M << MPI_ISR_SOF11_SHIFT)
-#define MPI_ISR_SOF8_M 0x1ULL
-#define MPI_ISR_SOF8_SHIFT 8
-#define MPI_ISR_SOF8_MASK (MPI_ISR_SOF8_M << MPI_ISR_SOF8_SHIFT)
-#define MPI_ISR_SOF9_M 0x1ULL
-#define MPI_ISR_SOF9_SHIFT 9
-#define MPI_ISR_SOF9_MASK (MPI_ISR_SOF9_M << MPI_ISR_SOF9_SHIFT)
-#define MPI_ISR_SOF2_M 0x1ULL
-#define MPI_ISR_SOF2_SHIFT 2
-#define MPI_ISR_SOF2_MASK (MPI_ISR_SOF2_M << MPI_ISR_SOF2_SHIFT)
-#define MPI_ISR_SOF3_M 0x1ULL
-#define MPI_ISR_SOF3_SHIFT 3
-#define MPI_ISR_SOF3_MASK (MPI_ISR_SOF3_M << MPI_ISR_SOF3_SHIFT)
-#define MPI_ISR_SOF0_M 0x1ULL
-#define MPI_ISR_SOF0_SHIFT 0
-#define MPI_ISR_SOF0_MASK (MPI_ISR_SOF0_M << MPI_ISR_SOF0_SHIFT)
-#define MPI_ISR_SOF1_M 0x1ULL
-#define MPI_ISR_SOF1_SHIFT 1
-#define MPI_ISR_SOF1_MASK (MPI_ISR_SOF1_M << MPI_ISR_SOF1_SHIFT)
-#define MPI_ISR_SOF6_M 0x1ULL
-#define MPI_ISR_SOF6_SHIFT 6
-#define MPI_ISR_SOF6_MASK (MPI_ISR_SOF6_M << MPI_ISR_SOF6_SHIFT)
-#define MPI_ISR_SOF7_M 0x1ULL
-#define MPI_ISR_SOF7_SHIFT 7
-#define MPI_ISR_SOF7_MASK (MPI_ISR_SOF7_M << MPI_ISR_SOF7_SHIFT)
-#define MPI_ISR_SOF4_M 0x1ULL
-#define MPI_ISR_SOF4_SHIFT 4
-#define MPI_ISR_SOF4_MASK (MPI_ISR_SOF4_M << MPI_ISR_SOF4_SHIFT)
-#define MPI_ISR_SOF5_M 0x1ULL
-#define MPI_ISR_SOF5_SHIFT 5
-#define MPI_ISR_SOF5_MASK (MPI_ISR_SOF5_M << MPI_ISR_SOF5_SHIFT)
-#define MPI_ITR 0x18
-#define MPI_ITR_DEF 0x0
-#define MPI_ITR_SOF9_M 0x1ULL
-#define MPI_ITR_SOF9_SHIFT 9
-#define MPI_ITR_SOF9_MASK (MPI_ITR_SOF9_M << MPI_ITR_SOF9_SHIFT)
-#define MPI_ITR_SOF8_M 0x1ULL
-#define MPI_ITR_SOF8_SHIFT 8
-#define MPI_ITR_SOF8_MASK (MPI_ITR_SOF8_M << MPI_ITR_SOF8_SHIFT)
-#define MPI_ITR_SOF1_M 0x1ULL
-#define MPI_ITR_SOF1_SHIFT 1
-#define MPI_ITR_SOF1_MASK (MPI_ITR_SOF1_M << MPI_ITR_SOF1_SHIFT)
-#define MPI_ITR_SOF0_M 0x1ULL
-#define MPI_ITR_SOF0_SHIFT 0
-#define MPI_ITR_SOF0_MASK (MPI_ITR_SOF0_M << MPI_ITR_SOF0_SHIFT)
-#define MPI_ITR_SOF3_M 0x1ULL
-#define MPI_ITR_SOF3_SHIFT 3
-#define MPI_ITR_SOF3_MASK (MPI_ITR_SOF3_M << MPI_ITR_SOF3_SHIFT)
-#define MPI_ITR_SOF2_M 0x1ULL
-#define MPI_ITR_SOF2_SHIFT 2
-#define MPI_ITR_SOF2_MASK (MPI_ITR_SOF2_M << MPI_ITR_SOF2_SHIFT)
-#define MPI_ITR_SOF5_M 0x1ULL
-#define MPI_ITR_SOF5_SHIFT 5
-#define MPI_ITR_SOF5_MASK (MPI_ITR_SOF5_M << MPI_ITR_SOF5_SHIFT)
-#define MPI_ITR_SOF4_M 0x1ULL
-#define MPI_ITR_SOF4_SHIFT 4
-#define MPI_ITR_SOF4_MASK (MPI_ITR_SOF4_M << MPI_ITR_SOF4_SHIFT)
-#define MPI_ITR_SOF7_M 0x1ULL
-#define MPI_ITR_SOF7_SHIFT 7
-#define MPI_ITR_SOF7_MASK (MPI_ITR_SOF7_M << MPI_ITR_SOF7_SHIFT)
-#define MPI_ITR_SOF6_M 0x1ULL
-#define MPI_ITR_SOF6_SHIFT 6
-#define MPI_ITR_SOF6_MASK (MPI_ITR_SOF6_M << MPI_ITR_SOF6_SHIFT)
-#define MPI_ITR_SOF11_M 0x1ULL
-#define MPI_ITR_SOF11_SHIFT 11
-#define MPI_ITR_SOF11_MASK (MPI_ITR_SOF11_M << MPI_ITR_SOF11_SHIFT)
-#define MPI_ITR_SOF10_M 0x1ULL
-#define MPI_ITR_SOF10_SHIFT 10
-#define MPI_ITR_SOF10_MASK (MPI_ITR_SOF10_M << MPI_ITR_SOF10_SHIFT)
-#define MPI_IER 0x20
-#define MPI_IER_DEF 0xfff
-#define MPI_IER_SOF11_M 0x1ULL
-#define MPI_IER_SOF11_SHIFT 11
-#define MPI_IER_SOF11_MASK (MPI_IER_SOF11_M << MPI_IER_SOF11_SHIFT)
-#define MPI_IER_SOF8_M 0x1ULL
-#define MPI_IER_SOF8_SHIFT 8
-#define MPI_IER_SOF8_MASK (MPI_IER_SOF8_M << MPI_IER_SOF8_SHIFT)
-#define MPI_IER_SOF9_M 0x1ULL
-#define MPI_IER_SOF9_SHIFT 9
-#define MPI_IER_SOF9_MASK (MPI_IER_SOF9_M << MPI_IER_SOF9_SHIFT)
-#define MPI_IER_SOF10_M 0x1ULL
-#define MPI_IER_SOF10_SHIFT 10
-#define MPI_IER_SOF10_MASK (MPI_IER_SOF10_M << MPI_IER_SOF10_SHIFT)
-#define MPI_IER_SOF0_M 0x1ULL
-#define MPI_IER_SOF0_SHIFT 0
-#define MPI_IER_SOF0_MASK (MPI_IER_SOF0_M << MPI_IER_SOF0_SHIFT)
-#define MPI_IER_SOF1_M 0x1ULL
-#define MPI_IER_SOF1_SHIFT 1
-#define MPI_IER_SOF1_MASK (MPI_IER_SOF1_M << MPI_IER_SOF1_SHIFT)
-#define MPI_IER_SOF2_M 0x1ULL
-#define MPI_IER_SOF2_SHIFT 2
-#define MPI_IER_SOF2_MASK (MPI_IER_SOF2_M << MPI_IER_SOF2_SHIFT)
-#define MPI_IER_SOF3_M 0x1ULL
-#define MPI_IER_SOF3_SHIFT 3
-#define MPI_IER_SOF3_MASK (MPI_IER_SOF3_M << MPI_IER_SOF3_SHIFT)
-#define MPI_IER_SOF4_M 0x1ULL
-#define MPI_IER_SOF4_SHIFT 4
-#define MPI_IER_SOF4_MASK (MPI_IER_SOF4_M << MPI_IER_SOF4_SHIFT)
-#define MPI_IER_SOF5_M 0x1ULL
-#define MPI_IER_SOF5_SHIFT 5
-#define MPI_IER_SOF5_MASK (MPI_IER_SOF5_M << MPI_IER_SOF5_SHIFT)
-#define MPI_IER_SOF6_M 0x1ULL
-#define MPI_IER_SOF6_SHIFT 6
-#define MPI_IER_SOF6_MASK (MPI_IER_SOF6_M << MPI_IER_SOF6_SHIFT)
-#define MPI_IER_SOF7_M 0x1ULL
-#define MPI_IER_SOF7_SHIFT 7
-#define MPI_IER_SOF7_MASK (MPI_IER_SOF7_M << MPI_IER_SOF7_SHIFT)
-#define MPI_IMR 0x28
-#define MPI_IMR_DEF 0x0
-#define MPI_IMR_SOF0_M 0x1ULL
-#define MPI_IMR_SOF0_SHIFT 0
-#define MPI_IMR_SOF0_MASK (MPI_IMR_SOF0_M << MPI_IMR_SOF0_SHIFT)
-#define MPI_IMR_SOF1_M 0x1ULL
-#define MPI_IMR_SOF1_SHIFT 1
-#define MPI_IMR_SOF1_MASK (MPI_IMR_SOF1_M << MPI_IMR_SOF1_SHIFT)
-#define MPI_IMR_SOF2_M 0x1ULL
-#define MPI_IMR_SOF2_SHIFT 2
-#define MPI_IMR_SOF2_MASK (MPI_IMR_SOF2_M << MPI_IMR_SOF2_SHIFT)
-#define MPI_IMR_SOF3_M 0x1ULL
-#define MPI_IMR_SOF3_SHIFT 3
-#define MPI_IMR_SOF3_MASK (MPI_IMR_SOF3_M << MPI_IMR_SOF3_SHIFT)
-#define MPI_IMR_SOF4_M 0x1ULL
-#define MPI_IMR_SOF4_SHIFT 4
-#define MPI_IMR_SOF4_MASK (MPI_IMR_SOF4_M << MPI_IMR_SOF4_SHIFT)
-#define MPI_IMR_SOF5_M 0x1ULL
-#define MPI_IMR_SOF5_SHIFT 5
-#define MPI_IMR_SOF5_MASK (MPI_IMR_SOF5_M << MPI_IMR_SOF5_SHIFT)
-#define MPI_IMR_SOF6_M 0x1ULL
-#define MPI_IMR_SOF6_SHIFT 6
-#define MPI_IMR_SOF6_MASK (MPI_IMR_SOF6_M << MPI_IMR_SOF6_SHIFT)
-#define MPI_IMR_SOF7_M 0x1ULL
-#define MPI_IMR_SOF7_SHIFT 7
-#define MPI_IMR_SOF7_MASK (MPI_IMR_SOF7_M << MPI_IMR_SOF7_SHIFT)
-#define MPI_IMR_SOF8_M 0x1ULL
-#define MPI_IMR_SOF8_SHIFT 8
-#define MPI_IMR_SOF8_MASK (MPI_IMR_SOF8_M << MPI_IMR_SOF8_SHIFT)
-#define MPI_IMR_SOF9_M 0x1ULL
-#define MPI_IMR_SOF9_SHIFT 9
-#define MPI_IMR_SOF9_MASK (MPI_IMR_SOF9_M << MPI_IMR_SOF9_SHIFT)
-#define MPI_IMR_SOF10_M 0x1ULL
-#define MPI_IMR_SOF10_SHIFT 10
-#define MPI_IMR_SOF10_MASK (MPI_IMR_SOF10_M << MPI_IMR_SOF10_SHIFT)
-#define MPI_IMR_SOF11_M 0x1ULL
-#define MPI_IMR_SOF11_SHIFT 11
-#define MPI_IMR_SOF11_MASK (MPI_IMR_SOF11_M << MPI_IMR_SOF11_SHIFT)
-#define MPI_ISR_OVF 0x30
-#define MPI_ISR_OVF_DEF 0x0
-#define MPI_ISR_OVF_SOF10_M 0x1ULL
-#define MPI_ISR_OVF_SOF10_SHIFT 10
-#define MPI_ISR_OVF_SOF10_MASK (MPI_ISR_OVF_SOF10_M << MPI_ISR_OVF_SOF10_SHIFT)
-#define MPI_ISR_OVF_SOF11_M 0x1ULL
-#define MPI_ISR_OVF_SOF11_SHIFT 11
-#define MPI_ISR_OVF_SOF11_MASK (MPI_ISR_OVF_SOF11_M << MPI_ISR_OVF_SOF11_SHIFT)
-#define MPI_ISR_OVF_SOF8_M 0x1ULL
-#define MPI_ISR_OVF_SOF8_SHIFT 8
-#define MPI_ISR_OVF_SOF8_MASK (MPI_ISR_OVF_SOF8_M << MPI_ISR_OVF_SOF8_SHIFT)
-#define MPI_ISR_OVF_SOF9_M 0x1ULL
-#define MPI_ISR_OVF_SOF9_SHIFT 9
-#define MPI_ISR_OVF_SOF9_MASK (MPI_ISR_OVF_SOF9_M << MPI_ISR_OVF_SOF9_SHIFT)
-#define MPI_ISR_OVF_SOF0_M 0x1ULL
-#define MPI_ISR_OVF_SOF0_SHIFT 0
-#define MPI_ISR_OVF_SOF0_MASK (MPI_ISR_OVF_SOF0_M << MPI_ISR_OVF_SOF0_SHIFT)
-#define MPI_ISR_OVF_SOF1_M 0x1ULL
-#define MPI_ISR_OVF_SOF1_SHIFT 1
-#define MPI_ISR_OVF_SOF1_MASK (MPI_ISR_OVF_SOF1_M << MPI_ISR_OVF_SOF1_SHIFT)
-#define MPI_ISR_OVF_SOF2_M 0x1ULL
-#define MPI_ISR_OVF_SOF2_SHIFT 2
-#define MPI_ISR_OVF_SOF2_MASK (MPI_ISR_OVF_SOF2_M << MPI_ISR_OVF_SOF2_SHIFT)
-#define MPI_ISR_OVF_SOF3_M 0x1ULL
-#define MPI_ISR_OVF_SOF3_SHIFT 3
-#define MPI_ISR_OVF_SOF3_MASK (MPI_ISR_OVF_SOF3_M << MPI_ISR_OVF_SOF3_SHIFT)
-#define MPI_ISR_OVF_SOF4_M 0x1ULL
-#define MPI_ISR_OVF_SOF4_SHIFT 4
-#define MPI_ISR_OVF_SOF4_MASK (MPI_ISR_OVF_SOF4_M << MPI_ISR_OVF_SOF4_SHIFT)
-#define MPI_ISR_OVF_SOF5_M 0x1ULL
-#define MPI_ISR_OVF_SOF5_SHIFT 5
-#define MPI_ISR_OVF_SOF5_MASK (MPI_ISR_OVF_SOF5_M << MPI_ISR_OVF_SOF5_SHIFT)
-#define MPI_ISR_OVF_SOF6_M 0x1ULL
-#define MPI_ISR_OVF_SOF6_SHIFT 6
-#define MPI_ISR_OVF_SOF6_MASK (MPI_ISR_OVF_SOF6_M << MPI_ISR_OVF_SOF6_SHIFT)
-#define MPI_ISR_OVF_SOF7_M 0x1ULL
-#define MPI_ISR_OVF_SOF7_SHIFT 7
-#define MPI_ISR_OVF_SOF7_MASK (MPI_ISR_OVF_SOF7_M << MPI_ISR_OVF_SOF7_SHIFT)
-#define MPI_ERR_ISR 0x38
-#define MPI_ERR_ISR_DEF 0x0
-#define MPI_ERR_ISR_OVF3_M 0x1ULL
-#define MPI_ERR_ISR_OVF3_SHIFT 3
-#define MPI_ERR_ISR_OVF3_MASK (MPI_ERR_ISR_OVF3_M << MPI_ERR_ISR_OVF3_SHIFT)
-#define MPI_ERR_ISR_OVF2_M 0x1ULL
-#define MPI_ERR_ISR_OVF2_SHIFT 2
-#define MPI_ERR_ISR_OVF2_MASK (MPI_ERR_ISR_OVF2_M << MPI_ERR_ISR_OVF2_SHIFT)
-#define MPI_ERR_ISR_OVF1_M 0x1ULL
-#define MPI_ERR_ISR_OVF1_SHIFT 1
-#define MPI_ERR_ISR_OVF1_MASK (MPI_ERR_ISR_OVF1_M << MPI_ERR_ISR_OVF1_SHIFT)
-#define MPI_ERR_ISR_OVF0_M 0x1ULL
-#define MPI_ERR_ISR_OVF0_SHIFT 0
-#define MPI_ERR_ISR_OVF0_MASK (MPI_ERR_ISR_OVF0_M << MPI_ERR_ISR_OVF0_SHIFT)
-#define MPI_ERR_ISR_OVF7_M 0x1ULL
-#define MPI_ERR_ISR_OVF7_SHIFT 7
-#define MPI_ERR_ISR_OVF7_MASK (MPI_ERR_ISR_OVF7_M << MPI_ERR_ISR_OVF7_SHIFT)
-#define MPI_ERR_ISR_OVF6_M 0x1ULL
-#define MPI_ERR_ISR_OVF6_SHIFT 6
-#define MPI_ERR_ISR_OVF6_MASK (MPI_ERR_ISR_OVF6_M << MPI_ERR_ISR_OVF6_SHIFT)
-#define MPI_ERR_ISR_OVF5_M 0x1ULL
-#define MPI_ERR_ISR_OVF5_SHIFT 5
-#define MPI_ERR_ISR_OVF5_MASK (MPI_ERR_ISR_OVF5_M << MPI_ERR_ISR_OVF5_SHIFT)
-#define MPI_ERR_ISR_OVF4_M 0x1ULL
-#define MPI_ERR_ISR_OVF4_SHIFT 4
-#define MPI_ERR_ISR_OVF4_MASK (MPI_ERR_ISR_OVF4_M << MPI_ERR_ISR_OVF4_SHIFT)
-#define MPI_ERR_ISR_OVF9_M 0x1ULL
-#define MPI_ERR_ISR_OVF9_SHIFT 9
-#define MPI_ERR_ISR_OVF9_MASK (MPI_ERR_ISR_OVF9_M << MPI_ERR_ISR_OVF9_SHIFT)
-#define MPI_ERR_ISR_OVF8_M 0x1ULL
-#define MPI_ERR_ISR_OVF8_SHIFT 8
-#define MPI_ERR_ISR_OVF8_MASK (MPI_ERR_ISR_OVF8_M << MPI_ERR_ISR_OVF8_SHIFT)
-#define MPI_ERR_ISR_OVF11_M 0x1ULL
-#define MPI_ERR_ISR_OVF11_SHIFT 11
-#define MPI_ERR_ISR_OVF11_MASK (MPI_ERR_ISR_OVF11_M << MPI_ERR_ISR_OVF11_SHIFT)
-#define MPI_ERR_ISR_OVF10_M 0x1ULL
-#define MPI_ERR_ISR_OVF10_SHIFT 10
-#define MPI_ERR_ISR_OVF10_MASK (MPI_ERR_ISR_OVF10_M << MPI_ERR_ISR_OVF10_SHIFT)
-#define MPI_ERR_ITR 0x40
-#define MPI_ERR_ITR_DEF 0x0
-#define MPI_ERR_ITR_OVF0_M 0x1ULL
-#define MPI_ERR_ITR_OVF0_SHIFT 0
-#define MPI_ERR_ITR_OVF0_MASK (MPI_ERR_ITR_OVF0_M << MPI_ERR_ITR_OVF0_SHIFT)
-#define MPI_ERR_ITR_OVF1_M 0x1ULL
-#define MPI_ERR_ITR_OVF1_SHIFT 1
-#define MPI_ERR_ITR_OVF1_MASK (MPI_ERR_ITR_OVF1_M << MPI_ERR_ITR_OVF1_SHIFT)
-#define MPI_ERR_ITR_OVF2_M 0x1ULL
-#define MPI_ERR_ITR_OVF2_SHIFT 2
-#define MPI_ERR_ITR_OVF2_MASK (MPI_ERR_ITR_OVF2_M << MPI_ERR_ITR_OVF2_SHIFT)
-#define MPI_ERR_ITR_OVF3_M 0x1ULL
-#define MPI_ERR_ITR_OVF3_SHIFT 3
-#define MPI_ERR_ITR_OVF3_MASK (MPI_ERR_ITR_OVF3_M << MPI_ERR_ITR_OVF3_SHIFT)
-#define MPI_ERR_ITR_OVF4_M 0x1ULL
-#define MPI_ERR_ITR_OVF4_SHIFT 4
-#define MPI_ERR_ITR_OVF4_MASK (MPI_ERR_ITR_OVF4_M << MPI_ERR_ITR_OVF4_SHIFT)
-#define MPI_ERR_ITR_OVF5_M 0x1ULL
-#define MPI_ERR_ITR_OVF5_SHIFT 5
-#define MPI_ERR_ITR_OVF5_MASK (MPI_ERR_ITR_OVF5_M << MPI_ERR_ITR_OVF5_SHIFT)
-#define MPI_ERR_ITR_OVF6_M 0x1ULL
-#define MPI_ERR_ITR_OVF6_SHIFT 6
-#define MPI_ERR_ITR_OVF6_MASK (MPI_ERR_ITR_OVF6_M << MPI_ERR_ITR_OVF6_SHIFT)
-#define MPI_ERR_ITR_OVF7_M 0x1ULL
-#define MPI_ERR_ITR_OVF7_SHIFT 7
-#define MPI_ERR_ITR_OVF7_MASK (MPI_ERR_ITR_OVF7_M << MPI_ERR_ITR_OVF7_SHIFT)
-#define MPI_ERR_ITR_OVF8_M 0x1ULL
-#define MPI_ERR_ITR_OVF8_SHIFT 8
-#define MPI_ERR_ITR_OVF8_MASK (MPI_ERR_ITR_OVF8_M << MPI_ERR_ITR_OVF8_SHIFT)
-#define MPI_ERR_ITR_OVF9_M 0x1ULL
-#define MPI_ERR_ITR_OVF9_SHIFT 9
-#define MPI_ERR_ITR_OVF9_MASK (MPI_ERR_ITR_OVF9_M << MPI_ERR_ITR_OVF9_SHIFT)
-#define MPI_ERR_ITR_OVF10_M 0x1ULL
-#define MPI_ERR_ITR_OVF10_SHIFT 10
-#define MPI_ERR_ITR_OVF10_MASK (MPI_ERR_ITR_OVF10_M << MPI_ERR_ITR_OVF10_SHIFT)
-#define MPI_ERR_ITR_OVF11_M 0x1ULL
-#define MPI_ERR_ITR_OVF11_SHIFT 11
-#define MPI_ERR_ITR_OVF11_MASK (MPI_ERR_ITR_OVF11_M << MPI_ERR_ITR_OVF11_SHIFT)
-#define MPI_ERR_IER 0x48
-#define MPI_ERR_IER_DEF 0xfff
-#define MPI_ERR_IER_OVF1_M 0x1ULL
-#define MPI_ERR_IER_OVF1_SHIFT 1
-#define MPI_ERR_IER_OVF1_MASK (MPI_ERR_IER_OVF1_M << MPI_ERR_IER_OVF1_SHIFT)
-#define MPI_ERR_IER_OVF0_M 0x1ULL
-#define MPI_ERR_IER_OVF0_SHIFT 0
-#define MPI_ERR_IER_OVF0_MASK (MPI_ERR_IER_OVF0_M << MPI_ERR_IER_OVF0_SHIFT)
-#define MPI_ERR_IER_OVF3_M 0x1ULL
-#define MPI_ERR_IER_OVF3_SHIFT 3
-#define MPI_ERR_IER_OVF3_MASK (MPI_ERR_IER_OVF3_M << MPI_ERR_IER_OVF3_SHIFT)
-#define MPI_ERR_IER_OVF2_M 0x1ULL
-#define MPI_ERR_IER_OVF2_SHIFT 2
-#define MPI_ERR_IER_OVF2_MASK (MPI_ERR_IER_OVF2_M << MPI_ERR_IER_OVF2_SHIFT)
-#define MPI_ERR_IER_OVF5_M 0x1ULL
-#define MPI_ERR_IER_OVF5_SHIFT 5
-#define MPI_ERR_IER_OVF5_MASK (MPI_ERR_IER_OVF5_M << MPI_ERR_IER_OVF5_SHIFT)
-#define MPI_ERR_IER_OVF4_M 0x1ULL
-#define MPI_ERR_IER_OVF4_SHIFT 4
-#define MPI_ERR_IER_OVF4_MASK (MPI_ERR_IER_OVF4_M << MPI_ERR_IER_OVF4_SHIFT)
-#define MPI_ERR_IER_OVF7_M 0x1ULL
-#define MPI_ERR_IER_OVF7_SHIFT 7
-#define MPI_ERR_IER_OVF7_MASK (MPI_ERR_IER_OVF7_M << MPI_ERR_IER_OVF7_SHIFT)
-#define MPI_ERR_IER_OVF6_M 0x1ULL
-#define MPI_ERR_IER_OVF6_SHIFT 6
-#define MPI_ERR_IER_OVF6_MASK (MPI_ERR_IER_OVF6_M << MPI_ERR_IER_OVF6_SHIFT)
-#define MPI_ERR_IER_OVF9_M 0x1ULL
-#define MPI_ERR_IER_OVF9_SHIFT 9
-#define MPI_ERR_IER_OVF9_MASK (MPI_ERR_IER_OVF9_M << MPI_ERR_IER_OVF9_SHIFT)
-#define MPI_ERR_IER_OVF8_M 0x1ULL
-#define MPI_ERR_IER_OVF8_SHIFT 8
-#define MPI_ERR_IER_OVF8_MASK (MPI_ERR_IER_OVF8_M << MPI_ERR_IER_OVF8_SHIFT)
-#define MPI_ERR_IER_OVF11_M 0x1ULL
-#define MPI_ERR_IER_OVF11_SHIFT 11
-#define MPI_ERR_IER_OVF11_MASK (MPI_ERR_IER_OVF11_M << MPI_ERR_IER_OVF11_SHIFT)
-#define MPI_ERR_IER_OVF10_M 0x1ULL
-#define MPI_ERR_IER_OVF10_SHIFT 10
-#define MPI_ERR_IER_OVF10_MASK (MPI_ERR_IER_OVF10_M << MPI_ERR_IER_OVF10_SHIFT)
-#define MPI_ERR_IMR 0x50
-#define MPI_ERR_IMR_DEF 0x0
-#define MPI_ERR_IMR_OVF11_M 0x1ULL
-#define MPI_ERR_IMR_OVF11_SHIFT 11
-#define MPI_ERR_IMR_OVF11_MASK (MPI_ERR_IMR_OVF11_M << MPI_ERR_IMR_OVF11_SHIFT)
-#define MPI_ERR_IMR_OVF10_M 0x1ULL
-#define MPI_ERR_IMR_OVF10_SHIFT 10
-#define MPI_ERR_IMR_OVF10_MASK (MPI_ERR_IMR_OVF10_M << MPI_ERR_IMR_OVF10_SHIFT)
-#define MPI_ERR_IMR_OVF9_M 0x1ULL
-#define MPI_ERR_IMR_OVF9_SHIFT 9
-#define MPI_ERR_IMR_OVF9_MASK (MPI_ERR_IMR_OVF9_M << MPI_ERR_IMR_OVF9_SHIFT)
-#define MPI_ERR_IMR_OVF8_M 0x1ULL
-#define MPI_ERR_IMR_OVF8_SHIFT 8
-#define MPI_ERR_IMR_OVF8_MASK (MPI_ERR_IMR_OVF8_M << MPI_ERR_IMR_OVF8_SHIFT)
-#define MPI_ERR_IMR_OVF1_M 0x1ULL
-#define MPI_ERR_IMR_OVF1_SHIFT 1
-#define MPI_ERR_IMR_OVF1_MASK (MPI_ERR_IMR_OVF1_M << MPI_ERR_IMR_OVF1_SHIFT)
-#define MPI_ERR_IMR_OVF0_M 0x1ULL
-#define MPI_ERR_IMR_OVF0_SHIFT 0
-#define MPI_ERR_IMR_OVF0_MASK (MPI_ERR_IMR_OVF0_M << MPI_ERR_IMR_OVF0_SHIFT)
-#define MPI_ERR_IMR_OVF3_M 0x1ULL
-#define MPI_ERR_IMR_OVF3_SHIFT 3
-#define MPI_ERR_IMR_OVF3_MASK (MPI_ERR_IMR_OVF3_M << MPI_ERR_IMR_OVF3_SHIFT)
-#define MPI_ERR_IMR_OVF2_M 0x1ULL
-#define MPI_ERR_IMR_OVF2_SHIFT 2
-#define MPI_ERR_IMR_OVF2_MASK (MPI_ERR_IMR_OVF2_M << MPI_ERR_IMR_OVF2_SHIFT)
-#define MPI_ERR_IMR_OVF5_M 0x1ULL
-#define MPI_ERR_IMR_OVF5_SHIFT 5
-#define MPI_ERR_IMR_OVF5_MASK (MPI_ERR_IMR_OVF5_M << MPI_ERR_IMR_OVF5_SHIFT)
-#define MPI_ERR_IMR_OVF4_M 0x1ULL
-#define MPI_ERR_IMR_OVF4_SHIFT 4
-#define MPI_ERR_IMR_OVF4_MASK (MPI_ERR_IMR_OVF4_M << MPI_ERR_IMR_OVF4_SHIFT)
-#define MPI_ERR_IMR_OVF7_M 0x1ULL
-#define MPI_ERR_IMR_OVF7_SHIFT 7
-#define MPI_ERR_IMR_OVF7_MASK (MPI_ERR_IMR_OVF7_M << MPI_ERR_IMR_OVF7_SHIFT)
-#define MPI_ERR_IMR_OVF6_M 0x1ULL
-#define MPI_ERR_IMR_OVF6_SHIFT 6
-#define MPI_ERR_IMR_OVF6_MASK (MPI_ERR_IMR_OVF6_M << MPI_ERR_IMR_OVF6_SHIFT)
-#define MPI_ERR_ISR_OVF 0x58
-#define MPI_ERR_ISR_OVF_DEF 0x0
-#define MPI_ERR_ISR_OVF_OVF11_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF11_SHIFT 11
-#define MPI_ERR_ISR_OVF_OVF11_MASK (MPI_ERR_ISR_OVF_OVF11_M << MPI_ERR_ISR_OVF_OVF11_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF10_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF10_SHIFT 10
-#define MPI_ERR_ISR_OVF_OVF10_MASK (MPI_ERR_ISR_OVF_OVF10_M << MPI_ERR_ISR_OVF_OVF10_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF1_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF1_SHIFT 1
-#define MPI_ERR_ISR_OVF_OVF1_MASK (MPI_ERR_ISR_OVF_OVF1_M << MPI_ERR_ISR_OVF_OVF1_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF0_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF0_SHIFT 0
-#define MPI_ERR_ISR_OVF_OVF0_MASK (MPI_ERR_ISR_OVF_OVF0_M << MPI_ERR_ISR_OVF_OVF0_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF3_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF3_SHIFT 3
-#define MPI_ERR_ISR_OVF_OVF3_MASK (MPI_ERR_ISR_OVF_OVF3_M << MPI_ERR_ISR_OVF_OVF3_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF2_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF2_SHIFT 2
-#define MPI_ERR_ISR_OVF_OVF2_MASK (MPI_ERR_ISR_OVF_OVF2_M << MPI_ERR_ISR_OVF_OVF2_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF5_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF5_SHIFT 5
-#define MPI_ERR_ISR_OVF_OVF5_MASK (MPI_ERR_ISR_OVF_OVF5_M << MPI_ERR_ISR_OVF_OVF5_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF4_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF4_SHIFT 4
-#define MPI_ERR_ISR_OVF_OVF4_MASK (MPI_ERR_ISR_OVF_OVF4_M << MPI_ERR_ISR_OVF_OVF4_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF7_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF7_SHIFT 7
-#define MPI_ERR_ISR_OVF_OVF7_MASK (MPI_ERR_ISR_OVF_OVF7_M << MPI_ERR_ISR_OVF_OVF7_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF6_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF6_SHIFT 6
-#define MPI_ERR_ISR_OVF_OVF6_MASK (MPI_ERR_ISR_OVF_OVF6_M << MPI_ERR_ISR_OVF_OVF6_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF9_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF9_SHIFT 9
-#define MPI_ERR_ISR_OVF_OVF9_MASK (MPI_ERR_ISR_OVF_OVF9_M << MPI_ERR_ISR_OVF_OVF9_SHIFT)
-#define MPI_ERR_ISR_OVF_OVF8_M 0x1ULL
-#define MPI_ERR_ISR_OVF_OVF8_SHIFT 8
-#define MPI_ERR_ISR_OVF_OVF8_MASK (MPI_ERR_ISR_OVF_OVF8_M << MPI_ERR_ISR_OVF_OVF8_SHIFT)
-#define MPI_STATUS 0x60
-#define MPI_STATUS_DEF 0xfff
-#define MPI_STATUS_STRM_IDLE_M 0xfffULL
-#define MPI_STATUS_STRM_IDLE_SHIFT 0
-#define MPI_STATUS_STRM_IDLE_MASK (MPI_STATUS_STRM_IDLE_M << MPI_STATUS_STRM_IDLE_SHIFT)
-#define MPI_STRM_SEL 0x68
-#define MPI_STRM_SEL_DEF 0xf
-#define MPI_STRM_SEL_MPI_STRM_SEL_M 0xfULL
-#define MPI_STRM_SEL_MPI_STRM_SEL_SHIFT 0
-#define MPI_STRM_SEL_MPI_STRM_SEL_MASK (MPI_STRM_SEL_MPI_STRM_SEL_M << MPI_STRM_SEL_MPI_STRM_SEL_SHIFT)
-#define MPI_STRM_CTRL 0x70
-#define MPI_STRM_CTRL_DEF 0x0
-#define MPI_STRM_CTRL_RST_M 0x1ULL
-#define MPI_STRM_CTRL_RST_SHIFT 2
-#define MPI_STRM_CTRL_RST_MASK (MPI_STRM_CTRL_RST_M << MPI_STRM_CTRL_RST_SHIFT)
-#define MPI_STRM_CTRL_CLEANUP_M 0x1ULL
-#define MPI_STRM_CTRL_CLEANUP_SHIFT 1
-#define MPI_STRM_CTRL_CLEANUP_MASK (MPI_STRM_CTRL_CLEANUP_M << MPI_STRM_CTRL_CLEANUP_SHIFT)
-#define MPI_STRM_CTRL_NUM_FRAME_M 0xffffULL
-#define MPI_STRM_CTRL_NUM_FRAME_SHIFT 8
-#define MPI_STRM_CTRL_NUM_FRAME_MASK (MPI_STRM_CTRL_NUM_FRAME_M << MPI_STRM_CTRL_NUM_FRAME_SHIFT)
-#define MPI_STRM_CNFG0 0x78
-#define MPI_STRM_CNFG0_DEF 0x1e002800003baa0
-#define MPI_STRM_CNFG0_DT_PROC_M 0x3fULL
-#define MPI_STRM_CNFG0_DT_PROC_SHIFT 10
-#define MPI_STRM_CNFG0_DT_PROC_MASK (MPI_STRM_CNFG0_DT_PROC_M << MPI_STRM_CNFG0_DT_PROC_SHIFT)
-#define MPI_STRM_CNFG0_IMG_WIDTH_M 0xffffULL
-#define MPI_STRM_CNFG0_IMG_WIDTH_SHIFT 32
-#define MPI_STRM_CNFG0_IMG_WIDTH_MASK (MPI_STRM_CNFG0_IMG_WIDTH_M << MPI_STRM_CNFG0_IMG_WIDTH_SHIFT)
-#define MPI_STRM_CNFG0_VC_M 0x3ULL
-#define MPI_STRM_CNFG0_VC_SHIFT 0
-#define MPI_STRM_CNFG0_VC_MASK (MPI_STRM_CNFG0_VC_M << MPI_STRM_CNFG0_VC_SHIFT)
-#define MPI_STRM_CNFG0_IMG_HEIGHT_M 0xffffULL
-#define MPI_STRM_CNFG0_IMG_HEIGHT_SHIFT 48
-#define MPI_STRM_CNFG0_IMG_HEIGHT_MASK (MPI_STRM_CNFG0_IMG_HEIGHT_M << MPI_STRM_CNFG0_IMG_HEIGHT_SHIFT)
-#define MPI_STRM_CNFG0_DT_IN_M 0x3fULL
-#define MPI_STRM_CNFG0_DT_IN_SHIFT 4
-#define MPI_STRM_CNFG0_DT_IN_MASK (MPI_STRM_CNFG0_DT_IN_M << MPI_STRM_CNFG0_DT_IN_SHIFT)
-#define MPI_STRM_CNFG0_STRP_HEIGHT_M 0x3fULL
-#define MPI_STRM_CNFG0_STRP_HEIGHT_SHIFT 16
-#define MPI_STRM_CNFG0_STRP_HEIGHT_MASK (MPI_STRM_CNFG0_STRP_HEIGHT_M << MPI_STRM_CNFG0_STRP_HEIGHT_SHIFT)
-#define MPI_STRM_CNFG1 0x80
-#define MPI_STRM_CNFG1_DEF 0x27000000000000
-#define MPI_STRM_CNFG1_SEG_END_M 0xffULL
-#define MPI_STRM_CNFG1_SEG_END_SHIFT 16
-#define MPI_STRM_CNFG1_SEG_END_MASK (MPI_STRM_CNFG1_SEG_END_M << MPI_STRM_CNFG1_SEG_END_SHIFT)
-#define MPI_STRM_CNFG1_SEG_WORDS_PER_ROW_M 0xfffULL
-#define MPI_STRM_CNFG1_SEG_WORDS_PER_ROW_SHIFT 48
-#define MPI_STRM_CNFG1_SEG_WORDS_PER_ROW_MASK (MPI_STRM_CNFG1_SEG_WORDS_PER_ROW_M << MPI_STRM_CNFG1_SEG_WORDS_PER_ROW_SHIFT)
-#define MPI_STRM_CNFG1_SEG_START_M 0xffULL
-#define MPI_STRM_CNFG1_SEG_START_SHIFT 0
-#define MPI_STRM_CNFG1_SEG_START_MASK (MPI_STRM_CNFG1_SEG_START_M << MPI_STRM_CNFG1_SEG_START_SHIFT)
-#define MPI_STRM_CNFG1_SEGS_PER_ROW_M 0xffULL
-#define MPI_STRM_CNFG1_SEGS_PER_ROW_SHIFT 32
-#define MPI_STRM_CNFG1_SEGS_PER_ROW_MASK (MPI_STRM_CNFG1_SEGS_PER_ROW_M << MPI_STRM_CNFG1_SEGS_PER_ROW_SHIFT)
-#define MPI_STRM_CNFG0_RO 0x88
-#define MPI_STRM_CNFG0_RO_DEF 0x1e002800003baa0
-#define MPI_STRM_CNFG0_RO_IMG_WIDTH_M 0xffffULL
-#define MPI_STRM_CNFG0_RO_IMG_WIDTH_SHIFT 32
-#define MPI_STRM_CNFG0_RO_IMG_WIDTH_MASK (MPI_STRM_CNFG0_RO_IMG_WIDTH_M << MPI_STRM_CNFG0_RO_IMG_WIDTH_SHIFT)
-#define MPI_STRM_CNFG0_RO_DT_PROC_M 0x3fULL
-#define MPI_STRM_CNFG0_RO_DT_PROC_SHIFT 10
-#define MPI_STRM_CNFG0_RO_DT_PROC_MASK (MPI_STRM_CNFG0_RO_DT_PROC_M << MPI_STRM_CNFG0_RO_DT_PROC_SHIFT)
-#define MPI_STRM_CNFG0_RO_IMG_HEIGHT_M 0xffffULL
-#define MPI_STRM_CNFG0_RO_IMG_HEIGHT_SHIFT 48
-#define MPI_STRM_CNFG0_RO_IMG_HEIGHT_MASK (MPI_STRM_CNFG0_RO_IMG_HEIGHT_M << MPI_STRM_CNFG0_RO_IMG_HEIGHT_SHIFT)
-#define MPI_STRM_CNFG0_RO_DT_IN_M 0x3fULL
-#define MPI_STRM_CNFG0_RO_DT_IN_SHIFT 4
-#define MPI_STRM_CNFG0_RO_DT_IN_MASK (MPI_STRM_CNFG0_RO_DT_IN_M << MPI_STRM_CNFG0_RO_DT_IN_SHIFT)
-#define MPI_STRM_CNFG0_RO_STRP_HEIGHT_M 0x3fULL
-#define MPI_STRM_CNFG0_RO_STRP_HEIGHT_SHIFT 16
-#define MPI_STRM_CNFG0_RO_STRP_HEIGHT_MASK (MPI_STRM_CNFG0_RO_STRP_HEIGHT_M << MPI_STRM_CNFG0_RO_STRP_HEIGHT_SHIFT)
-#define MPI_STRM_CNFG0_RO_VC_M 0x3ULL
-#define MPI_STRM_CNFG0_RO_VC_SHIFT 0
-#define MPI_STRM_CNFG0_RO_VC_MASK (MPI_STRM_CNFG0_RO_VC_M << MPI_STRM_CNFG0_RO_VC_SHIFT)
-#define MPI_STRM_CNFG1_RO 0x90
-#define MPI_STRM_CNFG1_RO_DEF 0x27000000000000
-#define MPI_STRM_CNFG1_RO_SEG_WORDS_PER_ROW_M 0xfffULL
-#define MPI_STRM_CNFG1_RO_SEG_WORDS_PER_ROW_SHIFT 48
-#define MPI_STRM_CNFG1_RO_SEG_WORDS_PER_ROW_MASK (MPI_STRM_CNFG1_RO_SEG_WORDS_PER_ROW_M << MPI_STRM_CNFG1_RO_SEG_WORDS_PER_ROW_SHIFT)
-#define MPI_STRM_CNFG1_RO_SEG_START_M 0xffULL
-#define MPI_STRM_CNFG1_RO_SEG_START_SHIFT 0
-#define MPI_STRM_CNFG1_RO_SEG_START_MASK (MPI_STRM_CNFG1_RO_SEG_START_M << MPI_STRM_CNFG1_RO_SEG_START_SHIFT)
-#define MPI_STRM_CNFG1_RO_SEG_END_M 0xffULL
-#define MPI_STRM_CNFG1_RO_SEG_END_SHIFT 16
-#define MPI_STRM_CNFG1_RO_SEG_END_MASK (MPI_STRM_CNFG1_RO_SEG_END_M << MPI_STRM_CNFG1_RO_SEG_END_SHIFT)
-#define MPI_STRM_CNFG1_RO_SEGS_PER_ROW_M 0xffULL
-#define MPI_STRM_CNFG1_RO_SEGS_PER_ROW_SHIFT 32
-#define MPI_STRM_CNFG1_RO_SEGS_PER_ROW_MASK (MPI_STRM_CNFG1_RO_SEGS_PER_ROW_M << MPI_STRM_CNFG1_RO_SEGS_PER_ROW_SHIFT)
-#define MPI_MISC_CTRL_I0 0x98
-#define MPI_MISC_CTRL_I0_DEF 0x4
-#define MPI_MISC_CTRL_I0_PPREF_CNT_M 0x7ULL
-#define MPI_MISC_CTRL_I0_PPREF_CNT_SHIFT 0
-#define MPI_MISC_CTRL_I0_PPREF_CNT_MASK (MPI_MISC_CTRL_I0_PPREF_CNT_M << MPI_MISC_CTRL_I0_PPREF_CNT_SHIFT)
-#define MPI_MISC_STATUS_I0 0xa0
-#define MPI_MISC_STATUS_I0_DEF 0x0
-#define MPI_MISC_STATUS_I0_PPREF_REQ_CNT_M 0x7ULL
-#define MPI_MISC_STATUS_I0_PPREF_REQ_CNT_SHIFT 4
-#define MPI_MISC_STATUS_I0_PPREF_REQ_CNT_MASK (MPI_MISC_STATUS_I0_PPREF_REQ_CNT_M << MPI_MISC_STATUS_I0_PPREF_REQ_CNT_SHIFT)
-#define MPI_MISC_STATUS_I0_PPREF_FIFO_CNT_M 0x7ULL
-#define MPI_MISC_STATUS_I0_PPREF_FIFO_CNT_SHIFT 0
-#define MPI_MISC_STATUS_I0_PPREF_FIFO_CNT_MASK (MPI_MISC_STATUS_I0_PPREF_FIFO_CNT_M << MPI_MISC_STATUS_I0_PPREF_FIFO_CNT_SHIFT)
-#define MPI_MISC_CTRL_I1 0xa8
-#define MPI_MISC_CTRL_I1_DEF 0x4
-#define MPI_MISC_CTRL_I1_PPREF_CNT_M 0x7ULL
-#define MPI_MISC_CTRL_I1_PPREF_CNT_SHIFT 0
-#define MPI_MISC_CTRL_I1_PPREF_CNT_MASK (MPI_MISC_CTRL_I1_PPREF_CNT_M << MPI_MISC_CTRL_I1_PPREF_CNT_SHIFT)
-#define MPI_MISC_STATUS_I1 0xb0
-#define MPI_MISC_STATUS_I1_DEF 0x0
-#define MPI_MISC_STATUS_I1_PPREF_FIFO_CNT_M 0x7ULL
-#define MPI_MISC_STATUS_I1_PPREF_FIFO_CNT_SHIFT 0
-#define MPI_MISC_STATUS_I1_PPREF_FIFO_CNT_MASK (MPI_MISC_STATUS_I1_PPREF_FIFO_CNT_M << MPI_MISC_STATUS_I1_PPREF_FIFO_CNT_SHIFT)
-#define MPI_MISC_STATUS_I1_PPREF_REQ_CNT_M 0x7ULL
-#define MPI_MISC_STATUS_I1_PPREF_REQ_CNT_SHIFT 4
-#define MPI_MISC_STATUS_I1_PPREF_REQ_CNT_MASK (MPI_MISC_STATUS_I1_PPREF_REQ_CNT_M << MPI_MISC_STATUS_I1_PPREF_REQ_CNT_SHIFT)
-#define MPI_MISC_CTRL_I2 0xb8
-#define MPI_MISC_CTRL_I2_DEF 0x4
-#define MPI_MISC_CTRL_I2_PPREF_CNT_M 0x7ULL
-#define MPI_MISC_CTRL_I2_PPREF_CNT_SHIFT 0
-#define MPI_MISC_CTRL_I2_PPREF_CNT_MASK (MPI_MISC_CTRL_I2_PPREF_CNT_M << MPI_MISC_CTRL_I2_PPREF_CNT_SHIFT)
-#define MPI_MISC_STATUS_I2 0xc0
-#define MPI_MISC_STATUS_I2_DEF 0x0
-#define MPI_MISC_STATUS_I2_PPREF_FIFO_CNT_M 0x7ULL
-#define MPI_MISC_STATUS_I2_PPREF_FIFO_CNT_SHIFT 0
-#define MPI_MISC_STATUS_I2_PPREF_FIFO_CNT_MASK (MPI_MISC_STATUS_I2_PPREF_FIFO_CNT_M << MPI_MISC_STATUS_I2_PPREF_FIFO_CNT_SHIFT)
-#define MPI_MISC_STATUS_I2_PPREF_REQ_CNT_M 0x7ULL
-#define MPI_MISC_STATUS_I2_PPREF_REQ_CNT_SHIFT 4
-#define MPI_MISC_STATUS_I2_PPREF_REQ_CNT_MASK (MPI_MISC_STATUS_I2_PPREF_REQ_CNT_M << MPI_MISC_STATUS_I2_PPREF_REQ_CNT_SHIFT)
-#define MPO_CAP 0xc8
-#define MPO_CAP_DEF 0x82
-#define MPO_CAP_MAX_STRM_M 0xfULL
-#define MPO_CAP_MAX_STRM_SHIFT 4
-#define MPO_CAP_MAX_STRM_MASK (MPO_CAP_MAX_STRM_M << MPO_CAP_MAX_STRM_SHIFT)
-#define MPO_CAP_MAX_IFC_M 0x3ULL
-#define MPO_CAP_MAX_IFC_SHIFT 0
-#define MPO_CAP_MAX_IFC_MASK (MPO_CAP_MAX_IFC_M << MPO_CAP_MAX_IFC_SHIFT)
-#define MPO_CTRL 0xd0
-#define MPO_CTRL_DEF 0x0
-#define MPO_CTRL_STRM_CONTINUOUS0_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS0_SHIFT 32
-#define MPO_CTRL_STRM_CONTINUOUS0_MASK (MPO_CTRL_STRM_CONTINUOUS0_M << MPO_CTRL_STRM_CONTINUOUS0_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS1_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS1_SHIFT 33
-#define MPO_CTRL_STRM_CONTINUOUS1_MASK (MPO_CTRL_STRM_CONTINUOUS1_M << MPO_CTRL_STRM_CONTINUOUS1_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS2_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS2_SHIFT 34
-#define MPO_CTRL_STRM_CONTINUOUS2_MASK (MPO_CTRL_STRM_CONTINUOUS2_M << MPO_CTRL_STRM_CONTINUOUS2_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS3_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS3_SHIFT 35
-#define MPO_CTRL_STRM_CONTINUOUS3_MASK (MPO_CTRL_STRM_CONTINUOUS3_M << MPO_CTRL_STRM_CONTINUOUS3_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS4_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS4_SHIFT 36
-#define MPO_CTRL_STRM_CONTINUOUS4_MASK (MPO_CTRL_STRM_CONTINUOUS4_M << MPO_CTRL_STRM_CONTINUOUS4_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS5_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS5_SHIFT 37
-#define MPO_CTRL_STRM_CONTINUOUS5_MASK (MPO_CTRL_STRM_CONTINUOUS5_M << MPO_CTRL_STRM_CONTINUOUS5_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS6_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS6_SHIFT 38
-#define MPO_CTRL_STRM_CONTINUOUS6_MASK (MPO_CTRL_STRM_CONTINUOUS6_M << MPO_CTRL_STRM_CONTINUOUS6_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS7_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS7_SHIFT 39
-#define MPO_CTRL_STRM_CONTINUOUS7_MASK (MPO_CTRL_STRM_CONTINUOUS7_M << MPO_CTRL_STRM_CONTINUOUS7_SHIFT)
-#define MPO_CTRL_STRM_ENA2_M 0x1ULL
-#define MPO_CTRL_STRM_ENA2_SHIFT 10
-#define MPO_CTRL_STRM_ENA2_MASK (MPO_CTRL_STRM_ENA2_M << MPO_CTRL_STRM_ENA2_SHIFT)
-#define MPO_CTRL_STRM_ENA3_M 0x1ULL
-#define MPO_CTRL_STRM_ENA3_SHIFT 11
-#define MPO_CTRL_STRM_ENA3_MASK (MPO_CTRL_STRM_ENA3_M << MPO_CTRL_STRM_ENA3_SHIFT)
-#define MPO_CTRL_STRM_ENA0_M 0x1ULL
-#define MPO_CTRL_STRM_ENA0_SHIFT 8
-#define MPO_CTRL_STRM_ENA0_MASK (MPO_CTRL_STRM_ENA0_M << MPO_CTRL_STRM_ENA0_SHIFT)
-#define MPO_CTRL_STRM_ENA1_M 0x1ULL
-#define MPO_CTRL_STRM_ENA1_SHIFT 9
-#define MPO_CTRL_STRM_ENA1_MASK (MPO_CTRL_STRM_ENA1_M << MPO_CTRL_STRM_ENA1_SHIFT)
-#define MPO_CTRL_STRM_ENA6_M 0x1ULL
-#define MPO_CTRL_STRM_ENA6_SHIFT 14
-#define MPO_CTRL_STRM_ENA6_MASK (MPO_CTRL_STRM_ENA6_M << MPO_CTRL_STRM_ENA6_SHIFT)
-#define MPO_CTRL_STRM_ENA7_M 0x1ULL
-#define MPO_CTRL_STRM_ENA7_SHIFT 15
-#define MPO_CTRL_STRM_ENA7_MASK (MPO_CTRL_STRM_ENA7_M << MPO_CTRL_STRM_ENA7_SHIFT)
-#define MPO_CTRL_STRM_ENA4_M 0x1ULL
-#define MPO_CTRL_STRM_ENA4_SHIFT 12
-#define MPO_CTRL_STRM_ENA4_MASK (MPO_CTRL_STRM_ENA4_M << MPO_CTRL_STRM_ENA4_SHIFT)
-#define MPO_CTRL_STRM_ENA5_M 0x1ULL
-#define MPO_CTRL_STRM_ENA5_SHIFT 13
-#define MPO_CTRL_STRM_ENA5_MASK (MPO_CTRL_STRM_ENA5_M << MPO_CTRL_STRM_ENA5_SHIFT)
-#define MPO_CTRL_STRM_ENA_SET5_M 0x1ULL
-#define MPO_CTRL_STRM_ENA_SET5_SHIFT 5
-#define MPO_CTRL_STRM_ENA_SET5_MASK (MPO_CTRL_STRM_ENA_SET5_M << MPO_CTRL_STRM_ENA_SET5_SHIFT)
-#define MPO_CTRL_STRM_ENA_SET4_M 0x1ULL
-#define MPO_CTRL_STRM_ENA_SET4_SHIFT 4
-#define MPO_CTRL_STRM_ENA_SET4_MASK (MPO_CTRL_STRM_ENA_SET4_M << MPO_CTRL_STRM_ENA_SET4_SHIFT)
-#define MPO_CTRL_STRM_ENA_SET7_M 0x1ULL
-#define MPO_CTRL_STRM_ENA_SET7_SHIFT 7
-#define MPO_CTRL_STRM_ENA_SET7_MASK (MPO_CTRL_STRM_ENA_SET7_M << MPO_CTRL_STRM_ENA_SET7_SHIFT)
-#define MPO_CTRL_STRM_ENA_SET6_M 0x1ULL
-#define MPO_CTRL_STRM_ENA_SET6_SHIFT 6
-#define MPO_CTRL_STRM_ENA_SET6_MASK (MPO_CTRL_STRM_ENA_SET6_M << MPO_CTRL_STRM_ENA_SET6_SHIFT)
-#define MPO_CTRL_STRM_ENA_SET1_M 0x1ULL
-#define MPO_CTRL_STRM_ENA_SET1_SHIFT 1
-#define MPO_CTRL_STRM_ENA_SET1_MASK (MPO_CTRL_STRM_ENA_SET1_M << MPO_CTRL_STRM_ENA_SET1_SHIFT)
-#define MPO_CTRL_STRM_ENA_SET0_M 0x1ULL
-#define MPO_CTRL_STRM_ENA_SET0_SHIFT 0
-#define MPO_CTRL_STRM_ENA_SET0_MASK (MPO_CTRL_STRM_ENA_SET0_M << MPO_CTRL_STRM_ENA_SET0_SHIFT)
-#define MPO_CTRL_STRM_ENA_SET3_M 0x1ULL
-#define MPO_CTRL_STRM_ENA_SET3_SHIFT 3
-#define MPO_CTRL_STRM_ENA_SET3_MASK (MPO_CTRL_STRM_ENA_SET3_M << MPO_CTRL_STRM_ENA_SET3_SHIFT)
-#define MPO_CTRL_STRM_ENA_SET2_M 0x1ULL
-#define MPO_CTRL_STRM_ENA_SET2_SHIFT 2
-#define MPO_CTRL_STRM_ENA_SET2_MASK (MPO_CTRL_STRM_ENA_SET2_M << MPO_CTRL_STRM_ENA_SET2_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_CLR0_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_CLR0_SHIFT 24
-#define MPO_CTRL_STRM_CONTINUOUS_CLR0_MASK (MPO_CTRL_STRM_CONTINUOUS_CLR0_M << MPO_CTRL_STRM_CONTINUOUS_CLR0_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_CLR1_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_CLR1_SHIFT 25
-#define MPO_CTRL_STRM_CONTINUOUS_CLR1_MASK (MPO_CTRL_STRM_CONTINUOUS_CLR1_M << MPO_CTRL_STRM_CONTINUOUS_CLR1_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_CLR2_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_CLR2_SHIFT 26
-#define MPO_CTRL_STRM_CONTINUOUS_CLR2_MASK (MPO_CTRL_STRM_CONTINUOUS_CLR2_M << MPO_CTRL_STRM_CONTINUOUS_CLR2_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_CLR3_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_CLR3_SHIFT 27
-#define MPO_CTRL_STRM_CONTINUOUS_CLR3_MASK (MPO_CTRL_STRM_CONTINUOUS_CLR3_M << MPO_CTRL_STRM_CONTINUOUS_CLR3_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_CLR4_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_CLR4_SHIFT 28
-#define MPO_CTRL_STRM_CONTINUOUS_CLR4_MASK (MPO_CTRL_STRM_CONTINUOUS_CLR4_M << MPO_CTRL_STRM_CONTINUOUS_CLR4_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_CLR5_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_CLR5_SHIFT 29
-#define MPO_CTRL_STRM_CONTINUOUS_CLR5_MASK (MPO_CTRL_STRM_CONTINUOUS_CLR5_M << MPO_CTRL_STRM_CONTINUOUS_CLR5_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_SET3_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_SET3_SHIFT 19
-#define MPO_CTRL_STRM_CONTINUOUS_SET3_MASK (MPO_CTRL_STRM_CONTINUOUS_SET3_M << MPO_CTRL_STRM_CONTINUOUS_SET3_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_SET2_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_SET2_SHIFT 18
-#define MPO_CTRL_STRM_CONTINUOUS_SET2_MASK (MPO_CTRL_STRM_CONTINUOUS_SET2_M << MPO_CTRL_STRM_CONTINUOUS_SET2_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_SET1_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_SET1_SHIFT 17
-#define MPO_CTRL_STRM_CONTINUOUS_SET1_MASK (MPO_CTRL_STRM_CONTINUOUS_SET1_M << MPO_CTRL_STRM_CONTINUOUS_SET1_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_SET0_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_SET0_SHIFT 16
-#define MPO_CTRL_STRM_CONTINUOUS_SET0_MASK (MPO_CTRL_STRM_CONTINUOUS_SET0_M << MPO_CTRL_STRM_CONTINUOUS_SET0_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_SET7_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_SET7_SHIFT 23
-#define MPO_CTRL_STRM_CONTINUOUS_SET7_MASK (MPO_CTRL_STRM_CONTINUOUS_SET7_M << MPO_CTRL_STRM_CONTINUOUS_SET7_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_SET6_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_SET6_SHIFT 22
-#define MPO_CTRL_STRM_CONTINUOUS_SET6_MASK (MPO_CTRL_STRM_CONTINUOUS_SET6_M << MPO_CTRL_STRM_CONTINUOUS_SET6_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_SET5_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_SET5_SHIFT 21
-#define MPO_CTRL_STRM_CONTINUOUS_SET5_MASK (MPO_CTRL_STRM_CONTINUOUS_SET5_M << MPO_CTRL_STRM_CONTINUOUS_SET5_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_SET4_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_SET4_SHIFT 20
-#define MPO_CTRL_STRM_CONTINUOUS_SET4_MASK (MPO_CTRL_STRM_CONTINUOUS_SET4_M << MPO_CTRL_STRM_CONTINUOUS_SET4_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_CLR7_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_CLR7_SHIFT 31
-#define MPO_CTRL_STRM_CONTINUOUS_CLR7_MASK (MPO_CTRL_STRM_CONTINUOUS_CLR7_M << MPO_CTRL_STRM_CONTINUOUS_CLR7_SHIFT)
-#define MPO_CTRL_STRM_CONTINUOUS_CLR6_M 0x1ULL
-#define MPO_CTRL_STRM_CONTINUOUS_CLR6_SHIFT 30
-#define MPO_CTRL_STRM_CONTINUOUS_CLR6_MASK (MPO_CTRL_STRM_CONTINUOUS_CLR6_M << MPO_CTRL_STRM_CONTINUOUS_CLR6_SHIFT)
-#define MPO_ISR 0xd8
-#define MPO_ISR_DEF 0x0
-#define MPO_ISR_EOF6_M 0x1ULL
-#define MPO_ISR_EOF6_SHIFT 6
-#define MPO_ISR_EOF6_MASK (MPO_ISR_EOF6_M << MPO_ISR_EOF6_SHIFT)
-#define MPO_ISR_EOF7_M 0x1ULL
-#define MPO_ISR_EOF7_SHIFT 7
-#define MPO_ISR_EOF7_MASK (MPO_ISR_EOF7_M << MPO_ISR_EOF7_SHIFT)
-#define MPO_ISR_EOF4_M 0x1ULL
-#define MPO_ISR_EOF4_SHIFT 4
-#define MPO_ISR_EOF4_MASK (MPO_ISR_EOF4_M << MPO_ISR_EOF4_SHIFT)
-#define MPO_ISR_EOF5_M 0x1ULL
-#define MPO_ISR_EOF5_SHIFT 5
-#define MPO_ISR_EOF5_MASK (MPO_ISR_EOF5_M << MPO_ISR_EOF5_SHIFT)
-#define MPO_ISR_EOF2_M 0x1ULL
-#define MPO_ISR_EOF2_SHIFT 2
-#define MPO_ISR_EOF2_MASK (MPO_ISR_EOF2_M << MPO_ISR_EOF2_SHIFT)
-#define MPO_ISR_EOF3_M 0x1ULL
-#define MPO_ISR_EOF3_SHIFT 3
-#define MPO_ISR_EOF3_MASK (MPO_ISR_EOF3_M << MPO_ISR_EOF3_SHIFT)
-#define MPO_ISR_EOF0_M 0x1ULL
-#define MPO_ISR_EOF0_SHIFT 0
-#define MPO_ISR_EOF0_MASK (MPO_ISR_EOF0_M << MPO_ISR_EOF0_SHIFT)
-#define MPO_ISR_EOF1_M 0x1ULL
-#define MPO_ISR_EOF1_SHIFT 1
-#define MPO_ISR_EOF1_MASK (MPO_ISR_EOF1_M << MPO_ISR_EOF1_SHIFT)
-#define MPO_ITR 0xe0
-#define MPO_ITR_DEF 0x0
-#define MPO_ITR_EOF1_M 0x1ULL
-#define MPO_ITR_EOF1_SHIFT 1
-#define MPO_ITR_EOF1_MASK (MPO_ITR_EOF1_M << MPO_ITR_EOF1_SHIFT)
-#define MPO_ITR_EOF0_M 0x1ULL
-#define MPO_ITR_EOF0_SHIFT 0
-#define MPO_ITR_EOF0_MASK (MPO_ITR_EOF0_M << MPO_ITR_EOF0_SHIFT)
-#define MPO_ITR_EOF3_M 0x1ULL
-#define MPO_ITR_EOF3_SHIFT 3
-#define MPO_ITR_EOF3_MASK (MPO_ITR_EOF3_M << MPO_ITR_EOF3_SHIFT)
-#define MPO_ITR_EOF2_M 0x1ULL
-#define MPO_ITR_EOF2_SHIFT 2
-#define MPO_ITR_EOF2_MASK (MPO_ITR_EOF2_M << MPO_ITR_EOF2_SHIFT)
-#define MPO_ITR_EOF5_M 0x1ULL
-#define MPO_ITR_EOF5_SHIFT 5
-#define MPO_ITR_EOF5_MASK (MPO_ITR_EOF5_M << MPO_ITR_EOF5_SHIFT)
-#define MPO_ITR_EOF4_M 0x1ULL
-#define MPO_ITR_EOF4_SHIFT 4
-#define MPO_ITR_EOF4_MASK (MPO_ITR_EOF4_M << MPO_ITR_EOF4_SHIFT)
-#define MPO_ITR_EOF7_M 0x1ULL
-#define MPO_ITR_EOF7_SHIFT 7
-#define MPO_ITR_EOF7_MASK (MPO_ITR_EOF7_M << MPO_ITR_EOF7_SHIFT)
-#define MPO_ITR_EOF6_M 0x1ULL
-#define MPO_ITR_EOF6_SHIFT 6
-#define MPO_ITR_EOF6_MASK (MPO_ITR_EOF6_M << MPO_ITR_EOF6_SHIFT)
-#define MPO_IER 0xe8
-#define MPO_IER_DEF 0xff
-#define MPO_IER_EOF4_M 0x1ULL
-#define MPO_IER_EOF4_SHIFT 4
-#define MPO_IER_EOF4_MASK (MPO_IER_EOF4_M << MPO_IER_EOF4_SHIFT)
-#define MPO_IER_EOF5_M 0x1ULL
-#define MPO_IER_EOF5_SHIFT 5
-#define MPO_IER_EOF5_MASK (MPO_IER_EOF5_M << MPO_IER_EOF5_SHIFT)
-#define MPO_IER_EOF6_M 0x1ULL
-#define MPO_IER_EOF6_SHIFT 6
-#define MPO_IER_EOF6_MASK (MPO_IER_EOF6_M << MPO_IER_EOF6_SHIFT)
-#define MPO_IER_EOF7_M 0x1ULL
-#define MPO_IER_EOF7_SHIFT 7
-#define MPO_IER_EOF7_MASK (MPO_IER_EOF7_M << MPO_IER_EOF7_SHIFT)
-#define MPO_IER_EOF0_M 0x1ULL
-#define MPO_IER_EOF0_SHIFT 0
-#define MPO_IER_EOF0_MASK (MPO_IER_EOF0_M << MPO_IER_EOF0_SHIFT)
-#define MPO_IER_EOF1_M 0x1ULL
-#define MPO_IER_EOF1_SHIFT 1
-#define MPO_IER_EOF1_MASK (MPO_IER_EOF1_M << MPO_IER_EOF1_SHIFT)
-#define MPO_IER_EOF2_M 0x1ULL
-#define MPO_IER_EOF2_SHIFT 2
-#define MPO_IER_EOF2_MASK (MPO_IER_EOF2_M << MPO_IER_EOF2_SHIFT)
-#define MPO_IER_EOF3_M 0x1ULL
-#define MPO_IER_EOF3_SHIFT 3
-#define MPO_IER_EOF3_MASK (MPO_IER_EOF3_M << MPO_IER_EOF3_SHIFT)
-#define MPO_IMR 0xf0
-#define MPO_IMR_DEF 0x0
-#define MPO_IMR_EOF4_M 0x1ULL
-#define MPO_IMR_EOF4_SHIFT 4
-#define MPO_IMR_EOF4_MASK (MPO_IMR_EOF4_M << MPO_IMR_EOF4_SHIFT)
-#define MPO_IMR_EOF5_M 0x1ULL
-#define MPO_IMR_EOF5_SHIFT 5
-#define MPO_IMR_EOF5_MASK (MPO_IMR_EOF5_M << MPO_IMR_EOF5_SHIFT)
-#define MPO_IMR_EOF6_M 0x1ULL
-#define MPO_IMR_EOF6_SHIFT 6
-#define MPO_IMR_EOF6_MASK (MPO_IMR_EOF6_M << MPO_IMR_EOF6_SHIFT)
-#define MPO_IMR_EOF7_M 0x1ULL
-#define MPO_IMR_EOF7_SHIFT 7
-#define MPO_IMR_EOF7_MASK (MPO_IMR_EOF7_M << MPO_IMR_EOF7_SHIFT)
-#define MPO_IMR_EOF0_M 0x1ULL
-#define MPO_IMR_EOF0_SHIFT 0
-#define MPO_IMR_EOF0_MASK (MPO_IMR_EOF0_M << MPO_IMR_EOF0_SHIFT)
-#define MPO_IMR_EOF1_M 0x1ULL
-#define MPO_IMR_EOF1_SHIFT 1
-#define MPO_IMR_EOF1_MASK (MPO_IMR_EOF1_M << MPO_IMR_EOF1_SHIFT)
-#define MPO_IMR_EOF2_M 0x1ULL
-#define MPO_IMR_EOF2_SHIFT 2
-#define MPO_IMR_EOF2_MASK (MPO_IMR_EOF2_M << MPO_IMR_EOF2_SHIFT)
-#define MPO_IMR_EOF3_M 0x1ULL
-#define MPO_IMR_EOF3_SHIFT 3
-#define MPO_IMR_EOF3_MASK (MPO_IMR_EOF3_M << MPO_IMR_EOF3_SHIFT)
-#define MPO_ISR_OVF 0xf8
-#define MPO_ISR_OVF_DEF 0x0
-#define MPO_ISR_OVF_EOF0_M 0x1ULL
-#define MPO_ISR_OVF_EOF0_SHIFT 0
-#define MPO_ISR_OVF_EOF0_MASK (MPO_ISR_OVF_EOF0_M << MPO_ISR_OVF_EOF0_SHIFT)
-#define MPO_ISR_OVF_EOF1_M 0x1ULL
-#define MPO_ISR_OVF_EOF1_SHIFT 1
-#define MPO_ISR_OVF_EOF1_MASK (MPO_ISR_OVF_EOF1_M << MPO_ISR_OVF_EOF1_SHIFT)
-#define MPO_ISR_OVF_EOF2_M 0x1ULL
-#define MPO_ISR_OVF_EOF2_SHIFT 2
-#define MPO_ISR_OVF_EOF2_MASK (MPO_ISR_OVF_EOF2_M << MPO_ISR_OVF_EOF2_SHIFT)
-#define MPO_ISR_OVF_EOF3_M 0x1ULL
-#define MPO_ISR_OVF_EOF3_SHIFT 3
-#define MPO_ISR_OVF_EOF3_MASK (MPO_ISR_OVF_EOF3_M << MPO_ISR_OVF_EOF3_SHIFT)
-#define MPO_ISR_OVF_EOF4_M 0x1ULL
-#define MPO_ISR_OVF_EOF4_SHIFT 4
-#define MPO_ISR_OVF_EOF4_MASK (MPO_ISR_OVF_EOF4_M << MPO_ISR_OVF_EOF4_SHIFT)
-#define MPO_ISR_OVF_EOF5_M 0x1ULL
-#define MPO_ISR_OVF_EOF5_SHIFT 5
-#define MPO_ISR_OVF_EOF5_MASK (MPO_ISR_OVF_EOF5_M << MPO_ISR_OVF_EOF5_SHIFT)
-#define MPO_ISR_OVF_EOF6_M 0x1ULL
-#define MPO_ISR_OVF_EOF6_SHIFT 6
-#define MPO_ISR_OVF_EOF6_MASK (MPO_ISR_OVF_EOF6_M << MPO_ISR_OVF_EOF6_SHIFT)
-#define MPO_ISR_OVF_EOF7_M 0x1ULL
-#define MPO_ISR_OVF_EOF7_SHIFT 7
-#define MPO_ISR_OVF_EOF7_MASK (MPO_ISR_OVF_EOF7_M << MPO_ISR_OVF_EOF7_SHIFT)
-#define MPO_STATUS 0x100
-#define MPO_STATUS_DEF 0xff
-#define MPO_STATUS_STRM_IDLE_M 0xffULL
-#define MPO_STATUS_STRM_IDLE_SHIFT 0
-#define MPO_STATUS_STRM_IDLE_MASK (MPO_STATUS_STRM_IDLE_M << MPO_STATUS_STRM_IDLE_SHIFT)
-#define MPO_STRM_SEL 0x108
-#define MPO_STRM_SEL_DEF 0xf
-#define MPO_STRM_SEL_MPO_STRM_SEL_M 0xfULL
-#define MPO_STRM_SEL_MPO_STRM_SEL_SHIFT 0
-#define MPO_STRM_SEL_MPO_STRM_SEL_MASK (MPO_STRM_SEL_MPO_STRM_SEL_M << MPO_STRM_SEL_MPO_STRM_SEL_SHIFT)
-#define MPO_STRM_CTRL 0x110
-#define MPO_STRM_CTRL_DEF 0x2
-#define MPO_STRM_CTRL_RSYNC_EN_M 0x1ULL
-#define MPO_STRM_CTRL_RSYNC_EN_SHIFT 1
-#define MPO_STRM_CTRL_RSYNC_EN_MASK (MPO_STRM_CTRL_RSYNC_EN_M << MPO_STRM_CTRL_RSYNC_EN_SHIFT)
-#define MPO_STRM_CTRL_RST_M 0x1ULL
-#define MPO_STRM_CTRL_RST_SHIFT 3
-#define MPO_STRM_CTRL_RST_MASK (MPO_STRM_CTRL_RST_M << MPO_STRM_CTRL_RST_SHIFT)
-#define MPO_STRM_CTRL_CLEANUP_M 0x1ULL
-#define MPO_STRM_CTRL_CLEANUP_SHIFT 2
-#define MPO_STRM_CTRL_CLEANUP_MASK (MPO_STRM_CTRL_CLEANUP_M << MPO_STRM_CTRL_CLEANUP_SHIFT)
-#define MPO_STRM_CNFG0 0x118
-#define MPO_STRM_CNFG0_DEF 0x1e002800003baa0
-#define MPO_STRM_CNFG0_IMG_WIDTH_M 0xffffULL
-#define MPO_STRM_CNFG0_IMG_WIDTH_SHIFT 32
-#define MPO_STRM_CNFG0_IMG_WIDTH_MASK (MPO_STRM_CNFG0_IMG_WIDTH_M << MPO_STRM_CNFG0_IMG_WIDTH_SHIFT)
-#define MPO_STRM_CNFG0_IMG_HEIGHT_M 0xffffULL
-#define MPO_STRM_CNFG0_IMG_HEIGHT_SHIFT 48
-#define MPO_STRM_CNFG0_IMG_HEIGHT_MASK (MPO_STRM_CNFG0_IMG_HEIGHT_M << MPO_STRM_CNFG0_IMG_HEIGHT_SHIFT)
-#define MPO_STRM_CNFG0_STRP_HEIGHT_M 0x3fULL
-#define MPO_STRM_CNFG0_STRP_HEIGHT_SHIFT 16
-#define MPO_STRM_CNFG0_STRP_HEIGHT_MASK (MPO_STRM_CNFG0_STRP_HEIGHT_M << MPO_STRM_CNFG0_STRP_HEIGHT_SHIFT)
-#define MPO_STRM_CNFG0_DT_OUT_M 0x3fULL
-#define MPO_STRM_CNFG0_DT_OUT_SHIFT 4
-#define MPO_STRM_CNFG0_DT_OUT_MASK (MPO_STRM_CNFG0_DT_OUT_M << MPO_STRM_CNFG0_DT_OUT_SHIFT)
-#define MPO_STRM_CNFG0_DT_PROC_M 0x3fULL
-#define MPO_STRM_CNFG0_DT_PROC_SHIFT 10
-#define MPO_STRM_CNFG0_DT_PROC_MASK (MPO_STRM_CNFG0_DT_PROC_M << MPO_STRM_CNFG0_DT_PROC_SHIFT)
-#define MPO_STRM_CNFG0_VC_M 0x3ULL
-#define MPO_STRM_CNFG0_VC_SHIFT 0
-#define MPO_STRM_CNFG0_VC_MASK (MPO_STRM_CNFG0_VC_M << MPO_STRM_CNFG0_VC_SHIFT)
-#define MPO_STRM_CNFG1 0x120
-#define MPO_STRM_CNFG1_DEF 0x1000020000
-#define MPO_STRM_CNFG1_SEGS_PER_ROW_M 0x7fULL
-#define MPO_STRM_CNFG1_SEGS_PER_ROW_SHIFT 16
-#define MPO_STRM_CNFG1_SEGS_PER_ROW_MASK (MPO_STRM_CNFG1_SEGS_PER_ROW_M << MPO_STRM_CNFG1_SEGS_PER_ROW_SHIFT)
-#define MPO_STRM_CNFG1_ORDER_M 0x3ULL
-#define MPO_STRM_CNFG1_ORDER_SHIFT 32
-#define MPO_STRM_CNFG1_ORDER_MASK (MPO_STRM_CNFG1_ORDER_M << MPO_STRM_CNFG1_ORDER_SHIFT)
-#define MPO_STRM_CNFG1_SEG_START_M 0x7fULL
-#define MPO_STRM_CNFG1_SEG_START_SHIFT 0
-#define MPO_STRM_CNFG1_SEG_START_MASK (MPO_STRM_CNFG1_SEG_START_M << MPO_STRM_CNFG1_SEG_START_SHIFT)
-#define MPO_STRM_CNFG1_RATIO_M 0x3fULL
-#define MPO_STRM_CNFG1_RATIO_SHIFT 36
-#define MPO_STRM_CNFG1_RATIO_MASK (MPO_STRM_CNFG1_RATIO_M << MPO_STRM_CNFG1_RATIO_SHIFT)
-#define MPO_STRM_CNFG0_RO 0x128
-#define MPO_STRM_CNFG0_RO_DEF 0x1e002800003baa0
-#define MPO_STRM_CNFG0_RO_DT_PROC_M 0x3fULL
-#define MPO_STRM_CNFG0_RO_DT_PROC_SHIFT 10
-#define MPO_STRM_CNFG0_RO_DT_PROC_MASK (MPO_STRM_CNFG0_RO_DT_PROC_M << MPO_STRM_CNFG0_RO_DT_PROC_SHIFT)
-#define MPO_STRM_CNFG0_RO_IMG_HEIGHT_M 0xffffULL
-#define MPO_STRM_CNFG0_RO_IMG_HEIGHT_SHIFT 48
-#define MPO_STRM_CNFG0_RO_IMG_HEIGHT_MASK (MPO_STRM_CNFG0_RO_IMG_HEIGHT_M << MPO_STRM_CNFG0_RO_IMG_HEIGHT_SHIFT)
-#define MPO_STRM_CNFG0_RO_DT_OUT_M 0x3fULL
-#define MPO_STRM_CNFG0_RO_DT_OUT_SHIFT 4
-#define MPO_STRM_CNFG0_RO_DT_OUT_MASK (MPO_STRM_CNFG0_RO_DT_OUT_M << MPO_STRM_CNFG0_RO_DT_OUT_SHIFT)
-#define MPO_STRM_CNFG0_RO_IMG_WIDTH_M 0xffffULL
-#define MPO_STRM_CNFG0_RO_IMG_WIDTH_SHIFT 32
-#define MPO_STRM_CNFG0_RO_IMG_WIDTH_MASK (MPO_STRM_CNFG0_RO_IMG_WIDTH_M << MPO_STRM_CNFG0_RO_IMG_WIDTH_SHIFT)
-#define MPO_STRM_CNFG0_RO_STRP_HEIGHT_M 0x3fULL
-#define MPO_STRM_CNFG0_RO_STRP_HEIGHT_SHIFT 16
-#define MPO_STRM_CNFG0_RO_STRP_HEIGHT_MASK (MPO_STRM_CNFG0_RO_STRP_HEIGHT_M << MPO_STRM_CNFG0_RO_STRP_HEIGHT_SHIFT)
-#define MPO_STRM_CNFG0_RO_VC_M 0x3ULL
-#define MPO_STRM_CNFG0_RO_VC_SHIFT 0
-#define MPO_STRM_CNFG0_RO_VC_MASK (MPO_STRM_CNFG0_RO_VC_M << MPO_STRM_CNFG0_RO_VC_SHIFT)
-#define MPO_STRM_CNFG1_RO 0x130
-#define MPO_STRM_CNFG1_RO_DEF 0x1000020000
-#define MPO_STRM_CNFG1_RO_SEG_START_M 0x7fULL
-#define MPO_STRM_CNFG1_RO_SEG_START_SHIFT 0
-#define MPO_STRM_CNFG1_RO_SEG_START_MASK (MPO_STRM_CNFG1_RO_SEG_START_M << MPO_STRM_CNFG1_RO_SEG_START_SHIFT)
-#define MPO_STRM_CNFG1_RO_RATIO_M 0x3fULL
-#define MPO_STRM_CNFG1_RO_RATIO_SHIFT 36
-#define MPO_STRM_CNFG1_RO_RATIO_MASK (MPO_STRM_CNFG1_RO_RATIO_M << MPO_STRM_CNFG1_RO_RATIO_SHIFT)
-#define MPO_STRM_CNFG1_RO_SEGS_PER_ROW_M 0x7fULL
-#define MPO_STRM_CNFG1_RO_SEGS_PER_ROW_SHIFT 16
-#define MPO_STRM_CNFG1_RO_SEGS_PER_ROW_MASK (MPO_STRM_CNFG1_RO_SEGS_PER_ROW_M << MPO_STRM_CNFG1_RO_SEGS_PER_ROW_SHIFT)
-#define MPO_STRM_CNFG1_RO_ORDER_M 0x3ULL
-#define MPO_STRM_CNFG1_RO_ORDER_SHIFT 32
-#define MPO_STRM_CNFG1_RO_ORDER_MASK (MPO_STRM_CNFG1_RO_ORDER_M << MPO_STRM_CNFG1_RO_ORDER_SHIFT)
-#define SSP_STATUS 0x138
-#define SSP_STATUS_DEF 0x200
-#define SSP_STATUS_SEG_AVAIL_M 0x3ffULL
-#define SSP_STATUS_SEG_AVAIL_SHIFT 0
-#define SSP_STATUS_SEG_AVAIL_MASK (SSP_STATUS_SEG_AVAIL_M << SSP_STATUS_SEG_AVAIL_SHIFT)
-#define MIF_SPARE 0x140
-#define MIF_SPARE_DEF 0x0
-#define MIF_SPARE_SPARE8_M 0x1ULL
-#define MIF_SPARE_SPARE8_SHIFT 8
-#define MIF_SPARE_SPARE8_MASK (MIF_SPARE_SPARE8_M << MIF_SPARE_SPARE8_SHIFT)
-#define MIF_SPARE_SPARE9_M 0x1ULL
-#define MIF_SPARE_SPARE9_SHIFT 9
-#define MIF_SPARE_SPARE9_MASK (MIF_SPARE_SPARE9_M << MIF_SPARE_SPARE9_SHIFT)
-#define MIF_SPARE_SPARE0_M 0x1ULL
-#define MIF_SPARE_SPARE0_SHIFT 0
-#define MIF_SPARE_SPARE0_MASK (MIF_SPARE_SPARE0_M << MIF_SPARE_SPARE0_SHIFT)
-#define MIF_SPARE_SPARE1_M 0x1ULL
-#define MIF_SPARE_SPARE1_SHIFT 1
-#define MIF_SPARE_SPARE1_MASK (MIF_SPARE_SPARE1_M << MIF_SPARE_SPARE1_SHIFT)
-#define MIF_SPARE_SPARE2_M 0x1ULL
-#define MIF_SPARE_SPARE2_SHIFT 2
-#define MIF_SPARE_SPARE2_MASK (MIF_SPARE_SPARE2_M << MIF_SPARE_SPARE2_SHIFT)
-#define MIF_SPARE_SPARE3_M 0x1ULL
-#define MIF_SPARE_SPARE3_SHIFT 3
-#define MIF_SPARE_SPARE3_MASK (MIF_SPARE_SPARE3_M << MIF_SPARE_SPARE3_SHIFT)
-#define MIF_SPARE_SPARE4_M 0x1ULL
-#define MIF_SPARE_SPARE4_SHIFT 4
-#define MIF_SPARE_SPARE4_MASK (MIF_SPARE_SPARE4_M << MIF_SPARE_SPARE4_SHIFT)
-#define MIF_SPARE_SPARE5_M 0x1ULL
-#define MIF_SPARE_SPARE5_SHIFT 5
-#define MIF_SPARE_SPARE5_MASK (MIF_SPARE_SPARE5_M << MIF_SPARE_SPARE5_SHIFT)
-#define MIF_SPARE_SPARE6_M 0x1ULL
-#define MIF_SPARE_SPARE6_SHIFT 6
-#define MIF_SPARE_SPARE6_MASK (MIF_SPARE_SPARE6_M << MIF_SPARE_SPARE6_SHIFT)
-#define MIF_SPARE_SPARE7_M 0x1ULL
-#define MIF_SPARE_SPARE7_SHIFT 7
-#define MIF_SPARE_SPARE7_MASK (MIF_SPARE_SPARE7_M << MIF_SPARE_SPARE7_SHIFT)
-#define MIF_SPARE_SPARE12_M 0x1ULL
-#define MIF_SPARE_SPARE12_SHIFT 12
-#define MIF_SPARE_SPARE12_MASK (MIF_SPARE_SPARE12_M << MIF_SPARE_SPARE12_SHIFT)
-#define MIF_SPARE_SPARE13_M 0x1ULL
-#define MIF_SPARE_SPARE13_SHIFT 13
-#define MIF_SPARE_SPARE13_MASK (MIF_SPARE_SPARE13_M << MIF_SPARE_SPARE13_SHIFT)
-#define MIF_SPARE_SPARE10_M 0x1ULL
-#define MIF_SPARE_SPARE10_SHIFT 10
-#define MIF_SPARE_SPARE10_MASK (MIF_SPARE_SPARE10_M << MIF_SPARE_SPARE10_SHIFT)
-#define MIF_SPARE_SPARE11_M 0x1ULL
-#define MIF_SPARE_SPARE11_SHIFT 11
-#define MIF_SPARE_SPARE11_MASK (MIF_SPARE_SPARE11_M << MIF_SPARE_SPARE11_SHIFT)
-#define MIF_SPARE_SPARE16_M 0x1ULL
-#define MIF_SPARE_SPARE16_SHIFT 16
-#define MIF_SPARE_SPARE16_MASK (MIF_SPARE_SPARE16_M << MIF_SPARE_SPARE16_SHIFT)
-#define MIF_SPARE_SPARE17_M 0x1ULL
-#define MIF_SPARE_SPARE17_SHIFT 17
-#define MIF_SPARE_SPARE17_MASK (MIF_SPARE_SPARE17_M << MIF_SPARE_SPARE17_SHIFT)
-#define MIF_SPARE_SPARE14_M 0x1ULL
-#define MIF_SPARE_SPARE14_SHIFT 14
-#define MIF_SPARE_SPARE14_MASK (MIF_SPARE_SPARE14_M << MIF_SPARE_SPARE14_SHIFT)
-#define MIF_SPARE_SPARE15_M 0x1ULL
-#define MIF_SPARE_SPARE15_SHIFT 15
-#define MIF_SPARE_SPARE15_MASK (MIF_SPARE_SPARE15_M << MIF_SPARE_SPARE15_SHIFT)
-#define MIF_SPARE_SPARE18_M 0x1ULL
-#define MIF_SPARE_SPARE18_SHIFT 18
-#define MIF_SPARE_SPARE18_MASK (MIF_SPARE_SPARE18_M << MIF_SPARE_SPARE18_SHIFT)
-#define MIF_SPARE_SPARE19_M 0x1ULL
-#define MIF_SPARE_SPARE19_SHIFT 19
-#define MIF_SPARE_SPARE19_MASK (MIF_SPARE_SPARE19_M << MIF_SPARE_SPARE19_SHIFT)
-#define MIF_SPARE_SPARE30_M 0x1ULL
-#define MIF_SPARE_SPARE30_SHIFT 30
-#define MIF_SPARE_SPARE30_MASK (MIF_SPARE_SPARE30_M << MIF_SPARE_SPARE30_SHIFT)
-#define MIF_SPARE_SPARE31_M 0x1ULL
-#define MIF_SPARE_SPARE31_SHIFT 31
-#define MIF_SPARE_SPARE31_MASK (MIF_SPARE_SPARE31_M << MIF_SPARE_SPARE31_SHIFT)
-#define MIF_SPARE_SPARE29_M 0x1ULL
-#define MIF_SPARE_SPARE29_SHIFT 29
-#define MIF_SPARE_SPARE29_MASK (MIF_SPARE_SPARE29_M << MIF_SPARE_SPARE29_SHIFT)
-#define MIF_SPARE_SPARE28_M 0x1ULL
-#define MIF_SPARE_SPARE28_SHIFT 28
-#define MIF_SPARE_SPARE28_MASK (MIF_SPARE_SPARE28_M << MIF_SPARE_SPARE28_SHIFT)
-#define MIF_SPARE_SPARE23_M 0x1ULL
-#define MIF_SPARE_SPARE23_SHIFT 23
-#define MIF_SPARE_SPARE23_MASK (MIF_SPARE_SPARE23_M << MIF_SPARE_SPARE23_SHIFT)
-#define MIF_SPARE_SPARE22_M 0x1ULL
-#define MIF_SPARE_SPARE22_SHIFT 22
-#define MIF_SPARE_SPARE22_MASK (MIF_SPARE_SPARE22_M << MIF_SPARE_SPARE22_SHIFT)
-#define MIF_SPARE_SPARE21_M 0x1ULL
-#define MIF_SPARE_SPARE21_SHIFT 21
-#define MIF_SPARE_SPARE21_MASK (MIF_SPARE_SPARE21_M << MIF_SPARE_SPARE21_SHIFT)
-#define MIF_SPARE_SPARE20_M 0x1ULL
-#define MIF_SPARE_SPARE20_SHIFT 20
-#define MIF_SPARE_SPARE20_MASK (MIF_SPARE_SPARE20_M << MIF_SPARE_SPARE20_SHIFT)
-#define MIF_SPARE_SPARE27_M 0x1ULL
-#define MIF_SPARE_SPARE27_SHIFT 27
-#define MIF_SPARE_SPARE27_MASK (MIF_SPARE_SPARE27_M << MIF_SPARE_SPARE27_SHIFT)
-#define MIF_SPARE_SPARE26_M 0x1ULL
-#define MIF_SPARE_SPARE26_SHIFT 26
-#define MIF_SPARE_SPARE26_MASK (MIF_SPARE_SPARE26_M << MIF_SPARE_SPARE26_SHIFT)
-#define MIF_SPARE_SPARE25_M 0x1ULL
-#define MIF_SPARE_SPARE25_SHIFT 25
-#define MIF_SPARE_SPARE25_MASK (MIF_SPARE_SPARE25_M << MIF_SPARE_SPARE25_SHIFT)
-#define MIF_SPARE_SPARE24_M 0x1ULL
-#define MIF_SPARE_SPARE24_SHIFT 24
-#define MIF_SPARE_SPARE24_MASK (MIF_SPARE_SPARE24_M << MIF_SPARE_SPARE24_SHIFT)
-
-/* Module : IPU_LIB_DREGFILE_STP*/
-#define STP_SEL 0x0
-#define STP_SEL_DEF 0xf
-#define STP_SEL_STP_SEL_M 0xfULL
-#define STP_SEL_STP_SEL_SHIFT 0
-#define STP_SEL_STP_SEL_MASK (STP_SEL_STP_SEL_M << STP_SEL_STP_SEL_SHIFT)
-#define STP_CTRL 0x8
-#define STP_CTRL_DEF 0x0
-#define STP_CTRL_TS_FR_M 0x1ULL
-#define STP_CTRL_TS_FR_SHIFT 4
-#define STP_CTRL_TS_FR_MASK (STP_CTRL_TS_FR_M << STP_CTRL_TS_FR_SHIFT)
-#define STP_CTRL_ENA_M 0x1ULL
-#define STP_CTRL_ENA_SHIFT 0
-#define STP_CTRL_ENA_MASK (STP_CTRL_ENA_M << STP_CTRL_ENA_SHIFT)
-#define STP_CTRL_RESUME_M 0x1ULL
-#define STP_CTRL_RESUME_SHIFT 2
-#define STP_CTRL_RESUME_MASK (STP_CTRL_RESUME_M << STP_CTRL_RESUME_SHIFT)
-#define STP_CTRL_RESET_M 0x1ULL
-#define STP_CTRL_RESET_SHIFT 1
-#define STP_CTRL_RESET_MASK (STP_CTRL_RESET_M << STP_CTRL_RESET_SHIFT)
-#define STP_CTRL_PC_FR_M 0x1ULL
-#define STP_CTRL_PC_FR_SHIFT 3
-#define STP_CTRL_PC_FR_MASK (STP_CTRL_PC_FR_M << STP_CTRL_PC_FR_SHIFT)
-#define STP_START 0x10
-#define STP_START_DEF 0x0
-#define STP_START_START_INST_M 0x7ffULL
-#define STP_START_START_INST_SHIFT 0
-#define STP_START_START_INST_MASK (STP_START_START_INST_M << STP_START_START_INST_SHIFT)
-#define STP_MASK 0x18
-#define STP_MASK_DEF 0x1ff
-#define STP_MASK_LBP_MASK_M 0x1ffULL
-#define STP_MASK_LBP_MASK_SHIFT 0
-#define STP_MASK_LBP_MASK_MASK (STP_MASK_LBP_MASK_M << STP_MASK_LBP_MASK_SHIFT)
-#define STP_STAT 0x20
-#define STP_STAT_DEF 0x0
-#define STP_STAT_PC_M 0x7ffULL
-#define STP_STAT_PC_SHIFT 0
-#define STP_STAT_PC_MASK (STP_STAT_PC_M << STP_STAT_PC_SHIFT)
-#define STP_STAT_STALLED_M 0x1ULL
-#define STP_STAT_STALLED_SHIFT 16
-#define STP_STAT_STALLED_MASK (STP_STAT_STALLED_M << STP_STAT_STALLED_SHIFT)
-#define STP_CAP 0x28
-#define STP_CAP_DEF 0x4080040004000800
-#define STP_CAP_HALO_MEM_M 0xffULL
-#define STP_CAP_HALO_MEM_SHIFT 56
-#define STP_CAP_HALO_MEM_MASK (STP_CAP_HALO_MEM_M << STP_CAP_HALO_MEM_SHIFT)
-#define STP_CAP_SCALAR_MEM_M 0xffffULL
-#define STP_CAP_SCALAR_MEM_SHIFT 16
-#define STP_CAP_SCALAR_MEM_MASK (STP_CAP_SCALAR_MEM_M << STP_CAP_SCALAR_MEM_SHIFT)
-#define STP_CAP_CONST_MEM_M 0xffffULL
-#define STP_CAP_CONST_MEM_SHIFT 32
-#define STP_CAP_CONST_MEM_MASK (STP_CAP_CONST_MEM_M << STP_CAP_CONST_MEM_SHIFT)
-#define STP_CAP_INST_MEM_M 0xffffULL
-#define STP_CAP_INST_MEM_SHIFT 0
-#define STP_CAP_INST_MEM_MASK (STP_CAP_INST_MEM_M << STP_CAP_INST_MEM_SHIFT)
-#define STP_CAP_VECTOR_MEM_M 0xffULL
-#define STP_CAP_VECTOR_MEM_SHIFT 48
-#define STP_CAP_VECTOR_MEM_MASK (STP_CAP_VECTOR_MEM_M << STP_CAP_VECTOR_MEM_SHIFT)
-#define STP_ISR 0x30
-#define STP_ISR_DEF 0x0
-#define STP_ISR_INT_M 0x1ULL
-#define STP_ISR_INT_SHIFT 0
-#define STP_ISR_INT_MASK (STP_ISR_INT_M << STP_ISR_INT_SHIFT)
-#define STP_ISR_ERR_M 0x1ULL
-#define STP_ISR_ERR_SHIFT 1
-#define STP_ISR_ERR_MASK (STP_ISR_ERR_M << STP_ISR_ERR_SHIFT)
-#define STP_ITR 0x38
-#define STP_ITR_DEF 0x0
-#define STP_ITR_ERR_M 0x1ULL
-#define STP_ITR_ERR_SHIFT 1
-#define STP_ITR_ERR_MASK (STP_ITR_ERR_M << STP_ITR_ERR_SHIFT)
-#define STP_ITR_INT_M 0x1ULL
-#define STP_ITR_INT_SHIFT 0
-#define STP_ITR_INT_MASK (STP_ITR_INT_M << STP_ITR_INT_SHIFT)
-#define STP_IER 0x40
-#define STP_IER_DEF 0x3
-#define STP_IER_ERR_M 0x1ULL
-#define STP_IER_ERR_SHIFT 1
-#define STP_IER_ERR_MASK (STP_IER_ERR_M << STP_IER_ERR_SHIFT)
-#define STP_IER_INT_M 0x1ULL
-#define STP_IER_INT_SHIFT 0
-#define STP_IER_INT_MASK (STP_IER_INT_M << STP_IER_INT_SHIFT)
-#define STP_IMR 0x48
-#define STP_IMR_DEF 0x0
-#define STP_IMR_ERR_M 0x1ULL
-#define STP_IMR_ERR_SHIFT 1
-#define STP_IMR_ERR_MASK (STP_IMR_ERR_M << STP_IMR_ERR_SHIFT)
-#define STP_IMR_INT_M 0x1ULL
-#define STP_IMR_INT_SHIFT 0
-#define STP_IMR_INT_MASK (STP_IMR_INT_M << STP_IMR_INT_SHIFT)
-#define STP_ISR_OVF 0x50
-#define STP_ISR_OVF_DEF 0x0
-#define STP_ISR_OVF_ERR_M 0x1ULL
-#define STP_ISR_OVF_ERR_SHIFT 1
-#define STP_ISR_OVF_ERR_MASK (STP_ISR_OVF_ERR_M << STP_ISR_OVF_ERR_SHIFT)
-#define STP_ISR_OVF_INT_M 0x1ULL
-#define STP_ISR_OVF_INT_SHIFT 0
-#define STP_ISR_OVF_INT_MASK (STP_ISR_OVF_INT_M << STP_ISR_OVF_INT_SHIFT)
-#define STP_IRQ_LOG 0x58
-#define STP_IRQ_LOG_DEF 0x0
-#define STP_IRQ_LOG_CODE_M 0xffffULL
-#define STP_IRQ_LOG_CODE_SHIFT 0
-#define STP_IRQ_LOG_CODE_MASK (STP_IRQ_LOG_CODE_M << STP_IRQ_LOG_CODE_SHIFT)
-#define STP_ERR_LOG 0x60
-#define STP_ERR_LOG_DEF 0x0
-#define STP_ERR_LOG_LBP_ID_M 0xfULL
-#define STP_ERR_LOG_LBP_ID_SHIFT 0
-#define STP_ERR_LOG_LBP_ID_MASK (STP_ERR_LOG_LBP_ID_M << STP_ERR_LOG_LBP_ID_SHIFT)
-#define STP_RAM_CTRL 0x68
-#define STP_RAM_CTRL_DEF 0x0
-#define STP_RAM_CTRL_RAM_TARG_M 0xfULL
-#define STP_RAM_CTRL_RAM_TARG_SHIFT 8
-#define STP_RAM_CTRL_RAM_TARG_MASK (STP_RAM_CTRL_RAM_TARG_M << STP_RAM_CTRL_RAM_TARG_SHIFT)
-#define STP_RAM_CTRL_WRITE_M 0x1ULL
-#define STP_RAM_CTRL_WRITE_SHIFT 1
-#define STP_RAM_CTRL_WRITE_MASK (STP_RAM_CTRL_WRITE_M << STP_RAM_CTRL_WRITE_SHIFT)
-#define STP_RAM_CTRL_RAM_ADDR_M 0xffffULL
-#define STP_RAM_CTRL_RAM_ADDR_SHIFT 16
-#define STP_RAM_CTRL_RAM_ADDR_MASK (STP_RAM_CTRL_RAM_ADDR_M << STP_RAM_CTRL_RAM_ADDR_SHIFT)
-#define STP_RAM_CTRL_RUN_M 0x1ULL
-#define STP_RAM_CTRL_RUN_SHIFT 0
-#define STP_RAM_CTRL_RUN_MASK (STP_RAM_CTRL_RUN_M << STP_RAM_CTRL_RUN_SHIFT)
-#define STP_RAM_CTRL_PRI_M 0x1ULL
-#define STP_RAM_CTRL_PRI_SHIFT 2
-#define STP_RAM_CTRL_PRI_MASK (STP_RAM_CTRL_PRI_M << STP_RAM_CTRL_PRI_SHIFT)
-#define STP_RAM_DATA0 0x70
-#define STP_RAM_DATA0_DEF 0x0
-#define STP_RAM_DATA1 0x78
-#define STP_RAM_DATA1_DEF 0x0
-#define STP_PMON_CFG 0x80
-#define STP_PMON_CFG_DEF 0x0
-#define STP_PMON_CFG_ENABLE_M 0x1ULL
-#define STP_PMON_CFG_ENABLE_SHIFT 0
-#define STP_PMON_CFG_ENABLE_MASK (STP_PMON_CFG_ENABLE_M << STP_PMON_CFG_ENABLE_SHIFT)
-#define STP_PMON_CNT_0_CFG 0x88
-#define STP_PMON_CNT_0_CFG_DEF 0x0
-#define STP_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
-#define STP_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
-#define STP_PMON_CNT_0_CFG_INC_MATCH_MASK (STP_PMON_CNT_0_CFG_INC_MATCH_M << STP_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
-#define STP_PMON_CNT_0_CFG_INC_SEL_M 0x1fULL
-#define STP_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
-#define STP_PMON_CNT_0_CFG_INC_SEL_MASK (STP_PMON_CNT_0_CFG_INC_SEL_M << STP_PMON_CNT_0_CFG_INC_SEL_SHIFT)
-#define STP_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
-#define STP_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
-#define STP_PMON_CNT_0_CFG_DEC_MATCH_MASK (STP_PMON_CNT_0_CFG_DEC_MATCH_M << STP_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
-#define STP_PMON_CNT_0_CFG_DEC_SEL_M 0x1fULL
-#define STP_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
-#define STP_PMON_CNT_0_CFG_DEC_SEL_MASK (STP_PMON_CNT_0_CFG_DEC_SEL_M << STP_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
-#define STP_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
-#define STP_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
-#define STP_PMON_CNT_0_CFG_THRESHOLD_MASK (STP_PMON_CNT_0_CFG_THRESHOLD_M << STP_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
-#define STP_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
-#define STP_PMON_CNT_0_CFG_INC_INV_SHIFT 47
-#define STP_PMON_CNT_0_CFG_INC_INV_MASK (STP_PMON_CNT_0_CFG_INC_INV_M << STP_PMON_CNT_0_CFG_INC_INV_SHIFT)
-#define STP_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
-#define STP_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
-#define STP_PMON_CNT_0_CFG_DEC_MASK_MASK (STP_PMON_CNT_0_CFG_DEC_MASK_M << STP_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
-#define STP_PMON_CNT_0_CFG_MODE_M 0x7ULL
-#define STP_PMON_CNT_0_CFG_MODE_SHIFT 0
-#define STP_PMON_CNT_0_CFG_MODE_MASK (STP_PMON_CNT_0_CFG_MODE_M << STP_PMON_CNT_0_CFG_MODE_SHIFT)
-#define STP_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
-#define STP_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
-#define STP_PMON_CNT_0_CFG_DEC_INV_MASK (STP_PMON_CNT_0_CFG_DEC_INV_M << STP_PMON_CNT_0_CFG_DEC_INV_SHIFT)
-#define STP_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
-#define STP_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
-#define STP_PMON_CNT_0_CFG_INC_MASK_MASK (STP_PMON_CNT_0_CFG_INC_MASK_M << STP_PMON_CNT_0_CFG_INC_MASK_SHIFT)
-#define STP_PMON_CNT_0 0x90
-#define STP_PMON_CNT_0_DEF 0x0
-#define STP_PMON_CNT_0_CNT_M 0xffffffffffULL
-#define STP_PMON_CNT_0_CNT_SHIFT 0
-#define STP_PMON_CNT_0_CNT_MASK (STP_PMON_CNT_0_CNT_M << STP_PMON_CNT_0_CNT_SHIFT)
-#define STP_PMON_CNT_0_STS_ACC 0x98
-#define STP_PMON_CNT_0_STS_ACC_DEF 0x0
-#define STP_PMON_CNT_0_STS 0xa0
-#define STP_PMON_CNT_0_STS_DEF 0x0
-#define STP_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
-#define STP_PMON_CNT_0_STS_ACC_UF_SHIFT 1
-#define STP_PMON_CNT_0_STS_ACC_UF_MASK (STP_PMON_CNT_0_STS_ACC_UF_M << STP_PMON_CNT_0_STS_ACC_UF_SHIFT)
-#define STP_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
-#define STP_PMON_CNT_0_STS_ACC_OF_SHIFT 0
-#define STP_PMON_CNT_0_STS_ACC_OF_MASK (STP_PMON_CNT_0_STS_ACC_OF_M << STP_PMON_CNT_0_STS_ACC_OF_SHIFT)
-#define STP_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
-#define STP_PMON_CNT_0_STS_CNT_OF_SHIFT 2
-#define STP_PMON_CNT_0_STS_CNT_OF_MASK (STP_PMON_CNT_0_STS_CNT_OF_M << STP_PMON_CNT_0_STS_CNT_OF_SHIFT)
-#define STP_PMON_CNT_1_CFG 0xa8
-#define STP_PMON_CNT_1_CFG_DEF 0x0
-#define STP_PMON_CNT_1_CFG_MODE_M 0x7ULL
-#define STP_PMON_CNT_1_CFG_MODE_SHIFT 0
-#define STP_PMON_CNT_1_CFG_MODE_MASK (STP_PMON_CNT_1_CFG_MODE_M << STP_PMON_CNT_1_CFG_MODE_SHIFT)
-#define STP_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
-#define STP_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
-#define STP_PMON_CNT_1_CFG_DEC_MASK_MASK (STP_PMON_CNT_1_CFG_DEC_MASK_M << STP_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
-#define STP_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
-#define STP_PMON_CNT_1_CFG_INC_INV_SHIFT 47
-#define STP_PMON_CNT_1_CFG_INC_INV_MASK (STP_PMON_CNT_1_CFG_INC_INV_M << STP_PMON_CNT_1_CFG_INC_INV_SHIFT)
-#define STP_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
-#define STP_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
-#define STP_PMON_CNT_1_CFG_INC_MASK_MASK (STP_PMON_CNT_1_CFG_INC_MASK_M << STP_PMON_CNT_1_CFG_INC_MASK_SHIFT)
-#define STP_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
-#define STP_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
-#define STP_PMON_CNT_1_CFG_INC_MATCH_MASK (STP_PMON_CNT_1_CFG_INC_MATCH_M << STP_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
-#define STP_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
-#define STP_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
-#define STP_PMON_CNT_1_CFG_DEC_INV_MASK (STP_PMON_CNT_1_CFG_DEC_INV_M << STP_PMON_CNT_1_CFG_DEC_INV_SHIFT)
-#define STP_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
-#define STP_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
-#define STP_PMON_CNT_1_CFG_DEC_MATCH_MASK (STP_PMON_CNT_1_CFG_DEC_MATCH_M << STP_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
-#define STP_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
-#define STP_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
-#define STP_PMON_CNT_1_CFG_THRESHOLD_MASK (STP_PMON_CNT_1_CFG_THRESHOLD_M << STP_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
-#define STP_PMON_CNT_1_CFG_INC_SEL_M 0x1fULL
-#define STP_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
-#define STP_PMON_CNT_1_CFG_INC_SEL_MASK (STP_PMON_CNT_1_CFG_INC_SEL_M << STP_PMON_CNT_1_CFG_INC_SEL_SHIFT)
-#define STP_PMON_CNT_1_CFG_DEC_SEL_M 0x1fULL
-#define STP_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
-#define STP_PMON_CNT_1_CFG_DEC_SEL_MASK (STP_PMON_CNT_1_CFG_DEC_SEL_M << STP_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
-#define STP_PMON_CNT_1 0xb0
-#define STP_PMON_CNT_1_DEF 0x0
-#define STP_PMON_CNT_1_CNT_M 0xffffffffffULL
-#define STP_PMON_CNT_1_CNT_SHIFT 0
-#define STP_PMON_CNT_1_CNT_MASK (STP_PMON_CNT_1_CNT_M << STP_PMON_CNT_1_CNT_SHIFT)
-#define STP_PMON_CNT_1_STS_ACC 0xb8
-#define STP_PMON_CNT_1_STS_ACC_DEF 0x0
-#define STP_PMON_CNT_1_STS 0xc0
-#define STP_PMON_CNT_1_STS_DEF 0x0
-#define STP_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
-#define STP_PMON_CNT_1_STS_CNT_OF_SHIFT 2
-#define STP_PMON_CNT_1_STS_CNT_OF_MASK (STP_PMON_CNT_1_STS_CNT_OF_M << STP_PMON_CNT_1_STS_CNT_OF_SHIFT)
-#define STP_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
-#define STP_PMON_CNT_1_STS_ACC_UF_SHIFT 1
-#define STP_PMON_CNT_1_STS_ACC_UF_MASK (STP_PMON_CNT_1_STS_ACC_UF_M << STP_PMON_CNT_1_STS_ACC_UF_SHIFT)
-#define STP_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
-#define STP_PMON_CNT_1_STS_ACC_OF_SHIFT 0
-#define STP_PMON_CNT_1_STS_ACC_OF_MASK (STP_PMON_CNT_1_STS_ACC_OF_M << STP_PMON_CNT_1_STS_ACC_OF_SHIFT)
-
-#endif /* __PAINTBOX_REGS_V1_GENERATED_H__ */
diff --git a/drivers/misc/paintbox/paintbox-regs.h b/drivers/misc/paintbox/paintbox-regs.h
index 17b5a56..5d9dd35 100644
--- a/drivers/misc/paintbox/paintbox-regs.h
+++ b/drivers/misc/paintbox/paintbox-regs.h
@@ -17,19 +17,15 @@
#include <linux/types.h>
-#if CONFIG_PAINTBOX_VERSION_MAJOR >= 1
-#include "paintbox-regs-v1-generated.h"
-#else
#include "paintbox-regs-v0-generated.h"
-#endif
-/* TODO(ahampson): The following information should be eventually be generated
+/* TODO: The following information should be eventually be generated
* by the generator script from the RTL.
*/
#define REG_UNUSED "UNKNOWN"
-/* TODO(ahampson): Switch this to uint64_t once all the registers are
+/* TODO: Switch this to uint64_t once all the registers are
* converted to 64bit.
*/
#define IPU_REG_WIDTH sizeof(uint32_t)
@@ -67,7 +63,7 @@
#define IPU_ISR_MPO_INTR_SHIFT (IPU_ISR_MPI_INTR_SHIFT + 3)
#define IPU_ISR_MPO_INTR_MASK (IPU_ISR_MPO_INTR_M << IPU_ISR_MPO_INTR_SHIFT)
-/* TODO(showarth): Switch these to IPU_REG_WIDTH_BYTES when the trace code is
+/* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is
* fully switched over.
*/
#if CONFIG_PAINTBOX_VERSION_MAJOR >= 1
@@ -78,25 +74,25 @@
#define IO_AON_NUM_REGS (IO_APB_BLOCK_LEN / IPU_REG_WIDTH)
#endif
-/* TODO(ahampson): Switch these to IPU_REG_WIDTH_BYTES when the trace code is
+/* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is
* fully switched over.
*/
#define IO_APB_BLOCK_LEN (APB_SPARE + IPU_REG_WIDTH)
#define IO_APB_NUM_REGS (IO_APB_BLOCK_LEN / IPU_REG_WIDTH)
-/* TODO(ahampson): Switch these to IPU_REG_WIDTH_BYTES when the trace code is
+/* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is
* fully switched over.
*/
#define IO_AXI_BLOCK_LEN (AXI_SPARE + IPU_REG_WIDTH)
#define IO_AXI_NUM_REGS (IO_AXI_BLOCK_LEN / IPU_REG_WIDTH)
-/* TODO(ahampson): Switch these to IPU_REG_WIDTH_BYTES when the trace code is
+/* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is
* fully switched over.
*/
#define STP_BLOCK_LEN (STP_PMON_CNT_1_STS + IPU_REG_WIDTH)
#define STP_NUM_REGS (STP_BLOCK_LEN / IPU_REG_WIDTH)
-/* TODO(ahampson): Switch these to IPU_REG_WIDTH_BYTES when the trace code is
+/* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is
* fully switched over.
*/
diff --git a/drivers/misc/paintbox/paintbox-sram.c b/drivers/misc/paintbox/paintbox-sram.c
index 734ff39..913d700 100644
--- a/drivers/misc/paintbox/paintbox-sram.c
+++ b/drivers/misc/paintbox/paintbox-sram.c
@@ -83,7 +83,7 @@
DUMP_REGISTERS(pb, data_reg, reg_count, __func__);
}
-/* TODO(ahampson): Remove once b/30316979 is fixed. RAM_DATA_MODE_SWAP is
+/* TODO: Remove once b/30316979 is fixed. RAM_DATA_MODE_SWAP is
* needed because the assembler writes the instruction in reverse byte order
* (due to an issue with the DV tools). Once that bug is fixed this function
* can be removed.
@@ -114,7 +114,7 @@
DUMP_REGISTERS(pb, data_reg, reg_count, __func__);
}
-/* TODO(ahampson): The conversion to the vector SRAM's column major lane
+/* TODO: The conversion to the vector SRAM's column major lane
* ordering needs to be moved to the runtime so it can be used for both DMA and
* PIO. This function can be removed once that support is ready.
*/
@@ -184,7 +184,7 @@
}
}
-/* TODO(ahampson): Remove once b/30316979 is fixed. RAM_DATA_MODE_SWAP is
+/* TODO: Remove once b/30316979 is fixed. RAM_DATA_MODE_SWAP is
* needed because the assember writes the instruction in reverse byte order (due
* to an issue with the DV tools). Once that bug is fixed this function can be
* removed.
@@ -212,7 +212,7 @@
}
}
-/* TODO(ahampson): The conversion to the vector SRAM's column major lane
+/* TODO: The conversion to the vector SRAM's column major lane
* ordering needs to be moved to the runtime so it can be used for both DMA and
* PIO. This function can be removed once that support is ready.
*/
diff --git a/drivers/misc/paintbox/paintbox-sram.h b/drivers/misc/paintbox/paintbox-sram.h
index 95359ab..f9b4811 100644
--- a/drivers/misc/paintbox/paintbox-sram.h
+++ b/drivers/misc/paintbox/paintbox-sram.h
@@ -22,13 +22,13 @@
#define RAM_DATA_MODE_NORMAL 0
-/* TODO(ahampson): Remove once b/30316979 is fixed. RAM_DATA_MODE_SWAP is
+/* TODO: Remove once b/30316979 is fixed. RAM_DATA_MODE_SWAP is
* needed because the assembler writes the instruction in reverse byte order
* (due to an issue with the DV tools).
*/
#define RAM_DATA_MODE_SWAP 1
-/* TODO(ahampson): The conversion to the vector SRAM's column major lane
+/* TODO: The conversion to the vector SRAM's column major lane
* ordering needs to be moved to the runtime so it can be used for both DMA and
* PIO.
*/
diff --git a/drivers/misc/paintbox/paintbox-stp-sram.c b/drivers/misc/paintbox/paintbox-stp-sram.c
index 0ad22b4..b37e90b 100644
--- a/drivers/misc/paintbox/paintbox-stp-sram.c
+++ b/drivers/misc/paintbox/paintbox-stp-sram.c
@@ -40,7 +40,7 @@
paintbox_stp_select(pb, sram_config->core_id);
- /* TODO(ahampson): This can be removed once the SWAP and COL_MAJOR
+ /* TODO: This can be removed once the SWAP and COL_MAJOR
* support is moved outside the driver.
*/
switch (sram_config->ram_data_mode) {
@@ -122,7 +122,7 @@
paintbox_stp_select(pb, sram_config->core_id);
}
- /* TODO(ahampson): This can be removed once the SWAP and COL_MAJOR
+ /* TODO: This can be removed once the SWAP and COL_MAJOR
* support is moved outside the driver.
*/
switch (sram_config->ram_data_mode) {
@@ -743,7 +743,7 @@
* the various lane groups of vector memory from their physical addresses to
* their logical addresses.
*
- * TODO(ahampson): Conversion between logical and physical addressing for the
+ * TODO: Conversion between logical and physical addressing for the
* lane groups may be moved to the runtime. If that is the case then this code
* can be remmoved.
*/
diff --git a/drivers/misc/paintbox/paintbox-stp.c b/drivers/misc/paintbox/paintbox-stp.c
index e160e28..ffc5d0b 100644
--- a/drivers/misc/paintbox/paintbox-stp.c
+++ b/drivers/misc/paintbox/paintbox-stp.c
@@ -383,7 +383,7 @@
* done for the Simulator. The FPGA does not have a similar mechanism
* How the post-DMA interrupt cleanup on the hardware will work is TBD.
*
- * TODO(ahampson): This should be moved into QEMU or Simulator Server.
+ * TODO: This should be moved into QEMU or Simulator Server.
* b/34815472
*/
#ifdef CONFIG_PAINTBOX_SIMULATOR_SUPPORT
@@ -430,7 +430,7 @@
* done for the Simulator. The FPGA does not have a similar mechanism
* How the post-DMA interrupt cleanup on the hardware will work is TBD.
*
- * TODO(ahampson): This should be moved into QEMU or Simulator Server.
+ * TODO: This should be moved into QEMU or Simulator Server.
* b/34815472
*/
ret = sim_wait_for_idle(pb, stp);
@@ -468,7 +468,7 @@
* a similar mechanism. How the post-DMA interrupt cleanup on
* the hardware will work is TBD.
*
- * TODO(ahampson): This should be moved into QEMU or Simulator
+ * TODO: This should be moved into QEMU or Simulator
* Server.
* b/34815472
*/
@@ -561,7 +561,7 @@
return 0;
}
-/* TODO(ahampson): This should be removed b/36069658 */
+/* TODO: This should be removed b/36069658 */
int setup_stp_ioctl(struct paintbox_data *pb, struct paintbox_session *session,
unsigned long arg)
{
@@ -598,7 +598,7 @@
dev_dbg(&pb->pdev->dev, "stp%u setup program len %zu bytes\n",
stp->stp_id, config.len);
- /* TODO(ahampson): The assembler generates the pISA in the byte order
+ /* TODO: The assembler generates the pISA in the byte order
* expected by the DV. In order for the pISA to be used by the hardware
* the instruction buffer needs to be byte swapped. This will
* eventually be fixed in the assembler. b/30316979
@@ -856,7 +856,7 @@
paintbox_irq_waiter_signal(pb, stp->irq, timestamp,
int_code, 0 /* error */);
- /* TODO(showarth): signal error to irq waiter. b/62351992 */
+ /* TODO: signal error to irq waiter. b/62351992 */
}
status = readl(pb->stp.reg_base + STP_ISR_OVF);
diff --git a/drivers/misc/paintbox/paintbox.c b/drivers/misc/paintbox/paintbox.c
index a0160d2..6c68822 100644
--- a/drivers/misc/paintbox/paintbox.c
+++ b/drivers/misc/paintbox/paintbox.c
@@ -115,7 +115,7 @@
mutex_lock(&pb->lock);
- /* TODO(ahampson): Cleanup release sequence. b/62372748 */
+ /* TODO: Cleanup release sequence. b/62372748 */
paintbox_mipi_release(pb, session);
paintbox_dma_release(pb, session);
diff --git a/include/uapi/paintbox.h b/include/uapi/paintbox.h
index 4974201..19979d3 100644
--- a/include/uapi/paintbox.h
+++ b/include/uapi/paintbox.h
@@ -2,7 +2,6 @@
* Driver interface for the Paintbox Image Processing Unit
*
* Copyright (C) 2015 Google, Inc.
- * Author: Adam Hampson <ahampson@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -20,7 +19,7 @@
#include <linux/compiler.h>
#include <linux/ioctl.h>
-/* TODO(ahampson): There are several enumerations and types that are used in
+/* TODO: There are several enumerations and types that are used in
* C and C++ code across the kernel, QEMU, and Simulator. A unified header file
* hierarchy should be created to avoid type duplication. This also has build
* system implications as the components using these types are spread out over
@@ -168,7 +167,7 @@
bool auto_start_transfer;
};
-/* TODO(ahampson): We can remove this when b/62371806 is fixed.
+/* TODO: We can remove this when b/62371806 is fixed.
*/
struct dma_transfer_read {
uint32_t channel_id;
@@ -585,7 +584,7 @@
* -ENOSYS: Unimplemented Functionality
*
*/
-/* TODO(ahampson): Reorganize and compress ioctl number space. b/36068296 */
+/* TODO: Reorganize and compress ioctl number space. b/36068296 */
#define PB_GET_IPU_CAPABILITIES _IOR('p', 1, struct ipu_capabilities)
#define PB_ALLOCATE_DMA_CHANNEL _IOW('p', 2, unsigned int)
#define PB_SETUP_DMA_TRANSFER _IOW('p', 3, struct dma_transfer_config)
