| /* Paintbox register header file |
| * |
| * Copyright (C) 2016 The Android Open Source Project |
| * |
| * This software is licensed under the terms of the GNU General Public |
| * License version 2, as published by the Free Software Foundation, and |
| * may be copied, distributed, and modified under those terms. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #ifndef _PAINTBOX_REGS_H |
| #define _PAINTBOX_REGS_H |
| |
| #include <linux/types.h> |
| |
| #include "paintbox-regs-v0-generated.h" |
| |
| /* TODO: The following information should be eventually be generated |
| * by the generator script from the RTL. |
| */ |
| |
| #define REG_UNUSED "UNKNOWN" |
| |
| /* TODO: Switch this to uint64_t once all the registers are |
| * converted to 64bit. |
| */ |
| #define IPU_REG_WIDTH sizeof(uint32_t) |
| #define IPU_REG_WIDTH_BYTES sizeof(uint64_t) |
| |
| /* Number of bytes allocated for each register trace when dumping the register |
| * contents through verbose logging or debugfs. |
| */ |
| #define REG_DEBUG_BUFFER_SIZE 96 |
| |
| #define REG_INDEX(r) ((r) / IPU_REG_WIDTH) |
| #define REG_NAME_ENTRY(r) [(r) / IPU_REG_WIDTH] = #r |
| |
| #define STP_INST_SRAM_INSTRUCTION_WIDTH_BYTES 16 |
| #define STP_CONST_SRAM_WORD_WIDTH_BYTES 2 |
| #define STP_SCALAR_SRAM_WORD_WIDTH_BYTES 2 |
| #define STP_VECTOR_SRAM_WORD_WIDTH_BYTES 2 |
| |
| /* Width of STP RAM transfer through PIO interface */ |
| #define STP_PIO_WORD_WIDTH_BYTES 16 |
| |
| #define IPU_RESERVED_OFFSET 0x1C00 |
| |
| /* IPU_I{M,S}R: |
| * ... | 30 29 | 28 26 |... |
| * ... | MIF_INT | ... |
| * ... | MPO_INTR | MPI_INTR | ... |
| */ |
| #define IPU_IMR_MPI_INTR_SHIFT IPU_IMR_MIF_INTR_SHIFT |
| #define IPU_IMR_MPO_INTR_SHIFT (IPU_IMR_MPI_INTR_SHIFT + 3) |
| #define IPU_ISR_MPI_INTR_M 0x7ULL |
| #define IPU_ISR_MPI_INTR_SHIFT IPU_ISR_MIF_INTR_SHIFT |
| #define IPU_ISR_MPI_INTR_MASK (IPU_ISR_MPI_INTR_M << IPU_ISR_MPI_INTR_SHIFT) |
| #define IPU_ISR_MPO_INTR_M 0x3ULL |
| #define IPU_ISR_MPO_INTR_SHIFT (IPU_ISR_MPI_INTR_SHIFT + 3) |
| #define IPU_ISR_MPO_INTR_MASK (IPU_ISR_MPO_INTR_M << IPU_ISR_MPO_INTR_SHIFT) |
| |
| /* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is |
| * fully switched over. |
| */ |
| #if CONFIG_PAINTBOX_VERSION_MAJOR >= 1 |
| #define IO_AON_BLOCK_LEN (AON_SPARE + IPU_REG_WIDTH) |
| #define IO_AON_NUM_REGS (IO_AON_BLOCK_LEN / IPU_REG_WIDTH) |
| #else |
| #define IO_AON_BLOCK_LEN (APB_SPARE + IPU_REG_WIDTH) |
| #define IO_AON_NUM_REGS (IO_APB_BLOCK_LEN / IPU_REG_WIDTH) |
| #endif |
| |
| /* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is |
| * fully switched over. |
| */ |
| #define IO_APB_BLOCK_LEN (APB_SPARE + IPU_REG_WIDTH) |
| #define IO_APB_NUM_REGS (IO_APB_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| /* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is |
| * fully switched over. |
| */ |
| #define IO_AXI_BLOCK_LEN (AXI_SPARE + IPU_REG_WIDTH) |
| #define IO_AXI_NUM_REGS (IO_AXI_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| /* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is |
| * fully switched over. |
| */ |
| #define STP_BLOCK_LEN (STP_PMON_CNT_1_STS + IPU_REG_WIDTH) |
| #define STP_NUM_REGS (STP_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| /* TODO: Switch these to IPU_REG_WIDTH_BYTES when the trace code is |
| * fully switched over. |
| */ |
| |
| /* LBP Block Boundaries */ |
| #define LBP_POOL_BLOCK_LEN (LBP_PMON_CNT_1_STS + IPU_REG_WIDTH) |
| #define LBP_POOL_NUM_REGS (LBP_POOL_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #if CONFIG_PAINTBOX_VERSION_MAJOR >= 1 |
| #define LBP_BLOCK_LEN (LB_SB_DELTA + IPU_REG_WIDTH) |
| #else |
| #define LBP_BLOCK_LEN (LB_L_PARAM + IPU_REG_WIDTH) |
| #endif |
| #define LBP_NUM_REGS (LBP_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| /* Block length for just the line buffer registers */ |
| #define LB_BLOCK_START LB_CTRL0 |
| #define LB_BLOCK_LEN (LBP_BLOCK_LEN - LB_BLOCK_START) |
| #define LB_NUM_REGS (LB_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #define LB_BLOCK_LEN (LBP_BLOCK_LEN - LB_BLOCK_START) |
| |
| |
| /* LBP_CAP0 Register Bits */ |
| #define LBP_CAP0_MAX_LB_MAX LBP_CAP0_MAX_LB_M |
| |
| /* LB_CTRL0 Register Bits */ |
| #define LB_CTRL0_NUM_RPTR_MAX LB_CTRL0_NUM_RPTR_M |
| #define LB_CTRL0_NUM_CHAN_MAX LB_CTRL0_NUM_CHAN_M |
| #define LB_CTRL0_FB_ROWS_MAX LB_CTRL0_FB_ROWS_M |
| #define LB_CTRL0_REUSE_ROWS_MAX LB_CTRL0_REUSE_ROWS_M |
| |
| /* LB_OFFSET Register Bits */ |
| #define LB_OFFSET_OFFSET_X_MIN -32767 |
| #define LB_OFFSET_OFFSET_X_MAX 32767 |
| #define LB_OFFSET_OFFSET_Y_MIN -32767 |
| #define LB_OFFSET_OFFSET_Y_MAX 32767 |
| #define LB_OFFSET_OFFSET_CHAN_MAX LB_OFFSET_OFFSET_CHAN_M |
| |
| /* LB_BDRY Register Bits */ |
| #define LB_BDRY_BDRY_VAL_CLAMP 0x00000000 |
| #define LB_BDRY_BDRY_VAL_REPEAT 0x00000001 |
| #define LB_BDRY_BDRY_VAL_REFLECT 0x00000002 |
| #define LB_BDRY_BDRY_VAL_RESERVED 0x00000003 |
| |
| /* LB_BASE Register Bits */ |
| #define LB_BASE_FB_BASE_ALIGN_MASK 0x1F |
| #define LB_BASE_FB_BASE_ALIGN_SHIFT 5 |
| #define LB_BASE_SB_BASE_ALIGN_MASK 0x1F |
| #define LB_BASE_SB_BASE_ALIGN_SHIFT 5 |
| |
| /* LB_STAT Register Bits */ |
| #define LB_STAT_EMPTY0 (1 << 1) |
| #define LB_STAT_EMPTY1 (1 << 2) |
| #define LB_STAT_EMPTY2 (1 << 3) |
| |
| /* LB_L_PARAM Register Bits */ |
| #define LB_L_PARAM_L_INC_MAX LB_L_PARAM_L_INC_M |
| #define LB_L_PARAM_L_WIDTH_MAX LB_L_PARAM_L_WIDTH_M |
| |
| #define LBP_DATA_REG_COUNT 4 |
| |
| /* MMU_ERR_LOG */ |
| #define MMU_IOVA_SHIFT 12 |
| |
| /* MMU_TABLE_BASE */ |
| #if CONFIG_PAINTBOX_VERSION_MAJOR == 0 |
| #ifdef CONFIG_PAINTBOX_FPGA_SUPPORT |
| #define MMU_TABLE_BASE_RSHIFT 12 |
| #else |
| #define MMU_TABLE_BASE_RSHIFT 13 |
| #endif |
| #else |
| #define MMU_TABLE_BASE_RSHIFT 12 |
| #endif |
| |
| /* MMU_ERR_BASE */ |
| #define MMU_ERROR_BASE_RSHIFT 12 |
| |
| /* MMU_FLUSH_ADDRESS */ |
| #define MMU_FLUSH_ADDRESS_RSHIFT 12 |
| |
| /* MMU_ISR / MMU_IMR */ |
| #define NUM_MMU_INTERRUPTS 1 |
| |
| /* BIF_ISR / BIF_IMR */ |
| #define NUM_BIF_INTERRUPTS 1 |
| |
| #define STP_LBP_MASK_DEF 0xFFFF |
| #define STP_DATA_REG_COUNT 2 |
| |
| /* Vector Memory Address Bits */ |
| #define STP_RAM_ADDR_ROW 0x0F |
| #define STP_RAM_ADDR_ROW_SHIFT 7 |
| #define STP_RAM_ADDR_ROW_MASK (STP_RAM_ADDR_ROW << STP_RAM_ADDR_ROW_SHIFT) |
| #define STP_RAM_ADDR_OFFSET_MASK 0x7F |
| |
| #define STP_RAM_TARG_INST_RAM 0 |
| #define STP_RAM_TARG_CNST_RAM 1 |
| #define STP_RAM_TARG_DATA_RAM 2 |
| #define STP_RAM_TARG_ALU_IO_RF_0 3 |
| #define STP_RAM_TARG_ALU_IO_RF_1 4 |
| #define STP_RAM_TARG_ALU_IO_RF_2 5 |
| #define STP_RAM_TARG_ALU_IO_RF_3 6 |
| #define STP_RAM_TARG_ALU_IO_RF_4 7 |
| #define STP_RAM_TARG_ALU_IO_RAM_0 11 |
| #define STP_RAM_TARG_ALU_IO_RAM_1 12 |
| #define STP_RAM_TARG_ALU_IO_RAM_2 13 |
| #define STP_RAM_TARG_ALU_IO_RAM_3 14 |
| #define STP_RAM_TARG_ALU_IO_RAM_4 15 |
| |
| #define COMMON_RAM_ADDR 0xFFFF |
| #define COMMON_RAM_ADDR_SHIFT 16 |
| |
| #define STP_LANE_GROUP_WIDTH 4 |
| #define VECTOR_GROUP_ROW_OFFSET_BYTES 4 |
| |
| /* DMA Block Boundaries */ |
| #define DMA_CTRL_BLOCK_START DMA_CTRL |
| #define DMA_CTRL_BLOCK_END (DMA_PMON_CNT_3_STS + IPU_REG_WIDTH_BYTES) |
| #define DMA_CTRL_BLOCK_LEN DMA_CTRL_BLOCK_END |
| #define DMA_CTRL_NUM_REGS (DMA_CTRL_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #define DMA_CHAN_BLOCK_START DMA_CHAN_MODE |
| #define DMA_CHAN_BLOCK_END (DMA_CHAN_DEPENDENCY + IPU_REG_WIDTH_BYTES) |
| #define DMA_CHAN_BLOCK_LEN (DMA_CHAN_BLOCK_END - DMA_CHAN_BLOCK_START) |
| #define DMA_CHAN_NUM_REGS (DMA_CHAN_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #define DMA_STAT_BLOCK_START DMA_STAT_CTRL |
| #define DMA_STAT_BLOCK_END (DMA_SPARE + IPU_REG_WIDTH_BYTES) |
| #define DMA_STAT_BLOCK_LEN (DMA_STAT_BLOCK_END - DMA_STAT_BLOCK_START) |
| #define DMA_STAT_NUM_REGS (DMA_STAT_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #define DMA_BLOCK_LEN DMA_STAT_BLOCK_END |
| #define DMA_NUM_REGS (DMA_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| /* DMA_CTRL Register Bits */ |
| #define DMA_CTRL_AXI_SWIZZLE_NONE 0 |
| #define DMA_CTRL_AXI_SWIZZLE_BIG_ENDIAN 1 |
| #define DMA_CTRL_AXI_SWIZZLE_NEIGHBOR_BYTES 2 |
| |
| /* DMA_CHAN_MODE Register Bits */ |
| #define DMA_CHAN_MODE_SRC_DRAM 0 |
| #define DMA_CHAN_MODE_SRC_LBP 1 |
| #define DMA_CHAN_MODE_SRC_STP 2 |
| #define DMA_CHAN_MODE_SRC_MIPI_IN 3 |
| #define DMA_CHAN_MODE_DST_DRAM 0 |
| #define DMA_CHAN_MODE_DST_LBP 1 |
| #define DMA_CHAN_MODE_DST_STP 2 |
| #define DMA_CHAN_MODE_DST_MIPI_OUT 3 |
| |
| /* DMA_CHAN_IMG_FORMAT Register Bits */ |
| #define DMA_CHAN_IMG_FORMAT_COMPONENTS_MIN 1 |
| #define DMA_CHAN_IMG_FORMAT_COMPONENTS_MAX \ |
| (DMA_CHAN_IMG_FORMAT_COMPONENTS_M + 1) |
| #define DMA_CHAN_IMG_FORMAT_PLANES_MIN 1 |
| #define DMA_CHAN_IMG_FORMAT_PLANES_MAX (DMA_CHAN_IMG_FORMAT_PLANES_M + 1) |
| #define DMA_CHAN_IMG_FORMAT_BIT_DEPTH8 0 |
| #define DMA_CHAN_IMG_FORMAT_BIT_DEPTH10 1 |
| #define DMA_CHAN_IMG_FORMAT_BIT_DEPTH12 2 |
| #define DMA_CHAN_IMG_FORMAT_BIT_DEPTH14 3 |
| #define DMA_CHAN_IMG_FORMAT_BIT_DEPTH16 4 |
| #define DMA_CHAN_IMG_FORMAT_RGBA_FORMAT_DISABLED 0 |
| #define DMA_CHAN_IMG_FORMAT_RGBA_FORMAT_RGBA 1 |
| #define DMA_CHAN_IMG_FORMAT_RGBA_FORMAT_ARGB 2 |
| |
| /* DMA_CHAN_IMG_SIZE Register Bits */ |
| #define DMA_CHAN_IMG_SIZE_HEIGHT_MAX DMA_CHAN_IMG_SIZE_IMG_HEIGHT_M |
| #define DMA_CHAN_IMG_SIZE_WIDTH_MAX DMA_CHAN_IMG_SIZE_IMG_WIDTH_M |
| |
| /* DMA_CHAN_IMG_POS Register Bits */ |
| #define DMA_CHAN_IMG_POS_START_MAX 32767 |
| #define DMA_CHAN_IMG_POS_START_MIN -32767 |
| #define DMA_CHAN_IMG_POS_LB_START_MAX 32767 |
| #define DMA_CHAN_IMG_POS_LB_START_MIN -32767 |
| |
| /* DMA CHAN_IMG_POS DRAM -> STP Register Bits */ |
| #define DMA_CHAN_LB_START_Y_STP_IRAM (0ULL << 2) |
| #define DMA_CHAN_LB_START_Y_STP_CRAM (1ULL << 2) |
| #define DMA_CHAN_LB_START_Y_STP_DRAM (2ULL << 2) |
| #define DMA_CHAN_LB_START_Y_STP_ARRAY_16x16 (3ULL << 2) |
| #define DMA_CHAN_LB_START_Y_STP_ARRAY_32x32 (4ULL << 2) |
| |
| /* DMA_CHAN_IMG_LAYOUT Register Bits */ |
| #define DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_MAX DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_M |
| #define DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_MAX DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_M |
| |
| /* DMA_CHAN_VA_BDRY Register Bits */ |
| #define DMA_CHAN_VA_BDRY_LEN_MAX DMA_CHAN_VA_BDRY_LEN_M |
| |
| /* DMA_CHAN_BIF_XFER Register Bits */ |
| #define DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_MAX 256 |
| #define DMA_CHAN_BIF_XFER_OUTSTANDING_MIN 1 |
| #define DMA_CHAN_BIF_XFER_OUTSTANDING_MAX 64 |
| |
| /* DMA_CHAN_NOC_XFER Register Bits */ |
| #define DMA_CHAN_NOC_XFER_SHEET_WIDTH_MAX 256 |
| #define DMA_CHAN_NOC_XFER_SHEET_HEIGHT_MAX 16 |
| #define DMA_CHAN_NOC_XFER_OUTSTANDING_MIN 1 |
| #define DMA_CHAN_NOC_XFER_OUTSTANDING_MAX 8 |
| #define DMA_CHAN_NOC_XFER_RETRY_INTERVAL_MIN 1 |
| #define DMA_CHAN_NOC_XFER_RETRY_INTERVAL_MAX DMA_CHAN_NOC_XFER_RETRY_INTERVAL_M |
| |
| /* MIPI Block Boundaries */ |
| #define MPI_COMMON_BLOCK_START MPI_CAP |
| #define MPI_COMMON_BLOCK_END (MPI_STRM_SEL + IPU_REG_WIDTH_BYTES) |
| #define MPI_COMMON_BLOCK_LEN MPI_COMMON_BLOCK_END |
| #define MPI_COMMON_NUM_REGS (MPI_COMMON_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #define MPI_STRM_BLOCK_START MPI_STRM_CTRL |
| #define MPI_STRM_BLOCK_END (MPI_STRM_CNFG1_RO + IPU_REG_WIDTH_BYTES) |
| #define MPI_STRM_BLOCK_LEN (MPI_STRM_BLOCK_END - MPI_STRM_BLOCK_START) |
| #define MPI_STRM_NUM_REGS (MPI_STRM_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #define MPO_COMMON_BLOCK_START MPO_CAP |
| #define MPO_COMMON_BLOCK_END (MPO_STRM_SEL + IPU_REG_WIDTH_BYTES) |
| #define MPO_COMMON_BLOCK_LEN (MPO_COMMON_BLOCK_END - MPO_COMMON_BLOCK_START) |
| #define MPO_COMMON_NUM_REGS (MPO_COMMON_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #define MPO_STRM_BLOCK_START MPO_STRM_CTRL |
| #define MPO_STRM_BLOCK_END (MPO_STRM_CNFG1_RO + IPU_REG_WIDTH_BYTES) |
| #define MPO_STRM_BLOCK_LEN (MPO_STRM_BLOCK_END - MPO_STRM_BLOCK_START) |
| #define MPO_STRM_NUM_REGS (MPO_STRM_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #define IO_IPU_BLOCK_LEN MPO_STRM_BLOCK_END |
| #define IO_IPU_NUM_REGS (IO_IPU_BLOCK_LEN / IPU_REG_WIDTH) |
| |
| #if CONFIG_PAINTBOX_VERSION_MAJOR >= 1 |
| #define MPI_CTRL_STRM_CONTINUOUS_SHIFT MPI_CTRL_STRM_CONTINUOUS0_SHIFT |
| #define MPI_CTRL_STRM_CONTINUOUS_MASK \ |
| (0xfffULL << MPI_CTRL_STRM_CONTINUOUS_SHIFT) |
| |
| #define MPO_CTRL_STRM_CONTINUOUS_SHIFT MPO_CTRL_STRM_CONTINUOUS0_SHIFT |
| #define MPO_CTRL_STRM_CONTINUOUS_MASK \ |
| (0xfffULL << MPO_CTRL_STRM_CONTINUOUS_SHIFT) |
| #endif |
| |
| /* MPI_STRM_CNFG0 Register Bits */ |
| #define MPI_STRM_CNFG0_VC_MAX MPI_STRM_CNFG0_VC_M |
| #define MPI_STRM_CNFG0_DT_IN_MAX MPI_STRM_CNFG0_DT_IN_M |
| #define MPI_STRM_CNFG0_DT_PROC_MAX MPI_STRM_CNFG0_DT_PROC_M |
| #define MPI_STRM_CNFG0_STRP_HEIGHT_MIN 1 |
| |
| /* Easel Errata b/32334151 |
| * MIPI input stripe height is restricted to 28 on V0 IPU |
| */ |
| #if CONFIG_PAINTBOX_VERSION_MAJOR == 0 |
| #define MPI_STRM_CNFG0_STRP_HEIGHT_MAX 28 |
| #else |
| #define MPI_STRM_CNFG0_STRP_HEIGHT_MAX 32 |
| #endif |
| #define MPI_STRM_CNFG0_STRP_HEIGHT_ROW_ALIGN 4 |
| #define MPI_STRM_CNFG0_IMG_WIDTH_MAX MPI_STRM_CNFG0_IMG_WIDTH_M |
| #define MPI_STRM_CNFG0_IMG_HEIGHT_MAX MPI_STRM_CNFG0_IMG_HEIGHT_M |
| |
| /* MPI_STRM_CNFG1 Register Bits */ |
| #define MPI_STRM_CNFG1_SEG_START_MAX MPI_STRM_CNFG1_SEG_START_M |
| #define MPI_STRM_CNFG1_SEG_END_MIN 1 |
| #define MPI_STRM_CNFG1_SEG_END_MAX 128 |
| #define MPI_STRM_CNFG1_SEGS_PER_ROW_MIN 1 |
| #define MPI_STRM_CNFG1_SEGS_PER_ROW_MAX 128 |
| #define MPI_STRM_CNFG1_SEG_WORDS_PER_ROW_MIN 1 |
| #define MPI_STRM_CNFG1_SEG_WORDS_PER_ROW_MAX 4096 |
| |
| /* MPO_STRM_CNFG0 Register Bits */ |
| #define MPO_STRM_CNFG0_STRP_HEIGHT_MIN 1 |
| #define MPO_STRM_CNFG0_STRP_HEIGHT_MAX 32 |
| |
| #endif /* __PAINTBOX_REGS_H__ */ |
