Chips/Hisilicon: Add common files for Hisilicon platforms
This patch contains common drivers and libraries for Hisilicon
platforms, used by the subsequent support for D02 and D03.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
new file mode 100755
index 0000000..219cb47
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
@@ -0,0 +1,54 @@
+#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IpmiCmdLib
+ FILE_GUID = E06060B9-1688-41d9-BC12-72567A4D3400
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IpmiCmdLib
+
+[Sources]
+
+[Binaries.AARCH64]
+ LIB|IpmiCmdLib.lib|*
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ ArmLib
+ BaseMemoryLib
+[Ppis]
+
+
+[Guids]
+
+[Protocols]
+ gIpmiInterfaceProtocolGuid
+ gHisiBoardNicProtocolGuid
+ gBmcInfoProtocolGuid
+
+[FixedPcd]
+
+
+
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib
new file mode 100644
index 0000000..3e8c8e1
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib
Binary files differ
diff --git a/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.inf b/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.inf
new file mode 100644
index 0000000..7a41ed8
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.inf
@@ -0,0 +1,54 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformSysCtrlLibPv660
+ FILE_GUID = EBF63479-8F72-4ada-8B2A-960322F7F61A
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSysCtrlLib
+
+[Sources.common]
+
+
+[Sources.AARCH64]
+
+[Binaries.AARCH64]
+ LIB|PlatformSysCtrlLibPv660.lib|*
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ OemAddressMapLib
+ OemMiscLib
+
+[FixedPcd]
+ gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType
+ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+
+ gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress
+ gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress
+ gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress
+ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress
+
+[BuildOptions]
+
diff --git a/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.lib b/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.lib
new file mode 100644
index 0000000..37082f9
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.lib
Binary files differ
diff --git a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.inf b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.inf
new file mode 100644
index 0000000..e7cd204
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.inf
@@ -0,0 +1,48 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Pv660SerdesLib
+ FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerdesLib
+
+[Binaries.common]
+ LIB|Pv660SerdesLib.lib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ BaseLib
+ BaseMemoryLib
+
+
+ OemMiscLib
+
+[BuildOptions]
+
+[FixedPcd]
+
+
+
diff --git a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib
new file mode 100644
index 0000000..6e9c41d
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib
Binary files differ
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 0000000..3d5ae91
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,40 @@
+/** @file
+
+ Copyright (c) 2014, Applied Micro Curcuit Corporation. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <PiDxe.h>
+#include <Guid/EventGroup.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/AcpiAml.h>
+#include "EthMac.h"
+
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ return EthMacInit();
+}
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
new file mode 100644
index 0000000..812a214
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -0,0 +1,72 @@
+## @file
+#
+# Copyright (c) 2014, Applied Micro Curcuit Corp. All rights reserved.<BR>
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiPlatform
+ FILE_GUID = e0829681-e9fa-4117-a8d7-84efadff863d
+ MODULE_TYPE = DXE_DRIVER
+ #MODULE_TYPE = UEFI_APPLICATION
+ VERSION_STRING = 1.0
+ ENTRY_POINT = AcpiPlatformEntryPoint
+
+[Sources]
+ AcpiPlatform.c
+ EthMac.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ShellPkg/ShellPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiLib
+ PcdLib
+ BaseMemoryLib
+ DebugLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ #UefiApplicationEntryPoint
+
+[Guids]
+ gShellVariableGuid # ALWAYS_CONSUMED
+ gArmMpCoreInfoGuid
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+ gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+ gHisiBoardNicProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+
+[FeaturePcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol
+
+[Pcd]
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gHisiBoardNicProtocolGuid
+
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c
new file mode 100644
index 0000000..41f5692
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c
@@ -0,0 +1,484 @@
+/** @file
+
+ Copyright (c) 2014, Applied Micro Curcuit Corporation. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ This driver is called to initialize the FW part of the PHY in preparation
+ for the OS.
+
+**/
+
+#include <Guid/ShellVariableGuid.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+
+#include <PiDxe.h>
+#include <Guid/EventGroup.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/AcpiAml.h>
+
+#include <Protocol/HisiBoardNicProtocol.h>
+
+// Turn on debug message by enabling below define
+//#define ACPI_DEBUG
+
+#ifdef ACPI_DEBUG
+#define DBG(arg...) DEBUG((EFI_D_ERROR,## arg))
+#else
+#define DBG(arg...)
+#endif
+
+#define EFI_ACPI_MAX_NUM_TABLES 20
+#define DSDT_SIGNATURE 0x54445344
+
+#define D02_ACPI_ETH_ID "HISI00C1"
+#define D03_ACPI_ETH_ID "HISI00C2"
+
+#define ACPI_ETH_MAC_KEY "local-mac-address"
+
+#define PREFIX_VARIABLE_NAME L"MAC"
+#define PREFIX_VARIABLE_NAME_COMPAT L"RGMII_MAC"
+#define MAC_MAX_LEN 30
+
+EFI_STATUS GetEnvMac(
+ IN UINTN MacNextID,
+ IN OUT UINT8 *MacBuffer)
+{
+ EFI_MAC_ADDRESS Mac;
+ EFI_STATUS Status;
+ HISI_BOARD_NIC_PROTOCOL *OemNic = NULL;
+
+ Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ Status = OemNic->GetMac(&Mac, MacNextID);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] GetMac failed %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ CopyMem (MacBuffer, &Mac, 6);
+ DEBUG((EFI_D_ERROR, "Port %d MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
+ MacNextID,
+ MacBuffer[0],
+ MacBuffer[1],
+ MacBuffer[2],
+ MacBuffer[3],
+ MacBuffer[4],
+ MacBuffer[5]
+ ));
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS _SearchReplacePackageMACAddress(
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ IN EFI_ACPI_HANDLE ChildHandle,
+ IN UINTN Level,
+ IN OUT BOOLEAN *Found,
+ IN UINTN MacNextID)
+{
+ // ASL template for ethernet driver:
+/*
+ * Name (_DSD, Package () {
+ * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ * Package () {
+ * Package (2) {"mac-address", Package (6) { 00, 11, 22, 33, 44, 55 }}
+ * Package (2) {"phy-channel", 0},
+ * Package (2) {"phy-mode", "rgmii"},
+ * Package (2) {"max-transfer-unit", 0x5dc}, // MTU of 1500
+ * Package (2) {"max-speed", 0x3e8}, // 1000 Mbps
+ * }
+ * })
+ */
+ EFI_STATUS Status;
+ EFI_ACPI_DATA_TYPE DataType;
+ CONST UINT8 *Data;
+ CONST VOID *Buffer;
+ UINTN DataSize;
+ UINTN Count;
+ EFI_ACPI_HANDLE CurrentHandle;
+ EFI_ACPI_HANDLE NextHandle;
+ UINT8 MACBuffer[MAC_MAX_LEN];
+
+ DBG("In Level:%d\n", Level);
+ Status = EFI_SUCCESS;
+ for (CurrentHandle = NULL; ;) {
+ Status = AcpiTableProtocol->GetChild(ChildHandle, &CurrentHandle);
+ if (Level != 3 && (EFI_ERROR(Status) || CurrentHandle == NULL))
+ break;
+
+ Status = AcpiTableProtocol->GetOption(CurrentHandle, 0, &DataType, &Buffer, &DataSize);
+ Data = Buffer;
+ DBG("_DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X\n",
+ DataSize, Data[0], DataSize > 1 ? Data[1] : 0);
+
+ if (Level < 2 && Data[0] != AML_PACKAGE_OP)
+ continue;
+
+ if (Level == 2 && Data[0] == AML_STRING_PREFIX) {
+ Status = AcpiTableProtocol->GetOption(CurrentHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ DBG(" _DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X\n",
+ DataSize, Data[0], DataSize > 1 ? Data[1] : 0);
+
+ Data = Buffer;
+ if (DataType != EFI_ACPI_DATA_TYPE_STRING
+ || AsciiStrCmp((CHAR8 *) Data, ACPI_ETH_MAC_KEY) != 0)
+ continue;
+
+ DBG("_DSD Key Type %d. Found MAC address key\n", DataType);
+
+ //
+ // We found the node.
+ //
+ *Found = TRUE;
+ continue;
+ }
+
+ if (Level == 3 && *Found) {
+
+ //Update the MAC
+ Status = GetEnvMac(MacNextID, MACBuffer);
+ if (EFI_ERROR(Status))
+ break;
+
+ for (Count = 0; Count < 6; Count++) {
+ Status = AcpiTableProtocol->GetOption(CurrentHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ Data = Buffer;
+ DBG(" _DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X DataType 0x%X\n",
+ DataSize, Data[0], DataSize > 1 ? Data[1] : 0, DataType);
+
+ if (DataType != EFI_ACPI_DATA_TYPE_UINT)
+ break;
+
+ // only need one byte.
+ // FIXME: Assume the CPU is little endian
+ Status = AcpiTableProtocol->SetOption(CurrentHandle, 1, (VOID *)&MACBuffer[Count], sizeof(UINT8));
+ if (EFI_ERROR(Status))
+ break;
+ Status = AcpiTableProtocol->GetChild(ChildHandle, &CurrentHandle);
+ if (EFI_ERROR(Status) || CurrentHandle == NULL)
+ break;
+ }
+ break;
+ }
+
+ if (Level > 3)
+ break;
+
+ //Search next package
+ AcpiTableProtocol->Open((VOID *) Buffer, &NextHandle);
+ Status = _SearchReplacePackageMACAddress(AcpiTableProtocol, NextHandle, Level + 1, Found, MacNextID);
+ AcpiTableProtocol->Close(NextHandle);
+ if (!EFI_ERROR(Status))
+ break;
+ }
+
+ return Status;
+}
+
+EFI_STATUS SearchReplacePackageMACAddress(
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ IN EFI_ACPI_HANDLE ChildHandle,
+ IN UINTN MacNextID)
+{
+ BOOLEAN Found = FALSE;
+ UINTN Level = 0;
+
+ return _SearchReplacePackageMACAddress(AcpiTableProtocol, ChildHandle, Level, &Found, MacNextID);
+}
+
+EFI_STATUS
+GetEthID (
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ EFI_ACPI_HANDLE ChildHandle,
+ UINTN *EthID
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_DATA_TYPE DataType;
+ CHAR8 Data[5];
+ CONST VOID *Buffer;
+ UINTN DataSize;
+
+ // Get NameString ETHx
+ Status = AcpiTableProtocol->GetOption (ChildHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] Get NameString failed: %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ CopyMem (Data, Buffer, 4);
+ DBG("Size %p Data %02x %02x %02x %02x\n", DataSize, Data[0], Data[1], Data[2], Data[3]);
+
+ Data[4] = '\0';
+ if (DataSize != 4 ||
+ AsciiStrnCmp ("ETH", Data, 3) != 0 ||
+ Data[3] > '9' || Data[3] < '0') {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] The NameString %a is not ETHn\n", __FUNCTION__, __LINE__, Data));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *EthID = Data[3] - '0';
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS ProcessDSDTDevice (
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ EFI_ACPI_HANDLE ChildHandle)
+{
+ EFI_STATUS Status;
+ EFI_ACPI_DATA_TYPE DataType;
+ CONST UINT8 *Data;
+ CONST VOID *Buffer;
+ UINTN DataSize;
+ EFI_ACPI_HANDLE DevHandle;
+ INTN Found = 0;
+ UINTN MacNextID;
+
+ Status = AcpiTableProtocol->GetOption(ChildHandle, 0, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ return EFI_SUCCESS;
+
+ Data = Buffer;
+ //
+ // Skip all non-device type
+ //
+ if (DataSize != 2 || Data[0] != AML_EXT_OP || Data[1] != AML_EXT_DEVICE_OP)
+ return EFI_SUCCESS;
+
+ //
+ // Walk the device type node
+ //
+ for (DevHandle = NULL; ; ) {
+ Status = AcpiTableProtocol->GetChild(ChildHandle, &DevHandle);
+ if (EFI_ERROR(Status) || DevHandle == NULL)
+ break;
+
+ //
+ // Search for _HID with Ethernet ID
+ //
+ Status = AcpiTableProtocol->GetOption(DevHandle, 0, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ Data = Buffer;
+ DBG("Data Type 0x%02X %02X\n", Data[0], DataSize > 1 ? Data[1] : 0);
+ if (DataSize == 1 && Data[0] == AML_NAME_OP) {
+ Status = AcpiTableProtocol->GetOption(DevHandle, 1, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ Data = Buffer;
+ if (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING) {
+ if (AsciiStrnCmp((CHAR8 *) Data, "_HID", 4) == 0) {
+ EFI_ACPI_HANDLE ValueHandle;
+
+ Status = AcpiTableProtocol->GetOption(DevHandle, 2, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ if (DataType != EFI_ACPI_DATA_TYPE_CHILD)
+ continue;
+
+ AcpiTableProtocol->Open((VOID *) Buffer, &ValueHandle);
+ Status = AcpiTableProtocol->GetOption(ValueHandle, 1, &DataType, &Buffer, &DataSize);
+
+ Data = Buffer;
+ DBG("[%a:%d] - _HID = %a\n", __FUNCTION__, __LINE__, Data);
+
+ if (EFI_ERROR(Status) ||
+ DataType != EFI_ACPI_DATA_TYPE_STRING ||
+ ((AsciiStrCmp((CHAR8 *) Data, D02_ACPI_ETH_ID) != 0) &&
+ (AsciiStrCmp((CHAR8 *) Data, D03_ACPI_ETH_ID) != 0))) {
+ AcpiTableProtocol->Close(ValueHandle);
+ Found = 0;
+ continue;
+ }
+
+ DBG("Found Ethernet device\n");
+ AcpiTableProtocol->Close(ValueHandle);
+ Status = GetEthID (AcpiTableProtocol, ChildHandle, &MacNextID);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ Found = 1;
+ } else if (Found == 1 && AsciiStrnCmp((CHAR8 *) Data, "_DSD", 4) == 0) {
+ //
+ // Patch MAC address for open source kernel
+ //
+ EFI_ACPI_HANDLE PkgHandle;
+ Status = AcpiTableProtocol->GetOption(DevHandle, 2, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status))
+ break;
+
+ if (DataType != EFI_ACPI_DATA_TYPE_CHILD)
+ continue;
+
+ //
+ // Open package data
+ //
+ AcpiTableProtocol->Open((VOID *) Buffer, &PkgHandle);
+ Status = AcpiTableProtocol->GetOption(PkgHandle, 0, &DataType, &Buffer, &DataSize);
+
+ Data = Buffer;
+ DBG("_DSD Subnode Store Op Code 0x%02X %02X\n",
+ Data[0], DataSize > 1 ? Data[1] : 0);
+
+ //
+ // Walk the _DSD node
+ //
+ if (DataSize == 1 && Data[0] == AML_PACKAGE_OP)
+ Status = SearchReplacePackageMACAddress(AcpiTableProtocol, PkgHandle, MacNextID);
+
+ AcpiTableProtocol->Close(PkgHandle);
+ }
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+BOOLEAN
+IsSbScope (
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ EFI_ACPI_HANDLE ChildHandle
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_DATA_TYPE DataType;
+ CONST UINT8 *Data;
+ CONST VOID *Buffer;
+ UINTN DataSize;
+
+ Status = AcpiTableProtocol->GetOption (ChildHandle, 0, &DataType, &Buffer, &DataSize);
+ if (EFI_ERROR(Status)) return FALSE;
+
+ Data = Buffer;
+ if (DataSize != 1 || Data[0] != AML_SCOPE_OP) {
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+EFI_STATUS ProcessDSDTChild(
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ EFI_ACPI_HANDLE ChildHandle)
+{
+ EFI_STATUS Status;
+ EFI_ACPI_HANDLE DevHandle;
+
+ // Check Scope(_SB) at first
+ if (!IsSbScope (AcpiTableProtocol, ChildHandle)) {
+ return ProcessDSDTDevice (AcpiTableProtocol, ChildHandle);
+ }
+
+ for (DevHandle = NULL; ; ) {
+ Status = AcpiTableProtocol->GetChild (ChildHandle, &DevHandle);
+ if (EFI_ERROR(Status) || DevHandle == NULL) {
+ break;
+ }
+
+ ProcessDSDTDevice (AcpiTableProtocol, DevHandle);
+ }
+
+ return EFI_SUCCESS;
+}
+
+static EFI_STATUS ProcessDSDT(
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+ EFI_ACPI_HANDLE TableHandle)
+{
+ EFI_STATUS Status;
+ EFI_ACPI_HANDLE ChildHandle;
+ //
+ // Parse table for device type
+ DBG ("[%a:%d] - TableHandle=%p\n", __FUNCTION__, __LINE__, TableHandle);
+ for (ChildHandle = NULL; ; ) {
+ Status = AcpiTableProtocol->GetChild(TableHandle, &ChildHandle);
+ DBG ("[%a:%d] - Child=%p, %r\n", __FUNCTION__, __LINE__, ChildHandle, Status);
+ if (EFI_ERROR(Status))
+ break;
+ if (ChildHandle == NULL)
+ break;
+
+ ProcessDSDTChild(AcpiTableProtocol, ChildHandle);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS EthMacInit(void)
+{
+ EFI_STATUS Status;
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol;
+ EFI_ACPI_SDT_HEADER *Table;
+ EFI_ACPI_TABLE_VERSION TableVersion;
+ UINTN TableKey;
+ EFI_ACPI_HANDLE TableHandle;
+ UINTN i;
+
+ DEBUG ((EFI_D_ERROR, "Updating Ethernet MAC in ACPI DSDT...\n"));
+
+ //
+ // Find the AcpiTable protocol
+ Status = gBS->LocateProtocol(&gEfiAcpiSdtProtocolGuid, NULL, (VOID**) &AcpiTableProtocol);
+ if (EFI_ERROR(Status)) {
+ DBG("Unable to locate ACPI table protocol\n");
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Search for DSDT Table
+ for (i = 0; i < EFI_ACPI_MAX_NUM_TABLES; i++) {
+ Status = AcpiTableProtocol->GetAcpiTable(i, &Table, &TableVersion, &TableKey);
+ if (EFI_ERROR(Status))
+ break;
+ if (Table->Signature != DSDT_SIGNATURE)
+ continue;
+
+ Status = AcpiTableProtocol->OpenSdt(TableKey, &TableHandle);
+ if (EFI_ERROR(Status))
+ break;
+
+ ProcessDSDT(AcpiTableProtocol, TableHandle);
+
+ AcpiTableProtocol->Close(TableHandle);
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.h b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.h
new file mode 100644
index 0000000..bf4cbb1
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.h
@@ -0,0 +1,22 @@
+/*
+ *
+ * Copyright (c) 2014, Applied Micro Circuits Corporation
+ * Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2015, Linaro Limited. All rights reserved.
+ * Author: Loc Ho <lho@apm.com>
+ *
+ * This program and the accompanying materials
+ *are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ */
+#ifndef _ETH_MAC_H_
+#define _ETH_MAC_H_
+
+EFI_STATUS EthMacInit(VOID);
+
+#endif
+
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c
new file mode 100644
index 0000000..91c0733
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c
@@ -0,0 +1,109 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "FlashFvbDxe.h"
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL* This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID* Buffer
+)
+{
+ FLASH_INSTANCE* Instance;
+ EFI_STATUS Status;
+
+ Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+ DEBUG ((EFI_D_INFO, "FlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+ if ( !This->Media->MediaPresent )
+ {
+ Status = EFI_NO_MEDIA;
+ }
+ else if ( This->Media->MediaId != MediaId )
+ {
+ Status = EFI_MEDIA_CHANGED;
+ }
+ else
+ {
+ Status = FlashReadBlocks (Instance, Lba, BufferSizeInBytes, Buffer);
+ }
+
+ return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL* This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID* Buffer
+)
+{
+ FLASH_INSTANCE* Instance;
+ EFI_STATUS Status;
+
+ Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+ DEBUG ((EFI_D_INFO, "FlashBlockIoWriteBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+ if ( !This->Media->MediaPresent )
+ {
+ Status = EFI_NO_MEDIA;
+ }
+ else if ( This->Media->MediaId != MediaId )
+ {
+ Status = EFI_MEDIA_CHANGED;
+ }
+ else if ( This->Media->ReadOnly )
+ {
+ Status = EFI_WRITE_PROTECTED;
+ }
+ else
+ {
+ Status = FlashWriteBlocks (Instance, Lba, BufferSizeInBytes, Buffer);
+ }
+
+ return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL* This
+)
+{
+ // No Flush required for the NOR Flash driver
+ // because cache operations are not permitted.
+
+ // Nothing to do so just return without error
+ return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
new file mode 100644
index 0000000..544228a
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
@@ -0,0 +1,1230 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on files under ArmPlatformPkg/Drivers/NorFlashDxe/
+**/
+
+#include "FlashFvbDxe.h"
+STATIC EFI_EVENT mFlashFvbVirtualAddrChangeEvent;
+STATIC UINTN mFlashNvStorageVariableBase;
+
+
+//
+// Global variable declarations
+//
+
+FLASH_DESCRIPTION mFlashDevices[FLASH_DEVICE_COUNT] =
+{
+ {
+ // UEFI Variable Services non-volatile storage
+ 0xa4000000,
+ FixedPcdGet32(PcdFlashNvStorageVariableBase),
+ 0x20000,
+ SIZE_64KB,
+ {0xCC2CBF29, 0x1498, 0x4CDD, {0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, 0x09, 0x09}}
+ }
+
+};
+
+FLASH_INSTANCE** mFlashInstances;
+
+FLASH_INSTANCE mFlashInstanceTemplate =
+{
+ FLASH_SIGNATURE, // Signature
+ NULL, // Handle ... NEED TO BE FILLED
+
+ FALSE, // Initialized
+ NULL, // Initialize
+
+ 0, // DeviceBaseAddress ... NEED TO BE FILLED
+ 0, // RegionBaseAddress ... NEED TO BE FILLED
+ 0, // Size ... NEED TO BE FILLED
+ 0, // StartLba
+
+ {
+ EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision
+ NULL, // Media ... NEED TO BE FILLED
+ NULL, //NorFlashBlockIoReset
+ FlashBlockIoReadBlocks,
+ FlashBlockIoWriteBlocks,
+ FlashBlockIoFlushBlocks
+ }, // BlockIoProtocol
+
+ {
+ 0, // MediaId ... NEED TO BE FILLED
+ FALSE, // RemovableMedia
+ TRUE, // MediaPresent
+ FALSE, // LogicalPartition
+ FALSE, // ReadOnly
+ FALSE, // WriteCaching;
+ SIZE_64KB, // BlockSize ... NEED TO BE FILLED
+ 4, // IoAlign
+ 0, // LastBlock ... NEED TO BE FILLED
+ 0, // LowestAlignedLba
+ 1, // LogicalBlocksPerPhysicalBlock
+ }, //Media;
+
+ FALSE, // SupportFvb ... NEED TO BE FILLED
+ {
+ FvbGetAttributes,
+ FvbSetAttributes,
+ FvbGetPhysicalAddress,
+ FvbGetBlockSize,
+ FvbRead,
+ FvbWrite,
+ FvbEraseBlocks,
+ NULL, //ParentHandle
+ }, // FvbProtoccol;
+
+ {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {(UINT8)(sizeof(VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8)},
+ },
+ { 0x0, 0x0, 0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }}, // GUID ... NEED TO BE FILLED
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {sizeof (EFI_DEVICE_PATH_PROTOCOL),
+ 0}
+ }
+ } // DevicePath
+};
+
+HISI_SPI_FLASH_PROTOCOL* mFlash;
+
+///
+/// The Firmware Volume Block Protocol is the low-level interface
+/// to a firmware volume. File-level access to a firmware volume
+/// should not be done using the Firmware Volume Block Protocol.
+/// Normal access to a firmware volume must use the Firmware
+/// Volume Protocol. Typically, only the file system driver that
+/// produces the Firmware Volume Protocol will bind to the
+/// Firmware Volume Block Protocol.
+///
+
+/**
+ Initialises the FV Header and Variable Store Header
+ to support variable operations.
+
+ @param[in] Ptr - Location to initialise the headers
+
+**/
+EFI_STATUS
+InitializeFvAndVariableStoreHeaders (
+ IN FLASH_INSTANCE* Instance
+)
+{
+ EFI_STATUS Status;
+ VOID* Headers;
+ UINTN HeadersLength;
+ EFI_FIRMWARE_VOLUME_HEADER* FirmwareVolumeHeader;
+ VARIABLE_STORE_HEADER* VariableStoreHeader;
+
+ if (!Instance->Initialized && Instance->Initialize)
+ {
+ Instance->Initialize (Instance);
+ }
+
+ HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY) + sizeof(VARIABLE_STORE_HEADER);
+ Headers = AllocateZeroPool(HeadersLength);
+
+ // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous.
+ ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) + PcdGet32(PcdFlashNvStorageVariableSize) == PcdGet32(PcdFlashNvStorageFtwWorkingBase));
+ ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) == PcdGet32(PcdFlashNvStorageFtwSpareBase));
+
+ // Check if the size of the area is at least one block size
+ ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0));
+ ASSERT((PcdGet32(PcdFlashNvStorageFtwWorkingSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageFtwWorkingSize) / Instance->Media.BlockSize > 0));
+ ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0));
+
+ // Ensure the Variable area Base Addresses are aligned on a block size boundaries
+ ASSERT((UINT32)PcdGet32(PcdFlashNvStorageVariableBase) % Instance->Media.BlockSize == 0);
+ ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwWorkingBase) % Instance->Media.BlockSize == 0);
+ ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareBase) % Instance->Media.BlockSize == 0);
+
+ //
+ // EFI_FIRMWARE_VOLUME_HEADER
+ //
+ FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
+ FirmwareVolumeHeader->FvLength =
+ PcdGet32(PcdFlashNvStorageVariableSize) +
+ PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32(PcdFlashNvStorageFtwSpareSize);
+ FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
+ FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) (
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY | // After erasure all bits take this value (i.e. '1')
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled
+ );
+ FirmwareVolumeHeader->HeaderLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY);
+ FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
+ FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1;
+ FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize;
+ FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
+ FirmwareVolumeHeader->BlockMap[1].Length = 0;
+ FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16*)FirmwareVolumeHeader, FirmwareVolumeHeader->HeaderLength);
+
+ //
+ // VARIABLE_STORE_HEADER
+ //
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)Headers + (UINTN)FirmwareVolumeHeader->HeaderLength);
+ CopyGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid);
+ VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength;
+ VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
+ VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
+
+ // Install the combined super-header in the NorFlash
+ Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
+
+ FreePool (Headers);
+ return Status;
+}
+
+/**
+ Check the integrity of firmware volume header.
+
+ @param[in] FwVolHeader - A pointer to a firmware volume header
+
+ @retval EFI_SUCCESS - The firmware volume is consistent
+ @retval EFI_NOT_FOUND - The firmware volume has been corrupted.
+
+**/
+EFI_STATUS
+ValidateFvHeader (
+ IN FLASH_INSTANCE* Instance
+)
+{
+ UINT16 Checksum;
+ EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader;
+ VARIABLE_STORE_HEADER* VariableStoreHeader;
+ UINTN VariableStoreLength;
+ UINTN FvLength;
+
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->RegionBaseAddress;
+
+ FvLength = PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32(PcdFlashNvStorageFtwSpareSize);
+
+ //
+ // Verify the header revision, header signature, length
+ // Length of FvBlock cannot be 2**64-1
+ // HeaderLength cannot be an odd number
+ //
+ if ( (FwVolHeader->Revision != EFI_FVH_REVISION)
+ || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
+ || (FwVolHeader->FvLength != FvLength)
+ )
+ {
+ DEBUG ((EFI_D_ERROR, "ValidateFvHeader: No Firmware Volume header present\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ // Check the Firmware Volume Guid
+ if ( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE )
+ {
+ DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Firmware Volume Guid non-compatible\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ // Verify the header checksum
+ Checksum = CalculateSum16((UINT16*)FwVolHeader, FwVolHeader->HeaderLength);
+ if (Checksum != 0)
+ {
+ DEBUG ((EFI_D_ERROR, "ValidateFvHeader: FV checksum is invalid (Checksum:0x%X)\n", Checksum));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader + (UINTN)FwVolHeader->HeaderLength);
+
+ // Check the Variable Store Guid
+ if ( CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) == FALSE )
+ {
+ DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Variable Store Guid non-compatible\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength;
+ if (VariableStoreHeader->Size != VariableStoreLength)
+ {
+ DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Variable Store Length does not match\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The FvbGetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
+ current settings are returned.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ OUT EFI_FVB_ATTRIBUTES_2* Attributes
+)
+{
+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
+ FLASH_INSTANCE* Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2) (
+
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY // After erasure all bits take this value (i.e. '1')
+
+ );
+
+ // Check if it is write protected
+ if (Instance->Media.ReadOnly != TRUE)
+ {
+
+ FlashFvbAttributes = FlashFvbAttributes |
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be enabled
+ }
+
+ *Attributes = FlashFvbAttributes;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The FvbSetAttributes() function sets configurable firmware volume attributes
+ and returns the new settings of the firmware volume.
+
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes On input, Attributes is a pointer to EFI_FVB_ATTRIBUTES_2
+ that contains the desired firmware volume settings.
+ On successful return, it contains the new settings of
+ the firmware volume.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with the capabilities
+ as declared in the firmware volume header.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN OUT EFI_FVB_ATTRIBUTES_2* Attributes
+)
+{
+ DEBUG ((EFI_D_ERROR, "FvbSetAttributes(0x%X) is not supported\n", *Attributes));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ The GetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address Pointer to a caller-allocated
+ EFI_PHYSICAL_ADDRESS that, on successful
+ return from GetPhysicalAddress(), contains the
+ base address of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ OUT EFI_PHYSICAL_ADDRESS* Address
+)
+{
+
+ if(NULL == Address)
+ {
+ return EFI_UNSUPPORTED;
+ };
+
+ *Address = mFlashNvStorageVariableBase;
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The GetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba Indicates the block for which to return the size.
+
+ @param BlockSize Pointer to a caller-allocated UINTN in which
+ the size of the block is returned.
+
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+ which the number of consecutive blocks,
+ starting with Lba, is returned. All
+ blocks in this range have a size of
+ BlockSize.
+
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN EFI_LBA Lba,
+ OUT UINTN* BlockSize,
+ OUT UINTN* NumberOfBlocks
+)
+{
+ EFI_STATUS Status;
+ FLASH_INSTANCE* Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ if (Lba > Instance->Media.LastBlock)
+ {
+ Status = EFI_INVALID_PARAMETER;
+ }
+ else
+ {
+ // This is easy because in this platform each NorFlash device has equal sized blocks.
+ *BlockSize = (UINTN) Instance->Media.BlockSize;
+ *NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1);
+
+
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The Read() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the Read() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The Read() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index from which to read.
+
+ @param Offset Offset into the block at which to begin reading.
+
+ @param NumBytes Pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the buffer.
+ At exit, *NumBytes contains the total number of bytes read.
+
+ @param Buffer Pointer to a caller-allocated buffer that will be used
+ to hold the data that is read.
+
+ @retval EFI_SUCCESS The firmware volume was read successfully, and contents are
+ in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
+ On output, NumBytes contains the total number of bytes
+ returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be read.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbRead (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN* NumBytes,
+ IN OUT UINT8* Buffer
+)
+{
+ EFI_STATUS Status;
+ UINTN BlockSize;
+ FLASH_INSTANCE* Instance;
+
+ UINTN StartAddress;
+ UINTN ReadAddress;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ if (!Instance->Initialized && Instance->Initialize)
+ {
+ if (EfiAtRuntime ()) {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Initialize at runtime is not supported!\n", __FUNCTION__, __LINE__));
+ return EFI_UNSUPPORTED;
+ }
+
+ Instance->Initialize(Instance);
+ }
+
+ Status = EFI_SUCCESS;
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ // The read must not span block boundaries.
+ // We need to check each variable individually because adding two large values together overflows.
+ if ((Offset >= BlockSize) ||
+ (*NumBytes > BlockSize) ||
+ ((Offset + *NumBytes) > BlockSize))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL] ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", __FUNCTION__, __LINE__, Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // We must have some bytes to read
+ if (*NumBytes == 0)
+ {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // Get the address to start reading from
+ StartAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress,
+ Lba,
+ BlockSize
+ );
+ ReadAddress = StartAddress - Instance->DeviceBaseAddress + Offset;
+
+ Status = mFlash->Read(mFlash, (UINT32)ReadAddress, Buffer, *NumBytes);
+ if (EFI_SUCCESS != Status)
+ {
+ // Return one of the pre-approved error statuses
+ Status = EFI_DEVICE_ERROR;
+ return Status;
+ }
+
+
+ return Status;
+}
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The Write() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the Write()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again. Before calling the
+ Write() function, it is recommended for the caller to first call
+ the EraseBlocks() function to erase the specified block to
+ write. A block erase cycle will transition bits from the
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the Write() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The Write() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the Write() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index to write to.
+
+ @param Offset Offset into the block at which to begin writing.
+
+ @param NumBytes The pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the buffer.
+ At exit, *NumBytes contains the total number of bytes actually written.
+
+ @param Buffer The pointer to a caller-allocated buffer that contains the source for the write.
+
+ @retval EFI_SUCCESS The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary.
+ On output, NumBytes contains the total number of bytes
+ actually written.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be written.
+
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbWrite (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN* NumBytes,
+ IN UINT8* Buffer
+)
+{
+ EFI_STATUS Status;
+ UINTN BlockSize;
+ FLASH_INSTANCE* Instance;
+ UINTN BlockAddress;
+ UINTN WriteAddress;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+ if (NULL == Instance)
+ {
+ return EFI_INVALID_PARAMETER;
+
+ }
+
+ if (!Instance->Initialized && Instance->Initialize)
+ {
+ if (EfiAtRuntime ()) {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Initialize at runtime is not supported!\n", __FUNCTION__, __LINE__));
+ return EFI_UNSUPPORTED;
+ }
+
+ Instance->Initialize(Instance);
+ }
+
+ Status = EFI_SUCCESS;
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE)
+ {
+ DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - Can not write: Device is in WriteDisabled state.\n"));
+ // It is in WriteDisabled state, return an error right away
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ // The write must not span block boundaries.
+ // We need to check each variable individually because adding two large values together overflows.
+ if ( ( Offset >= BlockSize ) ||
+ ( *NumBytes > BlockSize ) ||
+ ( (Offset + *NumBytes) > BlockSize ) )
+ {
+ DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // We must have some bytes to write
+ if (*NumBytes == 0)
+ {
+ DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ BlockAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, BlockSize);
+ WriteAddress = BlockAddress - Instance->DeviceBaseAddress + Offset;
+
+ Status = mFlash->Write(mFlash, (UINT32)WriteAddress, (UINT8*)Buffer, *NumBytes);
+ if (EFI_SUCCESS != Status)
+ {
+ DEBUG((EFI_D_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status));
+ return Status;
+ }
+
+ return Status;
+
+}
+
+/**
+ Erases and initialises a firmware volume block.
+
+ The EraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the EraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the EraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to EraseBlocks() must be fully
+ flushed to the hardware before the EraseBlocks() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ... The variable argument list is a list of tuples.
+ Each tuple describes a range of LBAs to erase
+ and consists of the following:
+ - An EFI_LBA that indicates the starting LBA
+ - A UINTN that indicates the number of blocks to erase.
+
+ The list is terminated with an EFI_LBA_LIST_TERMINATOR.
+ For example, the following indicates that two ranges of blocks
+ (5-7 and 10-11) are to be erased:
+ EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
+
+ @retval EFI_SUCCESS The erase request successfully completed.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be written.
+ The firmware device may have been partially erased.
+
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable argument list do
+ not exist in the firmware volume.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ ...
+)
+{
+ EFI_STATUS Status;
+ VA_LIST Args;
+ UINTN BlockAddress; // Physical address of Lba to erase
+ EFI_LBA StartingLba; // Lba from which we start erasing
+ UINTN NumOfLba; // Number of Lba blocks to erase
+ FLASH_INSTANCE* Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ Status = EFI_SUCCESS;
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE)
+ {
+ // Firmware volume is in WriteDisabled state
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Before erasing, check the entire list of parameters to ensure all specified blocks are valid
+ VA_START (Args, This);
+ do
+ {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR)
+ {
+ //Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // All blocks must be within range
+ if ((NumOfLba == 0) || ((Instance->StartLba + StartingLba + NumOfLba - 1) > Instance->Media.LastBlock))
+ {
+ VA_END (Args);
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+ }
+ while (TRUE);
+ VA_END (Args);
+
+ //
+ // To get here, all must be ok, so start erasing
+ //
+ VA_START (Args, This);
+ do
+ {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR)
+ {
+ // Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // Go through each one and erase it
+ while (NumOfLba > 0)
+ {
+
+ // Get the physical address of Lba to erase
+ BlockAddress = GET_BLOCK_ADDRESS (
+ Instance->RegionBaseAddress,
+ Instance->StartLba + StartingLba,
+ Instance->Media.BlockSize
+ );
+
+ // Erase it
+
+ Status = FlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
+ if (EFI_ERROR(Status))
+ {
+ VA_END (Args);
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+ // Move to the next Lba
+ StartingLba++;
+ NumOfLba--;
+ }
+ }
+ while (TRUE);
+ VA_END (Args);
+
+EXIT:
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+FvbInitialize (
+ IN FLASH_INSTANCE* Instance
+)
+{
+ EFI_STATUS Status;
+ UINT32 FvbNumLba;
+
+ Instance->Initialized = TRUE;
+ mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase);
+
+ // Set the index of the first LBA for the FVB
+ Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
+
+ // Determine if there is a valid header at the beginning of the Flash
+ Status = ValidateFvHeader (Instance);
+ if (EFI_ERROR(Status))
+ {
+ // There is no valid header, so time to install one.
+ // Erase all the Flash that is reserved for variable storage
+ FvbNumLba = (PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) + (UINT32)PcdGet32(PcdFlashNvStorageFtwSpareSize)) / Instance->Media.BlockSize;
+ Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR);
+ if (EFI_ERROR(Status))
+ {
+ return Status;
+ }
+
+ // Install all appropriate headers
+ Status = InitializeFvAndVariableStoreHeaders (Instance);
+ if (EFI_ERROR(Status))
+ {
+ return Status;
+ }
+ }
+ return Status;
+}
+
+
+EFI_STATUS
+FlashPlatformGetDevices (
+ OUT FLASH_DESCRIPTION** FlashDevices,
+ OUT UINT32* Count
+)
+{
+ if ((FlashDevices == NULL) || (Count == NULL))
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *FlashDevices = mFlashDevices;
+ *Count = FLASH_DEVICE_COUNT;
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+FlashCreateInstance (
+ IN UINTN FlashDeviceBase,
+ IN UINTN FlashRegionBase,
+ IN UINTN FlashSize,
+ IN UINT32 MediaId,
+ IN UINT32 BlockSize,
+ IN BOOLEAN SupportFvb,
+ IN CONST GUID* FlashGuid,
+ OUT FLASH_INSTANCE** FlashInstance
+)
+{
+ EFI_STATUS Status;
+ FLASH_INSTANCE* Instance;
+
+ if (FlashInstance == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Instance = AllocateRuntimeCopyPool (sizeof(FLASH_INSTANCE), &mFlashInstanceTemplate);
+ if (Instance == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Instance->DeviceBaseAddress = FlashDeviceBase;
+ Instance->RegionBaseAddress = FlashRegionBase;
+ Instance->Size = FlashSize;
+
+ Instance->BlockIoProtocol.Media = &Instance->Media;
+ Instance->Media.MediaId = MediaId;
+ Instance->Media.BlockSize = BlockSize;
+ Instance->Media.LastBlock = (FlashSize / BlockSize) - 1;
+
+ CopyGuid (&Instance->DevicePath.Vendor.Guid, FlashGuid);
+
+ if (SupportFvb)
+ {
+ Instance->SupportFvb = TRUE;
+ Instance->Initialize = FvbInitialize;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+ &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
+ &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol,
+ NULL
+ );
+
+ if (EFI_ERROR(Status))
+ {
+ FreePool(Instance);
+ return Status;
+ }
+ }
+ else
+ {
+ Instance->Initialized = TRUE;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+ &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
+ NULL
+ );
+ if (EFI_ERROR(Status))
+ {
+ FreePool(Instance);
+ return Status;
+ }
+ }
+
+ *FlashInstance = Instance;
+ return Status;
+}
+
+EFI_STATUS
+FlashUnlockSingleBlockIfNecessary (
+ IN FLASH_INSTANCE* Instance,
+ IN UINTN BlockAddress
+)
+{
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+FlashEraseSingleBlock (
+ IN FLASH_INSTANCE* Instance,
+ IN UINTN BlockAddress
+)
+{
+ EFI_STATUS Status;
+ UINTN EraseAddress;
+
+ Status = EFI_SUCCESS;
+ EraseAddress = BlockAddress - Instance->DeviceBaseAddress;
+
+ Status = mFlash->Erase(mFlash, (UINT32)EraseAddress, Instance->Media.BlockSize);
+ if (EFI_SUCCESS != Status)
+ {
+ DEBUG((EFI_D_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ * The following function presumes that the block has already been unlocked.
+ **/
+EFI_STATUS
+FlashUnlockAndEraseSingleBlock (
+ IN FLASH_INSTANCE* Instance,
+ IN UINTN BlockAddress
+)
+{
+ EFI_STATUS Status;
+ UINTN Index;
+
+ Index = 0;
+ // The block erase might fail a first time (SW bug ?). Retry it ...
+ do
+ {
+ // Unlock the block if we have to
+ Status = FlashUnlockSingleBlockIfNecessary (Instance, BlockAddress);
+ if (!EFI_ERROR(Status))
+ {
+ Status = FlashEraseSingleBlock (Instance, BlockAddress);
+ }
+ Index++;
+ }
+ while ((Index < FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED));
+
+ if (Index == FLASH_ERASE_RETRY)
+ {
+ DEBUG((EFI_D_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", BlockAddress, Index));
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+FlashWriteBlocks (
+ IN FLASH_INSTANCE* Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID* Buffer
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINTN BlockAddress;
+ UINT32 NumBlocks;
+ UINTN WriteAddress;
+
+ // The buffer must be valid
+ if (Buffer == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Instance->Media.ReadOnly == TRUE)
+ {
+ return EFI_WRITE_PROTECTED;
+ }
+
+ // We must have some bytes to read
+ if (BufferSizeInBytes == 0)
+ {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // The size of the buffer must be a multiple of the block size
+ if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0)
+ {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // All blocks must be within the device
+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
+ if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL]ERROR - Write will exceed last block.\n", __FUNCTION__, __LINE__ ));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ BlockAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, Instance->Media.BlockSize);
+
+ WriteAddress = BlockAddress - Instance->DeviceBaseAddress;
+
+ Status = mFlash->Write(mFlash, (UINT32)WriteAddress, (UINT8*)Buffer, BufferSizeInBytes);
+ if (EFI_SUCCESS != Status)
+ {
+ DEBUG((EFI_D_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status));
+ return Status;
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+FlashReadBlocks (
+ IN FLASH_INSTANCE* Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID* Buffer
+)
+{
+ UINT32 NumBlocks;
+ UINTN StartAddress;
+ UINTN ReadAddress;
+ EFI_STATUS Status;
+
+ // The buffer must be valid
+ if (Buffer == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // We must have some bytes to read
+ if (BufferSizeInBytes == 0)
+ {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // The size of the buffer must be a multiple of the block size
+ if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0)
+ {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // All blocks must be within the device
+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
+ if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1))
+ {
+ DEBUG((EFI_D_ERROR, "FlashReadBlocks: ERROR - Read will exceed last block\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Get the address to start reading from
+ StartAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress,
+ Lba,
+ Instance->Media.BlockSize
+ );
+
+
+ ReadAddress = StartAddress - Instance->DeviceBaseAddress;
+
+ Status = mFlash->Read(mFlash, (UINT32)ReadAddress, Buffer, BufferSizeInBytes);
+ if (EFI_SUCCESS != Status)
+ {
+ DEBUG((EFI_D_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+VOID
+EFIAPI
+FlashFvbVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EfiConvertPointer (0x0, (VOID**)&mFlash);
+ EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+FlashFvbInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE* SystemTable
+)
+{
+ EFI_STATUS Status;
+ UINT32 Index;
+ FLASH_DESCRIPTION* FlashDevices;
+ UINT32 FlashDeviceCount;
+ BOOLEAN ContainVariableStorage;
+
+
+ Status = FlashPlatformGetDevices (&FlashDevices, &FlashDeviceCount);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Fail to get Flash devices\n", __FUNCTION__, __LINE__));
+ return Status;
+ }
+
+ mFlashInstances = AllocatePool ((UINT32)(sizeof(FLASH_INSTANCE*) * FlashDeviceCount));
+
+ Status = gBS->LocateProtocol (&gHisiSpiFlashProtocolGuid, NULL, (VOID*) &mFlash);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Status=%r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ for (Index = 0; Index < FlashDeviceCount; Index++)
+ {
+ // Check if this Flash device contain the variable storage region
+ ContainVariableStorage =
+ (FlashDevices[Index].RegionBaseAddress <= (UINT32)PcdGet32 (PcdFlashNvStorageVariableBase)) &&
+ ((UINT32)(PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvStorageVariableSize)) <= FlashDevices[Index].RegionBaseAddress + FlashDevices[Index].Size);
+
+ Status = FlashCreateInstance (
+ FlashDevices[Index].DeviceBaseAddress,
+ FlashDevices[Index].RegionBaseAddress,
+ FlashDevices[Index].Size,
+ Index,
+ FlashDevices[Index].BlockSize,
+ ContainVariableStorage,
+ &FlashDevices[Index].Guid,
+ &mFlashInstances[Index]
+ );
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Fail to create instance for Flash[%d]\n", __FUNCTION__, __LINE__, Index));
+ }
+ }
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ FlashFvbVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mFlashFvbVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.h b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.h
new file mode 100644
index 0000000..76385b6
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.h
@@ -0,0 +1,228 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef __FLASH_FVB_DXE_H__
+#define __FLASH_FVB_DXE_H__
+
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/HobLib.h>
+#include <Protocol/BlockIo.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+#include <Library/DebugLib.h>
+
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/HisiSpiFlashProtocol.h>
+
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include <Guid/VariableFormat.h>
+#include <Guid/SystemNvDataGuid.h>
+
+
+#define FLASH_ERASE_RETRY 10
+#define FLASH_DEVICE_COUNT 1
+
+// Device access macros
+// These are necessary because we use 2 x 16bit parts to make up 32bit data
+typedef struct
+{
+ UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
+ UINTN RegionBaseAddress; // Start address of one single region
+ UINTN Size;
+ UINTN BlockSize;
+ EFI_GUID Guid;
+} FLASH_DESCRIPTION;
+
+#define GET_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) )
+
+#define FLASH_SIGNATURE SIGNATURE_32('s', 'p', 'i', '0')
+#define INSTANCE_FROM_FVB_THIS(a) CR(a, FLASH_INSTANCE, FvbProtocol, FLASH_SIGNATURE)
+#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, FLASH_INSTANCE, BlockIoProtocol, FLASH_SIGNATURE)
+
+typedef struct _FLASH_INSTANCE FLASH_INSTANCE;
+
+typedef EFI_STATUS (*FLASH_INITIALIZE) (FLASH_INSTANCE* Instance);
+
+typedef struct
+{
+ VENDOR_DEVICE_PATH Vendor;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} FLASH_DEVICE_PATH;
+
+struct _FLASH_INSTANCE
+{
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+
+ BOOLEAN Initialized;
+ FLASH_INITIALIZE Initialize;
+
+ UINTN DeviceBaseAddress;
+ UINTN RegionBaseAddress;
+ UINTN Size;
+ EFI_LBA StartLba;
+
+ EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
+ EFI_BLOCK_IO_MEDIA Media;
+
+ BOOLEAN SupportFvb;
+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
+
+ FLASH_DEVICE_PATH DevicePath;
+};
+
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL* This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID* Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL* This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID* Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL* This
+);
+
+
+//
+// FvbHw.c
+//
+
+EFI_STATUS
+EFIAPI
+FvbInitialize (
+ IN FLASH_INSTANCE* Instance
+);
+
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ OUT EFI_FVB_ATTRIBUTES_2* Attributes
+);
+
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN OUT EFI_FVB_ATTRIBUTES_2* Attributes
+);
+
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ OUT EFI_PHYSICAL_ADDRESS* Address
+);
+
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN EFI_LBA Lba,
+ OUT UINTN* BlockSize,
+ OUT UINTN* NumberOfBlocks
+);
+
+EFI_STATUS
+EFIAPI
+FvbRead(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN* NumBytes,
+ IN OUT UINT8* Buffer
+);
+
+EFI_STATUS
+EFIAPI
+FvbWrite(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN* NumBytes,
+ IN UINT8* Buffer
+);
+
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ ...
+);
+
+//
+// FlashFvbDxe.c
+//
+
+EFI_STATUS
+FlashUnlockAndEraseSingleBlock (
+ IN FLASH_INSTANCE* Instance,
+ IN UINTN BlockAddress
+);
+
+EFI_STATUS
+FlashWriteBlocks (
+ IN FLASH_INSTANCE* Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID* Buffer
+);
+
+EFI_STATUS
+FlashReadBlocks (
+ IN FLASH_INSTANCE* Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID* Buffer
+);
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
new file mode 100644
index 0000000..aa9c288
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
@@ -0,0 +1,69 @@
+#/** @file
+#
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FlashFvbDxe
+ FILE_GUID = 93E34C7E-B50E-11DF-9223-2443DFD72085
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = FlashFvbInitialize
+
+[Sources.common]
+ FlashFvbDxe.c
+ FlashBlockIoDxe.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ IoLib
+ BaseLib
+ DebugLib
+ HobLib
+ UefiLib
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiRuntimeLib
+
+[Guids]
+ gEfiSystemNvDataFvGuid
+ gEfiVariableGuid
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEfiFirmwareVolumeBlockProtocolGuid
+ gHisiSpiFlashProtocolGuid
+
+[Pcd.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+ gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked
+
+[Depex]
+ gHisiSpiFlashProtocolGuid
+
+[BuildOptions]
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashConfig.c b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashConfig.c
new file mode 100644
index 0000000..ab3b70c
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashConfig.c
@@ -0,0 +1,162 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include "NorFlashHw.h"
+
+
+#define COMMAND_TYPE1 0x1
+#define COMMAND_TYPE2 0x2
+#define COMMAND_TYPE3 0x4
+#define COMMAND_TYPE4 0x8
+#define COMMAND_TYPE5 0x10
+
+
+NOR_FLASH_INFO_TABLE gFlashInfo[]=
+{
+
+ {//S29GL512m
+ 0x00010001,
+ 0x227E227E,
+ 0x22232223,
+ 0x22012201,
+ 1,
+ 0x20000000,
+ 0x20000,
+ 0x0010,
+ COMMAND_TYPE1
+ },
+ {//S29GL1g
+ 0x00010001,
+ 0x227E227E,
+ 0x22282228,
+ 0x22012201,
+ 1,
+ 0x40000000,
+ 0x20000,
+ 0x0020,
+ COMMAND_TYPE1
+ },
+ {//M29ew512m
+ 0x00890089,
+ 0x227E227E,
+ 0x22232223,
+ 0x22012201,
+ 1,
+ 0x20000000,
+ 0x20000,
+ 0x0010,
+ COMMAND_TYPE1
+ },
+ {//M29EW2g
+ 0x00890089,
+ 0x227E227E,
+ 0x22482248,
+ 0x22012201,
+ 1,
+ 0x80000000,
+ 0x20000,
+ 0x0020,
+ COMMAND_TYPE1
+ },
+ {
+ 0x00890089,
+ 0x227E227E,
+ 0x22282228,
+ 0x22012201,
+ 1,
+ 0x10000000,
+ 0x20000,
+ 0x0020,
+ COMMAND_TYPE1
+ },
+ {
+ 0x00890089,
+ 0x227E227E,
+ 0x22282228,
+ 0x22012201,
+ 2,
+ 0x10000000,
+ 0x20000,
+ 0x0020,
+ COMMAND_TYPE1
+ }
+};
+
+
+
+FLASH_COMMAND_RESET gFlashCommandReset[]=
+{
+ {
+ COMMAND_TYPE1,
+ (0x00F000F0)
+ }
+
+};
+
+
+FLASH_COMMAND_ID gFlashCommandId[]=
+{
+ {
+ COMMAND_TYPE1,
+ (0x0555),
+ (0x00AA00AA),
+ (0x02AA),
+ (0x00550055),
+ (0x0555),
+ (0x00900090),
+ (0x0000),
+
+ (0x0001),
+ (0x000E),
+ (0x000F)
+ }
+};
+
+
+FLASH_COMMAND_WRITE gFlashCommandWrite[]=
+{
+ {
+ COMMAND_TYPE1,
+ (0x0555),
+ (0x00AA00AA),
+ (0x02AA),
+ (0x00550055),
+ (0x00250025),
+ (0x00290029)
+ }
+
+};
+
+
+FLASH_COMMAND_ERASE gFlashCommandErase[]=
+{
+ {
+ COMMAND_TYPE1,
+ (0x0555),
+ (0x00AA00AA),
+ (0x02AA),
+ (0x00550055),
+ (0x0555),
+ (0x00800080),
+ (0x0555),
+ (0x00AA00AA),
+ (0x02AA),
+ (0x00550055),
+ (0x00300030)
+ }
+
+};
+
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.c b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.c
new file mode 100644
index 0000000..8b8a5d7
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.c
@@ -0,0 +1,594 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <Protocol/NorFlashProtocol.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Protocol/Cpu.h>
+#include "NorFlashHw.h"
+
+
+EFI_STATUS Erase(
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT32 Length
+ );
+
+EFI_STATUS Write(
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ UINT32 ulLength
+ );
+
+EFI_STATUS Read(
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Buffer,
+ IN UINT32 ulLen
+ );
+
+UNI_NOR_FLASH_PROTOCOL gUniNorFlash = {
+ Erase,
+ Write,
+ Read
+};
+
+
+EFI_STATUS
+EFIAPI Read(
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Buffer,
+ IN UINT32 ulLen
+ )
+{
+ UINT32 index;
+ UINT64 ullAddr;
+ UINT32 ullCnt = 0;
+ UINT32 *puiBuffer32 = NULL;
+ UINT32 *puiDst32 = NULL;
+ UINT8 *pucBuffer8 = NULL;
+ UINT8 *pucDst8 = NULL;
+
+ if (Offset + ulLen > (gFlashInfo[gIndex.InfIndex].SingleChipSize * gFlashInfo[gIndex.InfIndex].ParallelNum))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Exceed the flash scope!\n", __FUNCTION__,__LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+ if (0 == ulLen)
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Length is Zero!\n", __FUNCTION__,__LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+ if (NULL == Buffer)
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Buffer is NULL!\n", __FUNCTION__,__LINE__));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+
+ ullAddr = gIndex.Base + Offset;
+
+ pucBuffer8 = (UINT8 *)Buffer;
+ pucDst8 = (UINT8 *)((UINTN)ullAddr);
+
+
+ if (ulLen < FOUR_BYTE_UNIT)
+ {
+ for(index = 0; index< ulLen; index++)
+ {
+ *pucBuffer8++ = *pucDst8++;
+ }
+ }
+ else
+ {
+
+ ullCnt = Offset % FOUR_BYTE_UNIT;
+ ullCnt = FOUR_BYTE_UNIT - ullCnt;
+
+ for(index = 0; index < ullCnt; index++)
+ {
+ *pucBuffer8++ = *pucDst8++;
+ }
+
+ ulLen -= ullCnt;
+
+ puiBuffer32 = (UINT32 *)pucBuffer8;
+ puiDst32 = (UINT32 *)pucDst8;
+ ullCnt = ulLen / FOUR_BYTE_UNIT;
+
+ for(index = 0; index < ullCnt; index++)
+ {
+ *puiBuffer32++ = *puiDst32++;
+ }
+
+ ullCnt = ulLen % FOUR_BYTE_UNIT;
+ pucBuffer8 = (UINT8 *)puiBuffer32;
+ pucDst8 = (UINT8 *)puiDst32;
+
+ for(index = 0; index < ullCnt; index++)
+ {
+ *pucBuffer8++ = *pucDst8++;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+
+static EFI_STATUS WriteAfterErase_Fill(
+ IN const UINT32 Offset,
+ IN const UINT8 *Buffer,
+ IN const UINT32 Length
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Loop;
+ UINT32 DataOffset;
+ UINT32 NewOffset;
+ UINT8 *NewDataUnit;
+
+ UINT32 FlashUnitLength;
+
+ FlashUnitLength = gFlashInfo[gIndex.InfIndex].BufferProgramSize << gFlashInfo[gIndex.InfIndex].ParallelNum;
+
+ if (0 == Length)
+ {
+ return EFI_SUCCESS;
+ }
+ if ((Offset % FlashUnitLength + Length) > FlashUnitLength)
+ {
+ DEBUG ((EFI_D_INFO, "[%a]:[%dL]:Exceed the Flash Size!\n", __FUNCTION__,__LINE__));
+ return EFI_UNSUPPORTED;
+ }
+
+
+ Status = gBS->AllocatePool(EfiBootServicesData, FlashUnitLength, (VOID *)&NewDataUnit);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Allocate Pool failed, %r!\n", __FUNCTION__,__LINE__, Status));
+ return Status;
+ }
+
+
+ NewOffset = Offset - (Offset % FlashUnitLength);
+
+ gBS->CopyMem((VOID *)NewDataUnit, (VOID *)(UINTN)(gIndex.Base + NewOffset), FlashUnitLength);
+
+ DataOffset = Offset % FlashUnitLength;
+ for (Loop = 0; Loop < Length; Loop ++)
+ {
+ NewDataUnit[(UINT32)(DataOffset + Loop)] = Buffer[Loop];
+ }
+
+ Status = BufferWrite(NewOffset, (void *)NewDataUnit, FlashUnitLength);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:BufferWrite %r!\n", __FUNCTION__,__LINE__, Status));
+ return Status;
+ }
+
+ (void)gBS->FreePool((VOID *)NewDataUnit);
+ return Status;
+}
+
+
+static EFI_STATUS WriteAfterErase_Final(
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ IN UINT32 Length
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Loop;
+ UINT32 FlashUnitLength;
+
+ FlashUnitLength = gFlashInfo[gIndex.InfIndex].BufferProgramSize << gFlashInfo[gIndex.InfIndex].ParallelNum;
+
+ if (0 == Length)
+ {
+ return EFI_SUCCESS;
+ }
+
+ if (0 != (Offset % FlashUnitLength))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: Offset must be a multiple of 0x%x!\n", __FUNCTION__,__LINE__,FlashUnitLength));
+ return EFI_UNSUPPORTED;
+ }
+
+
+ Loop = Length / FlashUnitLength;
+ while (Loop --)
+ {
+ Status = BufferWrite(Offset, (void *)Buffer, FlashUnitLength);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:BufferWrite Failed: %r!\n", __FUNCTION__,__LINE__, Status));
+ return EFI_DEVICE_ERROR;
+ }
+ Offset += FlashUnitLength;
+ Buffer += FlashUnitLength;
+ }
+
+
+ Length = Length % FlashUnitLength;
+ if (Length)
+ {
+ Status = WriteAfterErase_Fill(Offset, Buffer, Length);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:WriteAfterErase_Fill failed,%r!\n", __FUNCTION__,__LINE__, Status));
+ return Status;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+WriteAfterErase(
+ UINT32 TempBase,
+ UINT32 Offset,
+ UINT8 *Buffer,
+ UINT32 Length
+ )
+{
+ EFI_STATUS Status;
+ UINT32 FlashUnitLength;
+
+ FlashUnitLength = gFlashInfo[gIndex.InfIndex].BufferProgramSize << gFlashInfo[gIndex.InfIndex].ParallelNum;
+
+ if (0 == Length)
+ {
+ return EFI_SUCCESS;
+ }
+
+
+ if (Offset % FlashUnitLength)
+ {
+ UINT32 TempLength;
+
+
+ TempLength = FlashUnitLength - (Offset % FlashUnitLength);
+ if (TempLength > Length)
+ {
+ TempLength = Length;
+ }
+ Status = WriteAfterErase_Fill(Offset, Buffer, TempLength);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: %r!\n", __FUNCTION__,__LINE__, Status));
+ return Status;
+ }
+
+ Offset += TempLength;
+ Length -= TempLength;
+ Buffer += TempLength;
+
+ //Desc:if Offset >= gOneFlashSize,modify base
+ if (0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+ {
+ TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize;
+ gIndex.Base = TempBase;
+ Offset = 0;
+ }
+ }
+
+
+ Status = WriteAfterErase_Final(Offset, Buffer, Length);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: %r!\n", __FUNCTION__,__LINE__, Status));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+FlashSectorErase(
+ UINT32 TempBase,
+ UINT32 Offset,
+ UINT32 Length
+ )
+{
+ EFI_STATUS Status;
+ UINT32 SectorOffset;
+ UINT8 *StaticBuffer;
+ UINT8 *Buffer;
+ UINT32 TempOffset;
+ UINT32 TempLength;
+ UINT32 LeftLength;
+
+
+ if (0 == Length)
+ {
+ return EFI_SUCCESS;
+ }
+
+ LeftLength = gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum));
+ if (LeftLength < Length)
+ {
+ return EFI_UNSUPPORTED;
+ }
+
+
+ SectorOffset = Offset - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum));
+
+ Status = gBS->AllocatePool(EfiBootServicesData, gFlashInfo[gIndex.InfIndex].BlockSize * (UINTN)gFlashInfo[gIndex.InfIndex].ParallelNum, (VOID *)&StaticBuffer);
+ if (EFI_ERROR(Status))
+ {
+ return Status;
+ }
+
+ Buffer = StaticBuffer;
+
+ gBS->CopyMem((VOID *)Buffer, (VOID *)(UINTN)(TempBase + SectorOffset),
+ (gFlashInfo[gIndex.InfIndex].BlockSize * (UINTN)gFlashInfo[gIndex.InfIndex].ParallelNum));
+
+
+ Status = SectorErase(TempBase, SectorOffset);
+ if (EFI_ERROR(Status))
+ {
+ goto DO;
+ }
+
+
+ TempOffset = SectorOffset;
+ TempLength = Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum);
+
+ Status = WriteAfterErase(TempBase, TempOffset, Buffer, TempLength);
+ if (EFI_ERROR(Status))
+ {
+ goto DO;
+ }
+
+
+ Buffer = Buffer + TempLength + Length;
+ TempOffset = Offset + Length;
+ TempLength = SectorOffset + (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum) - TempOffset;
+
+ Status = WriteAfterErase(TempBase, TempOffset, Buffer, TempLength);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: %r!\n", __FUNCTION__,__LINE__,Status));
+ goto DO;
+ }
+
+ (void)gBS->FreePool((VOID *)StaticBuffer);
+ return EFI_SUCCESS;
+
+DO:
+ (void)gBS->FreePool((VOID *)StaticBuffer);
+ return Status;
+}
+
+
+EFI_STATUS
+EFIAPI Erase(
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT32 Length
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 Sectors;
+ UINT32 TempLength;
+ UINT32 TempBase;
+ UINT32 Loop;
+
+
+ if (Offset + Length > (gFlashInfo[gIndex.InfIndex].SingleChipSize * gFlashInfo[gIndex.InfIndex].ParallelNum))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Exceed the Flash Size!\n", __FUNCTION__,__LINE__));
+ return EFI_ABORTED;
+ }
+ if (0 == Length)
+ {
+ return EFI_SUCCESS;
+ }
+
+
+ Sectors = ((Offset + Length - 1) / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) - (Offset / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) + 1;
+ TempBase = gIndex.Base;
+
+ //if Offset >= gOneFlashSize,modify base
+ if(0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+ {
+ TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize * (Offset/gFlashInfo[gIndex.InfIndex].SingleChipSize);
+ Offset = Offset - (Offset & gFlashInfo[gIndex.InfIndex].SingleChipSize);
+ }
+
+ for (Loop = 0; Loop <= Sectors; Loop ++)
+ {
+
+ TempLength = gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum));
+
+
+ if (TempLength > Length)
+ {
+ TempLength = Length;
+ }
+
+ Status = FlashSectorErase(TempBase, Offset, TempLength);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: FlashErase One Sector Error, Status = %r!\n", __FUNCTION__,__LINE__,Status));
+ return Status;
+ }
+
+ Offset += TempLength;
+
+ //if Offset >= gOneFlashSize,modify base
+ if (0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+ {
+ TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize;
+ Offset = 0;
+ }
+ Length -= TempLength;
+ }
+
+ return Status;
+}
+
+
+EFI_STATUS
+EFIAPI Write(
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ UINT32 ulLength
+ )
+{
+ EFI_STATUS Status;
+ UINT32 TempLength;
+ UINT32 TempBase;
+ UINT32 Loop;
+ UINT32 Sectors;
+
+ if((Offset + ulLength) > (gFlashInfo[gIndex.InfIndex].SingleChipSize * gFlashInfo[gIndex.InfIndex].ParallelNum))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Exceed the Flash Size!\n", __FUNCTION__,__LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+ if (0 == ulLength)
+ {
+ return EFI_SUCCESS;
+ }
+
+
+ Sectors = ((Offset + ulLength - 1) / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) - (Offset / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) + 1;
+ TempBase = gIndex.Base;
+
+ //if Offset >= gOneFlashSize,modify base
+ if(0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+ {
+ TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize * (Offset/gFlashInfo[gIndex.InfIndex].SingleChipSize);
+ Offset = Offset - (Offset & gFlashInfo[gIndex.InfIndex].SingleChipSize);
+ }
+
+ for (Loop = 0; Loop <= Sectors; Loop ++)
+ {
+
+ TempLength = gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum));
+
+
+ if (TempLength > ulLength)
+ {
+ TempLength = ulLength;
+ }
+
+
+ if (TRUE == IsNeedToWrite(TempBase, Offset, Buffer, TempLength))
+ {
+ Status = FlashSectorErase(TempBase, Offset, TempLength);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:FlashErase One Sector Error, Status = %r!\n", __FUNCTION__,__LINE__,Status));
+ return Status;
+ }
+
+
+ Status = WriteAfterErase(TempBase, Offset, Buffer, TempLength);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:WriteAfterErase Status = %r!\n", __FUNCTION__,__LINE__,Status));
+ return Status;
+ }
+ }
+
+ Offset += TempLength;
+ Buffer += TempLength;
+
+ //if Offset >= gOneFlashSize,modify base
+ if (0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+ {
+ TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize;
+ Offset = 0;
+ }
+ ulLength -= TempLength;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+VOID SetFlashAttributeToUncache(VOID)
+{
+ EFI_CPU_ARCH_PROTOCOL *gCpu = NULL;
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "LocateProtocol gEfiCpuArchProtocolGuid Status = %r !\n", Status));
+ }
+
+ Status = gCpu->SetMemoryAttributes(
+ gCpu,
+ PcdGet64(PcdNORFlashBase),
+ PcdGet32(PcdNORFlashCachableSize),
+ EFI_MEMORY_UC
+ );
+
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "gCpu->SetMemoryAttributes Status = %r !\n", Status));
+ }
+
+}
+
+EFI_STATUS
+EFIAPI InitializeFlash (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable)
+{
+ EFI_STATUS Status;
+
+
+ gIndex.Base = (UINT32)PcdGet64(PcdNORFlashBase);
+
+ SetFlashAttributeToUncache();
+ Status = FlashInit(gIndex.Base);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "Init Flash Error !\n"));
+ return Status;
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR, "Init Flash OK!\n"));
+ }
+
+ Status = gBS->InstallProtocolInterface (
+ &ImageHandle,
+ &gUniNorFlashProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &gUniNorFlash);
+ if(EFI_SUCCESS != Status)
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Install Protocol Interface %r!\n", __FUNCTION__,__LINE__,Status));
+ }
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf
new file mode 100644
index 0000000..ef942f2
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = NorFlashDxe
+ FILE_GUID = E29977F9-20A4-4551-B0EC-BCE246592E73
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeFlash
+
+[Sources.common]
+ NorFlashDxe.c
+ NorFlashHw.c
+ NorFlashConfig.c
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ DebugLib
+ BaseLib
+ DebugLib
+ IoLib
+ SerialPortLib
+ ArmLib
+ CacheMaintenanceLib
+ UefiLib
+ PrintLib
+ PcdLib
+
+ DxeServicesTableLib
+[Guids]
+
+[Protocols]
+ gUniNorFlashProtocolGuid
+ gEfiCpuArchProtocolGuid
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdNORFlashBase
+ gHisiTokenSpaceGuid.PcdNORFlashCachableSize
+
+
+[Depex]
+ TRUE
+
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.c b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.c
new file mode 100644
index 0000000..3aeaeb9
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.c
@@ -0,0 +1,628 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/IoLib.h>
+#include "NorFlashHw.h"
+
+
+BOOLEAN gFlashBusy = FALSE;
+FLASH_INDEX gIndex = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+};
+
+
+UINT32 PortReadData (
+ UINT32 Index,
+ UINT32 FlashAddr
+ )
+{
+
+ switch (gFlashInfo[Index].ParallelNum)
+ {
+ case 2:
+ return MmioRead32 (FlashAddr);
+ case 1:
+ return MmioRead16 (FlashAddr);
+
+ default:
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:illegal PortWidth!\n", __FUNCTION__,__LINE__));
+ return 0xffffffff;
+ }
+}
+
+EFI_STATUS
+PortWriteData (
+ UINT32 Index,
+ UINT32 FlashAddr,
+ UINT32 InputData
+ )
+{
+
+ switch (gFlashInfo[Index].ParallelNum)
+ {
+ case 2:
+ MmioWrite32 (FlashAddr, InputData);
+ break;
+ case 1:
+ MmioWrite16 (FlashAddr, InputData);
+ break;
+ default:
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:illegal PortWidth!\n", __FUNCTION__,__LINE__));
+ return EFI_DEVICE_ERROR;
+ }
+ return EFI_SUCCESS;
+}
+
+UINT32 PortAdjustData(
+ UINT32 Index,
+ UINT32 ulInputData
+ )
+{
+
+ switch (gFlashInfo[Index].ParallelNum)
+ {
+ case 2:
+ return ulInputData;
+ case 1:
+ return (0x0000ffff & ulInputData );
+ default:
+ DEBUG((EFI_D_ERROR,"[FLASH_S29GL256N_PortAdjustData]: Error--illegal g_ulFlashS29Gl256NPortWidth!\n\r"));
+ return 0xffffffff;
+ }
+}
+
+
+EFI_STATUS GetCommandIndex(
+ UINT32 Index
+ )
+{
+ UINT32 CommandCount = 0;
+ UINT32 i;
+ UINT8 Flag = 1;
+
+ CommandCount = sizeof(gFlashCommandReset) / sizeof(FLASH_COMMAND_RESET);
+ for(i = 0;i < CommandCount; i ++ )
+ {
+ if(gFlashInfo[Index].CommandType & gFlashCommandReset[i].CommandType)
+ {
+ Flag = 0;
+ gIndex.ReIndex = i;
+ break;
+ }
+ }
+
+ if(Flag)
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Can not Get Reset Command!\n", __FUNCTION__,__LINE__));
+ return EFI_DEVICE_ERROR;
+ }
+
+ CommandCount = sizeof(gFlashCommandId) / sizeof(FLASH_COMMAND_ID);
+ for(Flag = 1,i = 0;i < CommandCount; i ++ )
+ {
+ if(gFlashInfo[Index].CommandType & gFlashCommandId[i].CommandType)
+ {
+ Flag = 0;
+ gIndex.IdIndex = i;
+ break;
+ }
+ }
+
+ if(Flag)
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Can not Get ID Command!\n", __FUNCTION__,__LINE__));
+ return EFI_DEVICE_ERROR;
+ }
+
+ CommandCount = sizeof(gFlashCommandWrite) / sizeof(FLASH_COMMAND_WRITE);
+ for(Flag = 1, i = 0;i < CommandCount; i ++ )
+ {
+ if(gFlashInfo[Index].CommandType & gFlashCommandWrite[i].CommandType)
+ {
+ Flag = 0;
+ gIndex.WIndex = i;
+ break;
+ }
+ }
+
+ if(Flag)
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Can not Get Write Command!\n", __FUNCTION__,__LINE__));
+ return EFI_DEVICE_ERROR;
+ }
+
+ CommandCount = sizeof(gFlashCommandErase) / sizeof(FLASH_COMMAND_ERASE);
+ for(Flag = 1, i = 0;i < CommandCount; i ++ )
+ {
+ if(gFlashInfo[Index].CommandType & gFlashCommandErase[i].CommandType)
+ {
+ Flag = 0;
+ gIndex.WIndex = i;
+ break;
+ }
+ }
+
+ if(Flag)
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Can not Get Erase Command!\n", __FUNCTION__,__LINE__));
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+VOID FlashReset(UINT32 Base)
+{
+ (VOID)PortWriteData(gIndex.InfIndex, Base, gFlashCommandReset[gIndex.ReIndex].ResetData);
+ (void)gBS->Stall(20000);
+}
+
+
+void GetManufacturerID(UINT32 Index, UINT32 Base, UINT8 *pbyData)
+{
+
+ UINT32 dwAddr;
+
+ FlashReset(Base);
+
+ dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep1 << gFlashInfo[Index].ParallelNum);
+ (VOID)PortWriteData(Index, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep1);
+
+ dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep2 << gFlashInfo[Index].ParallelNum);
+ (VOID)PortWriteData(Index, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep2);
+
+ dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep3 << gFlashInfo[Index].ParallelNum);
+ (VOID)PortWriteData(Index, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep3);
+
+ *pbyData = (UINT8)PortReadData(Index, Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddress << gFlashInfo[Index].ParallelNum));
+
+ FlashReset(Base); //must reset to return to the read mode
+}
+
+
+EFI_STATUS FlashInit(UINT32 Base)
+{
+ UINT32 FlashCount = 0;
+ UINT32 i = 0;
+ EFI_STATUS Status;
+ UINT8 Flag = 1;
+ UINT32 TempData = 0;
+ UINT32 TempDev1 = 0;
+ UINT32 TempDev2 = 0;
+ UINT32 TempDev3 = 0;
+ UINT32 dwAddr;
+
+ FlashCount = sizeof(gFlashInfo) / sizeof(NOR_FLASH_INFO_TABLE);
+ for(;i < FlashCount; i ++ )
+ {
+
+ Status = GetCommandIndex(i);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Get Command Index %r!\n", __FUNCTION__,__LINE__, Status));
+ return Status;
+ }
+
+ FlashReset(Base);
+
+ dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep1 << gFlashInfo[i].ParallelNum);
+ (VOID)PortWriteData(i, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep1);
+
+ dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep2 << gFlashInfo[i].ParallelNum);
+ (VOID)PortWriteData(i, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep2);
+
+ dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep3 << gFlashInfo[i].ParallelNum);
+ (VOID)PortWriteData(i, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep3);
+ //Get manufacture ID
+ TempData = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddress << gFlashInfo[i].ParallelNum));
+
+ //Get Device Id
+ TempDev1 = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].DeviceIDAddress1 << gFlashInfo[i].ParallelNum));
+ TempDev2 = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].DeviceIDAddress2 << gFlashInfo[i].ParallelNum));
+ TempDev3 = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].DeviceIDAddress3 << gFlashInfo[i].ParallelNum));
+ DEBUG ((EFI_D_ERROR, "[cdtest]manufactor ID 0x%x!\n",TempData));
+ DEBUG ((EFI_D_ERROR, "[cdtest]Device ID 1 0x%x!\n",TempDev1));
+ DEBUG ((EFI_D_ERROR, "[cdtest]Device ID 2 0x%x!\n",TempDev2));
+ DEBUG ((EFI_D_ERROR, "[cdtest]Device ID 3 0x%x!\n",TempDev3));
+
+ FlashReset(Base);
+
+
+ if((0xffffffff != TempData)
+ && (PortAdjustData(i, gFlashInfo[i].ManufacturerID) == TempData))
+ {
+ if((0xffffffff != TempDev1)
+ && (PortAdjustData(i, gFlashInfo[i].DeviceID1) == TempDev1))
+ {
+ if((0xffffffff != TempDev2)
+ && (PortAdjustData(i, gFlashInfo[i].DeviceID2) == TempDev2))
+ {
+ if((0xffffffff != TempDev3)
+ && (PortAdjustData(i, gFlashInfo[i].DeviceID3) == TempDev3))
+ {
+ Flag = 0;
+ gIndex.InfIndex = i;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ if(Flag)
+ {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+static BOOLEAN width8IsAll(
+ const UINT64 Base,
+ const UINT64 Offset,
+ const UINT64 Length,
+ const UINT8 Value
+)
+{
+ UINT64 NewAddr = Base + Offset;
+ UINT64 NewLength = Length;
+ while (NewLength --)
+ {
+ if (*(UINT8 *)(UINTN)NewAddr == Value)
+ {
+ NewAddr ++;
+ continue;
+ }
+ else
+ {
+ return FALSE;
+ }
+ }
+ return TRUE;
+}
+
+
+
+EFI_STATUS BufferWriteCommand(UINTN Base, UINTN Offset, void *pData)
+{
+ UINT32 dwCommAddr;
+ UINT32 *pdwData;
+ UINT16 *pwData;
+ UINT32 dwLoop;
+ UINT32 ulWriteWordCount;
+ UINT32 dwAddr;
+
+ if(gFlashBusy)
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL]:Flash is busy!\n", __FUNCTION__,__LINE__));
+ return EFI_NOT_READY;
+ }
+ gFlashBusy = TRUE;
+
+ if(2 == gFlashInfo[gIndex.InfIndex].ParallelNum)
+ {
+ pdwData = (UINT32 *)pData;
+
+ dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep1 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep1);
+
+ dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep2 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep2);
+
+ //dwAddr = Base + (Offset << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ dwAddr = (UINT32)Base + Offset;
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep3);
+
+
+ ulWriteWordCount = ((gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1) << 16) | (gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, ulWriteWordCount);
+
+
+ for (dwLoop = 0; dwLoop < gFlashInfo[gIndex.InfIndex].BufferProgramSize; dwLoop ++)
+ {
+ dwCommAddr = (UINT32)Base + (UINT32)Offset + (dwLoop << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ MmioWrite32 (dwCommAddr, *pdwData);
+ pdwData ++;
+ }
+
+ dwAddr = (UINT32)Base + (UINT32)Offset + ((gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1) << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramtoFlash);
+
+
+
+ }
+ else
+ {
+ pwData = (UINT16 *)pData;
+
+ dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep1 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep1);
+
+ dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep2 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep2);
+
+ //dwAddr = Base + (Offset << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ dwAddr = (UINT32)Base + Offset;
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep3);
+
+
+ ulWriteWordCount = gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1;
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, ulWriteWordCount);
+
+
+ for (dwLoop = 0; dwLoop < gFlashInfo[gIndex.InfIndex].BufferProgramSize; dwLoop ++)
+ {
+ dwCommAddr = (UINT32)Base + (UINT32)Offset + (dwLoop << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ MmioWrite16 (dwCommAddr, *pwData);
+ pwData ++;
+ }
+
+ dwAddr = (UINT32)Base + (UINT32)Offset + ((gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1) << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramtoFlash);
+
+ }
+
+ (void)gBS->Stall(200);
+
+ gFlashBusy = FALSE;
+ return EFI_SUCCESS;
+
+}
+
+
+EFI_STATUS SectorEraseCommand(UINTN Base, UINTN Offset)
+{
+ UINT32 dwAddr;
+
+ if(gFlashBusy)
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL]:Flash is busy!\n", __FUNCTION__,__LINE__));
+ return EFI_NOT_READY;
+ }
+
+ gFlashBusy = TRUE;
+
+ dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep1 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep1);
+
+ dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep2 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep2);
+
+ dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep3 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep3);
+
+ dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep4 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep4);
+
+ dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep5 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep5);
+
+ dwAddr = (UINT32)Base + Offset;
+ (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep6);
+
+ (void)gBS->Stall(500000);
+
+ gFlashBusy = FALSE;
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS CompleteCheck(UINT32 Base, UINT32 Offset, void *pData, UINT32 Length)
+{
+ UINT32 dwTestAddr;
+ UINT32 dwTestData;
+ UINT32 dwTemp = 0;
+ UINT32 dwTemp1 = 0;
+ UINT32 i;
+ UINT32 dwTimeOut = 3000000;
+
+ if(gFlashBusy)
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL]:Flash is busy!\n", __FUNCTION__,__LINE__));
+ return EFI_NOT_READY;
+ }
+ gFlashBusy = TRUE;
+
+ if(2 == gFlashInfo[gIndex.InfIndex].ParallelNum)
+ {
+ dwTestAddr = Base + Offset + Length - sizeof(UINT32);
+ dwTestData = *((UINT32 *)((UINT8 *)pData + Length - sizeof(UINT32)));
+
+ while(dwTimeOut--)
+ {
+ dwTemp1 = MmioRead32 (dwTestAddr);
+ if (dwTestData == dwTemp1)
+ {
+ dwTemp = MmioRead32 (dwTestAddr);
+ dwTemp1 = MmioRead32 (dwTestAddr);
+ if ((dwTemp == dwTemp1) && (dwTestData == dwTemp1))
+ {
+ gFlashBusy = FALSE;
+ return EFI_SUCCESS;
+ }
+ }
+
+ (void)gBS->Stall(1);
+ }
+
+ if((UINT16)(dwTemp1 >> 16) != (UINT16)(dwTestData >> 16))
+ {
+ DEBUG((EFI_D_ERROR, "CompleteCheck ERROR: chip1 address %x, buffer %x, flash %x!\n", Offset, dwTestData, dwTemp1));
+ }
+ if((UINT16)(dwTemp1) != (UINT16)(dwTestData))
+ {
+ DEBUG((EFI_D_ERROR, "CompleteCheck ERROR: chip2 address %x, buffer %x, flash %x!\n", Offset, dwTestData, dwTemp1));
+ }
+ }
+ else
+ {
+ dwTestAddr = Base + Offset + Length - sizeof(UINT16);
+ dwTestData = *((UINT16 *)((UINT8 *)pData + Length - sizeof(UINT16)));
+
+ while(dwTimeOut--)
+ {
+ dwTemp1 = MmioRead16 (dwTestAddr);
+ if (dwTestData == dwTemp1)
+ {
+ dwTemp = MmioRead16 (dwTestAddr);
+ dwTemp1 = MmioRead16 (dwTestAddr);
+ if ((dwTemp == dwTemp1) && (dwTestData == dwTemp1))
+ {
+ gFlashBusy = FALSE;
+ return EFI_SUCCESS;
+ }
+ }
+
+ (void)gBS->Stall(1);
+ }
+ }
+
+ for(i = 0; i < 5; i ++)
+ {
+ DEBUG((EFI_D_ERROR, "CompleteCheck ERROR: flash %x\n",PortReadData(gIndex.InfIndex, dwTestAddr)));
+ }
+
+ FlashReset(Base);
+
+ gFlashBusy = FALSE;
+ DEBUG((EFI_D_ERROR, "CompleteCheck ERROR: timeout address %x, buffer %x, flash %x\n", Offset, dwTestData, dwTemp1));
+ return EFI_TIMEOUT;
+}
+
+EFI_STATUS IsNeedToWrite(
+ IN UINT32 Base,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ IN UINT32 Length
+ )
+{
+ UINTN NewAddr = Base + Offset;
+ UINT8 FlashData = 0;
+ UINT8 BufferData = 0;
+
+ for(; Length > 0; Length --)
+ {
+ BufferData = *Buffer;
+ //lint -epn -e511
+ FlashData = *(UINT8 *)NewAddr;
+ if (BufferData != FlashData)
+ {
+ return TRUE;
+ }
+ NewAddr ++;
+ Buffer ++;
+ }
+
+ return FALSE;
+}
+
+
+EFI_STATUS BufferWrite(UINT32 Offset, void *pData, UINT32 Length)
+{
+ EFI_STATUS Status;
+ UINT32 dwLoop;
+ UINT32 Retry = 3;
+
+ if (FALSE == IsNeedToWrite(gIndex.Base, Offset, (UINT8 *)pData, Length))
+ {
+ return EFI_SUCCESS;
+ }
+
+ do
+ {
+ (void)BufferWriteCommand(gIndex.Base, Offset, pData);
+ Status = CompleteCheck(gIndex.Base, Offset, pData, Length);
+
+
+ if (EFI_SUCCESS == Status)
+ {
+ for (dwLoop = 0; dwLoop < Length; dwLoop ++)
+ {
+ if (*(UINT8 *)(UINTN)(gIndex.Base + Offset + dwLoop) != *((UINT8 *)pData + dwLoop))
+ {
+ DEBUG((EFI_D_ERROR, "Flash_WriteUnit ERROR: address %x, buffer %x, flash %x\n", Offset, *((UINT8 *)pData + dwLoop), *(UINT8 *)(UINTN)(gIndex.Base + Offset + dwLoop)));
+ Status = EFI_ABORTED;
+ continue;
+ }
+ }
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR, "Flash_WriteUnit ERROR: complete check failed, %r\n", Status));
+ continue;
+ }
+ } while ((Retry--) && EFI_ERROR(Status));
+
+ return Status;
+}
+
+
+EFI_STATUS SectorErase(UINT32 Base, UINT32 Offset)
+{
+ UINT8 gTemp[FLASH_MAX_UNIT];
+ UINT64 dwLoop = FLASH_MAX_UNIT - 1;
+ UINT32 Retry = 3;
+ EFI_STATUS Status;
+
+ do
+ {
+ gTemp[dwLoop] = 0xFF;
+ }while (dwLoop --);
+
+ do
+ {
+ (void)SectorEraseCommand(Base, Offset);
+ Status = CompleteCheck(Base, Offset, (void *)gTemp, FLASH_MAX_UNIT);
+
+
+ if (EFI_SUCCESS == Status)
+ {
+
+ if (width8IsAll(Base,Offset - (Offset % gFlashInfo[gIndex.InfIndex].BlockSize), gFlashInfo[gIndex.InfIndex].BlockSize, 0xFF))
+ {
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR, "Flash_SectorErase ERROR: not all address equal 0xFF\n"));
+
+ Status = EFI_ABORTED;
+ continue;
+ }
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR, "Flash_SectorErase ERROR: complete check failed, %r\n", Status));
+ continue;
+ }
+ }while ((Retry--) && EFI_ERROR(Status));
+
+ if(Retry)
+ {
+ //do nothing for pclint
+ }
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.h b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.h
new file mode 100644
index 0000000..36c0c9e
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.h
@@ -0,0 +1,116 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _NOR_FLASH_HW_H_
+#define _NOR_FLASH_HW_H_
+
+#include <Uefi/UefiBaseType.h>
+
+
+#define FOUR_BYTE_UNIT 4
+#define FLASH_MAX_UNIT 4
+
+#define FLASH_DEVICE_NUM 0x10
+
+
+
+typedef struct {
+ UINT32 ManufacturerID;
+ UINT32 DeviceID1;
+ UINT32 DeviceID2;
+ UINT32 DeviceID3;
+ UINT8 ParallelNum;
+ UINT32 SingleChipSize;
+ UINT32 BlockSize;
+ UINT32 BufferProgramSize;
+ UINT32 CommandType;
+}NOR_FLASH_INFO_TABLE;
+
+/*Define Command Address And Data*/
+/*reset*/
+typedef struct {
+ UINT32 CommandType;
+ UINT32 ResetData;
+}FLASH_COMMAND_RESET;
+
+/*manufacture ID & Device ID*/
+typedef struct {
+ UINT32 CommandType;
+ UINT32 ManuIDAddressStep1;
+ UINT32 ManuIDDataStep1;
+ UINT32 ManuIDAddressStep2;
+ UINT32 ManuIDDataStep2;
+ UINT32 ManuIDAddressStep3;
+ UINT32 ManuIDDataStep3;
+ UINT32 ManuIDAddress;
+
+ UINT32 DeviceIDAddress1;
+ UINT32 DeviceIDAddress2;
+ UINT32 DeviceIDAddress3;
+}FLASH_COMMAND_ID;
+
+/*Write Buffer*/
+typedef struct {
+ UINT32 CommandType;
+ UINT32 BufferProgramAddressStep1;
+ UINT32 BufferProgramDataStep1;
+ UINT32 BufferProgramAddressStep2;
+ UINT32 BufferProgramDataStep2;
+ UINT32 BufferProgramDataStep3;
+ UINT32 BufferProgramtoFlash;
+}FLASH_COMMAND_WRITE;
+
+/*erase*/
+typedef struct {
+ UINT32 CommandType;
+ UINT32 SectorEraseAddressStep1;
+ UINT32 SectorEraseDataStep1;
+ UINT32 SectorEraseAddressStep2;
+ UINT32 SectorEraseDataStep2;
+ UINT32 SectorEraseAddressStep3;
+ UINT32 SectorEraseDataStep3;
+ UINT32 SectorEraseAddressStep4;
+ UINT32 SectorEraseDataStep4;
+ UINT32 SectorEraseAddressStep5;
+ UINT32 SectorEraseDataStep5;
+ UINT32 SectorEraseDataStep6;
+}FLASH_COMMAND_ERASE;
+
+
+typedef struct {
+ UINT32 Base;
+ UINT32 InfIndex;
+ UINT32 ReIndex;
+ UINT32 IdIndex;
+ UINT32 WIndex;
+ UINT32 EIndex;
+}FLASH_INDEX;
+
+
+extern EFI_STATUS FlashInit(UINT32 Base);
+extern EFI_STATUS SectorErase(UINT32 Base, UINT32 Offset);
+extern EFI_STATUS BufferWrite(UINT32 Offset, void *pData, UINT32 Length);
+extern EFI_STATUS IsNeedToWrite(UINT32 Base, UINT32 Offset, UINT8 *Buffer, UINT32 Length);
+
+
+extern NOR_FLASH_INFO_TABLE gFlashInfo[FLASH_DEVICE_NUM];
+extern FLASH_COMMAND_RESET gFlashCommandReset[FLASH_DEVICE_NUM];
+extern FLASH_COMMAND_ID gFlashCommandId[FLASH_DEVICE_NUM];
+extern FLASH_COMMAND_WRITE gFlashCommandWrite[FLASH_DEVICE_NUM];
+extern FLASH_COMMAND_ERASE gFlashCommandErase[FLASH_DEVICE_NUM];
+extern FLASH_INDEX gIndex;
+
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
new file mode 100644
index 0000000..ccc263e
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
@@ -0,0 +1,1451 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2016, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#include <Uefi.h>
+#include <Protocol/EmbeddedGpio.h>
+#include <Guid/EventGroup.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/OemMiscLib.h>
+
+#include "PciHostBridge.h"
+
+UINTN RootBridgeNumber[PCIE_MAX_HOSTBRIDGE] = { PCIE_MAX_ROOTBRIDGE,PCIE_MAX_ROOTBRIDGE };
+
+UINT64 RootBridgeAttribute[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ { //Host Bridge0
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ },
+ { //Host Bridge1
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ }
+ };
+
+EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ { //Host Bridge0
+ /* Port 0 */
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A03),
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ /* Port 1 */
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A04),
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ /* Port 2 */
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A05),
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ /* Port 3 */
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A06),
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ }
+},
+{ // Host Bridge1
+ /* Port 0 */
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A07),
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ /* Port 1 */
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A08),
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ /* Port 2 */
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A09),
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ /* Port 3 */
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A0A),
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ }
+ }
+};
+
+EFI_HANDLE mDriverImageHandle;
+
+PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
+ PCI_HOST_BRIDGE_SIGNATURE, // Signature
+ NULL, // HostBridgeHandle
+ 0, // RootBridgeNumber
+ {NULL, NULL}, // Head
+ FALSE, // ResourceSubiteed
+ TRUE, // CanRestarted
+ {
+ NotifyPhase,
+ GetNextRootBridge,
+ GetAttributes,
+ StartBusEnumeration,
+ SetBusNumbers,
+ SubmitResources,
+ GetProposedResources,
+ PreprocessController
+ }
+};
+
+/**
+ Entry point of this driver
+
+ @param ImageHandle Handle of driver image
+ @param SystemTable Point to EFI_SYSTEM_TABLE
+
+ @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource
+ @retval EFI_DEVICE_ERROR Can not install the protocol instance
+ @retval EFI_SUCCESS Success to initialize the Pci host bridge.
+**/
+EFI_STATUS
+EFIAPI
+InitializePciHostBridge (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN Loop1;
+ UINTN Loop2;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge = NULL;
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+ UINT32 PcieRootBridgeMask;
+
+ if (!OemIsMpBoot())
+ {
+ PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);
+ PcieRootBridgeMask &= 0xf;
+ }
+ else
+ {
+ PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
+ }
+
+ mDriverImageHandle = ImageHandle;
+ //
+ // Create Host Bridge Device Handle
+ //
+
+ for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) {
+ if (((PcieRootBridgeMask >> (4 * Loop1)) & 0xF ) == 0) {
+ continue;
+ }
+
+
+ HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);
+ if (HostBridge == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];
+ InitializeListHead (&HostBridge->Head);
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &HostBridge->HostBridgeHandle,
+ &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool (HostBridge);
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Create Root Bridge Device Handle in this Host Bridge
+ //
+ for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {
+ if (!(((PcieRootBridgeMask >> (4 * Loop1)) >> Loop2 ) & 0x01)) {
+ continue;
+ }
+
+ PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));
+ if (PrivateData == NULL) {
+ FreePool (HostBridge);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ PrivateData->Port = Loop2;
+ PrivateData->SocType = PcdGet32(Pcdsoctype);
+ PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
+ PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
+
+ (VOID)RootBridgeConstructor (
+ &PrivateData->Io,
+ HostBridge->HostBridgeHandle,
+ RootBridgeAttribute[Loop1][Loop2],
+ &mResAppeture[Loop1][Loop2],
+ Loop1
+ );
+
+ Status = gBS->InstallMultipleProtocolInterfaces(
+ &PrivateData->Handle,
+ &gEfiDevicePathProtocolGuid, PrivateData->DevicePath,
+ &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ (VOID)gBS->UninstallMultipleProtocolInterfaces (
+ HostBridge->HostBridgeHandle,
+ &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
+ NULL
+ );
+ FreePool(PrivateData);
+ FreePool (HostBridge);
+ return EFI_DEVICE_ERROR;
+ }
+ // PCI Memory Space
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ mResAppeture[Loop1][Loop2] .MemBase,
+ mResAppeture[Loop1][Loop2] .MemLimit -mResAppeture[Loop1][Loop2] .MemBase + 1,
+ 0
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR,"PCIE AddMemorySpace Error\n"));
+ }
+ InsertTailList (&HostBridge->Head, &PrivateData->Link);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+NotifyAllocateMemResources(
+ IN PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance,
+ IN PCI_RESOURCE_TYPE Index,
+ IN OUT UINT64 *AllocatedLenMem
+)
+{
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ EFI_STATUS ReturnStatus;
+ UINT64 AddrLen;
+ UINTN BitsOfAlignment;
+
+ AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+ PCIE_DEBUG("Addrlen:%llx\n", AddrLen);
+ // Get the number of '1' in Alignment.
+ BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
+
+ BaseAddress = (RootBridgeInstance->MemBase + *AllocatedLenMem +
+ RootBridgeInstance->ResAllocNode[Index].Alignment)
+ & ~(RootBridgeInstance->ResAllocNode[Index].Alignment);
+ if ((BaseAddress + AddrLen - 1) > RootBridgeInstance->MemLimit) {
+ ReturnStatus = EFI_OUT_OF_RESOURCES;
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;
+ return ReturnStatus;
+ }
+
+ PCIE_DEBUG("(P)Mem32/64 request memory at:%llx\n", BaseAddress);
+ ReturnStatus = gDS->AllocateMemorySpace (
+ EfiGcdAllocateAddress,
+ EfiGcdMemoryTypeMemoryMappedIo,
+ BitsOfAlignment,
+ AddrLen,
+ &BaseAddress,
+ mDriverImageHandle,
+ NULL
+ );
+
+ if (!EFI_ERROR (ReturnStatus)) {
+ // We were able to allocate the PCI memory
+ RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
+ RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
+ *AllocatedLenMem += AddrLen;
+ PCIE_DEBUG("(P)Mem32/64 resource allocated:%llx\n", BaseAddress);
+
+ } else {
+ // Not able to allocate enough PCI memory
+ if (ReturnStatus != EFI_OUT_OF_RESOURCES) {
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;
+ }
+ }
+ return ReturnStatus;
+}
+
+EFI_STATUS
+EFIAPI
+NotifyAllocateResources(
+ IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance
+)
+{
+ EFI_STATUS ReturnStatus;
+ LIST_ENTRY *List;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+ PCI_RESOURCE_TYPE Index;
+
+ ReturnStatus = EFI_SUCCESS;
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ while (List != &HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+
+ UINT64 AllocatedLenMem = 0;
+ for (Index = TypeIo; Index < TypeBus; Index++) {
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
+ if(Index == TypeIo) {
+ PCIE_DEBUG("NOT SUPPOER IO RESOURCES ON THIS PLATFORM\n");
+ } else if ((Index >= TypeMem32) && (Index <= TypePMem64)) {
+ ReturnStatus = NotifyAllocateMemResources(RootBridgeInstance,Index,&AllocatedLenMem);
+ } else {
+ ASSERT (FALSE);
+ }
+ }
+ }
+
+ List = List->ForwardLink;
+ }
+
+ return ReturnStatus;
+}
+
+EFI_STATUS
+EFIAPI
+NotifyFreeResources(
+ IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance
+)
+{
+ EFI_STATUS ReturnStatus;
+ LIST_ENTRY *List;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+ PCI_RESOURCE_TYPE Index;
+ UINT64 AddrLen;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+
+ ReturnStatus = EFI_SUCCESS;
+ List = HostBridgeInstance->Head.ForwardLink;
+ while (List != &HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ for (Index = TypeIo; Index < TypeBus; Index++) {
+ if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
+ AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+ BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
+
+ if(Index <= TypePMem64){
+ ReturnStatus = gDS->FreeMemorySpace (BaseAddress, AddrLen);
+ }else{
+ ASSERT (FALSE);
+ }
+
+ RootBridgeInstance->ResAllocNode[Index].Type = Index;
+ RootBridgeInstance->ResAllocNode[Index].Base = 0;
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;
+ RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
+ }
+ }
+
+ List = List->ForwardLink;
+ }
+
+ HostBridgeInstance->ResourceSubmited = FALSE;
+ HostBridgeInstance->CanRestarted = TRUE;
+ return ReturnStatus;
+
+}
+
+VOID
+EFIAPI
+NotifyBeginEnumeration(
+ IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance
+)
+{
+ LIST_ENTRY *List;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+ PCI_RESOURCE_TYPE Index;
+
+ //
+ // Reset the Each Root Bridge
+ //
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ while (List != &HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ for (Index = TypeIo; Index < TypeMax; Index++) {
+ RootBridgeInstance->ResAllocNode[Index].Type = Index;
+ RootBridgeInstance->ResAllocNode[Index].Base = 0;
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;
+ RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
+ }
+
+ List = List->ForwardLink;
+ }
+
+ HostBridgeInstance->ResourceSubmited = FALSE;
+ HostBridgeInstance->CanRestarted = TRUE;
+}
+
+/**
+ These are the notifications from the PCI bus driver that it is about to enter a certain
+ phase of the PCI enumeration process.
+
+ This member function can be used to notify the host bridge driver to perform specific actions,
+ including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
+ Eight notification points are defined at this time. See belows:
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
+ structures. The PCI enumerator should issue this notification
+ before starting a fresh enumeration process. Enumeration cannot
+ be restarted after sending any other notification such as
+ EfiPciHostBridgeBeginBusAllocation.
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
+ required here. This notification can be used to perform any
+ chipset-specific programming.
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
+ specific action is required here. This notification can be used to
+ perform any chipset-specific programming.
+ EfiPciHostBridgeBeginResourceAllocation
+ The resource allocation phase is about to begin. No specific
+ action is required here. This notification can be used to perform
+ any chipset-specific programming.
+ EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
+ root bridges. These resource settings are returned on the next call to
+ GetProposedResources(). Before calling NotifyPhase() with a Phase of
+ EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
+ for gathering I/O and memory requests for
+ all the PCI root bridges and submitting these requests using
+ SubmitResources(). This function pads the resource amount
+ to suit the root bridge hardware, takes care of dependencies between
+ the PCI root bridges, and calls the Global Coherency Domain (GCD)
+ with the allocation request. In the case of padding, the allocated range
+ could be bigger than what was requested.
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
+ resources (proposed resources) for all the PCI root bridges. After the
+ hardware is programmed, reassigning resources will not be supported.
+ The bus settings are not affected.
+ EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
+ root bridges and resets the I/O and memory apertures to their initial
+ state. The bus settings are not affected. If the request to allocate
+ resources fails, the PCI enumerator can use this notification to
+ deallocate previous resources, adjust the requests, and retry
+ allocation.
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
+ required here. This notification can be used to perform any chipsetspecific
+ programming.
+
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in] Phase The phase during enumeration
+
+ @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
+ is valid for a Phase of EfiPciHostBridgeAllocateResources if
+ SubmitResources() has not been called for one or more
+ PCI root bridges before this call
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
+ for a Phase of EfiPciHostBridgeSetResources.
+ @retval EFI_INVALID_PARAMETER Invalid phase parameter
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
+ previously submitted resource requests cannot be fulfilled or
+ were only partially fulfilled.
+ @retval EFI_SUCCESS The notification was accepted without any errors.
+
+**/
+EFI_STATUS
+EFIAPI
+NotifyPhase(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
+ )
+{
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ EFI_STATUS ReturnStatus;
+
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ ReturnStatus = EFI_SUCCESS;
+
+ switch (Phase) {
+
+ case EfiPciHostBridgeBeginEnumeration:
+ PCIE_DEBUG("Case EfiPciHostBridgeBeginEnumeration\n");
+ if (HostBridgeInstance->CanRestarted) {
+ NotifyBeginEnumeration(HostBridgeInstance);
+ } else {
+ //
+ // Can not restart
+ //
+ return EFI_NOT_READY;
+ }
+ break;
+
+ case EfiPciHostBridgeEndEnumeration:
+ PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n");
+ break;
+
+ case EfiPciHostBridgeBeginBusAllocation:
+ PCIE_DEBUG("Case EfiPciHostBridgeBeginBusAllocation\n");
+ //
+ // No specific action is required here, can perform any chipset specific programing
+ //
+
+ HostBridgeInstance->CanRestarted = FALSE;
+ break;
+
+ case EfiPciHostBridgeEndBusAllocation:
+ PCIE_DEBUG("Case EfiPciHostBridgeEndBusAllocation\n");
+ //
+ // No specific action is required here, can perform any chipset specific programing
+ //
+ break;
+
+ case EfiPciHostBridgeBeginResourceAllocation:
+ PCIE_DEBUG("Case EfiPciHostBridgeBeginResourceAllocation\n");
+ //
+ // No specific action is required here, can perform any chipset specific programing
+ //
+ break;
+
+ case EfiPciHostBridgeAllocateResources:
+ PCIE_DEBUG("Case EfiPciHostBridgeAllocateResources\n");
+
+ if (HostBridgeInstance->ResourceSubmited) {
+ //
+ // Take care of the resource dependencies between the root bridges
+ //
+ ReturnStatus = NotifyAllocateResources(HostBridgeInstance);
+ } else {
+ return EFI_NOT_READY;
+ }
+ //break;
+
+ case EfiPciHostBridgeSetResources:
+ PCIE_DEBUG("Case EfiPciHostBridgeSetResources\n");
+ break;
+
+ case EfiPciHostBridgeFreeResources:
+ PCIE_DEBUG("Case EfiPciHostBridgeFreeResources\n");
+
+ ReturnStatus = NotifyFreeResources(HostBridgeInstance);
+ break;
+
+ case EfiPciHostBridgeEndResourceAllocation:
+ PCIE_DEBUG("Case EfiPciHostBridgeEndResourceAllocation\n");
+ HostBridgeInstance->CanRestarted = FALSE;
+ break;
+
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return ReturnStatus;
+}
+
+/**
+ Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
+
+ This function is called multiple times to retrieve the device handles of all the PCI root bridges that
+ are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
+ root bridges. On each call, the handle that was returned by the previous call is passed into the
+ interface, and on output the interface returns the device handle of the next PCI root bridge. The
+ caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+ for that root bridge. When there are no more PCI root bridges to report, the interface returns
+ EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
+ are returned by this function.
+ For D945 implementation, there is only one root bridge in PCI host bridge.
+
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
+
+ @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
+ specific Host bridge and return EFI_SUCCESS.
+ @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
+ returned on a previous call to GetNextRootBridge().
+**/
+EFI_STATUS
+EFIAPI
+GetNextRootBridge(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN OUT EFI_HANDLE *RootBridgeHandle
+ )
+{
+ BOOLEAN NoRootBridge;
+ LIST_ENTRY *List;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+
+ NoRootBridge = TRUE;
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ List = HostBridgeInstance->Head.ForwardLink;
+
+
+ while (List != &HostBridgeInstance->Head) {
+ NoRootBridge = FALSE;
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ if (*RootBridgeHandle == NULL) {
+ //
+ // Return the first Root Bridge Handle of the Host Bridge
+ //
+ *RootBridgeHandle = RootBridgeInstance->Handle;
+ return EFI_SUCCESS;
+ } else {
+ if (*RootBridgeHandle == RootBridgeInstance->Handle) {
+ //
+ // Get next if have
+ //
+ List = List->ForwardLink;
+ if (List!=&HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ *RootBridgeHandle = RootBridgeInstance->Handle;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_NOT_FOUND;
+ }
+ }
+ }
+
+ List = List->ForwardLink;
+ } //end while
+
+ if (NoRootBridge) {
+ return EFI_NOT_FOUND;
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+}
+
+/**
+ Returns the allocation attributes of a PCI root bridge.
+
+ The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
+ from one PCI root bridge to another. These attributes are different from the decode-related
+ attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
+ RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
+ handles of all the root bridges that are associated with this host bridge must be obtained by calling
+ GetNextRootBridge(). The attributes are static in the sense that they do not change during or
+ after the enumeration process. The hardware may provide mechanisms to change the attributes on
+ the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
+ installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
+ "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
+ For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
+ include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
+ prefetchable memory.
+ Attribute Description
+ ------------------------------------ ----------------------------------------------------------------------
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
+ windows for nonprefetchable and prefetchable memory. A PCI bus
+ driver needs to include requests for prefetchable memory in the
+ nonprefetchable memory pool.
+
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
+ windows. If this bit is not set, the PCI bus driver needs to include
+ requests for a 64-bit memory address in the corresponding 32-bit
+ memory pool.
+
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
+ EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
+
+ @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
+ @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
+ @retval EFI_SUCCESS Success to get attribute of interested root bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+GetAttributes(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT UINT64 *Attributes
+ )
+{
+ LIST_ENTRY *List;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+
+ if (Attributes == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ while (List != &HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {
+ *Attributes = RootBridgeInstance->RootBridgeAttrib;
+ return EFI_SUCCESS;
+ }
+
+ List = List->ForwardLink;
+ }
+
+ //
+ // RootBridgeHandle is not an EFI_HANDLE
+ // that was returned on a previous call to GetNextRootBridge()
+ //
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+ Sets up the specified PCI root bridge for the bus enumeration process.
+
+ This member function sets up the root bridge for bus enumeration and returns the PCI bus range
+ over which the search should be performed in ACPI 2.0 resource descriptor format.
+
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
+ @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
+
+ @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
+ @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
+ @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
+
+**/
+EFI_STATUS
+EFIAPI
+StartBusEnumeration(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
+ )
+{
+ LIST_ENTRY *List;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+ VOID *Buffer;
+ UINT8 *Temp;
+ UINT64 BusStart;
+ UINT64 BusEnd;
+
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ while (List != &HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {
+ //
+ // Set up the Root Bridge for Bus Enumeration
+ //
+ BusStart = RootBridgeInstance->BusBase;
+ BusEnd = RootBridgeInstance->BusLimit;
+ //
+ // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
+ //
+
+ Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
+ if (Buffer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Temp = (UINT8 *)Buffer;
+
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;
+
+ Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
+
+ *Configuration = Buffer;
+ return EFI_SUCCESS;
+ }
+ List = List->ForwardLink;
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+ Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
+
+ This member function programs the specified PCI root bridge to decode the bus range that is
+ specified by the input parameter Configuration.
+ The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
+
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+ @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
+ @param[in] Configuration The pointer to the PCI bus resource descriptor
+
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
+ @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
+ @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
+ bus descriptors.
+ @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
+ @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
+ @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+SetBusNumbers(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
+ )
+{
+ LIST_ENTRY *List;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+ UINT8 *Ptr;
+ UINTN BusStart;
+ UINTN BusEnd;
+ UINTN BusLen;
+
+ if (Configuration == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Ptr = Configuration;
+
+ //
+ // Check the Configuration is valid
+ //
+ if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+ if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ Ptr = Configuration;
+
+ while (List != &HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {
+ BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;
+ BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
+ BusEnd = BusStart + BusLen - 1;
+
+ if (BusStart > BusEnd) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Update the Bus Range
+ //
+ RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;
+ RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;
+ RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;
+
+ //
+ // Program the Root Bridge Hardware
+ //
+
+ return EFI_SUCCESS;
+ }
+
+ List = List->ForwardLink;
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+VOID
+EFIAPI
+SubmitGetResourceType(
+ IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr,
+ OUT UINT64* Index
+)
+{
+ switch (Ptr->ResType) {
+ case 0:
+ if (Ptr->AddrSpaceGranularity == 32) {
+ if (Ptr->SpecificFlag == 0x06)
+ *Index = TypePMem32;
+ else
+ *Index = TypeMem32;
+ }
+
+ if (Ptr->AddrSpaceGranularity == 64) {
+ if (Ptr->SpecificFlag == 0x06)
+ *Index = TypePMem64;
+ else
+ *Index = TypeMem64;
+ }
+ break;
+
+ case 1:
+ *Index = TypeIo;
+ break;
+
+ default:
+ break;
+ };
+
+}
+
+/**
+ Submits the I/O and memory resource requirements for the specified PCI root bridge.
+
+ This function is used to submit all the I/O and memory resources that are required by the specified
+ PCI root bridge. The input parameter Configuration is used to specify the following:
+ - The various types of resources that are required
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
+ @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
+
+ @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
+ @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
+ not supported by this PCI root bridge. This error will happen if the caller
+ did not combine resources according to Attributes that were returned by
+ GetAllocAttributes().
+ @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+SubmitResources(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
+ )
+{
+ LIST_ENTRY *List;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+ UINT8 *Temp;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
+ UINT64 AddrLen;
+ UINT64 Alignment;
+ UINTN Index;
+
+ PCIE_DEBUG("In SubmitResources\n");
+ //
+ // Check the input parameter: Configuration
+ //
+ if (Configuration == NULL)
+ return EFI_INVALID_PARAMETER;
+
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ Temp = (UINT8 *)Configuration;
+ while ( *Temp == 0x8A)
+ Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
+
+ if (*Temp != 0x79)
+ return EFI_INVALID_PARAMETER;
+
+ Temp = (UINT8 *)Configuration;
+ while (List != &HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {
+ while ( *Temp == 0x8A) {
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
+ PCIE_DEBUG("Ptr->ResType:%d\n", Ptr->ResType);
+ PCIE_DEBUG("Ptr->Addrlen:%llx\n", Ptr->AddrLen);
+ PCIE_DEBUG("Ptr->AddrRangeMax:%llx\n", Ptr->AddrRangeMax);
+ PCIE_DEBUG("Ptr->AddrRangeMin:%llx\n", Ptr->AddrRangeMin);
+ PCIE_DEBUG("Ptr->SpecificFlag:%llx\n", Ptr->SpecificFlag);
+ PCIE_DEBUG("Ptr->AddrSpaceGranularity:%d\n", Ptr->AddrSpaceGranularity);
+ PCIE_DEBUG("RootBridgeInstance->RootBridgeAttrib:%llx\n", RootBridgeInstance->RootBridgeAttrib);
+ //
+ // Check address range alignment
+ //
+ if (Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
+ return EFI_INVALID_PARAMETER;
+ }
+ Index = 0;
+ SubmitGetResourceType(Ptr,&Index);
+ AddrLen = (UINTN) Ptr->AddrLen;
+ Alignment = (UINTN) Ptr->AddrRangeMax;
+ RootBridgeInstance->ResAllocNode[Index].Length = AddrLen;
+ RootBridgeInstance->ResAllocNode[Index].Alignment = Alignment;
+ RootBridgeInstance->ResAllocNode[Index].Status = ResRequested;
+ HostBridgeInstance->ResourceSubmited = TRUE;
+
+ Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
+ }
+
+ return EFI_SUCCESS;
+ }
+
+ List = List->ForwardLink;
+ }
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+ Returns the proposed resource settings for the specified PCI root bridge.
+
+ This member function returns the proposed resource settings for the specified PCI root bridge. The
+ proposed resource settings are prepared when NotifyPhase() is called with a Phase of
+ EfiPciHostBridgeAllocateResources. The output parameter Configuration
+ specifies the following:
+ - The various types of resources, excluding bus resources, that are allocated
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
+
+ @retval EFI_SUCCESS The requested parameters were returned.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+SetResource(
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance,
+ VOID *Buffer
+
+)
+{
+ UINTN Index;
+ UINT8 *Temp;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
+ UINT64 ResStatus;
+
+ Temp = Buffer;
+
+ for (Index = 0; Index < TypeBus; Index ++)
+ {
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
+ ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
+
+ switch (Index) {
+
+ case TypeIo:
+ //
+ // Io
+ //
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 1;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 0;
+ /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+ (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = \
+ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+ break;
+
+ case TypeMem32:
+ //
+ // Memory 32
+ //
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 0;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 0;
+ Ptr->AddrSpaceGranularity = 32;
+ /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+ (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = \
+ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+ break;
+
+ case TypePMem32:
+ //
+ // Prefetch memory 32
+ //
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 0;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 6;
+ Ptr->AddrSpaceGranularity = 32;
+ /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+ (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = \
+ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+ break;
+
+ case TypeMem64:
+ //
+ // Memory 64
+ //
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 0;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 0;
+ Ptr->AddrSpaceGranularity = 64;
+ /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+ (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = \
+ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+ break;
+
+ case TypePMem64:
+ //
+ // Prefetch memory 64
+ //
+ Ptr->Desc = 0x8A;
+ Ptr->Len = 0x2B;
+ Ptr->ResType = 0;
+ Ptr->GenFlag = 0;
+ Ptr->SpecificFlag = 6;
+ Ptr->AddrSpaceGranularity = 64;
+ /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+ (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
+ Ptr->AddrRangeMax = 0;
+ Ptr->AddrTranslationOffset = \
+ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+ Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+ break;
+ };
+ PCIE_DEBUG("Ptr->ResType:%d\n", Ptr->ResType);
+ PCIE_DEBUG("Ptr->Addrlen:%llx\n", Ptr->AddrLen);
+ PCIE_DEBUG("Ptr->AddrRangeMax:%llx\n", Ptr->AddrRangeMax);
+ PCIE_DEBUG("Ptr->AddrRangeMin:%llx\n", Ptr->AddrRangeMin);
+ PCIE_DEBUG("Ptr->SpecificFlag:%llx\n", Ptr->SpecificFlag);
+ PCIE_DEBUG("Ptr->AddrTranslationOffset:%d\n", Ptr->AddrTranslationOffset);
+ PCIE_DEBUG("Ptr->AddrSpaceGranularity:%d\n", Ptr->AddrSpaceGranularity);
+
+ Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+ }
+ }
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
+
+ return EFI_SUCCESS;
+}
+/**
+ Returns the proposed resource settings for the specified PCI root bridge.
+
+ This member function returns the proposed resource settings for the specified PCI root bridge. The
+ proposed resource settings are prepared when NotifyPhase() is called with a Phase of
+ EfiPciHostBridgeAllocateResources. The output parameter Configuration
+ specifies the following:
+ - The various types of resources, excluding bus resources, that are allocated
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
+
+ @retval EFI_SUCCESS The requested parameters were returned.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+GetProposedResources(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
+ )
+{
+ LIST_ENTRY *List;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+ UINTN Index;
+ UINTN Number;
+ VOID *Buffer;
+
+ Buffer = NULL;
+ Number = 0;
+
+ PCIE_DEBUG("In GetProposedResources\n");
+ //
+ // Get the Host Bridge Instance from the resource allocation protocol
+ //
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ //
+ // Enumerate the root bridges in this host bridge
+ //
+ while (List != &HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {
+ for (Index = 0; Index < TypeBus; Index ++) {
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
+ Number ++;
+ }
+ }
+
+ Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
+ if (Buffer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ (VOID)SetResource(RootBridgeInstance,Buffer);
+
+ *Configuration = Buffer;
+
+ return EFI_SUCCESS;
+ }
+
+ List = List->ForwardLink;
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
+ PCI controllers before enumeration.
+
+ This function is called during the PCI enumeration process. No specific action is expected from this
+ member function. It allows the host bridge driver to preinitialize individual PCI controllers before
+ enumeration.
+
+ @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
+ InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
+ configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
+ the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
+ @param Phase The phase of the PCI device enumeration.
+
+ @retval EFI_SUCCESS The requested parameters were returned.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
+ not enumerate this device, including its child devices if it is a PCI-to-PCI
+ bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+PreprocessController (
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
+ )
+{
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+ LIST_ENTRY *List;
+
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ //
+ // Enumerate the root bridges in this host bridge
+ //
+ while (List != &HostBridgeInstance->Head) {
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {
+ break;
+ }
+ List = List->ForwardLink;
+ }
+ if (List == &HostBridgeInstance->Head) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
new file mode 100644
index 0000000..99c97cf
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
@@ -0,0 +1,519 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2016, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#ifndef _PCI_HOST_BRIDGE_H_
+#define _PCI_HOST_BRIDGE_H_
+
+#include <PiDxe.h>
+
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/Acpi.h>
+
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/Metronome.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/CpuIo2.h>
+
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+
+// Enable below statments to enable PCIE debug
+//#define PCIE_DEBUG_ENABLE
+//#define PCIE_VDEBUG_ENABLE
+//#define PCIE_CDEBUG_ENABLE
+
+#ifdef PCIE_CDEBUG_ENABLE
+# define PCIE_CSR_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg))
+#else
+# define PCIE_CSR_DEBUG(arg...)
+#endif
+
+#ifdef PCIE_VDEBUG_ENABLE
+# define PCIE_VDEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg))
+#else
+# define PCIE_VDEBUG(arg...)
+#endif
+
+#ifdef PCIE_DEBUG_ENABLE
+# define PCIE_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg))
+#else
+# define PCIE_DEBUG(arg...)
+#endif
+#define PCIE_WARN(arg...) DEBUG((EFI_D_WARN,## arg))
+#define PCIE_ERR(arg...) DEBUG((EFI_D_ERROR,## arg))
+#define PCIE_INFO(arg...) DEBUG((EFI_D_INFO,## arg))
+
+#define MAX_PCI_DEVICE_NUMBER 31
+#define MAX_PCI_FUNCTION_NUMBER 7
+#define MAX_PCI_REG_ADDRESS 0xFFFF
+
+typedef enum {
+ IoOperation,
+ MemOperation,
+ PciOperation
+} OPERATION_TYPE;
+
+#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE HostBridgeHandle;
+ UINTN RootBridgeNumber;
+ LIST_ENTRY Head;
+ BOOLEAN ResourceSubmited;
+ BOOLEAN CanRestarted;
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
+} PCI_HOST_BRIDGE_INSTANCE;
+
+#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \
+ CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
+
+//
+// HostBridge Resource Allocation interface
+//
+
+/**
+ These are the notifications from the PCI bus driver that it is about to enter a certain
+ phase of the PCI enumeration process.
+
+ This member function can be used to notify the host bridge driver to perform specific actions,
+ including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
+ Eight notification points are defined at this time. See belows:
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
+ structures. The PCI enumerator should issue this notification
+ before starting a fresh enumeration process. Enumeration cannot
+ be restarted after sending any other notification such as
+ EfiPciHostBridgeBeginBusAllocation.
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
+ required here. This notification can be used to perform any
+ chipset-specific programming.
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
+ specific action is required here. This notification can be used to
+ perform any chipset-specific programming.
+ EfiPciHostBridgeBeginResourceAllocation
+ The resource allocation phase is about to begin. No specific
+ action is required here. This notification can be used to perform
+ any chipset-specific programming.
+ EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
+ root bridges. These resource settings are returned on the next call to
+ GetProposedResources(). Before calling NotifyPhase() with a Phase of
+ EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
+ for gathering I/O and memory requests for
+ all the PCI root bridges and submitting these requests using
+ SubmitResources(). This function pads the resource amount
+ to suit the root bridge hardware, takes care of dependencies between
+ the PCI root bridges, and calls the Global Coherency Domain (GCD)
+ with the allocation request. In the case of padding, the allocated range
+ could be bigger than what was requested.
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
+ resources (proposed resources) for all the PCI root bridges. After the
+ hardware is programmed, reassigning resources will not be supported.
+ The bus settings are not affected.
+ EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
+ root bridges and resets the I/O and memory apertures to their initial
+ state. The bus settings are not affected. If the request to allocate
+ resources fails, the PCI enumerator can use this notification to
+ deallocate previous resources, adjust the requests, and retry
+ allocation.
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
+ required here. This notification can be used to perform any chipsetspecific
+ programming.
+
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in] Phase The phase during enumeration
+
+ @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
+ is valid for a Phase of EfiPciHostBridgeAllocateResources if
+ SubmitResources() has not been called for one or more
+ PCI root bridges before this call
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
+ for a Phase of EfiPciHostBridgeSetResources.
+ @retval EFI_INVALID_PARAMETER Invalid phase parameter
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
+ previously submitted resource requests cannot be fulfilled or
+ were only partially fulfilled.
+ @retval EFI_SUCCESS The notification was accepted without any errors.
+
+**/
+EFI_STATUS
+EFIAPI
+NotifyPhase(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
+ );
+
+/**
+ Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
+
+ This function is called multiple times to retrieve the device handles of all the PCI root bridges that
+ are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
+ root bridges. On each call, the handle that was returned by the previous call is passed into the
+ interface, and on output the interface returns the device handle of the next PCI root bridge. The
+ caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+ for that root bridge. When there are no more PCI root bridges to report, the interface returns
+ EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
+ are returned by this function.
+ For D945 implementation, there is only one root bridge in PCI host bridge.
+
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
+
+ @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
+ specific Host bridge and return EFI_SUCCESS.
+ @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
+ returned on a previous call to GetNextRootBridge().
+**/
+EFI_STATUS
+EFIAPI
+GetNextRootBridge(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN OUT EFI_HANDLE *RootBridgeHandle
+ );
+
+/**
+ Returns the allocation attributes of a PCI root bridge.
+
+ The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
+ from one PCI root bridge to another. These attributes are different from the decode-related
+ attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
+ RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
+ handles of all the root bridges that are associated with this host bridge must be obtained by calling
+ GetNextRootBridge(). The attributes are static in the sense that they do not change during or
+ after the enumeration process. The hardware may provide mechanisms to change the attributes on
+ the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
+ installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
+ "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
+ For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
+ include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
+ prefetchable memory.
+ Attribute Description
+ ------------------------------------ ----------------------------------------------------------------------
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
+ windows for nonprefetchable and prefetchable memory. A PCI bus
+ driver needs to include requests for prefetchable memory in the
+ nonprefetchable memory pool.
+
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
+ windows. If this bit is not set, the PCI bus driver needs to include
+ requests for a 64-bit memory address in the corresponding 32-bit
+ memory pool.
+
+ @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
+ EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
+
+ @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
+ @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
+ @retval EFI_SUCCESS Success to get attribute of interested root bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+GetAttributes(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT UINT64 *Attributes
+ );
+
+/**
+ Sets up the specified PCI root bridge for the bus enumeration process.
+
+ This member function sets up the root bridge for bus enumeration and returns the PCI bus range
+ over which the search should be performed in ACPI 2.0 resource descriptor format.
+
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
+ @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
+
+ @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
+ @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
+ @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
+
+**/
+EFI_STATUS
+EFIAPI
+StartBusEnumeration(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
+ );
+
+/**
+ Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
+
+ This member function programs the specified PCI root bridge to decode the bus range that is
+ specified by the input parameter Configuration.
+ The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
+
+ @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+ @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
+ @param[in] Configuration The pointer to the PCI bus resource descriptor
+
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
+ @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
+ @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
+ bus descriptors.
+ @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
+ @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
+ @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+SetBusNumbers(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
+ );
+
+/**
+ Submits the I/O and memory resource requirements for the specified PCI root bridge.
+
+ This function is used to submit all the I/O and memory resources that are required by the specified
+ PCI root bridge. The input parameter Configuration is used to specify the following:
+ - The various types of resources that are required
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
+ @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
+
+ @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
+ @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
+ not supported by this PCI root bridge. This error will happen if the caller
+ did not combine resources according to Attributes that were returned by
+ GetAllocAttributes().
+ @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+SubmitResources(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN VOID *Configuration
+ );
+
+/**
+ Returns the proposed resource settings for the specified PCI root bridge.
+
+ This member function returns the proposed resource settings for the specified PCI root bridge. The
+ proposed resource settings are prepared when NotifyPhase() is called with a Phase of
+ EfiPciHostBridgeAllocateResources. The output parameter Configuration
+ specifies the following:
+ - The various types of resources, excluding bus resources, that are allocated
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
+
+ @retval EFI_SUCCESS The requested parameters were returned.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+GetProposedResources(
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ OUT VOID **Configuration
+ );
+
+/**
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
+ PCI controllers before enumeration.
+
+ This function is called during the PCI enumeration process. No specific action is expected from this
+ member function. It allows the host bridge driver to preinitialize individual PCI controllers before
+ enumeration.
+
+ @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+ @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
+ InstallProtocolInterface() in the UEFI 2.0 Specification.
+ @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
+ configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
+ the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
+ @param Phase The phase of the PCI device enumeration.
+
+ @retval EFI_SUCCESS The requested parameters were returned.
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
+ not enumerate this device, including its child devices if it is a PCI-to-PCI
+ bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+PreprocessController (
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+ IN EFI_HANDLE RootBridgeHandle,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
+ );
+
+
+//
+// Define resource status constant
+//
+#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
+#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
+
+
+//
+// Driver Instance Data Prototypes
+//
+
+typedef struct {
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
+ UINTN NumberOfBytes;
+ UINTN NumberOfPages;
+ EFI_PHYSICAL_ADDRESS HostAddress;
+ EFI_PHYSICAL_ADDRESS MappedHostAddress;
+} MAP_INFO;
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+typedef enum {
+ TypeIo = 0,
+ TypeMem32,
+ TypePMem32,
+ TypeMem64,
+ TypePMem64,
+ TypeBus,
+ TypeMax
+} PCI_RESOURCE_TYPE;
+
+typedef enum {
+ ResNone = 0,
+ ResSubmitted,
+ ResRequested,
+ ResAllocated,
+ ResStatusMax
+} RES_STATUS;
+
+typedef struct {
+ PCI_RESOURCE_TYPE Type;
+ UINT64 Base;
+ UINT64 Length;
+ UINT64 Alignment;
+ RES_STATUS Status;
+} PCI_RES_NODE;
+
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')
+
+typedef struct {
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ EFI_HANDLE Handle;
+ UINT64 RootBridgeAttrib;
+ UINT64 Attributes;
+ UINT64 Supports;
+
+ //
+ // Specific for this memory controller: Bus, I/O, Mem
+ //
+ PCI_RES_NODE ResAllocNode[6];
+
+ //
+ // Addressing for Memory and I/O and Bus arrange
+ //
+ UINT64 BusBase;
+ UINT64 MemBase;
+ UINT64 IoBase;
+ UINT64 BusLimit;
+ UINT64 MemLimit;
+ UINT64 IoLimit;
+ UINT64 RbPciBar;
+ UINT64 Ecam;
+
+ UINTN PciAddress;
+ UINTN PciData;
+ UINTN Port;
+ UINT32 SocType;
+ UINT64 CpuMemRegionBase;
+ UINT64 CpuIoRegionBase;
+
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
+
+} PCI_ROOT_BRIDGE_INSTANCE;
+
+
+//
+// Driver Instance Data Macros
+//
+#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \
+ CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
+
+
+#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \
+ CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
+
+/**
+
+ Construct the Pci Root Bridge Io protocol
+
+ @param Protocol Point to protocol instance
+ @param HostBridgeHandle Handle of host bridge
+ @param Attri Attribute of host bridge
+ @param ResAppeture ResourceAppeture for host bridge
+
+ @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
+
+**/
+EFI_STATUS
+RootBridgeConstructor (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
+ IN EFI_HANDLE HostBridgeHandle,
+ IN UINT64 Attri,
+ IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture,
+ IN UINT32 Seg
+ );
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
new file mode 100644
index 0000000..5cfbee5
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
@@ -0,0 +1,74 @@
+## @file
+#
+# Component description file PCI Host Bridge driver.
+# Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PciHostBridge
+ FILE_GUID = B0E61270-263F-11E3-8224-0800200C9A66
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializePciHostBridge
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ DxeServicesTableLib
+ CacheMaintenanceLib
+ DmaLib
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ TimerLib
+ ArmLib
+ DevicePathLib
+ PcdLib
+ OemMiscLib
+
+[Sources]
+ PciHostBridge.c
+ PciRootBridgeIo.c
+ PciHostBridge.h
+
+[Protocols]
+ gEfiPciHostBridgeResourceAllocationProtocolGuid
+ gEfiPciRootBridgeIoProtocolGuid
+ gEfiMetronomeArchProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEmbeddedGpioProtocolGuid
+
+[depex]
+ gEfiMetronomeArchProtocolGuid
+
+[FeaturePcd]
+
+[Pcd]
+
+[FixedPcd]
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P
+ gHisiTokenSpaceGuid.Pcdsoctype
+
+[Guids]
+ gEfiEventExitBootServicesGuid ## PRODUCES ## Event
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
new file mode 100644
index 0000000..01aa1e0
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -0,0 +1,2311 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2016, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#include "PciHostBridge.h"
+#include <Library/DevicePathLib.h>
+#include <Library/DmaLib.h>
+#include <Library/PciExpressLib.h>
+#include <Regs/HisiPcieV1RegOffset.h>
+
+
+typedef struct {
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];
+ EFI_ACPI_END_TAG_DESCRIPTOR EndDesp;
+} RESOURCE_CONFIGURATION;
+
+RESOURCE_CONFIGURATION Configuration = {
+ {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},
+ {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},
+ {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},
+ {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},
+ {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},
+ {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},
+ {0x79, 0}
+};
+
+//
+// Protocol Member Function Prototypes
+//
+
+/**
+ Polls an address in memory mapped I/O space until an exit condition is met, or
+ a timeout occurs.
+
+ This function provides a standard way to poll a PCI memory location. A PCI memory read
+ operation is performed at the PCI memory address specified by Address for the width specified
+ by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
+ read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
+ Mask) is equal to Value.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Address The base address of the memory operations. The caller is
+ responsible for aligning Address if required.
+ @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
+ are ignored. The bits in the bytes below Width which are zero in
+ Mask are ignored when polling the memory address.
+ @param[in] Value The comparison value used for the polling exit criteria.
+ @param[in] Delay The number of 100 ns units to poll. Note that timer available may
+ be of poorer granularity.
+ @param[out] Result Pointer to the last value read from the memory location.
+
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
+ @retval EFI_INVALID_PARAMETER Width is invalid.
+ @retval EFI_INVALID_PARAMETER Result is NULL.
+ @retval EFI_TIMEOUT Delay expired before a match occurred.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+/**
+ Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
+ satisfied or after a defined duration.
+
+ This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
+ performed at the PCI I/O address specified by Address for the width specified by Width.
+ The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
+ repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
+ to Value.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the I/O operations.
+ @param[in] Address The base address of the I/O operations. The caller is responsible
+ for aligning Address if required.
+ @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
+ are ignored. The bits in the bytes below Width which are zero in
+ Mask are ignored when polling the I/O address.
+ @param[in] Value The comparison value used for the polling exit criteria.
+ @param[in] Delay The number of 100 ns units to poll. Note that timer available may
+ be of poorer granularity.
+ @param[out] Result Pointer to the last value read from the memory location.
+
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
+ @retval EFI_INVALID_PARAMETER Width is invalid.
+ @retval EFI_INVALID_PARAMETER Result is NULL.
+ @retval EFI_TIMEOUT Delay expired before a match occurred.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollIo (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
+ registers in the PCI root bridge memory space.
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+ any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operation.
+ @param[in] Address The base address of the memory operation. The caller is
+ responsible for aligning the Address if required.
+ @param[in] Count The number of memory operations to perform. Bytes moved is
+ Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
+ registers in the PCI root bridge memory space.
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+ any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operation.
+ @param[in] Address The base address of the memory operation. The caller is
+ responsible for aligning the Address if required.
+ @param[in] Count The number of memory operations to perform. Bytes moved is
+ Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
+ aligning the Address if required.
+ @param[in] Count The number of I/O operations to perform. Bytes moved is Width
+ size * Count, starting at Address.
+ @param[out] UserBuffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ OUT VOID *UserBuffer
+ );
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
+ aligning the Address if required.
+ @param[in] Count The number of I/O operations to perform. Bytes moved is Width
+ size * Count, starting at Address.
+ @param[in] UserBuffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN VOID *UserBuffer
+ );
+
+/**
+ Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
+ root bridge memory space.
+
+ The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
+ space to another region of PCI root bridge memory space. This is especially useful for video scroll
+ operation on a memory mapped video buffer.
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+ any alignment and memory width restrictions that a PCI root bridge on a platform might require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] DestAddress The destination address of the memory operation. The caller is
+ responsible for aligning the DestAddress if required.
+ @param[in] SrcAddress The source address of the memory operation. The caller is
+ responsible for aligning the SrcAddress if required.
+ @param[in] Count The number of memory operations to perform. Bytes moved is
+ Width size * Count, starting at DestAddress and SrcAddress.
+
+ @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoCopyMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
+ );
+
+/**
+ Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+ The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
+ registers for a PCI controller.
+ The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
+ any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
+ require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Address The address within the PCI configuration space for the PCI controller.
+ @param[in] Count The number of PCI configuration operations to perform. Bytes
+ moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+ The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
+ registers for a PCI controller.
+ The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
+ any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
+ require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Address The address within the PCI configuration space for the PCI controller.
+ @param[in] Count The number of PCI configuration operations to perform. Bytes
+ moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Provides the PCI controller-specific addresses required to access system memory from a
+ DMA bus master.
+
+ The Map() function provides the PCI controller specific addresses needed to access system
+ memory. This function is used to map system memory for PCI bus master DMA accesses.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Operation Indicates if the bus master is going to read or write to system memory.
+ @param[in] HostAddress The system memory address to map to the PCI controller.
+ @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
+ @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
+ to access the system memory's HostAddress.
+ @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
+
+ @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
+ @retval EFI_INVALID_PARAMETER Operation is invalid.
+ @retval EFI_INVALID_PARAMETER HostAddress is NULL.
+ @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
+ @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
+ @retval EFI_INVALID_PARAMETER Mapping is NULL.
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
+ @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ );
+
+/**
+ Completes the Map() operation and releases any corresponding resources.
+
+ The Unmap() function completes the Map() operation and releases any corresponding resources.
+ If the operation was an EfiPciOperationBusMasterWrite or
+ EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
+ Any resources used for the mapping are freed.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Mapping The mapping value returned from Map().
+
+ @retval EFI_SUCCESS The range was unmapped.
+ @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
+ @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoUnmap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ );
+
+/**
+ Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
+ EfiPciOperationBusMasterCommonBuffer64 mapping.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Type This parameter is not used and must be ignored.
+ @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
+ @param Pages The number of pages to allocate.
+ @param HostAddress A pointer to store the base system memory address of the allocated range.
+ @param Attributes The requested bit mask of attributes for the allocated range. Only
+ the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
+ and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
+
+ @retval EFI_SUCCESS The requested memory pages were allocated.
+ @retval EFI_INVALID_PARAMETER MemoryType is invalid.
+ @retval EFI_INVALID_PARAMETER HostAddress is NULL.
+ @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoAllocateBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ );
+
+/**
+ Frees memory that was allocated with AllocateBuffer().
+
+ The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Pages The number of pages to free.
+ @param HostAddress The base system memory address of the allocated range.
+
+ @retval EFI_SUCCESS The requested memory pages were freed.
+ @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
+ was not allocated with AllocateBuffer().
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFreeBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ OUT VOID *HostAddress
+ );
+
+/**
+ Flushes all PCI posted write transactions from a PCI host bridge to system memory.
+
+ The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
+ memory. Posted write transactions are generated by PCI bus masters when they perform write
+ transactions to target addresses in system memory.
+ This function does not flush posted write transactions from any PCI bridges. A PCI controller
+ specific action must be taken to guarantee that the posted write transactions have been flushed from
+ the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
+ a PCI read transaction from the PCI controller prior to calling Flush().
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+
+ @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
+ bridge to system memory.
+ @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
+ host bridge due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFlush (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
+ );
+
+/**
+ Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
+ attributes that a PCI root bridge is currently using.
+
+ The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
+ and the mask of attributes that the PCI root bridge is currently using.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Supported A pointer to the mask of attributes that this PCI root bridge
+ supports setting with SetAttributes().
+ @param Attributes A pointer to the mask of attributes that this PCI root bridge is
+ currently using.
+
+ @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
+ bridge supports is returned in Supports. If Attributes is
+ not NULL, then the attributes that the PCI root bridge is currently
+ using is returned in Attributes.
+ @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoGetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT UINT64 *Supported,
+ OUT UINT64 *Attributes
+ );
+
+/**
+ Sets attributes for a resource range on a PCI root bridge.
+
+ The SetAttributes() function sets the attributes specified in Attributes for the PCI root
+ bridge on the resource range specified by ResourceBase and ResourceLength. Since the
+ granularity of setting these attributes may vary from resource type to resource type, and from
+ platform to platform, the actual resource range and the one passed in by the caller may differ. As a
+ result, this function may set the attributes specified by Attributes on a larger resource range
+ than the caller requested. The actual range is returned in ResourceBase and
+ ResourceLength. The caller is responsible for verifying that the actual range for which the
+ attributes were set is acceptable.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Attributes The mask of attributes to set. If the attribute bit
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
+ MEMORY_DISABLE is set, then the resource range is specified by
+ ResourceBase and ResourceLength. If
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
+ MEMORY_DISABLE are not set, then ResourceBase and
+ ResourceLength are ignored, and may be NULL.
+ @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
+ by the attributes specified by Attributes.
+ @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
+ attributes specified by Attributes.
+
+ @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
+ @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
+ @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoSetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN OUT UINT64 *ResourceBase,
+ IN OUT UINT64 *ResourceLength
+ );
+
+/**
+ Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
+ resource descriptors.
+
+ There are only two resource descriptor types from the ACPI Specification that may be used to
+ describe the current resources allocated to a PCI root bridge. These are the QWORD Address
+ Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
+ QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
+ or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
+ Address Space Descriptors followed by an End Tag.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
+ current configuration of this PCI root bridge. The storage for the
+ ACPI 2.0 resource descriptors is allocated by this function. The
+ caller must treat the return buffer as read-only data, and the buffer
+ must not be freed by the caller.
+
+ @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
+ @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
+ @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoConfiguration (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT VOID **Resources
+ );
+
+//
+// Memory Controller Pci Root Bridge Io Module Variables
+//
+EFI_METRONOME_ARCH_PROTOCOL *mMetronome;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+UINT8 mInStride[] = {
+ 1, // EfiPciWidthUint8
+ 2, // EfiPciWidthUint16
+ 4, // EfiPciWidthUint32
+ 8, // EfiPciWidthUint64
+ 0, // EfiPciWidthFifoUint8
+ 0, // EfiPciWidthFifoUint16
+ 0, // EfiPciWidthFifoUint32
+ 0, // EfiPciWidthFifoUint64
+ 1, // EfiPciWidthFillUint8
+ 2, // EfiPciWidthFillUint16
+ 4, // EfiPciWidthFillUint32
+ 8 // EfiPciWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+UINT8 mOutStride[] = {
+ 1, // EfiPciWidthUint8
+ 2, // EfiPciWidthUint16
+ 4, // EfiPciWidthUint32
+ 8, // EfiPciWidthUint64
+ 1, // EfiPciWidthFifoUint8
+ 2, // EfiPciWidthFifoUint16
+ 4, // EfiPciWidthFifoUint32
+ 8, // EfiPciWidthFifoUint64
+ 0, // EfiPciWidthFillUint8
+ 0, // EfiPciWidthFillUint16
+ 0, // EfiPciWidthFillUint32
+ 0 // EfiPciWidthFillUint64
+};
+
+
+UINT64 GetPcieCfgAddress (
+ UINT64 Ecam,
+ UINTN Bus,
+ UINTN Device,
+ UINTN Function,
+ UINTN Reg
+ )
+{
+ return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg);
+}
+
+
+void SetAtuConfig0RW (
+ PCI_ROOT_BRIDGE_INSTANCE *Private,
+ UINT32 Index
+ )
+{
+ UINTN RbPciBase = Private->RbPciBar;
+ UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
+
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+void SetAtuConfig1RW (
+ PCI_ROOT_BRIDGE_INSTANCE *Private,
+ UINT32 Index
+ )
+{
+ UINTN RbPciBase = Private->RbPciBar;
+ UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
+
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index)
+{
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO);
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32));
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index)
+{
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM);
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32));
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private)
+{
+ SetAtuMemRW (Private->RbPciBar, Private->MemBase, Private->MemLimit, Private->CpuMemRegionBase, 0);
+ SetAtuConfig0RW (Private, 1);
+ SetAtuConfig1RW (Private, 2);
+ SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);
+}
+
+
+BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port)
+{
+ UINT32 Value = 0;
+
+ if (0x1610 == SocType)
+ {
+ Value = MmioRead32(RbPciBar + 0x131C);
+ if ((Value & 0x3F) == 0x11)
+ {
+ return TRUE;
+ }
+ return FALSE;
+ }
+ else
+ {
+ Value = MmioRead32 (0xb0000000 + 0x6818 + 0x100 * Port);
+ if ((Value & 0x3F) == 0x11)
+ {
+ return TRUE;
+ }
+ return FALSE;
+ }
+}
+
+/**
+
+ Construct the Pci Root Bridge Io protocol
+
+ @param Protocol Point to protocol instance
+ @param HostBridgeHandle Handle of host bridge
+ @param Attri Attribute of host bridge
+ @param ResAppeture ResourceAppeture for host bridge
+
+ @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
+
+**/
+EFI_STATUS
+RootBridgeConstructor (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
+ IN EFI_HANDLE HostBridgeHandle,
+ IN UINT64 Attri,
+ IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture,
+ IN UINT32 Seg
+ )
+{
+ EFI_STATUS Status;
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+ PCI_RESOURCE_TYPE Index;
+
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);
+
+ //
+ // The host to pci bridge, the host memory and io addresses are
+ // direct mapped to pci addresses, so no need translate, set bases to 0.
+ //
+ PrivateData->MemBase = ResAppeture->MemBase;
+ PrivateData->IoBase = ResAppeture->IoBase;
+ PrivateData->RbPciBar = ResAppeture->RbPciBar;
+ PrivateData->MemLimit = ResAppeture->MemLimit;
+ PrivateData->IoLimit = ResAppeture->IoLimit;
+ PrivateData->Ecam = ResAppeture->Ecam;
+ PrivateData->CpuMemRegionBase = ResAppeture->CpuMemRegionBase;
+ PrivateData->CpuIoRegionBase = ResAppeture->CpuIoRegionBase;
+
+ //
+ // Bus Appeture for this Root Bridge (Possible Range)
+ //
+ PrivateData->BusBase = ResAppeture->BusBase;
+ PrivateData->BusLimit = ResAppeture->BusLimit;
+
+ //
+ // Specific for this chipset
+ //
+ for (Index = TypeIo; Index < TypeMax; Index++) {
+ PrivateData->ResAllocNode[Index].Type = Index;
+ PrivateData->ResAllocNode[Index].Base = 0;
+ PrivateData->ResAllocNode[Index].Length = 0;
+ PrivateData->ResAllocNode[Index].Status = ResNone;
+ }
+
+ PrivateData->RootBridgeAttrib = Attri;
+
+ PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | \
+ EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER;
+ PrivateData->Attributes = PrivateData->Supports;
+
+ Protocol->ParentHandle = HostBridgeHandle;
+
+ Protocol->PollMem = RootBridgeIoPollMem;
+ Protocol->PollIo = RootBridgeIoPollIo;
+
+ Protocol->Mem.Read = RootBridgeIoMemRead;
+ Protocol->Mem.Write = RootBridgeIoMemWrite;
+
+ Protocol->Io.Read = RootBridgeIoIoRead;
+ Protocol->Io.Write = RootBridgeIoIoWrite;
+
+ Protocol->CopyMem = RootBridgeIoCopyMem;
+
+ Protocol->Pci.Read = RootBridgeIoPciRead;
+ Protocol->Pci.Write = RootBridgeIoPciWrite;
+
+ Protocol->Map = RootBridgeIoMap;
+ Protocol->Unmap = RootBridgeIoUnmap;
+
+ Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;
+ Protocol->FreeBuffer = RootBridgeIoFreeBuffer;
+
+ Protocol->Flush = RootBridgeIoFlush;
+
+ Protocol->GetAttributes = RootBridgeIoGetAttributes;
+ Protocol->SetAttributes = RootBridgeIoSetAttributes;
+
+ Protocol->Configuration = RootBridgeIoConfiguration;
+
+ Protocol->SegmentNumber = Seg;
+
+ InitAtu (PrivateData);
+
+ Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR,"LocateProtocol MetronomeArchProtocol Error\n"));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] OperationType I/O operation type: IO/MMIO/PCI.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The parameters for this request pass the checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+EFI_STATUS
+RootBridgeIoCheckParameter (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN OPERATION_TYPE OperationType,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
+ UINT64 MaxCount;
+ UINT64 Base;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiPciWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
+ Count = 1;
+ }
+
+ //
+ // Check to see if Width is in the valid range for I/O Port operations
+ //
+ Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Address is aligned
+ //
+ if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+ //
+ // Check to see if any address associated with this transfer exceeds the maximum
+ // allowed address. The maximum address implied by the parameters passed in is
+ // Address + Size * Count. If the following condition is met, then the transfer
+ // is not supported.
+ //
+ // Address + Size * Count > Limit + 1
+ //
+ // Since Limit can be the maximum integer value supported by the CPU and Count
+ // can also be the maximum integer value supported by the CPU, this range
+ // check must be adjusted to avoid all oveflow conditions.
+ //
+ // The following form of the range check is equivalent but assumes that
+ // Limit is of the form (2^n - 1).
+ //
+ if (OperationType == IoOperation) {
+ Base = PrivateData->IoBase;
+ Limit = PrivateData->IoLimit;
+ } else if (OperationType == MemOperation) {
+ Base = PrivateData->MemBase;
+ Limit = PrivateData->MemLimit;
+ } else {
+ PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
+ if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ /* The root complex has only one device / function */
+ if (PciRbAddr->Bus == PrivateData->BusBase && PciRbAddr->Device != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ /* The other side of the RC has only one device as well */
+ if (PciRbAddr->Bus == (PrivateData->BusBase + 1 ) && PciRbAddr->Device != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (PciRbAddr->ExtendedRegister != 0) {
+ Address = PciRbAddr->ExtendedRegister;
+ } else {
+ Address = PciRbAddr->Register;
+ }
+ Base = 0;
+ Limit = MAX_PCI_REG_ADDRESS;
+ }
+
+ if (Address < Base) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Count == 0) {
+ if (Address > Limit) {
+ return EFI_UNSUPPORTED;
+ }
+ } else {
+ MaxCount = RShiftU64 (Limit, Width);
+ if (MaxCount < (Count - 1)) {
+ return EFI_UNSUPPORTED;
+ }
+ if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Internal help function for read and write memory space.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Write Switch value for Read or Write.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
+ @param[in] Count The number of PCI configuration operations to perform. Bytes
+ moved is Width size * Count, starting at Address.
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+RootBridgeIoMemRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN BOOLEAN Write,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+ /* Address is bus resource */
+ Address -= PrivateData->MemBase;
+ Address += PrivateData->CpuMemRegionBase;
+
+ PCIE_DEBUG("RootBridgeIoMemRW Address:0x%llx\n", Address);
+ PCIE_DEBUG("RootBridgeIoMemRW Count:0x%llx\n", Count);
+ PCIE_DEBUG("RootBridgeIoMemRW Write:0x%llx\n", Write);
+ PCIE_DEBUG("RootBridgeIoMemRW Width:0x%llx\n", Width);
+
+ Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (Write) {
+ switch (OperationWidth) {
+ case EfiPciWidthUint8:
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ break;
+ case EfiPciWidthUint16:
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ break;
+ case EfiPciWidthUint32:
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ break;
+ case EfiPciWidthUint64:
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
+ }
+ } else {
+ switch (OperationWidth) {
+ case EfiPciWidthUint8:
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ break;
+ case EfiPciWidthUint16:
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ break;
+ case EfiPciWidthUint32:
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ break;
+ case EfiPciWidthUint64:
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
+ }
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Internal help function for read and write IO space.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Write Switch value for Read or Write.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
+ @param[in] Count The number of PCI configuration operations to perform. Bytes
+ moved is Width size * Count, starting at Address.
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+RootBridgeIoIoRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN BOOLEAN Write,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+ /* Address is bus resource */
+ Address -= PrivateData->IoBase;
+ Address += PrivateData->CpuIoRegionBase;
+
+ Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (Write) {
+ switch (OperationWidth) {
+ case EfiPciWidthUint8:
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ break;
+ case EfiPciWidthUint16:
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ break;
+ case EfiPciWidthUint32:
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ break;
+ case EfiPciWidthUint64:
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
+ }
+ } else {
+ switch (OperationWidth) {
+ case EfiPciWidthUint8:
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ break;
+ case EfiPciWidthUint16:
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ break;
+ case EfiPciWidthUint32:
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ break;
+ case EfiPciWidthUint64:
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
+ }
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Polls an address in memory mapped I/O space until an exit condition is met, or
+ a timeout occurs.
+
+ This function provides a standard way to poll a PCI memory location. A PCI memory read
+ operation is performed at the PCI memory address specified by Address for the width specified
+ by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
+ read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
+ Mask) is equal to Value.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Address The base address of the memory operations. The caller is
+ responsible for aligning Address if required.
+ @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
+ are ignored. The bits in the bytes below Width which are zero in
+ Mask are ignored when polling the memory address.
+ @param[in] Value The comparison value used for the polling exit criteria.
+ @param[in] Delay The number of 100 ns units to poll. Note that timer available may
+ be of poorer granularity.
+ @param[out] Result Pointer to the last value read from the memory location.
+
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
+ @retval EFI_INVALID_PARAMETER Width is invalid.
+ @retval EFI_INVALID_PARAMETER Result is NULL.
+ @retval EFI_TIMEOUT Delay expired before a match occurred.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ EFI_STATUS Status;
+ UINT64 NumberOfTicks;
+ UINT32 Remainder;
+
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // No matter what, always do a single poll.
+ //
+ Status = This->Mem.Read (This, Width, Address, 1, Result);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if ((*Result & Mask) == Value) {
+ return EFI_SUCCESS;
+ }
+
+ if (Delay == 0) {
+ return EFI_TIMEOUT;
+
+ } else {
+
+ //
+ // Determine the proper # of metronome ticks to wait for polling the
+ // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
+ // The "+1" to account for the possibility of the first tick being short
+ // because we started in the middle of a tick.
+ //
+ // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
+ // protocol definition is updated.
+ //
+ NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);
+ if (Remainder != 0) {
+ NumberOfTicks += 1;
+ }
+ NumberOfTicks += 1;
+
+ while (NumberOfTicks != 0) {
+
+ mMetronome->WaitForTick (mMetronome, 1);
+
+ Status = This->Mem.Read (This, Width, Address, 1, Result);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((*Result & Mask) == Value) {
+ return EFI_SUCCESS;
+ }
+
+ NumberOfTicks -= 1;
+ }
+ }
+ return EFI_TIMEOUT;
+}
+
+/**
+ Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
+ satisfied or after a defined duration.
+
+ This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
+ performed at the PCI I/O address specified by Address for the width specified by Width.
+ The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
+ repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
+ to Value.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the I/O operations.
+ @param[in] Address The base address of the I/O operations. The caller is responsible
+ for aligning Address if required.
+ @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
+ are ignored. The bits in the bytes below Width which are zero in
+ Mask are ignored when polling the I/O address.
+ @param[in] Value The comparison value used for the polling exit criteria.
+ @param[in] Delay The number of 100 ns units to poll. Note that timer available may
+ be of poorer granularity.
+ @param[out] Result Pointer to the last value read from the memory location.
+
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
+ @retval EFI_INVALID_PARAMETER Width is invalid.
+ @retval EFI_INVALID_PARAMETER Result is NULL.
+ @retval EFI_TIMEOUT Delay expired before a match occurred.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollIo (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ EFI_STATUS Status;
+ UINT64 NumberOfTicks;
+ UINT32 Remainder;
+
+ //
+ // No matter what, always do a single poll.
+ //
+
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = This->Io.Read (This, Width, Address, 1, Result);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if ((*Result & Mask) == Value) {
+ return EFI_SUCCESS;
+ }
+
+ if (Delay == 0) {
+ return EFI_SUCCESS;
+
+ } else {
+
+ //
+ // Determine the proper # of metronome ticks to wait for polling the
+ // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
+ // The "+1" to account for the possibility of the first tick being short
+ // because we started in the middle of a tick.
+ //
+ NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);
+ if (Remainder != 0) {
+ NumberOfTicks += 1;
+ }
+ NumberOfTicks += 1;
+
+ while (NumberOfTicks != 0) {
+
+ mMetronome->WaitForTick (mMetronome, 1);
+
+ Status = This->Io.Read (This, Width, Address, 1, Result);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((*Result & Mask) == Value) {
+ return EFI_SUCCESS;
+ }
+
+ NumberOfTicks -= 1;
+ }
+ }
+ return EFI_TIMEOUT;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
+ registers in the PCI root bridge memory space.
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+ any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operation.
+ @param[in] Address The base address of the memory operation. The caller is
+ responsible for aligning the Address if required.
+ @param[in] Count The number of memory operations to perform. Bytes moved is
+ Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
+ registers in the PCI root bridge memory space.
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+ any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operation.
+ @param[in] Address The base address of the memory operation. The caller is
+ responsible for aligning the Address if required.
+ @param[in] Count The number of memory operations to perform. Bytes moved is
+ Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Address The base address of the I/O operation. The caller is responsible for
+ aligning the Address if required.
+ @param[in] Count The number of I/O operations to perform. Bytes moved is Width
+ size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Address The base address of the I/O operation. The caller is responsible for
+ aligning the Address if required.
+ @param[in] Count The number of I/O operations to perform. Bytes moved is Width
+ size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);
+}
+
+/**
+ Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
+ root bridge memory space.
+
+ The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
+ space to another region of PCI root bridge memory space. This is especially useful for video scroll
+ operation on a memory mapped video buffer.
+ The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+ any alignment and memory width restrictions that a PCI root bridge on a platform might require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] DestAddress The destination address of the memory operation. The caller is
+ responsible for aligning the DestAddress if required.
+ @param[in] SrcAddress The source address of the memory operation. The caller is
+ responsible for aligning the SrcAddress if required.
+ @param[in] Count The number of memory operations to perform. Bytes moved is
+ Width size * Count, starting at DestAddress and SrcAddress.
+
+ @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoCopyMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN Direction;
+ UINTN Stride;
+ UINTN Index;
+ UINT64 Result;
+
+ if ((UINT32)Width > EfiPciWidthUint64) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (DestAddress == SrcAddress) {
+ return EFI_SUCCESS;
+ }
+
+ Stride = (UINTN)((UINTN)1 << Width);
+
+ Direction = TRUE;
+ if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {
+ Direction = FALSE;
+ SrcAddress = SrcAddress + (Count-1) * Stride;
+ DestAddress = DestAddress + (Count-1) * Stride;
+ }
+
+ for (Index = 0;Index < Count;Index++) {
+ Status = RootBridgeIoMemRead (
+ This,
+ Width,
+ SrcAddress,
+ 1,
+ &Result
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ Status = RootBridgeIoMemWrite (
+ This,
+ Width,
+ DestAddress,
+ 1,
+ &Result
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if (Direction) {
+ SrcAddress += Stride;
+ DestAddress += Stride;
+ } else {
+ SrcAddress -= Stride;
+ DestAddress -= Stride;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads memory-mapped registers.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+EFI_STATUS
+CpuMemoryServiceRead (
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+ UINT32 Uint32Buffer = 0;
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3)));
+ Uint32Buffer &= (0xFF << ((Address & 0x3) * 8));
+ *((UINT8*)Uint8Buffer) = (UINT8)(Uint32Buffer >> (((Address & 0x3) * 8)));
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ if (((Address & 0x3) == 1) || ((Address & 0x3) == 3)) {
+ return EFI_INVALID_PARAMETER;
+ }
+ Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3)));
+ Uint32Buffer &= (0xFFFF << ((Address & 0x3) * 8));
+ *(UINT16 *)Uint8Buffer = (UINT16)(Uint32Buffer >> (((Address & 0x3) * 8)));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+ The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
+ registers for a PCI controller.
+ The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
+ any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
+ require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Address The address within the PCI configuration space for the PCI controller.
+ @param[in] Count The number of PCI configuration operations to perform. Bytes
+ moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 EfiAddress,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ UINT32 Offset;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress;
+ UINT64 Address;
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+
+ EfiPciAddress = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress;
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
+
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Width >= EfiPciWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (EfiPciAddress->ExtendedRegister) {
+ Offset = EfiPciAddress->ExtendedRegister;
+ } else {
+ Offset = EfiPciAddress->Register;
+ }
+
+ PCIE_DEBUG ("[%a:%d] - bus %x dev %x func %x Off %x\n", __FUNCTION__, __LINE__,
+ EfiPciAddress->Bus,
+ EfiPciAddress->Device,
+ EfiPciAddress->Function,
+ Offset
+ );
+ if (EfiPciAddress->Bus < PrivateData->BusBase || EfiPciAddress->Bus > PrivateData->BusLimit) {
+ PCIE_DEBUG ("[%a:%d] - Bus number out of range %d\n", __FUNCTION__, __LINE__, EfiPciAddress->Bus);
+ SetMem (Buffer, mOutStride[Width] * Count, 0xFF);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // The UEFI PCI enumerator scans for devices at all possible addresses,
+ // and ignores some PCI rules - this results in some hardware being
+ // detected multiple times. We work around this by faking absent
+ // devices
+ if(EfiPciAddress->Bus == PrivateData->BusBase)
+ {
+ if((EfiPciAddress->Device != 0x0) || (EfiPciAddress->Function != 0)) {
+ SetMem (Buffer, mOutStride[Width] * Count, 0xFF);
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ if (EfiPciAddress->Bus == PrivateData->BusBase){
+ Address = PrivateData->RbPciBar + Offset;
+ }
+ else if(EfiPciAddress->Bus == PrivateData->BusBase + 1)
+ {
+ if (!PcieIsLinkUp(PrivateData->SocType,PrivateData->RbPciBar, PrivateData->Port))
+ {
+ SetMem (Buffer, mOutStride[Width] * Count, 0xFF);
+ return EFI_NOT_READY;
+ }
+ Address = GetPcieCfgAddress (
+ PrivateData->Ecam,
+ EfiPciAddress->Bus,
+ EfiPciAddress->Device,
+ EfiPciAddress->Function,
+ Offset
+ );
+ }
+ else
+ {
+ Address = GetPcieCfgAddress (
+ PrivateData->Ecam,
+ EfiPciAddress->Bus,
+ EfiPciAddress->Device,
+ EfiPciAddress->Function,
+ Offset
+ );
+ }
+
+ (VOID)CpuMemoryServiceRead((EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);
+ PCIE_DEBUG ("[%a:%d] - %x\n", __FUNCTION__, __LINE__, *(UINT32 *)Buffer);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes memory-mapped registers.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+EFI_STATUS
+CpuMemoryServiceWrite (
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+ UINT32 Uint32Buffer;
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ Uint32Buffer = MmioRead32 ((UINTN)(Address & (~0x03)));
+ Uint32Buffer &= ~(UINT32)(0xFF << ((Address & 0x3) * 8));
+ Uint32Buffer |= (UINT32)(*(UINT8 *)Uint8Buffer) << ((Address & 0x3) * 8);
+ MmioWrite32 ((UINTN)(Address & (~0x03)), Uint32Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ if (((Address & 0x3) == 1) || ((Address & 0x3) == 3)) {
+ return EFI_INVALID_PARAMETER;
+ }
+ Uint32Buffer = MmioRead32 ((UINTN)(Address & (~0x03)));
+ Uint32Buffer &= ~(UINT32)(0xFFFF << ((Address & 0x3) * 8));
+ Uint32Buffer |= (UINT32)(*(UINT16 *)Uint8Buffer) << ((Address & 0x3) * 8);
+ MmioWrite32 ((UINTN)(Address & (~0x03)), Uint32Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+ The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
+ registers for a PCI controller.
+ The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
+ any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
+ require.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Width Signifies the width of the memory operations.
+ @param[in] Address The address within the PCI configuration space for the PCI controller.
+ @param[in] Count The number of PCI configuration operations to perform. Bytes
+ moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results. For
+ write operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 EfiAddress,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT32 Offset;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress;
+ UINT64 Address;
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+
+ EfiPciAddress = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress;
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
+
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Width >= EfiPciWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (EfiPciAddress->ExtendedRegister)
+ Offset = EfiPciAddress->ExtendedRegister;
+ else
+ Offset = EfiPciAddress->Register;
+
+ PCIE_DEBUG ("[%a:%d] - bus %x dev %x func %x Off %x\n", __FUNCTION__, __LINE__,
+ EfiPciAddress->Bus,
+ EfiPciAddress->Device,
+ EfiPciAddress->Function,
+ Offset
+ );
+ if (((EfiPciAddress->Bus == PrivateData->BusBase) && (EfiPciAddress->Device == 0x00) && (EfiPciAddress->Function == 0))){
+ Address = PrivateData->RbPciBar + Offset;
+ if ((Offset == 0x14) || (Offset == 0x10)) {
+ return EFI_SUCCESS;
+ }
+ }
+ else if (EfiPciAddress->Bus == PrivateData->BusBase + 1)
+ {
+ if (!PcieIsLinkUp(PrivateData->SocType,PrivateData->RbPciBar, PrivateData->Port)) {
+ return EFI_NOT_READY;
+ }
+ Address = GetPcieCfgAddress (
+ PrivateData->Ecam,
+ EfiPciAddress->Bus,
+ EfiPciAddress->Device,
+ EfiPciAddress->Function,
+ Offset
+ );
+ }
+ else
+ {
+ Address = GetPcieCfgAddress (
+ PrivateData->Ecam,
+ EfiPciAddress->Bus,
+ EfiPciAddress->Device,
+ EfiPciAddress->Function,
+ Offset
+ );
+ }
+
+ (VOID)CpuMemoryServiceWrite ((EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);
+ PCIE_DEBUG ("[%a:%d] - 0x%08x\n", __FUNCTION__, __LINE__, *(UINT32 *)Buffer);
+ return EFI_SUCCESS;
+}
+
+/**
+ Provides the PCI controller-specific addresses required to access system memory from a
+ DMA bus master.
+
+ The Map() function provides the PCI controller specific addresses needed to access system
+ memory. This function is used to map system memory for PCI bus master DMA accesses.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Operation Indicates if the bus master is going to read or write to system memory.
+ @param[in] HostAddress The system memory address to map to the PCI controller.
+ @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
+ @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
+ to access the system memory's HostAddress.
+ @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
+
+ @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
+ @retval EFI_INVALID_PARAMETER Operation is invalid.
+ @retval EFI_INVALID_PARAMETER HostAddress is NULL.
+ @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
+ @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
+ @retval EFI_INVALID_PARAMETER Mapping is NULL.
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
+ @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ )
+{
+ DMA_MAP_OPERATION DmaOperation;
+
+ if (Operation == EfiPciOperationBusMasterRead) {
+ DmaOperation = MapOperationBusMasterRead;
+ } else if (Operation == EfiPciOperationBusMasterWrite) {
+ DmaOperation = MapOperationBusMasterWrite;
+ } else if (Operation == EfiPciOperationBusMasterCommonBuffer) {
+ DmaOperation = MapOperationBusMasterCommonBuffer;
+ } else if (Operation == EfiPciOperationBusMasterRead64) {
+ DmaOperation = MapOperationBusMasterRead;
+ } else if (Operation == EfiPciOperationBusMasterWrite64) {
+ DmaOperation = MapOperationBusMasterWrite;
+ } else if (Operation == EfiPciOperationBusMasterCommonBuffer64) {
+ DmaOperation = MapOperationBusMasterCommonBuffer;
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+ (VOID)DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
+ return EFI_SUCCESS;
+}
+
+/**
+ Completes the Map() operation and releases any corresponding resources.
+
+ The Unmap() function completes the Map() operation and releases any corresponding resources.
+ If the operation was an EfiPciOperationBusMasterWrite or
+ EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
+ Any resources used for the mapping are freed.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Mapping The mapping value returned from Map().
+
+ @retval EFI_SUCCESS The range was unmapped.
+ @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
+ @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoUnmap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ )
+{
+ return DmaUnmap (Mapping);
+}
+
+/**
+ Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
+ EfiPciOperationBusMasterCommonBuffer64 mapping.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Type This parameter is not used and must be ignored.
+ @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
+ @param Pages The number of pages to allocate.
+ @param HostAddress A pointer to store the base system memory address of the allocated range.
+ @param Attributes The requested bit mask of attributes for the allocated range. Only
+ the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
+ and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
+
+ @retval EFI_SUCCESS The requested memory pages were allocated.
+ @retval EFI_INVALID_PARAMETER MemoryType is invalid.
+ @retval EFI_INVALID_PARAMETER HostAddress is NULL.
+ @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoAllocateBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ )
+{
+ if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
+
+}
+
+/**
+ Frees memory that was allocated with AllocateBuffer().
+
+ The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Pages The number of pages to free.
+ @param HostAddress The base system memory address of the allocated range.
+
+ @retval EFI_SUCCESS The requested memory pages were freed.
+ @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
+ was not allocated with AllocateBuffer().
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFreeBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ OUT VOID *HostAddress
+ )
+{
+ return DmaFreeBuffer (Pages, HostAddress);
+}
+
+/**
+ Flushes all PCI posted write transactions from a PCI host bridge to system memory.
+
+ The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
+ memory. Posted write transactions are generated by PCI bus masters when they perform write
+ transactions to target addresses in system memory.
+ This function does not flush posted write transactions from any PCI bridges. A PCI controller
+ specific action must be taken to guarantee that the posted write transactions have been flushed from
+ the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
+ a PCI read transaction from the PCI controller prior to calling Flush().
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+
+ @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
+ bridge to system memory.
+ @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
+ host bridge due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFlush (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
+ )
+{
+ //
+ // not supported yet
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
+ attributes that a PCI root bridge is currently using.
+
+ The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
+ and the mask of attributes that the PCI root bridge is currently using.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Supported A pointer to the mask of attributes that this PCI root bridge
+ supports setting with SetAttributes().
+ @param Attributes A pointer to the mask of attributes that this PCI root bridge is
+ currently using.
+
+ @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
+ bridge supports is returned in Supports. If Attributes is
+ not NULL, then the attributes that the PCI root bridge is currently
+ using is returned in Attributes.
+ @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoGetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT UINT64 *Supported,
+ OUT UINT64 *Attributes
+ )
+{
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
+
+ if (Attributes == NULL && Supported == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Set the return value for Supported and Attributes
+ //
+ if (Supported != NULL) {
+ *Supported = PrivateData->Supports;
+ }
+
+ if (Attributes != NULL) {
+ *Attributes = PrivateData->Attributes;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Sets attributes for a resource range on a PCI root bridge.
+
+ The SetAttributes() function sets the attributes specified in Attributes for the PCI root
+ bridge on the resource range specified by ResourceBase and ResourceLength. Since the
+ granularity of setting these attributes may vary from resource type to resource type, and from
+ platform to platform, the actual resource range and the one passed in by the caller may differ. As a
+ result, this function may set the attributes specified by Attributes on a larger resource range
+ than the caller requested. The actual range is returned in ResourceBase and
+ ResourceLength. The caller is responsible for verifying that the actual range for which the
+ attributes were set is acceptable.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[in] Attributes The mask of attributes to set. If the attribute bit
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
+ MEMORY_DISABLE is set, then the resource range is specified by
+ ResourceBase and ResourceLength. If
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
+ MEMORY_DISABLE are not set, then ResourceBase and
+ ResourceLength are ignored, and may be NULL.
+ @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
+ by the attributes specified by Attributes.
+ @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
+ attributes specified by Attributes.
+
+ @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
+ @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
+ @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoSetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN OUT UINT64 *ResourceBase,
+ IN OUT UINT64 *ResourceLength
+ )
+{
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
+
+ if (Attributes != 0) {
+ if ((Attributes & (~(PrivateData->Supports))) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ //
+ // This is a generic driver for a PC-AT class system. It does not have any
+ // chipset specific knowlegde, so none of the attributes can be set or
+ // cleared. Any attempt to set attribute that are already set will succeed,
+ // and any attempt to set an attribute that is not supported will fail.
+ //
+ if (Attributes & (~PrivateData->Attributes)) {
+ /* FIXME: */
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
+ resource descriptors.
+
+ There are only two resource descriptor types from the ACPI Specification that may be used to
+ describe the current resources allocated to a PCI root bridge. These are the QWORD Address
+ Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
+ QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
+ or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
+ Address Space Descriptors followed by an End Tag.
+
+ @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
+ current configuration of this PCI root bridge. The storage for the
+ ACPI 2.0 resource descriptors is allocated by this function. The
+ caller must treat the return buffer as read-only data, and the buffer
+ must not be freed by the caller.
+
+ @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
+ @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
+ @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoConfiguration (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT VOID **Resources
+ )
+{
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+ UINTN Index;
+
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+ for (Index = 0; Index < TypeMax; Index++) {
+ if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
+ Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
+ Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
+ Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;
+ }
+ }
+
+ *Resources = &Configuration;
+ return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
new file mode 100644
index 0000000..8d8dacd
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
@@ -0,0 +1,205 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "AddSmbiosType9.h"
+
+extern SMBIOS_TABLE_TYPE9 gPcieSlotInfo[];
+extern UINT8 OemGetPcieSlotNumber ();
+
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
+ {67,0,0,0},
+ {225,0,0,3},
+ {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+VOID
+EFIAPI
+UpdateSmbiosType9Info(
+ IN OUT SMBIOS_TABLE_TYPE9 *Type9Record
+)
+{
+ EFI_STATUS Status;
+ UINTN HandleIndex;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINTN SegmentNumber;
+ UINTN BusNumber;
+ UINTN DeviceNumber;
+ UINTN FunctionNumber;
+ UINTN Index;
+ REPORT_PCIEDIDVID2BMC ReportPcieDidVid[PCIEDEVICE_REPORT_MAX];
+ if(OemIsMpBoot()){
+ (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport_2P,sizeof(PcieDeviceToReport_2P));
+ } else {
+ (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport,sizeof(PcieDeviceToReport));
+ }
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if(EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, " Locate gEfiPciIoProtocol Failed.\n"));
+ gBS->FreePool ((VOID *)HandleBuffer);
+ return;
+ }
+ for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[HandleIndex],
+ &gEfiPciIoProtocolGuid,
+ (VOID **)&PciIo
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LINE__, Status));
+ continue;
+ }
+ (VOID)PciIo->GetLocation(PciIo, &SegmentNumber, &BusNumber, &DeviceNumber, &FunctionNumber);
+ for(Index = 0; Index < sizeof(ReportPcieDidVid) / sizeof(REPORT_PCIEDIDVID2BMC); Index++){
+ if (Type9Record->SlotID == ReportPcieDidVid[Index].Slot + 1) {
+ if((BusNumber == ReportPcieDidVid[Index].Bus) && (DeviceNumber == ReportPcieDidVid[Index].Device)) {
+ DEBUG((EFI_D_ERROR,"PCIe device plot in slot Seg %d bdf %d %d %d\r\n",SegmentNumber,BusNumber,DeviceNumber,FunctionNumber));
+ Type9Record->SegmentGroupNum = SegmentNumber;
+ Type9Record->BusNum = BusNumber;
+ Type9Record->DevFuncNum = (DeviceNumber << 3) | FunctionNumber;
+ Type9Record->CurrentUsage = SlotUsageInUse;
+ break;
+ }
+ }
+ }
+ }
+ gBS->FreePool ((VOID *)HandleBuffer);
+ return;
+}
+EFI_STATUS
+EFIAPI
+AddSmbiosType9Entry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_TYPE SmbiosType;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ EFI_SMBIOS_PROTOCOL *Smbios;
+ EFI_SMBIOS_TABLE_HEADER *Record;
+ SMBIOS_TABLE_TYPE9 *Type9Record;
+ SMBIOS_TABLE_TYPE9 *SmbiosRecord = NULL;
+ CHAR8 *OptionalStrStart;
+
+ UINT8 SmbiosAddType9Number;
+ UINT8 Index;
+
+ CHAR16 *SlotDesignation = NULL;
+ UINTN SlotDesignationStrLen;
+
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **) &Smbios
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol Failed. Status : %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ do {
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ SmbiosType = EFI_SMBIOS_TYPE_SYSTEM_SLOTS;
+ Status = Smbios->GetNext (Smbios, &SmbiosHandle, &SmbiosType, &Record, NULL);
+ if (!EFI_ERROR(Status)) {
+ Status = Smbios->Remove (Smbios, SmbiosHandle);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Remove System Slot Failed. Status : %r\n", __FUNCTION__, __LINE__, Status));
+ break;
+ }
+ }
+ } while (SmbiosHandle != SMBIOS_HANDLE_PI_RESERVED);
+
+ SmbiosAddType9Number = OemGetPcieSlotNumber();
+
+ for (Index = 0; Index < SmbiosAddType9Number; Index++)
+ {
+ if (gPcieSlotInfo[Index].Hdr.Type != EFI_SMBIOS_TYPE_SYSTEM_SLOTS)
+ {
+ continue;
+ }
+
+ Type9Record = &gPcieSlotInfo[Index];
+
+ UpdateSmbiosType9Info (Type9Record);
+ SlotDesignation = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+ if (NULL == SlotDesignation)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] AllocateZeroPool Failed. Status : %r\n", __FUNCTION__, __LINE__, Status));
+
+ goto Exit;
+ }
+
+ SlotDesignationStrLen = UnicodeSPrint (SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE Slot%d", Type9Record->SlotID);
+
+ //
+ // Two zeros following the last string.
+ //
+ SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE9) + SlotDesignationStrLen + 1 + 1);
+ if(NULL == SmbiosRecord)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] AllocateZeroPool Failed. Status : %r\n", __FUNCTION__, __LINE__, Status));
+
+ goto Exit;
+ }
+
+ (VOID)CopyMem(SmbiosRecord, Type9Record, sizeof (SMBIOS_TABLE_TYPE9));
+
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9);
+
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+ UnicodeStrToAsciiStr(SlotDesignation, OptionalStrStart);
+
+ //
+ // Now we have got the full smbios record, call smbios protocol to add this record.
+ //
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = Smbios->Add (Smbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)SmbiosRecord);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type09 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ goto Exit;
+ }
+
+ FreePool(SmbiosRecord);
+ FreePool(SlotDesignation);
+ }
+
+ return EFI_SUCCESS;
+
+Exit:
+ if(SmbiosRecord != NULL)
+ {
+ FreePool(SmbiosRecord);
+ }
+
+ if(SlotDesignation != NULL)
+ {
+ FreePool(SlotDesignation);
+ }
+
+ return Status;
+}
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.h b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.h
new file mode 100644
index 0000000..5766152
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.h
@@ -0,0 +1,36 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _ADD_SMBIOS_TYPE9_H_
+#define _ADD_SMBIOS_TYPE9_H_
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/SmBios.h>
+#include <Protocol/Smbios.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/OemMiscLib.h>
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
new file mode 100644
index 0000000..a90399b
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AddSmbiosType9
+ FILE_GUID = 7AE6F104-66DF-48EF-B5A3-5050BF4908F0
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = AddSmbiosType9Entry
+
+[Sources]
+ AddSmbiosType9.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiLib
+ UefiDriverEntryPoint
+ OemMiscLib
+
+[Protocols]
+ gEfiSmbiosProtocolGuid
+ gEfiPciIoProtocolGuid
+
+[Guids]
+
+[Pcd]
+
+[Depex]
+ gEfiSmbiosProtocolGuid AND
+ gEfiPciIoProtocolGuid
diff --git a/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
new file mode 100644
index 0000000..da714c9
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
@@ -0,0 +1,762 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include "MemorySubClass.h"
+
+EFI_SMBIOS_PROTOCOL *mSmbios = NULL;
+EFI_HII_HANDLE mHiiHandle;
+
+UINT8 mMaxSkt;
+UINT8 mMaxCh;
+
+VOID
+SmbiosGetManufacturer (
+ IN UINT8 MfgIdLSB,
+ IN UINT8 MfgIdMSB,
+ OUT CHAR16 *Manufacturer
+)
+{
+ UINT32 Index = 0;
+
+ (VOID)StrCpyS(Manufacturer, SMBIOS_STRING_MAX_LENGTH - 1, L"Unknown");
+ while (JEP106[Index].MfgIdLSB != 0xFF && JEP106[Index].MfgIdMSB != 0xFF )
+ {
+ if (JEP106[Index].MfgIdLSB == MfgIdLSB && JEP106[Index].MfgIdMSB == MfgIdMSB)
+ {
+ (VOID)StrCpyS (Manufacturer, SMBIOS_STRING_MAX_LENGTH - 1, JEP106[Index].Name);
+ break;
+ }
+ Index++;
+ }
+}
+
+VOID
+SmbiosGetPartNumber (
+ IN pGBL_DATA pGblData,
+ IN UINT8 Skt,
+ IN UINT8 Ch,
+ IN UINT8 Dimm,
+ OUT CHAR16 *PartNumber
+ )
+{
+ CHAR16 StringBuffer2[SMBIOS_STRING_MAX_LENGTH];
+ UINT32 Index2;
+
+ (VOID)StrCpyS(PartNumber, SMBIOS_STRING_MAX_LENGTH - 1, L"");
+ if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR3)
+ {
+ for (Index2 = 0; Index2 < SPD_MODULE_PART; Index2++)
+ {
+ UnicodeSPrint (StringBuffer2, SMBIOS_STRING_MAX_LENGTH - 1, L"%c", pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdModPart[Index2]);
+ (VOID)StrCatS(PartNumber, SMBIOS_STRING_MAX_LENGTH - 1, StringBuffer2);
+ }
+ }
+ else
+ {
+ for (Index2 = 0; Index2 < SPD_MODULE_PART_DDR4; Index2++)
+ {
+ UnicodeSPrint (StringBuffer2, SMBIOS_STRING_MAX_LENGTH - 1, L"%c", pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdModPartDDR4[Index2]);
+ (VOID)StrCatS(PartNumber, SMBIOS_STRING_MAX_LENGTH - 1, StringBuffer2);
+ }
+ }
+
+ return;
+}
+
+VOID
+SmbiosGetSerialNumber (
+ IN pGBL_DATA pGblData,
+ IN UINT8 Skt,
+ IN UINT8 Ch,
+ IN UINT8 Dimm,
+ OUT CHAR16 *SerialNumber
+ )
+{
+ UINT32 Temp;
+
+ Temp = SwapBytes32 (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdSerialNum);
+
+ UnicodeSPrint(SerialNumber, SMBIOS_STRING_MAX_LENGTH, L"0x%08x", Temp);
+
+ return;
+}
+
+BOOLEAN
+IsDimmPresent (
+ IN pGBL_DATA pGblData,
+ IN UINT8 Skt,
+ IN UINT8 Ch,
+ IN UINT8 Dimm
+)
+{
+ if (pGblData->Channel[Skt][Ch].Status == FALSE ||
+ pGblData->Channel[Skt][Ch].Dimm[Dimm].Status == FALSE)
+ {
+ return FALSE;
+ }
+ else
+ {
+ return TRUE;
+ }
+}
+
+UINT8
+SmbiosGetMemoryType (
+ IN pGBL_DATA pGblData,
+ IN UINT8 Skt,
+ IN UINT8 Ch,
+ IN UINT8 Dimm
+)
+{
+ UINT8 MemoryType;
+
+ if(!IsDimmPresent(pGblData, Skt, Ch, Dimm))
+ {
+ return MemoryTypeUnknown;
+ }
+
+ if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR3)
+ {
+ MemoryType = MemoryTypeDdr3;
+ }
+ else if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR4)
+ {
+ MemoryType = MemoryTypeDdr4;
+ }
+ else
+ {
+ MemoryType = MemoryTypeUnknown;
+ }
+
+ return MemoryType;
+}
+
+VOID
+SmbiosGetTypeDetail (
+ IN pGBL_DATA pGblData,
+ IN UINT8 Skt,
+ IN UINT8 Ch,
+ IN UINT8 Dimm,
+ IN OUT MEMORY_DEVICE_TYPE_DETAIL *TypeDetail
+)
+{
+ if (NULL == TypeDetail)
+ {
+ return;
+ }
+
+ if(!IsDimmPresent(pGblData, Skt, Ch, Dimm))
+ {
+ TypeDetail->Unknown = 1;
+ return;
+ }
+
+ switch (pGblData->Channel[Skt][Ch].Dimm[Dimm].ModuleType)
+ {
+ case SPD_UDIMM:
+ TypeDetail->Unbuffered = 1;
+ break;
+
+ case SPD_LRDIMM:
+ TypeDetail->LrDimm = 1;
+ break;
+
+ case SPD_RDIMM:
+ TypeDetail->Registered = 1;
+ break;
+
+ default:
+ TypeDetail->Unknown = 1;
+ break;
+ }
+}
+
+VOID
+SmbiosGetDimmVoltageInfo (
+ IN pGBL_DATA pGblData,
+ IN UINT8 Skt,
+ IN UINT8 Ch,
+ IN UINT8 Dimm,
+ IN OUT SMBIOS_TABLE_TYPE17 *Type17Record
+
+)
+{
+ if(!IsDimmPresent(pGblData, Skt, Ch, Dimm))
+ {
+ return;
+ }
+
+ if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR3)
+ {
+ Type17Record->MinimumVoltage = 1250;
+ Type17Record->MaximumVoltage = 1500;
+
+ switch (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdVdd)
+ {
+ case SPD_VDD_150:
+ Type17Record->ConfiguredVoltage = 1500;
+ break;
+
+ case SPD_VDD_135:
+ Type17Record->ConfiguredVoltage = 1350;
+ break;
+
+ case SPD_VDD_125:
+ Type17Record->ConfiguredVoltage = 1250;
+ break;
+
+ default:
+ break;
+ }
+ }
+ else if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR4)
+ {
+ Type17Record->MinimumVoltage = 1200;
+ Type17Record->MaximumVoltage = 2000;
+ switch (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdVdd)
+ {
+ case SPD_VDD_120:
+ Type17Record->ConfiguredVoltage = 1200;
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+VOID
+SmbiosGetMemoryDevicesNumber (
+ IN OUT UINT16 *NumberOfDevices
+)
+{
+ UINT8 Skt, Ch, Dimm;
+
+ for(Skt = 0; Skt < mMaxSkt; Skt++)
+ {
+ for(Ch = 0; Ch < mMaxCh; Ch++)
+ {
+ for(Dimm = 0; Dimm < OemGetDimmSlot(Skt, Ch); Dimm++)
+ {
+ (*NumberOfDevices)++;
+ }
+ }
+ }
+}
+
+UINT8
+SmbiosGetPartitionWidth (
+)
+{
+
+ UINT8 Skt, Ch, Dimm;
+ UINT8 PartitionWidth = 0;
+
+ for(Skt = 0; Skt < mMaxSkt; Skt++)
+ {
+ for(Ch = 0; Ch < mMaxCh; Ch++)
+ {
+ for(Dimm = 0; Dimm < OemGetDimmSlot(Skt, Ch); Dimm++)
+ {
+ PartitionWidth++;
+ }
+ }
+ }
+
+ return PartitionWidth;
+}
+
+EFI_STATUS
+SmbiosAddType16Table (
+ IN pGBL_DATA pGblData,
+ OUT EFI_SMBIOS_HANDLE *MemArraySmbiosHandle
+ )
+{
+ EFI_STATUS Status;
+ UINT64 MemoryCapacity;
+ SMBIOS_TABLE_TYPE16 *Type16Record;
+
+ UINT16 NumberOfMemoryDevices = 0;
+
+ SmbiosGetMemoryDevicesNumber (&NumberOfMemoryDevices);
+
+ MemoryCapacity = (UINT64) LShiftU64 (NumberOfMemoryDevices * MAX_DIMM_SIZE, 20); // GB to KB.
+
+ //
+ // Type 16 SMBIOS Record
+ //
+ Type16Record = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE16) + 1 + 1);
+ if (NULL == Type16Record)
+ {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Type16Record->Hdr.Type = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY;
+ Type16Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE16);
+ Type16Record->Hdr.Handle = 0x0;
+ Type16Record->Location = MemoryArrayLocationSystemBoard;
+ Type16Record->Use = MemoryArrayUseSystemMemory;
+ Type16Record->MemoryErrorInformationHandle = 0xFFFE;
+ Type16Record->NumberOfMemoryDevices = NumberOfMemoryDevices;
+
+ if(pGblData->EccEn)
+ {
+ Type16Record->MemoryErrorCorrection = MemoryErrorCorrectionSingleBitEcc;
+ }
+ else
+ {
+ Type16Record->MemoryErrorCorrection = MemoryErrorCorrectionNone;
+ }
+
+ if (MemoryCapacity >= 0x80000000)
+ {
+ Type16Record->MaximumCapacity = 0x80000000; // in KB;
+ Type16Record->ExtendedMaximumCapacity = MemoryCapacity << 10; // Extended Max capacity should be stored in bytes.
+ }
+ else
+ {
+ Type16Record->MaximumCapacity = (UINT32)MemoryCapacity; // Max capacity should be stored in kilo bytes.
+ Type16Record->ExtendedMaximumCapacity = 0;
+ }
+
+ *MemArraySmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbios->Add (mSmbios, NULL, MemArraySmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type16Record);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type16 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(Type16Record);
+ return Status;
+}
+
+EFI_STATUS
+SmbiosAddType19Table (
+ IN pGBL_DATA pGblData,
+ IN EFI_SMBIOS_HANDLE MemArraySmbiosHandle
+ )
+{
+ EFI_STATUS Status;
+ UINT32 MemInfoTotalMem;
+ UINT64 TotalMemorySize;
+ EFI_SMBIOS_HANDLE MemArrayMappedAddrSmbiosHandle;
+ SMBIOS_TABLE_TYPE19 *Type19Record;
+
+ MemInfoTotalMem = pGblData->MemSize; // In MB
+
+ if (MemInfoTotalMem == 0)
+ {
+ return EFI_NOT_FOUND;
+ }
+
+ TotalMemorySize = (UINT64) LShiftU64 (MemInfoTotalMem, 10); // MB to KB.
+
+ //
+ // Type 19 SMBIOS Record
+ //
+ Type19Record = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE19) + 1 + 1);
+ if (NULL == Type19Record)
+ {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Type19Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS;
+ Type19Record->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE19);
+ Type19Record->Hdr.Handle = 0x0;
+ Type19Record->StartingAddress = 0x0;
+ Type19Record->EndingAddress = (UINT32) (TotalMemorySize - 1); // in KB;
+ Type19Record->MemoryArrayHandle = MemArraySmbiosHandle;
+ Type19Record->PartitionWidth = SmbiosGetPartitionWidth ();
+ Type19Record->ExtendedStartingAddress = 0x0;
+ Type19Record->ExtendedEndingAddress = 0x0;
+
+ MemArrayMappedAddrSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbios->Add (mSmbios, NULL, &MemArrayMappedAddrSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type19Record);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type19 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(Type19Record);
+ return Status;
+}
+
+
+EFI_STATUS
+SmbiosAddType17Table (
+ IN pGBL_DATA pGblData,
+ IN UINT8 Skt,
+ IN UINT8 Ch,
+ IN UINT8 Dimm,
+ IN EFI_SMBIOS_HANDLE MemArraySmbiosHandle
+ )
+{
+ EFI_STATUS Status;
+ SMBIOS_TABLE_TYPE17 *Type17Record;
+ EFI_SMBIOS_HANDLE MemDevSmbiosHandle;
+ UINTN TableSize;
+
+ UINTN StringBufferSize;
+ EFI_STRING StringBuffer;
+ UINT16 MemInfoMemFreq;
+ UINT16 MemoryTotalWidth;
+ UINT16 MemoryDataWidth;
+ UINT16 MemoryDeviceSize;
+ UINT16 MemorySpeed;
+ UINT8 Attributes;
+ UINT32 MemoryDeviceExtendSize;
+ UINT16 CfgMemorySpeed;
+
+ CHAR8 *OptionalStrStart;
+ UINTN DeviceLocatorStrLen;
+ UINTN BankLocatorStrLen;
+ UINTN ManufactureStrLen;
+ UINTN SerialNumberStrLen;
+ UINTN AssertTagStrLen;
+ UINTN PartNumberStrLen;
+ EFI_STRING DeviceLocatorStr;
+ EFI_STRING BankLocatorStr;
+ EFI_STRING ManufactureStr;
+ EFI_STRING SerialNumberStr;
+ EFI_STRING AssertTagStr;
+ EFI_STRING PartNumberStr;
+ EFI_STRING_ID DeviceLocator;
+
+ Type17Record = NULL;
+ DeviceLocatorStr = NULL;
+ BankLocatorStr = NULL;
+ ManufactureStr = NULL;
+ SerialNumberStr = NULL;
+ AssertTagStr = NULL;
+ PartNumberStr = NULL;
+
+ MemoryTotalWidth = 0;
+ MemoryDataWidth = 0;
+ MemoryDeviceSize = 0;
+ MemoryDeviceExtendSize = 0;
+ MemorySpeed = 0;
+ Attributes = 0;
+ CfgMemorySpeed = 0;
+
+ //
+ // Allocate Buffers
+ //
+ StringBufferSize = (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH;
+ StringBuffer = AllocateZeroPool (StringBufferSize);
+ if(NULL == StringBuffer)
+ {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+
+ //
+ // Manufacture
+ //
+ ManufactureStr = AllocateZeroPool (StringBufferSize);
+ if(NULL == ManufactureStr)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FREE_STR_BUF;
+ }
+ UnicodeSPrint(ManufactureStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM");
+
+ //
+ // SerialNumber
+ //
+ SerialNumberStr = AllocateZeroPool (StringBufferSize);
+ if(NULL == SerialNumberStr)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FREE_STR_MAN;
+ }
+ UnicodeSPrint(SerialNumberStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM");
+
+ //
+ // AssetTag
+ //
+ AssertTagStr = AllocateZeroPool (StringBufferSize);
+ if(NULL == AssertTagStr)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FREE_STR_SN;
+ }
+ UnicodeSPrint(AssertTagStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM");
+
+ //
+ // PartNumber
+ //
+ PartNumberStr = AllocateZeroPool (StringBufferSize);
+ if(NULL == PartNumberStr)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FREE_STR_AST;
+ }
+ UnicodeSPrint(PartNumberStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM");
+
+
+ if(IsDimmPresent(pGblData, Skt, Ch, Dimm))
+ {
+ MemoryDataWidth = pGblData->Channel[Skt][Ch].Dimm[Dimm].PrimaryBusWidth;
+ MemoryTotalWidth = MemoryDataWidth + pGblData->Channel[Skt][Ch].Dimm[Dimm].ExtensionBusWidth;
+
+ MemoryDeviceSize = pGblData->Channel[Skt][Ch].Dimm[Dimm].DimmSize; //in MB
+ MemoryDeviceExtendSize = 0;
+
+ if (MemoryDeviceSize >= 0x7fff)
+ {
+ MemoryDeviceExtendSize = MemoryDeviceSize; // in MB
+ MemoryDeviceSize = 0x7fff; // max value
+ }
+
+ MemInfoMemFreq = pGblData->Freq;
+ MemorySpeed = pGblData->Channel[Skt][Ch].Dimm[Dimm].DimmSpeed;
+ Attributes = pGblData->Channel[Skt][Ch].Dimm[Dimm].RankNum;
+ CfgMemorySpeed = MemInfoMemFreq;
+
+ //
+ // Manufacturer
+ //
+ SmbiosGetManufacturer (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdMMfgId & 0xFF,
+ pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdMMfgId >> 8,
+ ManufactureStr
+ );
+
+ //
+ // SerialNumber
+ //
+ SmbiosGetSerialNumber(pGblData, Skt, Ch, Dimm, SerialNumberStr);
+
+ //
+ // AssetTag
+ //
+ UnicodeSPrint(AssertTagStr, SMBIOS_STRING_MAX_LENGTH - 1, L"Unknown");
+
+ //
+ // PartNumber
+ //
+ SmbiosGetPartNumber(pGblData, Skt, Ch, Dimm, PartNumberStr);
+ }
+
+ //
+ // DeviceLocator
+ //
+ DeviceLocatorStr = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+ if(NULL == DeviceLocatorStr)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FREE_STR_PN;
+ }
+ DeviceLocator = gDimmToDevLocator[Skt][Ch][Dimm];
+ if (DeviceLocator != 0xFFFF)
+ {
+ UnicodeSPrint(DeviceLocatorStr, SMBIOS_STRING_MAX_LENGTH, L"DIMM%x%x%x ", Skt, Ch, Dimm);
+ StringBuffer = HiiGetPackageString (&gEfiCallerIdGuid, DeviceLocator, NULL);
+ (VOID)StrCatS(DeviceLocatorStr, SMBIOS_STRING_MAX_LENGTH, StringBuffer);
+ }
+ else
+ {
+ UnicodeSPrint(DeviceLocatorStr, SMBIOS_STRING_MAX_LENGTH, L"DIMM%x%x%x", Skt, Ch, Dimm);
+ }
+ DeviceLocatorStrLen = StrLen (DeviceLocatorStr);
+
+ //
+ // BankLocator
+ //
+ BankLocatorStr = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+ if(NULL == BankLocatorStr)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FREE_STR_DEV;
+ }
+ UnicodeSPrint(BankLocatorStr, SMBIOS_STRING_MAX_LENGTH, L"SOCKET %x CHANNEL %x DIMM %x", Skt, Ch, Dimm);
+ BankLocatorStrLen = StrLen (BankLocatorStr);
+
+ ManufactureStrLen = StrLen (ManufactureStr);
+ SerialNumberStrLen = StrLen (SerialNumberStr);
+ AssertTagStrLen = StrLen (AssertTagStr);
+ PartNumberStrLen = StrLen (PartNumberStr);
+
+ //
+ // Report Type 17 SMBIOS Record
+ //
+ TableSize = sizeof(SMBIOS_TABLE_TYPE17) + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1 + SerialNumberStrLen + 1 + AssertTagStrLen + 1 + PartNumberStrLen + 1 + 1;
+ Type17Record = AllocateZeroPool (TableSize);
+ if(NULL == Type17Record)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FREE_BL;
+ }
+
+ Type17Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_DEVICE;
+ Type17Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE17);
+ Type17Record->Hdr.Handle = 0;
+ Type17Record->MemoryArrayHandle = MemArraySmbiosHandle;
+ Type17Record->MemoryErrorInformationHandle = 0xFFFE;
+ Type17Record->TotalWidth = MemoryTotalWidth;
+ Type17Record->DataWidth = MemoryDataWidth;
+ Type17Record->Size = MemoryDeviceSize; // in MB
+ Type17Record->FormFactor = MemoryFormFactorDimm;
+ Type17Record->DeviceLocator = 1;
+ Type17Record->BankLocator = 2;
+ Type17Record->MemoryType = SmbiosGetMemoryType (pGblData, Skt, Ch, Dimm);
+
+ Type17Record->TypeDetail.Synchronous = 1;
+
+ SmbiosGetTypeDetail (pGblData, Skt, Ch, Dimm, &(Type17Record->TypeDetail));
+
+ Type17Record->Speed = MemorySpeed; // in MHZ
+ Type17Record->Manufacturer = 3;
+ Type17Record->SerialNumber = 4;
+ Type17Record->AssetTag = 5;
+ Type17Record->PartNumber = 6;
+ Type17Record->Attributes = Attributes;
+ Type17Record->ExtendedSize = MemoryDeviceExtendSize;
+ Type17Record->ConfiguredMemoryClockSpeed = CfgMemorySpeed;
+ //
+ // Add for smbios 2.8.0
+ //
+ SmbiosGetDimmVoltageInfo (pGblData, Skt, Ch, Dimm, Type17Record);
+
+ OptionalStrStart = (CHAR8 *) (Type17Record + 1);
+ UnicodeStrToAsciiStr (DeviceLocatorStr, OptionalStrStart);
+ UnicodeStrToAsciiStr (BankLocatorStr, OptionalStrStart + DeviceLocatorStrLen + 1);
+ UnicodeStrToAsciiStr (ManufactureStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1);
+ UnicodeStrToAsciiStr (SerialNumberStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1);
+ UnicodeStrToAsciiStr (AssertTagStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1 + SerialNumberStrLen + 1);
+ UnicodeStrToAsciiStr (PartNumberStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1 + SerialNumberStrLen + 1 + AssertTagStrLen + 1);
+
+ MemDevSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbios->Add (mSmbios, NULL, &MemDevSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type17Record);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type17 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool (Type17Record);
+
+FREE_BL:
+ FreePool (BankLocatorStr);
+
+FREE_STR_DEV:
+ FreePool (DeviceLocatorStr);
+
+FREE_STR_PN:
+ FreePool (PartNumberStr);
+
+FREE_STR_AST:
+ FreePool (AssertTagStr);
+
+FREE_STR_SN:
+ FreePool (SerialNumberStr);
+
+FREE_STR_MAN:
+ FreePool (ManufactureStr);
+
+FREE_STR_BUF:
+ FreePool (StringBuffer);
+
+ return Status;
+}
+
+
+/**
+ Standard EFI driver point. This driver locates the MemoryConfigurationData Variable,
+ if it exists, add the related SMBIOS tables by PI SMBIOS protocol.
+
+ @param ImageHandle Handle for the image of this driver
+ @param SystemTable Pointer to the EFI System Table
+
+ @retval EFI_SUCCESS The data was successfully stored.
+
+**/
+EFI_STATUS
+EFIAPI
+MemorySubClassEntryPoint(
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_PROTOCOL *Smbios;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ pGBL_DATA pGblData;
+ EFI_SMBIOS_HANDLE MemArraySmbiosHandle;
+ UINT8 Skt, Ch, Dimm;
+
+ GuidHob = GetFirstGuidHob(&gHisiEfiMemoryMapGuid);
+ if(NULL == GuidHob)
+ {
+ DEBUG((EFI_D_ERROR, "Could not get MemoryMap Guid hob. %r\n"));
+ return EFI_NOT_FOUND;
+ }
+ pGblData = (pGBL_DATA) GET_GUID_HOB_DATA(GuidHob);
+
+ //
+ // Locate dependent protocols
+ //
+ Status = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol. %r\n", Status));
+ return Status;
+ }
+ mSmbios = Smbios;
+
+ //
+ // Add our default strings to the HII database. They will be modified later.
+ //
+ mHiiHandle = OemGetPackages();
+ if(NULL == mHiiHandle)
+ {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mMaxSkt = OemGetSocketNumber();
+ mMaxCh = OemGetDdrChannel();
+ // Get DIMM slot number on Socket 0 Channel 0
+ // TODO: Assume all channels have same slot number
+
+ Status = SmbiosAddType16Table (pGblData, &MemArraySmbiosHandle);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "Smbios Add Type16 Table Failed. %r\n", Status));
+ return Status;
+ }
+
+ Status = SmbiosAddType19Table (pGblData, MemArraySmbiosHandle);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "Smbios Add Type19 Table Failed. %r\n", Status));
+ return Status;
+ }
+
+ for(Skt = 0; Skt < mMaxSkt; Skt++)
+ {
+ for(Ch = 0; Ch < mMaxCh; Ch++)
+ {
+ for(Dimm = 0; Dimm < OemGetDimmSlot(Skt, Ch); Dimm++)
+ {
+ Status = SmbiosAddType17Table (pGblData, Skt, Ch, Dimm, MemArraySmbiosHandle);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "Smbios Add Type17 Table Failed. %r\n", Status));
+ }
+ }
+ }
+ }
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
new file mode 100644
index 0000000..c35ce39
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
@@ -0,0 +1,79 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _MEMORY_SUBCLASS_DRIVER_H
+#define _MEMORY_SUBCLASS_DRIVER_H
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/HiiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/HobLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PcdLib.h>
+
+#include <Library/HwMemInitLib.h>
+#include <Guid/DebugMask.h>
+#include <Guid/MemoryMapData.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemMiscLib.h>
+
+//
+// This is the generated header file which includes whatever needs to be exported (strings + IFR)
+//
+
+extern UINT8 MemorySubClassStrings[];
+
+#define MAX_DIMM_SIZE 32 // In GB
+
+struct SPD_JEDEC_MANUFACTURER
+{
+ UINT8 MfgIdLSB;
+ UINT8 MfgIdMSB;
+ CHAR16 *Name;
+};
+
+struct SPD_JEDEC_MANUFACTURER JEP106[] = {
+ { 0, 0x10, L"NEC"},
+ { 0, 0x2c, L"Micron"},
+ { 0, 0x3d, L"Tektronix"},
+ { 0, 0x97, L"TI"},
+ { 0, 0xad, L"Hynix"},
+ { 0, 0xb3, L"IDT"},
+ { 0, 0xc1, L"Infineon"},
+ { 0, 0xce, L"Samsung"},
+ { 1, 0x94, L"Smart"},
+ { 1, 0x98, L"Kingston"},
+ { 2, 0xc8, L"Agilent"},
+ { 2, 0xfe, L"Elpida"},
+ { 3, 0x0b, L"Nanya"},
+ { 4, 0x43, L"Ramaxel"},
+ { 4, 0xb3, L"Inphi"},
+ { 5, 0x51, L"Qimonda"},
+ { 5, 0x57, L"AENEON"},
+ { 0xFF, 0xFF, L""}
+};
+
+
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
new file mode 100644
index 0000000..a2ea3a0
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
@@ -0,0 +1,59 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MemorySubClass
+ FILE_GUID = 62194F1A-5A0D-4B33-9EF0-7D05C6CB923A
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = MemorySubClassEntryPoint
+
+[Sources]
+ MemorySubClassStrings.uni
+ MemorySubClass.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ HobLib
+ HiiLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ PrintLib
+ PlatformSysCtrlLib
+ PcdLib
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+
+[Pcd]
+
+[Guids]
+ gHisiEfiMemoryMapGuid
+
+[Depex]
+ gEfiSmbiosProtocolGuid
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassStrings.uni b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassStrings.uni
new file mode 100644
index 0000000..edf8464
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassStrings.uni
@@ -0,0 +1,30 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+// Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// --*/
+
+/=#
+
+#langdef en-US "English"
+
+//
+// Begin English Language Strings
+//
+
+#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown"
+
+//
+// End English Language Strings
+//
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
new file mode 100644
index 0000000..07dae5f
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -0,0 +1,726 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "ProcessorSubClass.h"
+
+#include <FrameworkDxe.h>
+
+EFI_HII_HANDLE mHiiHandle;
+
+EFI_SMBIOS_PROTOCOL *mSmbios;
+
+SMBIOS_TABLE_TYPE7 mSmbiosCacheTable[] = {
+ //L1 Instruction Cache
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE7), //Length
+ 0 //Handle
+ },
+ 1, //SocketDesignation
+ 0, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 48, //InstalledSize
+ { //SupportedSRAMType
+ 0
+ },
+ { //CurrentSRAMType
+ 0
+ },
+ 0, //CacheSpeed
+ CacheErrorParity, //ErrorCorrectionType
+ CacheTypeInstruction, //SystemCacheType
+ CacheAssociativity8Way //Associativity
+ },
+
+ //L1 Data Cache
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE7), //Length
+ 0 //Handle
+ },
+ 1, //SocketDesignation
+ 0, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 32, //InstalledSize
+ { //SupportedSRAMType
+ 0
+ },
+ { //CurrentSRAMType
+ 0
+ },
+ 0, //CacheSpeed
+ CacheErrorSingleBit, //ErrorCorrectionType
+ CacheTypeData, //SystemCacheType
+ CacheAssociativity8Way //Associativity
+ },
+
+ //L2 Cache
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE7), //Length
+ 0 //Handle
+ },
+ 1, //SocketDesignation
+ 0, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 4096, //InstalledSize
+ { //SupportedSRAMType
+ 0
+ },
+ { //CurrentSRAMType
+ 0
+ },
+ 0, //CacheSpeed
+ CacheErrorSingleBit, //ErrorCorrectionType
+ CacheTypeUnified, //SystemCacheType
+ CacheAssociativity8Way //Associativity
+ },
+
+ //L3 Cache
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE7), //Length
+ 0 //Handle
+ },
+ 1, //SocketDesignation
+ 0, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 16384, //InstalledSize
+ { //SupportedSRAMType
+ 0
+ },
+ { //CurrentSRAMType
+ 0
+ },
+ 0, //CacheSpeed
+ CacheErrorSingleBit, //ErrorCorrectionType
+ CacheTypeUnified, //SystemCacheType
+ CacheAssociativity16Way //Associativity
+ }
+};
+
+SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] = {
+ //CPU0
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE4), //Length
+ 0 //Handle
+ },
+ 1, //Socket
+ CentralProcessor, //ProcessorType
+ ProcessorFamilyOther, //ProcessorFamily
+ 2, //ProcessorManufacture
+ { //ProcessorId
+ { //Signature
+ 0
+ },
+ { //FeatureFlags
+ 0
+ }
+ },
+ 3, //ProcessorVersion
+ { //Voltage
+ 0
+ },
+ EXTERNAL_CLOCK, //ExternalClock
+ CPU_MAX_SPEED, //MaxSpeed
+ 0, //CurrentSpeed
+ 0, //Status
+ ProcessorUpgradeUnknown, //ProcessorUpgrade
+ 0xFFFF, //L1CacheHandle
+ 0xFFFF, //L2CacheHandle
+ 0xFFFF, //L3CacheHandle
+ 4, //SerialNumber
+ 5, //AssetTag
+ 6, //PartNumber
+
+ 0, //CoreCount
+ 0, //EnabledCoreCount
+ 0, //ThreadCount
+ 0, //ProcessorCharacteristics
+
+ ProcessorFamilyARM, //ProcessorFamily2
+
+ 0, //CoreCount2
+ 0, //EnabledCoreCount2
+ 0 //ThreadCount2
+ },
+
+ //CPU1
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE4), //Length
+ 0 //Handle
+ },
+ 1, //Socket
+ CentralProcessor, //ProcessorType
+ ProcessorFamilyOther, //ProcessorFamily
+ 2, //ProcessorManufacture
+ { //ProcessorId
+ { //Signature
+ 0
+ },
+ { //FeatureFlags
+ 0
+ }
+ },
+ 3, //ProcessorVersion
+ { //Voltage
+ 0
+ },
+ EXTERNAL_CLOCK, //ExternalClock
+ CPU_MAX_SPEED, //MaxSpeed
+ 0, //CurrentSpeed
+ 0, //Status
+ ProcessorUpgradeUnknown, //ProcessorUpgrade
+ 0xFFFF, //L1CacheHandle
+ 0xFFFF, //L2CacheHandle
+ 0xFFFF, //L3CacheHandle
+ 4, //SerialNumber
+ 5, //AssetTag
+ 6, //PartNumber
+
+ 0, //CoreCount
+ 0, //EnabledCoreCount
+ 0, //ThreadCount
+ 0, //ProcessorCharacteristics
+
+ ProcessorFamilyARM, //ProcessorFamily2
+
+ 0, //CoreCount2
+ 0, //EnabledCoreCount2
+ 0 //ThreadCount2
+ }
+};
+
+
+UINT16
+GetCpuFrequency (
+ IN UINT8 ProcessorNumber
+)
+{
+ return (UINT16)(PlatformGetCpuFreq(ProcessorNumber)/1000/1000);
+}
+
+UINTN
+GetCacheSocketStr (
+ IN UINT8 CacheLevel,
+ OUT CHAR16 *CacheSocketStr
+ )
+{
+ UINTN CacheSocketStrLen = 0;
+
+ if(CacheLevel == CPU_CACHE_L1_Instruction)
+ {
+ CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, SMBIOS_STRING_MAX_LENGTH - 1, L"L%x Instruction Cache", CacheLevel + 1);
+ }
+ else if(CacheLevel == CPU_CACHE_L1_Data)
+ {
+ CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, SMBIOS_STRING_MAX_LENGTH - 1, L"L%x Data Cache", CacheLevel);
+ }
+ else
+ {
+ CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, SMBIOS_STRING_MAX_LENGTH - 1, L"L%x Cache", CacheLevel);
+ }
+
+ return CacheSocketStrLen;
+}
+
+VOID
+UpdateSmbiosCacheTable (
+ IN UINT8 CacheLevel
+ )
+{
+ UINT16 CoreCount;
+ UINT32 TotalSize;
+ UINT32 CacheSize;
+ UINT16 MaximumCacheSize;
+ UINT16 InstalledSize;
+ CACHE_CONFIGURATION CacheConfig;
+ CACHE_SRAM_TYPE_DATA CacheSramType = {0};
+
+ CoreCount = 16; // Default value is 16 Core
+ CacheSize = 0;
+
+ //
+ // Set Cache Configuration
+ //
+ CacheConfig.Bits.Socketed = 0; // Not Socketed
+ CacheConfig.Bits.Reserved1 = 0; //
+ CacheConfig.Bits.Location = 0; // Internal
+ CacheConfig.Bits.Enable = 1; // Enabled
+ CacheConfig.Bits.Reserved2 = 0;
+ if(CacheLevel == CPU_CACHE_L1_Instruction || CacheLevel == CPU_CACHE_L1_Data)
+ {
+ CacheConfig.Bits.Level = 0;
+ CacheConfig.Bits.OperationalMode = 1; // Write Back
+ }
+ else
+ {
+ CacheConfig.Bits.Level = CacheLevel - 1;
+ CacheConfig.Bits.OperationalMode = 2; // Varies with Memory Address
+ }
+
+ mSmbiosCacheTable[CacheLevel].CacheConfiguration = CacheConfig.Data;
+
+ //
+ // Set Cache Size
+ //
+ CacheSize = mSmbiosCacheTable[CacheLevel].InstalledSize;
+ if (PACKAGE_16CORE != PlatformGetPackageType()) // 32 Core
+ {
+ CoreCount = CoreCount * 2;
+
+ if (CacheLevel > 1)
+ {
+ CacheSize = CacheSize * 2;
+ }
+ }
+
+ if(CacheLevel <= 1)
+ {
+ TotalSize = CacheSize * CoreCount;
+ }
+ else
+ {
+ TotalSize = CacheSize;
+ }
+
+ if((TotalSize >> 15) == 0) // 1K granularity
+ {
+ MaximumCacheSize = (UINT16)TotalSize;
+ InstalledSize = (UINT16)TotalSize;
+ }
+ else // 64K granularity
+ {
+ MaximumCacheSize = (UINT16)(TotalSize >> 6);
+ InstalledSize = (UINT16)(TotalSize >> 6);
+
+ // Set BIT15 to 1
+ MaximumCacheSize |= BIT15;
+ InstalledSize |= BIT15;
+ }
+
+ mSmbiosCacheTable[CacheLevel].MaximumCacheSize = MaximumCacheSize;
+ mSmbiosCacheTable[CacheLevel].InstalledSize = InstalledSize;
+
+ //
+ // Set SRAM Type
+ //
+ CacheSramType.Synchronous = 1;
+ (VOID)CopyMem(&mSmbiosCacheTable[CacheLevel].SupportedSRAMType, &CacheSramType, sizeof(CACHE_SRAM_TYPE_DATA));
+ (VOID)CopyMem(&mSmbiosCacheTable[CacheLevel].CurrentSRAMType, &CacheSramType, sizeof(CACHE_SRAM_TYPE_DATA));
+}
+
+/**
+ Add Type 7 SMBIOS Record for Cache Information.
+
+ @param[in] ProcessorNumber Processor number of specified processor.
+ @param[out] L1CacheHandle Pointer to the handle of the L1 Cache SMBIOS record.
+ @param[out] L2CacheHandle Pointer to the handle of the L2 Cache SMBIOS record.
+ @param[out] L3CacheHandle Pointer to the handle of the L3 Cache SMBIOS record.
+
+**/
+EFI_STATUS
+AddSmbiosCacheTypeTable (
+ IN UINTN ProcessorNumber,
+ OUT EFI_SMBIOS_HANDLE *L1CacheHandle,
+ OUT EFI_SMBIOS_HANDLE *L2CacheHandle,
+ OUT EFI_SMBIOS_HANDLE *L3CacheHandle
+ )
+{
+ EFI_STATUS Status;
+ SMBIOS_TABLE_TYPE7 *Type7Record;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ UINTN TableSize;
+ UINT8 CacheLevel;
+ CHAR8 *OptionalStrStart;
+ EFI_STRING CacheSocketStr;
+ UINTN CacheSocketStrLen;
+ UINTN StringBufferSize;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // Get Cache information
+ //
+ for(CacheLevel = 0; CacheLevel < MAX_CACHE_LEVEL; CacheLevel++)
+ {
+ Type7Record = NULL;
+
+ if(mSmbiosCacheTable[CacheLevel].InstalledSize == 0)
+ {
+ continue;
+ }
+
+ //
+ // Update Cache information
+ //
+ if (mSmbiosCacheTable[CacheLevel].MaximumCacheSize == 0)
+ {
+ UpdateSmbiosCacheTable (CacheLevel);
+ }
+
+ StringBufferSize = sizeof(CHAR16) * SMBIOS_STRING_MAX_LENGTH;
+ CacheSocketStr = AllocateZeroPool(StringBufferSize);
+ if (CacheSocketStr == NULL)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Exit;
+ }
+
+ CacheSocketStrLen = GetCacheSocketStr (CacheLevel, CacheSocketStr);
+
+ TableSize = sizeof(SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1;
+ Type7Record = AllocateZeroPool (TableSize);
+ if (Type7Record == NULL)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Exit;
+ }
+
+ (VOID)CopyMem(Type7Record, &mSmbiosCacheTable[CacheLevel], sizeof (SMBIOS_TABLE_TYPE7));
+
+ OptionalStrStart = (CHAR8 *) (Type7Record + 1);
+ UnicodeStrToAsciiStr (CacheSocketStr, OptionalStrStart);
+
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type7Record);
+ if (EFI_ERROR (Status))
+ {
+ goto Exit;
+ }
+
+ // Config L1/L2/L3 Cache Handle
+ switch(CacheLevel)
+ {
+ case CPU_CACHE_L1_Instruction:
+ case CPU_CACHE_L1_Data:
+ *L1CacheHandle = SmbiosHandle;
+ break;
+ case CPU_CACHE_L2:
+ *L2CacheHandle = SmbiosHandle;
+ break;
+ case CPU_CACHE_L3:
+ *L3CacheHandle = SmbiosHandle;
+ break;
+ default :
+ break;
+ }
+Exit:
+ if(Type7Record != NULL)
+ {
+ FreePool (Type7Record);
+ }
+ if(CacheSocketStr != NULL)
+ {
+ FreePool (CacheSocketStr);
+ CacheSocketStr = NULL;
+ }
+ }
+
+ return Status;
+}
+
+/**
+ Add Type 4 SMBIOS Record for Processor Information.
+
+ @param[in] ProcessorNumber Processor number of specified processor.
+
+**/
+EFI_STATUS
+AddSmbiosProcessorTypeTable (
+ IN UINTN ProcessorNumber
+ )
+{
+ EFI_STATUS Status;
+ SMBIOS_TABLE_TYPE4 *Type4Record;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ EFI_SMBIOS_HANDLE L1CacheHandle;
+ EFI_SMBIOS_HANDLE L2CacheHandle;
+ EFI_SMBIOS_HANDLE L3CacheHandle;
+
+ CHAR8 *OptionalStrStart;
+ EFI_STRING_ID ProcessorManu;
+ EFI_STRING_ID ProcessorVersion;
+ EFI_STRING_ID SerialNumber;
+ EFI_STRING_ID AssetTag;
+ EFI_STRING_ID PartNumber;
+ EFI_STRING ProcessorSocketStr;
+ EFI_STRING ProcessorManuStr;
+ EFI_STRING ProcessorVersionStr;
+ EFI_STRING SerialNumberStr;
+ EFI_STRING AssetTagStr;
+ EFI_STRING PartNumberStr;
+ UINTN ProcessorSocketStrLen;
+ UINTN ProcessorManuStrLen;
+ UINTN ProcessorVersionStrLen;
+ UINTN SerialNumberStrLen;
+ UINTN AssetTagStrLen;
+ UINTN PartNumberStrLen;
+ UINTN StringBufferSize;
+ UINTN TotalSize;
+
+ UINT8 Voltage;
+ UINT16 CoreCount;
+ UINT16 CoreEnabled;
+ UINT16 ThreadCount;
+ UINT16 CurrentSpeed;
+ PROCESSOR_STATUS_DATA ProcessorStatus = {{0}};
+ PROCESSOR_CHARACTERISTICS_DATA ProcessorCharacteristics = {{0}};
+
+ CHAR16 *CpuVersion;
+ STRING_REF TokenToUpdate;
+
+ Type4Record = NULL;
+ ProcessorManuStr = NULL;
+ ProcessorVersionStr = NULL;
+ SerialNumberStr = NULL;
+ AssetTagStr = NULL;
+ PartNumberStr = NULL;
+
+ if(OemIsSocketPresent(ProcessorNumber)) //CPU is present
+ {
+ Voltage = BIT7 | 9; // 0.9V
+
+ Status = AddSmbiosCacheTypeTable (ProcessorNumber, &L1CacheHandle, &L2CacheHandle, &L3CacheHandle);
+ if(EFI_ERROR(Status))
+ {
+ return Status;
+ }
+
+ CurrentSpeed = GetCpuFrequency(ProcessorNumber);
+
+ CoreCount = PlatformGetCoreCount();
+ CoreEnabled = CoreCount;
+ ThreadCount = CoreCount;
+
+ CpuVersion = (CHAR16 *) PcdGetPtr (PcdCPUInfo);
+ if (StrLen(CpuVersion) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_PROCESSOR_VERSION);
+ HiiSetString (mHiiHandle, TokenToUpdate, CpuVersion, NULL);
+ }
+
+ ProcessorManu = STRING_TOKEN (STR_PROCESSOR_MANUFACTURE);
+ ProcessorVersion = STRING_TOKEN (STR_PROCESSOR_VERSION);
+ SerialNumber = STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER);
+ AssetTag = STRING_TOKEN (STR_PROCESSOR_ASSET_TAG);
+ PartNumber = STRING_TOKEN (STR_PROCESSOR_PART_NUMBER);
+
+ // Processor Status
+ ProcessorStatus.Bits.CpuStatus = 1; // CPU Enabled
+ ProcessorStatus.Bits.Reserved1 = 0;
+ ProcessorStatus.Bits.SocketPopulated = 1; // CPU Socket Populated
+ ProcessorStatus.Bits.Reserved2 = 0;
+
+ // Processor Characteristics
+ ProcessorCharacteristics.Bits.Reserved = 0;
+ ProcessorCharacteristics.Bits.Capable64Bit = 1; // 64-bit Capable
+ ProcessorCharacteristics.Bits.Unknown = 0;
+ ProcessorCharacteristics.Bits.EnhancedVirtualization = 1;
+ ProcessorCharacteristics.Bits.HardwareThread = 0;
+ ProcessorCharacteristics.Bits.MultiCore = 1;
+ ProcessorCharacteristics.Bits.ExecuteProtection = 1;
+ ProcessorCharacteristics.Bits.PowerPerformanceControl = 1;
+ ProcessorCharacteristics.Bits.Reserved2 = 0;
+ }
+ else
+ {
+ Voltage = 0;
+ CurrentSpeed = 0;
+ CoreCount = 0;
+ CoreEnabled = 0;
+ ThreadCount = 0;
+ L1CacheHandle = 0xFFFF;
+ L2CacheHandle = 0xFFFF;
+ L3CacheHandle = 0xFFFF;
+
+ ProcessorManu = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+ ProcessorVersion = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+ SerialNumber = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+ AssetTag = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+ PartNumber = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+ }
+
+ // Processor Socket Designation
+ StringBufferSize = sizeof(CHAR16) * SMBIOS_STRING_MAX_LENGTH;
+ ProcessorSocketStr = AllocateZeroPool(StringBufferSize);
+ if (ProcessorSocketStr == NULL)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Exit;
+ }
+
+ ProcessorSocketStrLen = UnicodeSPrint (ProcessorSocketStr, StringBufferSize, L"CPU%02d", ProcessorNumber + 1);
+
+ // Processor Manufacture
+ ProcessorManuStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorManu, NULL);
+ ProcessorManuStrLen = StrLen (ProcessorManuStr);
+
+ // Processor Version
+ ProcessorVersionStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorVersion, NULL);
+ ProcessorVersionStrLen = StrLen (ProcessorVersionStr);
+
+ // Serial Number
+ SerialNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber, NULL);
+ SerialNumberStrLen = StrLen (SerialNumberStr);
+
+ // Asset Tag
+ AssetTagStr = HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL);
+ AssetTagStrLen = StrLen (AssetTagStr);
+
+ // Part Number
+ PartNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NULL);
+ PartNumberStrLen = StrLen (PartNumberStr);
+
+ TotalSize = sizeof (SMBIOS_TABLE_TYPE4) + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1 + SerialNumberStrLen + 1 + AssetTagStrLen + 1 + PartNumberStrLen + 1 + 1;
+ Type4Record = AllocateZeroPool (TotalSize);
+ if (Type4Record == NULL)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Exit;
+ }
+
+ (VOID)CopyMem(Type4Record, &mSmbiosProcessorTable[ProcessorNumber], sizeof (SMBIOS_TABLE_TYPE4));
+
+ *(UINT8 *) &Type4Record->Voltage = Voltage;
+ Type4Record->CurrentSpeed = CurrentSpeed;
+ Type4Record->Status = ProcessorStatus.Data;
+ Type4Record->L1CacheHandle = L1CacheHandle;
+ Type4Record->L2CacheHandle = L2CacheHandle;
+ Type4Record->L3CacheHandle = L3CacheHandle;
+ Type4Record->CoreCount = CoreCount;
+ Type4Record->EnabledCoreCount = CoreEnabled;
+ Type4Record->ThreadCount = ThreadCount;
+ Type4Record->ProcessorCharacteristics = ProcessorCharacteristics.Data;
+
+ Type4Record->ExternalClock = (UINT16)(ArmReadCntFrq() / 1000 / 1000);
+
+ OptionalStrStart = (CHAR8 *) (Type4Record + 1);
+ UnicodeStrToAsciiStr (ProcessorSocketStr, OptionalStrStart);
+ UnicodeStrToAsciiStr (ProcessorManuStr, OptionalStrStart + ProcessorSocketStrLen + 1);
+ UnicodeStrToAsciiStr (ProcessorVersionStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1);
+ UnicodeStrToAsciiStr (SerialNumberStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1);
+ UnicodeStrToAsciiStr (AssetTagStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1 + SerialNumberStrLen + 1);
+ UnicodeStrToAsciiStr (PartNumberStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1 + SerialNumberStrLen + 1 + AssetTagStrLen + 1);
+
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type4Record);
+ if (EFI_ERROR (Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+ FreePool (Type4Record);
+
+Exit:
+ if(ProcessorSocketStr != NULL)
+ {
+ FreePool (ProcessorSocketStr);
+ }
+ if(ProcessorManuStr != NULL)
+ {
+ FreePool (ProcessorManuStr);
+ }
+ if(ProcessorVersionStr != NULL)
+ {
+ FreePool (ProcessorVersionStr);
+ }
+ if(SerialNumberStr != NULL)
+ {
+ FreePool (SerialNumberStr);
+ }
+ if(AssetTagStr != NULL)
+ {
+ FreePool (AssetTagStr);
+ }
+ if(PartNumberStr != NULL)
+ {
+ FreePool (PartNumberStr);
+ }
+
+ return Status;
+}
+
+/**
+ Standard EFI driver point. This driver locates the ProcessorConfigurationData Variable,
+ if it exists, add the related SMBIOS tables by PI SMBIOS protocol.
+
+ @param ImageHandle Handle for the image of this driver
+ @param SystemTable Pointer to the EFI System Table
+
+ @retval EFI_SUCCESS The data was successfully stored.
+
+**/
+EFI_STATUS
+EFIAPI
+ProcessorSubClassEntryPoint(
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 SocketIndex;
+
+ //
+ // Locate dependent protocols
+ //
+ Status = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&mSmbios);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol. %r\n", Status));
+ return Status;
+ }
+
+ //
+ // Add our default strings to the HII database. They will be modified later.
+ //
+ mHiiHandle = HiiAddPackages (
+ &gEfiCallerIdGuid,
+ NULL,
+ ProcessorSubClassStrings,
+ NULL,
+ NULL
+ );
+ if (mHiiHandle == NULL)
+ {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Add SMBIOS tables for populated sockets.
+ //
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++)
+ {
+ if((SocketIndex == 1) && !OemIsMpBoot())
+ {
+ break;
+ }
+ Status = AddSmbiosProcessorTypeTable (SocketIndex);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "Add Processor Type Table Failed! %r.\n", Status));
+ return Status;
+ }
+ }
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h
new file mode 100644
index 0000000..6ddc6cf
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h
@@ -0,0 +1,108 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PROCESSOR_SUBCLASS_DRIVER_H
+#define _PROCESSOR_SUBCLASS_DRIVER_H
+
+#include <Uefi.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/HiiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PcdLib.h>
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/ArmLib.h>
+
+//
+// This is the generated header file which includes whatever needs to be exported (strings + IFR)
+//
+
+extern UINT8 ProcessorSubClassStrings[];
+
+#define CPU_CACHE_L1_Instruction 0
+#define CPU_CACHE_L1_Data 1
+#define CPU_CACHE_L2 2
+#define CPU_CACHE_L3 3
+#define MAX_CACHE_LEVEL 4
+
+#define EXTERNAL_CLOCK 50 //50 MHz
+#define CPU_MAX_SPEED 2100 //2.1G
+
+//
+// Cache Info
+//
+typedef struct {
+ UINT16 InstalledSize; //In KB
+ CACHE_TYPE_DATA SystemCacheType;
+ CACHE_ASSOCIATIVITY_DATA Associativity;
+} CACHE_INFO;
+
+//
+// Cache Configuration
+//
+typedef union {
+ struct {
+ UINT16 Level :3;
+ UINT16 Socketed :1;
+ UINT16 Reserved1 :1;
+ UINT16 Location :2;
+ UINT16 Enable :1;
+ UINT16 OperationalMode :2;
+ UINT16 Reserved2 :6;
+ } Bits;
+ UINT16 Data;
+}CACHE_CONFIGURATION;
+
+//
+// Processor Status
+//
+typedef union {
+ struct {
+ UINT8 CpuStatus :3; // Indicates the status of the processor.
+ UINT8 Reserved1 :3; // Reserved for future use. Should be set to zero.
+ UINT8 SocketPopulated :1; // Indicates if the processor socket is populated or not.
+ UINT8 Reserved2 :1; // Reserved for future use. Should be set to zero.
+ } Bits;
+ UINT8 Data;
+}PROCESSOR_STATUS_DATA;
+
+//
+// Processor Characteristics
+//
+typedef union {
+ struct {
+ UINT16 Reserved :1;
+ UINT16 Unknown :1;
+ UINT16 Capable64Bit :1;
+ UINT16 MultiCore :1;
+ UINT16 HardwareThread :1;
+ UINT16 ExecuteProtection :1;
+ UINT16 EnhancedVirtualization :1;
+ UINT16 PowerPerformanceControl :1;
+ UINT16 Reserved2 :8;
+ } Bits;
+ UINT16 Data;
+} PROCESSOR_CHARACTERISTICS_DATA;
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
new file mode 100644
index 0000000..cc011d8
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ProcessorSubClass
+ FILE_GUID = 9B25B1EA-0FD4-455D-A450-AD640C8A9C1B
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ProcessorSubClassEntryPoint
+
+[Sources]
+ ProcessorSubClassStrings.uni
+ ProcessorSubClass.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ IoLib
+ HiiLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ PrintLib
+ PcdLib
+
+ PlatformSysCtrlLib
+ OemMiscLib
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdCPUInfo
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+
+[Guids]
+
+
+[Depex]
+ gEfiSmbiosProtocolGuid
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni
new file mode 100644
index 0000000..d2928fa
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni
@@ -0,0 +1,32 @@
+///// @file
+//
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+// Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+/////
+
+/=#
+
+#langdef en-US "English"
+
+//
+// Processor Information
+//
+#string STR_PROCESSOR_SOCKET_DESIGNATION #language en-US "Hisilicon PhosphorV660 Processor"
+#string STR_PROCESSOR_MANUFACTURE #language en-US "Hisilicon"
+#string STR_PROCESSOR_VERSION #language en-US "Hi1610ES"
+#string STR_PROCESSOR_SERIAL_NUMBER #language en-US "To be filled by O.E.M."
+#string STR_PROCESSOR_ASSET_TAG #language en-US "To be filled by O.E.M."
+#string STR_PROCESSOR_PART_NUMBER #language en-US "To be filled by O.E.M."
+#string STR_PROCESSOR_UNKNOWN #language en-US "Unknown"
+
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMisc.h b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMisc.h
new file mode 100644
index 0000000..66f9db9
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMisc.h
@@ -0,0 +1,226 @@
+/**@file
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ SmbiosMisc.h
+
+Abstract:
+
+ Header file for the SmbiosMisc Driver.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#ifndef _SMBIOS_MISC_DRIVER_H
+#define _SMBIOS_MISC_DRIVER_H
+
+#include <FrameworkDxe.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/HiiLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Guid/DebugMask.h>
+
+#include <Library/PrintLib.h>
+
+//
+// Data table entry update function.
+//
+typedef EFI_STATUS (EFIAPI EFI_MISC_SMBIOS_DATA_FUNCTION) (
+ IN VOID *RecordData,
+ IN EFI_SMBIOS_PROTOCOL *Smbios
+ );
+
+
+//
+// Data table entry definition.
+//
+typedef struct {
+ //
+ // intermediat input data for SMBIOS record
+ //
+ VOID *RecordData;
+ EFI_MISC_SMBIOS_DATA_FUNCTION *Function;
+} EFI_MISC_SMBIOS_DATA_TABLE;
+
+
+//
+// Data Table extern definitions.
+//
+#define MISC_SMBIOS_TABLE_EXTERNS(NAME1, NAME2, NAME3) \
+extern NAME1 NAME2 ## Data; \
+extern EFI_MISC_SMBIOS_DATA_FUNCTION NAME3 ## Function;
+
+
+//
+// Data Table entries
+//
+
+#define MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \
+{ \
+ & NAME1 ## Data, \
+ NAME2 ## Function \
+}
+
+
+//
+// Global definition macros.
+//
+#define MISC_SMBIOS_TABLE_DATA(NAME1, NAME2) \
+ NAME1 NAME2 ## Data
+
+#define MISC_SMBIOS_TABLE_FUNCTION(NAME2) \
+ EFI_STATUS EFIAPI NAME2 ## Function( \
+ IN VOID *RecordData, \
+ IN EFI_SMBIOS_PROTOCOL *Smbios \
+ )
+
+//
+// Data Table Array Entries
+//
+extern EFI_HII_HANDLE mHiiHandle;
+
+typedef struct _EFI_TYPE11_OEM_STRING{
+ UINT8 Offset;
+ EFI_STRING_ID RefOemDefineString;
+} EFI_TYPE11_OEM_STRING;
+
+typedef struct _EFI_TYPE12_SYSTEM_CONFIGURATION_OPTIONS_STRING{
+ UINT8 Offset;
+ EFI_STRING_ID RefType12SystemConfigurationOptionsString;
+} EFI_TYPE12_SYSTEM_CONFIGURATION_OPTIONS_STRING;
+
+typedef struct _EFI_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING{
+ UINT8 *LanguageSignature;
+ EFI_STRING_ID InstallableLanguageLongString;
+ EFI_STRING_ID InstallableLanguageAbbreviateString;
+} EFI_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING;
+
+typedef struct _EFI_TYPE40_ADDITIONAL_INFORMATION_ENTRY{
+ UINT8 RefType;
+ UINT8 RefOffset;
+ EFI_STRING_ID RefString;
+ UINT8 Value;
+} EFI_TYPE40_ADDITIONAL_INFORMATION_ENTRY;
+
+typedef enum {
+ STRING,
+ DATA,
+} OEM_DEFINE_TYPE;
+
+typedef struct {
+ OEM_DEFINE_TYPE Type;
+ UINTN Token;
+ UINTN DataSize;
+} OEM_DEFINE_INFO_STRING;
+
+typedef struct {
+ OEM_DEFINE_TYPE Type;
+ UINTN DataAddress;
+ UINTN DataSize;
+} OEM_DEFINE_INFO_DATA;
+
+typedef union {
+ OEM_DEFINE_INFO_STRING DefineString;
+ OEM_DEFINE_INFO_DATA DefineData;
+} EFI_OEM_DEFINE_ARRAY;
+
+typedef struct _DMI_STRING_STRUCTURE {
+ UINT8 Type;
+ UINT8 Offset;
+ UINT8 Valid;
+ UINT16 Length;
+ UINT8 String[1]; // Variable length field
+} DMI_STRING_STRUCTURE;
+
+typedef struct {
+ UINT8 Type; // The SMBIOS structure type
+ UINT8 FixedOffset; // The offset of the string reference
+ // within the structure's fixed data.
+} DMI_UPDATABLE_STRING;
+
+EFI_STATUS
+FindString (
+ IN UINT8 Type,
+ IN UINT8 Offset,
+ IN EFI_STRING_ID TokenToUpdate
+);
+
+EFI_STATUS
+FindUuid (
+ EFI_GUID *Uuid
+);
+
+EFI_STATUS
+StringToBiosVeriosn (
+ IN EFI_STRING_ID BiosVersionToken,
+ OUT UINT8 *MajorVersion,
+ OUT UINT8 *MinorVersion
+);
+
+
+/**
+ Logs SMBIOS record.
+
+ @param [in] Buffer Pointer to the data buffer.
+ @param [in] SmbiosHandle Pointer for retrieve handle.
+
+**/
+EFI_STATUS
+LogSmbiosData (
+ IN UINT8 *Buffer,
+ IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle
+ );
+
+/**
+ Get Link Type Handle.
+
+ @param [in] SmbiosType Get this Type from SMBIOS table
+ @param [out] HandleArray Pointer to Hadndler array with has been free by caller
+ @param [out] HandleCount Pointer to Hadndler Counter
+
+**/
+VOID
+GetLinkTypeHandle(
+ IN UINT8 SmbiosType,
+ OUT UINT16 **HandleArray,
+ OUT UINTN *HandleCount
+ );
+
+typedef enum {
+ ProductNameType01,
+ SerialNumType01,
+ UuidType01,
+ SystemManufacturerType01,
+ AssertTagType02,
+ SrNumType02,
+ BoardManufacturerType02,
+ AssetTagType03,
+ SrNumType03,
+ VersionType03,
+ ChassisTypeType03 ,
+ ManufacturerType03,
+} GET_INFO_BMC_OFFSET;
+
+VOID UpdateSmbiosInfo (IN EFI_HII_HANDLE mHiiHandle, IN EFI_STRING_ID TokenToUpdate, IN UINT8 Offset);
+EFI_STATUS GetUuidType1 (IN OUT EFI_GUID *Uuid);
+EFI_STATUS IpmiGetChassisType (IN OUT UINT8 *Type);
+#endif
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c
new file mode 100644
index 0000000..8e00865
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c
@@ -0,0 +1,58 @@
+/**@file
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ SmbiosMiscDataTable.c
+
+Abstract:
+
+ This file provide OEM to config SMBIOS Misc Type.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+ MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE0, MiscBiosVendor, MiscBiosVendor)
+ MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer, MiscSystemManufacturer)
+ MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer, MiscChassisManufacturer)
+ MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer, MiscBaseBoardManufacturer)
+ MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages, MiscNumberOfInstallableLanguages)
+ MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE32, MiscBootInformation, MiscBootInformation)
+ MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE38, MiscIpmiDeviceInformation, MiscIpmiDeviceInformation)
+
+
+EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[] = {
+ // Type0
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBiosVendor, MiscBiosVendor),
+ // Type1
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemManufacturer, MiscSystemManufacturer),
+ // Type3
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscChassisManufacturer, MiscChassisManufacturer),
+ // Type2
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBaseBoardManufacturer, MiscBaseBoardManufacturer),
+ // Type13
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscNumberOfInstallableLanguages, MiscNumberOfInstallableLanguages),
+ // Type32
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBootInformation, MiscBootInformation),
+ // Type38
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscIpmiDeviceInformation, MiscIpmiDeviceInformation),
+};
+
+
+//
+// Number of Data Table entries.
+//
+UINTN mSmbiosMiscDataTableEntries =
+ (sizeof mSmbiosMiscDataTable) / sizeof(EFI_MISC_SMBIOS_DATA_TABLE);
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
new file mode 100644
index 0000000..516d57d
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
@@ -0,0 +1,108 @@
+## @file
+# Component description file for SmbiosMisc instance.
+#
+# Parses the MiscSubclassDataTable and reports any generated data to the DataHub.
+# All .uni file who tagged with "ToolCode="DUMMY"" in following file list is included by
+# MiscSubclassDriver.uni file, the StrGather tool will expand MiscSubclassDriver.uni file
+# and parse all .uni file.
+# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+# Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+##
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SmbiosMiscDxe
+ FILE_GUID = EF0C99B6-B1D3-4025-9405-BF6A560FE0E0
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SmbiosMiscEntryPoint
+
+[Sources]
+ SmbiosMisc.h
+ SmbiosMiscDataTable.c
+ SmbiosMiscEntryPoint.c
+ SmbiosMiscLibString.uni
+ ./Type00/MiscBiosVendorData.c
+ ./Type00/MiscBiosVendorFunction.c
+ ./Type01/MiscSystemManufacturerData.c
+ ./Type01/MiscSystemManufacturerFunction.c
+ ./Type02/MiscBaseBoardManufacturerData.c
+ ./Type02/MiscBaseBoardManufacturerFunction.c
+ ./Type03/MiscChassisManufacturerData.c
+ ./Type03/MiscChassisManufacturerFunction.c
+ ./Type13/MiscNumberOfInstallableLanguagesData.c
+ ./Type13/MiscNumberOfInstallableLanguagesFunction.c
+ ./Type32/MiscBootInformationData.c
+ ./Type32/MiscBootInformationFunction.c
+ ./Type38/MiscIpmiDeviceInformationData.c
+ ./Type38/MiscIpmiDeviceInformationFunction.c
+
+ ./Type09/MiscSystemSlotDesignationData.c
+ ./Type09/MiscSystemSlotDesignationFunction.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ HiiLib
+ MemoryAllocationLib
+ DevicePathLib
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ HobLib
+
+ IpmiCmdLib
+
+ SerdesLib
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdFdSize
+ gHisiTokenSpaceGuid.PcdFirmwareVendor
+ gHisiTokenSpaceGuid.PcdBiosVersionString
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString
+
+ gHisiTokenSpaceGuid.PcdSystemProductName
+ gHisiTokenSpaceGuid.PcdSystemVersion
+ gHisiTokenSpaceGuid.PcdBaseBoardProductName
+ gHisiTokenSpaceGuid.PcdBaseBoardVersion
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+
+ gHisiTokenSpaceGuid.PcdBiosVersionForBmc
+
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang
+
+[Guids]
+ gEfiGenericVariableGuid
+ gVersionInfoHobGuid
+
+[Depex]
+ gEfiSmbiosProtocolGuid
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c
new file mode 100644
index 0000000..051410b
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c
@@ -0,0 +1,194 @@
+/**@file
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ SmbiosMiscEntryPoint.c
+
+Abstract:
+
+ This driver parses the mSmbiosMiscDataTable structure and reports
+ any generated data using SMBIOS protocol.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+#define MAX_HANDLE_COUNT 0x10
+
+EFI_HANDLE mImageHandle;
+EFI_HII_HANDLE mHiiHandle;
+EFI_SMBIOS_PROTOCOL *mSmbios = NULL;
+
+//
+// Data Table Array
+//
+extern EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[];
+//
+// Data Table Array Entries
+//
+extern UINTN mSmbiosMiscDataTableEntries;
+
+extern UINT8 SmbiosMiscDxeStrings[];
+
+
+
+/**
+ Standard EFI driver point. This driver parses the mSmbiosMiscDataTable
+ structure and reports any generated data using SMBIOS protocol.
+
+ @param ImageHandle Handle for the image of this driver
+ @param SystemTable Pointer to the EFI System Table
+
+ @retval EFI_SUCCESS The data was successfully stored.
+
+**/
+EFI_STATUS
+EFIAPI
+SmbiosMiscEntryPoint(
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ UINTN Index;
+ EFI_STATUS EfiStatus;
+ EFI_SMBIOS_PROTOCOL *Smbios;
+
+ mImageHandle = ImageHandle;
+
+ EfiStatus = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios);
+ if (EFI_ERROR(EfiStatus))
+ {
+ DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiStatus));
+ return EfiStatus;
+ }
+
+ mSmbios = Smbios;
+
+ mHiiHandle = HiiAddPackages (
+ &gEfiCallerIdGuid,
+ mImageHandle,
+ SmbiosMiscDxeStrings,
+ NULL
+ );
+ if(mHiiHandle == NULL)
+ {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ for (Index = 0; Index < mSmbiosMiscDataTableEntries; ++Index)
+ {
+ //
+ // If the entry have a function pointer, just log the data.
+ //
+ if (mSmbiosMiscDataTable[Index].Function != NULL)
+ {
+ EfiStatus = (*mSmbiosMiscDataTable[Index].Function)(
+ mSmbiosMiscDataTable[Index].RecordData,
+ Smbios
+ );
+
+ if (EFI_ERROR(EfiStatus))
+ {
+ DEBUG((EFI_D_ERROR, "Misc smbios store error. Index=%d, ReturnStatus=%r\n", Index, EfiStatus));
+ return EfiStatus;
+ }
+ }
+ }
+
+ return EfiStatus;
+}
+
+
+/**
+ Logs SMBIOS record.
+
+ @param Buffer The data for the fixed portion of the SMBIOS record. The format of the record is
+ determined by EFI_SMBIOS_TABLE_HEADER.Type. The size of the formatted area is defined
+ by EFI_SMBIOS_TABLE_HEADER.Length and either followed by a double-null (0x0000) or
+ a set of null terminated strings and a null.
+ @param SmbiosHandle A unique handle will be assigned to the SMBIOS record.
+
+ @retval EFI_SUCCESS Record was added.
+ @retval EFI_OUT_OF_RESOURCES Record was not added due to lack of system resources.
+
+**/
+EFI_STATUS
+LogSmbiosData (
+ IN UINT8 *Buffer,
+ IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle
+ )
+{
+ EFI_STATUS Status;
+
+ *SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+
+ Status = mSmbios->Add (
+ mSmbios,
+ NULL,
+ SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER *)Buffer
+ );
+
+ return Status;
+}
+
+
+VOID
+GetLinkTypeHandle(
+ IN UINT8 SmbiosType,
+ OUT UINT16 **HandleArray,
+ OUT UINTN *HandleCount
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ EFI_SMBIOS_TABLE_HEADER *LinkTypeData = NULL;
+
+ if(mSmbios == NULL)
+ return ;
+
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+
+ *HandleArray = AllocateZeroPool(sizeof(UINT16) * MAX_HANDLE_COUNT);
+ if (*HandleArray == NULL)
+ {
+ DEBUG ((EFI_D_INFO, "HandleArray allocate memory resource failed.\n"));
+ return;
+ }
+
+ *HandleCount = 0;
+
+ while(1)
+ {
+ Status = mSmbios->GetNext(
+ mSmbios,
+ &SmbiosHandle,
+ &SmbiosType,
+ &LinkTypeData,
+ NULL
+ );
+
+ if(!EFI_ERROR(Status))
+ {
+ (*HandleArray)[*HandleCount] = LinkTypeData->Handle;
+ (*HandleCount)++;
+ }
+ else
+ {
+ break;
+ }
+ }
+}
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscLibString.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscLibString.uni
new file mode 100644
index 0000000..2e434e3
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscLibString.uni
@@ -0,0 +1,28 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+
+/=#
+
+#langdef en-US "English"
+
+#include "./Type00/MiscBiosVendor.uni"
+#include "./Type01/MiscSystemManufacturer.uni"
+#include "./Type02/MiscBaseBoardManufacturer.uni"
+#include "./Type03/MiscChassisManufacturer.uni"
+#include "./Type13/MiscNumberOfInstallableLanguages.uni"
+#include "./Type09/MiscSystemSlotDesignation.uni"
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni
new file mode 100644
index 0000000..215952a
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni
@@ -0,0 +1,25 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+//#string STR_MISC_BIOS_VENDOR #language en-US "Bios Vendor"
+#string STR_MISC_BIOS_VERSION #language en-US "Bios Version"
+//#string STR_MISC_BIOS_RELEASE_DATE #language en-US "Bios Release Date"
+
+#string STR_MISC_BIOS_VENDOR #language en-US "Huawei Technologies Co., Ltd."
+#string STR_MISC_BIOS_RELEASE_DATE #language en-US "01/01/1900"
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c
new file mode 100644
index 0000000..b822768
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c
@@ -0,0 +1,105 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscBiosVendorData.c
+
+Abstract:
+
+ This file provide OEM to define Smbios Type0 Data
+
+Based on the files under Nt32Pkg/MiscSubClassPlatformDxe/
+
+**/
+
+
+#include "SmbiosMisc.h"
+
+
+//
+// Static (possibly build generated) Bios Vendor data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) = {
+ { //Hdr
+ EFI_SMBIOS_TYPE_BIOS_INFORMATION, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, //Vendor
+ 2, //BiosVersion
+ 0xE000, //BiosSegment
+ 3, //BiosReleaseDate
+ 0, //BiosSize
+ { //BiosCharacteristics
+ 0, // Reserved :2
+ 0, // Unknown :1
+ 0, // BiosCharacteristicsNotSupported :1
+ 0, // IsaIsSupported :1
+ 0, // McaIsSupported :1
+ 0, // EisaIsSupported :1
+ 1, // PciIsSupported :1
+ 0, // PcmciaIsSupported :1
+ 0, // PlugAndPlayIsSupported :1
+ 0, // ApmIsSupported :1
+ 1, // BiosIsUpgradable :1
+ 1, // BiosShadowingAllowed :1
+ 0, // VlVesaIsSupported :1
+ 0, // EscdSupportIsAvailable :1
+ 1, // BootFromCdIsSupported :1
+ 1, // SelectableBootIsSupported :1
+ 0, // RomBiosIsSocketed :1
+ 0, // BootFromPcmciaIsSupported :1
+ 1, // EDDSpecificationIsSupported :1
+ 1, // JapaneseNecFloppyIsSupported :1
+ 1, // JapaneseToshibaFloppyIsSupported :1
+ 1, // Floppy525_360IsSupported :1
+ 1, // Floppy525_12IsSupported :1
+ 1, // Floppy35_720IsSupported :1
+ 1, // Floppy35_288IsSupported :1
+ 0, // PrintScreenIsSupported :1
+ 1, // Keyboard8042IsSupported :1
+ 0, // SerialIsSupported :1
+ 0, // PrinterIsSupported :1
+ 1, // CgaMonoIsSupported :1
+ 0, // NecPc98 :1
+ 0 // ReservedForVendor :32
+ },
+
+ {
+ 0x03, //BIOSCharacteristicsExtensionBytes[0]
+ // { //BiosReserved
+ // 1, // AcpiIsSupported :1
+ // 1, // UsbLegacyIsSupported :1
+ // 0, // AgpIsSupported :1
+ // 0, // I20BootIsSupported :1
+ // 0, // Ls120BootIsSupported :1
+ // 0, // AtapiZipDriveBootIsSupported :1
+ // 0, // Boot1394IsSupported :1
+ // 0 // SmartBatteryIsSupported :1
+ // },
+ 0x0D //BIOSCharacteristicsExtensionBytes[1]
+ // { //SystemReserved
+ // 1, //BiosBootSpecIsSupported :1
+ // 0, //FunctionKeyNetworkBootIsSupported :1
+ // 1, //TargetContentDistributionEnabled :1
+ // 1, //UefiSpecificationSupported :1
+ // 0, //VirtualMachineSupported :1
+ // 0 //ExtensionByte2Reserved :3
+ // },
+ },
+ 0, //SystemBiosMajorRelease;
+ 0, //SystemBiosMinorRelease;
+ 0xFF, //EmbeddedControllerFirmwareMajorRelease;
+ 0xFF //EmbeddedControllerFirmwareMinorRelease;
+};
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c
new file mode 100644
index 0000000..9a42f04
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c
@@ -0,0 +1,258 @@
+/** @file
+
+ Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ MiscBiosVendorData.c
+
+Abstract:
+
+ This driver parses the mMiscSubclassDataTable structure and reports
+ any generated data to the DataHub.
+
+Based on the files under Nt32Pkg/MiscSubClassPlatformDxe/
+
+--*/
+
+//
+#include "SmbiosMisc.h"
+#include <Library/HobLib.h>
+#include <Guid/VersionInfoHobGuid.h>
+
+
+/**
+ Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with '64k'
+ as the unit.
+
+ @param Value Pointer to Base2_Data
+
+ @retval
+
+**/
+UINT8
+Base2ToByteWith64KUnit (
+ IN UINTN Value
+ )
+{
+ UINT8 Size;
+
+ Size = Value / SIZE_64KB + (Value % SIZE_64KB + SIZE_64KB - 1) / SIZE_64KB;
+
+ return Size;
+}
+
+
+/**
+
+**/
+VOID *
+GetBiosReleaseDate (
+ )
+{
+ CHAR16 *ReleaseDate = NULL;
+ VERSION_INFO *Version;
+ VOID *Hob;
+
+ ReleaseDate = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+ if(NULL == ReleaseDate)
+ {
+ return NULL;
+ }
+
+ Hob = GetFirstGuidHob (&gVersionInfoHobGuid);
+ if (Hob == NULL) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] Version info HOB not found!\n", __FUNCTION__, __LINE__));
+ return NULL;
+ }
+
+ Version = GET_GUID_HOB_DATA (Hob);
+ (VOID)UnicodeSPrintAsciiFormat( ReleaseDate,
+ (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH,
+ "%02d/%02d/%4d",
+ Version->BuildTime.Month,
+ Version->BuildTime.Day,
+ Version->BuildTime.Year
+ );
+
+ return ReleaseDate;
+}
+
+VOID *
+GetBiosVersion (
+ )
+{
+ VERSION_INFO *Version;
+ VOID *Hob;
+
+ Hob = GetFirstGuidHob (&gVersionInfoHobGuid);
+ if (Hob == NULL) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] Version info HOB not found!\n", __FUNCTION__, __LINE__));
+ return NULL;
+ }
+ Version = GET_GUID_HOB_DATA (Hob);
+ return Version->String;
+}
+
+
+/**
+ This function makes boot time changes to the contents of the
+ MiscBiosVendor (Type 0).
+
+ @param RecordData Pointer to copy of RecordData from the Data Table.
+
+ @retval EFI_SUCCESS All parameters were valid.
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscBiosVendor)
+{
+ CHAR8 *OptionalStrStart;
+ UINTN VendorStrLen;
+ UINTN VerStrLen;
+ UINTN DateStrLen;
+ UINTN BiosPhysicalSizeHexValue;
+ CHAR16 *Vendor;
+ CHAR16 *Version;
+ CHAR16 *ReleaseDate;
+ CHAR16 *Char16String;
+ EFI_STATUS Status;
+ STRING_REF TokenToUpdate;
+ STRING_REF TokenToGet;
+ SMBIOS_TABLE_TYPE0 *SmbiosRecord;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ SMBIOS_TABLE_TYPE0 *InputData;
+
+ //
+ // First check for invalid parameters.
+ //
+ if (RecordData == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InputData = (SMBIOS_TABLE_TYPE0 *)RecordData;
+
+ Vendor = (CHAR16 *) PcdGetPtr (PcdFirmwareVendor);
+ if (StrLen(Vendor) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
+ HiiSetString (mHiiHandle, TokenToUpdate, Vendor, NULL);
+ }
+
+ Version = GetBiosVersion();
+ if (StrLen (Version) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
+ HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);
+ }
+ else
+ {
+ Version = (CHAR16 *) PcdGetPtr (PcdBiosVersionForBmc);
+ if (StrLen (Version) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
+ HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);
+ }
+ else
+ {
+ Version = (CHAR16 *) PcdGetPtr (PcdBiosVersionString);
+ if (StrLen (Version) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
+ HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);
+ }
+ }
+ }
+
+ Char16String = GetBiosReleaseDate ();
+ if (StrLen(Char16String) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
+ HiiSetString (mHiiHandle, TokenToUpdate, Char16String, NULL);
+ }
+
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
+ Vendor = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ VendorStrLen = StrLen(Vendor);
+
+
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);
+ Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ VerStrLen = StrLen(Version);
+
+
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
+ ReleaseDate = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ DateStrLen = StrLen(ReleaseDate);
+
+ //
+ // Now update the BiosPhysicalSize
+ //
+ BiosPhysicalSizeHexValue = FixedPcdGet32 (PcdFdSize);
+
+ //
+ // Two zeros following the last string.
+ //
+ SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1);
+ if(NULL == SmbiosRecord)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Exit;
+ }
+
+ (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE0));
+
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);
+ SmbiosRecord->BiosSegment = (UINT16)(FixedPcdGet32 (PcdFdBaseAddress) / 0x10000);
+ SmbiosRecord->BiosSize = Base2ToByteWith64KUnit(BiosPhysicalSizeHexValue) - 1;
+
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+ UnicodeStrToAsciiStr(Vendor, OptionalStrStart);
+ UnicodeStrToAsciiStr(Version, OptionalStrStart + VendorStrLen + 1);
+ UnicodeStrToAsciiStr(ReleaseDate, OptionalStrStart + VendorStrLen + 1 + VerStrLen + 1);
+ //
+ // Now we have got the full smbios record, call smbios protocol to add this record.
+ //
+ Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type00 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(SmbiosRecord);
+
+Exit:
+ if(Vendor != NULL)
+ {
+ FreePool(Vendor);
+ }
+
+ if(Version != NULL)
+ {
+ FreePool(Version);
+ }
+
+ if(ReleaseDate != NULL)
+ {
+ FreePool(ReleaseDate);
+ }
+
+ if(Char16String != NULL)
+ {
+ FreePool(Char16String);
+ }
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni
new file mode 100644
index 0000000..1632f83
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni
@@ -0,0 +1,27 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+#string STR_MISC_SYSTEM_MANUFACTURER #language en-US "Huawei Technologies Co., Ltd."
+//#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "To be filled by O.E.M."
+#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "PANGEA"
+//#string STR_MISC_SYSTEM_VERSION #language en-US "To be filled by O.E.M."
+#string STR_MISC_SYSTEM_VERSION #language en-US "V200R002"
+#string STR_MISC_SYSTEM_SERIAL_NUMBER #language en-US "To be filled by O.E.M."
+#string STR_MISC_SYSTEM_SKU_NUMBER #language en-US "To be filled by O.E.M."
+#string STR_MISC_SYSTEM_FAMILY #language en-US "To be filled by O.E.M."
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c
new file mode 100644
index 0000000..37fc33b
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c
@@ -0,0 +1,52 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscSystemManufacturerData.c
+
+Abstract:
+
+ This file provide OEM to define Smbios Type1 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+
+**/
+
+/* Modify list
+DATA AUTHOR REASON
+*/
+
+#include "SmbiosMisc.h"
+
+
+//
+// Static (possibly build generated) System Manufacturer data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) = {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, // Manufacturer
+ 2, // ProductName
+ 3, // Version
+ 4, // SerialNumber
+ { // Uuid
+ 0x12345678, 0x1234, 0x5678, {0x90, 0xab, 0xcd, 0xde, 0xef, 0xaa, 0xbb, 0xcc}
+ },
+ SystemWakeupTypePowerSwitch, // SystemWakeupType
+ 5, // SKUNumber,
+ 6 // Family
+};
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c
new file mode 100644
index 0000000..fcefe24
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c
@@ -0,0 +1,195 @@
+/*++
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscSystemManufacturerFunction.c
+
+Abstract:
+
+ This driver parses the mMiscSubclassDataTable structure and reports
+ any generated data to smbios.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+
+**/
+
+#include "SmbiosMisc.h"
+
+/**
+ This function makes boot time changes to the contents of the
+ MiscSystemManufacturer (Type 1).
+
+ @param RecordData Pointer to copy of RecordData from the Data Table.
+
+ @retval EFI_SUCCESS All parameters were valid.
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer)
+{
+ CHAR8 *OptionalStrStart;
+ UINTN ManuStrLen;
+ UINTN VerStrLen;
+ UINTN PdNameStrLen;
+ UINTN SerialNumStrLen;
+ UINTN SKUNumStrLen;
+ UINTN FamilyStrLen;
+ EFI_STRING Manufacturer;
+ EFI_STRING ProductName;
+ EFI_STRING Version;
+ EFI_STRING SerialNumber;
+ EFI_STRING SKUNumber;
+ EFI_STRING Family;
+ STRING_REF TokenToGet;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ SMBIOS_TABLE_TYPE1 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE1 *InputData;
+ EFI_STATUS Status;
+ STRING_REF TokenToUpdate;
+ CHAR16 *Product;
+ CHAR16 *pVersion;
+
+ EFI_GUID Uuid;
+
+ //
+ // First check for invalid parameters.
+ //
+ if (RecordData == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InputData = (SMBIOS_TABLE_TYPE1 *)RecordData;
+
+ Product = (CHAR16 *) PcdGetPtr (PcdSystemProductName);
+ if (StrLen(Product) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);
+ HiiSetString (mHiiHandle, TokenToUpdate, Product, NULL);
+ }
+
+ pVersion = (CHAR16 *) PcdGetPtr (PcdSystemVersion);
+ if (StrLen(pVersion) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
+ HiiSetString (mHiiHandle, TokenToUpdate, pVersion, NULL);
+ }
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME), ProductNameType01);
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER), SerialNumType01);
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER), SystemManufacturerType01);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER);
+ Manufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ ManuStrLen = StrLen(Manufacturer);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);
+ ProductName = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ PdNameStrLen = StrLen(ProductName);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
+ Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ VerStrLen = StrLen(Version);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER);
+ SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ SerialNumStrLen = StrLen(SerialNumber);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER);
+ SKUNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ SKUNumStrLen = StrLen(SKUNumber);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY);
+ Family = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ FamilyStrLen = StrLen(Family);
+
+ //
+ // Two zeros following the last string.
+ //
+ SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen + 1
+ + PdNameStrLen + 1
+ + VerStrLen + 1
+ + SerialNumStrLen + 1
+ + SKUNumStrLen + 1
+ + FamilyStrLen + 1 + 1);
+
+ if (NULL == SmbiosRecord)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Exit;
+ }
+
+ (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE1));
+
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1);
+
+ SmbiosRecord->Uuid = InputData->Uuid;
+ Status = GetUuidType1 (&Uuid);
+ if (!EFI_ERROR (Status))
+ {
+ SmbiosRecord->Uuid = Uuid;
+ }
+
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+ UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);
+ UnicodeStrToAsciiStr(ProductName, OptionalStrStart + ManuStrLen + 1);
+ UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1);
+ UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1);
+ UnicodeStrToAsciiStr(SKUNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);
+ UnicodeStrToAsciiStr(Family, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen + 1);
+
+ //
+ // Now we have got the full smbios record, call smbios protocol to add this record.
+ //
+ Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(SmbiosRecord);
+
+Exit:
+ if(Manufacturer != NULL)
+ {
+ FreePool(Manufacturer);
+ }
+
+ if(ProductName != NULL)
+ {
+ FreePool(ProductName);
+ }
+
+ if(Version != NULL)
+ {
+ FreePool(Version);
+ }
+
+ if(SerialNumber != NULL)
+ {
+ FreePool(SerialNumber);
+ }
+
+ if(SKUNumber != NULL)
+ {
+ FreePool(SKUNumber);
+ }
+
+ if(Family != NULL)
+ {
+ FreePool(Family);
+ }
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni
new file mode 100644
index 0000000..11320c0
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni
@@ -0,0 +1,27 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+#string STR_MISC_BASE_BOARD_MANUFACTURER #language en-US "Huawei Technologies Co., Ltd."
+//#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "To Be Filled By O.E.M."
+#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "STL2SPCA"
+//#string STR_MISC_BASE_BOARD_VERSION #language en-US "To Be Filled By O.E.M."
+#string STR_MISC_BASE_BOARD_VERSION #language en-US "V200R002"
+#string STR_MISC_BASE_BOARD_SERIAL_NUMBER #language en-US "To Be Filled By O.E.M."
+#string STR_MISC_BASE_BOARD_ASSET_TAG #language en-US "To Be Filled By O.E.M."
+#string STR_MISC_BASE_BOARD_CHASSIS_LOCATION #language en-US "To Be Filled By O.E.M."
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c
new file mode 100644
index 0000000..20991b1
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c
@@ -0,0 +1,56 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscBaseBoardManufacturerData.c
+
+Abstract:
+
+ This file provide OEM to define Smbios Type2 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+//
+// Static (possibly build generated) Chassis Manufacturer data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer) = {
+ { // Hdr
+ EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, // BaseBoardManufacturer
+ 2, // BaseBoardProductName
+ 3, // BaseBoardVersion
+ 4, // BaseBoardSerialNumber
+ 5, // BaseBoardAssetTag
+ { // FeatureFlag
+ 1, // Motherboard :1
+ 0, // RequiresDaughterCard :1
+ 0, // Removable :1
+ 1, // Replaceable :1
+ 0, // HotSwappable :1
+ 0 // Reserved :3
+ },
+ 6, // BaseBoardChassisLocation
+ 0, // ChassisHandle;
+ BaseBoardTypeMotherBoard, // BoardType;
+ 0, // NumberOfContainedObjectHandles;
+ {
+ 0
+ } // ContainedObjectHandles[1];
+};
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c
new file mode 100644
index 0000000..a141f9e
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c
@@ -0,0 +1,198 @@
+/** @file
+
+ Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscBaseBoardManufacturerFunction.c
+
+Abstract:
+
+ This driver parses the mSmbiosMiscDataTable structure and reports
+ any generated data using SMBIOS protocol.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+
+/**
+ This function makes basic board manufacturer to the contents of the
+ Misc Base Board Manufacturer (Type 2).
+
+ @param RecordData Pointer to copy of RecordData from the Data Table.
+
+ @retval EFI_SUCCESS All parameters were valid.
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscBaseBoardManufacturer)
+{
+ CHAR8 *OptionalStrStart;
+ UINTN ManuStrLen;
+ UINTN ProductNameStrLen;
+ UINTN VerStrLen;
+ UINTN SerialNumStrLen;
+ UINTN AssetTagStrLen;
+ UINTN ChassisLocaStrLen;
+ UINTN HandleCount = 0;
+ UINT16 *HandleArray = NULL;
+ CHAR16 *BaseBoardManufacturer;
+ CHAR16 *BaseBoardProductName;
+ CHAR16 *Version;
+ EFI_STRING SerialNumber;
+ EFI_STRING AssetTag;
+ EFI_STRING ChassisLocation;
+ STRING_REF TokenToGet;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ SMBIOS_TABLE_TYPE2 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE2 *InputData = NULL;
+ EFI_STATUS Status;
+
+ STRING_REF TokenToUpdate;
+ //CHAR16 *ProductName;
+ //CHAR16 *pVersion;
+ //uniBIOS_y00216284_018_end 2015-1-13 09:08:22
+
+ //
+ // First check for invalid parameters.
+ //
+ if (RecordData == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InputData = (SMBIOS_TABLE_TYPE2*)RecordData;
+
+ BaseBoardProductName = (CHAR16 *) PcdGetPtr (PcdBaseBoardProductName);
+ if (StrLen(BaseBoardProductName) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);
+ HiiSetString (mHiiHandle, TokenToUpdate, BaseBoardProductName, NULL);
+ }
+
+ Version = (CHAR16 *) PcdGetPtr (PcdBaseBoardVersion);
+ if (StrLen(Version) > 0)
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);
+ HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);
+ }
+
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG), AssertTagType02);
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER), SrNumType02);
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER), BoardManufacturerType02);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);
+ BaseBoardManufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ ManuStrLen = StrLen(BaseBoardManufacturer);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);
+ BaseBoardProductName = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ ProductNameStrLen = StrLen(BaseBoardProductName);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);
+ Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ VerStrLen = StrLen(Version);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER);
+ SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ SerialNumStrLen = StrLen(SerialNumber);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG);
+ AssetTag = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ AssetTagStrLen = StrLen(AssetTag);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION);
+ ChassisLocation = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ ChassisLocaStrLen = StrLen(ChassisLocation);
+
+ //
+ // Two zeros following the last string.
+ //
+ SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE2) + ManuStrLen + 1
+ + ProductNameStrLen + 1
+ + VerStrLen + 1
+ + SerialNumStrLen + 1
+ + AssetTagStrLen + 1
+ + ChassisLocaStrLen + 1 + 1);
+ if (NULL == SmbiosRecord)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Exit;
+ }
+
+ (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE2));
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2);
+
+ //
+ // Update Contained objects Handle
+ //
+ SmbiosRecord->NumberOfContainedObjectHandles = 0;
+ GetLinkTypeHandle(EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, &HandleArray, &HandleCount);
+ if(HandleCount)
+ {
+ SmbiosRecord->ChassisHandle = HandleArray[0];
+ }
+
+ FreePool(HandleArray);
+
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+ UnicodeStrToAsciiStr(BaseBoardManufacturer, OptionalStrStart);
+ UnicodeStrToAsciiStr(BaseBoardProductName, OptionalStrStart + ManuStrLen + 1);
+ UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1);
+ UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1 + VerStrLen + 1);
+ UnicodeStrToAsciiStr(AssetTag, OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 );
+ UnicodeStrToAsciiStr(ChassisLocation, OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssetTagStrLen + 1);
+
+ Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type02 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(SmbiosRecord);
+
+Exit:
+ if(BaseBoardManufacturer != NULL)
+ {
+ FreePool(BaseBoardManufacturer);
+ }
+
+ if(BaseBoardProductName != NULL)
+ {
+ FreePool(BaseBoardProductName);
+ }
+
+ if(Version != NULL)
+ {
+ FreePool(Version);
+ }
+
+ if(SerialNumber != NULL)
+ {
+ FreePool(SerialNumber);
+ }
+
+ if(AssetTag != NULL)
+ {
+ FreePool(AssetTag);
+ }
+
+ if(ChassisLocation != NULL)
+ {
+ FreePool(ChassisLocation);
+ }
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni
new file mode 100644
index 0000000..543ef00
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni
@@ -0,0 +1,24 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+#string STR_MISC_CHASSIS_MANUFACTURER #language en-US "Huawei Technologies Co., Ltd."
+#string STR_MISC_CHASSIS_VERSION #language en-US "To Be Filled By O.E.M."
+#string STR_MISC_CHASSIS_SERIAL_NUMBER #language en-US "To Be Filled By O.E.M."
+#string STR_MISC_CHASSIS_ASSET_TAG #language en-US "To Be Filled By O.E.M."
+#string STR_MISC_CHASSIS_SKU_NUMBER #language en-US "To Be Filled By O.E.M."
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c
new file mode 100644
index 0000000..6237fbe
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c
@@ -0,0 +1,66 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscChassisManufacturerData.c
+
+Abstract:
+
+ This file provide OEM to define Smbios Type3 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+/* Modify list
+DATA AUTHOR REASON
+*/
+
+#include "SmbiosMisc.h"
+
+
+//
+// Static (possibly build generated) Chassis Manufacturer data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE , // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, // Manufactrurer
+ MiscChassisTypeMainServerChassis, // Type
+ 2, // Version
+ 3, // SerialNumber
+ 4, // AssetTag
+ ChassisStateSafe, // BootupState
+ ChassisStateSafe, // PowerSupplyState
+ ChassisStateSafe, // ThermalState
+ ChassisSecurityStatusNone, // SecurityState
+ {
+ 0, // OemDefined[0]
+ 0, // OemDefined[1]
+ 0, // OemDefined[2]
+ 0 // OemDefined[3]
+ },
+ 2, // Height
+ 1, // NumberofPowerCords
+ 0, // ContainedElementCount
+ 0, // ContainedElementRecordLength
+ { // ContainedElements[0]
+ {
+ 0, // ContainedElementType
+ 0, // ContainedElementMinimum
+ 0 // ContainedElementMaximum
+ }
+ }
+};
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
new file mode 100644
index 0000000..4bb1701
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
@@ -0,0 +1,199 @@
+/** @file
+
+Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscChassisManufacturerFunction.c
+
+Abstract:
+
+ This driver parses the mMiscSubclassDataTable structure and reports
+ any generated data to smbios.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+/* Modify list
+DATA AUTHOR REASON
+*/
+
+#include "SmbiosMisc.h"
+
+UINT8
+GetChassisType (
+)
+{
+ EFI_STATUS Status;
+ UINT8 ChassisType;
+ Status = IpmiGetChassisType(&ChassisType);
+ if (EFI_ERROR(Status))
+ {
+ return 0;
+ }
+
+ return ChassisType;
+}
+
+/**
+ This function makes boot time changes to the contents of the
+ MiscChassisManufacturer (Type 3).
+
+ @param RecordData Pointer to copy of RecordData from the Data Table.
+
+ @retval EFI_SUCCESS All parameters were valid.
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscChassisManufacturer)
+{
+ CHAR8 *OptionalStrStart;
+ UINTN ManuStrLen;
+ UINTN VerStrLen;
+ UINTN AssertTagStrLen;
+ UINTN SerialNumStrLen;
+ UINTN ChaNumStrLen;
+ EFI_STRING Manufacturer;
+ EFI_STRING Version;
+ EFI_STRING SerialNumber;
+ EFI_STRING AssertTag;
+ EFI_STRING ChassisSkuNumber;
+ STRING_REF TokenToGet;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ SMBIOS_TABLE_TYPE3 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE3 *InputData;
+ EFI_STATUS Status;
+
+ UINT8 ContainedElementCount;
+ CONTAINED_ELEMENT ContainedElements = {0};
+ UINT8 ExtendLength = 0;
+
+ UINT8 ChassisType;
+
+ //
+ // First check for invalid parameters.
+ //
+ if (RecordData == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InputData = (SMBIOS_TABLE_TYPE3 *)RecordData;
+
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG), AssetTagType03);
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER), SrNumType03);
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_VERSION), VersionType03);
+ UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER), ManufacturerType03);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);
+ Manufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ ManuStrLen = StrLen(Manufacturer);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION);
+ Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ VerStrLen = StrLen(Version);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);
+ SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ SerialNumStrLen = StrLen(SerialNumber);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);
+ AssertTag = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ AssertTagStrLen = StrLen(AssertTag);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER);
+ ChassisSkuNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ ChaNumStrLen = StrLen(ChassisSkuNumber);
+
+ ContainedElementCount = InputData->ContainedElementCount;
+
+ if (ContainedElementCount > 1)
+ {
+ ExtendLength = (ContainedElementCount - 1) * sizeof (CONTAINED_ELEMENT);
+ }
+
+ //
+ // Two zeros following the last string.
+ //
+ SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength + 1
+ + ManuStrLen + 1
+ + VerStrLen + 1
+ + SerialNumStrLen + 1
+ + AssertTagStrLen + 1
+ + ChaNumStrLen + 1 + 1);
+ if (NULL == SmbiosRecord)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Exit;
+ }
+
+ (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE3));
+
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength + 1;
+
+ ChassisType = GetChassisType ();
+ if (ChassisType != 0)
+ {
+ SmbiosRecord->Type = ChassisType;
+ }
+
+ //ContainedElements
+ (VOID)CopyMem(SmbiosRecord + 1, &ContainedElements, ExtendLength);
+
+ //ChassisSkuNumber
+ *((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength) = 5;
+
+ OptionalStrStart = (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength + 1);
+ UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);
+ UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1);
+ UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1);
+ UnicodeStrToAsciiStr(AssertTag, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);
+ UnicodeStrToAsciiStr(ChassisSkuNumber, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen +1 + AssertTagStrLen + 1);
+ //
+ // Now we have got the full smbios record, call smbios protocol to add this record.
+ //
+ Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type03 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(SmbiosRecord);
+
+Exit:
+ if(Manufacturer != NULL)
+ {
+ FreePool(Manufacturer);
+ }
+
+ if(Version != NULL)
+ {
+ FreePool(Version);
+ }
+
+ if(SerialNumber != NULL)
+ {
+ FreePool(SerialNumber);
+ }
+
+ if(AssertTag != NULL)
+ {
+ FreePool(AssertTag);
+ }
+
+ if(ChassisSkuNumber != NULL)
+ {
+ FreePool(ChassisSkuNumber);
+ }
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignation.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignation.uni
new file mode 100644
index 0000000..19968f2
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignation.uni
Binary files differ
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationData.c
new file mode 100644
index 0000000..f9b1f03
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationData.c
@@ -0,0 +1,162 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscSystemSlotDesignationData.c
+
+Abstract:
+
+ This file provide OEM to define Smbios Type09 Data
+
+**/
+
+#include "SmbiosMisc.h"
+
+
+//
+// Static (possibly build generated) Bios Vendor data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie0) = {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, // SlotDesignation
+ SlotTypePciExpressX8, // SlotType
+ SlotDataBusWidth8X, // SlotDataBusWidth
+ SlotUsageOther, // SlotUsage
+ SlotLengthOther, // SlotLength
+ 0x0000, // SlotId
+ { // SlotCharacteristics1
+ 0, // CharacteristicsUnknown :1;
+ 0, // Provides50Volts :1;
+ 0, // Provides33Volts :1;
+ 0, // SharedSlot :1;
+ 0, // PcCard16Supported :1;
+ 0, // CardBusSupported :1;
+ 0, // ZoomVideoSupported :1;
+ 0 // ModemRingResumeSupported:1;
+ },
+ { // SlotCharacteristics2
+ 0, // PmeSignalSupported :1;
+ 0, // HotPlugDevicesSupported :1;
+ 0, // SmbusSignalSupported :1;
+ 0 // Reserved :5;
+ },
+ 0x00, // SegmentGroupNum
+ 0x00, // BusNum
+ 0 // DevFuncNum
+};
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie1) = {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, // SlotDesignation
+ SlotTypePciExpressX8, // SlotType
+ SlotDataBusWidth8X, // SlotDataBusWidth
+ SlotUsageAvailable, // SlotUsage
+ SlotLengthOther, // SlotLength
+ 0x0001, // SlotId
+ { // SlotCharacteristics1
+ 0, // CharacteristicsUnknown :1;
+ 0, // Provides50Volts :1;
+ 0, // Provides33Volts :1;
+ 0, // SharedSlot :1;
+ 0, // PcCard16Supported :1;
+ 0, // CardBusSupported :1;
+ 0, // ZoomVideoSupported :1;
+ 0 // ModemRingResumeSupported:1;
+ },
+ { // SlotCharacteristics2
+ 0, // PmeSignalSupported :1;
+ 0, // HotPlugDevicesSupported :1;
+ 0, // SmbusSignalSupported :1;
+ 0 // Reserved :5;
+ },
+ 0x00, // SegmentGroupNum
+ 0x40, // BusNum
+ 0 // DevFuncNum
+};
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie2) = {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, // SlotDesignation
+ SlotTypePciExpressX8, // SlotType
+ SlotDataBusWidth8X, // SlotDataBusWidth
+ SlotUsageOther, // SlotUsage
+ SlotLengthOther, // SlotLength
+ 0x0002, // SlotId
+ { // SlotCharacteristics1
+ 0, // CharacteristicsUnknown :1;
+ 0, // Provides50Volts :1;
+ 0, // Provides33Volts :1;
+ 0, // SharedSlot :1;
+ 0, // PcCard16Supported :1;
+ 0, // CardBusSupported :1;
+ 0, // ZoomVideoSupported :1;
+ 0 // ModemRingResumeSupported:1;
+ },
+ { // SlotCharacteristics2
+ 0, // PmeSignalSupported :1;
+ 0, // HotPlugDevicesSupported :1;
+ 0, // SmbusSignalSupported :1;
+ 0 // Reserved :5;
+ },
+ 0x00, // SegmentGroupNum
+ 0x80, // BusNum
+ 0 // DevFuncNum
+};
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie3) = {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 1, // SlotDesignation
+ SlotTypePciExpressX4, // SlotType
+ SlotDataBusWidth4X, // SlotDataBusWidth
+ SlotUsageOther, // SlotUsage
+ SlotLengthOther, // SlotLength
+ 0x0003, // SlotId
+ { // SlotCharacteristics1
+ 0, // CharacteristicsUnknown :1;
+ 0, // Provides50Volts :1;
+ 0, // Provides33Volts :1;
+ 0, // SharedSlot :1;
+ 0, // PcCard16Supported :1;
+ 0, // CardBusSupported :1;
+ 0, // ZoomVideoSupported :1;
+ 0 // ModemRingResumeSupported:1;
+ },
+ { // SlotCharacteristics2
+ 0, // PmeSignalSupported :1;
+ 0, // HotPlugDevicesSupported :1;
+ 0, // SmbusSignalSupported :1;
+ 0 // Reserved :5;
+ },
+ 0x00, // SegmentGroupNum
+ 0xC0, // BusNum
+ 0 // DevFuncNum
+};
+
+/* eof - MiscSystemSlotsData.c */
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c
new file mode 100644
index 0000000..a0e3de3
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c
@@ -0,0 +1,204 @@
+/** @file
+ BIOS system slot designator information boot time changes.
+ SMBIOS type 9.
+
+ Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SmbiosMisc.h"
+
+#include <Library/SerdesLib.h>
+
+extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie0Data;
+extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie1Data;
+extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie2Data;
+extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie3Data;
+
+VOID
+UpdateSlotDesignation (
+ IN SMBIOS_TABLE_TYPE9 *InputData
+ )
+{
+ STRING_REF TokenToUpdate;
+ CHAR16 *SlotDesignation;
+ UINTN DesignationStrLen;
+
+ SlotDesignation = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+ if (NULL == SlotDesignation)
+ {
+ return;
+ }
+
+ if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data)
+ {
+ UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE0");
+ }
+ else if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data)
+ {
+ UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE1");
+ }
+ else if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data)
+ {
+ UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE2");
+ }
+ else if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data)
+ {
+ UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE3");
+ }
+
+ DesignationStrLen = StrLen (SlotDesignation);
+
+ if (DesignationStrLen > 0 )
+ {
+ TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_DESIGNATION);
+ HiiSetString (mHiiHandle, TokenToUpdate, SlotDesignation, NULL);
+ }
+
+ FreePool (SlotDesignation);
+}
+
+VOID
+UpdateSlotUsage(
+ IN OUT SMBIOS_TABLE_TYPE9 *InputData
+ )
+{
+ EFI_STATUS Status;
+ serdes_param_t sSerdesParam;
+
+ Status = OemGetSerdesParam (&sSerdesParam);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __FUNCTION__, __LINE__, Status));
+ return;
+ }
+
+ //
+ // PCIE0
+ //
+ if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && sSerdesParam.hilink1_mode == EM_HILINK1_PCIE0_8LANE)
+ {
+ InputData->CurrentUsage = SlotUsageAvailable;
+ }
+
+ //
+ // PCIE1
+ //
+ if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data)
+ {
+ if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE)
+ {
+ InputData->SlotDataBusWidth = SlotDataBusWidth4X;
+ }
+ }
+
+ //
+ // PCIE2
+ //
+ if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data)
+ {
+ if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE)
+ {
+ InputData->SlotDataBusWidth = SlotDataBusWidth4X;
+ InputData->CurrentUsage = SlotUsageAvailable;
+ }
+ else if (sSerdesParam.hilink2_mode == EM_HILINK2_PCIE2_8LANE)
+ {
+ InputData->CurrentUsage = SlotUsageAvailable;
+ }
+ }
+
+ //
+ // PCIE3
+ //
+ if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && sSerdesParam.hilink5_mode == EM_HILINK5_PCIE3_4LANE)
+ {
+ InputData->CurrentUsage = SlotUsageAvailable;
+ }
+}
+
+/**
+ This function makes boot time changes to the contents of the
+ MiscSystemSlotDesignator structure (Type 9).
+
+ @param RecordData Pointer to copy of RecordData from the Data Table.
+
+ @retval EFI_SUCCESS All parameters were valid.
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscSystemSlotDesignation)
+{
+ CHAR8 *OptionalStrStart;
+ UINTN SlotDesignationStrLen;
+ EFI_STATUS Status;
+ EFI_STRING SlotDesignation;
+ STRING_REF TokenToGet;
+ SMBIOS_TABLE_TYPE9 *SmbiosRecord;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ SMBIOS_TABLE_TYPE9 *InputData = NULL;
+
+ //
+ // First check for invalid parameters.
+ //
+ if (RecordData == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InputData = (SMBIOS_TABLE_TYPE9 *)RecordData;
+
+ UpdateSlotUsage (InputData);
+
+ UpdateSlotDesignation (InputData);
+
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_DESIGNATION);
+ SlotDesignation = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+ SlotDesignationStrLen = StrLen(SlotDesignation);
+
+ //
+ // Two zeros following the last string.
+ //
+ SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE9) + SlotDesignationStrLen + 1 + 1);
+ if(NULL == SmbiosRecord)
+ {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Exit;
+ }
+
+ (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE9));
+
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9);
+
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+ UnicodeStrToAsciiStr(SlotDesignation, OptionalStrStart);
+ //
+ // Now we have got the full smbios record, call smbios protocol to add this record.
+ //
+
+ Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type09 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(SmbiosRecord);
+
+Exit:
+ if(SlotDesignation != NULL)
+ {
+ FreePool(SlotDesignation);
+ }
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguages.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguages.uni
new file mode 100644
index 0000000..c9873ad
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguages.uni
@@ -0,0 +1,49 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+/=#
+//
+// Language String (Long Format)
+//
+#string STR_MISC_BIOS_LANGUAGES_ENG_LONG #language en-US "en|US|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_FRA_LONG #language en-US "fr|CA|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_CHN_LONG #language en-US "zh|TW|unicode"
+#string STR_MISC_BIOS_LANGUAGES_JPN_LONG #language en-US "ja|JP|unicode"
+#string STR_MISC_BIOS_LANGUAGES_ITA_LONG #language en-US "it|IT|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_SPA_LONG #language en-US "es|ES|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_GER_LONG #language en-US "de|DE|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_POR_LONG #language en-US "pt|PT|iso8859-1"
+
+
+//
+// Language String (Abbreviated Format)
+//
+#string STR_MISC_BIOS_LANGUAGES_ENG_ABBREVIATE #language en-US "enUS"
+#string STR_MISC_BIOS_LANGUAGES_FRA_ABBREVIATE #language en-US "frCA"
+#string STR_MISC_BIOS_LANGUAGES_CHN_ABBREVIATE #language en-US "zhTW"
+#string STR_MISC_BIOS_LANGUAGES_JPN_ABBREVIATE #language en-US "jaJP"
+#string STR_MISC_BIOS_LANGUAGES_ITA_ABBREVIATE #language en-US "itIT"
+#string STR_MISC_BIOS_LANGUAGES_SPA_ABBREVIATE #language en-US "esES"
+#string STR_MISC_BIOS_LANGUAGES_GER_ABBREVIATE #language en-US "deDE"
+#string STR_MISC_BIOS_LANGUAGES_POR_ABBREVIATE #language en-US "ptPT"
+
+#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_ABBREVIATE #language en-US "zhCN"
+#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_LONG #language en-US "zh|CN|unicode"
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c
new file mode 100644
index 0000000..60f6160
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c
@@ -0,0 +1,46 @@
+/**@file
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscNumberOfInstallableLanguagesData.c
+
+Abstract:
+
+ This file provide OEM to define Smbios Type13 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+//
+// Static (possibly build generated) Bios Vendor data.
+//
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages) =
+{
+ { // Hdr
+ EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ 0, // InstallableLanguages
+ 0, // Flags
+ {
+ 0 // Reserved[15]
+ },
+ 1 // CurrentLanguage
+};
+
+/* eof - MiscNumberOfInstallableLanguagesData.c */
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c
new file mode 100644
index 0000000..1f8f3ea
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c
@@ -0,0 +1,163 @@
+/** @file
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+/* Modify list
+DATA AUTHOR REASON
+*/
+
+#include "SmbiosMisc.h"
+
+/**
+ Get next language from language code list (with separator ';').
+
+ @param LangCode Input: point to first language in the list. On
+ Otput: point to next language in the list, or
+ NULL if no more language in the list.
+ @param Lang The first language in the list.
+
+**/
+VOID
+EFIAPI
+GetNextLanguage (
+ IN OUT CHAR8 **LangCode,
+ OUT CHAR8 *Lang
+ )
+{
+ UINTN Index;
+ CHAR8 *StringPtr;
+
+ if(NULL == LangCode || NULL == *LangCode || NULL == Lang) {
+ return;
+ }
+
+ Index = 0;
+ StringPtr = *LangCode;
+ while (StringPtr[Index] != 0 && StringPtr[Index] != ';') {
+ Index++;
+ }
+
+ (VOID)CopyMem(Lang, StringPtr, Index);
+ Lang[Index] = 0;
+
+ if (StringPtr[Index] == ';') {
+ Index++;
+ }
+ *LangCode = StringPtr + Index;
+}
+
+/**
+ This function returns the number of supported languages on HiiHandle.
+
+ @param HiiHandle The HII package list handle.
+
+ @retval The number of supported languages.
+
+**/
+UINT16
+EFIAPI
+GetSupportedLanguageNumber (
+ IN EFI_HII_HANDLE HiiHandle
+ )
+{
+ CHAR8 *Lang;
+ CHAR8 *Languages;
+ CHAR8 *LanguageString;
+ UINT16 LangNumber;
+
+ Languages = HiiGetSupportedLanguages (HiiHandle);
+ if (Languages == NULL) {
+ return 0;
+ }
+
+ LangNumber = 0;
+ Lang = AllocatePool (AsciiStrSize (Languages));
+ if (Lang != NULL) {
+ LanguageString = Languages;
+ while (*LanguageString != 0) {
+ GetNextLanguage (&LanguageString, Lang);
+ LangNumber++;
+ }
+ FreePool (Lang);
+ }
+ FreePool (Languages);
+ return LangNumber;
+}
+
+
+/**
+ This function makes boot time changes to the contents of the
+ MiscNumberOfInstallableLanguages (Type 13).
+
+ @param RecordData Pointer to copy of RecordData from the Data Table.
+
+ @retval EFI_SUCCESS All parameters were valid.
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscNumberOfInstallableLanguages)
+{
+ UINTN LangStrLen;
+ CHAR8 CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];
+ CHAR8 *OptionalStrStart;
+ EFI_STATUS Status;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ SMBIOS_TABLE_TYPE13 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE13 *InputData = NULL;;
+
+ //
+ // First check for invalid parameters.
+ //
+ if (RecordData == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InputData = (SMBIOS_TABLE_TYPE13 *)RecordData;
+
+ InputData->InstallableLanguages = GetSupportedLanguageNumber (mHiiHandle);
+
+ //
+ // Try to check if current langcode matches with the langcodes in installed languages
+ //
+ ZeroMem(CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1);
+ (VOID)AsciiStrCpyS(CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1, "en|US|iso8859-1");
+ LangStrLen = AsciiStrLen(CurrentLang);
+
+ //
+ // Two zeros following the last string.
+ //
+ SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1 + 1);
+ if(NULL == SmbiosRecord) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE13));
+
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13);
+
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+ (VOID)AsciiStrCpyS(OptionalStrStart, SMBIOS_STRING_MAX_LENGTH - 1, CurrentLang);
+ //
+ // Now we have got the full smbios record, call smbios protocol to add this record.
+ //
+ Status = LogSmbiosData((UINT8*)SmbiosRecord, &SmbiosHandle);
+ if(EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type13 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(SmbiosRecord);
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c
new file mode 100644
index 0000000..9f04694
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c
@@ -0,0 +1,48 @@
+/**@file
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscBootInformationData.c
+
+Abstract:
+
+ This driver parses the mMiscSubclassDataTable structure and reports
+ any generated data to the DataHub.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+//
+// Static (possibly build generated) Bios Vendor data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE32, MiscBootInformation) = {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type,
+ 0, // Length,
+ 0 // Handle
+ },
+ { // Reserved[6]
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ },
+ BootInformationStatusNoError // BootInformationStatus
+};
+
+/* eof - MiscBootInformationData.c */
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c
new file mode 100644
index 0000000..7840445
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c
@@ -0,0 +1,74 @@
+/** @file
+ boot information boot time changes.
+ SMBIOS type 32.
+
+Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+/* Modify list
+DATA AUTHOR REASON
+*/
+
+#include "SmbiosMisc.h"
+
+/**
+ This function makes boot time changes to the contents of the
+ MiscBootInformation (Type 32).
+
+ @param RecordData Pointer to copy of RecordData from the Data Table.
+
+ @retval EFI_SUCCESS All parameters were valid.
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.
+
+**/
+
+MISC_SMBIOS_TABLE_FUNCTION(MiscBootInformation)
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ SMBIOS_TABLE_TYPE32 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE32 *InputData;
+
+ //
+ // First check for invalid parameters.
+ //
+ if (RecordData == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InputData = (SMBIOS_TABLE_TYPE32 *)RecordData;
+
+ //
+ // Two zeros following the last string.
+ //
+ SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1);
+ if(NULL == SmbiosRecord) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE32));
+
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32);
+
+ //
+ // Now we have got the full smbios record, call smbios protocol to add this record.
+ //
+ Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+ if(EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type32 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(SmbiosRecord);
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationData.c
new file mode 100644
index 0000000..2dc99f1
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationData.c
@@ -0,0 +1,42 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscIpmiDeviceInformationData.c
+
+Abstract:
+
+ This file provide OEM to define Smbios Type38 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE38, MiscIpmiDeviceInformation) =
+{
+ { // Header
+ EFI_SMBIOS_TYPE_IPMI_DEVICE_INFORMATION, // Type;
+ 0, // Length;
+ 0 // Handle;
+ },
+ IPMIDeviceInfoInterfaceTypeUnknown, // InterfaceType
+ 0x00, // Ipmi Specification Revision
+ 0, // I2CSlaveAddress
+ 0xFF, // NvStorageDeviceAddress
+ 0x88, // BaseAddress
+ 0, // BaseAddressModifier/InterruptInfo
+ 0 // InterruptNumber
+};
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationFunction.c
new file mode 100644
index 0000000..f198237
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationFunction.c
@@ -0,0 +1,87 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MiscIpmiDeviceInformationFunction.c
+
+Abstract:
+
+ This driver parses the mMiscSubclassDataTable structure and reports
+ any generated data to smbios.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+/* Modify list
+DATA AUTHOR REASON
+*/
+
+#include "SmbiosMisc.h"
+
+#include <Protocol/IpmiInterfaceProtocol.h>
+
+/**
+ This function makes the attributes of IPMI to the contents of the
+ MiscChassisManufacturer structure.
+
+ @param RecordData Pointer to copy of RecordData from the Data Table.
+
+ @retval EFI_SUCCESS All parameters were valid.
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscIpmiDeviceInformation)
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ SMBIOS_TABLE_TYPE38 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE38 *InputData = NULL;
+
+ IPMI_INTERFACE_PROTOCOL *Ipmi;
+
+ //
+ // First check for invalid parameters.
+ //
+ if (RecordData == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InputData = (SMBIOS_TABLE_TYPE38*)RecordData;
+
+ SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE38) + 1 + 1);
+ if(NULL == SmbiosRecord) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE38));
+
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE38);
+
+ Status = gBS->LocateProtocol (&gIpmiInterfaceProtocolGuid, NULL, (VOID **)&Ipmi);
+ if (!EFI_ERROR (Status)) {
+ SmbiosRecord->InterfaceType = Ipmi->GetIpmiInterfaceType (Ipmi);
+ SmbiosRecord->BaseAddress = (UINT64)Ipmi->GetIpmiBaseAddress (Ipmi) | Ipmi->GetIpmiBaseAddressType (Ipmi);
+ SmbiosRecord->IPMISpecificationRevision = Ipmi->GetIpmiVersion (Ipmi);
+ }
+ //
+ // Now we have got the full smbios record, call smbios protocol to add this record.
+ //
+ Status = LogSmbiosData((UINT8*)SmbiosRecord, &SmbiosHandle);
+ if(EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type38 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+ }
+
+ FreePool(SmbiosRecord);
+ return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.c b/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.c
new file mode 100644
index 0000000..40e9137
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.c
@@ -0,0 +1,108 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <Guid/VersionInfoHobGuid.h>
+
+struct MonthDescription {
+ CONST CHAR8* MonthStr;
+ UINT32 MonthInt;
+} gMonthDescription[] = {
+ { "Jan", 1 },
+ { "Feb", 2 },
+ { "Mar", 3 },
+ { "Apr", 4 },
+ { "May", 5 },
+ { "Jun", 6 },
+ { "Jul", 7 },
+ { "Aug", 8 },
+ { "Sep", 9 },
+ { "Oct", 10 },
+ { "Nov", 11 },
+ { "Dec", 12 },
+ { "???", 1 }, // Use 1 as default month
+};
+
+VOID GetReleaseTime (EFI_TIME *Time)
+{
+ CONST CHAR8 *ReleaseDate = __DATE__;
+ CONST CHAR8 *ReleaseTime = __TIME__;
+ UINTN i;
+
+ for(i=0;i<12;i++)
+ {
+ if(0 == AsciiStrnCmp(ReleaseDate, gMonthDescription[i].MonthStr, 3))
+ {
+ break;
+ }
+ }
+ Time->Month = gMonthDescription[i].MonthInt;
+ Time->Day = AsciiStrDecimalToUintn(ReleaseDate+4);
+ Time->Year = AsciiStrDecimalToUintn(ReleaseDate+7);
+ Time->Hour = AsciiStrDecimalToUintn(ReleaseTime);
+ Time->Minute = AsciiStrDecimalToUintn(ReleaseTime+3);
+ Time->Second = AsciiStrDecimalToUintn(ReleaseTime+6);
+
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+VersionInfoEntry (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+ VERSION_INFO *VersionInfo;
+ EFI_TIME Time = {0};
+ CONST CHAR16 *ReleaseString =
+ (CHAR16 *) FixedPcdGetPtr (PcdFirmwareVersionString);
+
+ GetReleaseTime (&Time);
+
+ CharCount = AsciiSPrint (
+ Buffer,
+ sizeof (Buffer),
+ "\n\rBoot firmware (version %s built at %t)\n\r\n\r",
+ ReleaseString,
+ &Time
+ );
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ VersionInfo = BuildGuidHob (&gVersionInfoHobGuid,
+ sizeof (VERSION_INFO) -
+ sizeof (VersionInfo->String) +
+ StrSize (ReleaseString));
+ if (VersionInfo == NULL) {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%d] Build HOB failed!\n", __FILE__, __LINE__));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ CopyMem (&VersionInfo->BuildTime, &Time, sizeof (EFI_TIME));
+ CopyMem (VersionInfo->String, ReleaseString, StrSize (ReleaseString));
+
+ return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf b/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
new file mode 100644
index 0000000..bad1ae9
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
@@ -0,0 +1,53 @@
+#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = VersionInfoPeim
+ FILE_GUID = F414EE11-EEE3-4edc-8C12-0E80E446A849
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = VersionInfoEntry
+
+[Sources.common]
+ VersionInfoPeim.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ PcdLib
+ DebugLib
+ HobLib
+ BaseLib
+ BaseMemoryLib
+ PrintLib
+ SerialPortLib
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+
+[Guids]
+ gVersionInfoHobGuid
+
+[Depex]
+ TRUE
+
+[BuildOptions]
+
diff --git a/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
new file mode 100644
index 0000000..d14f9df
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
@@ -0,0 +1,682 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "VirtualEhciPciIo.h"
+#include <Protocol/PciRootBridgeIo.h>
+
+UINT32 mUsbMemBase;
+UINTN mSegmentNumber = 0;
+// Use 0xFF for the virtual PCI devices
+UINTN mBusNumber = 0xFF;
+UINTN mDeviceNumber = 0;
+UINTN mFunctionNumber = 0;
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS HostAddress;
+ EFI_PHYSICAL_ADDRESS DeviceAddress;
+ UINTN NumberOfBytes;
+ EFI_PCI_IO_PROTOCOL_OPERATION Operation;
+ BOOLEAN DoubleBuffer;
+} MEM_MAP_INFO_INSTANCE;
+
+
+EFI_CPU_ARCH_PROTOCOL *gCpu;
+
+
+EHCI_PCI_CONFIG mEhciPciConfig = {
+ {
+ 0x00,//UINT16 VendorId;
+ 0x00,//UINT16 DeviceId;
+ 0x00,//UINT16 Command;
+ 0x0010,//UINT16 Status;
+ 0x00,//UINT8 RevisionID;
+ {
+ PCI_IF_EHCI,//UINT8 ClassCode[3];
+ PCI_CLASS_SERIAL_USB,
+ PCI_CLASS_SERIAL
+ },
+ 0x00,//UINT8 CacheLineSize;
+ 0x00,//UINT8 LatencyTimer;
+ 0x00,//UINT8 HeaderType;
+ 0x00//UINT8 BIST;
+ },
+ {
+ {
+ 0x00,//UINT32 Bar[6];
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00
+ },
+ 0x00,//UINT32 CISPtr;
+ 0x00,//UINT16 SubsystemVendorID;
+ 0x00,//UINT16 SubsystemID;
+ 0x00,//UINT32 ExpansionRomBar;
+ 0x40,//UINT8 CapabilityPtr;
+ {
+ 0x00,//UINT8 Reserved1[3];
+ 0x00,
+ 0x00
+ },
+ 0x00,//UINT32 Reserved2;
+ 0x00,//UINT8 InterruptLine;
+ 0x00,//UINT8 InterruptPin;
+ 0x00,//UINT8 MinGnt;
+ 0x00//UINT8 MaxLat;
+ },
+ 0x0A,// UINT8 CapabilityID offset 0x40
+ 0x00,// UINT8 NextItemPtr
+ 0x2000 //UINT16 DebugPort
+};
+
+
+
+EFI_STATUS
+EhciPciIoPollMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoPollIo (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoMemRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ UINT32 i;
+
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (BarIndex != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Width = Width & 0x03;
+
+ //
+ // Loop for each iteration and move the data
+ //
+ switch (Width) {
+ case EfiPciWidthUint8:
+ for (i = 0; i < Count; i++){
+ *((UINT8 *)Buffer + i)= MmioRead8(mUsbMemBase + Offset + i);
+ }
+ break;
+ case EfiPciWidthUint16:
+ for (i = 0; i < Count; i++){
+ *((UINT16 *)Buffer + i)= MmioRead16(mUsbMemBase + Offset + i * 2);
+ }
+ break;
+ case EfiPciWidthUint32:
+ for (i = 0; i < Count; i++){
+ *((UINT32 *)Buffer + i)= MmioRead32(mUsbMemBase + Offset + i * 4);
+ }
+ break;
+ case EfiPciWidthUint64:
+ for (i = 0; i < Count; i++){
+ *((UINT64 *)Buffer + i)= MmioRead64(mUsbMemBase + Offset + i * 8);
+ }
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoMemWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ UINT32 i;
+
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ //
+ // Loop for each iteration and move the data
+ //
+ switch (Width) {
+ case EfiPciWidthUint8:
+ for (i = 0; i < Count; i++){
+ MmioWrite8(mUsbMemBase + Offset + i, *((UINT8 *)Buffer + i));
+ }
+ break;
+ case EfiPciWidthUint16:
+ for (i = 0; i < Count; i++){
+ MmioWrite16(mUsbMemBase + Offset + i * 2, *((UINT16 *)Buffer + i));
+ }
+ break;
+ case EfiPciWidthUint32:
+ for (i = 0; i < Count; i++){
+ MmioWrite32(mUsbMemBase + Offset + i * 4, *((UINT32 *)Buffer + i));
+ }
+ break;
+ case EfiPciWidthUint64:
+ for (i = 0; i < Count; i++){
+ MmioWrite64(mUsbMemBase + Offset + i * 8, *((UINT64 *)Buffer + i));
+ }
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+
+}
+
+EFI_STATUS
+EhciPciIoIoRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoIoWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoPciRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ UINT32 i;
+ UINT8 *DataPtr;
+
+ Width = Width & 0x03;
+
+ if (Offset < sizeof (EHCI_PCI_CONFIG) / sizeof (UINT8)){
+
+ DataPtr = (UINT8 *)(&mEhciPciConfig) + Offset;
+
+ switch (Width) {
+ case EfiPciWidthUint8:
+ for (i = 0; i < Count; i++){
+ *((UINT8 *)Buffer + i)= *(DataPtr + i);
+ }
+ break;
+ case EfiPciWidthUint16:
+ for (i = 0; i < Count; i++){
+ *((UINT16 *)Buffer + i)= *((UINT16 *)DataPtr + i);
+ }
+ break;
+ case EfiPciWidthUint32:
+ for (i = 0; i < Count; i++){
+ *(UINT32 *)(Buffer + i)= *((UINT32 *)DataPtr + i);
+ }
+ break;
+ case EfiPciWidthUint64:
+ for (i = 0; i < Count; i++){
+ *(UINT64 *)(Buffer + i)= *((UINT64 *)DataPtr + i);
+ }
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ } else {
+ switch (Width) {
+ case EfiPciWidthUint8:
+ *(UINT8 *)Buffer = 0xFF;
+ break;
+ case EfiPciWidthUint16:
+ *(UINT16 *)Buffer = 0xFFFF;
+ break;
+ case EfiPciWidthUint32:
+ *(UINT32 *)Buffer = 0xFFFFFFFF;
+ break;
+ case EfiPciWidthUint64:
+ *(UINT64 *)Buffer = 0xFFFFFFFFFFFFFFFF;
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoPciWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoCopyMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 DestBarIndex,
+ IN UINT64 DestOffset,
+ IN UINT8 SrcBarIndex,
+ IN UINT64 SrcOffset,
+ IN UINTN Count
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoMap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ )
+{
+ EFI_STATUS Status;
+ MEM_MAP_INFO_INSTANCE *Map;
+ VOID *Buffer;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
+
+ if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINT32)Operation >= EfiPciIoOperationMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *DeviceAddress = ConvertToPhysicalAddress (HostAddress);
+
+ // Remember range so we can flush on the other side
+ Map = AllocatePool (sizeof (MEM_MAP_INFO_INSTANCE));
+ if (Map == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ *Mapping = Map;
+
+ if ((((UINTN)HostAddress & (EFI_PAGE_SIZE - 1)) != 0) ||
+ ((*NumberOfBytes % EFI_PAGE_SIZE) != 0)) {
+
+ // Get the cacheability of the region
+ Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // If the mapped buffer is not an uncached buffer
+ if ( (GcdDescriptor.Attributes != EFI_MEMORY_WC) &&
+ (GcdDescriptor.Attributes != EFI_MEMORY_UC) )
+ {
+ //
+ // If the buffer does not fill entire cache lines we must double buffer into
+ // uncached memory. Device (PCI) address becomes uncached page.
+ //
+ Map->DoubleBuffer = TRUE;
+ Buffer = UncachedAllocatePages(EFI_SIZE_TO_PAGES (*NumberOfBytes));
+
+ if (Buffer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ CopyMem (Buffer, HostAddress, *NumberOfBytes);
+ *DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+ } else {
+ Map->DoubleBuffer = FALSE;
+ }
+ } else {
+ Map->DoubleBuffer = FALSE;
+
+ // Flush the Data Cache (should not have any effect if the memory region is uncached)
+ gCpu->FlushDataCache (gCpu, *DeviceAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);
+
+ Status = gDS->SetMemorySpaceAttributes (*DeviceAddress & ~(BASE_4KB - 1), ALIGN_VALUE (*NumberOfBytes, BASE_4KB), EFI_MEMORY_WC);
+ if (EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] SetMemorySpaceAttributes Fail. %r\n", __FUNCTION__, __LINE__, Status));
+ }
+ }
+
+ Map->HostAddress = (UINTN)HostAddress;
+ Map->DeviceAddress = *DeviceAddress;
+ Map->NumberOfBytes = *NumberOfBytes;
+ Map->Operation = Operation;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoUnmap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ )
+{
+ MEM_MAP_INFO_INSTANCE *Map;
+
+ if (Mapping == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Map = (MEM_MAP_INFO_INSTANCE *)Mapping;
+
+ if (Map->DoubleBuffer) {
+ if ((Map->Operation == EfiPciIoOperationBusMasterWrite) || (Map->Operation == EfiPciIoOperationBusMasterCommonBuffer)) {
+ CopyMem ((VOID *)(UINTN)Map->HostAddress, (VOID *)(UINTN)Map->DeviceAddress, Map->NumberOfBytes);
+ }
+
+ if((VOID *)(UINTN)Map->DeviceAddress != NULL) {
+ UncachedFreePages ((VOID *)(UINTN)Map->DeviceAddress, EFI_SIZE_TO_PAGES (Map->NumberOfBytes));
+ }
+
+
+ } else {
+ if (Map->Operation == EfiPciIoOperationBusMasterWrite) {
+ //
+ // Make sure we read buffer from uncached memory and not the cache
+ //
+ gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
+ }
+ }
+
+ FreePool (Map);
+
+ return EFI_SUCCESS;
+}
+
+
+
+EFI_STATUS
+EhciPciIoAllocateBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ )
+{
+ UINT32 HcCapParams;
+
+ if (Attributes &
+ (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE |
+ EFI_PCI_ATTRIBUTE_MEMORY_CACHED ))) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (HostAddress == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (MemoryType == EfiBootServicesData) {
+ HcCapParams = MmioRead32(mUsbMemBase + EHC_HCCPARAMS_OFFSET);
+ if ((BOOLEAN)(((HcCapParams) & (HCCP_64BIT)) == (HCCP_64BIT))){
+ *HostAddress = UncachedAllocatePages(Pages);
+ } else {
+ // TODO: We need support allocating UC memory below 4GB strictly
+ *HostAddress = UncachedAllocatePages(Pages);
+ }
+
+ }else{
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EhciPciIoFreeBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
+ )
+{
+ UncachedFreePages (HostAddress, Pages);
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoFlush (
+ IN EFI_PCI_IO_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoGetLocation (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ OUT UINTN *SegmentNumber,
+ OUT UINTN *BusNumber,
+ OUT UINTN *DeviceNumber,
+ OUT UINTN *FunctionNumber
+ )
+{
+
+ *SegmentNumber = mSegmentNumber;
+ *BusNumber = mBusNumber;
+ *DeviceNumber = mDeviceNumber;
+ *FunctionNumber = mFunctionNumber;
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EhciPciIoAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
+ IN UINT64 Attributes,
+ OUT UINT64 *Result OPTIONAL
+ )
+{
+ if (Result != NULL) {
+ *Result = 0;
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoGetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT8 BarIndex,
+ OUT UINT64 *Supports, OPTIONAL
+ OUT VOID **Resources OPTIONAL
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoSetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN UINT8 BarIndex,
+ IN OUT UINT64 *Offset,
+ IN OUT UINT64 *Length
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+//
+// Pci Io Protocol Interface
+//
+EFI_PCI_IO_PROTOCOL mEhciPciIoInterface = {
+ EhciPciIoPollMem,
+ EhciPciIoPollIo,
+ {
+ EhciPciIoMemRead,
+ EhciPciIoMemWrite
+ },
+ {
+ EhciPciIoIoRead,
+ EhciPciIoIoWrite
+ },
+ {
+ EhciPciIoPciRead,
+ EhciPciIoPciWrite
+ },
+ EhciPciIoCopyMem,
+ EhciPciIoMap,
+ EhciPciIoUnmap,
+ EhciPciIoAllocateBuffer,
+ EhciPciIoFreeBuffer,
+ EhciPciIoFlush,
+ EhciPciIoGetLocation,
+ EhciPciIoAttributes,
+ EhciPciIoGetBarAttributes,
+ EhciPciIoSetBarAttributes,
+ 0,
+ NULL
+};
+
+
+EFI_STATUS
+EFIAPI
+EhciVirtualPciIoInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_DEV_PATH EndNode;
+ EFI_DEV_PATH Node;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath = NULL;
+
+ mUsbMemBase = PlatformGetEhciBase ();
+
+ DEBUG ((EFI_D_ERROR, "mUsbMemBase: 0x%x\n", mUsbMemBase));
+
+ // Get the Cpu protocol for later use
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
+
+ //
+ // Install the pciio protocol, device path protocol
+ //
+ Handle = NULL;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiPciIoProtocolGuid,
+ &mEhciPciIoInterface,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ (void)ZeroMem (&Node, sizeof (Node));
+ Node.DevPath.Type = HARDWARE_DEVICE_PATH;
+ Node.DevPath.SubType = HW_PCI_DP;
+ (void)SetDevicePathNodeLength (&Node.DevPath, sizeof (PCI_DEVICE_PATH));
+ // Make USB controller device path different from built-in SATA controller
+ Node.Pci.Function = 1;
+ Node.Pci.Device = 0;
+
+ SetDevicePathEndNode (&EndNode.DevPath);
+
+ DevicePath = AppendDevicePathNode (&EndNode.DevPath, &Node.DevPath);
+
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiDevicePathProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ DevicePath
+ );
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] InstallProtocolInterface fail. %r\n", __FUNCTION__, __LINE__, Status));
+ }
+
+
+ return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.h b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.h
new file mode 100644
index 0000000..ae7a934
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.h
@@ -0,0 +1,82 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _EHCI_PCIIO_H_
+#define _EHCI_PCIIO_H_
+
+#include <Uefi.h>
+#include <PiDxe.h>
+
+#include <Protocol/Usb2HostController.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/Cpu.h>
+
+#include <Guid/EventGroup.h>
+
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/ArmLib.h>
+#include <Library/UncachedMemoryAllocationLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CacheMaintenanceLib.h>
+
+#include <Library/ReportStatusCodeLib.h>
+
+#include <IndustryStandard/Pci.h>
+#include <Library/PlatformSysCtrlLib.h>
+
+#define PCI_CLASS_SERIAL 0x0C
+#define PCI_CLASS_SERIAL_FIREWIRE 0x00
+#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
+#define PCI_CLASS_SERIAL_SSA 0x02
+#define PCI_CLASS_SERIAL_USB 0x03
+#define PCI_IF_EHCI 0x20
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
+#define PCI_CLASS_SERIAL_SMB 0x05
+
+//
+// Capability register offset
+//
+#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
+#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
+#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
+
+//
+// Capability register bit definition
+//
+#define HCSP_NPORTS 0x0F // Number of root hub port
+#define HCSP_PPC 0x10 // Port Power Control
+#define HCCP_64BIT 0x01 // 64-bit addressing capability
+
+
+typedef struct {
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_DEVICE_HEADER_TYPE_REGION Device;
+ UINT8 CapabilityID;
+ UINT8 NextItemPtr;
+ UINT16 DebugPort;
+} EHCI_PCI_CONFIG;
+
+
+#endif // _EHCI_PCIIO_H_
diff --git a/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
new file mode 100644
index 0000000..01c145a
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
@@ -0,0 +1,60 @@
+#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = VirtualEhciPciIo
+ FILE_GUID = CCC39A9C-33EC-4e5a-924B-2C5CD4CEF6A4
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = EhciVirtualPciIoInitialize
+
+
+[Sources]
+ VirtualEhciPciIo.h
+ VirtualEhciPciIo.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[FeaturePcd]
+
+
+[LibraryClasses]
+ MemoryAllocationLib
+ BaseLib
+ UefiLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+ IoLib
+ ReportStatusCodeLib
+ UncachedMemoryAllocationLib
+ ArmLib
+ DxeServicesTableLib
+ CacheMaintenanceLib
+ PlatformSysCtrlLib
+
+[Guids]
+
+[Protocols]
+ gEfiPciIoProtocolGuid ## TO_START
diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec
new file mode 100644
index 0000000..fd49bdc
--- /dev/null
+++ b/Chips/Hisilicon/HisiPkg.dec
@@ -0,0 +1,143 @@
+#/** @file
+#
+# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = HisiPkg
+ PACKAGE_GUID = c6013a10-758c-4c0d-bd07-e601e6721f86
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Include
+
+[Ppis]
+ gIpmiInterfacePpiGuid = {0x28ae4d88, 0xb658, 0x46b9, {0xa0, 0xe7, 0xd4, 0x95, 0xe2, 0xe8, 0x97, 0xf}}
+
+
+
+[Protocols]
+ gUniNorFlashProtocolGuid = {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}}
+ gHisiSpiFlashProtocolGuid = {0x339132DC, 0xCED7, 0x4f84, {0xAA, 0xE7, 0x2E, 0xC4, 0xF9, 0x14, 0x38, 0x2F}}
+
+ gHisiBoardNicProtocolGuid = {0xb5903955, 0x31e9, 0x4aaf, {0xb2, 0x83, 0x7, 0x9f, 0x3c, 0xc4, 0x71, 0x66}}
+ gHisiBoardXgeStatusProtocolGuid = {0xa6b8ed0e, 0xd8cc, 0x4853, {0xaa, 0x39, 0x2c, 0x3e, 0xcd, 0x7c, 0xa5, 0x97}}
+ gIpmiInterfaceProtocolGuid = {0xa37e200e, 0xda90, 0x473b, {0x8b, 0xb5, 0x1d, 0x7b, 0x11, 0xba, 0x32, 0x33}}
+ gBmcInfoProtocolGuid = {0x43fa6ffd, 0x35e4, 0x479e, {0xab, 0xec, 0x5, 0x3, 0xf6, 0x48, 0x0, 0xf5}}
+ gSataEnableFlagProtocolGuid = {0xc2b3c770, 0x8b4a, 0x4796, {0xb2, 0xcf, 0x1d, 0xee, 0x44, 0xd0, 0x32, 0xf3}}
+
+[Guids]
+ gHisiTokenSpaceGuid = {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, 0xf7, 0x7c, 0xfd, 0x52, 0x1d}}
+
+ gHisiEfiMemoryMapGuid = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}}
+ gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
+
+[LibraryClasses]
+ PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h
+ CpldIoLib|Include/Library/CpldIoLib.h
+ OemAddressMapLib|Include/Library/OemAddressMapLib.h
+ OemMiscLib|Include/Library/OemMiscLib.h
+ I2CLib|Include/Library/I2CLib.h
+ PlatformPciLib|Include/Library/PlatformPciLib.h
+
+[PcdsFixedAtBuild]
+
+ gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000|UINT32|0x01000010
+ gHisiTokenSpaceGuid.PcdUartClkInHz|24000000|UINT32|0x0100001F
+ gHisiTokenSpaceGuid.PcdSerialRegisterSpaceSize|0x10000|UINT64|0x01000019
+ gHisiTokenSpaceGuid.PcdCpldBaseAddress|0|UINT64|0x01000024
+ gHisiTokenSpaceGuid.PcdMailBoxAddress|0|UINT64|0x01000025
+
+ gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0|UINT64|0x01000037
+ gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0|UINT64|0x01000038
+
+ gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0|UINT64|0x01000041
+
+ gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0|UINT64|0x01000042
+
+ gHisiTokenSpaceGuid.PcdFirmwareVendor|L"Huawei Corp."|VOID*|0x30000052
+ gHisiTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
+ gHisiTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
+ gHisiTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000055
+ gHisiTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000056
+ gHisiTokenSpaceGuid.PcdCPUInfo|L""|VOID*|0x30000060
+ gHisiTokenSpaceGuid.PcdBiosVersionString|L""|VOID*|0x00010069
+ gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L""|VOID*|0x00010070
+
+ gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x0|UINT32|0x40000001
+
+ gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x0|UINT32|0x40000002
+ gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x0|UINT64|0x40000003
+
+ gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x0|UINT32|0x40000004
+ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008
+ gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009
+ gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a
+
+ gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038
+
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0|UINT32|0x00000044
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0|UINT32|0x00000045
+
+ gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x400000000000|UINT64|0x00000051 # 4T
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0|UINT64|0x00000052
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0|UINT64|0x00000053
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0|UINT64|0x00000054
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0|UINT64|0x00000055
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0|UINT64|0x00000056
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0|UINT64|0x00000057
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000058
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0|UINT64|0x00000059
+
+ gHisiTokenSpaceGuid.PciHb0Rb0Base|0|UINT64|0x0000005a
+ gHisiTokenSpaceGuid.PciHb0Rb1Base|0|UINT64|0x0000005b
+ gHisiTokenSpaceGuid.PciHb0Rb2Base|0|UINT64|0x0000005c
+ gHisiTokenSpaceGuid.PciHb0Rb3Base|0|UINT64|0x0000005d
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0|UINT64|0x8000005a
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0|UINT64|0x8000005b
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0|UINT64|0x8000005c
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0|UINT64|0x8000005d
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0|UINT64|0x6000005a
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0|UINT64|0x6000005b
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0|UINT64|0x6000005c
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0|UINT64|0x6000005d
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0|UINT64|0x7000005a
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0|UINT64|0x7000005b
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0|UINT64|0x7000005c
+ gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0|UINT64|0x7000005d
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0|UINT64|0x3000005a
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0|UINT64|0x3000005b
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0|UINT64|0x3000005c
+ gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0|UINT64|0x3000005d
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0|UINT64|0x9000005a
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0|UINT64|0x9000005b
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0|UINT64|0x9000005c
+ gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0|UINT64|0x9000005d
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0|UINT64|0x2000005a
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0|UINT64|0x2000005b
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0|UINT64|0x2000005c
+ gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0|UINT64|0x2000005d
+
+ gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061
+ gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0x0|UINT64|0x00000064
+
+[PcdsFeatureFlag]
+
+
+
diff --git a/Chips/Hisilicon/Include/Guid/MemoryMapData.h b/Chips/Hisilicon/Include/Guid/MemoryMapData.h
new file mode 100644
index 0000000..5e418f9
--- /dev/null
+++ b/Chips/Hisilicon/Include/Guid/MemoryMapData.h
@@ -0,0 +1,28 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef _MEMORY_MAP_GUID_H_
+#define _MEMORY_MAP_GUID_H_
+
+#define EFI_MEMORY_MAP_GUID \
+ { \
+ 0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \
+ }
+
+extern EFI_GUID gHisiEfiMemoryMapGuid;
+
+#endif
diff --git a/Chips/Hisilicon/Include/Guid/VersionInfoHobGuid.h b/Chips/Hisilicon/Include/Guid/VersionInfoHobGuid.h
new file mode 100644
index 0000000..a61a244
--- /dev/null
+++ b/Chips/Hisilicon/Include/Guid/VersionInfoHobGuid.h
@@ -0,0 +1,35 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _VERSION_INFO_HOB_GUID_H_
+#define _VERSION_INFO_HOB_GUID_H_
+
+// {0E13A14C-859C-4f22-82BD-180EE14212BF}
+#define VERSION_INFO_HOB_GUID \
+ {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
+
+extern GUID gVersionInfoHobGuid;
+
+#pragma pack(1)
+
+typedef struct {
+ EFI_TIME BuildTime;
+ CHAR16 String[1];
+} VERSION_INFO;
+
+#pragma pack()
+
+#endif
+
diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h
new file mode 100644
index 0000000..639b702
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h
@@ -0,0 +1,52 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef __ACPI_NEXT_LIB_H__
+#define __ACPI_NEXT_LIB_H__
+
+#define EFI_ACPI_6_0_GIC_ITS_INIT(GicITSHwId, GicITSBase) \
+ { \
+ EFI_ACPI_6_0_GIC_ITS, sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD\
+ }
+
+#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( \
+ GicRBase, GicRlength) \
+ { \
+ EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicRBase, GicRlength \
+ }
+
+#define EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \
+ { \
+ 3, sizeof (EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \
+ ACPIProcessorUID, Flags, ClockDomain \
+ }
+
+#define EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \
+ { \
+ 1, sizeof (EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \
+ AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \
+ EFI_ACPI_RESERVED_QWORD \
+ }
+
+
+#endif
+
diff --git a/Chips/Hisilicon/Include/Library/CpldIoLib.h b/Chips/Hisilicon/Include/Library/CpldIoLib.h
new file mode 100644
index 0000000..afc6b91
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/CpldIoLib.h
@@ -0,0 +1,22 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _CPLD_IO_LIB_H_
+#define _CPLD_IO_LIB_H_
+
+VOID WriteCpldReg(UINTN ulRegAddr, UINT8 ulValue);
+UINT8 ReadCpldReg(UINTN ulRegAddr);
+
+#endif /* _CPLD_IO_LIB_H_ */
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h
new file mode 100644
index 0000000..f424ae9
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h
@@ -0,0 +1,882 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _HW_MEM_INIT_LIB_H_
+#define _HW_MEM_INIT_LIB_H_
+
+#include <PlatformArch.h>
+
+#define I2C_CHANNEL 2
+#define MAX_I2C_DEV 6
+
+#define SPD_MODULE_PART 18
+#define SPD_MODULE_PART_DDR4 20
+
+#define NVRAM_ADDR 0x00D00000
+
+typedef enum {
+ DDR_FREQ_AUTO = 0,
+ DDR_FREQ_800,
+ DDR_FREQ_1000,
+ DDR_FREQ_1066,
+ DDR_FREQ_1200,
+ DDR_FREQ_1333,
+ DDR_FREQ_1400,
+ DDR_FREQ_1600,
+ DDR_FREQ_1800,
+ DDR_FREQ_1866,
+ DDR_FREQ_2000,
+ DDR_FREQ_2133,
+ DDR_FREQ_2200,
+ DDR_FREQ_2400,
+ DDR_FREQ_2600,
+ DDR_FREQ_2666,
+ DDR_FREQ_2800,
+ DDR_FREQ_2933,
+ DDR_FREQ_3000,
+ DDR_FREQ_3200,
+ DDR_FREQ_MAX
+} DDR_FREQUENCY_INDEX;
+
+typedef struct _DDR_FREQ_TCK
+{
+ UINT32 ddrFreq;
+ UINT32 ddrCk;
+}DDR_FREQ_TCK;
+
+typedef struct _GBL_CFG{
+
+
+}GBL_CFG;
+
+typedef struct _GBL_VAR{
+
+
+}GBL_VAR;
+
+typedef struct _GBL_NVDATA{
+
+
+}GBL_NVDATA;
+
+typedef struct _GOBAL {
+ const GBL_CFG Config; // constant input data
+ GBL_VAR Variable; // variable, volatile data
+ GBL_NVDATA NvData; // variable, non-volatile data for S3, warm boot path
+ UINT32 PreBootFailed;
+}GOBAL, *PGOBAL;
+
+struct DDR_RANK {
+ BOOLEAN Status;
+ UINT16 RttNom;
+ UINT16 RttPark;
+ UINT16 RttWr;
+ UINT16 MR0;
+ UINT16 MR1;
+ UINT16 MR2;
+ UINT16 MR3;
+ UINT16 MR4;
+ UINT16 MR5;
+ UINT16 MR6[9];
+};
+
+struct baseMargin {
+ INT16 n;
+ INT16 p;
+};
+
+struct rankMargin {
+ struct baseMargin rank[MAX_CHANNEL][MAX_RANK_CH];
+};
+
+typedef struct _DDR_DIMM{
+ BOOLEAN Status;
+ UINT8 mapout;
+ UINT8 DramType; //Byte 2
+ UINT8 ModuleType; //Byte 3
+ UINT8 ExtendModuleType;
+ UINT8 SDRAMCapacity; //Byte 4
+ UINT8 BankNum;
+ UINT8 BGNum; //Byte 4 For DDR4
+ UINT8 RowBits; //Byte 5
+ UINT8 ColBits; //Byte 5
+ UINT8 SpdVdd; //Byte 6
+ UINT8 DramWidth; //Byte 7
+ UINT8 RankNum; //Byte 7
+ UINT8 PrimaryBusWidth; //Byte 8
+ UINT8 ExtensionBusWidth; //Byte 8
+ UINT32 Mtb;
+ UINT32 Ftb;
+ UINT32 minTck;
+ UINT8 MtbDividend;
+ UINT8 MtbDivsor;
+ UINT8 nCL;
+ UINT8 nRCD;
+ UINT8 nRP;
+ UINT8 SPDftb;
+ UINT8 SpdMinTCK;
+ UINT8 SpdMinTCKFtb;
+ UINT8 SpdMaxTCK;
+ UINT8 SpdMinTCL;
+ UINT8 SpdMinTCLFtb;
+ UINT8 SpdMinTWR;
+ UINT8 SpdMinTRCD;
+ UINT8 SpdMinTRCDFtb;
+ UINT8 SpdMinTRRD;
+ UINT8 SpdMinTRRDL;
+ UINT16 SpdMinTRAS;
+ UINT16 SpdMinTRC;
+ UINT16 SpdMinTRCFtb;
+ UINT16 SpdMinTRFC;
+ UINT8 SpdMinTWTR;
+ UINT8 SpdMinTRTP;
+ UINT8 SpdMinTAA;
+ UINT8 SpdMinTAAFtb;
+ UINT8 SpdMinTFAW;
+ UINT8 SpdMinTRP;
+ UINT8 SpdMinTRPFtb;
+ UINT8 SpdMinTCCDL;
+ UINT8 SpdMinTCCDLFtb;
+ UINT8 SpdAddrMap;
+ UINT8 SpdModuleAttr;
+
+ UINT8 SpdModPart[SPD_MODULE_PART]; // Module Part Number
+ UINT8 SpdModPartDDR4[SPD_MODULE_PART_DDR4]; // Module Part Number DDR4
+ UINT16 SpdMMfgId; // Module Mfg Id from SPD
+ UINT16 SpdRMId; // Register Manufacturer Id
+ UINT16 SpdMMDate; // Module Manufacturing Date
+ UINT32 SpdSerialNum;
+ UINT16 DimmSize;
+ UINT16 DimmSpeed;
+ UINT32 RankSize;
+ struct DDR_RANK Rank[MAX_RANK_DIMM];
+}DDR_DIMM;
+
+typedef struct {
+ UINT32 ddrcTiming0;
+ UINT32 ddrcTiming1;
+ UINT32 ddrcTiming2;
+ UINT32 ddrcTiming3;
+ UINT32 ddrcTiming4;
+ UINT32 ddrcTiming5;
+ UINT32 ddrcTiming6;
+ UINT32 ddrcTiming7;
+}DDRC_TIMING;
+
+typedef struct _DDR_Channel{
+ BOOLEAN Status;
+ UINT8 CurrentDimmNum;
+ UINT8 CurrentRankNum;
+ UINT16 RankPresent;
+ UINT8 DramType;
+ UINT8 DramWidth;
+ UINT8 ModuleType;
+ UINT32 MemSize;
+ UINT32 CLSupport;
+ UINT32 minTck;
+ UINT32 nCL;
+ UINT32 nWR;
+ UINT32 nRCD;
+ UINT32 nRRD;
+ UINT32 nRRDL;
+ UINT32 nRAS;
+ UINT32 nRC;
+ UINT32 nRFC;
+ UINT32 nWTR;
+ UINT32 nRTP;
+ UINT32 nAA;
+ UINT32 nFAW;
+ UINT32 nRP;
+ UINT32 nCCDL;
+ UINT8 cwl; //tWL?
+ UINT8 pl; //parity latency
+ UINT8 wr_pre_2t_en;
+ UINT8 rd_pre_2t_en;
+ UINT8 cmd_2t_en;
+ UINT8 parity_en;
+ UINT8 wr_dbi_en;
+ UINT8 wr_dm_en;
+ UINT8 ddr4_crc_en;
+ UINT16 emrs0;
+ UINT16 emrs1;
+ UINT16 emrs1Wr;
+ UINT16 emrs2;
+ UINT16 emrs3;
+ UINT16 emrs4;
+ UINT16 emrs5;
+ UINT16 emrs5Wr;
+ UINT16 emrs6;
+ UINT16 emrs7;
+ UINT8 phy_rddata_set;
+ UINT8 phyif_tim_rdcs;
+ UINT8 phyif_tim_rden;
+ UINT8 phyif_tim_wden;
+ UINT8 phyif_tim_wdda;
+ UINT8 phyif_tim_wdcs;
+ UINT8 per_cs_training_en;
+ UINT32 phyRdDataEnIeDly;
+ UINT32 phyPadCalConfig;
+ UINT32 phyDqsFailRiseDelay;
+ UINT32 ddrcCfgDfiLat0;
+ UINT32 ddrcCfgDfiLat1;
+ UINT32 parityLatency;
+ DDRC_TIMING ddrcTiming;
+ DDR_DIMM Dimm[MAX_DIMM];
+}DDR_CHANNEL;
+
+typedef struct _NVRAM_RANK{
+ UINT16 MR6[9];
+}NVRAM_RANK;
+
+typedef struct _NVRAM_DIMM{
+ NVRAM_RANK Rank[MAX_RANK_DIMM];
+}NVRAM_DIMM;
+
+
+typedef struct _NVRAM_CHANNEL{
+ NVRAM_DIMM Dimm[MAX_DIMM];
+ UINT32 DDRC_CFG_ECC;
+ UINT32 DDRC_CFG_WORKMODE;
+ UINT32 DDRC_CFG_WORKMODE1;
+ UINT32 DDRC_CFG_WORKMODE2;
+ UINT32 DDRC_CFG_DDRMODE;
+ UINT32 DDRC_CFG_DIMM;
+ UINT32 DDRC_CFG_RNKVOL_0;
+ UINT32 DDRC_CFG_RNKVOL_1;
+ UINT32 DDRC_CFG_RNKVOL_2;
+ UINT32 DDRC_CFG_RNKVOL_3;
+ UINT32 DDRC_CFG_RNKVOL_4;
+ UINT32 DDRC_CFG_RNKVOL_5;
+ UINT32 DDRC_CFG_RNKVOL_6;
+ UINT32 DDRC_CFG_RNKVOL_7;
+ UINT32 DDRC_CFG_RNKVOL_8;
+ UINT32 DDRC_CFG_RNKVOL_9;
+ UINT32 DDRC_CFG_RNKVOL_10;
+ UINT32 DDRC_CFG_RNKVOL_11;
+ UINT32 DDRC_CFG_ODT_0;
+ UINT32 DDRC_CFG_ODT_1;
+ UINT32 DDRC_CFG_ODT_2;
+ UINT32 DDRC_CFG_ODT_3;
+ UINT32 DDRC_CFG_ODT_4;
+ UINT32 DDRC_CFG_ODT_5;
+ UINT32 DDRC_CFG_ODT_6;
+ UINT32 DDRC_CFG_ODT_7;
+ UINT32 DDRC_CFG_ODT_8;
+ UINT32 DDRC_CFG_ODT_9;
+ UINT32 DDRC_CFG_ODT_10;
+ UINT32 DDRC_CFG_ODT_11;
+ UINT32 DDRC_CFG_TIMING0;
+ UINT32 DDRC_CFG_TIMING1;
+ UINT32 DDRC_CFG_TIMING2;
+ UINT32 DDRC_CFG_TIMING3;
+ UINT32 DDRC_CFG_TIMING4;
+ UINT32 DDRC_CFG_TIMING5;
+ UINT32 DDRC_CFG_TIMING6;
+ UINT32 DDRC_CFG_TIMING7;
+ UINT32 DDRC_CFG_DFI_LAT0;
+ UINT32 DDRC_CFG_DFI_LAT1;
+ UINT32 DDRC_CFG_DDRPHY;
+ UINT32 Config[24];
+ BOOLEAN Status;
+}NVRAM_CHANNEL;
+
+typedef struct _NVRAM{
+ UINT32 NvramCrc;
+ NVRAM_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL];
+ UINT32 DdrFreqIdx;
+
+}NVRAM;
+
+typedef struct _MEMORY{
+ UINT8 Config0;
+ UINT8 marginTest;
+ UINT8 Config1[5];
+ UINT32 Config2;
+}MEMORY;
+
+typedef struct _GBL_DATA
+{
+ DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL];
+ UINT8 DramType;
+ UINT8 CurrentDimmNum;
+ UINT8 CurrentRankNum;
+ UINT8 MaxSPCNum;
+ UINT32 Freq;
+ UINT32 SpdTckMtb;
+ UINT32 SpdTckFtb;
+ UINT32 SpdTck;
+ UINT32 Tck;
+ UINT32 DdrFreqIdx;
+ UINT32 MemSize;
+ UINT32 EccEn;
+
+ BOOLEAN SetupExist;
+ UINT8 warmReset;
+ UINT8 needColdReset;
+
+ UINT8 cl;
+ UINT8 cwl;
+ UINT8 pl;
+ UINT8 wr_pre_2t_en;
+ UINT8 rd_pre_2t_en;
+ UINT8 cmd_2t_en;
+ UINT8 ddr4_parity_en;
+ UINT8 wr_dbi_en;
+ UINT8 wr_dm_en;
+ UINT8 ddr4_crc_en;
+ UINT16 emrs0;
+ UINT16 emrs1;
+ UINT16 emrs2;
+ UINT16 emrs3;
+ UINT16 emrs4;
+ UINT16 emrs5;
+ UINT16 emrs6;
+ UINT16 emrs7;
+ UINT8 phy_rddata_set;
+ UINT8 phyif_tim_rdcs;
+ UINT8 phyif_tim_rden;
+ UINT8 phyif_tim_wden;
+ UINT8 phyif_tim_wdda;
+ UINT8 phyif_tim_wdcs;
+ UINT8 dimm_trtr;
+ UINT8 dimm_twtw;
+ UINT8 rnk_trtr;
+ UINT8 rnk_twtw;
+ UINT8 rnk_trtw;
+ UINT8 rnk_twtr;
+ UINT8 per_cs_training_en;
+ UINT8 scale;
+ UINT8 ddrFreq;
+ UINT8 debugNeed;
+ UINT8 ddr3OdtEnable;
+ double fprd;
+ BOOLEAN chipIsEc;
+ NVRAM nvram;
+ MEMORY mem;
+
+}GBL_DATA, *pGBL_DATA;
+
+typedef union {
+ struct {
+ UINT16 freqIndex:4; //Frequency Index;
+ UINT16 slot0:4; //Channel slot0 for DIMM
+ UINT16 slot1:4; //Channel slot1 for DIMM
+ UINT16 slot2:4; //Channel slot2 for DIMM
+ }Bits;
+ UINT16 Data;
+}ODT_VALUE_INDEX;
+
+typedef union {
+ struct {
+ UINT8 RTTNom:3;
+ UINT8 reserved_3:1;
+ UINT8 RTTWr:2;
+ UINT8 reserved_6:2;
+ }Bits;
+ UINT8 Data;
+}ODT_RTT_VALUE_DDR3;
+
+typedef union {
+ struct {
+ UINT8 RTTNom:3;
+ UINT8 RTTPark:3;
+ UINT8 RTTWr:2;
+ }Bits;
+ UINT8 Data;
+}ODT_RTT_VALUE_DDR4;
+
+typedef union {
+ struct {
+ UINT16 tarDimm:2; // target DIMM
+ UINT16 tarRank:2; // target Rank
+ UINT16 slot0:4; // Channel slot0 for DIMM
+ UINT16 slot1:4; // Channel slot1 for DIMM
+ UINT16 slot2:4; // Channel slot2 for DIMM
+ }Bits;
+ UINT16 Data;
+}ODT_ACTIVE_INDEX;
+
+struct ODT_VALUE_STRUCT_DDR3 {
+ UINT16 config; // ODT_VALUE_INDEX
+ UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM]; // ODT_VALUE_RTT_DDR3
+};
+
+struct ODT_VALUE_STRUCT_DDR4 {
+ UINT16 config;
+ UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM];
+};
+
+struct ODT_ACTIVE_STRUCT {
+ UINT16 config; // ODT config index
+ UINT16 actBits[2]; // WR :Bits[3;0] = D0_R[3:0] Bits[7:4] = D1_R[3:0] Bits[11:8] = D2_R[3:0]
+};
+
+// JEDEC manufacturer IDs from JEP-106
+#define MFGID_AENEON 0x5705
+#define MFGID_QIMONDA 0x5105
+#define MFGID_NEC 0x1000
+#define MFGID_IDT 0xB300
+#define MFGID_TI 0x9700
+#define MFGID_HYNIX 0xAD00
+#define MFGID_MICRON 0x2C00
+#define MFGID_INFINEON 0xC100
+#define MFGID_SAMSUNG 0xCE00
+#define MFGID_TEK 0x3D00
+#define MFGID_KINGSTON 0x9801
+#define MFGID_ELPIDA 0xFE02
+#define MFGID_SMART 0x9401
+#define MFGID_AGILENT 0xC802
+#define MFGID_NANYA 0x0B03
+#define MFGID_INPHI 0xB304
+#define MFGID_MONTAGE 0x3206
+#define MFGID_RAMAXEL 0x4304
+
+//
+// DDR3 frequencies 800 - 2667
+// DDR4 frequencies 1333 - 3200
+//
+#define DDR_800 0 // tCK(ns)=2.5
+#define DDR_1000 1 // tCK(ns)=2.0
+#define DDR_1066 2 // tCK(ns)=1.875
+#define DDR_1200 3 // tCK(ns)=1.667
+#define DDR_1333 4 // tCK(ns)=1.5
+#define DDR_1400 5 // tCK(ns)=1.429
+#define DDR_1600 6 // tCK(ns)=1.25
+#define DDR_1800 7 // tCK(ns)=1.11
+#define DDR_1866 8 // tCK(ns)=1.07
+#define DDR_2000 9 // tCK(ns)=1.0
+#define DDR_2133 10 // tCK(ns)=0.9375
+#define DDR_2200 11 // tCK(ns)=0.909
+#define DDR_2400 12 // tCK(ns)=0.833
+#define DDR_2600 13 // tCK(ns)=0.769
+#define DDR_2666 14 // tCK(ns)=0.750
+#define DDR_2800 15 // tCK(ns)=0.714
+#define DDR_2933 16 // tCK(ns)=0.682
+#define DDR_3000 17 // tCK(ns)=0.667
+#define DDR_3200 18 // tCK(ns)=0.625
+#define DDR_MAX (DDR_3200)
+
+#define FREQUENCY_MTB_OFFSET 1000000
+#define FREQUENCY_FTB_OFFSET 1000
+
+//
+#define DDR_800_TCK_MIN 25000
+#define DDR_1000_TCK_MIN 20000
+#define DDR_1067_TCK_MIN 18750
+#define DDR_1200_TCK_MIN 16670
+#define DDR_1333_TCK_MIN 15000
+#define DDR_1400_TCK_MIN 14290
+#define DDR_1600_TCK_MIN 12500
+#define DDR_1800_TCK_MIN 11100
+#define DDR_1867_TCK_MIN 10710
+#define DDR_2000_TCK_MIN 10000
+#define DDR_2133_TCK_MIN 9380
+#define DDR_2200_TCK_MIN 9090
+#define DDR_2400_TCK_MIN 8330
+#define DDR_2600_TCK_MIN 7690
+#define DDR_2667_TCK_MIN 7500
+#define DDR_2800_TCK_MIN 7140
+#define DDR_2933_TCK_MIN 6820
+#define DDR_3000_TCK_MIN 6670
+#define DDR_3200_TCK_MIN 6250
+
+
+//
+// Serial Presence Detect bytes (JEDEC revision 1.0)
+//
+#define SPD_SIZE 0 // Bytes used, Device size, CRC coverage
+#define SPD_REVISION 1 // SPD Encoding Revision
+#define SPD_KEY_BYTE 2 // DRAM Device Type
+ #define SPD_TYPE_DDR3 0x0B // DDR3 SDRAM
+ #define SPD_TYPE_DDR4 0x0C // DDR4 SDRAM
+#define SPD_KEY_BYTE2 3 // Module Type and Thickness (RDIMM or UDIMM)
+ #define SPD_RDIMM 1 // Module type is RDIMM
+ #define SPD_UDIMM 2 // Module type is UDIMM
+ #define SPD_SODIMM 3 // Module type is SODIMM
+ #define SPD_MICRO_DIMM 4 // Module type is Micro-DIMM
+ #define SPD_LRDIMM_DDR4 4 // Module type is LRDIMM (DDR4)
+ #define SPD_MINI_RDIMM 5 // Module type is Mini-RDIMM
+ #define SPD_MINI_UDIMM 6 // Module type is Mini-UDIMM
+ #define SPD_MINI_CDIMM 7 // Module type is Mini-CDIMM
+ #define SPD_ECC_SO_UDIMM 9 // Module type is 72b-SO-UDIMM
+ #define SPD_ECC_SO_RDIMM 8 // Module type is 72b-SO-RDIMM
+ #define SPD_ECC_SO_CDIMM 10 // Module type is 72b-SO-CDIMM
+ #define SPD_LRDIMM 11 // Module type is LRDIMM
+ #define SPD_UDIMM_ECC 18 // Module type is UDIMM-ECC
+#define SPD_SDRAM_BANKS 4 // SDRAM Density and number of internal banks
+ #define SPD_1Gb 2 // Total SDRAM Capacity 1 Gigabits
+ #define SPD_2Gb 3 // Total SDRAM Capacity 2 Gigabits
+ #define SPD_4Gb 4 // Total SDRAM Capacity 4 Gigabits
+ #define SPD_8Gb 5 // Total SDRAM Capacity 8 Gigabits
+ #define SPD_16Gb 6 // Total SDRAM Capacity 16 Gigabits
+ #define SPD_32Gb 7 // Total SDRAM Capacity 32 Gigabits
+#define SPD_SDRAM_ADDR 5 // Number of Row and Column address bits
+ #define SPD_ROW_12 0 // 12 row bits
+ #define SPD_ROW_13 1 // 13 row bits
+ #define SPD_ROW_14 2 // 14 row bits
+ #define SPD_ROW_15 3 // 15 row bits
+ #define SPD_ROW_16 4 // 16 row bits
+ #define SPD_ROW_17 5 // 17 row bits
+ #define SPD_ROW_18 6 // 18 row bits
+ #define SPD_COL_9 0 // 9 colum bits
+ #define SPD_COL_10 1 // 10 colum bits
+ #define SPD_COL_11 2 // 11 colum bits
+ #define SPD_COL_12 3 // 12 colum bits
+#define SPD_VDD_SUPPORT 6 // Vdd DIMM supports
+ #define SPD_VDD_150 0 // Module Supports 1.50V
+ #define SPD_VDD_135 BIT1 // Module Supports 1.35V
+ #define SPD_VDD_125 BIT2 // Module Supports 1.25V
+#define SPD_MODULE_ORG_DDR3 7 // Number of Ranks and SDRAM device width
+#define SPD_MODULE_ORG_DDR4 12 // DDR4 Module Organization
+ #define DEVICE_WIDTH_X4 0 // SDRAM device width = 4 bits
+ #define DEVICE_WIDTH_X8 1 // SDRAM device width = 8 bits
+ #define DEVICE_WIDTH_X16 2 // SDRAM device width = 16 bits
+ #define SPD_NUM_RANKS_1 0
+ #define SPD_NUM_RANKS_2 1
+ #define SPD_NUM_RANKS_4 3
+ #define SPD_NUM_RANKS_8 4
+#define SPD_MEM_BUS_WID 8 // Width of SDRAM memory bus
+#define SPD_FTB 9 // Timebase for fine grain timing calculations
+#define SPD_MTB_DIVEND 10 // Medium Time Base Dividend
+#define SPD_MTB_DIVISOR 11 // Medium Time Base Divisor
+#define SPD_MIN_TCK 12 // Minimum cycle time (at max CL)
+ #define SPD_TCKMIN_800 20 // tCK(MTB)=20, tCK(ns)=2.5
+ #define SPD_TCKMIN_1067 15 // tCK(MTB)=15, tCK(ns)=1.875
+ #define SPD_TCKMIN_1333 12 // tCK(MTB)=12, tCK(ns)=1.5
+ #define SPD_TCKMIN_1600 10 // tCK(MTB)=10, tCK(ns)=1.25
+ #define SPD_TCKMIN_1867 9 // tCK(MTB)=9, tCK(ns)=1.07
+ #define SPD_TCKMIN_2133 8 // tCK(MTB)=8, tCK(ns)=0.9375
+ #define SPD_TCKMIN_2400 7 // tCK(MTB)=7, tCK(ns)=.833
+#define SPD_CAS_LT_SUP_LSB 14 // CAS Latencies Supported, Least Significant Byte
+#define SPD_CAS_LT_SUP_MSB 15 // CAS Latencies Supported, Most Significant Byte
+#define SPD_MIN_TAA 16 // Minimum CAS Latency Time (tAAmin)
+#define SPD_MIN_TWR 17 // Minimum Write Recovery Time
+#define SPD_MIN_TRCD 18 // Minimum RAS to CAS delay
+#define SPD_MIN_TRRD 19 // Minimum Row active to row active delay
+#define SPD_MIN_TRP 20 // Minimum Row Precharge time
+#define SPD_EXT_TRC_TRAS 21 // Upper nibbles for min tRAS and tRC
+#define SPD_MIN_TRAS 22 // Minimum Active to Precharge time
+#define SPD_MIN_TRC 23 // Minimum Active to Active/Refresh time
+#define SPD_MIN_TRFC_LSB 24 // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC_MSB 25 // Minimum Refresh Recovery time most-significant byte
+#define SPD_MIN_TWTR 26 // Minimum Internal Write to Read command delay
+#define SPD_MIN_TRTP 27 // Minimum Internal Read to Precharge command delay
+#define SPD_UN_TFAW 28 // Upper Nibble for tFAW
+#define SPD_MIN_TFAW 29 // Minimum Four Activate Window Delay Time (tFAWmin)
+#define SPD_OD_SUP 30 // SDRAM Output Drivers Supported
+#define SPD_RFSH_OPT 31 // SDRAM Refresh Options
+ #define ETR BIT0 // Bit location for Extended Temp Range
+ #define ETRR BIT1 // Bit location for Extended Temp Refresh Rate
+ #define ASR BIT2 // Bit location for Automatic Self Refresh
+ #define ODTS BIT3 // Bit location for On-die Thermal Sensor
+#define SPD_DIMM_TS 32 // Module Temperature Sensor
+#define SPD_SDRAM_TYPE 33 // SDRAM device type
+#define SPD_FTB_TCK 34 // Fine Offset for SDRAM tCK
+#define SPD_FTB_TAA 35 // Fine Offset for SDRAM tAA
+#define SPD_FTB_TRCD 36 // Fine Offset for SDRAM tRCD
+#define SPD_FTB_TRP 37 // Fine Offset for SDRAM tRP
+#define SPD_FTB_TRC 38 // Fine Offset for SDRAM tRC
+#define SPD_OPT_FEAT 41 // SDRAM Optional Features
+ #define SPD_PTRR BIT7 // Indicates if the DIMM is pTRR compliant
+
+ // UDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 2, 3, 4, 6, or 8
+
+#define SPD_ADDR_MAP_FECTD 63 // Address Mapping from Edge Connector to DRAM
+
+ // RDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 1, 5, or 9
+
+#define SPD_RDIMM_ATTR 63 // RDIMM module attributes
+#define SPD_DIMM_HS 64 // Module Heat Spreader Solution
+#define SPD_REG_VEN_LSB 65 // Register Vendor ID LSB
+#define SPD_REG_VEN_MSB 66 // Register Vendor ID MSB
+#define SPD_REG_REV 67 // Register Revision
+#define SPD_CNTL_0 69 // Register Control Word 0 & 1
+#define SPD_CNTL_1 70 // Register Control Word 2 & 3
+#define SPD_CNTL_2 71 // Register Control Word 4 & 5
+#define SPD_CNTL_3 72 // Register Control Word 6 & 7 (reserved)
+#define SPD_CNTL_4 73 // Register Control Word 8 & 9 (reserved)
+#define SPD_CNTL_5 74 // Register Control Word 10 & 11 (reserved)
+#define SPD_CNTL_6 75 // Register Control Word 12 & 13 (reserved)
+#define SPD_CNTL_7 76 // Register Control Word 14 & 15 (reserved)
+
+ // LRDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 0xB
+ // Based on DDR3 SPD 1.0 Document Release 2.1 draft, dated May 27, 2011
+
+#define SPD_LRDIMM_ATTR 63 // LRDIMM module attributes
+#define SPD_LRBUF_REV 64 // LR Buffer Revision
+#define SPD_LRBUF_VEN_LSB 65 // LR Buffer Vendor ID LSB
+#define SPD_LRBUF_VEN_MSB 66 // LR Buffer Vendor ID MSB
+#define SPD_LR_F0_RC2_3 67 // LR Buffer Function 0, Control Word 2 & 3
+#define SPD_LR_F0_RC4_5 68 // LR Buffer Function 0, Control Word 4 & 5
+#define SPD_LR_F1_RC8_11 69 // LR Buffer Function 1, Control Word 8 & 11
+#define SPD_LR_F1_RC12_13 70 // LR Buffer Function 1, Control Word 12 & 13
+#define SPD_LR_F1_RC14_15 71 // LR Buffer Function 1, Control Word 14 & 15
+
+ // Speed bin 0 = 800 & 1066
+#define SPD_LR_SB0_MDQ_DS_ODT 72 // LR Buffer Function 3, Control Word 8 & 9
+#define SPD_LR_SB0_DR01_QODT_ACT 73 // LR Buffer Function 3 & 4, Control Word 10 & 11
+#define SPD_LR_SB0_DR23_QODT_ACT 74 // LR Buffer Function 5 & 6, Control Word 10 & 11
+#define SPD_LR_SB0_DR45_QODT_ACT 75 // LR Buffer Function 7 & 8, Control Word 10 & 11
+#define SPD_LR_SB0_DR67_QODT_ACT 76 // LR Buffer Function 9 & 10, Control Word 10 & 11
+#define SPD_LR_SB0_MR1_2_RTT 77 // LR Buffer SMBus offsets 0xC0 - 0xC7
+
+ // Speed bin 1 = 1333 & 1600
+#define SPD_LR_SB1_MDQ_DS_ODT 78 // LR Buffer Function 3, Control Word 8 & 9
+#define SPD_LR_SB1_DR01_QODT_ACT 79 // LR Buffer Function 3 & 4, Control Word 10 & 11
+#define SPD_LR_SB1_DR23_QODT_ACT 80 // LR Buffer Function 5 & 6, Control Word 10 & 11
+#define SPD_LR_SB1_DR45_QODT_ACT 81 // LR Buffer Function 7 & 8, Control Word 10 & 11
+#define SPD_LR_SB1_DR67_QODT_ACT 82 // LR Buffer Function 9 & 10, Control Word 10 & 11
+#define SPD_LR_SB1_MR1_2_RTT 83 // LR Buffer SMBus offsets 0xC0 - 0xC7
+
+ // Speed bin 2 = 1866 & 2133
+#define SPD_LR_SB2_MDQ_DS_ODT 84 // LR Buffer Function 3, Control Word 8 & 9
+#define SPD_LR_SB2_DR01_QODT_ACT 85 // LR Buffer Function 3 & 4, Control Word 10 & 11
+#define SPD_LR_SB2_DR23_QODT_ACT 86 // LR Buffer Function 5 & 6, Control Word 10 & 11
+#define SPD_LR_SB2_DR45_QODT_ACT 87 // LR Buffer Function 7 & 8, Control Word 10 & 11
+#define SPD_LR_SB2_DR67_QODT_ACT 88 // LR Buffer Function 9 & 10, Control Word 10 & 11
+#define SPD_LR_SB2_MR1_2_RTT 89 // LR Buffer SMBus offsets 0xC0 - 0xC7
+
+#define SPD_LR_150_MIN_MOD_DELAY 90 // LR DIMM minimum DQ Read propagation delay at 1.5V
+#define SPD_LR_150_MAX_MOD_DELAY 91 // LR DIMM maximum DQ Read propagation delay at 1.5V
+#define SPD_LR_135_MIN_MOD_DELAY 92 // LR DIMM minimum DQ Read propagation delay at 1.35V
+#define SPD_LR_135_MAX_MOD_DELAY 93 // LR DIMM maximum DQ Read propagation delay at 1.35V
+#define SPD_LR_12x_MIN_MOD_DELAY 94 // LR DIMM minimum DQ Read propagation delay at 1.2xV
+#define SPD_LR_12x_MAX_MOD_DELAY 95 // LR DIMM maximum DQ Read propagation delay at 1.2xV
+
+#define SPD_LR_PERS_BYTE_0 102 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_1 103 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_2 104 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_3 105 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_4 106 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_5 107 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_6 108 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_7 109 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_8 110 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_9 111 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_10 112 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_11 113 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_12 114 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_13 115 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_14 116 // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTES_TOTAL 15 // LR DIMM Total number of Personality Bytes
+
+ // End module specific section
+
+#define SPD_MMID_LSB 117 // Module Manufacturer ID Code, Least Significant Byte
+#define SPD_MMID_MSB 118 // Module Manufacturer ID Code, Mostst Significant Byte
+#define SPD_MM_LOC 119 // Module Manufacturing Location
+#define SPD_MM_DATE 120 // Module Manufacturing Date 120-121
+#define SPD_MODULE_SN 122 // Module Serial Number 122-125
+#define SPD_CRC_LSB 126 // LSB of 16-bit CRC
+#define SPD_CRC_MSB 127 // MSB of 16-bit CRC
+
+#define SPD_MODULE_PN 128 // Module Part Number 128-145
+#define SPD_MODULE_RC 146 // Module Revision Code 146-147
+#define SPD_DRAM_MIDC_LSB 148 // DRAM Manufacturer ID Code, Least Significant Byte
+#define SPD_DRAM_MIDC_MSB 149 // DRAM Manufacturer ID Code, Most Significant Byte
+#ifdef MEM_NVDIMM_EN
+#define SPD_NVDIMM_ID_N 174 // If NVDIMM value will be 'N'
+#define SPD_NVDIMM_ID_V 175 // If NVDIMM value will be 'V'
+#endif //MEM_NVDIMM_EN
+#define SPD_BYTE_200 200 // Fixed value 0xBE
+
+ //
+ // DDR4 Specific Bytes
+ //
+#define SPD_SDRAM_TYPE_DDR4 6 // SDRAM Device Type (DDR4)
+#define SPD_OPT_FEAT_DDR4 7 // SDRAM Optional Features (DDR4)
+ #define SPD_MAC_MASK BIT0 | BIT1 | BIT2 // Mask for Maximum Active Count field
+ #define SPD_TRR_IMMUNE BIT3 // Indicates this DIMM does not require DRAM Maintenance
+#define SPD_RFSH_OPT_DDR4 8 // SDRAM Refresh Options (DDR4)
+#define SPD_VDD_DDR4 11 // Vdd DIMM supports (DDR4)
+ #define SPD_VDD_120 3 // Module operable and endurant 1.20V
+#define SPD_MODULE_ORG_DDR4 12 // Number of Ranks and SDRAM device width (DDR4)
+#define SPD_MEM_BUS_WID_DDR4 13 // Width of SDRAM memory bus
+#define SPD_DIMM_TS_DDR4 14 // Module Thermal Sensor
+#define SPD_TB_DDR4 17 // Timebase [3:2] MTB, [1:0] FTB
+#define SPD_MIN_TCK_DDR4 18 // Minimum cycle time
+ #define SPD_TCKMIN_DDR4_1600 10 // tCK(MTB)=10, tCK(ns)=1.25
+ #define SPD_TCKMIN_DDR4_1866 9 // tCK(MTB)=9, tCK(ns)=1.071
+ #define SPD_TCKMIN_DDR4_2133 8 // tCK(MTB)=8, tCK(ns)=.938
+ #define SPD_TCKMIN_DDR4_2400 7 // tCK(MTB)=7, tCK(ns)=.833
+#define SPD_MAX_TCK_DDR4 19 // Maximum cycle time
+#define SPD_CAS_LT_SUP_1_DDR4 20 // CAS Latencies Supported, first byte
+#define SPD_CAS_LT_SUP_2_DDR4 21 // CAS Latencies Supported, second byte
+#define SPD_CAS_LT_SUP_3_DDR4 22 // CAS Latencies Supported, third byte
+#define SPD_CAS_LT_SUP_4_DDR4 23 // CAS Latencies Supported, fourth byte
+#define SPD_MIN_TAA_DDR4 24 // Minimum CAS Latency Time (tAAmin)
+#define SPD_MIN_TRCD_DDR4 25 // Minimum RAS to CAS delay
+#define SPD_MIN_TRP_DDR4 26 // Minimum Row Precharge time
+#define SPD_EXT_TRC_TRAS_DDR4 27 // Upper nibbles for min tRAS and tRC
+#define SPD_MIN_TRAS_DDR4 28 // Minimum Active to Precharge time
+#define SPD_MIN_TRC_DDR4 29 // Minimum Active to Active/Refresh time
+#define SPD_MIN_TRFC1_LSB_DDR4 30 // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC1_MSB_DDR4 31 // Minimum Refresh Recovery time most-significant byte
+#define SPD_MIN_TRFC2_LSB_DDR4 32 // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC2_MSB_DDR4 33 // Minimum Refresh Recovery time most-significant byte
+#define SPD_MIN_TRFC3_LSB_DDR4 34 // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC3_MSB_DDR4 35 // Minimum Refresh Recovery time most-significant byte
+#define SPD_TFAW_UPPER_DDR4 36 // Upper nibble for tFAW
+#define SPD_MIN_TFAW_DDR4 37 // Minimum For Active Window Delay Time (tFAW)
+#define SPD_MIN_TRRDS_DDR4 38 // Minimum Active to Active Delay Time tRRD_S Different Bank Group
+#define SPD_MIN_TRRDL_DDR4 39 // Minimum Active to Active Delay Time tRRD_L Same Bank Group
+#define SPD_MIN_TCCDL_DDR4 40 // Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
+#define SPD_FTB_TCCDL_DDR4 117 // Fine offset for tCCD_L
+#define SPD_FTB_TRRDL_DDR4 118 // Fine offset for tRRD_L
+#define SPD_FTB_TRRDS_DDR4 119 // Fine offset for tRRD_S
+#define SPD_FTB_TRC_DDR4 120 // Fine offset for TRC
+#define SPD_FTB_TRP_DDR4 121 // Fine offset for TRP
+#define SPD_FTB_TRCD_DDR4 122 // Fine offset for TRCD
+#define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA
+#define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK
+#define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK
+
+#define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte
+#define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte
+#define SPD_MM_LOC_DDR4 322 // Module Manufacturing Location
+#define SPD_MM_DATE_DDR4 323 // Module Manufacturing Date 323-324
+#define SPD_MODULE_SN_DDR4 325 // Module Serial Number 325-328
+#define SPD_MODULE_PN_DDR4 329 // Module Part Number 329-348
+#define SPD_MODULE_RC_DDR4 349 // Module Revision Code
+#define SPD_DRAM_MIDC_LSB_DDR4 350 // DRAM Manufacturer ID Code, Least Significant Byte
+#define SPD_DRAM_MIDC_MSB_DDR4 351 // DRAM Manufacturer ID Code, Most Significant Byte
+#define SPD_DRAM_REV_DDR4 352 // DRAM Revision ID
+#define SPD_CRC_LSB_DDR4 382 // LSB of 16-bit CRC
+#define SPD_CRC_MSB_DDR4 383 // MSB of 16-bit CRC
+
+ // Begin DDR4 module specific section
+#define SPD_MODULE_NH_DDR4 128 // Module Nominal Height
+#define SPD_MODULE_MT_DDR4 129 // Module Maximum Thickness
+#define SPD_REF_RAW_CARD_DDR4 130 // Reference Raw Card Used
+
+ // UDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 2
+#define SPD_ADDR_MAP_FECTD_DDR4 131 // Address Mapping from Edge Connector to DRAM
+
+ // RDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 1
+#define SPD_RDIMM_ATTR_DDR4 131 // RDIMM module attributes
+#define SPD_DIMM_HS_DDR4 132 // Module Heat Spreader Solution
+#define SPD_REG_VEN_LSB_DDR4 133 // Register Vendor ID LSB
+#define SPD_REG_VEN_MSB_DDR4 134 // Register Vendor ID MSB
+#define SPD_REG_REV_DDR4 135 // Register Revision
+#define SPD_ADD_MAPPING_DDR4 136 // Address mapping from Reg to DRAM
+#define SPD_REG_OD_CTL_DDR4 137 // Register Output Drive Strength for Control
+#define SPD_REG_OD_CK_DDR4 138 // Register Output Drive Strength for Clock
+
+ // LRDIMM specific bytes
+ // Applicable when Module Type (key byte 3) = 0x4
+#define SPD_LRDIMM_ATTR_DDR4 131 // LRDIMM module attributes
+#define SPD_LRBUF_HS_DDR4 132 // LR Buffer Heat Spreader Solution
+#define SPD_LRBUF_VEN_LSB_DDR4 133 // LR Buffer Vendor ID LSB
+#define SPD_LRBUF_VEN_MSB_DDR4 134 // LR Buffer Vendor ID MSB
+#define SPD_LRBUF_REV_DDR4 135 // LR Buffer Register Revision
+#define SPD_LRBUF_DB_REV_DDR4 139 // LR Buffer Data Buffer Revision
+#define SPD_LRBUF_DRAM_VREFDQ_R0_DDR4 140 // LR Buffer DRAM VrefDQ for Package Rank 0
+#define SPD_LRBUF_DRAM_VREFDQ_R1_DDR4 141 // LR Buffer DRAM VrefDQ for Package Rank 1
+#define SPD_LRBUF_DRAM_VREFDQ_R2_DDR4 142 // LR Buffer DRAM VrefDQ for Package Rank 2
+#define SPD_LRBUF_DRAM_VREFDQ_R3_DDR4 143 // LR Buffer DRAM VrefDQ for Package Rank 3
+#define SPD_LRBUF_DB_VREFDQ_DDR4 144 // LR Data Buffer VrefDQ for DRAM Interface
+#define SPD_LRBUF_DB_DS_RTT_LE1866_DDR4 145 // LR Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
+#define SPD_LRBUF_DB_DS_RTT_GT1866_LE2400_DDR4 146 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 1866 and <= 2400
+#define SPD_LRBUF_DB_DS_RTT_GT2400_LE3200_DDR4 147 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 2400 and <= 3200
+#define SPD_LRBUF_DRAM_DS_DDR4 148 // LR Buffer DRAM Drive Strength (for data rates <= 1866, 1866 < data rate <= 2400, and 2400 < data rate <= 3200)
+#define SPD_LRBUF_DRAM_ODT_WR_NOM_LE1866_DDR4 149 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
+#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT1866_LE2400_DDR4 150 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <= 2400
+#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT2400_LE3200_DDR4 151 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <= 3200
+#define SPD_LRBUF_DRAM_ODT_PARK_LE1866_DDR4 152 // LR Buffer DRAM ODT (RTT_PARK) for data rate <= 1866
+#define SPD_LRBUF_DRAM_ODT_PARK_GT1866_LE2400_DDR4 153 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 1866 and <= 2400
+#define SPD_LRBUF_DRAM_ODT_PARK_GT2400_LE3200_DDR4 154 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 2400 and <= 3200
+
+ //
+ // End DDR4 Specific Bytes
+ //
+#define BANK0 0
+#define BANK1 BIT0
+#define BANK2 BIT1
+#define BANK3 BIT0 + BIT1
+#define BANK4 BIT2
+#define BANK5 BIT2 + BIT0
+#define BANK6 BIT2 + BIT1
+#define BANK7 BIT2 + BIT1 + BIT0
+
+#define RDIMM_RC00 0x00
+#define RDIMM_RC01 0x01
+#define RDIMM_RC02 0x02
+#define RDIMM_RC03 0x03
+#define RDIMM_RC04 0x04
+#define RDIMM_RC05 0x05
+#define RDIMM_RC08 0x08
+#define RDIMM_RC09 0x09
+#define RDIMM_RC0A 0x0A
+#define RDIMM_RC0B 0x0B
+#define RDIMM_RC0C 0x0C
+#define RDIMM_RC0D 0x0D
+#define RDIMM_RC0E 0x0E
+#define RDIMM_RC0F 0x0F
+#define RDIMM_RC1x 0x10
+#define RDIMM_RC2x 0x20
+#define RDIMM_RC3x 0x30
+#define RDIMM_RC4x 0x40
+#define RDIMM_RC5x 0x50
+#define RDIMM_RC6x 0x60
+#define RDIMM_RC7x 0x70
+#define RDIMM_RC8x 0x80
+#define RDIMM_RC9x 0x90
+#define RDIMM_RCAx 0xA0
+
+#define LRDIMM_BC00 0x00
+#define LRDIMM_BC01 0x01
+#define LRDIMM_BC02 0x02
+#define LRDIMM_BC03 0x03
+#define LRDIMM_BC04 0x04
+#define LRDIMM_BC05 0x05
+#define LRDIMM_BC06 0x06
+#define LRDIMM_BC07 0x07
+#define LRDIMM_BC08 0x08
+#define LRDIMM_BC09 0x09
+#define LRDIMM_BC0A 0x0A
+#define LRDIMM_BC0B 0x0B
+#define LRDIMM_BC0C 0x0C
+#define LRDIMM_BC0E 0x0E
+
+#define LRDIMM_BC0x 0x00
+#define LRDIMM_BC1x 0x10
+#define LRDIMM_BC2x 0x20
+#define LRDIMM_BC3x 0x30
+#define LRDIMM_BC4x 0x40
+#define LRDIMM_BC5x 0x50
+#define LRDIMM_BC6x 0x60
+#define LRDIMM_BC7x 0x70
+#define LRDIMM_BC8x 0x80
+#define LRDIMM_BC9x 0x90
+#define LRDIMM_BCAx 0xA0
+#define LRDIMM_BCBx 0xB0
+#define LRDIMM_BCCx 0xC0
+#define LRDIMM_BCDx 0xD0
+#define LRDIMM_BCEx 0xE0
+#define LRDIMM_BCFx 0xF0
+#define LRDIMM_F0 0x0
+#define LRDIMM_F1 0x1
+#define LRDIMM_F5 0x5
+#define LRDIMM_F6 0x6
+#define LRDIMM_F7 0x7
+#define LRDIMM_F8 0x8
+#define LRDIMM_F9 0x9
+
+#endif /* _HW_MEM_INIT_LIB_H_ */
diff --git a/Chips/Hisilicon/Include/Library/I2CLib.h b/Chips/Hisilicon/Include/Library/I2CLib.h
new file mode 100644
index 0000000..c3597f6
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/I2CLib.h
@@ -0,0 +1,73 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _I2C_LIB_H_
+#define _I2C_LIB_H_
+
+//I2C0 or I2C1
+typedef enum {
+ DEVICE_TYPE_SPD = 0,
+ DEVICE_TYPE_E2PROM,
+ DEVICE_TYPE_CPLD_3BYTE_OPERANDS,
+ DEVICE_TYPE_CPLD_4BYTE_OPERANDS
+}I2C_DEVICE_TYPE;
+
+
+typedef enum {
+ Normal = 0,
+ Fast,
+ SPEED_MODE_MAX
+}SPEED_MODE;
+
+
+#define I2C_PORT_MAX 9
+
+
+
+typedef struct {
+ UINT32 Socket;
+ UINT32 Port;
+ I2C_DEVICE_TYPE DeviceType;
+ UINT32 SlaveDeviceAddress;
+}I2C_DEVICE;
+
+
+UINTN
+EFIAPI
+I2CInit(UINT32 Socket, UINT32 Port, SPEED_MODE SpeedMode);
+
+EFI_STATUS
+EFIAPI
+I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CWriteMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset, UINT32 ulLength, UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CReadMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CSdaConfig(UINT32 Socket, UINT32 Port);
+
+
+#endif
diff --git a/Chips/Hisilicon/Include/Library/OemMiscLib.h b/Chips/Hisilicon/Include/Library/OemMiscLib.h
new file mode 100644
index 0000000..19d92e0
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/OemMiscLib.h
@@ -0,0 +1,50 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _OEM_MISC_LIB_H_
+#define _OEM_MISC_LIB_H_
+
+#include <Uefi.h>
+
+#include <PlatformArch.h>
+#include <Library/I2CLib.h>
+
+#define PCIEDEVICE_REPORT_MAX 4
+typedef struct _REPORT_PCIEDIDVID2BMC{
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+ UINTN Slot;
+}REPORT_PCIEDIDVID2BMC;
+extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX];
+
+BOOLEAN OemIsSocketPresent (UINTN Socket);
+VOID CoreSelectBoot(VOID);
+VOID OemPcieResetAndOffReset(void);
+extern I2C_DEVICE gDS3231RtcDevice;
+
+UINTN OemGetSocketNumber(VOID);
+UINTN OemGetDdrChannel (VOID);
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel);
+
+BOOLEAN OemIsMpBoot();
+UINT32 OemIsWarmBoot();
+
+VOID OemBiosSwitch(UINT32 Master);
+
+extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM];
+EFI_HII_HANDLE EFIAPI OemGetPackages ();
+#endif
diff --git a/Chips/Hisilicon/Include/Library/PlatformPciLib.h b/Chips/Hisilicon/Include/Library/PlatformPciLib.h
new file mode 100644
index 0000000..72d2d21
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/PlatformPciLib.h
@@ -0,0 +1,93 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_PCI_LIB_H_
+#define _PLATFORM_PCI_LIB_H_
+
+#define PCIE_MAX_HOSTBRIDGE 2
+#define PCIE_MAX_ROOTBRIDGE 4
+
+#define PCI_HB0RB0_PCI_BASE FixedPcdGet64(PciHb0Rb0Base)
+#define PCI_HB0RB1_PCI_BASE FixedPcdGet64(PciHb0Rb1Base)
+#define PCI_HB0RB2_PCI_BASE FixedPcdGet64(PciHb0Rb2Base)
+#define PCI_HB0RB3_PCI_BASE FixedPcdGet64(PciHb0Rb3Base)
+
+#define PCI_HB1RB0_PCI_BASE 0xb0090000
+#define PCI_HB1RB1_PCI_BASE 0xb0200000
+#define PCI_HB1RB2_PCI_BASE 0xb00a0000
+#define PCI_HB1RB3_PCI_BASE 0xb00b0000
+
+#define PCI_HB0RB0_ECAM_BASE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB0_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceSize)
+#define PCI_HB0RB1_ECAM_BASE FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB1_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceSize)
+#define PCI_HB0RB2_ECAM_BASE FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB2_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceSize)
+#define PCI_HB0RB3_ECAM_BASE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB3_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceSize)
+
+#define PCI_HB1RB0_ECAM_BASE (FixedPcdGet64 (PcdHb1BaseAddress) + PCI_HB0RB0_ECAM_BASE)
+#define PCI_HB1RB0_ECAM_SIZE PCI_HB0RB0_ECAM_SIZE
+#define PCI_HB1RB1_ECAM_BASE (FixedPcdGet64 (PcdHb1BaseAddress) + PCI_HB0RB1_ECAM_BASE)
+#define PCI_HB1RB1_ECAM_SIZE PCI_HB0RB1_ECAM_SIZE
+#define PCI_HB1RB2_ECAM_BASE 0xb8000000
+#define PCI_HB1RB2_ECAM_SIZE 0x4000000
+#define PCI_HB1RB3_ECAM_BASE 0xbc000000
+#define PCI_HB1RB3_ECAM_SIZE 0x4000000
+#define PCI_HB0RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb0PciRegionBaseAddress))
+#define PCI_HB0RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb0PciRegionSize))
+#define PCI_HB0RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb1PciRegionBaseAddress))
+#define PCI_HB0RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb1PciRegionSize))
+#define PCI_HB0RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb2PciRegionBaseAddress))
+#define PCI_HB0RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb2PciRegionSize))
+#define PCI_HB0RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb3PciRegionBaseAddress))
+#define PCI_HB0RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb3PciRegionSize))
+
+#define PCI_HB0RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuMemRegionBase))
+#define PCI_HB0RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuMemRegionBase))
+#define PCI_HB0RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuMemRegionBase))
+#define PCI_HB0RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuMemRegionBase))
+
+#define PCI_HB0RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuIoRegionBase))
+#define PCI_HB0RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuIoRegionBase))
+#define PCI_HB0RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuIoRegionBase))
+#define PCI_HB0RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuIoRegionBase))
+
+#define PCI_HB0RB0_IO_BASE (FixedPcdGet64 (PcdHb0Rb0IoBase))
+#define PCI_HB0RB1_IO_BASE (FixedPcdGet64 (PcdHb0Rb1IoBase))
+#define PCI_HB0RB2_IO_BASE (FixedPcdGet64 (PcdHb0Rb2IoBase))
+#define PCI_HB0RB3_IO_BASE (FixedPcdGet64 (PcdHb0Rb3IoBase))
+
+#define PCI_HB0RB0_IO_SIZE (FixedPcdGet64 (PcdHb0Rb0IoSize))
+#define PCI_HB0RB1_IO_SIZE (FixedPcdGet64 (PcdHb0Rb1IoSize))
+#define PCI_HB0RB2_IO_SIZE (FixedPcdGet64 (PcdHb0Rb2IoSize))
+#define PCI_HB0RB3_IO_SIZE (FixedPcdGet64 (PcdHb0Rb3IoSize))
+
+typedef struct {
+ UINT64 Ecam;
+ UINT64 BusBase;
+ UINT64 BusLimit;
+ UINT64 MemBase;
+ UINT64 MemLimit;
+ UINT64 IoBase;
+ UINT64 IoLimit;
+ UINT64 CpuMemRegionBase;
+ UINT64 CpuIoRegionBase;
+ UINT64 RbPciBar;
+} PCI_ROOT_BRIDGE_RESOURCE_APPETURE;
+
+extern PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+#endif
+
diff --git a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
new file mode 100644
index 0000000..f374112
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
@@ -0,0 +1,97 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_SYS_CTRL_LIB_H_
+#define _PLATFORM_SYS_CTRL_LIB_H_
+
+#define PACKAGE_16CORE 0
+#define PACKAGE_32CORE 1
+#define PACKAGE_RESERVED 2
+#define PACKAGE_TYPE_NUM 3
+
+UINT32 PlatformGetPackageType (VOID);
+
+VOID DisplayCpuInfo (VOID);
+UINT32 CheckChipIsEc(VOID);
+
+UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll);
+
+#define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF
+#define DJTAG_CHAIN_ID_AA 1
+#define DJTAG_CHAIN_ID_LLC 4
+
+
+#define SC_DJTAG_MSTR_EN_OFFSET 0x6800
+#define SC_DJTAG_MSTR_START_EN_OFFSET 0x6804
+#define SC_DJTAG_SEC_ACC_EN_OFFSET 0x6808
+#define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET 0x680C
+#define SC_DJTAG_MSTR_WR_OFFSET 0x6810
+#define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET 0x6814
+#define SC_DJTAG_MSTR_ADDR_OFFSET 0x6818
+#define SC_DJTAG_MSTR_DATA_OFFSET 0x681C
+#define SC_DJTAG_TMOUT_OFFSET 0x6820
+#define SC_TDRE_OP_ADDR_OFFSET 0x6824
+#define SC_TDRE_WDATA_OFFSET 0x6828
+#define SC_TDRE_REPAIR_EN_OFFSET 0x682C
+#define SC_DJTAG_RD_DATA0_OFFSET 0xE800
+#define SC_TDRE_RDATA0_OFFSET 0xE830
+
+
+UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port);
+
+VOID PlatformAddressMapCleanUp (VOID);
+VOID PlatformDisableDdrWindow (VOID);
+
+VOID PlatformEnableArchTimer (VOID);
+
+EFI_STATUS
+DawFindFreeWindow (UINTN Socket, UINTN *DawIndex);
+
+VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value);
+
+VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+VOID RemoveRoceReset(VOID);
+
+UINTN PlatformGetDdrChannel (VOID);
+
+VOID ITSCONFIG (VOID);
+
+VOID MN_CONFIG (VOID);
+
+VOID SmmuConfigForOS (VOID);
+VOID SmmuConfigForBios (VOID);
+
+VOID StartupAp (VOID);
+
+VOID LlcCleanInvalidate (VOID);
+
+UINTN PlatformGetCpuFreq (UINT8 Socket);
+VOID ClearInterruptStatus(VOID);
+
+UINTN PlatformGetCoreCount (VOID);
+VOID DAWConfigEn(UINT32 socket);
+
+VOID DResetUsb ();
+UINT32 PlatformGetEhciBase ();
+UINT32 PlatformGetOhciBase ();
+VOID PlatformPllInit();
+VOID PlatformDeviceDReset();
+VOID PlatformGicdInit();
+VOID PlatformLpcInit();
+
+#endif
diff --git a/Chips/Hisilicon/Include/PlatformArch.h b/Chips/Hisilicon/Include/PlatformArch.h
new file mode 100644
index 0000000..f1ccbb6
--- /dev/null
+++ b/Chips/Hisilicon/Include/PlatformArch.h
@@ -0,0 +1,33 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef _PLATFORM_ARCH_H_
+#define _PLATFORM_ARCH_H_
+
+#define MAX_SOCKET 2
+#define MAX_DIE 4
+#define MAX_DDRC 2
+#define MAX_NODE (MAX_SOCKET * MAX_DIE)
+#define MAX_CHANNEL 4
+#define MAX_DIMM 3
+#define MAX_RANK_CH 12
+#define MAX_RANK_DIMM 4
+
+#define S1_BASE 0x40000000000
+
+#endif
+
diff --git a/Chips/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h b/Chips/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h
new file mode 100644
index 0000000..8a9d13c
--- /dev/null
+++ b/Chips/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h
@@ -0,0 +1,61 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _HISI_BOARD_NIC_PROTOCOL_H_
+#define _HISI_BOARD_NIC_PROTOCOL_H_
+
+#define HISI_BOARD_NIC_PROTOCOL_GUID \
+ { 0xb5903955, 0x31e9, 0x4aaf, { 0xb2, 0x83, 0x7, 0x9f, 0x3c, 0xc4, 0x71, 0x66 } }
+
+#define HISI_BOARD_XGE_STATUS_PROTOCOL_GUID \
+ { 0xa6b8ed0e, 0xd8cc, 0x4853, { 0xaa, 0x39, 0x2c, 0x3e, 0xcd, 0x7c, 0xa5, 0x97 } }
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_BOARD_NIC_GET_MAC_ADDRESS) (
+ IN OUT EFI_MAC_ADDRESS *Mac,
+ IN UINTN Port
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_BOARD_NIC_SET_MAC_ADDRESS) (
+ IN EFI_MAC_ADDRESS *Mac,
+ IN UINTN Port
+ );
+
+typedef struct {
+ HISI_BOARD_NIC_GET_MAC_ADDRESS GetMac;
+ HISI_BOARD_NIC_SET_MAC_ADDRESS SetMac;
+} HISI_BOARD_NIC_PROTOCOL;
+
+typedef
+VOID
+(*HISI_BOARD_FEEDBACK_XGE_STATUS) (
+ BOOLEAN IsLinkup,
+ BOOLEAN IsActOK,
+ UINT32 port
+ );
+
+typedef struct {
+ HISI_BOARD_FEEDBACK_XGE_STATUS FeedbackXgeStatus;
+} HISI_BOARD_XGE_STATUS_PROTOCOL;
+
+
+extern EFI_GUID gHisiBoardNicProtocolGuid;
+extern EFI_GUID gHisiBoardXgeStatusProtocolGuid;
+
+
+#endif
diff --git a/Chips/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h b/Chips/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h
new file mode 100644
index 0000000..b7ed9ce
--- /dev/null
+++ b/Chips/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h
@@ -0,0 +1,66 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _HISI_SPI_FLASH_PROTOCOL_H_
+#define _HISI_SPI_FLASH_PROTOCOL_H_
+
+typedef struct _HISI_SPI_FLASH_PROTOCOL HISI_SPI_FLASH_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_ERASE_INTERFACE) (
+ IN HISI_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT32 ulLength
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_WRITE_INTERFACE) (
+ IN HISI_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ IN UINT32 ulLength
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_READ_INTERFACE) (
+ IN HISI_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Buffer,
+ IN UINT32 ulLength
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_ERASE_WRITE_INTERFACE) (
+ IN HISI_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ IN UINT32 ulLength
+ );
+
+struct _HISI_SPI_FLASH_PROTOCOL {
+ HISI_SPI_FLASH_ERASE_INTERFACE Erase;
+ HISI_SPI_FLASH_WRITE_INTERFACE Write;
+ HISI_SPI_FLASH_READ_INTERFACE Read;
+ HISI_SPI_FLASH_ERASE_WRITE_INTERFACE EraseWrite;
+};
+
+extern EFI_GUID gHisiSpiFlashProtocolGuid;
+
+#endif
diff --git a/Chips/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h b/Chips/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h
new file mode 100644
index 0000000..c5f0f85
--- /dev/null
+++ b/Chips/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h
@@ -0,0 +1,99 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IPMI_INTERFACE_PROTOCOL_H_
+#define _IPMI_INTERFACE_PROTOCOL_H_
+
+#define IPMI_INTERFACE_PROTOCOL_GUID \
+ {0xa37e200e, 0xda90, 0x473b, {0x8b, 0xb5, 0x1d, 0x7b, 0x11, 0xba, 0x32, 0x33}}
+
+typedef struct _IPMI_INTERFACE_PROTOCOL IPMI_INTERFACE_PROTOCOL;
+
+//
+// Structure to store IPMI Network Function, LUN and command
+//
+typedef struct {
+ UINT8 Lun : 2;
+ UINT8 NetFn : 6;
+ UINT8 Cmd;
+} IPMI_CMD_HEADER;
+
+//
+// System Interface Type
+//
+typedef enum {
+ IPMI_SYSTEM_INTERFACE_UNKNOWN,
+ IPMI_SYSTEM_INTERFACE_KCS,
+ IPMI_SYSTEM_INTERFACE_SMIC,
+ IPMI_SYSTEM_INTERFACE_BT,
+ IPMI_SYSTEM_INTERFACE_SSIF,
+ IPMI_SYSTEM_INTERFACE_MAX_TYPE
+} IPMI_SYSTEM_INTERFACE_TYPE;
+
+//
+// System Interface Address Type
+//
+typedef enum {
+ IPMI_MEMORY,
+ IPMI_IO,
+ IPMI_MAX_INTERFACE_ADDRESS_TYPE
+} IPMI_INTERFACE_ADDRESS_TYPE;
+
+typedef
+EFI_STATUS
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_EXECUTE_IPMI_CMD) (
+ IN IPMI_INTERFACE_PROTOCOL *This,
+ IN IPMI_CMD_HEADER Request,
+ IN VOID *SendData OPTIONAL,
+ IN UINT8 SendLength,
+ OUT VOID *RecvData,
+ OUT UINT8 *RecvLength,
+ OUT UINT16 *StatusCodes OPTIONAL
+);
+typedef
+IPMI_SYSTEM_INTERFACE_TYPE
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_INTERFACE_TYPE) (
+ IN IPMI_INTERFACE_PROTOCOL *This
+);
+typedef
+UINT16
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS) (
+ IN IPMI_INTERFACE_PROTOCOL *This
+);
+typedef
+IPMI_INTERFACE_ADDRESS_TYPE
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS_TYPE) (
+ IN IPMI_INTERFACE_PROTOCOL *This
+);
+typedef
+UINT8
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_VERSION) (
+ IN IPMI_INTERFACE_PROTOCOL *This
+);
+
+//
+// Structure of IPMI_INTERFACE_PROTOCOL
+//
+struct _IPMI_INTERFACE_PROTOCOL{
+ IPMI_INTERFACE_PROTOCOL_EXECUTE_IPMI_CMD ExecuteIpmiCmd;
+ IPMI_INTERFACE_PROTOCOL_GET_IPMI_INTERFACE_TYPE GetIpmiInterfaceType;
+ IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS GetIpmiBaseAddress;
+ IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS_TYPE GetIpmiBaseAddressType;
+ IPMI_INTERFACE_PROTOCOL_GET_IPMI_VERSION GetIpmiVersion;
+} ;
+
+extern EFI_GUID gIpmiInterfaceProtocolGuid;
+
+#endif
diff --git a/Chips/Hisilicon/Include/Protocol/NorFlashProtocol.h b/Chips/Hisilicon/Include/Protocol/NorFlashProtocol.h
new file mode 100644
index 0000000..29e9de8
--- /dev/null
+++ b/Chips/Hisilicon/Include/Protocol/NorFlashProtocol.h
@@ -0,0 +1,59 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _NOR_FLASH_PROTOCOL_H_
+#define _NOR_FLASH_PROTOCOL_H_
+
+#define UNI_NOR_FLASH_PROTOCOL_GUID \
+ {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}}
+
+typedef struct _UNI_NOR_FLASH_PROTOCOL UNI_NOR_FLASH_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_ERASE_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT32 Length
+ );
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_WRITE_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ UINT32 ulLength
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_READ_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Buffer,
+ IN UINT32 ulLen
+ );
+
+
+struct _UNI_NOR_FLASH_PROTOCOL {
+ UNI_FLASH_ERASE_INTERFACE Erase;
+ UNI_FLASH_WRITE_INTERFACE Write;
+ UNI_FLASH_READ_INTERFACE Read;
+};
+
+extern EFI_GUID gUniNorFlashProtocolGuid;
+
+#endif
diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
new file mode 100644
index 0000000..bdd80f8
--- /dev/null
+++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
@@ -0,0 +1,16536 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_REG_OFFSET__
+#define __PCIE_REG_OFFSET__
+
+
+
+
+#define PCIE_EEP_PCI_CFG_HDR0_REG (0x0)
+#define PCIE_EEP_PCI_CFG_HDR1_REG (0x4)
+#define PCIE_EEP_PCI_CFG_HDR2_REG (0x8)
+#define PCIE_EEP_PCI_CFG_HDR3_REG (0xC)
+#define PCIE_EEP_PCI_CFG_HDR4_REG (0x10)
+#define PCIE_EEP_PCI_CFG_HDR5_REG (0x14)
+#define PCIE_EEP_PCI_CFG_HDR6_REG (0x18)
+#define PCIE_EEP_PCI_CFG_HDR7_REG (0x1C)
+#define PCIE_EEP_PCI_CFG_HDR8_REG (0x20)
+#define PCIE_EEP_PCI_CFG_HDR9_REG (0x24)
+#define PCIE_EEP_PCI_CFG_HDR10_REG (0x28)
+#define PCIE_EEP_PCI_CFG_HDR11_REG (0x2C)
+#define PCIE_EEP_PCI_CFG_HDR12_REG (0x30)
+#define PCIE_EEP_PCI_CFG_HDR13_REG (0x34)
+#define PCIE_EEP_PCI_CFG_HDR14_REG (0x38)
+#define PCIE_EEP_PCI_CFG_HDR15_REG (0x3C)
+#define PCIE_EEP_PCI_PM_CAP0_REG (0x40)
+#define PCIE_EEP_PCI_PM_CAP1_REG (0x44)
+#define PCIE_EEP_PCI_MSI_CAP0_REG (0x50)
+#define PCIE_EEP_PCI_MSI_CAP1_REG (0x54)
+#define PCIE_EEP_PCI_MSI_CAP2_REG (0x58)
+#define PCIE_EEP_PCI_MSI_CAP3_REG (0x5C)
+#define PCIE_EEP_PCIE_CAP0_REG (0x70)
+#define PCIE_EEP_PCIE_CAP1_REG (0x74)
+#define PCIE_EEP_PCIE_CAP2_REG (0x78)
+#define PCIE_EEP_PCIE_CAP3_REG (0x7C)
+#define PCIE_EEP_PCIE_CAP4_REG (0x80)
+#define PCIE_EEP_PCIE_CAP5_REG (0x84)
+#define PCIE_EEP_PCIE_CAP6_REG (0x88)
+#define PCIE_EEP_PCIE_CAP7_REG (0x8C)
+#define PCIE_EEP_PCIE_CAP8_REG (0x90)
+#define PCIE_EEP_PCIE_CAP9_REG (0x94)
+#define PCIE_EEP_PCIE_CAP10_REG (0x98)
+#define PCIE_EEP_PCIE_CAP11_REG (0x9C)
+#define PCIE_EEP_PCIE_CAP12_REG (0xA0)
+#define PCIE_EEP_SLOT_CAP_REG (0xC0)
+#define PCIE_EEP_AER_CAP0_REG (0x100)
+#define PCIE_EEP_AER_CAP1_REG (0x104)
+#define PCIE_EEP_AER_CAP2_REG (0x108)
+#define PCIE_EEP_AER_CAP3_REG (0x10C)
+#define PCIE_EEP_AER_CAP4_REG (0x110)
+#define PCIE_EEP_AER_CAP5_REG (0x114)
+#define PCIE_EEP_AER_CAP6_REG (0x118)
+#define PCIE_EEP_AER_CAP7_REG (0x11C)
+#define PCIE_EEP_AER_CAP8_REG (0x120)
+#define PCIE_EEP_AER_CAP9_REG (0x124)
+#define PCIE_EEP_AER_CAP10_REG (0x128)
+#define PCIE_EEP_AER_CAP11_REG (0x12C)
+#define PCIE_EEP_AER_CAP12_REG (0x130)
+#define PCIE_EEP_AER_CAP13_REG (0x134)
+#define PCIE_EEP_VC_CAP0_REG (0x140)
+#define PCIE_EEP_VC_CAP1_REG (0x144)
+#define PCIE_EEP_VC_CAP2_REG (0x148)
+#define PCIE_EEP_VC_CAP3_REG (0x14C)
+#define PCIE_EEP_VC_CAP4_REG (0x150)
+#define PCIE_EEP_VC_CAP5_REG (0x154)
+#define PCIE_EEP_VC_CAP6_REG (0x158)
+#define PCIE_EEP_VC_CAP7_REG (0x15C)
+#define PCIE_EEP_VC_CAP8_REG (0x160)
+#define PCIE_EEP_VC_CAP9_REG (0x164)
+#define PCIE_EEP_PORT_LOGIC0_REG (0x700)
+#define PCIE_EEP_PORT_LOGIC1_REG (0x704)
+#define PCIE_EEP_PORT_LOGIC2_REG (0x708)
+#define PCIE_EEP_PORT_LOGIC3_REG (0x70C)
+#define PCIE_EEP_PORT_LOGIC4_REG (0x710)
+#define PCIE_EEP_PORT_LOGIC5_REG (0x714)
+#define PCIE_EEP_PORT_LOGIC6_REG (0x718)
+#define PCIE_EEP_PORT_LOGIC7_REG (0x71C)
+#define PCIE_EEP_PORT_LOGIC8_REG (0x720)
+#define PCIE_EEP_PORT_LOGIC9_REG (0x724)
+#define PCIE_EEP_PORT_LOGIC10_REG (0x728)
+#define PCIE_EEP_PORT_LOGIC11_REG (0x72C)
+#define PCIE_EEP_PORT_LOGIC12_REG (0x730)
+#define PCIE_EEP_PORT_LOGIC13_REG (0x734)
+#define PCIE_EEP_PORT_LOGIC14_REG (0x738)
+#define PCIE_EEP_PORT_LOGIC15_REG (0x73C)
+#define PCIE_EEP_PORT_LOGIC16_REG (0x748)
+#define PCIE_EEP_PORT_LOGIC17_REG (0x74C)
+#define PCIE_EEP_PORT_LOGIC18_REG (0x750)
+#define PCIE_EEP_PORT_LOGIC19_REG (0x7A8)
+#define PCIE_EEP_PORT_LOGIC20_REG (0x7AC)
+#define PCIE_EEP_PORT_LOGIC21_REG (0x7B0)
+#define PCIE_EEP_PORT_LOGIC22_REG (0x80C)
+#define PCIE_EEP_PORTLOGIC23_REG (0x810)
+#define PCIE_EEP_PORTLOGIC24_REG (0x814)
+#define PCIE_EEP_PORTLOGIC25_REG (0x818)
+#define PCIE_EEP_PORTLOGIC26_REG (0x81C)
+#define PCIE_EEP_PORTLOGIC27_REG (0x820)
+#define PCIE_EEP_PORTLOGIC28_REG (0x824)
+#define PCIE_EEP_PORTLOGIC29_REG (0x828)
+#define PCIE_EEP_PORTLOGIC30_REG (0x82C)
+#define PCIE_EEP_PORTLOGIC31_REG (0x830)
+#define PCIE_EEP_PORTLOGIC32_REG (0x834)
+#define PCIE_EEP_PORTLOGIC33_REG (0x838)
+#define PCIE_EEP_PORTLOGIC34_REG (0x83C)
+#define PCIE_EEP_PORTLOGIC35_REG (0x840)
+#define PCIE_EEP_PORTLOGIC36_REG (0x844)
+#define PCIE_EEP_PORTLOGIC37_REG (0x848)
+#define PCIE_EEP_PORTLOGIC38_REG (0x84C)
+#define PCIE_EEP_PORTLOGIC39_REG (0x850)
+#define PCIE_EEP_PORTLOGIC40_REG (0x854)
+#define PCIE_EEP_PORTLOGIC41_REG (0x858)
+#define PCIE_EEP_PORTLOGIC42_REG (0x85C)
+#define PCIE_EEP_PORTLOGIC43_REG (0x860)
+#define PCIE_EEP_PORTLOGIC44_REG (0x864)
+#define PCIE_EEP_PORTLOGIC45_REG (0x868)
+#define PCIE_EEP_PORTLOGIC46_REG (0x86C)
+#define PCIE_EEP_PORTLOGIC47_REG (0x870)
+#define PCIE_EEP_PORTLOGIC48_REG (0x874)
+#define PCIE_EEP_PORTLOGIC49_REG (0x878)
+#define PCIE_EEP_PORTLOGIC50_REG (0x87C)
+#define PCIE_EEP_PORTLOGIC51_REG (0x880)
+#define PCIE_EEP_PORTLOGIC52_REG (0x884)
+#define PCIE_EEP_PORTLOGIC53_REG (0x888)
+#define PCIE_EEP_GEN3_CONTRL_REG (0x890)
+#define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8)
+#define PCIE_EEP_PORTLOGIC54_REG (0x900)
+#define PCIE_EEP_PORTLOGIC55_REG (0x904)
+#define PCIE_EEP_PORTLOGIC56_REG (0x908)
+#define PCIE_EEP_PORTLOGIC57_REG (0x90C)
+#define PCIE_EEP_PORTLOGIC58_REG (0x910)
+#define PCIE_EEP_PORTLOGIC59_REG (0x914)
+#define PCIE_EEP_PORTLOGIC60_REG (0x918)
+#define PCIE_EEP_PORTLOGIC61_REG (0x91C)
+#define PCIE_EEP_PORTLOGIC62_REG (0x97C)
+#define PCIE_EEP_PORTLOGIC63_REG (0x980)
+#define PCIE_EEP_PORTLOGIC64_REG (0x99C)
+#define PCIE_EEP_PORTLOGIC65_REG (0x9A0)
+#define PCIE_EEP_PORTLOGIC66_REG (0x9BC)
+#define PCIE_EEP_PORTLOGIC67_REG (0x9C4)
+#define PCIE_EEP_PORTLOGIC68_REG (0x9C8)
+#define PCIE_EEP_PORTLOGIC69_REG (0x9CC)
+#define PCIE_EEP_PORTLOGIC70_REG (0x9D0)
+#define PCIE_EEP_PORTLOGIC71_REG (0x9D4)
+#define PCIE_EEP_PORTLOGIC72_REG (0x9D8)
+#define PCIE_EEP_PORTLOGIC73_REG (0x9DC)
+#define PCIE_EEP_PORTLOGIC74_REG (0x9E0)
+#define PCIE_EEP_PORTLOGIC75_REG (0xA00)
+#define PCIE_EEP_PORTLOGIC76_REG (0xA10)
+#define PCIE_EEP_PORTLOGIC77_REG (0xA18)
+#define PCIE_EEP_PORTLOGIC78_REG (0xA1C)
+#define PCIE_EEP_PORTLOGIC79_REG (0xA24)
+#define PCIE_EEP_PORTLOGIC80_REG (0xA28)
+#define PCIE_EEP_PORTLOGIC81_REG (0xA34)
+#define PCIE_EEP_PORTLOGIC82_REG (0xA3C)
+#define PCIE_EEP_PORTLOGIC83_REG (0xA40)
+#define PCIE_EEP_PORTLOGIC84_REG (0xA44)
+#define PCIE_EEP_PORTLOGIC85_REG (0xA48)
+#define PCIE_EEP_PORTLOGIC86_REG (0xA6C)
+#define PCIE_EEP_PORTLOGIC87_REG (0xA70)
+#define PCIE_EEP_PORTLOGIC88_REG (0xA78)
+#define PCIE_EEP_PORTLOGIC89_REG (0xA7C)
+#define PCIE_EEP_PORTLOGIC90_REG (0xA80)
+#define PCIE_EEP_PORTLOGIC91_REG (0xA84)
+#define PCIE_EEP_PORTLOGIC92_REG (0xA88)
+#define PCIE_EEP_PORTLOGIC93_REG (0xA8C)
+#define PCIE_EEP_PORTLOGIC94_REG (0xA90)
+
+//pcie iatu internal registers define
+#define IATU_OFFSET 0x700
+#define IATU_VIEW_POINT 0x200
+#define IATU_REGION_CTRL1 0x204
+#define IATU_REGION_CTRL2 0x208
+#define IATU_REGION_BASE_LOW 0x20C
+#define IATU_REGION_BASE_HIGH 0x210
+#define IATU_REGION_BASE_LIMIT 0x214
+#define IATU_REGION_TARGET_LOW 0x218
+#define IATU_REGION_TARGET_HIGH 0x21C
+#define IATU_SHIIF_MODE 0x90000000
+#define IATU_NORMAL_MODE 0x80000000
+#define IATU_CTRL1_TYPE_CONFIG0 0x4
+#define IATU_CTRL1_TYPE_CONFIG1 0x5
+#define IATU_CTRL1_TYPE_MEM 0
+#define IATU_CTRL1_TYPE_IO 2
+
+
+typedef union tagPipeLoopBack
+{
+ struct
+ {
+ UINT32 reserved : 31 ;
+ UINT32 pipe_loopback_enable : 1 ;
+ }Bits;
+ UINT32 UInt32;
+}PCIE_PIPE_LOOPBACK_U;
+
+typedef union tagEepPciCfgHdr0
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR0_U;
+
+
+
+typedef union tagEepPciCfgHdr1
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_2 : 5 ;
+ UINT32 Reserved_1 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_0 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_parity_error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR1_U;
+
+typedef union tagEepPciCfgHdr2
+{
+
+ struct
+ {
+ UINT32 revision_identification : 8 ;
+ UINT32 Reserved_3 : 8 ;
+ UINT32 sub_class : 8 ;
+ UINT32 baseclass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR2_U;
+
+
+
+typedef union tagEepPciCfgHdr3
+{
+
+ struct
+ {
+ UINT32 cache_line_size : 8 ;
+ UINT32 mstr_lat_tmr : 8 ;
+ UINT32 multi_function_device : 7 ;
+ UINT32 hdr_type : 1 ;
+ UINT32 bist : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR3_U;
+
+
+
+typedef union tagEepPciCfgHdr4
+{
+
+ struct
+ {
+ UINT32 sbar01_space_inicator : 1 ;
+ UINT32 sbar01_type : 2 ;
+ UINT32 sbar01_prefetchable : 1 ;
+ UINT32 sbar01_lower : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR4_U;
+
+
+
+typedef union tagEepPciCfgHdr6
+{
+
+ struct
+ {
+ UINT32 sbar23_space_inicator : 1 ;
+ UINT32 sbar23_type : 2 ;
+ UINT32 sbar23_prefetchable : 1 ;
+ UINT32 Reserved_4 : 8 ;
+ UINT32 sbar23_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR6_U;
+
+
+
+typedef union tagEepPciCfgHdr8
+{
+
+ struct
+ {
+ UINT32 sbar45_space_inicator : 1 ;
+ UINT32 sbar45_type : 2 ;
+ UINT32 sbar45_prefetchable : 1 ;
+ UINT32 Reserved_5 : 8 ;
+ UINT32 sbar45_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR8_U;
+
+
+
+typedef union tagEepPciCfgHdr11
+{
+
+ struct
+ {
+ UINT32 subsystem_vendor_id : 16 ;
+ UINT32 subsystemid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR11_U;
+
+
+
+typedef union tagEepPciCfgHdr13
+{
+
+ struct
+ {
+ UINT32 capptr : 8 ;
+ UINT32 Reserved_6 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR13_U;
+
+
+
+typedef union tagEepPciCfgHdr15
+{
+
+ struct
+ {
+ UINT32 int_line : 8 ;
+ UINT32 int_pin : 8 ;
+ UINT32 Min_Grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR15_U;
+
+
+
+typedef union tagEepPciMsiCap0
+{
+
+ struct
+ {
+ UINT32 msi_cap_id : 8 ;
+ UINT32 next_capability_pointer : 8 ;
+ UINT32 msi_enabled : 1 ;
+ UINT32 multiple_message_capable : 3 ;
+ UINT32 multiple_message_enabled : 3 ;
+ UINT32 msi_64_en : 1 ;
+ UINT32 pvm_en : 1 ;
+ UINT32 message_control_register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_MSI_CAP0_U;
+
+
+
+typedef union tagEepPciMsiCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_11 : 2 ;
+ UINT32 msi_addr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_MSI_CAP1_U;
+
+
+
+typedef union tagEepPciMsiCap3
+{
+
+ struct
+ {
+ UINT32 msi_data : 16 ;
+ UINT32 Reserved_12 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCI_MSI_CAP3_U;
+
+
+
+typedef union tagEepPcieCap0
+{
+
+ struct
+ {
+ UINT32 pcie_cap_id : 8 ;
+ UINT32 pcie_next_ptr : 8 ;
+ UINT32 pcie_capability_version : 4 ;
+ UINT32 device_port_type : 4 ;
+ UINT32 slot_implemented : 1 ;
+ UINT32 interrupt_message_number : 5 ;
+ UINT32 Reserved_13 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP0_U;
+
+
+
+typedef union tagEepPcieCap1
+{
+
+ struct
+ {
+ UINT32 max_payload_size_supported : 3 ;
+ UINT32 phantom_function_supported : 2 ;
+ UINT32 extended_tagEepfield_supported : 1 ;
+ UINT32 endpoint_l0sacceptable_latency : 3 ;
+ UINT32 endpoint_l1acceptable_latency : 3 ;
+ UINT32 undefined : 3 ;
+ UINT32 Reserved_16 : 3 ;
+ UINT32 captured_slot_power_limit_value : 8 ;
+ UINT32 captured_slot_power_limit_scale : 2 ;
+ UINT32 function_level_reset : 1 ;
+ UINT32 Reserved_15 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP1_U;
+
+
+
+typedef union tagEepPcieCap2
+{
+
+ struct
+ {
+ UINT32 correctable_error_reporting_enable : 1 ;
+ UINT32 non_fatal_error_reporting_enable : 1 ;
+ UINT32 fatal_error_reporting_enable : 1 ;
+ UINT32 urenable : 1 ;
+ UINT32 enable_relaxed_ordering : 1 ;
+ UINT32 max_payload_size : 3 ;
+ UINT32 extended_tagEepfieldenable : 1 ;
+ UINT32 phantom_function_enable : 1 ;
+ UINT32 auxpowerpmenable : 1 ;
+ UINT32 enablenosnoop : 1 ;
+ UINT32 max_read_request_size : 3 ;
+ UINT32 Reserved_18 : 1 ;
+ UINT32 correctableerrordetected : 1 ;
+ UINT32 non_fatalerrordetected : 1 ;
+ UINT32 fatalerrordetected : 1 ;
+ UINT32 unsupportedrequestdetected : 1 ;
+ UINT32 auxpowerdetected : 1 ;
+ UINT32 transactionpending : 1 ;
+ UINT32 Reserved_17 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP2_U;
+
+
+
+typedef union tagEepPcieCap3
+{
+
+ struct
+ {
+ UINT32 max_link_speed : 4 ;
+ UINT32 max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exitlatency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_19 : 1 ;
+ UINT32 port_number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagEepPcieCap4
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_22 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_21 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_20 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagEepPcieCap5
+{
+
+ struct
+ {
+ UINT32 attentioonbuttonpresent : 1 ;
+ UINT32 powercontrollerpresent : 1 ;
+ UINT32 mrlsensorpresent : 1 ;
+ UINT32 attentionindicatorpresent : 1 ;
+ UINT32 powerindicatorpresent : 1 ;
+ UINT32 hot_plugsurprise : 1 ;
+ UINT32 hot_plugcapable : 1 ;
+ UINT32 slotpowerlimitvalue : 8 ;
+ UINT32 slotpowerlimitscale : 2 ;
+ UINT32 electromechanicalinterlockpresen : 1 ;
+ UINT32 no_cmd_complete_support : 1 ;
+ UINT32 phy_slot_number : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP5_U;
+
+
+
+
+typedef union tagEepPcieCap6
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpressedenable : 1 ;
+ UINT32 powerfaultdetectedenable : 1 ;
+ UINT32 mrlsensorchangedenable : 1 ;
+ UINT32 presencedetectchangedenable : 1 ;
+ UINT32 commandcompletedinterruptenable : 1 ;
+ UINT32 hot_pluginterruptenable : 1 ;
+ UINT32 attentionindicatorcontrol : 2 ;
+ UINT32 powerindicatorcontrol : 2 ;
+ UINT32 powercontrollercontrol : 1 ;
+ UINT32 electromechanicalinterlockcontrol : 1 ;
+ UINT32 datalinklayerstatechangedenable : 1 ;
+ UINT32 Reserved_23 : 3 ;
+ UINT32 attentionbuttonpressed : 1 ;
+ UINT32 powerfaultdetected : 1 ;
+ UINT32 mrlsensorchanged : 1 ;
+ UINT32 presencedetectchanged : 1 ;
+ UINT32 commandcompleted : 1 ;
+ UINT32 mrlsensorstate : 1 ;
+ UINT32 presencedetectstate : 1 ;
+ UINT32 electromechanicalinterlockstatus : 1 ;
+ UINT32 datalinklayerstatechanged : 1 ;
+ UINT32 slot_ctrl_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagEepPcieCap7
+{
+
+ struct
+ {
+ UINT32 systemerroroncorrectableerrorenable : 1 ;
+ UINT32 systemerroronnon_fatalerrorenable : 1 ;
+ UINT32 systemerroronfatalerrorenable : 1 ;
+ UINT32 pmeinterruptenable : 1 ;
+ UINT32 crssoftwarevisibilityenable : 1 ;
+ UINT32 Reserved_24 : 11 ;
+ UINT32 crssoftwarevisibility : 1 ;
+ UINT32 root_cap : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagEepPcieCap8
+{
+
+ struct
+ {
+ UINT32 pmerequesterid : 16 ;
+ UINT32 pmestatus : 1 ;
+ UINT32 pmepending : 1 ;
+ UINT32 root_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagEepPcieCap9
+{
+
+ struct
+ {
+ UINT32 completiontimeoutrangessupported : 4 ;
+ UINT32 completiontimeoutdisablesupported : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoproutingsupported : 1 ;
+ UINT32 _2_bitatomicopcompletersupported : 1 ;
+ UINT32 _4_bitatomicopcompletersupported : 1 ;
+ UINT32 _28_bitcascompletersupported : 1 ;
+ UINT32 noro_enabledpr_prpassing : 1 ;
+ UINT32 Reserved_25 : 1 ;
+ UINT32 tphcompletersupported : 2 ;
+ UINT32 dev_cap2 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagEepPcieCap10
+{
+
+ struct
+ {
+ UINT32 completiontimeoutvalue : 4 ;
+ UINT32 completiontimeoutdisable : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoprequesterenable : 1 ;
+ UINT32 atomicopegressblocking : 1 ;
+ UINT32 idorequestenable : 1 ;
+ UINT32 idocompletionenable : 1 ;
+ UINT32 dev_ctrl2 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagEepPcieCap11
+{
+
+ struct
+ {
+ UINT32 Reserved_27 : 1 ;
+ UINT32 gen1_suport : 1 ;
+ UINT32 gen2_suport : 1 ;
+ UINT32 gen3_suport : 1 ;
+ UINT32 Reserved_26 : 4 ;
+ UINT32 crosslink_supported : 1 ;
+ UINT32 link_cap2 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagEepPcieCap12
+{
+
+ struct
+ {
+ UINT32 targetlinkspeed : 4 ;
+ UINT32 entercompliance : 1 ;
+ UINT32 hardwareautonomousspeeddisa : 1 ;
+ UINT32 selectablede_empha : 1 ;
+ UINT32 transmitmargin : 3 ;
+ UINT32 _entermodifiedcompliance : 1 ;
+ UINT32 compliancesos : 1 ;
+ UINT32 de_emphasislevel : 4 ;
+ UINT32 currentde_emphasislevel : 1 ;
+ UINT32 equalizationcomplete : 1 ;
+ UINT32 equalizationphase1successful : 1 ;
+ UINT32 equalizationphase2successful : 1 ;
+ UINT32 equalizationphase3successful : 1 ;
+ UINT32 linkequalizationrequest : 1 ;
+ UINT32 link_ctrl2_status2 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagEepSlotCap
+{
+
+ struct
+ {
+ UINT32 slotnumberingcapabilitiesid : 8 ;
+ UINT32 nextcapabilitypointer : 8 ;
+ UINT32 add_incardslotsprovided : 5 ;
+ UINT32 firstinchassis : 1 ;
+ UINT32 Reserved_28 : 2 ;
+ UINT32 slot_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_SLOT_CAP_U;
+
+
+
+
+typedef union tagEepAerCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 aer_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP0_U;
+
+
+
+
+typedef union tagEepAerCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_34 : 1 ;
+ UINT32 Reserved_33 : 3 ;
+ UINT32 datalinkprotocolerrorsta : 1 ;
+ UINT32 surprisedownerrorstatus : 1 ;
+ UINT32 Reserved_32 : 6 ;
+ UINT32 poisonedtlpstatu : 1 ;
+ UINT32 flowcontrolprotocolerrorst : 1 ;
+ UINT32 completiontimeouts : 1 ;
+ UINT32 completerabortstatus : 1 ;
+ UINT32 receiveroverflowstatus : 1 ;
+ UINT32 malformedtlpstatus : 1 ;
+ UINT32 ecrcerrorstatus : 1 ;
+ UINT32 ecrcerrorstat : 1 ;
+ UINT32 unsupportedrequesterrorstatus : 1 ;
+ UINT32 Reserved_31 : 3 ;
+ UINT32 atomicopegressblockedstatus : 1 ;
+ UINT32 uncorr_err_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP1_U;
+
+
+
+
+typedef union tagEepAerCap2
+{
+
+ struct
+ {
+ UINT32 Reserved_38 : 1 ;
+ UINT32 Reserved_37 : 3 ;
+ UINT32 datalinkprotocolerrormask : 1 ;
+ UINT32 surprisedownerrormask : 1 ;
+ UINT32 Reserved_36 : 6 ;
+ UINT32 poisonedtlpmask : 1 ;
+ UINT32 flowcontrolprotocolerrormask : 1 ;
+ UINT32 completiontimeoutmask : 1 ;
+ UINT32 completerabortmask : 1 ;
+ UINT32 unexpectedcompletionmask : 1 ;
+ UINT32 receiveroverflowmask : 1 ;
+ UINT32 malformedtlpmask : 1 ;
+ UINT32 ecrcerrormask : 1 ;
+ UINT32 unsupportedrequesterrormask : 1 ;
+ UINT32 Reserved_35 : 3 ;
+ UINT32 atomicopegressblockedmask : 1 ;
+ UINT32 uncorr_err_mask : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP2_U;
+
+
+
+
+typedef union tagEepAerCap3
+{
+
+ struct
+ {
+ UINT32 Reserved_42 : 1 ;
+ UINT32 Reserved_41 : 3 ;
+ UINT32 datalinkprotocolerrorsever : 1 ;
+ UINT32 surprisedownerrorseverity : 1 ;
+ UINT32 Reserved_40 : 6 ;
+ UINT32 poisonedtlpseverity : 1 ;
+ UINT32 flowcontrolprotocolerrorseveri : 1 ;
+ UINT32 completiontimeoutseverity : 1 ;
+ UINT32 completerabortseverity : 1 ;
+ UINT32 unexpectedcompletionseverity : 1 ;
+ UINT32 receiveroverflowseverity : 1 ;
+ UINT32 malformedtlpseverity : 1 ;
+ UINT32 ecrcerrorseverity : 1 ;
+ UINT32 unsupportedrequesterrorseverity : 1 ;
+ UINT32 Reserved_39 : 3 ;
+ UINT32 atomicopegressblockedseverity : 1 ;
+ UINT32 uncorr_err_ser : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP3_U;
+
+
+
+
+typedef union tagEepAerCap4
+{
+
+ struct
+ {
+ UINT32 receivererrorstatus : 1 ;
+ UINT32 Reserved_44 : 5 ;
+ UINT32 badtlpstatus : 1 ;
+ UINT32 baddllpstatus : 1 ;
+ UINT32 replay_numrolloverstatus : 1 ;
+ UINT32 Reserved_43 : 3 ;
+ UINT32 replytimertimeoutstatus : 1 ;
+ UINT32 advisorynon_fatalerrorstatus : 1 ;
+ UINT32 corr_err_status : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP4_U;
+
+
+
+
+typedef union tagEepAerCap5
+{
+
+ struct
+ {
+ UINT32 receivererrormask : 1 ;
+ UINT32 Reserved_46 : 5 ;
+ UINT32 badtlpmask : 1 ;
+ UINT32 baddllpmask : 1 ;
+ UINT32 replay_numrollovermask : 1 ;
+ UINT32 Reserved_45 : 3 ;
+ UINT32 replytimertimeoutmask : 1 ;
+ UINT32 advisorynon_fatalerrormask : 1 ;
+ UINT32 corr_err_mask : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP5_U;
+
+
+
+
+typedef union tagEepAerCap6
+{
+
+ struct
+ {
+ UINT32 firsterrorpointer : 5 ;
+ UINT32 ecrcgenerationcapability : 1 ;
+ UINT32 ecrcgenerationenable : 1 ;
+ UINT32 ecrccheckcapable : 1 ;
+ UINT32 ecrccheckenable : 1 ;
+ UINT32 adv_cap_ctrl : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP6_U;
+
+typedef union tagGen3Ctrol
+{
+ struct
+ {
+ UINT32 reserved : 16 ;
+ UINT32 equalization_disable : 1 ;
+ UINT32 reserved2 : 15 ;
+ }Bits;
+ UINT32 UInt32;
+}PCIE_GRN3_CONTRL;
+
+
+
+
+typedef union tagEepAerCap11
+{
+
+ struct
+ {
+ UINT32 correctableerrorreportingenable : 1 ;
+ UINT32 non_fatalerrorreportingenable : 1 ;
+ UINT32 fatalerrorreportingenable : 1 ;
+ UINT32 root_err_cmd : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP11_U;
+
+
+
+
+typedef union tagEepAerCap12
+{
+
+ struct
+ {
+ UINT32 err_correceived : 1 ;
+ UINT32 multipleerr_correceived : 1 ;
+ UINT32 err_fatal_nonfatalreceived : 1 ;
+ UINT32 multipleerr_fatal_nonfatalreceived : 1 ;
+ UINT32 firstuncorrectablefatal : 1 ;
+ UINT32 non_fatalerrormessagesreceived : 1 ;
+ UINT32 fatalerrormessagesreceived : 1 ;
+ UINT32 Reserved_47 : 20 ;
+ UINT32 root_err_status : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP12_U;
+
+
+
+
+typedef union tagEepAerCap13
+{
+
+ struct
+ {
+ UINT32 err_corsourceidentification : 16 ;
+ UINT32 err_src_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_AER_CAP13_U;
+
+
+
+
+typedef union tagEepVcCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 vc_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP0_U;
+
+
+
+
+typedef union tagEepVcCap1
+{
+
+ struct
+ {
+ UINT32 extendedvccount : 3 ;
+ UINT32 Reserved_50 : 1 ;
+ UINT32 lowpriorityextendedvccount : 3 ;
+ UINT32 Reserved_49 : 1 ;
+ UINT32 referenceclock : 2 ;
+ UINT32 portarbitrationtableentrysize : 2 ;
+ UINT32 vc_cap1 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP1_U;
+
+
+
+
+typedef union tagEepVcCap2
+{
+
+ struct
+ {
+ UINT32 vcarbitrationcapability : 8 ;
+ UINT32 Reserved_51 : 16 ;
+ UINT32 vc_cap2 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP2_U;
+
+
+
+
+typedef union tagEepVcCap3
+{
+
+ struct
+ {
+ UINT32 loadvcarbitrationtable : 1 ;
+ UINT32 vcarbitrationselect : 3 ;
+ UINT32 Reserved_53 : 12 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 Reserved_52 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP3_U;
+
+
+
+
+typedef union tagEepVcCap4
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_56 : 6 ;
+ UINT32 Reserved_55 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_54 : 1 ;
+ UINT32 vc_res_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP4_U;
+
+
+
+
+typedef union tagEepVcCap5
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_59 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselec : 3 ;
+ UINT32 Reserved_58 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_57 : 4 ;
+ UINT32 vc_res_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP5_U;
+
+
+
+
+typedef union tagEepVcCap6
+{
+
+ struct
+ {
+ UINT32 Reserved_60 : 16 ;
+ UINT32 portarbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP6_U;
+
+
+
+
+typedef union tagEepVcCap7
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_63 : 6 ;
+ UINT32 Reserved_62 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_61 : 1 ;
+ UINT32 vc_res_cap0 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP7_U;
+
+
+
+
+typedef union tagEepVcCap8
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_66 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselect : 3 ;
+ UINT32 Reserved_65 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_64 : 4 ;
+ UINT32 vc_res_ctrl0 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP8_U;
+
+
+
+
+typedef union tagEepVcCap9
+{
+
+ struct
+ {
+ UINT32 Reserved_67 : 16 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status0 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_VC_CAP9_U;
+
+
+
+
+typedef union tagEepPortLogic0
+{
+
+ struct
+ {
+ UINT32 ack_lat_timer : 16 ;
+ UINT32 replay_timer : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagEepPortLogic2
+{
+
+ struct
+ {
+ UINT32 linknumber : 8 ;
+ UINT32 Reserved_70 : 7 ;
+ UINT32 forcelink : 1 ;
+ UINT32 linkstate : 6 ;
+ UINT32 Reserved_69 : 2 ;
+ UINT32 port_force_link : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagEepPortLogic3
+{
+
+ struct
+ {
+ UINT32 ackfrequency : 8 ;
+ UINT32 n_fts : 8 ;
+ UINT32 commonclockn_fts : 8 ;
+ UINT32 l0sentrancelatency : 3 ;
+ UINT32 l1entrancelatency : 3 ;
+ UINT32 enteraspml1withoutreceiveinl0s : 1 ;
+ UINT32 ack_aspm : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagEepPortLogic4
+{
+
+ struct
+ {
+ UINT32 vendorspecificdllprequest : 1 ;
+ UINT32 scrambledisable : 1 ;
+ UINT32 loopbackenable : 1 ;
+ UINT32 resetassert : 1 ;
+ UINT32 Reserved_73 : 1 ;
+ UINT32 dlllinkenable : 1 ;
+ UINT32 Reserved_72 : 1 ;
+ UINT32 fastlinkmode : 1 ;
+ UINT32 Reserved_71 : 8 ;
+ UINT32 linkmodeenable : 6 ;
+ UINT32 crosslinkenable : 1 ;
+ UINT32 crosslinkactive : 1 ;
+ UINT32 port_link_ctrl : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagEepPortLogic5
+{
+
+ struct
+ {
+ UINT32 insertlaneskewfortransmit : 24 ;
+ UINT32 flowcontroldisable : 1 ;
+ UINT32 ack_nakdisable : 1 ;
+ UINT32 Reserved_74 : 5 ;
+ UINT32 lane_skew : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagEepPortLogic6
+{
+
+ struct
+ {
+ UINT32 numberoftssymbols : 4 ;
+ UINT32 Reserved_76 : 4 ;
+ UINT32 numberofskpsymbols : 3 ;
+ UINT32 Reserved_75 : 3 ;
+ UINT32 timermodifierforreplaytimer : 5 ;
+ UINT32 timermodifierforack_naklatencytimer : 5 ;
+ UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ;
+ UINT32 sym_num : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagEepPortLogic7
+{
+
+ struct
+ {
+ UINT32 vc0posteddataqueuedepth : 11 ;
+ UINT32 Reserved_77 : 4 ;
+ UINT32 sym_timer : 1 ;
+ UINT32 maskfunctionmismatchfilteringfo : 1 ;
+ UINT32 maskpoisonedtlpfiltering : 1 ;
+ UINT32 maskbarmatchfiltering : 1 ;
+ UINT32 masktype1configurationrequestfiltering : 1 ;
+ UINT32 masklockedrequestfiltering : 1 ;
+ UINT32 masktagerrorrulesforreceivedcompletions : 1 ;
+ UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ;
+ UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ;
+ UINT32 maske_crcerror_filtering : 1 ;
+ UINT32 maske_crcerror_filtering_forcompletions : 1 ;
+ UINT32 message_control : 1 ;
+ UINT32 maskfilteringofreceived : 1 ;
+ UINT32 flt_mask1 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagEepPortLogic8
+{
+
+ struct
+ {
+ UINT32 cx_flt_mask_venmsg0_drop : 1 ;
+ UINT32 cx_flt_mask_venmsg1_drop : 1 ;
+ UINT32 cx_flt_mask_dabort_4ucpl : 1 ;
+ UINT32 cx_flt_mask_handle_flush : 1 ;
+ UINT32 flt_mask2 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagEepPortLogic9
+{
+
+ struct
+ {
+ UINT32 amba_multi_outbound_decomp_np : 1 ;
+ UINT32 amba_obnp_ctrl : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagEepPortLogic12
+{
+
+ struct
+ {
+ UINT32 transmitposteddatafccredits : 12 ;
+ UINT32 transmitpostedheaderfccredits : 8 ;
+ UINT32 tx_pfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagEepPortLogic13
+{
+
+ struct
+ {
+ UINT32 transmitnon_posteddatafccredits : 12 ;
+ UINT32 transmitnon_postedheaderfccredits : 8 ;
+ UINT32 tx_npfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagEepPortLogic14
+{
+
+ struct
+ {
+ UINT32 transmitcompletiondatafccredits : 12 ;
+ UINT32 transmitcompletionheaderfccredits : 8 ;
+ UINT32 tx_cplfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagEepPortLogic15
+{
+
+ struct
+ {
+ UINT32 rx_tlp_fc_credit_not_retured : 1 ;
+ UINT32 tx_retry_buf_not_empty : 1 ;
+ UINT32 rx_queue_not_empty : 1 ;
+ UINT32 Reserved_79 : 13 ;
+ UINT32 fc_latency_timer_override_value : 13 ;
+ UINT32 Reserved_78 : 2 ;
+ UINT32 fc_latency_timer_override_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagEepPortLogic16
+{
+
+ struct
+ {
+ UINT32 vc0posteddatacredits : 12 ;
+ UINT32 vc0postedheadercredits : 8 ;
+ UINT32 Reserved_81 : 1 ;
+ UINT32 vc0_postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemo : 1 ;
+ UINT32 Reserved_80 : 6 ;
+ UINT32 tlptypeorderingforvc0 : 1 ;
+ UINT32 rx_pque_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagEepPortLogic17
+{
+
+ struct
+ {
+ UINT32 vc0non_posteddatacredits : 12 ;
+ UINT32 vc0non_postedheadercredits : 8 ;
+ UINT32 rx_npque_ctrl : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagEepPortLogic18
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_credits : 12 ;
+ UINT32 vc0_cpl_header_credt : 8 ;
+ UINT32 Reserved_83 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagEepPortLogic19
+{
+
+ struct
+ {
+ UINT32 vco_posted_data_que_path : 14 ;
+ UINT32 Reserved_84 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 vc_pbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagEepPortLogic20
+{
+
+ struct
+ {
+ UINT32 vco_np_data_que_depth : 14 ;
+ UINT32 Reserved_86 : 2 ;
+ UINT32 vco_np_header_que_depth : 10 ;
+ UINT32 vc_npbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagEepPortLogic21
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_queue_depth : 14 ;
+ UINT32 Reserved_88 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 Reserved_87 : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagEepPortLogic22
+{
+
+ struct
+ {
+ UINT32 n_fts : 8 ;
+ UINT32 pre_determ_num_of_lane : 9 ;
+ UINT32 det_sp_change : 1 ;
+ UINT32 config_phy_tx_sw : 1 ;
+ UINT32 config_tx_comp_rcv_bit : 1 ;
+ UINT32 set_emp_level : 1 ;
+ UINT32 Reserved_89 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagEepPortlogic25
+{
+
+ struct
+ {
+ UINT32 remote_rd_req_size : 3 ;
+ UINT32 Reserved_92 : 5 ;
+ UINT32 remote_max_brd_tag : 8 ;
+ UINT32 Reserved_91 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagEepPortlogic26
+{
+
+ struct
+ {
+ UINT32 resize_master_resp_compser : 1 ;
+ UINT32 axi_ctrl1 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagEepPortlogic54
+{
+
+ struct
+ {
+ UINT32 region_index : 4 ;
+ UINT32 Reserved_93 : 27 ;
+ UINT32 iatu_view : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC54_U;
+
+
+
+
+typedef union tagEepPortlogic55
+{
+
+ struct
+ {
+ UINT32 iatu1_type : 5 ;
+ UINT32 iatu1_tc : 3 ;
+ UINT32 iatu1_td : 1 ;
+ UINT32 iatu1_attr : 2 ;
+ UINT32 Reserved_97 : 5 ;
+ UINT32 iatu1_at : 2 ;
+ UINT32 Reserved_96 : 2 ;
+ UINT32 iatu1_id : 3 ;
+ UINT32 Reserved_95 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagEepPortlogic56
+{
+
+ struct
+ {
+ UINT32 iatu2_type : 8 ;
+ UINT32 iatu2_bar_num : 3 ;
+ UINT32 Reserved_101 : 3 ;
+ UINT32 iatu2_tc_match_en : 1 ;
+ UINT32 iatu2_td_match_en : 1 ;
+ UINT32 iatu2_attr_match_en : 1 ;
+ UINT32 Reserved_100 : 1 ;
+ UINT32 iatu2_at_match_en : 1 ;
+ UINT32 iatu2_func_num_match_en : 1 ;
+ UINT32 iatu2_virtual_func_num_match_en : 1 ;
+ UINT32 message_code_match_en : 1 ;
+ UINT32 Reserved_99 : 2 ;
+ UINT32 iatu2_response_code : 2 ;
+ UINT32 Reserved_98 : 1 ;
+ UINT32 iatu2_fuzzy_type_match_mode : 1 ;
+ UINT32 iatu2_cfg_shift_mode : 1 ;
+ UINT32 iatu2_ivert_mode : 1 ;
+ UINT32 iatu2_match_mode : 1 ;
+ UINT32 iatu2_region_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagEepPortlogic57
+{
+
+ struct
+ {
+ UINT32 iatu_start_low : 12 ;
+ UINT32 iatu_start_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagEepPortlogic59
+{
+
+ struct
+ {
+ UINT32 iatu_limit_low : 12 ;
+ UINT32 iatu_limit_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagEepPortlogic60
+{
+
+ struct
+ {
+ UINT32 xlated_addr_high : 12 ;
+ UINT32 xlated_addr_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagEepPortlogic62
+{
+
+ struct
+ {
+ UINT32 dma_wr_eng_en : 1 ;
+ UINT32 dma_wr_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagEepPortlogic63
+{
+
+ struct
+ {
+ UINT32 wr_doorbell_num : 3 ;
+ UINT32 Reserved_103 : 28 ;
+ UINT32 dma_wr_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagEepPortlogic64
+{
+
+ struct
+ {
+ UINT32 dma_read_eng_en : 1 ;
+ UINT32 Reserved_104 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagEepPortlogic65
+{
+
+ struct
+ {
+ UINT32 rd_doorbell_num : 3 ;
+ UINT32 Reserved_106 : 28 ;
+ UINT32 dma_rd_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagEepPortlogic66
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_108 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_107 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagEepPortlogic67
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_111 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 Reserved_110 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagEepPortlogic68
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_114 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 Reserved_113 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagEepPortlogic69
+{
+
+ struct
+ {
+ UINT32 app_rd_err_det : 8 ;
+ UINT32 Reserved_116 : 8 ;
+ UINT32 ll_element_fetch_err_det : 8 ;
+ UINT32 Reserved_115 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagEepPortlogic74
+{
+
+ struct
+ {
+ UINT32 dma_wr_c0_imwr_data : 16 ;
+ UINT32 dma_wr_c1_imwr_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagEepPortlogic75
+{
+
+ struct
+ {
+ UINT32 wr_ch_ll_remote_abort_int_en : 8 ;
+ UINT32 Reserved_118 : 8 ;
+ UINT32 wr_ch_ll_local_abort_int_en : 8 ;
+ UINT32 Reserved_117 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagEepPortlogic76
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_121 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_120 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagEepPortlogic77
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_123 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 dma_rd_int_mask : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagEepPortlogic78
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_125 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 dma_rd_int_clr : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagEepPortlogic79
+{
+
+ struct
+ {
+ UINT32 app_wr_err_det : 8 ;
+ UINT32 Reserved_126 : 8 ;
+ UINT32 link_list_fetch_err_det : 8 ;
+ UINT32 dma_rd_err_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagEepPortlogic80
+{
+
+ struct
+ {
+ UINT32 unspt_request : 8 ;
+ UINT32 completer_abort : 8 ;
+ UINT32 cpl_time_out : 8 ;
+ UINT32 data_poison : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagEepPortlogic81
+{
+
+ struct
+ {
+ UINT32 remote_abort_int_en : 8 ;
+ UINT32 Reserved_128 : 8 ;
+ UINT32 local_abort_int_en : 8 ;
+ UINT32 dma_rd_ll_err_ena : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagEepPortlogic86
+{
+
+ struct
+ {
+ UINT32 channel_dir : 3 ;
+ UINT32 Reserved_131 : 28 ;
+ UINT32 dma_ch_con_idx : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagEepPortlogic87
+{
+
+ struct
+ {
+ UINT32 cycle_bit : 1 ;
+ UINT32 toggle_cycle_bit : 1 ;
+ UINT32 load_link_pointer : 1 ;
+ UINT32 local_int_en : 1 ;
+ UINT32 remote_int_en : 1 ;
+ UINT32 channel_status : 2 ;
+ UINT32 Reserved_135 : 1 ;
+ UINT32 consumer_cycle_state : 1 ;
+ UINT32 linked_list_en : 1 ;
+ UINT32 Reserved_134 : 2 ;
+ UINT32 func_num_dma : 5 ;
+ UINT32 Reserved_133 : 7 ;
+ UINT32 no_snoop : 1 ;
+ UINT32 ro : 1 ;
+ UINT32 td : 1 ;
+ UINT32 tc : 3 ;
+ UINT32 dma_ch_ctrl : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagEepPortlogic93
+{
+
+ struct
+ {
+ UINT32 Reserved_137 : 2 ;
+ UINT32 dma_ll_ptr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EEP_PORTLOGIC93_U;
+
+
+
+#define PCIE_MEEP_SBAR23XLAT_LOWER_REG (0x0)
+#define PCIE_MEEP_SBAR23XLAT_UPPER_REG (0x4)
+#define PCIE_MEEP_SBAR45XLAT_LOWER_REG (0x8)
+#define PCIE_MEEP_SBAR45XLAT_UPPER_REG (0xC)
+#define PCIE_MEEP_SBAR23LMT_LOWER_REG (0x10)
+#define PCIE_MEEP_SBAR23LMT_UPPER_REG (0x14)
+#define PCIE_MEEP_SBAR45LMT_LOWER_REG (0x18)
+#define PCIE_MEEP_SBAR45LMT_UPPER_REG (0x1C)
+#define PCIE_MEEP_SDOORBELL_REG (0x20)
+#define PCIE_MEEP_SDOORBELL_MASK_REG (0x24)
+#define PCIE_MEEP_CBDF_SBDF_REG (0x28)
+#define PCIE_MEEP_NTB_CNTL_REG (0x2C)
+#define PCIE_MEEP_PCI_CFG_HDR0_REG (0x1000)
+#define PCIE_MEEP_PCI_CFG_HDR1_REG (0x1004)
+#define PCIE_MEEP_PCI_CFG_HDR2_REG (0x1008)
+#define PCIE_MEEP_PCI_CFG_HDR3_REG (0x100C)
+#define PCIE_MEEP_PCI_CFG_HDR4_REG (0x1010)
+#define PCIE_MEEP_PCI_CFG_HDR5_REG (0x1014)
+#define PCIE_MEEP_PCI_CFG_HDR6_REG (0x1018)
+#define PCIE_MEEP_PCI_CFG_HDR7_REG (0x101C)
+#define PCIE_MEEP_PCI_CFG_HDR8_REG (0x1020)
+#define PCIE_MEEP_PCI_CFG_HDR9_REG (0x1024)
+#define PCIE_MEEP_PCI_CFG_HDR10_REG (0x1028)
+#define PCIE_MEEP_PCI_CFG_HDR11_REG (0x102C)
+#define PCIE_MEEP_PCI_CFG_HDR12_REG (0x1030)
+#define PCIE_MEEP_PCI_CFG_HDR13_REG (0x1034)
+#define PCIE_MEEP_PCI_CFG_HDR14_REG (0x1038)
+#define PCIE_MEEP_PCI_CFG_HDR15_REG (0x103C)
+#define PCIE_MEEP_PCI_PM_CAP0_REG (0x1040)
+#define PCIE_MEEP_PCI_PM_CAP1_REG (0x1044)
+#define PCIE_MEEP_PCI_MSI_CAP0_REG (0x1050)
+#define PCIE_MEEP_PCI_MSI_CAP1_REG (0x1054)
+#define PCIE_MEEP_PCI_MSI_CAP2_REG (0x1058)
+#define PCIE_MEEP_PCI_MSI_CAP3_REG (0x105C)
+#define PCIE_MEEP_PCIE_CAP0_REG (0x1070)
+#define PCIE_MEEP_PCIE_CAP1_REG (0x1074)
+#define PCIE_MEEP_PCIE_CAP2_REG (0x1078)
+#define PCIE_MEEP_PCIE_CAP3_REG (0x107C)
+#define PCIE_MEEP_PCIE_CAP4_REG (0x1080)
+#define PCIE_MEEP_PCIE_CAP5_REG (0x1084)
+#define PCIE_MEEP_PCIE_CAP6_REG (0x1088)
+#define PCIE_MEEP_PCIE_CAP7_REG (0x108C)
+#define PCIE_MEEP_PCIE_CAP8_REG (0x1090)
+#define PCIE_MEEP_PCIE_CAP9_REG (0x1094)
+#define PCIE_MEEP_PCIE_CAP10_REG (0x1098)
+#define PCIE_MEEP_PCIE_CAP11_REG (0x109C)
+#define PCIE_MEEP_PCIE_CAP12_REG (0x10A0)
+#define PCIE_MEEP_SLOT_CAP_REG (0x10C0)
+#define PCIE_MEEP_AER_CAP0_REG (0x1100)
+#define PCIE_MEEP_AER_CAP1_REG (0x1104)
+#define PCIE_MEEP_AER_CAP2_REG (0x1108)
+#define PCIE_MEEP_AER_CAP3_REG (0x110C)
+#define PCIE_MEEP_AER_CAP4_REG (0x1110)
+#define PCIE_MEEP_AER_CAP5_REG (0x1114)
+#define PCIE_MEEP_AER_CAP6_REG (0x1118)
+#define PCIE_MEEP_AER_CAP7_REG (0x11C)
+#define PCIE_MEEP_AER_CAP8_REG (0x120)
+#define PCIE_MEEP_AER_CAP9_REG (0x124)
+#define PCIE_MEEP_AER_CAP10_REG (0x128)
+#define PCIE_MEEP_AER_CAP11_REG (0x112C)
+#define PCIE_MEEP_AER_CAP12_REG (0x1130)
+#define PCIE_MEEP_AER_CAP13_REG (0x1134)
+#define PCIE_MEEP_VC_CAP0_REG (0x1140)
+#define PCIE_MEEP_VC_CAP1_REG (0x1144)
+#define PCIE_MEEP_VC_CAP2_REG (0x1148)
+#define PCIE_MEEP_VC_CAP3_REG (0x114C)
+#define PCIE_MEEP_VC_CAP4_REG (0x1150)
+#define PCIE_MEEP_VC_CAP5_REG (0x1154)
+#define PCIE_MEEP_VC_CAP6_REG (0x1158)
+#define PCIE_MEEP_VC_CAP7_REG (0x115C)
+#define PCIE_MEEP_VC_CAP8_REG (0x1160)
+#define PCIE_MEEP_VC_CAP9_REG (0x1164)
+#define PCIE_MEEP_PORT_LOGIC0_REG (0x1700)
+#define PCIE_MEEP_PORT_LOGIC1_REG (0x1704)
+#define PCIE_MEEP_PORT_LOGIC2_REG (0x1708)
+#define PCIE_MEEP_PORT_LOGIC3_REG (0x170C)
+#define PCIE_MEEP_PORT_LOGIC4_REG (0x1710)
+#define PCIE_MEEP_PORT_LOGIC5_REG (0x1714)
+#define PCIE_MEEP_PORT_LOGIC6_REG (0x1718)
+#define PCIE_MEEP_PORT_LOGIC7_REG (0x171C)
+#define PCIE_MEEP_PORT_LOGIC8_REG (0x1720)
+#define PCIE_MEEP_PORT_LOGIC9_REG (0x1724)
+#define PCIE_MEEP_PORT_LOGIC10_REG (0x1728)
+#define PCIE_MEEP_PORT_LOGIC11_REG (0x172C)
+#define PCIE_MEEP_PORT_LOGIC12_REG (0x1730)
+#define PCIE_MEEP_PORT_LOGIC13_REG (0x1734)
+#define PCIE_MEEP_PORT_LOGIC14_REG (0x1738)
+#define PCIE_MEEP_PORT_LOGIC15_REG (0x173C)
+#define PCIE_MEEP_PORT_LOGIC16_REG (0x1748)
+#define PCIE_MEEP_PORT_LOGIC17_REG (0x174C)
+#define PCIE_MEEP_PORT_LOGIC18_REG (0x1750)
+#define PCIE_MEEP_PORT_LOGIC19_REG (0x17A8)
+#define PCIE_MEEP_PORT_LOGIC20_REG (0x17AC)
+#define PCIE_MEEP_PORT_LOGIC21_REG (0x17B0)
+#define PCIE_MEEP_PORT_LOGIC22_REG (0x180C)
+#define PCIE_MEEP_PORTLOGIC23_REG (0x1810)
+#define PCIE_MEEP_PORTLOGIC24_REG (0x1814)
+#define PCIE_MEEP_PORTLOGIC25_REG (0x1818)
+#define PCIE_MEEP_PORTLOGIC26_REG (0x181C)
+#define PCIE_MEEP_PORTLOGIC27_REG (0x1820)
+#define PCIE_MEEP_PORTLOGIC28_REG (0x1824)
+#define PCIE_MEEP_PORTLOGIC29_REG (0x1828)
+#define PCIE_MEEP_PORTLOGIC30_REG (0x182C)
+#define PCIE_MEEP_PORTLOGIC31_REG (0x1830)
+#define PCIE_MEEP_PORTLOGIC32_REG (0x1834)
+#define PCIE_MEEP_PORTLOGIC33_REG (0x1838)
+#define PCIE_MEEP_PORTLOGIC34_REG (0x183C)
+#define PCIE_MEEP_PORTLOGIC35_REG (0x1840)
+#define PCIE_MEEP_PORTLOGIC36_REG (0x1844)
+#define PCIE_MEEP_PORTLOGIC37_REG (0x1848)
+#define PCIE_MEEP_PORTLOGIC38_REG (0x184C)
+#define PCIE_MEEP_PORTLOGIC39_REG (0x1850)
+#define PCIE_MEEP_PORTLOGIC40_REG (0x1854)
+#define PCIE_MEEP_PORTLOGIC41_REG (0x1858)
+#define PCIE_MEEP_PORTLOGIC42_REG (0x185C)
+#define PCIE_MEEP_PORTLOGIC43_REG (0x1860)
+#define PCIE_MEEP_PORTLOGIC44_REG (0x1864)
+#define PCIE_MEEP_PORTLOGIC45_REG (0x1868)
+#define PCIE_MEEP_PORTLOGIC46_REG (0x186C)
+#define PCIE_MEEP_PORTLOGIC47_REG (0x1870)
+#define PCIE_MEEP_PORTLOGIC48_REG (0x1874)
+#define PCIE_MEEP_PORTLOGIC49_REG (0x1878)
+#define PCIE_MEEP_PORTLOGIC50_REG (0x187C)
+#define PCIE_MEEP_PORTLOGIC51_REG (0x1880)
+#define PCIE_MEEP_PORTLOGIC52_REG (0x1884)
+#define PCIE_MEEP_PORTLOGIC53_REG (0x1888)
+#define PCIE_MEEP_PORTLOGIC54_REG (0x1900)
+#define PCIE_MEEP_PORTLOGIC55_REG (0x1904)
+#define PCIE_MEEP_PORTLOGIC56_REG (0x908)
+#define PCIE_MEEP_PORTLOGIC57_REG (0x190C)
+#define PCIE_MEEP_PORTLOGIC58_REG (0x1910)
+#define PCIE_MEEP_PORTLOGIC59_REG (0x1914)
+#define PCIE_MEEP_PORTLOGIC60_REG (0x1918)
+#define PCIE_MEEP_PORTLOGIC61_REG (0x191C)
+#define PCIE_MEEP_PORTLOGIC62_REG (0x197C)
+#define PCIE_MEEP_PORTLOGIC63_REG (0x1980)
+#define PCIE_MEEP_PORTLOGIC64_REG (0x199C)
+#define PCIE_MEEP_PORTLOGIC65_REG (0x19A0)
+#define PCIE_MEEP_PORTLOGIC66_REG (0x19BC)
+#define PCIE_MEEP_PORTLOGIC67_REG (0x19C4)
+#define PCIE_MEEP_PORTLOGIC68_REG (0x19C8)
+#define PCIE_MEEP_PORTLOGIC69_REG (0x19CC)
+#define PCIE_MEEP_PORTLOGIC70_REG (0x19D0)
+#define PCIE_MEEP_PORTLOGIC71_REG (0x19D4)
+#define PCIE_MEEP_PORTLOGIC72_REG (0x19D8)
+#define PCIE_MEEP_PORTLOGIC73_REG (0x19DC)
+#define PCIE_MEEP_PORTLOGIC74_REG (0x19E0)
+#define PCIE_MEEP_PORTLOGIC75_REG (0x1A00)
+#define PCIE_MEEP_PORTLOGIC76_REG (0x1A10)
+#define PCIE_MEEP_PORTLOGIC77_REG (0x1A18)
+#define PCIE_MEEP_PORTLOGIC78_REG (0x1A1C)
+#define PCIE_MEEP_PORTLOGIC79_REG (0x1A24)
+#define PCIE_MEEP_PORTLOGIC80_REG (0x1A28)
+#define PCIE_MEEP_PORTLOGIC81_REG (0x1A34)
+#define PCIE_MEEP_PORTLOGIC82_REG (0x1A3C)
+#define PCIE_MEEP_PORTLOGIC83_REG (0x1A40)
+#define PCIE_MEEP_PORTLOGIC84_REG (0x1A44)
+#define PCIE_MEEP_PORTLOGIC85_REG (0xA48)
+#define PCIE_MEEP_PORTLOGIC86_REG (0xA6C)
+#define PCIE_MEEP_PORTLOGIC87_REG (0x1A70)
+#define PCIE_MEEP_PORTLOGIC88_REG (0x1A78)
+#define PCIE_MEEP_PORTLOGIC89_REG (0x1A7C)
+#define PCIE_MEEP_PORTLOGIC90_REG (0x1A80)
+#define PCIE_MEEP_PORTLOGIC91_REG (0x1A84)
+#define PCIE_MEEP_PORTLOGIC92_REG (0x1A88)
+#define PCIE_MEEP_PORTLOGIC93_REG (0x1A8C)
+#define PCIE_MEEP_PORTLOGIC94_REG (0x1A90)
+#define PCIE_MEEP_PBAR23XLAT_LOWER_REG (0x8000)
+#define PCIE_MEEP_PBAR23XLAT_UPPER_REG (0x8004)
+#define PCIE_MEEP_PBAR45XLAT_LOWER_REG (0x8008)
+#define PCIE_MEEP_PBAR45XLAT_UPPER_REG (0x800C)
+#define PCIE_MEEP_PBAR23LMT_LOWER_REG (0x8010)
+#define PCIE_MEEP_PBAR23LMT_UPPER_REG (0x8014)
+#define PCIE_MEEP_PBAR45LMT_LOWER_REG (0x8018)
+#define PCIE_MEEP_PBAR45LMT_UPPER_REG (0x801C)
+#define PCIE_MEEP_PDOORBELL_REG (0x8020)
+#define PCIE_MEEP_PDOORBELL_MASK_REG (0x8024)
+#define PCIE_MEEP_B2B_BAR01XLAT_LOWER_REG (0x8028)
+#define PCIE_MEEP_B2B_BAR01XLAT_UPPER_REG (0x802C)
+#define PCIE_MEEP_B2B_DOORBELL_REG (0x8030)
+#define PCIE_MEEP_SPAD0_REG (0x8038)
+#define PCIE_MEEP_SPAD1_REG (0x803C)
+#define PCIE_MEEP_SPAD2_REG (0x8040)
+#define PCIE_MEEP_SPAD3_REG (0x8044)
+#define PCIE_MEEP_SPAD4_REG (0x8048)
+#define PCIE_MEEP_SPAD5_REG (0x804C)
+#define PCIE_MEEP_SPAD6_REG (0x8050)
+#define PCIE_MEEP_SPAD7_REG (0x8054)
+#define PCIE_MEEP_SPAD8_REG (0x8058)
+#define PCIE_MEEP_SPAD9_REG (0x805C)
+#define PCIE_MEEP_SPAD10_REG (0x8060)
+#define PCIE_MEEP_SPAD11_REG (0x8064)
+#define PCIE_MEEP_SPAD12_REG (0x8068)
+#define PCIE_MEEP_SPAD13_REG (0x806C)
+#define PCIE_MEEP_SPAD14_REG (0x8070)
+#define PCIE_MEEP_SPAD15_REG (0x8074)
+#define PCIE_MEEP_SPAD16_REG (0x8078)
+#define PCIE_MEEP_SPAD17_REG (0x807C)
+#define PCIE_MEEP_SPAD18_REG (0x8080)
+#define PCIE_MEEP_SPAD19_REG (0x8084)
+#define PCIE_MEEP_SPAD20_REG (0x8088)
+#define PCIE_MEEP_SPAD21_REG (0x808C)
+#define PCIE_MEEP_SPAD22_REG (0x8090)
+#define PCIE_MEEP_SPAD23_REG (0x8094)
+#define PCIE_MEEP_SPAD24_REG (0x8098)
+#define PCIE_MEEP_SPAD25_REG (0x809C)
+#define PCIE_MEEP_SPAD26_REG (0x80A0)
+#define PCIE_MEEP_SPAD27_REG (0x80A4)
+#define PCIE_MEEP_SPAD28_REG (0x80A8)
+#define PCIE_MEEP_SPAD29_REG (0x80AC)
+#define PCIE_MEEP_SPAD30_REG (0x80B0)
+#define PCIE_MEEP_SPAD31_REG (0x80B4)
+#define PCIE_MEEP_PPD_REG (0x8138)
+#define PCIE_MEEP_DEVICE_VENDOR_ID_REG (0x9000)
+#define PCIE_MEEP_PCISTS_PCICMD_REG (0x9004)
+#define PCIE_MEEP_CCR_RID_REG (0x9008)
+#define PCIE_MEEP_PBAR01_BASE_LOWER_REG (0x9010)
+#define PCIE_MEEP_PBAR01_BASE_UPPER_REG (0x9014)
+#define PCIE_MEEP_PBAR23_BASE_LOWER_REG (0x9018)
+#define PCIE_MEEP_PBAR23_BASE_UPPER_REG (0x901C)
+#define PCIE_MEEP_PBAR45_BASE_LOWER_REG (0x9020)
+#define PCIE_MEEP_PBAR45_BASE_UPPER_REG (0x9024)
+#define PCIE_MEEP_CARDBUSCISPTR_REG (0x9028)
+#define PCIE_MEEP_SUBSYSTEMID_REG (0x902C)
+#define PCIE_MEEP_EXPANSIONROM_BASE_ADDR_REG (0x9030)
+#define PCIE_MEEP_CAPPTR_REG (0x9034)
+#define PCIE_MEEP_INTERRUPT_REG (0x903C)
+#define PCIE_MEEP_MSI_CAPABILITY_REGISTER_REG (0x9050)
+#define PCIE_MEEP_MSI_LOWER32_BITADDRESS_REG (0x9054)
+#define PCIE_MEEP_MSI_UPPER32_BIT_ADDRESS_REG (0x9058)
+#define PCIE_MEEP_MSI_DATA_REG (0x905C)
+#define PCIE_MEEP_MSI_MASK_REG (0x9060)
+#define PCIE_MEEP_MSI_PENDING_REG (0x9064)
+#define PCIE_MEEP_PCIE_CAPABILITY_REGISTER_REG (0x9070)
+#define PCIE_MEEP_DEVICE_CAPABILITIES_REGISTER_REG (0x9074)
+#define PCIE_MEEP_DEVICE_STATUS_REGISTER_REG (0x9078)
+#define PCIE_MEEP_LINK_CAPABILITY_REG (0x907C)
+#define PCIE_MEEP_LINK_CONTROL_STATUS_REG (0x9080)
+#define PCIE_MEEP_AER_CAP_HEADER_REG (0x9100)
+#define PCIE_MEEP_UC_ERROR_STATUS_REG (0x9104)
+#define PCIE_MEEP_UC_ERROR_MASK_REG (0x9108)
+#define PCIE_MEEP_UC_ERROR_SEVERITY_REG (0x910C)
+#define PCIE_MEEP_C_ERROR_STATUS_REG (0x9110)
+#define PCIE_MEEP_C_ERROR_MASK_REG (0x9114)
+#define PCIE_MEEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG (0x9118)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_1_REG (0x911C)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_2_REG (0x9120)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_3_REG (0x9124)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_4_REG (0x9128)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_1_REG (0x9130)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_2_REG (0x9134)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_3_REG (0x9138)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_4_REG (0x913C)
+#define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_LOWER_REG (0x9700)
+#define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_UPPER_REG (0x9704)
+#define PCIE_MEEP_NTB_IEP_BAR01_CTRL_REG (0x9708)
+#define PCIE_MEEP_NTB_IEP_BAR23_CTRL_REG (0x970C)
+#define PCIE_MEEP_NTB_IEP_BAR45_CTRL_REG (0x9710)
+#define PCIE_MEEP_MSI_CTRL_ADDRESS_LOWER_REG (0x9714)
+#define PCIE_MEEP_MSI_CTRL_ADDRESS_UPPER_REG (0x9718)
+#define PCIE_MEEP_MSI_CTRL_INT_EN_REG (0x971C)
+#define PCIE_MEEP_MSI_CTRL_INT0_MASK_REG (0x9720)
+#define PCIE_MEEP_MSI_CTRL_INT_STATUS_REG (0x9724)
+#define PCIE_MEEP_DBI_RO_WR_EN_REG (0x9728)
+#define PCIE_MEEP_AXI_ERR_RESPONSE_REG (0x972C)
+
+
+
+typedef union tagMeepSbar23xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_0 : 12 ;
+ UINT32 sbar23xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar45xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_1 : 12 ;
+ UINT32 sbar45xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar23lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_2 : 12 ;
+ UINT32 sbar45limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar45lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_3 : 12 ;
+ UINT32 sbar45limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar45lmtUpper
+{
+
+ struct
+ {
+ UINT32 Reserved_4 : 12 ;
+ UINT32 sbar45limit_upper : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SBAR45LMT_UPPER_U;
+
+
+
+
+typedef union tagMeepCbdfSbdf
+{
+
+ struct
+ {
+ UINT32 sfunc : 3 ;
+ UINT32 sdev : 5 ;
+ UINT32 sbus : 8 ;
+ UINT32 cap_sfunc : 3 ;
+ UINT32 cap_sdev : 5 ;
+ UINT32 cap_sbus : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_CBDF_SBDF_U;
+
+
+
+
+typedef union tagMeepNtbCntl
+{
+
+ struct
+ {
+ UINT32 s_link_disable : 1 ;
+ UINT32 Reserved_6 : 1 ;
+ UINT32 eep_shadow_en : 1 ;
+ UINT32 Reserved_5 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_NTB_CNTL_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr0
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR0_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr1
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_10 : 5 ;
+ UINT32 Reserved_9 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_8 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_parity_error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR1_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr2
+{
+
+ struct
+ {
+ UINT32 revision_identification : 8 ;
+ UINT32 Reserved_11 : 8 ;
+ UINT32 sub_class : 8 ;
+ UINT32 baseclass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR2_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr3
+{
+
+ struct
+ {
+ UINT32 cache_line_size : 8 ;
+ UINT32 mstr_lat_tmr : 8 ;
+ UINT32 multi_function_device : 7 ;
+ UINT32 hdr_type : 1 ;
+ UINT32 bist : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR3_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr4
+{
+
+ struct
+ {
+ UINT32 sbar01_space_inicator : 1 ;
+ UINT32 sbar01_type : 2 ;
+ UINT32 sbar01_prefetchable : 1 ;
+ UINT32 sbar01_lower : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR4_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr6
+{
+
+ struct
+ {
+ UINT32 sbar23_space_inicator : 1 ;
+ UINT32 sbar23_type : 2 ;
+ UINT32 sbar23_prefetchable : 1 ;
+ UINT32 Reserved_12 : 8 ;
+ UINT32 sbar23_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR6_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr8
+{
+
+ struct
+ {
+ UINT32 sbar45_space_inicator : 1 ;
+ UINT32 sbar45_type : 2 ;
+ UINT32 sbar45_prefetchable : 1 ;
+ UINT32 Reserved_13 : 8 ;
+ UINT32 sbar45_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR8_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr11
+{
+
+ struct
+ {
+ UINT32 subsystem_vendor_id : 16 ;
+ UINT32 subsystemid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR11_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr13
+{
+
+ struct
+ {
+ UINT32 cap_ptr : 8 ;
+ UINT32 Reserved_14 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR13_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr15
+{
+
+ struct
+ {
+ UINT32 int_line : 8 ;
+ UINT32 int_pin : 8 ;
+ UINT32 Min_Grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR15_U;
+
+
+
+
+typedef union tagMeepPciMsiCap0
+{
+
+ struct
+ {
+ UINT32 msi_cap_id : 8 ;
+ UINT32 next_capability_pointer : 8 ;
+ UINT32 msi_enabled : 1 ;
+ UINT32 multiple_message_capable : 3 ;
+ UINT32 multiple_message_enabled : 3 ;
+ UINT32 msi_64_en : 1 ;
+ UINT32 pvm : 1 ;
+ UINT32 Reserved_18 : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_MSI_CAP0_U;
+
+
+
+
+typedef union tagMeepPciMsiCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_20 : 2 ;
+ UINT32 msi_addr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_MSI_CAP1_U;
+
+
+
+
+typedef union tagMeepPciMsiCap3
+{
+
+ struct
+ {
+ UINT32 msi_data : 16 ;
+ UINT32 Reserved_21 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCI_MSI_CAP3_U;
+
+
+
+
+typedef union tagMeepPcieCap0
+{
+
+ struct
+ {
+ UINT32 pcie_cap_id : 8 ;
+ UINT32 pcie_next_ptr : 8 ;
+ UINT32 pcie_capability_version : 4 ;
+ UINT32 device_port_type : 4 ;
+ UINT32 slot_implemented : 1 ;
+ UINT32 interrupt_message_number : 5 ;
+ UINT32 Reserved_22 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP0_U;
+
+
+
+
+typedef union tagMeepPcieCap1
+{
+
+ struct
+ {
+ UINT32 max_payload_size_supported : 3 ;
+ UINT32 phantom_function_supported : 2 ;
+ UINT32 extended_tagfield_supported : 1 ;
+ UINT32 endpoint_l0sacceptable_latency : 3 ;
+ UINT32 endpoint_l1acceptable_latency : 3 ;
+ UINT32 undefined : 3 ;
+ UINT32 Reserved_24 : 3 ;
+ UINT32 captured_slot_power_limit_value : 8 ;
+ UINT32 captured_slot_power_limit_scale : 2 ;
+ UINT32 function_level_reset : 1 ;
+ UINT32 dev_cap : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP1_U;
+
+
+
+
+typedef union tagMeepPcieCap2
+{
+
+ struct
+ {
+ UINT32 correctable_error_reporting_enable : 1 ;
+ UINT32 non_fatal_error_reporting_enable : 1 ;
+ UINT32 fatal_error_reporting_enable : 1 ;
+ UINT32 urenable : 1 ;
+ UINT32 enable_relaxed_ordering : 1 ;
+ UINT32 max_payload_size : 3 ;
+ UINT32 extended_tagfieldenable : 1 ;
+ UINT32 phantom_function_enable : 1 ;
+ UINT32 auxpowerpmenable : 1 ;
+ UINT32 enablenosnoop : 1 ;
+ UINT32 max_read_request_size : 3 ;
+ UINT32 Reserved_26 : 1 ;
+ UINT32 correctableerrordetected : 1 ;
+ UINT32 non_fatalerrordetected : 1 ;
+ UINT32 fatalerrordetected : 1 ;
+ UINT32 unsupportedrequestdetected : 1 ;
+ UINT32 auxpowerdetected : 1 ;
+ UINT32 transactionpending : 1 ;
+ UINT32 Reserved_25 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP2_U;
+
+
+
+
+typedef union tagMeepPcieCap3
+{
+
+ struct
+ {
+ UINT32 max_link_speed : 4 ;
+ UINT32 max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exitlatency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_27 : 1 ;
+ UINT32 port_number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagMeepPcieCap4
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_30 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_29 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_28 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagMeepPcieCap5
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpresent : 1 ;
+ UINT32 powercontrollerpresent : 1 ;
+ UINT32 mrlsensorpresent : 1 ;
+ UINT32 attentionindicatorpresent : 1 ;
+ UINT32 powerindicatorpresent : 1 ;
+ UINT32 hot_plugsurprise : 1 ;
+ UINT32 hot_plugcapable : 1 ;
+ UINT32 slotpowerlimitvalue : 8 ;
+ UINT32 slotpowerlimitscale : 2 ;
+ UINT32 electromechanicalinterlockpresen : 1 ;
+ UINT32 no_cmd_complete_support : 1 ;
+ UINT32 phy_slot_number : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP5_U;
+
+
+
+
+typedef union tagMeepPcieCap6
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpressedenable : 1 ;
+ UINT32 powerfaultdetectedenable : 1 ;
+ UINT32 mrlsensorchangedenable : 1 ;
+ UINT32 presencedetectchangedenable : 1 ;
+ UINT32 commandcompletedinterruptenable : 1 ;
+ UINT32 hot_pluginterruptenable : 1 ;
+ UINT32 attentionindicatorcontrol : 2 ;
+ UINT32 powerindicatorcontrol : 2 ;
+ UINT32 powercontrollercontrol : 1 ;
+ UINT32 electromechanicalinterlockcontrol : 1 ;
+ UINT32 datalinklayerstatechangedenable : 1 ;
+ UINT32 Reserved_31 : 3 ;
+ UINT32 attentionbuttonpressed : 1 ;
+ UINT32 powerfaultdetected : 1 ;
+ UINT32 mrlsensorchanged : 1 ;
+ UINT32 presencedetectchanged : 1 ;
+ UINT32 commandcompleted : 1 ;
+ UINT32 mrlsensorstate : 1 ;
+ UINT32 presencedetectstate : 1 ;
+ UINT32 electromechanicalinterlockstatus : 1 ;
+ UINT32 datalinklayerstatechanged : 1 ;
+ UINT32 slot_ctrl_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagMeepPcieCap7
+{
+
+ struct
+ {
+ UINT32 systemerroroncorrectableerrorenable : 1 ;
+ UINT32 systemerroronnon_fatalerrorenable : 1 ;
+ UINT32 systemerroronfatalerrorenable : 1 ;
+ UINT32 pmeinterruptenable : 1 ;
+ UINT32 crssoftwarevisibilityenable : 1 ;
+ UINT32 Reserved_32 : 11 ;
+ UINT32 crssoftwarevisibility : 1 ;
+ UINT32 root_cap : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagMeepPcieCap8
+{
+
+ struct
+ {
+ UINT32 pmerequesterid : 16 ;
+ UINT32 pmestatus : 1 ;
+ UINT32 pmepending : 1 ;
+ UINT32 root_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagMeepPcieCap9
+{
+
+ struct
+ {
+ UINT32 completiontimeoutrangessupported : 4 ;
+ UINT32 completiontimeoutdisablesupported : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoproutingsupported : 1 ;
+ UINT32 _2_bitatomicopcompletersupported : 1 ;
+ UINT32 _4_bitatomicopcompletersupported : 1 ;
+ UINT32 _28_bitcascompletersupported : 1 ;
+ UINT32 noro_enabledpr_prpassing : 1 ;
+ UINT32 Reserved_33 : 1 ;
+ UINT32 tphcompletersupported : 2 ;
+ UINT32 dev_cap2 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagMeepPcieCap10
+{
+
+ struct
+ {
+ UINT32 completiontimeoutvalue : 4 ;
+ UINT32 completiontimeoutdisable : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoprequesterenable : 1 ;
+ UINT32 atomicopegressblocking : 1 ;
+ UINT32 idorequestenable : 1 ;
+ UINT32 idocompletionenable : 1 ;
+ UINT32 dev_ctrl2 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagMeepPcieCap11
+{
+
+ struct
+ {
+ UINT32 Reserved_35 : 1 ;
+ UINT32 gen1_suport : 1 ;
+ UINT32 gen2_suport : 1 ;
+ UINT32 gen3_suport : 1 ;
+ UINT32 Reserved_34 : 4 ;
+ UINT32 crosslink_supported : 1 ;
+ UINT32 link_cap2 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagMeepPcieCap12
+{
+
+ struct
+ {
+ UINT32 targetlinkspeed : 4 ;
+ UINT32 entercompliance : 1 ;
+ UINT32 hardwareautonomousspeeddisa : 1 ;
+ UINT32 selectablede_empha : 1 ;
+ UINT32 transmitmargin : 3 ;
+ UINT32 _entermodifiedcompliance : 1 ;
+ UINT32 compliancesos : 1 ;
+ UINT32 de_emphasislevel : 4 ;
+ UINT32 currentde_emphasislevel : 1 ;
+ UINT32 equalizationcomplete : 1 ;
+ UINT32 equalizationphase1successful : 1 ;
+ UINT32 equalizationphase2successful : 1 ;
+ UINT32 equalizationphase3successful : 1 ;
+ UINT32 linkequalizationrequest : 1 ;
+ UINT32 link_ctrl2_status2 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagMeepSlotCap
+{
+
+ struct
+ {
+ UINT32 slotnumberingcapabilitiesid : 8 ;
+ UINT32 nextcapabilitypointer : 8 ;
+ UINT32 add_incardslotsprovided : 5 ;
+ UINT32 firstinchassis : 1 ;
+ UINT32 Reserved_36 : 2 ;
+ UINT32 slot_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SLOT_CAP_U;
+
+
+
+
+typedef union tagMeepAerCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 aer_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP0_U;
+
+
+
+
+typedef union tagMeepAerCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_42 : 1 ;
+ UINT32 Reserved_41 : 3 ;
+ UINT32 datalinkprotocolerrorsta : 1 ;
+ UINT32 surprisedownerrorstatus : 1 ;
+ UINT32 Reserved_40 : 6 ;
+ UINT32 poisonedtlpstatu : 1 ;
+ UINT32 flowcontrolprotocolerrorst : 1 ;
+ UINT32 completiontimeouts : 1 ;
+ UINT32 completerabortstatus : 1 ;
+ UINT32 receiveroverflowstatus : 1 ;
+ UINT32 malformedtlpstatus : 1 ;
+ UINT32 ecrcerrorstatus : 1 ;
+ UINT32 ecrcerrorstat : 1 ;
+ UINT32 unsupportedrequesterrorstatus : 1 ;
+ UINT32 Reserved_39 : 3 ;
+ UINT32 atomicopegressblockedstatus : 1 ;
+ UINT32 uncorr_err_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP1_U;
+
+
+
+
+typedef union tagMeepAerCap2
+{
+
+ struct
+ {
+ UINT32 Reserved_46 : 1 ;
+ UINT32 Reserved_45 : 3 ;
+ UINT32 datalinkprotocolerrormask : 1 ;
+ UINT32 surprisedownerrormask : 1 ;
+ UINT32 Reserved_44 : 6 ;
+ UINT32 poisonedtlpmask : 1 ;
+ UINT32 flowcontrolprotocolerrormask : 1 ;
+ UINT32 completiontimeoutmask : 1 ;
+ UINT32 completerabortmask : 1 ;
+ UINT32 unexpectedcompletionmask : 1 ;
+ UINT32 receiveroverflowmask : 1 ;
+ UINT32 malformedtlpmask : 1 ;
+ UINT32 ecrcerrormask : 1 ;
+ UINT32 unsupportedrequesterrormask : 1 ;
+ UINT32 Reserved_43 : 3 ;
+ UINT32 atomicopegressblockedmask : 1 ;
+ UINT32 uncorr_err_mask : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP2_U;
+
+
+
+
+typedef union tagMeepAerCap3
+{
+
+ struct
+ {
+ UINT32 Reserved_50 : 1 ;
+ UINT32 Reserved_49 : 3 ;
+ UINT32 datalinkprotocolerrorsever : 1 ;
+ UINT32 surprisedownerrorseverity : 1 ;
+ UINT32 Reserved_48 : 6 ;
+ UINT32 poisonedtlpseverity : 1 ;
+ UINT32 flowcontrolprotocolerrorseveri : 1 ;
+ UINT32 completiontimeoutseverity : 1 ;
+ UINT32 completerabortseverity : 1 ;
+ UINT32 unexpectedcompletionseverity : 1 ;
+ UINT32 receiveroverflowseverity : 1 ;
+ UINT32 malformedtlpseverity : 1 ;
+ UINT32 ecrcerrorseverity : 1 ;
+ UINT32 unsupportedrequesterrorseverity : 1 ;
+ UINT32 Reserved_47 : 3 ;
+ UINT32 atomicopegressblockedseverity : 1 ;
+ UINT32 uncorr_err_ser : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP3_U;
+
+
+
+
+typedef union tagMeepAerCap4
+{
+
+ struct
+ {
+ UINT32 receivererrorstatus : 1 ;
+ UINT32 Reserved_52 : 5 ;
+ UINT32 badtlpstatus : 1 ;
+ UINT32 baddllpstatus : 1 ;
+ UINT32 replay_numrolloverstatus : 1 ;
+ UINT32 Reserved_51 : 3 ;
+ UINT32 replytimertimeoutstatus : 1 ;
+ UINT32 advisorynon_fatalerrorstatus : 1 ;
+ UINT32 corr_err_status : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP4_U;
+
+
+
+
+typedef union tagMeepAerCap5
+{
+
+ struct
+ {
+ UINT32 receivererrormask : 1 ;
+ UINT32 Reserved_54 : 5 ;
+ UINT32 badtlpmask : 1 ;
+ UINT32 baddllpmask : 1 ;
+ UINT32 replay_numrollovermask : 1 ;
+ UINT32 Reserved_53 : 3 ;
+ UINT32 replytimertimeoutmask : 1 ;
+ UINT32 advisorynon_fatalerrormask : 1 ;
+ UINT32 corr_err_mask : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP5_U;
+
+
+
+
+typedef union tagMeepAerCap6
+{
+
+ struct
+ {
+ UINT32 firsterrorpointer : 5 ;
+ UINT32 ecrcgenerationcapability : 1 ;
+ UINT32 ecrcgenerationenable : 1 ;
+ UINT32 ecrccheckcapable : 1 ;
+ UINT32 ecrccheckenable : 1 ;
+ UINT32 adv_cap_ctrl : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP6_U;
+
+
+
+
+typedef union tagMeepAerCap11
+{
+
+ struct
+ {
+ UINT32 correctableerrorreportingenable : 1 ;
+ UINT32 non_fatalerrorreportingenable : 1 ;
+ UINT32 fatalerrorreportingenable : 1 ;
+ UINT32 root_err_cmd : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP11_U;
+
+
+
+
+typedef union tagMeepAerCap12
+{
+
+ struct
+ {
+ UINT32 err_correceived : 1 ;
+ UINT32 multipleerr_correceived : 1 ;
+ UINT32 err_fatal_nonfatalreceived : 1 ;
+ UINT32 multipleerr_fatal_nonfatalreceived : 1 ;
+ UINT32 firstuncorrectablefatal : 1 ;
+ UINT32 non_fatalerrormessagesreceived : 1 ;
+ UINT32 fatalerrormessagesreceived : 1 ;
+ UINT32 Reserved_57 : 20 ;
+ UINT32 root_err_status : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP12_U;
+
+
+
+
+typedef union tagMeepAerCap13
+{
+
+ struct
+ {
+ UINT32 err_corsourceidentification : 16 ;
+ UINT32 err_src_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_CAP13_U;
+
+
+
+
+typedef union tagMeepVcCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 vc_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP0_U;
+
+
+
+
+typedef union tagMeepVcCap1
+{
+
+ struct
+ {
+ UINT32 extendedvccount : 3 ;
+ UINT32 Reserved_60 : 1 ;
+ UINT32 lowpriorityextendedvccount : 3 ;
+ UINT32 Reserved_59 : 1 ;
+ UINT32 referenceclock : 2 ;
+ UINT32 portarbitrationtableentrysize : 2 ;
+ UINT32 vc_cap1 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP1_U;
+
+
+
+
+typedef union tagMeepVcCap2
+{
+
+ struct
+ {
+ UINT32 vcarbitrationcapability : 8 ;
+ UINT32 Reserved_61 : 16 ;
+ UINT32 vc_cap2 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP2_U;
+
+
+
+
+typedef union tagMeepVcCap3
+{
+
+ struct
+ {
+ UINT32 loadvcarbitrationtable : 1 ;
+ UINT32 vcarbitrationselect : 3 ;
+ UINT32 Reserved_63 : 12 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 Reserved_62 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP3_U;
+
+
+
+
+typedef union tagMeepVcCap4
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_66 : 6 ;
+ UINT32 Reserved_65 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_64 : 1 ;
+ UINT32 vc_res_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP4_U;
+
+
+
+
+typedef union tagMeepVcCap5
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_69 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselec : 3 ;
+ UINT32 Reserved_68 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_67 : 4 ;
+ UINT32 vc_res_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP5_U;
+
+
+
+
+typedef union tagMeepVcCap6
+{
+
+ struct
+ {
+ UINT32 Reserved_70 : 16 ;
+ UINT32 portarbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP6_U;
+
+
+
+
+typedef union tagMeepVcCap7
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_73 : 6 ;
+ UINT32 Reserved_72 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_71 : 1 ;
+ UINT32 vc_res_cap0 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP7_U;
+
+
+
+
+typedef union tagMeepVcCap8
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_76 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselect : 3 ;
+ UINT32 Reserved_75 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_74 : 4 ;
+ UINT32 vc_res_ctrl0 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP8_U;
+
+
+
+
+typedef union tagMeepVcCap9
+{
+
+ struct
+ {
+ UINT32 Reserved_77 : 16 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status0 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_VC_CAP9_U;
+
+
+
+
+typedef union tagMeepPortLogic0
+{
+
+ struct
+ {
+ UINT32 ack_lat_timer : 16 ;
+ UINT32 replay_timer : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagMeepPortLogic2
+{
+
+ struct
+ {
+ UINT32 linknumber : 8 ;
+ UINT32 Reserved_80 : 7 ;
+ UINT32 forcelink : 1 ;
+ UINT32 linkstate : 6 ;
+ UINT32 Reserved_79 : 2 ;
+ UINT32 port_force_link : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagMeepPortLogic3
+{
+
+ struct
+ {
+ UINT32 ackfrequency : 8 ;
+ UINT32 n_fts : 8 ;
+ UINT32 commonclockn_fts : 8 ;
+ UINT32 l0sentrancelatency : 3 ;
+ UINT32 l1entrancelatency : 3 ;
+ UINT32 enteraspml1withoutreceiveinl0s : 1 ;
+ UINT32 ack_aspm : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagMeepPortLogic4
+{
+
+ struct
+ {
+ UINT32 vendorspecificdllprequest : 1 ;
+ UINT32 scrambledisable : 1 ;
+ UINT32 loopbackenable : 1 ;
+ UINT32 resetassert : 1 ;
+ UINT32 Reserved_83 : 1 ;
+ UINT32 dlllinkenable : 1 ;
+ UINT32 Reserved_82 : 1 ;
+ UINT32 fastlinkmode : 1 ;
+ UINT32 Reserved_81 : 8 ;
+ UINT32 linkmodeenable : 6 ;
+ UINT32 crosslinkenable : 1 ;
+ UINT32 crosslinkactive : 1 ;
+ UINT32 port_link_ctrl : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagMeepPortLogic5
+{
+
+ struct
+ {
+ UINT32 insertlaneskewfortransmit : 24 ;
+ UINT32 flowcontroldisable : 1 ;
+ UINT32 ack_nakdisable : 1 ;
+ UINT32 Reserved_84 : 5 ;
+ UINT32 lane_skew : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagMeepPortLogic6
+{
+
+ struct
+ {
+ UINT32 numberoftssymbols : 4 ;
+ UINT32 Reserved_86 : 4 ;
+ UINT32 numberofskpsymbols : 3 ;
+ UINT32 Reserved_85 : 3 ;
+ UINT32 timermodifierforreplaytimer : 5 ;
+ UINT32 timermodifierforack_naklatencytimer : 5 ;
+ UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ;
+ UINT32 sym_num : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagMeepPortLogic7
+{
+
+ struct
+ {
+ UINT32 vc0posteddataqueuedepth : 11 ;
+ UINT32 Reserved_87 : 4 ;
+ UINT32 sym_timer : 1 ;
+ UINT32 maskfunctionmismatchfilteringfo : 1 ;
+ UINT32 maskpoisonedtlpfiltering : 1 ;
+ UINT32 maskbarmatchfiltering : 1 ;
+ UINT32 masktype1configurationrequestfiltering : 1 ;
+ UINT32 masklockedrequestfiltering : 1 ;
+ UINT32 masktagerrorrulesforreceivedcompletions : 1 ;
+ UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ;
+ UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ;
+ UINT32 maske_crcerror_filtering : 1 ;
+ UINT32 maske_crcerror_filtering_forcompletions : 1 ;
+ UINT32 message_control : 1 ;
+ UINT32 maskfilteringofreceived : 1 ;
+ UINT32 flt_mask1 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagMeepPortLogic8
+{
+
+ struct
+ {
+ UINT32 cx_flt_mask_venmsg0_drop : 1 ;
+ UINT32 cx_flt_mask_venmsg1_drop : 1 ;
+ UINT32 cx_flt_mask_dabort_4ucpl : 1 ;
+ UINT32 cx_flt_mask_handle_flush : 1 ;
+ UINT32 flt_mask2 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagMeepPortLogic9
+{
+
+ struct
+ {
+ UINT32 amba_multi_outbound_decomp_np : 1 ;
+ UINT32 amba_obnp_ctrl : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagMeepPortLogic12
+{
+
+ struct
+ {
+ UINT32 transmitposteddatafccredits : 12 ;
+ UINT32 transmitpostedheaderfccredits : 8 ;
+ UINT32 tx_pfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagMeepPortLogic13
+{
+
+ struct
+ {
+ UINT32 transmitnon_posteddatafccredits : 12 ;
+ UINT32 transmitnon_postedheaderfccredits : 8 ;
+ UINT32 tx_npfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagMeepPortLogic14
+{
+
+ struct
+ {
+ UINT32 transmitcompletiondatafccredits : 12 ;
+ UINT32 transmitcompletionheaderfccredits : 8 ;
+ UINT32 tx_cplfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagMeepPortLogic15
+{
+
+ struct
+ {
+ UINT32 rx_tlp_fc_credit_not_retured : 1 ;
+ UINT32 tx_retry_buf_not_empty : 1 ;
+ UINT32 rx_queue_not_empty : 1 ;
+ UINT32 Reserved_89 : 13 ;
+ UINT32 fc_latency_timer_override_value : 13 ;
+ UINT32 Reserved_88 : 2 ;
+ UINT32 fc_latency_timer_override_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagMeepPortLogic16
+{
+
+ struct
+ {
+ UINT32 vc0posteddatacredits : 12 ;
+ UINT32 vc0postedheadercredits : 8 ;
+ UINT32 Reserved_91 : 1 ;
+ UINT32 vc0_postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemo : 1 ;
+ UINT32 Reserved_90 : 6 ;
+ UINT32 tlptypeorderingforvc0 : 1 ;
+ UINT32 rx_pque_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagMeepPortLogic17
+{
+
+ struct
+ {
+ UINT32 vc0non_posteddatarcredits : 12 ;
+ UINT32 vc0non_postedheadercredits : 8 ;
+ UINT32 Reserved_93 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagMeepPortLogic18
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_credits : 12 ;
+ UINT32 vc0_cpl_header_credt : 8 ;
+ UINT32 Reserved_94 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagMeepPortLogic19
+{
+
+ struct
+ {
+ UINT32 vco_posted_data_que_path : 14 ;
+ UINT32 Reserved_95 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 vc_pbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagMeepPortLogic20
+{
+
+ struct
+ {
+ UINT32 vco_np_data_que_depth : 14 ;
+ UINT32 Reserved_97 : 2 ;
+ UINT32 vco_np_header_que_depth : 10 ;
+ UINT32 vc_npbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagMeepPortLogic21
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_queue_depth : 14 ;
+ UINT32 Reserved_99 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 Reserved_98 : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagMeepPortLogic22
+{
+
+ struct
+ {
+ UINT32 n_fts : 8 ;
+ UINT32 pre_determ_num_of_lane : 9 ;
+ UINT32 det_sp_change : 1 ;
+ UINT32 config_phy_tx_sw : 1 ;
+ UINT32 config_tx_comp_rcv_bit : 1 ;
+ UINT32 set_emp_level : 1 ;
+ UINT32 Reserved_100 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagMeepPortlogic25
+{
+
+ struct
+ {
+ UINT32 remote_rd_req_size : 3 ;
+ UINT32 Reserved_103 : 5 ;
+ UINT32 remote_max_brd_tag : 8 ;
+ UINT32 Reserved_102 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagMeepPortlogic26
+{
+
+ struct
+ {
+ UINT32 resize_master_resp_compser : 1 ;
+ UINT32 axi_ctrl1 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagMeepPortlogic55
+{
+
+ struct
+ {
+ UINT32 iatu1_type : 5 ;
+ UINT32 iatu1_tc : 3 ;
+ UINT32 iatu1_td : 1 ;
+ UINT32 iatu1_attr : 2 ;
+ UINT32 Reserved_107 : 5 ;
+ UINT32 iatu1_at : 2 ;
+ UINT32 Reserved_106 : 2 ;
+ UINT32 iatu1_id : 3 ;
+ UINT32 Reserved_105 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagMeepPortlogic56
+{
+
+ struct
+ {
+ UINT32 iatu2_type : 8 ;
+ UINT32 iatu2_bar_num : 3 ;
+ UINT32 Reserved_111 : 3 ;
+ UINT32 iatu2_tc_match_en : 1 ;
+ UINT32 iatu2_td_match_en : 1 ;
+ UINT32 iatu2_attr_match_en : 1 ;
+ UINT32 Reserved_110 : 1 ;
+ UINT32 iatu2_at_match_en : 1 ;
+ UINT32 iatu2_func_num_match_en : 1 ;
+ UINT32 iatu2_virtual_func_num_match_en : 1 ;
+ UINT32 message_code_match_en : 1 ;
+ UINT32 Reserved_109 : 2 ;
+ UINT32 iatu2_response_code : 2 ;
+ UINT32 Reserved_108 : 1 ;
+ UINT32 iatu2_fuzzy_type_match_mode : 1 ;
+ UINT32 iatu2_cfg_shift_mode : 1 ;
+ UINT32 iatu2_ivert_mode : 1 ;
+ UINT32 iatu2_match_mode : 1 ;
+ UINT32 iatu2_region_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagMeepPortlogic57
+{
+
+ struct
+ {
+ UINT32 iatu_start_low : 12 ;
+ UINT32 iatu_start_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagMeepPortlogic59
+{
+
+ struct
+ {
+ UINT32 iatu_limit_low : 12 ;
+ UINT32 iatu_limit_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagMeepPortlogic60
+{
+
+ struct
+ {
+ UINT32 xlated_addr_high : 12 ;
+ UINT32 xlated_addr_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagMeepPortlogic62
+{
+
+ struct
+ {
+ UINT32 dma_wr_eng_en : 1 ;
+ UINT32 dma_wr_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagMeepPortlogic63
+{
+
+ struct
+ {
+ UINT32 wr_doorbell_num : 3 ;
+ UINT32 Reserved_115 : 28 ;
+ UINT32 dma_wr_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagMeepPortlogic64
+{
+
+ struct
+ {
+ UINT32 dma_read_eng_en : 1 ;
+ UINT32 dma_rd_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagMeepPortlogic65
+{
+
+ struct
+ {
+ UINT32 rd_doorbell_num : 3 ;
+ UINT32 Reserved_117 : 28 ;
+ UINT32 dma_rd_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagMeepPortlogic66
+{
+
+ struct
+ {
+ UINT32 done_int_status : 1 ;
+ UINT32 Reserved_119 : 15 ;
+ UINT32 abort_int_status : 1 ;
+ UINT32 Reserved_118 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagMeepPortlogic67
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 1 ;
+ UINT32 Reserved_122 : 15 ;
+ UINT32 abort_int_mask : 1 ;
+ UINT32 Reserved_121 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagMeepPortlogic68
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 1 ;
+ UINT32 Reserved_125 : 15 ;
+ UINT32 abort_int_clr : 1 ;
+ UINT32 Reserved_124 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagMeepPortlogic69
+{
+
+ struct
+ {
+ UINT32 app_rd_err_det : 1 ;
+ UINT32 Reserved_127 : 15 ;
+ UINT32 ll_element_fetch_err_det : 1 ;
+ UINT32 Reserved_126 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagMeepPortlogic74
+{
+
+ struct
+ {
+ UINT32 dma_wr_c0_imwr_data : 16 ;
+ UINT32 dma_wr_c1_imwr_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagMeepPortlogic75
+{
+
+ struct
+ {
+ UINT32 wr_ch_ll_remote_abort_int_en : 1 ;
+ UINT32 Reserved_129 : 15 ;
+ UINT32 wr_ch_ll_local_abort_int_en : 1 ;
+ UINT32 Reserved_128 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagMeepPortlogic76
+{
+
+ struct
+ {
+ UINT32 done_int_status : 1 ;
+ UINT32 Reserved_132 : 15 ;
+ UINT32 abort_int_status : 1 ;
+ UINT32 Reserved_131 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagMeepPortlogic77
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 1 ;
+ UINT32 Reserved_134 : 15 ;
+ UINT32 abort_int_mask : 1 ;
+ UINT32 dma_rd_int_mask : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagMeepPortlogic78
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 1 ;
+ UINT32 Reserved_136 : 15 ;
+ UINT32 abort_int_clr : 1 ;
+ UINT32 dma_rd_int_clr : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagMeepPortlogic79
+{
+
+ struct
+ {
+ UINT32 app_wr_err_det : 1 ;
+ UINT32 Reserved_137 : 15 ;
+ UINT32 link_list_fetch_err_det : 1 ;
+ UINT32 dma_rd_err_low : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagMeepPortlogic80
+{
+
+ struct
+ {
+ UINT32 unspt_request : 8 ;
+ UINT32 completer_abort : 8 ;
+ UINT32 cpl_time_out : 8 ;
+ UINT32 data_poison : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagMeepPortlogic81
+{
+
+ struct
+ {
+ UINT32 remote_abort_int_en : 1 ;
+ UINT32 Reserved_139 : 15 ;
+ UINT32 local_abort_int_en : 1 ;
+ UINT32 dma_rd_ll_err_ena : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagMeepPortlogic86
+{
+
+ struct
+ {
+ UINT32 channel_dir : 3 ;
+ UINT32 Reserved_143 : 28 ;
+ UINT32 dma_ch_con_idx : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagMeepPortlogic87
+{
+
+ struct
+ {
+ UINT32 cycle_bit : 1 ;
+ UINT32 toggle_cycle_bit : 1 ;
+ UINT32 load_link_pointer : 1 ;
+ UINT32 local_int_en : 1 ;
+ UINT32 remote_int_en : 1 ;
+ UINT32 channel_status : 2 ;
+ UINT32 Reserved_147 : 1 ;
+ UINT32 consumer_cycle_state : 1 ;
+ UINT32 linked_list_en : 1 ;
+ UINT32 Reserved_146 : 2 ;
+ UINT32 func_num_dma : 5 ;
+ UINT32 Reserved_145 : 7 ;
+ UINT32 no_snoop : 1 ;
+ UINT32 ro : 1 ;
+ UINT32 td : 1 ;
+ UINT32 tc : 3 ;
+ UINT32 dma_ch_ctrl : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagMeepPortlogic93
+{
+
+ struct
+ {
+ UINT32 Reserved_150 : 2 ;
+ UINT32 dma_ll_ptr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PORTLOGIC93_U;
+
+
+
+
+typedef union tagMeepPbar23xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_151 : 12 ;
+ UINT32 PBAR23_Xlat_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_153 : 12 ;
+ UINT32 PBAR45_Xlat_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar23lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_154 : 12 ;
+ UINT32 PBAR23_Limit_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_155 : 12 ;
+ UINT32 PBAR45_Limit_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45lmtUpper
+{
+
+ struct
+ {
+ UINT32 Reserved_156 : 12 ;
+ UINT32 PBAR45_Limit_Upper : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR45LMT_UPPER_U;
+
+
+
+
+typedef union tagMeepB2bBar01xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_157 : 17 ;
+ UINT32 B2B_PBAR01_Xlat_Lower : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_B2B_BAR01XLAT_Lower_U;
+
+
+
+
+typedef union tagMeepPpd
+{
+
+ struct
+ {
+ UINT32 port_def : 1 ;
+ UINT32 Reserved_159 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PPD_U;
+
+
+
+
+typedef union tagMeepDeviceVendorId
+{
+
+ struct
+ {
+ UINT32 Vendor_ID : 16 ;
+ UINT32 Device_ID : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Device_Vendor_ID_U;
+
+
+
+
+typedef union tagMeepPcistsPcicmd
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 Interrupt_Disable : 1 ;
+ UINT32 Reserved_164 : 5 ;
+ UINT32 Reserved_163 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_162 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 Signaled_Target_Abort : 1 ;
+ UINT32 Received_Target_Abort : 1 ;
+ UINT32 Received_Master_Abort : 1 ;
+ UINT32 Signaled_System_Error : 1 ;
+ UINT32 Detected_Parity_Error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCISTS_PCICMD_U;
+
+
+
+
+typedef union tagMeepCcrRid
+{
+
+ struct
+ {
+ UINT32 revision_identification : 8 ;
+ UINT32 Reserved_165 : 8 ;
+ UINT32 sub_class : 8 ;
+ UINT32 baseclass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_CCR_RID_U;
+
+
+
+
+typedef union tagMeepPbar01BaseLower
+{
+
+ struct
+ {
+ UINT32 BAR01_Space_Inicator : 1 ;
+ UINT32 BAR01_Type : 2 ;
+ UINT32 BAR01_Prefetchable : 1 ;
+ UINT32 Reserved_166 : 13 ;
+ UINT32 base_address_register_01_lower : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR01_BASE_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar23BaseLower
+{
+
+ struct
+ {
+ UINT32 BAR23_Space_Inicator : 1 ;
+ UINT32 BAR23_Type : 2 ;
+ UINT32 BAR23_Prefetchable : 1 ;
+ UINT32 Reserved_168 : 8 ;
+ UINT32 Base_Address_Register_23_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR23_BASE_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45BaseLower
+{
+
+ struct
+ {
+ UINT32 BAR45_Space_Inicator : 1 ;
+ UINT32 BAR45_Type : 2 ;
+ UINT32 BAR45_Prefetchable : 1 ;
+ UINT32 Reserved_169 : 8 ;
+ UINT32 Base_Address_Register_45_Lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PBAR45_BASE_LOWER_U;
+
+
+
+
+typedef union tagMeepSubsystemid
+{
+
+ struct
+ {
+ UINT32 SubsystemID : 16 ;
+ UINT32 SubsystemVendorID : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_SubSystemId_U;
+
+
+
+
+typedef union tagMeepCapptr
+{
+
+ struct
+ {
+ UINT32 CapPtr : 8 ;
+ UINT32 Reserved_172 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_CapPtr_U;
+
+
+
+
+typedef union tagMeepInterrupt
+{
+
+ struct
+ {
+ UINT32 Interrupt_Line : 8 ;
+ UINT32 interrupt_pin : 8 ;
+ UINT32 min_grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Interrupt_U;
+
+
+
+
+typedef union tagMeepMsiCapabilityRegister
+{
+
+ struct
+ {
+ UINT32 CapabilityID : 8 ;
+ UINT32 Next_Capability_Pointer : 8 ;
+ UINT32 MSI_Enabled : 1 ;
+ UINT32 Multiple_Message_Capable : 3 ;
+ UINT32 Multiple_Message_Enabled : 3 ;
+ UINT32 MSI_64_EN : 1 ;
+ UINT32 PVM_EN : 1 ;
+ UINT32 Message_Control_Register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_Capability_Register_U;
+
+
+
+
+typedef union tagMeepMsiLower32Bitaddress
+{
+
+ struct
+ {
+ UINT32 Reserved_175 : 2 ;
+ UINT32 Lower32_bitAddress : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_Lower32_bitAddress_U;
+
+
+
+
+typedef union tagMeepMsiData
+{
+
+ struct
+ {
+ UINT32 MSI_Data : 16 ;
+ UINT32 Reserved_176 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_Data_U;
+
+
+
+
+typedef union tagMeepMsiMask
+{
+
+ struct
+ {
+ UINT32 MsiMask : 1 ;
+ UINT32 Reserved_177 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_MASK_U;
+
+
+
+
+typedef union tagMeepMsiPending
+{
+
+ struct
+ {
+ UINT32 MsiPending : 1 ;
+ UINT32 Reserved_178 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_Pending_U;
+
+
+
+
+typedef union tagMeepPcieCapabilityRegister
+{
+
+ struct
+ {
+ UINT32 Capability_ID : 8 ;
+ UINT32 Next_Capability_Pointer : 8 ;
+ UINT32 PCIE_Capability_Version : 4 ;
+ UINT32 Device_Port_Type : 4 ;
+ UINT32 Slot_Implemented : 1 ;
+ UINT32 Interrupt_Message_Number : 5 ;
+ UINT32 Reserved_179 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_PCIE_Capability_Register_U;
+
+
+
+
+typedef union tagMeepDeviceCapabilitiesRegister
+{
+
+ struct
+ {
+ UINT32 Max_Payload_Size_Supported : 3 ;
+ UINT32 Phantom_Function_Supported : 2 ;
+ UINT32 Extended_TagField_Supported : 1 ;
+ UINT32 Endpoint_L0sAcceptable_Latency : 3 ;
+ UINT32 Endpoint_L1Acceptable_Latency : 3 ;
+ UINT32 Undefined : 3 ;
+ UINT32 Reserved_182 : 3 ;
+ UINT32 Captured_Slot_Power_Limit_Value : 8 ;
+ UINT32 Captured_Slot_Power_Limit_Scale : 2 ;
+ UINT32 Function_Level_Reset : 1 ;
+ UINT32 Reserved_181 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Device_Capabilities_Register_U;
+
+
+
+
+typedef union tagMeepDeviceStatusRegister
+{
+
+ struct
+ {
+ UINT32 Correctable_Error_Reporting_Enable : 1 ;
+ UINT32 Non_Fatal_Error_Reporting_Enable : 1 ;
+ UINT32 Fatal_Error_Reporting_Enable : 1 ;
+ UINT32 UREnable : 1 ;
+ UINT32 Enable_Relaxed_Ordering : 1 ;
+ UINT32 Max_Payload_Size : 3 ;
+ UINT32 Extended_TagFieldEnable : 1 ;
+ UINT32 Phantom_Function_Enable : 1 ;
+ UINT32 AUXPowerPMEnable : 1 ;
+ UINT32 EnableNoSnoop : 1 ;
+ UINT32 Max_Read_Request_Size : 3 ;
+ UINT32 Reserved_184 : 1 ;
+ UINT32 CorrectableErrorDetected : 1 ;
+ UINT32 Non_FatalErrordetected : 1 ;
+ UINT32 FatalErrorDetected : 1 ;
+ UINT32 UnsupportedRequestDetected : 1 ;
+ UINT32 AuxPowerDetected : 1 ;
+ UINT32 TransactionPending : 1 ;
+ UINT32 Reserved_183 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Device_Status_Register_U;
+
+
+
+
+typedef union tagMeepLinkCapability
+{
+
+ struct
+ {
+ UINT32 Max_Link_Speed : 4 ;
+ UINT32 Max_Link_Width : 6 ;
+ UINT32 Active_State_Power_Management : 2 ;
+ UINT32 L0s_ExitLatency : 3 ;
+ UINT32 L1_Exit_Latency : 3 ;
+ UINT32 Clock_Power_Management : 1 ;
+ UINT32 Surprise_Down_Error_Report_Cap : 1 ;
+ UINT32 Data_Link_Layer_Active_Report_Cap : 1 ;
+ UINT32 Link_Bandwidth_Noti_Cap : 1 ;
+ UINT32 ASPM_Option_Compliance : 1 ;
+ UINT32 Reserved_185 : 1 ;
+ UINT32 Port_Number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Link_Capability_U;
+
+
+
+
+typedef union tagMeepLinkControlStatus
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_188 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_187 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_186 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Link_Control_Status_U;
+
+
+
+
+typedef union tagMeepAerCapHeader
+{
+
+ struct
+ {
+ UINT32 PCIE_Extended_Capability_ID : 16 ;
+ UINT32 Capability_Version : 4 ;
+ UINT32 Next_Capability_Offset : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AER_Cap_header_U;
+
+
+
+
+typedef union tagMeepUcErrorStatus
+{
+
+ struct
+ {
+ UINT32 Reserved_193 : 1 ;
+ UINT32 Reserved_192 : 3 ;
+ UINT32 DataLinkProtocolErrorStatus : 1 ;
+ UINT32 SurpriseDownErrorStatus : 1 ;
+ UINT32 Reserved_191 : 6 ;
+ UINT32 PoisonedTLPStatus : 1 ;
+ UINT32 FlowControlProtocolErrorStatus : 1 ;
+ UINT32 CompletionTimeoutStatus : 1 ;
+ UINT32 CompleterAbortStatus : 1 ;
+ UINT32 UnexpectedCompletionStatus : 1 ;
+ UINT32 ReceiverOverflowStatus : 1 ;
+ UINT32 MalformedTLPStatus : 1 ;
+ UINT32 ECRCErrorStatus : 1 ;
+ UINT32 UnsupportedRequestErrorStatus : 1 ;
+ UINT32 Reserved_190 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_UC_Error_Status_U;
+
+
+
+
+typedef union tagMeepUcErrorMask
+{
+
+ struct
+ {
+ UINT32 Reserved_197 : 1 ;
+ UINT32 Reserved_196 : 3 ;
+ UINT32 DataLinkProtocolErrorMask : 1 ;
+ UINT32 SurpriseDownErrorMask : 1 ;
+ UINT32 Reserved_195 : 6 ;
+ UINT32 PoisonedTLPMask : 1 ;
+ UINT32 FlowControlProtocolErrorMask : 1 ;
+ UINT32 CompletionTimeoutMask : 1 ;
+ UINT32 CompleterAbortMask : 1 ;
+ UINT32 UnexpectedCompletionMask : 1 ;
+ UINT32 ReceiverOverflowMask : 1 ;
+ UINT32 MalformedTLPMask : 1 ;
+ UINT32 ECRCErrorMask : 1 ;
+ UINT32 UnsupportedRequestErrorMask : 1 ;
+ UINT32 Reserved_194 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_UC_Error_Mask_U;
+
+
+
+
+typedef union tagMeepUcErrorSeverity
+{
+
+ struct
+ {
+ UINT32 Reserved_201 : 1 ;
+ UINT32 Reserved_200 : 3 ;
+ UINT32 DataLinkProtocolErrorSeverity : 1 ;
+ UINT32 SurpriseDownErrorSeverity : 1 ;
+ UINT32 Reserved_199 : 6 ;
+ UINT32 PoisonedTLPSeverity : 1 ;
+ UINT32 FlowControlProtocolErrorSeverity : 1 ;
+ UINT32 CompletionTimeoutSeverity : 1 ;
+ UINT32 CompleterAbortSeverity : 1 ;
+ UINT32 UnexpectedCompletionSeverity : 1 ;
+ UINT32 ReceiverOverflowSeverity : 1 ;
+ UINT32 MalformedTLPSeverity : 1 ;
+ UINT32 ECRCErrorSeverity : 1 ;
+ UINT32 UnsupportedRequestErrorSeverity : 1 ;
+ UINT32 Reserved_198 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_UC_Error_Severity_U;
+
+
+
+
+typedef union tagMeepCErrorStatus
+{
+
+ struct
+ {
+ UINT32 Receiver_Error_Status : 1 ;
+ UINT32 Reserved_204 : 5 ;
+ UINT32 Bad_TLP_Status : 1 ;
+ UINT32 Bad_DLLP_Status : 1 ;
+ UINT32 REPLAY_NUM_Rollover_Status : 1 ;
+ UINT32 Reserved_203 : 3 ;
+ UINT32 Replay_Timer_Timeout_Status : 1 ;
+ UINT32 Advisory_Non_Fatal_Error_Status : 1 ;
+ UINT32 Reserved_202 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_C_Error_Status_U;
+
+
+
+
+typedef union tagMeepCErrorMask
+{
+
+ struct
+ {
+ UINT32 Receiver_Error_Mask : 1 ;
+ UINT32 Reserved_207 : 5 ;
+ UINT32 Bad_TLP_Mask : 1 ;
+ UINT32 Bad_DLLP_Mask : 1 ;
+ UINT32 REPLAY_NUMRollover_Mask : 1 ;
+ UINT32 Reserved_206 : 3 ;
+ UINT32 Replay_Timer_Timeout_Mask : 1 ;
+ UINT32 Advisory_Non_Fatal_Error_Mask : 1 ;
+ UINT32 Reserved_205 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_C_Error_Mask_U;
+
+
+
+
+typedef union tagMeepAdvancedErrorCapabilitiesAndControl
+{
+
+ struct
+ {
+ UINT32 First_Error_Pointer : 5 ;
+ UINT32 ECRC_Generation_Capability : 1 ;
+ UINT32 ECRC_Generation_Enable : 1 ;
+ UINT32 ECRC_Check_Capable : 1 ;
+ UINT32 ECRC_Check_Enable : 1 ;
+ UINT32 Reserved_209 : 2 ;
+ UINT32 TLP_Prefix_Log_Present : 1 ;
+ UINT32 Reserved_208 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_Advanced_Error_Capabilities_and_Control_U;
+
+
+
+
+typedef union tagMeepNtbIepBar01Ctrl
+{
+
+ struct
+ {
+ UINT32 bar01_type : 5 ;
+ UINT32 bar01_tc : 3 ;
+ UINT32 bar01_td : 1 ;
+ UINT32 bar01_attr : 2 ;
+ UINT32 Reserved_213 : 5 ;
+ UINT32 bar01_at : 2 ;
+ UINT32 bar01_match_en : 1 ;
+ UINT32 Reserved_212 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_NTB_IEP_BAR01_CTRL_U;
+
+
+
+
+typedef union tagMeepNtbIepBar23Ctrl
+{
+
+ struct
+ {
+ UINT32 bar23_type : 5 ;
+ UINT32 bar23_tc : 3 ;
+ UINT32 bar23_td : 1 ;
+ UINT32 bar23_attr : 2 ;
+ UINT32 Reserved_215 : 5 ;
+ UINT32 bar23_at : 2 ;
+ UINT32 bar23_match_en : 1 ;
+ UINT32 Reserved_214 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_NTB_IEP_BAR23_CTRL_U;
+
+
+
+
+typedef union tagMeepNtbIepBar45Ctrl
+{
+
+ struct
+ {
+ UINT32 bar45_type : 5 ;
+ UINT32 bar45_tc : 3 ;
+ UINT32 bar45_td : 1 ;
+ UINT32 bar45_attr : 2 ;
+ UINT32 Reserved_217 : 5 ;
+ UINT32 bar45_at : 2 ;
+ UINT32 bar45_match_en : 1 ;
+ UINT32 Reserved_216 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_NTB_IEP_BAR45_CTRL_U;
+
+
+
+
+typedef union tagMeepMsiCtrlIntEn
+{
+
+ struct
+ {
+ UINT32 msi_int_en : 1 ;
+ UINT32 Reserved_218 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_CTRL_INT_EN_U;
+
+
+
+
+typedef union tagMeepMsiCtrlInt0Mask
+{
+
+ struct
+ {
+ UINT32 msi_int_mask : 1 ;
+ UINT32 Reserved_219 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_CTRL_INT0_MASK_U;
+
+
+
+
+typedef union tagMeepMsiCtrlIntStatus
+{
+
+ struct
+ {
+ UINT32 msi_int : 1 ;
+ UINT32 Reserved_220 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_MSI_CTRL_INT_STATUS_U;
+
+
+
+
+typedef union tagMeepDbiRoWrEn
+{
+
+ struct
+ {
+ UINT32 dbi_ro_wr_en : 1 ;
+ UINT32 Reserved_221 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_DBI_RO_WR_EN_U;
+
+
+
+
+typedef union tagAxiErrResponse
+{
+
+ struct
+ {
+ UINT32 err_resp_mode : 4 ;
+ UINT32 Reserved_222 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MEEP_AXI_ERR_RESPONSE_U;
+
+
+
+
+
+
+
+#define PCIE_MIEP_PBAR23XLAT_LOWER_REG (0x0)
+#define PCIE_MIEP_PBAR23XLAT_UPPER_REG (0x4)
+#define PCIE_MIEP_PBAR45XLAT_LOWER_REG (0x8)
+#define PCIE_MIEP_PBAR45XLAT_UPPER_REG (0xC)
+#define PCIE_MIEP_PBAR23LMT_LOWER_REG (0x10)
+#define PCIE_MIEP_PBAR23LMT_UPPER_REG (0x14)
+#define PCIE_MIEP_PBAR45LMT_LOWER_REG (0x18)
+#define PCIE_MIEP_PBAR45LMT_UPPER_REG (0x1C)
+#define PCIE_MIEP_PDOORBELL_REG (0x20)
+#define PCIE_MIEP_PDOORBELL_MASK_REG (0x24)
+#define PCIE_MIEP_B2B_BAR01XLAT_LOWER_REG (0x28)
+#define PCIE_MIEP_B2B_BAR01XLAT_UPPER_REG (0x2C)
+#define PCIE_MIEP_B2BDOORBELL_REG (0x30)
+#define PCIE_MIEP_SPAD0_REG (0x38)
+#define PCIE_MIEP_SPAD1_REG (0x3C)
+#define PCIE_MIEP_SPAD2_REG (0x40)
+#define PCIE_MIEP_SPAD3_REG (0x44)
+#define PCIE_MIEP_SPAD4_REG (0x48)
+#define PCIE_MIEP_SPAD5_REG (0x4C)
+#define PCIE_MIEP_SPAD6_REG (0x50)
+#define PCIE_MIEP_SPAD7_REG (0x54)
+#define PCIE_MIEP_SPAD8_REG (0x58)
+#define PCIE_MIEP_SPAD9_REG (0x5C)
+#define PCIE_MIEP_SPAD10_REG (0x60)
+#define PCIE_MIEP_SPAD11_REG (0x64)
+#define PCIE_MIEP_SPAD12_REG (0x68)
+#define PCIE_MIEP_SPAD13_REG (0x6C)
+#define PCIE_MIEP_SPAD14_REG (0x70)
+#define PCIE_MIEP_SPAD15_REG (0x74)
+#define PCIE_MIEP_SPAD16_REG (0x78)
+#define PCIE_MIEP_SPAD17_REG (0x7C)
+#define PCIE_MIEP_SPAD18_REG (0x80)
+#define PCIE_MIEP_SPAD19_REG (0x84)
+#define PCIE_MIEP_SPAD20_REG (0x88)
+#define PCIE_MIEP_SPAD21_REG (0x8C)
+#define PCIE_MIEP_SPAD22_REG (0x90)
+#define PCIE_MIEP_SPAD23_REG (0x94)
+#define PCIE_MIEP_SPAD24_REG (0x98)
+#define PCIE_MIEP_SPAD25_REG (0x9C)
+#define PCIE_MIEP_SPAD26_REG (0xA0)
+#define PCIE_MIEP_SPAD27_REG (0xA4)
+#define PCIE_MIEP_SPAD28_REG (0xA8)
+#define PCIE_MIEP_SPAD29_REG (0xAC)
+#define PCIE_MIEP_SPAD30_REG (0xB0)
+#define PCIE_MIEP_SPAD31_REG (0xB4)
+#define PCIE_MIEP_B2BSPAD0_REG (0xB8)
+#define PCIE_MIEP_B2BSPAD1_REG (0xBC)
+#define PCIE_MIEP_B2BSPAD2_REG (0xC0)
+#define PCIE_MIEP_B2BSPAD3_REG (0xC4)
+#define PCIE_MIEP_B2BSPAD4_REG (0xC8)
+#define PCIE_MIEP_B2BSPAD5_REG (0xCC)
+#define PCIE_MIEP_B2BSPAD6_REG (0xD0)
+#define PCIE_MIEP_B2BSPAD7_REG (0xD4)
+#define PCIE_MIEP_B2BSPAD8_REG (0xD8)
+#define PCIE_MIEP_B2BSPAD9_REG (0xDC)
+#define PCIE_MIEP_B2BSPAD10_REG (0xE0)
+#define PCIE_MIEP_B2BSPAD11_REG (0xE4)
+#define PCIE_MIEP_B2BSPAD12_REG (0xE8)
+#define PCIE_MIEP_B2BSPAD13_REG (0xEC)
+#define PCIE_MIEP_B2BSPAD14_REG (0xF0)
+#define PCIE_MIEP_B2BSPAD15_REG (0xF4)
+#define PCIE_MIEP_B2BSPAD16_REG (0xF8)
+#define PCIE_MIEP_B2BSPAD17_REG (0xFC)
+#define PCIE_MIEP_B2BSPAD18_REG (0x100)
+#define PCIE_MIEP_B2BSPAD19_REG (0x104)
+#define PCIE_MIEP_B2BSPAD20_REG (0x108)
+#define PCIE_MIEP_B2BSPAD21_REG (0x10C)
+#define PCIE_MIEP_B2BSPAD22_REG (0x110)
+#define PCIE_MIEP_B2BSPAD23_REG (0x114)
+#define PCIE_MIEP_B2BSPAD24_REG (0x118)
+#define PCIE_MIEP_B2BSPAD25_REG (0x11C)
+#define PCIE_MIEP_B2BSPAD26_REG (0x120)
+#define PCIE_MIEP_B2BSPAD27_REG (0x124)
+#define PCIE_MIEP_B2BSPAD28_REG (0x128)
+#define PCIE_MIEP_B2BSPAD29_REG (0x12C)
+#define PCIE_MIEP_B2BSPAD30_REG (0x130)
+#define PCIE_MIEP_B2BSPAD31_REG (0x134)
+#define PCIE_MIEP_PPD_REG (0x138)
+#define PCIE_MIEP_P_DEVICE_VENDOR_ID_REG (0x1000)
+#define PCIE_MIEP_P_PCISTS_PCICMD_REG (0x1004)
+#define PCIE_MIEP_P_CCR_RID_REG (0x1008)
+#define PCIE_MIEP_P_BIST_TYPE_REG (0x100C)
+#define PCIE_MIEP_PBAR01_BASE_LOWER_REG (0x1010)
+#define PCIE_MIEP_PBAR01_BASE_UPPER_REG (0x1014)
+#define PCIE_MIEP_PBAR23_BASE_LOWER_REG (0x1018)
+#define PCIE_MIEP_PBAR23_BASE_UPPER_REG (0x101C)
+#define PCIE_MIEP_PBAR45_BASE_LOWER_REG (0x1020)
+#define PCIE_MIEP_PBAR45_BASE_UPPER_REG (0x1024)
+#define PCIE_MIEP_P_SUBSYSTEMID_REG (0x102C)
+#define PCIE_MIEP_P_INTERRUPT_REG (0x103C)
+#define PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_REG (0x1054)
+#define PCIE_MIEP_P_MSI_UPPER32_BIT_ADDRESS_REG (0x1058)
+#define PCIE_MIEP_P_LINK_CAPABILITY_REG (0x107C)
+#define PCIE_MIEP_P_AER_CAP_HEADER_REG (0x1100)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_1_REG (0x111C)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_2_REG (0x1120)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_3_REG (0x1124)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_4_REG (0x1128)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_1_REG (0x1130)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_2_REG (0x1134)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_3_REG (0x1138)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_4_REG (0x113C)
+#define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_LOWER_REG (0x1700)
+#define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_UPPER_REG (0x1704)
+#define PCIE_MIEP_P_MSI_CTRL_ADDRESS_LOWER_REG (0x1714)
+#define PCIE_MIEP_P_MSI_CTRL_ADDRESS_UPPER_REG (0x1718)
+#define PCIE_MIEP_SBAR23XLAT_LOWER_REG (0x8000)
+#define PCIE_MIEP_SBAR23XLAT_UPPER_REG (0x8004)
+#define PCIE_MIEP_SBAR45XLAT_LOWER_REG (0x8008)
+#define PCIE_MIEP_SBAR45XLAT_UPPER_REG (0x800C)
+#define PCIE_MIEP_SBAR23LMT_LOWER_REG (0x8010)
+#define PCIE_MIEP_SBAR23LMT_UPPER_REG (0x8014)
+#define PCIE_MIEP_SBAR45LMT_LOWER_REG (0x8018)
+#define PCIE_MIEP_SBAR45LMT_UPPER_REG (0x801C)
+#define PCIE_MIEP_SDOORBELL_REG (0x8020)
+#define PCIE_MIEP_SDOORBELL_MASK_REG (0x8024)
+#define PCIE_MIEP_CBDF_SBDF_REG (0x8028)
+#define PCIE_MIEP_PCI_CFG_HDR0_REG (0x9000)
+#define PCIE_MIEP_PCI_CFG_HDR1_REG (0x9004)
+#define PCIE_MIEP_PCI_CFG_HDR9_REG (0x9024)
+#define PCIE_MIEP_PCI_CFG_HDR10_REG (0x9028)
+#define PCIE_MIEP_PCI_CFG_HDR11_REG (0x902C)
+#define PCIE_MIEP_PCI_CFG_HDR12_REG (0x9030)
+#define PCIE_MIEP_PCI_CFG_HDR13_REG (0x9034)
+#define PCIE_MIEP_PCI_CFG_HDR14_REG (0x9038)
+#define PCIE_MIEP_PCI_CFG_HDR15_REG (0x903C)
+#define PCIE_MIEP_PCI_PM_CAP0_REG (0x9040)
+#define PCIE_MIEP_PCI_PM_CAP1_REG (0x9044)
+#define PCIE_MIEP_PCI_MSI_CAP0_REG (0x9050)
+#define PCIE_MIEP_PCI_MSI_CAP1_REG (0x9054)
+#define PCIE_MIEP_PCI_MSI_CAP2_REG (0x9058)
+#define PCIE_MIEP_PCI_MSI_CAP3_REG (0x905C)
+#define PCIE_MIEP_PCIE_CAP0_REG (0x9070)
+#define PCIE_MIEP_PCIE_CAP1_REG (0x9074)
+#define PCIE_MIEP_PCIE_CAP2_REG (0x9078)
+#define PCIE_MIEP_PCIE_CAP3_REG (0x907C)
+#define PCIE_MIEP_PCIE_CAP4_REG (0x9080)
+#define PCIE_MIEP_PCIE_CAP5_REG (0x9084)
+#define PCIE_MIEP_PCIE_CAP6_REG (0x9088)
+#define PCIE_MIEP_PCIE_CAP7_REG (0x908C)
+#define PCIE_MIEP_PCIE_CAP8_REG (0x9090)
+#define PCIE_MIEP_PCIE_CAP9_REG (0x9094)
+#define PCIE_MIEP_PCIE_CAP10_REG (0x9098)
+#define PCIE_MIEP_PCIE_CAP11_REG (0x909C)
+#define PCIE_MIEP_PCIE_CAP12_REG (0x90A0)
+#define PCIE_MIEP_SLOT_CAP_REG (0x90C0)
+#define PCIE_MIEP_AER_CAP0_REG (0x9100)
+#define PCIE_MIEP_AER_CAP1_REG (0x9104)
+#define PCIE_MIEP_AER_CAP2_REG (0x9108)
+#define PCIE_MIEP_AER_CAP3_REG (0x910C)
+#define PCIE_MIEP_AER_CAP4_REG (0x9110)
+#define PCIE_MIEP_AER_CAP5_REG (0x9114)
+#define PCIE_MIEP_AER_CAP6_REG (0x9118)
+#define PCIE_MIEP_AER_CAP7_REG (0x911C)
+#define PCIE_MIEP_AER_CAP8_REG (0x9120)
+#define PCIE_MIEP_AER_CAP9_REG (0x9124)
+#define PCIE_MIEP_AER_CAP10_REG (0x9128)
+#define PCIE_MIEP_AER_CAP11_REG (0x912C)
+#define PCIE_MIEP_AER_CAP12_REG (0x9130)
+#define PCIE_MIEP_AER_CAP13_REG (0x9134)
+#define PCIE_MIEP_VC_CAP0_REG (0x9140)
+#define PCIE_MIEP_VC_CAP1_REG (0x9144)
+#define PCIE_MIEP_VC_CAP2_REG (0x9148)
+#define PCIE_MIEP_VC_CAP3_REG (0x914C)
+#define PCIE_MIEP_VC_CAP4_REG (0x9150)
+#define PCIE_MIEP_VC_CAP5_REG (0x9154)
+#define PCIE_MIEP_VC_CAP6_REG (0x9158)
+#define PCIE_MIEP_VC_CAP7_REG (0x915C)
+#define PCIE_MIEP_VC_CAP8_REG (0x9160)
+#define PCIE_MIEP_VC_CAP9_REG (0x9164)
+#define PCIE_MIEP_PORT_LOGIC0_REG (0x9700)
+#define PCIE_MIEP_PORT_LOGIC1_REG (0x9704)
+#define PCIE_MIEP_PORT_LOGIC2_REG (0x9708)
+#define PCIE_MIEP_PORT_LOGIC3_REG (0x970C)
+#define PCIE_MIEP_PORT_LOGIC4_REG (0x9710)
+#define PCIE_MIEP_PORT_LOGIC5_REG (0x9714)
+#define PCIE_MIEP_PORT_LOGIC6_REG (0x9718)
+#define PCIE_MIEP_PORT_LOGIC7_REG (0x971C)
+#define PCIE_MIEP_PORT_LOGIC8_REG (0x9720)
+#define PCIE_MIEP_PORT_LOGIC9_REG (0x9724)
+#define PCIE_MIEP_PORT_LOGIC10_REG (0x9728)
+#define PCIE_MIEP_PORT_LOGIC11_REG (0x972C)
+#define PCIE_MIEP_PORT_LOGIC12_REG (0x9730)
+#define PCIE_MIEP_PORT_LOGIC13_REG (0x9734)
+#define PCIE_MIEP_PORT_LOGIC14_REG (0x9738)
+#define PCIE_MIEP_PORT_LOGIC15_REG (0x973C)
+#define PCIE_MIEP_PORT_LOGIC16_REG (0x9748)
+#define PCIE_MIEP_PORT_LOGIC17_REG (0x974C)
+#define PCIE_MIEP_PORT_LOGIC18_REG (0x9750)
+#define PCIE_MIEP_PORT_LOGIC19_REG (0x97A8)
+#define PCIE_MIEP_PORT_LOGIC20_REG (0x97AC)
+#define PCIE_MIEP_PORT_LOGIC21_REG (0x97B0)
+#define PCIE_MIEP_PORT_LOGIC22_REG (0x980C)
+#define PCIE_MIEP_PORTLOGIC23_REG (0x9810)
+#define PCIE_MIEP_PORTLOGIC24_REG (0x9814)
+#define PCIE_MIEP_PORTLOGIC25_REG (0x9818)
+#define PCIE_MIEP_PORTLOGIC26_REG (0x981C)
+#define PCIE_MIEP_PORTLOGIC27_REG (0x9820)
+#define PCIE_MIEP_PORTLOGIC28_REG (0x9824)
+#define PCIE_MIEP_PORTLOGIC29_REG (0x9828)
+#define PCIE_MIEP_PORTLOGIC30_REG (0x982C)
+#define PCIE_MIEP_PORTLOGIC31_REG (0x9830)
+#define PCIE_MIEP_PORTLOGIC32_REG (0x9834)
+#define PCIE_MIEP_PORTLOGIC33_REG (0x9838)
+#define PCIE_MIEP_PORTLOGIC34_REG (0x983C)
+#define PCIE_MIEP_PORTLOGIC35_REG (0x9840)
+#define PCIE_MIEP_PORTLOGIC36_REG (0x9844)
+#define PCIE_MIEP_PORTLOGIC37_REG (0x9848)
+#define PCIE_MIEP_PORTLOGIC38_REG (0x984C)
+#define PCIE_MIEP_PORTLOGIC39_REG (0x9850)
+#define PCIE_MIEP_PORTLOGIC40_REG (0x9854)
+#define PCIE_MIEP_PORTLOGIC41_REG (0x9858)
+#define PCIE_MIEP_PORTLOGIC42_REG (0x985C)
+#define PCIE_MIEP_PORTLOGIC43_REG (0x9860)
+#define PCIE_MIEP_PORTLOGIC44_REG (0x9864)
+#define PCIE_MIEP_PORTLOGIC45_REG (0x9868)
+#define PCIE_MIEP_PORTLOGIC46_REG (0x986C)
+#define PCIE_MIEP_PORTLOGIC47_REG (0x9870)
+#define PCIE_MIEP_PORTLOGIC48_REG (0x9874)
+#define PCIE_MIEP_PORTLOGIC49_REG (0x9878)
+#define PCIE_MIEP_PORTLOGIC50_REG (0x987C)
+#define PCIE_MIEP_PORTLOGIC51_REG (0x9880)
+#define PCIE_MIEP_PORTLOGIC52_REG (0x9884)
+#define PCIE_MIEP_PORTLOGIC53_REG (0x9888)
+#define PCIE_MIEP_PORTLOGIC54_REG (0x9900)
+#define PCIE_MIEP_PORTLOGIC55_REG (0x9904)
+#define PCIE_MIEP_PORTLOGIC56_REG (0x9908)
+#define PCIE_MIEP_PORTLOGIC57_REG (0x990C)
+#define PCIE_MIEP_PORTLOGIC58_REG (0x9910)
+#define PCIE_MIEP_PORTLOGIC59_REG (0x9914)
+#define PCIE_MIEP_PORTLOGIC60_REG (0x9918)
+#define PCIE_MIEP_PORTLOGIC61_REG (0x991C)
+#define PCIE_MIEP_PORTLOGIC62_REG (0x997C)
+#define PCIE_MIEP_PORTLOGIC63_REG (0x9980)
+#define PCIE_MIEP_PORTLOGIC64_REG (0x999C)
+#define PCIE_MIEP_PORTLOGIC65_REG (0x99A0)
+#define PCIE_MIEP_PORTLOGIC66_REG (0x99BC)
+#define PCIE_MIEP_PORTLOGIC67_REG (0x99C4)
+#define PCIE_MIEP_PORTLOGIC68_REG (0x99C8)
+#define PCIE_MIEP_PORTLOGIC69_REG (0x99CC)
+#define PCIE_MIEP_PORTLOGIC70_REG (0x99D0)
+#define PCIE_MIEP_PORTLOGIC71_REG (0x99D4)
+#define PCIE_MIEP_PORTLOGIC72_REG (0x99D8)
+#define PCIE_MIEP_PORTLOGIC73_REG (0x99DC)
+#define PCIE_MIEP_PORTLOGIC74_REG (0x99E0)
+#define PCIE_MIEP_PORTLOGIC75_REG (0x9A00)
+#define PCIE_MIEP_PORTLOGIC76_REG (0x9A10)
+#define PCIE_MIEP_PORTLOGIC77_REG (0x9A18)
+#define PCIE_MIEP_PORTLOGIC78_REG (0x9A1C)
+#define PCIE_MIEP_PORTLOGIC79_REG (0x9A24)
+#define PCIE_MIEP_PORTLOGIC80_REG (0x9A28)
+#define PCIE_MIEP_PORTLOGIC81_REG (0x9A34)
+#define PCIE_MIEP_PORTLOGIC82_REG (0x9A3C)
+#define PCIE_MIEP_PORTLOGIC83_REG (0x9A40)
+#define PCIE_MIEP_PORTLOGIC84_REG (0x9A44)
+#define PCIE_MIEP_PORTLOGIC85_REG (0x9A48)
+#define PCIE_MIEP_PORTLOGIC86_REG (0x9A6C)
+#define PCIE_MIEP_PORTLOGIC87_REG (0x9A70)
+#define PCIE_MIEP_PORTLOGIC88_REG (0x9A78)
+#define PCIE_MIEP_PORTLOGIC89_REG (0x9A7C)
+#define PCIE_MIEP_PORTLOGIC90_REG (0x9A80)
+#define PCIE_MIEP_PORTLOGIC91_REG (0x9A84)
+#define PCIE_MIEP_PORTLOGIC92_REG (0x9A88)
+#define PCIE_MIEP_PORTLOGIC93_REG (0x9A8C)
+#define PCIE_MIEP_PORTLOGIC94_REG (0x9A90)
+
+
+
+
+typedef union tagMiepPbar23xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_0 : 12 ;
+ UINT32 pbar23_xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar45xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_1 : 12 ;
+ UINT32 pbar45_xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar23lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_2 : 12 ;
+ UINT32 pbar23_limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar45lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_3 : 12 ;
+ UINT32 pbar45_limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepB2bBar01xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_4 : 17 ;
+ UINT32 b2b_pbar01_xlat_lower : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_B2B_BAR01XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepPpd
+{
+
+ struct
+ {
+ UINT32 port_def : 1 ;
+ UINT32 Reserved_6 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PPD_U;
+
+
+
+
+typedef union tagMiepPDeviceVendorId
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_DEVICE_VENDOR_ID_U;
+
+
+
+
+typedef union tagMiepPPcistsPcicmd
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_10 : 5 ;
+ UINT32 Reserved_9 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_8 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_parity_error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_PCISTS_PCICMD_U;
+
+
+
+
+typedef union tagMiepPCcrRid
+{
+
+ struct
+ {
+ UINT32 revision_id : 8 ;
+ UINT32 Reserved_11 : 8 ;
+ UINT32 cfg_sub_class : 8 ;
+ UINT32 cfg_base_class : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_CCR_RID_U;
+
+
+
+
+typedef union tagMiepPBistType
+{
+
+ struct
+ {
+ UINT32 cache_line_size : 8 ;
+ UINT32 primary_latency_timer : 8 ;
+ UINT32 cfg_hdr_type : 8 ;
+ UINT32 bist : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_BIST_TYPE_U;
+
+
+
+
+typedef union tagMiepPbar01BaseLower
+{
+
+ struct
+ {
+ UINT32 cfg_iep_bar0_io : 1 ;
+ UINT32 cfg_iep_bar0_type : 2 ;
+ UINT32 cfg_iep_bar0_pref : 1 ;
+ UINT32 Reserved_12 : 13 ;
+ UINT32 bar0_low : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR01_BASE_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar23BaseLower
+{
+
+ struct
+ {
+ UINT32 cfg_iep_bar2_io : 1 ;
+ UINT32 cfg_iep_bar2_type : 2 ;
+ UINT32 cfg_iep_bar2_pref : 1 ;
+ UINT32 Reserved_13 : 8 ;
+ UINT32 bar2_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR23_BASE_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar45BaseLower
+{
+
+ struct
+ {
+ UINT32 cfg_iep_bar4_io : 1 ;
+ UINT32 cfg_iep_bar4_type : 2 ;
+ UINT32 cfg_iep_bar4_pref : 1 ;
+ UINT32 Reserved_14 : 8 ;
+ UINT32 bar4_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PBAR45_BASE_LOWER_U;
+
+
+
+
+typedef union tagMiepPSubsystemid
+{
+
+ struct
+ {
+ UINT32 subsystem_device_id : 16 ;
+ UINT32 subsystem_vendor_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_SUBSYSTEMID_U;
+
+
+
+
+typedef union tagMiepPInterrupt
+{
+
+ struct
+ {
+ UINT32 int_line_reg : 8 ;
+ UINT32 cfg_int_pin : 8 ;
+ UINT32 min_gnt : 8 ;
+ UINT32 max_lat : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_INTERRUPT_U;
+
+
+
+
+typedef union tagMiepPMsiLower32Bitaddress
+{
+
+ struct
+ {
+ UINT32 Reserved_17 : 2 ;
+ UINT32 iep_msi_addr_low32 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_U;
+
+
+
+
+typedef union tagMiepPLinkCapability
+{
+
+ struct
+ {
+ UINT32 cfg_pcie_max_link_speed : 4 ;
+ UINT32 cfg_pcie_max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exit_latency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_19 : 1 ;
+ UINT32 cfg_pcie_port_num : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_LINK_CAPABILITY_U;
+
+
+
+
+typedef union tagMiepPAerCapHeader
+{
+
+ struct
+ {
+ UINT32 PCIE_Extended_Capability_ID : 16 ;
+ UINT32 Capability_Version : 4 ;
+ UINT32 Next_Capability_Offset : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_P_AER_CAP_HEADER_U;
+
+
+
+
+typedef union tagMiepSbar23xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_26 : 12 ;
+ UINT32 sbar23_xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar45xlatLower
+{
+
+ struct
+ {
+ UINT32 Reserved_28 : 12 ;
+ UINT32 sbar45_xlat_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar23lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_29 : 12 ;
+ UINT32 sbar23_limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar45lmtLower
+{
+
+ struct
+ {
+ UINT32 Reserved_30 : 12 ;
+ UINT32 sbar45_limit_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar45lmtUpper
+{
+
+ struct
+ {
+ UINT32 Reserved_31 : 12 ;
+ UINT32 sbar45_limit_upper : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SBAR45LMT_UPPER_U;
+
+
+
+
+typedef union tagMiepCbdfSbdf
+{
+
+ struct
+ {
+ UINT32 sfunc : 3 ;
+ UINT32 sdev : 5 ;
+ UINT32 sbus : 8 ;
+ UINT32 cap_sfunc_num : 3 ;
+ UINT32 cap_sdev_num : 5 ;
+ UINT32 cap_sbus_num : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_CBDF_SBDF_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr0
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR0_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr1
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_35 : 5 ;
+ UINT32 Reserved_34 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_33 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_perr : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR1_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr11
+{
+
+ struct
+ {
+ UINT32 subsystem_vendor_id : 16 ;
+ UINT32 subsystemid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR11_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr13
+{
+
+ struct
+ {
+ UINT32 capptr : 8 ;
+ UINT32 Reserved_37 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR13_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr15
+{
+
+ struct
+ {
+ UINT32 int_line : 8 ;
+ UINT32 int_pin : 8 ;
+ UINT32 min_grant : 8 ;
+ UINT32 max_latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR15_U;
+
+
+
+
+typedef union tagMiepPciMsiCap0
+{
+
+ struct
+ {
+ UINT32 msi_cap_id : 8 ;
+ UINT32 next_capability_pointer : 8 ;
+ UINT32 msi_enabled : 1 ;
+ UINT32 multiple_message_capable : 3 ;
+ UINT32 multiple_message_enabled : 3 ;
+ UINT32 msi_64_en : 1 ;
+ UINT32 pvm_en : 1 ;
+ UINT32 message_control_register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_MSI_CAP0_U;
+
+
+
+
+typedef union tagMiepPciMsiCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_42 : 2 ;
+ UINT32 msi_addr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_MSI_CAP1_U;
+
+
+
+
+typedef union tagMiepPciMsiCap3
+{
+
+ struct
+ {
+ UINT32 msi_data : 16 ;
+ UINT32 Reserved_43 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCI_MSI_CAP3_U;
+
+
+
+
+typedef union tagMiepPcieCap0
+{
+
+ struct
+ {
+ UINT32 pcie_cap_id : 8 ;
+ UINT32 pcie_next_ptr : 8 ;
+ UINT32 pcie_capability_version : 4 ;
+ UINT32 device_port_type : 4 ;
+ UINT32 slot_implemented : 1 ;
+ UINT32 interrupt_message_number : 5 ;
+ UINT32 Reserved_44 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP0_U;
+
+
+
+
+typedef union tagMiepPcieCap1
+{
+
+ struct
+ {
+ UINT32 max_payload_size_supported : 3 ;
+ UINT32 phantom_function_supported : 2 ;
+ UINT32 extended_tagfield_supported : 1 ;
+ UINT32 endpoint_l0sacceptable_latency : 3 ;
+ UINT32 endpoint_l1acceptable_latency : 3 ;
+ UINT32 undefined : 3 ;
+ UINT32 Reserved_47 : 3 ;
+ UINT32 captured_slot_power_limit_value : 8 ;
+ UINT32 captured_slot_power_limit_scale : 2 ;
+ UINT32 function_level_reset : 1 ;
+ UINT32 Reserved_46 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP1_U;
+
+
+
+
+typedef union tagMiepPcieCap2
+{
+
+ struct
+ {
+ UINT32 correctable_error_reporting_enable : 1 ;
+ UINT32 non_fatal_error_reporting_enable : 1 ;
+ UINT32 fatal_error_reporting_enable : 1 ;
+ UINT32 urenable : 1 ;
+ UINT32 enable_relaxed_ordering : 1 ;
+ UINT32 max_payload_size : 3 ;
+ UINT32 extended_tagfieldenable : 1 ;
+ UINT32 phantom_function_enable : 1 ;
+ UINT32 auxpowerpmenable : 1 ;
+ UINT32 enablenosnoop : 1 ;
+ UINT32 max_read_request_size : 3 ;
+ UINT32 Reserved_49 : 1 ;
+ UINT32 correctableerrordetected : 1 ;
+ UINT32 non_fatalerrordetected : 1 ;
+ UINT32 fatalerrordetected : 1 ;
+ UINT32 unsupportedrequestdetected : 1 ;
+ UINT32 auxpowerdetected : 1 ;
+ UINT32 transactionpending : 1 ;
+ UINT32 Reserved_48 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP2_U;
+
+
+
+
+typedef union tagMiepPcieCap3
+{
+
+ struct
+ {
+ UINT32 max_link_speed : 4 ;
+ UINT32 max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exitlatency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_50 : 1 ;
+ UINT32 port_number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagMiepPcieCap4
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_53 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_52 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_51 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagMiepPcieCap5
+{
+
+ struct
+ {
+ UINT32 attentioonbuttonpresent : 1 ;
+ UINT32 powercontrollerpresent : 1 ;
+ UINT32 mrlsensorpresent : 1 ;
+ UINT32 attentionindicatorpresent : 1 ;
+ UINT32 powerindicatorpresent : 1 ;
+ UINT32 hot_plugsurprise : 1 ;
+ UINT32 hot_plugcapable : 1 ;
+ UINT32 slotpowerlimitvalue : 8 ;
+ UINT32 slotpowerlimitscale : 2 ;
+ UINT32 electromechanicalinterlockpresen : 1 ;
+ UINT32 no_cmd_complete_support : 1 ;
+ UINT32 phy_slot_number : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP5_U;
+
+
+
+
+typedef union tagMiepPcieCap6
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpressedenable : 1 ;
+ UINT32 powerfaultdetectedenable : 1 ;
+ UINT32 mrlsensorchangedenable : 1 ;
+ UINT32 presencedetectchangedenable : 1 ;
+ UINT32 commandcompletedinterruptenable : 1 ;
+ UINT32 hot_pluginterruptenable : 1 ;
+ UINT32 attentionindicatorcontrol : 2 ;
+ UINT32 powerindicatorcontrol : 2 ;
+ UINT32 powercontrollercontrol : 1 ;
+ UINT32 electromechanicalinterlockcontrol : 1 ;
+ UINT32 datalinklayerstatechangedenable : 1 ;
+ UINT32 Reserved_54 : 3 ;
+ UINT32 attentionbuttonpressed : 1 ;
+ UINT32 powerfaultdetected : 1 ;
+ UINT32 mrlsensorchanged : 1 ;
+ UINT32 presencedetectchanged : 1 ;
+ UINT32 commandcompleted : 1 ;
+ UINT32 mrlsensorstate : 1 ;
+ UINT32 presencedetectstate : 1 ;
+ UINT32 electromechanicalinterlockstatus : 1 ;
+ UINT32 datalinklayerstatechanged : 1 ;
+ UINT32 slot_ctrl_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagMiepPcieCap7
+{
+
+ struct
+ {
+ UINT32 systemerroroncorrectableerrorenable : 1 ;
+ UINT32 systemerroronnon_fatalerrorenable : 1 ;
+ UINT32 systemerroronfatalerrorenable : 1 ;
+ UINT32 pmeinterruptenable : 1 ;
+ UINT32 crssoftwarevisibilityenable : 1 ;
+ UINT32 Reserved_55 : 11 ;
+ UINT32 crssoftwarevisibility : 1 ;
+ UINT32 root_cap : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagMiepPcieCap8
+{
+
+ struct
+ {
+ UINT32 pmerequesterid : 16 ;
+ UINT32 pmestatus : 1 ;
+ UINT32 pmepending : 1 ;
+ UINT32 root_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagMiepPcieCap9
+{
+
+ struct
+ {
+ UINT32 completiontimeoutrangessupported : 4 ;
+ UINT32 completiontimeoutdisablesupported : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoproutingsupported : 1 ;
+ UINT32 _2_bitatomicopcompletersupported : 1 ;
+ UINT32 _4_bitatomicopcompletersupported : 1 ;
+ UINT32 _28_bitcascompletersupported : 1 ;
+ UINT32 noro_enabledpr_prpassing : 1 ;
+ UINT32 Reserved_56 : 1 ;
+ UINT32 tphcompletersupported : 2 ;
+ UINT32 dev_cap2 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagMiepPcieCap10
+{
+
+ struct
+ {
+ UINT32 completiontimeoutvalue : 4 ;
+ UINT32 completiontimeoutdisable : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoprequesterenable : 1 ;
+ UINT32 atomicopegressblocking : 1 ;
+ UINT32 idorequestenable : 1 ;
+ UINT32 idocompletionenable : 1 ;
+ UINT32 dev_ctrl2 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagMiepPcieCap11
+{
+
+ struct
+ {
+ UINT32 Reserved_58 : 1 ;
+ UINT32 gen1_suport : 1 ;
+ UINT32 gen2_suport : 1 ;
+ UINT32 gen3_suport : 1 ;
+ UINT32 Reserved_57 : 4 ;
+ UINT32 crosslink_supported : 1 ;
+ UINT32 link_cap2 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagMiepPcieCap12
+{
+
+ struct
+ {
+ UINT32 targetlinkspeed : 4 ;
+ UINT32 entercompliance : 1 ;
+ UINT32 hardwareautonomousspeeddisa : 1 ;
+ UINT32 selectablede_empha : 1 ;
+ UINT32 transmitmargin : 3 ;
+ UINT32 _entermodifiedcompliance : 1 ;
+ UINT32 compliancesos : 1 ;
+ UINT32 de_emphasislevel : 4 ;
+ UINT32 currentde_emphasislevel : 1 ;
+ UINT32 equalizationcomplete : 1 ;
+ UINT32 equalizationphase1successful : 1 ;
+ UINT32 equalizationphase2successful : 1 ;
+ UINT32 equalizationphase3successful : 1 ;
+ UINT32 linkequalizationrequest : 1 ;
+ UINT32 link_ctrl2_status2 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagMiepSlotCap
+{
+
+ struct
+ {
+ UINT32 slotnumberingcapabilitiesid : 8 ;
+ UINT32 nextcapabilitypointer : 8 ;
+ UINT32 add_incardslotsprovided : 5 ;
+ UINT32 firstinchassis : 1 ;
+ UINT32 Reserved_59 : 2 ;
+ UINT32 slot_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_SLOT_CAP_U;
+
+
+
+
+typedef union tagMiepAerCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 aer_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP0_U;
+
+
+
+
+typedef union tagMiepAerCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_65 : 1 ;
+ UINT32 Reserved_64 : 3 ;
+ UINT32 datalinkprotocolerrorsta : 1 ;
+ UINT32 surprisedownerrorstatus : 1 ;
+ UINT32 Reserved_63 : 6 ;
+ UINT32 poisonedtlpstatu : 1 ;
+ UINT32 flowcontrolprotocolerrorst : 1 ;
+ UINT32 completiontimeouts : 1 ;
+ UINT32 completerabortstatus : 1 ;
+ UINT32 receiveroverflowstatus : 1 ;
+ UINT32 malformedtlpstatus : 1 ;
+ UINT32 ecrcerrorstatus : 1 ;
+ UINT32 ecrcerrorstat : 1 ;
+ UINT32 unsupportedrequesterrorstatus : 1 ;
+ UINT32 Reserved_62 : 3 ;
+ UINT32 atomicopegressblockedstatus : 1 ;
+ UINT32 uncorr_err_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP1_U;
+
+
+
+
+typedef union tagMiepAerCap2
+{
+
+ struct
+ {
+ UINT32 Reserved_69 : 1 ;
+ UINT32 Reserved_68 : 3 ;
+ UINT32 datalinkprotocolerrormask : 1 ;
+ UINT32 surprisedownerrormask : 1 ;
+ UINT32 Reserved_67 : 6 ;
+ UINT32 poisonedtlpmask : 1 ;
+ UINT32 flowcontrolprotocolerrormask : 1 ;
+ UINT32 completiontimeoutmask : 1 ;
+ UINT32 completerabortmask : 1 ;
+ UINT32 unexpectedcompletionmask : 1 ;
+ UINT32 receiveroverflowmask : 1 ;
+ UINT32 malformedtlpmask : 1 ;
+ UINT32 ecrcerrormask : 1 ;
+ UINT32 unsupportedrequesterrormask : 1 ;
+ UINT32 Reserved_66 : 3 ;
+ UINT32 atomicopegressblockedmask : 1 ;
+ UINT32 uncorr_err_mask : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP2_U;
+
+
+
+
+typedef union tagMiepAerCap3
+{
+
+ struct
+ {
+ UINT32 Reserved_73 : 1 ;
+ UINT32 Reserved_72 : 3 ;
+ UINT32 datalinkprotocolerrorsever : 1 ;
+ UINT32 surprisedownerrorseverity : 1 ;
+ UINT32 Reserved_71 : 6 ;
+ UINT32 poisonedtlpseverity : 1 ;
+ UINT32 flowcontrolprotocolerrorseveri : 1 ;
+ UINT32 completiontimeoutseverity : 1 ;
+ UINT32 completerabortseverity : 1 ;
+ UINT32 unexpectedcompletionseverity : 1 ;
+ UINT32 receiveroverflowseverity : 1 ;
+ UINT32 malformedtlpseverity : 1 ;
+ UINT32 ecrcerrorseverity : 1 ;
+ UINT32 unsupportedrequesterrorseverity : 1 ;
+ UINT32 Reserved_70 : 3 ;
+ UINT32 atomicopegressblockedseverity : 1 ;
+ UINT32 uncorr_err_ser : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP3_U;
+
+
+
+
+typedef union tagMiepAerCap4
+{
+
+ struct
+ {
+ UINT32 receivererrorstatus : 1 ;
+ UINT32 Reserved_75 : 5 ;
+ UINT32 badtlpstatus : 1 ;
+ UINT32 baddllpstatus : 1 ;
+ UINT32 replay_numrolloverstatus : 1 ;
+ UINT32 Reserved_74 : 3 ;
+ UINT32 replytimertimeoutstatus : 1 ;
+ UINT32 advisorynon_fatalerrorstatus : 1 ;
+ UINT32 corr_err_status : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP4_U;
+
+
+
+
+typedef union tagMiepAerCap5
+{
+
+ struct
+ {
+ UINT32 receivererrormask : 1 ;
+ UINT32 Reserved_77 : 5 ;
+ UINT32 badtlpmask : 1 ;
+ UINT32 baddllpmask : 1 ;
+ UINT32 replay_numrollovermask : 1 ;
+ UINT32 Reserved_76 : 3 ;
+ UINT32 replytimertimeoutmask : 1 ;
+ UINT32 advisorynon_fatalerrormask : 1 ;
+ UINT32 corr_err_mask : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP5_U;
+
+
+
+
+typedef union tagMiepAerCap6
+{
+
+ struct
+ {
+ UINT32 firsterrorpointer : 5 ;
+ UINT32 ecrcgenerationcapability : 1 ;
+ UINT32 ecrcgenerationenable : 1 ;
+ UINT32 ecrccheckcapable : 1 ;
+ UINT32 ecrccheckenable : 1 ;
+ UINT32 adv_cap_ctrl : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP6_U;
+
+
+
+
+typedef union tagMiepAerCap11
+{
+
+ struct
+ {
+ UINT32 correctableerrorreportingenable : 1 ;
+ UINT32 non_fatalerrorreportingenable : 1 ;
+ UINT32 fatalerrorreportingenable : 1 ;
+ UINT32 root_err_cmd : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP11_U;
+
+
+
+
+typedef union tagMiepAerCap12
+{
+
+ struct
+ {
+ UINT32 err_correceived : 1 ;
+ UINT32 multipleerr_correceived : 1 ;
+ UINT32 err_fatal_nonfatalreceived : 1 ;
+ UINT32 multipleerr_fatal_nonfatalreceived : 1 ;
+ UINT32 firstuncorrectablefatal : 1 ;
+ UINT32 non_fatalerrormessagesreceived : 1 ;
+ UINT32 fatalerrormessagesreceived : 1 ;
+ UINT32 Reserved_78 : 20 ;
+ UINT32 root_err_status : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP12_U;
+
+
+
+
+typedef union tagMiepAerCap13
+{
+
+ struct
+ {
+ UINT32 err_corsourceidentification : 16 ;
+ UINT32 err_src_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_AER_CAP13_U;
+
+
+
+
+typedef union tagMiepVcCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 vc_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP0_U;
+
+
+
+
+typedef union tagMiepVcCap1
+{
+
+ struct
+ {
+ UINT32 extendedvccount : 3 ;
+ UINT32 Reserved_81 : 1 ;
+ UINT32 lowpriorityextendedvccount : 3 ;
+ UINT32 Reserved_80 : 1 ;
+ UINT32 referenceclock : 2 ;
+ UINT32 portarbitrationtableentrysize : 2 ;
+ UINT32 vc_cap1 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP1_U;
+
+
+
+
+typedef union tagMiepVcCap2
+{
+
+ struct
+ {
+ UINT32 vcarbitrationcapability : 8 ;
+ UINT32 Reserved_82 : 16 ;
+ UINT32 vc_cap2 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP2_U;
+
+
+
+
+typedef union tagMiepVcCap3
+{
+
+ struct
+ {
+ UINT32 loadvcarbitrationtable : 1 ;
+ UINT32 vcarbitrationselect : 3 ;
+ UINT32 Reserved_84 : 12 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 Reserved_83 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP3_U;
+
+
+
+
+typedef union tagMiepVcCap4
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_87 : 6 ;
+ UINT32 Reserved_86 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_85 : 1 ;
+ UINT32 vc_res_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP4_U;
+
+
+
+
+typedef union tagMiepVcCap5
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_90 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselec : 3 ;
+ UINT32 Reserved_89 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_88 : 4 ;
+ UINT32 vc_res_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP5_U;
+
+
+
+
+typedef union tagMiepVcCap6
+{
+
+ struct
+ {
+ UINT32 Reserved_91 : 16 ;
+ UINT32 portarbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP6_U;
+
+
+
+
+typedef union tagMiepVcCap7
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_94 : 6 ;
+ UINT32 Reserved_93 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_92 : 1 ;
+ UINT32 vc_res_cap0 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP7_U;
+
+
+
+
+typedef union tagMiepVcCap8
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_97 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselect : 3 ;
+ UINT32 Reserved_96 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_95 : 4 ;
+ UINT32 vc_res_ctrl0 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP8_U;
+
+
+
+
+typedef union tagMiepVcCap9
+{
+
+ struct
+ {
+ UINT32 Reserved_98 : 16 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status0 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_VC_CAP9_U;
+
+
+
+
+typedef union tagMiepPortLogic0
+{
+
+ struct
+ {
+ UINT32 ack_lat_timer : 16 ;
+ UINT32 replay_timer : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagMiepPortLogic2
+{
+
+ struct
+ {
+ UINT32 linknumber : 8 ;
+ UINT32 Reserved_101 : 7 ;
+ UINT32 forcelink : 1 ;
+ UINT32 linkstate : 6 ;
+ UINT32 Reserved_100 : 2 ;
+ UINT32 port_force_link : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagMiepPortLogic3
+{
+
+ struct
+ {
+ UINT32 ackfrequency : 8 ;
+ UINT32 n_fts : 8 ;
+ UINT32 commonclockn_fts : 8 ;
+ UINT32 l0sentrancelatency : 3 ;
+ UINT32 l1entrancelatency : 3 ;
+ UINT32 enteraspml1withoutreceiveinl0s : 1 ;
+ UINT32 ack_aspm : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagMiepPortLogic4
+{
+
+ struct
+ {
+ UINT32 vendorspecificdllprequest : 1 ;
+ UINT32 scrambledisable : 1 ;
+ UINT32 loopbackenable : 1 ;
+ UINT32 resetassert : 1 ;
+ UINT32 Reserved_104 : 1 ;
+ UINT32 dlllinkenable : 1 ;
+ UINT32 Reserved_103 : 1 ;
+ UINT32 fastlinkmode : 1 ;
+ UINT32 Reserved_102 : 8 ;
+ UINT32 linkmodeenable : 6 ;
+ UINT32 crosslinkenable : 1 ;
+ UINT32 crosslinkactive : 1 ;
+ UINT32 port_link_ctrl : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagMiepPortLogic5
+{
+
+ struct
+ {
+ UINT32 insertlaneskewfortransmit : 24 ;
+ UINT32 flowcontroldisable : 1 ;
+ UINT32 ack_nakdisable : 1 ;
+ UINT32 Reserved_105 : 5 ;
+ UINT32 lane_skew : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagMiepPortLogic6
+{
+
+ struct
+ {
+ UINT32 numberoftssymbols : 4 ;
+ UINT32 Reserved_107 : 4 ;
+ UINT32 numberofskpsymbols : 3 ;
+ UINT32 Reserved_106 : 3 ;
+ UINT32 timermodifierforreplaytimer : 5 ;
+ UINT32 timermodifierforack_naklatencytimer : 5 ;
+ UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ;
+ UINT32 sym_num : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagMiepPortLogic7
+{
+
+ struct
+ {
+ UINT32 vc0posteddataqueuedepth : 11 ;
+ UINT32 Reserved_108 : 4 ;
+ UINT32 sym_timer : 1 ;
+ UINT32 maskfunctionmismatchfilteringfo : 1 ;
+ UINT32 maskpoisonedtlpfiltering : 1 ;
+ UINT32 maskbarmatchfiltering : 1 ;
+ UINT32 masktype1configurationrequestfiltering : 1 ;
+ UINT32 masklockedrequestfiltering : 1 ;
+ UINT32 masktagerrorrulesforreceivedcompletions : 1 ;
+ UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ;
+ UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ;
+ UINT32 maske_crcerror_filtering : 1 ;
+ UINT32 maske_crcerror_filtering_forcompletions : 1 ;
+ UINT32 message_control : 1 ;
+ UINT32 maskfilteringofreceived : 1 ;
+ UINT32 flt_mask1 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagMiepPortLogic8
+{
+
+ struct
+ {
+ UINT32 cx_flt_mask_venmsg0_drop : 1 ;
+ UINT32 cx_flt_mask_venmsg1_drop : 1 ;
+ UINT32 cx_flt_mask_dabort_4ucpl : 1 ;
+ UINT32 cx_flt_mask_handle_flush : 1 ;
+ UINT32 flt_mask2 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagMiepPortLogic9
+{
+
+ struct
+ {
+ UINT32 amba_multi_outbound_decomp_np : 1 ;
+ UINT32 amba_obnp_ctrl : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagMiepPortLogic12
+{
+
+ struct
+ {
+ UINT32 transmitposteddatafccredits : 12 ;
+ UINT32 transmitpostedheaderfccredits : 8 ;
+ UINT32 tx_pfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagMiepPortLogic13
+{
+
+ struct
+ {
+ UINT32 transmitnon_posteddatafccredits : 12 ;
+ UINT32 transmitnon_postedheaderfccredits : 8 ;
+ UINT32 tx_npfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagMiepPortLogic14
+{
+
+ struct
+ {
+ UINT32 transmitcompletiondatafccredits : 12 ;
+ UINT32 transmitcompletionheaderfccredits : 8 ;
+ UINT32 tx_cplfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagMiepPortLogic15
+{
+
+ struct
+ {
+ UINT32 rx_tlp_fc_credit_not_retured : 1 ;
+ UINT32 tx_retry_buf_not_empty : 1 ;
+ UINT32 rx_queue_not_empty : 1 ;
+ UINT32 Reserved_110 : 13 ;
+ UINT32 fc_latency_timer_override_value : 13 ;
+ UINT32 Reserved_109 : 2 ;
+ UINT32 fc_latency_timer_override_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagMiepPortLogic16
+{
+
+ struct
+ {
+ UINT32 vc0posteddatacredits : 12 ;
+ UINT32 vc0postedheadercredits : 8 ;
+ UINT32 Reserved_112 : 1 ;
+ UINT32 vc0_postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemo : 1 ;
+ UINT32 Reserved_111 : 6 ;
+ UINT32 tlptypeorderingforvc0 : 1 ;
+ UINT32 rx_pque_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagMiepPortLogic17
+{
+
+ struct
+ {
+ UINT32 vc0non_posteddatacredits : 12 ;
+ UINT32 vc0non_postedheadercredits : 8 ;
+ UINT32 rx_npque_ctrl : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagMiepPortLogic18
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_credits : 12 ;
+ UINT32 vc0_cpl_header_credt : 8 ;
+ UINT32 Reserved_114 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagMiepPortLogic19
+{
+
+ struct
+ {
+ UINT32 vco_posted_data_que_path : 14 ;
+ UINT32 Reserved_115 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 vc_pbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagMiepPortLogic20
+{
+
+ struct
+ {
+ UINT32 vco_np_data_que_depth : 14 ;
+ UINT32 Reserved_117 : 2 ;
+ UINT32 vco_np_header_que_depth : 10 ;
+ UINT32 vc_npbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagMiepPortLogic21
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_queue_depth : 14 ;
+ UINT32 Reserved_119 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 Reserved_118 : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagMiepPortLogic22
+{
+
+ struct
+ {
+ UINT32 n_fts : 8 ;
+ UINT32 pre_determ_num_of_lane : 9 ;
+ UINT32 det_sp_change : 1 ;
+ UINT32 config_phy_tx_sw : 1 ;
+ UINT32 config_tx_comp_rcv_bit : 1 ;
+ UINT32 set_emp_level : 1 ;
+ UINT32 Reserved_120 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagMiepPortlogic25
+{
+
+ struct
+ {
+ UINT32 remote_rd_req_size : 3 ;
+ UINT32 Reserved_123 : 5 ;
+ UINT32 remote_max_brd_tag : 8 ;
+ UINT32 Reserved_122 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagMiepPortlogic26
+{
+
+ struct
+ {
+ UINT32 resize_master_resp_compser : 1 ;
+ UINT32 axi_ctrl1 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagMiepPortlogic54
+{
+
+ struct
+ {
+ UINT32 region_index : 4 ;
+ UINT32 Reserved_124 : 27 ;
+ UINT32 iatu_view : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC54_U;
+
+
+
+
+typedef union tagMiepPortlogic55
+{
+
+ struct
+ {
+ UINT32 iatu1_type : 5 ;
+ UINT32 iatu1_tc : 3 ;
+ UINT32 iatu1_td : 1 ;
+ UINT32 iatu1_attr : 2 ;
+ UINT32 Reserved_128 : 5 ;
+ UINT32 iatu1_at : 2 ;
+ UINT32 Reserved_127 : 2 ;
+ UINT32 iatu1_id : 3 ;
+ UINT32 Reserved_126 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagMiepPortlogic56
+{
+
+ struct
+ {
+ UINT32 iatu2_type : 8 ;
+ UINT32 iatu2_bar_num : 3 ;
+ UINT32 Reserved_132 : 3 ;
+ UINT32 iatu2_tc_match_en : 1 ;
+ UINT32 iatu2_td_match_en : 1 ;
+ UINT32 iatu2_attr_match_en : 1 ;
+ UINT32 Reserved_131 : 1 ;
+ UINT32 iatu2_at_match_en : 1 ;
+ UINT32 iatu2_func_num_match_en : 1 ;
+ UINT32 iatu2_virtual_func_num_match_en : 1 ;
+ UINT32 message_code_match_en : 1 ;
+ UINT32 Reserved_130 : 2 ;
+ UINT32 iatu2_response_code : 2 ;
+ UINT32 Reserved_129 : 1 ;
+ UINT32 iatu2_fuzzy_type_match_mode : 1 ;
+ UINT32 iatu2_cfg_shift_mode : 1 ;
+ UINT32 iatu2_ivert_mode : 1 ;
+ UINT32 iatu2_match_mode : 1 ;
+ UINT32 iatu2_region_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagMiepPortlogic57
+{
+
+ struct
+ {
+ UINT32 iatu_start_low : 12 ;
+ UINT32 iatu_start_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagMiepPortlogic59
+{
+
+ struct
+ {
+ UINT32 iatu_limit_low : 12 ;
+ UINT32 iatu_limit_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagMiepPortlogic60
+{
+
+ struct
+ {
+ UINT32 xlated_addr_high : 12 ;
+ UINT32 xlated_addr_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagMiepPortlogic62
+{
+
+ struct
+ {
+ UINT32 dma_wr_eng_en : 1 ;
+ UINT32 dma_wr_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagMiepPortlogic63
+{
+
+ struct
+ {
+ UINT32 wr_doorbell_num : 3 ;
+ UINT32 Reserved_134 : 28 ;
+ UINT32 dma_wr_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagMiepPortlogic64
+{
+
+ struct
+ {
+ UINT32 dma_read_eng_en : 1 ;
+ UINT32 Reserved_135 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagMiepPortlogic65
+{
+
+ struct
+ {
+ UINT32 rd_doorbell_num : 3 ;
+ UINT32 Reserved_137 : 28 ;
+ UINT32 dma_rd_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagMiepPortlogic66
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_139 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_138 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagMiepPortlogic67
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_142 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 Reserved_141 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagMiepPortlogic68
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_145 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 Reserved_144 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagMiepPortlogic69
+{
+
+ struct
+ {
+ UINT32 app_rd_err_det : 8 ;
+ UINT32 Reserved_147 : 8 ;
+ UINT32 ll_element_fetch_err_det : 8 ;
+ UINT32 Reserved_146 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagMiepPortlogic74
+{
+
+ struct
+ {
+ UINT32 dma_wr_c0_imwr_data : 16 ;
+ UINT32 dma_wr_c1_imwr_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagMiepPortlogic75
+{
+
+ struct
+ {
+ UINT32 wr_ch_ll_remote_abort_int_en : 8 ;
+ UINT32 Reserved_149 : 8 ;
+ UINT32 wr_ch_ll_local_abort_int_en : 8 ;
+ UINT32 Reserved_148 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagMiepPortlogic76
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_152 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_151 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagMiepPortlogic77
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_154 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 dma_rd_int_mask : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagMiepPortlogic78
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_156 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 dma_rd_int_clr : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagMiepPortlogic79
+{
+
+ struct
+ {
+ UINT32 app_wr_err_det : 8 ;
+ UINT32 Reserved_157 : 8 ;
+ UINT32 link_list_fetch_err_det : 8 ;
+ UINT32 dma_rd_err_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagMiepPortlogic80
+{
+
+ struct
+ {
+ UINT32 unspt_request : 8 ;
+ UINT32 completer_abort : 8 ;
+ UINT32 cpl_time_out : 8 ;
+ UINT32 dma_rd_err_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagMiepPortlogic81
+{
+
+ struct
+ {
+ UINT32 remote_abort_int_en : 8 ;
+ UINT32 Reserved_159 : 8 ;
+ UINT32 local_abort_int_en : 8 ;
+ UINT32 dma_rd_ll_err_ena : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagMiepPortlogic86
+{
+
+ struct
+ {
+ UINT32 channel_dir : 3 ;
+ UINT32 Reserved_162 : 28 ;
+ UINT32 dma_ch_con_idx : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagMiepPortlogic87
+{
+
+ struct
+ {
+ UINT32 cycle_bit : 1 ;
+ UINT32 toggle_cycle_bit : 1 ;
+ UINT32 load_link_pointer : 1 ;
+ UINT32 local_int_en : 1 ;
+ UINT32 remote_int_en : 1 ;
+ UINT32 channel_status : 2 ;
+ UINT32 Reserved_166 : 1 ;
+ UINT32 consumer_cycle_state : 1 ;
+ UINT32 linked_list_en : 1 ;
+ UINT32 Reserved_165 : 2 ;
+ UINT32 func_num_dma : 5 ;
+ UINT32 Reserved_164 : 7 ;
+ UINT32 no_snoop : 1 ;
+ UINT32 ro : 1 ;
+ UINT32 td : 1 ;
+ UINT32 tc : 3 ;
+ UINT32 dma_ch_ctrl : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagMiepPortlogic93
+{
+
+ struct
+ {
+ UINT32 Reserved_168 : 2 ;
+ UINT32 dma_ll_ptr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_MIEP_PORTLOGIC93_U;
+
+
+
+#define PCIE_IEP_BASE (0x00000000)
+
+
+
+
+#define PCIE_IEP_DEVICE_VENDOR_ID_REG (PCIE_IEP_BASE + 0x0)
+#define PCIE_IEP_PCISTS_PCICMD_REG (PCIE_IEP_BASE + 0x4)
+#define PCIE_IEP_CCR_RID_REG (PCIE_IEP_BASE + 0x8)
+#define PCIE_IEP_PBAR01_BASE_LOWER_REG (PCIE_IEP_BASE + 0x10)
+#define PCIE_IEP_PBAR01_BASE_UPPER_REG (PCIE_IEP_BASE + 0x14)
+#define PCIE_IEP_PBAR23_BASE_LOWER_REG (PCIE_IEP_BASE + 0x18)
+#define PCIE_IEP_PBAR23_BASE_UPPER_REG (PCIE_IEP_BASE + 0x1C)
+#define PCIE_IEP_PBAR45_BASE_LOWER_REG (PCIE_IEP_BASE + 0x20)
+#define PCIE_IEP_PBAR45_BASE_UPPER_REG (PCIE_IEP_BASE + 0x24)
+#define PCIE_IEP_CARDBUSCISPTR_REG (PCIE_IEP_BASE + 0x28)
+#define PCIE_IEP_SUBSYSTEMID_REG (PCIE_IEP_BASE + 0x2C)
+#define PCIE_IEP_EXPANSIONROM_BASE_ADDR_REG (PCIE_IEP_BASE + 0x30)
+#define PCIE_IEP_CAPPTR_REG (PCIE_IEP_BASE + 0x34)
+#define PCIE_IEP_INTERRUPT_REG (PCIE_IEP_BASE + 0x3C)
+#define PCIE_IEP_MSI_CAPABILITY_REGISTER_REG (PCIE_IEP_BASE + 0x50)
+#define PCIE_IEP_MSI_LOWER32_BITADDRESS_REG (PCIE_IEP_BASE + 0x54)
+#define PCIE_IEP_MSI_UPPER32_BIT_ADDRESS_REG (PCIE_IEP_BASE + 0x58)
+#define PCIE_IEP_MSI_DATA_REG (PCIE_IEP_BASE + 0x5C)
+#define PCIE_IEP_MSI_MASK_REG (PCIE_IEP_BASE + 0x60)
+#define PCIE_IEP_MSI_PENDING_REG (PCIE_IEP_BASE + 0x64)
+#define PCIE_IEP_PCIE_CAPABILITY_REGISTER_REG (PCIE_IEP_BASE + 0x70)
+#define PCIE_IEP_DEVICE_CAPABILITIES_REGISTER_REG (PCIE_IEP_BASE + 0x74)
+#define PCIE_IEP_DEVICE_STATUS_REGISTER_REG (PCIE_IEP_BASE + 0x78)
+#define PCIE_IEP_LINK_CAPABILITY_REG (PCIE_IEP_BASE + 0x7C)
+#define PCIE_IEP_LINK_CONTROL_STATUS_REG (PCIE_IEP_BASE + 0x80)
+#define PCIE_IEP_AER_CAP_HEADER_REG (PCIE_IEP_BASE + 0x100)
+#define PCIE_IEP_UC_ERROR_STATUS_REG (PCIE_IEP_BASE + 0x104)
+#define PCIE_IEP_UC_ERROR_MASK_REG (PCIE_IEP_BASE + 0x108)
+#define PCIE_IEP_UC_ERROR_SEVERITY_REG (PCIE_IEP_BASE + 0x10C)
+#define PCIE_IEP_C_ERROR_STATUS_REG (PCIE_IEP_BASE + 0x110)
+#define PCIE_IEP_C_ERROR_MASK_REG (PCIE_IEP_BASE + 0x114)
+#define PCIE_IEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG (PCIE_IEP_BASE + 0x118)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_1_REG (PCIE_IEP_BASE + 0x11C)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_2_REG (PCIE_IEP_BASE + 0x120)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_3_REG (PCIE_IEP_BASE + 0x124)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_4_REG (PCIE_IEP_BASE + 0x128)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_1_REG (PCIE_IEP_BASE + 0x130)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_2_REG (PCIE_IEP_BASE + 0x134)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_3_REG (PCIE_IEP_BASE + 0x138)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_4_REG (PCIE_IEP_BASE + 0x13C)
+#define PCIE_IEP_NTB_IEP_CFG_SPACE_LOWER_REG (PCIE_IEP_BASE + 0x700)
+#define PCIE_IEP_NTB_IEP_CFG_SPACE_UPPER_REG (PCIE_IEP_BASE + 0x704)
+#define PCIE_IEP_NTB_IEP_BAR01_CTRL_REG (PCIE_IEP_BASE + 0x708)
+#define PCIE_IEP_NTB_IEP_BAR23_CTRL_REG (PCIE_IEP_BASE + 0x70C)
+#define PCIE_IEP_NTB_IEP_BAR45_CTRL_REG (PCIE_IEP_BASE + 0x710)
+#define PCIE_IEP_MSI_CTRL_ADDRESS_LOWER_REG (PCIE_IEP_BASE + 0x714)
+#define PCIE_IEP_MSI_CTRL_ADDRESS_UPPER_REG (PCIE_IEP_BASE + 0x718)
+#define PCIE_IEP_MSI_CTRL_INT_EN_REG (PCIE_IEP_BASE + 0x71C)
+#define PCIE_IEP_MSI_CTRL_INT0_MASK_REG (PCIE_IEP_BASE + 0x720)
+#define PCIE_IEP_MSI_CTRL_INT_STATUS_REG (PCIE_IEP_BASE + 0x724)
+
+
+
+typedef union tagIepDeviceVendorId
+{
+
+ struct
+ {
+ UINT32 Vendor_ID : 16 ;
+ UINT32 Device_ID : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_DEVICE_VENDOR_ID_U;
+
+
+
+
+typedef union tagIepPcistsPcicmd
+{
+
+ struct
+ {
+ UINT32 IO_Space_Enable : 1 ;
+ UINT32 Memory_Space_Enable : 1 ;
+ UINT32 Bus_Master_Enable : 1 ;
+ UINT32 SpecialCycleEnable : 1 ;
+ UINT32 Memory_Write_and_Invalidate : 1 ;
+ UINT32 VGA_palette_snoop_Enable : 1 ;
+ UINT32 Parity_Error_Response : 1 ;
+ UINT32 IDSEL_Stepping_WaitCycle_Control : 1 ;
+ UINT32 SERR_Enable : 1 ;
+ UINT32 FastBack_to_BackEnable : 1 ;
+ UINT32 Interrupt_Disable : 1 ;
+ UINT32 Reserved_2 : 5 ;
+ UINT32 Reserved_1 : 3 ;
+ UINT32 INTx_Status : 1 ;
+ UINT32 CapabilitiesList : 1 ;
+ UINT32 pcibus66MHzcapable : 1 ;
+ UINT32 Reserved_0 : 1 ;
+ UINT32 FastBack_to_Back : 1 ;
+ UINT32 MasterDataParityError : 1 ;
+ UINT32 DEVSEL_Timing : 2 ;
+ UINT32 Signaled_Target_Abort : 1 ;
+ UINT32 Received_Target_Abort : 1 ;
+ UINT32 Received_Master_Abort : 1 ;
+ UINT32 Signaled_System_Error : 1 ;
+ UINT32 Detected_Parity_Error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PCISTS_PCICMD_U;
+
+
+
+
+typedef union tagIepCcrRid
+{
+
+ struct
+ {
+ UINT32 Revision_Identification : 8 ;
+ UINT32 Reserved_3 : 8 ;
+ UINT32 Sub_Class : 8 ;
+ UINT32 BaseClass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_CCR_RID_U;
+
+
+
+
+typedef union tagIepPbar01BaseLower
+{
+
+ struct
+ {
+ UINT32 BAR01_Space_Inicator : 1 ;
+ UINT32 BAR01_Type : 2 ;
+ UINT32 BAR01_Prefetchable : 1 ;
+ UINT32 Reserved_4 : 12 ;
+ UINT32 pbar01_lower : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PBAR01_BASE_LOWER_U;
+
+
+
+
+typedef union tagIepPbar23BaseLower
+{
+
+ struct
+ {
+ UINT32 pbar23_space_inicator : 1 ;
+ UINT32 pbar23_type : 2 ;
+ UINT32 pbar23_prefetchable : 1 ;
+ UINT32 Reserved_6 : 8 ;
+ UINT32 pbar23_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PBAR23_BASE_LOWER_U;
+
+
+
+
+typedef union tagIepPbar45BaseLower
+{
+
+ struct
+ {
+ UINT32 pbar45_space_inicator : 1 ;
+ UINT32 pbar45_type : 2 ;
+ UINT32 pbar45_prefetchable : 1 ;
+ UINT32 Reserved_7 : 8 ;
+ UINT32 pbar45_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PBAR45_BASE_LOWER_U;
+
+
+
+
+typedef union tagIepSubsystemid
+{
+
+ struct
+ {
+ UINT32 SubsystemID : 16 ;
+ UINT32 SubsystemVendorID : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_SubSystemId_U;
+
+
+
+
+typedef union tagIepCapptr
+{
+
+ struct
+ {
+ UINT32 CapPtr : 8 ;
+ UINT32 Reserved_10 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_CapPtr_U;
+
+
+
+
+typedef union tagIepInterrupt
+{
+
+ struct
+ {
+ UINT32 Interrupt_Line : 8 ;
+ UINT32 Interrupt_Pin : 8 ;
+ UINT32 Min_Grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Interrupt_U;
+
+
+
+
+typedef union tagIepMsiCapabilityRegister
+{
+
+ struct
+ {
+ UINT32 CapabilityID : 8 ;
+ UINT32 Next_Capability_Pointer : 8 ;
+ UINT32 MSI_Enabled : 1 ;
+ UINT32 Multiple_Message_Capable : 3 ;
+ UINT32 Multiple_Message_Enabled : 3 ;
+ UINT32 MSI_64_EN : 1 ;
+ UINT32 PVM_EN : 1 ;
+ UINT32 Message_Control_Register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_Capability_Register_U;
+
+
+
+
+typedef union tagIepMsiLower32Bitaddress
+{
+
+ struct
+ {
+ UINT32 Reserved_13 : 2 ;
+ UINT32 Lower32_bitAddress : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_Lower32_bitAddress_U;
+
+
+
+
+typedef union tagIepMsiData
+{
+
+ struct
+ {
+ UINT32 MSI_Data : 16 ;
+ UINT32 Reserved_14 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_Data_U;
+
+
+
+
+typedef union tagIepMsiMask
+{
+
+ struct
+ {
+ UINT32 MsiMask : 1 ;
+ UINT32 Reserved_15 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_MASK_U;
+
+
+
+
+typedef union tagIepMsiPending
+{
+
+ struct
+ {
+ UINT32 MsiPending : 1 ;
+ UINT32 Reserved_16 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_Pending_U;
+
+
+
+
+typedef union tagIepPcieCapabilityRegister
+{
+
+ struct
+ {
+ UINT32 Capability_ID : 8 ;
+ UINT32 Next_Capability_Pointer : 8 ;
+ UINT32 PCIE_Capability_Version : 4 ;
+ UINT32 Device_Port_Type : 4 ;
+ UINT32 Slot_Implemented : 1 ;
+ UINT32 Interrupt_Message_Number : 5 ;
+ UINT32 Reserved_17 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_PCIE_Capability_Register_U;
+
+
+
+
+typedef union tagIepDeviceCapabilitiesRegister
+{
+
+ struct
+ {
+ UINT32 Max_Payload_Size_Supported : 3 ;
+ UINT32 Phantom_Function_Supported : 2 ;
+ UINT32 Extended_TagField_Supported : 1 ;
+ UINT32 Endpoint_L0sAcceptable_Latency : 3 ;
+ UINT32 Endpoint_L1Acceptable_Latency : 3 ;
+ UINT32 Undefined : 3 ;
+ UINT32 Reserved_20 : 3 ;
+ UINT32 Captured_Slot_Power_Limit_Value : 8 ;
+ UINT32 Captured_Slot_Power_Limit_Scale : 2 ;
+ UINT32 Function_Level_Reset : 1 ;
+ UINT32 Reserved_19 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Device_Capabilities_Register_U;
+
+
+
+
+typedef union tagIepDeviceStatusRegister
+{
+
+ struct
+ {
+ UINT32 Correctable_Error_Reporting_Enable : 1 ;
+ UINT32 Non_Fatal_Error_Reporting_Enable : 1 ;
+ UINT32 Fatal_Error_Reporting_Enable : 1 ;
+ UINT32 UREnable : 1 ;
+ UINT32 Enable_Relaxed_Ordering : 1 ;
+ UINT32 Max_Payload_Size : 3 ;
+ UINT32 Extended_TagFieldEnable : 1 ;
+ UINT32 Phantom_Function_Enable : 1 ;
+ UINT32 AUXPowerPMEnable : 1 ;
+ UINT32 EnableNoSnoop : 1 ;
+ UINT32 Max_Read_Request_Size : 3 ;
+ UINT32 Reserved_22 : 1 ;
+ UINT32 CorrectableErrorDetected : 1 ;
+ UINT32 Non_FatalErrordetected : 1 ;
+ UINT32 FatalErrorDetected : 1 ;
+ UINT32 UnsupportedRequestDetected : 1 ;
+ UINT32 AuxPowerDetected : 1 ;
+ UINT32 TransactionPending : 1 ;
+ UINT32 Reserved_21 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Device_Status_Register_U;
+
+
+
+
+typedef union tagIepLinkCapability
+{
+
+ struct
+ {
+ UINT32 Max_Link_Speed : 4 ;
+ UINT32 Max_Link_Width : 6 ;
+ UINT32 Active_State_Power_Management : 2 ;
+ UINT32 L0s_ExitLatency : 3 ;
+ UINT32 L1_Exit_Latency : 3 ;
+ UINT32 Clock_Power_Management : 1 ;
+ UINT32 Surprise_Down_Error_Report_Cap : 1 ;
+ UINT32 Data_Link_Layer_Active_Report_Cap : 1 ;
+ UINT32 Link_Bandwidth_Noti_Cap : 1 ;
+ UINT32 ASPM_Option_Compliance : 1 ;
+ UINT32 Reserved_23 : 1 ;
+ UINT32 Port_Number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Link_Capability_U;
+
+
+
+
+typedef union tagIepLinkControlStatus
+{
+
+ struct
+ {
+ UINT32 Active_State_Power_Management : 2 ;
+ UINT32 Reserved_26 : 1 ;
+ UINT32 RCB : 1 ;
+ UINT32 Link_Disable : 1 ;
+ UINT32 Retrain_Link : 1 ;
+ UINT32 Common_Clock_Config : 1 ;
+ UINT32 Extended_Sync : 1 ;
+ UINT32 Enable_Clock_Pwr_Management : 1 ;
+ UINT32 Hw_Auto_Width_Disable : 1 ;
+ UINT32 Link_Bandwidth_Management_Int_En : 1 ;
+ UINT32 Link_Auto_Bandwidth_Int_En : 1 ;
+ UINT32 Reserved_25 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_24 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_config : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Link_Control_Status_U;
+
+
+
+
+typedef union tagIepAerCapHeader
+{
+
+ struct
+ {
+ UINT32 PCIE_Extended_Capability_ID : 16 ;
+ UINT32 Capability_Version : 4 ;
+ UINT32 Next_Capability_Offset : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_AER_Cap_header_U;
+
+
+
+
+typedef union tagIepUcErrorStatus
+{
+
+ struct
+ {
+ UINT32 Reserved_31 : 1 ;
+ UINT32 Reserved_30 : 3 ;
+ UINT32 DataLinkProtocolErrorStatus : 1 ;
+ UINT32 SurpriseDownErrorStatus : 1 ;
+ UINT32 Reserved_29 : 6 ;
+ UINT32 PoisonedTLPStatus : 1 ;
+ UINT32 FlowControlProtocolErrorStatus : 1 ;
+ UINT32 CompletionTimeoutStatus : 1 ;
+ UINT32 CompleterAbortStatus : 1 ;
+ UINT32 UnexpectedCompletionStatus : 1 ;
+ UINT32 ReceiverOverflowStatus : 1 ;
+ UINT32 MalformedTLPStatus : 1 ;
+ UINT32 ECRCErrorStatus : 1 ;
+ UINT32 UnsupportedRequestErrorStatus : 1 ;
+ UINT32 Reserved_28 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_UC_Error_Status_U;
+
+
+
+
+typedef union tagIepUcErrorMask
+{
+
+ struct
+ {
+ UINT32 Reserved_35 : 1 ;
+ UINT32 Reserved_34 : 3 ;
+ UINT32 DataLinkProtocolErrorMask : 1 ;
+ UINT32 SurpriseDownErrorMask : 1 ;
+ UINT32 Reserved_33 : 6 ;
+ UINT32 PoisonedTLPMask : 1 ;
+ UINT32 FlowControlProtocolErrorMask : 1 ;
+ UINT32 CompletionTimeoutMask : 1 ;
+ UINT32 CompleterAbortMask : 1 ;
+ UINT32 UnexpectedCompletionMask : 1 ;
+ UINT32 ReceiverOverflowMask : 1 ;
+ UINT32 MalformedTLPMask : 1 ;
+ UINT32 ECRCErrorMask : 1 ;
+ UINT32 UnsupportedRequestErrorMask : 1 ;
+ UINT32 Reserved_32 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_UC_Error_Mask_U;
+
+
+
+
+typedef union tagIepUcErrorSeverity
+{
+
+ struct
+ {
+ UINT32 Reserved_39 : 1 ;
+ UINT32 Reserved_38 : 3 ;
+ UINT32 DataLinkProtocolErrorSeverity : 1 ;
+ UINT32 SurpriseDownErrorSeverity : 1 ;
+ UINT32 Reserved_37 : 6 ;
+ UINT32 PoisonedTLPSeverity : 1 ;
+ UINT32 FlowControlProtocolErrorSeverity : 1 ;
+ UINT32 CompletionTimeoutSeverity : 1 ;
+ UINT32 CompleterAbortSeverity : 1 ;
+ UINT32 UnexpectedCompletionSeverity : 1 ;
+ UINT32 ReceiverOverflowSeverity : 1 ;
+ UINT32 MalformedTLPSeverity : 1 ;
+ UINT32 ECRCErrorSeverity : 1 ;
+ UINT32 UnsupportedRequestErrorSeverity : 1 ;
+ UINT32 Reserved_36 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_UC_Error_Severity_U;
+
+
+
+
+typedef union tagIepCErrorStatus
+{
+
+ struct
+ {
+ UINT32 Receiver_Error_Status : 1 ;
+ UINT32 Reserved_42 : 5 ;
+ UINT32 Bad_TLP_Status : 1 ;
+ UINT32 Bad_DLLP_Status : 1 ;
+ UINT32 REPLAY_NUM_Rollover_Status : 1 ;
+ UINT32 Reserved_41 : 3 ;
+ UINT32 Replay_Timer_Timeout_Status : 1 ;
+ UINT32 Advisory_Non_Fatal_Error_Status : 1 ;
+ UINT32 Reserved_40 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_C_Error_Status_U;
+
+
+
+
+typedef union tagIepCErrorMask
+{
+
+ struct
+ {
+ UINT32 Receiver_Error_Mask : 1 ;
+ UINT32 Reserved_45 : 5 ;
+ UINT32 Bad_TLP_Mask : 1 ;
+ UINT32 Bad_DLLP_Mask : 1 ;
+ UINT32 REPLAY_NUMRollover_Mask : 1 ;
+ UINT32 Reserved_44 : 3 ;
+ UINT32 Replay_Timer_Timeout_Mask : 1 ;
+ UINT32 Advisory_Non_Fatal_Error_Mask : 1 ;
+ UINT32 Reserved_43 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_C_Error_Mask_U;
+
+
+
+
+typedef union tagIepAdvancedErrorCapabilitiesAndControl
+{
+
+ struct
+ {
+ UINT32 First_Error_Pointer : 5 ;
+ UINT32 ECRC_Generation_Capability : 1 ;
+ UINT32 ECRC_Generation_Enable : 1 ;
+ UINT32 ECRC_Check_Capable : 1 ;
+ UINT32 ECRC_Check_Enable : 1 ;
+ UINT32 Reserved_47 : 2 ;
+ UINT32 TLP_Prefix_Log_Present : 1 ;
+ UINT32 Reserved_46 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_Advanced_Error_Capabilities_and_Control_U;
+
+
+
+
+typedef union tagIepNtbIepBar01Ctrl
+{
+
+ struct
+ {
+ UINT32 bar01_type : 5 ;
+ UINT32 bar01_tc : 3 ;
+ UINT32 bar01_td : 1 ;
+ UINT32 bar01_attr : 2 ;
+ UINT32 Reserved_51 : 5 ;
+ UINT32 bar01_at : 2 ;
+ UINT32 bar01_match_en : 1 ;
+ UINT32 Reserved_50 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_NTB_IEP_BAR01_CTRL_U;
+
+
+
+
+typedef union tagIepNtbIepBar23Ctrl
+{
+
+ struct
+ {
+ UINT32 bar23_type : 5 ;
+ UINT32 bar23_tc : 3 ;
+ UINT32 bar23_td : 1 ;
+ UINT32 bar23_attr : 2 ;
+ UINT32 Reserved_53 : 5 ;
+ UINT32 bar23_at : 2 ;
+ UINT32 bar23_match_en : 1 ;
+ UINT32 Reserved_52 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_NTB_IEP_BAR23_CTRL_U;
+
+
+
+
+typedef union tagIepNtbIepBar45Ctrl
+{
+
+ struct
+ {
+ UINT32 bar45_type : 5 ;
+ UINT32 bar45_tc : 3 ;
+ UINT32 bar45_td : 1 ;
+ UINT32 bar45_attr : 2 ;
+ UINT32 Reserved_55 : 5 ;
+ UINT32 bar45_at : 2 ;
+ UINT32 bar45_match_en : 1 ;
+ UINT32 Reserved_54 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_NTB_IEP_BAR45_CTRL_U;
+
+
+
+
+typedef union tagIepMsiCtrlIntEn
+{
+
+ struct
+ {
+ UINT32 msi_int_en : 1 ;
+ UINT32 Reserved_56 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_CTRL_INT_EN_U;
+
+
+
+
+typedef union tagIepMsiCtrlInt0Mask
+{
+
+ struct
+ {
+ UINT32 msi_int_mask : 1 ;
+ UINT32 Reserved_57 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_CTRL_INT0_MASK_U;
+
+
+
+
+typedef union tagIepMsiCtrlIntStatus
+{
+
+ struct
+ {
+ UINT32 msi_int : 1 ;
+ UINT32 Reserved_58 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_IEP_MSI_CTRL_INT_STATUS_U;
+
+
+#define PCI_SYS_BASE (0x00000000)
+
+
+
+
+#define PCIE_CTRL_0_REG (PCI_SYS_BASE + 0xF8)
+#define PCIE_CTRL_1_REG (PCI_SYS_BASE + 0xFC)
+#define PCIE_CTRL_2_REG (PCI_SYS_BASE + 0x100)
+#define PCIE_CTRL_3_REG (PCI_SYS_BASE + 0x104)
+#define PCIE_CTRL_4_REG (PCI_SYS_BASE + 0x108)
+#define PCIE_CTRL_5_REG (PCI_SYS_BASE + 0x10C)
+#define PCIE_CTRL_6_REG (PCI_SYS_BASE + 0x110)
+#define PCIE_CTRL_7_REG (PCI_SYS_BASE + 0x114)
+#define PCIE_CTRL_9_REG (PCI_SYS_BASE + 0x11C)
+#define PCIE_CTRL_10_REG (PCI_SYS_BASE + 0x120)
+#define PCIE_CTRL_11_REG (PCI_SYS_BASE + 0x124)
+#define PCIE_SYS_CTRL12_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_SYS_CTRL13_REG (PCI_SYS_BASE + 0x4)
+#define PCIE_SYS_CTRL14_REG (PCI_SYS_BASE + 0x8)
+#define PCIE_SYS_CTRL15_REG (PCI_SYS_BASE + 0xC)
+#define PCIE_SYS_CTRL16_REG (PCI_SYS_BASE + 0x10)
+#define PCIE_SYS_CTRL17_REG (PCI_SYS_BASE + 0x14)
+#define PCIE_SYS_CTRL18_REG (PCI_SYS_BASE + 0x18)
+#define PCIE_SYS_CTRL19_REG (PCI_SYS_BASE + 0x1C)
+#define PCIE_SYS_CTRL20_REG (PCI_SYS_BASE + 0x20)
+#define PCIE_RD_TAB_SEL BIT31
+#define PCIE_RD_TAB_EN BIT30
+#define PCIE_SYS_CTRL21_REG (PCI_SYS_BASE + 0x24)
+#define PCIE_SYS_CTRL22_REG (PCI_SYS_BASE + 0x28)
+#define PCIE_SYS_CTRL23_REG (PCI_SYS_BASE + 0x2C)
+#define PCIE_SYS_CTRL24_REG (PCI_SYS_BASE + 0x1b4)
+#define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4)
+#define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8)
+#define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30)
+#define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34)
+#define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38)
+#define PCIE_SYS_STATE8_REG (PCI_SYS_BASE + 0x3C)
+#define PCIE_SYS_STATE9_REG (PCI_SYS_BASE + 0x40)
+#define PCIE_SYS_STATE10_REG (PCI_SYS_BASE + 0x44)
+#define PCIE_SYS_STATE11_REG (PCI_SYS_BASE + 0x48)
+#define PCIE_SYS_STATE12_REG (PCI_SYS_BASE + 0x4C)
+#define PCIE_SYS_STATE13_REG (PCI_SYS_BASE + 0x50)
+#define PCIE_SYS_STATE14_REG (PCI_SYS_BASE + 0x54)
+#define PCIE_SYS_STATE15_REG (PCI_SYS_BASE + 0x58)
+#define PCIE_SYS_STATE16_REG (PCI_SYS_BASE + 0x5C)
+#define PCIE_SYS_STATE17_REG (PCI_SYS_BASE + 0x60)
+#define PCIE_SYS_STATE18_REG (PCI_SYS_BASE + 0x64)
+#define PCIE_SYS_STATE19_REG (PCI_SYS_BASE + 0x68)
+#define PCIE_SYS_STATE20_REG (PCI_SYS_BASE + 0x6C)
+#define PCIE_SYS_STATE21_REG (PCI_SYS_BASE + 0x70)
+#define PCIE_SYS_STATE22_REG (PCI_SYS_BASE + 0x74)
+#define PCIE_SYS_STATE23_REG (PCI_SYS_BASE + 0x78)
+#define PCIE_SYS_STATE24_REG (PCI_SYS_BASE + 0x7C)
+#define PCIE_SYS_STATE25_REG (PCI_SYS_BASE + 0x80)
+#define PCIE_SYS_STATE26_REG (PCI_SYS_BASE + 0x84)
+#define PCIE_SYS_STATE27_REG (PCI_SYS_BASE + 0x88)
+#define PCIE_SYS_STATE28_REG (PCI_SYS_BASE + 0x8C)
+#define PCIE_SYS_STATE29_REG (PCI_SYS_BASE + 0x90)
+#define PCIE_SYS_STATE30_REG (PCI_SYS_BASE + 0x94)
+#define PCIE_SYS_STATE31_REG (PCI_SYS_BASE + 0x98)
+#define PCIE_SYS_STATE32_REG (PCI_SYS_BASE + 0x9C)
+#define PCIE_SYS_STATE33_REG (PCI_SYS_BASE + 0xA0)
+#define PCIE_SYS_STATE34_REG (PCI_SYS_BASE + 0xA4)
+#define PCIE_SYS_STATE35_REG (PCI_SYS_BASE + 0xA8)
+#define PCIE_SYS_STATE36_REG (PCI_SYS_BASE + 0xAC)
+#define PCIE_SYS_STATE37_REG (PCI_SYS_BASE + 0xB0)
+#define PCIE_SYS_STATE38_REG (PCI_SYS_BASE + 0xB4)
+#define PCIE_SYS_STATE39_REG (PCI_SYS_BASE + 0xB8)
+#define PCIE_SYS_STATE40_REG (PCI_SYS_BASE + 0xBC)
+#define PCIE_SYS_STATE41_REG (PCI_SYS_BASE + 0xC0)
+#define PCIE_SYS_STATE42_REG (PCI_SYS_BASE + 0xC4)
+#define PCIE_SYS_STATE43_REG (PCI_SYS_BASE + 0xC8)
+#define PCIE_SYS_STATE44_REG (PCI_SYS_BASE + 0xCC)
+#define PCIE_SYS_STATE45_REG (PCI_SYS_BASE + 0xD0)
+#define PCIE_SYS_STATE46_REG (PCI_SYS_BASE + 0xD4)
+#define PCIE_SYS_STATE47_REG (PCI_SYS_BASE + 0xD8)
+#define PCIE_SYS_STATE48_REG (PCI_SYS_BASE + 0xDC)
+#define PCIE_SYS_STATE49_REG (PCI_SYS_BASE + 0xE0)
+#define PCIE_SYS_STATE50_REG (PCI_SYS_BASE + 0xE4)
+#define PCIE_SYS_STATE51_REG (PCI_SYS_BASE + 0xE8)
+#define PCIE_SYS_STATE52_REG (PCI_SYS_BASE + 0xEC)
+#define PCIE_SYS_STATE53_REG (PCI_SYS_BASE + 0xF0)
+#define PCIE_SYS_STATE54_REG (PCI_SYS_BASE + 0xF4)
+#define PCIE_STAT_0_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_1_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_2_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_3_REG (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_4_REG (PCI_SYS_BASE + 0x0)
+
+
+
+typedef union tagPcieCtrl0
+{
+
+ struct
+ {
+ UINT32 pcie2_slv_awmisc_info : 22 ;
+ UINT32 pcie2_slv_resp_err_map : 6 ;
+ UINT32 pcie2_slv_device_type : 4 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_0_U;
+
+
+
+
+typedef union tagPcieCtrl1
+{
+
+ struct
+ {
+ UINT32 pcie2_slv_armisc_info : 22 ;
+ UINT32 pcie2_common_clocks : 1 ;
+ UINT32 pcie2_app_clk_req_n : 1 ;
+ UINT32 pcie2_ven_msg_code : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_1_U;
+
+
+
+
+typedef union tagPcieCtrl2
+{
+
+ struct
+ {
+ UINT32 pcie2_mstr_bmisc_info : 14 ;
+ UINT32 pcie2_mstr_rmisc_info : 12 ;
+ UINT32 pcie2_ven_msi_req : 1 ;
+ UINT32 pcie2_ven_msi_vector : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_2_U;
+
+
+
+
+typedef union tagPcieCtrl3
+{
+
+ struct
+ {
+ UINT32 pcie2_ven_msg_req : 1 ;
+ UINT32 pcie2_ven_msg_fmt : 2 ;
+ UINT32 pcie2_ven_msg_type : 5 ;
+ UINT32 pcie2_ven_msg_td : 1 ;
+ UINT32 pcie2_ven_msg_ep : 1 ;
+ UINT32 pcie2_ven_msg_attr : 2 ;
+ UINT32 pcie2_ven_msg_len : 10 ;
+ UINT32 pcie2_ven_msg_tag : 8 ;
+ UINT32 pcie_mstr_rresp_int_enable : 1 ;
+ UINT32 pcie_mstr_bresp_int_enable : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_3_U;
+
+
+
+
+typedef union tagPcieCtrl7
+{
+
+ struct
+ {
+ UINT32 pcie2_app_init_rst : 1 ;
+ UINT32 pcie2_app_req_entr_l1 : 1 ;
+ UINT32 pcie2_app_ready_entr_l23 : 1 ;
+ UINT32 pcie2_app_req_exit_l1 : 1 ;
+ UINT32 pcie2_app_req_retry_en : 1 ;
+ UINT32 pcie2_sys_int : 1 ;
+ UINT32 pcie2_outband_pwrup_cmd : 1 ;
+ UINT32 pcie2_app_unlock_msg : 1 ;
+ UINT32 pcie2_apps_pm_xmt_turnoff : 1 ;
+ UINT32 pcie2_apps_pm_xmt_pme : 1 ;
+ UINT32 pcie2_sys_aux_pwr_det : 1 ;
+ UINT32 pcie2_app_ltssm_enable : 1 ;
+ UINT32 pcie2_cfg_pwr_ctrler_ctrl_pol : 1 ;
+ UINT32 Reserved_7 : 1 ;
+ UINT32 pcie2_sys_mrl_sensor_state : 1 ;
+ UINT32 pcie2_sys_pwr_fault_det : 1 ;
+ UINT32 pcie2_sys_mrl_sensor_chged : 1 ;
+ UINT32 Reserved_6 : 1 ;
+ UINT32 pcie2_sys_cmd_cpled_int : 1 ;
+ UINT32 pcie2_sys_eml_interlock_engaged : 1 ;
+ UINT32 pcie2_cfg_l1_clk_removal_en : 1 ;
+ UINT32 pcie0_int_ctrl : 8 ;
+ UINT32 pcie_linkdown_auto_rstn_enable : 1 ;
+ UINT32 pcie_err_bresp_enable : 1 ;
+ UINT32 pcie_err_rresp_enable : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_7_U;
+
+
+
+
+typedef union tagPcieCtrl9
+{
+
+ struct
+ {
+ UINT32 cfg_l1_aux_clk_switch_core_clk_gate_en : 1 ;
+ UINT32 cfg_l1_mac_powerdown_override_to_p2_en : 1 ;
+ UINT32 Reserved_9 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_9_U;
+
+
+
+
+typedef union tagPcieCtrl10
+{
+
+ struct
+ {
+ UINT32 cfg_aer_rc_err_msi_mask : 1 ;
+ UINT32 cfg_sys_err_rc_mask : 1 ;
+ UINT32 radm_correctable_err_mask : 1 ;
+ UINT32 radm_nonfatal_err_mask : 1 ;
+ UINT32 radm_fatal_err_mask : 1 ;
+ UINT32 radm_pm_pme_mask : 1 ;
+ UINT32 radm_pm_to_ack_mask : 1 ;
+ UINT32 ven_msi_int_mask : 1 ;
+ UINT32 radm_cpl_timeout_mask : 1 ;
+ UINT32 radm_msg_unlock_mask : 1 ;
+ UINT32 cfg_pme_msi_mask : 1 ;
+ UINT32 bridge_flush_not_mask : 1 ;
+ UINT32 link_req_rst_not_mask : 1 ;
+ UINT32 pcie_p2_exit_int_mask : 1 ;
+ UINT32 pcie_rx_lane_flip_en_tmp : 1 ;
+ UINT32 pcie_tx_lane_flip_en_tmp : 1 ;
+ UINT32 radm_pm_turnoff_mask : 1 ;
+ UINT32 Reserved_11 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_10_U;
+
+
+
+
+typedef union tagPcieCtrl11
+{
+
+ struct
+ {
+ UINT32 cfg_aer_rc_err_msi_clr : 1 ;
+ UINT32 cfg_sys_err_rc_clr : 1 ;
+ UINT32 radm_correctable_err_clr : 1 ;
+ UINT32 radm_nonfatal_err_clr : 1 ;
+ UINT32 radm_fatal_err_clr : 1 ;
+ UINT32 radm_pm_pme_clr : 1 ;
+ UINT32 radm_pm_to_ack_clr : 1 ;
+ UINT32 ven_msi_int_clr : 1 ;
+ UINT32 radm_cpl_timeout_clr : 1 ;
+ UINT32 radm_msg_unlock_clr : 1 ;
+ UINT32 cfg_pme_msi_clr : 1 ;
+ UINT32 bridge_flush_not_clr : 1 ;
+ UINT32 link_req_rst_not_clr : 1 ;
+ UINT32 pcie_p2_exit_int_clr : 1 ;
+ UINT32 pcie_slv_err_int_clr : 1 ;
+ UINT32 pcie_mstr_err_int_clr : 1 ;
+ UINT32 radm_pm_turnoff_clr : 1 ;
+ UINT32 cfg_ntb_mode : 1 ;
+ UINT32 Reserved_13 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_CTRL_11_U;
+
+
+
+
+typedef union tagPcieSysCtrl12
+{
+
+ struct
+ {
+ UINT32 slv_awmisc_info_func_num : 1 ;
+ UINT32 slv_awmisc_info_vfunc_active : 1 ;
+ UINT32 slv_awmisc_info_vfunc_num : 1 ;
+ UINT32 Reserved_17 : 1 ;
+ UINT32 slv_armisc_info_func_num : 1 ;
+ UINT32 slv_armisc_info_vfunc_active : 1 ;
+ UINT32 slv_armisc_info_vfunc_num : 1 ;
+ UINT32 Reserved_16 : 1 ;
+ UINT32 slv_awmisc_info_nw : 1 ;
+ UINT32 slv_awmisc_info_ats : 2 ;
+ UINT32 slv_armisc_info_nw : 1 ;
+ UINT32 slv_armisc_info_ats : 2 ;
+ UINT32 mstr_bmisc_info_ats : 2 ;
+ UINT32 mstr_rmisc_info_ats : 2 ;
+ UINT32 pcie_rfs_ctrl : 6 ;
+ UINT32 pcie_rft_ctrl : 7 ;
+ UINT32 Reserved_15 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL12_U;
+
+
+
+
+typedef union tagPcieSysCtrl16
+{
+
+ struct
+ {
+ UINT32 app_flr_pf_done : 1 ;
+ UINT32 app_flr_vf_done : 2 ;
+ UINT32 Reserved_23 : 5 ;
+ UINT32 ven_msi_vfunc_active : 1 ;
+ UINT32 ven_msi_vfunc_num : 1 ;
+ UINT32 ven_msg_vfunc_active : 1 ;
+ UINT32 ven_msg_vfunc_num : 1 ;
+ UINT32 Reserved_22 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL16_U;
+
+
+
+
+typedef union tagPcieSysCtrl20
+{
+
+ struct
+ {
+ UINT32 ro_sel : 1 ;
+ UINT32 dbi_func_num : 1 ;
+ UINT32 dbi_vfunc_num : 1 ;
+ UINT32 dbi_vfunc_active : 1 ;
+ UINT32 dbi_addr_h20 : 20 ;
+ UINT32 dbi_bar_num : 3 ;
+ UINT32 dbi_rom_access : 1 ;
+ UINT32 dbi_io_access : 1 ;
+ UINT32 memicg_bypass : 1 ;
+ UINT32 Reserved_28 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL20_U;
+
+
+
+
+typedef union tagPcieSysCtrl21
+{
+
+ struct
+ {
+ UINT32 pcie_sys_pre_det_state : 1 ;
+ UINT32 pcie_sys_atten_button_pressed : 1 ;
+ UINT32 Reserved_30 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL21_U;
+
+
+
+
+typedef union tagPcieSysCtrl23
+{
+
+ struct
+ {
+ UINT32 Reserved_35 : 2 ;
+ UINT32 Reserved_34 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_CTRL23_U;
+
+
+
+
+typedef union tagPcieSysState5
+{
+
+ struct
+ {
+ UINT32 mstr_awmisc_info_func_num : 1 ;
+ UINT32 mstr_awmisc_info_vfunc_active : 1 ;
+ UINT32 mstr_awmisc_info_vfunc_num : 1 ;
+ UINT32 Reserved_39 : 1 ;
+ UINT32 mstr_armisc_info_func_num : 1 ;
+ UINT32 mstr_armisc_info_vfunc_active : 1 ;
+ UINT32 mstr_armisc_info_vfunc_num : 1 ;
+ UINT32 Reserved_38 : 1 ;
+ UINT32 mstr_awmisc_info_nw : 1 ;
+ UINT32 mstr_awmisc_info_ats : 2 ;
+ UINT32 mstr_armisc_info_nw : 1 ;
+ UINT32 mstr_armisc_info_ats : 2 ;
+ UINT32 slv_bmisc_info_ats : 2 ;
+ UINT32 slv_rmisc_info_ats : 2 ;
+ UINT32 Reserved_37 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE5_U;
+
+
+
+
+typedef union tagPcieSysState6
+{
+
+ struct
+ {
+ UINT32 cfg_flr_pf_active : 1 ;
+ UINT32 cfg_flr_vf_active : 2 ;
+ UINT32 Reserved_41 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE6_U;
+
+
+
+
+typedef union tagPcieSysState7
+{
+
+ struct
+ {
+ UINT32 radm_timeout_vfunc_active : 1 ;
+ UINT32 radm_timeout_vfunc_num : 1 ;
+ UINT32 trgt_timeout_cpl_vfunc_active : 1 ;
+ UINT32 trgt_timeout_cpl_vfunc_num : 1 ;
+ UINT32 Reserved_43 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE7_U;
+
+
+
+
+typedef union tagPcieSysState11
+{
+
+ struct
+ {
+ UINT32 cfg_msi_64 : 1 ;
+ UINT32 cfg_vf_msi_en : 2 ;
+ UINT32 cfg_vf_msi_64 : 2 ;
+ UINT32 cfg_multi_msi_en : 3 ;
+ UINT32 cfg_vf_multi_msi_en : 6 ;
+ UINT32 Reserved_48 : 2 ;
+ UINT32 cfg_msi_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE11_U;
+
+
+
+
+typedef union tagPcieSysState12
+{
+
+ struct
+ {
+ UINT32 cfg_vf_en : 1 ;
+ UINT32 cfg_ari_fwd_en : 1 ;
+ UINT32 cfg_vf_bme : 2 ;
+ UINT32 Reserved_51 : 4 ;
+ UINT32 cfg_num_vf : 16 ;
+ UINT32 Reserved_50 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE12_U;
+
+
+
+
+typedef union tagPcieSysState20
+{
+
+ struct
+ {
+ UINT32 slv_bmisc_info : 11 ;
+ UINT32 slv_rmisc_info : 11 ;
+ UINT32 rtlh_rfc_upd : 1 ;
+ UINT32 Reserved_60 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE20_U;
+
+
+
+
+typedef union tagPcieSysState21
+{
+
+ struct
+ {
+ UINT32 cfg_msix_en : 1 ;
+ UINT32 cfg_msix_func_mask : 1 ;
+ UINT32 cfg_vf_msix_func_mask : 2 ;
+ UINT32 cfg_vf_msix_en : 2 ;
+ UINT32 Reserved_62 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE21_U;
+
+
+
+
+typedef union tagPcieSysState22
+{
+
+ struct
+ {
+ UINT32 lbc_ext_vfunc_active : 1 ;
+ UINT32 lbc_ext_vfunc_num : 1 ;
+ UINT32 lbc_dbi_ack : 1 ;
+ UINT32 pcie_mstr_awmisc_info : 24 ;
+ UINT32 Reserved_64 : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE22_U;
+
+
+
+
+typedef union tagPcieSysState27
+{
+
+ struct
+ {
+ UINT32 trgt_cpl_timeout : 1 ;
+ UINT32 trgt_timeout_cpl_func_num : 1 ;
+ UINT32 trgt_timeout_cpl_tc : 3 ;
+ UINT32 trgt_timeout_cpl_attr : 2 ;
+ UINT32 trgt_timeout_cpl_len : 12 ;
+ UINT32 trgt_lookup_empty : 1 ;
+ UINT32 Reserved_70 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE27_U;
+
+
+
+
+typedef union tagPcieSysState28
+{
+
+ struct
+ {
+ UINT32 trgt_timeout_lookup_id : 8 ;
+ UINT32 trgt_lookup_id : 8 ;
+ UINT32 radm_timeout_cpl_tag : 8 ;
+ UINT32 Reserved_72 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE28_U;
+
+
+
+
+typedef union tagPcieSysState29
+{
+
+ struct
+ {
+ UINT32 trgt_cpl_timeout : 1 ;
+ UINT32 radm_timeout_func_num : 1 ;
+ UINT32 radm_timeout_cpl_tc : 3 ;
+ UINT32 radm_timeout_cpl_attr : 2 ;
+ UINT32 radm_timeout_cpl_len : 12 ;
+ UINT32 radm_pm_turnoff : 1 ;
+ UINT32 Reserved_74 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE29_U;
+
+
+
+
+typedef union tagPcieSysState30
+{
+
+ struct
+ {
+ UINT32 cfg_pbus_num : 8 ;
+ UINT32 cfg_pbus_dev_num : 5 ;
+ UINT32 cfg_link_auto_bw_int : 1 ;
+ UINT32 cfg_bw_mgt_int : 1 ;
+ UINT32 Reserved_76 : 17 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE30_U;
+
+
+
+
+typedef union tagPcieSysState32
+{
+
+ struct
+ {
+ UINT32 mstr_awmisc_info_dma : 6 ;
+ UINT32 mstr_armisc_info_dma : 6 ;
+ UINT32 cfg_hw_auto_sp_dis : 1 ;
+ UINT32 link_timeout_flush_not : 1 ;
+ UINT32 mac_phy_clk_req_n : 1 ;
+ UINT32 wake_ref_rst_n : 1 ;
+ UINT32 pcie_wake : 1 ;
+ UINT32 Reserved_79 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE32_U;
+
+
+
+
+typedef union tagPcieSysState39
+{
+
+ struct
+ {
+ UINT32 radm_msg_unlock_reqid : 16 ;
+ UINT32 radm_nonfatal_err_reqid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE39_U;
+
+
+
+
+typedef union tagPcieSysState44
+{
+
+ struct
+ {
+ UINT32 radm_unlock_reqid : 16 ;
+ UINT32 radm_nonfatal_err_reqid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE44_U;
+
+
+
+
+typedef union tagPcieSysState49
+{
+
+ struct
+ {
+ UINT32 radm_pm_pme_reqid : 16 ;
+ UINT32 radm_pm_ack_to_reqid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_SYS_STATE49_U;
+
+
+
+
+typedef union tagPcieStat0
+{
+
+ struct
+ {
+ UINT32 pcie2_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie2_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie2_cfg_pwr_ind : 2 ;
+ UINT32 pcie2_cfg_atten_ind : 2 ;
+ UINT32 pcie2_cfg_pwr_ctrler_ctrl : 1 ;
+ UINT32 pcie2_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie2_cfg_mem_space_en : 1 ;
+ UINT32 pcie2_cfg_rcb : 1 ;
+ UINT32 pcie2_rdlh_link_up : 1 ;
+ UINT32 pcie2_pm_curnt_state : 3 ;
+ UINT32 pcie2_cfg_aer_rc_err_int : 1 ;
+ UINT32 Reserved_106 : 1 ;
+ UINT32 pcie2_cfg_aer_int_msg_num : 5 ;
+ UINT32 Reserved_105 : 1 ;
+ UINT32 pcie2_xmlh_link_up : 1 ;
+ UINT32 pcie2_wake : 1 ;
+ UINT32 pcie2_cfg_eml_control : 1 ;
+ UINT32 pcie2_hp_pme : 1 ;
+ UINT32 pcie2_hp_int : 1 ;
+ UINT32 pcie2_hp_msi : 1 ;
+ UINT32 pcie2_pm_status : 1 ;
+ UINT32 pcie2_ref_clk_req_n : 1 ;
+ UINT32 Reserved_104 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_STAT_0_U;
+
+
+
+
+typedef union tagPcieStat1
+{
+
+ struct
+ {
+ UINT32 axi_parity_errs_reg : 4 ;
+ UINT32 app_parity_errs_reg : 3 ;
+ UINT32 pm_linkst_in_l1 : 1 ;
+ UINT32 pm_linkst_in_l2 : 1 ;
+ UINT32 pm_linkst_l2_exit : 1 ;
+ UINT32 mac_phy_power_down : 2 ;
+ UINT32 radm_correctabl_err_reg : 1 ;
+ UINT32 radm_nonfatal_err_reg : 1 ;
+ UINT32 radm_fatal_err_reg : 1 ;
+ UINT32 radm_pm_to_pme_reg : 1 ;
+ UINT32 radm_pm_to_ack_reg : 1 ;
+ UINT32 radm_cpl_timeout_reg : 1 ;
+ UINT32 radm_msg_unlock_reg : 1 ;
+ UINT32 cfg_pme_msi_reg : 1 ;
+ UINT32 bridge_flush_not_reg : 1 ;
+ UINT32 link_req_rst_not_reg : 1 ;
+ UINT32 pcie2_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie2_cfg_sys_err_rc : 1 ;
+ UINT32 Reserved_107 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_STAT_1_U;
+
+
+
+
+typedef union tagPcieStat3
+{
+
+ struct
+ {
+ UINT32 radm_msg_req_id : 16 ;
+ UINT32 Reserved_108 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_STAT_3_U;
+
+
+
+
+typedef union tagPcieStat4
+{
+
+ struct
+ {
+ UINT32 ltssm_state : 6 ;
+ UINT32 mac_phy_rate : 2 ;
+ UINT32 pcie_slv_err_int_state : 1 ;
+ UINT32 retry_sram_addr : 10 ;
+ UINT32 pcie_mstr_rresp_int_state : 1 ;
+ UINT32 pcie_mstr_bresp_int_state : 1 ;
+ UINT32 pcie_radm_inta_int_state : 1 ;
+ UINT32 pcie_radm_intb_int_state : 1 ;
+ UINT32 pcie_radm_intc_int_state : 1 ;
+ UINT32 pcie_radm_intd_int_state : 1 ;
+ UINT32 pme_int_state : 1 ;
+ UINT32 radm_vendr_msg_int_state : 1 ;
+ UINT32 Reserved_109 : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_STAT_4_U;
+
+
+#define PCIE_MUL_BASE (0x1000)
+
+
+
+
+#define PCIE_MUL_MC_CTRL_REG (PCIE_MUL_BASE + 0x0)
+#define PCIE_MUL_CFG_WIN0_BAR_LOWER_REG (PCIE_MUL_BASE + 0x4)
+#define PCIE_MUL_CFG_WIN0_BAR_UPPER_REG (PCIE_MUL_BASE + 0x8)
+#define PCIE_MUL_CFG_WIN1_BAR_LOWER_REG (PCIE_MUL_BASE + 0xC)
+#define PCIE_MUL_CFG_WIN1_BAR_UPPER_REG (PCIE_MUL_BASE + 0x10)
+#define PCIE_MUL_CFG_WIN2_BAR_LOWER_REG (PCIE_MUL_BASE + 0x14)
+#define PCIE_MUL_CFG_WIN2_BAR_UPPER_REG (PCIE_MUL_BASE + 0x18)
+#define PCIE_MUL_CFG_WIN3_BAR_LOWER_REG (PCIE_MUL_BASE + 0x1C)
+#define PCIE_MUL_CFG_WIN3_BAR_UPPER_REG (PCIE_MUL_BASE + 0x20)
+#define PCIE_MUL_CFG_WIN4_BAR_LOWER_REG (PCIE_MUL_BASE + 0x24)
+#define PCIE_MUL_CFG_WIN4_BAR_UPPER_REG (PCIE_MUL_BASE + 0x28)
+#define PCIE_MUL_CFG_WIN5_BAR_LOWER_REG (PCIE_MUL_BASE + 0x2C)
+#define PCIE_MUL_CFG_WIN5_BAR_UPPER_REG (PCIE_MUL_BASE + 0x30)
+#define PCIE_MUL_CFG_WIN6_BAR_LOWER_REG (PCIE_MUL_BASE + 0x34)
+#define PCIE_MUL_CFG_WIN6_BAR_UPPER_REG (PCIE_MUL_BASE + 0x38)
+#define PCIE_MUL_CFG_WIN7_BAR_LOWER_REG (PCIE_MUL_BASE + 0x3C)
+#define PCIE_MUL_CFG_WIN7_BAR_UPPER_REG (PCIE_MUL_BASE + 0x40)
+#define PCIE_MUL_CFG_WIN8_BAR_LOWER_REG (PCIE_MUL_BASE + 0x44)
+#define PCIE_MUL_CFG_WIN8_BAR_UPPER_REG (PCIE_MUL_BASE + 0x48)
+#define PCIE_MUL_CFG_WIN9_BAR_LOWER_REG (PCIE_MUL_BASE + 0x4C)
+#define PCIE_MUL_CFG_WIN9_BAR_UPPER_REG (PCIE_MUL_BASE + 0x50)
+#define PCIE_MUL_CFG_WIN10_BAR_LOWER_REG (PCIE_MUL_BASE + 0x54)
+#define PCIE_MUL_CFG_WIN10_BAR_UPPER_REG (PCIE_MUL_BASE + 0x58)
+#define PCIE_MUL_CFG_WIN11_BAR_LOWER_REG (PCIE_MUL_BASE + 0x5C)
+#define PCIE_MUL_CFG_WIN11_BAR_UPPER_REG (PCIE_MUL_BASE + 0x60)
+#define PCIE_MUL_CFG_WIN12_BAR_LOWER_REG (PCIE_MUL_BASE + 0x64)
+#define PCIE_MUL_CFG_WIN12_BAR_UPPER_REG (PCIE_MUL_BASE + 0x68)
+#define PCIE_MUL_CFG_WIN13_BAR_LOWER_REG (PCIE_MUL_BASE + 0x6C)
+#define PCIE_MUL_CFG_WIN13_BAR_UPPER_REG (PCIE_MUL_BASE + 0x70)
+#define PCIE_MUL_CFG_WIN14_BAR_LOWER_REG (PCIE_MUL_BASE + 0x74)
+#define PCIE_MUL_CFG_WIN14_BAR_UPPER_REG (PCIE_MUL_BASE + 0x78)
+#define PCIE_MUL_CFG_WIN15_BAR_LOWER_REG (PCIE_MUL_BASE + 0x7C)
+#define PCIE_MUL_CFG_WIN15_BAR_UPPER_REG (PCIE_MUL_BASE + 0x80)
+#define PCIE_MUL_CFG_WIN0_SIZE_REG (PCIE_MUL_BASE + 0x84)
+#define PCIE_MUL_CFG_WIN1_SIZE_REG (PCIE_MUL_BASE + 0x88)
+#define PCIE_MUL_CFG_WIN2_SIZE_REG (PCIE_MUL_BASE + 0x8C)
+#define PCIE_MUL_CFG_WIN3_SIZE_REG (PCIE_MUL_BASE + 0x90)
+#define PCIE_MUL_CFG_WIN4_SIZE_REG (PCIE_MUL_BASE + 0x94)
+#define PCIE_MUL_CFG_WIN5_SIZE_REG (PCIE_MUL_BASE + 0x98)
+#define PCIE_MUL_CFG_WIN6_SIZE_REG (PCIE_MUL_BASE + 0x9C)
+#define PCIE_MUL_CFG_WIN7_SIZE_REG (PCIE_MUL_BASE + 0xA0)
+#define PCIE_MUL_CFG_WIN8_SIZE_REG (PCIE_MUL_BASE + 0xA4)
+#define PCIE_MUL_CFG_WIN9_SIZE_REG (PCIE_MUL_BASE + 0xA8)
+#define PCIE_MUL_CFG_WIN10_SIZE_REG (PCIE_MUL_BASE + 0xAC)
+#define PCIE_MUL_CFG_WIN11_SIZE_REG (PCIE_MUL_BASE + 0xB0)
+#define PCIE_MUL_CFG_WIN12_SIZE_REG (PCIE_MUL_BASE + 0xB4)
+#define PCIE_MUL_CFG_WIN13_SIZE_REG (PCIE_MUL_BASE + 0xB8)
+#define PCIE_MUL_CFG_WIN14_SIZE_REG (PCIE_MUL_BASE + 0xBC)
+#define PCIE_MUL_CFG_WIN15_SIZE_REG (PCIE_MUL_BASE + 0xC0)
+#define PCIE_MUL_CFG_WIN0_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xC4)
+#define PCIE_MUL_CFG_WIN0_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xC8)
+#define PCIE_MUL_CFG_WIN1_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xCC)
+#define PCIE_MUL_CFG_WIN1_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xD0)
+#define PCIE_MUL_CFG_WIN2_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xD4)
+#define PCIE_MUL_CFG_WIN2_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xD8)
+#define PCIE_MUL_CFG_WIN3_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xDC)
+#define PCIE_MUL_CFG_WIN3_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xE0)
+#define PCIE_MUL_CFG_WIN4_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xE4)
+#define PCIE_MUL_CFG_WIN4_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xE8)
+#define PCIE_MUL_CFG_WIN5_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xEC)
+#define PCIE_MUL_CFG_WIN5_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xF0)
+#define PCIE_MUL_CFG_WIN6_XLAT_BASE_LOWER_REG (PCIE_MUL_BASE + 0xF4)
+#define PCIE_MUL_CFG_WIN6_XLAT_BASE_UPPER_REG (PCIE_MUL_BASE + 0xF8)
+#define PCIE_MUL_CFG_WIN7_XLAT_LOWER_REG (PCIE_MUL_BASE + 0xFC)
+#define PCIE_MUL_CFG_WIN7_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x100)
+#define PCIE_MUL_CFG_WIN8_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x104)
+#define PCIE_MUL_CFG_WIN8_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x108)
+#define PCIE_MUL_CFG_WIN9_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x10C)
+#define PCIE_MUL_CFG_WIN9_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x110)
+#define PCIE_MUL_CFG_WIN10_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x114)
+#define PCIE_MUL_CFG_WIN10_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x118)
+#define PCIE_MUL_CFG_WIN11_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x11C)
+#define PCIE_MUL_CFG_WIN11_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x120)
+#define PCIE_MUL_CFG_WIN12_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x124)
+#define PCIE_MUL_CFG_WIN12_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x128)
+#define PCIE_MUL_CFG_WIN13_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x12C)
+#define PCIE_MUL_CFG_WIN13_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x130)
+#define PCIE_MUL_CFG_WIN14_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x134)
+#define PCIE_MUL_CFG_WIN14_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x138)
+#define PCIE_MUL_CFG_WIN15_XLAT_LOWER_REG (PCIE_MUL_BASE + 0x13C)
+#define PCIE_MUL_CFG_WIN15_XLAT_UPPER_REG (PCIE_MUL_BASE + 0x140)
+#define PCIE_MUL_CFG_WIN_XLAT_EN_REG (PCIE_MUL_BASE + 0x144)
+#define PCIE_MUL_CFG_MCAST_CMD_TIMEOUT_REG (PCIE_MUL_BASE + 0x148)
+#define PCIE_MUL_CFG_INT_STATUS_REG (PCIE_MUL_BASE + 0x14C)
+#define PCIE_MUL_CFG_INJECT_ECC_ERR_REG (PCIE_MUL_BASE + 0x150)
+
+
+
+
+typedef union tagMcCtrl
+{
+
+ struct
+ {
+ UINT32 cfg_mcast_en : 1 ;
+ UINT32 cfg_win0_mcast_en : 1 ;
+ UINT32 cfg_win1_mcast_en : 1 ;
+ UINT32 cfg_win2_mcast_en : 1 ;
+ UINT32 cfg_win3_mcast_en : 1 ;
+ UINT32 cfg_win4_mcast_en : 1 ;
+ UINT32 cfg_win5_mcast_en : 1 ;
+ UINT32 cfg_win6_mcast_en : 1 ;
+ UINT32 cfg_win7_mcast_en : 1 ;
+ UINT32 cfg_win8_mcast_en : 1 ;
+ UINT32 cfg_win9_mcast_en : 1 ;
+ UINT32 cfg_win10_mcast_en : 1 ;
+ UINT32 cfg_win11_mcast_en : 1 ;
+ UINT32 cfg_win12_mcast_en : 1 ;
+ UINT32 cfg_win13_mcast_en : 1 ;
+ UINT32 cfg_win14_mcast_en : 1 ;
+ UINT32 cfg_win15_mcast_en : 1 ;
+ UINT32 Reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_mc_ctrl_u;
+
+
+
+
+typedef union tagCfgWin0Size
+{
+
+ struct
+ {
+ UINT32 cfg_win0_size : 6 ;
+ UINT32 Reserved_1 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win0_size_u;
+
+
+
+
+typedef union tagCfgWin1Size
+{
+
+ struct
+ {
+ UINT32 cfg_win1_size : 6 ;
+ UINT32 Reserved_2 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win1_size_u;
+
+
+
+
+typedef union tagCfgWin2Size
+{
+
+ struct
+ {
+ UINT32 cfg_win2_size : 6 ;
+ UINT32 Reserved_3 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win2_size_u;
+
+
+
+
+typedef union tagCfgWin3Size
+{
+
+ struct
+ {
+ UINT32 cfg_win3_size : 6 ;
+ UINT32 Reserved_4 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win3_size_u;
+
+
+
+
+typedef union tagCfgWin4Size
+{
+
+ struct
+ {
+ UINT32 cfg_win4_size : 6 ;
+ UINT32 Reserved_5 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win4_size_u;
+
+
+
+
+typedef union tagCfgWin5Size
+{
+
+ struct
+ {
+ UINT32 cfg_win5_size : 6 ;
+ UINT32 Reserved_6 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win5_size_u;
+
+
+
+
+typedef union tagCfgWin6Size
+{
+
+ struct
+ {
+ UINT32 cfg_win6_size : 6 ;
+ UINT32 Reserved_7 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win6_size_u;
+
+
+
+
+typedef union tagCfgWin7Size
+{
+
+ struct
+ {
+ UINT32 cfg_win7_size : 6 ;
+ UINT32 Reserved_8 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win7_size_u;
+
+
+
+
+typedef union tagCfgWin8Size
+{
+
+ struct
+ {
+ UINT32 cfg_win8_size : 6 ;
+ UINT32 Reserved_9 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win8_size_u;
+
+
+
+
+typedef union tagCfgWin9Size
+{
+
+ struct
+ {
+ UINT32 cfg_win9_size : 6 ;
+ UINT32 Reserved_10 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win9_size_u;
+
+
+
+
+typedef union tagCfgWin10Size
+{
+
+ struct
+ {
+ UINT32 cfg_win10_size : 6 ;
+ UINT32 Reserved_11 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win10_size_u;
+
+
+
+
+typedef union tagCfgWin11Size
+{
+
+ struct
+ {
+ UINT32 cfg_win11_size : 6 ;
+ UINT32 Reserved_12 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win11_size_u;
+
+
+
+
+typedef union tagCfgWin12Size
+{
+
+ struct
+ {
+ UINT32 cfg_win12_size : 6 ;
+ UINT32 Reserved_13 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win12_size_u;
+
+
+
+
+typedef union tagCfgWin13Size
+{
+
+ struct
+ {
+ UINT32 cfg_win13_size : 6 ;
+ UINT32 Reserved_14 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win13_size_u;
+
+
+
+
+typedef union tagCfgWin14Size
+{
+
+ struct
+ {
+ UINT32 cfg_win14_size : 6 ;
+ UINT32 Reserved_15 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win14_size_u;
+
+
+
+
+typedef union tagCfgWin15Size
+{
+
+ struct
+ {
+ UINT32 cfg_win15_size : 6 ;
+ UINT32 Reserved_16 : 26 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win15_size_u;
+
+
+
+
+typedef union tagCfgWinXlatEn
+{
+
+ struct
+ {
+ UINT32 cfg_win0_xlat_en : 1 ;
+ UINT32 cfg_win1_xlat_en : 1 ;
+ UINT32 cfg_win2_xlat_en : 1 ;
+ UINT32 cfg_win3_xlat_en : 1 ;
+ UINT32 cfg_win4_xlat_en : 1 ;
+ UINT32 cfg_win5_xlat_en : 1 ;
+ UINT32 cfg_win6_xlat_en : 1 ;
+ UINT32 cfg_win7_xlat_en : 1 ;
+ UINT32 cfg_win8_xlat_en : 1 ;
+ UINT32 cfg_win9_xlat_en : 1 ;
+ UINT32 cfg_win10_xlat_en : 1 ;
+ UINT32 cfg_win11_xlat_en : 1 ;
+ UINT32 cfg_win12_xlat_en : 1 ;
+ UINT32 cfg_win13_xlat_en : 1 ;
+ UINT32 cfg_win14_xlat_en : 1 ;
+ UINT32 cfg_win15_xlat_en : 1 ;
+ UINT32 Reserved_17 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_win_xlat_en_u;
+
+
+
+
+typedef union tagCfgMcastCmdTimeout
+{
+
+ struct
+ {
+ UINT32 cfg_mcast_cmd_timeout : 10 ;
+ UINT32 Reserved_18 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_mcast_cmd_timeout_u;
+
+
+
+
+typedef union tagCfgIntStatus
+{
+
+ struct
+ {
+ UINT32 timeout_int : 1 ;
+ UINT32 ecc_err1_int : 1 ;
+ UINT32 ecc_err2_int : 1 ;
+ UINT32 Reserved_19 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_int_status_u;
+
+
+
+
+typedef union tagCfgInjectEccErr
+{
+
+ struct
+ {
+ UINT32 ecc_err_inject_en : 1 ;
+ UINT32 Reserved_20 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} pcie_mul_cfg_inject_ecc_err_u;
+
+
+#define PCIE_EP_BASE (0x00000000)
+
+
+
+
+#define PCIE_EP_PCI_CFG_HDR0_REG (PCIE_EP_BASE + 0x0)
+#define PCIE_EP_PCI_CFG_HDR1_REG (PCIE_EP_BASE + 0x4)
+#define PCIE_EP_PCI_CFG_HDR2_REG (PCIE_EP_BASE + 0x8)
+#define PCIE_EP_PCI_CFG_HDR3_REG (PCIE_EP_BASE + 0xC)
+#define PCIE_EP_PCI_CFG_HDR4_REG (PCIE_EP_BASE + 0x10)
+#define PCIE_EP_PCI_CFG_HDR5_REG (PCIE_EP_BASE + 0x14)
+#define PCIE_EP_PCI_CFG_HDR6_REG (PCIE_EP_BASE + 0x18)
+#define PCIE_EP_PCI_CFG_HDR7_REG (PCIE_EP_BASE + 0x1C)
+#define PCIE_EP_PCI_CFG_HDR8_REG (PCIE_EP_BASE + 0x20)
+#define PCIE_EP_PCI_CFG_HDR9_REG (PCIE_EP_BASE + 0x24)
+#define PCIE_EP_PCI_CFG_HDR10_REG (PCIE_EP_BASE + 0x28)
+#define PCIE_EP_PCI_CFG_HDR11_REG (PCIE_EP_BASE + 0x2C)
+#define PCIE_EP_PCI_CFG_HDR12_REG (PCIE_EP_BASE + 0x30)
+#define PCIE_EP_PCI_CFG_HDR13_REG (PCIE_EP_BASE + 0x34)
+#define PCIE_EP_PCI_CFG_HDR14_REG (PCIE_EP_BASE + 0x38)
+#define PCIE_EP_PCI_CFG_HDR15_REG (PCIE_EP_BASE + 0x3C)
+#define PCIE_EP_PCI_PM_CAP0_REG (PCIE_EP_BASE + 0x40)
+#define PCIE_EP_PCI_PM_CAP1_REG (PCIE_EP_BASE + 0x44)
+#define PCIE_EP_PCI_MSI_CAP0_REG (PCIE_EP_BASE + 0x50)
+#define PCIE_EP_PCI_MSI_CAP1_REG (PCIE_EP_BASE + 0x54)
+#define PCIE_EP_PCI_MSI_CAP2_REG (PCIE_EP_BASE + 0x58)
+#define PCIE_EP_PCI_MSI_CAP3_REG (PCIE_EP_BASE + 0x5C)
+#define PCIE_EP_PCIE_CAP0_REG (PCIE_EP_BASE + 0x70)
+#define PCIE_EP_PCIE_CAP1_REG (PCIE_EP_BASE + 0x74)
+#define PCIE_EP_PCIE_CAP2_REG (PCIE_EP_BASE + 0x78)
+#define PCIE_EP_PCIE_CAP3_REG (PCIE_EP_BASE + 0x7C)
+#define PCIE_EP_PCIE_CAP4_REG (PCIE_EP_BASE + 0x80)
+#define PCIE_EP_PCIE_CAP5_REG (PCIE_EP_BASE + 0x84)
+#define PCIE_EP_PCIE_CAP6_REG (PCIE_EP_BASE + 0x88)
+#define PCIE_EP_PCIE_CAP7_REG (PCIE_EP_BASE + 0x8C)
+#define PCIE_EP_PCIE_CAP8_REG (PCIE_EP_BASE + 0x90)
+#define PCIE_EP_PCIE_CAP9_REG (PCIE_EP_BASE + 0x94)
+#define PCIE_EP_PCIE_CAP10_REG (PCIE_EP_BASE + 0x98)
+#define PCIE_EP_PCIE_CAP11_REG (PCIE_EP_BASE + 0x9C)
+#define PCIE_EP_PCIE_CAP12_REG (PCIE_EP_BASE + 0xA0)
+#define PCIE_EP_SLOT_CAP_REG (PCIE_EP_BASE + 0xC0)
+#define PCIE_EP_AER_CAP0_REG (PCIE_EP_BASE + 0x100)
+#define PCIE_EP_AER_CAP1_REG (PCIE_EP_BASE + 0x104)
+#define PCIE_EP_AER_CAP2_REG (PCIE_EP_BASE + 0x108)
+#define PCIE_EP_AER_CAP3_REG (PCIE_EP_BASE + 0x10C)
+#define PCIE_EP_AER_CAP4_REG (PCIE_EP_BASE + 0x110)
+#define PCIE_EP_AER_CAP5_REG (PCIE_EP_BASE + 0x114)
+#define PCIE_EP_AER_CAP6_REG (PCIE_EP_BASE + 0x118)
+#define PCIE_EP_AER_CAP7_REG (PCIE_EP_BASE + 0x11C)
+#define PCIE_EP_AER_CAP8_REG (PCIE_EP_BASE + 0x120)
+#define PCIE_EP_AER_CAP9_REG (PCIE_EP_BASE + 0x124)
+#define PCIE_EP_AER_CAP10_REG (PCIE_EP_BASE + 0x128)
+#define PCIE_EP_AER_CAP11_REG (PCIE_EP_BASE + 0x12C)
+#define PCIE_EP_AER_CAP12_REG (PCIE_EP_BASE + 0x130)
+#define PCIE_EP_AER_CAP13_REG (PCIE_EP_BASE + 0x134)
+#define PCIE_EP_VC_CAP0_REG (PCIE_EP_BASE + 0x140)
+#define PCIE_EP_VC_CAP1_REG (PCIE_EP_BASE + 0x144)
+#define PCIE_EP_VC_CAP2_REG (PCIE_EP_BASE + 0x148)
+#define PCIE_EP_VC_CAP3_REG (PCIE_EP_BASE + 0x14C)
+#define PCIE_EP_VC_CAP4_REG (PCIE_EP_BASE + 0x150)
+#define PCIE_EP_VC_CAP5_REG (PCIE_EP_BASE + 0x154)
+#define PCIE_EP_VC_CAP6_REG (PCIE_EP_BASE + 0x158)
+#define PCIE_EP_VC_CAP7_REG (PCIE_EP_BASE + 0x15C)
+#define PCIE_EP_VC_CAP8_REG (PCIE_EP_BASE + 0x160)
+#define PCIE_EP_VC_CAP9_REG (PCIE_EP_BASE + 0x164)
+#define PCIE_EP_PORT_LOGIC0_REG (PCIE_EP_BASE + 0x700)
+#define PCIE_EP_PORT_LOGIC1_REG (PCIE_EP_BASE + 0x704)
+#define PCIE_EP_PORT_LOGIC2_REG (PCIE_EP_BASE + 0x708)
+#define PCIE_EP_PORT_LOGIC3_REG (PCIE_EP_BASE + 0x0)
+#define PCIE_EP_PORT_LOGIC4_REG (PCIE_EP_BASE + 0x710)
+#define PCIE_EP_PORT_LOGIC5_REG (PCIE_EP_BASE + 0x714)
+#define PCIE_EP_PORT_LOGIC6_REG (PCIE_EP_BASE + 0x718)
+#define PCIE_EP_PORT_LOGIC7_REG (PCIE_EP_BASE + 0x71C)
+#define PCIE_EP_PORT_LOGIC8_REG (PCIE_EP_BASE + 0x720)
+#define PCIE_EP_PORT_LOGIC9_REG (PCIE_EP_BASE + 0x724)
+#define PCIE_EP_PORT_LOGIC10_REG (PCIE_EP_BASE + 0x728)
+#define PCIE_EP_PORT_LOGIC11_REG (PCIE_EP_BASE + 0x72C)
+#define PCIE_EP_PORT_LOGIC12_REG (PCIE_EP_BASE + 0x730)
+#define PCIE_EP_PORT_LOGIC13_REG (PCIE_EP_BASE + 0x734)
+#define PCIE_EP_PORT_LOGIC14_REG (PCIE_EP_BASE + 0x738)
+#define PCIE_EP_PORT_LOGIC15_REG (PCIE_EP_BASE + 0x73C)
+#define PCIE_EP_PORT_LOGIC16_REG (PCIE_EP_BASE + 0x748)
+#define PCIE_EP_PORT_LOGIC17_REG (PCIE_EP_BASE + 0x74C)
+#define PCIE_EP_PORT_LOGIC18_REG (PCIE_EP_BASE + 0x750)
+#define PCIE_EP_PORT_LOGIC19_REG (PCIE_EP_BASE + 0x7A8)
+#define PCIE_EP_PORT_LOGIC20_REG (PCIE_EP_BASE + 0x7AC)
+#define PCIE_EP_PORT_LOGIC21_REG (PCIE_EP_BASE + 0x7B0)
+#define PCIE_EP_PORT_LOGIC22_REG (PCIE_EP_BASE + 0x80C)
+#define PCIE_EP_PORTLOGIC23_REG (PCIE_EP_BASE + 0x810)
+#define PCIE_EP_PORTLOGIC24_REG (PCIE_EP_BASE + 0x814)
+#define PCIE_EP_PORTLOGIC25_REG (PCIE_EP_BASE + 0x818)
+#define PCIE_EP_PORTLOGIC26_REG (PCIE_EP_BASE + 0x81C)
+#define PCIE_EP_PORTLOGIC27_REG (PCIE_EP_BASE + 0x820)
+#define PCIE_EP_PORTLOGIC28_REG (PCIE_EP_BASE + 0x824)
+#define PCIE_EP_PORTLOGIC29_REG (PCIE_EP_BASE + 0x828)
+#define PCIE_EP_PORTLOGIC30_REG (PCIE_EP_BASE + 0x82C)
+#define PCIE_EP_PORTLOGIC31_REG (PCIE_EP_BASE + 0x830)
+#define PCIE_EP_PORTLOGIC32_REG (PCIE_EP_BASE + 0x834)
+#define PCIE_EP_PORTLOGIC33_REG (PCIE_EP_BASE + 0x838)
+#define PCIE_EP_PORTLOGIC34_REG (PCIE_EP_BASE + 0x83C)
+#define PCIE_EP_PORTLOGIC35_REG (PCIE_EP_BASE + 0x840)
+#define PCIE_EP_PORTLOGIC36_REG (PCIE_EP_BASE + 0x844)
+#define PCIE_EP_PORTLOGIC37_REG (PCIE_EP_BASE + 0x848)
+#define PCIE_EP_PORTLOGIC38_REG (PCIE_EP_BASE + 0x84C)
+#define PCIE_EP_PORTLOGIC39_REG (PCIE_EP_BASE + 0x850)
+#define PCIE_EP_PORTLOGIC40_REG (PCIE_EP_BASE + 0x854)
+#define PCIE_EP_PORTLOGIC41_REG (PCIE_EP_BASE + 0x858)
+#define PCIE_EP_PORTLOGIC42_REG (PCIE_EP_BASE + 0x85C)
+#define PCIE_EP_PORTLOGIC43_REG (PCIE_EP_BASE + 0x860)
+#define PCIE_EP_PORTLOGIC44_REG (PCIE_EP_BASE + 0x864)
+#define PCIE_EP_PORTLOGIC45_REG (PCIE_EP_BASE + 0x868)
+#define PCIE_EP_PORTLOGIC46_REG (PCIE_EP_BASE + 0x86C)
+#define PCIE_EP_PORTLOGIC47_REG (PCIE_EP_BASE + 0x870)
+#define PCIE_EP_PORTLOGIC48_REG (PCIE_EP_BASE + 0x874)
+#define PCIE_EP_PORTLOGIC49_REG (PCIE_EP_BASE + 0x878)
+#define PCIE_EP_PORTLOGIC50_REG (PCIE_EP_BASE + 0x87C)
+#define PCIE_EP_PORTLOGIC51_REG (PCIE_EP_BASE + 0x880)
+#define PCIE_EP_PORTLOGIC52_REG (PCIE_EP_BASE + 0x884)
+#define PCIE_EP_PORTLOGIC53_REG (PCIE_EP_BASE + 0x888)
+#define PCIE_EP_LINK_TIMEOUT_OFF_REG (PCIE_EP_BASE + 0x8d4)
+#define PCIE_EP_PORTLOGIC54_REG (PCIE_EP_BASE + 0x900)
+#define PCIE_EP_PORTLOGIC55_REG (PCIE_EP_BASE + 0x904)
+#define PCIE_EP_PORTLOGIC56_REG (PCIE_EP_BASE + 0x908)
+#define PCIE_EP_PORTLOGIC57_REG (PCIE_EP_BASE + 0x90C)
+#define PCIE_EP_PORTLOGIC58_REG (PCIE_EP_BASE + 0x910)
+#define PCIE_EP_PORTLOGIC59_REG (PCIE_EP_BASE + 0x914)
+#define PCIE_EP_PORTLOGIC60_REG (PCIE_EP_BASE + 0x918)
+#define PCIE_EP_PORTLOGIC61_REG (PCIE_EP_BASE + 0x91C)
+#define PCIE_EP_PORTLOGIC62_REG (PCIE_EP_BASE + 0x97C)
+#define PCIE_EP_PORTLOGIC63_REG (PCIE_EP_BASE + 0x980)
+#define PCIE_EP_PORTLOGIC64_REG (PCIE_EP_BASE + 0x99C)
+#define PCIE_EP_PORTLOGIC65_REG (PCIE_EP_BASE + 0x9A0)
+#define PCIE_EP_PORTLOGIC66_REG (PCIE_EP_BASE + 0x9BC)
+#define PCIE_EP_PORTLOGIC67_REG (PCIE_EP_BASE + 0x9C4)
+#define PCIE_EP_PORTLOGIC68_REG (PCIE_EP_BASE + 0x9C8)
+#define PCIE_EP_PORTLOGIC69_REG (PCIE_EP_BASE + 0x9CC)
+#define PCIE_EP_PORTLOGIC70_REG (PCIE_EP_BASE + 0x9D0)
+#define PCIE_EP_PORTLOGIC71_REG (PCIE_EP_BASE + 0x9D4)
+#define PCIE_EP_PORTLOGIC72_REG (PCIE_EP_BASE + 0x9D8)
+#define PCIE_EP_PORTLOGIC73_REG (PCIE_EP_BASE + 0x9DC)
+#define PCIE_EP_PORTLOGIC74_REG (PCIE_EP_BASE + 0x9E0)
+#define PCIE_EP_PORTLOGIC75_REG (PCIE_EP_BASE + 0xA00)
+#define PCIE_EP_PORTLOGIC76_REG (PCIE_EP_BASE + 0xA10)
+#define PCIE_EP_PORTLOGIC77_REG (PCIE_EP_BASE + 0xA18)
+#define PCIE_EP_PORTLOGIC78_REG (PCIE_EP_BASE + 0xA1C)
+#define PCIE_EP_PORTLOGIC79_REG (PCIE_EP_BASE + 0xA24)
+#define PCIE_EP_PORTLOGIC80_REG (PCIE_EP_BASE + 0xA28)
+#define PCIE_EP_PORTLOGIC81_REG (PCIE_EP_BASE + 0xA34)
+#define PCIE_EP_PORTLOGIC82_REG (PCIE_EP_BASE + 0xA3C)
+#define PCIE_EP_PORTLOGIC83_REG (PCIE_EP_BASE + 0xA40)
+#define PCIE_EP_PORTLOGIC84_REG (PCIE_EP_BASE + 0xA44)
+#define PCIE_EP_PORTLOGIC85_REG (PCIE_EP_BASE + 0xA48)
+#define PCIE_EP_PORTLOGIC86_REG (PCIE_EP_BASE + 0xA6C)
+#define PCIE_EP_PORTLOGIC87_REG (PCIE_EP_BASE + 0xA70)
+#define PCIE_EP_PORTLOGIC88_REG (PCIE_EP_BASE + 0xA78)
+#define PCIE_EP_PORTLOGIC89_REG (PCIE_EP_BASE + 0xA7C)
+#define PCIE_EP_PORTLOGIC90_REG (PCIE_EP_BASE + 0xA80)
+#define PCIE_EP_PORTLOGIC91_REG (PCIE_EP_BASE + 0xA84)
+#define PCIE_EP_PORTLOGIC92_REG (PCIE_EP_BASE + 0xA88)
+#define PCIE_EP_PORTLOGIC93_REG (PCIE_EP_BASE + 0xA8C)
+#define PCIE_EP_PORTLOGIC94_REG (PCIE_EP_BASE + 0xA90)
+
+
+
+typedef union tagPciCfgHdr0
+{
+
+ struct
+ {
+ UINT32 vendor_id : 16 ;
+ UINT32 device_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR0_U;
+
+
+
+
+typedef union tagPciCfgHdr1
+{
+
+ struct
+ {
+ UINT32 io_space_enable : 1 ;
+ UINT32 memory_space_enable : 1 ;
+ UINT32 bus_master_enable : 1 ;
+ UINT32 specialcycleenable : 1 ;
+ UINT32 memory_write_and_invalidate : 1 ;
+ UINT32 vga_palette_snoop_enable : 1 ;
+ UINT32 parity_error_response : 1 ;
+ UINT32 idsel_stepping_waitcycle_control : 1 ;
+ UINT32 serr_enable : 1 ;
+ UINT32 fastback_to_backenable : 1 ;
+ UINT32 interrupt_disable : 1 ;
+ UINT32 Reserved_2 : 5 ;
+ UINT32 Reserved_1 : 3 ;
+ UINT32 intx_status : 1 ;
+ UINT32 capabilitieslist : 1 ;
+ UINT32 pcibus66mhzcapable : 1 ;
+ UINT32 Reserved_0 : 1 ;
+ UINT32 fastback_to_back : 1 ;
+ UINT32 masterdataparityerror : 1 ;
+ UINT32 devsel_timing : 2 ;
+ UINT32 signaled_target_abort : 1 ;
+ UINT32 received_target_abort : 1 ;
+ UINT32 received_master_abort : 1 ;
+ UINT32 signaled_system_error : 1 ;
+ UINT32 detected_parity_error : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR1_U;
+
+
+
+
+typedef union tagPciCfgHdr2
+{
+
+ struct
+ {
+ UINT32 revision_identification : 8 ;
+ UINT32 Reserved_3 : 8 ;
+ UINT32 sub_class : 8 ;
+ UINT32 baseclass : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR2_U;
+
+
+
+
+typedef union tagPciCfgHdr3
+{
+
+ struct
+ {
+ UINT32 cache_line_size : 8 ;
+ UINT32 mstr_lat_tmr : 8 ;
+ UINT32 multi_function_device : 7 ;
+ UINT32 hdr_type : 1 ;
+ UINT32 bist : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR3_U;
+
+
+
+
+typedef union tagPciCfgHdr4
+{
+
+ struct
+ {
+ UINT32 sbar01_space_inicator : 1 ;
+ UINT32 sbar01_type : 2 ;
+ UINT32 sbar01_prefetchable : 1 ;
+ UINT32 sbar01_lower : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR4_U;
+
+
+
+
+typedef union tagPciCfgHdr6
+{
+
+ struct
+ {
+ UINT32 sbar23_space_inicator : 1 ;
+ UINT32 sbar23_type : 2 ;
+ UINT32 sbar23_prefetchable : 1 ;
+ UINT32 Reserved_4 : 8 ;
+ UINT32 sbar23_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR6_U;
+
+typedef union tagPciLinkTimeOut
+{
+
+ struct
+ {
+ UINT32 link_timeout_prepriod_default : 8 ;
+ UINT32 link_timeout_enable_default : 1 ;
+ UINT32 Reserved_4 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_LINK_TIMEOUT_OFF_U;
+
+
+
+
+
+typedef union tagPciCfgHdr8
+{
+
+ struct
+ {
+ UINT32 sbar45_space_inicator : 1 ;
+ UINT32 sbar45_type : 2 ;
+ UINT32 sbar45_prefetchable : 1 ;
+ UINT32 Reserved_5 : 8 ;
+ UINT32 sbar45_lower : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR8_U;
+
+
+
+
+typedef union tagPciCfgHdr11
+{
+
+ struct
+ {
+ UINT32 subsystem_vendor_id : 16 ;
+ UINT32 subsystemid : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR11_U;
+
+
+
+
+typedef union tagPciCfgHdr13
+{
+
+ struct
+ {
+ UINT32 capptr : 8 ;
+ UINT32 Reserved_6 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR13_U;
+
+
+
+
+typedef union tagPciCfgHdr15
+{
+
+ struct
+ {
+ UINT32 int_line : 8 ;
+ UINT32 int_pin : 8 ;
+ UINT32 Min_Grant : 8 ;
+ UINT32 Max_Latency : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_CFG_HDR15_U;
+
+
+
+
+typedef union tagPciMsiCap0
+{
+
+ struct
+ {
+ UINT32 msi_cap_id : 8 ;
+ UINT32 next_capability_pointer : 8 ;
+ UINT32 msi_enabled : 1 ;
+ UINT32 multiple_message_capable : 3 ;
+ UINT32 multiple_message_enabled : 3 ;
+ UINT32 msi_64_en : 1 ;
+ UINT32 pvm_en : 1 ;
+ UINT32 message_control_register : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_MSI_CAP0_U;
+
+
+
+
+typedef union tagPciMsiCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_11 : 2 ;
+ UINT32 msi_addr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_MSI_CAP1_U;
+
+
+
+
+typedef union tagPciMsiCap3
+{
+
+ struct
+ {
+ UINT32 msi_data : 16 ;
+ UINT32 Reserved_12 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCI_MSI_CAP3_U;
+
+
+
+
+typedef union tagPcieCap0
+{
+
+ struct
+ {
+ UINT32 pcie_cap_id : 8 ;
+ UINT32 pcie_next_ptr : 8 ;
+ UINT32 pcie_capability_version : 4 ;
+ UINT32 device_port_type : 4 ;
+ UINT32 slot_implemented : 1 ;
+ UINT32 interrupt_message_number : 5 ;
+ UINT32 Reserved_13 : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP0_U;
+
+
+
+
+typedef union tagPcieCap1
+{
+
+ struct
+ {
+ UINT32 max_payload_size_supported : 3 ;
+ UINT32 phantom_function_supported : 2 ;
+ UINT32 extended_tagfield_supported : 1 ;
+ UINT32 endpoint_l0sacceptable_latency : 3 ;
+ UINT32 endpoint_l1acceptable_latency : 3 ;
+ UINT32 undefined : 3 ;
+ UINT32 Reserved_16 : 3 ;
+ UINT32 captured_slot_power_limit_value : 8 ;
+ UINT32 captured_slot_power_limit_scale : 2 ;
+ UINT32 function_level_reset : 1 ;
+ UINT32 Reserved_15 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP1_U;
+
+
+
+
+typedef union tagPcieCap2
+{
+
+ struct
+ {
+ UINT32 correctable_error_reporting_enable : 1 ;
+ UINT32 non_fatal_error_reporting_enable : 1 ;
+ UINT32 fatal_error_reporting_enable : 1 ;
+ UINT32 urenable : 1 ;
+ UINT32 enable_relaxed_ordering : 1 ;
+ UINT32 max_payload_size : 3 ;
+ UINT32 extended_tagfieldenable : 1 ;
+ UINT32 phantom_function_enable : 1 ;
+ UINT32 auxpowerpmenable : 1 ;
+ UINT32 enablenosnoop : 1 ;
+ UINT32 max_read_request_size : 3 ;
+ UINT32 Reserved_18 : 1 ;
+ UINT32 correctableerrordetected : 1 ;
+ UINT32 non_fatalerrordetected : 1 ;
+ UINT32 fatalerrordetected : 1 ;
+ UINT32 unsupportedrequestdetected : 1 ;
+ UINT32 auxpowerdetected : 1 ;
+ UINT32 transactionpending : 1 ;
+ UINT32 Reserved_17 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP2_U;
+
+
+
+
+typedef union tagPcieCap3
+{
+
+ struct
+ {
+ UINT32 max_link_speed : 4 ;
+ UINT32 max_link_width : 6 ;
+ UINT32 active_state_power_management : 2 ;
+ UINT32 l0s_exitlatency : 3 ;
+ UINT32 l1_exit_latency : 3 ;
+ UINT32 clock_power_management : 1 ;
+ UINT32 surprise_down_error_report_cap : 1 ;
+ UINT32 data_link_layer_active_report_cap : 1 ;
+ UINT32 link_bandwidth_noti_cap : 1 ;
+ UINT32 aspm_option_compliance : 1 ;
+ UINT32 Reserved_19 : 1 ;
+ UINT32 port_number : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagPcieCap4
+{
+
+ struct
+ {
+ UINT32 active_state_power_management : 2 ;
+ UINT32 Reserved_22 : 1 ;
+ UINT32 rcb : 1 ;
+ UINT32 link_disable : 1 ;
+ UINT32 retrain_link : 1 ;
+ UINT32 common_clock_config : 1 ;
+ UINT32 extended_sync : 1 ;
+ UINT32 enable_clock_pwr_management : 1 ;
+ UINT32 hw_auto_width_disable : 1 ;
+ UINT32 link_bandwidth_management_int_en : 1 ;
+ UINT32 link_auto_bandwidth_int_en : 1 ;
+ UINT32 Reserved_21 : 4 ;
+ UINT32 current_link_speed : 4 ;
+ UINT32 negotiated_link_width : 6 ;
+ UINT32 Reserved_20 : 1 ;
+ UINT32 link_training : 1 ;
+ UINT32 slot_clock_configration : 1 ;
+ UINT32 data_link_layer_active : 1 ;
+ UINT32 link_bandwidth_management_status : 1 ;
+ UINT32 link_auto_bandwidth_status : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagPcieCap5
+{
+
+ struct
+ {
+ UINT32 attentioonbuttonpresent : 1 ;
+ UINT32 powercontrollerpresent : 1 ;
+ UINT32 mrlsensorpresent : 1 ;
+ UINT32 attentionindicatorpresent : 1 ;
+ UINT32 powerindicatorpresent : 1 ;
+ UINT32 hot_plugsurprise : 1 ;
+ UINT32 hot_plugcapable : 1 ;
+ UINT32 slotpowerlimitvalue : 8 ;
+ UINT32 slotpowerlimitscale : 2 ;
+ UINT32 electromechanicalinterlockpresen : 1 ;
+ UINT32 no_cmd_complete_support : 1 ;
+ UINT32 phy_slot_number : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP5_U;
+
+
+
+
+
+typedef union tagPcieCap6
+{
+
+ struct
+ {
+ UINT32 attentionbuttonpressedenable : 1 ;
+ UINT32 powerfaultdetectedenable : 1 ;
+ UINT32 mrlsensorchangedenable : 1 ;
+ UINT32 presencedetectchangedenable : 1 ;
+ UINT32 commandcompletedinterruptenable : 1 ;
+ UINT32 hot_pluginterruptenable : 1 ;
+ UINT32 attentionindicatorcontrol : 2 ;
+ UINT32 powerindicatorcontrol : 2 ;
+ UINT32 powercontrollercontrol : 1 ;
+ UINT32 electromechanicalinterlockcontrol : 1 ;
+ UINT32 datalinklayerstatechangedenable : 1 ;
+ UINT32 Reserved_23 : 3 ;
+ UINT32 attentionbuttonpressed : 1 ;
+ UINT32 powerfaultdetected : 1 ;
+ UINT32 mrlsensorchanged : 1 ;
+ UINT32 presencedetectchanged : 1 ;
+ UINT32 commandcompleted : 1 ;
+ UINT32 mrlsensorstate : 1 ;
+ UINT32 presencedetectstate : 1 ;
+ UINT32 electromechanicalinterlockstatus : 1 ;
+ UINT32 datalinklayerstatechanged : 1 ;
+ UINT32 slot_ctrl_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagPcieCap7
+{
+
+ struct
+ {
+ UINT32 systemerroroncorrectableerrorenable : 1 ;
+ UINT32 systemerroronnon_fatalerrorenable : 1 ;
+ UINT32 systemerroronfatalerrorenable : 1 ;
+ UINT32 pmeinterruptenable : 1 ;
+ UINT32 crssoftwarevisibilityenable : 1 ;
+ UINT32 Reserved_24 : 11 ;
+ UINT32 crssoftwarevisibility : 1 ;
+ UINT32 root_cap : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagPcieCap8
+{
+
+ struct
+ {
+ UINT32 pmerequesterid : 16 ;
+ UINT32 pmestatus : 1 ;
+ UINT32 pmepending : 1 ;
+ UINT32 root_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagPcieCap9
+{
+
+ struct
+ {
+ UINT32 completiontimeoutrangessupported : 4 ;
+ UINT32 completiontimeoutdisablesupported : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoproutingsupported : 1 ;
+ UINT32 _2_bitatomicopcompletersupported : 1 ;
+ UINT32 _4_bitatomicopcompletersupported : 1 ;
+ UINT32 _28_bitcascompletersupported : 1 ;
+ UINT32 noro_enabledpr_prpassing : 1 ;
+ UINT32 Reserved_25 : 1 ;
+ UINT32 tphcompletersupported : 2 ;
+ UINT32 dev_cap2 : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagPcieCap10
+{
+
+ struct
+ {
+ UINT32 completiontimeoutvalue : 4 ;
+ UINT32 completiontimeoutdisable : 1 ;
+ UINT32 ariforwardingsupported : 1 ;
+ UINT32 atomicoprequesterenable : 1 ;
+ UINT32 atomicopegressblocking : 1 ;
+ UINT32 idorequestenable : 1 ;
+ UINT32 idocompletionenable : 1 ;
+ UINT32 dev_ctrl2 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagPcieCap11
+{
+
+ struct
+ {
+ UINT32 Reserved_27 : 1 ;
+ UINT32 gen1_suport : 1 ;
+ UINT32 gen2_suport : 1 ;
+ UINT32 gen3_suport : 1 ;
+ UINT32 Reserved_26 : 4 ;
+ UINT32 crosslink_supported : 1 ;
+ UINT32 link_cap2 : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagPcieCap12
+{
+
+ struct
+ {
+ UINT32 targetlinkspeed : 4 ;
+ UINT32 entercompliance : 1 ;
+ UINT32 hardwareautonomousspeeddisa : 1 ;
+ UINT32 selectablede_empha : 1 ;
+ UINT32 transmitmargin : 3 ;
+ UINT32 _entermodifiedcompliance : 1 ;
+ UINT32 compliancesos : 1 ;
+ UINT32 de_emphasislevel : 4 ;
+ UINT32 currentde_emphasislevel : 1 ;
+ UINT32 equalizationcomplete : 1 ;
+ UINT32 equalizationphase1successful : 1 ;
+ UINT32 equalizationphase2successful : 1 ;
+ UINT32 equalizationphase3successful : 1 ;
+ UINT32 linkequalizationrequest : 1 ;
+ UINT32 link_ctrl2_status2 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagSlotCap
+{
+
+ struct
+ {
+ UINT32 slotnumberingcapabilitiesid : 8 ;
+ UINT32 nextcapabilitypointer : 8 ;
+ UINT32 add_incardslotsprovided : 5 ;
+ UINT32 firstinchassis : 1 ;
+ UINT32 Reserved_28 : 2 ;
+ UINT32 slot_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_SLOT_CAP_U;
+
+
+
+
+typedef union tagAerCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 aer_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP0_U;
+
+
+
+
+typedef union tagAerCap1
+{
+
+ struct
+ {
+ UINT32 Reserved_34 : 1 ;
+ UINT32 Reserved_33 : 3 ;
+ UINT32 datalinkprotocolerrorsta : 1 ;
+ UINT32 surprisedownerrorstatus : 1 ;
+ UINT32 Reserved_32 : 6 ;
+ UINT32 poisonedtlpstatu : 1 ;
+ UINT32 flowcontrolprotocolerrorst : 1 ;
+ UINT32 completiontimeouts : 1 ;
+ UINT32 completerabortstatus : 1 ;
+ UINT32 receiveroverflowstatus : 1 ;
+ UINT32 malformedtlpstatus : 1 ;
+ UINT32 ecrcerrorstatus : 1 ;
+ UINT32 ecrcerrorstat : 1 ;
+ UINT32 unsupportedrequesterrorstatus : 1 ;
+ UINT32 Reserved_31 : 3 ;
+ UINT32 atomicopegressblockedstatus : 1 ;
+ UINT32 uncorr_err_status : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP1_U;
+
+
+
+
+typedef union tagAerCap2
+{
+
+ struct
+ {
+ UINT32 Reserved_38 : 1 ;
+ UINT32 Reserved_37 : 3 ;
+ UINT32 datalinkprotocolerrormask : 1 ;
+ UINT32 surprisedownerrormask : 1 ;
+ UINT32 Reserved_36 : 6 ;
+ UINT32 poisonedtlpmask : 1 ;
+ UINT32 flowcontrolprotocolerrormask : 1 ;
+ UINT32 completiontimeoutmask : 1 ;
+ UINT32 completerabortmask : 1 ;
+ UINT32 unexpectedcompletionmask : 1 ;
+ UINT32 receiveroverflowmask : 1 ;
+ UINT32 malformedtlpmask : 1 ;
+ UINT32 ecrcerrormask : 1 ;
+ UINT32 unsupportedrequesterrormask : 1 ;
+ UINT32 Reserved_35 : 3 ;
+ UINT32 atomicopegressblockedmask : 1 ;
+ UINT32 uncorr_err_mask : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP2_U;
+
+
+
+
+typedef union tagAerCap3
+{
+
+ struct
+ {
+ UINT32 Reserved_42 : 1 ;
+ UINT32 Reserved_41 : 3 ;
+ UINT32 datalinkprotocolerrorsever : 1 ;
+ UINT32 surprisedownerrorseverity : 1 ;
+ UINT32 Reserved_40 : 6 ;
+ UINT32 poisonedtlpseverity : 1 ;
+ UINT32 flowcontrolprotocolerrorseveri : 1 ;
+ UINT32 completiontimeoutseverity : 1 ;
+ UINT32 completerabortseverity : 1 ;
+ UINT32 unexpectedcompletionseverity : 1 ;
+ UINT32 receiveroverflowseverity : 1 ;
+ UINT32 malformedtlpseverity : 1 ;
+ UINT32 ecrcerrorseverity : 1 ;
+ UINT32 unsupportedrequesterrorseverity : 1 ;
+ UINT32 Reserved_39 : 3 ;
+ UINT32 atomicopegressblockedseverity : 1 ;
+ UINT32 uncorr_err_ser : 7 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP3_U;
+
+
+
+
+typedef union tagAerCap4
+{
+
+ struct
+ {
+ UINT32 receivererrorstatus : 1 ;
+ UINT32 Reserved_44 : 5 ;
+ UINT32 badtlpstatus : 1 ;
+ UINT32 baddllpstatus : 1 ;
+ UINT32 replay_numrolloverstatus : 1 ;
+ UINT32 Reserved_43 : 3 ;
+ UINT32 replytimertimeoutstatus : 1 ;
+ UINT32 advisorynon_fatalerrorstatus : 1 ;
+ UINT32 corr_err_status : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP4_U;
+
+
+
+
+typedef union tagAerCap5
+{
+
+ struct
+ {
+ UINT32 receivererrormask : 1 ;
+ UINT32 Reserved_46 : 5 ;
+ UINT32 badtlpmask : 1 ;
+ UINT32 baddllpmask : 1 ;
+ UINT32 replay_numrollovermask : 1 ;
+ UINT32 Reserved_45 : 3 ;
+ UINT32 replytimertimeoutmask : 1 ;
+ UINT32 advisorynon_fatalerrormask : 1 ;
+ UINT32 corr_err_mask : 18 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP5_U;
+
+
+
+
+typedef union tagAerCap6
+{
+
+ struct
+ {
+ UINT32 firsterrorpointer : 5 ;
+ UINT32 ecrcgenerationcapability : 1 ;
+ UINT32 ecrcgenerationenable : 1 ;
+ UINT32 ecrccheckcapable : 1 ;
+ UINT32 ecrccheckenable : 1 ;
+ UINT32 adv_cap_ctrl : 23 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP6_U;
+
+
+
+
+typedef union tagAerCap11
+{
+
+ struct
+ {
+ UINT32 correctableerrorreportingenable : 1 ;
+ UINT32 non_fatalerrorreportingenable : 1 ;
+ UINT32 fatalerrorreportingenable : 1 ;
+ UINT32 root_err_cmd : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP11_U;
+
+
+
+
+typedef union tagAerCap12
+{
+
+ struct
+ {
+ UINT32 err_correceived : 1 ;
+ UINT32 multipleerr_correceived : 1 ;
+ UINT32 err_fatal_nonfatalreceived : 1 ;
+ UINT32 multipleerr_fatal_nonfatalreceived : 1 ;
+ UINT32 firstuncorrectablefatal : 1 ;
+ UINT32 non_fatalerrormessagesreceived : 1 ;
+ UINT32 fatalerrormessagesreceived : 1 ;
+ UINT32 Reserved_47 : 20 ;
+ UINT32 root_err_status : 5 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP12_U;
+
+
+
+
+typedef union tagAerCap13
+{
+
+ struct
+ {
+ UINT32 err_corsourceidentification : 16 ;
+ UINT32 err_src_id : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_AER_CAP13_U;
+
+
+
+
+typedef union tagVcCap0
+{
+
+ struct
+ {
+ UINT32 pciexpressextendedcapabilityid : 16 ;
+ UINT32 capabilityversion : 4 ;
+ UINT32 vc_cap_hdr : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP0_U;
+
+
+
+
+typedef union tagVcCap1
+{
+
+ struct
+ {
+ UINT32 extendedvccount : 3 ;
+ UINT32 Reserved_50 : 1 ;
+ UINT32 lowpriorityextendedvccount : 3 ;
+ UINT32 Reserved_49 : 1 ;
+ UINT32 referenceclock : 2 ;
+ UINT32 portarbitrationtableentrysize : 2 ;
+ UINT32 vc_cap1 : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP1_U;
+
+
+
+
+typedef union tagVcCap2
+{
+
+ struct
+ {
+ UINT32 vcarbitrationcapability : 8 ;
+ UINT32 Reserved_51 : 16 ;
+ UINT32 vc_cap2 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP2_U;
+
+
+
+
+typedef union tagVcCap3
+{
+
+ struct
+ {
+ UINT32 loadvcarbitrationtable : 1 ;
+ UINT32 vcarbitrationselect : 3 ;
+ UINT32 Reserved_53 : 12 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 Reserved_52 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP3_U;
+
+
+
+
+typedef union tagVcCap4
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_56 : 6 ;
+ UINT32 Reserved_55 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_54 : 1 ;
+ UINT32 vc_res_cap : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP4_U;
+
+
+
+
+typedef union tagVcCap5
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_59 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselec : 3 ;
+ UINT32 Reserved_58 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_57 : 4 ;
+ UINT32 vc_res_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP5_U;
+
+
+
+
+typedef union tagVcCap6
+{
+
+ struct
+ {
+ UINT32 Reserved_60 : 16 ;
+ UINT32 portarbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP6_U;
+
+
+
+
+typedef union tagVcCap7
+{
+
+ struct
+ {
+ UINT32 portarbitrationcapability : 8 ;
+ UINT32 Reserved_63 : 6 ;
+ UINT32 Reserved_62 : 1 ;
+ UINT32 rejectsnooptransactions : 1 ;
+ UINT32 maximumtimeslots : 7 ;
+ UINT32 Reserved_61 : 1 ;
+ UINT32 vc_res_cap0 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP7_U;
+
+
+
+
+typedef union tagVcCap8
+{
+
+ struct
+ {
+ UINT32 tc_vcmap : 8 ;
+ UINT32 Reserved_66 : 8 ;
+ UINT32 loadportarbitrationtable : 1 ;
+ UINT32 portarbitrationselect : 3 ;
+ UINT32 Reserved_65 : 4 ;
+ UINT32 vcid : 3 ;
+ UINT32 Reserved_64 : 4 ;
+ UINT32 vc_res_ctrl0 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP8_U;
+
+
+
+
+typedef union tagVcCap9
+{
+
+ struct
+ {
+ UINT32 Reserved_67 : 16 ;
+ UINT32 arbitrationtablestatus : 1 ;
+ UINT32 vcnegotiationpending : 1 ;
+ UINT32 vc_res_status0 : 14 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_VC_CAP9_U;
+
+
+
+
+typedef union tagPortLogic0
+{
+
+ struct
+ {
+ UINT32 ack_lat_timer : 16 ;
+ UINT32 replay_timer : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagPortLogic2
+{
+
+ struct
+ {
+ UINT32 linknumber : 8 ;
+ UINT32 Reserved_70 : 7 ;
+ UINT32 forcelink : 1 ;
+ UINT32 linkstate : 6 ;
+ UINT32 Reserved_69 : 2 ;
+ UINT32 port_force_link : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagPortLogic3
+{
+
+ struct
+ {
+ UINT32 ackfrequency : 8 ;
+ UINT32 n_fts : 8 ;
+ UINT32 commonclockn_fts : 8 ;
+ UINT32 l0sentrancelatency : 3 ;
+ UINT32 l1entrancelatency : 3 ;
+ UINT32 enteraspml1withoutreceiveinl0s : 1 ;
+ UINT32 ack_aspm : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagPortLogic4
+{
+
+ struct
+ {
+ UINT32 vendorspecificdllprequest : 1 ;
+ UINT32 scrambledisable : 1 ;
+ UINT32 loopbackenable : 1 ;
+ UINT32 resetassert : 1 ;
+ UINT32 Reserved_73 : 1 ;
+ UINT32 dlllinkenable : 1 ;
+ UINT32 Reserved_72 : 1 ;
+ UINT32 fastlinkmode : 1 ;
+ UINT32 Reserved_71 : 8 ;
+ UINT32 linkmodeenable : 6 ;
+ UINT32 crosslinkenable : 1 ;
+ UINT32 crosslinkactive : 1 ;
+ UINT32 port_link_ctrl : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagPortLogic5
+{
+
+ struct
+ {
+ UINT32 insertlaneskewfortransmit : 24 ;
+ UINT32 flowcontroldisable : 1 ;
+ UINT32 ack_nakdisable : 1 ;
+ UINT32 Reserved_75 : 5 ;
+ UINT32 lane_skew : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagPortLogic6
+{
+
+ struct
+ {
+ UINT32 numberoftssymbols : 4 ;
+ UINT32 Reserved_77 : 4 ;
+ UINT32 numberofskpsymbols : 3 ;
+ UINT32 Reserved_76 : 3 ;
+ UINT32 timermodifierforreplaytimer : 5 ;
+ UINT32 timermodifierforack_naklatencytimer : 5 ;
+ UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ;
+ UINT32 sym_num : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagPortLogic7
+{
+
+ struct
+ {
+ UINT32 vc0posteddataqueuedepth : 11 ;
+ UINT32 Reserved_78 : 4 ;
+ UINT32 sym_timer : 1 ;
+ UINT32 maskfunctionmismatchfilteringfo : 1 ;
+ UINT32 maskpoisonedtlpfiltering : 1 ;
+ UINT32 maskbarmatchfiltering : 1 ;
+ UINT32 masktype1configurationrequestfiltering : 1 ;
+ UINT32 masklockedrequestfiltering : 1 ;
+ UINT32 masktagerrorrulesforreceivedcompletions : 1 ;
+ UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ;
+ UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ;
+ UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ;
+ UINT32 maske_crcerror_filtering : 1 ;
+ UINT32 maske_crcerror_filtering_forcompletions : 1 ;
+ UINT32 message_control : 1 ;
+ UINT32 maskfilteringofreceived : 1 ;
+ UINT32 flt_mask1 : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagPortLogic8
+{
+
+ struct
+ {
+ UINT32 cx_flt_mask_venmsg0_drop : 1 ;
+ UINT32 cx_flt_mask_venmsg1_drop : 1 ;
+ UINT32 cx_flt_mask_dabort_4ucpl : 1 ;
+ UINT32 cx_flt_mask_handle_flush : 1 ;
+ UINT32 flt_mask2 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagPortLogic9
+{
+
+ struct
+ {
+ UINT32 amba_multi_outbound_decomp_np : 1 ;
+ UINT32 amba_obnp_ctrl : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagPortLogic12
+{
+
+ struct
+ {
+ UINT32 transmitposteddatafccredits : 12 ;
+ UINT32 transmitpostedheaderfccredits : 8 ;
+ UINT32 tx_pfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagPortLogic13
+{
+
+ struct
+ {
+ UINT32 transmitnon_posteddatafccredits : 12 ;
+ UINT32 transmitnon_postedheaderfccredits : 8 ;
+ UINT32 tx_npfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagPortLogic14
+{
+
+ struct
+ {
+ UINT32 transmitcompletiondatafccredits : 12 ;
+ UINT32 transmitcompletionheaderfccredits : 8 ;
+ UINT32 tx_cplfc_status : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagPortLogic15
+{
+
+ struct
+ {
+ UINT32 rx_tlp_fc_credit_not_retured : 1 ;
+ UINT32 tx_retry_buf_not_empty : 1 ;
+ UINT32 rx_queue_not_empty : 1 ;
+ UINT32 Reserved_80 : 13 ;
+ UINT32 fc_latency_timer_override_value : 13 ;
+ UINT32 Reserved_79 : 2 ;
+ UINT32 fc_latency_timer_override_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagPortLogic16
+{
+
+ struct
+ {
+ UINT32 vc0posteddatacredits : 12 ;
+ UINT32 vc0postedheadercredits : 8 ;
+ UINT32 Reserved_82 : 1 ;
+ UINT32 vc0_postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemode : 1 ;
+ UINT32 vc0postedtlpqueuemo : 1 ;
+ UINT32 Reserved_81 : 6 ;
+ UINT32 tlptypeorderingforvc0 : 1 ;
+ UINT32 rx_pque_ctrl : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagPortLogic17
+{
+
+ struct
+ {
+ UINT32 vc0non_posteddatacredits : 12 ;
+ UINT32 vc0non_postedheadercredits : 8 ;
+ UINT32 rx_npque_ctrl : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagPortLogic18
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_credits : 12 ;
+ UINT32 vc0_cpl_header_credt : 8 ;
+ UINT32 Reserved_84 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagPortLogic19
+{
+
+ struct
+ {
+ UINT32 vco_posted_data_que_path : 14 ;
+ UINT32 Reserved_85 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 vc_pbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagPortLogic20
+{
+
+ struct
+ {
+ UINT32 vco_np_data_que_depth : 14 ;
+ UINT32 Reserved_87 : 2 ;
+ UINT32 vco_np_header_que_depth : 10 ;
+ UINT32 vc_npbuf_ctrl : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagPortLogic21
+{
+
+ struct
+ {
+ UINT32 vco_comp_data_queue_depth : 14 ;
+ UINT32 Reserved_89 : 2 ;
+ UINT32 vco_posted_head_queue_depth : 10 ;
+ UINT32 Reserved_88 : 6 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagPortLogic22
+{
+
+ struct
+ {
+ UINT32 n_fts : 8 ;
+ UINT32 pre_determ_num_of_lane : 9 ;
+ UINT32 det_sp_change : 1 ;
+ UINT32 config_phy_tx_sw : 1 ;
+ UINT32 config_tx_comp_rcv_bit : 1 ;
+ UINT32 set_emp_level : 1 ;
+ UINT32 Reserved_90 : 11 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagPortlogic25
+{
+
+ struct
+ {
+ UINT32 remote_rd_req_size : 3 ;
+ UINT32 Reserved_93 : 5 ;
+ UINT32 remote_max_brd_tag : 8 ;
+ UINT32 Reserved_92 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagPortlogic26
+{
+
+ struct
+ {
+ UINT32 resize_master_resp_compser : 1 ;
+ UINT32 axi_ctrl1 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagPortlogic54
+{
+
+ struct
+ {
+ UINT32 region_index : 4 ;
+ UINT32 Reserved_94 : 27 ;
+ UINT32 iatu_view : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC54_U;
+
+
+
+
+typedef union tagPortlogic55
+{
+
+ struct
+ {
+ UINT32 iatu1_type : 5 ;
+ UINT32 iatu1_tc : 3 ;
+ UINT32 iatu1_td : 1 ;
+ UINT32 iatu1_attr : 2 ;
+ UINT32 Reserved_98 : 5 ;
+ UINT32 iatu1_at : 2 ;
+ UINT32 Reserved_97 : 2 ;
+ UINT32 iatu1_id : 3 ;
+ UINT32 Reserved_96 : 9 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagPortlogic56
+{
+
+ struct
+ {
+ UINT32 iatu2_type : 8 ;
+ UINT32 iatu2_bar_num : 3 ;
+ UINT32 Reserved_102 : 3 ;
+ UINT32 iatu2_tc_match_en : 1 ;
+ UINT32 iatu2_td_match_en : 1 ;
+ UINT32 iatu2_attr_match_en : 1 ;
+ UINT32 Reserved_101 : 1 ;
+ UINT32 iatu2_at_match_en : 1 ;
+ UINT32 iatu2_func_num_match_en : 1 ;
+ UINT32 iatu2_virtual_func_num_match_en : 1 ;
+ UINT32 message_code_match_en : 1 ;
+ UINT32 Reserved_100 : 2 ;
+ UINT32 iatu2_response_code : 2 ;
+ UINT32 Reserved_99 : 1 ;
+ UINT32 iatu2_fuzzy_type_match_mode : 1 ;
+ UINT32 iatu2_cfg_shift_mode : 1 ;
+ UINT32 iatu2_ivert_mode : 1 ;
+ UINT32 iatu2_match_mode : 1 ;
+ UINT32 iatu2_region_en : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagPortlogic57
+{
+
+ struct
+ {
+ UINT32 iatu_start_low : 12 ;
+ UINT32 iatu_start_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagPortlogic59
+{
+
+ struct
+ {
+ UINT32 iatu_limit_low : 12 ;
+ UINT32 iatu_limit_high : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagPortlogic60
+{
+
+ struct
+ {
+ UINT32 xlated_addr_high : 12 ;
+ UINT32 xlated_addr_low : 20 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagPortlogic62
+{
+
+ struct
+ {
+ UINT32 dma_wr_eng_en : 1 ;
+ UINT32 dma_wr_ena : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagPortlogic63
+{
+
+ struct
+ {
+ UINT32 wr_doorbell_num : 3 ;
+ UINT32 Reserved_104 : 28 ;
+ UINT32 dma_wr_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagPortlogic64
+{
+
+ struct
+ {
+ UINT32 dma_read_eng_en : 1 ;
+ UINT32 Reserved_105 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagPortlogic65
+{
+
+ struct
+ {
+ UINT32 rd_doorbell_num : 3 ;
+ UINT32 Reserved_107 : 28 ;
+ UINT32 dma_rd_dbell_stop : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagPortlogic66
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_109 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_108 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagPortlogic67
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_112 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 Reserved_111 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagPortlogic68
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_115 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 Reserved_114 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagPortlogic69
+{
+
+ struct
+ {
+ UINT32 app_rd_err_det : 8 ;
+ UINT32 Reserved_117 : 8 ;
+ UINT32 ll_element_fetch_err_det : 8 ;
+ UINT32 Reserved_116 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagPortlogic74
+{
+
+ struct
+ {
+ UINT32 dma_wr_c0_imwr_data : 16 ;
+ UINT32 dma_wr_c1_imwr_data : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagPortlogic75
+{
+
+ struct
+ {
+ UINT32 wr_ch_ll_remote_abort_int_en : 8 ;
+ UINT32 Reserved_119 : 8 ;
+ UINT32 wr_ch_ll_local_abort_int_en : 8 ;
+ UINT32 Reserved_118 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagPortlogic76
+{
+
+ struct
+ {
+ UINT32 done_int_status : 8 ;
+ UINT32 Reserved_122 : 8 ;
+ UINT32 abort_int_status : 8 ;
+ UINT32 Reserved_121 : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagPortlogic77
+{
+
+ struct
+ {
+ UINT32 done_int_mask : 8 ;
+ UINT32 Reserved_124 : 8 ;
+ UINT32 abort_int_mask : 8 ;
+ UINT32 dma_rd_int_mask : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagPortlogic78
+{
+
+ struct
+ {
+ UINT32 done_int_clr : 8 ;
+ UINT32 Reserved_126 : 8 ;
+ UINT32 abort_int_clr : 8 ;
+ UINT32 dma_rd_int_clr : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagPortlogic79
+{
+
+ struct
+ {
+ UINT32 app_wr_err_det : 8 ;
+ UINT32 Reserved_127 : 8 ;
+ UINT32 link_list_fetch_err_det : 8 ;
+ UINT32 dma_rd_err_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagPortlogic80
+{
+
+ struct
+ {
+ UINT32 unspt_request : 8 ;
+ UINT32 completer_abort : 8 ;
+ UINT32 cpl_time_out : 8 ;
+ UINT32 data_poison : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagPortlogic81
+{
+
+ struct
+ {
+ UINT32 remote_abort_int_en : 8 ;
+ UINT32 Reserved_129 : 8 ;
+ UINT32 local_abort_int_en : 8 ;
+ UINT32 dma_rd_ll_err_ena : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagPortlogic86
+{
+
+ struct
+ {
+ UINT32 channel_dir : 3 ;
+ UINT32 Reserved_132 : 28 ;
+ UINT32 dma_ch_con_idx : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagPortlogic87
+{
+
+ struct
+ {
+ UINT32 cycle_bit : 1 ;
+ UINT32 toggle_cycle_bit : 1 ;
+ UINT32 load_link_pointer : 1 ;
+ UINT32 local_int_en : 1 ;
+ UINT32 remote_int_en : 1 ;
+ UINT32 channel_status : 2 ;
+ UINT32 Reserved_136 : 1 ;
+ UINT32 consumer_cycle_state : 1 ;
+ UINT32 linked_list_en : 1 ;
+ UINT32 Reserved_135 : 2 ;
+ UINT32 func_num_dma : 5 ;
+ UINT32 Reserved_134 : 7 ;
+ UINT32 no_snoop : 1 ;
+ UINT32 ro : 1 ;
+ UINT32 td : 1 ;
+ UINT32 tc : 3 ;
+ UINT32 dma_ch_ctrl : 2 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagPortlogic93
+{
+
+ struct
+ {
+ UINT32 Reserved_138 : 2 ;
+ UINT32 dma_ll_ptr_low : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} PCIE_EP_PORTLOGIC93_U;
+
+
+#define PCIE_SUBCTRL_BASE (0x0)
+
+
+
+
+
+#define PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x300)
+#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(port_id) \
+ (PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG + (port_id << 3))
+#define PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x304)
+#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(port_id) \
+ (PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG + (port_id << 3))
+#define PCIE_SUBCTRL_SC_PCIE1_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x308)
+#define PCIE_SUBCTRL_SC_PCIE1_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x30C)
+#define PCIE_SUBCTRL_SC_PCIE2_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x310)
+#define PCIE_SUBCTRL_SC_PCIE2_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x314)
+#define PCIE_SUBCTRL_SC_SAS_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x318)
+#define PCIE_SUBCTRL_SC_SAS_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x31C)
+#define PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x320)
+#define PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x324)
+#define PCIE_SUBCTRL_SC_ITS_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x328)
+#define PCIE_SUBCTRL_SC_ITS_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x32C)
+#define PCIE_SUBCTRL_SC_SLLC_CLK_EN_REG (PCIE_SUBCTRL_BASE + 0x360)
+#define PCIE_SUBCTRL_SC_SLLC_CLK_DIS_REG (PCIE_SUBCTRL_BASE + 0x364)
+#define PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA00)
+#define PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA04)
+#define PCIE_SUBCTRL_SC_PCIE1_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA08)
+#define PCIE_SUBCTRL_SC_PCIE1_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA0C)
+#define PCIE_SUBCTRL_SC_PCIE2_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA10)
+#define PCIE_SUBCTRL_SC_PCIE2_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA14)
+#define PCIE_SUBCTRL_SC_SAS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA18)
+#define PCIE_SUBCTRL_SC_SAS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA1C)
+#define PCIE_SUBCTRL_SC_MCTP0_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA20)
+#define PCIE_SUBCTRL_SC_MCTP0_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA24)
+#define PCIE_SUBCTRL_SC_MCTP1_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA28)
+#define PCIE_SUBCTRL_SC_MCTP1_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA2C)
+#define PCIE_SUBCTRL_SC_MCTP2_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA30)
+#define PCIE_SUBCTRL_SC_MCTP2_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA34)
+#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA58)
+#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA5C)
+#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA60)
+#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA64)
+#define PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA68)
+#define PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA6C)
+#define PCIE_SUBCTRL_SC_MCTP3_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA70)
+#define PCIE_SUBCTRL_SC_MCTP3_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA74)
+#define PCIE_SUBCTRL_SC_ITS_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xA80)
+#define PCIE_SUBCTRL_SC_ITS_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xA84)
+#define PCIE_SUBCTRL_SC_SLLC_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAA0)
+#define PCIE_SUBCTRL_SC_SLLC_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xAA4)
+#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAC0)
+#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG (PCIE_SUBCTRL_BASE + 0xAC4)
+#define PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG (PCIE_SUBCTRL_BASE + 0xAC8)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (PCIE_SUBCTRL_BASE + 0x1000)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY0_REG (PCIE_SUBCTRL_BASE + 0x1004)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY1_REG (PCIE_SUBCTRL_BASE + 0x1008)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY2_REG (PCIE_SUBCTRL_BASE + 0x100C)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (PCIE_SUBCTRL_BASE + 0x1010)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (PCIE_SUBCTRL_BASE + 0x1014)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_BASE + 0x1018)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_BASE + 0x101C)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_BASE + 0x1020)
+#define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_BASE + 0x1030)
+#define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_BASE + 0x1100)
+#define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_BASE + 0x1104)
+#define PCIE_SUBCTRL_SC_DISPATCH_INTSTAT_REG (PCIE_SUBCTRL_BASE + 0x1108)
+#define PCIE_SUBCTRL_SC_DISPATCH_INTCLR_REG (PCIE_SUBCTRL_BASE + 0x110C)
+#define PCIE_SUBCTRL_SC_DISPATCH_ERRSTAT_REG (PCIE_SUBCTRL_BASE + 0x1110)
+#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (PCIE_SUBCTRL_BASE + 0x1200)
+#define PCIE_SUBCTRL_SC_FTE_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2200)
+#define PCIE_SUBCTRL_SC_HILINK0_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2300)
+#define PCIE_SUBCTRL_SC_HILINK1_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2304)
+#define PCIE_SUBCTRL_SC_HILINK2_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2308)
+#define PCIE_SUBCTRL_SC_HILINK5_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2314)
+#define PCIE_SUBCTRL_SC_HILINK1_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2324)
+#define PCIE_SUBCTRL_SC_HILINK2_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2328)
+#define PCIE_SUBCTRL_SC_HILINK5_AHB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2334)
+#define PCIE_SUBCTRL_SC_HILINK5_LRSTB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2340)
+#define PCIE_SUBCTRL_SC_HILINK6_LRSTB_MUX_CTRL_REG (PCIE_SUBCTRL_BASE + 0x2344)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2400)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2404)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2408)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x240C)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2410)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2414)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2418)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x241C)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2420)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2424)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2500)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2504)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2508)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x250C)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2510)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2514)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2518)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x251C)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2520)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2524)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2600)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2604)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2608)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x260C)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2610)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2614)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2618)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x261C)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2620)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2624)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_SS_REFCLK_REG (PCIE_SUBCTRL_BASE + 0x2700)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2704)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LIFECLK2DIG_SEL_REG (PCIE_SUBCTRL_BASE + 0x2708)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SELEXT_REG (PCIE_SUBCTRL_BASE + 0x270C)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SEL_REG (PCIE_SUBCTRL_BASE + 0x2710)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CTRL_BUS_MODE_REG (PCIE_SUBCTRL_BASE + 0x2714)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_MACROPWRDB_REG (PCIE_SUBCTRL_BASE + 0x2718)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_GRSTB_REG (PCIE_SUBCTRL_BASE + 0x271C)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_BIT_SLIP_REG (PCIE_SUBCTRL_BASE + 0x2720)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LRSTB_REG (PCIE_SUBCTRL_BASE + 0x2724)
+#define PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2800)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2880)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2890)
+#define PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2900)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2980)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2990)
+#define PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2A00)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_CFG_REG (PCIE_SUBCTRL_BASE + 0x2A80)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_CFG_REG (PCIE_SUBCTRL_BASE + 0x2A90)
+#define PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG (PCIE_SUBCTRL_BASE + 0x2B00)
+#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL0_REG (PCIE_SUBCTRL_BASE + 0x3000)
+#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL1_REG (PCIE_SUBCTRL_BASE + 0x3004)
+#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL2_REG (PCIE_SUBCTRL_BASE + 0x3008)
+#define PCIE_SUBCTRL_SC_SLLC0_MEM_CTRL_REG (PCIE_SUBCTRL_BASE + 0x3010)
+#define PCIE_SUBCTRL_SC_SAS_MEM_CTRL_REG (PCIE_SUBCTRL_BASE + 0x3030)
+#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL0_REG (PCIE_SUBCTRL_BASE + 0x3040)
+#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL1_REG (PCIE_SUBCTRL_BASE + 0x3044)
+#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL2_REG (PCIE_SUBCTRL_BASE + 0x3048)
+#define PCIE_SUBCTRL_SC_SKEW_COMMON_0_REG (PCIE_SUBCTRL_BASE + 0x3400)
+#define PCIE_SUBCTRL_SC_SKEW_COMMON_1_REG (PCIE_SUBCTRL_BASE + 0x3404)
+#define PCIE_SUBCTRL_SC_SKEW_COMMON_2_REG (PCIE_SUBCTRL_BASE + 0x3408)
+#define PCIE_SUBCTRL_SC_SKEW_A_0_REG (PCIE_SUBCTRL_BASE + 0x3500)
+#define PCIE_SUBCTRL_SC_SKEW_A_1_REG (PCIE_SUBCTRL_BASE + 0x3504)
+#define PCIE_SUBCTRL_SC_SKEW_A_2_REG (PCIE_SUBCTRL_BASE + 0x3508)
+#define PCIE_SUBCTRL_SC_SKEW_A_3_REG (PCIE_SUBCTRL_BASE + 0x350C)
+#define PCIE_SUBCTRL_SC_SKEW_A_4_REG (PCIE_SUBCTRL_BASE + 0x3510)
+#define PCIE_SUBCTRL_SC_SKEW_A_5_REG (PCIE_SUBCTRL_BASE + 0x3514)
+#define PCIE_SUBCTRL_SC_SKEW_A_6_REG (PCIE_SUBCTRL_BASE + 0x3518)
+#define PCIE_SUBCTRL_SC_SKEW_A_7_REG (PCIE_SUBCTRL_BASE + 0x351C)
+#define PCIE_SUBCTRL_SC_SKEW_A_8_REG (PCIE_SUBCTRL_BASE + 0x3520)
+#define PCIE_SUBCTRL_SC_SKEW_B_0_REG (PCIE_SUBCTRL_BASE + 0x3600)
+#define PCIE_SUBCTRL_SC_SKEW_B_1_REG (PCIE_SUBCTRL_BASE + 0x3604)
+#define PCIE_SUBCTRL_SC_SKEW_B_2_REG (PCIE_SUBCTRL_BASE + 0x3608)
+#define PCIE_SUBCTRL_SC_SKEW_B_3_REG (PCIE_SUBCTRL_BASE + 0x360C)
+#define PCIE_SUBCTRL_SC_SKEW_B_4_REG (PCIE_SUBCTRL_BASE + 0x3610)
+#define PCIE_SUBCTRL_SC_SKEW_B_5_REG (PCIE_SUBCTRL_BASE + 0x3614)
+#define PCIE_SUBCTRL_SC_SKEW_B_6_REG (PCIE_SUBCTRL_BASE + 0x3618)
+#define PCIE_SUBCTRL_SC_SKEW_B_7_REG (PCIE_SUBCTRL_BASE + 0x361C)
+#define PCIE_SUBCTRL_SC_SKEW_B_8_REG (PCIE_SUBCTRL_BASE + 0x3620)
+#define PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5300)
+#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(port_id) \
+ (PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG + (port_id << 2))
+#define PCIE_SUBCTRL_SC_PCIE1_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5304)
+#define PCIE_SUBCTRL_SC_PCIE2_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5308)
+#define PCIE_SUBCTRL_SC_SAS_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x530C)
+#define PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5310)
+#define PCIE_SUBCTRL_SC_ITS_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5314)
+#define PCIE_SUBCTRL_SC_SLLC_CLK_ST_REG (PCIE_SUBCTRL_BASE + 0x5330)
+#define PCIE_SUBCTRL_SC_PCIE0_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A00)
+#define PCIE_SUBCTRL_SC_PCIE1_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A04)
+#define PCIE_SUBCTRL_SC_PCIE2_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A08)
+#define PCIE_SUBCTRL_SC_SAS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A0C)
+#define PCIE_SUBCTRL_SC_MCTP0_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A10)
+#define PCIE_SUBCTRL_SC_MCTP1_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A14)
+#define PCIE_SUBCTRL_SC_MCTP2_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A18)
+#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A2C)
+#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A30)
+#define PCIE_SUBCTRL_SC_PCIE3_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A34)
+#define PCIE_SUBCTRL_SC_MCTP3_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A38)
+#define PCIE_SUBCTRL_SC_ITS_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A40)
+#define PCIE_SUBCTRL_SC_SLLC_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A50)
+#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG (PCIE_SUBCTRL_BASE + 0x5A60)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6400)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6404)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6408)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6500)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6504)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6508)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6600)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6604)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6608)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_PLLOUTOFLOCK_REG (PCIE_SUBCTRL_BASE + 0x6700)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_PRBS_ERR_REG (PCIE_SUBCTRL_BASE + 0x6704)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LOS_REG (PCIE_SUBCTRL_BASE + 0x6708)
+#define PCIE_SUBCTRL_SC_PCIE0_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6800)
+#define PCIE_SUBCTRL_SC_PCIE0_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6804)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6808)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x680C)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6810)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6814)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6818)
+#define PCIE_LTSSM_STATE_MASK (0x3f)
+#define PCIE_LTSSM_LINKUP_STATE (0x11)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6880)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6884)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6890)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6894)
+#define PCIE_SUBCTRL_SC_PCIE0_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x68A0)
+#define PCIE_SUBCTRL_SC_PCIE0_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x68C0)
+#define PCIE_SUBCTRL_SC_PCIE1_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6900)
+#define PCIE_SUBCTRL_SC_PCIE1_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6904)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6908)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x690C)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6910)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6914)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6918)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6980)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6984)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6990)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6994)
+#define PCIE_SUBCTRL_SC_PCIE1_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x69A0)
+#define PCIE_SUBCTRL_SC_PCIE1_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x69C0)
+#define PCIE_SUBCTRL_SC_PCIE2_RXEQINPRO_STAT_REG (PCIE_SUBCTRL_BASE + 0x6A00)
+#define PCIE_SUBCTRL_SC_PCIE2_LINKINT_RCVRY_STAT_REG (PCIE_SUBCTRL_BASE + 0x6A04)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6A08)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x6A0C)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6A10)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6A14)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6A18)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6A80)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6A84)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6A90)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS1_REG (PCIE_SUBCTRL_BASE + 0x6A94)
+#define PCIE_SUBCTRL_SC_PCIE2_DSIZE_BRG_ECC_ERR_REG (PCIE_SUBCTRL_BASE + 0x6AA0)
+#define PCIE_SUBCTRL_SC_PCIE2_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x6AC0)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE0_REG (PCIE_SUBCTRL_BASE + 0x6B08)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE1_REG (PCIE_SUBCTRL_BASE + 0x6B0C)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE2_REG (PCIE_SUBCTRL_BASE + 0x6B10)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6B14)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6B18)
+#define PCIE_SUBCTRL_SC_PCIE3_PCIEPHY_CTRL_ERROR_REG (PCIE_SUBCTRL_BASE + 0x6BC0)
+#define PCIE_SUBCTRL_SC_SKEW_ST_0_REG (PCIE_SUBCTRL_BASE + 0x7400)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_0_REG (PCIE_SUBCTRL_BASE + 0x7500)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_1_REG (PCIE_SUBCTRL_BASE + 0x7504)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_2_REG (PCIE_SUBCTRL_BASE + 0x7508)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_3_REG (PCIE_SUBCTRL_BASE + 0x750C)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_0_REG (PCIE_SUBCTRL_BASE + 0x7600)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_1_REG (PCIE_SUBCTRL_BASE + 0x7604)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_2_REG (PCIE_SUBCTRL_BASE + 0x7608)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_3_REG (PCIE_SUBCTRL_BASE + 0x760C)
+#define PCIE_SUBCTRL_SC_ECO_RSV0_REG (PCIE_SUBCTRL_BASE + 0x8000)
+#define PCIE_SUBCTRL_SC_ECO_RSV1_REG (PCIE_SUBCTRL_BASE + 0x8004)
+#define PCIE_SUBCTRL_SC_ECO_RSV2_REG (PCIE_SUBCTRL_BASE + 0x8008)
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie0_enb : 1 ;
+ UINT32 clk_pcie0_pipe_enb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie0_dsb : 1 ;
+ UINT32 clk_pcie0_pipe_dsb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie1_enb : 1 ;
+ UINT32 clk_pcie1_pipe_enb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie1_dsb : 1 ;
+ UINT32 clk_pcie1_pipe_dsb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie2_enb : 1 ;
+ UINT32 clk_pcie2_pipe_enb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie2_dsb : 1 ;
+ UINT32 clk_pcie2_pipe_dsb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sas_enb : 1 ;
+ UINT32 clk_sas_mem_enb : 1 ;
+ UINT32 clk_sas_ahb_enb : 1 ;
+ UINT32 clk_sas_oob_enb : 1 ;
+ UINT32 clk_sas_ch0_rx_enb : 1 ;
+ UINT32 clk_sas_ch1_rx_enb : 1 ;
+ UINT32 clk_sas_ch2_rx_enb : 1 ;
+ UINT32 clk_sas_ch3_rx_enb : 1 ;
+ UINT32 clk_sas_ch4_rx_enb : 1 ;
+ UINT32 clk_sas_ch5_rx_enb : 1 ;
+ UINT32 clk_sas_ch6_rx_enb : 1 ;
+ UINT32 clk_sas_ch7_rx_enb : 1 ;
+ UINT32 clk_sas_ch0_tx_enb : 1 ;
+ UINT32 clk_sas_ch1_tx_enb : 1 ;
+ UINT32 clk_sas_ch2_tx_enb : 1 ;
+ UINT32 clk_sas_ch3_tx_enb : 1 ;
+ UINT32 clk_sas_ch4_tx_enb : 1 ;
+ UINT32 clk_sas_ch5_tx_enb : 1 ;
+ UINT32 clk_sas_ch6_tx_enb : 1 ;
+ UINT32 clk_sas_ch7_tx_enb : 1 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sas_dsb : 1 ;
+ UINT32 clk_sas_mem_dsb : 1 ;
+ UINT32 clk_sas_ahb_dsb : 1 ;
+ UINT32 clk_sas_oob_dsb : 1 ;
+ UINT32 clk_sas_ch0_rx_dsb : 1 ;
+ UINT32 clk_sas_ch1_rx_dsb : 1 ;
+ UINT32 clk_sas_ch2_rx_dsb : 1 ;
+ UINT32 clk_sas_ch3_rx_dsb : 1 ;
+ UINT32 clk_sas_ch4_rx_dsb : 1 ;
+ UINT32 clk_sas_ch5_rx_dsb : 1 ;
+ UINT32 clk_sas_ch6_rx_dsb : 1 ;
+ UINT32 clk_sas_ch7_rx_dsb : 1 ;
+ UINT32 clk_sas_ch0_tx_dsb : 1 ;
+ UINT32 clk_sas_ch1_tx_dsb : 1 ;
+ UINT32 clk_sas_ch2_tx_dsb : 1 ;
+ UINT32 clk_sas_ch3_tx_dsb : 1 ;
+ UINT32 clk_sas_ch4_tx_dsb : 1 ;
+ UINT32 clk_sas_ch5_tx_dsb : 1 ;
+ UINT32 clk_sas_ch6_tx_dsb : 1 ;
+ UINT32 clk_sas_ch7_tx_dsb : 1 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie3_enb : 1 ;
+ UINT32 clk_pcie3_pipe_enb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie3_dsb : 1 ;
+ UINT32 clk_pcie3_pipe_dsb : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_its_enb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_its_dsb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sllc_enb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_clk_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sllc_dsb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_clk_dis;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sas_srst_req : 1 ;
+ UINT32 sas_oob_srst_req : 1 ;
+ UINT32 sas_ahb_srst_req : 1 ;
+ UINT32 sas_ch0_rx_srst_req : 1 ;
+ UINT32 sas_ch1_rx_srst_req : 1 ;
+ UINT32 sas_ch2_rx_srst_req : 1 ;
+ UINT32 sas_ch3_rx_srst_req : 1 ;
+ UINT32 sas_ch4_rx_srst_req : 1 ;
+ UINT32 sas_ch5_rx_srst_req : 1 ;
+ UINT32 sas_ch6_rx_srst_req : 1 ;
+ UINT32 sas_ch7_rx_srst_req : 1 ;
+ UINT32 sas_ch0_tx_srst_req : 1 ;
+ UINT32 sas_ch1_tx_srst_req : 1 ;
+ UINT32 sas_ch2_tx_srst_req : 1 ;
+ UINT32 sas_ch3_tx_srst_req : 1 ;
+ UINT32 sas_ch4_tx_srst_req : 1 ;
+ UINT32 sas_ch5_tx_srst_req : 1 ;
+ UINT32 sas_ch6_tx_srst_req : 1 ;
+ UINT32 sas_ch7_tx_srst_req : 1 ;
+ UINT32 reserved_0 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sas_srst_dreq : 1 ;
+ UINT32 sas_oob_srst_dreq : 1 ;
+ UINT32 sas_ahb_srst_dreq : 1 ;
+ UINT32 sas_ch0_rx_srst_dreq : 1 ;
+ UINT32 sas_ch1_rx_srst_dreq : 1 ;
+ UINT32 sas_ch2_rx_srst_dreq : 1 ;
+ UINT32 sas_ch3_rx_srst_dreq : 1 ;
+ UINT32 sas_ch4_rx_srst_dreq : 1 ;
+ UINT32 sas_ch5_rx_srst_dreq : 1 ;
+ UINT32 sas_ch6_rx_srst_dreq : 1 ;
+ UINT32 sas_ch7_rx_srst_dreq : 1 ;
+ UINT32 sas_ch0_tx_srst_dreq : 1 ;
+ UINT32 sas_ch1_tx_srst_dreq : 1 ;
+ UINT32 sas_ch2_tx_srst_dreq : 1 ;
+ UINT32 sas_ch3_tx_srst_dreq : 1 ;
+ UINT32 sas_ch4_tx_srst_dreq : 1 ;
+ UINT32 sas_ch5_tx_srst_dreq : 1 ;
+ UINT32 sas_ch6_tx_srst_dreq : 1 ;
+ UINT32 sas_ch7_tx_srst_dreq : 1 ;
+ UINT32 reserved_0 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp0_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp0_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp0_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp0_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp1_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp1_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp1_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp1_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp2_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp2_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp2_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp2_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_tsvrx0_srst_req : 1 ;
+ UINT32 sllc_tsvrx1_srst_req : 1 ;
+ UINT32 sllc_tsvrx2_srst_req : 1 ;
+ UINT32 sllc_tsvrx3_srst_req : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_tsvrx_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_tsvrx0_srst_dreq : 1 ;
+ UINT32 sllc_tsvrx1_srst_dreq : 1 ;
+ UINT32 sllc_tsvrx2_srst_dreq : 1 ;
+ UINT32 sllc_tsvrx3_srst_dreq : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_tsvrx_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_hilink_pcs_lane0_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane1_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane2_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane3_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane4_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane5_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane6_srst_req : 1 ;
+ UINT32 pcie0_hilink_pcs_lane7_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane0_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane1_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane2_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane3_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane4_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane5_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane6_srst_req : 1 ;
+ UINT32 pcie1_hilink_pcs_lane7_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane0_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane1_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane2_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane3_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane4_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane5_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane6_srst_req : 1 ;
+ UINT32 pcie2_hilink_pcs_lane7_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane0_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane1_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane2_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane3_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane4_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane5_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane6_srst_req : 1 ;
+ UINT32 pcie3_hilink_pcs_lane7_srst_req : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_hilink_pcs_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_hilink_pcs_lane0_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane1_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane2_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane3_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane4_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane5_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane6_srst_dreq : 1 ;
+ UINT32 pcie0_hilink_pcs_lane7_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane0_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane1_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane2_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane3_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane4_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane5_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane6_srst_dreq : 1 ;
+ UINT32 pcie1_hilink_pcs_lane7_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane0_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane1_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane2_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane3_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane4_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane5_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane6_srst_dreq : 1 ;
+ UINT32 pcie2_hilink_pcs_lane7_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane0_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane1_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane2_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane3_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane4_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane5_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane6_srst_dreq : 1 ;
+ UINT32 pcie3_hilink_pcs_lane7_srst_dreq : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_hilink_pcs_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp3_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp3_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp3_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp3_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 its_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 its_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_srst_req : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_srst_dreq : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_pcs_local_srst_req : 1 ;
+ UINT32 pcie1_pcs_local_srst_req : 1 ;
+ UINT32 pcie2_pcs_local_srst_req : 1 ;
+ UINT32 pcie3_pcs_local_srst_req : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcs_local_reset_req;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_pcs_local_srst_dreq : 1 ;
+ UINT32 pcie1_pcs_local_srst_dreq : 1 ;
+ UINT32 pcie2_pcs_local_srst_dreq : 1 ;
+ UINT32 pcie3_pcs_local_srst_dreq : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcs_local_reset_dreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 dispatch_daw_en : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_disp_daw_en;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array0_did : 3 ;
+ UINT32 daw_array0_size : 5 ;
+ UINT32 daw_array0_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array0_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array1_did : 3 ;
+ UINT32 daw_array1_size : 5 ;
+ UINT32 daw_array1_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array1_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array2_did : 3 ;
+ UINT32 daw_array2_size : 5 ;
+ UINT32 daw_array2_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array2_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array3_did : 3 ;
+ UINT32 daw_array3_size : 5 ;
+ UINT32 daw_array3_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array3_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array3;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array4_did : 3 ;
+ UINT32 daw_array4_size : 5 ;
+ UINT32 daw_array4_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array4_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array5_did : 3 ;
+ UINT32 daw_array5_size : 5 ;
+ UINT32 daw_array5_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array5_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array5;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array6_did : 3 ;
+ UINT32 daw_array6_size : 5 ;
+ UINT32 daw_array6_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array6_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array6;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 daw_array7_did : 3 ;
+ UINT32 daw_array7_size : 5 ;
+ UINT32 daw_array7_sync : 1 ;
+ UINT32 reserved_0 : 4 ;
+ UINT32 daw_array7_addr : 19 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_daw_array7;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 retry_num_limit : 16 ;
+ UINT32 retry_en : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_retry_control;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 intmask : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_intmask;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 rawint : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_rawint;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 intsts : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_intstat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 intclr : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_intclr;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 err_opcode : 5 ;
+ UINT32 err_addr : 17 ;
+ UINT32 reserved_0 : 10 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_dispatch_errstat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sys_remap_vld : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_remap_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mux_sel_fte : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_fte_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink2_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink2_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_ahb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_ahb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink2_ahb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink2_ahb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_ahb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_ahb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_lrstb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_lrstb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_lrstb_mux_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_lrstb_mux_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_ss_refclk0_x2s : 2 ;
+ UINT32 hilink0_ss_refclk0_x2n : 2 ;
+ UINT32 hilink0_ss_refclk0_x2e : 2 ;
+ UINT32 hilink0_ss_refclk0_x2w : 2 ;
+ UINT32 hilink0_ss_refclk1_x2s : 2 ;
+ UINT32 hilink0_ss_refclk1_x2n : 2 ;
+ UINT32 hilink0_ss_refclk1_x2e : 2 ;
+ UINT32 hilink0_ss_refclk1_x2w : 2 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_ss_refclk;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_cs_refclk0_dirsel0 : 2 ;
+ UINT32 hilink0_cs_refclk0_dirsel1 : 2 ;
+ UINT32 hilink0_cs_refclk0_dirsel2 : 2 ;
+ UINT32 hilink0_cs_refclk0_dirsel3 : 2 ;
+ UINT32 hilink0_cs_refclk0_dirsel4 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel0 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel1 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel2 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel3 : 2 ;
+ UINT32 hilink0_cs_refclk1_dirsel4 : 2 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_lifeclk2dig_sel : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_core_clk_selext : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_core_clk_selext;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_core_clk_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_core_clk_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_ctrl_bus_mode : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_macropwrdb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_macropwrdb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_grstb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_grstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_bit_slip : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_bit_slip;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_lrstb : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_lrstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_ss_refclk0_x2s : 2 ;
+ UINT32 hilink1_ss_refclk0_x2n : 2 ;
+ UINT32 hilink1_ss_refclk0_x2e : 2 ;
+ UINT32 hilink1_ss_refclk0_x2w : 2 ;
+ UINT32 hilink1_ss_refclk1_x2s : 2 ;
+ UINT32 hilink1_ss_refclk1_x2n : 2 ;
+ UINT32 hilink1_ss_refclk1_x2e : 2 ;
+ UINT32 hilink1_ss_refclk1_x2w : 2 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_ss_refclk;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_cs_refclk0_dirsel0 : 2 ;
+ UINT32 hilink1_cs_refclk0_dirsel1 : 2 ;
+ UINT32 hilink1_cs_refclk0_dirsel2 : 2 ;
+ UINT32 hilink1_cs_refclk0_dirsel3 : 2 ;
+ UINT32 hilink1_cs_refclk0_dirsel4 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel0 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel1 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel2 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel3 : 2 ;
+ UINT32 hilink1_cs_refclk1_dirsel4 : 2 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_lifeclk2dig_sel : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_core_clk_selext : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_core_clk_selext;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_core_clk_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_core_clk_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_ctrl_bus_mode : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_macropwrdb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_macropwrdb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_grstb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_grstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_bit_slip : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_bit_slip;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_lrstb : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_lrstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_ss_refclk0_x2s : 2 ;
+ UINT32 hilink5_ss_refclk0_x2n : 2 ;
+ UINT32 hilink5_ss_refclk0_x2e : 2 ;
+ UINT32 hilink5_ss_refclk0_x2w : 2 ;
+ UINT32 hilink5_ss_refclk1_x2s : 2 ;
+ UINT32 hilink5_ss_refclk1_x2n : 2 ;
+ UINT32 hilink5_ss_refclk1_x2e : 2 ;
+ UINT32 hilink5_ss_refclk1_x2w : 2 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_ss_refclk;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_cs_refclk0_dirsel0 : 2 ;
+ UINT32 hilink5_cs_refclk0_dirsel1 : 2 ;
+ UINT32 hilink5_cs_refclk0_dirsel2 : 2 ;
+ UINT32 hilink5_cs_refclk0_dirsel3 : 2 ;
+ UINT32 hilink5_cs_refclk0_dirsel4 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel0 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel1 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel2 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel3 : 2 ;
+ UINT32 hilink5_cs_refclk1_dirsel4 : 2 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_lifeclk2dig_sel : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_core_clk_selext : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_core_clk_selext;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_core_clk_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_core_clk_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_ctrl_bus_mode : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_macropwrdb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_macropwrdb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_grstb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_grstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_bit_slip : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_bit_slip;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_lrstb : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_lrstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_ss_refclk0_x2s : 2 ;
+ UINT32 hilink6_ss_refclk0_x2n : 2 ;
+ UINT32 hilink6_ss_refclk0_x2e : 2 ;
+ UINT32 hilink6_ss_refclk0_x2w : 2 ;
+ UINT32 hilink6_ss_refclk1_x2s : 2 ;
+ UINT32 hilink6_ss_refclk1_x2n : 2 ;
+ UINT32 hilink6_ss_refclk1_x2e : 2 ;
+ UINT32 hilink6_ss_refclk1_x2w : 2 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_ss_refclk;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_cs_refclk0_dirsel0 : 2 ;
+ UINT32 hilink6_cs_refclk0_dirsel1 : 2 ;
+ UINT32 hilink6_cs_refclk0_dirsel2 : 2 ;
+ UINT32 hilink6_cs_refclk0_dirsel3 : 2 ;
+ UINT32 hilink6_cs_refclk0_dirsel4 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel0 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel1 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel2 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel3 : 2 ;
+ UINT32 hilink6_cs_refclk1_dirsel4 : 2 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_lifeclk2dig_sel : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_core_clk_selext : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_core_clk_selext;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_core_clk_sel : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_core_clk_sel;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_ctrl_bus_mode : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_macropwrdb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_macropwrdb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_grstb : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_grstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_bit_slip : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_bit_slip;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_lrstb : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_lrstb;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_phy_clk_req_n : 1 ;
+ UINT32 pcie0_apb_cfg_sel : 2 ;
+ UINT32 reserved_0 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_clkreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_cfg_max_wr_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie0_wr_rate_limit : 4 ;
+ UINT32 pcie0_ctrl_lat_stat_wr_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie0_en_device_wr_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_wr_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_cfg_max_rd_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie0_rd_rate_limit : 4 ;
+ UINT32 pcie0_ctrl_lat_stat_rd_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie0_en_device_rd_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_rd_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1hilink_phy_clk_req_n : 1 ;
+ UINT32 pcie1vsemi_phy_clk_req_n : 1 ;
+ UINT32 pcie1_apb_cfg_sel : 2 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_clkreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_cfg_max_wr_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie1_wr_rate_limit : 4 ;
+ UINT32 pcie1_ctrl_lat_stat_wr_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie1_en_device_wr_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_wr_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_cfg_max_rd_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie1_rd_rate_limit : 4 ;
+ UINT32 pcie1_ctrl_lat_stat_rd_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie1_en_device_rd_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_rd_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2hilink_phy_clk_req_n : 1 ;
+ UINT32 pcie2vsemi_phy_clk_req_n : 1 ;
+ UINT32 pcie2_apb_cfg_sel : 2 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_clkreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_cfg_max_wr_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie2_wr_rate_limit : 4 ;
+ UINT32 pcie2_ctrl_lat_stat_wr_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie2_en_device_wr_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_wr_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_cfg_max_rd_trans : 6 ;
+ UINT32 reserved_0 : 2 ;
+ UINT32 pcie2_rd_rate_limit : 4 ;
+ UINT32 pcie2_ctrl_lat_stat_rd_en : 1 ;
+ UINT32 reserved_1 : 3 ;
+ UINT32 pcie2_en_device_rd_ooo : 1 ;
+ UINT32 reserved_2 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_rd_cfg;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_phy_clk_req_n : 1 ;
+ UINT32 pcie3_apb_cfg_sel : 2 ;
+ UINT32 reserved_0 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_clkreq;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rfs_smmu : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_smmu_mem_ctrl0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 tsel_hc_smmu : 3 ;
+ UINT32 reserved_0 : 29 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_smmu_mem_ctrl1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 test_hc_smmu : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_smmu_mem_ctrl2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rft_sllc0 : 10 ;
+ UINT32 reserved_0 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc0_mem_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rfs_sas : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_mem_ctrl;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rft_pcie : 10 ;
+ UINT32 reserved_0 : 22 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_mem_ctrl0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rashsd_pcie : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_mem_ctrl1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 ctrl_rfs_pcie : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_mem_ctrl2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_en : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_common_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_addr_offset : 5 ;
+ UINT32 reserved_0 : 27 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_common_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_config_in : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_common_2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_bypass_a : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_config_in_a : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_out_delay_sel_a : 2 ;
+ UINT32 skew_in_delay_sel_a : 2 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_sel_a_1 : 1 ;
+ UINT32 skew_sel_a_0 : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_3;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_update_en_a : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_varible_set_a : 16 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_5;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_dcell_set_a_h : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_7;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_sel_osc_a : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_a_8;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_bypass_b : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_config_in_b : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_out_delay_sel_b : 2 ;
+ UINT32 skew_in_delay_sel_b : 2 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_2;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_sel_b_1 : 1 ;
+ UINT32 skew_sel_b_0 : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_3;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_update_en_b : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_varible_set_b : 16 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_5;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_dcell_set_b_h : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_7;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_sel_osc_b : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_b_8;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie0_st : 1 ;
+ UINT32 clk_pcie0_pipe_st : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie1_st : 1 ;
+ UINT32 clk_pcie1_pipe_st : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie2_st : 1 ;
+ UINT32 clk_pcie2_pipe_st : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sas_st : 1 ;
+ UINT32 clk_sas_mem_st : 1 ;
+ UINT32 clk_sas_ahb_st : 1 ;
+ UINT32 clk_sas_oob_st : 1 ;
+ UINT32 clk_sas_ch0_rx_st : 1 ;
+ UINT32 clk_sas_ch1_rx_st : 1 ;
+ UINT32 clk_sas_ch2_rx_st : 1 ;
+ UINT32 clk_sas_ch3_rx_st : 1 ;
+ UINT32 clk_sas_ch4_rx_st : 1 ;
+ UINT32 clk_sas_ch5_rx_st : 1 ;
+ UINT32 clk_sas_ch6_rx_st : 1 ;
+ UINT32 clk_sas_ch7_rx_st : 1 ;
+ UINT32 clk_sas_ch0_tx_st : 1 ;
+ UINT32 clk_sas_ch1_tx_st : 1 ;
+ UINT32 clk_sas_ch2_tx_st : 1 ;
+ UINT32 clk_sas_ch3_tx_st : 1 ;
+ UINT32 clk_sas_ch4_tx_st : 1 ;
+ UINT32 clk_sas_ch5_tx_st : 1 ;
+ UINT32 clk_sas_ch6_tx_st : 1 ;
+ UINT32 clk_sas_ch7_tx_st : 1 ;
+ UINT32 reserved_0 : 12 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_pcie3_st : 1 ;
+ UINT32 clk_pcie3_pipe_st : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_its_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 clk_sllc_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_clk_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sas_srst_st : 1 ;
+ UINT32 sas_oob_srst_st : 1 ;
+ UINT32 sas_ahb_srst_st : 1 ;
+ UINT32 sas_ch0_rx_srst_st : 1 ;
+ UINT32 sas_ch1_rx_srst_st : 1 ;
+ UINT32 sas_ch2_rx_srst_st : 1 ;
+ UINT32 sas_ch3_rx_srst_st : 1 ;
+ UINT32 sas_ch4_rx_srst_st : 1 ;
+ UINT32 sas_ch5_rx_srst_st : 1 ;
+ UINT32 sas_ch6_rx_srst_st : 1 ;
+ UINT32 sas_ch7_rx_srst_st : 1 ;
+ UINT32 sas_ch0_tx_srst_st : 1 ;
+ UINT32 sas_ch1_tx_srst_st : 1 ;
+ UINT32 sas_ch2_tx_srst_st : 1 ;
+ UINT32 sas_ch3_tx_srst_st : 1 ;
+ UINT32 sas_ch4_tx_srst_st : 1 ;
+ UINT32 sas_ch5_tx_srst_st : 1 ;
+ UINT32 sas_ch6_tx_srst_st : 1 ;
+ UINT32 sas_ch7_tx_srst_st : 1 ;
+ UINT32 reserved_0 : 13 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sas_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp0_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp0_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp1_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp1_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp2_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp2_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_tsvrx0_srst_st : 1 ;
+ UINT32 sllc_tsvrx1_srst_st : 1 ;
+ UINT32 sllc_tsvrx2_srst_st : 1 ;
+ UINT32 sllc_tsvrx3_srst_st : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_tsvrx_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_hilink_pcs_lane0_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane1_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane2_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane3_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane4_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane5_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane6_srst_st : 1 ;
+ UINT32 pcie0_hilink_pcs_lane7_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane0_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane1_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane2_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane3_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane4_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane5_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane6_srst_st : 1 ;
+ UINT32 pcie1_hilink_pcs_lane7_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane0_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane1_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane2_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane3_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane4_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane5_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane6_srst_st : 1 ;
+ UINT32 pcie2_hilink_pcs_lane7_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane0_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane1_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane2_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane3_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane4_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane5_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane6_srst_st : 1 ;
+ UINT32 pcie3_hilink_pcs_lane7_srst_st : 1 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie_hilink_pcs_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 mctp3_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_mctp3_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 its_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_its_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 sllc_srst_st : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_sllc_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_pcs_local_srst_st : 1 ;
+ UINT32 pcie1_pcs_local_srst_st : 1 ;
+ UINT32 pcie2_pcs_local_srst_st : 1 ;
+ UINT32 pcie3_pcs_local_srst_st : 1 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcs_local_reset_st;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_plloutoflock : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_plloutoflock;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_prbs_err : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_prbs_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink0_los : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink0_macro_los;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_plloutoflock : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_plloutoflock;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_prbs_err : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_prbs_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink1_los : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink1_macro_los;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_plloutoflock : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_plloutoflock;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_prbs_err : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_prbs_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink5_los : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink5_macro_los;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_plloutoflock : 2 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_plloutoflock;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_prbs_err : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_prbs_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 hilink6_los : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_hilink6_macro_los;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_mac_phy_rxeqinprogress : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_rxeqinpro_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_cfg_link_eq_req_int : 1 ;
+ UINT32 pcie0_xmlh_ltssm_state_rcvry_eq : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_linkint_rcvry_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie0_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie0_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie0_cfg_mem_space_en : 1 ;
+ UINT32 pcie0_cfg_rcb : 1 ;
+ UINT32 pcie0_rdlh_link_up : 1 ;
+ UINT32 pcie0_pm_curnt_state : 3 ;
+ UINT32 pcie0_cfg_aer_rc_err_int : 1 ;
+ UINT32 pcie0_cfg_aer_int_msg_num : 5 ;
+ UINT32 pcie0_xmlh_link_up : 1 ;
+ UINT32 pcie0_wake : 1 ;
+ UINT32 pcie0_cfg_eml_control : 1 ;
+ UINT32 pcie0_hp_pme : 1 ;
+ UINT32 pcie0_hp_int : 1 ;
+ UINT32 pcie0_hp_msi : 1 ;
+ UINT32 pcie0_pm_status : 1 ;
+ UINT32 pcie0_ref_clk_req_n : 1 ;
+ UINT32 pcie0_p2_exit_reg : 1 ;
+ UINT32 pcie0_radm_msg_req_id_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+}U_SC_PCIE0_SYS_STATE0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_axi_parity_errs_reg : 4 ;
+ UINT32 pcie0_app_parity_errs_reg : 3 ;
+ UINT32 pcie0_pm_linkst_in_l1 : 1 ;
+ UINT32 pcie0_pm_linkst_in_l2 : 1 ;
+ UINT32 pcie0_pm_linkst_l2_exit : 1 ;
+ UINT32 pcie0_mac_phy_power_down : 2 ;
+ UINT32 pcie0_radm_correctabl_err_reg : 1 ;
+ UINT32 pcie0_radm_nonfatal_err_reg : 1 ;
+ UINT32 pcie0_radm_fatal_err_reg : 1 ;
+ UINT32 pcie0_radm_pm_to_pme_reg : 1 ;
+ UINT32 pcie0_radm_pm_to_ack_reg : 1 ;
+ UINT32 pcie0_radm_cpl_timeout_reg : 1 ;
+ UINT32 pcie0_radm_msg_unlock_reg : 1 ;
+ UINT32 pcie0_cfg_pme_msi_reg : 1 ;
+ UINT32 pcie0_bridge_flush_not_reg : 1 ;
+ UINT32 pcie0_link_req_rst_not_reg : 1 ;
+ UINT32 pcie0_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie0_cfg_sys_err_rc : 1 ;
+ UINT32 pcie0_radm_msg_req_id_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} U_SC_PCIE0_SYS_STATE1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_ltssm_state : 6 ;
+ UINT32 pcie0_mac_phy_rate : 2 ;
+ UINT32 pcie0_slv_err_int : 1 ;
+ UINT32 pcie0_retry_sram_addr : 10 ;
+ UINT32 pcie0_mstr_rresp_int : 1 ;
+ UINT32 pcie0_mstr_bresp_int : 1 ;
+ UINT32 pcie0_radm_inta_reg : 1 ;
+ UINT32 pcie0_radm_intb_reg : 1 ;
+ UINT32 pcie0_radm_intc_reg : 1 ;
+ UINT32 pcie0_radm_intd_reg : 1 ;
+ UINT32 pcie0_cfg_pme_int_reg : 1 ;
+ UINT32 pcie0_radm_vendor_msg_reg : 1 ;
+ UINT32 pcie0_bridge_flush_not : 1 ;
+ UINT32 pcie0_link_req_rst_not : 1 ;
+ UINT32 reserved_0 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} U_SC_PCIE0_SYS_STATE4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_curr_wr_latency : 16 ;
+ UINT32 pcie0_curr_wr_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_wr_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_curr_rd_latency : 16 ;
+ UINT32 pcie0_curr_rd_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_rd_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_rob_ecc_err_detect : 1 ;
+ UINT32 pcie0_rob_ecc_err_multpl : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_dsize_brg_ecc_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie0_pciephy_ctrl_error : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie0_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_mac_phy_rxeqinprogress : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_rxeqinpro_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_cfg_link_eq_req_int : 1 ;
+ UINT32 pcie1_xmlh_ltssm_state_rcvry_eq : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_linkint_rcvry_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie1_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie1_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie1_cfg_mem_space_en : 1 ;
+ UINT32 pcie1_cfg_rcb : 1 ;
+ UINT32 pcie1_rdlh_link_up : 1 ;
+ UINT32 pcie1_pm_curnt_state : 3 ;
+ UINT32 pcie1_cfg_aer_rc_err_int : 1 ;
+ UINT32 pcie1_cfg_aer_int_msg_num : 5 ;
+ UINT32 pcie1_xmlh_link_up : 1 ;
+ UINT32 pcie1_wake : 1 ;
+ UINT32 pcie1_cfg_eml_control : 1 ;
+ UINT32 pcie1_hp_pme : 1 ;
+ UINT32 pcie1_hp_int : 1 ;
+ UINT32 pcie1_hp_msi : 1 ;
+ UINT32 pcie1_pm_status : 1 ;
+ UINT32 pcie1_ref_clk_req_n : 1 ;
+ UINT32 pcie1_p2_exit_reg : 1 ;
+ UINT32 pcie1_radm_msg_req_id_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_sys_state0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_axi_parity_errs_reg : 4 ;
+ UINT32 pcie1_app_parity_errs_reg : 3 ;
+ UINT32 pcie1_pm_linkst_in_l1 : 1 ;
+ UINT32 pcie1_pm_linkst_in_l2 : 1 ;
+ UINT32 pcie1_pm_linkst_l2_exit : 1 ;
+ UINT32 pcie1_mac_phy_power_down : 2 ;
+ UINT32 pcie1_radm_correctabl_err_reg : 1 ;
+ UINT32 pcie1_radm_nonfatal_err_reg : 1 ;
+ UINT32 pcie1_radm_fatal_err_reg : 1 ;
+ UINT32 pcie1_radm_pm_to_pme_reg : 1 ;
+ UINT32 pcie1_radm_pm_to_ack_reg : 1 ;
+ UINT32 pcie1_radm_cpl_timeout_reg : 1 ;
+ UINT32 pcie1_radm_msg_unlock_reg : 1 ;
+ UINT32 pcie1_cfg_pme_msi_reg : 1 ;
+ UINT32 pcie1_bridge_flush_not_reg : 1 ;
+ UINT32 pcie1_link_req_rst_not_reg : 1 ;
+ UINT32 pcie1_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie1_cfg_sys_err_rc : 1 ;
+ UINT32 pcie1_radm_msg_req_id_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_sys_state1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_ltssm_state : 6 ;
+ UINT32 pcie1_mac_phy_rate : 2 ;
+ UINT32 pcie1_slv_err_int : 1 ;
+ UINT32 pcie1_retry_sram_addr : 10 ;
+ UINT32 pcie1_mstr_rresp_int : 1 ;
+ UINT32 pcie1_mstr_bresp_int : 1 ;
+ UINT32 pcie1_radm_inta_reg : 1 ;
+ UINT32 pcie1_radm_intb_reg : 1 ;
+ UINT32 pcie1_radm_intc_reg : 1 ;
+ UINT32 pcie1_radm_intd_reg : 1 ;
+ UINT32 pcie1_cfg_pme_int_reg : 1 ;
+ UINT32 pcie1_radm_vendor_msg_reg : 1 ;
+ UINT32 pcie1_bridge_flush_not : 1 ;
+ UINT32 pcie1_link_req_rst_not : 1 ;
+ UINT32 reserved_0 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_sys_state4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_curr_wr_latency : 16 ;
+ UINT32 pcie1_curr_wr_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_wr_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_curr_rd_latency : 16 ;
+ UINT32 pcie1_curr_rd_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_rd_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_rob_ecc_err_detect : 1 ;
+ UINT32 pcie1_rob_ecc_err_multpl : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_dsize_brg_ecc_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie1_pciephy_ctrl_error : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie1_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_mac_phy_rxeqinprogress : 8 ;
+ UINT32 reserved_0 : 24 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_rxeqinpro_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_cfg_link_eq_req_int : 1 ;
+ UINT32 pcie2_xmlh_ltssm_state_rcvry_eq : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_linkint_rcvry_stat;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie2_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie2_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie2_cfg_mem_space_en : 1 ;
+ UINT32 pcie2_cfg_rcb : 1 ;
+ UINT32 pcie2_rdlh_link_up : 1 ;
+ UINT32 pcie2_pm_curnt_state : 3 ;
+ UINT32 pcie2_cfg_aer_rc_err_int : 1 ;
+ UINT32 pcie2_cfg_aer_int_msg_num : 5 ;
+ UINT32 pcie2_xmlh_link_up : 1 ;
+ UINT32 pcie2_wake : 1 ;
+ UINT32 pcie2_cfg_eml_control : 1 ;
+ UINT32 pcie2_hp_pme : 1 ;
+ UINT32 pcie2_hp_int : 1 ;
+ UINT32 pcie2_hp_msi : 1 ;
+ UINT32 pcie2_pm_status : 1 ;
+ UINT32 pcie2_ref_clk_req_n : 1 ;
+ UINT32 pcie2_p2_exit_reg : 1 ;
+ UINT32 pcie2_radm_msg_req_id_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_sys_state0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_axi_parity_errs_reg : 4 ;
+ UINT32 pcie2_app_parity_errs_reg : 3 ;
+ UINT32 pcie2_pm_linkst_in_l1 : 1 ;
+ UINT32 pcie2_pm_linkst_in_l2 : 1 ;
+ UINT32 pcie2_pm_linkst_l2_exit : 1 ;
+ UINT32 pcie2_mac_phy_power_down : 2 ;
+ UINT32 pcie2_radm_correctabl_err_reg : 1 ;
+ UINT32 pcie2_radm_nonfatal_err_reg : 1 ;
+ UINT32 pcie2_radm_fatal_err_reg : 1 ;
+ UINT32 pcie2_radm_pm_to_pme_reg : 1 ;
+ UINT32 pcie2_radm_pm_to_ack_reg : 1 ;
+ UINT32 pcie2_radm_cpl_timeout_reg : 1 ;
+ UINT32 pcie2_radm_msg_unlock_reg : 1 ;
+ UINT32 pcie2_cfg_pme_msi_reg : 1 ;
+ UINT32 pcie2_bridge_flush_not_reg : 1 ;
+ UINT32 pcie2_link_req_rst_not_reg : 1 ;
+ UINT32 pcie2_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie2_cfg_sys_err_rc : 1 ;
+ UINT32 pcie2_radm_msg_req_id_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_sys_state1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_ltssm_state : 6 ;
+ UINT32 pcie2_mac_phy_rate : 2 ;
+ UINT32 pcie2_slv_err_int : 1 ;
+ UINT32 pcie2_retry_sram_addr : 10 ;
+ UINT32 pcie2_mstr_rresp_int : 1 ;
+ UINT32 pcie2_mstr_bresp_int : 1 ;
+ UINT32 pcie2_radm_inta_reg : 1 ;
+ UINT32 pcie2_radm_intb_reg : 1 ;
+ UINT32 pcie2_radm_intc_reg : 1 ;
+ UINT32 pcie2_radm_intd_reg : 1 ;
+ UINT32 pcie2_cfg_pme_int_reg : 1 ;
+ UINT32 pcie2_radm_vendor_msg_reg : 1 ;
+ UINT32 pcie2_bridge_flush_not : 1 ;
+ UINT32 pcie2_link_req_rst_not : 1 ;
+ UINT32 reserved_0 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_sys_state4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_curr_wr_latency : 16 ;
+ UINT32 pcie2_curr_wr_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_wr_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_curr_rd_latency : 16 ;
+ UINT32 pcie2_curr_rd_port_sts : 1 ;
+ UINT32 reserved_0 : 15 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_rd_sts1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_rob_ecc_err_detect : 1 ;
+ UINT32 pcie2_rob_ecc_err_multpl : 1 ;
+ UINT32 reserved_0 : 30 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_dsize_brg_ecc_err;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie2_pciephy_ctrl_error : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie2_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_gm_cmposer_lookup_err : 1 ;
+ UINT32 pcie3_radmx_cmposer_lookup_err : 1 ;
+ UINT32 pcie3_pm_xtlh_block_tlp : 1 ;
+ UINT32 pcie3_cfg_mem_space_en : 1 ;
+ UINT32 pcie3_cfg_rcb : 1 ;
+ UINT32 pcie3_rdlh_link_up : 1 ;
+ UINT32 pcie3_pm_curnt_state : 3 ;
+ UINT32 pcie3_cfg_aer_rc_err_int : 1 ;
+ UINT32 pcie3_cfg_aer_int_msg_num : 5 ;
+ UINT32 pcie3_xmlh_link_up : 1 ;
+ UINT32 pcie3_wake : 1 ;
+ UINT32 pcie3_cfg_eml_control : 1 ;
+ UINT32 pcie3_hp_pme : 1 ;
+ UINT32 pcie3_hp_int : 1 ;
+ UINT32 pcie3_hp_msi : 1 ;
+ UINT32 pcie3_pm_status : 1 ;
+ UINT32 pcie3_ref_clk_req_n : 1 ;
+ UINT32 pcie3_p2_exit_reg : 1 ;
+ UINT32 pcie3_radm_msg_req_id_low : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_sys_state0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_axi_parity_errs_reg : 4 ;
+ UINT32 pcie3_app_parity_errs_reg : 3 ;
+ UINT32 pcie3_pm_linkst_in_l1 : 1 ;
+ UINT32 pcie3_pm_linkst_in_l2 : 1 ;
+ UINT32 pcie3_pm_linkst_l2_exit : 1 ;
+ UINT32 pcie3_mac_phy_power_down : 2 ;
+ UINT32 pcie3_radm_correctabl_err_reg : 1 ;
+ UINT32 pcie3_radm_nonfatal_err_reg : 1 ;
+ UINT32 pcie3_radm_fatal_err_reg : 1 ;
+ UINT32 pcie3_radm_pm_to_pme_reg : 1 ;
+ UINT32 pcie3_radm_pm_to_ack_reg : 1 ;
+ UINT32 pcie3_radm_cpl_timeout_reg : 1 ;
+ UINT32 pcie3_radm_msg_unlock_reg : 1 ;
+ UINT32 pcie3_cfg_pme_msi_reg : 1 ;
+ UINT32 pcie3_bridge_flush_not_reg : 1 ;
+ UINT32 pcie3_link_req_rst_not_reg : 1 ;
+ UINT32 pcie3_cfg_aer_rc_err_msi : 1 ;
+ UINT32 pcie3_cfg_sys_err_rc : 1 ;
+ UINT32 pcie3_radm_msg_req_id_high : 8 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_sys_state1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_ltssm_state : 6 ;
+ UINT32 pcie3_mac_phy_rate : 2 ;
+ UINT32 pcie3_slv_err_int : 1 ;
+ UINT32 pcie3_retry_sram_addr : 10 ;
+ UINT32 pcie3_mstr_rresp_int : 1 ;
+ UINT32 pcie3_mstr_bresp_int : 1 ;
+ UINT32 pcie3_radm_inta_reg : 1 ;
+ UINT32 pcie3_radm_intb_reg : 1 ;
+ UINT32 pcie3_radm_intc_reg : 1 ;
+ UINT32 pcie3_radm_intd_reg : 1 ;
+ UINT32 pcie3_cfg_pme_int_reg : 1 ;
+ UINT32 pcie3_radm_vendor_msg_reg : 1 ;
+ UINT32 pcie3_bridge_flush_not : 1 ;
+ UINT32 pcie3_link_req_rst_not : 1 ;
+ UINT32 reserved_0 : 3 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_sys_state4;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 pcie3_pciephy_ctrl_error : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_pcie3_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_lock_a : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_a_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_varible_out_a : 16 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_a_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_dcell_out_a_h : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_a_3;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_lock_b : 1 ;
+ UINT32 reserved_0 : 31 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_b_0;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_varible_out_b : 16 ;
+ UINT32 reserved_0 : 16 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_b_1;
+
+
+typedef union
+{
+
+ struct
+ {
+ UINT32 skew_dcell_out_b_h : 4 ;
+ UINT32 reserved_0 : 28 ;
+ } Bits;
+
+
+ UINT32 UInt32;
+
+} u_sc_skew_st_b_3;
+
+#endif
+
+
diff --git a/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.c b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.c
new file mode 100644
index 0000000..72bb7f5
--- /dev/null
+++ b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.c
@@ -0,0 +1,53 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CpldIoLib.h>
+
+
+VOID WriteCpldReg(UINTN ulRegAddr, UINT8 ulValue)
+{
+ MmioWrite8 (ulRegAddr + PcdGet64(PcdCpldBaseAddress), ulValue);
+}
+
+
+UINT8 ReadCpldReg(UINTN ulRegAddr)
+{
+ return MmioRead8 (ulRegAddr + PcdGet64(PcdCpldBaseAddress));
+}
+
+
+VOID ReadCpldBytes(UINT16 Addr, UINT8 *Data, UINT8 Bytes)
+{
+ UINT8 i;
+
+ for(i = 0;i < Bytes; i++)
+ {
+ *(Data + i) = ReadCpldReg(Addr + i);
+ }
+}
+
+VOID WriteCpldBytes(UINT16 Addr, UINT8 *Data, UINT8 Bytes)
+{
+ UINT8 i;
+
+ for(i = 0; i < Bytes; i++)
+ {
+ WriteCpldReg(Addr + i, *(Data + i));
+ }
+}
diff --git a/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
new file mode 100644
index 0000000..d6e23cc
--- /dev/null
+++ b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
@@ -0,0 +1,47 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CpldIoLib
+ FILE_GUID = 4633665C-0029-464E-9788-58B8D49FF57E
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CpldIoLib
+
+[Sources.common]
+ CpldIoLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ BaseLib
+ ArmLib
+ TimerLib
+
+[BuildOptions]
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdCpldBaseAddress
diff --git a/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h
new file mode 100644
index 0000000..d1e6c41
--- /dev/null
+++ b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h
@@ -0,0 +1,178 @@
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+**/
+
+
+#ifndef __DS3231_REAL_TIME_CLOCK_H__
+#define __DS3231_REAL_TIME_CLOCK_H__
+
+#define DS3231_REGADDR_SECONDS 0x00
+#define DS3231_REGADDR_MIUTES 0x01
+#define DS3231_REGADDR_HOURS 0x02
+#define DS3231_REGADDR_DAY 0x03
+#define DS3231_REGADDR_DATE 0x04
+#define DS3231_REGADDR_MONTH 0x05
+#define DS3231_REGADDR_YEAR 0x06
+#define DS3231_REGADDR_ALARM1SEC 0x07
+#define DS3231_REGADDR_ALARM1MIN 0x08
+#define DS3231_REGADDR_ALARM1HOUR 0x09
+#define DS3231_REGADDR_ALARM1DAY 0x0A
+#define DS3231_REGADDR_ALARM2MIN 0x0B
+#define DS3231_REGADDR_ALARM2HOUR 0x0C
+#define DS3231_REGADDR_ALARM2DAY 0x0D
+#define DS3231_REGADDR_CONTROL 0x0E
+#define DS3231_REGADDR_STATUS 0x0F
+#define DS3231_REGADDR_AGOFFSET 0x10
+#define DS3231_REGADDR_TEMPMSB 0x11
+#define DS3231_REGADDR_TEMPLSB 0x12
+
+
+typedef union {
+ struct{
+ UINT8 A1IE:1;
+ UINT8 A2IE:1;
+ UINT8 INTCN:1;
+ UINT8 RSV:2;
+ UINT8 CONV:1;
+ UINT8 BBSQW:1;
+ UINT8 EOSC_N:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_CONTROL;
+
+typedef union {
+ struct{
+ UINT8 A1F:1;
+ UINT8 A2F:1;
+ UINT8 BSY:1;
+ UINT8 EN32KHZ:2;
+ UINT8 Rsv:3;
+ UINT8 OSF:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_STATUS;
+
+
+typedef union {
+ struct{
+ UINT8 Data:7;
+ UINT8 Sign:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_AGOFFSET;
+
+typedef union {
+ struct{
+ UINT8 Data:7;
+ UINT8 Sign:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_TEMPMSB;
+
+
+typedef union {
+ struct{
+ UINT8 Rsv:6;
+ UINT8 Data:2;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_TEMPLSB;
+
+typedef union {
+ struct{
+ UINT8 Seconds:4;
+ UINT8 Seconds10:3;
+ UINT8 Rsv:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_SECONDS;
+
+typedef union {
+ struct{
+ UINT8 Minutes:4;
+ UINT8 Minutes10:3;
+ UINT8 Rsv:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_MINUTES;
+
+typedef union {
+ struct{
+ UINT8 Hour:4;
+ UINT8 Hours10:1;
+ UINT8 PM_20Hours:1;
+ UINT8 Hour24_n:1;
+ UINT8 Rsv:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_HOURS;
+
+typedef union {
+ struct{
+ UINT8 Day:3;
+ UINT8 Rsv:5;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_DAY;
+
+typedef union {
+ struct{
+ UINT8 Month:4;
+ UINT8 Month10:1;
+ UINT8 Rsv:2;
+ UINT8 Century:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_MONTH;
+
+typedef union {
+ struct{
+ UINT8 Year:4;
+ UINT8 Year10:4;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_YEAR;
+
+typedef union {
+ struct{
+ UINT8 Seconds:4;
+ UINT8 Seconds10:3;
+ UINT8 A1M1:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_ALARM1SEC;
+
+typedef union {
+ struct{
+ UINT8 Minutes:4;
+ UINT8 Minutes10:3;
+ UINT8 A1M2:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_ALARM1MIN;
+
+typedef union {
+ struct{
+ UINT8 Hour:4;
+ UINT8 Hours10:1;
+ UINT8 PM_20Hours:1;
+ UINT8 Hours24:1;
+ UINT8 A1M3:1;
+ }bits;
+ UINT8 u8;
+}RTC_DS3231_ALARM1HOUR;
+
+#endif
diff --git a/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
new file mode 100644
index 0000000..693ddd8
--- /dev/null
+++ b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
@@ -0,0 +1,433 @@
+/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Currently this driver does not support runtime virtual calling.
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+**/
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+// Use EfiAtRuntime to check stage
+#include <Library/UefiRuntimeLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/TimerLib.h>
+#include <Library/EfiTimeBaseLib.h>
+#include <Protocol/RealTimeClock.h>
+#include <Library/I2CLib.h>
+#include "DS3231RealTimeClock.h"
+
+extern I2C_DEVICE gDS3231RtcDevice;
+
+STATIC BOOLEAN mDS3231Initialized = FALSE;
+
+EFI_STATUS
+IdentifyDS3231 (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+ return Status;
+}
+
+EFI_STATUS
+InitializeDS3231 (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ I2C_DEVICE Dev;
+ RTC_DS3231_CONTROL Temp;
+ RTC_DS3231_HOURS Hours;
+
+ // Prepare the hardware
+ (VOID)IdentifyDS3231();
+
+ (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+ Status = I2CInit(Dev.Socket,Dev.Port,Normal);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ // Ensure interrupts are masked. We do not want RTC interrupts in UEFI
+ Status = I2CRead(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ Temp.bits.INTCN = 0;
+ Status = I2CWrite(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+
+ MicroSecondDelay(2000);
+ Status = I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ Hours.bits.Hour24_n = 0;
+ Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+
+
+ mDS3231Initialized = TRUE;
+
+ EXIT:
+ return Status;
+}
+
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT8 Temp;
+ UINT8 BaseHour = 0;
+ UINT16 BaseYear = 1900;
+
+ I2C_DEVICE Dev;
+
+ // Ensure Time is a valid pointer
+ if (NULL == Time) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Initialize the hardware if not already done
+ if (!mDS3231Initialized) {
+ Status = InitializeDS3231 ();
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_READY;
+ }
+ }
+
+ (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+
+ Time->Month = ((Temp>>4)&1)*10+(Temp&0x0F);
+
+
+ if(Temp&0x80){
+ BaseYear = 2000;
+ }
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_YEAR,1,&Temp);
+
+ Time->Year = BaseYear+(Temp>>4) *10 + (Temp&0x0F);
+
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_DATE,1,&Temp);
+
+ Time->Day = ((Temp>>4)&3) *10 + (Temp&0x0F);
+
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Temp);
+
+ BaseHour = 0;
+ if((Temp&0x30) == 0x30){
+ return EFI_DEVICE_ERROR;
+ }else if(Temp&0x20){
+ BaseHour = 20;
+ }else if(Temp&0x10){
+ BaseHour = 10;
+ }
+ Time->Hour = BaseHour + (Temp&0x0F);
+
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_MIUTES,1,&Temp);
+
+ Time->Minute = ((Temp>>4)&7) * 10 + (Temp&0x0F);
+
+
+ Status |= I2CRead(&Dev,DS3231_REGADDR_SECONDS,1,&Temp);
+
+ Time->Second = (Temp>>4) * 10 + (Temp&0x0F);
+
+ Time->Nanosecond = 0;
+ Time->Daylight = 0;
+ Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+
+ if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ I2C_DEVICE Dev;
+ UINT8 Temp;
+ UINT16 BaseYear = 1900;
+
+ // Check the input parameters are within the range specified by UEFI
+ if(!IsTimeValid(Time)){
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Initialize the hardware if not already done
+ if (!mDS3231Initialized) {
+ Status = InitializeDS3231 ();
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ }
+
+ (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+ Temp = ((Time->Second/10)<<4) | (Time->Second%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_SECONDS,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ Temp = ((Time->Minute/10)<<4) | (Time->Minute%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_MIUTES,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ Temp = 0;
+ if(Time->Hour > 19){
+ Temp = 2;
+ } else if(Time->Hour > 9){
+ Temp = 1;
+ }
+ Temp = (Temp << 4) | (Time->Hour%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ Temp = ((Time->Day/10)<<4) | (Time->Day%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_DATE,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ Temp = 0;
+ if(Time->Year >= 2000){
+ Temp = 0x8;
+ BaseYear = 2000;
+ }
+
+ if(Time->Month > 9){
+ Temp |= 0x1;
+ }
+ Temp = (Temp<<4) | (Time->Month%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ Temp = (((Time->Year-BaseYear)/10)<<4) | (Time->Year%10);
+ MicroSecondDelay(1000);
+ Status = I2CWrite(&Dev,DS3231_REGADDR_YEAR,1,&Temp);
+ if(EFI_ERROR (Status)){
+ goto EXIT;
+ }
+
+ EXIT:
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+
+ EFI_TIME EfiTime;
+
+ // Setup the setters and getters
+ gRT->GetTime = LibGetTime;
+ gRT->SetTime = LibSetTime;
+ gRT->GetWakeupTime = LibGetWakeupTime;
+ gRT->SetWakeupTime = LibSetWakeupTime;
+
+ Status = gRT->GetTime (&EfiTime, NULL);
+ if(EFI_ERROR (Status) || (EfiTime.Year < 2000) || (EfiTime.Year > 2099)){
+ EfiTime.Year = 2000;
+ EfiTime.Month = 1;
+ EfiTime.Day = 1;
+ EfiTime.Hour = 0;
+ EfiTime.Minute = 0;
+ EfiTime.Second = 0;
+ EfiTime.Nanosecond = 0;
+ EfiTime.Daylight = 0;
+ EfiTime.TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+
+ Status = gRT->SetTime(&EfiTime);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LINE__, Status));
+ }
+ }
+
+ // Install the protocol
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiRealTimeClockArchProtocolGuid, NULL,
+ NULL
+ );
+
+ return Status;
+}
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ //
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+ // to virtual address. After the OS transitions to calling in virtual mode, all future
+ // runtime calls will be made in virtual mode.
+ //
+ return;
+}
diff --git a/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
new file mode 100644
index 0000000..10ce5ff
--- /dev/null
+++ b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
@@ -0,0 +1,49 @@
+#/** @file
+#
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+# Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DS3231RealTimeClockLib
+ FILE_GUID = 470DFB96-E205-4515-A75E-2E60F853E79D
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ DS3231RealTimeClockLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ OpenPlatformPkg/OpenPlatformPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ IoLib
+ UefiLib
+ DebugLib
+ PcdLib
+ I2CLib
+ TimerLib
+# Use EFiAtRuntime to check stage
+ UefiRuntimeLib
+ EfiTimeBaseLib
+
+[Pcd]
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c
new file mode 100644
index 0000000..ce70ca5
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c
@@ -0,0 +1,302 @@
+/** @file
+ UART Serial Port library functions
+
+ Copyright (c) 2006 - 2009, Intel Corporation
+ Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+**/
+#include <Uefi.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/IoLib.h>
+#include <Protocol/SerialIo.h>
+
+#include "Dw8250SerialPortLib.h"
+
+
+/**
+ Initialize the serial device hardware.
+
+ If no initialization is required, then return RETURN_SUCCESS.
+ If the serial device was successfuly initialized, then return RETURN_SUCCESS.
+ If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+ @retval RETURN_SUCCESS The serial device was initialized.
+ @retval RETURN_DEVICE_ERROR The serail device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ UINT32 ulUartClkFreq;
+
+ MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8);
+ MmioWrite8 (UART_FCR_REG, UART_FCR_EN | UART_FCR_RXCLR | UART_FCR_TXCLR);
+ MmioWrite8 (UART_LCR_REG, UART_LCR_DLAB | UART_LCR_DLS8);
+
+ ulUartClkFreq = PcdGet32(PcdUartClkInHz);
+
+ MmioWrite8 (UART_DLL_REG, (ulUartClkFreq / (16 * (UINT32)BAUDRATE) ) & 0xff);
+ MmioWrite8 (UART_DLH_REG, ((ulUartClkFreq/ (16 * (UINT32)BAUDRATE) ) >> 8 ) & 0xff);
+ MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8);
+ MmioWrite8 (UART_IEL_REG, 0x00);
+
+ return RETURN_SUCCESS;
+}
+
+
+/**
+ Write data from buffer to serial device.
+
+ Writes NumberOfBytes data bytes from Buffer to the serial device.
+ The number of bytes actually written to the serial device is returned.
+ If the return value is less than NumberOfBytes, then the write operation failed.
+
+ If Buffer is NULL, then ASSERT().
+
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to be written.
+ @param NumberOfBytes Number of bytes to written to the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes written to the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN Result;
+
+ if (NULL == Buffer) {
+ return 0;
+ }
+
+ Result = NumberOfBytes;
+
+ while (NumberOfBytes--) {
+
+ SerialPortWriteChar(*Buffer);
+ Buffer++;
+ }
+
+ return Result;
+}
+
+
+/**
+ Reads data from a serial device into a buffer.
+
+ @param Buffer Pointer to the data buffer to store the data read from the serial device.
+ @param NumberOfBytes Number of bytes to read from the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes read from the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN Result;
+
+ if (NULL == Buffer) {
+ return 0;
+ }
+
+ Result = 0;
+
+ while (NumberOfBytes--) {
+ //
+ // Wait for the serail port to be ready.
+ //
+ *Buffer=SerialPortReadChar();
+ Buffer++ ;
+ Result++;
+ }
+
+ return Result;
+}
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ Polls aserial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+
+ return (BOOLEAN) ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR);
+
+}
+
+
+VOID SerialPortWriteChar(UINT8 scShowChar)
+{
+ UINT32 ulLoop = 0;
+
+ while(ulLoop < (UINT32)UART_SEND_DELAY)
+ {
+
+ if ((MmioRead8 (UART_USR_REG) & 0x02) == 0x02)
+ {
+ break;
+ }
+
+ ulLoop++;
+ }
+ MmioWrite8 (UART_THR_REG, (UINT8)scShowChar);
+
+ ulLoop = 0;
+ while(ulLoop < (UINT32)UART_SEND_DELAY)
+ {
+ if ((MmioRead8 (UART_USR_REG) & 0x04) == 0x04)
+ {
+ break;
+ }
+ ulLoop++;
+ }
+
+ return;
+}
+
+
+UINT8 SerialPortReadChar(VOID)
+{
+ UINT8 recvchar = 0;
+
+ while(1)
+ {
+ if ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR)
+ {
+ break;
+ }
+ }
+
+ recvchar = MmioRead8 (UART_RBR_REG);
+
+ return recvchar;
+}
+
+/**
+ Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
+ data bits, and stop bits on a serial device.
+
+ @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
+ device's default interface speed.
+ On output, the value actually set.
+ @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
+ serial interface. A ReceiveFifoDepth value of 0 will use
+ the device's default FIFO depth.
+ On output, the value actually set.
+ @param Timeout The requested time out for a single character in microseconds.
+ This timeout applies to both the transmit and receive side of the
+ interface. A Timeout value of 0 will use the device's default time
+ out value.
+ On output, the value actually set.
+ @param Parity The type of parity to use on this serial device. A Parity value of
+ DefaultParity will use the device's default parity value.
+ On output, the value actually set.
+ @param DataBits The number of data bits to use on the serial device. A DataBits
+ vaule of 0 will use the device's default data bit setting.
+ On output, the value actually set.
+ @param StopBits The number of stop bits to use on this serial device. A StopBits
+ value of DefaultStopBits will use the device's default number of
+ stop bits.
+ On output, the value actually set.
+
+ @retval RETURN_SUCCESS The new attributes were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Set the serial device control bits.
+
+ @param Control Control bits which are to be set on the serial device.
+
+ @retval EFI_SUCCESS The new control bits were set on the serial device.
+ @retval EFI_UNSUPPORTED The serial device does not support this operation.
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Get the serial device control bits.
+
+ @param Control Control signals read from the serial device.
+
+ @retval EFI_SUCCESS The control bits were read from the serial device.
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+
+ if (SerialPortPoll ()) {
+ // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY
+ *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ } else {
+ *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h
new file mode 100644
index 0000000..5e80257
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h
@@ -0,0 +1,116 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+**/
+
+#ifndef __DW8250_SERIALPORTLIB_H__
+#define __DW8250_SERIALPORTLIB_H__
+
+
+#define SERIAL_0_BASE_ADR (PcdGet64(PcdSerialRegisterBase))
+
+
+#define UART_SEND_DELAY (PcdGet32(PcdSerialPortSendDelay))
+#define BAUDRATE (PcdGet64(PcdUartDefaultBaudRate))
+
+
+#define UART_THR_REG (SERIAL_0_BASE_ADR + UART_THR)
+#define UART_RBR_REG (SERIAL_0_BASE_ADR + UART_RBR)
+#define UART_DLL_REG (SERIAL_0_BASE_ADR + UART_DLL)
+#define UART_DLH_REG (SERIAL_0_BASE_ADR + UART_DLH)
+#define UART_IEL_REG (SERIAL_0_BASE_ADR + UART_IEL)
+#define UART_IIR_REG (SERIAL_0_BASE_ADR + UART_IIR)
+#define UART_FCR_REG (SERIAL_0_BASE_ADR + UART_FCR)
+#define UART_LCR_REG (SERIAL_0_BASE_ADR + UART_LCR)
+#define UART_LSR_REG (SERIAL_0_BASE_ADR + UART_LSR)
+#define UART_USR_REG (SERIAL_0_BASE_ADR + UART_USR)
+
+
+#define UART_RBR 0x00
+#define UART_THR 0x00
+#define UART_DLL 0x00
+#define UART_DLH 0x04
+#define UART_IEL 0x04
+#define UART_IIR 0x08
+#define UART_FCR 0x08
+#define UART_LCR 0x0C
+#define UART_MCR 0x10
+#define UART_LSR 0x14
+#define UART_USR 0x7C
+
+/* register definitions */
+
+#define UART_FCR_EN 0x01
+#define UART_FCR_RXCLR 0x02
+#define UART_FCR_TXCLR 0x04
+#define UART_FCR_CLEARFIFO 0x00
+#define UART_FCR_RXL1 0x00
+#define UART_FCR_RXL4 0x40
+#define UART_FCR_RXL8 0x80
+#define UART_FCR_RXL14 0xc0
+#define UART_FCR_TXL0 0x00
+#define UART_FCR_TXL4 0x20
+#define UART_FCR_TXL8 0x30
+#define UART_FCR_TXL14 0x10
+
+/*LCR Name: Line Control Register fields*/
+#define UART_LCR_DLAB 0x80
+#define UART_LCR_EPS 0x10
+#define UART_LCR_PEN 0x08
+#define UART_LCR_STOP 0x04
+#define UART_LCR_DLS8 0x03
+#define UART_LCR_DLS7 0x02
+#define UART_LCR_DLS6 0x01
+#define UART_LCR_DLS5 0x00
+
+
+#define UART_DLH_AND_DLL_WIDTH 0xFF
+
+
+#define UART_IER_PTIME 0x80
+#define UART_IER_ELSI 0x04
+#define UART_IER_ETBEI 0x02
+#define UART_IER_ERBFI 0x01
+
+
+#define UART_IIR_FIFOSE 0xC0
+
+
+#define UART_IIR_InterruptID 0x01
+#define UART_IIR_INTIDTE 0x02
+#define UART_IIR_INTIDRA 0x04
+#define UART_IIR_INTIDRLS 0x06
+#define UART_IIR_INTMASK 0x0f
+#define UART_IIR_RDA 0x04
+#define UART_IIR_TE 0x02
+
+#define UART_LSR_TEMT 0x40
+#define UART_LSR_THRE 0x20
+#define UART_LSR_BI 0x10
+#define UART_LSR_FE 0x08
+#define UART_LSR_PE 0x04
+#define UART_LSR_R 0x02
+#define UART_LSR_DR 0x01
+
+
+#define UART_USR_BUSY 0x01
+
+#define FIFO_MAXSIZE 32
+
+extern UINT8 SerialPortReadChar(VOID);
+extern VOID SerialPortWriteChar(UINT8 scShowChar);
+
+#endif
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
new file mode 100644
index 0000000..6161e95
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
@@ -0,0 +1,45 @@
+#/** @file
+#
+# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Dw8250SerialPortLib
+ FILE_GUID = 16D53E86-7EA6-47bd-861F-511ED9B8ABE0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+
+[Sources.common]
+ Dw8250SerialPortLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gHisiTokenSpaceGuid.PcdSerialPortSendDelay
+ gHisiTokenSpaceGuid.PcdUartClkInHz
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.c b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.c
new file mode 100644
index 0000000..d092659
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.c
@@ -0,0 +1,356 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+**/
+#include <Uefi.h>
+#include <PiDxe.h>
+
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+
+#include <Protocol/SerialIo.h>
+#include <Guid/EventGroup.h>
+#include "Dw8250SerialPortRuntimeLib.h"
+
+UINT64 mSerialRegBaseAddr = 0;
+
+EFI_EVENT mSerialVirtualAddressChangeEvent = NULL;
+
+VOID
+EFIAPI
+SerialVirtualAddressChangeCallBack (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EfiConvertPointer (0, (VOID **) &mSerialRegBaseAddr);
+
+ return;
+}
+
+
+EFI_STATUS
+EFIAPI
+SerialPortLibDestructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ if(!mSerialVirtualAddressChangeEvent ){
+ return Status;
+ }
+
+ Status = gBS->CloseEvent(mSerialVirtualAddressChangeEvent);
+ return Status;
+}
+
+/**
+ Initialize the serial device hardware.
+
+ If no initialization is required, then return RETURN_SUCCESS.
+ If the serial device was successfuly initialized, then return RETURN_SUCCESS.
+ If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+ @retval RETURN_SUCCESS The serial device was initialized.
+ @retval RETURN_DEVICE_ERROR The serail device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0};
+
+ mSerialRegBaseAddr = PcdGet64(PcdSerialRegisterBase);
+
+ Status = gDS->GetMemorySpaceDescriptor(PcdGet64(PcdSerialRegisterBase),&desp);
+ if(EFI_ERROR(Status)){
+ return Status;
+ }
+ desp.Attributes |= EFI_MEMORY_RUNTIME;
+ Status = gDS->SetMemorySpaceAttributes(PcdGet64(PcdSerialRegisterBase),PcdGet64(PcdSerialRegisterSpaceSize), desp.Attributes);
+ if(EFI_ERROR(Status)){
+ return Status;
+ }
+
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ SerialVirtualAddressChangeCallBack,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mSerialVirtualAddressChangeEvent
+ );
+
+ if(EFI_ERROR(Status)){
+ mSerialVirtualAddressChangeEvent = NULL;
+ }
+
+ return Status;
+}
+
+
+/**
+ Write data from buffer to serial device.
+
+ Writes NumberOfBytes data bytes from Buffer to the serial device.
+ The number of bytes actually written to the serial device is returned.
+ If the return value is less than NumberOfBytes, then the write operation failed.
+
+ If Buffer is NULL, then ASSERT().
+
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to be written.
+ @param NumberOfBytes Number of bytes to written to the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes written to the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN Result;
+
+ if (NULL == Buffer) {
+ return 0;
+ }
+
+ Result = NumberOfBytes;
+
+ while (NumberOfBytes--) {
+
+ SerialPortWriteChar(*Buffer);
+ Buffer++;
+ }
+
+ return Result;
+}
+
+
+/**
+ Reads data from a serial device into a buffer.
+
+ @param Buffer Pointer to the data buffer to store the data read from the serial device.
+ @param NumberOfBytes Number of bytes to read from the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes read from the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN Result;
+
+ if (NULL == Buffer) {
+ return 0;
+ }
+
+ Result = 0;
+
+ while (NumberOfBytes--) {
+ //
+ // Wait for the serail port to be ready.
+ //
+ *Buffer=SerialPortReadChar();
+ Buffer++ ;
+ Result++;
+ }
+
+ return Result;
+}
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ Polls aserial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+
+ return (BOOLEAN) ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR);
+
+}
+
+
+VOID SerialPortWriteChar(UINT8 scShowChar)
+{
+ UINT32 ulLoop = 0;
+
+ while(ulLoop < (UINT32)UART_SEND_DELAY)
+ {
+
+ if ((MmioRead8 (UART_USR_REG) & 0x02) == 0x02)
+ {
+ break;
+ }
+
+ ulLoop++;
+ }
+ MmioWrite8 (UART_THR_REG, (UINT8)scShowChar);
+
+ ulLoop = 0;
+ while(ulLoop < (UINT32)UART_SEND_DELAY)
+ {
+ if ((MmioRead8 (UART_USR_REG) & 0x04) == 0x04)
+ {
+ break;
+ }
+ ulLoop++;
+ }
+
+ return;
+}
+
+
+UINT8 SerialPortReadChar(VOID)
+{
+ UINT8 recvchar = 0;
+
+ do
+ {
+ if ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR) {
+ break;
+ }
+
+ }while(MmioRead8 (UART_USR_REG) & UART_USR_BUSY);
+
+ recvchar = MmioRead8 (UART_RBR_REG);
+
+ return recvchar;
+}
+
+/**
+ Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
+ data bits, and stop bits on a serial device.
+
+ @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
+ device's default interface speed.
+ On output, the value actually set.
+ @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
+ serial interface. A ReceiveFifoDepth value of 0 will use
+ the device's default FIFO depth.
+ On output, the value actually set.
+ @param Timeout The requested time out for a single character in microseconds.
+ This timeout applies to both the transmit and receive side of the
+ interface. A Timeout value of 0 will use the device's default time
+ out value.
+ On output, the value actually set.
+ @param Parity The type of parity to use on this serial device. A Parity value of
+ DefaultParity will use the device's default parity value.
+ On output, the value actually set.
+ @param DataBits The number of data bits to use on the serial device. A DataBits
+ vaule of 0 will use the device's default data bit setting.
+ On output, the value actually set.
+ @param StopBits The number of stop bits to use on this serial device. A StopBits
+ value of DefaultStopBits will use the device's default number of
+ stop bits.
+ On output, the value actually set.
+
+ @retval RETURN_SUCCESS The new attributes were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Set the serial device control bits.
+
+ @param Control Control bits which are to be set on the serial device.
+
+ @retval EFI_SUCCESS The new control bits were set on the serial device.
+ @retval EFI_UNSUPPORTED The serial device does not support this operation.
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Get the serial device control bits.
+
+ @param Control Control signals read from the serial device.
+
+ @retval EFI_SUCCESS The control bits were read from the serial device.
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+
+ if (SerialPortPoll ()) {
+ // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY
+ *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ } else {
+ *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.h b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.h
new file mode 100644
index 0000000..f5dcb9e
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.h
@@ -0,0 +1,116 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+**/
+
+#ifndef __DW8250_SERIALPORTLIB_H__
+#define __DW8250_SERIALPORTLIB_H__
+
+
+#define SERIAL_0_BASE_ADR (mSerialRegBaseAddr)
+
+
+#define UART_SEND_DELAY (PcdGet32(PcdSerialPortSendDelay))
+#define BAUDRATE (PcdGet64(PcdUartDefaultBaudRate))
+
+
+#define UART_THR_REG (SERIAL_0_BASE_ADR + UART_THR)
+#define UART_RBR_REG (SERIAL_0_BASE_ADR + UART_RBR)
+#define UART_DLL_REG (SERIAL_0_BASE_ADR + UART_DLL)
+#define UART_DLH_REG (SERIAL_0_BASE_ADR + UART_DLH)
+#define UART_IEL_REG (SERIAL_0_BASE_ADR + UART_IEL)
+#define UART_IIR_REG (SERIAL_0_BASE_ADR + UART_IIR)
+#define UART_FCR_REG (SERIAL_0_BASE_ADR + UART_FCR)
+#define UART_LCR_REG (SERIAL_0_BASE_ADR + UART_LCR)
+#define UART_LSR_REG (SERIAL_0_BASE_ADR + UART_LSR)
+#define UART_USR_REG (SERIAL_0_BASE_ADR + UART_USR)
+
+
+#define UART_RBR 0x00
+#define UART_THR 0x00
+#define UART_DLL 0x00
+#define UART_DLH 0x04
+#define UART_IEL 0x04
+#define UART_IIR 0x08
+#define UART_FCR 0x08
+#define UART_LCR 0x0C
+#define UART_MCR 0x10
+#define UART_LSR 0x14
+#define UART_USR 0x7C
+
+/* register definitions */
+
+#define UART_FCR_EN 0x01
+#define UART_FCR_RXCLR 0x02
+#define UART_FCR_TXCLR 0x04
+#define UART_FCR_CLEARFIFO 0x00
+#define UART_FCR_RXL1 0x00
+#define UART_FCR_RXL4 0x40
+#define UART_FCR_RXL8 0x80
+#define UART_FCR_RXL14 0xc0
+#define UART_FCR_TXL0 0x00
+#define UART_FCR_TXL4 0x20
+#define UART_FCR_TXL8 0x30
+#define UART_FCR_TXL14 0x10
+
+/*LCR Name: Line Control Register fields*/
+#define UART_LCR_DLAB 0x80
+#define UART_LCR_EPS 0x10
+#define UART_LCR_PEN 0x08
+#define UART_LCR_STOP 0x04
+#define UART_LCR_DLS8 0x03
+#define UART_LCR_DLS7 0x02
+#define UART_LCR_DLS6 0x01
+#define UART_LCR_DLS5 0x00
+
+
+#define UART_DLH_AND_DLL_WIDTH 0xFF
+
+
+#define UART_IER_PTIME 0x80
+#define UART_IER_ELSI 0x04
+#define UART_IER_ETBEI 0x02
+#define UART_IER_ERBFI 0x01
+
+
+#define UART_IIR_FIFOSE 0xC0
+
+
+#define UART_IIR_InterruptID 0x01
+#define UART_IIR_INTIDTE 0x02
+#define UART_IIR_INTIDRA 0x04
+#define UART_IIR_INTIDRLS 0x06
+#define UART_IIR_INTMASK 0x0f
+#define UART_IIR_RDA 0x04
+#define UART_IIR_TE 0x02
+
+#define UART_LSR_TEMT 0x40
+#define UART_LSR_THRE 0x20
+#define UART_LSR_BI 0x10
+#define UART_LSR_FE 0x08
+#define UART_LSR_PE 0x04
+#define UART_LSR_R 0x02
+#define UART_LSR_DR 0x01
+
+
+#define UART_USR_BUSY 0x01
+
+#define FIFO_MAXSIZE 32
+
+extern UINT8 SerialPortReadChar(VOID);
+extern VOID SerialPortWriteChar(UINT8 scShowChar);
+
+#endif
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf
new file mode 100644
index 0000000..c4ff57c
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf
@@ -0,0 +1,52 @@
+#/** @file
+#
+# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Dw8250SerialPortLib
+ FILE_GUID = 16D53E86-7EA6-47bd-861F-511ED9B8ABE0
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+ DESTRUCTOR = SerialPortLibDestructor
+
+[Sources.common]
+ Dw8250SerialPortRuntimeLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ UefiRuntimeLib
+ UefiBootServicesTableLib
+ DxeServicesTableLib
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid ## CONSUMES ## Event
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gHisiTokenSpaceGuid.PcdSerialRegisterSpaceSize
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gHisiTokenSpaceGuid.PcdSerialPortSendDelay
+ gHisiTokenSpaceGuid.PcdUartClkInHz
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CHw.h b/Chips/Hisilicon/Library/I2CLib/I2CHw.h
new file mode 100644
index 0000000..0937997
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CHw.h
@@ -0,0 +1,268 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _I2C_HW_H_
+#define _I2C_HW_H_
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+
+#define I2C_READ_TIMEOUT 500
+#define I2C_DRV_ONCE_WRITE_BYTES_NUM 8
+#define I2C_DRV_ONCE_READ_BYTES_NUM 8
+#define I2C_READ_SIGNAL 0x0100
+#define I2C_TXRX_THRESHOLD 0x7
+#define I2C_SS_SCLHCNT 0x493
+#define I2C_SS_SCLLCNT 0x4fe
+
+#define I2C_REG_WRITE(reg,data) \
+ MmioWrite32 ((reg), (data))
+
+#define I2C_REG_READ(reg,result) \
+ (result) = MmioRead32 ((reg))
+
+ #define I2C_CON_OFFSET 0x0
+ #define I2C_TAR_OFFSET 0x4
+ #define I2C_SAR_OFFSET 0x8
+ #define I2C_DATA_CMD_OFFSET 0x10
+ #define I2C_SS_SCL_HCNT_OFFSET 0x14
+ #define I2C_SS_SCL_LCNT_OFFSET 0x18
+ #define I2C_FS_SCL_HCNT_OFFSET 0x1c
+ #define I2C_FS_SCL_LCNT_OFFSET 0x20
+ #define I2C_INTR_STAT_OFFSET 0x2c
+ #define I2C_INTR_MASK_OFFSET 0x30
+ #define I2C_RAW_INTR_STAT_OFFSET 0x34
+ #define I2C_RX_TL_OFFSET 0x38
+ #define I2C_TX_TL_OFFSET 0x3c
+ #define I2C_CLR_INTR_OFFSET 0x40
+ #define I2C_CLR_RX_UNDER_OFFSET 0x44
+ #define I2C_CLR_RX_OVER_OFFSET 0x48
+ #define I2C_CLR_TX_OVER_OFFSET 0x4c
+ #define I2C_CLR_RD_REQ_OFFSET 0x50
+ #define I2C_CLR_TX_ABRT_OFFSET 0x54
+ #define I2C_CLR_RX_DONE_OFFSET 0x58
+ #define I2C_CLR_ACTIVITY_OFFSET 0x5c
+ #define I2C_CLR_STOP_DET_OFFSET 0x60
+ #define I2C_CLR_START_DET_OFFSET 0x64
+ #define I2C_CLR_GEN_CALL_OFFSET 0x68
+ #define I2C_ENABLE_OFFSET 0x6c
+ #define I2C_STATUS_OFFSET 0x70
+ #define I2C_TXFLR_OFFSET 0x74
+ #define I2C_RXFLR_OFFSET 0x78
+ #define I2C_SDA_HOLD 0x7c
+ #define I2C_TX_ABRT_SOURCE_OFFSET 0x80
+ #define I2C_SLV_DATA_ONLY_OFFSET 0x84
+ #define I2C_DMA_CR_OFFSET 0x88
+ #define I2C_DMA_TDLR_OFFSET 0x8c
+ #define I2C_DMA_RDLR_OFFSET 0x90
+ #define I2C_SDA_SETUP_OFFSET 0x94
+ #define I2C_ACK_GENERAL_CALL_OFFSET 0x98
+ #define I2C_ENABLE_STATUS_OFFSET 0x9c
+
+
+ typedef union tagI2c0Con
+ {
+ struct
+ {
+ UINT32 master : 1 ;
+ UINT32 spedd : 2 ;
+ UINT32 slave_10bit : 1 ;
+ UINT32 master_10bit : 1 ;
+ UINT32 restart_en : 1 ;
+ UINT32 slave_disable : 1 ;
+ UINT32 Reserved_0 : 25 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_CON_U;
+
+
+ typedef union tagI2c0Tar
+ {
+ struct
+ {
+ UINT32 ic_tar : 10 ;
+ UINT32 gc_or_start : 1 ;
+ UINT32 special : 1 ;
+ UINT32 ic_10bitaddr_master : 1 ;
+ UINT32 Reserved_1 : 19 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_TAR_U;
+
+
+ typedef union tagI2c0DataCmd
+ {
+ struct
+ {
+ UINT32 dat : 8 ;
+ UINT32 cmd : 1 ;
+ UINT32 Reserved_5 : 23 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_DATA_CMD_U;
+
+
+ typedef union tagI2c0SsSclHcnt
+ {
+ struct
+ {
+ UINT32 ic_ss_scl_hcnt : 16 ;
+ UINT32 Reserved_7 : 16 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_SS_SCL_HCNT_U;
+
+
+ typedef union tagI2c0SsSclLcnt
+ {
+ struct
+ {
+ UINT32 ic_ss_scl_lcnt : 16 ;
+ UINT32 Reserved_9 : 16 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_SS_SCL_LCNT_U;
+
+
+ typedef union tagI2c0FsSclHcnt
+ {
+ struct
+ {
+ UINT32 ic_fs_scl_hcnt : 16 ;
+ UINT32 Reserved_11 : 16 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_FS_SCL_HCNT_U;
+
+
+ typedef union tagI2c0FsSclLcnt
+ {
+ struct
+ {
+ UINT32 ic_fs_scl_lcnt : 16 ;
+ UINT32 Reserved_13 : 16 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_FS_SCL_LCNT_U;
+
+
+ typedef union tagI2c0IntrMask
+ {
+ struct
+ {
+ UINT32 m_rx_under : 1 ;
+ UINT32 m_rx_over : 1 ;
+ UINT32 m_rx_full : 1 ;
+ UINT32 m_tx_over : 1 ;
+ UINT32 m_tx_empty : 1 ;
+ UINT32 m_rd_req : 1 ;
+ UINT32 m_tx_abrt : 1 ;
+ UINT32 m_rx_done : 1 ;
+ UINT32 m_activity : 1 ;
+ UINT32 m_stop_det : 1 ;
+ UINT32 m_start_det : 1 ;
+ UINT32 m_gen_call : 1 ;
+ UINT32 Reserved_17 : 20 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_INTR_MASK_U;
+
+
+ typedef union tagI2c0RxTl
+ {
+ struct
+ {
+ UINT32 rx_tl : 8 ;
+ UINT32 Reserved_21 : 24 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_RX_TL_U;
+
+
+ typedef union tagI2c0TxTl
+ {
+ struct
+ {
+ UINT32 tx_tl : 8 ;
+ UINT32 Reserved_23 : 24 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_TX_TL_U;
+
+
+ typedef union tagI2c0Enable
+ {
+ struct
+ {
+ UINT32 enable : 1 ;
+ UINT32 Reserved_47 : 31 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_ENABLE_U;
+
+
+ typedef union tagI2c0Status
+ {
+ struct
+ {
+ UINT32 activity : 1 ;
+ UINT32 tfnf : 1 ;
+ UINT32 tfe : 1 ;
+ UINT32 rfne : 1 ;
+ UINT32 rff : 1 ;
+ UINT32 mst_activity : 1 ;
+ UINT32 slv_activity : 1 ;
+ UINT32 Reserved_49 : 25 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_STATUS_U;
+
+
+ typedef union tagI2c0Txflr
+ {
+ struct
+ {
+ UINT32 txflr : 4 ;
+ UINT32 Reserved_51 : 28 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_TXFLR_U;
+
+
+ typedef union tagI2c0Rxflr
+ {
+ struct
+ {
+ UINT32 rxflr : 4 ;
+ UINT32 Reserved_53 : 28 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_RXFLR_U;
+
+
+ typedef union tagI2c0EnableStatus
+ {
+ struct
+ {
+ UINT32 ic_en : 1 ;
+ UINT32 slv_disable_while_busy: 1 ;
+ UINT32 slv_rx_data_lost : 1 ;
+ UINT32 Reserved_69 : 29 ;
+ } bits;
+ UINT32 Val32;
+ } I2C0_ENABLE_STATUS_U;
+
+
+#endif
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLib.c b/Chips/Hisilicon/Library/I2CLib/I2CLib.c
new file mode 100644
index 0000000..087a4ba
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLib.c
@@ -0,0 +1,679 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/I2CLib.h>
+#include <Library/TimerLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+
+#include "I2CLibInternal.h"
+#include "I2CHw.h"
+
+VOID I2C_Delay(UINT32 ulCount)
+{
+ MicroSecondDelay(ulCount);
+ return;
+}
+
+
+EFI_STATUS
+EFIAPI
+I2C_Disable(UINT32 Socket,UINT8 Port)
+{
+ UINT32 ulTimeCnt = I2C_READ_TIMEOUT;
+ I2C0_STATUS_U I2cStatusReg;
+ I2C0_ENABLE_U I2cEnableReg;
+ I2C0_ENABLE_STATUS_U I2cEnableStatusReg;
+
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ I2C_REG_READ((Base + I2C_STATUS_OFFSET), I2cStatusReg.Val32);
+
+ while (I2cStatusReg.bits.activity)
+ {
+ I2C_Delay(10000);
+
+ ulTimeCnt--;
+ I2C_REG_READ(Base + I2C_STATUS_OFFSET, I2cStatusReg.Val32);
+ if (0 == ulTimeCnt)
+ {
+ return EFI_DEVICE_ERROR;
+ }
+ }
+
+
+ I2C_REG_READ(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+ I2cEnableReg.bits.enable = 0;
+ I2C_REG_WRITE(Base + I2C_ENABLE_OFFSET,I2cEnableReg.Val32);
+
+ I2C_REG_READ(Base + I2C_ENABLE_OFFSET,I2cEnableStatusReg.Val32);
+ if (0 == I2cEnableStatusReg.bits.ic_en)
+ {
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ return EFI_DEVICE_ERROR;
+ }
+}
+
+
+EFI_STATUS
+EFIAPI
+I2C_Enable(UINT32 Socket,UINT8 Port)
+{
+ I2C0_ENABLE_U I2cEnableReg;
+ I2C0_ENABLE_STATUS_U I2cEnableStatusReg;
+
+ UINTN Base = GetI2cBase(Socket, Port);
+
+
+ I2C_REG_READ(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+ I2cEnableReg.bits.enable = 1;
+ I2C_REG_WRITE(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+
+
+ I2C_REG_READ(Base + I2C_ENABLE_STATUS_OFFSET, I2cEnableStatusReg.Val32);
+ if (1 == I2cEnableStatusReg.bits.ic_en)
+ {
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ return EFI_DEVICE_ERROR;
+ }
+}
+
+void I2C_SetTarget(UINT32 Socket,UINT8 Port,UINT32 I2cDeviceAddr)
+{
+ I2C0_TAR_U I2cTargetReg;
+ UINTN Base = GetI2cBase(Socket, Port);
+
+
+ I2C_REG_READ(Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
+ I2cTargetReg.bits.ic_tar = I2cDeviceAddr;
+ I2C_REG_WRITE(Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
+
+ return;
+}
+
+
+EFI_STATUS
+EFIAPI
+I2CInit(UINT32 Socket, UINT32 Port, SPEED_MODE SpeedMode)
+{
+ I2C0_CON_U I2cControlReg;
+ I2C0_SS_SCL_HCNT_U I2cStandardSpeedSclHighCount;
+ I2C0_SS_SCL_LCNT_U I2cStandardSpeedSclLowCount;
+ I2C0_RX_TL_U I2cRxFifoReg;
+ I2C0_TX_TL_U I2cTxFifoReg;
+ I2C0_INTR_MASK_U I2cIntrMask;
+ EFI_STATUS Status;
+
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ if((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX) || (SpeedMode >= SPEED_MODE_MAX)){
+ return EFI_INVALID_PARAMETER;
+ }
+
+
+ Status = I2C_Disable(Socket,Port);
+ if(EFI_ERROR(Status))
+ {
+ return EFI_DEVICE_ERROR;
+ }
+
+
+ I2C_REG_READ(Base + I2C_CON_OFFSET, I2cControlReg.Val32);
+ I2cControlReg.bits.master = 1;
+ I2cControlReg.bits.spedd = 0x1;
+ I2cControlReg.bits.restart_en = 1;
+ I2cControlReg.bits.slave_disable = 1;
+ I2C_REG_WRITE(Base + I2C_CON_OFFSET,I2cControlReg.Val32);
+
+
+ if(Normal == SpeedMode)
+ {
+ I2C_REG_READ(Base + I2C_SS_SCL_HCNT_OFFSET,I2cStandardSpeedSclHighCount.Val32);
+ I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
+ I2C_REG_WRITE(Base + I2C_SS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
+ I2C_REG_READ(Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+ I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
+ I2C_REG_WRITE(Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+ }
+ else
+ {
+ I2C_REG_READ(Base + I2C_FS_SCL_HCNT_OFFSET,I2cStandardSpeedSclHighCount.Val32);
+ I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
+ I2C_REG_WRITE(Base + I2C_FS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
+ I2C_REG_READ(Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+ I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
+ I2C_REG_WRITE(Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+ }
+
+
+ I2C_REG_READ(Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
+ I2cRxFifoReg.bits.rx_tl = I2C_TXRX_THRESHOLD;
+ I2C_REG_WRITE(Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
+ I2C_REG_READ(Base + I2C_TX_TL_OFFSET,I2cTxFifoReg.Val32);
+ I2cTxFifoReg.bits.tx_tl = I2C_TXRX_THRESHOLD;
+ I2C_REG_WRITE(Base + I2C_TX_TL_OFFSET, I2cTxFifoReg.Val32);
+
+
+ I2C_REG_READ(Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
+ I2cIntrMask.Val32 = 0x0;
+ I2C_REG_WRITE(Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
+
+
+ Status = I2C_Enable(Socket,Port);
+ if(EFI_ERROR(Status))
+ {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return I2cLibRuntimeSetup (Socket, Port);
+}
+
+EFI_STATUS
+EFIAPI
+I2CSdaConfig(UINT32 Socket, UINT32 Port)
+{
+
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ if((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX)){
+ return EFI_INVALID_PARAMETER;
+ }
+
+ I2C_REG_WRITE(Base + I2C_SDA_HOLD, 0x14);
+
+ return EFI_SUCCESS;
+}
+
+
+
+UINT32 I2C_GetTxStatus(UINT32 Socket,UINT8 Port)
+{
+ I2C0_TXFLR_U ulFifo;
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ I2C_REG_READ(Base + I2C_TXFLR_OFFSET, ulFifo.Val32);
+ return ulFifo.bits.txflr;
+}
+
+UINT32
+I2C_GetRxStatus(UINT32 Socket,UINT8 Port)
+{
+ I2C0_RXFLR_U ulFifo;
+ UINTN Base = GetI2cBase(Socket, Port);
+
+ I2C_REG_READ(Base + I2C_RXFLR_OFFSET, ulFifo.Val32);
+ return ulFifo.bits.rxflr;
+}
+
+EFI_STATUS
+EFIAPI
+WriteBeforeRead(I2C_DEVICE *I2cInfo, UINT32 ulLength, UINT8 *pBuf)
+{
+ UINT32 ulFifo;
+ UINT32 ulCnt;
+ UINT32 ulTimes = 0;
+
+ UINTN Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ for(ulCnt = 0; ulCnt < ulLength; ulCnt++)
+ {
+ ulTimes = 0;
+ while(ulFifo > I2C_TXRX_THRESHOLD)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ ulTimes = 0;
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf)
+{
+ UINT32 ulFifo;
+ UINT32 ulTimes = 0;
+ UINT32 Idx;
+ UINTN Base;
+
+
+ if(I2cInfo->Port >= I2C_PORT_MAX)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+
+ (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+
+ if(I2cInfo->DeviceType)
+ {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+ }
+ else
+ {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+ }
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ ulTimes = 0;
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ for(Idx = 0; Idx < ulLength; Idx++)
+ {
+ ulTimes = 0;
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(ulFifo > I2C_TXRX_THRESHOLD)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+ }
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ ulTimes = 0;
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ DEBUG ((EFI_D_ERROR, "I2C Write try to finished,time out!\n"));
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf)
+{
+ UINT32 ulCnt;
+ UINT16 usTotalLen = 0;
+ UINT32 ulFifo;
+ UINT32 ulTimes = 0;
+ UINT8 I2CWAddr[2];
+ EFI_STATUS Status;
+ UINT32 BytesLeft;
+ UINT32 Idx = 0;
+ UINTN Base;
+
+
+ if(I2cInfo->Port >= I2C_PORT_MAX)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+ Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+ if(I2cInfo->DeviceType)
+ {
+ I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
+ I2CWAddr[1] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 2,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+ else
+ {
+ I2CWAddr[0] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 1,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+
+ while(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+ usTotalLen = ulRxLen;
+ BytesLeft = usTotalLen;
+
+ while(BytesLeft >= I2C_DRV_ONCE_READ_BYTES_NUM){
+
+
+ for(ulCnt = 0; ulCnt < I2C_DRV_ONCE_READ_BYTES_NUM; ulCnt++) {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
+ }
+
+
+ for(ulCnt = 0; ulCnt < I2C_DRV_ONCE_READ_BYTES_NUM; ulCnt++) {
+ ulTimes = 0;
+ do {
+ I2C_Delay(2);
+
+ while(++ulTimes > I2C_READ_TIMEOUT) {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port);
+
+ }while(0 == ulFifo);
+
+ I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+ }
+ BytesLeft -= I2C_DRV_ONCE_READ_BYTES_NUM;
+ }
+
+
+ for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
+ }
+
+
+ for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+ ulTimes = 0;
+ do {
+ I2C_Delay(2);
+
+ while(++ulTimes > I2C_READ_TIMEOUT) {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }while(0 == ulFifo);
+
+ I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+ }
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+I2CReadMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf)
+{
+ UINT32 ulCnt;
+ UINT16 usTotalLen = 0;
+ UINT32 ulFifo;
+ UINT32 ulTimes = 0;
+ UINT8 I2CWAddr[4];
+ EFI_STATUS Status;
+ UINT32 BytesLeft;
+ UINT32 Idx = 0;
+ UINTN Base;
+
+
+ if(I2cInfo->Port >= I2C_PORT_MAX)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+ Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+ if(I2cInfo->DeviceType == DEVICE_TYPE_E2PROM)
+ {
+ I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
+ I2CWAddr[1] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 2,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+ else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS)
+ {
+ I2CWAddr[0] = (InfoOffset >> 16) & 0xff;
+ I2CWAddr[1] = (InfoOffset >> 8) & 0xff;
+ I2CWAddr[2] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 3,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+ else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS)
+ {
+ I2CWAddr[0] = (InfoOffset >> 24) & 0xff;
+ I2CWAddr[1] = (InfoOffset >> 16) & 0xff;
+ I2CWAddr[2] = (InfoOffset >> 8) & 0xff;
+ I2CWAddr[3] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 4,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+ else
+ {
+ I2CWAddr[0] = (InfoOffset & 0xff);
+ Status = WriteBeforeRead(I2cInfo, 1,I2CWAddr);
+ if(EFI_ERROR(Status))
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_ABORTED;
+ }
+ }
+
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+ usTotalLen = ulRxLen;
+ BytesLeft = usTotalLen;
+
+ for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
+ }
+
+
+ for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+ ulTimes = 0;
+ do {
+ I2C_Delay(2);
+
+ while(++ulTimes > I2C_READ_TIMEOUT) {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }while(0 == ulFifo);
+
+ I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+ }
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+I2CWriteMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset, UINT32 ulLength, UINT8 *pBuf)
+{
+ UINT32 ulFifo;
+ UINT32 ulTimes = 0;
+ UINT32 Idx;
+ UINTN Base;
+
+
+ if(I2cInfo->Port >= I2C_PORT_MAX)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+
+ (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+
+ I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+
+
+ if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS)
+ {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+ }
+
+ else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS)
+ {
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 24) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+ }
+
+ else
+ {
+
+ }
+
+ ulTimes = 0;
+ for(Idx = 0; Idx < ulLength; Idx++)
+ {
+
+ I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+
+ }
+
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ ulTimes = 0;
+ while(0 != ulFifo)
+ {
+ I2C_Delay(2);
+
+ if(++ulTimes > I2C_READ_TIMEOUT)
+ {
+ DEBUG ((EFI_D_ERROR, "I2C Write try to finished,time out!\n"));
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+ return EFI_TIMEOUT;
+ }
+ ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+ }
+ (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLib.inf b/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
new file mode 100644
index 0000000..b5cbfc3
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
@@ -0,0 +1,49 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = I2CLib
+ FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = I2CLib
+
+[Sources.common]
+ I2CLib.c
+ I2CLibCommon.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ BaseLib
+ ArmLib
+ TimerLib
+
+ PlatformSysCtrlLib
+
+[BuildOptions]
+
+[Pcd]
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLibCommon.c b/Chips/Hisilicon/Library/I2CLib/I2CLibCommon.c
new file mode 100644
index 0000000..499c2d7
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLibCommon.c
@@ -0,0 +1,35 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include "I2CLibInternal.h"
+
+UINTN GetI2cBase (UINT32 Socket, UINT8 Port)
+{
+ return PlatformGetI2cBase(Socket, Port);
+}
+
+EFI_STATUS
+I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port)
+{
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLibInternal.h b/Chips/Hisilicon/Library/I2CLib/I2CLibInternal.h
new file mode 100644
index 0000000..1429729
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLibInternal.h
@@ -0,0 +1,29 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _I2C_LIB_INTERNAL_H_
+#define _I2C_LIB_INTERNAL_H_
+
+#include <PlatformArch.h>
+#include <Library/I2CLib.h>
+
+UINTN GetI2cBase (UINT32 Socket, UINT8 Port);
+
+EFI_STATUS
+I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port);
+
+
+#endif
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.c b/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.c
new file mode 100644
index 0000000..678b5a0
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.c
@@ -0,0 +1,109 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Guid/EventGroup.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include "I2CLibInternal.h"
+
+STATIC EFI_EVENT mI2cLibVirtualAddrChangeEvent;
+
+STATIC UINTN gI2cBase[MAX_SOCKET][I2C_PORT_MAX];
+
+UINTN GetI2cBase (UINT32 Socket, UINT8 Port)
+{
+ if (gI2cBase[Socket][Port] == 0) {
+ gI2cBase[Socket][Port] = PlatformGetI2cBase(Socket, Port);
+ }
+
+ return gI2cBase[Socket][Port];
+}
+
+VOID
+EFIAPI
+I2cLibVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINT32 Socket;
+ UINT8 Port;
+
+ // We assume that all I2C ports used in one runtime driver need to be
+ // converted into virtual address.
+ for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
+ for (Port = 0; Port < I2C_PORT_MAX; Port++) {
+ if (gI2cBase[Socket][Port] != 0) {
+ EfiConvertPointer (0x0, (VOID **)&gI2cBase[Socket][Port]);
+ }
+ }
+ }
+
+ return;
+}
+
+EFI_STATUS
+I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port)
+{
+ EFI_STATUS Status;
+
+ UINTN Base = GetI2cBase (Socket, Port);
+
+ // Declare the controller as EFI_MEMORY_RUNTIME
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ Base, SIZE_64KB,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_WARN, "[%a:%d] AddMemorySpace failed: %r\n", __FUNCTION__, __LINE__, Status));
+ }
+
+ Status = gDS->SetMemorySpaceAttributes (Base, SIZE_64KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] SetMemorySpaceAttributes failed: %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ //
+ // Register for the virtual address change event
+ //
+ // Only create event once
+ if (mI2cLibVirtualAddrChangeEvent == NULL) {
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ I2cLibVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mI2cLibVirtualAddrChangeEvent
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] Create event failed: %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
new file mode 100644
index 0000000..24a232f
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
@@ -0,0 +1,51 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = I2CLibRuntime
+ FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = I2CLib
+
+[Sources.common]
+ I2CLib.c
+ I2CLibRuntime.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ BaseLib
+ ArmLib
+ TimerLib
+ DxeServicesTableLib
+ UefiRuntimeLib
+
+ PlatformSysCtrlLib
+
+[BuildOptions]
+
+[Pcd]
+
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c
new file mode 100644
index 0000000..43a4385
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c
@@ -0,0 +1,524 @@
+/** @file
+ Implementation for PlatformBdsLib library class interfaces.
+
+ Copyright (C) 2015, Red Hat, Inc.
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmVirtPkg/Library/PlatformIntelBdsLib/
+
+**/
+
+#include <IndustryStandard/Pci22.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformBdsLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#include "IntelBdsPlatform.h"
+
+
+//3CEF354A-3B7A-4519-AD70-72A134698311
+GUID gEblFileGuid = {0x3CEF354A, 0x3B7A, 0x4519, {0xAD, 0x70,
+ 0x72, 0xA1, 0x34, 0x69, 0x83, 0x11} };
+
+// Need to keep the same with FlashStartOs.inf
+// 282cae50-940e-11e5-b7b8-774201c0f2d8
+GUID gFlashStartOsAppGuid = { 0x282cae50, 0x940e, 0x11e5, {0xb7, 0xb8,
+ 0x77, 0x42, 0x01, 0xc0, 0xf2, 0xd8} };
+
+// Need to keep the same with EslStartOs.inf
+// 8880a72c-9411-11e5-b6f0-97310bc151d1
+GUID gEslStartOsAppGuid = { 0x8880a72c, 0x9411, 0x11e5, {0xb6, 0xf0,
+ 0x97, 0x31, 0x0b, 0xc1, 0x51, 0xd1} };
+
+EFI_STATUS
+BdsDeleteAllInvalidEfiBootOption (
+ VOID
+ );
+
+#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }
+
+
+#pragma pack (1)
+typedef struct {
+ VENDOR_DEVICE_PATH SerialDxe;
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEFINED_DEVICE_PATH Vt100;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_SERIAL_CONSOLE;
+#pragma pack ()
+
+#define SERIAL_DXE_FILE_GUID { \
+ 0xD3987D4B, 0x971A, 0x435F, \
+ { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \
+ }
+
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+ //
+ // VENDOR_DEVICE_PATH SerialDxe
+ //
+ {
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
+ SERIAL_DXE_FILE_GUID
+ },
+
+ //
+ // UART_DEVICE_PATH Uart
+ //
+ {
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+ 0, // Reserved
+ FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
+ FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits
+ FixedPcdGet8 (PcdUartDefaultParity), // Parity
+ FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits
+ },
+
+ //
+ // VENDOR_DEFINED_DEVICE_PATH Vt100
+ //
+ {
+ {
+ MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,
+ DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)
+ },
+ EFI_VT_100_GUID
+ },
+
+ //
+ // EFI_DEVICE_PATH_PROTOCOL End
+ //
+ {
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+ }
+};
+
+
+#pragma pack (1)
+typedef struct {
+ USB_CLASS_DEVICE_PATH Keyboard;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_USB_KEYBOARD;
+#pragma pack ()
+
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
+ //
+ // USB_CLASS_DEVICE_PATH Keyboard
+ //
+ {
+ {
+ MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP,
+ DP_NODE_LEN (USB_CLASS_DEVICE_PATH)
+ },
+ 0xFFFF, // VendorId: any
+ 0xFFFF, // ProductId: any
+ 3, // DeviceClass: HID
+ 1, // DeviceSubClass: boot
+ 1 // DeviceProtocol: keyboard
+ },
+
+ //
+ // EFI_DEVICE_PATH_PROTOCOL End
+ //
+ {
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+ }
+};
+
+
+//
+// BDS Platform Functions
+//
+/**
+ Platform Bds init. Include the platform firmware vendor, revision
+ and so crc check.
+
+**/
+VOID
+EFIAPI
+PlatformBdsInit (
+ VOID
+ )
+{
+}
+
+
+/**
+ Check if the handle satisfies a particular condition.
+
+ @param[in] Handle The handle to check.
+ @param[in] ReportText A caller-allocated string passed in for reporting
+ purposes. It must never be NULL.
+
+ @retval TRUE The condition is satisfied.
+ @retval FALSE Otherwise. This includes the case when the condition could not
+ be fully evaluated due to an error.
+**/
+typedef
+BOOLEAN
+(EFIAPI *FILTER_FUNCTION) (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ );
+
+
+/**
+ Process a handle.
+
+ @param[in] Handle The handle to process.
+ @param[in] ReportText A caller-allocated string passed in for reporting
+ purposes. It must never be NULL.
+**/
+typedef
+VOID
+(EFIAPI *CALLBACK_FUNCTION) (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ );
+
+/**
+ Locate all handles that carry the specified protocol, filter them with a
+ callback function, and pass each handle that passes the filter to another
+ callback.
+
+ @param[in] ProtocolGuid The protocol to look for.
+
+ @param[in] Filter The filter function to pass each handle to. If this
+ parameter is NULL, then all handles are processed.
+
+ @param[in] Process The callback function to pass each handle to that
+ clears the filter.
+**/
+STATIC
+VOID
+FilterAndProcess (
+ IN EFI_GUID *ProtocolGuid,
+ IN FILTER_FUNCTION Filter OPTIONAL,
+ IN CALLBACK_FUNCTION Process
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *Handles;
+ UINTN NoHandles;
+ UINTN Idx;
+
+ Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,
+ NULL /* SearchKey */, &NoHandles, &Handles);
+ if (EFI_ERROR (Status)) {
+ //
+ // This is not an error, just an informative condition.
+ //
+ DEBUG ((EFI_D_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,
+ Status));
+ return;
+ }
+
+ ASSERT (NoHandles > 0);
+ for (Idx = 0; Idx < NoHandles; ++Idx) {
+ CHAR16 *DevicePathText;
+ STATIC CHAR16 Fallback[] = L"<device path unavailable>";
+
+ //
+ // The ConvertDevicePathToText() function handles NULL input transparently.
+ //
+ DevicePathText = ConvertDevicePathToText (
+ DevicePathFromHandle (Handles[Idx]),
+ FALSE, // DisplayOnly
+ FALSE // AllowShortcuts
+ );
+ if (DevicePathText == NULL) {
+ DevicePathText = Fallback;
+ }
+
+ if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) {
+ Process (Handles[Idx], DevicePathText);
+ }
+
+ if (DevicePathText != Fallback) {
+ FreePool (DevicePathText);
+ }
+ }
+ gBS->FreePool (Handles);
+}
+
+
+/**
+ This FILTER_FUNCTION checks if a handle corresponds to a PCI display device.
+**/
+STATIC
+BOOLEAN
+EFIAPI
+IsPciDisplay (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ )
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
+
+ Status = gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid,
+ (VOID**)&PciIo);
+ if (EFI_ERROR (Status)) {
+ //
+ // This is not an error worth reporting.
+ //
+ return FALSE;
+ }
+
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */,
+ sizeof Pci / sizeof (UINT32), &Pci);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status));
+ return FALSE;
+ }
+
+ return IS_PCI_DISPLAY (&Pci);
+}
+
+
+/**
+ This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking
+ the matching driver to produce all first-level child handles.
+**/
+STATIC
+VOID
+EFIAPI
+Connect (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->ConnectController (
+ Handle, // ControllerHandle
+ NULL, // DriverImageHandle
+ NULL, // RemainingDevicePath -- produce all children
+ FALSE // Recursive
+ );
+ DEBUG ((EFI_ERROR (Status) ? EFI_D_ERROR : EFI_D_VERBOSE, "%a: %s: %r\n",
+ __FUNCTION__, ReportText, Status));
+}
+
+
+/**
+ This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the
+ handle, and adds it to ConOut and ErrOut.
+**/
+STATIC
+VOID
+EFIAPI
+AddOutput (
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ DevicePath = DevicePathFromHandle (Handle);
+ if (DevicePath == NULL) {
+ DEBUG ((EFI_D_ERROR, "%a: %s: handle %p: device path not found\n",
+ __FUNCTION__, ReportText, Handle));
+ return;
+ }
+
+ Status = BdsLibUpdateConsoleVariable (L"ConOut", DevicePath, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__,
+ ReportText, Status));
+ return;
+ }
+
+ Status = BdsLibUpdateConsoleVariable (L"ErrOut", DevicePath, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__,
+ ReportText, Status));
+ return;
+ }
+
+ DEBUG ((EFI_D_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTION__,
+ ReportText));
+}
+
+
+/**
+ The function will execute with as the platform policy, current policy
+ is driven by boot mode. IBV/OEM can customize this code for their specific
+ policy action.
+
+ @param DriverOptionList The header of the driver option link list
+ @param BootOptionList The header of the boot option link list
+ @param ProcessCapsules A pointer to ProcessCapsules()
+ @param BaseMemoryTest A pointer to BaseMemoryTest()
+
+**/
+VOID
+EFIAPI
+PlatformBdsPolicyBehavior (
+ IN LIST_ENTRY *DriverOptionList,
+ IN LIST_ENTRY *BootOptionList,
+ IN PROCESS_CAPSULES ProcessCapsules,
+ IN BASEM_MEMORY_TEST BaseMemoryTest
+ )
+{
+ EFI_STATUS Status;
+ //
+ // Locate the PCI root bridges and make the PCI bus driver connect each,
+ // non-recursively. This will produce a number of child handles with PciIo on
+ // them.
+ //
+ FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect);
+
+ //
+ // Find all display class PCI devices (using the handles from the previous
+ // step), and connect them non-recursively. This should produce a number of
+ // child handles with GOPs on them.
+ //
+ FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect);
+
+ //
+ // Now add the device path of all handles with GOP on them to ConOut and
+ // ErrOut.
+ //
+ FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput);
+
+ //
+ // Add the hardcoded short-form USB keyboard device path to ConIn.
+ //
+ BdsLibUpdateConsoleVariable (L"ConIn",
+ (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);
+
+ //
+ // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.
+ //
+ BdsLibUpdateConsoleVariable (L"ConIn",
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+ BdsLibUpdateConsoleVariable (L"ConOut",
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+ BdsLibUpdateConsoleVariable (L"ErrOut",
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+
+ //
+ // Connect the consoles based on the above variables.
+ //
+ BdsLibConnectAllDefaultConsoles ();
+
+ //
+ // Show the splash screen.
+ //
+ EnableQuietBoot (PcdGetPtr (PcdLogoFile));
+
+ //
+ // Connect the rest of the devices.
+ //
+ BdsLibConnectAll ();
+
+ //
+ // Add memory test to convert memory above 4GB to be tested
+ //
+ Status = BaseMemoryTest (QUICK);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] - Base memory test failed: %r\n", __FUNCTION__, __LINE__, Status));
+ }
+
+ //
+ // Process QEMU's -kernel command line option. Note that the kernel booted
+ // this way should receive ACPI tables, which is why we connect all devices
+ // first (see above) -- PCI enumeration blocks ACPI table installation, if
+ // there is a PCI host.
+ //
+ //TryRunningQemuKernel ();
+
+ BdsLibEnumerateAllBootOption (BootOptionList);
+
+ // Add Flash Start OS and ESL Start OS boot option
+ (VOID) HwBdsLibRegisterAppBootOption (BootOptionList, &gFlashStartOsAppGuid, L"Flash Start OS");
+ (VOID) HwBdsLibRegisterAppBootOption (BootOptionList, &gEslStartOsAppGuid, L"ESL Start OS");
+
+ // Add EBL as boot option
+ (VOID) HwBdsLibRegisterAppBootOption (BootOptionList, &gEblFileGuid, L"Embedded Boot Loader (EBL)");
+
+ // Remove EFI Misc Device Boot Options
+ BdsDeleteAllInvalidEfiBootOption ();
+
+ //SetBootOrderFromQemu (BootOptionList);
+ //
+ // The BootOrder variable may have changed, reload the in-memory list with
+ // it.
+ //
+ BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");
+
+ //PlatformBdsEnterFrontPage (GetFrontPageTimeoutFromQemu(), TRUE);
+ Print (L"Press Enter to boot OS immediately.\n");
+ Print (L"Press any other key in %d seconds to stop automatical booting...\n", PcdGet16(PcdPlatformBootTimeOut));
+ PlatformBdsEnterFrontPage (PcdGet16(PcdPlatformBootTimeOut), TRUE);
+}
+
+/**
+ Hook point after a boot attempt succeeds. We don't expect a boot option to
+ return, so the UEFI 2.0 specification defines that you will default to an
+ interactive mode and stop processing the BootOrder list in this case. This
+ is also a platform implementation and can be customized by IBV/OEM.
+
+ @param Option Pointer to Boot Option that succeeded to boot.
+
+**/
+VOID
+EFIAPI
+PlatformBdsBootSuccess (
+ IN BDS_COMMON_OPTION *Option
+ )
+{
+}
+
+/**
+ Hook point after a boot attempt fails.
+
+ @param Option Pointer to Boot Option that failed to boot.
+ @param Status Status returned from failed boot.
+ @param ExitData Exit data returned from failed boot.
+ @param ExitDataSize Exit data size returned from failed boot.
+
+**/
+VOID
+EFIAPI
+PlatformBdsBootFail (
+ IN BDS_COMMON_OPTION *Option,
+ IN EFI_STATUS Status,
+ IN CHAR16 *ExitData,
+ IN UINTN ExitDataSize
+ )
+{
+}
+
+/**
+ This function locks platform flash that is not allowed to be updated during normal boot path.
+ The flash layout is platform specific.
+**/
+VOID
+EFIAPI
+PlatformBdsLockNonUpdatableFlash (
+ VOID
+ )
+{
+ return;
+}
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.h b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.h
new file mode 100644
index 0000000..4a91262
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.h
@@ -0,0 +1,61 @@
+/** @file
+ Head file for BDS Platform specific code
+
+ Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmVirtPkg/Library/PlatformIntelBdsLib/
+
+**/
+
+#ifndef _INTEL_BDS_PLATFORM_H_
+#define _INTEL_BDS_PLATFORM_H_
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+
+#include "IntelBdsPlatformCommon.h"
+
+VOID
+PlatformBdsEnterFrontPage (
+ IN UINT16 TimeoutDefault,
+ IN BOOLEAN ConnectAllHappened
+ );
+
+/**
+ Download the kernel, the initial ramdisk, and the kernel command line from
+ QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two
+ image files, and load and start the kernel from it.
+
+ The kernel will be instructed via its command line to load the initrd from
+ the same Simple FileSystem.
+
+ @retval EFI_NOT_FOUND Kernel image was not found.
+ @retval EFI_OUT_OF_RESOURCES Memory allocation failed.
+ @retval EFI_PROTOCOL_ERROR Unterminated kernel command line.
+
+ @return Error codes from any of the underlying
+ functions. On success, the function doesn't
+ return.
+**/
+EFI_STATUS
+EFIAPI
+TryRunningQemuKernel (
+ VOID
+ );
+
+#endif // _INTEL_BDS_PLATFORM_H
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.c b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.c
new file mode 100644
index 0000000..9ea701d
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.c
@@ -0,0 +1,118 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "IntelBdsPlatform.h"
+#include <Library/UefiLib.h>
+#include <Library/GenericBdsLib.h>
+#include <Protocol/FirmwareVolume2.h>
+
+VOID
+EFIAPI
+BdsLibBuildOptionFromApp (
+ IN EFI_HANDLE Handle,
+ IN OUT LIST_ENTRY *BdsBootOptionList,
+ IN GUID *FileGuid,
+ IN CHAR16 *Description
+ )
+{
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH ShellNode;
+
+ DevicePath = DevicePathFromHandle (Handle);
+
+ //
+ // Build the shell device path
+ //
+ EfiInitializeFwVolDevicepathNode (&ShellNode, FileGuid);
+
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *) &ShellNode);
+
+ //
+ // Create and register the shell boot option
+ //
+ BdsLibRegisterNewOption (BdsBootOptionList, DevicePath, Description, L"BootOrder");
+
+}
+EFI_STATUS
+EFIAPI
+HwBdsLibRegisterAppBootOption (
+ IN OUT LIST_ENTRY *BdsBootOptionList,
+ IN GUID *FileGuid,
+ IN CHAR16 *Description
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN FvHandleCount;
+ EFI_HANDLE *FvHandleBuffer;
+ EFI_FV_FILETYPE Type;
+ UINTN Size;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINT32 AuthenticationStatus;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ UINTN Count = 0;
+
+ //
+ // Check if we have on flash shell
+ //
+ gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &FvHandleCount,
+ &FvHandleBuffer
+ );
+ for (Index = 0; Index < FvHandleCount; Index++) {
+ gBS->HandleProtocol (
+ FvHandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &Fv
+ );
+
+ Status = Fv->ReadFile (
+ Fv,
+ FileGuid,
+ NULL,
+ &Size,
+ &Type,
+ &Attributes,
+ &AuthenticationStatus
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Skip if no shell file in the FV
+ //
+ continue;
+ }
+ //
+ // Build the shell boot option
+ //
+ BdsLibBuildOptionFromApp (FvHandleBuffer[Index], BdsBootOptionList,
+ FileGuid, Description);
+
+ Count++;
+ }
+
+ if (FvHandleCount != 0) {
+ FreePool (FvHandleBuffer);
+ }
+
+ if (Count == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.h b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.h
new file mode 100644
index 0000000..73b901a
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.h
@@ -0,0 +1,27 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _HW_BDS_LIB_H_
+#define _HW_BDS_LIB_H_
+
+EFI_STATUS
+EFIAPI
+HwBdsLibRegisterAppBootOption (
+ IN OUT LIST_ENTRY *BdsBootOptionList,
+ IN GUID *FileGuid,
+ IN CHAR16 *Description
+ );
+
+#endif
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
new file mode 100644
index 0000000..236e314
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
@@ -0,0 +1,79 @@
+## @file
+# Implementation for PlatformBdsLib library class interfaces.
+#
+# Copyright (C) 2015, Red Hat, Inc.
+# Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+# Based on the files under ArmVirtPkg/Library/PlatformIntelBdsLib/
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformIntelBdsLib
+ FILE_GUID = 46DF84EB-F603-4D39-99D8-E1E86B50BCC2
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformBdsLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = ARM AARCH64
+#
+
+[Sources]
+ IntelBdsPlatform.c
+ IntelBdsPlatformCommon.c
+
+[Packages]
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DevicePathLib
+ GenericBdsLib
+ MemoryAllocationLib
+ PcdLib
+ PrintLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[FixedPcd]
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+
+[Guids]
+ gEfiFileInfoGuid
+ gEfiFileSystemInfoGuid
+ gEfiFileSystemVolumeLabelInfoIdGuid
+
+[Protocols]
+ gEfiDevicePathProtocolGuid
+ gEfiGraphicsOutputProtocolGuid
+ gEfiLoadedImageProtocolGuid
+ gEfiPciRootBridgeIoProtocolGuid
+ gEfiSimpleFileSystemProtocolGuid
diff --git a/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.c b/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.c
new file mode 100644
index 0000000..0139077
--- /dev/null
+++ b/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.c
@@ -0,0 +1,429 @@
+/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+**/
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/IoLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/EfiTimeBaseLib.h>
+
+#include <Protocol/RealTimeClock.h>
+
+#include <Guid/GlobalVariable.h>
+#include <Guid/EventGroup.h>
+
+#include <Library/ArmArchTimer.h>
+
+STATIC CONST CHAR16 mTimeZoneVariableName[] = L"PV660VirtualRtcTimeZone";
+STATIC CONST CHAR16 mDaylightVariableName[] = L"PV660VirtualRtcDaylight";
+STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
+STATIC EFI_RUNTIME_SERVICES *mRT;
+
+
+STATIC INTN mEpochDiff = 0;
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT64 Temp;
+ UINT32 EpochSeconds;
+ INT16 TimeZone = 0;
+ UINT8 Daylight = 0;
+ UINTN Size;
+
+ // Ensure Time is a valid pointer
+ if (Time == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ArmArchTimerReadReg(CntPct,&Temp);
+
+ // UINT32 force convertion for PC-LINT
+ EpochSeconds = mEpochDiff + Temp / (UINT32) PcdGet32(PcdArmArchTimerFreqInHz);
+
+ // Get the current time zone information from non-volatile storage
+ Size = sizeof (TimeZone);
+ Status = mRT->GetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ NULL,
+ &Size,
+ (VOID *)&TimeZone
+ );
+
+ if (EFI_ERROR (Status)) {
+ ASSERT(Status != EFI_INVALID_PARAMETER);
+ ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+
+ if (Status != EFI_NOT_FOUND)
+ goto EXIT;
+
+ // The time zone variable does not exist in non-volatile storage, so create it.
+ Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+ // Store it
+ Status = mRT->SetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ Size,
+ (VOID *)&(Time->TimeZone)
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ EFI_D_ERROR,
+ "LibGetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+ mTimeZoneVariableName,
+ Status
+ ));
+ goto EXIT;
+ }
+ } else {
+ // Got the time zone
+ Time->TimeZone = TimeZone;
+
+ // Check TimeZone bounds: -1440 to 1440 or 2047
+ if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440))
+ && (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE)) {
+ Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+ }
+
+ // Adjust for the correct time zone
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
+ EpochSeconds += Time->TimeZone * SEC_PER_MIN;
+ }
+ }
+
+ // Get the current daylight information from non-volatile storage
+ Size = sizeof (Daylight);
+ Status = mRT->GetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ NULL,
+ &Size,
+ (VOID *)&Daylight
+ );
+
+ if (EFI_ERROR (Status)) {
+ ASSERT(Status != EFI_INVALID_PARAMETER);
+ ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+
+ if (Status != EFI_NOT_FOUND)
+ goto EXIT;
+
+ // The daylight variable does not exist in non-volatile storage, so create it.
+ Time->Daylight = 0;
+ // Store it
+ Status = mRT->SetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ Size,
+ (VOID *)&(Time->Daylight)
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ EFI_D_ERROR,
+ "LibGetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+ mDaylightVariableName,
+ Status
+ ));
+ goto EXIT;
+ }
+ } else {
+ // Got the daylight information
+ Time->Daylight = Daylight;
+
+ // Adjust for the correct period
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {
+ // Convert to adjusted time, i.e. spring forwards one hour
+ EpochSeconds += SEC_PER_HOUR;
+ }
+ }
+
+ // Convert from internal 32-bit time to UEFI time
+ EpochToEfiTime (EpochSeconds, Time);
+
+ // Update the Capabilities info
+ if (Capabilities != NULL) {
+ Capabilities->Resolution = 1;
+ // Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000
+
+ Capabilities->Accuracy = PcdGet32 (PcdArmArchTimerFreqInHz);
+ // FALSE: Setting the time does not clear the values below the resolution level
+ Capabilities->SetsToZero = FALSE;
+ }
+
+ EXIT:
+ return Status;
+}
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ EFI_STATUS Status;
+ UINTN EpochSeconds;
+ UINTN Temp;
+
+ // Check the input parameters are within the range specified by UEFI
+ if (!IsTimeValid (Time)) {
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+
+ // Because the PL031 is a 32-bit counter counting seconds,
+ // the maximum time span is just over 136 years.
+ // Time is stored in Unix Epoch format, so it starts in 1970,
+ // Therefore it can not exceed the year 2106.
+ if ((Time->Year < 1970) || (Time->Year >= 2106)) {
+ Status = EFI_UNSUPPORTED;
+ goto EXIT;
+ }
+
+ EpochSeconds = EfiTimeToEpoch (Time);
+
+ // Adjust for the correct time zone, i.e. convert to UTC time zone
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
+ EpochSeconds -= Time->TimeZone * SEC_PER_MIN;
+ }
+
+ // TODO: Automatic Daylight activation
+
+ // Adjust for the correct period
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {
+ // Convert to un-adjusted time, i.e. fall back one hour
+ EpochSeconds -= SEC_PER_HOUR;
+ }
+
+ ArmArchTimerReadReg(CntPct,&Temp);
+
+ // UINT32 force convertion for PC-LINT
+ mEpochDiff = EpochSeconds - Temp / (UINT32) PcdGet32(PcdArmArchTimerFreqInHz);
+
+ // The accesses to Variable Services can be very slow, because we may be writing to Flash.
+ // Do this after having set the RTC.
+
+ // Save the current time zone information into non-volatile storage
+ Status = mRT->SetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof (Time->TimeZone),
+ (VOID *)&(Time->TimeZone)
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ EFI_D_ERROR,
+ "LibSetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+ mTimeZoneVariableName,
+ Status
+ ));
+ goto EXIT;
+ }
+
+ // Save the current daylight information into non-volatile storage
+ Status = mRT->SetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof(Time->Daylight),
+ (VOID *)&(Time->Daylight)
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ EFI_D_ERROR,
+ "LibSetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+ mDaylightVariableName,
+ Status
+ ));
+ goto EXIT;
+ }
+
+ EXIT:
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ //
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+ // to virtual address. After the OS transitions to calling in virtual mode, all future
+ // runtime calls will be made in virtual mode.
+ //
+ EfiConvertPointer (0x0, (VOID**)&mRT);
+ return;
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ // Setup the setters and getters
+ gRT->GetTime = LibGetTime;
+ gRT->SetTime = LibSetTime;
+ gRT->GetWakeupTime = LibGetWakeupTime;
+ gRT->SetWakeupTime = LibSetWakeupTime;
+
+ mRT = gRT;
+
+ // Install the protocol
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiRealTimeClockArchProtocolGuid, NULL,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ LibRtcVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mRtcVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.inf b/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.inf
new file mode 100644
index 0000000..84528bd
--- /dev/null
+++ b/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.inf
@@ -0,0 +1,47 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RealTimeClockLibVirtual
+ FILE_GUID = 432B35C1-A0CC-4720-A4B9-1EFD70050107
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ RealTimeClockLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ OpenPlatformPkg/OpenPlatformPkg.dec
+
+[LibraryClasses]
+ IoLib
+ UefiLib
+ DebugLib
+ PcdLib
+ DxeServicesTableLib
+ UefiRuntimeLib
+ ArmLib
+ EfiTimeBaseLib
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
diff --git a/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.c b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.c
new file mode 100644
index 0000000..49e330b
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.c
@@ -0,0 +1,94 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/SerdesLib.h>
+
+#include "Smmu.h"
+
+SMMU_DEVICE mSpecialSmmu[] = {
+ {FixedPcdGet64 (PcdM3SmmuBaseAddress), 0},
+ {FixedPcdGet64 (PcdPcieSmmuBaseAddress), 0},
+};
+
+VOID
+SpecialSmmuConfig (VOID)
+{
+ UINTN Index;
+
+ for (Index = 0; Index < sizeof (mSpecialSmmu) / sizeof (mSpecialSmmu[0]); Index++) {
+ (VOID) SmmuConfigSwitch (&mSpecialSmmu[Index]);
+ }
+}
+
+VOID
+SpecialSmmuEnable (VOID)
+{
+ UINTN Index;
+
+ for (Index = 0; Index < sizeof (mSpecialSmmu) / sizeof (mSpecialSmmu[0]); Index++) {
+ (VOID) SmmuEnableTable (&mSpecialSmmu[Index]);
+ }
+}
+
+VOID
+EFIAPI
+ExitBootServicesEventSmmu (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ SmmuConfigForOS ();
+ SpecialSmmuEnable ();
+ DEBUG((EFI_D_ERROR,"SMMU ExitBootServicesEvent\n"));
+}
+
+
+EFI_STATUS
+EFIAPI
+IoInitDxeEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable)
+{
+ EFI_STATUS Status;
+ EFI_EVENT Event = NULL;
+
+ (VOID) EfiSerdesInitWrap ();
+
+ SmmuConfigForBios ();
+
+ SpecialSmmuConfig ();
+
+ Status = gBS->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,
+ TPL_CALLBACK,
+ ExitBootServicesEventSmmu,
+ NULL,
+ &Event
+ );
+
+ if (EFI_ERROR(Status))
+ {
+ DEBUG ((EFI_D_ERROR, "[%a:%d] - CreateEvent failed: %r\n", __FUNCTION__,
+ __LINE__, Status));
+ }
+
+ return Status;
+}
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf
new file mode 100644
index 0000000..6e19068
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf
@@ -0,0 +1,57 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IoInitDxe
+ FILE_GUID = e99c606a-5626-11e5-b09e-bb93f4e4c400
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = IoInitDxeEntry
+
+[Sources.common]
+ IoInitDxe.c
+ Smmu.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ DebugLib
+ BaseLib
+ PcdLib
+ CacheMaintenanceLib
+ SerdesLib
+ PlatformSysCtrlLib
+
+[Guids]
+
+[Protocols]
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+ gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+ gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+
+[Depex]
+ TRUE
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.c b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.c
new file mode 100644
index 0000000..5ccb7d1
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.c
@@ -0,0 +1,442 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ArmLib.h>
+
+#include "Smmu.h"
+
+/* Maximum number of context banks per SMMU */
+#define SMMU_MAX_CBS 256
+
+#ifdef CONFIG_MM_OUTER_SHAREABLE
+#define SH_DOMAIN 2 /* outer shareable */
+#else
+#define SH_DOMAIN 3 /* inner shareable */
+#endif
+
+#define SMMU_OS_VMID 0
+#define SMMU_CB_NUMIRPT 8
+#define SMMU_S1CBT_SIZE 0x10000
+#define SMMU_S2CBT_SIZE 0x2000
+#define SMMU_S1CBT_SHIFT 16
+#define SMMU_S2CBT_SHIFT 12
+
+
+#define SMMU_CTRL_CR0 0x0
+#define SMMU_CTRL_ACR 0x8
+#define SMMU_CFG_S2CTBAR 0xc
+#define SMMU_IDR0 0x10
+#define SMMU_IDR1 0x14
+#define SMMU_IDR2 0x18
+#define SMMU_HIS_GFAR_LOW 0x20
+#define SMMU_HIS_GFAR_HIGH 0x24
+#define SMMU_RINT_GFSR 0x28
+#define SMMU_RINT_GFSYNR 0x2c
+#define SMMU_CFG_GFIM 0x30
+#define SMMU_CFG_CBF 0x34
+#define SMMU_TLBIALL 0x40
+#define SMMU_TLBIVMID 0x44
+#define SMMU_TLBISID 0x48
+#define SMMU_TLBIVA_LOW 0x4c
+#define SMMU_TLBIVA_HIGH 0x50
+#define SMMU_TLBGSYNC 0x54
+#define SMMU_TLBGSTATUS 0x58
+#define SMMU_CXTIALL 0x60
+#define SMMU_CXTIVMID 0x64
+#define SMMU_CXTISID 0x68
+#define SMMU_CXTGSYNC 0x6c
+#define SMMU_CXTGSTATUS 0x70
+#define SMMU_RINT_CB_FSR(n) (0x100 + ((n) << 2))
+#define SMMU_RINT_CB_FSYNR(n) (0x120 + ((n) << 2))
+#define SMMU_HIS_CB_FAR_LOW(n) (0x140 + ((n) << 3))
+#define SMMU_HIS_CB_FAR_HIGH(n) (0x144 + ((n) << 3))
+#define SMMU_CTRL_CB_RESUME(n) (0x180 + ((n) << 2))
+#define SMMU_RINT_CB_FSYNR_MSTID 0x1a0
+
+#define SMMU_CB_S2CR(n) (0x0 + ((n) << 5))
+#define SMMU_CB_CBAR(n) (0x4 + ((n) << 5))
+#define SMMU_CB_S1CTBAR(n) (0x18 + ((n) << 5))
+
+#define SMMU_S1_MAIR0 0x0
+#define SMMU_S1_MAIR1 0x4
+#define SMMU_S1_TTBR0_L 0x8
+#define SMMU_S1_TTBR0_H 0xc
+#define SMMU_S1_TTBR1_L 0x10
+#define SMMU_S1_TTBR1_H 0x14
+#define SMMU_S1_TTBCR 0x18
+#define SMMU_S1_SCTLR 0x1c
+
+#define CFG_CBF_S1_ORGN_WA (1 << 12)
+#define CFG_CBF_S1_IRGN_WA (1 << 10)
+#define CFG_CBF_S1_SHCFG (SH_DOMAIN << 8)
+#define CFG_CBF_S2_ORGN_WA (1 << 4)
+#define CFG_CBF_S2_IRGN_WA (1 << 2)
+#define CFG_CBF_S2_SHCFG (SH_DOMAIN << 0)
+
+/* Configuration registers */
+#define sCR0_CLIENTPD (1 << 0)
+#define sCR0_GFRE (1 << 1)
+#define sCR0_GFIE (1 << 2)
+#define sCR0_GCFGFRE (1 << 4)
+#define sCR0_GCFGFIE (1 << 5)
+
+#define sACR_WC_EN (7 << 0)
+
+#define ID0_S1TS (1 << 30)
+#define ID0_S2TS (1 << 29)
+#define ID0_NTS (1 << 28)
+#define ID0_PTFS_SHIFT 24
+#define ID0_PTFS_MASK 0x2
+#define ID0_PTFS_V8_ONLY 0x2
+#define ID0_CTTW (1 << 14)
+
+#define ID2_OAS_SHIFT 8
+#define ID2_OAS_MASK 0xff
+#define ID2_IAS_SHIFT 0
+#define ID2_IAS_MASK 0xff
+
+#define S2CR_TYPE_SHIFT 16
+#define S2CR_TYPE_MASK 0x3
+#define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
+#define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
+#define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
+#define S2CR_SHCFG_NS (3 << 8)
+#define S2CR_MTCFG (1 << 11)
+#define S2CR_MEMATTR_OIWB (0xf << 12)
+#define S2CR_MTSH_WEAKEST (S2CR_SHCFG_NS | \
+ S2CR_MTCFG | S2CR_MEMATTR_OIWB)
+
+/* Context bank attribute registers */
+#define CBAR_VMID_SHIFT 0
+#define CBAR_VMID_MASK 0xff
+#define CBAR_S1_BPSHCFG_SHIFT 8
+#define CBAR_S1_BPSHCFG_MASK 3
+#define CBAR_S1_BPSHCFG_NSH 3
+#define CBAR_S1_MEMATTR_SHIFT 12
+#define CBAR_S1_MEMATTR_MASK 0xf
+#define CBAR_S1_MEMATTR_WB 0xf
+#define CBAR_TYPE_SHIFT 16
+#define CBAR_TYPE_MASK 0x3
+#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
+#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
+#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
+#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
+#define CBAR_IRPTNDX_SHIFT 24
+#define CBAR_IRPTNDX_MASK 0xff
+
+#define SMMU_CB_BASE(smmu) ((smmu)->s1cbt)
+#define SMMU_CB(n) ((n) << 5)
+
+#define sTLBGSTATUS_GSACTIVE (1 << 0)
+#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
+
+#define SCTLR_WACFG_WA (2 << 26)
+#define SCTLR_RACFG_RA (2 << 24)
+#ifdef CONFIG_P660_2P
+#define SCTLR_SHCFG (1 << 22)
+#else
+#define SCTLR_SHCFG (2 << 22)
+#endif
+#define SCTLR_MTCFG (1 << 20)
+#define SCTLR_MEMATTR_WB (0xf << 16)
+#define SCTLR_MEMATTR_NC (0x5 << 16)
+#define SCTLR_MEMATTR_NGNRE (0x1 << 16)
+#define SCTLR_CACHE_WBRAWA (SCTLR_WACFG_WA | SCTLR_RACFG_RA | \
+ SCTLR_SHCFG | SCTLR_MTCFG | SCTLR_MEMATTR_WB)
+#define SCTLR_CACHE_NC (SCTLR_SHCFG | \
+ SCTLR_MTCFG | SCTLR_MEMATTR_NC)
+#define SCTLR_CACHE_NGNRE (SCTLR_SHCFG | \
+ SCTLR_MTCFG | SCTLR_MEMATTR_NGNRE)
+
+#define SCTLR_CFCFG (1 << 7)
+#define SCTLR_CFIE (1 << 6)
+#define SCTLR_CFRE (1 << 5)
+#define SCTLR_E (1 << 4)
+#define SCTLR_AFED (1 << 3)
+#define SCTLR_M (1 << 0)
+#define SCTLR_EAE_SBOP (SCTLR_AFED)
+
+#define RESUME_RETRY (0 << 0)
+#define RESUME_TERMINATE (1 << 0)
+
+#define TTBCR_TG0_4K (0 << 14)
+#define TTBCR_TG0_64K (3 << 14)
+
+#define TTBCR_SH0_SHIFT 12
+#define TTBCR_SH0_MASK 0x3
+#define TTBCR_SH_NS 0
+#define TTBCR_SH_OS 2
+#define TTBCR_SH_IS 3
+#define TTBCR_ORGN0_SHIFT 10
+#define TTBCR_IRGN0_SHIFT 8
+#define TTBCR_RGN_MASK 0x3
+#define TTBCR_RGN_NC 0
+#define TTBCR_RGN_WBWA 1
+#define TTBCR_RGN_WT 2
+#define TTBCR_RGN_WB 3
+#define TTBCR_T1SZ_SHIFT 16
+#define TTBCR_T0SZ_SHIFT 0
+#define TTBCR_SZ_MASK 0xf
+
+#define MAIR_ATTR_SHIFT(n) ((n) << 3)
+#define MAIR_ATTR_MASK 0xff
+#define MAIR_ATTR_DEVICE 0x04
+#define MAIR_ATTR_NC 0x44
+#define MAIR_ATTR_WBRWA 0xff
+#define MAIR_ATTR_IDX_NC 0
+#define MAIR_ATTR_IDX_CACHE 1
+#define MAIR_ATTR_IDX_DEV 2
+
+#define FSR_MULTI (1 << 31)
+#define FSR_EF (1 << 4)
+#define FSR_PF (1 << 3)
+#define FSR_AFF (1 << 2)
+#define FSR_TF (1 << 1)
+#define FSR_IGN (FSR_AFF)
+#define FSR_FAULT (FSR_MULTI | FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
+
+#define FSYNR0_ASID(n) (0xff & ((n) >> 24))
+#define FSYNR0_VMID(n) (0xff & ((n) >> 16))
+#define FSYNR0_WNR (1 << 4)
+#define FSYNR0_SS (1 << 2)
+#define FSYNR0_CF (1 << 0)
+
+#define SMMU_FEAT_COHERENT_WALK (1 << 0)
+#define SMMU_FEAT_STREAM_MATCH (1 << 1)
+#define SMMU_FEAT_TRANS_S1 (1 << 2)
+#define SMMU_FEAT_TRANS_S2 (1 << 3)
+#define SMMU_FEAT_TRANS_NESTED (1 << 4)
+
+static UINT32 hisi_bypass_vmid = 0xff;
+
+VOID writel_relaxed (UINT32 Value, UINTN Base)
+{
+ MmioWrite32 (Base, Value);
+}
+
+UINT32 readl_relaxed (UINTN Base)
+{
+ return MmioRead32 (Base);
+}
+
+/* Wait for any pending TLB invalidations to complete */
+static void hisi_smmu_tlb_sync(SMMU_DEVICE *smmu)
+{
+ int count = 0;
+ UINTN gr0_base = smmu->Base;
+
+ writel_relaxed(0, gr0_base + SMMU_TLBGSYNC);
+ while (readl_relaxed(gr0_base + SMMU_TLBGSTATUS)
+ & sTLBGSTATUS_GSACTIVE) {
+ if (++count == TLB_LOOP_TIMEOUT) {
+ DEBUG ((EFI_D_ERROR, "TLB sync timed out -- SMMU (0x%p) may be deadlocked\n", gr0_base));
+ return;
+ }
+ MicroSecondDelay (1);
+ }
+}
+
+
+VOID *
+SmmuAllocateTable (
+ UINTN Size,
+ UINTN Alignment
+ )
+{
+ return AllocateAlignedReservedPages (EFI_SIZE_TO_PAGES (Size), Alignment);
+}
+
+
+EFI_STATUS
+SmmuInit (
+ SMMU_DEVICE *Smmu
+ )
+{
+ UINT32 Value;
+ UINTN Base = Smmu->Base;
+ UINTN Index;
+
+ /* Clear Global FSR */
+ Value = MmioRead32 (Base + SMMU_RINT_GFSR);
+ MmioWrite32 (Base + SMMU_RINT_GFSR, Value);
+
+ /* mask all global interrupt */
+ MmioWrite32 (Base + SMMU_CFG_GFIM, 0xFFFFFFFF);
+
+ Value = CFG_CBF_S1_ORGN_WA | CFG_CBF_S1_IRGN_WA | CFG_CBF_S1_SHCFG;
+ Value |= CFG_CBF_S2_ORGN_WA | CFG_CBF_S2_IRGN_WA | CFG_CBF_S2_SHCFG;
+ MmioWrite32 (Base + SMMU_CFG_CBF, Value);
+
+ /* Clear CB_FSR */
+ for (Index = 0; Index < SMMU_CB_NUMIRPT; Index++) {
+ MmioWrite32 (Base + SMMU_RINT_CB_FSR(Index), FSR_FAULT);
+ }
+
+ return EFI_SUCCESS;
+}
+
+VOID *
+SmmuCreateS2Cbt (VOID)
+{
+ VOID *Table;
+ UINTN Index;
+
+ Table = SmmuAllocateTable (SMMU_S2CBT_SIZE, LShiftU64 (1, SMMU_S2CBT_SHIFT));
+ if (Table == NULL) {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Allocate table failed!\n", __FUNCTION__, __LINE__));
+ return NULL;
+ }
+ ZeroMem (Table, SMMU_S2CBT_SIZE);
+
+ for (Index = 0; Index < SMMU_MAX_CBS; Index++) {
+ MmioWrite32 ((UINTN)Table + SMMU_CB_S1CTBAR(Index), 0);
+ MmioWrite32 ((UINTN)Table + SMMU_CB_S2CR(Index), S2CR_TYPE_BYPASS);
+ }
+ return Table;
+}
+
+VOID *
+SmmuCreateS1Cbt (VOID)
+{
+ VOID *Table;
+
+ Table = SmmuAllocateTable (SMMU_S1CBT_SIZE, LShiftU64 (1, SMMU_S1CBT_SHIFT));
+ if (Table == NULL) {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Allocate table failed!\n", __FUNCTION__, __LINE__));
+ return NULL;
+ }
+ ZeroMem (Table, SMMU_S1CBT_SIZE);
+
+ return Table;
+}
+
+EFI_STATUS
+SmmuConfigSwitch (
+ SMMU_DEVICE *Smmu
+ )
+{
+ VOID* S2;
+ VOID* S1;
+ UINT32 reg;
+
+ S2 = SmmuCreateS2Cbt ();
+ if (S2 == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ Smmu->S2Cbt = (UINTN) S2;
+
+ S1 = SmmuCreateS1Cbt ();
+ if (S1 == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S1CTBAR(SMMU_OS_VMID), (UINT32) RShiftU64 ((UINT64)S1, SMMU_S1CBT_SHIFT));
+
+ // Force device for VMID 0 ASID 0
+ MmioWrite32 ((UINTN)S1 + SMMU_CB(0) + SMMU_S1_SCTLR, SCTLR_CACHE_WBRAWA);
+ // Force device for VMID 0 ASID 1
+ MmioWrite32 ((UINTN)S1 + SMMU_CB(1) + SMMU_S1_SCTLR, SCTLR_CACHE_NGNRE);
+
+ /*
+ * Use the weakest attribute, so no impact stage 1 output attribute.
+ */
+ reg = CBAR_TYPE_S1_TRANS_S2_BYPASS |
+ (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
+ (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
+ MmioWrite32 (Smmu->S2Cbt + SMMU_CB_CBAR(SMMU_OS_VMID), reg);
+
+ /* Mark S2CR as translation */
+ reg = S2CR_TYPE_TRANS | S2CR_MTSH_WEAKEST;
+ MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S2CR(SMMU_OS_VMID), reg);
+
+ /* Bypass need use another S2CR */
+ reg = S2CR_TYPE_BYPASS;
+ MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S2CR(hisi_bypass_vmid), reg);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SmmuFlushCbt (
+ SMMU_DEVICE *Smmu
+ )
+{
+ UINTN Index;
+
+ if (Smmu->S2Cbt == 0) {
+ DEBUG ((EFI_D_ERROR, "[%a]:[%dL] S2Cbt is null!\n", __FUNCTION__, __LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ WriteBackInvalidateDataCacheRange ((VOID *)Smmu->S2Cbt, SMMU_S2CBT_SIZE);
+ for (Index = 0; Index < SMMU_MAX_CBS; Index++) {
+ UINTN S1Ctb = MmioRead32 (Smmu->S2Cbt + SMMU_CB_S1CTBAR(SMMU_OS_VMID));
+ if (S1Ctb) {
+ // TODO: shall we really need to flush 64KB? Or 8KB is enough?
+ WriteBackInvalidateDataCacheRange ((VOID *)LShiftU64 (S1Ctb, SMMU_S1CBT_SHIFT), SMMU_S1CBT_SIZE);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SmmuEnableTable (
+ SMMU_DEVICE *Smmu
+ )
+{
+ UINT32 reg;
+ UINTN gr0_base = Smmu->Base;
+
+ (VOID) SmmuFlushCbt (Smmu);
+
+ /* Clear Global FSR */
+ reg = readl_relaxed(gr0_base + SMMU_RINT_GFSR);
+ writel_relaxed(reg, gr0_base + SMMU_RINT_GFSR);
+
+ /* unmask all global interrupt */
+ writel_relaxed(0, gr0_base + SMMU_CFG_GFIM);
+
+ reg = CFG_CBF_S1_ORGN_WA | CFG_CBF_S1_IRGN_WA | CFG_CBF_S1_SHCFG;
+ reg |= CFG_CBF_S2_ORGN_WA | CFG_CBF_S2_IRGN_WA | CFG_CBF_S2_SHCFG;
+ writel_relaxed(reg, gr0_base + SMMU_CFG_CBF);
+
+ reg = (UINT32) RShiftU64 (Smmu->S2Cbt, SMMU_S2CBT_SHIFT);
+ writel_relaxed(reg, gr0_base + SMMU_CFG_S2CTBAR);
+
+ /* Invalidate all TLB, just in case */
+ writel_relaxed(0, gr0_base + SMMU_TLBIALL);
+ hisi_smmu_tlb_sync(Smmu);
+
+ writel_relaxed(sACR_WC_EN, gr0_base + SMMU_CTRL_ACR);
+
+ /* Enable fault reporting */
+ reg = (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
+ reg &= ~sCR0_CLIENTPD;
+
+ writel_relaxed(reg, gr0_base + SMMU_CTRL_CR0);
+ ArmDataSynchronizationBarrier ();
+
+ return EFI_SUCCESS;
+};
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.h b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.h
new file mode 100644
index 0000000..16e7305
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.h
@@ -0,0 +1,36 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _SMMU_H_
+#define _SMMU_H_
+
+typedef struct {
+ UINTN Base;
+ UINTN S2Cbt;
+} SMMU_DEVICE;
+
+EFI_STATUS
+SmmuConfigSwitch (
+ SMMU_DEVICE *Smmu
+ );
+
+EFI_STATUS
+SmmuEnableTable (
+ SMMU_DEVICE *Smmu
+ );
+
+
+#endif
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c
new file mode 100644
index 0000000..88ad718
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c
@@ -0,0 +1,103 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include "PcieInit.h"
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+
+extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
+extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
+extern EFI_STATUS PciePortInit (UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
+
+PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] =
+{
+ //Port 0
+ {
+ 0x0, //Portindex
+
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ }, //PortInfo
+
+ },
+
+ //Port 1
+ {
+ 0x1, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+
+ //Port 2
+ {
+ 0x2, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+
+ //Port 3
+ {
+ 0x3, //Portindex
+ {
+ PCIE_ROOT_COMPLEX, //PortType
+ PCIE_WITDH_X8, //PortWidth
+ PCIE_GEN3_0, //PortGen
+ },
+
+ },
+};
+
+EFI_STATUS
+PcieInitEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+
+{
+ UINT32 Port;
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 HostBridgeNum = 0;
+
+ for (HostBridgeNum = 0; HostBridgeNum < PCIE_HOST_BRIDGE_NUM; HostBridgeNum++)
+ {
+ for (Port = 0; Port < PCIE_MAX_PORT_NUM; Port++)
+ {
+ if (!((((PcdGet32(PcdPcieRootBridgeMask) >> (4 * HostBridgeNum))) >> Port) & 0x1))
+ {
+ continue;
+ }
+
+ Status = PciePortInit(HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
+ }
+
+ }
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h
new file mode 100644
index 0000000..d837416
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h
@@ -0,0 +1,93 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_H__
+#define __PCIE_INIT_H__
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+
+extern EFI_GUID gEfiPcieRootBridgeProtocolGuid;
+
+#define PCIE_LOG_ID 1
+
+#define PCIE_CONFIG_SPACE_SIZE 0x1000 //4k
+#define PCIE_MEMORY_SPACE_SIZE 0x800000 //8M
+#define PCIE_IO_SPACE_SIZE 0x800000 //8M
+#define PCIE_TYPE1_MEM_SIZE (PCIE_MEMORY_SPACE_SIZE + PCIE_IO_SPACE_SIZE)
+
+#define CONFIG_SPACE_BASE_ADDR_LOW 0xe2000000
+#define CONFIG_SPACE_BASE_ADDR_HIGH 0x0
+#define CONFIG_SPACE_ADDR_LIMIT (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_MEM_BASE_ADDR_LOW (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE)
+#define PCIE_MEM_BASE_ADDR_HIGH 0x0
+#define PCIE_MEM_ADDR_LIMIT (PCIE_MEM_BASE_ADDR_LOW + PCIE_MEMORY_SPACE_SIZE - PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_IO_BASE_ADDR_LOW (PCIE_MEM_ADDR_LIMIT - 1)
+#define PCIE_IO_BASE_ADDR_HIGH 0x0
+#define PCIE_IO_ADDR_LIMIT (PCIE_IO_BASE_ADDR_LOW + PCIE_IO_SPACE_SIZE - 1)
+
+#define PCIE_INBOUND_BASE 0xD0000000
+
+
+#define PCIE_ALL_DMA_BASE (0x100000000)
+#define PCIE0_ALL_DMA_BASE (PCIE_ALL_DMA_BASE)
+#define PCIE0_ALL_DMA_SIZE (0x8000000)
+#define PCIE0_ALL_BAR01_BASE (0x10000000)
+#define PCIE0_ALL_BAR23_BASE (PCIE0_ALL_BAR01_BASE + PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE01_BASE 0x2c0000000 //(HRD_ATTR_TRAN_ADDR_BASE_HOST_ADDR)
+#define PCIE0_ALL_TRANSLATE01_SIZE (PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE23_BASE (PCIE0_ALL_TRANSLATE01_BASE + PCIE0_ALL_TRANSLATE01_SIZE)
+#define PCIE0_ALL_TRANSLATE23_SIZE (PCIE0_ALL_DMA_SIZE)
+
+
+#define PCIE0_REG_BASE (0xb0070000)
+#define PCIE1_REG_BASE (0xb0080000)
+#define PCIE2_REG_BASE (0xb0090000)
+#define PCIE3_REG_BASE (0xb00a0000)
+
+#define PCIE_BASE_BAR (0xf0000000)
+#define PCIE_BAR_SIZE (0x1000000)
+
+
+#define PCIE_AXI_SIZE (0x1000000)
+#define PCIE0_AXI_BASE (0xb3000000)
+#define PCIE1_AXI_BASE (PCIE0_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE2_AXI_BASE (PCIE1_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE3_AXI_BASE (PCIE2_AXI_BASE + PCIE_AXI_SIZE)
+
+//#define PCIE_CONFIG_SPACE_SIZE (0x1000)
+#define PCIE0_CONFIG_BASE (PCIE1_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE1_CONFIG_BASE (PCIE2_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE2_CONFIG_BASE (PCIE3_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE3_CONFIG_BASE (PCIE3_AXI_BASE + PCIE_AXI_SIZE - PCIE_CONFIG_SPACE_SIZE)
+
+
+#define PCIE0_TRANSLATE_BASE (0x30000000)
+#define PCIE1_TRANSLATE_BASE (PCIE0_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE2_TRANSLATE_BASE (PCIE1_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE3_TRANSLATE_BASE (PCIE2_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+
+#define PCIE0_BAR_BASE (PCIE0_AXI_BASE)
+#define PCIE1_BAR_BASE (PCIE1_AXI_BASE)
+#define PCIE2_BAR_BASE (PCIE2_AXI_BASE)
+#define PCIE3_BAR_BASE (PCIE3_AXI_BASE)
+
+
+#endif
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf
new file mode 100644
index 0000000..4bbb54f
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf
@@ -0,0 +1,56 @@
+#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PcieInitDxe
+ FILE_GUID = 2D53A704-A544-4A82-83DF-FFECF4B4AA97
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PcieInitEntry
+
+[Sources]
+ PcieInit.c
+ PcieInitLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiLib
+ BaseLib
+ DebugLib
+ ArmLib
+ TimerLib
+ PcdLib
+ IoLib
+
+[Protocols]
+
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
+
+[depex]
+ TRUE
+
+
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c
new file mode 100644
index 0000000..3581b41
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c
@@ -0,0 +1,1048 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+
+static PCIE_INIT_CFG mPcieIntCfg;
+UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000};
+UINT64 pcie_serders_base[2][4] = {{0xB2080000,0xB2000000,0xB2100000,0xB2200000},{BASE_4TB + 0xB2080000,BASE_4TB + 0xB2000000,BASE_4TB + 0xB2100000,BASE_4TB + 0xB2200000}};
+UINT64 io_sub0_base = 0xa0000000;
+UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000};
+#define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000))
+UINT32 loop_test_flag[4] = {0,0,0,0};
+UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR;
+#define PCIE_GEN1 0 /* PCIE 1.0 */
+#define PCIE_GEN2 1 /* PCIE 2.0 */
+#define PCIE_GEN3 2 /* PCIE 3.0 */
+#define DS_API(lane) ((0x1FF6c + 8*(15-lane))*2)
+
+extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg;
+extern PCIE_IATU gastr_pcie_iatu_cfg;
+extern PCIE_IATU_VA mPcieIatuTable;
+
+VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value)
+{
+ RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+
+}
+
+UINT32 PcieRegRead(UINT32 Port, UINTN Offset)
+{
+ UINT32 Value = 0;
+
+ RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+ return Value;
+}
+
+VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
+{
+ RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+}
+
+UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
+{
+ UINT32 Value = 0;
+ RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+ return Value;
+}
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode)
+{
+ u_sc_pcie0_clkreq pcie0;
+ u_sc_pcie1_clkreq pcie1;
+ u_sc_pcie2_clkreq pcie2;
+ u_sc_pcie3_clkreq pcie3;
+
+ switch(Port)
+ {
+ case 0:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+ pcie0.Bits.pcie0_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+ break;
+ case 1:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+ pcie1.Bits.pcie1_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+ break;
+ case 2:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+ pcie2.Bits.pcie2_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+ break;
+ case 3:
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+ pcie3.Bits.pcie3_apb_cfg_sel = Mode;
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+ break;
+ default:
+ break;
+ }
+}
+
+
+
+EFI_STATUS PcieEnableItssm(UINT32 HostBridgeNum, UINT32 Port)
+{
+ PCIE_CTRL_7_U pcie_ctrl7;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(mPcieIntCfg.PortIsInitilized[Port])
+ {
+ return PCIE_ERR_ALREADY_INIT;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+ pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1;
+ PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieDisableItssm(UINT32 HostBridgeNum, UINT32 Port)
+{
+ PCIE_CTRL_7_U pcie_ctrl7;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return PCIE_ERR_PARAM_INVALID;
+ }
+
+
+ if(mPcieIntCfg.PortIsInitilized[Port])
+ {
+ return PCIE_ERR_ALREADY_INIT;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+ pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0;
+ PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed)
+{
+ PCIE_EP_PCIE_CAP12_U pcie_cap12;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG);
+ pcie_cap12.Bits.targetlinkspeed = Speed;
+ PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+
+ if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+ mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+ {
+ pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG);
+ pcie_cap12.Bits.targetlinkspeed = Speed;
+ PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+ PCIE_EP_PORT_LOGIC4_U pcie_logic4;
+ PCIE_EP_PORT_LOGIC22_U logic22;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return PCIE_ERR_PARAM_INVALID;
+ }
+
+ pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+ pcie_logic4.Bits.linkmodeenable = Width;
+ pcie_logic4.Bits.crosslinkenable = 0;
+ pcie_logic4.Bits.fastlinkmode = 1;
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+ logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.Bits.n_fts = 0xff;
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else
+ {
+ logic22.Bits.pre_determ_num_of_lane = 3;
+ }
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+ if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+ mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+ {
+ pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG);
+ pcie_logic4.Bits.linkmodeenable = Width;
+ pcie_logic4.Bits.crosslinkenable = 0;
+ pcie_logic4.Bits.fastlinkmode = 1;
+ PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+ logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.Bits.n_fts = 0xff;
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else
+ {
+ logic22.Bits.pre_determ_num_of_lane = 3;
+ }
+ PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+ PCIE_EP_PORT_LOGIC22_U logic22;
+ PCIE_EEP_PCI_CFG_HDR15_U hdr15;
+ UINT32 Value = 0;
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+ Value &= ~(0x3f<<16);
+
+ if(Width == PCIE_WITDH_X1)
+ {
+ Value |= (0x1 << 16);
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ Value |= (0x3 << 16);
+ }
+ else if(Width == PCIE_WITDH_X4)
+ {
+ Value |= (0x7 << 16);
+ }
+ else if(Width == PCIE_WITDH_X8)
+ {
+ Value |= (0xf << 16);
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR,"Width is not invalid\n"));
+ }
+
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value);
+
+ logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+ logic22.UInt32 &= ~(0x1f<<8);
+
+ if(Width == PCIE_WITDH_X1)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 1;
+ }
+ else if(Width == PCIE_WITDH_X2)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 2;
+ }
+ else if(Width == PCIE_WITDH_X4)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 4;
+ }
+ else if(Width == PCIE_WITDH_X8)
+ {
+ logic22.Bits.pre_determ_num_of_lane = 8;
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR,"Width is not invalid\n"));
+ }
+
+ PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+ /* setup RC BARs */
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004);
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000);
+
+ /* setup interrupt pins */
+ hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG);
+ hdr15.UInt32 &= 0xffff00ff;
+ hdr15.UInt32 |= 0x00000100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32);
+
+ /* setup bus numbers */
+ Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG);
+ Value &= 0xff000000;
+ Value |= 0x00010100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value);
+
+ /* setup command register */
+ Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG);
+ Value &= 0xffff0000;
+ Value |= 0x1|0x2|0x4|0x100;
+ PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value);
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS PcieModeSet(UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType)
+{
+ PCIE_CTRL_0_U str_pcie_ctrl_0;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(mPcieIntCfg.PortIsInitilized[Port])
+ {
+ return PCIE_ERR_ALREADY_INIT;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG);
+ if(PcieType == PCIE_END_POINT)
+ {
+ str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE;
+ }
+ else
+ {
+ str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC;
+ }
+ PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+}
+
+VOID PciePcsInit(UINT32 HostBridgeNum, UINT32 Port)
+{
+
+ if(Port<=2)
+ {
+ RegWrite(pcie_serders_base[HostBridgeNum][Port] + 0xc088, 0x212);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0);
+ }
+ else
+
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff);
+ }
+
+}
+
+VOID PcieEqualization(UINT32 Port)
+{
+ UINT32 Value;
+
+ PcieRegWrite(Port, 0x890, 0x1400);
+ PcieRegWrite(Port, 0x894, 0xfd7);
+
+ PcieRegWrite(Port, 0x89c, 0x0);
+ PcieRegWrite(Port, 0x898, 0xfc00);
+ PcieRegWrite(Port, 0x89c, 0x1);
+ PcieRegWrite(Port, 0x898, 0xbd00);
+ PcieRegWrite(Port, 0x89c, 0x2);
+ PcieRegWrite(Port, 0x898, 0xccc0);
+ PcieRegWrite(Port, 0x89c, 0x3);
+ PcieRegWrite(Port, 0x898, 0x8dc0);
+ PcieRegWrite(Port, 0x89c, 0x4);
+ PcieRegWrite(Port, 0x898, 0xfc0);
+ PcieRegWrite(Port, 0x89c, 0x5);
+ PcieRegWrite(Port, 0x898, 0xe46);
+ PcieRegWrite(Port, 0x89c, 0x6);
+ PcieRegWrite(Port, 0x898, 0xdc8);
+ PcieRegWrite(Port, 0x89c, 0x7);
+ PcieRegWrite(Port, 0x898, 0xcb46);
+ PcieRegWrite(Port, 0x89c, 0x8);
+ PcieRegWrite(Port, 0x898, 0x8c07);
+ PcieRegWrite(Port, 0x89c, 0x9);
+ PcieRegWrite(Port, 0x898, 0xd0b);
+ PcieRegWrite(Port, 0x8a8, 0x103ff21);
+
+ Value = PcieRegRead(Port, 0x80);
+ Value |= 0x80;
+ PcieRegWrite(Port, 0x80, Value);
+
+ PcieRegWrite(Port, 0x184, 0x44444444);
+ PcieRegWrite(Port, 0x188, 0x44444444);
+ PcieRegWrite(Port, 0x18c, 0x44444444);
+ PcieRegWrite(Port, 0x190, 0x44444444);
+
+}
+
+
+EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
+ {
+ (VOID)PcieDisableItssm(HostBridgeNum, Port);
+ }
+
+ mPcieIntCfg.PortIsInitilized[Port] = FALSE;
+ mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
+ ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
+
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS AssertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
+ {
+ (VOID)PcieDisableItssm(HostBridgeNum, Port);
+ }
+
+ mPcieIntCfg.PortIsInitilized[Port] = FALSE;
+ mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
+ ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
+
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
+ {
+ (VOID)PcieDisableItssm(HostBridgeNum, Port);
+ }
+
+ mPcieIntCfg.PortIsInitilized[Port] = FALSE;
+ mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
+ mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
+ ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
+
+ if(Port <= 2)
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
+ MicroSecondDelay(0x1000);
+ }
+ else
+ {
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
+ MicroSecondDelay(0x1000);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port)
+{
+ u_sc_pcie_hilink_pcs_reset_req reset_req;
+ UINT32 pcs_local_reset_status;
+ UINT32 pcs_local_status_checked;
+ UINT32 hilink_reset_status;
+ UINT32 hilink_status_checked;
+ UINT32 count = 0;
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
+ MicroSecondDelay(0x1000);
+
+ /* read reset status, make sure pcs is reset */
+ do {
+ MicroSecondDelay(1000);
+ count ++;
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_reset_status);
+ pcs_local_status_checked =
+ ((pcs_local_reset_status & (1 << Port)) !=
+ (1 << Port));
+
+ } while ((pcs_local_status_checked) && (count < 1000));
+
+ if (pcs_local_status_checked)
+ DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n"));
+
+ count = 0;
+ do {
+ MicroSecondDelay(1000);
+ count ++;
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
+ hilink_status_checked =
+ ((hilink_reset_status & (0xff << (Port << 3))) !=
+ (0xff << (Port << 3)));
+ } while ((hilink_status_checked) && (count < 1000));
+
+ if (hilink_status_checked)
+ DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n"));
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+ u_sc_pcie_hilink_pcs_reset_req reset_req;
+ UINT32 pcs_local_status;
+ UINT32 pcs_local_status_checked;
+ UINT32 hilink_reset_status;
+ UINT32 hilink_status_checked;
+ UINT32 count = 0;
+
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
+
+ reset_req.UInt32 = 0;
+ reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
+
+ /* read reset status, make sure pcs is deassert */
+ do {
+ MicroSecondDelay(1000);
+ count ++;
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_status);
+ pcs_local_status_checked = (pcs_local_status & (1 << Port));
+ } while ((pcs_local_status_checked) && (count < 1000));
+
+ /* get a timeout error */
+ if (pcs_local_status_checked)
+ DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
+
+ count = 0;
+ do {
+ MicroSecondDelay(1000);
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
+ hilink_status_checked = (hilink_reset_status &
+ (0xff << (Port << 3)));
+ } while ((hilink_status_checked) && (count < 1000));
+
+ if (hilink_status_checked)
+ DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
+
+ return EFI_SUCCESS;
+}
+
+VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 val;
+ UINT32 current_speed;
+ UINT32 ltssm_state;
+ UINT32 timeout = 0;
+ UINT32 eq = 0;
+ UINT32 loop = 100000;
+ U_SC_PCIE0_SYS_STATE4 PcieStat;
+
+ while (loop)
+ {
+ MicroSecondDelay(10);
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ val = PcieStat.UInt32;
+ current_speed = (val >> 6) & 0x3;
+ if (current_speed == PCIE_GEN3)
+ break;
+ loop--;
+ }
+ if (!loop) {
+ DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
+ return;
+ }
+
+ ltssm_state = val & PCIE_LTSSM_STATE_MASK;
+ while ((current_speed == PCIE_GEN3) &&
+ (ltssm_state != PCIE_LTSSM_LINKUP_STATE) && (timeout < 200)) {
+ if ((ltssm_state & 0x30) == 0x20)
+ eq = 1;
+
+ if ((ltssm_state == 0xd) && (eq == 1))
+ {
+ MicroSecondDelay(5000);
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ val = PcieStat.UInt32;
+ ltssm_state = val & PCIE_LTSSM_STATE_MASK;
+ current_speed = (val >> 6) & 0x3;
+ if (ltssm_state == 0xd)
+ {
+ DEBUG((EFI_D_ERROR, "Do symbol align reset rate %d ltssm 0x%x\n",current_speed, ltssm_state));
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x8000000);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x8000000);
+
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0);
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0);
+ }
+ break;
+ }
+
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ val = PcieStat.UInt32;
+ ltssm_state = val & PCIE_LTSSM_STATE_MASK;
+ current_speed = (val >> 6) & 0x3;
+
+ MicroSecondDelay(1000);
+ timeout++;
+ }
+
+ if (timeout >= 200) {
+ DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
+ return;
+ }
+ DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
+}
+
+VOID Gen3DfeEnable(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 val;
+ UINT32 lane;
+ UINT32 current_speed;
+ U_SC_PCIE0_SYS_STATE4 PcieStat;
+
+ if (Port == 3)
+ return;
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ val = PcieStat.UInt32;
+ current_speed = (val >> 6) & 0x3;
+ if (current_speed != PCIE_GEN3)
+ return;
+ for (lane = 0; lane < 8; lane++)
+ RegWrite(pcie_serders_base[HostBridgeNum][Port] + (UINT32)DS_API(lane) + 4, 0x3851);
+
+ DEBUG((EFI_D_ERROR, "enable DFE success\n"));
+}
+
+EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock)
+{
+ UINT32 reg_clock_disable;
+ UINT32 reg_clock_enable;
+ UINT32 reg_clock_status;
+ UINT32 clock_status;
+ UINT32 clock_status_checked;
+ UINT32 clock_ctrl;
+ UINT32 count = 0;
+
+ if (Port == 3) {
+ reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG;
+ reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG;
+ reg_clock_status = PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG;
+ } else {
+ reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(Port);
+ reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(Port);
+ reg_clock_status = PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(Port);
+ }
+
+ if (0x1610 == soctype)
+ {
+ clock_ctrl = 0x7;
+ }
+ else
+ {
+ clock_ctrl = 0x3;
+ if (Clock)
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, clock_ctrl);
+ else
+ RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, clock_ctrl);
+ }
+
+ do {
+ count ++;
+ MicroSecondDelay(1000);
+ RegRead(pcie_subctrl_base[HostBridgeNum] + reg_clock_status, clock_status);
+ if (Clock)
+ clock_status_checked =
+ ((clock_status & clock_ctrl) != clock_ctrl);
+ else
+ clock_status_checked =
+ ((clock_status & clock_ctrl) != 0);
+ } while ((clock_status_checked) && (count < 1000)); //1S
+
+ /* get a timeout error */
+ if (clock_status_checked)
+ DEBUG((EFI_D_ERROR, "clock operation failed!\n"));
+
+ return EFI_SUCCESS;
+}
+
+VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd)
+{
+ UINT32 Value = 0;
+
+ if (0x1610 == soctype)
+ {
+ }
+ else
+ {
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value);
+ Value &= ~(0xf);
+ Value |= Spd;
+ RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value);
+ return;
+ }
+ return;
+}
+
+VOID PcieSpdControl(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;;
+
+ /* set link width speed control register */
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value);
+ /*
+ * set the Directed Speed Change field of the Link Width and Speed
+ * Change Control register
+ */
+ Value |= (1 << 17);
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value);
+}
+
+VOID PcieSetDb2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 enable)
+{
+ UINT32 dbi_ctrl;
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl);
+ if (enable)
+ dbi_ctrl |= BIT0;
+ else
+ dbi_ctrl &= ~BIT0;
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+}
+
+VOID PcieDisabledBar0(UINT32 HostBridgeNum, UINT32 Port)
+{
+ PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_ENABLE);
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x10,0);
+ PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_DISABLE);
+}
+
+/* Configure vmid/asid table in PCIe host */
+VOID PcieConfigContextP660(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 i = 0;
+ UINTN val = 0;;
+
+ /*
+ * enable to clean vmid and asid tables though apb bus
+ * */
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+ /* enable ar channel */
+ val |= PCIE_RD_TAB_SEL | PCIE_RD_TAB_EN;
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE);
+ for (i = 0; i < 0x800; i++)
+ PcieRegWrite(Port, i * 4, 0);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ /* enable aw channel */
+ val &= (~PCIE_RD_TAB_SEL);
+ val |= PCIE_RD_TAB_EN;
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE);
+
+ /*
+ * init vmid and asid tables for all PCIe devices as 0
+ * vmid table: 0 ~ 0x3ff, asid table: 0x400 ~ 0x7ff
+ */
+ for (i = 0; i < 0x800; i++)
+ PcieRegWrite(Port, i * 4, 0);
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+ RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+ /* disable ar channel */
+ val |= PCIE_RD_TAB_SEL;
+ val &= (~PCIE_RD_TAB_EN);
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+ /* disable aw channel */
+ val &= ((~PCIE_RD_TAB_SEL) & (~PCIE_RD_TAB_EN));
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL24_REG, 0xb7010040 & 0xffffffff);
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL28_REG, 0);
+
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL16_REG, (1<<12)|(1<<16));
+ RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL29_REG, (1<<12));
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);;
+}
+
+EFI_STATUS PcieMaskLinkUpInit(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ Value = PcieRegRead(Port, 0x1d0);
+ Value |= 1 << 12;
+ PcieRegWrite(Port,0x1d0, Value);
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+ return EFI_SUCCESS;
+}
+
+BOOLEAN PcieIsLinkUp(UINT32 HostBridgeNum, UINT32 Port)
+{
+ UINT32 Value = 0;
+ U_SC_PCIE0_SYS_STATE4 PcieStat;
+
+ RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+ Value = PcieStat.UInt32;
+ if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
+ return TRUE;
+
+ return FALSE;
+}
+
+VOID PcieWriteOwnConfig(UINT32 Port, UINT32 Offset)
+{
+ UINT32 Value = 0;
+ Value = PcieRegRead(Port,Offset & (~0x3));
+ Value &= 0x0000ffff;
+ Value |= 0x06040000;
+ PcieRegWrite(Port, Offset & (~0x3), Value);
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+PciePortInit (
+ IN UINT32 HostBridgeNum,
+ IN PCIE_DRIVER_CFG *PcieCfg
+ )
+{
+ UINT32 Count = 0;
+ UINT32 PortIndex = PcieCfg->PortIndex;
+ UINT32 Value = 0;
+
+
+ if(PortIndex >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(mPcieIntCfg.PortIsInitilized[PortIndex])
+ {
+ return PCIE_ERR_ALREADY_INIT;
+ }
+
+ mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
+
+ /* assert reset signals */
+ (VOID)AssertPcieCoreReset(HostBridgeNum, PortIndex);
+ (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 0);
+ (VOID)AssertPciePcsReset(HostBridgeNum, PortIndex);
+
+ /* de-assert phy reset */
+ (VOID)DeassertPciePcsReset(HostBridgeNum, PortIndex);
+
+ /* de-assert core reset */
+ (VOID)DeassertPcieCoreReset(HostBridgeNum, PortIndex);
+ (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 1);
+
+ do {
+ RegRead(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(PortIndex * 0x10000) + 0x8108, Value);
+ if (Count == 10) {
+ DEBUG((EFI_D_ERROR, "PCIe Failed! PLL Locked: 0x%x\n\n",Value));
+ return EFI_NOT_READY;
+ }
+ Count++;
+ MicroSecondDelay(100000);
+ } while ((Value & 0x3) == 0);
+ Count = 0;
+
+ /* initialize phy */
+ (VOID)PciePcsInit(HostBridgeNum, PortIndex);
+
+ (VOID)PcieModeSet(HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType);
+ (VOID)PcieSpdSet(0x660, HostBridgeNum, PortIndex, 3);
+ (VOID)PcieSpdControl(HostBridgeNum, PortIndex);
+ /* setup root complex */
+ (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth);
+
+ /* Pcie Equalization*/
+ (VOID)PcieEqualization(PortIndex);
+
+ /* assert LTSSM enable */
+ (VOID)PcieEnableItssm(HostBridgeNum, PortIndex);
+
+ /*
+ * This is a PCS hardware bug, we fix it by resetting
+ * PCS symalign module state machine
+ */
+ (VOID)PcieGen3Config(HostBridgeNum, PortIndex);
+ PcieConfigContextP660(HostBridgeNum, PortIndex);
+ (VOID)PcieDisabledBar0(HostBridgeNum, PortIndex);
+ (VOID)PcieWriteOwnConfig(PortIndex, 0xa);
+ /* check if the link is up or not */
+ while (!PcieIsLinkUp(HostBridgeNum, PortIndex)) {
+ MicroSecondDelay(1000);
+ Count++;
+ if (Count >= 1000) {
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex));
+ return PCIE_ERR_LINK_OVER_TIME;
+ }
+ }
+ DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex));
+
+ /* dfe enable is just for 660 */
+ (VOID)Gen3DfeEnable(HostBridgeNum, PortIndex);
+
+
+ PcieRegWrite(PortIndex, 0x80c, 0x208FF);
+
+ return EFI_SUCCESS;
+}
+
+
+
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable)
+{
+ PCIE_SYS_CTRL20_U dbi_ro_enable;
+
+ if(Port >= PCIE_MAX_PORT_NUM)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+ dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG);
+ dbi_ro_enable.Bits.ro_sel = Enable;
+ PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32);
+ PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+ return EFI_SUCCESS;
+
+}
+
+VOID PcieDelay(UINT32 dCount)
+{
+ volatile UINT32 *uwCnt = &dCount;
+
+ while(*uwCnt > 0)
+ {
+ *uwCnt = *uwCnt - 1;
+ }
+
+}
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h
new file mode 100644
index 0000000..00a2b27
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h
@@ -0,0 +1,239 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_LIB_H__
+#define __PCIE_INIT_LIB_H__
+
+#include <Uefi.h>
+#include <Regs/HisiPcieV1RegOffset.h>
+#include "PcieKernelApi.h"
+
+#define PCIE_AXI_SLAVE_BASE (0xb3000000)
+#define PCIE_MAX_AXI_SIZE (0x1000000)
+#define PCIE_AXI_BASE(port) (PCIE_AXI_SLAVE_BASE + port * PCIE_MAX_AXI_SIZE)
+#define PCIE_SMMU_BASE (0xb0040000)
+
+
+#define PCIE_DMA_CHANNEL_NUM (2)
+#define PCIE_DMA_RESOURCE_MODE_SIZE (0x40000)
+#define PCIE_DMA_BURST_SIZE (0x80000000)
+
+#define PCIE_ADDR_BASE_OFFSET 0x46C00000
+#define PCIE_ADDR_BASE_HOST_ADDR (PCIE_ADDR_BASE_OFFSET + NP_DDR_BASE_ADDR_HOST)
+#define NP_DDR_BASE_ADDR_HOST 0x236E00000ULL
+
+
+
+#define PCIE_GIC_MSI_ITS_BASE (0xb7010040)
+#define PCIE_INT_BASE (13824)
+#define PCIE_INT_LIMIT (PCIE_INT_BASE + 64)
+
+#define PCIE_NTB_MEM_SIZE (0x1000000)
+#define PCIE_NTB_BAR01_SIZE (0x10000) // 64K
+#define PCIE_NTB_BAR23_SIZE (0x800000) // 8M
+#define PCIE_NTB_BAR45_SIZE (0x800000)
+
+#define PCIE_IATU_END {PCIE_IATU_OUTBOUND,0,0,0}
+#define PCIE_IATU_INBOUND_MASK (0x80000000)
+#define PCIE_IATU_INDEX_MASK (0x7f)
+#define PCIE_IATU_TYPE_MASK (0x1f)
+#define PCIE_IATU_EN (0x1 << 0)
+#define PCIE_IATU_SHIFT_MODE (0x1 << 1)
+#define PCIE_IATU_BAR_MODE (0x1 << 2)
+#define PCIE_IATU_FUNC_MODE (0x1 << 3)
+#define PCIE_IATU_AT_MODE (0x1 << 4)
+#define PCIE_IATU_ATTR_MODE (0x1 << 5)
+#define PCIE_IATU_TD_MODE (0x1 << 6) //TD
+#define PCIE_IATU_TC_MODE (0x1 << 7) // TC
+#define PCIE_IATU_PREFETCH_MODE (0x1 << 8)
+#define PCIE_IATU_DMA_BY_PASS_MODE (0x1 << 9) //DMA bypass untranslate
+
+#define PCIE_BAR_MASK_SIZE (0x800000)
+#define PCIE_BAR_TYPE_32 (0)
+#define PCIE_BAR_TYPE_64 (2)
+#define PCIE_BAR_PREFETCH_MODE (1)
+
+#define RegWrite(addr,data) (*(volatile UINT32*)(UINTN)(addr) = (data))
+#define RegRead(addr,data) ((data) = *(volatile UINT32*)(UINTN)(addr))
+
+
+typedef struct tagPcieDebugInfo
+{
+ UINT32 pcie_rdma_start_cnt;
+ UINT32 pcie_wdma_start_cnt;
+ UINT64 pcie_wdma_transfer_len;
+ UINT64 pcie_rdma_transfer_len;
+ UINT32 pcie_rdma_fail_cnt;
+ UINT32 pcie_wdma_fail_cnt;
+}pcie_debug_info_s;
+
+
+#define bdf_2_b(bdf) ((bdf >> 8) & 0xFF)
+#define bdf_2_d(bdf) ((bdf >> 3) & 0x1F)
+#define bdf_2_f(bdf) ((bdf >> 0) & 0x7)
+#define b_d_f_2_bdf(b,d,f) (((b & 0xff) << 8 ) | ((d & 0x1f) << 3) | ((f & 0x7) << 0))
+
+
+
+typedef UINT32 (*pcie_dma_func_int)(UINT32 ulErrno, UINT32 ulReserved);
+
+
+typedef struct {
+ UINT32 ViewPort; //iATU Viewport Register
+ UINT32 RegionCtrl1; //Region Control 1 Register
+ UINT32 RegionCtrl2; //Region Control 2 Register
+ UINT32 BaseLow; //Lower Base Address Register
+ UINT32 BaseHigh; //Upper Base Address Register
+ UINT32 Limit; //Limit Address Register
+ UINT32 TargetLow; //Lower Target Address Register
+ UINT32 TargetHigh; //Upper Target Address Register
+} PCIE_IATU_VA;
+
+typedef enum {
+ PCIE_IATU_OUTBOUND = 0x0,
+ PCIE_IATU_INBOUND = 0x1,
+} PCIE_IATU_DIR;
+
+typedef struct {
+ PCIE_IATU_DIR IatuType;
+ UINT64 IatuBase;
+ UINT64 IatuSize;
+ UINT64 IatuTarget;
+} PCIE_IATU;
+
+typedef struct {
+ UINT32 IatuType;
+ UINT64 IatuBase;
+ UINT32 IatuLimit;
+ UINT64 IatuTarget;
+ UINT32 Valid;
+} PCIE_IATU_HW;
+
+typedef struct {
+ UINT32 PortIndex;
+ PCIE_PORT_INFO PortInfo;
+ PCIE_IATU_HW OutBound[PCIE_MAX_OUTBOUND];
+ PCIE_IATU_HW InBound[PCIE_MAX_INBOUND];
+} PCIE_DRIVER_CFG;
+
+typedef enum {
+ PCIE_CONFIG_REG = 0x0,
+ PCIE_SYS_CONTROL = 0x1,
+ PCIE_SLV_CONTENT_MODE = 0x2,
+} PCIE_RW_MODE;
+
+typedef union {
+ PCIE_DRIVER_CFG PcieDevice;
+ PCIE_NTB_CFG NtbDevice;
+} DRIVER_CFG_U;
+
+typedef struct {
+ VOID *MappedOutbound[PCIE_MAX_OUTBOUND];
+ UINT32 OutboundType[PCIE_MAX_OUTBOUND];
+ UINT32 OutboundEn[PCIE_MAX_OUTBOUND];
+} PCIE_MAPPED_IATU_ADDR;
+
+typedef struct {
+ BOOLEAN PortIsInitilized[PCIE_MAX_PORT_NUM];
+ DRIVER_CFG_U Dev[PCIE_MAX_PORT_NUM];
+ VOID *DmaResource[PCIE_MAX_PORT_NUM];
+ UINT32 DmaChannel[PCIE_MAX_PORT_NUM][2];
+ VOID *RegResource[PCIE_MAX_PORT_NUM];
+ VOID *CfgResource[PCIE_MAX_PORT_NUM];
+} PCIE_INIT_CFG;
+
+typedef enum {
+ PCIE_MMIO_IEP_CFG = 0x1000,
+ PCIE_MMIO_IEP_CTRL = 0x0,
+ PCIE_MMIO_EEP_CFG = 0x9000,
+ PCIE_MMIO_EEP_CTRL = 0x8000,
+} NTB_MMIO_MODE;
+
+typedef struct tagPcieDmaDes
+{
+ UINT32 uwChanCtrl;
+ UINT32 uwLen;
+ UINT32 uwLocalLow;
+ UINT32 uwLocalHigh;
+ UINT32 uwTagetLow;
+ UINT32 uwTagetHigh;
+}pcie_dma_des_s,*pcie_dma_des_ps;
+
+typedef enum {
+ PCIE_IATU_MEM,
+ PCIE_IATU_CFG = 0x4,
+ PCIE_IATU_IO
+} PCIE_IATU_OUT_TYPE;
+
+typedef enum {
+ PCIE_PAYLOAD_128B = 0,
+ PCIE_PAYLOAD_256B,
+ PCIE_PAYLOAD_512B,
+ PCIE_PAYLOAD_1024B,
+ PCIE_PAYLOAD_2048B,
+ PCIE_PAYLOAD_4096B,
+ PCIE_RESERVED_PAYLOAD
+} PCIE_PAYLOAD_SIZE;
+
+typedef struct tagPcieDfxInfo
+{
+ PCIE_EP_AER_CAP0_U aer_cap0;
+ PCIE_EP_AER_CAP1_U aer_cap1;
+ PCIE_EP_AER_CAP2_U aer_cap2;
+ PCIE_EP_AER_CAP3_U aer_cap3;
+ PCIE_EP_AER_CAP4_U aer_cap4;
+ PCIE_EP_AER_CAP5_U aer_cap5;
+ PCIE_EP_AER_CAP6_U aer_cap6;
+ UINT32 hdr_log0;
+ UINT32 hdr_log1;
+ UINT32 hdr_log2;
+ UINT32 hdr_log3;
+ PCIE_EP_AER_CAP11_U aer_cap11;
+ PCIE_EP_AER_CAP12_U aer_cap12;
+ PCIE_EP_AER_CAP13_U aer_cap13;
+
+ PCIE_EP_PORTLOGIC62_U port_logic62;
+ PCIE_EP_PORTLOGIC64_U port_logic64;
+ PCIE_EP_PORTLOGIC66_U port_logic66;
+ PCIE_EP_PORTLOGIC67_U port_logic67;
+ PCIE_EP_PORTLOGIC69_U port_logic69;
+ PCIE_EP_PORTLOGIC75_U port_logic75;
+ PCIE_EP_PORTLOGIC76_U port_logic76;
+ PCIE_EP_PORTLOGIC77_U port_logic77;
+ PCIE_EP_PORTLOGIC79_U port_logic79;
+ PCIE_EP_PORTLOGIC80_U port_logic80;
+ PCIE_EP_PORTLOGIC81_U port_logic81;
+ PCIE_EP_PORTLOGIC87_U port_logic87;
+
+ PCIE_CTRL_10_U pcie_ctrl10;
+ UINT32 slve_rerr_addr_low;
+ UINT32 slve_rerr_addr_up;
+ UINT32 slve_werr_addr_low;
+ UINT32 slve_werr_addr_up;
+ UINT32 pcie_state4;
+ UINT32 pcie_state5;
+}PCIE_DFX_INFO_S;
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode);
+
+UINT32 PcieIsLinkDown(UINT32 Port);
+
+BOOLEAN PcieIsLinkUp(UINT32 HostBridgeNum, UINT32 Port);
+
+EFI_STATUS PcieWaitLinkUp(UINT32 Port);
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable);
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h
new file mode 100644
index 0000000..d1ba1c8
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h
@@ -0,0 +1,346 @@
+/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_KERNEL_API_H__
+#define __PCIE_KERNEL_API_H__
+
+#define PCIE_HOST_BRIDGE_NUM (1)
+#define PCIE_MAX_PORT_NUM (4)
+#define PCIE_MAX_OUTBOUND (6)
+#define PCIE_MAX_INBOUND (4)
+#define PCIE3_MAX_OUTBOUND (16)
+#define PCIE3_MAX_INBOUND (16)
+
+#define PCIE_LINK_LOOP_CNT (0x1000)
+#define PCIE_IATU_ADDR_MASK (0xFFFFF000)
+#define PCIE_1M_ALIGN_SHIRFT (20)
+#define PCIE_BDF_MASK (0xF0000FFF)
+#define PCIE_BUS_SHIRFT (20)
+#define PCIE_DEV_SHIRFT (15)
+#define PCIE_FUNC_SHIRFT (12)
+
+#define PCIE_DBI_CS2_ENABLE (0x1)
+#define PCIE_DBI_CS2_DISABLE (0x0)
+
+#define PCIE_DMA_CHANLE_READ (0x1)
+#define PCIE_DMA_CHANLE_WRITE (0x0)
+
+
+#define PCIE_ERR_IATU_TABLE_NULL EFIERR (1)
+#define PCIE_ERR_LINK_OVER_TIME EFIERR (2)
+#define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE EFIERR (3)
+#define PCIE_ERR_ALREADY_INIT EFIERR (4)
+#define PCIE_ERR_PARAM_INVALID EFIERR (5)
+#define PCIE_ERR_MEM_OPT_OVER EFIERR (6)
+#define PCIE_ERR_NOT_INIT EFIERR (7)
+#define PCIE_ERR_CFG_OPT_OVER EFIERR (8)
+#define PCIE_ERR_DMA_READ_CHANLE_BUSY EFIERR (9)
+#define PCIE_ERR_DMA_WRITE_CHANLE_BUSY EFIERR (10)
+#define PCIE_ERR_DMAR_NO_RESORCE EFIERR (11)
+#define PCIE_ERR_DMAW_NO_RESORCE EFIERR (12)
+#define PCIE_ERR_DMA_OVER_MAX_RESORCE EFIERR (13)
+#define PCIE_ERR_NO_IATU_WINDOW EFIERR (14)
+#define PCIE_ERR_DMA_TRANSPORT_OVER_TIME EFIERR (15)
+#define PCIE_ERR_DMA_MEM_ALLOC_ERROR EFIERR (16)
+#define PCIE_ERR_DMA_ABORT EFIERR (17)
+#define PCIE_ERR_UNSUPPORT_BAR_TYPE EFIERR (18)
+
+typedef enum {
+ PCIE_ROOT_COMPLEX,
+ PCIE_END_POINT,
+ PCIE_NTB_TO_NTB,
+ PCIE_NTB_TO_RP,
+} PCIE_PORT_TYPE;
+
+typedef enum {
+ PCIE_GEN1_0 = 1, //PCIE 1.0
+ PCIE_GEN2_0 = 2, //PCIE 2.0
+ PCIE_GEN3_0 = 4 //PCIE 3.0
+} PCIE_PORT_GEN;
+
+typedef enum {
+ PCIE_WITDH_X1 = 0x1,
+ PCIE_WITDH_X2 = 0x3,
+ PCIE_WITDH_X4 = 0x7,
+ PCIE_WITDH_X8 = 0xf,
+ PCIE_WITDH_INVALID
+} PCIE_PORT_WIDTH;
+
+
+typedef struct {
+ PCIE_PORT_TYPE PortType;
+ PCIE_PORT_WIDTH PortWidth;
+ PCIE_PORT_GEN PortGen;
+ UINT8 PcieLinkUp;
+} PCIE_PORT_INFO;
+
+typedef struct tagPciecfg_params
+{
+ UINT32 preemphasis;
+ UINT32 deemphasis;
+ UINT32 swing;
+ UINT32 balance;
+}pcie_cfg_params_s;
+
+typedef enum {
+ PCIE_CORRECTABLE_ERROR = 0,
+ PCIE_NON_FATAL_ERROR,
+ PCIE_FATAL_ERROR,
+ PCIE_UNSUPPORTED_REQUEST_ERROR,
+ PCIE_ALL_ERROR
+} PCIE_ERROR_TYPE;
+
+typedef union tagPcieDeviceStatus
+{
+ struct
+ {
+ UINT16 correctable_error : 1;
+ UINT16 non_fatal_error : 1;
+ UINT16 fatal_error : 1;
+ UINT16 unsupported_error : 1;
+ UINT16 aux_power : 1;
+ UINT16 transaction_pending : 1;
+ UINT16 reserved_6_15 : 10;
+ }Bits;
+
+ UINT16 Value;
+}pcie_device_status_u;
+
+
+typedef union tagPcieUcAerStatus
+{
+ struct
+ {
+ UINT32 undefined : 1 ; /* [0] undefined */
+ UINT32 reserved_1_3 : 3 ; /* reserved */
+ UINT32 data_link_proto_error : 1 ; /* Data Link Protocol Error Status */
+ UINT32 reserved_5_11 : 7 ; /* reserved */
+ UINT32 poisoned_tlp_status : 1 ; /* Poisoned TLP Status */
+ UINT32 flow_control_proto_error : 1 ; /* Flow Control Protocol Error Status */
+ UINT32 completion_time_out : 1 ; /* Completion Timeout Status */
+ UINT32 compler_abort_status : 1 ; /* Completer Abort Status */
+ UINT32 unexpect_completion_status : 1 ; /* Unexpected Completion Status */
+ UINT32 receiver_overflow_status : 1 ; /*Receiver Overflow Status */
+ UINT32 malformed_tlp_status : 1 ; /* Malformed TLP Status*/
+ UINT32 ecrc_error_status : 1 ; /* ECRC Error Status */
+ UINT32 unsupport_request_error_status : 1 ; /* Unsupported Request Error Status */
+ UINT32 reserved_21 : 1 ; /* reserved */
+ UINT32 uncorrectable_interal_error : 1 ; /* Uncorrectable Internal Error Status */
+ UINT32 reserved_23 : 1 ; /* reserved*/
+ UINT32 atomicop_egress_blocked_status : 1 ; /* AtomicOp Egress Blocked Status */
+ UINT32 tlp_prefix_blocked_error_status : 1 ; /* TLP Prefix Blocked Error Status */
+ UINT32 reserved_26_31 : 1 ; /* reserved */
+ }Bits;
+
+ UINT32 Value;
+}pcie_uc_aer_status_u;
+
+typedef union tagPcieCoAerStatus
+{
+ struct
+ {
+ UINT32 receiver_error_status : 1 ; /* Receiver Error Status */
+ UINT32 reserved_1_5 : 5 ; /* Reserved */
+ UINT32 bad_tlp_status : 1 ; /* Bad TLP Status */
+ UINT32 bad_dllp_status : 1 ; /* Bad DLLP Status */
+ UINT32 reply_num_rollover_status : 1 ; /* REPLAY_NUM Rollover Status*/
+ UINT32 reserved_9_11 : 3 ; /* Reserved */
+ UINT32 reply_timer_timeout : 1 ; /* Replay Timer Timeout Status */
+ UINT32 advisory_nonfatal_error : 1 ; /* Advisory Non-Fatal Error Status*/
+ UINT32 corrected_internal_error : 1 ; /*Corrected Internal Error Status*/
+ UINT32 reserved_15_31 : 1 ; /* Reserved */
+ }Bits;
+ UINT32 Value;
+}pcie_co_aer_status_u;
+
+typedef struct tagPcieAerStatus
+{
+ pcie_uc_aer_status_u uc_aer_status;
+ pcie_co_aer_status_u co_aer_status;
+}pcie_aer_status_s;
+
+
+
+typedef struct tagPcieLoopTestResult
+{
+ UINT32 tx_pkts_cnt;
+ UINT32 rx_pkts_cnt;
+ UINT32 error_pkts_cnt;
+ UINT32 droped_pkts_cnt;
+ UINT32 push_cnt;
+ pcie_device_status_u device_status;
+ pcie_aer_status_s pcie_aer_status;
+} pcie_loop_test_result_s;
+
+typedef struct tagPcieDmaChannelAttrs {
+ UINT32 dma_chan_en;
+ UINT32 dma_mode;
+ UINT32 channel_status;
+}pcie_dma_channel_attrs_s;
+
+typedef enum tagPcieDmaChannelStatus
+{
+ PCIE_DMA_CS_RESERVED = 0,
+ PCIE_DMA_CS_RUNNING = 1,
+ PCIE_DMA_CS_HALTED = 2,
+ PCIE_DMA_CS_STOPPED = 3
+}pcie_dma_channel_status_e;
+
+typedef enum tagPcieDmaIntType{
+ PCIE_DMA_INT_TYPE_DONE=0,
+ PCIE_DMA_INT_TYPE_ABORT,
+ PCIE_DMA_INT_ALL,
+ PCIE_DMA_INT_NONE
+}pcie_dma_int_type_e;
+
+typedef enum tagPcieMulWinSize
+{
+ WIN_SIZE_4K = 0xc,
+ WIN_SIZE_8K,
+ WIN_SIZE_16K,
+ WIN_SIZE_32K,
+ WIN_SIZE_64K,
+ WIN_SIZE_128K,
+ WIN_SIZE_256K,
+ WIN_SIZE_512K,
+ WIN_SIZE_1M,
+ WIN_SIZE_2M,
+ WIN_SIZE_4M,
+ WIN_SIZE_8M,
+ WIN_SIZE_16M,
+ WIN_SIZE_32M,
+ WIN_SIZE_64M,
+ WIN_SIZE_128M,
+ WIN_SIZE_256M,
+ WIN_SIZE_512M,
+ WIN_SIZE_1G,
+ WIN_SIZE_2G,
+ WIN_SIZE_4G,
+ WIN_SIZE_8G,
+ WIN_SIZE_16G,
+ WIN_SIZE_32G,
+ WIN_SIZE_64G,
+ WIN_SIZE_128G,
+ WIN_SIZE_256G,
+ WIN_SIZE_512G = 0x27,
+}pcie_mul_win_size_e;
+
+typedef struct tagPcieMultiCastCfg
+{
+ UINT64 multicast_base_addr;
+ pcie_mul_win_size_e base_addr_size;
+ UINT64 base_translate_addr;
+}pcie_multicast_cfg_s;
+
+typedef enum tagPcieMode
+{
+ PCIE_EP_DEVICE = 0x0,
+ LEGACY_PCIE_EP_DEVICE = 0x1,
+ RP_OF_PCIE_RC = 0x4,
+ PCIE_INVALID = 0x100
+}pcie_mode_e;
+
+typedef struct{
+ UINT32 PortIndex;
+ PCIE_PORT_INFO PortInfo;
+ UINT64 iep_bar01; /*iep bar 01*/
+ UINT64 iep_bar23;
+ UINT64 iep_bar45;
+ UINT64 iep_bar01_xlat;
+ UINT64 iep_bar23_xlat;
+ UINT64 iep_bar45_xlat;
+ UINT64 iep_bar_lmt23;
+ UINT64 iep_bar_lmt45; /*bar limit*/
+ UINT64 eep_bar01;
+ UINT64 eep_bar23;
+ UINT64 eep_bar45;
+ UINT64 eep_bar23_xlat;
+ UINT64 eep_bar45_xlat;
+ UINT64 eep_bar_lmt23; /*bar limit*/
+ UINT64 eep_bar_lmt45; /*bar limit*/
+} PCIE_NTB_CFG;
+
+extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info);
+
+extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl);
+
+extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed);
+
+extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+
+extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control);
+
+extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute);
+
+extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status);
+
+extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel);
+
+
+extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status);
+
+extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type);
+
+
+extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num);
+
+extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg);
+
+extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell);
+
+extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result);
+extern int pcie_port_reset(UINT32 Port);
+
+extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \
+pcie_device_status_u *pcie_stat);
+extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
+
+extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status);
+extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
+
+extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length);
+
+extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length);
+
+extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length);
+
+extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length);
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.c b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.c
new file mode 100644
index 0000000..90adc25
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.c
@@ -0,0 +1,119 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <Uefi.h>
+#include <Pi/PiDxeCis.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/PrintLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Protocol/AcpiTable.h>
+#include <IndustryStandard/Acpi.h>
+#include <Uefi/UefiSpec.h>
+#include <Guid/Acpi.h>
+#include "UnInstallAcpiTable.h"
+
+#define EFI_ACPI_MAX_NUM_TABLES 20
+EFI_GUID gSataControlGuid = EFI_SATA_CONTROL_GUID;
+
+EFI_STATUS
+UnInstallSsdtTable (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable)
+{
+ EFI_STATUS Status;
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol;
+ EFI_ACPI_SDT_HEADER *Table;
+ EFI_ACPI_TABLE_VERSION TableVersion;
+ UINTN TableKey;
+ UINTN i;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ UINT8 DataPtr1 = 2;
+ UINTN DataPtr1Size;
+ UINT32 SsdtName;
+
+ DataPtr1Size = sizeof(DataPtr1);
+
+ Status = gRT->GetVariable (
+ SATA_ENABLE_FLAG,
+ &gSataControlGuid,
+ NULL,
+ &DataPtr1Size,
+ &DataPtr1
+ );
+ if (!EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR,"Get Variable ok\n"));
+
+ }
+
+ if (SATAENABLE == DataPtr1) {
+ Status = gBS->InstallProtocolInterface (
+ &ImageHandle,
+ &gSataEnableFlagProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ if (!EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR,"Install SataEnableFlag Protocol ok, %r\n",Status));
+
+ }
+ DEBUG((EFI_D_ERROR, "Current SataEnable Flag is Sata, try to uninstall Sas SSDT table\n"));
+ SsdtName = EFI_SAS_SIGNATURE;
+ }
+ else {
+ DEBUG((EFI_D_ERROR, "Current SataEnable Flag is Sas, try to uninstall Sata SSDT table\n"));
+ SsdtName = EFI_SATA_SIGNATURE;
+ }
+
+ //Locate AcpiTableProtocol
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
+ if (EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR,"Unable to locate ACPI table protocol\n"));
+ return EFI_ABORTED;
+ }
+ //
+ // Find the Acpi Sdt protocol
+ Status = gBS->LocateProtocol(&gEfiAcpiSdtProtocolGuid, NULL, (VOID**) &AcpiTableProtocol);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR,"Unable to locate ACPI Sdt protocol\n"));
+ return EFI_ABORTED;
+ }
+
+ //
+ // Search for SSDT Table and delete the matched SSDT table
+ for (i = 0; i < EFI_ACPI_MAX_NUM_TABLES; i++) {
+ Status = AcpiTableProtocol->GetAcpiTable(i, &Table, &TableVersion, &TableKey);
+ if (EFI_ERROR(Status))
+ break;
+ if (Table->Signature == EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
+
+ if(*(UINT64*)Table->OemTableId == SsdtName) {
+ Status = AcpiTable->UninstallAcpiTable (AcpiTable, TableKey);
+ if (!EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR,"Successfully remove the SSDT table\n"));
+ return EFI_SUCCESS;
+ }
+ }
+ }
+
+ }
+ return EFI_SUCCESS;
+
+}
+
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.h b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.h
new file mode 100644
index 0000000..67e89e4
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.h
@@ -0,0 +1,30 @@
+/*
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#ifndef _EFI_UNINSTALL_ACPI_H_
+#define _EFI_UNINSTALL_ACPI_H_
+
+#define EFI_SATA_CONTROL_GUID \
+ { \
+ 0x287e41a8, 0x5108, 0x4faf, { 0xbe, 0x3d, 0xd4, 0xdd, 0xff, 0xcd, 0x4e, 0x9f } \
+ }
+
+#define SATA_ENABLE_FLAG (L"SataEnableFlag")
+#define EFI_SAS_SIGNATURE SIGNATURE_32 ('S', 'A', 'S', '0')
+#define EFI_SATA_SIGNATURE SIGNATURE_32 ('S', 'A', 'T', 'A')
+#define SATAENABLE 1
+#define SATADISABLE 0
+
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf
new file mode 100644
index 0000000..f83dd28
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf
@@ -0,0 +1,57 @@
+#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = UnInstallSsdt
+ FILE_GUID = E39977F0-20A4-4551-B0ED-BCE246592E78
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = UnInstallSsdtTable
+
+[Sources.common]
+ UnInstallAcpiTable.c
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ DebugLib
+ BaseLib
+ DxeServicesTableLib
+
+[Guids]
+ gEfiAcpiTableGuid
+ gEfiAcpi20TableGuid
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid
+ gEfiAcpiSdtProtocolGuid
+ gSataEnableFlagProtocolGuid
+
+[Pcd]
+
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiVariableArchProtocolGuid
+
+
diff --git a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h
new file mode 100644
index 0000000..070934b
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h
@@ -0,0 +1,127 @@
+/** @file
+*
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _SERDES_LIB_H_
+#define _SERDES_LIB_H_
+
+
+typedef enum hilink0_mode_type
+{
+ EM_HILINK0_PCIE1_8LANE = 0,
+ EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 1,
+}hilink0_mode_type_e;
+
+typedef enum hilink1_mode_type
+{
+ EM_HILINK1_PCIE0_8LANE = 0,
+ EM_HILINK1_HCCS_8LANE = 1,
+}hilink1_mode_type_e;
+
+typedef enum hilink2_mode_type
+{
+ EM_HILINK2_PCIE2_8LANE = 0,
+ EM_HILINK2_SAS0_8LANE = 1,
+}hilink2_mode_type_e;
+
+typedef enum hilink3_mode_type
+{
+ EM_HILINK3_GE_4LANE = 0,
+ EM_HILINK3_GE_2LANE_XGE_2LANE = 1, //lane0,lane1-ge,lane2,lane3 xge
+}hilink3_mode_type_e;
+
+
+typedef enum hilink4_mode_type
+{
+ EM_HILINK4_GE_4LANE = 0,
+ EM_HILINK4_XGE_4LANE = 1,
+}hilink4_mode_type_e;
+
+typedef enum hilink5_mode_type
+{
+ EM_HILINK5_SAS1_4LANE = 0,
+ EM_HILINK5_PCIE3_4LANE = 1,
+}hilink5_mode_type_e;
+
+
+typedef struct serdes_param
+{
+ hilink0_mode_type_e hilink0_mode;
+ hilink1_mode_type_e hilink1_mode;
+ hilink2_mode_type_e hilink2_mode;
+ hilink3_mode_type_e hilink3_mode;
+ hilink4_mode_type_e hilink4_mode;
+ hilink5_mode_type_e hilink5_mode;
+}serdes_param_t;
+
+
+#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF
+#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF
+
+typedef struct {
+ UINT32 MacroId;
+ UINT32 DsNum;
+} SERDES_POLARITY_INVERT;
+
+
+EFI_STATUS OemGetSerdesParam (serdes_param_t *Param);
+extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
+extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
+UINT32 GetEthType(UINT8 EthChannel);
+
+EFI_STATUS
+EfiSerdesInitWrap (VOID);
+
+void serdes_state_show(UINT32 macro1);
+//uniBIOS__l00228991_start DTS2015042210118 2015-4-22 20:06:34
+
+void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg);
+//uniBIOS__l00228991_end DTS2015042210118 2015-4-22 20:06:34
+
+//uniBIOS_l00306713_000_start 2015-3-19 17:37:06
+
+//EYE test
+UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData);
+
+UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum);
+
+//PRBS test
+int serdes_prbs_test(UINT8 ulMacroId , UINT8 ulDsNum,UINT8 PrbsType);
+
+int serdes_prbs_test_cancle(UINT8 ulMacroId,UINT8 ulDsNum);
+
+//CTLE/DFE
+void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane);
+
+void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane);
+
+void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane);
+
+void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane);
+
+void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane);
+//uniBIOS_l00306713_000_end 2015-3-19 17:37:06
+
+
+//uniBIOS_l00306713_000_start 2015-7-15 9:13:55
+
+int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+
+int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+
+int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+//uniBIOS_l00306713_000_end 2015-7-15 9:13:55
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf b/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000..1096175
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf
@@ -0,0 +1,60 @@
+## @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Pv660AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt/Dsdt.asl
+ Facs.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Mcfg.aslc
+ Iort.asl
+ Spcr.aslc
+ Dbg2.aslc
+ SASSSDT.ASL
+ SATASSDT.ASL
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc
new file mode 100644
index 0000000..93b2c90
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc
@@ -0,0 +1,94 @@
+/** @file
+* Debug Port Table 2 (DBG2)
+*
+* Copyright (c) 2012 - 2014, Linaro Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Pv660Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/DebugPort2Table.h>
+
+#define NUMBER_DEBUG_DEVICE_INFO 1
+#define NUMBER_OF_GENERIC_ADDRESS 1
+#define NAMESPACE_STRING_SIZE 8
+
+#pragma pack(1)
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS];
+ UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS];
+ CHAR8 NamespaceString[NAMESPACE_STRING_SIZE];
+} EFI_ACPI_DBG2_DDI_STRUCT;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc;
+ EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO];
+} EFI_ACPI_DEBUG_PORT_2_TABLE;
+
+#pragma pack()
+
+EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = {
+ {
+ ARM_ACPI_HEADER(
+ EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_DEBUG_PORT_2_TABLE,
+ EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION
+ ),
+ OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi),
+ NUMBER_DEBUG_DEVICE_INFO
+ },
+ {
+ {
+ {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ sizeof(EFI_ACPI_DBG2_DDI_STRUCT),
+ NUMBER_OF_GENERIC_ADDRESS,
+ NAMESPACE_STRING_SIZE,
+ OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString),
+ 0, //OemDataLength
+ 0, //OemDataOffset
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550,
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+ OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address),
+ OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize),
+ },
+ {
+ {
+ EFI_ACPI_6_0_SYSTEM_MEMORY,
+ 32,
+ 0,
+ EFI_ACPI_6_0_BYTE,
+ FixedPcdGet64(PcdSerialRegisterBase)
+ }
+ },
+ {
+ 0x1000
+ },
+ "COM0"
+ }
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Dbg2;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl
new file mode 100644
index 0000000..e995295
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl
@@ -0,0 +1,88 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ //
+ // A57x16 Processor declaration
+ //
+ Device(CPU0) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ Device(CPU1) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ }
+ Device(CPU2) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ }
+ Device(CPU3) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ }
+ Device(CPU4) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 4)
+ }
+ Device(CPU5) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 5)
+ }
+ Device(CPU6) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 6)
+ }
+ Device(CPU7) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 7)
+ }
+ Device(CPU8) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 8)
+ }
+ Device(CPU9) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 9)
+ }
+ Device(CP10) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 10)
+ }
+ Device(CP11) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 11)
+ }
+ Device(CP12) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 12)
+ }
+ Device(CP13) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 13)
+ }
+ Device(CP14) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 14)
+ }
+ Device(CP15) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 15)
+ }
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
new file mode 100644
index 0000000..43027e4
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
@@ -0,0 +1,37 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ // UART 8250
+ Device(COM0) {
+ Name(_HID, "APMC0D08") //Or AMD0020, trick to use dw8250 serial driver
+ Name(_CID, "8250dw")
+ Name(_UID, Zero)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x80300000, 0x1000) //0x7FF80000, 0x1000
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-frequency", 200000000},
+ }
+ })
+ }
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl
new file mode 100644
index 0000000..5188060
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl
@@ -0,0 +1,38 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ // sysctl dsa
+ Device(CTL0) {
+ Name(_HID, "HISI0061")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xC0000000, 0x10000)
+ })
+ }
+ // sysctl pcie
+ Device(CTL1) {
+ Name(_HID, "HISI0061")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xB0000000, 0x10000)
+ })
+ }
+ // sysctl peri_c
+ Device(CTL2) {
+ Name(_HID, "HISI0061")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x80000000, 0x10000)
+ })
+ }
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl
new file mode 100644
index 0000000..ce5a085
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl
@@ -0,0 +1,29 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include "Pv660Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI-D02", EFI_ACPI_ARM_OEM_REVISION) {
+ include ("Mbig.asl")
+ include ("CPU.asl")
+ include ("Com.asl")
+ include ("Usb.asl")
+ include ("Ctl.asl")
+ include ("Hns.asl")
+ include ("Pci.asl")
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl
new file mode 100644
index 0000000..5945fc3
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl
@@ -0,0 +1,952 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ Device (MDIO)
+ {
+ OperationRegion(CLKR, SystemMemory, 0x80000338, 8)
+ Field(CLKR, DWordAcc, NoLock, Preserve) {
+ CLKE, 1, // clock enable
+ , 31,
+ CLKD, 1, // clode disable
+ , 31,
+ }
+ OperationRegion(RSTR, SystemMemory, 0x80000A38, 8)
+ Field(RSTR, DWordAcc, NoLock, Preserve) {
+ RSTE, 1, // reset
+ , 31,
+ RSTD, 1, // de-reset
+ , 31,
+ }
+
+ Name(_HID, "HISI0141")
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0x803c0000 , 0x10000)
+ })
+
+ Method(_RST, 0, Serialized) {
+ Store (0x1, RSTE)
+ Sleep (10)
+ Store (0x1, CLKD)
+ Sleep (10)
+ Store (0x1, RSTD)
+ Sleep (10)
+ Store (0x1, CLKE)
+ Sleep (10)
+ }
+ }
+
+ Device (DSF0)
+ {
+ OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
+ Field(H3SR, DWordAcc, NoLock, Preserve) {
+ H3ST, 1,
+ , 31, //RESERVED
+ }
+ OperationRegion(H4SR, SystemMemory, 0xC0000190, 4)
+ Field(H4SR, DWordAcc, NoLock, Preserve) {
+ H4ST, 1,
+ , 31, //RESERVED
+ }
+ // DSAF RESET
+ OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
+ Field(DRER, DWordAcc, NoLock, Preserve) {
+ DRTE, 1,
+ , 31, //RESERVED
+ DRTD, 1,
+ , 31, //RESERVED
+ }
+ // NT RESET
+ OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
+ Field(NRER, DWordAcc, NoLock, Preserve) {
+ NRTE, 1,
+ , 31, //RESERVED
+ NRTD, 1,
+ , 31, //RESERVED
+ }
+ // XGE RESET
+ OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+ Field(XRER, DWordAcc, NoLock, Preserve) {
+ XRTE, 31,
+ , 1, //RESERVED
+ XRTD, 31,
+ , 1, //RESERVED
+ }
+
+ // GE RESET
+ OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+ Field(GRTR, DWordAcc, NoLock, Preserve) {
+ GR0E, 30,
+ , 2, //RESERVED
+ GR0D, 30,
+ , 2, //RESERVED
+ GR1E, 18,
+ , 14, //RESERVED
+ GR1D, 18,
+ , 14, //RESERVED
+ }
+ // PPE RESET
+ OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+ Field(PRTR, DWordAcc, NoLock, Preserve) {
+ PRTE, 10,
+ , 22, //RESERVED
+ PRTD, 10,
+ , 22, //RESERVED
+ }
+
+ // RCB PPE COM RESET
+ OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
+ Field(RRTR, DWordAcc, NoLock, Preserve) {
+ RRTE, 1,
+ , 31, //RESERVED
+ RRTD, 1,
+ , 31, //RESERVED
+ }
+
+ // ROCE
+
+ // CPLD LED
+
+ // Serdes
+ OperationRegion(H4LR, SystemMemory, 0xC2288100, 0x1000)
+ Field(H4LR, DWordAcc, NoLock, Preserve) {
+ H4L0, 16, // port0
+ H4R0, 16, //RESERVED
+ Offset (0x400),
+ H4L1, 16, // port1
+ H4R1, 16, //RESERVED
+ Offset (0x800),
+ H4L2, 16, // port2
+ H4R2, 16, //RESERVED
+ Offset (0xc00),
+ H4L3, 16, // port3
+ H4R3, 16, //RESERVED
+ }
+ OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
+ Field(H3LR, DWordAcc, NoLock, Preserve) {
+ H3L2, 16, // port4
+ , 16, //RESERVED
+ Offset (0x400),
+ H3L3, 16, // port5
+ , 16, //RESERVED
+ }
+ Name (_HID, "HISI00B1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
+ Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 149,150,151,152,153,154,26,27,155,156,157,158,159,160, //[14] ge fifo err 8 / xge 6
+ 6,7,8,9,16,17,18,19,22,23,24,25, //[12] rcb com 4*3
+ 0,1,2,3,4,5,12,13, //[8] ppe tnl 0-7
+ 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, //[21] dsaf event int 3+18
+ 161,162,163,164,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, //[256] sevice rcb 2*128
+ 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415,
+ 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431,
+ 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447,
+ 448, 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463,
+ 464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479,
+ 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495,
+ 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511,
+ 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 527,
+ 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543,
+ 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559,
+ 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575,
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"mode", "6port-16rss"},
+ Package () {"buf-size", 4096},
+ Package () {"desc-num", 1024},
+ Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+ }
+ })
+
+ //reset XGE port
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XRST, 2, Serialized) {
+ ShiftLeft (0x2082082, Arg0, Local0)
+ Or (Local0, 0x1, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset XGE core
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XCRT, 2, Serialized) {
+ ShiftLeft (0x2080, Arg0, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset GE port
+ //Arg0 : GE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(GRST, 2, Serialized) {
+ If (LLessEqual (Arg0, 5)) {
+ //Service port
+ ShiftLeft (0x1041041, Arg0, Local0)
+ ShiftLeft (0x1, Arg0, Local1)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local1, GR1E)
+ Store(Local0, GR0E)
+ } Else {
+ Store(Local0, GR0D)
+ Store(Local1, GR1D)
+ }
+ }
+ }
+
+ //reset PPE port
+ //Arg0 : PPE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(PRST, 2, Serialized) {
+ ShiftLeft (0x1, Arg0, Local0)
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, PRTE)
+ } Else {
+ Store(Local0, PRTD)
+ }
+ }
+
+ // Set Serdes Loopback
+ //Arg0 : port
+ //Arg1 : 0 disable, 1 enable
+ Method(SRLP, 2, Serialized) {
+ ShiftLeft (Arg1, 10, Local0)
+ Switch (ToInteger(Arg0))
+ {
+ case (0x0){
+ Store (H4L0, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H4L0)
+ }
+ case (0x1){
+ Store (H4L1, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H4L1)
+ }
+ case (0x2){
+ Store (H4L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H4L2)
+ }
+ case (0x3){
+ Store (H4L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H4L3)
+ }
+ case (0x4){
+ Store (H3L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H3L2)
+ }
+ case (0x5){
+ Store (H3L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H3L3)
+ }
+ }
+ }
+
+ //Reset
+ //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
+ //Arg1 : port
+ //Arg2 : 0 disable, 1 enable
+ Method(DRST, 3, Serialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ //DSAF reset
+ case (0x1)
+ {
+ Store (Arg2, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Store (0x1, DRTE)
+ Store (0x1, NRTE)
+ Sleep (10)
+ Store (0x1, RRTE)
+ }
+ Else
+ {
+ Store (0x1, DRTD)
+ Store (0x1, NRTD)
+ Sleep (10)
+ Store (0x1, RRTD)
+ }
+ }
+ //Reset PPE port
+ case (0x2)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ PRST (Local0, Local1)
+ }
+
+ //Reset XGE core
+ case (0x3)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XCRT (Local0, Local1)
+ }
+ //Reset XGE port
+ case (0x4)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XRST (Local0, Local1)
+ }
+
+ //Reset GE port
+ case (0x5)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ GRST (Local0, Local1)
+ }
+ }
+ }
+
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index
+ // 0 : Return Supported Functions bit mask
+ // 1 : Reset Sequence
+ // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
+ // Arg3[1] : port index in dsaf
+ // Arg3[2] : 0 reset, 1 cancle reset
+ // 2 : Set Serdes Loopback
+ // Arg3[0] : port
+ // Arg3[1] : 0 disable, 1 enable
+ // 3 : LED op set
+ // Arg3[0] : op type
+ // Arg3[1] : port
+ // Arg3[2] : para
+ // 4 : Get port type (GE or XGE)
+ // Arg3[0] : port index in dsaf
+ // Return : 0 GE, 1 XGE
+ // 5 : Get sfp status
+ // Arg3[0] : port index in dsaf
+ // Return : 0 no sfp, 1 have sfp
+ // Arg3: Package Parameters
+ Method (_DSM, 4, Serialized)
+ {
+ If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+ {
+ If (LEqual (Arg1, 0x00))
+ {
+ Switch (ToInteger(Arg2))
+ {
+ case (0x0)
+ {
+ Return (Buffer () {0x3F})
+ }
+
+ //Reset Sequence
+ case (0x1)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ Store (DeRefOf (Index (Arg3, 2)), Local2)
+ DRST (Local0, Local1, Local2)
+ }
+
+ //Set Serdes Loopback
+ case (0x2)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ SRLP (Local0, Local1)
+ }
+
+ //LED op set
+ case (0x3)
+ {
+
+ }
+
+ // Get port type (GE or XGE)
+ case (0x4)
+ {
+ Store (0, Local1)
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ If (LLessEqual (Local0, 3))
+ {
+ Store (H4ST, Local1)
+ }
+ ElseIf (LLessEqual (Local0, 5))
+ {
+ Store (H3ST, Local1)
+ }
+
+ Return (Local1)
+ }
+
+ //Get sfp status
+ case (0x5)
+ {
+
+ }
+ }
+ }
+ }
+ Return (Buffer() {0x00})
+ }
+ Device (PRT0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ }
+ })
+ }
+ Device (PRT1)
+ {
+ Name (_ADR, 0x1)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 1},
+ }
+ })
+ }
+ Device (PRT4)
+ {
+ Name (_ADR, 0x4)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 4},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 0},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ }
+ })
+ }
+ Device (PRT5)
+ {
+ Name (_ADR, 0x5)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 5},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 1},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ }
+ })
+ }
+ }
+/*
+ Device (DSF1)
+ {
+ OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
+ Field(H3SR, DWordAcc, NoLock, Preserve) {
+ H3ST, 1,
+ , 31, //RESERVED
+ }
+
+ // XGE RESET
+ OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+ Field(XRER, DWordAcc, NoLock, Preserve) {
+ XRTE, 31,
+ , 1, //RESERVED
+ XRTD, 31,
+ , 1, //RESERVED
+ }
+
+ // GE RESET
+ OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+ Field(GRTR, DWordAcc, NoLock, Preserve) {
+ GR0E, 30,
+ , 2, //RESERVED
+ GR0D, 30,
+ , 2, //RESERVED
+ GR1E, 18,
+ , 14, //RESERVED
+ GR1D, 18,
+ , 14, //RESERVED
+ }
+
+ // PPE RESET
+ OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+ Field(PRTR, DWordAcc, NoLock, Preserve) {
+ PRTE, 10,
+ , 22, //RESERVED
+ PRTD, 10,
+ , 22, //RESERVED
+ }
+
+ // ROCE
+
+ // CPLD LED
+
+ // Serdes
+ OperationRegion(H3LR, SystemMemory, 0xC2208100, 0x4)
+ Field(H3LR, DWordAcc, NoLock, Preserve) {
+ H3L0, 16, // debug port0
+ , 16, //RESERVED
+ }
+ Name(_HID, "HISI00B1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc2000000 , 0x890000)
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 14, 15,
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"mode", "single-port"},
+ Package () {"buf-size", 4096},
+ Package () {"desc-num", 1024},
+ Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+ }
+ })
+
+ // Set Serdes Loopback
+ //Arg0 : port
+ //Arg1 : 0 disable, 1 enable
+ Method(SRLP, 1, Serialized) {
+ ShiftLeft (Arg0, 10, Local0)
+ Store (H3L0, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H3L0)
+ }
+
+ //Reset
+ //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3)
+ //Arg1 : 0 disable, 1 enable
+ Method(DRST, 2, Serialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ //DSAF reset
+ case (0x1)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store (0x100, PRTE)
+ } Else {
+ Store (0x100, PRTD)
+ }
+ }
+ //Reset PPE port
+ case (0x2)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store(0x40, PRTE)
+ } Else {
+ Store(0x40, PRTD)
+ }
+ }
+
+ //Reset GE port
+ case (0x5)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store(0x15540, GR1E)
+ Store(0x100, PRTE)
+ } Else {
+ Store(0x15540, GR1D)
+ Store(0x100, PRTD)
+ }
+ }
+ }
+ }
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index
+ // 0 : Return Supported Functions bit mask
+ // 1 : Reset Sequence
+ // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge)
+ // Arg3[1] : reserved
+ // Arg3[2] : 0 reset, 1 cancle reset
+ // 2 : Set Serdes Loopback
+ // Arg3[0] : reserved
+ // Arg3[1] : 0 disable, 1 enable
+ // 3 : LED op set
+ // Arg3[0] : op type
+ // Arg3[1] : reserved
+ // Arg3[2] : para
+ // 4 : Get port type (GE or XGE)
+ // Arg3[0] : reserved
+ // Return : 0 GE, 1 XGE
+ // 5 : Get sfp status
+ // Arg3[0] : reserved
+ // Return : 0 no sfp, 1 have sfp
+ // Arg3: Package Parameters
+ Method (_DSM, 4, Serialized)
+ {
+ If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+ {
+ If (LEqual (Arg1, 0x00))
+ {
+ Switch (ToInteger(Arg2))
+ {
+ case (0x0)
+ {
+ Return (Buffer () {0x3F})
+ }
+
+ //Reset Sequence
+ case (0x1)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 2)), Local2)
+ DRST (Local0, Local2)
+ }
+
+ //Set Serdes Loopback
+ case (0x2)
+ {
+ Store (DeRefOf (Index (Arg3, 2)), Local0)
+ SRLP (Local0)
+ }
+
+ //LED op set
+ case (0x3)
+ {
+
+ }
+
+ // Get port type (GE or XGE)
+ case (0x4)
+ {
+ Store (H3ST, Local0)
+ Return (Local0)
+ }
+
+ //Get sfp status
+ case (0x5)
+ {
+
+ }
+ }
+ }
+ }
+ Return (Buffer() {0x00})
+ }
+
+ Device (PRT0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 0},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ }
+ })
+ }
+ }
+ Device (DSF2)
+ {
+ OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
+ Field(H3SR, DWordAcc, NoLock, Preserve) {
+ H3ST, 1,
+ , 31, //RESERVED
+ }
+
+ // XGE RESET
+ OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+ Field(XRER, DWordAcc, NoLock, Preserve) {
+ XRTE, 31,
+ , 1, //RESERVED
+ XRTD, 31,
+ , 1, //RESERVED
+ }
+
+ // GE RESET
+ OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+ Field(GRTR, DWordAcc, NoLock, Preserve) {
+ GR0E, 30,
+ , 2, //RESERVED
+ GR0D, 30,
+ , 2, //RESERVED
+ GR1E, 18,
+ , 14, //RESERVED
+ GR1D, 18,
+ , 14, //RESERVED
+ }
+
+ // PPE RESET
+ OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+ Field(PRTR, DWordAcc, NoLock, Preserve) {
+ PRTE, 10,
+ , 22, //RESERVED
+ PRTD, 10,
+ , 22, //RESERVED
+ }
+
+ // ROCE
+
+ // CPLD LED
+
+ // Serdes
+ OperationRegion(H3LR, SystemMemory, 0xC2208500, 0x4)
+ Field(H3LR, DWordAcc, NoLock, Preserve) {
+ H3L1, 16, // debug port1
+ , 16, //RESERVED
+ }
+ Name(_HID, "HISI00B1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc2100000 , 0x890000)
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 20, 21,
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"mode", "single-port"},
+ Package () {"buf-size", 4096},
+ Package () {"desc-num", 1024},
+ Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+ }
+ })
+
+ // Set Serdes Loopback
+ //Arg0 : port
+ //Arg1 : 0 disable, 1 enable
+ Method(SRLP, 1, Serialized) {
+ ShiftLeft (Arg0, 10, Local0)
+ Store (H3L1, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H3L1)
+ }
+
+ //Reset
+ //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3)
+ //Arg1 : 0 disable, 1 enable
+ Method(DRST, 2, Serialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ //DSAF reset
+ case (0x1)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store (0x200, PRTE)
+ } Else {
+ Store (0x2200, PRTD)
+ }
+ }
+
+ //Reset PPE port
+ case (0x2)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store(0x80, PRTE)
+ } Else {
+ Store(0x80, PRTD)
+ }
+ }
+
+ //Reset GE port
+ case (0x5)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store(0x2aa80, GR1E)
+ Store(0x200, PRTE)
+ } Else {
+ Store(0x2aa80, GR1D)
+ Store(0x200, PRTD)
+ }
+ }
+ }
+ }
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index
+ // 0 : Return Supported Functions bit mask
+ // 1 : Reset sequence
+ // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge)
+ // Arg3[1] : reserved
+ // Arg3[2] : 0 reset, 1 cancle reset
+ // 2 : Set Serdes Loopback
+ // Arg3[0] : reserved
+ // Arg3[1] : 0 disable, 1 enable
+ // 3 : LED op set
+ // Arg3[0] : op type
+ // Arg3[1] : reserved
+ // Arg3[2] : para
+ // 4 : Get port type (GE or XGE)
+ // Arg3[0] : reserved
+ // Return : 0 GE, 1 XGE
+ // 5 : Get sfp status
+ // Arg3[0] : reserved
+ // Return : 0 no sfp, 1 have sfp
+ // Arg3: Package Parameters
+ Method (_DSM, 4, Serialized)
+ {
+ If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+ {
+ If (LEqual (Arg1, 0x00))
+ {
+ Switch (ToInteger(Arg2))
+ {
+ case (0x0)
+ {
+ Return (Buffer () {0x3F})
+ }
+
+ //Reset Sequence
+ case (0x1)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 2)), Local2)
+ DRST (Local0, Local2)
+ }
+
+ //Set Serdes Loopback
+ case (0x2)
+ {
+ Store (DeRefOf (Index (Arg3, 2)), Local0)
+ SRLP (Local0)
+ }
+
+ //LED op set
+ case (0x3)
+ {
+
+ }
+
+ // Get port type (GE or XGE)
+ case (0x4)
+ {
+ Store (H3ST, Local0)
+ Return (Local0)
+ }
+
+ //Get sfp status
+ case (0x5)
+ {
+
+ }
+ }
+ }
+ }
+ Return (Buffer() {0x00})
+ }
+
+ Device (PRT0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 1},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ }
+ })
+ }
+ }
+*/
+ Device (ETH5) {
+ Name(_HID, "HISI00C1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 5},
+ }
+ })
+ }
+ Device (ETH4) {
+ Name(_HID, "HISI00C1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 4},
+ }
+ })
+ }
+ Device (ETH0) {
+ Name(_HID, "HISI00C1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 0},
+ }
+ })
+ }
+ Device (ETH1) {
+ Name(_HID, "HISI00C1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 1},
+ }
+ })
+ }
+
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl
new file mode 100644
index 0000000..e7d3f72
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl
@@ -0,0 +1,86 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ // Mbi-gen totem
+ Device(MBI0) {
+ Name(_HID, "HISI0151")
+ Name(_CID, "MBIGen")
+ Name(_UID, 0)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x8c030000, 0x10000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 256}
+ }
+ })
+ }
+
+ // mbi-gen dsa
+ Device(MBI1) {
+ Name(_HID, "HISI0151")
+ Name(_CID, "MBIGen")
+ Name(_UID, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc6030000, 0x10000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 640}
+ }
+ })
+ }
+
+ // mbi-gen m3
+ Device(MBI2) {
+ Name(_HID, "HISI0151")
+ Name(_CID, "MBIGen")
+ Name(_UID, 2)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xa3030000, 0x10000)
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 256}
+ }
+ })
+ }
+
+ // mbi-gen pcie
+ Device(MBI3) {
+ Name(_HID, "HISI0151")
+ Name(_CID, "MBIGen")
+ Name(_UID, 3)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xb7030000, 0x10000)
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 640}
+ }
+ })
+ }
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl
new file mode 100644
index 0000000..244ff93
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl
@@ -0,0 +1,181 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+Scope(_SB)
+{
+ // PCIe Root bus
+ Device (PCI1)
+ {
+ Name (_HID, "HISI0080") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 1) // Segment of this Root complex
+ Name(_BBN, 64) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 64, // AddressMinimum - Minimum Bus Number
+ 127, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 64 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x00000000b0000000, // Min Base Address pci address
+ 0x00000000b7feffff, // Max Base Address
+ 0x0000021f58000000, // Translate
+ 0x0000000007ff0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Min Base Address
+ 0x000000000000ffff, // Max Base Address
+ 0x000002200fff0000, // Translate
+ 0x0000000000010000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+
+ Device (RES1)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xb0080000 , 0x10000)
+ })
+ }
+
+ OperationRegion(SCTR, SystemMemory, 0xb0006918, 4)
+ Field(SCTR, AnyAcc, NoLock, Preserve) {
+ LSTA, 32,
+ }
+ Method(_DSM, 0x4, Serialized) {
+ If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
+
+ switch(ToInteger(Arg2))
+ {
+ // Function 0: Return LinkStatus
+ case(0) {
+ Store (0, Local0)
+ Store (LSTA, Local0)
+ Return (Local0)
+ }
+ default {
+ }
+ }
+ }
+ // If not one of the function identifiers we recognize, then return a buffer
+ // with bit 0 set to 0 indicating no functions supported.
+ return(Buffer(){0})
+ }
+ } // Device(PCI1)
+
+ // PCIe Root bus
+ Device (PCI2)
+ {
+ Name (_HID, "HISI0080") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 2) // Segment of this Root complex
+ Name(_BBN, 128) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 128, // AddressMinimum - Minimum Bus Number
+ 191, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 64 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x00000000c0000000, // Min Base Address
+ 0x00000000c3feffff, // Max Base Address
+ 0x0000023f4c000000, // Translate
+ 0x0000000003ff0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Min Base Address
+ 0x000000000000ffff, // Max Base Address
+ 0x000002400fff0000, // Translate
+ 0x0000000000010000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+
+ Device (RES2)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xb0090000 , 0x10000)
+ })
+ }
+
+ OperationRegion(SCTR, SystemMemory, 0xb0006a18, 4)
+ Field(SCTR, AnyAcc, NoLock, Preserve) {
+ LSTA, 32,
+ }
+ Method(_DSM, 0x4, Serialized) {
+ If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949")))
+ {
+ switch(ToInteger(Arg2))
+ {
+ // Function 0: Return LinkStatus
+ case(0) {
+ Store (0, Local0)
+ Store (LSTA, Local0)
+ Return (Local0)
+ }
+ default {
+ }
+ }
+ }
+ // If not one of the function identifiers we recognize, then return a buffer
+ // with bit 0 set to 0 indicating no functions supported.
+ return(Buffer(){0})
+ }
+ } // Device(PCI2)
+}
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl
new file mode 100644
index 0000000..4c3c642
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl
@@ -0,0 +1,152 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ Device(SAS0) {
+ Name(_HID, "HISI0161")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc1000000, 0x10000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ //phy irq(0~79)
+ 259,263,264,
+ 269,273,274,
+ 279,283,284,
+ 289,293,294,
+ 299,303,304,
+ 309,313,314,
+ 319,323,324,
+ 329,333,334,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ //cq irq (80~111)
+ 336,337,338,339,340,341,342,343,
+ 344,345,346,347,348,349,350,351,
+ 352,353,354,355,356,357,358,359,
+ 360,361,362,363,364,365,366,367,
+ }
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 376, //chip fatal error irq(120)
+ 381, //chip fatal error irq(125)
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-parent",Package() {\_SB.MBI1}},
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x0a}},
+ Package () {"queue-count", 32},
+ Package () {"phy-count", 8},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x338),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xa60),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a30),
+ STS, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ }
+ }
+
+ Device(SAS1) {
+ Name(_HID, "HISI0161")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xb1000000, 0x10000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ //phy irq(0~79)
+ 259,263,264,
+ 269,273,274,
+ 279,283,284,
+ 289,293,294,
+ 299,303,304,
+ 309,313,314,
+ 319,323,324,
+ 329,333,334,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ //cq irq (80~111)
+ 336,337,338,339,340,341,342,343,
+ 344,345,346,347,348,349,350,351,
+ 352,353,354,355,356,357,358,359,
+ 360,361,362,363,364,365,366,367,
+ }
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 376, //chip fatal error irq(120)
+ 381, //chip fatal error irq(125)
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-parent",Package() {\_SB.MBI3}},
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+ Package () {"queue-count", 32},
+ Package () {"phy-count", 8},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xB0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x318),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xa18),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a0c),
+ STS, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ }
+ }
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl
new file mode 100644
index 0000000..9ad2d96
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl
@@ -0,0 +1,39 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+//
+// SATA AHCI
+//
+
+Device (AHCI)
+{
+ Name(_HID, "HISI0001") // HiSi AHCI
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xb1002800, 0x00000B00)
+ Memory32Fixed (ReadWrite, 0xb1000000, 0x00002800)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 382 }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-parent",Package() {\_SB.MBI3}}
+ }
+ })
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl
new file mode 100644
index 0000000..a0082af
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl
@@ -0,0 +1,136 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+ Device (USB0)
+ {
+ Name (_HID, "PNP0D20") // _HID: Hardware ID
+ Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xA1000000, // Address Base
+ 0x00010000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
+ }
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"interrupt-parent",Package() {\_SB.MBI2}}
+ }
+ })
+
+ Device (RHUB)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Device (PRT1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ 0xFF,
+ Zero,
+ Zero,
+ Zero
+ })
+ Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
+ {
+ ToPLD (
+ PLD_Revision = 0x1,
+ PLD_IgnoreColor = 0x1,
+ PLD_Red = 0x0,
+ PLD_Green = 0x0,
+ PLD_Blue = 0x0,
+ PLD_Width = 0x0,
+ PLD_Height = 0x0,
+ PLD_UserVisible = 0x1,
+ PLD_Dock = 0x0,
+ PLD_Lid = 0x0,
+ PLD_Panel = "UNKNOWN",
+ PLD_VerticalPosition = "UPPER",
+ PLD_HorizontalPosition = "LEFT",
+ PLD_Shape = "UNKNOWN",
+ PLD_GroupOrientation = 0x0,
+ PLD_GroupToken = 0x0,
+ PLD_GroupPosition = 0x0,
+ PLD_Bay = 0x0,
+ PLD_Ejectable = 0x0,
+ PLD_EjectRequired = 0x0,
+ PLD_CabinetNumber = 0x0,
+ PLD_CardCageNumber = 0x0,
+ PLD_Reference = 0x0,
+ PLD_Rotation = 0x0,
+ PLD_Order = 0x0,
+ PLD_VerticalOffset = 0x0,
+ PLD_HorizontalOffset = 0x0)
+
+ })
+ }
+
+ Device (PRT2)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+
+ Device (PRT3)
+ {
+ Name (_ADR, 0x03) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+
+ Device (PRT4)
+ {
+ Name (_ADR, 0x04) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+ }
+ }
+}
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc
new file mode 100644
index 0000000..72cc66c
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc
@@ -0,0 +1,67 @@
+/** @file
+* Firmware ACPI Control Structure (FACS)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
+ sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length
+ 0xA152, // UINT32 HardwareSignature
+ 0, // UINT32 FirmwareWakingVector
+ 0, // UINT32 GlobalLock
+ 0, // UINT32 Flags
+ 0, // UINT64 XFirmwareWakingVector
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;
+ { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1]
+ EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]
+ 0, // UINT32 OspmFlags "Platform firmware must
+ // initialize this field to zero."
+ { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22]
+ EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23]
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Facs;
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc
new file mode 100644
index 0000000..5907c65
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc
@@ -0,0 +1,92 @@
+/** @file
+* Fixed ACPI Description Table (FADT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+//#include "ArmPlatform.h"
+#include "Pv660Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000..3caf144
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc
@@ -0,0 +1,96 @@
+/** @file
+* Generic Timer Description Table (GTDT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Pv660Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[PV660_WATCHDOG_COUNT];
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+ {
+ ARM_ACPI_HEADER(
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE,
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+#ifdef notyet
+ PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
+ sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+ },
+ {
+ EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+ //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
+ 0, 0, 0, 0),
+ EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+ //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
+ 0, 0, 0, 0)
+ }
+#else /* !notyet */
+ 0, 0
+ }
+#endif
+ };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl
new file mode 100644
index 0000000..44056b5
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl
@@ -0,0 +1,274 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20151124-64
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Template for [IORT] ACPI Table (static data table)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+[0004] Signature : "IORT" [IO Remapping Table]
+[0004] Table Length : 0000010C
+[0001] Revision : 00
+[0001] Checksum : BC
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20150410
+
+[0004] Node Count : 0000000A
+[0004] Node Offset : 00000034
+[0004] Reserved : 00000000
+[0004] Optional Padding : 00 00 00 00
+
+/* ITS 0, for totem */
+[0001] Type : 00
+[0002] Length : 0018
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000000
+[0004] Mapping Offset : 00000000
+
+[0004] ItsCount : 00000001
+[0004] Identifiers : 00000000
+
+/* ITS 1, for dsa */
+[0001] Type : 00
+[0002] Length : 0018
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000000
+[0004] Mapping Offset : 00000000
+
+[0004] ItsCount : 00000001
+[0004] Identifiers : 00000001
+
+/* ITS 2, m3 */
+[0001] Type : 00
+[0002] Length : 0018
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000000
+[0004] Mapping Offset : 00000000
+
+[0004] ItsCount : 00000001
+[0004] Identifiers : 00000002
+
+/* ITS 3, pcie */
+[0001] Type : 00
+[0002] Length : 0018
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000000
+[0004] Mapping Offset : 00000000
+
+[0004] ItsCount : 00000001
+[0004] Identifiers : 00000003
+
+/* mbi-gen pc, named component */
+[0001] Type : 01
+[0002] Length : 003B
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000027
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0012] Device Name : "\_SB_.MBI0"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000FFCC
+[0004] Output Reference : 00000034 // point to its totem
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* mbi-gen dsa, named component */
+[0001] Type : 01
+[0002] Length : 003B
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000027
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0011] Device Name : "\_SB_.MBI1"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000FFCC
+[0004] Output Reference : 0000004C
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* mbi-gen m3, named component */
+[0001] Type : 01
+[0002] Length : 003B
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000027
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0011] Device Name : "\_SB_.MBI2"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000FFCC
+[0004] Output Reference : 00000064
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* mbi-gen pcie, named component */
+[0001] Type : 01
+[0002] Length : 003B
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000027
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0011] Device Name : "\_SB_.MBI3"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000FFCC
+[0004] Output Reference : 0000007C
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+ /* RC 0 */
+[0001] Type : 02
+[0002] Length : 0034
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000020
+
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000001
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0004] ATS Attribute : 00000000
+[0004] PCI Segment Number : 00000001
+
+[0004] Input base : 00004000
+[0004] ID Count : 00004000
+[0004] Output Base : 00004000
+[0004] Output Reference : 0000007C
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* RC 1 */
+[0001] Type : 02
+[0002] Length : 0034
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000020
+
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000001
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0004] ATS Attribute : 00000000
+[0004] PCI Segment Number : 00000002
+
+[0004] Input base : 00008000
+[0004] ID Count : 00004000
+[0004] Output Base : 00008000
+[0004] Output Reference : 0000007C
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/*
+[0001] Type : 03
+[0002] Length : 005C
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000000
+[0004] Mapping Offset : 0000005C
+
+[0008] Base Address : 0000000000000000
+[0008] Span : 0000000000000000
+[0004] Model : 00000000
+[0004] Flags (decoded below) : 00000000
+ DVM Supported : 0
+ Coherent Walk : 0
+[0004] Global Interrupt Offset : 0000003C
+[0004] Context Interrupt Count : 00000001
+[0004] Context Interrupt Offset : 0000004C
+[0004] PMU Interrupt Count : 00000001
+[0004] PMU Interrupt Offset : 00000054
+
+[0008] SMMU_NSgIrpt Interrupt : 0000000000000000
+[0008] SMMU_NSgCfgIrpt Interrupt : 0000000000000000
+[0008] Context Interrupt : 0000000000000000
+[0008] PMU Interrupt : 0000000000000000
+*/
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc
new file mode 100644
index 0000000..600b984
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc
@@ -0,0 +1,130 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+* Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Pv660Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiNextLib.h>
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+// 0x20000 is only for socket 0
+#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x20000 | ((ClusterId) << 8) | (CoreId))
+
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16];
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[4];
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_1_0_APIC_SIGNATURE,
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
+ // GsivId, GicRBase, Mpidr)
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+ // ACPI v5.1).
+ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+ // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */),
+ EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+ 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */),
+ },
+
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4),
+ {
+ EFI_ACPI_6_0_GIC_ITS_INIT(0,0x8C000000), // pc
+ EFI_ACPI_6_0_GIC_ITS_INIT(1,0xC6000000), // dsa
+ EFI_ACPI_6_0_GIC_ITS_INIT(2,0xA3000000), // m3
+ EFI_ACPI_6_0_GIC_ITS_INIT(3,0xB7000000) // pcie
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc
new file mode 100644
index 0000000..f783534
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * Yi Li - yi.li@linaro.org
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Pv660Platform.h"
+
+#define ACPI_5_0_MCFG_VERSION 0x1
+
+#pragma pack(1)
+typedef struct
+{
+ UINT64 ullBaseAddress;
+ UINT16 usSegGroupNum;
+ UINT8 ucStartBusNum;
+ UINT8 ucEndBusNum;
+ UINT32 Reserved2;
+}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved1;
+}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+ EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+ EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[2];
+}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+ {
+ {
+ EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+ ACPI_5_0_MCFG_VERSION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_ARM_OEM_ID},
+ EFI_ACPI_ARM_OEM_TABLE_ID,
+ EFI_ACPI_ARM_OEM_REVISION,
+ EFI_ACPI_ARM_CREATOR_ID,
+ EFI_ACPI_ARM_CREATOR_REVISION
+ },
+ 0x0000000000000000, //Reserved
+ },
+ {
+
+ {
+ 0x0000022000000000, //Base Address
+ 0x0001, //Segment Group Number
+ 0x40, //Start Bus Number
+ 0x7f, //End Bus Number
+ 0x00000000, //Reserved
+ },
+ {
+ 0x0000024000000000, //Base Address
+ 0x0002, //Segment Group Number
+ 0x80, //Start Bus Number
+ 0xbf, //End Bus Number
+ 0x00000000, //Reserved
+ },
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h
new file mode 100644
index 0000000..5af8f1a
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h
@@ -0,0 +1,48 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+
+#ifndef _PV660_PLATFORM_H_
+#define _PV660_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','-','D','0','2') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION 0x20140727
+#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('H','I','S','I')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
+ EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#define PV660_WATCHDOG_COUNT 2
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL
new file mode 100644
index 0000000..29b3ff4
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL
@@ -0,0 +1,169 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+#include "Pv660Platform.h"
+DefinitionBlock (
+ "SASSSDT.aml", // Output Filename
+ "SSDT", // Signature
+ 0x01, // SSDT Compliance Revision
+ "HISI", // OEM ID
+ "SAS0", // Table ID
+ EFI_ACPI_ARM_OEM_REVISION // OEM Revision
+ )
+{
+ External(\_SB.MBI1)
+ External(\_SB.MBI3)
+ Scope(_SB) {
+ Device(SAS0) {
+ Name(_HID, "HISI0161")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc1000000, 0x10000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ //phy irq(0~79)
+ 259,263,264,
+ 269,273,274,
+ 279,283,284,
+ 289,293,294,
+ 299,303,304,
+ 309,313,314,
+ 319,323,324,
+ 329,333,334,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ //cq irq (80~111)
+ 336,337,338,339,340,341,342,343,
+ 344,345,346,347,348,349,350,351,
+ 352,353,354,355,356,357,358,359,
+ 360,361,362,363,364,365,366,367,
+ }
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 376, //chip fatal error irq(120)
+ 381, //chip fatal error irq(125)
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-parent",Package() {\_SB.MBI1}},
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x0a}},
+ Package () {"queue-count", 32},
+ Package () {"phy-count", 8},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x338),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xa60),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a30),
+ STS, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ }
+ }
+
+ Device(SAS1) {
+ Name(_HID, "HISI0161")
+ Name(_CCA, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xb1000000, 0x10000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ //phy irq(0~79)
+ 259,263,264,
+ 269,273,274,
+ 279,283,284,
+ 289,293,294,
+ 299,303,304,
+ 309,313,314,
+ 319,323,324,
+ 329,333,334,
+ }
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ //cq irq (80~111)
+ 336,337,338,339,340,341,342,343,
+ 344,345,346,347,348,349,350,351,
+ 352,353,354,355,356,357,358,359,
+ 360,361,362,363,364,365,366,367,
+ }
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 376, //chip fatal error irq(120)
+ 381, //chip fatal error irq(125)
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-parent",Package() {\_SB.MBI3}},
+ Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+ Package () {"queue-count", 32},
+ Package () {"phy-count", 8},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0xB0000000, 0x10000)
+ Field (CTL, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x318),
+ CLK, 32,
+ CLKD, 32,
+ Offset (0xa18),
+ RST, 32,
+ DRST, 32,
+ Offset (0x5a0c),
+ STS, 32,
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7ffff, RST)
+ Store(0x7ffff, CLKD)
+ Sleep(1)
+ Store(0x7ffff, DRST)
+ Store(0x7ffff, CLK)
+ Sleep(1)
+ }
+ }
+
+ }
+
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL
new file mode 100644
index 0000000..e82ee4c
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL
@@ -0,0 +1,51 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+#include "Pv660Platform.h"
+
+DefinitionBlock (
+ "SATASSDT.aml", // Output Filename
+ "SSDT", // Signature
+ 0x01, // DSDT Compliance Revision
+ "HISI", // OEM ID
+ "SATA", // Table ID
+ EFI_ACPI_ARM_OEM_REVISION // OEM Revision
+ )
+{
+External(\_SB.MBI3)
+Scope(_SB) {
+ Device (AHCI)
+ {
+ Name(_HID, "HISI0001") // HiSi AHCI
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xb1002800, 0x00000B00)
+ Memory32Fixed (ReadWrite, 0xb1000000, 0x00002800)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 382 }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"interrupt-parent",Package() {\_SB.MBI3}}
+ }
+ })
+ }
+
+}
+
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc
new file mode 100644
index 0000000..2fa2959
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * Yi Li - yi.li@linaro.org
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Pv660Platform.h"
+
+#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000014
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
+
+typedef struct {
+ EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header;
+ EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+
+} EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE;
+#pragma pack()
+
+//
+// System Locality Information Table
+// Please modify all values in Slit.h only.
+//
+EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
+ {
+ {
+ EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE),
+ EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_ARM_OEM_ID},
+ EFI_ACPI_ARM_OEM_TABLE_ID,
+ EFI_ACPI_ARM_OEM_REVISION,
+ EFI_ACPI_ARM_CREATOR_ID,
+ EFI_ACPI_ARM_CREATOR_REVISION,
+ },
+ //
+ // Beginning of SLIT specific fields
+ //
+ EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
+ },
+ {
+ {{0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27}}, //Locality 0
+ {{0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26}}, //Locality 1
+ {{0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}, //Locality 2
+ {{0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24}}, //Locality 3
+ {{0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23}}, //Locality 4
+ {{0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22}}, //Locality 5
+ {{0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21}}, //Locality 6
+ {{0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}}, //Locality 7
+ {{0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}}, //Locality 8
+ {{0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}}, //Locality 9
+ {{0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D}}, //Locality 10
+ {{0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C}}, //Locality 11
+ {{0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B}}, //Locality 12
+ {{0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A}}, //Locality 13
+ {{0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19}}, //Locality 14
+ {{0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18}}, //Locality 15
+ {{0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17}}, //Locality 16
+ {{0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16}}, //Locality 17
+ {{0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10}}, //Locality 18
+ {{0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A}}, //Locality 19
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Slit;
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc
new file mode 100644
index 0000000..7eef5f9
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc
@@ -0,0 +1,64 @@
+/** @file
+* Serial Port Console Redirection Table (SPCR)
+*
+* Copyright (c) 2012 - 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include "Pv660Platform.h"
+
+EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ //Header;
+ ARM_ACPI_HEADER(
+ EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION
+ ),
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //InterfaceType;
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, //Reserved1[3];
+ //BaseAddress;
+ {
+ EFI_ACPI_6_0_SYSTEM_MEMORY,
+ 32,
+ 0,
+ EFI_ACPI_6_0_BYTE,
+ FixedPcdGet64(PcdSerialRegisterBase)
+ },
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //InterruptType;
+ 0, //Irq;
+ 349, //GlobalSystemInterrupt;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, //BaudRate;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, //Parity;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, //StopBits;
+ 0, //FlowControl;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, //TerminalType;
+ EFI_ACPI_RESERVED_BYTE, //Language;
+ 0xFFFF, //PciDeviceId;
+ 0xFFFF, //PciVendorId;
+ 0, //PciBusNumber;
+ 0, //PciDeviceNumber;
+ 0, //PciFunctionNumber;
+ 0, //PciFlags;
+ 0, //PciSegment;
+ EFI_ACPI_RESERVED_DWORD //Reserved2;
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc
new file mode 100644
index 0000000..1d38191
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * Yi Li - yi.li@linaro.org
+ *
+ * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Pv660Platform.h"
+#include <Library/AcpiLib.h>
+#include <Library/AcpiNextLib.h>
+
+
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE_COUNT 4
+#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 4
+
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
+ EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE Apic;
+ EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE Memory[2];
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE GICC[16];
+} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE;
+
+#pragma pack()
+
+
+//
+// Static Resource Affinity Table definition
+//
+EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE Srat = {
+ {
+ {EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE),
+ EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_ARM_OEM_ID},
+ EFI_ACPI_ARM_OEM_TABLE_ID,
+ EFI_ACPI_ARM_OEM_REVISION,
+ EFI_ACPI_ARM_CREATOR_ID,
+ EFI_ACPI_ARM_CREATOR_REVISION},
+ /*Reserved*/
+ 0x00000001, // Reserved to be 1 for backward compatibility
+ EFI_ACPI_RESERVED_QWORD
+ },
+ /**/
+ {
+ 0x00, // Subtable Type:Processor Local APIC/SAPIC Affinity
+ sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE), //Length
+ 0x00, //Proximity Domain Low(8)
+ 0x00, //Apic ID
+ 0x00000001, //Flags
+ 0x00, //Local Sapic EID
+ {0,0,0}, //Proximity Domain High(24)
+ 0x00000000, //ClockDomain
+ },
+ //
+ //
+ // Memory Affinity
+ //
+ {
+ EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x40000000,0x00000000,0x00000001),
+ EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x40000000,0x00000002,0xC0000000,0x00000001,0x00000001),
+ },
+
+ /*Processor Local x2APIC Affinity*/
+ //{
+ // 0x02, // Subtable Type:Processor Local x2APIC Affinity
+ // sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE),
+ // {0,0}, //Reserved1
+ // 0x00000000, //Proximity Domain
+ // 0x00000000, //Apic ID
+ // 0x00000001, //Flags
+ // 0x00000000, //Clock Domain
+ // {0,0,0,0}, //Reserved2
+ //},
+
+ {
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14
+ EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000) //GICC Affinity Processor 15
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Srat;
+
