Enable pre-upload clang formatting.
Also re-format the code with clang format.
Bug: 110489128
Change-Id: If59b4480c9a90660bf00607432aebc707d56ba6e
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..97e6791
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,24 @@
+# Trusty Style
+# This is a Google-derived style with 4-space indent and a few quirks for
+# systems code.
+BasedOnStyle: Chromium
+
+# 4-space indent, no tabs.
+IndentWidth: 4
+UseTab: Never
+TabWidth: 4
+
+# Double indent arguments when none of them are on the first line.
+ContinuationIndentWidth: 8
+ConstructorInitializerIndentWidth: 8
+
+# Don't indent public/private/protected.
+# It's a little more common to do a half indent, but folks didn't like that.
+AccessModifierOffset: -4
+
+# Don't indent case labels.
+IndentCaseLabels: false
+
+# Don't break strings to make it easier to grep for error messages.
+# Note: this can result in lines that exceed the column limit.
+BreakStringLiterals: false
diff --git a/PREUPLOAD.cfg b/PREUPLOAD.cfg
new file mode 100644
index 0000000..587b0de
--- /dev/null
+++ b/PREUPLOAD.cfg
@@ -0,0 +1,7 @@
+[Builtin Hooks]
+clang_format = true
+commit_msg_bug_field = true
+commit_msg_changeid_field = true
+
+[Builtin Hooks Options]
+clang_format = --commit ${PREUPLOAD_COMMIT} --style file --extensions c,h,cc,cpp
diff --git a/app/hwcrypto/caam.c b/app/hwcrypto/caam.c
index ad4afcf..59ad770 100644
--- a/app/hwcrypto/caam.c
+++ b/app/hwcrypto/caam.c
@@ -28,21 +28,21 @@
#include <assert.h>
#include <malloc.h>
-#include <openssl/hkdf.h>
#include <openssl/digest.h>
+#include <openssl/hkdf.h>
#include <reg.h>
#include <stdio.h>
-#include <string.h>
#include <stdlib.h>
+#include <string.h>
#include <sys/mman.h>
#include <uapi/err.h>
-#include "caam.h"
#include <imx-regs.h>
+#include "caam.h"
#include "fsl_caam_internal.h"
-#define TLOG_LVL TLOG_LVL_DEFAULT
-#define TLOG_TAG "caam_drv"
+#define TLOG_LVL TLOG_LVL_DEFAULT
+#define TLOG_TAG "caam_drv"
#include "tlog.h"
struct caam_job_rings {
@@ -50,40 +50,31 @@
uint32_t out[2]; /* single entry output ring (consists of two words) */
};
-
/*
* According to CAAM docs max number of descriptors in single sequence is 64
* You can chain them though
*/
-#define MAX_DSC_NUM 64
+#define MAX_DSC_NUM 64
struct caam_job {
- uint32_t dsc[MAX_DSC_NUM]; /* job descriptors */
- uint32_t dsc_used; /* number of filled entries */
- uint32_t status; /* job result */
+ uint32_t dsc[MAX_DSC_NUM]; /* job descriptors */
+ uint32_t dsc_used; /* number of filled entries */
+ uint32_t status; /* job result */
};
-static struct caam_job_rings *g_rings;
-static struct caam_job *g_job;
+static struct caam_job_rings* g_rings;
+static struct caam_job* g_job;
const uint32_t rng_inst_dsc[] = {
- RNG_INST_DESC1,
- RNG_INST_DESC2,
- RNG_INST_DESC3,
- RNG_INST_DESC4,
- RNG_INST_DESC5,
- RNG_INST_DESC6,
- RNG_INST_DESC7,
- RNG_INST_DESC8,
- RNG_INST_DESC9
-};
+ RNG_INST_DESC1, RNG_INST_DESC2, RNG_INST_DESC3,
+ RNG_INST_DESC4, RNG_INST_DESC5, RNG_INST_DESC6,
+ RNG_INST_DESC7, RNG_INST_DESC8, RNG_INST_DESC9};
#if WITH_CAAM_SELF_TEST
static void caam_test(void);
#endif
-static void caam_clk_get(void)
-{
+static void caam_clk_get(void) {
uint32_t val;
/* make sure clock is on */
@@ -91,15 +82,14 @@
#if defined(MACH_IMX6)
val |= (3 << 8) | (3 < 10) | (3 << 12);
#elif defined(MACH_IMX7)
- val = (3 << 0); /* Always enabled (for now) */
+ val = (3 << 0); /* Always enabled (for now) */
#else
#error Unsupported IMX architecture
#endif
writel(val, ccm_base + CCM_CAAM_CCGR_OFFSET);
}
-static void setup_job_rings(void)
-{
+static void setup_job_rings(void) {
int rc;
struct dma_pmem pmem;
@@ -111,16 +101,17 @@
abort();
}
- writel((uint32_t)pmem.paddr + __offsetof(struct caam_job_rings, in), CAAM_IRBAR0); // input ring address
- writel((uint32_t)pmem.paddr + __offsetof(struct caam_job_rings, out), CAAM_ORBAR0); // output ring address
+ writel((uint32_t)pmem.paddr + __offsetof(struct caam_job_rings, in),
+ CAAM_IRBAR0); // input ring address
+ writel((uint32_t)pmem.paddr + __offsetof(struct caam_job_rings, out),
+ CAAM_ORBAR0); // output ring address
/* Initialize job ring sizes */
writel(countof(g_rings->in), CAAM_IRSR0);
writel(countof(g_rings->in), CAAM_ORSR0);
}
-static void run_job(struct caam_job *job)
-{
+static void run_job(struct caam_job* job) {
int ret;
uint32_t job_pa;
struct dma_pmem pmem;
@@ -146,7 +137,8 @@
writel(1, CAAM_IRJAR0);
/* Wait for job ring to complete the job: 1 completed job expected */
- while(readl(CAAM_ORSFR0) != 1);
+ while (readl(CAAM_ORSFR0) != 1)
+ ;
finish_dma(g_rings->out, sizeof(g_rings->out), DMA_FLAG_FROM_DEVICE);
@@ -159,21 +151,23 @@
writel(1, CAAM_ORJRR0);
}
-int init_caam_env(void)
-{
- caam_base = mmap(NULL, CAAM_REG_SIZE, PROT_READ | PROT_WRITE, MMAP_FLAG_IO_HANDLE, CAAM_MMIO_ID, 0);
+int init_caam_env(void) {
+ caam_base = mmap(NULL, CAAM_REG_SIZE, PROT_READ | PROT_WRITE,
+ MMAP_FLAG_IO_HANDLE, CAAM_MMIO_ID, 0);
if (caam_base == MAP_FAILED) {
TLOGE("caam base mapping failed!\n");
return ERR_GENERIC;
}
- sram_base = mmap(NULL, CAAM_SEC_RAM_SIZE, PROT_READ | PROT_WRITE, MMAP_FLAG_IO_HANDLE, CAAM_SEC_RAM_MMIO_ID, 0);
+ sram_base = mmap(NULL, CAAM_SEC_RAM_SIZE, PROT_READ | PROT_WRITE,
+ MMAP_FLAG_IO_HANDLE, CAAM_SEC_RAM_MMIO_ID, 0);
if (sram_base == MAP_FAILED) {
TLOGE("caam secure ram base mapping failed!\n");
return ERR_GENERIC;
}
- ccm_base = mmap(NULL, CCM_REG_SIZE, PROT_READ | PROT_WRITE, MMAP_FLAG_IO_HANDLE, CCM_MMIO_ID, 0);
+ ccm_base = mmap(NULL, CCM_REG_SIZE, PROT_READ | PROT_WRITE,
+ MMAP_FLAG_IO_HANDLE, CCM_MMIO_ID, 0);
if (ccm_base == MAP_FAILED) {
TLOGE("ccm base mapping failed!\n");
return ERR_GENERIC;
@@ -204,8 +198,7 @@
return 0;
}
-void caam_open(void)
-{
+void caam_open(void) {
uint32_t temp_reg;
/* switch on CAAM clock */
@@ -262,9 +255,11 @@
return;
}
-uint32_t caam_decap_blob(const uint8_t *kmod, size_t kmod_size,
- uint8_t *plain, const uint8_t *blob, uint32_t size)
-{
+uint32_t caam_decap_blob(const uint8_t* kmod,
+ size_t kmod_size,
+ uint8_t* plain,
+ const uint8_t* blob,
+ uint32_t size) {
int ret;
uint32_t kmod_pa;
uint32_t blob_pa;
@@ -274,21 +269,22 @@
assert(size + CAAM_KB_HEADER_LEN < 0xFFFFu);
assert(kmod_size == 16);
- ret = prepare_dma((void *)kmod, kmod_size, DMA_FLAG_TO_DEVICE, &pmem);
+ ret = prepare_dma((void*)kmod, kmod_size, DMA_FLAG_TO_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
}
kmod_pa = (uint32_t)pmem.paddr;
- ret = prepare_dma((void *)blob, size + CAAM_KB_HEADER_LEN, DMA_FLAG_TO_DEVICE, &pmem);
+ ret = prepare_dma((void*)blob, size + CAAM_KB_HEADER_LEN,
+ DMA_FLAG_TO_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
}
blob_pa = (uint32_t)pmem.paddr;
- ret = prepare_dma((void *)plain, size, DMA_FLAG_FROM_DEVICE, &pmem);
+ ret = prepare_dma((void*)plain, size, DMA_FLAG_FROM_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
@@ -316,9 +312,11 @@
return CAAM_SUCCESS;
}
-uint32_t caam_gen_blob(const uint8_t *kmod, size_t kmod_size,
- const uint8_t *plain, uint8_t *blob, uint32_t size)
-{
+uint32_t caam_gen_blob(const uint8_t* kmod,
+ size_t kmod_size,
+ const uint8_t* plain,
+ uint8_t* blob,
+ uint32_t size) {
int ret;
uint32_t kmod_pa;
uint32_t blob_pa;
@@ -328,21 +326,22 @@
assert(size + CAAM_KB_HEADER_LEN < 0xFFFFu);
assert(kmod_size == 16);
- ret = prepare_dma((void *)kmod, kmod_size, DMA_FLAG_TO_DEVICE, &pmem);
+ ret = prepare_dma((void*)kmod, kmod_size, DMA_FLAG_TO_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
}
kmod_pa = (uint32_t)pmem.paddr;
- ret = prepare_dma((void *)plain, size, DMA_FLAG_TO_DEVICE, &pmem);
+ ret = prepare_dma((void*)plain, size, DMA_FLAG_TO_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
}
plain_pa = (uint32_t)pmem.paddr;
- ret = prepare_dma((void *)blob, size + CAAM_KB_HEADER_LEN, DMA_FLAG_FROM_DEVICE, &pmem);
+ ret = prepare_dma((void*)blob, size + CAAM_KB_HEADER_LEN,
+ DMA_FLAG_FROM_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
@@ -370,9 +369,12 @@
return CAAM_SUCCESS;
}
-uint32_t caam_aes_op(const uint8_t *key, size_t key_size,
- const uint8_t *in, uint8_t *out, size_t len, bool enc)
-{
+uint32_t caam_aes_op(const uint8_t* key,
+ size_t key_size,
+ const uint8_t* in,
+ uint8_t* out,
+ size_t len,
+ bool enc) {
int ret;
uint32_t in_pa;
uint32_t out_pa;
@@ -383,14 +385,14 @@
assert(len <= 0xFFFFu);
assert(len % 16 == 0);
- ret = prepare_dma((void *)key, key_size, DMA_FLAG_TO_DEVICE, &pmem);
+ ret = prepare_dma((void*)key, key_size, DMA_FLAG_TO_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
}
key_pa = (uint32_t)pmem.paddr;
- ret = prepare_dma((void *)in, len, DMA_FLAG_TO_DEVICE, &pmem);
+ ret = prepare_dma((void*)in, len, DMA_FLAG_TO_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
@@ -429,15 +431,13 @@
return CAAM_SUCCESS;
}
-uint32_t caam_hwrng(uint8_t *out, size_t len)
-{
+uint32_t caam_hwrng(uint8_t* out, size_t len) {
int ret;
struct dma_pmem pmem;
while (len) {
ret = prepare_dma(out, len,
- DMA_FLAG_FROM_DEVICE | DMA_FLAG_ALLOW_PARTIAL,
- &pmem);
+ DMA_FLAG_FROM_DEVICE | DMA_FLAG_ALLOW_PARTIAL, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
@@ -465,14 +465,11 @@
return CAAM_SUCCESS;
}
-void *caam_get_keybox(void)
-{
+void* caam_get_keybox(void) {
return sram_base;
}
-
-uint32_t caam_hash(uint8_t *in, uint8_t *out, uint32_t len)
-{
+uint32_t caam_hash(uint8_t* in, uint8_t* out, uint32_t len) {
int ret;
uint32_t in_pa;
uint32_t out_pa;
@@ -480,7 +477,7 @@
assert(len <= 0xFFFFu);
- ret = prepare_dma((void *)in, len, DMA_FLAG_TO_DEVICE, &pmem);
+ ret = prepare_dma((void*)in, len, DMA_FLAG_TO_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
@@ -513,15 +510,14 @@
return CAAM_SUCCESS;
}
-uint32_t caam_gen_kdfv1_root_key(uint8_t *out, uint32_t size)
-{
+uint32_t caam_gen_kdfv1_root_key(uint8_t* out, uint32_t size) {
int ret;
uint32_t pa;
struct dma_pmem pmem;
assert(size == 32);
- ret = prepare_dma((void *)out, size, DMA_FLAG_FROM_DEVICE, &pmem);
+ ret = prepare_dma((void*)out, size, DMA_FLAG_FROM_DEVICE, &pmem);
if (ret != 1) {
TLOGE("failed (%d) to prepare dma buffer\n", ret);
return CAAM_FAILURE;
@@ -540,10 +536,10 @@
*/
g_job->dsc[0] = 0xB080000B;
g_job->dsc[1] = 0x14C00010;
- g_job->dsc[2] = 0x7083A393; /* salt word 0 */
- g_job->dsc[3] = 0x2CC0C9F7; /* salt word 1 */
- g_job->dsc[4] = 0xFC5D2FC0; /* salt word 2 */
- g_job->dsc[5] = 0x2C4B04E7; /* salt word 3 */
+ g_job->dsc[2] = 0x7083A393; /* salt word 0 */
+ g_job->dsc[3] = 0x2CC0C9F7; /* salt word 1 */
+ g_job->dsc[4] = 0xFC5D2FC0; /* salt word 2 */
+ g_job->dsc[5] = 0x2C4B04E7; /* salt word 3 */
g_job->dsc[6] = 0xF0000000;
g_job->dsc[7] = 0;
g_job->dsc[8] = 0xF8000030;
@@ -562,14 +558,12 @@
return CAAM_SUCCESS;
}
-
-#if WITH_CAAM_SELF_TEST
+#if WITH_CAAM_SELF_TEST
/*
* HWRNG
*/
-static void caam_hwrng_test(void)
-{
+static void caam_hwrng_test(void) {
DECLARE_SG_SAFE_BUF(out1, 32);
DECLARE_SG_SAFE_BUF(out2, 32);
@@ -585,8 +579,7 @@
/*
* Blob
*/
-static void caam_blob_test(void)
-{
+static void caam_blob_test(void) {
uint i = 0;
DECLARE_SG_SAFE_BUF(keymd, 16);
DECLARE_SG_SAFE_BUF(plain, 32);
@@ -597,7 +590,7 @@
caam_hwrng(keymd, sizeof(keymd));
/* build known input */
- for (i = 0; i< sizeof(plain); i++) {
+ for (i = 0; i < sizeof(plain); i++) {
plain[i] = i + '0';
plain_bak[i] = plain[i];
}
@@ -619,8 +612,7 @@
/*
* AES
*/
-static void caam_aes_test(void)
-{
+static void caam_aes_test(void) {
DECLARE_SG_SAFE_BUF(key, 16);
DECLARE_SG_SAFE_BUF(buf1, 32);
DECLARE_SG_SAFE_BUF(buf2, 32);
@@ -661,8 +653,7 @@
/*
* HASH (SHA-1)
*/
-static void caam_hash_test(void)
-{
+static void caam_hash_test(void) {
DECLARE_SG_SAFE_BUF(in, 32);
DECLARE_SG_SAFE_BUF(hash1, 32);
DECLARE_SG_SAFE_BUF(hash2, 32);
@@ -687,8 +678,7 @@
TLOGI("caam hash test PASS!!!\n");
}
-static void caam_kdfv1_root_key_test(void)
-{
+static void caam_kdfv1_root_key_test(void) {
DECLARE_SG_SAFE_BUF(out1, 32);
DECLARE_SG_SAFE_BUF(out2, 32);
@@ -701,8 +691,7 @@
TLOGI("caam gen kdf root key test PASS!!!\n");
}
-static void caam_test(void)
-{
+static void caam_test(void) {
caam_hwrng_test();
caam_blob_test();
caam_kdfv1_root_key_test();
@@ -711,4 +700,3 @@
}
#endif /* WITH_CAAM_SELF_TEST */
-
diff --git a/app/hwcrypto/caam.h b/app/hwcrypto/caam.h
index 1cb9dce..c52a355 100644
--- a/app/hwcrypto/caam.h
+++ b/app/hwcrypto/caam.h
@@ -29,35 +29,44 @@
#ifndef _CAAM_H
#define _CAAM_H
-#define CAAM_MMIO_ID 8
-#define CAAM_SEC_RAM_MMIO_ID 9
-#define CCM_MMIO_ID 10
+#define CAAM_MMIO_ID 8
+#define CAAM_SEC_RAM_MMIO_ID 9
+#define CCM_MMIO_ID 10
-#define CAAM_KB_HEADER_LEN 48
-#define CAAM_SUCCESS 0
-#define CAAM_FAILURE 1
+#define CAAM_KB_HEADER_LEN 48
+#define CAAM_SUCCESS 0
+#define CAAM_FAILURE 1
int init_caam_env(void);
void caam_open(void);
-uint32_t caam_gen_blob(const uint8_t *kmod, size_t kmod_size,
- const uint8_t *plain_text, uint8_t *blob, uint32_t size);
+uint32_t caam_gen_blob(const uint8_t* kmod,
+ size_t kmod_size,
+ const uint8_t* plain_text,
+ uint8_t* blob,
+ uint32_t size);
-uint32_t caam_decap_blob(const uint8_t *kmod, size_t kmod_size,
- uint8_t *plain_text, const uint8_t *blob, uint32_t size);
+uint32_t caam_decap_blob(const uint8_t* kmod,
+ size_t kmod_size,
+ uint8_t* plain_text,
+ const uint8_t* blob,
+ uint32_t size);
-uint32_t caam_aes_op(const uint8_t *key, size_t key_size,
- const uint8_t *input, uint8_t *output, size_t len, bool enc);
+uint32_t caam_aes_op(const uint8_t* key,
+ size_t key_size,
+ const uint8_t* input,
+ uint8_t* output,
+ size_t len,
+ bool enc);
-uint32_t caam_hwrng(uint8_t *output_ptr, uint32_t output_len);
+uint32_t caam_hwrng(uint8_t* output_ptr, uint32_t output_len);
-uint32_t caam_gen_kdfv1_root_key(uint8_t *out, size_t size);
+uint32_t caam_gen_kdfv1_root_key(uint8_t* out, size_t size);
-void *caam_get_keybox(void);
+void* caam_get_keybox(void);
/* Declare small scatter gather safe buffer (size must be power of 2) */
-#define DECLARE_SG_SAFE_BUF(nm, sz) \
- uint8_t nm[sz] __attribute__ ((aligned (sz)))
+#define DECLARE_SG_SAFE_BUF(nm, sz) uint8_t nm[sz] __attribute__((aligned(sz)))
#endif
diff --git a/app/hwcrypto/common.h b/app/hwcrypto/common.h
index c97b9c3..74691c4 100644
--- a/app/hwcrypto/common.h
+++ b/app/hwcrypto/common.h
@@ -20,30 +20,35 @@
#include <sys/types.h>
#include <trusty_ipc.h>
-typedef void (*event_handler_proc_t) (const uevent_t *ev, void *ctx);
+typedef void (*event_handler_proc_t)(const uevent_t* ev, void* ctx);
typedef struct tipc_event_handler {
event_handler_proc_t proc;
- void *priv;
+ void* priv;
} tipc_event_handler_t;
-
__BEGIN_CDECLS
/*
* tipc helpers
*/
-void tipc_handle_port_errors(const uevent_t *ev);
-void tipc_handle_chan_errors(const uevent_t *ev);
+void tipc_handle_port_errors(const uevent_t* ev);
+void tipc_handle_chan_errors(const uevent_t* ev);
-int tipc_send_single_buf(handle_t chan, const void *buf, size_t len);
-int tipc_recv_single_buf(handle_t chan, void *buf, size_t len);
+int tipc_send_single_buf(handle_t chan, const void* buf, size_t len);
+int tipc_recv_single_buf(handle_t chan, void* buf, size_t len);
-int tipc_send_two_segments(handle_t chan, const void *hdr, size_t hdr_len,
- const void *payload, size_t payload_len);
+int tipc_send_two_segments(handle_t chan,
+ const void* hdr,
+ size_t hdr_len,
+ const void* payload,
+ size_t payload_len);
-int tipc_recv_two_segments(handle_t chan, void *hdr, size_t hdr_len,
- void *payload, size_t payload_len);
+int tipc_recv_two_segments(handle_t chan,
+ void* hdr,
+ size_t hdr_len,
+ void* payload,
+ size_t payload_len);
/*
* tipc services
@@ -52,4 +57,3 @@
int hwkey_setup_service(void);
__END_CDECLS
-
diff --git a/app/hwcrypto/fsl_caam_internal.h b/app/hwcrypto/fsl_caam_internal.h
index b406986..6e09618 100644
--- a/app/hwcrypto/fsl_caam_internal.h
+++ b/app/hwcrypto/fsl_caam_internal.h
@@ -2,134 +2,135 @@
* Copyright (c) 2012-2016, Freescale Semiconductor, Inc.
* All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
*
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
+ * o Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
*
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
+ * o Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CAAM_INTERNAL_H__
-#define __CAAM_INTERNAL_H__
+#define __CAAM_INTERNAL_H__
-static uint8_t *caam_base;
-static uint8_t *ccm_base;
-static uint8_t *sram_base;
+static uint8_t* caam_base;
+static uint8_t* ccm_base;
+static uint8_t* sram_base;
/* 4kbyte pages */
#define CAAM_SEC_RAM_START_ADDR (sram_base)
-#define SEC_MEM_PAGE0 CAAM_SEC_RAM_START_ADDR
-#define SEC_MEM_PAGE1 (CAAM_SEC_RAM_START_ADDR + 0x1000)
-#define SEC_MEM_PAGE2 (CAAM_SEC_RAM_START_ADDR + 0x2000)
-#define SEC_MEM_PAGE3 (CAAM_SEC_RAM_START_ADDR + 0x3000)
+#define SEC_MEM_PAGE0 CAAM_SEC_RAM_START_ADDR
+#define SEC_MEM_PAGE1 (CAAM_SEC_RAM_START_ADDR + 0x1000)
+#define SEC_MEM_PAGE2 (CAAM_SEC_RAM_START_ADDR + 0x2000)
+#define SEC_MEM_PAGE3 (CAAM_SEC_RAM_START_ADDR + 0x3000)
/* Configuration and special key registers */
-#define CAAM_MCFGR ( 0x0004 + caam_base )
-#define CAAM_SCFGR ( 0x000c + caam_base )
-#define CAAM_JR0MIDR ( 0x0010 + caam_base )
-#define CAAM_JR1MIDR ( 0x0018 + caam_base )
-#define CAAM_DECORR ( 0x009c + caam_base )
-#define CAAM_DECO0MID ( 0x00a0 + caam_base )
-#define CAAM_DAR ( 0x0120 + caam_base )
-#define CAAM_DRR ( 0x0124 + caam_base )
-#define CAAM_JDKEKR ( 0x0400 + caam_base )
-#define CAAM_TDKEKR ( 0x0420 + caam_base )
-#define CAAM_TDSKR ( 0x0440 + caam_base )
-#define CAAM_SKNR ( 0x04e0 + caam_base )
-#define CAAM_SMSTA ( 0x0FB4 + caam_base )
-#define CAAM_STA ( 0x0FD4 + caam_base )
-#define CAAM_SMPO_0 ( 0x1FBC + caam_base )
+#define CAAM_MCFGR (0x0004 + caam_base)
+#define CAAM_SCFGR (0x000c + caam_base)
+#define CAAM_JR0MIDR (0x0010 + caam_base)
+#define CAAM_JR1MIDR (0x0018 + caam_base)
+#define CAAM_DECORR (0x009c + caam_base)
+#define CAAM_DECO0MID (0x00a0 + caam_base)
+#define CAAM_DAR (0x0120 + caam_base)
+#define CAAM_DRR (0x0124 + caam_base)
+#define CAAM_JDKEKR (0x0400 + caam_base)
+#define CAAM_TDKEKR (0x0420 + caam_base)
+#define CAAM_TDSKR (0x0440 + caam_base)
+#define CAAM_SKNR (0x04e0 + caam_base)
+#define CAAM_SMSTA (0x0FB4 + caam_base)
+#define CAAM_STA (0x0FD4 + caam_base)
+#define CAAM_SMPO_0 (0x1FBC + caam_base)
/* RNG registers */
-#define CAAM_RTMCTL ( 0x0600 + caam_base )
-#define CAAM_RTSDCTL ( 0x0610 + caam_base )
-#define CAAM_RTFRQMIN ( 0x0618 + caam_base )
-#define CAAM_RTFRQMAX ( 0x061C + caam_base )
-#define CAAM_RTSTATUS ( 0x063C + caam_base )
-#define CAAM_RDSTA ( 0x06C0 + caam_base )
+#define CAAM_RTMCTL (0x0600 + caam_base)
+#define CAAM_RTSDCTL (0x0610 + caam_base)
+#define CAAM_RTFRQMIN (0x0618 + caam_base)
+#define CAAM_RTFRQMAX (0x061C + caam_base)
+#define CAAM_RTSTATUS (0x063C + caam_base)
+#define CAAM_RDSTA (0x06C0 + caam_base)
/* Job Ring 0 registers */
-#define CAAM_IRBAR0 ( 0x1004 + caam_base )
-#define CAAM_IRSR0 ( 0x100c + caam_base )
-#define CAAM_IRSAR0 ( 0x1014 + caam_base )
-#define CAAM_IRJAR0 ( 0x101c + caam_base )
-#define CAAM_ORBAR0 ( 0x1024 + caam_base )
-#define CAAM_ORSR0 ( 0x102c + caam_base )
-#define CAAM_ORJRR0 ( 0x1034 + caam_base )
-#define CAAM_ORSFR0 ( 0x103c + caam_base )
-#define CAAM_JRSTAR0 ( 0x1044 + caam_base )
-#define CAAM_JRINTR0 ( 0x104c + caam_base )
-#define CAAM_JRCFGR0_MS ( 0x1050 + caam_base )
-#define CAAM_JRCFGR0_LS ( 0x1054 + caam_base )
-#define CAAM_IRRIR0 ( 0x105c + caam_base )
-#define CAAM_ORWIR0 ( 0x1064 + caam_base )
-#define CAAM_JRCR0 ( 0x106c + caam_base )
-#define CAAM_SMCJR0 ( 0x10f4 + caam_base )
-#define CAAM_SMCSJR0 ( 0x10fc + caam_base )
+#define CAAM_IRBAR0 (0x1004 + caam_base)
+#define CAAM_IRSR0 (0x100c + caam_base)
+#define CAAM_IRSAR0 (0x1014 + caam_base)
+#define CAAM_IRJAR0 (0x101c + caam_base)
+#define CAAM_ORBAR0 (0x1024 + caam_base)
+#define CAAM_ORSR0 (0x102c + caam_base)
+#define CAAM_ORJRR0 (0x1034 + caam_base)
+#define CAAM_ORSFR0 (0x103c + caam_base)
+#define CAAM_JRSTAR0 (0x1044 + caam_base)
+#define CAAM_JRINTR0 (0x104c + caam_base)
+#define CAAM_JRCFGR0_MS (0x1050 + caam_base)
+#define CAAM_JRCFGR0_LS (0x1054 + caam_base)
+#define CAAM_IRRIR0 (0x105c + caam_base)
+#define CAAM_ORWIR0 (0x1064 + caam_base)
+#define CAAM_JRCR0 (0x106c + caam_base)
+#define CAAM_SMCJR0 (0x10f4 + caam_base)
+#define CAAM_SMCSJR0 (0x10fc + caam_base)
#if 0
-#define CAAM_SMAPJR0(y) (CAAM_BASE_ADDR + 0x1104 + y*16)
-#define CAAM_SMAG2JR0(y) (CAAM_BASE_ADDR + 0x1108 + y*16)
-#define CAAM_SMAG1JR0(y) (CAAM_BASE_ADDR + 0x110C + y*16)
-#define CAAM_SMAPJR0_PRTN1 CAAM_BASE_ADDR + 0x1114
+#define CAAM_SMAPJR0(y) (CAAM_BASE_ADDR + 0x1104 + y * 16)
+#define CAAM_SMAG2JR0(y) (CAAM_BASE_ADDR + 0x1108 + y * 16)
+#define CAAM_SMAG1JR0(y) (CAAM_BASE_ADDR + 0x110C + y * 16)
+#define CAAM_SMAPJR0_PRTN1 CAAM_BASE_ADDR + 0x1114
#define CAAM_SMAG2JR0_PRTN1 CAAM_BASE_ADDR + 0x1118
#define CAAM_SMAG1JR0_PRTN1 CAAM_BASE_ADDR + 0x111c
-#define CAAM_SMPO CAAM_BASE_ADDR + 0x1fbc
+#define CAAM_SMPO CAAM_BASE_ADDR + 0x1fbc
#endif
-#define JRCFG_LS_IMSK 0x00000001
-#define JR_MID 2
-#define KS_G1 (1 << JR_MID)
-#define PERM 0x0000B008
+#define JRCFG_LS_IMSK 0x00000001
+#define JR_MID 2
+#define KS_G1 (1 << JR_MID)
+#define PERM 0x0000B008
-#define CMD_PAGE_ALLOC 0x1
-#define CMD_PAGE_DEALLOC 0x2
-#define CMD_PART_DEALLOC 0x3
-#define CMD_INQUIRY 0x5
-#define PAGE(x) (x << 16)
-#define PARTITION(x) (x << 8)
+#define CMD_PAGE_ALLOC 0x1
+#define CMD_PAGE_DEALLOC 0x2
+#define CMD_PART_DEALLOC 0x3
+#define CMD_INQUIRY 0x5
+#define PAGE(x) (x << 16)
+#define PARTITION(x) (x << 8)
-#define SMCSJR_AERR (3 << 12)
-#define SMCSJR_CERR (3 << 14)
-#define CMD_COMPLETE (3 << 14)
+#define SMCSJR_AERR (3 << 12)
+#define SMCSJR_CERR (3 << 14)
+#define CMD_COMPLETE (3 << 14)
-#define SMCSJR_PO (3 << 6)
-#define PAGE_AVAILABLE 0
-#define PAGE_OWNED (3 << 6)
+#define SMCSJR_PO (3 << 6)
+#define PAGE_AVAILABLE 0
+#define PAGE_OWNED (3 << 6)
-#define PARTITION_OWNER(x) (0x3 << (x*2))
+#define PARTITION_OWNER(x) (0x3 << (x * 2))
-#define CAAM_BUSY_MASK 0x00000001
-#define CAAM_IDLE_MASK 0x00000002
-#define JOB_RING_ENTRIES 1
-#define JOB_RING_STS (0xF << 28)
+#define CAAM_BUSY_MASK 0x00000001
+#define CAAM_IDLE_MASK 0x00000002
+#define JOB_RING_ENTRIES 1
+#define JOB_RING_STS (0xF << 28)
-#define RNG_TRIM_OSC_DIV 0
-#define RNG_TRIM_ENT_DLY 3200
+#define RNG_TRIM_OSC_DIV 0
+#define RNG_TRIM_ENT_DLY 3200
-#define RTMCTL_PGM (1 << 16)
-#define RTMCTL_ERR (1 << 12)
-#define RDSTA_IF0 1
-#define RDSTA_SKVN (1 << 30)
+#define RTMCTL_PGM (1 << 16)
+#define RTMCTL_ERR (1 << 12)
+#define RDSTA_IF0 1
+#define RDSTA_SKVN (1 << 30)
#define DECAP_BLOB_DESC1 0xB0800009
#define DECAP_BLOB_DESC2 0x14C00C08
@@ -141,15 +142,15 @@
#define DECAP_BLOB_DESC8 SEC_MEM_PAGE1
#define DECAP_BLOB_DESC9 0x860D0008
-#define ENCAP_BLOB_DESC1 0xB0800009
+#define ENCAP_BLOB_DESC1 0xB0800009
#define ENCAP_BLOB_DESC2 0x14C00C08
#define ENCAP_BLOB_DESC3 0x00105566
#define ENCAP_BLOB_DESC4 0x00000000
#define ENCAP_BLOB_DESC5 0xF00003d0
#define ENCAP_BLOB_DESC6 SEC_MEM_PAGE1
-#define ENCAP_BLOB_DESC7 0xF8000400
-#define ENCAP_BLOB_DESC8 0x00000000
-#define ENCAP_BLOB_DESC9 0x870D0008
+#define ENCAP_BLOB_DESC7 0xF8000400
+#define ENCAP_BLOB_DESC8 0x00000000
+#define ENCAP_BLOB_DESC9 0x870D0008
#define RNG_INST_DESC1 0xB0800009
#define RNG_INST_DESC2 0x12A00008
diff --git a/app/hwcrypto/hwkey_keyslots.h b/app/hwcrypto/hwkey_keyslots.h
index dc0341a..ba9714e 100644
--- a/app/hwcrypto/hwkey_keyslots.h
+++ b/app/hwcrypto/hwkey_keyslots.h
@@ -31,12 +31,11 @@
#include "caam.h"
-#define RPMBKEY_LEN (32 + CAAM_KB_HEADER_LEN)
+#define RPMBKEY_LEN (32 + CAAM_KB_HEADER_LEN)
#define PUBKEY_LEN (1032 + CAAM_KB_HEADER_LEN)
#define KEYPACK_MAGIC "!KS"
-struct keyslot_package
-{
+struct keyslot_package {
char magic[4];
unsigned int rpmb_keyblob_len;
unsigned char rpmb_keyblob[RPMBKEY_LEN];
diff --git a/app/hwcrypto/hwkey_srv.c b/app/hwcrypto/hwkey_srv.c
index d9ec2f2..4abb293 100644
--- a/app/hwcrypto/hwkey_srv.c
+++ b/app/hwcrypto/hwkey_srv.c
@@ -26,11 +26,11 @@
#include <interface/hwkey/hwkey.h>
#include "common.h"
-#include "uuids.h"
#include "hwkey_srv_priv.h"
+#include "uuids.h"
-#define TLOG_LVL TLOG_LVL_DEFAULT
-#define TLOG_TAG "hwkey_srv"
+#define TLOG_LVL TLOG_LVL_DEFAULT
+#define TLOG_TAG "hwkey_srv"
#include "tlog.h"
#define HWKEY_MAX_PAYLOAD_SIZE 2048
@@ -41,23 +41,25 @@
uuid_t uuid;
};
-static void hwkey_port_handler(const uevent_t *ev, void *priv);
-static void hwkey_chan_handler(const uevent_t *ev, void *priv);
+static void hwkey_port_handler(const uevent_t* ev, void* priv);
+static void hwkey_chan_handler(const uevent_t* ev, void* priv);
static tipc_event_handler_t hwkey_port_evt_handler = {
- .proc = hwkey_port_handler,
+ .proc = hwkey_port_handler,
};
-/* Make sure that key_data and reg_data buffers are not crossing page boundary so it is
- * safe to pass them to DMA. An extra byte for req_data buf is used to zero terminate string
- * so it is OK to have it on separate page as it will never be accesed by DMA engine.
+/* Make sure that key_data and reg_data buffers are not crossing page boundary
+ * so it is safe to pass them to DMA. An extra byte for req_data buf is used to
+ * zero terminate string so it is OK to have it on separate page as it will
+ * never be accesed by DMA engine.
*/
-static uint8_t key_data[HWKEY_MAX_PAYLOAD_SIZE] __attribute__((aligned(HWKEY_MAX_PAYLOAD_SIZE)));
-static uint8_t req_data[HWKEY_MAX_PAYLOAD_SIZE+1] __attribute__((aligned(HWKEY_MAX_PAYLOAD_SIZE)));
+static uint8_t key_data[HWKEY_MAX_PAYLOAD_SIZE]
+ __attribute__((aligned(HWKEY_MAX_PAYLOAD_SIZE)));
+static uint8_t req_data[HWKEY_MAX_PAYLOAD_SIZE + 1]
+ __attribute__((aligned(HWKEY_MAX_PAYLOAD_SIZE)));
static uint key_slot_cnt;
-static const struct hwkey_keyslot *key_slots;
-
+static const struct hwkey_keyslot* key_slots;
#if WITH_HWCRYPTO_UNITTEST
/*
@@ -69,9 +71,10 @@
static const uuid_t hwcrypto_unittest_uuid = HWCRYPTO_UNITTEST_APP_UUID;
static uint8_t _unittest_key32[32] = "unittestkeyslotunittestkeyslotun";
-static uint32_t get_unittest_key32(const struct hwkey_keyslot *slot,
- uint8_t *kbuf, size_t kbuf_len, size_t *klen)
-{
+static uint32_t get_unittest_key32(const struct hwkey_keyslot* slot,
+ uint8_t* kbuf,
+ size_t kbuf_len,
+ size_t* klen) {
assert(kbuf);
assert(klen);
assert(kbuf_len >= sizeof(_unittest_key32));
@@ -84,19 +87,18 @@
}
static const struct hwkey_keyslot test_key_slots[] = {
- {
- .uuid = &hwcrypto_unittest_uuid,
- .key_id = "com.android.trusty.hwcrypto.unittest.key32",
- .handler = get_unittest_key32,
- },
+ {
+ .uuid = &hwcrypto_unittest_uuid,
+ .key_id = "com.android.trusty.hwcrypto.unittest.key32",
+ .handler = get_unittest_key32,
+ },
};
#endif /* WITH_HWCRYPTO_UNITTEST */
/*
* Close specified hwkey context
*/
-static void hwkey_ctx_close(struct hwkey_chan_ctx *ctx)
-{
+static void hwkey_ctx_close(struct hwkey_chan_ctx* ctx) {
close(ctx->chan);
free(ctx);
}
@@ -104,26 +106,26 @@
/*
* Send response message
*/
-static int hwkey_send_rsp(struct hwkey_chan_ctx *ctx,
- struct hwkey_msg *rsp_hdr,
- uint8_t *rsp_data, size_t rsp_data_len)
-{
+static int hwkey_send_rsp(struct hwkey_chan_ctx* ctx,
+ struct hwkey_msg* rsp_hdr,
+ uint8_t* rsp_data,
+ size_t rsp_data_len) {
rsp_hdr->cmd |= HWKEY_RESP_BIT;
- return tipc_send_two_segments(ctx->chan,
- rsp_hdr, sizeof(*rsp_hdr),
+ return tipc_send_two_segments(ctx->chan, rsp_hdr, sizeof(*rsp_hdr),
rsp_data, rsp_data_len);
}
-
-static uint32_t _handle_slots(struct hwkey_chan_ctx *ctx, const char *slot_id,
- const struct hwkey_keyslot *slots, uint slot_cnt,
- uint8_t *kbuf, size_t kbuf_len, size_t *klen)
-{
+static uint32_t _handle_slots(struct hwkey_chan_ctx* ctx,
+ const char* slot_id,
+ const struct hwkey_keyslot* slots,
+ uint slot_cnt,
+ uint8_t* kbuf,
+ size_t kbuf_len,
+ size_t* klen) {
if (!slots)
return HWKEY_ERR_NOT_FOUND;
for (uint i = 0; i < slot_cnt; i++, slots++) {
-
/* check key id */
if (strcmp(slots->key_id, slot_id))
continue;
@@ -138,26 +140,24 @@
return HWKEY_ERR_NOT_FOUND;
}
-
/*
* Handle get key slot command
*/
-static int hwkey_handle_get_keyslot_cmd(struct hwkey_chan_ctx *ctx,
- struct hwkey_msg *hdr,
- const char *slot_id)
-{
+static int hwkey_handle_get_keyslot_cmd(struct hwkey_chan_ctx* ctx,
+ struct hwkey_msg* hdr,
+ const char* slot_id) {
int rc;
size_t klen = 0;
- hdr->status = _handle_slots(ctx, slot_id, key_slots, key_slot_cnt,
- key_data, sizeof(key_data), &klen);
+ hdr->status = _handle_slots(ctx, slot_id, key_slots, key_slot_cnt, key_data,
+ sizeof(key_data), &klen);
#if WITH_HWCRYPTO_UNITTEST
if (hdr->status == HWKEY_ERR_NOT_FOUND) {
/* also search test keys */
- hdr->status = _handle_slots(ctx, slot_id,
- test_key_slots, countof(test_key_slots),
- key_data, sizeof(key_data), &klen);
+ hdr->status = _handle_slots(ctx, slot_id, test_key_slots,
+ countof(test_key_slots), key_data,
+ sizeof(key_data), &klen);
}
#endif
@@ -172,10 +172,10 @@
/*
* Handle Derive key cmd
*/
-static int hwkey_handle_derive_key_cmd(struct hwkey_chan_ctx *ctx,
- struct hwkey_msg *hdr,
- const uint8_t *ikm_data, size_t ikm_len)
-{
+static int hwkey_handle_derive_key_cmd(struct hwkey_chan_ctx* ctx,
+ struct hwkey_msg* hdr,
+ const uint8_t* ikm_data,
+ size_t ikm_len) {
int rc;
size_t key_len = sizeof(key_data);
@@ -185,8 +185,8 @@
switch (hdr->arg1) {
case HWKEY_KDF_VERSION_1:
- hdr->status = derive_key_v1(&ctx->uuid, ikm_data, ikm_len,
- key_data, &key_len);
+ hdr->status = derive_key_v1(&ctx->uuid, ikm_data, ikm_len, key_data,
+ &key_len);
break;
default:
@@ -206,14 +206,13 @@
/*
* Read and queue HWKEY request message
*/
-static int hwkey_chan_handle_msg(struct hwkey_chan_ctx *ctx)
-{
+static int hwkey_chan_handle_msg(struct hwkey_chan_ctx* ctx) {
int rc;
size_t req_data_len;
struct hwkey_msg hdr;
- rc = tipc_recv_two_segments(ctx->chan, &hdr, sizeof(hdr),
- req_data, sizeof(req_data) - 1);
+ rc = tipc_recv_two_segments(ctx->chan, &hdr, sizeof(hdr), req_data,
+ sizeof(req_data) - 1);
if (rc < 0) {
TLOGE("failed (%d) to recv msg from chan %d\n", rc, ctx->chan);
return rc;
@@ -226,7 +225,7 @@
switch (hdr.cmd) {
case HWKEY_GET_KEYSLOT:
req_data[req_data_len] = 0; /* force zero termination */
- rc = hwkey_handle_get_keyslot_cmd(ctx, &hdr, (const char *)req_data);
+ rc = hwkey_handle_get_keyslot_cmd(ctx, &hdr, (const char*)req_data);
break;
case HWKEY_DERIVE:
@@ -246,9 +245,8 @@
/*
* HWKEY service channel event handler
*/
-static void hwkey_chan_handler(const uevent_t *ev, void *priv)
-{
- struct hwkey_chan_ctx *ctx = priv;
+static void hwkey_chan_handler(const uevent_t* ev, void* priv) {
+ struct hwkey_chan_ctx* ctx = priv;
assert(ctx);
assert(ev->handle == ctx->chan);
@@ -265,8 +263,8 @@
int rc = hwkey_chan_handle_msg(ctx);
if (rc < 0) {
/* report an error and close channel */
- TLOGE("failed (%d) to handle event on channel %d\n",
- rc, ev->handle);
+ TLOGE("failed (%d) to handle event on channel %d\n", rc,
+ ev->handle);
hwkey_ctx_close(ctx);
}
}
@@ -275,8 +273,7 @@
/*
* HWKEY service port event handler
*/
-static void hwkey_port_handler(const uevent_t *ev, void *priv)
-{
+static void hwkey_port_handler(const uevent_t* ev, void* priv) {
uuid_t peer_uuid;
tipc_handle_port_errors(ev);
@@ -289,8 +286,8 @@
return;
}
- handle_t chan = (handle_t) rc;
- struct hwkey_chan_ctx *ctx = calloc(1, sizeof(*ctx));
+ handle_t chan = (handle_t)rc;
+ struct hwkey_chan_ctx* ctx = calloc(1, sizeof(*ctx));
if (!ctx) {
TLOGE("failed (%d) to allocate context on chan %d\n", rc, chan);
close(chan);
@@ -315,8 +312,7 @@
/*
* Install Key slot provider
*/
-void hwkey_install_keys(const struct hwkey_keyslot *keys, uint kcnt)
-{
+void hwkey_install_keys(const struct hwkey_keyslot* keys, uint kcnt) {
assert(key_slots == NULL);
assert(key_slot_cnt == 0);
assert(keys && kcnt);
@@ -328,22 +324,22 @@
/*
* Initialize HWKEY service
*/
-int hwkey_start_service(void)
-{
+int hwkey_start_service(void) {
int rc;
handle_t port;
TLOGI("Start HWKEY service\n");
/* Initialize service */
- rc = port_create(HWKEY_PORT, 1, sizeof(struct hwkey_msg) + HWKEY_MAX_PAYLOAD_SIZE,
+ rc = port_create(HWKEY_PORT, 1,
+ sizeof(struct hwkey_msg) + HWKEY_MAX_PAYLOAD_SIZE,
IPC_PORT_ALLOW_TA_CONNECT);
if (rc < 0) {
TLOGE("Failed (%d) to create port %s\n", rc, HWKEY_PORT);
return rc;
}
- port = (handle_t) rc;
+ port = (handle_t)rc;
rc = set_cookie(port, &hwkey_port_evt_handler);
if (rc) {
TLOGE("failed (%d) to set_cookie on port %d\n", rc, port);
diff --git a/app/hwcrypto/hwkey_srv_priv.h b/app/hwcrypto/hwkey_srv_priv.h
index 7ec94f8..a813c15 100644
--- a/app/hwcrypto/hwkey_srv_priv.h
+++ b/app/hwcrypto/hwkey_srv_priv.h
@@ -20,25 +20,27 @@
#include <trusty_uuid.h>
struct hwkey_keyslot {
- const char *key_id;
- const uuid_t *uuid;
- const void *priv;
- uint32_t (*handler)(const struct hwkey_keyslot *slot,
- uint8_t *kbuf, size_t kbuf_len, size_t *klen);
+ const char* key_id;
+ const uuid_t* uuid;
+ const void* priv;
+ uint32_t (*handler)(const struct hwkey_keyslot* slot,
+ uint8_t* kbuf,
+ size_t kbuf_len,
+ size_t* klen);
};
__BEGIN_CDECLS
void hwkey_init_srv_provider(void);
-void hwkey_install_keys(const struct hwkey_keyslot *keys, uint kcnt);
+void hwkey_install_keys(const struct hwkey_keyslot* keys, uint kcnt);
-int hwkey_start_service(void);
+int hwkey_start_service(void);
-uint32_t derive_key_v1(const uuid_t *uuid,
- const uint8_t *ikm_data, size_t ikm_len,
- uint8_t *key_data, size_t *key_len);
+uint32_t derive_key_v1(const uuid_t* uuid,
+ const uint8_t* ikm_data,
+ size_t ikm_len,
+ uint8_t* key_data,
+ size_t* key_len);
__END_CDECLS
-
-
diff --git a/app/hwcrypto/hwkey_srv_provider.c b/app/hwcrypto/hwkey_srv_provider.c
index 9f55de7..3baab58 100644
--- a/app/hwcrypto/hwkey_srv_provider.c
+++ b/app/hwcrypto/hwkey_srv_provider.c
@@ -23,36 +23,36 @@
#include <uapi/err.h>
#include <interface/hwkey/hwkey.h>
-#include <openssl/cipher.h>
#include <openssl/aes.h>
+#include <openssl/cipher.h>
#include <openssl/digest.h>
#include <openssl/err.h>
#include <openssl/hkdf.h>
#include "caam.h"
#include "common.h"
-#include "uuids.h"
-#include "hwkey_srv_priv.h"
#include "hwkey_keyslots.h"
+#include "hwkey_srv_priv.h"
+#include "uuids.h"
-#define TLOG_LVL TLOG_LVL_DEFAULT
-#define TLOG_TAG "hwkey_caam"
+#define TLOG_LVL TLOG_LVL_DEFAULT
+#define TLOG_TAG "hwkey_caam"
#include "tlog.h"
-static const uint8_t skeymod[16] __attribute__ ((aligned (16))) = {
- 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00
-};
+static const uint8_t skeymod[16] __attribute__((aligned(16))) = {
+ 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00};
-static uint8_t kdfv1_key[32] __attribute__ ((aligned (32)));
+static uint8_t kdfv1_key[32] __attribute__((aligned(32)));
/*
* Derive key V1 - HKDF based key derive.
*/
-uint32_t derive_key_v1(const uuid_t *uuid,
- const uint8_t *ikm_data, size_t ikm_len,
- uint8_t *key_buf, size_t *key_len)
-{
+uint32_t derive_key_v1(const uuid_t* uuid,
+ const uint8_t* ikm_data,
+ size_t ikm_len,
+ uint8_t* key_buf,
+ size_t* key_len) {
uint32_t res;
*key_len = 0;
@@ -60,10 +60,9 @@
if (!ikm_len)
return HWKEY_ERR_BAD_LEN;
- if (!HKDF(key_buf, ikm_len, EVP_sha256(),
- (const uint8_t *)kdfv1_key, sizeof(kdfv1_key),
- (const uint8_t *)uuid, sizeof(uuid_t),
- ikm_data, ikm_len)) {
+ if (!HKDF(key_buf, ikm_len, EVP_sha256(), (const uint8_t*)kdfv1_key,
+ sizeof(kdfv1_key), (const uint8_t*)uuid, sizeof(uuid_t), ikm_data,
+ ikm_len)) {
TLOGE("HDKF failed 0x%x\n", ERR_get_error());
memset(key_buf, 0, ikm_len);
res = HWKEY_ERR_GENERIC;
@@ -78,28 +77,29 @@
/*
* RPMB Key support
*/
-#define RPMB_SS_AUTH_KEY_SIZE 32
-#define RPMB_SS_AUTH_KEY_ID "com.android.trusty.storage_auth.rpmb"
+#define RPMB_SS_AUTH_KEY_SIZE 32
+#define RPMB_SS_AUTH_KEY_ID "com.android.trusty.storage_auth.rpmb"
/* Secure storage service app uuid */
static const uuid_t ss_uuid = SECURE_STORAGE_SERVER_APP_UUID;
-static size_t rpmb_keyblob_len;
+static size_t rpmb_keyblob_len;
static uint8_t rpmb_keyblob[RPMBKEY_LEN];
/*
* Fetch RPMB Secure Storage Authentication key
*/
-static uint32_t get_rpmb_ss_auth_key(const struct hwkey_keyslot *slot,
- uint8_t *kbuf, size_t kbuf_len, size_t *klen)
-{
+static uint32_t get_rpmb_ss_auth_key(const struct hwkey_keyslot* slot,
+ uint8_t* kbuf,
+ size_t kbuf_len,
+ size_t* klen) {
uint32_t res;
assert(kbuf_len >= RPMB_SS_AUTH_KEY_SIZE);
if (rpmb_keyblob_len != sizeof(rpmb_keyblob))
return HWKEY_ERR_NOT_FOUND; /* no RPMB key */
- res = caam_decap_blob(skeymod, sizeof(skeymod),
- kbuf, rpmb_keyblob, RPMB_SS_AUTH_KEY_SIZE);
+ res = caam_decap_blob(skeymod, sizeof(skeymod), kbuf, rpmb_keyblob,
+ RPMB_SS_AUTH_KEY_SIZE);
if (res == CAAM_SUCCESS) {
*klen = RPMB_SS_AUTH_KEY_SIZE;
return HWKEY_NO_ERROR;
@@ -115,17 +115,16 @@
* List of keys slots that hwkey service supports
*/
static const struct hwkey_keyslot _keys[] = {
- {
- .uuid = &ss_uuid,
- .key_id = RPMB_SS_AUTH_KEY_ID,
- .handler = get_rpmb_ss_auth_key,
- },
+ {
+ .uuid = &ss_uuid,
+ .key_id = RPMB_SS_AUTH_KEY_ID,
+ .handler = get_rpmb_ss_auth_key,
+ },
};
-static void unpack_kbox(void)
-{
+static void unpack_kbox(void) {
uint32_t res;
- struct keyslot_package *kbox = caam_get_keybox();
+ struct keyslot_package* kbox = caam_get_keybox();
if (strncmp(kbox->magic, KEYPACK_MAGIC, 4)) {
TLOGE("Invalid magic\n");
@@ -151,12 +150,10 @@
memset(kbox, 0, sizeof(*kbox));
}
-
/*
* Initialize Fake HWKEY service provider
*/
-void hwkey_init_srv_provider(void)
-{
+void hwkey_init_srv_provider(void) {
int rc;
TLOGI("Init HWKEY service provider\n");
@@ -168,7 +165,7 @@
/* start service */
rc = hwkey_start_service();
- if (rc != NO_ERROR ) {
+ if (rc != NO_ERROR) {
TLOGE("failed (%d) to start HWKEY service\n", rc);
}
}
diff --git a/app/hwcrypto/hwrng_srv.c b/app/hwcrypto/hwrng_srv.c
index 0986d76..accd7a2 100644
--- a/app/hwcrypto/hwrng_srv.c
+++ b/app/hwcrypto/hwrng_srv.c
@@ -27,12 +27,12 @@
#include "common.h"
#include "hwrng_srv_priv.h"
-#define TLOG_LVL TLOG_LVL_DEFAULT
-#define TLOG_TAG "hwrng_srv"
+#define TLOG_LVL TLOG_LVL_DEFAULT
+#define TLOG_TAG "hwrng_srv"
#include "tlog.h"
-#define HWRNG_SRV_NAME HWRNG_PORT
-#define MAX_HWRNG_MSG_SIZE 4096
+#define HWRNG_SRV_NAME HWRNG_PORT
+#define MAX_HWRNG_MSG_SIZE 4096
struct hwrng_chan_ctx {
tipc_event_handler_t evt_handler;
@@ -42,13 +42,13 @@
bool send_blocked;
};
-static void hwrng_port_handler(const uevent_t *ev, void *priv);
-static void hwrng_chan_handler(const uevent_t *ev, void *priv);
+static void hwrng_port_handler(const uevent_t* ev, void* priv);
+static void hwrng_chan_handler(const uevent_t* ev, void* priv);
-static handle_t hwrng_port = INVALID_IPC_HANDLE;
+static handle_t hwrng_port = INVALID_IPC_HANDLE;
static tipc_event_handler_t hwrng_port_evt_handler = {
- .proc = hwrng_port_handler,
+ .proc = hwrng_port_handler,
};
static uint8_t rng_data[MAX_HWRNG_MSG_SIZE];
@@ -60,16 +60,15 @@
/*
* Hexdump content of memory region
*/
-static void _hexdump8(const void *ptr, size_t len)
-{
+static void _hexdump8(const void* ptr, size_t len) {
addr_t address = (addr_t)ptr;
size_t count;
size_t i;
- for (count = 0 ; count < len; count += 16) {
+ for (count = 0; count < len; count += 16) {
fprintf(stderr, "0x%08lx: ", address);
- for (i=0; i < MIN(len - count, 16); i++) {
- fprintf(stderr, "0x%02hhx ", *(const uint8_t *)(address + i));
+ for (i = 0; i < MIN(len - count, 16); i++) {
+ fprintf(stderr, "0x%02hhx ", *(const uint8_t*)(address + i));
}
fprintf(stderr, "\n");
address += 16;
@@ -79,8 +78,7 @@
/*
* Close specified HWRNG service channel
*/
-static void hwrng_close_chan(struct hwrng_chan_ctx *ctx)
-{
+static void hwrng_close_chan(struct hwrng_chan_ctx* ctx) {
close(ctx->chan);
if (list_in_list(&ctx->node))
@@ -92,18 +90,16 @@
/*
* Handle HWRNG request queue
*/
-static bool hwrng_handle_req_queue(void)
-{
- struct hwrng_chan_ctx *ctx;
- struct hwrng_chan_ctx *temp;
+static bool hwrng_handle_req_queue(void) {
+ struct hwrng_chan_ctx* ctx;
+ struct hwrng_chan_ctx* temp;
/* service channels */
bool need_more = false;
/* for all pending requests */
- list_for_every_entry_safe(&hwrng_req_list, ctx, temp,
- struct hwrng_chan_ctx, node) {
-
+ list_for_every_entry_safe(&hwrng_req_list, ctx, temp, struct hwrng_chan_ctx,
+ node) {
if (ctx->send_blocked)
continue; /* cant service it rignt now */
@@ -145,16 +141,14 @@
/*
* Check if we can handle request queue
*/
-static void hwrng_kick_req_queue(void)
-{
+static void hwrng_kick_req_queue(void) {
hwrng_handle_req_queue();
}
/*
* Read and queue HWRNG request message
*/
-static int hwrng_chan_handle_msg(struct hwrng_chan_ctx *ctx)
-{
+static int hwrng_chan_handle_msg(struct hwrng_chan_ctx* ctx) {
int rc;
struct hwrng_req req;
@@ -183,9 +177,8 @@
/*
* Channel handler where HWRNG requests are coming from
*/
-static void hwrng_chan_handler(const uevent_t *ev, void *priv)
-{
- struct hwrng_chan_ctx *ctx = priv;
+static void hwrng_chan_handler(const uevent_t* ev, void* priv) {
+ struct hwrng_chan_ctx* ctx = priv;
assert(ctx);
assert(ev->handle == ctx->chan);
@@ -214,8 +207,7 @@
/*
* Port were HWRNG requests are coming from
*/
-static void hwrng_port_handler(const uevent_t *ev, void *priv)
-{
+static void hwrng_port_handler(const uevent_t* ev, void* priv) {
uuid_t peer_uuid;
tipc_handle_port_errors(ev);
@@ -229,10 +221,10 @@
TLOGE("failed (%d) to accept on port %d\n", rc, ev->handle);
return;
}
- chan = (handle_t) rc;
+ chan = (handle_t)rc;
/* allocate state */
- struct hwrng_chan_ctx *ctx = calloc(1, sizeof(*ctx));
+ struct hwrng_chan_ctx* ctx = calloc(1, sizeof(*ctx));
if (!ctx) {
TLOGE("failed to alloc state for chan %d\n", chan);
close(chan);
@@ -258,8 +250,7 @@
/*
* Initialize HWRNG services
*/
-int hwrng_start_service(void)
-{
+int hwrng_start_service(void) {
int rc;
TLOGI("Start HWRNG service\n");
diff --git a/app/hwcrypto/hwrng_srv_priv.h b/app/hwcrypto/hwrng_srv_priv.h
index 5a26125..2cd715d 100644
--- a/app/hwcrypto/hwrng_srv_priv.h
+++ b/app/hwcrypto/hwrng_srv_priv.h
@@ -20,8 +20,8 @@
__BEGIN_CDECLS
void hwrng_init_srv_provider(void);
-int hwrng_start_service(void);
+int hwrng_start_service(void);
-void hwrng_dev_get_rng_data(uint8_t *buf, size_t buf_len);
+void hwrng_dev_get_rng_data(uint8_t* buf, size_t buf_len);
__END_CDECLS
diff --git a/app/hwcrypto/hwrng_srv_provider.c b/app/hwcrypto/hwrng_srv_provider.c
index 2f5957c..2cb81ac 100644
--- a/app/hwcrypto/hwrng_srv_provider.c
+++ b/app/hwcrypto/hwrng_srv_provider.c
@@ -16,27 +16,25 @@
*/
#include <assert.h>
-#include <uapi/err.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <uapi/err.h>
#include "caam.h"
#include "common.h"
#include "hwrng_srv_priv.h"
-#define TLOG_LVL TLOG_LVL_DEFAULT
-#define TLOG_TAG "hwrng_caam"
+#define TLOG_LVL TLOG_LVL_DEFAULT
+#define TLOG_TAG "hwrng_caam"
#include "tlog.h"
-void hwrng_dev_get_rng_data(uint8_t *buf, size_t buf_len)
-{
+void hwrng_dev_get_rng_data(uint8_t* buf, size_t buf_len) {
uint32_t res = caam_hwrng(buf, buf_len);
assert(res == CAAM_SUCCESS);
}
-void hwrng_init_srv_provider(void)
-{
+void hwrng_init_srv_provider(void) {
int rc;
TLOGE("Init HWRNG service provider\n");
@@ -46,4 +44,3 @@
TLOGE("failed (%d) to start HWRNG service\n", rc);
}
}
-
diff --git a/app/hwcrypto/main.c b/app/hwcrypto/main.c
index ac1ce4b..1348002 100644
--- a/app/hwcrypto/main.c
+++ b/app/hwcrypto/main.c
@@ -14,7 +14,6 @@
* limitations under the License.
*/
-
#include <assert.h>
#include <stdio.h>
#include <stdlib.h>
@@ -23,38 +22,35 @@
#include "caam.h"
#include "common.h"
-#include "hwrng_srv_priv.h"
#include "hwkey_srv_priv.h"
+#include "hwrng_srv_priv.h"
-#define TLOG_LVL TLOG_LVL_DEFAULT
-#define TLOG_TAG "hwcrypto"
+#define TLOG_LVL TLOG_LVL_DEFAULT
+#define TLOG_TAG "hwcrypto"
#include "tlog.h"
/*
* Hexdump content of memory region
*/
-void _hexdump8(const void *ptr, size_t len)
-{
+void _hexdump8(const void* ptr, size_t len) {
addr_t address = (addr_t)ptr;
size_t count;
size_t i;
- for (count = 0 ; count < len; count += 16) {
+ for (count = 0; count < len; count += 16) {
fprintf(stderr, "0x%08lx: ", address);
- for (i=0; i < MIN(len - count, 16); i++) {
- fprintf(stderr, "0x%02hhx ", *(const uint8_t *)(address + i));
+ for (i = 0; i < MIN(len - count, 16); i++) {
+ fprintf(stderr, "0x%02hhx ", *(const uint8_t*)(address + i));
}
fprintf(stderr, "\n");
address += 16;
}
}
-
/*
* Handle common unexpected port events
*/
-void tipc_handle_port_errors(const uevent_t *ev)
-{
+void tipc_handle_port_errors(const uevent_t* ev) {
if ((ev->event & IPC_HANDLE_POLL_ERROR) ||
(ev->event & IPC_HANDLE_POLL_HUP) ||
(ev->event & IPC_HANDLE_POLL_MSG) ||
@@ -68,8 +64,7 @@
/*
* Handle common unexpected channel events
*/
-void tipc_handle_chan_errors(const uevent_t *ev)
-{
+void tipc_handle_chan_errors(const uevent_t* ev) {
if ((ev->event & IPC_HANDLE_POLL_ERROR) ||
(ev->event & IPC_HANDLE_POLL_READY)) {
/* close it as it is in an error state */
@@ -81,11 +76,10 @@
/*
* Send single buf message
*/
-int tipc_send_single_buf(handle_t chan, const void *buf, size_t len)
-{
+int tipc_send_single_buf(handle_t chan, const void* buf, size_t len) {
iovec_t iov = {
- .base = (void *)buf,
- .len = len,
+ .base = (void*)buf,
+ .len = len,
};
ipc_msg_t msg = {
.iov = &iov,
@@ -98,8 +92,7 @@
/*
* Receive single buf message
*/
-int tipc_recv_single_buf(handle_t chan, void *buf, size_t len)
-{
+int tipc_recv_single_buf(handle_t chan, void* buf, size_t len) {
int rc;
ipc_msg_info_t msg_inf;
@@ -113,7 +106,7 @@
} else {
iovec_t iov = {
.base = buf,
- .len = len,
+ .len = len,
};
ipc_msg_t msg = {
.iov = &iov,
@@ -129,22 +122,24 @@
/*
* Send message consisting of two segments (header and payload)
*/
-int tipc_send_two_segments(handle_t chan, const void *hdr, size_t hdr_len,
- const void *payload, size_t payload_len)
-{
+int tipc_send_two_segments(handle_t chan,
+ const void* hdr,
+ size_t hdr_len,
+ const void* payload,
+ size_t payload_len) {
iovec_t iovs[2] = {
- {
- .base = (void *)hdr,
- .len = hdr_len,
- },
- {
- .base = (void *)payload,
- .len = payload_len,
- },
+ {
+ .base = (void*)hdr,
+ .len = hdr_len,
+ },
+ {
+ .base = (void*)payload,
+ .len = payload_len,
+ },
};
ipc_msg_t msg = {
- .iov = iovs,
- .num_iov = countof(iovs),
+ .iov = iovs,
+ .num_iov = countof(iovs),
};
return send_msg(chan, &msg);
}
@@ -152,9 +147,11 @@
/*
* Receive message consisting of two segments (header and payload).
*/
-int tipc_recv_two_segments(handle_t chan, void *hdr, size_t hdr_len,
- void *payload, size_t payload_len)
-{
+int tipc_recv_two_segments(handle_t chan,
+ void* hdr,
+ size_t hdr_len,
+ void* payload,
+ size_t payload_len) {
int rc;
ipc_msg_info_t msg_inf;
@@ -166,16 +163,14 @@
/* unexpected msg size */
rc = ERR_BAD_LEN;
} else {
- iovec_t iovs[2] = {
- {
- .base = hdr,
- .len = hdr_len,
- },
- {
- .base = payload,
- .len = payload_len,
- }
- };
+ iovec_t iovs[2] = {{
+ .base = hdr,
+ .len = hdr_len,
+ },
+ {
+ .base = payload,
+ .len = payload_len,
+ }};
ipc_msg_t msg = {
.iov = iovs,
.num_iov = countof(iovs),
@@ -190,8 +185,7 @@
/*
* Dispatch event
*/
-static void dispatch_event(const uevent_t *ev)
-{
+static void dispatch_event(const uevent_t* ev) {
assert(ev);
if (ev->event == IPC_HANDLE_POLL_NONE) {
@@ -201,7 +195,7 @@
}
/* check if we have handler */
- struct tipc_event_handler *handler = ev->cookie;
+ struct tipc_event_handler* handler = ev->cookie;
if (handler && handler->proc) {
/* invoke it */
handler->proc(ev, handler->priv);
@@ -209,8 +203,8 @@
}
/* no handler? close it */
- TLOGE("no handler for event (0x%x) with handle %d\n",
- ev->event, ev->handle);
+ TLOGE("no handler for event (0x%x) with handle %d\n", ev->event,
+ ev->handle);
close(ev->handle);
@@ -220,8 +214,7 @@
/*
* Main application event loop
*/
-int main(void)
-{
+int main(void) {
int rc;
uevent_t event;
@@ -242,7 +235,7 @@
/* enter main event loop */
while (true) {
event.handle = INVALID_IPC_HANDLE;
- event.event = 0;
+ event.event = 0;
event.cookie = NULL;
rc = wait_any(&event, -1);
diff --git a/app/hwcrypto/manifest.c b/app/hwcrypto/manifest.c
index b59bd55..adfbbaa 100644
--- a/app/hwcrypto/manifest.c
+++ b/app/hwcrypto/manifest.c
@@ -14,24 +14,30 @@
* limitations under the License.
*/
+#include <imx-regs.h>
#include <stddef.h>
#include <stdio.h>
#include <trusty_app_manifest.h>
-#include <imx-regs.h>
#include "caam.h"
#include "uuids.h"
-trusty_app_manifest_t TRUSTY_APP_MANIFEST_ATTRS trusty_app_manifest =
-{
- .uuid = IMX_HWCRYPTO_UUID,
+trusty_app_manifest_t TRUSTY_APP_MANIFEST_ATTRS trusty_app_manifest = {
+ .uuid = IMX_HWCRYPTO_UUID,
- .config_options = {
- /* Max HEAP size */
- TRUSTY_APP_CONFIG_MIN_HEAP_SIZE(2 * 4096),
- /* MMIO regions */
- TRUSTY_APP_CONFIG_MAP_MEM(CAAM_MMIO_ID, CAAM_PHY_BASE_ADDR, CAAM_REG_SIZE),
- TRUSTY_APP_CONFIG_MAP_MEM(CAAM_SEC_RAM_MMIO_ID, CAAM_PHY_ARB_BASE_ADDR, CAAM_SEC_RAM_SIZE),
- TRUSTY_APP_CONFIG_MAP_MEM(CCM_MMIO_ID, CCM_PHY_BASE_ADDR, CCM_REG_SIZE),
- },
+ .config_options =
+ {
+ /* Max HEAP size */
+ TRUSTY_APP_CONFIG_MIN_HEAP_SIZE(2 * 4096),
+ /* MMIO regions */
+ TRUSTY_APP_CONFIG_MAP_MEM(CAAM_MMIO_ID,
+ CAAM_PHY_BASE_ADDR,
+ CAAM_REG_SIZE),
+ TRUSTY_APP_CONFIG_MAP_MEM(CAAM_SEC_RAM_MMIO_ID,
+ CAAM_PHY_ARB_BASE_ADDR,
+ CAAM_SEC_RAM_SIZE),
+ TRUSTY_APP_CONFIG_MAP_MEM(CCM_MMIO_ID,
+ CCM_PHY_BASE_ADDR,
+ CCM_REG_SIZE),
+ },
};
diff --git a/app/hwcrypto/tlog.h b/app/hwcrypto/tlog.h
index 622a589..2445f1c 100644
--- a/app/hwcrypto/tlog.h
+++ b/app/hwcrypto/tlog.h
@@ -18,10 +18,10 @@
#include <stdio.h>
-#define TLOG_LVL_NONE 0
-#define TLOG_LVL_ERROR 1
-#define TLOG_LVL_INFO 2
-#define TLOG_LVL_DEBUG 3
+#define TLOG_LVL_NONE 0
+#define TLOG_LVL_ERROR 1
+#define TLOG_LVL_INFO 2
+#define TLOG_LVL_DEBUG 3
#ifndef TLOG_LVL
#define TLOG_LVL TLOG_LVL_DEFAULT
@@ -29,21 +29,21 @@
#if TLOG_LVL >= TLOG_LVL_DEBUG
#define TLOGD(fmt, ...) \
- fprintf(stderr, "%s: %d: " fmt, TLOG_TAG, __LINE__, ## __VA_ARGS__)
+ fprintf(stderr, "%s: %d: " fmt, TLOG_TAG, __LINE__, ##__VA_ARGS__)
#else
#define TLOGD(fmt, ...)
#endif
#if TLOG_LVL >= TLOG_LVL_INFO
#define TLOGI(fmt, ...) \
- fprintf(stderr, "%s: %d: " fmt, TLOG_TAG, __LINE__, ## __VA_ARGS__)
+ fprintf(stderr, "%s: %d: " fmt, TLOG_TAG, __LINE__, ##__VA_ARGS__)
#else
#define TLOGI(fmt, ...)
#endif
#if TLOG_LVL >= TLOG_LVL_ERROR
#define TLOGE(fmt, ...) \
- fprintf(stderr, "%s: %d: " fmt, TLOG_TAG, __LINE__, ## __VA_ARGS__)
+ fprintf(stderr, "%s: %d: " fmt, TLOG_TAG, __LINE__, ##__VA_ARGS__)
#else
#define TLOGE(fmt, ...)
#endif
diff --git a/app/hwcrypto/uuids.h b/app/hwcrypto/uuids.h
index 63e36d6..b1ef05e 100644
--- a/app/hwcrypto/uuids.h
+++ b/app/hwcrypto/uuids.h
@@ -17,16 +17,25 @@
#pragma once
/* This App UUID: {1adaf827-806b-4bcf-bcec-7e7d2f5a0a5c} */
-#define IMX_HWCRYPTO_UUID \
- { 0x1adaf827, 0x806b, 0x4bcf, \
- { 0xbc, 0xec, 0x7e, 0x7d, 0x2f, 0x5a, 0x0a, 0x5c }}
+#define IMX_HWCRYPTO_UUID \
+ { \
+ 0x1adaf827, 0x806b, 0x4bcf, { \
+ 0xbc, 0xec, 0x7e, 0x7d, 0x2f, 0x5a, 0x0a, 0x5c \
+ } \
+ }
/* HWCRYPTO unittest App UUID */
-#define HWCRYPTO_UNITTEST_APP_UUID \
- { 0xab742471, 0xd6e6, 0x4806, \
- { 0x85, 0xf6, 0x05, 0x55, 0xb0, 0x24, 0xf4, 0xda }}
+#define HWCRYPTO_UNITTEST_APP_UUID \
+ { \
+ 0xab742471, 0xd6e6, 0x4806, { \
+ 0x85, 0xf6, 0x05, 0x55, 0xb0, 0x24, 0xf4, 0xda \
+ } \
+ }
/* Secure Storage Server App UUID */
-#define SECURE_STORAGE_SERVER_APP_UUID \
- {0xcea8706d, 0x6cb4, 0x49f3,\
- { 0xb9, 0x94, 0x29, 0xe0, 0xe4, 0x78, 0xbd, 0x29 }}
+#define SECURE_STORAGE_SERVER_APP_UUID \
+ { \
+ 0xcea8706d, 0x6cb4, 0x49f3, { \
+ 0xb9, 0x94, 0x29, 0xe0, 0xe4, 0x78, 0xbd, 0x29 \
+ } \
+ }
diff --git a/platform/imx/common/include/platform/tzasc.h b/platform/imx/common/include/platform/tzasc.h
index 56d2e7b..1448fe3 100644
--- a/platform/imx/common/include/platform/tzasc.h
+++ b/platform/imx/common/include/platform/tzasc.h
@@ -29,66 +29,65 @@
#ifndef TZASC_H_
#define TZASC_H_
-#include <reg.h>
#include <imx-regs.h>
+#include <reg.h>
#include <sys/types.h>
-#define TZ_IRQ 140
+#define TZ_IRQ 140
-#define TZ_REG(r) (*REG32(r))
+#define TZ_REG(r) (*REG32(r))
-#define TZ_CONFIG (TZ_BASE_VIRT + 0x000)
-#define TZ_ACTION (TZ_BASE_VIRT + 0x004)
-#define TZ_INT_STATUS (TZ_BASE_VIRT + 0x010)
-#define TZ_INT_CLEAR (TZ_BASE_VIRT + 0x014)
-#define TZ_FAIL_ADDR_LOW (TZ_BASE_VIRT + 0x020)
-#define TZ_FAIL_ADDR_HIGH (TZ_BASE_VIRT + 0x024)
-#define TZ_FAIL_CONTROL (TZ_BASE_VIRT + 0x028)
-#define TZ_FAIL_ID (TZ_BASE_VIRT + 0x02c)
-#define TZ_SPECULATION_CTL (TZ_BASE_VIRT + 0x030)
-#define TZ_SPECULATION_CTL_DISABLE_ALL (0x3)
+#define TZ_CONFIG (TZ_BASE_VIRT + 0x000)
+#define TZ_ACTION (TZ_BASE_VIRT + 0x004)
+#define TZ_INT_STATUS (TZ_BASE_VIRT + 0x010)
+#define TZ_INT_CLEAR (TZ_BASE_VIRT + 0x014)
+#define TZ_FAIL_ADDR_LOW (TZ_BASE_VIRT + 0x020)
+#define TZ_FAIL_ADDR_HIGH (TZ_BASE_VIRT + 0x024)
+#define TZ_FAIL_CONTROL (TZ_BASE_VIRT + 0x028)
+#define TZ_FAIL_ID (TZ_BASE_VIRT + 0x02c)
+#define TZ_SPECULATION_CTL (TZ_BASE_VIRT + 0x030)
+#define TZ_SPECULATION_CTL_DISABLE_ALL (0x3)
-#define TZ_REGION_BASE (TZ_BASE_VIRT + 0x100)
-#define TZ_GET_REGION_ADDR(n) (TZ_REGION_BASE + (n * 0x10))
+#define TZ_REGION_BASE (TZ_BASE_VIRT + 0x100)
+#define TZ_GET_REGION_ADDR(n) (TZ_REGION_BASE + (n * 0x10))
-#define TZ_SP_NS_W (0x1 << 0)
-#define TZ_SP_NS_R (0x1 << 1)
-#define TZ_SP_S_W (0x1 << 2)
-#define TZ_SP_S_R (0x1 << 3)
+#define TZ_SP_NS_W (0x1 << 0)
+#define TZ_SP_NS_R (0x1 << 1)
+#define TZ_SP_S_W (0x1 << 2)
+#define TZ_SP_S_R (0x1 << 3)
-#define TZ_SP_SHIFT 28
-#define TZ_ATTR_SP_S_WR_ONLR (0x0 | ((TZ_SP_S_W | TZ_SP_S_R) << TZ_SP_SHIFT))
-#define TZ_ATTR_SP_ALL (0x0 | ((TZ_SP_S_W | TZ_SP_S_R | TZ_SP_NS_R | TZ_SP_NS_W) << TZ_SP_SHIFT))
+#define TZ_SP_SHIFT 28
+#define TZ_ATTR_SP_S_WR_ONLR (0x0 | ((TZ_SP_S_W | TZ_SP_S_R) << TZ_SP_SHIFT))
+#define TZ_ATTR_SP_ALL \
+ (0x0 | ((TZ_SP_S_W | TZ_SP_S_R | TZ_SP_NS_R | TZ_SP_NS_W) << TZ_SP_SHIFT))
-#define TZ_REGION_SIZE_4M 0x15
-#define TZ_REGION_SIZE_8M 0x16
-#define TZ_REGION_SIZE_16M 0x17
-#define TZ_REGION_SIZE_32M 0x18
-#define TZ_REGION_SIZE_64M 0x19
-#define TZ_REGION_SIZE_128M 0x1A
-#define TZ_REGION_SIZE_256M 0x1B
-#define TZ_REGION_SIZE_512M 0x1C
-#define TZ_REGION_SIZE_1G 0x1D
-#define TZ_REGION_SIZE_2G 0x1E
-#define TZ_REGION_SIZE_4G 0x1F
+#define TZ_REGION_SIZE_4M 0x15
+#define TZ_REGION_SIZE_8M 0x16
+#define TZ_REGION_SIZE_16M 0x17
+#define TZ_REGION_SIZE_32M 0x18
+#define TZ_REGION_SIZE_64M 0x19
+#define TZ_REGION_SIZE_128M 0x1A
+#define TZ_REGION_SIZE_256M 0x1B
+#define TZ_REGION_SIZE_512M 0x1C
+#define TZ_REGION_SIZE_1G 0x1D
+#define TZ_REGION_SIZE_2G 0x1E
+#define TZ_REGION_SIZE_4G 0x1F
+#define TZ_REGION_SIZE_SHIFT 1
+#define TZ_ATTR_REGION_SIZE(s) (0x0 | ((s) << TZ_REGION_SIZE_SHIFT))
-#define TZ_REGION_SIZE_SHIFT 1
-#define TZ_ATTR_REGION_SIZE(s) (0x0 | ((s) << TZ_REGION_SIZE_SHIFT))
+#define TZ_ATTR_DISABLE_REGION 0x0
-#define TZ_ATTR_DISABLE_REGION 0x0
+#define TZ_REGION_ENABLE 0x1
+#define TZ_REGION_DISABLE 0x0
+#define TZ_ATTR(sp, sub_dis, size, en) (0x0 | (sp | sub_dis | size | en))
-#define TZ_REGION_ENABLE 0x1
-#define TZ_REGION_DISABLE 0x0
-#define TZ_ATTR(sp,sub_dis,size,en) (0x0 | (sp | sub_dis | size | en))
-
-
-typedef struct tzasc_region{
- paddr_t addr_l;
- paddr_t addr_h;
- uint32_t attr;
+typedef struct tzasc_region {
+ paddr_t addr_l;
+ paddr_t addr_h;
+ uint32_t attr;
} tzasc_region_t;
-void initial_tzasc(const tzasc_region_t *r, uint num);
+void initial_tzasc(const tzasc_region_t* r, uint num);
#endif
diff --git a/platform/imx/debug.c b/platform/imx/debug.c
index a00d95d..d10e510 100644
--- a/platform/imx/debug.c
+++ b/platform/imx/debug.c
@@ -21,22 +21,19 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <dev/uart.h>
#include <kernel/thread.h>
#include <platform/debug.h>
-#include <dev/uart.h>
-
-void platform_dputc(char c)
-{
- uart_putc(0, c);
+void platform_dputc(char c) {
+ uart_putc(0, c);
}
-int platform_dgetc(char *c, bool wait)
-{
- int res = -1;
+int platform_dgetc(char* c, bool wait) {
+ int res = -1;
- if (wait)
- thread_sleep(100);
+ if (wait)
+ thread_sleep(100);
- return res;
+ return res;
}
diff --git a/platform/imx/drivers/imx_uart.c b/platform/imx/drivers/imx_uart.c
index 724e560..b9835d8 100644
--- a/platform/imx/drivers/imx_uart.c
+++ b/platform/imx/drivers/imx_uart.c
@@ -26,96 +26,93 @@
*/
#include <debug.h>
-#include <reg.h>
#include <dev/uart.h>
#include <imx-regs.h>
+#include <reg.h>
-#define READ32(addr) (*REG32(addr))
-#define WRITE32(val, addr) (READ32(addr) = val)
+#define READ32(addr) (*REG32(addr))
+#define WRITE32(val, addr) (READ32(addr) = val)
/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx31) */
+#define URXD 0x0 /* Receiver Register */
+#define UTXD 0x40 /* Transmitter Register */
+#define UCR1 0x80 /* Control Register 1 */
+#define UCR2 0x84 /* Control Register 2 */
+#define UCR3 0x88 /* Control Register 3 */
+#define UCR4 0x8c /* Control Register 4 */
+#define UFCR 0x90 /* FIFO Control Register */
+#define USR1 0x94 /* Status Register 1 */
+#define USR2 0x98 /* Status Register 2 */
+#define UESC 0x9c /* Escape Character Register */
+#define UTIM 0xa0 /* Escape Timer Register */
+#define UBIR 0xa4 /* BRM Incremental Register */
+#define UBMR 0xa8 /* BRM Modulator Register */
+#define UBRC 0xac /* Baud Rate Count Register */
+#define UTS 0xb4 /* UART Test Register (mx31) */
/* UART Control Register Bit Fields.*/
-#define URXD_CHARRDY (1<<15)
-#define URXD_ERR (1<<14)
-#define URXD_OVRRUN (1<<13)
-#define URXD_FRMERR (1<<12)
-#define URXD_BRK (1<<11)
-#define URXD_PRERR (1<<10)
-#define URXD_RX_DATA (0xFF)
-#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
-#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
-#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
-#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
-#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
-#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
-#define UCR1_IREN (1<<7) /* Infrared interface enable */
-#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
-#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
-#define UCR1_SNDBRK (1<<4) /* Send break */
-#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
-#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
-#define UCR1_DOZE (1<<1) /* Doze */
-#define UCR1_UARTEN (1<<0) /* UART enabled */
+#define URXD_CHARRDY (1 << 15)
+#define URXD_ERR (1 << 14)
+#define URXD_OVRRUN (1 << 13)
+#define URXD_FRMERR (1 << 12)
+#define URXD_BRK (1 << 11)
+#define URXD_PRERR (1 << 10)
+#define URXD_RX_DATA (0xFF)
+#define UCR1_ADEN (1 << 15) /* Auto dectect interrupt */
+#define UCR1_ADBR (1 << 14) /* Auto detect baud rate */
+#define UCR1_TRDYEN (1 << 13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN (1 << 12) /* Idle condition interrupt */
+#define UCR1_RRDYEN (1 << 9) /* Recv ready interrupt enable */
+#define UCR1_RDMAEN (1 << 8) /* Recv ready DMA enable */
+#define UCR1_IREN (1 << 7) /* Infrared interface enable */
+#define UCR1_TXMPTYEN (1 << 6) /* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN (1 << 5) /* RTS delta interrupt enable */
+#define UCR1_SNDBRK (1 << 4) /* Send break */
+#define UCR1_TDMAEN (1 << 3) /* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN (1 << 2) /* UART clock enabled */
+#define UCR1_DOZE (1 << 1) /* Doze */
+#define UCR1_UARTEN (1 << 0) /* UART enabled */
-#define UTS_FRCPERR (1<<13) /* Force parity error */
-#define UTS_LOOP (1<<12) /* Loop tx and rx */
-#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
-#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
-#define UTS_SOFTRST (1<<0) /* Software reset */
-#define UART_BASE (SOC_REGS_VIRT + (CONFIG_CONSOLE_TTY_BASE - SOC_REGS_PHY))
+#define UTS_FRCPERR (1 << 13) /* Force parity error */
+#define UTS_LOOP (1 << 12) /* Loop tx and rx */
+#define UTS_TXEMPTY (1 << 6) /* TxFIFO empty */
+#define UTS_RXEMPTY (1 << 5) /* RxFIFO empty */
+#define UTS_TXFULL (1 << 4) /* TxFIFO full */
+#define UTS_RXFULL (1 << 3) /* RxFIFO full */
+#define UTS_SOFTRST (1 << 0) /* Software reset */
+#define UART_BASE (SOC_REGS_VIRT + (CONFIG_CONSOLE_TTY_BASE - SOC_REGS_PHY))
-void uart_init(void)
-{
- /*
- * Do nothing, debug uart share with normal world,
- * everything for uart intialization were done in bootloader.
- */
+void uart_init(void) {
+ /*
+ * Do nothing, debug uart share with normal world,
+ * everything for uart intialization were done in bootloader.
+ */
}
-void uart_flush_tx(int port)
-{
- while (!(READ32(UART_BASE + UTS) & UTS_TXEMPTY))
- ;
+void uart_flush_tx(int port) {
+ while (!(READ32(UART_BASE + UTS) & UTS_TXEMPTY))
+ ;
}
-int uart_getc(int port, bool wait)
-{
- if (wait)
- while (READ32(UART_BASE + UTS) & UTS_RXEMPTY);
- else if (!(READ32(UART_BASE + UTS) & UTS_RXEMPTY))
- return -1;
+int uart_getc(int port, bool wait) {
+ if (wait)
+ while (READ32(UART_BASE + UTS) & UTS_RXEMPTY)
+ ;
+ else if (!(READ32(UART_BASE + UTS) & UTS_RXEMPTY))
+ return -1;
- return (READ32(UART_BASE + URXD) & URXD_RX_DATA);
+ return (READ32(UART_BASE + URXD) & URXD_RX_DATA);
}
-int uart_putc(int port, char c )
-{
- if (c == '\n')
- uart_putc(0, '\r');
+int uart_putc(int port, char c) {
+ if (c == '\n')
+ uart_putc(0, '\r');
- WRITE32(c, UART_BASE + UTXD);
+ WRITE32(c, UART_BASE + UTXD);
- /* wait until sent */
- while (!(READ32(UART_BASE + UTS) & UTS_TXEMPTY))
- ;
+ /* wait until sent */
+ while (!(READ32(UART_BASE + UTS) & UTS_TXEMPTY))
+ ;
- return 0;
+ return 0;
}
diff --git a/platform/imx/platform.c b/platform/imx/platform.c
index b7755cb..1e1aa48 100644
--- a/platform/imx/platform.c
+++ b/platform/imx/platform.c
@@ -21,10 +21,10 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <imx-regs.h>
#include <debug.h>
#include <dev/interrupt/arm_gic.h>
#include <dev/timer/arm_generic.h>
+#include <imx-regs.h>
#include <kernel/vm.h>
#include <lk/init.h>
#include <string.h>
@@ -33,98 +33,90 @@
#include <tzasc_regions.h>
#endif
-
#define ARM_GENERIC_TIMER_INT_CNTV 27
#define ARM_GENERIC_TIMER_INT_CNTPS 29
#define ARM_GENERIC_TIMER_INT_CNTP 30
-#define ARM_GENERIC_TIMER_INT_SELECTED(timer) ARM_GENERIC_TIMER_INT_ ## timer
-#define XARM_GENERIC_TIMER_INT_SELECTED(timer) ARM_GENERIC_TIMER_INT_SELECTED(timer)
-#define ARM_GENERIC_TIMER_INT XARM_GENERIC_TIMER_INT_SELECTED(TIMER_ARM_GENERIC_SELECTED)
+#define ARM_GENERIC_TIMER_INT_SELECTED(timer) ARM_GENERIC_TIMER_INT_##timer
+#define XARM_GENERIC_TIMER_INT_SELECTED(timer) \
+ ARM_GENERIC_TIMER_INT_SELECTED(timer)
+#define ARM_GENERIC_TIMER_INT \
+ XARM_GENERIC_TIMER_INT_SELECTED(TIMER_ARM_GENERIC_SELECTED)
/* initial memory mappings. parsed by start.S */
struct mmu_initial_mapping mmu_initial_mappings[] = {
- /* Mark next entry as dynamic as it might be updated
- by platform_reset code to specify actual size and
- location of RAM to use */
- {
- .phys = MEMBASE + KERNEL_LOAD_OFFSET,
- .virt = KERNEL_BASE + KERNEL_LOAD_OFFSET,
- .size = MEMSIZE,
- .flags = MMU_INITIAL_MAPPING_FLAG_DYNAMIC,
- .name = "ram" },
- {
- .phys = SOC_REGS_PHY,
- .virt = SOC_REGS_VIRT,
- .size = SOC_REGS_SIZE,
- .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
- .name = "soc"
- },
- /* null entry to terminate the list */
- { 0 }
-};
+ /* Mark next entry as dynamic as it might be updated
+ by platform_reset code to specify actual size and
+ location of RAM to use */
+ {.phys = MEMBASE + KERNEL_LOAD_OFFSET,
+ .virt = KERNEL_BASE + KERNEL_LOAD_OFFSET,
+ .size = MEMSIZE,
+ .flags = MMU_INITIAL_MAPPING_FLAG_DYNAMIC,
+ .name = "ram"},
+ {.phys = SOC_REGS_PHY,
+ .virt = SOC_REGS_VIRT,
+ .size = SOC_REGS_SIZE,
+ .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
+ .name = "soc"},
+ /* null entry to terminate the list */
+ {0}};
-static pmm_arena_t ram_arena = {
- .name = "ram",
- .base = MEMBASE + KERNEL_LOAD_OFFSET,
- .size = MEMSIZE,
- .flags = PMM_ARENA_FLAG_KMAP
-};
+static pmm_arena_t ram_arena = {.name = "ram",
+ .base = MEMBASE + KERNEL_LOAD_OFFSET,
+ .size = MEMSIZE,
+ .flags = PMM_ARENA_FLAG_KMAP};
+void platform_init_mmu_mappings(void) {
+ /* go through mmu_initial_mapping to find dynamic entry
+ * matching ram_arena (by name) and adjust it.
+ */
+ struct mmu_initial_mapping* m = mmu_initial_mappings;
+ for (uint i = 0; i < countof(mmu_initial_mappings); i++, m++) {
+ if (!(m->flags & MMU_INITIAL_MAPPING_FLAG_DYNAMIC))
+ continue;
-void platform_init_mmu_mappings(void)
-{
- /* go through mmu_initial_mapping to find dynamic entry
- * matching ram_arena (by name) and adjust it.
- */
- struct mmu_initial_mapping *m = mmu_initial_mappings;
- for (uint i = 0; i < countof(mmu_initial_mappings); i++, m++) {
- if (!(m->flags & MMU_INITIAL_MAPPING_FLAG_DYNAMIC))
- continue;
+ if (strcmp(m->name, ram_arena.name) == 0) {
+ /* update ram_arena */
+ ram_arena.base = m->phys;
+ ram_arena.size = m->size;
+ ram_arena.flags = PMM_ARENA_FLAG_KMAP;
- if (strcmp(m->name, ram_arena.name) == 0) {
- /* update ram_arena */
- ram_arena.base = m->phys;
- ram_arena.size = m->size;
- ram_arena.flags = PMM_ARENA_FLAG_KMAP;
-
- break;
- }
- }
- pmm_add_arena(&ram_arena);
+ break;
+ }
+ }
+ pmm_add_arena(&ram_arena);
}
-static void generic_arm64_map_regs(const char *name, vaddr_t vaddr,
- paddr_t paddr, size_t size)
-{
- status_t ret;
- void *vaddrp = (void *)vaddr;
+static void generic_arm64_map_regs(const char* name,
+ vaddr_t vaddr,
+ paddr_t paddr,
+ size_t size) {
+ status_t ret;
+ void* vaddrp = (void*)vaddr;
- ret = vmm_alloc_physical(vmm_get_kernel_aspace(), name,
- size, &vaddrp, 0, paddr,
- VMM_FLAG_VALLOC_SPECIFIC,
- ARCH_MMU_FLAG_UNCACHED_DEVICE);
- if (ret) {
- dprintf(CRITICAL, "%s: failed %d name=%s\n", __func__, ret, name);
- }
+ ret = vmm_alloc_physical(vmm_get_kernel_aspace(), name, size, &vaddrp, 0,
+ paddr, VMM_FLAG_VALLOC_SPECIFIC,
+ ARCH_MMU_FLAG_UNCACHED_DEVICE);
+ if (ret) {
+ dprintf(CRITICAL, "%s: failed %d name=%s\n", __func__, ret, name);
+ }
}
-static void platform_after_vm_init(uint level)
-{
- generic_arm64_map_regs("gic", GIC_BASE_VIRT, GIC_BASE_PHY, GIC_REG_SIZE);
+static void platform_after_vm_init(uint level) {
+ generic_arm64_map_regs("gic", GIC_BASE_VIRT, GIC_BASE_PHY, GIC_REG_SIZE);
- /* Initialize the interrupt controller. */
- arm_gic_init();
+ /* Initialize the interrupt controller. */
+ arm_gic_init();
- /* Initialize the timer block. */
- arm_generic_timer_init(ARM_GENERIC_TIMER_INT, 0);
+ /* Initialize the timer block. */
+ arm_generic_timer_init(ARM_GENERIC_TIMER_INT, 0);
- /* SOC is mapped in initial mapping */
+ /* SOC is mapped in initial mapping */
#ifdef WITH_TZASC
- /* Initialize TZASC. */
- /* TZASC registers are mapped by initial mapping */
- initial_tzasc(tzasc_regions, countof(tzasc_regions));
+ /* Initialize TZASC. */
+ /* TZASC registers are mapped by initial mapping */
+ initial_tzasc(tzasc_regions, countof(tzasc_regions));
#endif
}
@@ -134,13 +126,13 @@
extern void virt_timer_init(void);
/* Reset CNTVOFF register to be able to use virt arch timer */
-static void platform_per_cpu_virt_timer_init(uint level)
-{
- virt_timer_init();
+static void platform_per_cpu_virt_timer_init(uint level) {
+ virt_timer_init();
}
LK_INIT_HOOK_FLAGS(platform_per_cpu_virt_timer,
platform_per_cpu_virt_timer_init,
- LK_INIT_LEVEL_PLATFORM_EARLY, LK_INIT_FLAG_ALL_CPUS);
+ LK_INIT_LEVEL_PLATFORM_EARLY,
+ LK_INIT_FLAG_ALL_CPUS);
#endif
diff --git a/platform/imx/soc/imx6ul/include/imx-regs.h b/platform/imx/soc/imx6ul/include/imx-regs.h
index 779f8c2..ade0248 100644
--- a/platform/imx/soc/imx6ul/include/imx-regs.h
+++ b/platform/imx/soc/imx6ul/include/imx-regs.h
@@ -34,7 +34,7 @@
#define GIC_BASE_PHY 0xa01000
#define GIC_BASE_VIRT 0x70a01000
-#define SOC_REGS_PHY 0x02000000
+#define SOC_REGS_PHY 0x02000000
#define SOC_REGS_VIRT 0x72000000
#define SOC_REGS_SIZE 0x00400000
@@ -47,7 +47,7 @@
#define CCM_PHY_BASE_ADDR (0x02000000 + 0x80000 + 0x44000)
#define CCM_REG_SIZE 0x4000
-#define CCM_CAAM_CCGR_OFFSET (0x68) /* CAAM CCGR (CCGR0) */
+#define CCM_CAAM_CCGR_OFFSET (0x68) /* CAAM CCGR (CCGR0) */
/* Registers for GIC */
#define MAX_INT 160
diff --git a/platform/imx/soc/imx6ul/include/tzasc_regions.h b/platform/imx/soc/imx6ul/include/tzasc_regions.h
index 9882d61..4733ab2 100644
--- a/platform/imx/soc/imx6ul/include/tzasc_regions.h
+++ b/platform/imx/soc/imx6ul/include/tzasc_regions.h
@@ -32,33 +32,26 @@
#include <platform/tzasc.h>
static const tzasc_region_t tzasc_regions[] = {
- {
- .addr_l = 0,
- .addr_h = 0,
- .attr = TZ_ATTR(TZ_ATTR_SP_ALL,
- TZ_ATTR_DISABLE_REGION,
- TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_4G),
- TZ_REGION_ENABLE)
- },
+ {.addr_l = 0,
+ .addr_h = 0,
+ .attr = TZ_ATTR(TZ_ATTR_SP_ALL,
+ TZ_ATTR_DISABLE_REGION,
+ TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_4G),
+ TZ_REGION_ENABLE)},
- {
- .addr_l = 0x80000000,
- .addr_h = 0,
- .attr = TZ_ATTR(TZ_ATTR_SP_ALL,
- TZ_ATTR_DISABLE_REGION,
- TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_512M),
- TZ_REGION_ENABLE)
- },
+ {.addr_l = 0x80000000,
+ .addr_h = 0,
+ .attr = TZ_ATTR(TZ_ATTR_SP_ALL,
+ TZ_ATTR_DISABLE_REGION,
+ TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_512M),
+ TZ_REGION_ENABLE)},
- {
- .addr_l = MEMBASE,
- .addr_h = 0x0,
- .attr = TZ_ATTR(TZ_ATTR_SP_S_WR_ONLR,
- TZ_ATTR_DISABLE_REGION,
- TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_32M),
- TZ_REGION_ENABLE)
- },
+ {.addr_l = MEMBASE,
+ .addr_h = 0x0,
+ .attr = TZ_ATTR(TZ_ATTR_SP_S_WR_ONLR,
+ TZ_ATTR_DISABLE_REGION,
+ TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_32M),
+ TZ_REGION_ENABLE)},
};
-
#endif
diff --git a/platform/imx/soc/imx7d/include/imx-regs.h b/platform/imx/soc/imx7d/include/imx-regs.h
index d8185f6..0df3df7 100644
--- a/platform/imx/soc/imx7d/include/imx-regs.h
+++ b/platform/imx/soc/imx7d/include/imx-regs.h
@@ -31,10 +31,10 @@
#define MACH_IMX7
-#define GIC_BASE_PHY 0x31001000
+#define GIC_BASE_PHY 0x31001000
#define GIC_BASE_VIRT 0x71001000
-#define SOC_REGS_PHY 0x30000000
+#define SOC_REGS_PHY 0x30000000
#define SOC_REGS_VIRT 0x70000000
#define SOC_REGS_SIZE 0x01000000
@@ -47,7 +47,7 @@
#define CCM_PHY_BASE_ADDR 0x30380000
#define CCM_REG_SIZE 0x10000
-#define CCM_CAAM_CCGR_OFFSET (0x4000 + 16 * 36) /* CAAM CCGR is CCGR36 */
+#define CCM_CAAM_CCGR_OFFSET (0x4000 + 16 * 36) /* CAAM CCGR is CCGR36 */
/* Registers for GIC */
#define MAX_INT 160
diff --git a/platform/imx/soc/imx7d/include/tzasc_regions.h b/platform/imx/soc/imx7d/include/tzasc_regions.h
index 9882d61..4733ab2 100644
--- a/platform/imx/soc/imx7d/include/tzasc_regions.h
+++ b/platform/imx/soc/imx7d/include/tzasc_regions.h
@@ -32,33 +32,26 @@
#include <platform/tzasc.h>
static const tzasc_region_t tzasc_regions[] = {
- {
- .addr_l = 0,
- .addr_h = 0,
- .attr = TZ_ATTR(TZ_ATTR_SP_ALL,
- TZ_ATTR_DISABLE_REGION,
- TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_4G),
- TZ_REGION_ENABLE)
- },
+ {.addr_l = 0,
+ .addr_h = 0,
+ .attr = TZ_ATTR(TZ_ATTR_SP_ALL,
+ TZ_ATTR_DISABLE_REGION,
+ TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_4G),
+ TZ_REGION_ENABLE)},
- {
- .addr_l = 0x80000000,
- .addr_h = 0,
- .attr = TZ_ATTR(TZ_ATTR_SP_ALL,
- TZ_ATTR_DISABLE_REGION,
- TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_512M),
- TZ_REGION_ENABLE)
- },
+ {.addr_l = 0x80000000,
+ .addr_h = 0,
+ .attr = TZ_ATTR(TZ_ATTR_SP_ALL,
+ TZ_ATTR_DISABLE_REGION,
+ TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_512M),
+ TZ_REGION_ENABLE)},
- {
- .addr_l = MEMBASE,
- .addr_h = 0x0,
- .attr = TZ_ATTR(TZ_ATTR_SP_S_WR_ONLR,
- TZ_ATTR_DISABLE_REGION,
- TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_32M),
- TZ_REGION_ENABLE)
- },
+ {.addr_l = MEMBASE,
+ .addr_h = 0x0,
+ .attr = TZ_ATTR(TZ_ATTR_SP_S_WR_ONLR,
+ TZ_ATTR_DISABLE_REGION,
+ TZ_ATTR_REGION_SIZE(TZ_REGION_SIZE_32M),
+ TZ_REGION_ENABLE)},
};
-
#endif
diff --git a/platform/imx/soc/imx7d/secondary_init.c b/platform/imx/soc/imx7d/secondary_init.c
index 9e09fe9..172d671 100644
--- a/platform/imx/soc/imx7d/secondary_init.c
+++ b/platform/imx/soc/imx7d/secondary_init.c
@@ -29,10 +29,9 @@
extern void platform_secondary_entry(void);
-static void imx7d_smp_init(uint level)
-{
- paddr_t entry_pa = vaddr_to_paddr(platform_secondary_entry);
- writel(entry_pa, SRC_GPR3);
+static void imx7d_smp_init(uint level) {
+ paddr_t entry_pa = vaddr_to_paddr(platform_secondary_entry);
+ writel(entry_pa, SRC_GPR3);
}
LK_INIT_HOOK(imx7d_smp, imx7d_smp_init, LK_INIT_LEVEL_LAST);
diff --git a/platform/imx/tzasc.c b/platform/imx/tzasc.c
index 0fc8666..728bddc 100644
--- a/platform/imx/tzasc.c
+++ b/platform/imx/tzasc.c
@@ -29,20 +29,19 @@
#include <compiler.h>
#include <platform/tzasc.h>
-void initial_tzasc(const tzasc_region_t *r, uint num)
-{
- /*
- * ACTION field 0x2 means
- * sets tzasc_int HIGH and issues an OKAY response
- */
- TZ_REG(TZ_ACTION) = 0x2;
+void initial_tzasc(const tzasc_region_t* r, uint num) {
+ /*
+ * ACTION field 0x2 means
+ * sets tzasc_int HIGH and issues an OKAY response
+ */
+ TZ_REG(TZ_ACTION) = 0x2;
- //From number 0 region to config.
- for (uint i = 0; i < num; i++, r++) {
- TZ_REG(TZ_GET_REGION_ADDR(i)) = r->addr_l;
- TZ_REG(TZ_GET_REGION_ADDR(i) + 0x4) = r->addr_h;
- TZ_REG(TZ_GET_REGION_ADDR(i) + 0x8) = r->attr;
- }
+ // From number 0 region to config.
+ for (uint i = 0; i < num; i++, r++) {
+ TZ_REG(TZ_GET_REGION_ADDR(i)) = r->addr_l;
+ TZ_REG(TZ_GET_REGION_ADDR(i) + 0x4) = r->addr_h;
+ TZ_REG(TZ_GET_REGION_ADDR(i) + 0x8) = r->attr;
+ }
- TZ_REG(TZ_INT_CLEAR) = 0;
+ TZ_REG(TZ_INT_CLEAR) = 0;
}
