| /* |
| * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| #include <arch.h> |
| #include <asm_macros.S> |
| #include <mt8173_def.h> |
| |
| .globl plat_secondary_cold_boot_setup |
| .globl plat_report_exception |
| .globl platform_is_primary_cpu |
| .globl plat_my_core_pos |
| |
| /* ----------------------------------------------------- |
| * void plat_secondary_cold_boot_setup (void); |
| * |
| * This function performs any platform specific actions |
| * needed for a secondary cpu after a cold reset e.g |
| * mark the cpu's presence, mechanism to place it in a |
| * holding pen etc. |
| * ----------------------------------------------------- |
| */ |
| func plat_secondary_cold_boot_setup |
| /* MT8173 Oak does not do cold boot for secondary CPU */ |
| cb_panic: |
| b cb_panic |
| endfunc plat_secondary_cold_boot_setup |
| |
| func platform_is_primary_cpu |
| and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) |
| cmp x0, #MT8173_PRIMARY_CPU |
| cset x0, eq |
| ret |
| endfunc platform_is_primary_cpu |
| |
| /* ----------------------------------------------------- |
| * unsigned int plat_my_core_pos(void); |
| * |
| * result: CorePos = CoreId + (ClusterId << 2) |
| * ----------------------------------------------------- |
| */ |
| func plat_my_core_pos |
| mrs x0, mpidr_el1 |
| and x1, x0, #MPIDR_CPU_MASK |
| and x0, x0, #MPIDR_CLUSTER_MASK |
| add x0, x1, x0, LSR #6 |
| ret |
| endfunc plat_my_core_pos |
