| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK |
| |
| --- | |
| define i32 @test_icmp_eq_i8(i8 %a, i8 %b) { |
| %r = icmp eq i8 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_eq_i16(i16 %a, i16 %b) { |
| %r = icmp eq i16 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_eq_i64(i64 %a, i64 %b) { |
| %r = icmp eq i64 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_eq_i32(i32 %a, i32 %b) { |
| %r = icmp eq i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_ne_i32(i32 %a, i32 %b) { |
| %r = icmp ne i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_ugt_i32(i32 %a, i32 %b) { |
| %r = icmp ugt i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_uge_i32(i32 %a, i32 %b) { |
| %r = icmp uge i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_ult_i32(i32 %a, i32 %b) { |
| %r = icmp ult i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_ule_i32(i32 %a, i32 %b) { |
| %r = icmp ule i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_sgt_i32(i32 %a, i32 %b) { |
| %r = icmp sgt i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_sge_i32(i32 %a, i32 %b) { |
| %r = icmp sge i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_slt_i32(i32 %a, i32 %b) { |
| %r = icmp slt i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| define i32 @test_icmp_sle_i32(i32 %a, i32 %b) { |
| %r = icmp sle i32 %a, %b |
| %res = zext i1 %r to i32 |
| ret i32 %res |
| } |
| |
| ... |
| --- |
| name: test_icmp_eq_i8 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_eq_i8 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY $sil |
| ; CHECK-NEXT: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s8) = COPY $dil |
| %1(s8) = COPY $sil |
| %4(s8) = G_ICMP intpred(eq), %0(s8), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_eq_i16 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_eq_i16 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si |
| ; CHECK-NEXT: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s16) = COPY $di |
| %1(s16) = COPY $si |
| %4(s8) = G_ICMP intpred(eq), %0(s16), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_eq_i64 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $rdi, $rsi |
| |
| ; CHECK-LABEL: name: test_icmp_eq_i64 |
| ; CHECK: liveins: $rdi, $rsi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi |
| ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s64) = COPY $rdi |
| %1(s64) = COPY $rsi |
| %4(s8) = G_ICMP intpred(eq), %0(s64), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_eq_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_eq_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(eq), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_ne_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_ne_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(ne), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_ugt_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_ugt_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(ugt), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_uge_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_uge_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(uge), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_ult_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_ult_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(ult), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_ule_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_ule_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(ule), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_sgt_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_sgt_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(sgt), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_sge_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_sge_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(sge), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_slt_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_slt_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(slt), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: test_icmp_sle_i32 |
| alignment: 16 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: gpr } |
| - { id: 1, class: gpr } |
| - { id: 2, class: _ } |
| - { id: 3, class: gpr } |
| - { id: 4, class: gpr } |
| - { id: 5, class: gpr } |
| - { id: 6, class: gpr } |
| body: | |
| bb.1 (%ir-block.0): |
| liveins: $edi, $esi |
| |
| ; CHECK-LABEL: name: test_icmp_sle_i32 |
| ; CHECK: liveins: $edi, $esi |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi |
| ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags |
| ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags |
| ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] |
| ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags |
| ; CHECK-NEXT: $eax = COPY [[AND32ri]] |
| ; CHECK-NEXT: RET 0, implicit $eax |
| %0(s32) = COPY $edi |
| %1(s32) = COPY $esi |
| %4(s8) = G_ICMP intpred(sle), %0(s32), %1 |
| %5(s32) = G_CONSTANT i32 1 |
| %6(s32) = G_ANYEXT %4(s8) |
| %3(s32) = G_AND %6, %5 |
| $eax = COPY %3(s32) |
| RET 0, implicit $eax |
| |
| ... |