src/llvm-project/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
# RUN:     -start-after finalize-isel -stop-after prologepilog -o - %s | FileCheck %s

--- |
  define void @mask_reg_alloc() {
    ret void
  }
...
---
name: mask_reg_alloc
tracksRegLiveness: true
body:             |
  bb.0 (%ir-block.0):
    liveins: $v0, $v1, $v2, $v3
    ; CHECK-LABEL: name: mask_reg_alloc
    ; CHECK: liveins: $v0, $v1, $v2, $v3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 undef renamable $v8, killed renamable $v2, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: renamable $v0 = COPY killed renamable $v1
    ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 undef renamable $v9, killed renamable $v3, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 undef renamable $v0, killed renamable $v8, killed renamable $v9, 1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:vr = COPY $v0
    %1:vr = COPY $v1
    %2:vr = COPY $v2
    %3:vr = COPY $v3
    %4:vmv0 = COPY %0
    %pt1:vrnov0 = IMPLICIT_DEF
    %5:vrnov0 = PseudoVMERGE_VIM_M1 %pt1, killed %2, 1, %4, 1, 3
    %6:vmv0 = COPY %1
    %pt2:vrnov0 = IMPLICIT_DEF
    %7:vrnov0 = PseudoVMERGE_VIM_M1 %pt2, killed %3, 1, %6, 1, 3
    %pt:vr = IMPLICIT_DEF
    %8:vr = PseudoVADD_VV_M1 %pt, killed %5, killed %7, 1, 3, 0
    $v0 = COPY %8
    PseudoRET implicit $v0
...