src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck -check-prefix=RV32I %s

--- |
  @var = global i32 0

  define ptr @test_global() {
    ret ptr @var
  }

...
---
name:            test_global
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0 (%ir-block.0):
    ; RV32I-LABEL: name: test_global
    ; RV32I: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @var
    ; RV32I-NEXT: $x10 = COPY [[GV]](p0)
    ; RV32I-NEXT: PseudoRET implicit $x10
    %0:_(p0) = G_GLOBAL_VALUE @var
    $x10 = COPY %0(p0)
    PseudoRET implicit $x10

...