src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV64I
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
# RUN:   | FileCheck %s --check-prefixes=RV64ZBB

---
name:            smin_i8
body:             |
  bb.0.entry:
    ; RV64I-LABEL: name: smin_i8
    ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
    ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
    ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
    ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
    ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
    ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
    ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]]
    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
    ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
    ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
    ; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C2]](s64)
    ; RV64I-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
    ; RV64I-NEXT: $x10 = COPY [[ASHR2]](s64)
    ; RV64I-NEXT: PseudoRET implicit $x10
    ;
    ; RV64ZBB-LABEL: name: smin_i8
    ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
    ; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
    ; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
    ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
    ; RV64ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
    ; RV64ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
    ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASHR]], [[ASHR1]]
    ; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
    ; RV64ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMIN]], [[C2]](s64)
    ; RV64ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
    ; RV64ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
    ; RV64ZBB-NEXT: PseudoRET implicit $x10
    %0:_(s64) = COPY $x10
    %1:_(s64) = COPY $x11
    %2:_(s8) = G_TRUNC %0(s64)
    %3:_(s8) = G_TRUNC %1(s64)
    %4:_(s8) = G_SMIN %2, %3
    %5:_(s64) = G_SEXT %4(s8)
    $x10 = COPY %5(s64)
    PseudoRET implicit $x10
...

---
name:            smin_i16
body:             |
  bb.0.entry:
    ; RV64I-LABEL: name: smin_i16
    ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
    ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
    ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
    ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
    ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
    ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
    ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]]
    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
    ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
    ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
    ; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C2]](s64)
    ; RV64I-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
    ; RV64I-NEXT: $x10 = COPY [[ASHR2]](s64)
    ; RV64I-NEXT: PseudoRET implicit $x10
    ;
    ; RV64ZBB-LABEL: name: smin_i16
    ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
    ; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
    ; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
    ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
    ; RV64ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
    ; RV64ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
    ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASHR]], [[ASHR1]]
    ; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
    ; RV64ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMIN]], [[C2]](s64)
    ; RV64ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
    ; RV64ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
    ; RV64ZBB-NEXT: PseudoRET implicit $x10
    %0:_(s64) = COPY $x10
    %1:_(s64) = COPY $x11
    %2:_(s16) = G_TRUNC %0(s64)
    %3:_(s16) = G_TRUNC %1(s64)
    %4:_(s16) = G_SMIN %2, %3
    %5:_(s64) = G_SEXT %4(s16)
    $x10 = COPY %5(s64)
    PseudoRET implicit $x10
...

---
name:            smin_i32
body:             |
  bb.0.entry:
    ; RV64I-LABEL: name: smin_i32
    ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
    ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
    ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
    ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
    ; RV64I-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SELECT]](s32)
    ; RV64I-NEXT: $x10 = COPY [[SEXT]](s64)
    ; RV64I-NEXT: PseudoRET implicit $x10
    ;
    ; RV64ZBB-LABEL: name: smin_i32
    ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
    ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
    ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
    ; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 32
    ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
    ; RV64ZBB-NEXT: PseudoRET implicit $x10
    %0:_(s64) = COPY $x10
    %1:_(s64) = COPY $x11
    %2:_(s32) = G_TRUNC %0(s64)
    %3:_(s32) = G_TRUNC %1(s64)
    %4:_(s32) = G_SMIN %2, %3
    %5:_(s64) = G_SEXT %4(s32)
    $x10 = COPY %5(s64)
    PseudoRET implicit $x10
...

---
name:            smin_i64
body:             |
  bb.0.entry:
    ; RV64I-LABEL: name: smin_i64
    ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
    ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]]
    ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64)
    ; RV64I-NEXT: PseudoRET implicit $x10
    ;
    ; RV64ZBB-LABEL: name: smin_i64
    ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[COPY]], [[COPY1]]
    ; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64)
    ; RV64ZBB-NEXT: PseudoRET implicit $x10
    %0:_(s64) = COPY $x10
    %1:_(s64) = COPY $x11
    %2:_(s64) = G_SMIN %0, %1
    $x10 = COPY %2(s64)
    PseudoRET implicit $x10
...