| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \ |
| # RUN: | FileCheck %s --check-prefix=RV32I |
| # RUN: llc -mattr=+m -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ |
| # RUN: | FileCheck %s --check-prefix=RV32ZBB |
| |
| --- |
| name: ctlz_i8 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; RV32I-LABEL: name: ctlz_i8 |
| ; RV32I: liveins: $x10 |
| ; RV32I-NEXT: {{ $}} |
| ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] |
| ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) |
| ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] |
| ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]] |
| ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) |
| ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] |
| ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]] |
| ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C4]](s32) |
| ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] |
| ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C7]] |
| ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C6]](s32) |
| ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 |
| ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C8]] |
| ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR2]], [[AND4]] |
| ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C10]] |
| ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C9]](s32) |
| ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 |
| ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C11]] |
| ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C11]] |
| ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[AND7]] |
| ; RV32I-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C12]](s32) |
| ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR5]], [[ADD]] |
| ; RV32I-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 |
| ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C13]] |
| ; RV32I-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND8]], [[C14]] |
| ; RV32I-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C15]](s32) |
| ; RV32I-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C16]], [[LSHR6]] |
| ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) |
| ; RV32I-NEXT: PseudoRET implicit $x10 |
| ; |
| ; RV32ZBB-LABEL: name: ctlz_i8 |
| ; RV32ZBB: liveins: $x10 |
| ; RV32ZBB-NEXT: {{ $}} |
| ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) |
| ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]] |
| ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) |
| ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) |
| ; RV32ZBB-NEXT: PseudoRET implicit $x10 |
| %1:_(s32) = COPY $x10 |
| %0:_(s8) = G_TRUNC %1(s32) |
| %2:_(s8) = G_CTLZ %0(s8) |
| %3:_(s32) = G_ANYEXT %2(s8) |
| $x10 = COPY %3(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: ctlz_i16 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; RV32I-LABEL: name: ctlz_i16 |
| ; RV32I: liveins: $x10 |
| ; RV32I-NEXT: {{ $}} |
| ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] |
| ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) |
| ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] |
| ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]] |
| ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) |
| ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] |
| ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]] |
| ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C4]](s32) |
| ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] |
| ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C7]] |
| ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C6]](s32) |
| ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] |
| ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C9]] |
| ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C8]](s32) |
| ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 |
| ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C10]] |
| ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR3]], [[AND5]] |
| ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C12]] |
| ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C11]](s32) |
| ; RV32I-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 |
| ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C13]] |
| ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C13]] |
| ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[AND8]] |
| ; RV32I-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C14]](s32) |
| ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD]] |
| ; RV32I-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 |
| ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C15]] |
| ; RV32I-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 257 |
| ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C16]] |
| ; RV32I-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C18]] |
| ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C17]](s32) |
| ; RV32I-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C19]], [[LSHR7]] |
| ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) |
| ; RV32I-NEXT: PseudoRET implicit $x10 |
| ; |
| ; RV32ZBB-LABEL: name: ctlz_i16 |
| ; RV32ZBB: liveins: $x10 |
| ; RV32ZBB-NEXT: {{ $}} |
| ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) |
| ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]] |
| ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) |
| ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) |
| ; RV32ZBB-NEXT: PseudoRET implicit $x10 |
| %1:_(s32) = COPY $x10 |
| %0:_(s16) = G_TRUNC %1(s32) |
| %2:_(s16) = G_CTLZ %0(s16) |
| %3:_(s32) = G_ANYEXT %2(s16) |
| $x10 = COPY %3(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: ctlz_i32 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; RV32I-LABEL: name: ctlz_i32 |
| ; RV32I: liveins: $x10 |
| ; RV32I-NEXT: {{ $}} |
| ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) |
| ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] |
| ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32) |
| ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] |
| ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C2]](s32) |
| ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] |
| ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C3]](s32) |
| ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] |
| ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C4]](s32) |
| ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] |
| ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C5]](s32) |
| ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 |
| ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C6]] |
| ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] |
| ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C7]](s32) |
| ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 |
| ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C8]] |
| ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C8]] |
| ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] |
| ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C9]](s32) |
| ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] |
| ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 |
| ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C10]] |
| ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 |
| ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C11]] |
| ; RV32I-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C12]](s32) |
| ; RV32I-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[LSHR8]] |
| ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) |
| ; RV32I-NEXT: PseudoRET implicit $x10 |
| ; |
| ; RV32ZBB-LABEL: name: ctlz_i32 |
| ; RV32ZBB: liveins: $x10 |
| ; RV32ZBB-NEXT: {{ $}} |
| ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) |
| ; RV32ZBB-NEXT: $x10 = COPY [[CTLZ]](s32) |
| ; RV32ZBB-NEXT: PseudoRET implicit $x10 |
| %0:_(s32) = COPY $x10 |
| %1:_(s32) = G_CTLZ %0(s32) |
| $x10 = COPY %1(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: ctlz_i64 |
| body: | |
| bb.1: |
| liveins: $x10, $x11 |
| |
| ; RV32I-LABEL: name: ctlz_i64 |
| ; RV32I: liveins: $x10, $x11 |
| ; RV32I-NEXT: {{ $}} |
| ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 |
| ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] |
| ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32) |
| ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] |
| ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32) |
| ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] |
| ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32) |
| ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] |
| ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C4]](s32) |
| ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] |
| ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C5]](s32) |
| ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] |
| ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C6]](s32) |
| ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 |
| ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C7]] |
| ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] |
| ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C8]](s32) |
| ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 |
| ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C9]] |
| ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C9]] |
| ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] |
| ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C10]](s32) |
| ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] |
| ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 |
| ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C11]] |
| ; RV32I-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 |
| ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C12]] |
| ; RV32I-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C13]](s32) |
| ; RV32I-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C14]], [[LSHR8]] |
| ; RV32I-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SUB1]], [[C15]] |
| ; RV32I-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C16]](s32) |
| ; RV32I-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[LSHR9]] |
| ; RV32I-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[OR5]], [[C17]](s32) |
| ; RV32I-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[LSHR10]] |
| ; RV32I-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[OR6]], [[C18]](s32) |
| ; RV32I-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[LSHR11]] |
| ; RV32I-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[OR7]], [[C19]](s32) |
| ; RV32I-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[LSHR12]] |
| ; RV32I-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32I-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[OR8]], [[C20]](s32) |
| ; RV32I-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[LSHR13]] |
| ; RV32I-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[OR9]], [[C21]](s32) |
| ; RV32I-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 |
| ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C22]] |
| ; RV32I-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[OR9]], [[AND4]] |
| ; RV32I-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[SUB2]], [[C23]](s32) |
| ; RV32I-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 |
| ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C24]] |
| ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C24]] |
| ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]] |
| ; RV32I-NEXT: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[ADD3]], [[C25]](s32) |
| ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR16]], [[ADD3]] |
| ; RV32I-NEXT: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 |
| ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD4]], [[C26]] |
| ; RV32I-NEXT: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 |
| ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C27]] |
| ; RV32I-NEXT: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; RV32I-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C28]](s32) |
| ; RV32I-NEXT: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32I-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C29]], [[LSHR17]] |
| ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD2]], [[SUB3]] |
| ; RV32I-NEXT: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) |
| ; RV32I-NEXT: $x11 = COPY [[C30]](s32) |
| ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 |
| ; |
| ; RV32ZBB-LABEL: name: ctlz_i64 |
| ; RV32ZBB: liveins: $x10, $x11 |
| ; RV32ZBB-NEXT: {{ $}} |
| ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 |
| ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] |
| ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) |
| ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]] |
| ; RV32ZBB-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32) |
| ; RV32ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTLZ1]] |
| ; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32ZBB-NEXT: $x10 = COPY [[SELECT]](s32) |
| ; RV32ZBB-NEXT: $x11 = COPY [[C2]](s32) |
| ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11 |
| %1:_(s32) = COPY $x10 |
| %2:_(s32) = COPY $x11 |
| %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) |
| %3:_(s64) = G_CTLZ %0(s64) |
| %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) |
| $x10 = COPY %4(s32) |
| $x11 = COPY %5(s32) |
| PseudoRET implicit $x10, implicit $x11 |
| |
| ... |
| --- |
| name: ctlz_zero_undef_i8 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; RV32I-LABEL: name: ctlz_zero_undef_i8 |
| ; RV32I: liveins: $x10 |
| ; RV32I-NEXT: {{ $}} |
| ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] |
| ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) |
| ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] |
| ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]] |
| ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) |
| ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] |
| ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]] |
| ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C4]](s32) |
| ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] |
| ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C7]] |
| ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C6]](s32) |
| ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 |
| ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C8]] |
| ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR2]], [[AND4]] |
| ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C10]] |
| ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C9]](s32) |
| ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 |
| ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C11]] |
| ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C11]] |
| ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[AND7]] |
| ; RV32I-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C12]](s32) |
| ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR5]], [[ADD]] |
| ; RV32I-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 |
| ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C13]] |
| ; RV32I-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND8]], [[C14]] |
| ; RV32I-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C15]](s32) |
| ; RV32I-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C16]], [[LSHR6]] |
| ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) |
| ; RV32I-NEXT: PseudoRET implicit $x10 |
| ; |
| ; RV32ZBB-LABEL: name: ctlz_zero_undef_i8 |
| ; RV32ZBB: liveins: $x10 |
| ; RV32ZBB-NEXT: {{ $}} |
| ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) |
| ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]] |
| ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) |
| ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) |
| ; RV32ZBB-NEXT: PseudoRET implicit $x10 |
| %1:_(s32) = COPY $x10 |
| %0:_(s8) = G_TRUNC %1(s32) |
| %2:_(s8) = G_CTLZ_ZERO_UNDEF %0(s8) |
| %3:_(s32) = G_ANYEXT %2(s8) |
| $x10 = COPY %3(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: ctlz_zero_undef_i16 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; RV32I-LABEL: name: ctlz_zero_undef_i16 |
| ; RV32I: liveins: $x10 |
| ; RV32I-NEXT: {{ $}} |
| ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] |
| ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) |
| ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] |
| ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]] |
| ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) |
| ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] |
| ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]] |
| ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C4]](s32) |
| ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] |
| ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C7]] |
| ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C6]](s32) |
| ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] |
| ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C9]] |
| ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C8]](s32) |
| ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 |
| ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C10]] |
| ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR3]], [[AND5]] |
| ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C12]] |
| ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C11]](s32) |
| ; RV32I-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 |
| ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C13]] |
| ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C13]] |
| ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[AND8]] |
| ; RV32I-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C14]](s32) |
| ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD]] |
| ; RV32I-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 |
| ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C15]] |
| ; RV32I-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 257 |
| ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C16]] |
| ; RV32I-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C18]] |
| ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C17]](s32) |
| ; RV32I-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C19]], [[LSHR7]] |
| ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) |
| ; RV32I-NEXT: PseudoRET implicit $x10 |
| ; |
| ; RV32ZBB-LABEL: name: ctlz_zero_undef_i16 |
| ; RV32ZBB: liveins: $x10 |
| ; RV32ZBB-NEXT: {{ $}} |
| ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 |
| ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) |
| ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]] |
| ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) |
| ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) |
| ; RV32ZBB-NEXT: PseudoRET implicit $x10 |
| %1:_(s32) = COPY $x10 |
| %0:_(s16) = G_TRUNC %1(s32) |
| %2:_(s16) = G_CTLZ_ZERO_UNDEF %0(s16) |
| %3:_(s32) = G_ANYEXT %2(s16) |
| $x10 = COPY %3(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: ctlz_zero_undef_i32 |
| body: | |
| bb.1: |
| liveins: $x10 |
| |
| ; RV32I-LABEL: name: ctlz_zero_undef_i32 |
| ; RV32I: liveins: $x10 |
| ; RV32I-NEXT: {{ $}} |
| ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) |
| ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] |
| ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32) |
| ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] |
| ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C2]](s32) |
| ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] |
| ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C3]](s32) |
| ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] |
| ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C4]](s32) |
| ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] |
| ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C5]](s32) |
| ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 |
| ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C6]] |
| ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] |
| ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C7]](s32) |
| ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 |
| ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C8]] |
| ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C8]] |
| ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] |
| ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C9]](s32) |
| ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] |
| ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 |
| ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C10]] |
| ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 |
| ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C11]] |
| ; RV32I-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C12]](s32) |
| ; RV32I-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[LSHR8]] |
| ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) |
| ; RV32I-NEXT: PseudoRET implicit $x10 |
| ; |
| ; RV32ZBB-LABEL: name: ctlz_zero_undef_i32 |
| ; RV32ZBB: liveins: $x10 |
| ; RV32ZBB-NEXT: {{ $}} |
| ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) |
| ; RV32ZBB-NEXT: $x10 = COPY [[CTLZ]](s32) |
| ; RV32ZBB-NEXT: PseudoRET implicit $x10 |
| %0:_(s32) = COPY $x10 |
| %1:_(s32) = G_CTLZ_ZERO_UNDEF %0(s32) |
| $x10 = COPY %1(s32) |
| PseudoRET implicit $x10 |
| |
| ... |
| --- |
| name: ctlz_zero_undef_i64 |
| body: | |
| bb.1: |
| liveins: $x10, $x11 |
| |
| ; RV32I-LABEL: name: ctlz_zero_undef_i64 |
| ; RV32I: liveins: $x10, $x11 |
| ; RV32I-NEXT: {{ $}} |
| ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 |
| ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] |
| ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32) |
| ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] |
| ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32) |
| ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] |
| ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32) |
| ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] |
| ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C4]](s32) |
| ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] |
| ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C5]](s32) |
| ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] |
| ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C6]](s32) |
| ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 |
| ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C7]] |
| ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] |
| ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C8]](s32) |
| ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 |
| ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C9]] |
| ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C9]] |
| ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] |
| ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C10]](s32) |
| ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] |
| ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 |
| ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C11]] |
| ; RV32I-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 |
| ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C12]] |
| ; RV32I-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C13]](s32) |
| ; RV32I-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C14]], [[LSHR8]] |
| ; RV32I-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SUB1]], [[C15]] |
| ; RV32I-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C16]](s32) |
| ; RV32I-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[LSHR9]] |
| ; RV32I-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[OR5]], [[C17]](s32) |
| ; RV32I-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[LSHR10]] |
| ; RV32I-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[OR6]], [[C18]](s32) |
| ; RV32I-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[LSHR11]] |
| ; RV32I-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 |
| ; RV32I-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[OR7]], [[C19]](s32) |
| ; RV32I-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[LSHR12]] |
| ; RV32I-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 |
| ; RV32I-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[OR8]], [[C20]](s32) |
| ; RV32I-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[LSHR13]] |
| ; RV32I-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; RV32I-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[OR9]], [[C21]](s32) |
| ; RV32I-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 |
| ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C22]] |
| ; RV32I-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[OR9]], [[AND4]] |
| ; RV32I-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; RV32I-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[SUB2]], [[C23]](s32) |
| ; RV32I-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 |
| ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C24]] |
| ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C24]] |
| ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]] |
| ; RV32I-NEXT: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; RV32I-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[ADD3]], [[C25]](s32) |
| ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR16]], [[ADD3]] |
| ; RV32I-NEXT: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 |
| ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD4]], [[C26]] |
| ; RV32I-NEXT: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 |
| ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C27]] |
| ; RV32I-NEXT: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; RV32I-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C28]](s32) |
| ; RV32I-NEXT: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32I-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C29]], [[LSHR17]] |
| ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD2]], [[SUB3]] |
| ; RV32I-NEXT: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) |
| ; RV32I-NEXT: $x11 = COPY [[C30]](s32) |
| ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 |
| ; |
| ; RV32ZBB-LABEL: name: ctlz_zero_undef_i64 |
| ; RV32ZBB: liveins: $x10, $x11 |
| ; RV32ZBB-NEXT: {{ $}} |
| ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 |
| ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] |
| ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) |
| ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 |
| ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]] |
| ; RV32ZBB-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32) |
| ; RV32ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTLZ1]] |
| ; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32ZBB-NEXT: $x10 = COPY [[SELECT]](s32) |
| ; RV32ZBB-NEXT: $x11 = COPY [[C2]](s32) |
| ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11 |
| %1:_(s32) = COPY $x10 |
| %2:_(s32) = COPY $x11 |
| %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) |
| %3:_(s64) = G_CTLZ_ZERO_UNDEF %0(s64) |
| %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) |
| $x10 = COPY %4(s32) |
| $x11 = COPY %5(s32) |
| PseudoRET implicit $x10, implicit $x11 |
| |
| ... |
