src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
#
--- |
  define void @store_i8(i8 %val, ptr %addr) { ret void }
  define void @store_i16(i16 %val, ptr %addr) { ret void }
  define void @store_i32(i32 %val, ptr %addr) { ret void }
  define void @store_p0(ptr %val, ptr %addr) { ret void }
  define void @store_fi_i32(ptr %val) {
    %ptr0 = alloca i32
    ret void
  }
  define void @store_fi_gep_i32(ptr %val) {
    %ptr0 = alloca [2 x i32]
    ret void
  }
  define void @store_gep_i32(i32 %val, ptr %addr) { ret void }
...
---
name:            store_i8
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10, $x11, $x11

    ; CHECK-LABEL: name: store_i8
    ; CHECK: liveins: $x10, $x11, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: SB [[COPY]], [[COPY1]], 0 :: (store (s8))
    ; CHECK-NEXT: PseudoRET
    %0:gprb(s32) = COPY $x10
    %1:gprb(p0) = COPY $x11
    G_STORE %0(s32), %1(p0) :: (store (s8))
    PseudoRET

...
---
name:            store_i16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: store_i16
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: SH [[COPY]], [[COPY1]], 0 :: (store (s16))
    ; CHECK-NEXT: PseudoRET
    %0:gprb(s32) = COPY $x10
    %1:gprb(p0) = COPY $x11
    G_STORE %0(s32), %1(p0) :: (store (s16))
    PseudoRET

...
---
name:            store_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: store_i32
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: SW [[COPY]], [[COPY1]], 0 :: (store (s32))
    ; CHECK-NEXT: PseudoRET
    %0:gprb(s32) = COPY $x10
    %1:gprb(p0) = COPY $x11
    G_STORE %0(s32), %1(p0) :: (store (s32))
    PseudoRET

...
---
name:            store_p0
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: store_p0
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: SW [[COPY]], [[COPY1]], 0 :: (store (p0))
    ; CHECK-NEXT: PseudoRET
    %0:gprb(p0) = COPY $x10
    %1:gprb(p0) = COPY $x11
    G_STORE %0(p0), %1(p0) :: (store (p0))
    PseudoRET

...
---
name:            store_fi_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

stack:
  - { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }

body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: store_fi_i32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: SW [[COPY]], %stack.0.ptr0, 0 :: (store (s32))
    ; CHECK-NEXT: PseudoRET
    %0:gprb(s32) = COPY $x10
    %1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
    G_STORE %0(s32), %1(p0) :: (store (s32))
    PseudoRET

...
---
name:            store_fi_gep_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

stack:
  - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 4 }

body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: store_fi_gep_i32
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: SW [[COPY]], %stack.0.ptr0, 4 :: (store (s32))
    ; CHECK-NEXT: PseudoRET
    %0:gprb(s32) = COPY $x10
    %1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
    %2:gprb(s32) = G_CONSTANT i32 4
    %3:gprb(p0) = G_PTR_ADD %1(p0), %2(s32)
    G_STORE %0(s32), %3(p0) :: (store (s32))
    PseudoRET

...
---
name:            store_gep_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: store_gep_i32
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: SW [[COPY]], [[COPY1]], 4 :: (store (s32))
    ; CHECK-NEXT: PseudoRET
    %0:gprb(s32) = COPY $x10
    %1:gprb(p0) = COPY $x11
    %2:gprb(s32) = G_CONSTANT i32 4
    %3:gprb(p0) = G_PTR_ADD %1(p0), %2(s32)
    G_STORE %0(s32), %3(p0) :: (store (s32))
    PseudoRET

...