src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
---
name:            add_i64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: add_i64
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $x10 = COPY [[ADD]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s64) = COPY $x11
    %2:gprb(p0) = G_PTR_ADD %0, %1
    $x10 = COPY %2(p0)
    PseudoRET implicit $x10

...
---
name:            addi_i64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: addi_i64
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 20
    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s64) = G_CONSTANT i64 20
    %2:gprb(p0) = G_PTR_ADD %0, %1
    $x10 = COPY %2(p0)
    PseudoRET implicit $x10

...