src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/merge-unmerge-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name:            merge_i64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10
    ; CHECK-LABEL: name: merge_i64
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[COPY]]
    ; CHECK-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:gprb(s32) = COPY $x10
    %1:fprb(s64) = G_MERGE_VALUES %0(s32), %0(s32)
    $f10_d = COPY %1(s64)
    PseudoRET implicit $f10_d
...
---
name:            unmerge_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $f10_d
    ; CHECK-LABEL: name: unmerge_i32
    ; CHECK: liveins: $f10_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[SplitF64Pseudo:%[0-9]+]]:gpr, [[SplitF64Pseudo1:%[0-9]+]]:gpr = SplitF64Pseudo [[COPY]]
    ; CHECK-NEXT: $x10 = COPY [[SplitF64Pseudo]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s64) = COPY $f10_d
    %1:gprb(s32), %2:gprb(s32) = G_UNMERGE_VALUES %0(s64)
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10
...