src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name:            fadd_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f

    ; CHECK-LABEL: name: fadd_f32
    ; CHECK: liveins: $f10_f, $f11_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_f = COPY [[FADD_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = COPY $f11_f
    %2:fprb(s32) = G_FADD %0, %1
    $f10_f = COPY %2(s32)
    PseudoRET implicit $f10_f

...
---
name:            fsub_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f

    ; CHECK-LABEL: name: fsub_f32
    ; CHECK: liveins: $f10_f, $f11_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[FSUB_S:%[0-9]+]]:fpr32 = nofpexcept FSUB_S [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_f = COPY [[FSUB_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = COPY $f11_f
    %2:fprb(s32) = G_FSUB %0, %1
    $f10_f = COPY %2(s32)
    PseudoRET implicit $f10_f

...
---
name:            fmul_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f

    ; CHECK-LABEL: name: fmul_f32
    ; CHECK: liveins: $f10_f, $f11_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[FMUL_S:%[0-9]+]]:fpr32 = nofpexcept FMUL_S [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_f = COPY [[FMUL_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = COPY $f11_f
    %2:fprb(s32) = G_FMUL %0, %1
    $f10_f = COPY %2(s32)
    PseudoRET implicit $f10_f

...
---
name:            fdiv_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f

    ; CHECK-LABEL: name: fdiv_f32
    ; CHECK: liveins: $f10_f, $f11_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[FDIV_S:%[0-9]+]]:fpr32 = nofpexcept FDIV_S [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_f = COPY [[FDIV_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = COPY $f11_f
    %2:fprb(s32) = G_FDIV %0, %1
    $f10_f = COPY %2(s32)
    PseudoRET implicit $f10_f

...
---
name:            fma_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f, $f12_f

    ; CHECK-LABEL: name: fma_f32
    ; CHECK: liveins: $f10_f, $f11_f, $f12_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f12_f
    ; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nofpexcept FMADD_S [[COPY]], [[COPY1]], [[COPY2]], 7
    ; CHECK-NEXT: $f10_f = COPY [[FMADD_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = COPY $f11_f
    %2:fprb(s32) = COPY $f12_f
    %3:fprb(s32) = G_FMA %0, %1, %2
    $f10_f = COPY %3(s32)
    PseudoRET implicit $f10_f

...
---
name:            fneg_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f, $f12_f

    ; CHECK-LABEL: name: fneg_f32
    ; CHECK: liveins: $f10_f, $f11_f, $f12_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[FSGNJN_S:%[0-9]+]]:fpr32 = FSGNJN_S [[COPY]], [[COPY]]
    ; CHECK-NEXT: $f10_f = COPY [[FSGNJN_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = G_FNEG %0
    $f10_f = COPY %1(s32)
    PseudoRET implicit $f10_f

...
---
name:            fabs_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f, $f12_f

    ; CHECK-LABEL: name: fabs_f32
    ; CHECK: liveins: $f10_f, $f11_f, $f12_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[FSGNJX_S:%[0-9]+]]:fpr32 = FSGNJX_S [[COPY]], [[COPY]]
    ; CHECK-NEXT: $f10_f = COPY [[FSGNJX_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = G_FABS %0
    $f10_f = COPY %1(s32)
    PseudoRET implicit $f10_f

...
---
name:            fsqrt_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f, $f12_f

    ; CHECK-LABEL: name: fsqrt_f32
    ; CHECK: liveins: $f10_f, $f11_f, $f12_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[FSQRT_S:%[0-9]+]]:fpr32 = nofpexcept FSQRT_S [[COPY]], 7
    ; CHECK-NEXT: $f10_f = COPY [[FSQRT_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = G_FSQRT %0
    $f10_f = COPY %1(s32)
    PseudoRET implicit $f10_f

...
---
name:            fadd_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d, $f11_d

    ; CHECK-LABEL: name: fadd_f64
    ; CHECK: liveins: $f10_d, $f11_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
    ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_d = COPY [[FADD_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = COPY $f11_d
    %2:fprb(s64) = G_FADD %0, %1
    $f10_d = COPY %2(s64)
    PseudoRET implicit $f10_d

...
---
name:            fmaxnum_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f

    ; CHECK-LABEL: name: fmaxnum_f32
    ; CHECK: liveins: $f10_f, $f11_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[FMAX_S:%[0-9]+]]:fpr32 = nofpexcept FMAX_S [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_f = COPY [[FMAX_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = COPY $f11_f
    %2:fprb(s32) = G_FMAXNUM %0, %1
    $f10_f = COPY %2(s32)
    PseudoRET implicit $f10_f

...
---
name:            fminnum_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f

    ; CHECK-LABEL: name: fminnum_f32
    ; CHECK: liveins: $f10_f, $f11_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[FMIN_S:%[0-9]+]]:fpr32 = nofpexcept FMIN_S [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_f = COPY [[FMIN_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = COPY $f11_f
    %2:fprb(s32) = G_FMINNUM %0, %1
    $f10_f = COPY %2(s32)
    PseudoRET implicit $f10_f

...
---
name:            fcopysign_f32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_f, $f11_f

    ; CHECK-LABEL: name: fcopysign_f32
    ; CHECK: liveins: $f10_f, $f11_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]]
    ; CHECK-NEXT: PseudoRET implicit $f10_f
    %0:fprb(s32) = COPY $f10_f
    %1:fprb(s32) = COPY $f11_f
    %2:fprb(s32) = G_FCOPYSIGN %0, %1
    $f10_f = COPY %2(s32)
    PseudoRET implicit $f10_f

...
---
name:            fsub_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d, $f11_d

    ; CHECK-LABEL: name: fsub_f64
    ; CHECK: liveins: $f10_d, $f11_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
    ; CHECK-NEXT: [[FSUB_D:%[0-9]+]]:fpr64 = nofpexcept FSUB_D [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_d = COPY [[FSUB_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = COPY $f11_d
    %2:fprb(s64) = G_FSUB %0, %1
    $f10_d = COPY %2(s64)
    PseudoRET implicit $f10_d

...
---
name:            fmul_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d, $f11_d

    ; CHECK-LABEL: name: fmul_f64
    ; CHECK: liveins: $f10_d, $f11_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
    ; CHECK-NEXT: [[FMUL_D:%[0-9]+]]:fpr64 = nofpexcept FMUL_D [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_d = COPY [[FMUL_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = COPY $f11_d
    %2:fprb(s64) = G_FMUL %0, %1
    $f10_d = COPY %2(s64)
    PseudoRET implicit $f10_d

...
---
name:            fdiv_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d, $f11_d

    ; CHECK-LABEL: name: fdiv_f64
    ; CHECK: liveins: $f10_d, $f11_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
    ; CHECK-NEXT: [[FDIV_D:%[0-9]+]]:fpr64 = nofpexcept FDIV_D [[COPY]], [[COPY1]], 7
    ; CHECK-NEXT: $f10_d = COPY [[FDIV_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = COPY $f11_d
    %2:fprb(s64) = G_FDIV %0, %1
    $f10_d = COPY %2(s64)
    PseudoRET implicit $f10_d

...
---
name:            fma_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d, $f11_d, $f12_d

    ; CHECK-LABEL: name: fma_f64
    ; CHECK: liveins: $f10_d, $f11_d, $f12_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f12_d
    ; CHECK-NEXT: [[FMADD_D:%[0-9]+]]:fpr64 = nofpexcept FMADD_D [[COPY]], [[COPY1]], [[COPY2]], 7
    ; CHECK-NEXT: $f10_d = COPY [[FMADD_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = COPY $f11_d
    %2:fprb(s64) = COPY $f12_d
    %3:fprb(s64) = G_FMA %0, %1, %2
    $f10_d = COPY %3(s64)
    PseudoRET implicit $f10_d

...
---
name:            fneg_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d

    ; CHECK-LABEL: name: fneg_f64
    ; CHECK: liveins: $f10_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[FSGNJN_D:%[0-9]+]]:fpr64 = FSGNJN_D [[COPY]], [[COPY]]
    ; CHECK-NEXT: $f10_d = COPY [[FSGNJN_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = G_FNEG %0
    $f10_d = COPY %1(s64)
    PseudoRET implicit $f10_d

...
---
name:            fabs_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d

    ; CHECK-LABEL: name: fabs_f64
    ; CHECK: liveins: $f10_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[FSGNJX_D:%[0-9]+]]:fpr64 = FSGNJX_D [[COPY]], [[COPY]]
    ; CHECK-NEXT: $f10_d = COPY [[FSGNJX_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = G_FABS %0
    $f10_d = COPY %1(s64)
    PseudoRET implicit $f10_d

...
---
name:            fsqrt_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d

    ; CHECK-LABEL: name: fsqrt_f64
    ; CHECK: liveins: $f10_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[FSQRT_D:%[0-9]+]]:fpr64 = nofpexcept FSQRT_D [[COPY]], 7
    ; CHECK-NEXT: $f10_d = COPY [[FSQRT_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = G_FSQRT %0
    $f10_d = COPY %1(s64)
    PseudoRET implicit $f10_d

...
---
name:            fmaxnum_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d, $f11_d

    ; CHECK-LABEL: name: fmaxnum_f64
    ; CHECK: liveins: $f10_d, $f11_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
    ; CHECK-NEXT: [[FMAX_D:%[0-9]+]]:fpr64 = nofpexcept FMAX_D [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_d = COPY [[FMAX_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = COPY $f11_d
    %2:fprb(s64) = G_FMAXNUM %0, %1
    $f10_d = COPY %2(s64)
    PseudoRET implicit $f10_d

...
---
name:            fminnum_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d, $f11_d

    ; CHECK-LABEL: name: fminnum_f64
    ; CHECK: liveins: $f10_d, $f11_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
    ; CHECK-NEXT: [[FMIN_D:%[0-9]+]]:fpr64 = nofpexcept FMIN_D [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_d = COPY [[FMIN_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = COPY $f11_d
    %2:fprb(s64) = G_FMINNUM %0, %1
    $f10_d = COPY %2(s64)
    PseudoRET implicit $f10_d

...
---
name:            fcopysign_f64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $f10_d, $f11_d

    ; CHECK-LABEL: name: fcopysign_f64
    ; CHECK: liveins: $f10_d, $f11_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
    ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]]
    ; CHECK-NEXT: PseudoRET implicit $f10_d
    %0:fprb(s64) = COPY $f10_d
    %1:fprb(s64) = COPY $f11_d
    %2:fprb(s64) = G_FCOPYSIGN %0, %1
    $f10_d = COPY %2(s64)
    PseudoRET implicit $f10_d

...