src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
---
name:            const_i32_INT_MIN
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: const_i32_INT_MIN
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
    ; CHECK-NEXT: $x10 = COPY [[LUI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = G_CONSTANT i32 -2147483648
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            const_i32_neg_2147483000
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: const_i32_neg_2147483000
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 648
    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = G_CONSTANT i32 -2147483000
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            const_i32_INT_MAX
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: const_i32_INT_MAX
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -1
    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = G_CONSTANT i32 2147483647
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            const_i32_2147483000
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: const_i32_2147483000
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -648
    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = G_CONSTANT i32 2147483000
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            const_i32_256
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: const_i32_256
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 256
    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = G_CONSTANT i32 256
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...
---
name:            const_i32_0
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:            |
  bb.0:
    liveins: $x10

    ; CHECK-LABEL: name: const_i32_0
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
    ; CHECK-NEXT: $x10 = COPY [[COPY]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprb(s32) = G_CONSTANT i32 0
    $x10 = COPY %0(s32)
    PseudoRET implicit $x10

...