src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
# RUN:   -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s

---
name:            indirectbr
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; RV32I-LABEL: name: indirectbr
  ; RV32I: bb.0:
  ; RV32I-NEXT:   successors: %bb.1, %bb.2
  ; RV32I-NEXT:   liveins: $x10
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gprjalr = COPY $x10
  ; RV32I-NEXT:   [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x0
  ; RV32I-NEXT:   PseudoBRIND [[COPY]], 0
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.1:
  ; RV32I-NEXT:   $x10 = COPY [[COPY1]]
  ; RV32I-NEXT:   PseudoRET implicit $x10
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.2:
  ; RV32I-NEXT:   $x10 = COPY [[ADDI]]
  ; RV32I-NEXT:   PseudoRET implicit $x10
  bb.1:
    successors: %bb.2, %bb.3
    liveins: $x10

    %0:gprb(p0) = COPY $x10
    %1:gprb(s32) = G_CONSTANT i32 1
    %2:gprb(s32) = G_CONSTANT i32 0
    G_BRINDIRECT %0(p0)

  bb.2:
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

  bb.3:
    $x10 = COPY %1(s32)
    PseudoRET implicit $x10

...