src/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir

# RUN: not llc -mtriple=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
---
name: empty_scratch_rsrc_reg
machineFunctionInfo:
  scratchRSrcReg:  ''
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
body:             |
  bb.0:

    S_ENDPGM
...