src/llvm-project/llvm/test/CodeGen/AMDGPU/split-mbb-lis-subrange.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass liveintervals,phi-node-elimination -o - %s | FileCheck -check-prefixes=GCN %s

# This checks liveintervals pass verification and phi-node-elimination correctly preserves them.

---
name: split_critical_edge_subranges
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: split_critical_edge_subranges
  ; GCN: bb.0:
  ; GCN-NEXT:   successors: %bb.5(0x40000000), %bb.1(0x40000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   %coord:vreg_64 = IMPLICIT_DEF
  ; GCN-NEXT:   %desc:sgpr_256 = IMPLICIT_DEF
  ; GCN-NEXT:   %c0:sreg_32 = IMPLICIT_DEF
  ; GCN-NEXT:   %c1:sreg_32 = IMPLICIT_DEF
  ; GCN-NEXT:   %const:vgpr_32 = IMPLICIT_DEF
  ; GCN-NEXT:   %load:vreg_64 = IMAGE_LOAD_V2_V2_gfx11 %coord, %desc, 3, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s64), align 16, addrspace 4)
  ; GCN-NEXT:   %s0a:vgpr_32 = COPY %load.sub0
  ; GCN-NEXT:   %s0b:vgpr_32 = COPY %load.sub1
  ; GCN-NEXT:   S_CMP_EQ_U32 %c0, %c1, implicit-def $scc
  ; GCN-NEXT:   S_CBRANCH_SCC0 %bb.1, implicit $scc
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.5:
  ; GCN-NEXT:   successors: %bb.3(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY %s0a
  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY %s0b
  ; GCN-NEXT:   S_BRANCH %bb.3
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.1:
  ; GCN-NEXT:   successors: %bb.3(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   %s0c:vgpr_32 = V_ADD_F32_e64 0, %s0a, 0, %const, 0, 0, implicit $mode, implicit $exec
  ; GCN-NEXT:   %s0d:vgpr_32 = V_ADD_F32_e64 0, %s0b, 0, %const, 0, 0, implicit $mode, implicit $exec
  ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY %s0c
  ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY %s0d
  ; GCN-NEXT:   S_BRANCH %bb.3
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.2:
  ; GCN-NEXT:   S_NOP 0
  ; GCN-NEXT:   S_ENDPGM 0
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.3:
  ; GCN-NEXT:   successors: %bb.4(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   %phi1:vgpr_32 = COPY [[COPY3]]
  ; GCN-NEXT:   %phi0:vgpr_32 = COPY [[COPY2]]
  ; GCN-NEXT:   S_BRANCH %bb.4
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.4:
  ; GCN-NEXT:   S_ENDPGM 0, implicit %phi0, implicit %phi1
  bb.0:
    %coord:vreg_64 = IMPLICIT_DEF
    %desc:sgpr_256 = IMPLICIT_DEF
    %c0:sreg_32 = IMPLICIT_DEF
    %c1:sreg_32 = IMPLICIT_DEF
    %const:vgpr_32 = IMPLICIT_DEF
    %load:vreg_64 = IMAGE_LOAD_V2_V2_gfx11 %coord:vreg_64, killed %desc:sgpr_256, 3, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s64), align 16, addrspace 4)
    %s0a:vgpr_32 = COPY %load.sub0:vreg_64
    %s0b:vgpr_32 = COPY %load.sub1:vreg_64
    S_CMP_EQ_U32 killed %c0:sreg_32, killed %c1:sreg_32, implicit-def $scc
    S_CBRANCH_SCC1 %bb.3, implicit $scc
    S_BRANCH %bb.1

  bb.1:
    %s0c:vgpr_32 = V_ADD_F32_e64 0, %s0a:vgpr_32, 0, %const:vgpr_32, 0, 0, implicit $mode, implicit $exec
    %s0d:vgpr_32 = V_ADD_F32_e64 0, %s0b:vgpr_32, 0, %const:vgpr_32, 0, 0, implicit $mode, implicit $exec
    S_BRANCH %bb.3

  bb.2:
    S_NOP 0
    S_ENDPGM 0

  bb.3:
    %phi0:vgpr_32 = PHI %s0a:vgpr_32, %bb.0, %s0c:vgpr_32, %bb.1
    %phi1:vgpr_32 = PHI %s0b:vgpr_32, %bb.0, %s0d:vgpr_32, %bb.1
    S_BRANCH %bb.4

  bb.4:
    S_ENDPGM 0, implicit %phi0:vgpr_32, implicit %phi1:vgpr_32
...