src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

---
name:            v_s_exp_f32
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_exp_f32
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[FEXP2_:%[0-9]+]]:sgpr(s32) = G_FEXP2 [[FEXP2_]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FEXP2_]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_FEXP2 %1
    $vgpr0 = COPY %1(s32)
...
---
name:            v_s_exp_f16
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_exp_f16
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[FEXP2_:%[0-9]+]]:sgpr(s16) = G_FEXP2 [[TRUNC]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[FEXP2_]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s16) = G_TRUNC %0(s32)
    %2:_(s16) = G_FEXP2 %1
    %3:_(s32) = G_ANYEXT %2(s16)
    $vgpr0 = COPY %3(s32)

...
---
name:            v_s_log_f32
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_log_f32
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:sgpr(s32) = G_FLOG2 [[COPY]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FLOG2_]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_FLOG2 %0
    $vgpr0 = COPY %1(s32)

...
---
name:            v_s_log_f16
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_log_f16
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:sgpr(s16) = G_FLOG2 [[TRUNC]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[FLOG2_]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s16) = G_TRUNC %0(s32)
    %2:_(s16) = G_FLOG2 %1
    %3:_(s32) = G_ANYEXT %2(s16)
    $vgpr0 = COPY %3(s32)

...
---
name:            v_s_rcp_f32
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_rcp_f32
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY]](s32)
    ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0(s32)
    $vgpr0 = COPY %1(s32)

...
---
name:            v_s_rcp_f16
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_rcp_f16
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s16) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](s16)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[INT]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s16) = G_TRUNC %0(s32)
    %2:_(s16) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1(s16)
    %3:_(s32) = G_ANYEXT %2(s16)
    $vgpr0 = COPY %3(s32)

...
---
name:            v_s_rsq_f32
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_rsq_f32
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
    ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0(s32)
    $vgpr0 = COPY %1(s32)

...
---
name:            v_s_rsq_f16
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_rsq_f16
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[TRUNC]](s16)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[INT]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s16) = G_TRUNC %0(s32)
    %2:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1(s16)
    %3:_(s32) = G_ANYEXT %2(s16)
    $vgpr0 = COPY %3(s32)

...
---
name:            v_s_sqrt_f32
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_sqrt_f32
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:sgpr(s32) = G_FSQRT [[COPY]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FSQRT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_FSQRT %0
    $vgpr0 = COPY %1(s32)

...
---
name:            v_s_sqrt_f16
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_s_sqrt_f16
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:sgpr(s16) = G_FSQRT [[TRUNC]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[FSQRT]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s16) = G_TRUNC %0(s32)
    %2:_(s16) = G_FSQRT %1
    %3:_(s32) = G_ANYEXT %2(s16)
    $vgpr0 = COPY %3(s32)

...
---
name:            v_amdgcn_sqrt_f32
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_amdgcn_sqrt_f32
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[COPY]](s32)
    ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %0(s32)
    $vgpr0 = COPY %1(s32)

...
---
name:            v_amdgcn_sqrt_f16
legalized:       true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: v_amdgcn_sqrt_f16
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[TRUNC]](s16)
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[INT]](s16)
    ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s16) = G_TRUNC %0(s32)
    %2:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %1(s16)
    %3:_(s32) = G_ANYEXT %2(s16)
    $vgpr0 = COPY %3(s32)

...