src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

---
name: fceil_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0
    ; CHECK-LABEL: name: fceil_s
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
    ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY1]]
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_FCEIL %0
...

---
name: fceil_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: fceil_v
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_FCEIL %0
...