| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s |
| |
| --- |
| name: fexp2_s16_vs |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; CHECK-LABEL: name: fexp2_s16_vs |
| ; CHECK: liveins: $sgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; CHECK-NEXT: [[V_EXP_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec |
| ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_EXP_F16_e64_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s16) = G_TRUNC %0 |
| %2:vgpr(s16) = G_FEXP2 %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: fexp2_s16_vv |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: fexp2_s16_vv |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK-NEXT: [[V_EXP_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec |
| ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_EXP_F16_e64_]] |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:vgpr(s16) = G_TRUNC %0 |
| %2:vgpr(s16) = G_FEXP2 %1 |
| S_ENDPGM 0, implicit %2 |
| ... |