src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---
name: cttz_zero_undef_s32_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: cttz_zero_undef_s32_ss
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK-NEXT: [[S_FF1_I32_B32_:%[0-9]+]]:sreg_32 = S_FF1_I32_B32 [[COPY]]
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FF1_I32_B32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = G_CTTZ_ZERO_UNDEF %0
    S_ENDPGM 0, implicit %1
...

---
name: cttz_zero_undef_s32_vs
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: cttz_zero_undef_s32_vs
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = G_CTTZ_ZERO_UNDEF %0
    S_ENDPGM 0, implicit %1
...

---
name: cttz_zero_undef_s32_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: cttz_zero_undef_s32_vv
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = G_CTTZ_ZERO_UNDEF %0
    S_ENDPGM 0, implicit %1
...

---
name: cttz_zero_undef_s64_ss
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: cttz_zero_undef_s64_ss
    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[S_FF1_I32_B64_:%[0-9]+]]:sreg_32 = S_FF1_I32_B64 [[COPY]]
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FF1_I32_B64_]]
    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %1:sgpr(s32) = G_CTTZ_ZERO_UNDEF %0
    S_ENDPGM 0, implicit %1
...