| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 |
| # RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering %s -o - | FileCheck -check-prefix=GFX10 %s |
| |
| --- |
| name: temporal_divergent_i1_phi |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| ; GFX10-LABEL: name: temporal_divergent_i1_phi |
| ; GFX10: bb.0: |
| ; GFX10-NEXT: successors: %bb.1(0x80000000) |
| ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) |
| ; GFX10-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true |
| ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.1: |
| ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.0 |
| ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1 |
| ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.0, %11(s1), %bb.1 |
| ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true |
| ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI2]], [[C2]] |
| ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI1]](s32) |
| ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] |
| ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C3]] |
| ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32) |
| ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec |
| ; GFX10-NEXT: G_BR %bb.2 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.2: |
| ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[PHI2]](s1), %bb.1 |
| ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.1 |
| ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) |
| ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 |
| ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 |
| ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI3]](s1), [[C5]], [[C4]] |
| ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32)) |
| ; GFX10-NEXT: SI_RETURN |
| bb.0: |
| successors: %bb.1(0x80000000) |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32) |
| %4:_(s1) = G_CONSTANT i1 true |
| %5:_(s32) = G_CONSTANT i32 0 |
| |
| bb.1: |
| successors: %bb.2(0x04000000), %bb.1(0x7c000000) |
| |
| %6:_(s32) = G_PHI %7(s32), %bb.1, %5(s32), %bb.0 |
| %8:_(s32) = G_PHI %5(s32), %bb.0, %9(s32), %bb.1 |
| %10:_(s1) = G_PHI %4(s1), %bb.0, %11(s1), %bb.1 |
| %12:_(s1) = G_CONSTANT i1 true |
| %11:_(s1) = G_XOR %10, %12 |
| %13:_(s32) = G_UITOFP %8(s32) |
| %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0 |
| %15:_(s32) = G_CONSTANT i32 1 |
| %9:_(s32) = G_ADD %8, %15 |
| %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32) |
| SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec |
| G_BR %bb.2 |
| |
| bb.2: |
| %16:_(s1) = G_PHI %10(s1), %bb.1 |
| %17:_(s32) = G_PHI %7(s32), %bb.1 |
| G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32) |
| %18:_(s32) = G_FCONSTANT float 0.000000e+00 |
| %19:_(s32) = G_FCONSTANT float 1.000000e+00 |
| %20:_(s32) = G_SELECT %16(s1), %19, %18 |
| G_STORE %20(s32), %3(p0) :: (store (s32)) |
| SI_RETURN |
| ... |
| |
| --- |
| name: temporal_divergent_i1_non_phi |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| ; GFX10-LABEL: name: temporal_divergent_i1_non_phi |
| ; GFX10: bb.0: |
| ; GFX10-NEXT: successors: %bb.1(0x80000000) |
| ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) |
| ; GFX10-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true |
| ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.1: |
| ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.0 |
| ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1 |
| ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.0, %11(s1), %bb.1 |
| ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true |
| ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI2]], [[C2]] |
| ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI1]](s32) |
| ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] |
| ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C3]] |
| ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32) |
| ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec |
| ; GFX10-NEXT: G_BR %bb.2 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.2: |
| ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[XOR]](s1), %bb.1 |
| ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.1 |
| ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) |
| ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 |
| ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 |
| ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI3]](s1), [[C5]], [[C4]] |
| ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32)) |
| ; GFX10-NEXT: SI_RETURN |
| bb.0: |
| successors: %bb.1(0x80000000) |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32) |
| %4:_(s1) = G_CONSTANT i1 true |
| %5:_(s32) = G_CONSTANT i32 0 |
| |
| bb.1: |
| successors: %bb.2(0x04000000), %bb.1(0x7c000000) |
| |
| %6:_(s32) = G_PHI %7(s32), %bb.1, %5(s32), %bb.0 |
| %8:_(s32) = G_PHI %5(s32), %bb.0, %9(s32), %bb.1 |
| %10:_(s1) = G_PHI %4(s1), %bb.0, %11(s1), %bb.1 |
| %12:_(s1) = G_CONSTANT i1 true |
| %11:_(s1) = G_XOR %10, %12 |
| %13:_(s32) = G_UITOFP %8(s32) |
| %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0 |
| %15:_(s32) = G_CONSTANT i32 1 |
| %9:_(s32) = G_ADD %8, %15 |
| %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32) |
| SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec |
| G_BR %bb.2 |
| |
| bb.2: |
| %16:_(s1) = G_PHI %11(s1), %bb.1 |
| %17:_(s32) = G_PHI %7(s32), %bb.1 |
| G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32) |
| %18:_(s32) = G_FCONSTANT float 0.000000e+00 |
| %19:_(s32) = G_FCONSTANT float 1.000000e+00 |
| %20:_(s32) = G_SELECT %16(s1), %19, %18 |
| G_STORE %20(s32), %3(p0) :: (store (s32)) |
| SI_RETURN |
| ... |
| |
| --- |
| name: loop_with_1break |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| ; GFX10-LABEL: name: loop_with_1break |
| ; GFX10: bb.0: |
| ; GFX10-NEXT: successors: %bb.1(0x80000000) |
| ; GFX10-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) |
| ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr0 |
| ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr1 |
| ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32) |
| ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr2 |
| ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr3 |
| ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY5]](s32), [[COPY6]](s32) |
| ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.1: |
| ; GFX10-NEXT: successors: %bb.3(0x50000000), %bb.5(0x30000000) |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %13(s32), %bb.5, [[C]](s32), %bb.0 |
| ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %15(s32), %bb.5 |
| ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true |
| ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32) |
| ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32) |
| ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64) |
| ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1) |
| ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]] |
| ; GFX10-NEXT: G_BRCOND [[ICMP]](s1), %bb.3 |
| ; GFX10-NEXT: G_BR %bb.5 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.2: |
| ; GFX10-NEXT: successors: %bb.4(0x80000000) |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 |
| ; GFX10-NEXT: G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1) |
| ; GFX10-NEXT: G_BR %bb.4 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.3: |
| ; GFX10-NEXT: successors: %bb.5(0x80000000) |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 false |
| ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C6]](s32) |
| ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64) |
| ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1) |
| ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C7]] |
| ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1) |
| ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C7]] |
| ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[COPY2]] |
| ; GFX10-NEXT: G_BR %bb.5 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.4: |
| ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32) |
| ; GFX10-NEXT: S_ENDPGM 0 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.5: |
| ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000) |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1 |
| ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C5]](s1), %bb.3, [[C1]](s1), %bb.1 |
| ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.3, [[C1]](s1), %bb.1 |
| ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI4]](s1), [[PHI]](s32) |
| ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec |
| ; GFX10-NEXT: G_BR %bb.6 |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: bb.6: |
| ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) |
| ; GFX10-NEXT: {{ $}} |
| ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[PHI3]](s1), %bb.5 |
| ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.5 |
| ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI6]](s32) |
| ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI5]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec |
| ; GFX10-NEXT: G_BR %bb.2 |
| bb.0: |
| successors: %bb.1(0x80000000) |
| liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2 |
| |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) |
| %3:_(s32) = COPY $vgpr2 |
| %4:_(s32) = COPY $sgpr0 |
| %5:_(s32) = COPY $sgpr1 |
| %6:_(p1) = G_MERGE_VALUES %4(s32), %5(s32) |
| %7:_(s32) = COPY $sgpr2 |
| %8:_(s32) = COPY $sgpr3 |
| %9:_(p1) = G_MERGE_VALUES %7(s32), %8(s32) |
| %10:_(s32) = G_CONSTANT i32 0 |
| %11:_(s32) = G_IMPLICIT_DEF |
| |
| bb.1: |
| successors: %bb.3(0x50000000), %bb.5(0x30000000) |
| |
| %12:_(s32) = G_PHI %13(s32), %bb.5, %10(s32), %bb.0 |
| %14:_(s32) = G_PHI %10(s32), %bb.0, %15(s32), %bb.5 |
| %16:_(s1) = G_CONSTANT i1 true |
| %17:_(s64) = G_SEXT %14(s32) |
| %18:_(s32) = G_CONSTANT i32 2 |
| %19:_(s64) = G_SHL %17, %18(s32) |
| %20:_(p1) = G_PTR_ADD %6, %19(s64) |
| %21:_(s32) = G_LOAD %20(p1) :: (load (s32), addrspace 1) |
| %22:_(s32) = G_CONSTANT i32 0 |
| %23:_(s1) = G_ICMP intpred(ne), %21(s32), %22 |
| G_BRCOND %23(s1), %bb.3 |
| G_BR %bb.5 |
| |
| bb.2: |
| successors: %bb.4(0x80000000) |
| |
| %24:_(s32) = G_CONSTANT i32 10 |
| G_STORE %24(s32), %9(p1) :: (store (s32), addrspace 1) |
| G_BR %bb.4 |
| |
| bb.3: |
| successors: %bb.5(0x80000000) |
| |
| %25:_(s1) = G_CONSTANT i1 false |
| %26:_(s32) = G_CONSTANT i32 2 |
| %27:_(s64) = G_SHL %17, %26(s32) |
| %28:_(p1) = G_PTR_ADD %2, %27(s64) |
| %29:_(s32) = G_LOAD %28(p1) :: (load (s32), addrspace 1) |
| %30:_(s32) = G_CONSTANT i32 1 |
| %31:_(s32) = G_ADD %29, %30 |
| G_STORE %31(s32), %28(p1) :: (store (s32), addrspace 1) |
| %32:_(s32) = G_ADD %14, %30 |
| %33:_(s1) = G_ICMP intpred(ult), %14(s32), %3 |
| G_BR %bb.5 |
| |
| bb.4: |
| G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32) |
| S_ENDPGM 0 |
| |
| bb.5: |
| successors: %bb.6(0x04000000), %bb.1(0x7c000000) |
| |
| %15:_(s32) = G_PHI %32(s32), %bb.3, %11(s32), %bb.1 |
| %35:_(s1) = G_PHI %25(s1), %bb.3, %16(s1), %bb.1 |
| %36:_(s1) = G_PHI %33(s1), %bb.3, %16(s1), %bb.1 |
| %13:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %36(s1), %12(s32) |
| SI_LOOP %13(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec |
| G_BR %bb.6 |
| |
| bb.6: |
| successors: %bb.2(0x40000000), %bb.4(0x40000000) |
| |
| %37:sreg_32_xm0_xexec(s1) = G_PHI %35(s1), %bb.5 |
| %38:_(s32) = G_PHI %13(s32), %bb.5 |
| G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %38(s32) |
| %34:sreg_32_xm0_xexec(s32) = SI_IF %37(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec |
| G_BR %bb.2 |
| ... |