src/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir - toolchain/rustc - Git at Google

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
 # RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s

 ---
 name:            fshr_i8
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1, $w2

     ; CHECK-LABEL: name: fshr_i8
     ; CHECK: liveins: $w0, $w1, $w2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
     ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[COPY3]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s64)
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
     ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
     ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %3:_(s32) = COPY $w0
     %0:_(s8) = G_TRUNC %3(s32)
     %4:_(s32) = COPY $w1
     %1:_(s8) = G_TRUNC %4(s32)
     %5:_(s32) = COPY $w2
     %2:_(s8) = G_TRUNC %5(s32)
     %6:_(s8) = G_FSHR %0, %1, %2(s8)
     %7:_(s32) = G_ANYEXT %6(s8)
     $w0 = COPY %7(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i16
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1, $w2

     ; CHECK-LABEL: name: fshr_i16
     ; CHECK: liveins: $w0, $w1, $w2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
     ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[COPY3]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s64)
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
     ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
     ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %3:_(s32) = COPY $w0
     %0:_(s16) = G_TRUNC %3(s32)
     %4:_(s32) = COPY $w1
     %1:_(s16) = G_TRUNC %4(s32)
     %5:_(s32) = COPY $w2
     %2:_(s16) = G_TRUNC %5(s32)
     %6:_(s16) = G_FSHR %0, %1, %2(s16)
     %7:_(s32) = G_ANYEXT %6(s16)
     $w0 = COPY %7(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i32
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1, $w2

     ; CHECK-LABEL: name: fshr_i32
     ; CHECK: liveins: $w0, $w1, $w2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
     ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s64)
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[AND]](s32)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
     ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %2:_(s32) = COPY $w2
     %3:_(s32) = G_FSHR %0, %1, %2(s32)
     $w0 = COPY %3(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i64
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1, $x2

     ; CHECK-LABEL: name: fshr_i64
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]]
     ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64)
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND1]](s64)
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[AND]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
     ; CHECK-NEXT: $x0 = COPY [[OR]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = G_FSHR %0, %1, %2(s64)
     $x0 = COPY %3(s64)
     RET_ReallyLR implicit $x0

 ...


 ---
 name:            fshr_i8_const_shift
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1

     ; CHECK-LABEL: name: fshr_i8_const_shift
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
     ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s8) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s8) = G_TRUNC %3(s32)
     %7:_(s8) = G_CONSTANT i8 7
     %5:_(s8) = G_FSHR %0, %1, %7(s8)
     %6:_(s32) = G_ANYEXT %5(s8)
     $w0 = COPY %6(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i8_const_overshift
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1

     ; CHECK-LABEL: name: fshr_i8_const_overshift
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
     ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s8) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s8) = G_TRUNC %3(s32)
     %7:_(s8) = G_CONSTANT i8 10
     %5:_(s8) = G_FSHR %0, %1, %7(s8)
     %6:_(s32) = G_ANYEXT %5(s8)
     $w0 = COPY %6(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i8_shift_by_bandwidth
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1

     ; CHECK-LABEL: name: fshr_i8_shift_by_bandwidth
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[C1]](s64)
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
     ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C3]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
     ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s8) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s8) = G_TRUNC %3(s32)
     %7:_(s8) = G_CONSTANT i8 8
     %5:_(s8) = G_FSHR %0, %1, %7(s8)
     %6:_(s32) = G_ANYEXT %5(s8)
     $w0 = COPY %6(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i16_const_shift
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1

     ; CHECK-LABEL: name: fshr_i16_const_shift
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
     ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s16) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s16) = G_TRUNC %3(s32)
     %4:_(s16) = G_CONSTANT i16 5
     %5:_(s16) = G_FSHR %0, %1, %4(s16)
     %6:_(s32) = G_ANYEXT %5(s16)
     $w0 = COPY %6(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i16_const_overshift
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1

     ; CHECK-LABEL: name: fshr_i16_const_overshift
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
     ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s16) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s16) = G_TRUNC %3(s32)
     %4:_(s16) = G_CONSTANT i16 20
     %5:_(s16) = G_FSHR %0, %1, %4(s16)
     %6:_(s32) = G_ANYEXT %5(s16)
     $w0 = COPY %6(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i16_shift_by_bandwidth
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1

     ; CHECK-LABEL: name: fshr_i16_shift_by_bandwidth
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[C1]](s64)
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
     ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C3]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
     ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %2:_(s32) = COPY $w0
     %0:_(s16) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $w1
     %1:_(s16) = G_TRUNC %3(s32)
     %4:_(s16) = G_CONSTANT i16 16
     %5:_(s16) = G_FSHR %0, %1, %4(s16)
     %6:_(s32) = G_ANYEXT %5(s16)
     $w0 = COPY %6(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i32_const_shift
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1

     ; CHECK-LABEL: name: fshr_i32_const_shift
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 9
     ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
     ; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %2:_(s32) = G_CONSTANT i32 9
     %3:_(s32) = G_FSHR %0, %1, %2(s32)
     $w0 = COPY %3(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i32_const_overshift
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1

     ; CHECK-LABEL: name: fshr_i32_const_overshift
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
     ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
     ; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %4:_(s32) = G_CONSTANT i32  42
     %3:_(s32) = G_FSHR %0, %1, %4(s32)
     $w0 = COPY %3(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i32_shift_by_bitwidth
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1

     ; CHECK-LABEL: name: fshr_i32_shift_by_bitwidth
     ; CHECK: liveins: $w0, $w1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %1:_(s32) = COPY $w1
     $w0 = COPY %1(s32)
     RET_ReallyLR implicit $w0

 ...

 ---
 name:            fshr_i64_const_shift
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1

     ; CHECK-LABEL: name: fshr_i64_const_shift
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 41
     ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
     ; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %4:_(s64) = G_CONSTANT i64 41
     %3:_(s64) = G_FSHR %0, %1, %4(s64)
     $x0 = COPY %3(s64)
     RET_ReallyLR implicit $x0

 ...

 ---
 name:            fshr_i64_const_overshift
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1

     ; CHECK-LABEL: name: fshr_i64_const_overshift
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
     ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
     ; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %4:_(s64) = G_CONSTANT i64 72
     %3:_(s64) = G_FSHR %0, %1, %4(s64)
     $x0 = COPY %3(s64)
     RET_ReallyLR implicit $x0

 ...

 ---
 name:            fshr_i64_shift_by_bandwidth
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1

     ; CHECK-LABEL: name: fshr_i64_shift_by_bandwidth
     ; CHECK: liveins: $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64)
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[C]](s64)
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C1]](s64)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
     ; CHECK-NEXT: $x0 = COPY [[OR]](s64)
     ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %4:_(s64) = G_CONSTANT i64 64
     %3:_(s64) = G_FSHR %0, %1, %4(s64)
     $x0 = COPY %3(s64)
     RET_ReallyLR implicit $x0

 ...

 ---
 name:            fshr_v4i32_shift_by_bitwidth
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $q0, $q1

     ; CHECK-LABEL: name: fshr_v4i32_shift_by_bitwidth
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
     ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
     ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32), [[C2]](s32), [[C2]](s32)
     ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[BUILD_VECTOR2]](<4 x s32>)
     ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(<4 x s32>) = G_SHL [[SHL]], [[BUILD_VECTOR1]](<4 x s32>)
     ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY1]], [[BUILD_VECTOR]](<4 x s32>)
     ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[SHL1]], [[LSHR]]
     ; CHECK-NEXT: $q0 = COPY [[OR]](<4 x s32>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %0:_(<4 x s32>) = COPY $q0
     %1:_(<4 x s32>) = COPY $q1
     %3:_(s32) = G_CONSTANT i32 32
     %2:_(<4 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32), %3(s32), %3(s32)
     %4:_(<4 x s32>) = G_FSHR %0, %1, %2(<4 x s32>)
     $q0 = COPY %4(<4 x s32>)
     RET_ReallyLR implicit $q0

 ...
	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
	# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=legalizer -global-isel-abort=1 %s -o - \| FileCheck %s

	---
	name: fshr_i8
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1, $w2

	; CHECK-LABEL: name: fshr_i8
	; CHECK: liveins: $w0, $w1, $w2
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
	; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
	; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
	; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[COPY3]]
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s64)
	; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
	; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
	; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
	; CHECK-NEXT: $w0 = COPY [[OR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%3:_(s32) = COPY $w0
	%0:_(s8) = G_TRUNC %3(s32)
	%4:_(s32) = COPY $w1
	%1:_(s8) = G_TRUNC %4(s32)
	%5:_(s32) = COPY $w2
	%2:_(s8) = G_TRUNC %5(s32)
	%6:_(s8) = G_FSHR %0, %1, %2(s8)
	%7:_(s32) = G_ANYEXT %6(s8)
	$w0 = COPY %7(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i16
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1, $w2

	; CHECK-LABEL: name: fshr_i16
	; CHECK: liveins: $w0, $w1, $w2
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
	; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
	; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
	; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[COPY3]]
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s64)
	; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
	; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
	; CHECK-NEXT: $w0 = COPY [[OR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%3:_(s32) = COPY $w0
	%0:_(s16) = G_TRUNC %3(s32)
	%4:_(s32) = COPY $w1
	%1:_(s16) = G_TRUNC %4(s32)
	%5:_(s32) = COPY $w2
	%2:_(s16) = G_TRUNC %5(s32)
	%6:_(s16) = G_FSHR %0, %1, %2(s16)
	%7:_(s32) = G_ANYEXT %6(s16)
	$w0 = COPY %7(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i32
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1, $w2

	; CHECK-LABEL: name: fshr_i32
	; CHECK: liveins: $w0, $w1, $w2
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
	; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
	; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s64)
	; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[AND]](s32)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
	; CHECK-NEXT: $w0 = COPY [[OR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%0:_(s32) = COPY $w0
	%1:_(s32) = COPY $w1
	%2:_(s32) = COPY $w2
	%3:_(s32) = G_FSHR %0, %1, %2(s32)
	$w0 = COPY %3(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i64
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $x0, $x1, $x2

	; CHECK-LABEL: name: fshr_i64
	; CHECK: liveins: $x0, $x1, $x2
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
	; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
	; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]]
	; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64)
	; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND1]](s64)
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[AND]](s64)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
	; CHECK-NEXT: $x0 = COPY [[OR]](s64)
	; CHECK-NEXT: RET_ReallyLR implicit $x0
	%0:_(s64) = COPY $x0
	%1:_(s64) = COPY $x1
	%2:_(s64) = COPY $x2
	%3:_(s64) = G_FSHR %0, %1, %2(s64)
	$x0 = COPY %3(s64)
	RET_ReallyLR implicit $x0

	...


	---
	name: fshr_i8_const_shift
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1

	; CHECK-LABEL: name: fshr_i8_const_shift
	; CHECK: liveins: $w0, $w1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
	; CHECK-NEXT: $w0 = COPY [[OR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%2:_(s32) = COPY $w0
	%0:_(s8) = G_TRUNC %2(s32)
	%3:_(s32) = COPY $w1
	%1:_(s8) = G_TRUNC %3(s32)
	%7:_(s8) = G_CONSTANT i8 7
	%5:_(s8) = G_FSHR %0, %1, %7(s8)
	%6:_(s32) = G_ANYEXT %5(s8)
	$w0 = COPY %6(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i8_const_overshift
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1

	; CHECK-LABEL: name: fshr_i8_const_overshift
	; CHECK: liveins: $w0, $w1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
	; CHECK-NEXT: $w0 = COPY [[OR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%2:_(s32) = COPY $w0
	%0:_(s8) = G_TRUNC %2(s32)
	%3:_(s32) = COPY $w1
	%1:_(s8) = G_TRUNC %3(s32)
	%7:_(s8) = G_CONSTANT i8 10
	%5:_(s8) = G_FSHR %0, %1, %7(s8)
	%6:_(s32) = G_ANYEXT %5(s8)
	$w0 = COPY %6(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i8_shift_by_bandwidth
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1

	; CHECK-LABEL: name: fshr_i8_shift_by_bandwidth
	; CHECK: liveins: $w0, $w1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
	; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[C1]](s64)
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
	; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C3]](s64)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
	; CHECK-NEXT: $w0 = COPY [[OR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%2:_(s32) = COPY $w0
	%0:_(s8) = G_TRUNC %2(s32)
	%3:_(s32) = COPY $w1
	%1:_(s8) = G_TRUNC %3(s32)
	%7:_(s8) = G_CONSTANT i8 8
	%5:_(s8) = G_FSHR %0, %1, %7(s8)
	%6:_(s32) = G_ANYEXT %5(s8)
	$w0 = COPY %6(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i16_const_shift
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1

	; CHECK-LABEL: name: fshr_i16_const_shift
	; CHECK: liveins: $w0, $w1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
	; CHECK-NEXT: $w0 = COPY [[OR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%2:_(s32) = COPY $w0
	%0:_(s16) = G_TRUNC %2(s32)
	%3:_(s32) = COPY $w1
	%1:_(s16) = G_TRUNC %3(s32)
	%4:_(s16) = G_CONSTANT i16 5
	%5:_(s16) = G_FSHR %0, %1, %4(s16)
	%6:_(s32) = G_ANYEXT %5(s16)
	$w0 = COPY %6(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i16_const_overshift
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1

	; CHECK-LABEL: name: fshr_i16_const_overshift
	; CHECK: liveins: $w0, $w1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
	; CHECK-NEXT: $w0 = COPY [[OR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%2:_(s32) = COPY $w0
	%0:_(s16) = G_TRUNC %2(s32)
	%3:_(s32) = COPY $w1
	%1:_(s16) = G_TRUNC %3(s32)
	%4:_(s16) = G_CONSTANT i16 20
	%5:_(s16) = G_FSHR %0, %1, %4(s16)
	%6:_(s32) = G_ANYEXT %5(s16)
	$w0 = COPY %6(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i16_shift_by_bandwidth
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1

	; CHECK-LABEL: name: fshr_i16_shift_by_bandwidth
	; CHECK: liveins: $w0, $w1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
	; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[C1]](s64)
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
	; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C3]](s64)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
	; CHECK-NEXT: $w0 = COPY [[OR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%2:_(s32) = COPY $w0
	%0:_(s16) = G_TRUNC %2(s32)
	%3:_(s32) = COPY $w1
	%1:_(s16) = G_TRUNC %3(s32)
	%4:_(s16) = G_CONSTANT i16 16
	%5:_(s16) = G_FSHR %0, %1, %4(s16)
	%6:_(s32) = G_ANYEXT %5(s16)
	$w0 = COPY %6(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i32_const_shift
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1

	; CHECK-LABEL: name: fshr_i32_const_shift
	; CHECK: liveins: $w0, $w1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 9
	; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
	; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%0:_(s32) = COPY $w0
	%1:_(s32) = COPY $w1
	%2:_(s32) = G_CONSTANT i32 9
	%3:_(s32) = G_FSHR %0, %1, %2(s32)
	$w0 = COPY %3(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i32_const_overshift
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1

	; CHECK-LABEL: name: fshr_i32_const_overshift
	; CHECK: liveins: $w0, $w1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
	; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
	; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%0:_(s32) = COPY $w0
	%1:_(s32) = COPY $w1
	%4:_(s32) = G_CONSTANT i32 42
	%3:_(s32) = G_FSHR %0, %1, %4(s32)
	$w0 = COPY %3(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i32_shift_by_bitwidth
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $w0, $w1

	; CHECK-LABEL: name: fshr_i32_shift_by_bitwidth
	; CHECK: liveins: $w0, $w1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w1
	; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
	; CHECK-NEXT: RET_ReallyLR implicit $w0
	%1:_(s32) = COPY $w1
	$w0 = COPY %1(s32)
	RET_ReallyLR implicit $w0

	...

	---
	name: fshr_i64_const_shift
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $x0, $x1

	; CHECK-LABEL: name: fshr_i64_const_shift
	; CHECK: liveins: $x0, $x1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 41
	; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
	; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
	; CHECK-NEXT: RET_ReallyLR implicit $x0
	%0:_(s64) = COPY $x0
	%1:_(s64) = COPY $x1
	%4:_(s64) = G_CONSTANT i64 41
	%3:_(s64) = G_FSHR %0, %1, %4(s64)
	$x0 = COPY %3(s64)
	RET_ReallyLR implicit $x0

	...

	---
	name: fshr_i64_const_overshift
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $x0, $x1

	; CHECK-LABEL: name: fshr_i64_const_overshift
	; CHECK: liveins: $x0, $x1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
	; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
	; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
	; CHECK-NEXT: RET_ReallyLR implicit $x0
	%0:_(s64) = COPY $x0
	%1:_(s64) = COPY $x1
	%4:_(s64) = G_CONSTANT i64 72
	%3:_(s64) = G_FSHR %0, %1, %4(s64)
	$x0 = COPY %3(s64)
	RET_ReallyLR implicit $x0

	...

	---
	name: fshr_i64_shift_by_bandwidth
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $x0, $x1

	; CHECK-LABEL: name: fshr_i64_shift_by_bandwidth
	; CHECK: liveins: $x0, $x1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64)
	; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[C]](s64)
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C1]](s64)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
	; CHECK-NEXT: $x0 = COPY [[OR]](s64)
	; CHECK-NEXT: RET_ReallyLR implicit $x0
	%0:_(s64) = COPY $x0
	%1:_(s64) = COPY $x1
	%4:_(s64) = G_CONSTANT i64 64
	%3:_(s64) = G_FSHR %0, %1, %4(s64)
	$x0 = COPY %3(s64)
	RET_ReallyLR implicit $x0

	...

	---
	name: fshr_v4i32_shift_by_bitwidth
	alignment: 4
	tracksRegLiveness: true
	body: \|
	bb.0:
	liveins: $q0, $q1

	; CHECK-LABEL: name: fshr_v4i32_shift_by_bitwidth
	; CHECK: liveins: $q0, $q1
	; CHECK-NEXT: {{ $}}
	; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
	; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
	; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
	; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
	; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
	; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
	; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
	; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32), [[C2]](s32), [[C2]](s32)
	; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[BUILD_VECTOR2]](<4 x s32>)
	; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(<4 x s32>) = G_SHL [[SHL]], [[BUILD_VECTOR1]](<4 x s32>)
	; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY1]], [[BUILD_VECTOR]](<4 x s32>)
	; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[SHL1]], [[LSHR]]
	; CHECK-NEXT: $q0 = COPY [[OR]](<4 x s32>)
	; CHECK-NEXT: RET_ReallyLR implicit $q0
	%0:_(<4 x s32>) = COPY $q0
	%1:_(<4 x s32>) = COPY $q1
	%3:_(s32) = G_CONSTANT i32 32
	%2:_(<4 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32), %3(s32), %3(s32)
	%4:_(<4 x s32>) = G_FSHR %0, %1, %2(<4 x s32>)
	$q0 = COPY %4(<4 x s32>)
	RET_ReallyLR implicit $q0

	...