src/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name:            fadd
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: fadd
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_FCONSTANT float 1.000000e+00
    ; CHECK-NEXT: %add:_(s32) = G_FADD [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %add(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_FCONSTANT float 1.000000e+00
    %add:_(s32) = G_FADD %cst, %0
    $s0 = COPY %add
    RET_ReallyLR

...
---
name:            fmul
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: fmul
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst:_(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: %mul:_(s32) = G_FMUL [[COPY]], %cst
    ; CHECK-NEXT: $s0 = COPY %mul(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(s32) = COPY $s0
    %cst:_(s32) = G_FCONSTANT float 2.000000e+00
    %mul:_(s32) = G_FMUL %cst, %0
    $s0 = COPY %mul
    RET_ReallyLR
...
---
name:            fmul_vector
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: fmul_vector
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK-NEXT: %cst_scalar:_(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: %cst:_(<4 x s32>) = G_BUILD_VECTOR %cst_scalar(s32), %cst_scalar(s32), %cst_scalar(s32), %cst_scalar(s32)
    ; CHECK-NEXT: %mul:_(<4 x s32>) = G_FMUL [[COPY]], %cst
    ; CHECK-NEXT: $q0 = COPY %mul(<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(<4 x s32>) = COPY $q0
    %cst_scalar:_(s32) = G_FCONSTANT float 2.000000e+00
    %cst:_(<4 x s32>) = G_BUILD_VECTOR %cst_scalar, %cst_scalar, %cst_scalar, %cst_scalar
    %mul:_(<4 x s32>) = G_FMUL %cst, %0
    $q0 = COPY %mul
    RET_ReallyLR
...
---
name:            fmul_splat_with_undef
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $q0

    ; CHECK-LABEL: name: fmul_splat_with_undef
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK-NEXT: %undef:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %cst_scalar:_(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: %cst:_(<4 x s32>) = G_BUILD_VECTOR %undef(s32), %undef(s32), %cst_scalar(s32), %cst_scalar(s32)
    ; CHECK-NEXT: %mul:_(<4 x s32>) = G_FMUL [[COPY]], %cst
    ; CHECK-NEXT: $q0 = COPY %mul(<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(<4 x s32>) = COPY $q0
    %undef:_(s32) = G_IMPLICIT_DEF
    %cst_scalar:_(s32) = G_FCONSTANT float 2.000000e+00
    %cst:_(<4 x s32>) = G_BUILD_VECTOR %undef, %undef, %cst_scalar, %cst_scalar
    %mul:_(<4 x s32>) = G_FMUL %cst, %0
    $q0 = COPY %mul
    RET_ReallyLR
...
---
name:            fmul_vector_nonsplat
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $s0

    ; CHECK-LABEL: name: fmul_vector_nonsplat
    ; CHECK: liveins: $s0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK-NEXT: %scalar:_(s32) = COPY $s0
    ; CHECK-NEXT: %cst_scalar:_(s32) = G_FCONSTANT float 2.000000e+00
    ; CHECK-NEXT: %cst:_(<4 x s32>) = G_BUILD_VECTOR %cst_scalar(s32), %cst_scalar(s32), %cst_scalar(s32), %scalar(s32)
    ; CHECK-NEXT: %mul:_(<4 x s32>) = G_FMUL %cst, [[COPY]]
    ; CHECK-NEXT: $q0 = COPY %mul(<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR
    %0:_(<4 x s32>) = COPY $q0
    %scalar:_(s32) = COPY $s0
    %cst_scalar:_(s32) = G_FCONSTANT float 2.000000e+00
    %cst:_(<4 x s32>) = G_BUILD_VECTOR %cst_scalar, %cst_scalar, %cst_scalar, %scalar
    %mul:_(<4 x s32>) = G_FMUL %cst, %0
    $q0 = COPY %mul
    RET_ReallyLR
...