| //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file defines the interfaces that RISCV uses to lower LLVM code into a |
| // selection DAG. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "RISCVISelLowering.h" |
| #include "RISCV.h" |
| #include "RISCVRegisterInfo.h" |
| #include "RISCVSubtarget.h" |
| #include "RISCVTargetMachine.h" |
| #include "llvm/CodeGen/CallingConvLower.h" |
| #include "llvm/CodeGen/MachineFrameInfo.h" |
| #include "llvm/CodeGen/MachineFunction.h" |
| #include "llvm/CodeGen/MachineInstrBuilder.h" |
| #include "llvm/CodeGen/MachineRegisterInfo.h" |
| #include "llvm/CodeGen/SelectionDAGISel.h" |
| #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" |
| #include "llvm/CodeGen/ValueTypes.h" |
| #include "llvm/IR/DiagnosticInfo.h" |
| #include "llvm/IR/DiagnosticPrinter.h" |
| #include "llvm/Support/Debug.h" |
| #include "llvm/Support/ErrorHandling.h" |
| #include "llvm/Support/raw_ostream.h" |
| |
| using namespace llvm; |
| |
| #define DEBUG_TYPE "riscv-lower" |
| |
| RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, |
| const RISCVSubtarget &STI) |
| : TargetLowering(TM), Subtarget(STI) { |
| |
| MVT XLenVT = Subtarget.getXLenVT(); |
| |
| // Set up the register classes. |
| addRegisterClass(XLenVT, &RISCV::GPRRegClass); |
| |
| // Compute derived properties from the register classes. |
| computeRegisterProperties(STI.getRegisterInfo()); |
| |
| setStackPointerRegisterToSaveRestore(RISCV::X2); |
| |
| for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) |
| setLoadExtAction(N, XLenVT, MVT::i1, Promote); |
| |
| // TODO: add all necessary setOperationAction calls. |
| setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand); |
| |
| setOperationAction(ISD::BR_JT, MVT::Other, Expand); |
| setOperationAction(ISD::BR_CC, XLenVT, Expand); |
| setOperationAction(ISD::SELECT, XLenVT, Custom); |
| setOperationAction(ISD::SELECT_CC, XLenVT, Expand); |
| |
| setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); |
| setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); |
| |
| for (auto VT : {MVT::i1, MVT::i8, MVT::i16}) |
| setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); |
| |
| setOperationAction(ISD::ADDC, XLenVT, Expand); |
| setOperationAction(ISD::ADDE, XLenVT, Expand); |
| setOperationAction(ISD::SUBC, XLenVT, Expand); |
| setOperationAction(ISD::SUBE, XLenVT, Expand); |
| |
| setOperationAction(ISD::SREM, XLenVT, Expand); |
| setOperationAction(ISD::SDIVREM, XLenVT, Expand); |
| setOperationAction(ISD::SDIV, XLenVT, Expand); |
| setOperationAction(ISD::UREM, XLenVT, Expand); |
| setOperationAction(ISD::UDIVREM, XLenVT, Expand); |
| setOperationAction(ISD::UDIV, XLenVT, Expand); |
| |
| setOperationAction(ISD::MUL, XLenVT, Expand); |
| setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand); |
| setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand); |
| setOperationAction(ISD::MULHS, XLenVT, Expand); |
| setOperationAction(ISD::MULHU, XLenVT, Expand); |
| |
| setOperationAction(ISD::SHL_PARTS, XLenVT, Expand); |
| setOperationAction(ISD::SRL_PARTS, XLenVT, Expand); |
| setOperationAction(ISD::SRA_PARTS, XLenVT, Expand); |
| |
| setOperationAction(ISD::ROTL, XLenVT, Expand); |
| setOperationAction(ISD::ROTR, XLenVT, Expand); |
| setOperationAction(ISD::BSWAP, XLenVT, Expand); |
| setOperationAction(ISD::CTTZ, XLenVT, Expand); |
| setOperationAction(ISD::CTLZ, XLenVT, Expand); |
| setOperationAction(ISD::CTPOP, XLenVT, Expand); |
| |
| setOperationAction(ISD::GlobalAddress, XLenVT, Custom); |
| setOperationAction(ISD::BlockAddress, XLenVT, Custom); |
| |
| setBooleanContents(ZeroOrOneBooleanContent); |
| |
| // Function alignments (log2). |
| setMinFunctionAlignment(3); |
| setPrefFunctionAlignment(3); |
| |
| // Effectively disable jump table generation. |
| setMinimumJumpTableEntries(INT_MAX); |
| } |
| |
| // Changes the condition code and swaps operands if necessary, so the SetCC |
| // operation matches one of the comparisons supported directly in the RISC-V |
| // ISA. |
| static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { |
| switch (CC) { |
| default: |
| break; |
| case ISD::SETGT: |
| case ISD::SETLE: |
| case ISD::SETUGT: |
| case ISD::SETULE: |
| CC = ISD::getSetCCSwappedOperands(CC); |
| std::swap(LHS, RHS); |
| break; |
| } |
| } |
| |
| // Return the RISC-V branch opcode that matches the given DAG integer |
| // condition code. The CondCode must be one of those supported by the RISC-V |
| // ISA (see normaliseSetCC). |
| static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC) { |
| switch (CC) { |
| default: |
| llvm_unreachable("Unsupported CondCode"); |
| case ISD::SETEQ: |
| return RISCV::BEQ; |
| case ISD::SETNE: |
| return RISCV::BNE; |
| case ISD::SETLT: |
| return RISCV::BLT; |
| case ISD::SETGE: |
| return RISCV::BGE; |
| case ISD::SETULT: |
| return RISCV::BLTU; |
| case ISD::SETUGE: |
| return RISCV::BGEU; |
| } |
| } |
| |
| SDValue RISCVTargetLowering::LowerOperation(SDValue Op, |
| SelectionDAG &DAG) const { |
| switch (Op.getOpcode()) { |
| default: |
| report_fatal_error("unimplemented operand"); |
| case ISD::GlobalAddress: |
| return lowerGlobalAddress(Op, DAG); |
| case ISD::BlockAddress: |
| return lowerBlockAddress(Op, DAG); |
| case ISD::SELECT: |
| return lowerSELECT(Op, DAG); |
| } |
| } |
| |
| SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op, |
| SelectionDAG &DAG) const { |
| SDLoc DL(Op); |
| EVT Ty = Op.getValueType(); |
| GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); |
| const GlobalValue *GV = N->getGlobal(); |
| int64_t Offset = N->getOffset(); |
| |
| if (isPositionIndependent() || Subtarget.is64Bit()) |
| report_fatal_error("Unable to lowerGlobalAddress"); |
| |
| SDValue GAHi = |
| DAG.getTargetGlobalAddress(GV, DL, Ty, Offset, RISCVII::MO_HI); |
| SDValue GALo = |
| DAG.getTargetGlobalAddress(GV, DL, Ty, Offset, RISCVII::MO_LO); |
| SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0); |
| SDValue MNLo = |
| SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0); |
| return MNLo; |
| } |
| |
| SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op, |
| SelectionDAG &DAG) const { |
| SDLoc DL(Op); |
| EVT Ty = Op.getValueType(); |
| BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); |
| const BlockAddress *BA = N->getBlockAddress(); |
| int64_t Offset = N->getOffset(); |
| |
| if (isPositionIndependent() || Subtarget.is64Bit()) |
| report_fatal_error("Unable to lowerBlockAddress"); |
| |
| SDValue BAHi = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_HI); |
| SDValue BALo = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_LO); |
| SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, BAHi), 0); |
| SDValue MNLo = |
| SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, BALo), 0); |
| return MNLo; |
| } |
| |
| SDValue RISCVTargetLowering::lowerExternalSymbol(SDValue Op, |
| SelectionDAG &DAG) const { |
| SDLoc DL(Op); |
| EVT Ty = Op.getValueType(); |
| ExternalSymbolSDNode *N = cast<ExternalSymbolSDNode>(Op); |
| const char *Sym = N->getSymbol(); |
| |
| // TODO: should also handle gp-relative loads. |
| |
| if (isPositionIndependent() || Subtarget.is64Bit()) |
| report_fatal_error("Unable to lowerExternalSymbol"); |
| |
| SDValue GAHi = DAG.getTargetExternalSymbol(Sym, Ty, RISCVII::MO_HI); |
| SDValue GALo = DAG.getTargetExternalSymbol(Sym, Ty, RISCVII::MO_LO); |
| SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0); |
| SDValue MNLo = |
| SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0); |
| return MNLo; |
| } |
| |
| SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { |
| SDValue CondV = Op.getOperand(0); |
| SDValue TrueV = Op.getOperand(1); |
| SDValue FalseV = Op.getOperand(2); |
| SDLoc DL(Op); |
| MVT XLenVT = Subtarget.getXLenVT(); |
| |
| // If the result type is XLenVT and CondV is the output of a SETCC node |
| // which also operated on XLenVT inputs, then merge the SETCC node into the |
| // lowered RISCVISD::SELECT_CC to take advantage of the integer |
| // compare+branch instructions. i.e.: |
| // (select (setcc lhs, rhs, cc), truev, falsev) |
| // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev) |
| if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC && |
| CondV.getOperand(0).getSimpleValueType() == XLenVT) { |
| SDValue LHS = CondV.getOperand(0); |
| SDValue RHS = CondV.getOperand(1); |
| auto CC = cast<CondCodeSDNode>(CondV.getOperand(2)); |
| ISD::CondCode CCVal = CC->get(); |
| |
| normaliseSetCC(LHS, RHS, CCVal); |
| |
| SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT); |
| SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); |
| SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; |
| return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops); |
| } |
| |
| // Otherwise: |
| // (select condv, truev, falsev) |
| // -> (riscvisd::select_cc condv, zero, setne, truev, falsev) |
| SDValue Zero = DAG.getConstant(0, DL, XLenVT); |
| SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT); |
| |
| SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); |
| SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV}; |
| |
| return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops); |
| } |
| |
| MachineBasicBlock * |
| RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, |
| MachineBasicBlock *BB) const { |
| const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); |
| DebugLoc DL = MI.getDebugLoc(); |
| |
| assert(MI.getOpcode() == RISCV::Select_GPR_Using_CC_GPR && |
| "Unexpected instr type to insert"); |
| |
| // To "insert" a SELECT instruction, we actually have to insert the triangle |
| // control-flow pattern. The incoming instruction knows the destination vreg |
| // to set, the condition code register to branch on, the true/false values to |
| // select between, and the condcode to use to select the appropriate branch. |
| // |
| // We produce the following control flow: |
| // HeadMBB |
| // | \ |
| // | IfFalseMBB |
| // | / |
| // TailMBB |
| const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
| MachineFunction::iterator I = ++BB->getIterator(); |
| |
| MachineBasicBlock *HeadMBB = BB; |
| MachineFunction *F = BB->getParent(); |
| MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB); |
| MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB); |
| |
| F->insert(I, IfFalseMBB); |
| F->insert(I, TailMBB); |
| // Move all remaining instructions to TailMBB. |
| TailMBB->splice(TailMBB->begin(), HeadMBB, |
| std::next(MachineBasicBlock::iterator(MI)), HeadMBB->end()); |
| // Update machine-CFG edges by transferring all successors of the current |
| // block to the new block which will contain the Phi node for the select. |
| TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB); |
| // Set the successors for HeadMBB. |
| HeadMBB->addSuccessor(IfFalseMBB); |
| HeadMBB->addSuccessor(TailMBB); |
| |
| // Insert appropriate branch. |
| unsigned LHS = MI.getOperand(1).getReg(); |
| unsigned RHS = MI.getOperand(2).getReg(); |
| auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm()); |
| unsigned Opcode = getBranchOpcodeForIntCondCode(CC); |
| |
| BuildMI(HeadMBB, DL, TII.get(Opcode)) |
| .addReg(LHS) |
| .addReg(RHS) |
| .addMBB(TailMBB); |
| |
| // IfFalseMBB just falls through to TailMBB. |
| IfFalseMBB->addSuccessor(TailMBB); |
| |
| // %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ] |
| BuildMI(*TailMBB, TailMBB->begin(), DL, TII.get(RISCV::PHI), |
| MI.getOperand(0).getReg()) |
| .addReg(MI.getOperand(4).getReg()) |
| .addMBB(HeadMBB) |
| .addReg(MI.getOperand(5).getReg()) |
| .addMBB(IfFalseMBB); |
| |
| MI.eraseFromParent(); // The pseudo instruction is gone now. |
| return TailMBB; |
| } |
| |
| // Calling Convention Implementation. |
| // The expectations for frontend ABI lowering vary from target to target. |
| // Ideally, an LLVM frontend would be able to avoid worrying about many ABI |
| // details, but this is a longer term goal. For now, we simply try to keep the |
| // role of the frontend as simple and well-defined as possible. The rules can |
| // be summarised as: |
| // * Never split up large scalar arguments. We handle them here. |
| // * If a hardfloat calling convention is being used, and the struct may be |
| // passed in a pair of registers (fp+fp, int+fp), and both registers are |
| // available, then pass as two separate arguments. If either the GPRs or FPRs |
| // are exhausted, then pass according to the rule below. |
| // * If a struct could never be passed in registers or directly in a stack |
| // slot (as it is larger than 2*XLEN and the floating point rules don't |
| // apply), then pass it using a pointer with the byval attribute. |
| // * If a struct is less than 2*XLEN, then coerce to either a two-element |
| // word-sized array or a 2*XLEN scalar (depending on alignment). |
| // * The frontend can determine whether a struct is returned by reference or |
| // not based on its size and fields. If it will be returned by reference, the |
| // frontend must modify the prototype so a pointer with the sret annotation is |
| // passed as the first argument. This is not necessary for large scalar |
| // returns. |
| // * Struct return values and varargs should be coerced to structs containing |
| // register-size fields in the same situations they would be for fixed |
| // arguments. |
| |
| static const MCPhysReg ArgGPRs[] = { |
| RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, |
| RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17 |
| }; |
| |
| // Pass a 2*XLEN argument that has been split into two XLEN values through |
| // registers or the stack as necessary. |
| static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, |
| ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, |
| MVT ValVT2, MVT LocVT2, |
| ISD::ArgFlagsTy ArgFlags2) { |
| unsigned XLenInBytes = XLen / 8; |
| if (unsigned Reg = State.AllocateReg(ArgGPRs)) { |
| // At least one half can be passed via register. |
| State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, |
| VA1.getLocVT(), CCValAssign::Full)); |
| } else { |
| // Both halves must be passed on the stack, with proper alignment. |
| unsigned StackAlign = std::max(XLenInBytes, ArgFlags1.getOrigAlign()); |
| State.addLoc( |
| CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), |
| State.AllocateStack(XLenInBytes, StackAlign), |
| VA1.getLocVT(), CCValAssign::Full)); |
| State.addLoc(CCValAssign::getMem( |
| ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2, |
| CCValAssign::Full)); |
| return false; |
| } |
| |
| if (unsigned Reg = State.AllocateReg(ArgGPRs)) { |
| // The second half can also be passed via register. |
| State.addLoc( |
| CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full)); |
| } else { |
| // The second half is passed via the stack, without additional alignment. |
| State.addLoc(CCValAssign::getMem( |
| ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2, |
| CCValAssign::Full)); |
| } |
| |
| return false; |
| } |
| |
| // Implements the RISC-V calling convention. Returns true upon failure. |
| static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT, |
| CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, |
| CCState &State, bool IsFixed, bool IsRet) { |
| unsigned XLen = DL.getLargestLegalIntTypeSizeInBits(); |
| assert(XLen == 32 || XLen == 64); |
| MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64; |
| assert(ValVT == XLenVT && "Unexpected ValVT"); |
| assert(LocVT == XLenVT && "Unexpected LocVT"); |
| assert(IsFixed && "Vararg support not yet implemented"); |
| |
| // Any return value split in to more than two values can't be returned |
| // directly. |
| if (IsRet && ValNo > 1) |
| return true; |
| |
| SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs(); |
| SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags = |
| State.getPendingArgFlags(); |
| |
| assert(PendingLocs.size() == PendingArgFlags.size() && |
| "PendingLocs and PendingArgFlags out of sync"); |
| |
| // Split arguments might be passed indirectly, so keep track of the pending |
| // values. |
| if (ArgFlags.isSplit() || !PendingLocs.empty()) { |
| LocVT = XLenVT; |
| LocInfo = CCValAssign::Indirect; |
| PendingLocs.push_back( |
| CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); |
| PendingArgFlags.push_back(ArgFlags); |
| if (!ArgFlags.isSplitEnd()) { |
| return false; |
| } |
| } |
| |
| // If the split argument only had two elements, it should be passed directly |
| // in registers or on the stack. |
| if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) { |
| assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()"); |
| // Apply the normal calling convention rules to the first half of the |
| // split argument. |
| CCValAssign VA = PendingLocs[0]; |
| ISD::ArgFlagsTy AF = PendingArgFlags[0]; |
| PendingLocs.clear(); |
| PendingArgFlags.clear(); |
| return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT, |
| ArgFlags); |
| } |
| |
| // Allocate to a register if possible, or else a stack slot. |
| unsigned Reg = State.AllocateReg(ArgGPRs); |
| unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, XLen / 8); |
| |
| // If we reach this point and PendingLocs is non-empty, we must be at the |
| // end of a split argument that must be passed indirectly. |
| if (!PendingLocs.empty()) { |
| assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()"); |
| assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()"); |
| |
| for (auto &It : PendingLocs) { |
| if (Reg) |
| It.convertToReg(Reg); |
| else |
| It.convertToMem(StackOffset); |
| State.addLoc(It); |
| } |
| PendingLocs.clear(); |
| PendingArgFlags.clear(); |
| return false; |
| } |
| |
| assert(LocVT == XLenVT && "Expected an XLenVT at this stage"); |
| |
| if (Reg) { |
| State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
| } else { |
| State.addLoc( |
| CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); |
| } |
| return false; |
| } |
| |
| void RISCVTargetLowering::analyzeInputArgs( |
| MachineFunction &MF, CCState &CCInfo, |
| const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const { |
| unsigned NumArgs = Ins.size(); |
| |
| for (unsigned i = 0; i != NumArgs; ++i) { |
| MVT ArgVT = Ins[i].VT; |
| ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; |
| |
| if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full, |
| ArgFlags, CCInfo, /*IsRet=*/true, IsRet)) { |
| DEBUG(dbgs() << "InputArg #" << i << " has unhandled type " |
| << EVT(ArgVT).getEVTString() << '\n'); |
| llvm_unreachable(nullptr); |
| } |
| } |
| } |
| |
| void RISCVTargetLowering::analyzeOutputArgs( |
| MachineFunction &MF, CCState &CCInfo, |
| const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet) const { |
| unsigned NumArgs = Outs.size(); |
| |
| for (unsigned i = 0; i != NumArgs; i++) { |
| MVT ArgVT = Outs[i].VT; |
| ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; |
| |
| if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full, |
| ArgFlags, CCInfo, Outs[i].IsFixed, IsRet)) { |
| DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type " |
| << EVT(ArgVT).getEVTString() << "\n"); |
| llvm_unreachable(nullptr); |
| } |
| } |
| } |
| |
| // The caller is responsible for loading the full value if the argument is |
| // passed with CCValAssign::Indirect. |
| static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, |
| const CCValAssign &VA, const SDLoc &DL) { |
| MachineFunction &MF = DAG.getMachineFunction(); |
| MachineRegisterInfo &RegInfo = MF.getRegInfo(); |
| EVT LocVT = VA.getLocVT(); |
| SDValue Val; |
| |
| unsigned VReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); |
| RegInfo.addLiveIn(VA.getLocReg(), VReg); |
| Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT); |
| |
| switch (VA.getLocInfo()) { |
| default: |
| llvm_unreachable("Unexpected CCValAssign::LocInfo"); |
| case CCValAssign::Full: |
| case CCValAssign::Indirect: |
| return Val; |
| } |
| } |
| |
| // The caller is responsible for loading the full value if the argument is |
| // passed with CCValAssign::Indirect. |
| static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, |
| const CCValAssign &VA, const SDLoc &DL) { |
| MachineFunction &MF = DAG.getMachineFunction(); |
| MachineFrameInfo &MFI = MF.getFrameInfo(); |
| EVT LocVT = VA.getLocVT(); |
| EVT ValVT = VA.getValVT(); |
| EVT PtrVT = MVT::getIntegerVT(DAG.getDataLayout().getPointerSizeInBits(0)); |
| int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8, |
| VA.getLocMemOffset(), /*Immutable=*/true); |
| SDValue FIN = DAG.getFrameIndex(FI, PtrVT); |
| SDValue Val; |
| |
| ISD::LoadExtType ExtType; |
| switch (VA.getLocInfo()) { |
| default: |
| llvm_unreachable("Unexpected CCValAssign::LocInfo"); |
| case CCValAssign::Full: |
| case CCValAssign::Indirect: |
| ExtType = ISD::NON_EXTLOAD; |
| break; |
| } |
| Val = DAG.getExtLoad( |
| ExtType, DL, LocVT, Chain, FIN, |
| MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), ValVT); |
| return Val; |
| } |
| |
| // Transform physical registers into virtual registers. |
| SDValue RISCVTargetLowering::LowerFormalArguments( |
| SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, |
| const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, |
| SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { |
| |
| switch (CallConv) { |
| default: |
| report_fatal_error("Unsupported calling convention"); |
| case CallingConv::C: |
| case CallingConv::Fast: |
| break; |
| } |
| |
| MachineFunction &MF = DAG.getMachineFunction(); |
| EVT PtrVT = getPointerTy(DAG.getDataLayout()); |
| |
| if (IsVarArg) |
| report_fatal_error("VarArg not supported"); |
| |
| // Assign locations to all of the incoming arguments. |
| SmallVector<CCValAssign, 16> ArgLocs; |
| CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); |
| analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false); |
| |
| for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { |
| CCValAssign &VA = ArgLocs[i]; |
| assert(VA.getLocVT() == Subtarget.getXLenVT() && "Unhandled argument type"); |
| SDValue ArgValue; |
| if (VA.isRegLoc()) |
| ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL); |
| else |
| ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL); |
| |
| if (VA.getLocInfo() == CCValAssign::Indirect) { |
| // If the original argument was split and passed by reference (e.g. i128 |
| // on RV32), we need to load all parts of it here (using the same |
| // address). |
| InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, |
| MachinePointerInfo())); |
| unsigned ArgIndex = Ins[i].OrigArgIndex; |
| assert(Ins[i].PartOffset == 0); |
| while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) { |
| CCValAssign &PartVA = ArgLocs[i + 1]; |
| unsigned PartOffset = Ins[i + 1].PartOffset; |
| SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue, |
| DAG.getIntPtrConstant(PartOffset, DL)); |
| InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address, |
| MachinePointerInfo())); |
| ++i; |
| } |
| continue; |
| } |
| InVals.push_back(ArgValue); |
| } |
| return Chain; |
| } |
| |
| // Lower a call to a callseq_start + CALL + callseq_end chain, and add input |
| // and output parameter nodes. |
| SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, |
| SmallVectorImpl<SDValue> &InVals) const { |
| SelectionDAG &DAG = CLI.DAG; |
| SDLoc &DL = CLI.DL; |
| SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; |
| SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; |
| SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; |
| SDValue Chain = CLI.Chain; |
| SDValue Callee = CLI.Callee; |
| CLI.IsTailCall = false; |
| CallingConv::ID CallConv = CLI.CallConv; |
| bool IsVarArg = CLI.IsVarArg; |
| EVT PtrVT = getPointerTy(DAG.getDataLayout()); |
| MVT XLenVT = Subtarget.getXLenVT(); |
| |
| if (IsVarArg) { |
| report_fatal_error("LowerCall with varargs not implemented"); |
| } |
| |
| MachineFunction &MF = DAG.getMachineFunction(); |
| |
| // Analyze the operands of the call, assigning locations to each operand. |
| SmallVector<CCValAssign, 16> ArgLocs; |
| CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); |
| analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false); |
| |
| // Get a count of how many bytes are to be pushed on the stack. |
| unsigned NumBytes = ArgCCInfo.getNextStackOffset(); |
| |
| // Create local copies for byval args |
| SmallVector<SDValue, 8> ByValArgs; |
| for (unsigned i = 0, e = Outs.size(); i != e; ++i) { |
| ISD::ArgFlagsTy Flags = Outs[i].Flags; |
| if (!Flags.isByVal()) |
| continue; |
| |
| SDValue Arg = OutVals[i]; |
| unsigned Size = Flags.getByValSize(); |
| unsigned Align = Flags.getByValAlign(); |
| |
| int FI = MF.getFrameInfo().CreateStackObject(Size, Align, /*isSS=*/false); |
| SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); |
| SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT); |
| |
| Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align, |
| /*IsVolatile=*/false, |
| /*AlwaysInline=*/false, |
| /*isTailCall=*/false, MachinePointerInfo(), |
| MachinePointerInfo()); |
| ByValArgs.push_back(FIPtr); |
| } |
| |
| Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL); |
| |
| // Copy argument values to their designated locations. |
| SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; |
| SmallVector<SDValue, 8> MemOpChains; |
| SDValue StackPtr; |
| for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) { |
| CCValAssign &VA = ArgLocs[i]; |
| SDValue ArgValue = OutVals[i]; |
| ISD::ArgFlagsTy Flags = Outs[i].Flags; |
| |
| // Promote the value if needed. |
| // For now, only handle fully promoted and indirect arguments. |
| switch (VA.getLocInfo()) { |
| case CCValAssign::Full: |
| break; |
| case CCValAssign::Indirect: { |
| // Store the argument in a stack slot and pass its address. |
| SDValue SpillSlot = DAG.CreateStackTemporary(Outs[i].ArgVT); |
| int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); |
| MemOpChains.push_back( |
| DAG.getStore(Chain, DL, ArgValue, SpillSlot, |
| MachinePointerInfo::getFixedStack(MF, FI))); |
| // If the original argument was split (e.g. i128), we need |
| // to store all parts of it here (and pass just one address). |
| unsigned ArgIndex = Outs[i].OrigArgIndex; |
| assert(Outs[i].PartOffset == 0); |
| while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) { |
| SDValue PartValue = OutVals[i + 1]; |
| unsigned PartOffset = Outs[i + 1].PartOffset; |
| SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot, |
| DAG.getIntPtrConstant(PartOffset, DL)); |
| MemOpChains.push_back( |
| DAG.getStore(Chain, DL, PartValue, Address, |
| MachinePointerInfo::getFixedStack(MF, FI))); |
| ++i; |
| } |
| ArgValue = SpillSlot; |
| break; |
| } |
| default: |
| llvm_unreachable("Unknown loc info!"); |
| } |
| |
| // Use local copy if it is a byval arg. |
| if (Flags.isByVal()) |
| ArgValue = ByValArgs[j++]; |
| |
| if (VA.isRegLoc()) { |
| // Queue up the argument copies and emit them at the end. |
| RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); |
| } else { |
| assert(VA.isMemLoc() && "Argument not register or memory"); |
| |
| // Work out the address of the stack slot. |
| if (!StackPtr.getNode()) |
| StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT); |
| SDValue Address = |
| DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, |
| DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); |
| |
| // Emit the store. |
| MemOpChains.push_back( |
| DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo())); |
| } |
| } |
| |
| // Join the stores, which are independent of one another. |
| if (!MemOpChains.empty()) |
| Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); |
| |
| SDValue Glue; |
| |
| // Build a sequence of copy-to-reg nodes, chained and glued together. |
| for (auto &Reg : RegsToPass) { |
| Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue); |
| Glue = Chain.getValue(1); |
| } |
| |
| if (isa<GlobalAddressSDNode>(Callee)) { |
| Callee = lowerGlobalAddress(Callee, DAG); |
| } else if (isa<ExternalSymbolSDNode>(Callee)) { |
| Callee = lowerExternalSymbol(Callee, DAG); |
| } |
| |
| // The first call operand is the chain and the second is the target address. |
| SmallVector<SDValue, 8> Ops; |
| Ops.push_back(Chain); |
| Ops.push_back(Callee); |
| |
| // Add argument registers to the end of the list so that they are |
| // known live into the call. |
| for (auto &Reg : RegsToPass) |
| Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); |
| |
| // Add a register mask operand representing the call-preserved registers. |
| const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); |
| const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); |
| assert(Mask && "Missing call preserved mask for calling convention"); |
| Ops.push_back(DAG.getRegisterMask(Mask)); |
| |
| // Glue the call to the argument copies, if any. |
| if (Glue.getNode()) |
| Ops.push_back(Glue); |
| |
| // Emit the call. |
| SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); |
| Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops); |
| Glue = Chain.getValue(1); |
| |
| // Mark the end of the call, which is glued to the call itself. |
| Chain = DAG.getCALLSEQ_END(Chain, |
| DAG.getConstant(NumBytes, DL, PtrVT, true), |
| DAG.getConstant(0, DL, PtrVT, true), |
| Glue, DL); |
| Glue = Chain.getValue(1); |
| |
| // Assign locations to each value returned by this call. |
| SmallVector<CCValAssign, 16> RVLocs; |
| CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); |
| analyzeInputArgs(MF, RetCCInfo, Ins, /*IsRet=*/true); |
| |
| // Copy all of the result registers out of their specified physreg. |
| for (auto &VA : RVLocs) { |
| // Copy the value out, gluing the copy to the end of the call sequence. |
| SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), |
| VA.getLocVT(), Glue); |
| Chain = RetValue.getValue(1); |
| Glue = RetValue.getValue(2); |
| |
| assert(VA.getLocInfo() == CCValAssign::Full && "Unknown loc info!"); |
| InVals.push_back(RetValue); |
| } |
| |
| return Chain; |
| } |
| |
| bool RISCVTargetLowering::CanLowerReturn( |
| CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, |
| const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { |
| SmallVector<CCValAssign, 16> RVLocs; |
| CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); |
| for (unsigned i = 0, e = Outs.size(); i != e; ++i) { |
| MVT VT = Outs[i].VT; |
| ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; |
| if (CC_RISCV(MF.getDataLayout(), i, VT, VT, CCValAssign::Full, ArgFlags, |
| CCInfo, /*IsFixed=*/true, /*IsRet=*/true)) |
| return false; |
| } |
| return true; |
| } |
| |
| SDValue |
| RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, |
| bool IsVarArg, |
| const SmallVectorImpl<ISD::OutputArg> &Outs, |
| const SmallVectorImpl<SDValue> &OutVals, |
| const SDLoc &DL, SelectionDAG &DAG) const { |
| if (IsVarArg) { |
| report_fatal_error("VarArg not supported"); |
| } |
| |
| // Stores the assignment of the return value to a location. |
| SmallVector<CCValAssign, 16> RVLocs; |
| |
| // Info about the registers and stack slot. |
| CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, |
| *DAG.getContext()); |
| |
| analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true); |
| |
| SDValue Flag; |
| SmallVector<SDValue, 4> RetOps(1, Chain); |
| |
| // Copy the result values into the output registers. |
| for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) { |
| SDValue Val = OutVals[i]; |
| CCValAssign &VA = RVLocs[i]; |
| assert(VA.isRegLoc() && "Can only return in registers!"); |
| assert(VA.getLocInfo() == CCValAssign::Full && |
| "Unexpected CCValAssign::LocInfo"); |
| |
| Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); |
| |
| // Guarantee that all emitted copies are stuck together. |
| Flag = Chain.getValue(1); |
| RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); |
| } |
| |
| RetOps[0] = Chain; // Update chain. |
| |
| // Add the flag if we have it. |
| if (Flag.getNode()) { |
| RetOps.push_back(Flag); |
| } |
| |
| return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps); |
| } |
| |
| const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { |
| switch ((RISCVISD::NodeType)Opcode) { |
| case RISCVISD::FIRST_NUMBER: |
| break; |
| case RISCVISD::RET_FLAG: |
| return "RISCVISD::RET_FLAG"; |
| case RISCVISD::CALL: |
| return "RISCVISD::CALL"; |
| case RISCVISD::SELECT_CC: |
| return "RISCVISD::SELECT_CC"; |
| } |
| return nullptr; |
| } |