| From 23091f7d504afde4bba3fc885718a1633746e063 Mon Sep 17 00:00:00 2001 |
| From: Florian Hahn <flo@fhahn.com> |
| Date: Mon, 31 Jan 2022 18:20:46 +0000 |
| Subject: [PATCH] [AArch64] Bail out for float operands in SetCC optimization. |
| |
| The optimization added in D118139 causes a crash on the added test case |
| while trying to zero extend an vector of floats. |
| |
| Fix the crash by bailing out for floating point operands. |
| |
| Reviewed By: DavidTruby |
| |
| Differential Revision: https://reviews.llvm.org/D118615 |
| --- |
| .../Target/AArch64/AArch64ISelLowering.cpp | 10 ++++-- |
| llvm/test/CodeGen/AArch64/select_cc.ll | 31 +++++++++++++++++++ |
| 2 files changed, 39 insertions(+), 2 deletions(-) |
| |
| diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
| index 5bcf25a87348..944145dd7ad6 100644 |
| --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
| +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
| @@ -15422,6 +15422,12 @@ performSignExtendSetCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, |
| N->getOperand(0)->getOpcode() == ISD::SETCC); |
| const SDValue SetCC = N->getOperand(0); |
| |
| + const SDValue CCOp0 = SetCC.getOperand(0); |
| + const SDValue CCOp1 = SetCC.getOperand(1); |
| + if (!CCOp0->getValueType(0).isInteger() || |
| + !CCOp1->getValueType(0).isInteger()) |
| + return SDValue(); |
| + |
| ISD::CondCode Code = |
| cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get(); |
| |
| @@ -15431,9 +15437,9 @@ performSignExtendSetCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, |
| if (isCheapToExtend(SetCC.getOperand(0)) && |
| isCheapToExtend(SetCC.getOperand(1))) { |
| const SDValue Ext1 = |
| - DAG.getNode(ExtType, SDLoc(N), N->getValueType(0), SetCC.getOperand(0)); |
| + DAG.getNode(ExtType, SDLoc(N), N->getValueType(0), CCOp0); |
| const SDValue Ext2 = |
| - DAG.getNode(ExtType, SDLoc(N), N->getValueType(0), SetCC.getOperand(1)); |
| + DAG.getNode(ExtType, SDLoc(N), N->getValueType(0), CCOp1); |
| |
| return DAG.getSetCC( |
| SDLoc(SetCC), N->getValueType(0), Ext1, Ext2, |
| diff --git a/llvm/test/CodeGen/AArch64/select_cc.ll b/llvm/test/CodeGen/AArch64/select_cc.ll |
| index 785e6b800ed7..1444eecb946c 100644 |
| --- a/llvm/test/CodeGen/AArch64/select_cc.ll |
| +++ b/llvm/test/CodeGen/AArch64/select_cc.ll |
| @@ -52,3 +52,34 @@ entry: |
| %sel = select i1 %cc, i64 0, i64 4 |
| ret i64 %sel |
| } |
| + |
| +define <2 x double> @select_olt_load_cmp(<2 x double> %a, <2 x float>* %src) { |
| +; CHECK-LABEL: select_olt_load_cmp: |
| +; CHECK: // %bb.0: // %entry |
| +; CHECK-NEXT: movi d1, #0000000000000000 |
| +; CHECK-NEXT: ldr d2, [x0] |
| +; CHECK-NEXT: fcmgt v1.2s, v2.2s, v1.2s |
| +; CHECK-NEXT: sshll v1.2d, v1.2s, #0 |
| +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b |
| +; CHECK-NEXT: ret |
| +entry: |
| + %l = load <2 x float>, <2 x float>* %src, align 4 |
| + %cmp = fcmp olt <2 x float> zeroinitializer, %l |
| + %sel = select <2 x i1> %cmp, <2 x double> %a, <2 x double> zeroinitializer |
| + ret <2 x double> %sel |
| +} |
| + |
| +define <4 x i32> @select_icmp_sgt(<4 x i32> %a, <4 x i8> %b) { |
| +; CHECK-LABEL: select_icmp_sgt: |
| +; CHECK: // %bb.0: // %entry |
| +; CHECK-NEXT: shl v1.4h, v1.4h, #8 |
| +; CHECK-NEXT: sshr v1.4h, v1.4h, #8 |
| +; CHECK-NEXT: cmgt v1.4h, v1.4h, #0 |
| +; CHECK-NEXT: sshll v1.4s, v1.4h, #0 |
| +; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b |
| +; CHECK-NEXT: ret |
| +entry: |
| + %cmp = icmp sgt <4 x i8> %b, zeroinitializer |
| + %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %a |
| + ret <4 x i32> %sel |
| +} |
| -- |
| 2.35.1.473.g83b2b277ed-goog |
| |