commit 3fe67141c703755557b352f9335b8b1a7662f6b4
author Jatin Bhateja <jbhateja@openjdk.org> Tue Jul 09 15:42:44 2019 -0700
committer Jatin Bhateja <jbhateja@openjdk.org> Tue Jul 09 15:42:44 2019 -0700
tree 05f96bc594aab96fa0146bc3a4374da8a2d7a191
parent 75d87ff2543ba407ca9d338b13e09cbdc382fb83

8227222: vmTestbase/jit/FloatingPoint/gen_math/Loops04/Loops04.java failed XMM register should be 0-15

Reviewed-by: thartmann, vlivanov, ctornqvi, bsrbnd

src/hotspot/cpu/x86/x86_64.ad

diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad
index 92e1fe3..b0858e2 100644
--- a/src/hotspot/cpu/x86/x86_64.ad
+++ b/src/hotspot/cpu/x86/x86_64.ad
@@ -5543,7 +5543,7 @@
   ins_pipe( pipe_slow );
 %}
 
-instruct maxF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{
+instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
   predicate(UseAVX > 0 && n->is_reduction());
   match(Set dst (MaxF a b));
   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
@@ -5579,7 +5579,7 @@
   ins_pipe( pipe_slow );
 %}
 
-instruct maxD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{
+instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
   predicate(UseAVX > 0 && n->is_reduction());
   match(Set dst (MaxD a b));
   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
@@ -5615,7 +5615,7 @@
   ins_pipe( pipe_slow );
 %}
 
-instruct minF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{
+instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
   predicate(UseAVX > 0 && n->is_reduction());
   match(Set dst (MinF a b));
   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
@@ -5651,7 +5651,7 @@
   ins_pipe( pipe_slow );
 %}
 
-instruct minD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{
+instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
   predicate(UseAVX > 0 && n->is_reduction());
   match(Set dst (MinD a b));
   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);