| /* |
| * Copyright (c) 2011 Intel Corporation. All Rights Reserved. |
| * Copyright (c) Imagination Technologies Limited, UK |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation the rights to use, copy, modify, merge, publish, |
| * distribute, sub license, and/or sell copies of the Software, and to |
| * permit persons to whom the Software is furnished to do so, subject to |
| * the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial portions |
| * of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
| * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| |
| /****************************************************************************** |
| |
| @File msvdx_rendec_vc1_reg_io2.h |
| |
| @Title MSVDX Offsets |
| |
| @Platform </b>\n |
| |
| @Description </b>\n This file contains the MSVDX_RENDEC_VC1_REG_IO2_H |
| Defintions. |
| |
| ******************************************************************************/ |
| #if !defined (__MSVDX_RENDEC_VC1_REG_IO2_H__) |
| #define __MSVDX_RENDEC_VC1_REG_IO2_H__ |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| |
| #define VC1_RENDEC_CMD_VC1GEN00_OFFSET (0x0000) |
| |
| // VC1_RENDEC_CMD VC1GEN00 ADDRESS |
| #define VC1_RENDEC_CMD_VC1GEN00_ADDRESS_MASK (0x00FFFFFF) |
| #define VC1_RENDEC_CMD_VC1GEN00_ADDRESS_LSBMASK (0x00FFFFFF) |
| #define VC1_RENDEC_CMD_VC1GEN00_ADDRESS_SHIFT (0) |
| |
| #define VC1_RENDEC_CMD_VC1SEQUENCE00_OFFSET (0x0004) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE00 PICTURE_HEIGHT |
| #define VC1_RENDEC_CMD_VC1SEQUENCE00_PICTURE_HEIGHT_MASK (0x00FFF000) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE00_PICTURE_HEIGHT_LSBMASK (0x00000FFF) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE00_PICTURE_HEIGHT_SHIFT (12) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE00 PICTURE_WIDTH |
| #define VC1_RENDEC_CMD_VC1SEQUENCE00_PICTURE_WIDTH_MASK (0x00000FFF) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE00_PICTURE_WIDTH_LSBMASK (0x00000FFF) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE00_PICTURE_WIDTH_SHIFT (0) |
| |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_OFFSET (0x0008) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 CHROMA_INTERLEAVED |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CHROMA_INTERLEAVED_MASK (0x08000000) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CHROMA_INTERLEAVED_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CHROMA_INTERLEAVED_SHIFT (27) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 ROW_STRIDE |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_ROW_STRIDE_MASK (0x07000000) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_ROW_STRIDE_LSBMASK (0x00000007) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_ROW_STRIDE_SHIFT (24) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 CODEC_PROFILE |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CODEC_PROFILE_MASK (0x00300000) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CODEC_PROFILE_LSBMASK (0x00000003) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CODEC_PROFILE_SHIFT (20) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 CODEC_MODE |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CODEC_MODE_MASK (0x00070000) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CODEC_MODE_LSBMASK (0x00000007) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CODEC_MODE_SHIFT (16) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 ASYNC_MODE |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_ASYNC_MODE_MASK (0x00006000) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_ASYNC_MODE_LSBMASK (0x00000003) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_ASYNC_MODE_SHIFT (13) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 CHROMA_FORMAT |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CHROMA_FORMAT_MASK (0x00001000) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CHROMA_FORMAT_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_CHROMA_FORMAT_SHIFT (12) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 INTERLACED |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_INTERLACED_MASK (0x00000800) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_INTERLACED_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_INTERLACED_SHIFT (11) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 VC1_OVERLAP |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_VC1_OVERLAP_MASK (0x00000400) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_VC1_OVERLAP_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_VC1_OVERLAP_SHIFT (10) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 PIC_CONDOVER |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_PIC_CONDOVER_MASK (0x00000300) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_PIC_CONDOVER_LSBMASK (0x00000003) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_PIC_CONDOVER_SHIFT (8) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 SEQ01_RESERVED |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_SEQ01_RESERVED_MASK (0x000000E0) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_SEQ01_RESERVED_LSBMASK (0x00000007) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_SEQ01_RESERVED_SHIFT (5) |
| |
| // VC1_RENDEC_CMD VC1SEQUENCE01 PIC_QUANT |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_PIC_QUANT_MASK (0x0000001F) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_PIC_QUANT_LSBMASK (0x0000001F) |
| #define VC1_RENDEC_CMD_VC1SEQUENCE01_PIC_QUANT_SHIFT (0) |
| |
| #define VC1_RENDEC_CMD_VC1SLICE00_OFFSET (0x000C) |
| |
| // VC1_RENDEC_CMD VC1SLICE00 CONFIG_REF_OFFSET |
| #define VC1_RENDEC_CMD_VC1SLICE00_CONFIG_REF_OFFSET_MASK (0x00FFF000) |
| #define VC1_RENDEC_CMD_VC1SLICE00_CONFIG_REF_OFFSET_LSBMASK (0x00000FFF) |
| #define VC1_RENDEC_CMD_VC1SLICE00_CONFIG_REF_OFFSET_SHIFT (12) |
| |
| // VC1_RENDEC_CMD VC1SLICE00 CONFIG_ROW_OFFSET |
| #define VC1_RENDEC_CMD_VC1SLICE00_CONFIG_ROW_OFFSET_MASK (0x00000FFF) |
| #define VC1_RENDEC_CMD_VC1SLICE00_CONFIG_ROW_OFFSET_LSBMASK (0x00000FFF) |
| #define VC1_RENDEC_CMD_VC1SLICE00_CONFIG_ROW_OFFSET_SHIFT (0) |
| |
| #define VC1_RENDEC_CMD_VC1SLICE01_OFFSET (0x0010) |
| |
| // VC1_RENDEC_CMD VC1SLICE01 VC1_LUMSHIFT2 |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSHIFT2_MASK (0x00FC0000) |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSHIFT2_LSBMASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSHIFT2_SHIFT (18) |
| |
| // VC1_RENDEC_CMD VC1SLICE01 VC1_LUMSCALE2 |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSCALE2_MASK (0x0003F000) |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSCALE2_LSBMASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSCALE2_SHIFT (12) |
| |
| // VC1_RENDEC_CMD VC1SLICE01 VC1_LUMSHIFT1 |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSHIFT1_MASK (0x00000FC0) |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSHIFT1_LSBMASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSHIFT1_SHIFT (6) |
| |
| // VC1_RENDEC_CMD VC1SLICE01 VC1_LUMSCALE1 |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSCALE1_MASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSCALE1_LSBMASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE01_VC1_LUMSCALE1_SHIFT (0) |
| |
| #define VC1_RENDEC_CMD_VC1SLICE02_OFFSET (0x0014) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 VC1_PREV_INT_COMP |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_PREV_INT_COMP_MASK (0x0C000000) |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_PREV_INT_COMP_LSBMASK (0x00000003) |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_PREV_INT_COMP_SHIFT (26) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 VC1_BACK_INT_COMP |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_BACK_INT_COMP_MASK (0x03000000) |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_BACK_INT_COMP_LSBMASK (0x00000003) |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_BACK_INT_COMP_SHIFT (24) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 RND_CTRL_BIT |
| #define VC1_RENDEC_CMD_VC1SLICE02_RND_CTRL_BIT_MASK (0x00400000) |
| #define VC1_RENDEC_CMD_VC1SLICE02_RND_CTRL_BIT_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SLICE02_RND_CTRL_BIT_SHIFT (22) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 MODE_CONFIG |
| #define VC1_RENDEC_CMD_VC1SLICE02_MODE_CONFIG_MASK (0x003E0000) |
| #define VC1_RENDEC_CMD_VC1SLICE02_MODE_CONFIG_LSBMASK (0x0000001F) |
| #define VC1_RENDEC_CMD_VC1SLICE02_MODE_CONFIG_SHIFT (17) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 SUBPEL_FILTER_MODE |
| #define VC1_RENDEC_CMD_VC1SLICE02_SUBPEL_FILTER_MODE_MASK (0x00010000) |
| #define VC1_RENDEC_CMD_VC1SLICE02_SUBPEL_FILTER_MODE_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SLICE02_SUBPEL_FILTER_MODE_SHIFT (16) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 VC1_FASTUVMC |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_FASTUVMC_MASK (0x00008000) |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_FASTUVMC_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_FASTUVMC_SHIFT (15) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 VC1_LOOPFILTER |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_LOOPFILTER_MASK (0x00004000) |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_LOOPFILTER_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SLICE02_VC1_LOOPFILTER_SHIFT (14) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 SLICE02_RESERVED |
| #define VC1_RENDEC_CMD_VC1SLICE02_SLICE02_RESERVED_MASK (0x00003FF0) |
| #define VC1_RENDEC_CMD_VC1SLICE02_SLICE02_RESERVED_LSBMASK (0x000003FF) |
| #define VC1_RENDEC_CMD_VC1SLICE02_SLICE02_RESERVED_SHIFT (4) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 SLICE_FIELD_TYPE |
| #define VC1_RENDEC_CMD_VC1SLICE02_SLICE_FIELD_TYPE_MASK (0x0000000C) |
| #define VC1_RENDEC_CMD_VC1SLICE02_SLICE_FIELD_TYPE_LSBMASK (0x00000003) |
| #define VC1_RENDEC_CMD_VC1SLICE02_SLICE_FIELD_TYPE_SHIFT (2) |
| |
| // VC1_RENDEC_CMD VC1SLICE02 SLICE_CODE_TYPE |
| #define VC1_RENDEC_CMD_VC1SLICE02_SLICE_CODE_TYPE_MASK (0x00000003) |
| #define VC1_RENDEC_CMD_VC1SLICE02_SLICE_CODE_TYPE_LSBMASK (0x00000003) |
| #define VC1_RENDEC_CMD_VC1SLICE02_SLICE_CODE_TYPE_SHIFT (0) |
| |
| #define VC1_RENDEC_CMD_VC1SLICE03_OFFSET (0x0018) |
| |
| // VC1_RENDEC_CMD VC1SLICE03 RANGE_MAPUV_FLAG |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPUV_FLAG_MASK (0x00000080) |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPUV_FLAG_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPUV_FLAG_SHIFT (7) |
| |
| // VC1_RENDEC_CMD VC1SLICE03 RANGE_MAPUV |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPUV_MASK (0x00000070) |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPUV_LSBMASK (0x00000007) |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPUV_SHIFT (4) |
| |
| // VC1_RENDEC_CMD VC1SLICE03 RANGE_MAPY_FLAG |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPY_FLAG_MASK (0x00000008) |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPY_FLAG_LSBMASK (0x00000001) |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPY_FLAG_SHIFT (3) |
| |
| // VC1_RENDEC_CMD VC1SLICE03 RANGE_MAPY |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPY_MASK (0x00000007) |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPY_LSBMASK (0x00000007) |
| #define VC1_RENDEC_CMD_VC1SLICE03_RANGE_MAPY_SHIFT (0) |
| |
| #define VC1_RENDEC_CMD_VC1SLICE04_OFFSET (0x001C) |
| |
| // VC1_RENDEC_CMD VC1SLICE04 VC1_LUMSHIFT_PREV |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSHIFT_PREV_MASK (0x00FC0000) |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSHIFT_PREV_LSBMASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSHIFT_PREV_SHIFT (18) |
| |
| // VC1_RENDEC_CMD VC1SLICE04 VC1_LUMSCALE_PREV |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSCALE_PREV_MASK (0x0003F000) |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSCALE_PREV_LSBMASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSCALE_PREV_SHIFT (12) |
| |
| // VC1_RENDEC_CMD VC1SLICE04 VC1_LUMSHIFT_BACK |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSHIFT_BACK_MASK (0x00000FC0) |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSHIFT_BACK_LSBMASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSHIFT_BACK_SHIFT (6) |
| |
| // VC1_RENDEC_CMD VC1SLICE04 VC1_LUMSCALE_BACK |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSCALE_BACK_MASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSCALE_BACK_LSBMASK (0x0000003F) |
| #define VC1_RENDEC_CMD_VC1SLICE04_VC1_LUMSCALE_BACK_SHIFT (0) |
| |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* __MSVDX_RENDEC_VC1_REG_IO2_H__ */ |
