bootstub: optimizations and cleanup of bootstub
BZ: 98228
Optimizations of bootstub code:
-clean up naming (replacing mrst references to mid where applicable)
-Code size reduction
-increase code efficiency
-change uart functionality to more accurately support on other platforms.
Instead of assuming SPI 0 for non recognized SOCs, will now skip spi/uart
initializations and simply return from print routines
-increase version to 1.3
Change-Id: Id355fa64d53422cb8fa28e4fd5155e0e1b9d0b55
Signed-off-by: Eric Ernst <eric.ernst@intel.com>
Reviewed-on: http://android.intel.com:8080/99552
Reviewed-by: Gao, Bin <bin.gao@intel.com>
Reviewed-by: Chouleur, Sylvain <sylvain.chouleur@intel.com>
Reviewed-by: Noziska, Patrick J <patrick.j.noziska@intel.com>
Reviewed-by: Yang, Fei <fei.yang@intel.com>
Tested-by: Ng, Cheon-woei <cheon-woei.ng@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
diff --git a/bootstub.c b/bootstub.c
index 26c96d2..fb1d765 100644
--- a/bootstub.c
+++ b/bootstub.c
@@ -27,6 +27,8 @@
#define bs_printk(x) { if (! *(int *)SPI_UART_SUPPRESSION) bs_spi_printk(x);}
+extern int no_uart_used;
+
static void *memcpy(void *dest, const void *src, size_t count)
{
char *tmp = dest;
@@ -95,7 +97,7 @@
} else {
bs_printk("Won't relocate initramfs, are you in SLE?\n");
}
- if (mrst_identify_cpu() == MRST_CPU_CHIP_VALLEYVIEW2) {
+ if (mid_identify_cpu() == MID_CPU_CHIP_VALLEYVIEW2) {
nr_entries = get_e820_by_bios(bp->e820_map);
bp->e820_entries = (nr_entries > 0) ? nr_entries : 0;
} else {
@@ -133,33 +135,44 @@
CR_EBX
};
-int mrst_identify_cpu(void)
+int mid_identify_cpu(void)
{
u32 regs[4];
cpuid(1, ®s[CR_EAX], ®s[CR_EBX], ®s[CR_ECX], ®s[CR_EDX]);
- if ((regs[CR_EAX] & CPUID_MASK) == PENWELL_FAMILY)
- return MRST_CPU_CHIP_PENWELL;
- else if ((regs[CR_EAX] & CPUID_MASK) == CLOVERVIEW_FAMILY)
- return MRST_CPU_CHIP_CLOVERVIEW;
- else if ((regs[CR_EAX] & CPUID_MASK) == VALLEYVIEW2_FAMILY)
- return MRST_CPU_CHIP_VALLEYVIEW2;
- return MRST_CPU_CHIP_LINCROFT;
+ switch ( regs[CR_EAX] & CPUID_MASK ) {
+
+ case PENWELL_FAMILY:
+ return MID_CPU_CHIP_PENWELL;
+ case CLOVERVIEW_FAMILY:
+ return MID_CPU_CHIP_CLOVERVIEW;
+ case VALLEYVIEW2_FAMILY:
+ return MID_CPU_CHIP_VALLEYVIEW2;
+ default:
+ return MID_CPU_CHIP_OTHER;
+ }
}
static void setup_spi(void)
{
if (!(*(int *)SPI_TYPE)) {
- if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL) {
- *(int *)SPI_TYPE = 1;
- bs_printk("Penwell detected ...\n");
- } else if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW) {
- *(int *)SPI_TYPE = 1;
- bs_printk("Cloverview detected ...\n");
- } else {
- *(int *)SPI_TYPE = 1;
- bs_printk("Lincroft detected ...\n");
+ switch ( mid_identify_cpu() ) {
+
+ case MID_CPU_CHIP_PENWELL:
+ *(int *)SPI_TYPE = SPI_1;
+ bs_printk("PNW detected\n");
+ break;
+
+ case MID_CPU_CHIP_CLOVERVIEW:
+ *(int *)SPI_TYPE = SPI_1;
+ bs_printk("CLV detected\n");
+ break;
+
+ case MID_CPU_CHIP_VALLEYVIEW2:
+ case MID_CPU_CHIP_OTHER:
+ default:
+ no_uart_used = 1;
}
}
}
@@ -167,7 +180,7 @@
int bootstub(void)
{
setup_spi();
- bs_printk("Bootstub Version: 1.2 ...\n");
+ bs_printk("Bootstub Version: 1.3 ...\n");
setup_boot_params((struct boot_params *)BOOT_PARAMS_OFFSET,
(struct setup_header *)SETUP_HEADER_OFFSET);
bs_printk("Jump to kernel 32bit entry ...\n");
diff --git a/bootstub.h b/bootstub.h
index b1fc0d5..8db1690 100644
--- a/bootstub.h
+++ b/bootstub.h
@@ -9,16 +9,20 @@
#define CLOVERVIEW_FAMILY 0x30650
#define VALLEYVIEW2_FAMILY 0x30670
-#define MRST_CPU_CHIP_LINCROFT 1
-#define MRST_CPU_CHIP_PENWELL 2
-#define MRST_CPU_CHIP_CLOVERVIEW 3
-#define MRST_CPU_CHIP_VALLEYVIEW2 4
+#define MID_CPU_CHIP_LINCROFT 1
+#define MID_CPU_CHIP_PENWELL 2
+#define MID_CPU_CHIP_CLOVERVIEW 3
+#define MID_CPU_CHIP_VALLEYVIEW2 4
+#define MID_CPU_CHIP_OTHER 0xFF
#define CMDLINE_OFFSET 0x1100000
#define BZIMAGE_SIZE_OFFSET (CMDLINE_OFFSET + CMDLINE_SIZE)
#define INITRD_SIZE_OFFSET (BZIMAGE_SIZE_OFFSET + 4)
#define SPI_UART_SUPPRESSION (INITRD_SIZE_OFFSET + 4)
#define SPI_TYPE (SPI_UART_SUPPRESSION + 4) /*0:SPI0 1:SPI1*/
+#define SPI_0 0
+#define SPI_1 1
+
#define STACK_OFFSET 0x1101000
#define BZIMAGE_OFFSET 0x1102000
@@ -48,7 +52,7 @@
((u64)(base & 0x00ffffff) << 16) | \
((u64)(limit & 0x0000ffff)))
int get_e820_by_bios(void *e820_buf);
-int mrst_identify_cpu(void);
+int mid_identify_cpu(void);
#endif
#endif
diff --git a/spi-uart.c b/spi-uart.c
index 7ff8323..ffe5676 100644
--- a/spi-uart.c
+++ b/spi-uart.c
@@ -22,6 +22,7 @@
#define MRST_SPI_TIMEOUT 0x200000
static int spi_inited = 0;
+int no_uart_used = 0;
static volatile struct mrst_spi_reg *pspi = 0;
static void spi_init()
@@ -30,24 +31,21 @@
u32 *clk_reg, clk_cdiv;
switch (*(int *)SPI_TYPE) {
- case 0:
- if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW)
- pspi = (struct mrst_spi_reg *)CTP_REGBASE_SPI0;
- else
- pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI0;
- break;
- case 1:
- if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW)
+ case SPI_1:
+ if (mid_identify_cpu() == MID_CPU_CHIP_CLOVERVIEW)
pspi = (struct mrst_spi_reg *)CTP_REGBASE_SPI1;
else
pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI1;
break;
+
+ case SPI_0:
default:
- if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW)
+ if (mid_identify_cpu() == MID_CPU_CHIP_CLOVERVIEW)
pspi = (struct mrst_spi_reg *)CTP_REGBASE_SPI0;
else
pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI0;
}
+
/* disable SPI controller first */
pspi->ssienr = 0x0;
@@ -75,6 +73,7 @@
pspi->ssienr |= 0x1;
spi_inited = 1;
+
}
/* set the ratio rate, INT */
@@ -122,6 +121,9 @@
void bs_spi_printk(const char *str)
{
+ if ( no_uart_used )
+ return;
+
if (!spi_inited) {
spi_init();
max3110_write_config();
