Add x87 instructions.
Bug: 276787675
Test: berberis_host_tests/berberis_host_test
Change-Id: I602f8f0d5ca5f5d1988517a429fcdfd787d5268a
diff --git a/assembler/asm_defs.py b/assembler/asm_defs.py
index 3d7da03..2e0e420 100644
--- a/assembler/asm_defs.py
+++ b/assembler/asm_defs.py
@@ -116,7 +116,7 @@
# Operands of this type are NOT passed to assembler
def is_implicit_reg(arg_type):
return arg_type in ('RAX', 'EAX', 'AX', 'AL',
- 'RCX', 'ECX', 'CL', 'ST',
+ 'RCX', 'ECX', 'CL', 'ST', 'ST1',
'RDX', 'EDX', 'DX', 'CC',
'RBX', 'EBX', 'BX', 'SW',
'RDI', 'RSI', 'RSP', 'FLAGS')
diff --git a/assembler/gen_asm_tests_x86.py b/assembler/gen_asm_tests_x86.py
index eb047fd..4f643c9 100644
--- a/assembler/gen_asm_tests_x86.py
+++ b/assembler/gen_asm_tests_x86.py
@@ -218,7 +218,7 @@
FIXED_REGISTER_CLASSES = (
'AL', 'AX', 'EAX', 'RAX',
- 'CL', 'ECX', 'RCX', 'ST',
+ 'CL', 'ECX', 'RCX', 'ST', 'ST1',
'DX', 'EDX', 'RDX', 'CC',
'BX', 'EBX', 'RBX', 'SW',
'EBP', 'RSP', 'FLAGS'
@@ -393,6 +393,12 @@
if insn_name[0:4] == 'LOCK':
# TODO(b/161986409): replace '\n' with ' ' when clang would be fixed.
fixed_name = '%s\n%s' % (insn_name[0:4], insn_name[4:])
+ fixed_name = {
+ # GNU disassembler accepts these instructions, but not Clang assembler.
+ 'FNDISI': '.byte 0xdb, 0xe1',
+ 'FNENI': '.byte 0xdb, 0xe0',
+ 'FNSETPM': '.byte 0xdb, 0xe4',
+ }.get(fixed_name, fixed_name)
if label_present:
print('.p2align 5, 0x90', file=file)
print('0:', file=file)
diff --git a/assembler/instructions/insn_def_x86.json b/assembler/instructions/insn_def_x86.json
index 2950c03..51b86c7 100644
--- a/assembler/instructions/insn_def_x86.json
+++ b/assembler/instructions/insn_def_x86.json
@@ -957,7 +957,34 @@
},
{
"encodings": {
- "FaddFromSt": { "opcodes": [ "Dc", "0" ] }
+ "F2xm1": { "opcodes": [ "D9", "F0" ] },
+ "Fabs": { "opcodes": [ "D9", "E1" ] },
+ "Fchs": { "opcodes": [ "D9", "E0" ] },
+ "Fcos": { "opcodes": [ "D9", "FF" ] },
+ "Frndint": { "opcodes": [ "D9", "FC" ] },
+ "Fscale": { "opcodes": [ "D9", "FD" ] },
+ "Fsin": { "opcodes": [ "D9", "FE" ] },
+ "Fsqrt": { "opcodes": [ "D9", "FA" ] },
+ "Ftst": { "opcodes": [ "D9", "E4" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use_def" }
+ ]
+ },
+ {
+ "encodings": {
+ "FaddFromSt": { "opcodes": [ "DC", "0" ] },
+ "FaddpFromSt": { "opcodes": [ "DE", "0" ] },
+ "FdivFromSt": { "opcodes": [ "DC", "6" ] },
+ "FdivpFromSt": { "opcodes": [ "DE", "6" ] },
+ "FdivrFromSt": { "opcodes": [ "DC", "7" ] },
+ "FdivrpFromSt": { "opcodes": [ "DE", "7" ] },
+ "FmulFromSt": { "opcodes": [ "DC", "1" ] },
+ "FmulpFromSt": { "opcodes": [ "DE", "1" ] },
+ "FsubFromSt": { "opcodes": [ "DC", "4" ] },
+ "FsubpFromSt": { "opcodes": [ "DE", "4" ] },
+ "FsubrFromSt": { "opcodes": [ "DC", "5" ] },
+ "FsubrpFromSt": { "opcodes": [ "DE", "5" ] }
},
"args": [
{ "class": "RegX87", "usage": "use_def" },
@@ -966,7 +993,12 @@
},
{
"encodings": {
- "FaddToSt": { "opcodes": [ "D8", "0" ] }
+ "FaddToSt": { "opcodes": [ "D8", "0" ] },
+ "FdivToSt": { "opcodes": [ "D8", "6" ] },
+ "FdivrToSt": { "opcodes": [ "D8", "7" ] },
+ "FmulToSt": { "opcodes": [ "D8", "1" ] },
+ "FsubToSt": { "opcodes": [ "D8", "4" ] },
+ "FsubrToSt": { "opcodes": [ "D8", "5" ] }
},
"args": [
{ "class": "ST", "usage": "use_def" },
@@ -975,7 +1007,81 @@
},
{
"encodings": {
- "Fcom": { "opcodes": [ "D8", "2" ] }
+ "Faddl": { "opcodes": [ "DC", "0" ] },
+ "Fdivl": { "opcodes": [ "DC", "6" ] },
+ "Fdivrl": { "opcodes": [ "DC", "7" ] },
+ "Fmull": { "opcodes": [ "DC", "1" ] },
+ "Fsubl": { "opcodes": [ "DC", "4" ] },
+ "Fsubrl": { "opcodes": [ "DC", "5" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use_def" },
+ { "class": "MemX8764", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fadds": { "opcodes": [ "D8", "0" ] },
+ "Fdivrs": { "opcodes": [ "D8", "7" ] },
+ "Fdivs": { "opcodes": [ "D8", "6" ] },
+ "Fiaddl": { "opcodes": [ "DA", "0" ] },
+ "Fidivl": { "opcodes": [ "DA", "6" ] },
+ "Fidivrl": { "opcodes": [ "DA", "7" ] },
+ "Fimull": { "opcodes": [ "DA", "1" ] },
+ "Fisubl": { "opcodes": [ "DA", "4" ] },
+ "Fisubrl": { "opcodes": [ "DA", "5" ] },
+ "Fmuls": { "opcodes": [ "D8", "1" ] },
+ "Fsubrs": { "opcodes": [ "D8", "5" ] },
+ "Fsubs": { "opcodes": [ "D8", "4" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use_def" },
+ { "class": "MemX8732", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fbld": { "opcodes": [ "DF", "4" ] },
+ "Fldt": { "opcodes": [ "DB", "5" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "def" },
+ { "class": "MemX8780", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fbstp": { "opcodes": [ "DF", "6" ] },
+ "Fstpt": { "opcodes": [ "DB", "7" ] }
+ },
+ "args": [
+ { "class": "MemX8780", "usage": "def" },
+ { "class": "ST", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "FcmovbToSt": { "opcodes": [ "DA", "0" ] },
+ "FcmovbeToSt": { "opcodes": [ "DA", "2" ] },
+ "FcmoveToSt": { "opcodes": [ "DA", "1" ] },
+ "FcmovnbToSt": { "opcodes": [ "DB", "0" ] },
+ "FcmovnbeToSt": { "opcodes": [ "DB", "2" ] },
+ "FcmovneToSt": { "opcodes": [ "DB", "1" ] },
+ "FcmovnuToSt": { "opcodes": [ "DB", "3" ] },
+ "FcmovuToSt": { "opcodes": [ "DA", "3" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use_def" },
+ { "class": "RegX87", "usage": "use" },
+ { "class": "FLAGS", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fcom": { "opcodes": [ "D8", "2" ] },
+ "Fcomp": { "opcodes": [ "D8", "3" ] },
+ "Fucom": { "opcodes": [ "DD", "4" ] },
+ "Fucomp": { "opcodes": [ "DD", "5" ] }
},
"args": [
{ "class": "ST", "usage": "use" },
@@ -985,6 +1091,101 @@
},
{
"encodings": {
+ "Fcomi": { "opcodes": [ "DB", "6" ] },
+ "Fcomip": { "opcodes": [ "DF", "6" ] },
+ "Fucomi": { "opcodes": [ "DB", "5" ] },
+ "Fucomip": { "opcodes": [ "DF", "5" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use" },
+ { "class": "RegX87", "usage": "use" },
+ { "class": "FLAGS", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fcoml": { "opcodes": [ "DC", "2" ] },
+ "Fcompl": { "opcodes": [ "DC", "3" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use" },
+ { "class": "MemX8764", "usage": "use" },
+ { "class": "CC", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fcompp": { "opcodes": [ "DE", "D9" ] },
+ "Fucompp": { "opcodes": [ "DA", "E9" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use" },
+ { "class": "ST1", "usage": "use" },
+ { "class": "CC", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fcomps": { "opcodes": [ "D8", "3" ] },
+ "Fcoms": { "opcodes": [ "D8", "2" ] },
+ "Ficoml": { "opcodes": [ "DA", "2" ] },
+ "Ficompl": { "opcodes": [ "DA", "3" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use" },
+ { "class": "MemX8732", "usage": "use" },
+ { "class": "CC", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fdecstp": { "opcodes": [ "D9", "F6" ] },
+ "Fincstp": { "opcodes": [ "D9", "F7" ] },
+ "Fnop": { "opcodes": [ "D9", "D0" ] },
+ "Fwait": { "opcodes": [ "9B" ] },
+ "Int3": { "opcodes": [ "CC" ] },
+ "Mfence": { "opcodes": [ "0F", "AE", "F0" ] },
+ "Nop": { "opcodes": [ "90" ] },
+ "UD2": { "opcodes": [ "0F", "0B" ] },
+ "Wait": { "opcodes": [ "9B" ] }
+ },
+ "args": []
+ },
+ {
+ "encodings": {
+ "Ffree": { "opcodes": [ "DD", "0" ] }
+ },
+ "args": [
+ { "class": "RegX87", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fiadds": { "opcodes": [ "DE", "0" ] },
+ "Fidivrs": { "opcodes": [ "DE", "7" ] },
+ "Fidivs": { "opcodes": [ "DE", "6" ] },
+ "Fimuls": { "opcodes": [ "DE", "1" ] },
+ "Fisubrs": { "opcodes": [ "DE", "5" ] },
+ "Fisubs": { "opcodes": [ "DE", "4" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use_def" },
+ { "class": "MemX8716", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "Ficomps": { "opcodes": [ "DE", "3" ] },
+ "Ficoms": { "opcodes": [ "DE", "2" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use" },
+ { "class": "MemX8716", "usage": "use" },
+ { "class": "CC", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
"Fildl": { "opcodes": [ "DB", "0" ] },
"Flds": { "opcodes": [ "D9", "0" ] }
},
@@ -1009,13 +1210,14 @@
},
"args": [
{ "class": "ST", "usage": "def" },
- { "class": "MemX8732", "usage": "use" }
+ { "class": "MemX8716", "usage": "use" }
]
},
{
"encodings": {
"Fistl": { "opcodes": [ "DB", "2" ] },
"Fistpl": { "opcodes": [ "DB", "3" ] },
+ "Fisttpl": { "feature": "SSE3", "opcodes": [ "DB", "1" ] },
"Fstps": { "opcodes": [ "D9", "3" ] },
"Fsts": { "opcodes": [ "D9", "2" ] }
},
@@ -1027,6 +1229,7 @@
{
"encodings": {
"Fistpll": { "opcodes": [ "DF", "7" ] },
+ "Fisttpll": { "feature": "SSE3", "opcodes": [ "DD", "1" ] },
"Fstl": { "opcodes": [ "DD", "2" ] },
"Fstpl": { "opcodes": [ "DD", "3" ] }
},
@@ -1037,6 +1240,40 @@
},
{
"encodings": {
+ "Fistps": { "opcodes": [ "DF", "3" ] },
+ "Fists": { "opcodes": [ "DF", "2" ] },
+ "Fisttps": { "feature": "SSE3", "opcodes": [ "DF", "1" ] }
+ },
+ "args": [
+ { "class": "MemX8716", "usage": "def" },
+ { "class": "ST", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fld1": { "opcodes": [ "D9", "E8" ] },
+ "Fldl2e": { "opcodes": [ "D9", "EA" ] },
+ "Fldl2t": { "opcodes": [ "D9", "E9" ] },
+ "Fldlg2": { "opcodes": [ "D9", "EC" ] },
+ "Fldln2": { "opcodes": [ "D9", "ED" ] },
+ "Fldpi": { "opcodes": [ "D9", "EB" ] },
+ "Fldz": { "opcodes": [ "D9", "EE" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use_def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fld": { "opcodes": [ "D9", "0" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "def" },
+ { "class": "RegX87", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
"Fldcw": { "opcodes": [ "D9", "5" ] }
},
"args": [
@@ -1046,6 +1283,40 @@
},
{
"encodings": {
+ "Fldenv": { "opcodes": [ "D9", "4" ] },
+ "Frstor": { "opcodes": [ "DD", "4" ] },
+ "Fxrstor": { "opcodes": [ "0F", "AE", "1" ] }
+ },
+ "args": [
+ { "class": "MemX87", "usage": "use" },
+ { "class": "CC", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fnclex": { "opcodes": [ "DB", "E2" ] },
+ "Fndisi": { "opcodes": [ "DB", "E1" ] },
+ "Fneni": { "opcodes": [ "DB", "E0" ] },
+ "Fninit": { "opcodes": [ "DB", "E3" ] },
+ "Fnsetpm": { "opcodes": [ "DB", "E4" ] }
+ },
+ "args": [
+ { "class": "CC", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fnsave": { "opcodes": [ "DD", "6" ] },
+ "Fnstenv": { "opcodes": [ "D9", "6" ] },
+ "Fxsave": { "opcodes": [ "0F", "AE", "0" ] }
+ },
+ "args": [
+ { "class": "CC", "usage": "def" },
+ { "class": "MemX87", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
"Fnstcw": { "opcodes": [ "D9", "7" ] }
},
"args": [
@@ -1073,6 +1344,58 @@
},
{
"encodings": {
+ "Fpatan": { "opcodes": [ "D9", "F3" ] },
+ "Fprem": { "opcodes": [ "D9", "F8" ] },
+ "Fprem1": { "opcodes": [ "D9", "F5" ] },
+ "Fyl2x": { "opcodes": [ "D9", "F1" ] },
+ "Fyl2xp1": { "opcodes": [ "D9", "F9" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use_def" },
+ { "class": "ST1", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fptan": { "opcodes": [ "D9", "F2" ] },
+ "Fsincos": { "opcodes": [ "D9", "FB" ] },
+ "Fxtract": { "opcodes": [ "D9", "F4" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use_def" },
+ { "class": "ST1", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fst": { "opcodes": [ "DD", "2" ] },
+ "Fstp": { "opcodes": [ "DD", "3" ] }
+ },
+ "args": [
+ { "class": "RegX87", "usage": "def" },
+ { "class": "ST", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fxam": { "opcodes": [ "D9", "E5" ] }
+ },
+ "args": [
+ { "class": "ST", "usage": "use" },
+ { "class": "CC", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fxch": { "opcodes": [ "D9", "1" ] }
+ },
+ "args": [
+ { "class": "RegX87", "usage": "use_def" },
+ { "class": "ST", "usage": "use_def" }
+ ]
+ },
+ {
+ "encodings": {
"Imulb": { "opcodes": [ "F6", "5" ] },
"Mulb": { "opcodes": [ "F6", "4" ] }
},
@@ -1172,15 +1495,6 @@
]
},
{
- "encodings": {
- "Int3": { "opcodes": [ "CC" ] },
- "Mfence": { "opcodes": [ "0F", "AE", "F0" ] },
- "Nop": { "opcodes": [ "90" ] },
- "UD2": { "opcodes": [ "0F", "0B" ] }
- },
- "args": []
- },
- {
"stems": [ "Jcc" ],
"args": [
{ "class": "Cond" },
diff --git a/assembler/instructions/insn_def_x86_64.json b/assembler/instructions/insn_def_x86_64.json
index 0a98cb9..b31f8bc 100644
--- a/assembler/instructions/insn_def_x86_64.json
+++ b/assembler/instructions/insn_def_x86_64.json
@@ -364,6 +364,24 @@
},
{
"encodings": {
+ "Fxrstor64": { "opcodes": [ "0F", "AE", "1" ] }
+ },
+ "args": [
+ { "class": "Mem64", "usage": "use" },
+ { "class": "CC", "usage": "def" }
+ ]
+ },
+ {
+ "encodings": {
+ "Fxsave64": { "opcodes": [ "0F", "AE", "0" ] }
+ },
+ "args": [
+ { "class": "CC", "usage": "def" },
+ { "class": "Mem64", "usage": "use" }
+ ]
+ },
+ {
+ "encodings": {
"Imulq": { "opcodes": [ "F7", "5" ] },
"Mulq": { "opcodes": [ "F7", "4" ] }
},
