| // Copyright 2015, VIXL authors |
| // All rights reserved. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are met: |
| // |
| // * Redistributions of source code must retain the above copyright notice, |
| // this list of conditions and the following disclaimer. |
| // * Redistributions in binary form must reproduce the above copyright notice, |
| // this list of conditions and the following disclaimer in the documentation |
| // and/or other materials provided with the distribution. |
| // * Neither the name of ARM Limited nor the names of its contributors may be |
| // used to endorse or promote products derived from this software without |
| // specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND |
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| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| |
| |
| // --------------------------------------------------------------------- |
| // This file is auto generated using tools/generate_simulator_traces.py. |
| // |
| // PLEASE DO NOT EDIT. |
| // --------------------------------------------------------------------- |
| |
| #ifndef VIXL_SIM_FSQRT_8H_TRACE_AARCH64_H_ |
| #define VIXL_SIM_FSQRT_8H_TRACE_AARCH64_H_ |
| |
| const uint16_t kExpected_NEON_fsqrt_8H[] = { |
| 0xff23, 0xfe00, 0xff23, 0xfe01, 0x7e00, 0x7e00, 0x7e00, 0x0000, |
| 0xfe00, 0xff23, 0xfe01, 0x7e00, 0x7e00, 0x7e00, 0x0000, 0x2000, |
| 0xff23, 0xfe01, 0x7e00, 0x7e00, 0x7e00, 0x0000, 0x2000, 0x39a8, |
| 0xfe01, 0x7e00, 0x7e00, 0x7e00, 0x0000, 0x2000, 0x39a8, 0x39a8, |
| 0x7e00, 0x7e00, 0x7e00, 0x0000, 0x2000, 0x39a8, 0x39a8, 0x39a9, |
| 0x7e00, 0x7e00, 0x0000, 0x2000, 0x39a8, 0x39a8, 0x39a9, 0x3bff, |
| 0x7e00, 0x0000, 0x2000, 0x39a8, 0x39a8, 0x39a9, 0x3bff, 0x3c00, |
| 0x0000, 0x2000, 0x39a8, 0x39a8, 0x39a9, 0x3bff, 0x3c00, 0x3c00, |
| 0x2000, 0x39a8, 0x39a8, 0x39a9, 0x3bff, 0x3c00, 0x3c00, 0x3ce6, |
| 0x39a8, 0x39a8, 0x39a9, 0x3bff, 0x3c00, 0x3c00, 0x3ce6, 0x4253, |
| 0x39a8, 0x39a9, 0x3bff, 0x3c00, 0x3c00, 0x3ce6, 0x4253, 0x5bff, |
| 0x39a9, 0x3bff, 0x3c00, 0x3c00, 0x3ce6, 0x4253, 0x5bff, 0x7c00, |
| 0x3bff, 0x3c00, 0x3c00, 0x3ce6, 0x4253, 0x5bff, 0x7c00, 0x7f23, |
| 0x3c00, 0x3c00, 0x3ce6, 0x4253, 0x5bff, 0x7c00, 0x7f23, 0x7e00, |
| 0x3c00, 0x3ce6, 0x4253, 0x5bff, 0x7c00, 0x7f23, 0x7e00, 0x7f23, |
| 0x3ce6, 0x4253, 0x5bff, 0x7c00, 0x7f23, 0x7e00, 0x7f23, 0x7e01, |
| 0x4253, 0x5bff, 0x7c00, 0x7f23, 0x7e00, 0x7f23, 0x7e01, 0x143e, |
| 0x5bff, 0x7c00, 0x7f23, 0x7e00, 0x7f23, 0x7e01, 0x143e, 0x1fff, |
| 0x7c00, 0x7f23, 0x7e00, 0x7f23, 0x7e01, 0x143e, 0x1fff, 0x0c00, |
| 0x7f23, 0x7e00, 0x7f23, 0x7e01, 0x143e, 0x1fff, 0x0c00, 0x8000, |
| 0x7e00, 0x7f23, 0x7e01, 0x143e, 0x1fff, 0x0c00, 0x8000, 0x7e00, |
| 0x7f23, 0x7e01, 0x143e, 0x1fff, 0x0c00, 0x8000, 0x7e00, 0x7e00, |
| 0x7e01, 0x143e, 0x1fff, 0x0c00, 0x8000, 0x7e00, 0x7e00, 0x7e00, |
| 0x143e, 0x1fff, 0x0c00, 0x8000, 0x7e00, 0x7e00, 0x7e00, 0x7e00, |
| 0x1fff, 0x0c00, 0x8000, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, |
| 0x0c00, 0x8000, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, |
| 0x8000, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, |
| 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, |
| 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, |
| 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, |
| 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, |
| 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0xff23, |
| 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0xff23, 0xfe00, |
| 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0xff23, 0xfe00, 0xff23, |
| 0x7e00, 0x7e00, 0x7e00, 0x7e00, 0xff23, 0xfe00, 0xff23, 0xfe01, |
| 0x7e00, 0x7e00, 0x7e00, 0xff23, 0xfe00, 0xff23, 0xfe01, 0x7e00, |
| 0x7e00, 0x7e00, 0xff23, 0xfe00, 0xff23, 0xfe01, 0x7e00, 0x7e00, |
| 0x7e00, 0xff23, 0xfe00, 0xff23, 0xfe01, 0x7e00, 0x7e00, 0x7e00, |
| }; |
| const unsigned kExpectedCount_NEON_fsqrt_8H = 38; |
| |
| #endif // VIXL_SIM_FSQRT_8H_TRACE_AARCH64_H_ |