commit dc661669ef2e2fd18c4e21333d6a12112b520436
author Pirama Arumuga Nainar <pirama@google.com> Mon May 18 22:40:26 2015 -0700
committer Pirama Arumuga Nainar <pirama@google.com> Tue May 19 13:44:09 2015 -0700
tree 12d0614590d1c15e3b91a8d04ae0f432742651d4
parent f83765e26812f0d09307defe5dcbabb19632ab45

Temporary workaround for b/21273194

Create a new Register object that is equivalent to register lr (x30).
This is a temporary workaround to b/21273194.  For some reason, the
const global object vixl::lr is uninitialized at this point.

Change-Id: I107778c2f66da6b4868edbfe0448349adaa0af59
(cherry picked from commit 2f76f9ce52a6f9c084686f0e3b77834ff8a10c59)

src/vixl/a64/assembler-a64.cc

diff --git a/src/vixl/a64/assembler-a64.cc b/src/vixl/a64/assembler-a64.cc
index 9f85e8f..89b96f0 100644
--- a/src/vixl/a64/assembler-a64.cc
+++ b/src/vixl/a64/assembler-a64.cc
@@ -132,7 +132,10 @@
 CPURegList CPURegList::GetCallerSaved(unsigned size) {
   // Registers x0-x18 and lr (x30) are caller-saved.
   CPURegList list = CPURegList(CPURegister::kRegister, size, 0, 18);
-  list.Combine(lr);
+  // Temporary workaround for bug 21273194: Create a Register object equivalent
+  // to register lr (x30)
+  // list.Combine(lr);
+  list.Combine(Register(30, size));
   return list;
 }