commit 24c0a1eebd3409e415c4dccca1216b41f819aad4
author Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> Fri Jan 17 14:35:09 2020 +0000
committer Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> Fri Jan 17 14:35:09 2020 +0000
tree 75f101f639c15ac42fa37270d7630bd641eba717
parent c97d5666cbcc8c98166977d4d7670ccf21501068
parent 4ffae8eec534828d6dca56d9c8fba259298613d0

Merge "Remove non-zero register asserts from Csinc/Csinv/Csneg" am: 4ffae8eec5

Change-Id: Ie8db127f25f53cd44a4f56da571639f477f4dbc9

src/aarch64/macro-assembler-aarch64.h

diff --git a/src/aarch64/macro-assembler-aarch64.h b/src/aarch64/macro-assembler-aarch64.h
index 9c09f1c..31db8da 100644
--- a/src/aarch64/macro-assembler-aarch64.h
+++ b/src/aarch64/macro-assembler-aarch64.h
@@ -1273,8 +1273,6 @@
              Condition cond) {
     VIXL_ASSERT(allow_macro_instructions_);
     VIXL_ASSERT(!rd.IsZero());
-    VIXL_ASSERT(!rn.IsZero());
-    VIXL_ASSERT(!rm.IsZero());
     VIXL_ASSERT((cond != al) && (cond != nv));
     SingleEmissionCheckScope guard(this);
     csinc(rd, rn, rm, cond);
@@ -1285,8 +1283,6 @@
              Condition cond) {
     VIXL_ASSERT(allow_macro_instructions_);
     VIXL_ASSERT(!rd.IsZero());
-    VIXL_ASSERT(!rn.IsZero());
-    VIXL_ASSERT(!rm.IsZero());
     VIXL_ASSERT((cond != al) && (cond != nv));
     SingleEmissionCheckScope guard(this);
     csinv(rd, rn, rm, cond);
@@ -1297,8 +1293,6 @@
              Condition cond) {
     VIXL_ASSERT(allow_macro_instructions_);
     VIXL_ASSERT(!rd.IsZero());
-    VIXL_ASSERT(!rn.IsZero());
-    VIXL_ASSERT(!rm.IsZero());
     VIXL_ASSERT((cond != al) && (cond != nv));
     SingleEmissionCheckScope guard(this);
     csneg(rd, rn, rm, cond);

test/aarch64/test-assembler-aarch64.cc

diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index f968c28..c4696e5 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -5941,6 +5941,66 @@
   }
 }
 
+TEST(csel_zero) {
+  SETUP();
+
+  START();
+
+  __ Mov(x15, 0x0);
+  __ Mov(x16, 0x0000001f0000002f);
+
+  // Check results when zero registers are used as inputs
+  // for Csinc, Csinv and Csneg for both true and false conditions.
+  __ Cmp(x15, 0);
+  __ Csinc(x0, x16, xzr, eq);
+  __ Csinc(x1, xzr, x16, eq);
+  __ Cmp(x15, 1);
+  __ Csinc(w2, w16, wzr, eq);
+  __ Csinc(w3, wzr, w16, eq);
+
+  __ Csinc(x4, xzr, xzr, eq);
+
+  __ Cmp(x15, 0);
+  __ Csinv(x5, x16, xzr, eq);
+  __ Csinv(x6, xzr, x16, eq);
+  __ Cmp(x15, 1);
+  __ Csinv(w7, w16, wzr, eq);
+  __ Csinv(w8, wzr, w16, eq);
+
+  __ Csinv(x9, xzr, xzr, eq);
+
+  __ Cmp(x15, 0);
+  __ Csneg(x10, x16, xzr, eq);
+  __ Csneg(x11, xzr, x16, eq);
+  __ Cmp(x15, 1);
+  __ Csneg(w12, w16, wzr, eq);
+  __ Csneg(w13, wzr, w16, eq);
+
+  __ Csneg(x14, xzr, xzr, eq);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_64(0x0000001f0000002f, x0);
+    ASSERT_EQUAL_64(0x0, x1);
+    ASSERT_EQUAL_32(0x1, w2);
+    ASSERT_EQUAL_32(0x30, w3);
+    ASSERT_EQUAL_64(0x1, x4);
+    ASSERT_EQUAL_64(0x0000001f0000002f, x5);
+    ASSERT_EQUAL_64(0x0, x6);
+    ASSERT_EQUAL_32(0xffffffff, w7);
+    ASSERT_EQUAL_32(0xffffffd0, w8);
+    ASSERT_EQUAL_64(0xffffffffffffffff, x9);
+    ASSERT_EQUAL_64(0x0000001f0000002f, x10);
+    ASSERT_EQUAL_64(0x0, x11);
+    ASSERT_EQUAL_32(0x0, w12);
+    ASSERT_EQUAL_32(0xffffffd1, w13);
+    ASSERT_EQUAL_64(0x0, x14);
+  }
+}
+
 
 TEST(csel_imm) {
   SETUP();