Merge remote-tracking branch 'aosp/upstream-master' into master am: f822f577a8 am: e3a79de276 am: 751f025227
am: 7bdec85d20
Change-Id: Ic2138a14251b92b52c9037f1d1d3bedf8be71da4
diff --git a/README.md b/README.md
index 17b81a2..d421a37 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
-VIXL: AArch64 Runtime Code Generation Library Version 1.13
-==========================================================
+VIXL: ARMv8 Runtime Code Generation Library, Development Version
+================================================================
Contents:
@@ -15,15 +15,15 @@
VIXL contains three components.
- 1. A programmatic **assembler** to generate A64 code at runtime. The assembler
- abstracts some of the constraints of the A64 ISA; for example, most
+ 1. Programmatic **assemblers** to generate A64, A32 or T32 code at runtime. The
+ assemblers abstract some of the constraints of each ISA; for example, most
instructions support any immediate.
- 2. A **disassembler** that can print any instruction emitted by the assembler.
- 3. A **simulator** that can simulate any instruction emitted by the assembler.
- The simulator allows generated code to be run on another architecture
- without the need for a full ISA model.
+ 2. **Disassemblers** that can print any instruction emitted by the assemblers.
+ 3. A **simulator** that can simulate any instruction emitted by the A64
+ assembler. The simulator allows generated code to be run on another
+ architecture without the need for a full ISA model.
-The VIXL git repository can be found [on GitHub][vixl].
+The VIXL git repository can be found [on 'https://git.linaro.org'][vixl].
Changes from previous versions of VIXL can be found in the
[Changelog](doc/changelog.md).
@@ -59,8 +59,8 @@
Refer to the 'Usage' section for details.
-Known Limitations
-=================
+Known Limitations for AArch64 code generation
+=============================================
VIXL was developed for JavaScript engines so a number of features from A64 were
deemed unnecessary:
@@ -72,7 +72,7 @@
The VIXL simulator supports only those instructions that the VIXL assembler can
generate. The `doc` directory contains a
-[list of supported instructions](doc/supported-instructions.md).
+[list of supported A64 instructions](doc/aarch64/supported-instructions-aarch64.md).
The VIXL simulator was developed to run on 64-bit amd64 platforms. Whilst it
builds and mostly works for 32-bit x86 platforms, there are a number of
@@ -162,24 +162,25 @@
Getting Started
---------------
-A short introduction to using VIXL can be found [here](doc/getting-started.md).
-Example source code is provided in the [examples](examples) directory. You can
-build all the examples with `scons examples` from the root directory, or use
+We have separate guides for introducing VIXL, depending on what architecture you
+are targeting. A guide for working with AArch32 can be found
+[here][getting-started-aarch32], while the AArch64 guide is
+[here][getting-started-aarch64]. Example source code is provided in the
+[examples](examples) directory. You can build examples with either `scons
+aarch32_examples` or `scons aarch64_examples` from the root directory, or use
`scons --help` to get a detailed list of available build targets.
-Using VIXL
-----------
-
-In addition to [getting started](doc/getting-started.md) and the
-[examples](examples), you can find documentation and guides on various topics
-that may be helpful [here](doc/topics/index.md).
-
-
[cpplint]: http://google-styleguide.googlecode.com/svn/trunk/cpplint/cpplint.py
"Google's cpplint.py script."
-[vixl]: https://github.com/armvixl/vixl
- "The VIXL repository on GitHub."
+[vixl]: https://git.linaro.org/arm/vixl.git
+ "The VIXL repository at 'https://git.linaro.org'."
+
+[getting-started-aarch32]: doc/aarch32/getting-started-aarch32.md
+ "Introduction to VIXL for AArch32."
+
+[getting-started-aarch64]: doc/aarch64/getting-started-aarch64.md
+ "Introduction to VIXL for AArch64."
diff --git a/SConstruct b/SConstruct
index 4d20845..e4a56e2 100644
--- a/SConstruct
+++ b/SConstruct
@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import glob
+import itertools
import os
from os.path import join
import platform
@@ -81,7 +82,6 @@
'-Wextra',
'-Wredundant-decls',
'-pedantic',
- '-Wmissing-noreturn',
'-Wwrite-strings',
'-Wunused'],
'CPPPATH' : [config.dir_src_vixl]
@@ -95,16 +95,6 @@
'mode:release' : {
'CCFLAGS' : ['-O3'],
},
- 'target_arch:aarch32' : {
- 'CCFLAGS' : ['-DVIXL_INCLUDE_TARGET_AARCH32']
- },
- 'target_arch:aarch64' : {
- 'CCFLAGS' : ['-DVIXL_INCLUDE_TARGET_AARCH64']
- },
- 'target_arch:both' : {
- 'CCFLAGS' : ['-DVIXL_INCLUDE_TARGET_AARCH32',
- '-DVIXL_INCLUDE_TARGET_AARCH64']
- },
'simulator:aarch64' : {
'CCFLAGS' : ['-DVIXL_INCLUDE_SIMULATOR_AARCH64'],
},
@@ -142,25 +132,20 @@
def IsAArch64Host(env):
return env['host_arch'] == 'aarch64'
+def CanTargetA32(env):
+ return 'a32' in env['target']
+
+def CanTargetT32(env):
+ return 't32' in env['target']
+
def CanTargetAArch32(env):
- return env['target_arch'] in ['aarch32', 'both']
+ return CanTargetA32(env) or CanTargetT32(env)
+
+def CanTargetA64(env):
+ return 'a64' in env['target']
def CanTargetAArch64(env):
- return env['target_arch'] in ['aarch64', 'both']
-
-
-# The architecture targeted by default will depend on the compiler being
-# used. 'host_arch' is extracted from the compiler while 'target_arch' can be
-# set by the user.
-# By default, we target both AArch32 and AArch64 unless the compiler targets a
-# 32-bit architecture. At the moment, we cannot build VIXL's AArch64 support on
-# a 32-bit platform.
-# TODO: Port VIXL to build on a 32-bit platform.
-def target_arch_handler(env):
- if Is32BitHost(env):
- env['target_arch'] = 'aarch32'
- else:
- env['target_arch'] = 'both'
+ return CanTargetA64(env)
# By default, include the simulator only if AArch64 is targeted and we are not
@@ -186,17 +171,10 @@
pass
-def target_arch_validator(env):
- # TODO: Port VIXL64 to work on a 32-bit platform.
- if Is32BitHost(env) and CanTargetAArch64(env):
- raise UserError('Building VIXL for AArch64 in 32-bit is not supported. Set '
- '`target_arch` to `aarch32`')
-
-
def simulator_validator(env):
if env['simulator'] == 'aarch64' and not CanTargetAArch64(env):
raise UserError('Building an AArch64 simulator implies that VIXL targets '
- 'AArch64. Set `target_arch` to `aarch64` or `both`.')
+ 'AArch64. Set `target` to include `aarch64` or `a64`.')
# Default variables may depend on each other, therefore we need this dictionnary
@@ -205,9 +183,6 @@
# variable_name : [ 'default val', 'handler', 'validator']
'symbols' : [ 'mode==debug', symbols_handler, default_validator ],
'modifiable_flags' : [ 'mode==debug', modifiable_flags_handler, default_validator],
- 'target_arch' : [ 'AArch32 only if the host compiler targets a 32-bit '
- 'architecture - otherwise both', target_arch_handler,
- target_arch_validator],
'simulator' : [ 'on if the target architectures include AArch64 but '
'the host is not AArch64, else off',
simulator_handler, simulator_validator ],
@@ -227,9 +202,37 @@
return (name, help, default_value, validator)
+def AliasedListVariable(name, help, default_value, allowed_values, aliasing):
+ help = '%s (all|auto|comma-separated list) (any combination from [%s])' % \
+ (help, ', '.join(allowed_values))
+
+ def validator(name, value, env):
+ # Here list has been converted to space separated strings.
+ if value == '': return # auto
+ for v in value.split():
+ if v not in allowed_values:
+ raise UserError('Invalid value for %s: %s' % (name, value))
+
+ def converter(value):
+ if value == 'auto': return []
+ if value == 'all':
+ translated = [aliasing[v] for v in allowed_values]
+ return list(set(itertools.chain.from_iterable(translated)))
+ # The validator is run later hence the get.
+ translated = [aliasing.get(v, v) for v in value.split(',')]
+ return list(set(itertools.chain.from_iterable(translated)))
+
+ return (name, help, default_value, validator, converter)
+
+
vars = Variables()
# Define command line build options.
vars.AddVariables(
+ AliasedListVariable('target', 'Target ISA/Architecture', 'auto',
+ ['aarch32', 'a32', 't32', 'aarch64', 'a64'],
+ {'aarch32' : ['a32', 't32'],
+ 'a32' : ['a32'], 't32' : ['t32'],
+ 'aarch64' : ['a64'], 'a64' : ['a64']}),
EnumVariable('mode', 'Build mode',
'release', allowed_values=config.build_options_modes),
EnumVariable('negative_testing',
@@ -237,8 +240,6 @@
'off', allowed_values=['on', 'off']),
DefaultVariable('symbols', 'Include debugging symbols in the binaries',
['on', 'off']),
- DefaultVariable('target_arch', 'Target architecture',
- ['aarch32', 'aarch64', 'both']),
DefaultVariable('simulator', 'Simulators to include', ['aarch64', 'none']),
DefaultVariable('code_buffer_allocator',
'Configure the allocation mechanism in the CodeBuffer',
@@ -252,8 +253,8 @@
# set. These are the options that should be reflected in the build directory
# path.
options_influencing_build_path = [
- 'target_arch', 'mode', 'symbols', 'CXX', 'std', 'simulator',
- 'negative_testing', 'code_buffer_allocator'
+ 'target', 'mode', 'symbols', 'CXX', 'std', 'simulator', 'negative_testing',
+ 'code_buffer_allocator'
]
@@ -274,6 +275,41 @@
env['ENV']['TERM'] = os.getenv('TERM')
+# The architecture targeted by default will depend on the compiler being
+# used. 'host_arch' is extracted from the compiler while 'target' can be
+# set by the user.
+# By default, we target both AArch32 and AArch64 unless the compiler targets a
+# 32-bit architecture. At the moment, we cannot build VIXL's AArch64 support on
+# a 32-bit platform.
+# TODO: Port VIXL to build on a 32-bit platform.
+def target_handler(env):
+ # Auto detect
+ if Is32BitHost(env):
+ # We use list(set(...)) to keep the same order as if it was specify as
+ # an option.
+ env['target'] = list(set(['a32', 't32']))
+ else:
+ env['target'] = list(set(['a64', 'a32', 't32']))
+
+
+def target_validator(env):
+ # TODO: Port VIXL64 to work on a 32-bit platform.
+ if Is32BitHost(env) and CanTargetAArch64(env):
+ raise UserError('Building VIXL for AArch64 in 32-bit is not supported. Set '
+ '`target` to `aarch32`')
+
+
+# The target option is handled differently from the rest.
+def ProcessTargetOption(env):
+ if env['target'] == []: target_handler(env)
+
+ if 'a32' in env['target']: env['CCFLAGS'] += ['-DVIXL_INCLUDE_TARGET_A32']
+ if 't32' in env['target']: env['CCFLAGS'] += ['-DVIXL_INCLUDE_TARGET_T32']
+ if 'a64' in env['target']: env['CCFLAGS'] += ['-DVIXL_INCLUDE_TARGET_A64']
+
+ target_validator(env)
+
+
def ProcessBuildOptions(env):
# 'all' is unconditionally processed.
if 'all' in options:
@@ -283,6 +319,10 @@
else:
env[var] = options['all'][var]
+ # The target option *must* be processed before the options defined in
+ # vars_default_handlers.
+ ProcessTargetOption(env)
+
# Other build options must match 'option:value'
env_dict = env.Dictionary()
@@ -307,6 +347,11 @@
def ConfigureEnvironmentForCompiler(env):
+ if CanTargetA32(env) and CanTargetT32(env):
+ # When building for only one aarch32 isa, fixing the no-return is not worth
+ # the effort.
+ env.Append(CPPFLAGS = ['-Wmissing-noreturn'])
+
compiler = util.CompilerInformation(env)
if compiler == 'clang':
# These warnings only work for Clang.
@@ -353,7 +398,7 @@
# full build when an option changes.
build_dir = config.dir_build
for option in options_influencing_build_path:
- option_value = env[option] if option in env else ''
+ option_value = ''.join(env[option]) if option in env else ''
build_dir = join(build_dir, option + '_'+ option_value)
return build_dir
@@ -374,10 +419,10 @@
# Source files are in `src` and in `src/aarch64/`.
variant_dir_vixl = PrepareVariantDir(join('src'), build_dir)
sources = [Glob(join(variant_dir_vixl, '*.cc'))]
- if env['target_arch'] in ['aarch32', 'both']:
+ if CanTargetAArch32(env):
variant_dir_aarch32 = PrepareVariantDir(join('src', 'aarch32'), build_dir)
sources.append(Glob(join(variant_dir_aarch32, '*.cc')))
- if env['target_arch'] in ['aarch64', 'both']:
+ if CanTargetAArch64(env):
variant_dir_aarch64 = PrepareVariantDir(join('src', 'aarch64'), build_dir)
sources.append(Glob(join(variant_dir_aarch64, '*.cc')))
return env.Library(join(build_dir, 'vixl'), sources)
@@ -411,7 +456,7 @@
test_objects = [env.Object(Glob(join(test_build_dir, '*.cc')))]
# AArch32 support
-if env['target_arch'] in ['aarch32', 'both']:
+if CanTargetAArch32(env):
# The examples.
aarch32_example_names = util.ListCCFilesWithoutExt(config.dir_aarch32_examples)
aarch32_examples_build_dir = PrepareVariantDir('examples/aarch32', TargetBuildDir(env))
@@ -443,7 +488,7 @@
CPPPATH = env['CPPPATH'] + [config.dir_tests]))
# AArch64 support
-if env['target_arch'] in ['aarch64', 'both']:
+if CanTargetAArch64(env):
# The benchmarks.
aarch64_benchmark_names = util.ListCCFilesWithoutExt(config.dir_aarch64_benchmarks)
aarch64_benchmarks_build_dir = PrepareVariantDir('benchmarks/aarch64', TargetBuildDir(env))
diff --git a/doc/design/code-generation.md b/doc/aarch32/design/code-generation-aarch32.md
similarity index 100%
rename from doc/design/code-generation.md
rename to doc/aarch32/design/code-generation-aarch32.md
diff --git a/doc/design/aarch32/literal-pool.md b/doc/aarch32/design/literal-pool-aarch32.md
similarity index 100%
rename from doc/design/aarch32/literal-pool.md
rename to doc/aarch32/design/literal-pool-aarch32.md
diff --git a/doc/getting-started-aarch32.md b/doc/aarch32/getting-started-aarch32.md
similarity index 100%
rename from doc/getting-started-aarch32.md
rename to doc/aarch32/getting-started-aarch32.md
diff --git a/doc/getting-started-aarch64.md b/doc/aarch64/getting-started-aarch64.md
similarity index 97%
rename from doc/getting-started-aarch64.md
rename to doc/aarch64/getting-started-aarch64.md
index 4637a8d..ff8c2e7 100644
--- a/doc/getting-started-aarch64.md
+++ b/doc/aarch64/getting-started-aarch64.md
@@ -197,3 +197,11 @@
demonstrate the basics of the VIXL framework. There are more complex code
examples in the VIXL `examples/aarch64` directory showing more features of both the
macro assembler and the ARMv8 architecture.
+
+
+Extras
+------
+
+In addition to this document and the [examples](/examples/aarch64), you can find
+documentation and guides on various topics that may be helpful
+[here](/doc/aarch64/topics/index.md).
diff --git a/doc/supported-instructions-aarch64.md b/doc/aarch64/supported-instructions-aarch64.md
similarity index 100%
rename from doc/supported-instructions-aarch64.md
rename to doc/aarch64/supported-instructions-aarch64.md
diff --git a/doc/topics/aarch64/extending-the-disassembler.md b/doc/aarch64/topics/extending-the-disassembler.md
similarity index 100%
rename from doc/topics/aarch64/extending-the-disassembler.md
rename to doc/aarch64/topics/extending-the-disassembler.md
diff --git a/doc/topics/aarch64/index.md b/doc/aarch64/topics/index.md
similarity index 93%
rename from doc/topics/aarch64/index.md
rename to doc/aarch64/topics/index.md
index e38aaad..0e11450 100644
--- a/doc/topics/aarch64/index.md
+++ b/doc/aarch64/topics/index.md
@@ -2,7 +2,7 @@
you think of any topic that may be useful and is not listed here, please contact
us at <vixl@arm.com>.
-You can also have a look at the ['getting started' page](../getting-started.md).
+You can also have a look at the ['getting started' page](../getting-started-aarch64.md).
* [Extending and customizing the disassembler](extending-the-disassembler.md)
* [Using VIM YouCompleteMe with VIXL](ycm.md)
diff --git a/doc/topics/aarch64/ycm.md b/doc/aarch64/topics/ycm.md
similarity index 100%
rename from doc/topics/aarch64/ycm.md
rename to doc/aarch64/topics/ycm.md
diff --git a/examples/aarch32/examples.h b/examples/aarch32/examples.h
index 36ecf32..280a467 100644
--- a/examples/aarch32/examples.h
+++ b/examples/aarch32/examples.h
@@ -93,7 +93,7 @@
// Generate a function with the following prototype:
// uint32_t demo_function(uint32_t x)
//
-// This is the example used in doc/getting-started-a32.txt
+// This is the example used in doc/getting-started-aarch32.md
void GenerateDemo(MacroAssembler* masm);
#endif // VIXL_EXAMPLE_EXAMPLES_H_
diff --git a/src/aarch32/assembler-aarch32.cc b/src/aarch32/assembler-aarch32.cc
index c91e0c0..5c3ec82 100644
--- a/src/aarch32/assembler-aarch32.cc
+++ b/src/aarch32/assembler-aarch32.cc
@@ -81,7 +81,7 @@
void Assembler::BindHelper(Label* label) {
VIXL_ASSERT(!label->IsBound());
- label->Bind(GetCursorOffset(), IsUsingT32());
+ label->Bind(GetCursorOffset(), GetInstructionSetInUse());
for (Label::ForwardRefList::iterator ref = label->GetFirstForwardRef();
ref != label->GetEndForwardRef();
@@ -103,7 +103,7 @@
GetCursorOffset() + GetArchitectureStatePCOffset(),
label);
}
- label->AddForwardRef(GetCursorOffset(), IsUsingT32(), op);
+ label->AddForwardRef(GetCursorOffset(), GetInstructionSetInUse(), op);
return instr;
}
@@ -3477,13 +3477,16 @@
CheckIT(cond);
if (IsUsingT32()) {
// CLZ{<c>}{<q>} <Rd>, <Rm> ; T1
- EmitT32_32(0xfab0f080U | (rd.GetCode() << 8) | rm.GetCode() |
- (rm.GetCode() << 16));
- AdvanceIT();
- return;
+ if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
+ EmitT32_32(0xfab0f080U | (rd.GetCode() << 8) | rm.GetCode() |
+ (rm.GetCode() << 16));
+ AdvanceIT();
+ return;
+ }
} else {
// CLZ{<c>}{<q>} <Rd>, <Rm> ; A1
- if (cond.IsNotNever()) {
+ if (cond.IsNotNever() &&
+ ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
EmitA32(0x016f0f10U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
rm.GetCode());
return;
diff --git a/src/aarch32/assembler-aarch32.h b/src/aarch32/assembler-aarch32.h
index 7e030ee..37c4334 100644
--- a/src/aarch32/assembler-aarch32.h
+++ b/src/aarch32/assembler-aarch32.h
@@ -70,39 +70,103 @@
const Label::LabelEmitOperator& op);
public:
- explicit Assembler(InstructionSet isa = A32)
+ class AllowUnpredictableScope {
+ Assembler* assembler_;
+ bool old_;
+
+ public:
+ explicit AllowUnpredictableScope(Assembler* assembler)
+ : assembler_(assembler), old_(assembler->allow_unpredictable_) {
+ assembler_->allow_unpredictable_ = true;
+ }
+ ~AllowUnpredictableScope() { assembler_->allow_unpredictable_ = old_; }
+ };
+ class AllowStronglyDiscouragedScope {
+ Assembler* assembler_;
+ bool old_;
+
+ public:
+ explicit AllowStronglyDiscouragedScope(Assembler* assembler)
+ : assembler_(assembler), old_(assembler->allow_strongly_discouraged_) {
+ assembler_->allow_strongly_discouraged_ = true;
+ }
+ ~AllowStronglyDiscouragedScope() {
+ assembler_->allow_strongly_discouraged_ = old_;
+ }
+ };
+
+ explicit Assembler(InstructionSet isa = kDefaultISA)
: isa_(isa),
first_condition_(al),
it_mask_(0),
has_32_dregs_(true),
allow_unpredictable_(false),
- allow_strongly_discouraged_(false) {}
- explicit Assembler(size_t capacity, InstructionSet isa = A32)
+ allow_strongly_discouraged_(false) {
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+ // Avoid compiler warning.
+ USE(isa_);
+ VIXL_ASSERT(isa == A32);
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+ USE(isa_);
+ VIXL_ASSERT(isa == T32);
+#endif
+ }
+ explicit Assembler(size_t capacity, InstructionSet isa = kDefaultISA)
: AssemblerBase(capacity),
isa_(isa),
first_condition_(al),
it_mask_(0),
has_32_dregs_(true),
allow_unpredictable_(false),
- allow_strongly_discouraged_(false) {}
- Assembler(byte* buffer, size_t capacity, InstructionSet isa = A32)
+ allow_strongly_discouraged_(false) {
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+ VIXL_ASSERT(isa == A32);
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+ VIXL_ASSERT(isa == T32);
+#endif
+ }
+ Assembler(byte* buffer, size_t capacity, InstructionSet isa = kDefaultISA)
: AssemblerBase(buffer, capacity),
isa_(isa),
first_condition_(al),
it_mask_(0),
has_32_dregs_(true),
allow_unpredictable_(false),
- allow_strongly_discouraged_(false) {}
+ allow_strongly_discouraged_(false) {
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+ VIXL_ASSERT(isa == A32);
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+ VIXL_ASSERT(isa == T32);
+#endif
+ }
virtual ~Assembler() {}
+
void UseInstructionSet(InstructionSet isa) {
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+ USE(isa);
+ VIXL_ASSERT(isa == A32);
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+ USE(isa);
+ VIXL_ASSERT(isa == T32);
+#else
VIXL_ASSERT((isa_ == isa) || (GetCursorOffset() == 0));
isa_ = isa;
+#endif
}
+
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+ InstructionSet GetInstructionSetInUse() const { return A32; }
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+ InstructionSet GetInstructionSetInUse() const { return T32; }
+#else
InstructionSet GetInstructionSetInUse() const { return isa_; }
+#endif
+
void UseT32() { UseInstructionSet(T32); }
void UseA32() { UseInstructionSet(A32); }
bool IsUsingT32() const { return GetInstructionSetInUse() == T32; }
bool IsUsingA32() const { return GetInstructionSetInUse() == A32; }
+
void SetIT(Condition first_condition, uint16_t it_mask) {
VIXL_ASSERT(it_mask_ == 0);
first_condition_ = first_condition;
@@ -5997,45 +6061,9 @@
std::string("' instruction.\n"));
VIXL_ABORT_WITH_MSG(error_message.c_str());
}
- bool AllowUnpredictable() { return allow_unpredictable_; }
- bool AllowStronglyDiscouraged() { return allow_strongly_discouraged_; }
-
- // Allow the following scopes to modify the internal allow_unpredictable_ and
- // allow_strongly_discouraged_ members.
- friend class AllowUnpredictableScope;
- friend class AllowStronglyDiscouragedScope;
-};
-
-// Temporarily allow generating UNPREDICTABLE instruction. Using this scope is
-// only allowed when using the assembler directly.
-class AllowUnpredictableScope {
- Assembler* assembler_;
- bool old_;
-
- public:
- explicit AllowUnpredictableScope(Assembler* assembler)
- : assembler_(assembler), old_(assembler->allow_unpredictable_) {
- VIXL_ASSERT(assembler_->AllowAssembler());
- assembler_->allow_unpredictable_ = true;
- }
- ~AllowUnpredictableScope() { assembler_->allow_unpredictable_ = old_; }
-};
-
-// Temporarily allow generating strongly discouraged instructions. For example,
-// this includes T32 conditional instructions that are not otherwise conditional
-// in A32. Using this scope is only allowed when using the assembler directly.
-class AllowStronglyDiscouragedScope {
- Assembler* assembler_;
- bool old_;
-
- public:
- explicit AllowStronglyDiscouragedScope(Assembler* assembler)
- : assembler_(assembler), old_(assembler->allow_strongly_discouraged_) {
- VIXL_ASSERT(assembler_->AllowAssembler());
- assembler_->allow_strongly_discouraged_ = true;
- }
- ~AllowStronglyDiscouragedScope() {
- assembler_->allow_strongly_discouraged_ = old_;
+ virtual bool AllowUnpredictable() { return allow_unpredictable_; }
+ virtual bool AllowStronglyDiscouraged() {
+ return allow_strongly_discouraged_;
}
};
diff --git a/src/aarch32/constants-aarch32.h b/src/aarch32/constants-aarch32.h
index 449af80..c53c24e 100644
--- a/src/aarch32/constants-aarch32.h
+++ b/src/aarch32/constants-aarch32.h
@@ -32,9 +32,17 @@
#include <stdint.h>
}
+
namespace vixl {
namespace aarch32 {
+enum InstructionSet { A32, T32 };
+#ifdef VIXL_INCLUDE_TARGET_T32_ONLY
+const InstructionSet kDefaultISA = T32;
+#else
+const InstructionSet kDefaultISA = A32;
+#endif
+
const unsigned kRegSizeInBits = 32;
const unsigned kRegSizeInBytes = kRegSizeInBits / 8;
const unsigned kSRegSizeInBits = 32;
diff --git a/src/aarch32/instructions-aarch32.h b/src/aarch32/instructions-aarch32.h
index 36012c7..18292a8 100644
--- a/src/aarch32/instructions-aarch32.h
+++ b/src/aarch32/instructions-aarch32.h
@@ -56,7 +56,6 @@
class AlignedMemOperand;
enum AddrMode { Offset = 0, PreIndex = 1, PostIndex = 2 };
-enum InstructionSet { A32, T32 };
class CPURegister {
public:
diff --git a/src/aarch32/label-aarch32.cc b/src/aarch32/label-aarch32.cc
index b327e25..3ac8422 100644
--- a/src/aarch32/label-aarch32.cc
+++ b/src/aarch32/label-aarch32.cc
@@ -35,8 +35,15 @@
VIXL_ASSERT(IsBlocked());
if (--monitor_ == 0) {
// Ensure the pool has not been blocked for too long.
- VIXL_ASSERT(masm_->GetCursorOffset() <= near_checkpoint_);
- VIXL_ASSERT(masm_->GetCursorOffset() <= far_checkpoint_);
+ // This may generate some veneers if some labels has been added by the code
+ // which used Block/Release.
+
+ // TODO: This check is _temporarily_ disabled to work around some usage in
+ // ART, which assumes that pools will not be generated immediately after
+ // macros or ExactAssemblyScopes. The next instruction that is generated
+ // will perform this check anyway, but in a place less convenient for
+ // debugging.
+ // masm_->EnsureEmitFor(0);
}
}
diff --git a/src/aarch32/label-aarch32.h b/src/aarch32/label-aarch32.h
index 2dac5c4..4d4931d 100644
--- a/src/aarch32/label-aarch32.h
+++ b/src/aarch32/label-aarch32.h
@@ -70,14 +70,32 @@
class ForwardReference {
public:
- ForwardReference(int32_t location, const LabelEmitOperator& op, bool t32)
- : location_(location), op_(op), is_t32_(t32), is_branch_(false) {}
+ ForwardReference(int32_t location,
+ const LabelEmitOperator& op,
+ InstructionSet isa)
+ : location_(location), op_(op), isa_(isa), is_branch_(false) {
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+ USE(isa_);
+ VIXL_ASSERT(isa_ == A32);
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+ USE(isa_);
+ VIXL_ASSERT(isa == T32);
+#endif
+ }
Offset GetMaxForwardDistance() const { return op_.GetMaxForwardDistance(); }
int32_t GetLocation() const { return location_; }
uint32_t GetStatePCOffset() const {
- return is_t32_ ? kT32PcDelta : kA32PcDelta;
+ return IsUsingT32() ? kT32PcDelta : kA32PcDelta;
}
- bool IsUsingT32() const { return is_t32_; }
+
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+ bool IsUsingT32() const { return false; }
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+ bool IsUsingT32() const { return true; }
+#else
+ bool IsUsingT32() const { return isa_ == T32; }
+#endif
+
bool IsBranch() const { return is_branch_; }
void SetIsBranch() { is_branch_ = true; }
const LabelEmitOperator& GetEmitOperator() const { return op_; }
@@ -93,7 +111,7 @@
private:
int32_t location_;
const LabelEmitOperator& op_;
- bool is_t32_;
+ InstructionSet isa_;
bool is_branch_;
};
@@ -123,7 +141,7 @@
pc_offset_(0),
is_bound_(false),
minus_zero_(false),
- is_t32_(false),
+ isa_(kDefaultISA),
referenced_(false),
veneer_pool_manager_(NULL),
is_near_(false),
@@ -133,7 +151,7 @@
pc_offset_(pc_offset),
is_bound_(true),
minus_zero_(minus_zero),
- is_t32_(false),
+ isa_(kDefaultISA),
referenced_(false),
veneer_pool_manager_(NULL),
is_near_(false),
@@ -145,13 +163,24 @@
}
#endif
}
+
+#undef DEFAULT_IS_T32
+
bool IsBound() const { return is_bound_; }
bool HasForwardReference() const { return !forward_.empty(); }
- void Bind(Offset offset, bool isT32) {
+ void Bind(Offset offset, InstructionSet isa) {
VIXL_ASSERT(!IsBound());
+ USE(isa);
+ USE(isa_);
imm_offset_ = offset;
is_bound_ = true;
- is_t32_ = isT32;
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+ VIXL_ASSERT(isa == A32);
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+ VIXL_ASSERT(isa == T32);
+#else
+ isa_ = isa;
+#endif
}
uint32_t GetPcOffset() const { return pc_offset_; }
Offset GetLocation() const {
@@ -159,8 +188,14 @@
return imm_offset_ + static_cast<Offset>(pc_offset_);
}
bool IsUsingT32() const {
- VIXL_ASSERT(IsBound()); // Must be bound to know if it's a T32 label
- return is_t32_;
+ VIXL_ASSERT(IsBound()); // Must be bound to know its ISA.
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+ return false;
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+ return true;
+#else
+ return isa_ == T32;
+#endif
}
bool IsMinusZero() const {
VIXL_ASSERT(IsBound());
@@ -185,10 +220,10 @@
return AlignDown(GetCheckpoint(), byte_align);
}
void AddForwardRef(int32_t instr_location,
- bool isT32,
+ InstructionSet isa,
const LabelEmitOperator& op) {
VIXL_ASSERT(referenced_);
- forward_.push_back(ForwardReference(instr_location, op, isT32));
+ forward_.push_back(ForwardReference(instr_location, op, isa));
}
ForwardRefList::iterator GetFirstForwardRef() { return forward_.begin(); }
@@ -252,8 +287,8 @@
bool is_bound_;
// Special flag for 'pc - 0'.
bool minus_zero_;
- // Is the label in T32 state.
- bool is_t32_;
+ // Which ISA is the label in.
+ InstructionSet isa_;
// True if the label has been used at least once.
bool referenced_;
// Not null if the label is currently inserted in the veneer pool.
@@ -272,6 +307,8 @@
: masm_(masm),
near_checkpoint_(Label::kMaxOffset),
far_checkpoint_(Label::kMaxOffset),
+ max_near_checkpoint_(0),
+ near_checkpoint_margin_(0),
last_label_reference_offset_(0),
monitor_(0) {}
bool IsEmpty() const {
@@ -287,7 +324,8 @@
Label::Offset tmp =
far_checkpoint_ - static_cast<Label::Offset>(veneer_max_size);
// Make room for a branch over the pools.
- return std::min(near_checkpoint_, tmp) - kMaxInstructionSizeInBytes;
+ return std::min(near_checkpoint_, tmp) - kMaxInstructionSizeInBytes -
+ near_checkpoint_margin_;
}
size_t GetMaxSize() const {
return (near_labels_.size() + far_labels_.size()) *
@@ -307,11 +345,17 @@
// Lists of all unbound labels which are used by a branch instruction.
std::list<Label*> near_labels_;
std::list<Label*> far_labels_;
- // Max offset in the code buffer where the veneer needs to be emitted.
+ // Offset in the code buffer after which the veneer needs to be emitted.
+ // It's the lowest checkpoint value in the associated list.
// A default value of Label::kMaxOffset means that the checkpoint is
- // invalid.
+ // invalid (no entry in the list).
Label::Offset near_checkpoint_;
Label::Offset far_checkpoint_;
+ // Highest checkpoint value for the near list.
+ Label::Offset max_near_checkpoint_;
+ // Margin we have to take to ensure that 16 bit branch instructions will be
+ // able to generate 32 bit veneers.
+ uint32_t near_checkpoint_margin_;
// Offset where the last reference to a label has been added to the pool.
Label::Offset last_label_reference_offset_;
// Indicates whether the emission of this pool is blocked.
diff --git a/src/aarch32/macro-assembler-aarch32.cc b/src/aarch32/macro-assembler-aarch32.cc
index 57d3cbe..1e7a6b5 100644
--- a/src/aarch32/macro-assembler-aarch32.cc
+++ b/src/aarch32/macro-assembler-aarch32.cc
@@ -36,6 +36,24 @@
namespace vixl {
namespace aarch32 {
+// We use a subclass to access the protected `ExactAssemblyScope` constructor
+// giving us control over the pools, and make the constructor private to limit
+// usage to code paths emitting pools.
+class ExactAssemblyScopeWithoutPoolsCheck : public ExactAssemblyScope {
+ private:
+ ExactAssemblyScopeWithoutPoolsCheck(MacroAssembler* masm,
+ size_t size,
+ SizePolicy size_policy = kExactSize)
+ : ExactAssemblyScope(masm,
+ size,
+ size_policy,
+ ExactAssemblyScope::kIgnorePools) {}
+
+ friend class MacroAssembler;
+ friend class VeneerPoolManager;
+};
+
+
void UseScratchRegisterScope::Open(MacroAssembler* masm) {
VIXL_ASSERT(masm_ == NULL);
VIXL_ASSERT(masm != NULL);
@@ -211,8 +229,8 @@
// We found two 16 bit forward branches generated one after the other.
// That means that the pool will grow by one 32-bit branch when
// the cursor offset will move forward by only one 16-bit branch.
- // Update the cbz/cbnz checkpoint to manage the difference.
- near_checkpoint_ -=
+ // Update the near checkpoint margin to manage the difference.
+ near_checkpoint_margin_ +=
k32BitT32InstructionSizeInBytes - k16BitT32InstructionSizeInBytes;
}
}
@@ -240,6 +258,15 @@
Label::Offset tmp = label->GetCheckpoint();
if (label->IsNear()) {
if (near_checkpoint_ > tmp) near_checkpoint_ = tmp;
+ if (max_near_checkpoint_ >= tmp) {
+ // This checkpoint is before some already in the near list. That means
+ // that the veneer (if needed) will be emitted before some of the veneers
+ // already in the list. We adjust the margin with the size of a veneer
+ // branch.
+ near_checkpoint_margin_ += k32BitT32InstructionSizeInBytes;
+ } else {
+ max_near_checkpoint_ = tmp;
+ }
} else {
if (far_checkpoint_ > tmp) far_checkpoint_ = tmp;
}
@@ -303,17 +330,22 @@
far_checkpoint_ = std::min(far_checkpoint_, label_checkpoint);
}
// Generate the veneer.
- masm_->B(label);
+ ExactAssemblyScopeWithoutPoolsCheck guard(masm_,
+ kMaxInstructionSizeInBytes,
+ ExactAssemblyScope::kMaximumSize);
+ masm_->b(label);
+ masm_->AddBranchLabel(label);
}
void VeneerPoolManager::Emit(Label::Offset target) {
VIXL_ASSERT(!IsBlocked());
// Sort labels (regarding their checkpoint) to avoid that a veneer
- // becomes out of range. Near labels are always sorted as it holds only one
- // range.
+ // becomes out of range.
+ near_labels_.sort(Label::CompareLabels);
far_labels_.sort(Label::CompareLabels);
// To avoid too many veneers, generate veneers which will be necessary soon.
+ target += static_cast<int>(GetMaxSize()) + near_checkpoint_margin_;
static const size_t kVeneerEmissionMargin = 1 * KBytes;
// To avoid too many veneers, use generated veneers for other not too far
// uses.
@@ -323,6 +355,8 @@
// Reset the checkpoints. They will be computed again in the loop.
near_checkpoint_ = Label::kMaxOffset;
far_checkpoint_ = Label::kMaxOffset;
+ max_near_checkpoint_ = 0;
+ near_checkpoint_margin_ = 0;
for (std::list<Label*>::iterator it = near_labels_.begin();
it != near_labels_.end();) {
Label* label = *it;
@@ -366,69 +400,43 @@
}
-// We use a subclass to access the protected `ExactAssemblyScope` constructor
-// giving us control over the pools, and make the constructor private to limit
-// usage to code paths emitting pools.
-class ExactAssemblyScopeWithoutPoolsCheck : public ExactAssemblyScope {
- private:
- ExactAssemblyScopeWithoutPoolsCheck(MacroAssembler* masm,
- size_t size,
- SizePolicy size_policy = kExactSize)
- : ExactAssemblyScope(masm,
- size,
- size_policy,
- ExactAssemblyScope::kIgnorePools) {}
-
- friend void MacroAssembler::EmitLiteralPool(LiteralPool* const literal_pool,
- EmitOption option);
-
- // TODO: `PerformEnsureEmit` is `private`, so we have to make the
- // `MacroAssembler` a friend.
- friend class MacroAssembler;
-};
-
-
void MacroAssembler::PerformEnsureEmit(Label::Offset target, uint32_t size) {
- if (!doing_veneer_pool_generation_) {
- EmitOption option = kBranchRequired;
- Label after_pools;
- Label::Offset literal_target = GetTargetForLiteralEmission();
- VIXL_ASSERT(literal_target >= 0);
- bool generate_veneers = target > veneer_pool_manager_.GetCheckpoint();
- if (target > literal_target) {
- // We will generate the literal pool. Generate all the veneers which
- // would become out of range.
- size_t literal_pool_size = literal_pool_manager_.GetLiteralPoolSize() +
- kMaxInstructionSizeInBytes;
- VIXL_ASSERT(IsInt32(literal_pool_size));
- Label::Offset veneers_target =
- AlignUp(target + static_cast<Label::Offset>(literal_pool_size), 4);
- VIXL_ASSERT(veneers_target >= 0);
- if (veneers_target > veneer_pool_manager_.GetCheckpoint()) {
- generate_veneers = true;
- }
+ EmitOption option = kBranchRequired;
+ Label after_pools;
+ Label::Offset literal_target = GetTargetForLiteralEmission();
+ VIXL_ASSERT(literal_target >= 0);
+ bool generate_veneers = target > veneer_pool_manager_.GetCheckpoint();
+ if (target > literal_target) {
+ // We will generate the literal pool. Generate all the veneers which
+ // would become out of range.
+ size_t literal_pool_size =
+ literal_pool_manager_.GetLiteralPoolSize() + kMaxInstructionSizeInBytes;
+ VIXL_ASSERT(IsInt32(literal_pool_size));
+ Label::Offset veneers_target =
+ AlignUp(target + static_cast<Label::Offset>(literal_pool_size), 4);
+ VIXL_ASSERT(veneers_target >= 0);
+ if (veneers_target > veneer_pool_manager_.GetCheckpoint()) {
+ generate_veneers = true;
}
- if (generate_veneers) {
- {
- ExactAssemblyScopeWithoutPoolsCheck
- guard(this,
- kMaxInstructionSizeInBytes,
- ExactAssemblyScope::kMaximumSize);
- b(&after_pools);
- }
- doing_veneer_pool_generation_ = true;
- veneer_pool_manager_.Emit(target);
- doing_veneer_pool_generation_ = false;
- option = kNoBranchRequired;
- }
- // Check if the macro-assembler's internal literal pool should be emitted
- // to avoid any overflow. If we already generated the veneers, we can
- // emit the pool (the branch is already done).
- if ((target > literal_target) || (option == kNoBranchRequired)) {
- EmitLiteralPool(option);
- }
- BindHelper(&after_pools);
}
+ if (generate_veneers) {
+ {
+ ExactAssemblyScopeWithoutPoolsCheck
+ guard(this,
+ kMaxInstructionSizeInBytes,
+ ExactAssemblyScope::kMaximumSize);
+ b(&after_pools);
+ }
+ veneer_pool_manager_.Emit(target);
+ option = kNoBranchRequired;
+ }
+ // Check if the macro-assembler's internal literal pool should be emitted
+ // to avoid any overflow. If we already generated the veneers, we can
+ // emit the pool (the branch is already done).
+ if ((target > literal_target) || (option == kNoBranchRequired)) {
+ EmitLiteralPool(option);
+ }
+ BindHelper(&after_pools);
if (GetBuffer()->IsManaged()) {
bool grow_requested;
GetBuffer()->EnsureSpaceFor(size, &grow_requested);
@@ -693,6 +701,11 @@
uint32_t load_store_offset = offset & extra_offset_mask;
uint32_t add_offset = offset & ~extra_offset_mask;
+ if ((add_offset != 0) &&
+ (IsModifiedImmediate(offset) || IsModifiedImmediate(-offset))) {
+ load_store_offset = 0;
+ add_offset = offset;
+ }
if (base.IsPC()) {
// Special handling for PC bases. We must read the PC in the first
@@ -1393,6 +1406,29 @@
}
+bool MacroAssembler::GenerateSplitInstruction(
+ InstructionCondSizeRROp instruction,
+ Condition cond,
+ Register rd,
+ Register rn,
+ uint32_t imm,
+ uint32_t mask) {
+ uint32_t high = imm & ~mask;
+ if (!IsModifiedImmediate(high) && !rn.IsPC()) return false;
+ // If high is a modified immediate, we can perform the operation with
+ // only 2 instructions.
+ // Else, if rn is PC, we want to avoid moving PC into a temporary.
+ // Therefore, we also use the pattern even if the second call may
+ // generate 3 instructions.
+ uint32_t low = imm & mask;
+ CodeBufferCheckScope scope(this,
+ (rn.IsPC() ? 4 : 2) * kMaxInstructionSizeInBytes);
+ (this->*instruction)(cond, Best, rd, rn, low);
+ (this->*instruction)(cond, Best, rd, rd, high);
+ return true;
+}
+
+
void MacroAssembler::Delegate(InstructionType type,
InstructionCondSizeRROp instruction,
Condition cond,
@@ -1511,10 +1547,45 @@
return;
}
}
+
+ // When rn is PC, only handle negative offsets. The correct way to handle
+ // positive offsets isn't clear; does the user want the offset from the
+ // start of the macro, or from the end (to allow a certain amount of space)?
+ // When type is Add or Sub, imm is always positive (imm < 0 has just been
+ // handled and imm == 0 would have been generated without the need of a
+ // delegate). Therefore, only add to PC is forbidden here.
+ if ((((type == kAdd) && !rn.IsPC()) || (type == kSub)) &&
+ (IsUsingA32() || (!rd.IsPC() && !rn.IsPC()))) {
+ VIXL_ASSERT(imm > 0);
+ // Try to break the constant into two modified immediates.
+ // For T32 also try to break the constant into one imm12 and one modified
+ // immediate. Count the trailing zeroes and get the biggest even value.
+ int trailing_zeroes = CountTrailingZeros(imm) & ~1u;
+ uint32_t mask = ((trailing_zeroes < 4) && IsUsingT32())
+ ? 0xfff
+ : (0xff << trailing_zeroes);
+ if (GenerateSplitInstruction(instruction, cond, rd, rn, imm, mask)) {
+ return;
+ }
+ InstructionCondSizeRROp asmcb = NULL;
+ switch (type) {
+ case kAdd:
+ asmcb = &Assembler::sub;
+ break;
+ case kSub:
+ asmcb = &Assembler::add;
+ break;
+ default:
+ VIXL_UNREACHABLE();
+ }
+ if (GenerateSplitInstruction(asmcb, cond, rd, rn, -imm, mask)) {
+ return;
+ }
+ }
+
UseScratchRegisterScope temps(this);
// Allow using the destination as a scratch register if possible.
if (!rd.Is(rn)) temps.Include(rd);
-
if (rn.IsPC()) {
// If we're reading the PC, we need to do it in the first instruction,
// otherwise we'll read the wrong value. We rely on this to handle the
@@ -2073,21 +2144,15 @@
const Register& rn = operand.GetBaseRegister();
AddrMode addrmode = operand.GetAddrMode();
int32_t offset = operand.GetOffsetImmediate();
- uint32_t mask = GetOffsetMask(type, addrmode);
- bool negative;
- // Try to maximize the offset use by the MemOperand (load_store_offset).
- // Add or subtract the part which can't be used by the MemOperand
- // (add_sub_offset).
- int32_t add_sub_offset;
- int32_t load_store_offset;
- load_store_offset = offset & mask;
- if (offset >= 0) {
- negative = false;
- add_sub_offset = offset & ~mask;
- } else {
- negative = true;
- add_sub_offset = -offset & ~mask;
- if (load_store_offset > 0) add_sub_offset += mask + 1;
+ uint32_t extra_offset_mask = GetOffsetMask(type, addrmode);
+ // Try to maximize the offset used by the MemOperand (load_store_offset).
+ // Add the part which can't be used by the MemOperand (add_offset).
+ uint32_t load_store_offset = offset & extra_offset_mask;
+ uint32_t add_offset = offset & ~extra_offset_mask;
+ if ((add_offset != 0) &&
+ (IsModifiedImmediate(offset) || IsModifiedImmediate(-offset))) {
+ load_store_offset = 0;
+ add_offset = offset;
}
switch (addrmode) {
case PreIndex:
@@ -2099,11 +2164,7 @@
// ldr r0, [r1]
{
CodeBufferCheckScope scope(this, 3 * kMaxInstructionSizeInBytes);
- if (negative) {
- sub(cond, rn, rn, add_sub_offset);
- } else {
- add(cond, rn, rn, add_sub_offset);
- }
+ add(cond, rn, rn, add_offset);
}
{
CodeBufferCheckScope scope(this, kMaxInstructionSizeInBytes);
@@ -2129,11 +2190,7 @@
// ldr r0, [r0]
{
CodeBufferCheckScope scope(this, 3 * kMaxInstructionSizeInBytes);
- if (negative) {
- sub(cond, scratch, rn, add_sub_offset);
- } else {
- add(cond, scratch, rn, add_sub_offset);
- }
+ add(cond, scratch, rn, add_offset);
}
{
CodeBufferCheckScope scope(this, kMaxInstructionSizeInBytes);
@@ -2162,11 +2219,7 @@
}
{
CodeBufferCheckScope scope(this, 3 * kMaxInstructionSizeInBytes);
- if (negative) {
- sub(cond, rn, rn, add_sub_offset);
- } else {
- add(cond, rn, rn, add_sub_offset);
- }
+ add(cond, rn, rn, add_offset);
}
return;
}
@@ -2313,6 +2366,16 @@
const Register& rn = operand.GetBaseRegister();
AddrMode addrmode = operand.GetAddrMode();
int32_t offset = operand.GetOffsetImmediate();
+ uint32_t extra_offset_mask = GetOffsetMask(type, addrmode);
+ // Try to maximize the offset used by the MemOperand (load_store_offset).
+ // Add the part which can't be used by the MemOperand (add_offset).
+ uint32_t load_store_offset = offset & extra_offset_mask;
+ uint32_t add_offset = offset & ~extra_offset_mask;
+ if ((add_offset != 0) &&
+ (IsModifiedImmediate(offset) || IsModifiedImmediate(-offset))) {
+ load_store_offset = 0;
+ add_offset = offset;
+ }
switch (addrmode) {
case PreIndex: {
// Allow using the destinations as a scratch registers if possible.
@@ -2328,11 +2391,14 @@
// ldrd r0, r1, [r2]
{
CodeBufferCheckScope scope(this, 3 * kMaxInstructionSizeInBytes);
- add(cond, rn, rn, offset);
+ add(cond, rn, rn, add_offset);
}
{
CodeBufferCheckScope scope(this, kMaxInstructionSizeInBytes);
- (this->*instruction)(cond, rt, rt2, MemOperand(rn, Offset));
+ (this->*instruction)(cond,
+ rt,
+ rt2,
+ MemOperand(rn, load_store_offset, PreIndex));
}
return;
}
@@ -2350,11 +2416,14 @@
// ldrd r0, r1, [r0]
{
CodeBufferCheckScope scope(this, 3 * kMaxInstructionSizeInBytes);
- add(cond, scratch, rn, offset);
+ add(cond, scratch, rn, add_offset);
}
{
CodeBufferCheckScope scope(this, kMaxInstructionSizeInBytes);
- (this->*instruction)(cond, rt, rt2, MemOperand(scratch, Offset));
+ (this->*instruction)(cond,
+ rt,
+ rt2,
+ MemOperand(scratch, load_store_offset));
}
return;
}
@@ -2369,11 +2438,14 @@
// add r2, ip
{
CodeBufferCheckScope scope(this, kMaxInstructionSizeInBytes);
- (this->*instruction)(cond, rt, rt2, MemOperand(rn, Offset));
+ (this->*instruction)(cond,
+ rt,
+ rt2,
+ MemOperand(rn, load_store_offset, PostIndex));
}
{
CodeBufferCheckScope scope(this, 3 * kMaxInstructionSizeInBytes);
- add(cond, rn, rn, offset);
+ add(cond, rn, rn, add_offset);
}
return;
}
diff --git a/src/aarch32/macro-assembler-aarch32.h b/src/aarch32/macro-assembler-aarch32.h
index 9e653e9..706b5a5 100644
--- a/src/aarch32/macro-assembler-aarch32.h
+++ b/src/aarch32/macro-assembler-aarch32.h
@@ -455,15 +455,14 @@
}
public:
- explicit MacroAssembler(InstructionSet isa = A32)
+ explicit MacroAssembler(InstructionSet isa = kDefaultISA)
: Assembler(isa),
available_(r12),
current_scratch_scope_(NULL),
checkpoint_(Label::kMaxOffset),
literal_pool_manager_(this),
veneer_pool_manager_(this),
- generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE),
- doing_veneer_pool_generation_(false) {
+ generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) {
#ifdef VIXL_DEBUG
SetAllowMacroInstructions(true);
#else
@@ -472,29 +471,27 @@
#endif
ComputeCheckpoint();
}
- explicit MacroAssembler(size_t size, InstructionSet isa = A32)
+ explicit MacroAssembler(size_t size, InstructionSet isa = kDefaultISA)
: Assembler(size, isa),
available_(r12),
current_scratch_scope_(NULL),
checkpoint_(Label::kMaxOffset),
literal_pool_manager_(this),
veneer_pool_manager_(this),
- generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE),
- doing_veneer_pool_generation_(false) {
+ generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) {
#ifdef VIXL_DEBUG
SetAllowMacroInstructions(true);
#endif
ComputeCheckpoint();
}
- MacroAssembler(byte* buffer, size_t size, InstructionSet isa = A32)
+ MacroAssembler(byte* buffer, size_t size, InstructionSet isa = kDefaultISA)
: Assembler(buffer, size, isa),
available_(r12),
current_scratch_scope_(NULL),
checkpoint_(Label::kMaxOffset),
literal_pool_manager_(this),
veneer_pool_manager_(this),
- generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE),
- doing_veneer_pool_generation_(false) {
+ generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) {
#ifdef VIXL_DEBUG
SetAllowMacroInstructions(true);
#endif
@@ -976,6 +973,12 @@
EncodingSize size,
Register rd,
Label* label) VIXL_OVERRIDE;
+ bool GenerateSplitInstruction(InstructionCondSizeRROp instruction,
+ Condition cond,
+ Register rd,
+ Register rn,
+ uint32_t imm,
+ uint32_t mask);
virtual void Delegate(InstructionType type,
InstructionCondSizeRROp instruction,
Condition cond,
@@ -10947,6 +10950,16 @@
void Vsub(VRegister rd, VRegister rn, VRegister rm) { Vsub(al, rd, rn, rm); }
// End of generated code.
+ virtual bool AllowUnpredictable() VIXL_OVERRIDE {
+ VIXL_ABORT_WITH_MSG("Unpredictable instruction.\n");
+ return false;
+ }
+ virtual bool AllowStronglyDiscouraged() VIXL_OVERRIDE {
+ VIXL_ABORT_WITH_MSG(
+ "ARM strongly recommends to not use this instruction.\n");
+ return false;
+ }
+
private:
RegisterList available_;
VRegisterList available_vfp_;
@@ -10957,7 +10970,6 @@
VeneerPoolManager veneer_pool_manager_;
bool generate_simulator_code_;
bool allow_macro_instructions_;
- bool doing_veneer_pool_generation_;
};
// This scope utility allows scratch registers to be managed safely. The
diff --git a/src/code-buffer-vixl.h b/src/code-buffer-vixl.h
index bcda2b4..17a2f61 100644
--- a/src/code-buffer-vixl.h
+++ b/src/code-buffer-vixl.h
@@ -50,8 +50,8 @@
#else
// These require page-aligned memory blocks, which we can only guarantee with
// mmap.
- VIXL_NO_RETURN_IN_DEBUG_MODE void SetExecutable() { VIXL_UNREACHABLE(); }
- VIXL_NO_RETURN_IN_DEBUG_MODE void SetWritable() { VIXL_UNREACHABLE(); }
+ VIXL_NO_RETURN_IN_DEBUG_MODE void SetExecutable() { VIXL_UNIMPLEMENTED(); }
+ VIXL_NO_RETURN_IN_DEBUG_MODE void SetWritable() { VIXL_UNIMPLEMENTED(); }
#endif
ptrdiff_t GetOffsetFrom(ptrdiff_t offset) const {
diff --git a/src/code-generation-scopes-vixl.h b/src/code-generation-scopes-vixl.h
index 4fdfe1a..7e47d5e 100644
--- a/src/code-generation-scopes-vixl.h
+++ b/src/code-generation-scopes-vixl.h
@@ -179,10 +179,13 @@
// Nothing to do.
return;
}
+ // Perform the opposite of `Open`, which is:
+ // - Check the code generation limit was not exceeded.
+ // - Release the pools.
+ CodeBufferCheckScope::Close();
if (pool_policy_ == kCheckPools) {
masm_->ReleasePools();
}
- CodeBufferCheckScope::Close();
VIXL_ASSERT(!initialised_);
}
diff --git a/src/globals-vixl.h b/src/globals-vixl.h
index d24ff8e..5474a43 100644
--- a/src/globals-vixl.h
+++ b/src/globals-vixl.h
@@ -256,4 +256,18 @@
#error "Please see the release notes for USE_SIMULATOR."
#endif
+// Target Architecture/ISA
+#ifdef VIXL_INCLUDE_TARGET_A64
+#define VIXL_INCLUDE_TARGET_AARCH64
+#endif
+
+#if defined(VIXL_INCLUDE_TARGET_A32) && defined(VIXL_INCLUDE_TARGET_T32)
+#define VIXL_INCLUDE_TARGET_AARCH32
+#elif defined(VIXL_INCLUDE_TARGET_A32)
+#define VIXL_INCLUDE_TARGET_A32_ONLY
+#else
+#define VIXL_INCLUDE_TARGET_T32_ONLY
+#endif
+
+
#endif // VIXL_GLOBALS_H
diff --git a/test/aarch32/config/cond-rd-rn-a32.json b/test/aarch32/config/cond-rd-rn-a32.json
index dc12e52..cacba07 100644
--- a/test/aarch32/config/cond-rd-rn-a32.json
+++ b/test/aarch32/config/cond-rd-rn-a32.json
@@ -84,7 +84,8 @@
"name": "Operands",
"operands": [
"cond", "rd", "rn"
- ]
+ ],
+ "operand-limit": 500
}
]
},
diff --git a/test/aarch32/config/cond-rd-rn-t32.json b/test/aarch32/config/cond-rd-rn-t32.json
index b306ced..fcbe003 100644
--- a/test/aarch32/config/cond-rd-rn-t32.json
+++ b/test/aarch32/config/cond-rd-rn-t32.json
@@ -91,7 +91,8 @@
"name": "Operands",
"operands": [
"cond", "rd", "rn"
- ]
+ ],
+ "operand-limit": 500
}
]
},
diff --git a/test/aarch32/config/template-assembler-aarch32.cc.in b/test/aarch32/config/template-assembler-aarch32.cc.in
index 54ca7c0..459dae9 100644
--- a/test/aarch32/config/template-assembler-aarch32.cc.in
+++ b/test/aarch32/config/template-assembler-aarch32.cc.in
@@ -54,6 +54,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef ${isa_guard}
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -210,6 +211,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/config/template-macro-assembler-aarch32.cc.in b/test/aarch32/config/template-macro-assembler-aarch32.cc.in
index 28768da..ab37208 100644
--- a/test/aarch32/config/template-macro-assembler-aarch32.cc.in
+++ b/test/aarch32/config/template-macro-assembler-aarch32.cc.in
@@ -58,6 +58,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef ${isa_guard}
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -162,6 +163,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/config/template-simulator-aarch32.cc.in b/test/aarch32/config/template-simulator-aarch32.cc.in
index 5e6385a..4dd876e 100644
--- a/test/aarch32/config/template-simulator-aarch32.cc.in
+++ b/test/aarch32/config/template-simulator-aarch32.cc.in
@@ -122,6 +122,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef ${isa_guard}
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -328,6 +329,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-aarch32.cc b/test/aarch32/test-assembler-aarch32.cc
index 5bf886b..f344ab5 100644
--- a/test/aarch32/test-assembler-aarch32.cc
+++ b/test/aarch32/test-assembler-aarch32.cc
@@ -40,8 +40,41 @@
#define STRINGIFY(x) #x
+#ifdef VIXL_INCLUDE_TARGET_A32_ONLY
+#define TEST_T32(Name) \
+void Test##Name##Impl(InstructionSet isa __attribute__((unused)))
+#else
+// Tests declared with this macro will only target T32.
+#define TEST_T32(Name) \
+void Test##Name##Impl(InstructionSet isa); \
+void Test##Name() { \
+ Test##Name##Impl(T32); \
+} \
+Test test_##Name(STRINGIFY(AARCH32_T32_##Name), &Test##Name); \
+void Test##Name##Impl(InstructionSet isa __attribute__((unused)))
+#endif
+
+#ifdef VIXL_INCLUDE_TARGET_T32_ONLY
+#define TEST_A32(Name) \
+void Test##Name##Impl(InstructionSet isa __attribute__((unused)))
+#else
+// Test declared with this macro will only target A32.
+#define TEST_A32(Name) \
+void Test##Name##Impl(InstructionSet isa); \
+void Test##Name() { \
+ Test##Name##Impl(A32); \
+} \
+Test test_##Name(STRINGIFY(AARCH32_A32_##Name), &Test##Name); \
+void Test##Name##Impl(InstructionSet isa __attribute__((unused)))
+#endif
+
// Tests declared with this macro will be run twice: once targeting A32 and
// once targeting T32.
+#if defined(VIXL_INCLUDE_TARGET_A32_ONLY)
+#define TEST(Name) TEST_A32(Name)
+#elif defined(VIXL_INCLUDE_TARGET_T32_ONLY)
+#define TEST(Name) TEST_T32(Name)
+#else
#define TEST(Name) \
void Test##Name##Impl(InstructionSet isa); \
void Test##Name() { \
@@ -52,24 +85,7 @@
} \
Test test_##Name(STRINGIFY(AARCH32_ASM_##Name), &Test##Name); \
void Test##Name##Impl(InstructionSet isa __attribute__((unused)))
-
-// Test declared with this macro will only target A32.
-#define TEST_A32(Name) \
-void Test##Name##Impl(InstructionSet isa); \
-void Test##Name() { \
- Test##Name##Impl(A32); \
-} \
-Test test_##Name(STRINGIFY(AARCH32_A32_##Name), &Test##Name); \
-void Test##Name##Impl(InstructionSet isa __attribute__((unused)))
-
-// Tests declared with this macro will only target T32.
-#define TEST_T32(Name) \
-void Test##Name##Impl(InstructionSet isa); \
-void Test##Name() { \
- Test##Name##Impl(T32); \
-} \
-Test test_##Name(STRINGIFY(AARCH32_T32_##Name), &Test##Name); \
-void Test##Name##Impl(InstructionSet isa __attribute__((unused)))
+#endif
// Tests declared with this macro are not expected to use any provided test
// helpers such as SETUP, RUN, etc.
@@ -2497,6 +2513,157 @@
}
+// Check that the veneer pool is correctly emitted even if we do enough narrow
+// branches before a cbz so that the cbz needs its veneer emitted first in the
+// pool in order to work.
+TEST_T32(b_narrow_and_cbz_sort) {
+ SETUP();
+ START();
+
+ const int kLabelsCount = 40;
+ const int kNops = 30;
+ Label b_labels[kLabelsCount];
+ Label cbz_label;
+
+ __ Nop();
+
+ __ Mov(r0, 0);
+ __ Cmp(r0, 0);
+
+ for (int i = 0; i < kLabelsCount; ++i) {
+ __ B(ne, &b_labels[i], kNear);
+ }
+
+ {
+ ExactAssemblyScope scope(&masm,
+ k16BitT32InstructionSizeInBytes * kNops,
+ ExactAssemblyScope::kExactSize);
+ for (int i = 0; i < kNops; i++) {
+ __ nop();
+ }
+ }
+
+ // The pool should not be emitted here.
+ __ Cbz(r0, &cbz_label);
+
+ // Force pool emission. If the labels are not sorted, the cbz will be out
+ // of range.
+ int32_t margin = masm.GetMarginBeforeVeneerEmission();
+ int32_t end = masm.GetCursorOffset() + margin;
+
+ {
+ ExactAssemblyScope scope(&masm, margin, ExactAssemblyScope::kExactSize);
+ while (masm.GetCursorOffset() < end) {
+ __ nop();
+ }
+ }
+
+ __ Mov(r0, 1);
+
+ for (int i = 0; i < kLabelsCount; ++i) {
+ __ Bind(&b_labels[i]);
+ }
+
+ __ Bind(&cbz_label);
+
+ END();
+
+ RUN();
+
+ ASSERT_EQUAL_32(0, r0);
+
+ TEARDOWN();
+}
+
+
+TEST_T32(b_narrow_and_cbz_sort_2) {
+ SETUP();
+ START();
+
+ const int kLabelsCount = 40;
+ const int kNops = 30;
+ Label b_labels[kLabelsCount];
+ Label cbz_label;
+
+ __ Mov(r0, 0);
+ __ Cmp(r0, 0);
+
+ for (int i = 0; i < kLabelsCount; ++i) {
+ __ B(ne, &b_labels[i], kNear);
+ }
+
+ {
+ ExactAssemblyScope scope(&masm,
+ k16BitT32InstructionSizeInBytes * kNops,
+ ExactAssemblyScope::kExactSize);
+ for (int i = 0; i < kNops; i++) {
+ __ nop();
+ }
+ }
+
+ // The pool should not be emitted here.
+ __ Cbz(r0, &cbz_label);
+
+ // Force pool emission. If the labels are not sorted, the cbz will be out
+ // of range.
+ int32_t margin = masm.GetMarginBeforeVeneerEmission();
+ int32_t end = masm.GetCursorOffset() + margin;
+
+ while (masm.GetCursorOffset() < end) __ Nop();
+
+ __ Mov(r0, 1);
+
+ for (int i = 0; i < kLabelsCount; ++i) {
+ __ Bind(&b_labels[i]);
+ }
+
+ __ Bind(&cbz_label);
+
+ END();
+
+ RUN();
+
+ ASSERT_EQUAL_32(0, r0);
+
+ TEARDOWN();
+}
+
+
+TEST_T32(long_branch) {
+ SETUP();
+ START();
+
+ for (int label_count = 128; label_count < 2048; label_count *= 2) {
+ Label* l = new Label[label_count];
+
+ for (int i = 0; i < label_count; i++) {
+ __ B(&l[i]);
+ }
+
+ for (int i = 0; i < label_count; i++) {
+ __ B(ne, &l[i]);
+ }
+
+ for (int i = 0; i < 261625; i++) {
+ __ Clz(r0, r0);
+ }
+
+ for (int i = label_count - 1; i >= 0; i--) {
+ __ Bind(&l[i]);
+ __ Nop();
+ }
+
+ delete[] l;
+ }
+
+ masm.FinalizeCode();
+
+ END();
+ RUN();
+ TEARDOWN();
+}
+
+
TEST_T32(unaligned_branch_after_literal) {
SETUP();
@@ -2931,37 +3098,55 @@
TEST_NOASM(set_isa_constructors) {
byte buffer[1024];
+#ifndef VIXL_INCLUDE_TARGET_T32_ONLY
// A32 by default.
CheckInstructionSetA32(Assembler());
CheckInstructionSetA32(Assembler(1024));
CheckInstructionSetA32(Assembler(buffer, sizeof(buffer)));
+
+ CheckInstructionSetA32(MacroAssembler());
+ CheckInstructionSetA32(MacroAssembler(1024));
+ CheckInstructionSetA32(MacroAssembler(buffer, sizeof(buffer)));
+#else
+ // T32 by default.
+ CheckInstructionSetT32(Assembler());
+ CheckInstructionSetT32(Assembler(1024));
+ CheckInstructionSetT32(Assembler(buffer, sizeof(buffer)));
+
+ CheckInstructionSetT32(MacroAssembler());
+ CheckInstructionSetT32(MacroAssembler(1024));
+ CheckInstructionSetT32(MacroAssembler(buffer, sizeof(buffer)));
+#endif
+
+#ifdef VIXL_INCLUDE_TARGET_A32
// Explicit A32.
CheckInstructionSetA32(Assembler(A32));
CheckInstructionSetA32(Assembler(1024, A32));
CheckInstructionSetA32(Assembler(buffer, sizeof(buffer), A32));
+
+ CheckInstructionSetA32(MacroAssembler(A32));
+ CheckInstructionSetA32(MacroAssembler(1024, A32));
+ CheckInstructionSetA32(MacroAssembler(buffer, sizeof(buffer), A32));
+#endif
+
+#ifdef VIXL_INCLUDE_TARGET_T32
// Explicit T32.
CheckInstructionSetT32(Assembler(T32));
CheckInstructionSetT32(Assembler(1024, T32));
CheckInstructionSetT32(Assembler(buffer, sizeof(buffer), T32));
- // A32 by default.
- CheckInstructionSetA32(MacroAssembler());
- CheckInstructionSetA32(MacroAssembler(1024));
- CheckInstructionSetA32(MacroAssembler(buffer, sizeof(buffer)));
- // Explicit A32.
- CheckInstructionSetA32(MacroAssembler(A32));
- CheckInstructionSetA32(MacroAssembler(1024, A32));
- CheckInstructionSetA32(MacroAssembler(buffer, sizeof(buffer), A32));
- // Explicit T32.
CheckInstructionSetT32(MacroAssembler(T32));
CheckInstructionSetT32(MacroAssembler(1024, T32));
CheckInstructionSetT32(MacroAssembler(buffer, sizeof(buffer), T32));
+#endif
}
TEST_NOASM(set_isa_empty) {
// It is possible to change the instruction set if no instructions have yet
- // been generated.
+ // been generated. This test only makes sense when both A32 and T32 are
+ // supported.
+#ifdef VIXL_INCLUDE_TARGET_AARCH32
Assembler assm;
CheckInstructionSetA32(assm);
assm.UseT32();
@@ -2983,12 +3168,14 @@
CheckInstructionSetT32(masm);
masm.UseInstructionSet(A32);
CheckInstructionSetA32(masm);
+#endif
}
TEST_NOASM(set_isa_noop) {
// It is possible to call a no-op UseA32/T32 or UseInstructionSet even if
// one or more instructions have been generated.
+#ifdef VIXL_INCLUDE_TARGET_A32
{
Assembler assm(A32);
CheckInstructionSetA32(assm);
@@ -3003,6 +3190,21 @@
assm.FinalizeCode();
}
{
+ MacroAssembler masm(A32);
+ CheckInstructionSetA32(masm);
+ masm.Bx(lr);
+ VIXL_ASSERT(masm.GetCursorOffset() > 0);
+ CheckInstructionSetA32(masm);
+ masm.UseA32();
+ CheckInstructionSetA32(masm);
+ masm.UseInstructionSet(A32);
+ CheckInstructionSetA32(masm);
+ masm.FinalizeCode();
+ }
+#endif
+
+#ifdef VIXL_INCLUDE_TARGET_T32
+ {
Assembler assm(T32);
CheckInstructionSetT32(assm);
CodeBufferCheckScope scope(&assm, kMaxInstructionSizeInBytes);
@@ -3016,18 +3218,6 @@
assm.FinalizeCode();
}
{
- MacroAssembler masm(A32);
- CheckInstructionSetA32(masm);
- masm.Bx(lr);
- VIXL_ASSERT(masm.GetCursorOffset() > 0);
- CheckInstructionSetA32(masm);
- masm.UseA32();
- CheckInstructionSetA32(masm);
- masm.UseInstructionSet(A32);
- CheckInstructionSetA32(masm);
- masm.FinalizeCode();
- }
- {
MacroAssembler masm(T32);
CheckInstructionSetT32(masm);
masm.Bx(lr);
@@ -3039,6 +3229,7 @@
CheckInstructionSetT32(masm);
masm.FinalizeCode();
}
+#endif
}
@@ -3329,7 +3520,7 @@
}
-TEST_T32(cbz_fuzz) {
+TEST_T32(near_branch_fuzz) {
SETUP();
START();
@@ -3342,11 +3533,14 @@
// Use multiple iterations, as each produces a different predictably random
// sequence.
- const int iterations = 32;
+ const int iterations = 64;
int loop_count = 0;
__ Mov(r1, 0);
+ // Initialise the status flags to Z set.
+ __ Cmp(r1, r1);
+
// Gradually increasing the number of cases effectively increases the
// probability of nops being emitted in the sequence. The branch-to-bind
// ratio in the sequence is fixed at 4:1 by the ratio of cases.
@@ -3376,12 +3570,14 @@
__ Add(r1, r1, 1);
}
break;
- case 1: // Branch.
+ case 1: // Compare and branch if zero (untaken as r0 == 1).
case 2:
- case 3:
- case 4:
__ Cbz(r0, &l[label_index]);
break;
+ case 3: // Conditional branch (untaken as Z set) preferred near.
+ case 4:
+ __ BPreferNear(ne, &l[label_index]);
+ break;
default: // Nop.
__ Nop();
break;
@@ -3396,7 +3592,7 @@
if (allbound) break;
}
- // Ensure that the veneer pools are emitted, to keep each case
+ // Ensure that the veneer pools are emitted, to keep each branch/bind test
// independent.
masm.FinalizeCode();
delete[] l;
@@ -3412,6 +3608,7 @@
}
+#ifdef VIXL_INCLUDE_TARGET_T32
TEST_NOASM(code_buffer_precise_growth) {
static const int kBaseBufferSize = 16;
MacroAssembler masm(kBaseBufferSize, T32);
@@ -3436,8 +3633,10 @@
masm.FinalizeCode();
}
+#endif
+#ifdef VIXL_INCLUDE_TARGET_T32
TEST_NOASM(out_of_space_immediately_before_PerformEnsureEmit) {
static const int kBaseBufferSize = 64;
MacroAssembler masm(kBaseBufferSize, T32);
@@ -3480,6 +3679,7 @@
masm.FinalizeCode();
}
+#endif
TEST_T32(distant_literal_references) {
diff --git a/test/aarch32/test-assembler-cond-rd-memop-immediate-512-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-immediate-512-a32.cc
index 35fbe45..c338197 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-immediate-512-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-immediate-512-a32.cc
@@ -61,6 +61,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3739,6 +3740,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-memop-immediate-8192-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-immediate-8192-a32.cc
index 80859b7..360e36f 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-immediate-8192-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-immediate-8192-a32.cc
@@ -61,6 +61,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3739,6 +3740,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-memop-rs-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-rs-a32.cc
index 020c334..8ea950e 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-rs-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-rs-a32.cc
@@ -65,6 +65,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3746,6 +3747,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc
index 93a8c0c..4a5c2da 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc
@@ -61,6 +61,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3743,6 +3744,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc
index f80dceb..34c3156 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc
@@ -61,6 +61,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3743,6 +3744,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-const-a32-can-use-pc.cc b/test/aarch32/test-assembler-cond-rd-operand-const-a32-can-use-pc.cc
index c7f1ee6..5c19b43 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-const-a32-can-use-pc.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-const-a32-can-use-pc.cc
@@ -61,6 +61,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -930,6 +931,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-const-a32-cannot-use-pc.cc b/test/aarch32/test-assembler-cond-rd-operand-const-a32-cannot-use-pc.cc
index 7534cae..e012224 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-const-a32-cannot-use-pc.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-const-a32-cannot-use-pc.cc
@@ -61,6 +61,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -893,6 +894,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-const-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-const-t32.cc
index 5ec5f30..f11f2cd 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-const-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-const-t32.cc
@@ -65,6 +65,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1365,6 +1366,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-imm16-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-imm16-t32.cc
index 1738035..c1c3542 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-imm16-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-imm16-t32.cc
@@ -60,6 +60,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -622,6 +623,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-a32.cc
index a4dc98b..0b8a824 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-a32.cc
@@ -71,6 +71,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1253,6 +1254,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc
index e6d0137..e322ac6 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc
@@ -63,6 +63,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1454,6 +1455,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc
index f418361..5db30a5 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc
@@ -63,6 +63,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1342,6 +1343,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc
index 23f5b76..e3ee01b 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc
@@ -65,6 +65,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1551,6 +1552,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc
index c3eee38..376d895 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1232,6 +1233,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc
index cef4038..5a3c80e 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc
@@ -65,6 +65,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1575,6 +1576,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc
index 64fc9ef..8146d20 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc
@@ -65,6 +65,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -923,6 +924,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc
index ca83b36..e276499 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -732,6 +733,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc
index 4debd44..d582fae 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc
@@ -65,6 +65,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -951,6 +952,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc
index c68b6bc..731feef 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc
@@ -65,6 +65,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2343,6 +2344,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc
index 9c8d412..a5f798b 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1232,6 +1233,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc
index db4b79d..417ef2f 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -488,6 +489,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc
index 2c5f278..8c1826d 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2279,6 +2280,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc
index d302c76..eb4a2c6 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -339,6 +340,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc
index 9b15fce..a8368c5 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-t32-in-it-block.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3380,6 +3381,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc
index 1c2a5aa..1082bde 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1126,6 +1127,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-t32.cc
index 48683f5..c7d2e5f 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-t32.cc
@@ -71,6 +71,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -478,6 +479,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-pc-operand-imm12-t32.cc b/test/aarch32/test-assembler-cond-rd-pc-operand-imm12-t32.cc
index b5272e1..04e548c 100644
--- a/test/aarch32/test-assembler-cond-rd-pc-operand-imm12-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-pc-operand-imm12-t32.cc
@@ -60,6 +60,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1235,6 +1236,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-pc-operand-imm8-t32.cc b/test/aarch32/test-assembler-cond-rd-pc-operand-imm8-t32.cc
index 4c74eb2..184af9f 100644
--- a/test/aarch32/test-assembler-cond-rd-pc-operand-imm8-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-pc-operand-imm8-t32.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1230,6 +1231,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-a32.cc
index 5f7fc6b..102cc10 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-a32.cc
@@ -64,6 +64,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -736,6 +737,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-const-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-const-a32.cc
index 4815648..80912cc 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-const-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-const-a32.cc
@@ -77,6 +77,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2768,6 +2769,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-const-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-const-t32.cc
index 7bd20d3..49005fa 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-const-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-const-t32.cc
@@ -77,6 +77,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2768,6 +2769,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-imm12-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-imm12-t32.cc
index d1ea4a6..0bbd8f7 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-imm12-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-imm12-t32.cc
@@ -61,6 +61,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1237,6 +1238,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-a32.cc
index 39e5b1b..fd5a9e9 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-a32.cc
@@ -91,6 +91,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -797,6 +798,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc
index 12e3d87..61adfc2 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc
@@ -63,6 +63,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -5244,6 +5245,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc
index 3d54fe2..8ac7899 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc
@@ -63,6 +63,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -5244,6 +5245,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
index 1f34995..649fcf0 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
@@ -77,6 +77,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2773,6 +2774,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
index 628b7a3..20db4cc 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
@@ -77,6 +77,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2773,6 +2774,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
index 1ad8ae2..2448447 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
@@ -77,6 +77,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2773,6 +2774,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
index 3e53c4e..72a74d6 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
@@ -77,6 +77,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2773,6 +2774,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc
index 301d321..b5e2446 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc
@@ -77,6 +77,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -5272,6 +5273,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc
index 8027935..4fa3721 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -734,6 +735,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc
index 9ad7d99..24566ca 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc
@@ -67,6 +67,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -750,6 +751,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc
index ef22349..b353843 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -731,6 +732,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc
index 15ac7d3..12ced41 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -441,6 +442,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc
index 3b707f2..e4be2d4 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -343,6 +344,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32.cc
index 71b20f1..d1ba575 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32.cc
@@ -91,6 +91,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -797,6 +798,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-rm-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-rm-a32.cc
index cc351c5..88703af 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-rm-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-rm-a32.cc
@@ -115,6 +115,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -643,6 +644,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-rm-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-rm-t32.cc
index 6c2c8ca..129fdd0 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-rm-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-rm-t32.cc
@@ -114,6 +114,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -641,6 +642,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-rn-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-t32.cc
index eb90d6e..0798a44 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-t32.cc
@@ -64,6 +64,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -461,6 +462,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rd-sp-operand-imm8-t32.cc b/test/aarch32/test-assembler-cond-rd-sp-operand-imm8-t32.cc
index 43c7d44..17d1384 100644
--- a/test/aarch32/test-assembler-cond-rd-sp-operand-imm8-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-sp-operand-imm8-t32.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -486,6 +487,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc b/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc
index cd430fc..602438c 100644
--- a/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1229,6 +1230,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32.cc b/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32.cc
index 3be77e4..05fc1c9 100644
--- a/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32.cc
@@ -60,6 +60,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2280,6 +2281,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc
index 0af2713..8c4b630 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1234,6 +1235,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc
index b9cb872..a39626f 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -746,6 +747,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc
index d9ea90e..aedd642 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1234,6 +1235,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc
index 25c6c9f..86a8265 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2282,6 +2283,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc
index a45e300..1bf5b4c 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1127,6 +1128,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc
index 79a5b11..de83daf 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -295,6 +296,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc
index 5d44eee..9764189 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1125,6 +1126,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc
index 1196edf..eca42a4 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc
@@ -57,6 +57,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -293,6 +294,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-cond-sp-sp-operand-imm7-t32.cc b/test/aarch32/test-assembler-cond-sp-sp-operand-imm7-t32.cc
index fff12bb..55b54f4 100644
--- a/test/aarch32/test-assembler-cond-sp-sp-operand-imm7-t32.cc
+++ b/test/aarch32/test-assembler-cond-sp-sp-operand-imm7-t32.cc
@@ -59,6 +59,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -361,6 +362,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-rd-rn-rm-a32.cc b/test/aarch32/test-assembler-rd-rn-rm-a32.cc
index e8a6fb0..25cc8f2 100644
--- a/test/aarch32/test-assembler-rd-rn-rm-a32.cc
+++ b/test/aarch32/test-assembler-rd-rn-rm-a32.cc
@@ -63,6 +63,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -734,6 +735,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-assembler-rd-rn-rm-t32.cc b/test/aarch32/test-assembler-rd-rn-rm-t32.cc
index 87ee32c..a6905ca 100644
--- a/test/aarch32/test-assembler-rd-rn-rm-t32.cc
+++ b/test/aarch32/test-assembler-rd-rn-rm-t32.cc
@@ -63,6 +63,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -734,6 +735,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-disasm-a32.cc b/test/aarch32/test-disasm-a32.cc
index 23216f8..3145935 100644
--- a/test/aarch32/test-disasm-a32.cc
+++ b/test/aarch32/test-disasm-a32.cc
@@ -44,6 +44,18 @@
#define __ masm.
#define TEST(name) TEST_(AARCH32_DISASM_##name)
+#ifdef VIXL_INCLUDE_TARGET_T32
+#define TEST_T32(name) TEST_(AARCH32_DISASM_##name)
+#else
+#define TEST_T32(name) void Test##name()
+#endif
+
+#ifdef VIXL_INCLUDE_TARGET_A32
+#define TEST_A32(name) TEST_(AARCH32_DISASM_##name)
+#else
+#define TEST_A32(name) void Test##name()
+#endif
+
#define BUF_SIZE (4096)
#define SETUP() \
@@ -124,23 +136,35 @@
#define END_COMPARE(EXP) END_COMPARE_CHECK_SIZE(EXP,-1)
+#ifdef VIXL_INCLUDE_TARGET_A32
#define COMPARE_A32(ASM, EXP) \
masm.UseA32(); \
START_COMPARE() \
masm.ASM; \
END_COMPARE(EXP)
+#else
+#define COMPARE_A32(ASM, EXP)
+#endif
+#ifdef VIXL_INCLUDE_TARGET_T32
#define COMPARE_T32(ASM, EXP) \
masm.UseT32(); \
START_COMPARE() \
masm.ASM; \
END_COMPARE(EXP)
+#else
+#define COMPARE_T32(ASM, EXP)
+#endif
+#ifdef VIXL_INCLUDE_TARGET_T32
#define COMPARE_T32_CHECK_SIZE(ASM, EXP, SIZE) \
masm.UseT32(); \
START_COMPARE() \
masm.ASM; \
END_COMPARE_CHECK_SIZE(EXP, SIZE)
+#else
+#define COMPARE_T32_CHECK_SIZE(ASM, EXP, SIZE)
+#endif
#define COMPARE_BOTH(ASM, EXP) \
COMPARE_A32(ASM, EXP) \
@@ -194,29 +218,45 @@
} \
}
+#ifdef VIXL_INCLUDE_TARGET_A32
#define MUST_FAIL_TEST_A32(ASM, EXP) \
masm.UseA32(); \
NEGATIVE_TEST({ masm.ASM; }, EXP, false) \
masm.GetBuffer()->Reset();
+#else
+#define MUST_FAIL_TEST_A32(ASM, EXP)
+#endif
+#ifdef VIXL_INCLUDE_TARGET_T32
#define MUST_FAIL_TEST_T32(ASM, EXP) \
masm.UseT32(); \
NEGATIVE_TEST({ masm.ASM; }, EXP, false) \
masm.GetBuffer()->Reset();
+#else
+#define MUST_FAIL_TEST_T32(ASM, EXP)
+#endif
#define MUST_FAIL_TEST_BOTH(ASM, EXP) \
MUST_FAIL_TEST_A32(ASM, EXP) \
MUST_FAIL_TEST_T32(ASM, EXP)
+#ifdef VIXL_INCLUDE_TARGET_A32
#define MUST_FAIL_TEST_A32_BLOCK(ASM, EXP) \
masm.UseA32(); \
NEGATIVE_TEST(ASM, EXP, false) \
masm.GetBuffer()->Reset();
+#else
+#define MUST_FAIL_TEST_A32_BLOCK(ASM, EXP)
+#endif
+#ifdef VIXL_INCLUDE_TARGET_T32
#define MUST_FAIL_TEST_T32_BLOCK(ASM, EXP) \
masm.UseT32(); \
NEGATIVE_TEST(ASM, EXP, false) \
masm.GetBuffer()->Reset();
+#else
+#define MUST_FAIL_TEST_T32_BLOCK(ASM, EXP)
+#endif
#define MUST_FAIL_TEST_BOTH_BLOCK(ASM, EXP) \
MUST_FAIL_TEST_A32_BLOCK(ASM, EXP) \
@@ -238,15 +278,23 @@
#endif
#ifdef VIXL_NEGATIVE_TESTING
+#ifdef VIXL_INCLUDE_TARGET_A32
#define SHOULD_FAIL_TEST_A32(ASM) \
masm.UseA32(); \
NEGATIVE_TEST({ masm.ASM; }, "", true) \
masm.GetBuffer()->Reset();
+#else
+#define SHOULD_FAIL_TEST_A32(ASM)
+#endif
+#ifdef VIXL_INCLUDE_TARGET_T32
#define SHOULD_FAIL_TEST_T32(ASM) \
masm.UseT32(); \
NEGATIVE_TEST({ masm.ASM; }, "", true) \
masm.GetBuffer()->Reset();
+#else
+#define SHOULD_FAIL_TEST_T32(ASM)
+#endif
#define SHOULD_FAIL_TEST_BOTH(ASM) \
SHOULD_FAIL_TEST_A32(ASM) \
@@ -292,7 +340,7 @@
};
-TEST(t32_disassembler_limit1) {
+TEST_T32(t32_disassembler_limit1) {
SETUP();
masm.UseT32();
@@ -306,7 +354,7 @@
}
-TEST(t32_disassembler_limit2) {
+TEST_T32(t32_disassembler_limit2) {
SETUP();
masm.UseT32();
@@ -561,9 +609,8 @@
SETUP();
COMPARE_BOTH(Ldr(r0, MemOperand(r1, 0xfff123)),
- "mov r0, #61440\n" // #0xf000
- "movt r0, #255\n" // #0x00ff
- "add r0, r1, r0\n"
+ "add r0, r1, #1044480\n" // #0xff000
+ "add r0, #15728640\n" // #0x00f00000
"ldr r0, [r0, #291]\n"); // #0x123
COMPARE_BOTH(Ldr(r0, MemOperand(r1, 0xff123)),
"add r0, r1, #1044480\n" // #0xff000
@@ -573,9 +620,8 @@
"ldr r0, [r0, #3805]\n"); // #0xedd
COMPARE_A32(Ldr(r0, MemOperand(r1, 0xfff123, PreIndex)),
- "mov ip, #61440\n" // #0xf000
- "movt ip, #255\n" // #0x00ff
- "add r1, ip\n"
+ "add r1, #1044480\n" // #0xff000
+ "add r1, #15728640\n" // #0x00f00000
"ldr r0, [r1, #291]!\n"); // #0x123
COMPARE_A32(Ldr(r0, MemOperand(r1, 0xff123, PreIndex)),
"add r1, #1044480\n" // #0xff000
@@ -585,9 +631,8 @@
"ldr r0, [r1, #3805]!\n"); // #0xedd
COMPARE_T32(Ldr(r0, MemOperand(r1, 0xfff12, PreIndex)),
- "mov ip, #65280\n" // #0xff00
- "movt ip, #15\n" // #0x000f
- "add r1, ip\n"
+ "add r1, #65280\n" // #0xff00
+ "add r1, #983040\n" // #0x000f0000
"ldr r0, [r1, #18]!\n"); // #0x12
COMPARE_T32(Ldr(r0, MemOperand(r1, 0xff12, PreIndex)),
"add r1, #65280\n" // #0xff00
@@ -595,17 +640,11 @@
COMPARE_T32(Ldr(r0, MemOperand(r1, -0xff12, PreIndex)),
"sub r1, #65536\n" // #0x10000
"ldr r0, [r1, #238]!\n"); // #0xee
- COMPARE_A32(Ldr(r0, MemOperand(r1, 0xfff123, PreIndex)),
- "mov ip, #61440\n" // #0xf000
- "movt ip, #255\n" // #0x00ff
- "add r1, ip\n"
- "ldr r0, [r1, #291]!\n"); // #0x123
COMPARE_A32(Ldr(r0, MemOperand(r1, 0xfff123, PostIndex)),
"ldr r0, [r1], #291\n" // #0x123
- "mov ip, #61440\n" // #0xf000
- "movt ip, #255\n" // #0x00ff
- "add r1, ip\n");
+ "add r1, #1044480\n" // #0xff000
+ "add r1, #15728640\n"); // #0x00f00000
COMPARE_A32(Ldr(r0, MemOperand(r1, 0xff123, PostIndex)),
"ldr r0, [r1], #291\n" // #0x123
"add r1, #1044480\n"); // #0xff000
@@ -615,9 +654,8 @@
COMPARE_T32(Ldr(r0, MemOperand(r1, 0xfff12, PostIndex)),
"ldr r0, [r1], #18\n" // #0x12
- "mov ip, #65280\n" // #0xff00
- "movt ip, #15\n" // #0x000f
- "add r1, ip\n");
+ "add r1, #65280\n" // #0xff00
+ "add r1, #983040\n"); // #0x000f0000
COMPARE_T32(Ldr(r0, MemOperand(r1, 0xff12, PostIndex)),
"ldr r0, [r1], #18\n" // #0x12
"add r1, #65280\n"); // #0xff00
@@ -625,33 +663,29 @@
"ldr r0, [r1], #238\n" // #0xee
"sub r1, #65536\n"); // #0x10000
- COMPARE_T32(Ldrh(r0, MemOperand(r1, 0xfff123)),
- "mov r0, #61440\n" // #0xf000
- "movt r0, #255\n" // #0x00ff
- "add r0, r1, r0\n"
- "ldrh r0, [r0, #291]\n"); // #0x123
COMPARE_A32(Ldrh(r0, MemOperand(r1, 0xfff123)),
- "mov r0, #61696\n" // #0xf100
- "movt r0, #255\n" // #0x00ff
- "add r0, r1, r0\n"
+ "add r0, r1, #61696\n" // #0xf100
+ "add r0, #16711680\n" // #0x00ff0000
"ldrh r0, [r0, #35]\n"); // #0x23
+ COMPARE_T32(Ldrh(r0, MemOperand(r1, 0xfff123)),
+ "add r0, r1, #1044480\n" // #0xff000
+ "add r0, #15728640\n" // #0x00f00000
+ "ldrh r0, [r0, #291]\n"); // #0x123
+ COMPARE_A32(Ldrh(r0, MemOperand(r1, 0xff123)),
+ "add r0, r1, #61696\n" // #0xf100
+ "add r0, #983040\n" // #0x000f0000
+ "ldrh r0, [r0, #35]\n"); // #0x23
COMPARE_T32(Ldrh(r0, MemOperand(r1, 0xff123)),
"add r0, r1, #1044480\n" // #0xff000
"ldrh r0, [r0, #291]\n"); // #0x123
- COMPARE_A32(Ldrh(r0, MemOperand(r1, 0xff123)),
- "mov r0, #61696\n" // #0xf100
- "movt r0, #15\n" // #0xf
- "add r0, r1, r0\n"
- "ldrh r0, [r0, #35]\n"); // #0x23
+ COMPARE_A32(Ldrh(r0, MemOperand(r1, -0xff123)),
+ "sub r0, r1, #61952\n" // #0xf200
+ "sub r0, #983040\n" // #0x000f0000
+ "ldrh r0, [r0, #221]\n"); // #0xdd
COMPARE_T32(Ldrh(r0, MemOperand(r1, -0xff123)),
"sub r0, r1, #1048576\n" // #0x100000
"ldrh r0, [r0, #3805]\n"); // #0xedd
- COMPARE_A32(Ldrh(r0, MemOperand(r1, -0xff123)),
- "mov r0, #61952\n" // #0xf200
- "movt r0, #15\n" // #0xf
- "sub r0, r1, r0\n"
- "ldrh r0, [r0, #221]\n"); // #0xdd
MUST_FAIL_TEST_BOTH(Ldr(r0, MemOperand(r0, 0xfff12, PreIndex)),
"Ill-formed 'ldr' instruction.\n");
@@ -868,7 +902,7 @@
"ldrd r0, r1, [r3]\n");
// Destination registers need to start with a even numbered register on A32.
MUST_FAIL_TEST_A32(Ldrd(r1, r2, MemOperand(r3)),
- "Ill-formed 'ldrd' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_T32(Ldrd(r1, r2, MemOperand(r3)),
"ldrd r1, r2, [r3]\n");
// Registers need to be adjacent on A32.
@@ -893,82 +927,121 @@
COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, -1020)),
"ldrd r0, r1, [r2, #-1020]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r2, 0xabcd)),
- "mov r0, #43981\n"
- "add r0, r2, r0\n"
- "ldrd r0, r1, [r0]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r2, -0xabcd)),
- "mov r0, #43981\n"
- "sub r0, r2, r0\n"
- "ldrd r0, r1, [r0]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, 0xabcc)),
+ "add r0, r2, #43776\n"
+ "ldrd r0, r1, [r0, #204]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, 0xabcc)),
+ "add r0, r2, #43008\n"
+ "ldrd r0, r1, [r0, #972]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, -0xabcc)),
+ "sub r0, r2, #44032\n"
+ "ldrd r0, r1, [r0, #52]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, -0xabcc)),
+ "sub r0, r2, #44032\n"
+ "ldrd r0, r1, [r0, #52]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, 0xabcdec)),
+ "add r0, r2, #52480\n"
+ "add r0, #11206656\n"
+ "ldrd r0, r1, [r0, #236]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, 0xabcdec)),
+ "add r0, r2, #248832\n"
+ "add r0, #11010048\n"
+ "ldrd r0, r1, [r0, #492]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, -0xabcdec)),
+ "sub r0, r2, #52736\n"
+ "sub r0, #11206656\n"
+ "ldrd r0, r1, [r0, #20]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, -0xabcdec)),
+ "sub r0, r2, #774144\n"
+ "sub r0, #10485760\n"
+ "ldrd r0, r1, [r0, #532]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r2, 0xabcdef)),
- "mov r0, #52719\n"
- "movt r0, #171\n"
- "add r0, r2, r0\n"
- "ldrd r0, r1, [r0]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r2, -0xabcdef)),
- "mov r0, #52719\n"
- "movt r0, #171\n"
- "sub r0, r2, r0\n"
- "ldrd r0, r1, [r0]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r0, 0xabcc)),
+ "add r1, r0, #43776\n"
+ "ldrd r0, r1, [r1, #204]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r0, 0xabcc)),
+ "add r1, r0, #43008\n"
+ "ldrd r0, r1, [r1, #972]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r0, -0xabcc)),
+ "sub r1, r0, #44032\n"
+ "ldrd r0, r1, [r1, #52]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r0, -0xabcc)),
+ "sub r1, r0, #44032\n"
+ "ldrd r0, r1, [r1, #52]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r0, 0xabcdec)),
+ "add r1, r0, #52480\n"
+ "add r1, #11206656\n"
+ "ldrd r0, r1, [r1, #236]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r0, 0xabcdec)),
+ "add r1, r0, #248832\n"
+ "add r1, #11010048\n"
+ "ldrd r0, r1, [r1, #492]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r0, -0xabcdec)),
+ "sub r1, r0, #52736\n"
+ "sub r1, #11206656\n"
+ "ldrd r0, r1, [r1, #20]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r0, -0xabcdec)),
+ "sub r1, r0, #774144\n"
+ "sub r1, #10485760\n"
+ "ldrd r0, r1, [r1, #532]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r0, 0xabcd)),
- "mov r1, #43981\n"
- "add r1, r0, r1\n"
- "ldrd r0, r1, [r1]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r0, -0xabcd)),
- "mov r1, #43981\n"
- "sub r1, r0, r1\n"
- "ldrd r0, r1, [r1]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r0, 0xabcdef)),
- "mov r1, #52719\n"
- "movt r1, #171\n"
- "add r1, r0, r1\n"
- "ldrd r0, r1, [r1]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r0, -0xabcdef)),
- "mov r1, #52719\n"
- "movt r1, #171\n"
- "sub r1, r0, r1\n"
- "ldrd r0, r1, [r1]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r1, 0xabcc)),
+ "add r0, r1, #43776\n"
+ "ldrd r0, r1, [r0, #204]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r1, 0xabcc)),
+ "add r0, r1, #43008\n"
+ "ldrd r0, r1, [r0, #972]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r1, -0xabcc)),
+ "sub r0, r1, #44032\n"
+ "ldrd r0, r1, [r0, #52]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r1, -0xabcc)),
+ "sub r0, r1, #44032\n"
+ "ldrd r0, r1, [r0, #52]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r1, 0xabcdec)),
+ "add r0, r1, #52480\n"
+ "add r0, #11206656\n"
+ "ldrd r0, r1, [r0, #236]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r1, 0xabcdec)),
+ "add r0, r1, #248832\n"
+ "add r0, #11010048\n"
+ "ldrd r0, r1, [r0, #492]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r1, -0xabcdec)),
+ "sub r0, r1, #52736\n"
+ "sub r0, #11206656\n"
+ "ldrd r0, r1, [r0, #20]\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r1, -0xabcdec)),
+ "sub r0, r1, #774144\n"
+ "sub r0, #10485760\n"
+ "ldrd r0, r1, [r0, #532]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r1, 0xabcd)),
- "mov r0, #43981\n"
- "add r0, r1, r0\n"
- "ldrd r0, r1, [r0]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r1, -0xabcd)),
- "mov r0, #43981\n"
- "sub r0, r1, r0\n"
- "ldrd r0, r1, [r0]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r1, 0xabcdef)),
- "mov r0, #52719\n"
- "movt r0, #171\n"
- "add r0, r1, r0\n"
- "ldrd r0, r1, [r0]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r1, -0xabcdef)),
- "mov r0, #52719\n"
- "movt r0, #171\n"
- "sub r0, r1, r0\n"
- "ldrd r0, r1, [r0]\n");
-
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r2, 0xabcd, PostIndex)),
- "ldrd r0, r1, [r2]\n"
- "mov ip, #43981\n"
- "add r2, ip\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r2, -0xabcd, PostIndex)),
- "ldrd r0, r1, [r2]\n"
- "mov ip, #43981\n"
- "sub r2, ip\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r2, 0xabcdef, PostIndex)),
- "ldrd r0, r1, [r2]\n"
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "add r2, ip\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r2, -0xabcdef, PostIndex)),
- "ldrd r0, r1, [r2]\n"
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "sub r2, ip\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, 0xabcc, PostIndex)),
+ "ldrd r0, r1, [r2], #204\n"
+ "add r2, #43776\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, 0xabcc, PostIndex)),
+ "ldrd r0, r1, [r2], #972\n"
+ "add r2, #43008\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, -0xabcc, PostIndex)),
+ "ldrd r0, r1, [r2], #52\n"
+ "sub r2, #44032\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, -0xabcc, PostIndex)),
+ "ldrd r0, r1, [r2], #52\n"
+ "sub r2, #44032\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, 0xabcdec, PostIndex)),
+ "ldrd r0, r1, [r2], #236\n"
+ "add r2, #52480\n"
+ "add r2, #11206656\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, 0xabcdec, PostIndex)),
+ "ldrd r0, r1, [r2], #492\n"
+ "add r2, #248832\n"
+ "add r2, #11010048\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, -0xabcdec, PostIndex)),
+ "ldrd r0, r1, [r2], #20\n"
+ "sub r2, #52736\n"
+ "sub r2, #11206656\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, -0xabcdec, PostIndex)),
+ "ldrd r0, r1, [r2], #532\n"
+ "sub r2, #774144\n"
+ "sub r2, #10485760\n");
// PostIndex with the same register as base and destination is invalid.
MUST_FAIL_TEST_BOTH(Ldrd(r0, r1, MemOperand(r0, 0xabcd, PostIndex)),
@@ -976,24 +1049,34 @@
MUST_FAIL_TEST_BOTH(Ldrd(r0, r1, MemOperand(r1, 0xabcdef, PostIndex)),
"Ill-formed 'ldrd' instruction.\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r0, 0xabcd, PreIndex)),
- "mov r1, #43981\n"
- "add r0, r1\n"
- "ldrd r0, r1, [r0]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r0, -0xabcd, PreIndex)),
- "mov r1, #43981\n"
- "sub r0, r1\n"
- "ldrd r0, r1, [r0]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r1, 0xabcdef, PreIndex)),
- "mov r0, #52719\n"
- "movt r0, #171\n"
- "add r1, r0\n"
- "ldrd r0, r1, [r1]\n");
- COMPARE_BOTH(Ldrd(r0, r1, MemOperand(r1, -0xabcdef, PreIndex)),
- "mov r0, #52719\n"
- "movt r0, #171\n"
- "sub r1, r0\n"
- "ldrd r0, r1, [r1]\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, 0xabcc, PreIndex)),
+ "add r2, #43776\n"
+ "ldrd r0, r1, [r2, #204]!\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, 0xabcc, PreIndex)),
+ "add r2, #43008\n"
+ "ldrd r0, r1, [r2, #972]!\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, -0xabcc, PreIndex)),
+ "sub r2, #44032\n"
+ "ldrd r0, r1, [r2, #52]!\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, -0xabcc, PreIndex)),
+ "sub r2, #44032\n"
+ "ldrd r0, r1, [r2, #52]!\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, 0xabcdec, PreIndex)),
+ "add r2, #52480\n"
+ "add r2, #11206656\n"
+ "ldrd r0, r1, [r2, #236]!\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, 0xabcdec, PreIndex)),
+ "add r2, #248832\n"
+ "add r2, #11010048\n"
+ "ldrd r0, r1, [r2, #492]!\n");
+ COMPARE_A32(Ldrd(r0, r1, MemOperand(r2, -0xabcdec, PreIndex)),
+ "sub r2, #52736\n"
+ "sub r2, #11206656\n"
+ "ldrd r0, r1, [r2, #20]!\n");
+ COMPARE_T32(Ldrd(r0, r1, MemOperand(r2, -0xabcdec, PreIndex)),
+ "sub r2, #774144\n"
+ "sub r2, #10485760\n"
+ "ldrd r0, r1, [r2, #532]!\n");
// - Tests with register offsets.
@@ -1040,18 +1123,18 @@
// First register is odd - rejected by the Assembler.
MUST_FAIL_TEST_A32(Ldrd(r1, r2, MemOperand(r0)),
- "Ill-formed 'ldrd' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Ldrd(r1, r2, MemOperand(r0, r0, PreIndex)),
- "Ill-formed 'ldrd' instruction.\n");
+ "Unpredictable instruction.\n");
// First register is odd - rejected by the MacroAssembler.
MUST_FAIL_TEST_A32(Ldrd(r1, r2, MemOperand(r0, 0xabcd, PreIndex)),
"Ill-formed 'ldrd' instruction.\n");
// First register is lr - rejected by the Assembler.
MUST_FAIL_TEST_A32(Ldrd(lr, pc, MemOperand(r0)),
- "Ill-formed 'ldrd' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Ldrd(lr, pc, MemOperand(r0, r0, PreIndex)),
- "Ill-formed 'ldrd' instruction.\n");
+ "Unpredictable instruction.\n");
// First register is lr - rejected by the MacroAssembler.
MUST_FAIL_TEST_A32(Ldrd(lr, pc, MemOperand(r0, 0xabcd, PreIndex)),
"Ill-formed 'ldrd' instruction.\n");
@@ -1072,7 +1155,7 @@
"strd r0, r1, [r3]\n");
// Destination registers need to start with a even numbered register on A32.
MUST_FAIL_TEST_A32(Strd(r1, r2, MemOperand(r3)),
- "Ill-formed 'strd' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_T32(Strd(r1, r2, MemOperand(r3)),
"strd r1, r2, [r3]\n");
// Registers need to be adjacent on A32.
@@ -1097,81 +1180,121 @@
COMPARE_T32(Strd(r0, r1, MemOperand(r2, -1020)),
"strd r0, r1, [r2, #-1020]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r2, 0xabcd)),
- "mov ip, #43981\n"
- "add ip, r2, ip\n"
- "strd r0, r1, [ip]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r2, -0xabcd)),
- "mov ip, #43981\n"
- "sub ip, r2, ip\n"
- "strd r0, r1, [ip]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r2, 0xabcdef)),
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "add ip, r2, ip\n"
- "strd r0, r1, [ip]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r2, -0xabcdef)),
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "sub ip, r2, ip\n"
- "strd r0, r1, [ip]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, 0xabcc)),
+ "add ip, r2, #43776\n"
+ "strd r0, r1, [ip, #204]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, 0xabcc)),
+ "add ip, r2, #43008\n"
+ "strd r0, r1, [ip, #972]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, -0xabcc)),
+ "sub ip, r2, #44032\n"
+ "strd r0, r1, [ip, #52]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, -0xabcc)),
+ "sub ip, r2, #44032\n"
+ "strd r0, r1, [ip, #52]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, 0xabcdec)),
+ "add ip, r2, #52480\n"
+ "add ip, #11206656\n"
+ "strd r0, r1, [ip, #236]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, 0xabcdec)),
+ "add ip, r2, #248832\n"
+ "add ip, #11010048\n"
+ "strd r0, r1, [ip, #492]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, -0xabcdec)),
+ "sub ip, r2, #52736\n"
+ "sub ip, #11206656\n"
+ "strd r0, r1, [ip, #20]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, -0xabcdec)),
+ "sub ip, r2, #774144\n"
+ "sub ip, #10485760\n"
+ "strd r0, r1, [ip, #532]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r0, 0xabcd)),
- "mov ip, #43981\n"
- "add ip, r0, ip\n"
- "strd r0, r1, [ip]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r0, -0xabcd)),
- "mov ip, #43981\n"
- "sub ip, r0, ip\n"
- "strd r0, r1, [ip]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r0, 0xabcdef)),
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "add ip, r0, ip\n"
- "strd r0, r1, [ip]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r0, -0xabcdef)),
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "sub ip, r0, ip\n"
- "strd r0, r1, [ip]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r0, 0xabcc)),
+ "add ip, r0, #43776\n"
+ "strd r0, r1, [ip, #204]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r0, 0xabcc)),
+ "add ip, r0, #43008\n"
+ "strd r0, r1, [ip, #972]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r0, -0xabcc)),
+ "sub ip, r0, #44032\n"
+ "strd r0, r1, [ip, #52]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r0, -0xabcc)),
+ "sub ip, r0, #44032\n"
+ "strd r0, r1, [ip, #52]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r0, 0xabcdec)),
+ "add ip, r0, #52480\n"
+ "add ip, #11206656\n"
+ "strd r0, r1, [ip, #236]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r0, 0xabcdec)),
+ "add ip, r0, #248832\n"
+ "add ip, #11010048\n"
+ "strd r0, r1, [ip, #492]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r0, -0xabcdec)),
+ "sub ip, r0, #52736\n"
+ "sub ip, #11206656\n"
+ "strd r0, r1, [ip, #20]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r0, -0xabcdec)),
+ "sub ip, r0, #774144\n"
+ "sub ip, #10485760\n"
+ "strd r0, r1, [ip, #532]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r1, 0xabcd)),
- "mov ip, #43981\n"
- "add ip, r1, ip\n"
- "strd r0, r1, [ip]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r1, -0xabcd)),
- "mov ip, #43981\n"
- "sub ip, r1, ip\n"
- "strd r0, r1, [ip]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r1, 0xabcdef)),
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "add ip, r1, ip\n"
- "strd r0, r1, [ip]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r1, -0xabcdef)),
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "sub ip, r1, ip\n"
- "strd r0, r1, [ip]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r1, 0xabcc)),
+ "add ip, r1, #43776\n"
+ "strd r0, r1, [ip, #204]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r1, 0xabcc)),
+ "add ip, r1, #43008\n"
+ "strd r0, r1, [ip, #972]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r1, -0xabcc)),
+ "sub ip, r1, #44032\n"
+ "strd r0, r1, [ip, #52]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r1, -0xabcc)),
+ "sub ip, r1, #44032\n"
+ "strd r0, r1, [ip, #52]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r1, 0xabcdec)),
+ "add ip, r1, #52480\n"
+ "add ip, #11206656\n"
+ "strd r0, r1, [ip, #236]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r1, 0xabcdec)),
+ "add ip, r1, #248832\n"
+ "add ip, #11010048\n"
+ "strd r0, r1, [ip, #492]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r1, -0xabcdec)),
+ "sub ip, r1, #52736\n"
+ "sub ip, #11206656\n"
+ "strd r0, r1, [ip, #20]\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r1, -0xabcdec)),
+ "sub ip, r1, #774144\n"
+ "sub ip, #10485760\n"
+ "strd r0, r1, [ip, #532]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r2, 0xabcd, PostIndex)),
- "strd r0, r1, [r2]\n"
- "mov ip, #43981\n"
- "add r2, ip\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r2, -0xabcd, PostIndex)),
- "strd r0, r1, [r2]\n"
- "mov ip, #43981\n"
- "sub r2, ip\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r2, 0xabcdef, PostIndex)),
- "strd r0, r1, [r2]\n"
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "add r2, ip\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r2, -0xabcdef, PostIndex)),
- "strd r0, r1, [r2]\n"
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "sub r2, ip\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, 0xabcc, PostIndex)),
+ "strd r0, r1, [r2], #204\n"
+ "add r2, #43776\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, 0xabcc, PostIndex)),
+ "strd r0, r1, [r2], #972\n"
+ "add r2, #43008\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, -0xabcc, PostIndex)),
+ "strd r0, r1, [r2], #52\n"
+ "sub r2, #44032\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, -0xabcc, PostIndex)),
+ "strd r0, r1, [r2], #52\n"
+ "sub r2, #44032\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, 0xabcdec, PostIndex)),
+ "strd r0, r1, [r2], #236\n"
+ "add r2, #52480\n"
+ "add r2, #11206656\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, 0xabcdec, PostIndex)),
+ "strd r0, r1, [r2], #492\n"
+ "add r2, #248832\n"
+ "add r2, #11010048\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, -0xabcdec, PostIndex)),
+ "strd r0, r1, [r2], #20\n"
+ "sub r2, #52736\n"
+ "sub r2, #11206656\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, -0xabcdec, PostIndex)),
+ "strd r0, r1, [r2], #532\n"
+ "sub r2, #774144\n"
+ "sub r2, #10485760\n");
// PostIndex with the same register as base and source is invalid.
MUST_FAIL_TEST_BOTH(Strd(r0, r1, MemOperand(r0, 0xabcd, PostIndex)),
@@ -1179,24 +1302,34 @@
MUST_FAIL_TEST_BOTH(Strd(r0, r1, MemOperand(r1, 0xabcdef, PostIndex)),
"Ill-formed 'strd' instruction.\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r0, 0xabcd, PreIndex)),
- "mov ip, #43981\n"
- "add r0, ip\n"
- "strd r0, r1, [r0]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r0, -0xabcd, PreIndex)),
- "mov ip, #43981\n"
- "sub r0, ip\n"
- "strd r0, r1, [r0]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r1, 0xabcdef, PreIndex)),
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "add r1, ip\n"
- "strd r0, r1, [r1]\n");
- COMPARE_BOTH(Strd(r0, r1, MemOperand(r1, -0xabcdef, PreIndex)),
- "mov ip, #52719\n"
- "movt ip, #171\n"
- "sub r1, ip\n"
- "strd r0, r1, [r1]\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, 0xabcc, PreIndex)),
+ "add r2, #43776\n"
+ "strd r0, r1, [r2, #204]!\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, 0xabcc, PreIndex)),
+ "add r2, #43008\n"
+ "strd r0, r1, [r2, #972]!\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, -0xabcc, PreIndex)),
+ "sub r2, #44032\n"
+ "strd r0, r1, [r2, #52]!\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, -0xabcc, PreIndex)),
+ "sub r2, #44032\n"
+ "strd r0, r1, [r2, #52]!\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, 0xabcdec, PreIndex)),
+ "add r2, #52480\n"
+ "add r2, #11206656\n"
+ "strd r0, r1, [r2, #236]!\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, 0xabcdec, PreIndex)),
+ "add r2, #248832\n"
+ "add r2, #11010048\n"
+ "strd r0, r1, [r2, #492]!\n");
+ COMPARE_A32(Strd(r0, r1, MemOperand(r2, -0xabcdec, PreIndex)),
+ "sub r2, #52736\n"
+ "sub r2, #11206656\n"
+ "strd r0, r1, [r2, #20]!\n");
+ COMPARE_T32(Strd(r0, r1, MemOperand(r2, -0xabcdec, PreIndex)),
+ "sub r2, #774144\n"
+ "sub r2, #10485760\n"
+ "strd r0, r1, [r2, #532]!\n");
// - Tests with register offsets.
@@ -1243,18 +1376,18 @@
// First register is odd - rejected by the Assembler.
MUST_FAIL_TEST_A32(Strd(r1, r2, MemOperand(r0)),
- "Ill-formed 'strd' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Strd(r1, r2, MemOperand(r0, r0, PreIndex)),
- "Ill-formed 'strd' instruction.\n");
+ "Unpredictable instruction.\n");
// First register is odd - rejected by the MacroAssembler.
MUST_FAIL_TEST_A32(Strd(r1, r2, MemOperand(r0, 0xabcd, PreIndex)),
"Ill-formed 'strd' instruction.\n");
// First register is lr - rejected by the Assembler.
MUST_FAIL_TEST_A32(Strd(lr, pc, MemOperand(r0)),
- "Ill-formed 'strd' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Strd(lr, pc, MemOperand(r0, r0, PreIndex)),
- "Ill-formed 'strd' instruction.\n");
+ "Unpredictable instruction.\n");
// First register is lr - rejected by the MacroAssembler.
MUST_FAIL_TEST_A32(Strd(lr, pc, MemOperand(r0, 0xabcd, PreIndex)),
"Ill-formed 'strd' instruction.\n");
@@ -1306,7 +1439,7 @@
"tst r0, r0\n");
COMPARE_A32(Movs(pc, 0x1),
"movs pc, #1\n");
- MUST_FAIL_TEST_T32(Movs(pc, 0x1), "Ill-formed 'movs' instruction.\n");
+ MUST_FAIL_TEST_T32(Movs(pc, 0x1), "Unpredictable instruction.\n");
MUST_FAIL_TEST_BOTH(Movs(pc, 0xbadbeed),
"Ill-formed 'movs' instruction.\n");
@@ -1513,11 +1646,16 @@
TEST(macro_assembler_Cbz) {
SETUP();
+#ifdef VIXL_INCLUDE_TARGET_A32
// Cbz/Cbnz are not available in A32 mode.
+ // Make sure GetArchitectureStatePCOffset() returns the correct value.
+ __ UseA32();
Label label_64(__ GetCursorOffset() + __ GetArchitectureStatePCOffset(), 64);
MUST_FAIL_TEST_A32(Cbz(r0, &label_64), "Cbz is only available for T32.\n");
MUST_FAIL_TEST_A32(Cbnz(r0, &label_64), "Cbnz is only available for T32.\n");
+#endif
+#ifdef VIXL_INCLUDE_TARGET_T32
// Make sure GetArchitectureStatePCOffset() returns the correct value.
__ UseT32();
// Largest encodable offset.
@@ -1562,6 +1700,7 @@
COMPARE_T32(Cbnz(r0, &label_neg128),
"cbz r0, 0x00000004\n"
"b 0xffffff84\n");
+#endif
CLEANUP();
}
@@ -1577,13 +1716,12 @@
"add ip, r8, #1371\n" \
STRING_OP # DST_REG ", [ip]\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r8, 4113)), \
- "mov ip, #4113\n" \
- "add ip, r8, ip\n" \
+ "add ip, r8, #17\n" \
+ "add ip, #4096\n" \
STRING_OP # DST_REG ", [ip]\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r8, 65808)), \
- "mov ip, #272\n" \
- "movt ip, #1\n" \
- "add ip, r8, ip\n" \
+ "add ip, r8, #272\n" \
+ "add ip, #65536\n" \
STRING_OP # DST_REG ", [ip]\n"); \
\
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r8, -1024)), \
@@ -1593,13 +1731,12 @@
"sub ip, r8, #1371\n" \
STRING_OP # DST_REG ", [ip]\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r8, -4113)), \
- "mov ip, #4113\n" \
- "sub ip, r8, ip\n" \
+ "sub ip, r8, #17\n" \
+ "sub ip, #4096\n" \
STRING_OP # DST_REG ", [ip]\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r8, -65808)), \
- "mov ip, #272\n" \
- "movt ip, #1\n" \
- "sub ip, r8, ip\n" \
+ "sub ip, r8, #272\n" \
+ "sub ip, #65536\n" \
STRING_OP # DST_REG ", [ip]\n"); \
\
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r9, 0, PreIndex)), \
@@ -1608,26 +1745,24 @@
"add r9, #137\n" \
STRING_OP # DST_REG ", [r9]\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r9, 4110, PreIndex)), \
- "mov ip, #4110\n" \
- "add r9, ip\n" \
+ "add r9, #14\n" \
+ "add r9, #4096\n" \
STRING_OP # DST_REG ", [r9]\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r9, 65623, PreIndex)), \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "add r9, ip\n" \
+ "add r9, #87\n" \
+ "add r9, #65536\n" \
STRING_OP # DST_REG ", [r9]\n"); \
\
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r9, -137, PreIndex)), \
"sub r9, #137\n" \
STRING_OP # DST_REG ", [r9]\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r9, -4110, PreIndex)), \
- "mov ip, #4110\n" \
- "sub r9, ip\n" \
+ "sub r9, #14\n" \
+ "sub r9, #4096\n" \
STRING_OP # DST_REG ", [r9]\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r9, -65623, PreIndex)), \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "sub r9, ip\n" \
+ "sub r9, #87\n" \
+ "sub r9, #65536\n" \
STRING_OP # DST_REG ", [r9]\n"); \
\
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r10, 0, PostIndex)), \
@@ -1637,26 +1772,24 @@
"add r10, #137\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r10, 4110, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
- "mov ip, #4110\n" \
- "add r10, ip\n"); \
+ "add r10, #14\n" \
+ "add r10, #4096\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r10, 65623, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "add r10, ip\n"); \
+ "add r10, #87\n" \
+ "add r10, #65536\n"); \
\
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r10, -137, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
"sub r10, #137\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r10, -4110, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
- "mov ip, #4110\n" \
- "sub r10, ip\n"); \
+ "sub r10, #14\n" \
+ "sub r10, #4096\n"); \
COMPARE_T32(MACRO_OP(DST_REG, MemOperand(r10, -65623, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "sub r10, ip\n"); \
+ "sub r10, #87\n" \
+ "sub r10, #65536\n"); \
CLEANUP();
TEST(macro_assembler_T32_Vldr_d) {
@@ -1684,26 +1817,24 @@
"add ip, r8, #137\n" \
STRING_OP # DST_REG ", [ip]\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r8, 274)), \
- "mov ip, #274\n" \
- "add ip, r8, ip\n" \
+ "add ip, r8, #18\n" \
+ "add ip, #256\n" \
STRING_OP # DST_REG ", [ip]\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r8, 65623)), \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "add ip, r8, ip\n" \
+ "add ip, r8, #87\n" \
+ "add ip, #65536\n" \
STRING_OP # DST_REG ", [ip]\n"); \
\
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r8, -137)), \
"sub ip, r8, #137\n" \
STRING_OP # DST_REG ", [ip]\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r8, -274)), \
- "mov ip, #274\n" \
- "sub ip, r8, ip\n" \
+ "sub ip, r8, #18\n" \
+ "sub ip, #256\n" \
STRING_OP # DST_REG ", [ip]\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r8, -65623)), \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "sub ip, r8, ip\n" \
+ "sub ip, r8, #87\n" \
+ "sub ip, #65536\n" \
STRING_OP # DST_REG ", [ip]\n"); \
\
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r9, 0, PreIndex)), \
@@ -1712,26 +1843,24 @@
"add r9, #137\n" \
STRING_OP # DST_REG ", [r9]\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r9, 274, PreIndex)), \
- "mov ip, #274\n" \
- "add r9, ip\n" \
+ "add r9, #18\n" \
+ "add r9, #256\n" \
STRING_OP # DST_REG ", [r9]\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r9, 65623, PreIndex)), \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "add r9, ip\n" \
+ "add r9, #87\n" \
+ "add r9, #65536\n" \
STRING_OP # DST_REG ", [r9]\n"); \
\
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r9, -137, PreIndex)), \
"sub r9, #137\n" \
STRING_OP # DST_REG ", [r9]\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r9, -274, PreIndex)), \
- "mov ip, #274\n" \
- "sub r9, ip\n" \
+ "sub r9, #18\n" \
+ "sub r9, #256\n" \
STRING_OP # DST_REG ", [r9]\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r9, -65623, PreIndex)), \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "sub r9, ip\n" \
+ "sub r9, #87\n" \
+ "sub r9, #65536\n" \
STRING_OP # DST_REG ", [r9]\n"); \
\
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r10, 0, PostIndex)), \
@@ -1741,26 +1870,24 @@
"add r10, #137\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r10, 274, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
- "mov ip, #274\n" \
- "add r10, ip\n"); \
+ "add r10, #18\n" \
+ "add r10, #256\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r10, 65623, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "add r10, ip\n"); \
+ "add r10, #87\n" \
+ "add r10, #65536\n"); \
\
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r10, -137, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
"sub r10, #137\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r10, -274, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
- "mov ip, #274\n" \
- "sub r10, ip\n"); \
+ "sub r10, #18\n" \
+ "sub r10, #256\n"); \
COMPARE_A32(MACRO_OP(DST_REG, MemOperand(r10, -65623, PostIndex)), \
STRING_OP # DST_REG ", [r10]\n" \
- "mov ip, #87\n" \
- "movt ip, #1\n" \
- "sub r10, ip\n"); \
+ "sub r10, #87\n" \
+ "sub r10, #65536\n"); \
CLEANUP();
@@ -2060,7 +2187,7 @@
// Deprecated, but accepted:
SHOULD_FAIL_TEST_A32(Push(RegisterList(pc)));
// Whereas we don't accept the single-register version:
- MUST_FAIL_TEST_A32(Push(pc), "Ill-formed 'push' instruction.\n");
+ MUST_FAIL_TEST_A32(Push(pc), "Unpredictable instruction.\n");
// For T32, pushing the PC is allowed:
COMPARE_T32(Push(pc), "push {pc}\n");
@@ -2145,72 +2272,72 @@
COMPARE_A32(Adc(pc, r0, 1), "adc pc, r0, #1\n");
COMPARE_A32(Adc(r0, pc, 1), "adc r0, pc, #1\n");
MUST_FAIL_TEST_T32(Adc(pc, r0, 1),
- "Ill-formed 'adc' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Adc(r0, pc, 1),
- "Ill-formed 'adc' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_A32(Adcs(pc, r0, 1), "adcs pc, r0, #1\n");
COMPARE_A32(Adcs(r0, pc, 1), "adcs r0, pc, #1\n");
MUST_FAIL_TEST_T32(Adcs(pc, r0, 1),
- "Ill-formed 'adcs' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Adcs(r0, pc, 1),
- "Ill-formed 'adcs' instruction.\n");
+ "Unpredictable instruction.\n");
// ADC, ADCS (register).
COMPARE_A32(Adc(pc, r0, r1), "adc pc, r0, r1\n");
COMPARE_A32(Adc(r0, pc, r1), "adc r0, pc, r1\n");
COMPARE_A32(Adc(r0, r1, pc), "adc r0, r1, pc\n");
MUST_FAIL_TEST_T32(Adc(pc, r0, r1),
- "Ill-formed 'adc' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Adc(r0, pc, r1),
- "Ill-formed 'adc' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Adc(r0, r1, pc),
- "Ill-formed 'adc' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_A32(Adcs(pc, r0, r1), "adcs pc, r0, r1\n");
COMPARE_A32(Adcs(r0, pc, r1), "adcs r0, pc, r1\n");
COMPARE_A32(Adcs(r0, r1, pc), "adcs r0, r1, pc\n");
MUST_FAIL_TEST_T32(Adcs(pc, r0, r1),
- "Ill-formed 'adcs' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Adcs(r0, pc, r1),
- "Ill-formed 'adcs' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Adcs(r0, r1, pc),
- "Ill-formed 'adcs' instruction.\n");
+ "Unpredictable instruction.\n");
// ADC, ADCS (register-shifted register).
MUST_FAIL_TEST_A32(Adc(pc, r0, Operand(r1, LSL, r2)),
- "Ill-formed 'adc' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adc(r0, pc, Operand(r1, LSL, r2)),
- "Ill-formed 'adc' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adc(r0, r1, Operand(pc, LSL, r2)),
- "Ill-formed 'adc' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adc(r0, r1, Operand(r2, LSL, pc)),
- "Ill-formed 'adc' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adcs(pc, r0, Operand(r1, LSL, r2)),
- "Ill-formed 'adcs' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adcs(r0, pc, Operand(r1, LSL, r2)),
- "Ill-formed 'adcs' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adcs(r0, r1, Operand(pc, LSL, r2)),
- "Ill-formed 'adcs' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adcs(r0, r1, Operand(r2, LSL, pc)),
- "Ill-formed 'adcs' instruction.\n");
+ "Unpredictable instruction.\n");
// ADD (immediate, to PC).
COMPARE_A32(Add(r0, pc, 1), "adr r0, 0x00000009\n");
COMPARE_T32(Add(r0, pc, 1), "adr r0, 0x00000005\n");
COMPARE_A32(Add(pc, pc, 1), "adr pc, 0x00000009\n");
MUST_FAIL_TEST_T32(Add(pc, pc, 1),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
// ADD, ADDS (immediate).
COMPARE_A32(Add(pc, r0, 1), "add pc, r0, #1\n");
MUST_FAIL_TEST_T32(Add(pc, r0, 1),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Add(pc, r0, 0x123),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_A32(Adds(pc, r0, 1), "adds pc, r0, #1\n");
COMPARE_A32(Adds(r0, pc, 1), "adds r0, pc, #1\n");
// TODO: Try to make these error messages more consistent.
MUST_FAIL_TEST_T32(Adds(r0, pc, 1),
- "Ill-formed 'adds' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Adds(r0, pc, 0x123),
"Ill-formed 'adds' instruction.\n");
@@ -2221,46 +2348,46 @@
COMPARE_T32(Add(r0, r0, pc), "add r0, pc\n");
COMPARE_T32(Add(pc, pc, r0), "add pc, r0\n");
MUST_FAIL_TEST_T32(Add(pc, pc, pc),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Add(pc, r0, r1),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Add(r0, pc, r1),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Add(r0, r1, pc),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_A32(Adds(pc, r0, r1), "adds pc, r0, r1\n");
COMPARE_A32(Adds(r0, pc, r1), "adds r0, pc, r1\n");
COMPARE_A32(Adds(r0, r1, pc), "adds r0, r1, pc\n");
MUST_FAIL_TEST_T32(Adds(r0, pc, r1),
- "Ill-formed 'adds' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_T32(Adds(r0, r1, pc),
- "Ill-formed 'adds' instruction.\n");
+ "Unpredictable instruction.\n");
// ADD, ADDS (register-shifted register)
MUST_FAIL_TEST_A32(Add(pc, r0, Operand(r1, LSL, r2)),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Add(r0, pc, Operand(r1, LSL, r2)),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Add(r0, r1, Operand(pc, LSL, r2)),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Add(r0, r1, Operand(r2, LSL, pc)),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_A32(Add(pc, sp, 1), "add pc, sp, #1\n");
MUST_FAIL_TEST_T32(Add(pc, sp, 1),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adds(pc, r0, Operand(r1, LSL, r2)),
- "Ill-formed 'adds' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adds(r0, pc, Operand(r1, LSL, r2)),
- "Ill-formed 'adds' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adds(r0, r1, Operand(pc, LSL, r2)),
- "Ill-formed 'adds' instruction.\n");
+ "Unpredictable instruction.\n");
MUST_FAIL_TEST_A32(Adds(r0, r1, Operand(r2, LSL, pc)),
- "Ill-formed 'adds' instruction.\n");
+ "Unpredictable instruction.\n");
// ADD, ADDS (SP plus immediate).
COMPARE_A32(Add(pc, sp, 1), "add pc, sp, #1\n");
MUST_FAIL_TEST_T32(Add(pc, sp, 1),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_A32(Adds(pc, sp, 1), "adds pc, sp, #1\n");
MUST_FAIL_TEST_T32(Adds(pc, sp, 1),
"Ill-formed 'adds' instruction.\n");
@@ -2268,10 +2395,10 @@
// ADD, ADDS (SP plus register).
COMPARE_A32(Add(pc, sp, r0), "add pc, sp, r0\n");
MUST_FAIL_TEST_T32(Add(pc, sp, r0),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_A32(Add(r0, sp, pc), "add r0, sp, pc\n");
MUST_FAIL_TEST_T32(Add(r0, sp, pc),
- "Ill-formed 'add' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_BOTH(Add(pc, sp, pc), "add pc, sp, pc\n");
COMPARE_BOTH(Add(sp, sp, pc), "add sp, pc\n");
COMPARE_A32(Adds(pc, sp, r0), "adds pc, sp, r0\n");
@@ -2279,13 +2406,13 @@
"Ill-formed 'adds' instruction.\n");
COMPARE_A32(Adds(r0, sp, pc), "adds r0, sp, pc\n");
MUST_FAIL_TEST_T32(Adds(r0, sp, pc),
- "Ill-formed 'adds' instruction.\n");
+ "Unpredictable instruction.\n");
COMPARE_A32(Adds(pc, sp, pc), "adds pc, sp, pc\n");
MUST_FAIL_TEST_T32(Adds(pc, sp, pc),
"Ill-formed 'adds' instruction.\n");
COMPARE_A32(Adds(sp, sp, pc), "adds sp, pc\n");
MUST_FAIL_TEST_T32(Adds(sp, sp, pc),
- "Ill-formed 'adds' instruction.\n");
+ "Unpredictable instruction.\n");
// ADR.
{
@@ -2293,35 +2420,32 @@
masm.Bind(&label);
COMPARE_A32(Adr(pc, &label), "adr pc, 0x00000000\n");
MUST_FAIL_TEST_T32(Adr(pc, &label),
- "Ill-formed 'adr' instruction.\n");
+ "Unpredictable instruction.\n");
}
+ // CLZ.
+ MUST_FAIL_TEST_BOTH(Clz(pc, r0), "Unpredictable instruction.\n");
+ MUST_FAIL_TEST_BOTH(Clz(r0, pc), "Unpredictable instruction.\n");
+
// MOV, MOVS (immediate).
COMPARE_A32(Mov(pc, 1), "mov pc, #1\n");
- MUST_FAIL_TEST_T32(Mov(pc, 1),
- "Unpredictable instruction.\n");
- MUST_FAIL_TEST_BOTH(Mov(pc, 0xfff),
- "Unpredictable instruction.\n");
+ MUST_FAIL_TEST_T32(Mov(pc, 1), "Unpredictable instruction.\n");
+ MUST_FAIL_TEST_T32(Mov(pc, 0xfff), "Unpredictable instruction.\n");
COMPARE_A32(Mov(pc, 0xf000), "mov pc, #61440\n");
- MUST_FAIL_TEST_T32(Mov(pc, 0xf000),
- "Unpredictable instruction.\n");
+ MUST_FAIL_TEST_T32(Mov(pc, 0xf000), "Unpredictable instruction.\n");
COMPARE_A32(Movs(pc, 1), "movs pc, #1\n");
- MUST_FAIL_TEST_T32(Movs(pc, 1),
- "Unpredictable instruction.\n");
+ MUST_FAIL_TEST_T32(Movs(pc, 1), "Unpredictable instruction.\n");
MUST_FAIL_TEST_BOTH(Movs(pc, 0xfff),
"Ill-formed 'movs' instruction.\n");
COMPARE_A32(Movs(pc, 0xf000), "movs pc, #61440\n");
- MUST_FAIL_TEST_T32(Movs(pc, 0xf000),
- "Unpredictable instruction.\n");
+ MUST_FAIL_TEST_T32(Movs(pc, 0xf000), "Unpredictable instruction.\n");
// MOV, MOVS (register).
COMPARE_BOTH(Mov(pc, r0), "mov pc, r0\n");
COMPARE_BOTH(Mov(r0, pc), "mov r0, pc\n");
- MUST_FAIL_TEST_BOTH(Movs(pc, r0),
- "Unpredictable instruction.\n");
+ MUST_FAIL_TEST_BOTH(Movs(pc, r0), "Unpredictable instruction.\n");
COMPARE_A32(Movs(r0, pc), "movs r0, pc\n");
- MUST_FAIL_TEST_T32(Movs(r0, pc),
- "Unpredictable instruction.\n");
+ MUST_FAIL_TEST_T32(Movs(r0, pc), "Unpredictable instruction.\n");
// MOV, MOVS (register-shifted register).
MUST_FAIL_TEST_BOTH(Mov(pc, Operand(r0, ASR, r1)),
@@ -2370,18 +2494,17 @@
MUST_FAIL_TEST_A32(Add(r0, pc, 0x10001), "Ill-formed 'add' instruction.\n");
MUST_FAIL_TEST_A32(Add(r0, pc, 0x12345678), "Ill-formed 'add' instruction.\n");
MUST_FAIL_TEST_A32(Add(r0, pc, 0x7fffffff), "Ill-formed 'add' instruction.\n");
- COMPARE_A32(Add(r0, pc, -1025), "mov r0, pc\n"
- "mov ip, #1025\n"
- "sub r0, ip\n");
- COMPARE_A32(Add(r0, pc, -0xffff), "mov r0, pc\n"
- "mov ip, #65535\n"
- "sub r0, ip\n");
- COMPARE_A32(Add(r0, pc, -0x10001), "mov r0, pc\n"
- "mov ip, #1\n"
- "movt ip, #1\n"
- "sub r0, ip\n");
- COMPARE_A32(Add(r0, pc, -0x12345678), "mov r0, pc\n"
- "mov ip, #22136\n"
+ COMPARE_A32(Add(r0, pc, -1025), "adr r0, 0x00000007\n"
+ "sub r0, #1024\n");
+ COMPARE_A32(Add(r0, pc, -0xffff), "adr r0, 0xffffff09\n"
+ "sub r0, #65280\n");
+ COMPARE_A32(Add(r0, pc, -0x10001), "adr r0, 0x00000007\n"
+ "sub r0, #65536\n");
+ COMPARE_A32(Add(r0, pc, -0x2345678), "adr r0, 0xfffffd90\n"
+ "sub r0, #21504\n"
+ "sub r0, #36962304\n");
+ COMPARE_A32(Add(r0, pc, -0x12345678), "adr r0, 0xfffffd90\n"
+ "mov ip, #21504\n"
"movt ip, #4660\n"
"sub r0, ip\n");
@@ -2389,23 +2512,22 @@
MUST_FAIL_TEST_A32(Sub(r0, pc, -0xffff), "Ill-formed 'add' instruction.\n");
MUST_FAIL_TEST_A32(Sub(r0, pc, -0x10001), "Ill-formed 'add' instruction.\n");
MUST_FAIL_TEST_A32(Sub(r0, pc, -0x12345678), "Ill-formed 'add' instruction.\n");
- COMPARE_A32(Sub(r0, pc, 1025), "mov r0, pc\n"
- "mov ip, #1025\n"
- "sub r0, ip\n");
- COMPARE_A32(Sub(r0, pc, 0xffff), "mov r0, pc\n"
- "mov ip, #65535\n"
- "sub r0, ip\n");
- COMPARE_A32(Sub(r0, pc, 0x10001), "mov r0, pc\n"
- "mov ip, #1\n"
- "movt ip, #1\n"
- "sub r0, ip\n");
- COMPARE_A32(Sub(r0, pc, 0x12345678), "mov r0, pc\n"
- "mov ip, #22136\n"
+ COMPARE_A32(Sub(r0, pc, 1025), "adr r0, 0x00000007\n"
+ "sub r0, #1024\n");
+ COMPARE_A32(Sub(r0, pc, 0xffff), "adr r0, 0xffffff09\n"
+ "sub r0, #65280\n");
+ COMPARE_A32(Sub(r0, pc, 0x10001), "adr r0, 0x00000007\n"
+ "sub r0, #65536\n");
+ COMPARE_A32(Sub(r0, pc, 0x2345678), "adr r0, 0xfffffd90\n"
+ "sub r0, #21504\n"
+ "sub r0, #36962304\n");
+ COMPARE_A32(Sub(r0, pc, 0x12345678), "adr r0, 0xfffffd90\n"
+ "mov ip, #21504\n"
"movt ip, #4660\n"
"sub r0, ip\n");
- COMPARE_A32(Sub(r0, pc, 0x7fffffff), "mov r0, pc\n"
- "mvn ip, #2147483648\n"
- "sub r0, ip\n");
+ COMPARE_A32(Sub(r0, pc, 0x7fffffff), "adr r0, 0xffffff09\n"
+ "add r0, #256\n"
+ "add r0, #2147483648\n");
CLEANUP();
}
@@ -2436,7 +2558,7 @@
// Only negative offsets are supported, because the proper behaviour for
// positive offsets is not clear.
- MUST_FAIL_TEST_T32(Add(r0, pc, 4096), "Ill-formed 'add' instruction.\n");
+ MUST_FAIL_TEST_T32(Add(r0, pc, 4096), "Unpredictable instruction.\n");
// TODO: This case is incorrect; the instruction is unpredictable. The test
// must be updated once the bug is fixed.
@@ -2451,10 +2573,14 @@
"movt ip, #4660\n"
"sub r0, ip\n");
COMPARE_T32(Add(r0, pc, -0x7fffffff), "mov r0, pc\n"
- "mvn ip, #2147483648\n"
- "sub r0, ip\n");
+ "add r0, #1\n"
+ "add r0, #2147483648\n");
- MUST_FAIL_TEST_T32(Sub(r0, pc, -4096), "Ill-formed 'add' instruction.\n");
+ // TODO: This test aborts in the Assembler (with unpredictable instruction
+ // errors) before the MacroAssembler gets a chance to do something
+ // predictable.
+ // COMPARE_T32(Sub(r0, pc, -4096), "mov r0, pc\n"
+ // "add r0, #4096\n");
// TODO: This case is incorrect; the instruction is unpredictable. The test
// must be updated once the bug is fixed.
@@ -2469,8 +2595,8 @@
"movt ip, #4660\n"
"sub r0, ip\n");
COMPARE_T32(Sub(r0, pc, 0x7fffffff), "mov r0, pc\n"
- "mvn ip, #2147483648\n"
- "sub r0, ip\n");
+ "add r0, #1\n"
+ "add r0, #2147483648\n");
CLEANUP();
}
@@ -3335,8 +3461,8 @@
r1,
0xffffffff,
0xfff)),
- "sub r2, r1, #4096\n"
- "ldr r0, [r2, #4095]\n");
+ "sub r2, r1, #1\n"
+ "ldr r0, [r2]\n");
// TODO: Improve the code generation for these cases.
@@ -3352,17 +3478,15 @@
r1,
0x7fffffff,
0xfff)),
- "mov r2, #61440\n"
- "movt r2, #32767\n"
- "add r2, r1, r2\n"
- "ldr r0, [r2, #4095]\n");
+ "sub r2, r1, #1\n"
+ "sub r2, #2147483648\n"
+ "ldr r0, [r2]\n");
COMPARE_A32(Ldr(r0, masm.MemOperandComputationHelper(r2,
r1,
0xffcba000,
0xfff)),
- "mov r2, #24576\n"
- "movt r2, #52\n"
- "sub r2, r1, r2\n"
+ "sub r2, r1, #286720\n"
+ "sub r2, #3145728\n"
"ldr r0, [r2]\n");
CLEANUP();
@@ -3535,6 +3659,7 @@
CLEANUP();
}
+
#define CHECK_T32_16(ASM, EXP) COMPARE_T32_CHECK_SIZE(ASM, EXP, 2)
// For instructions inside an IT block, we need to account for the IT
// instruction as well (another 16 bits).
@@ -3868,7 +3993,6 @@
#undef CHECK_T32_16
#undef CHECK_T32_16_IT_BLOCK
-
TEST(nop_code) {
SETUP();
@@ -3886,5 +4010,62 @@
CLEANUP();
}
+
+TEST(big_add_sub) {
+ SETUP();
+
+ COMPARE_A32(Add(r0, r1, 0x4321),
+ "add r0, r1, #33\n"
+ "add r0, #17152\n");
+ COMPARE_T32(Add(r0, r1, 0x4321),
+ "add r0, r1, #801\n"
+ "add r0, #16384\n");
+ COMPARE_BOTH(Add(r0, r1, 0x432100),
+ "add r0, r1, #8448\n"
+ "add r0, #4390912\n");
+ COMPARE_BOTH(Add(r0, r1, 0x43000210),
+ "add r0, r1, #528\n"
+ "add r0, #1124073472\n");
+ COMPARE_BOTH(Add(r0, r1, 0x30c00210),
+ "add r0, r1, #528\n"
+ "add r0, #817889280\n");
+ COMPARE_BOTH(Add(r0, r1, 0x43000021),
+ "add r0, r1, #33\n"
+ "add r0, #1124073472\n");
+ COMPARE_T32(Add(r0, r1, 0x54321),
+ "add r0, r1, #801\n"
+ "add r0, #344064\n");
+ COMPARE_T32(Add(r0, r1, 0x54000321),
+ "add r0, r1, #801\n"
+ "add r0, #1409286144\n");
+
+ COMPARE_A32(Sub(r0, r1, 0x4321),
+ "sub r0, r1, #33\n"
+ "sub r0, #17152\n");
+ COMPARE_T32(Sub(r0, r1, 0x4321),
+ "sub r0, r1, #801\n"
+ "sub r0, #16384\n");
+ COMPARE_BOTH(Sub(r0, r1, 0x432100),
+ "sub r0, r1, #8448\n"
+ "sub r0, #4390912\n");
+ COMPARE_BOTH(Sub(r0, r1, 0x43000210),
+ "sub r0, r1, #528\n"
+ "sub r0, #1124073472\n");
+ COMPARE_BOTH(Sub(r0, r1, 0x30c00210),
+ "sub r0, r1, #528\n"
+ "sub r0, #817889280\n");
+ COMPARE_BOTH(Sub(r0, r1, 0x43000021),
+ "sub r0, r1, #33\n"
+ "sub r0, #1124073472\n");
+ COMPARE_T32(Sub(r0, r1, 0x54321),
+ "sub r0, r1, #801\n"
+ "sub r0, #344064\n");
+ COMPARE_T32(Sub(r0, r1, 0x54000321),
+ "sub r0, r1, #801\n"
+ "sub r0, #1409286144\n");
+
+ CLEANUP();
+}
+
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-macro-assembler-cond-rd-rn-a32.cc b/test/aarch32/test-macro-assembler-cond-rd-rn-a32.cc
index ea09144..ad0e451 100644
--- a/test/aarch32/test-macro-assembler-cond-rd-rn-a32.cc
+++ b/test/aarch32/test-macro-assembler-cond-rd-rn-a32.cc
@@ -68,6 +68,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -90,3381 +91,506 @@
};
// Each element of this array produce one instruction encoding.
-const TestData kTests[] = {{{eq, r0, r0}, "eq, r0, r0", "eq_r0_r0"},
- {{eq, r0, r1}, "eq, r0, r1", "eq_r0_r1"},
- {{eq, r0, r2}, "eq, r0, r2", "eq_r0_r2"},
- {{eq, r0, r3}, "eq, r0, r3", "eq_r0_r3"},
- {{eq, r0, r4}, "eq, r0, r4", "eq_r0_r4"},
- {{eq, r0, r5}, "eq, r0, r5", "eq_r0_r5"},
- {{eq, r0, r6}, "eq, r0, r6", "eq_r0_r6"},
- {{eq, r0, r7}, "eq, r0, r7", "eq_r0_r7"},
- {{eq, r0, r8}, "eq, r0, r8", "eq_r0_r8"},
- {{eq, r0, r9}, "eq, r0, r9", "eq_r0_r9"},
- {{eq, r0, r10}, "eq, r0, r10", "eq_r0_r10"},
- {{eq, r0, r11}, "eq, r0, r11", "eq_r0_r11"},
- {{eq, r0, r12}, "eq, r0, r12", "eq_r0_r12"},
- {{eq, r0, r13}, "eq, r0, r13", "eq_r0_r13"},
- {{eq, r0, r14}, "eq, r0, r14", "eq_r0_r14"},
- {{eq, r1, r0}, "eq, r1, r0", "eq_r1_r0"},
- {{eq, r1, r1}, "eq, r1, r1", "eq_r1_r1"},
- {{eq, r1, r2}, "eq, r1, r2", "eq_r1_r2"},
- {{eq, r1, r3}, "eq, r1, r3", "eq_r1_r3"},
- {{eq, r1, r4}, "eq, r1, r4", "eq_r1_r4"},
- {{eq, r1, r5}, "eq, r1, r5", "eq_r1_r5"},
- {{eq, r1, r6}, "eq, r1, r6", "eq_r1_r6"},
- {{eq, r1, r7}, "eq, r1, r7", "eq_r1_r7"},
- {{eq, r1, r8}, "eq, r1, r8", "eq_r1_r8"},
- {{eq, r1, r9}, "eq, r1, r9", "eq_r1_r9"},
- {{eq, r1, r10}, "eq, r1, r10", "eq_r1_r10"},
- {{eq, r1, r11}, "eq, r1, r11", "eq_r1_r11"},
- {{eq, r1, r12}, "eq, r1, r12", "eq_r1_r12"},
- {{eq, r1, r13}, "eq, r1, r13", "eq_r1_r13"},
- {{eq, r1, r14}, "eq, r1, r14", "eq_r1_r14"},
- {{eq, r2, r0}, "eq, r2, r0", "eq_r2_r0"},
- {{eq, r2, r1}, "eq, r2, r1", "eq_r2_r1"},
- {{eq, r2, r2}, "eq, r2, r2", "eq_r2_r2"},
- {{eq, r2, r3}, "eq, r2, r3", "eq_r2_r3"},
- {{eq, r2, r4}, "eq, r2, r4", "eq_r2_r4"},
- {{eq, r2, r5}, "eq, r2, r5", "eq_r2_r5"},
- {{eq, r2, r6}, "eq, r2, r6", "eq_r2_r6"},
- {{eq, r2, r7}, "eq, r2, r7", "eq_r2_r7"},
- {{eq, r2, r8}, "eq, r2, r8", "eq_r2_r8"},
- {{eq, r2, r9}, "eq, r2, r9", "eq_r2_r9"},
- {{eq, r2, r10}, "eq, r2, r10", "eq_r2_r10"},
- {{eq, r2, r11}, "eq, r2, r11", "eq_r2_r11"},
- {{eq, r2, r12}, "eq, r2, r12", "eq_r2_r12"},
- {{eq, r2, r13}, "eq, r2, r13", "eq_r2_r13"},
- {{eq, r2, r14}, "eq, r2, r14", "eq_r2_r14"},
- {{eq, r3, r0}, "eq, r3, r0", "eq_r3_r0"},
- {{eq, r3, r1}, "eq, r3, r1", "eq_r3_r1"},
- {{eq, r3, r2}, "eq, r3, r2", "eq_r3_r2"},
- {{eq, r3, r3}, "eq, r3, r3", "eq_r3_r3"},
- {{eq, r3, r4}, "eq, r3, r4", "eq_r3_r4"},
- {{eq, r3, r5}, "eq, r3, r5", "eq_r3_r5"},
- {{eq, r3, r6}, "eq, r3, r6", "eq_r3_r6"},
- {{eq, r3, r7}, "eq, r3, r7", "eq_r3_r7"},
- {{eq, r3, r8}, "eq, r3, r8", "eq_r3_r8"},
- {{eq, r3, r9}, "eq, r3, r9", "eq_r3_r9"},
- {{eq, r3, r10}, "eq, r3, r10", "eq_r3_r10"},
- {{eq, r3, r11}, "eq, r3, r11", "eq_r3_r11"},
- {{eq, r3, r12}, "eq, r3, r12", "eq_r3_r12"},
- {{eq, r3, r13}, "eq, r3, r13", "eq_r3_r13"},
- {{eq, r3, r14}, "eq, r3, r14", "eq_r3_r14"},
- {{eq, r4, r0}, "eq, r4, r0", "eq_r4_r0"},
- {{eq, r4, r1}, "eq, r4, r1", "eq_r4_r1"},
- {{eq, r4, r2}, "eq, r4, r2", "eq_r4_r2"},
- {{eq, r4, r3}, "eq, r4, r3", "eq_r4_r3"},
- {{eq, r4, r4}, "eq, r4, r4", "eq_r4_r4"},
- {{eq, r4, r5}, "eq, r4, r5", "eq_r4_r5"},
- {{eq, r4, r6}, "eq, r4, r6", "eq_r4_r6"},
- {{eq, r4, r7}, "eq, r4, r7", "eq_r4_r7"},
- {{eq, r4, r8}, "eq, r4, r8", "eq_r4_r8"},
- {{eq, r4, r9}, "eq, r4, r9", "eq_r4_r9"},
- {{eq, r4, r10}, "eq, r4, r10", "eq_r4_r10"},
- {{eq, r4, r11}, "eq, r4, r11", "eq_r4_r11"},
- {{eq, r4, r12}, "eq, r4, r12", "eq_r4_r12"},
- {{eq, r4, r13}, "eq, r4, r13", "eq_r4_r13"},
- {{eq, r4, r14}, "eq, r4, r14", "eq_r4_r14"},
- {{eq, r5, r0}, "eq, r5, r0", "eq_r5_r0"},
- {{eq, r5, r1}, "eq, r5, r1", "eq_r5_r1"},
- {{eq, r5, r2}, "eq, r5, r2", "eq_r5_r2"},
- {{eq, r5, r3}, "eq, r5, r3", "eq_r5_r3"},
- {{eq, r5, r4}, "eq, r5, r4", "eq_r5_r4"},
- {{eq, r5, r5}, "eq, r5, r5", "eq_r5_r5"},
- {{eq, r5, r6}, "eq, r5, r6", "eq_r5_r6"},
- {{eq, r5, r7}, "eq, r5, r7", "eq_r5_r7"},
- {{eq, r5, r8}, "eq, r5, r8", "eq_r5_r8"},
- {{eq, r5, r9}, "eq, r5, r9", "eq_r5_r9"},
- {{eq, r5, r10}, "eq, r5, r10", "eq_r5_r10"},
- {{eq, r5, r11}, "eq, r5, r11", "eq_r5_r11"},
- {{eq, r5, r12}, "eq, r5, r12", "eq_r5_r12"},
- {{eq, r5, r13}, "eq, r5, r13", "eq_r5_r13"},
- {{eq, r5, r14}, "eq, r5, r14", "eq_r5_r14"},
- {{eq, r6, r0}, "eq, r6, r0", "eq_r6_r0"},
- {{eq, r6, r1}, "eq, r6, r1", "eq_r6_r1"},
- {{eq, r6, r2}, "eq, r6, r2", "eq_r6_r2"},
- {{eq, r6, r3}, "eq, r6, r3", "eq_r6_r3"},
- {{eq, r6, r4}, "eq, r6, r4", "eq_r6_r4"},
- {{eq, r6, r5}, "eq, r6, r5", "eq_r6_r5"},
- {{eq, r6, r6}, "eq, r6, r6", "eq_r6_r6"},
- {{eq, r6, r7}, "eq, r6, r7", "eq_r6_r7"},
- {{eq, r6, r8}, "eq, r6, r8", "eq_r6_r8"},
- {{eq, r6, r9}, "eq, r6, r9", "eq_r6_r9"},
- {{eq, r6, r10}, "eq, r6, r10", "eq_r6_r10"},
- {{eq, r6, r11}, "eq, r6, r11", "eq_r6_r11"},
- {{eq, r6, r12}, "eq, r6, r12", "eq_r6_r12"},
- {{eq, r6, r13}, "eq, r6, r13", "eq_r6_r13"},
- {{eq, r6, r14}, "eq, r6, r14", "eq_r6_r14"},
- {{eq, r7, r0}, "eq, r7, r0", "eq_r7_r0"},
- {{eq, r7, r1}, "eq, r7, r1", "eq_r7_r1"},
- {{eq, r7, r2}, "eq, r7, r2", "eq_r7_r2"},
- {{eq, r7, r3}, "eq, r7, r3", "eq_r7_r3"},
- {{eq, r7, r4}, "eq, r7, r4", "eq_r7_r4"},
- {{eq, r7, r5}, "eq, r7, r5", "eq_r7_r5"},
- {{eq, r7, r6}, "eq, r7, r6", "eq_r7_r6"},
- {{eq, r7, r7}, "eq, r7, r7", "eq_r7_r7"},
- {{eq, r7, r8}, "eq, r7, r8", "eq_r7_r8"},
- {{eq, r7, r9}, "eq, r7, r9", "eq_r7_r9"},
- {{eq, r7, r10}, "eq, r7, r10", "eq_r7_r10"},
- {{eq, r7, r11}, "eq, r7, r11", "eq_r7_r11"},
- {{eq, r7, r12}, "eq, r7, r12", "eq_r7_r12"},
- {{eq, r7, r13}, "eq, r7, r13", "eq_r7_r13"},
- {{eq, r7, r14}, "eq, r7, r14", "eq_r7_r14"},
- {{eq, r8, r0}, "eq, r8, r0", "eq_r8_r0"},
- {{eq, r8, r1}, "eq, r8, r1", "eq_r8_r1"},
- {{eq, r8, r2}, "eq, r8, r2", "eq_r8_r2"},
- {{eq, r8, r3}, "eq, r8, r3", "eq_r8_r3"},
- {{eq, r8, r4}, "eq, r8, r4", "eq_r8_r4"},
- {{eq, r8, r5}, "eq, r8, r5", "eq_r8_r5"},
- {{eq, r8, r6}, "eq, r8, r6", "eq_r8_r6"},
- {{eq, r8, r7}, "eq, r8, r7", "eq_r8_r7"},
- {{eq, r8, r8}, "eq, r8, r8", "eq_r8_r8"},
- {{eq, r8, r9}, "eq, r8, r9", "eq_r8_r9"},
- {{eq, r8, r10}, "eq, r8, r10", "eq_r8_r10"},
- {{eq, r8, r11}, "eq, r8, r11", "eq_r8_r11"},
- {{eq, r8, r12}, "eq, r8, r12", "eq_r8_r12"},
- {{eq, r8, r13}, "eq, r8, r13", "eq_r8_r13"},
- {{eq, r8, r14}, "eq, r8, r14", "eq_r8_r14"},
- {{eq, r9, r0}, "eq, r9, r0", "eq_r9_r0"},
- {{eq, r9, r1}, "eq, r9, r1", "eq_r9_r1"},
- {{eq, r9, r2}, "eq, r9, r2", "eq_r9_r2"},
- {{eq, r9, r3}, "eq, r9, r3", "eq_r9_r3"},
- {{eq, r9, r4}, "eq, r9, r4", "eq_r9_r4"},
- {{eq, r9, r5}, "eq, r9, r5", "eq_r9_r5"},
- {{eq, r9, r6}, "eq, r9, r6", "eq_r9_r6"},
- {{eq, r9, r7}, "eq, r9, r7", "eq_r9_r7"},
- {{eq, r9, r8}, "eq, r9, r8", "eq_r9_r8"},
- {{eq, r9, r9}, "eq, r9, r9", "eq_r9_r9"},
- {{eq, r9, r10}, "eq, r9, r10", "eq_r9_r10"},
- {{eq, r9, r11}, "eq, r9, r11", "eq_r9_r11"},
- {{eq, r9, r12}, "eq, r9, r12", "eq_r9_r12"},
- {{eq, r9, r13}, "eq, r9, r13", "eq_r9_r13"},
- {{eq, r9, r14}, "eq, r9, r14", "eq_r9_r14"},
- {{eq, r10, r0}, "eq, r10, r0", "eq_r10_r0"},
- {{eq, r10, r1}, "eq, r10, r1", "eq_r10_r1"},
- {{eq, r10, r2}, "eq, r10, r2", "eq_r10_r2"},
- {{eq, r10, r3}, "eq, r10, r3", "eq_r10_r3"},
- {{eq, r10, r4}, "eq, r10, r4", "eq_r10_r4"},
- {{eq, r10, r5}, "eq, r10, r5", "eq_r10_r5"},
- {{eq, r10, r6}, "eq, r10, r6", "eq_r10_r6"},
- {{eq, r10, r7}, "eq, r10, r7", "eq_r10_r7"},
- {{eq, r10, r8}, "eq, r10, r8", "eq_r10_r8"},
- {{eq, r10, r9}, "eq, r10, r9", "eq_r10_r9"},
- {{eq, r10, r10}, "eq, r10, r10", "eq_r10_r10"},
- {{eq, r10, r11}, "eq, r10, r11", "eq_r10_r11"},
- {{eq, r10, r12}, "eq, r10, r12", "eq_r10_r12"},
- {{eq, r10, r13}, "eq, r10, r13", "eq_r10_r13"},
- {{eq, r10, r14}, "eq, r10, r14", "eq_r10_r14"},
- {{eq, r11, r0}, "eq, r11, r0", "eq_r11_r0"},
- {{eq, r11, r1}, "eq, r11, r1", "eq_r11_r1"},
- {{eq, r11, r2}, "eq, r11, r2", "eq_r11_r2"},
- {{eq, r11, r3}, "eq, r11, r3", "eq_r11_r3"},
- {{eq, r11, r4}, "eq, r11, r4", "eq_r11_r4"},
- {{eq, r11, r5}, "eq, r11, r5", "eq_r11_r5"},
- {{eq, r11, r6}, "eq, r11, r6", "eq_r11_r6"},
- {{eq, r11, r7}, "eq, r11, r7", "eq_r11_r7"},
- {{eq, r11, r8}, "eq, r11, r8", "eq_r11_r8"},
- {{eq, r11, r9}, "eq, r11, r9", "eq_r11_r9"},
- {{eq, r11, r10}, "eq, r11, r10", "eq_r11_r10"},
- {{eq, r11, r11}, "eq, r11, r11", "eq_r11_r11"},
- {{eq, r11, r12}, "eq, r11, r12", "eq_r11_r12"},
- {{eq, r11, r13}, "eq, r11, r13", "eq_r11_r13"},
- {{eq, r11, r14}, "eq, r11, r14", "eq_r11_r14"},
- {{eq, r12, r0}, "eq, r12, r0", "eq_r12_r0"},
- {{eq, r12, r1}, "eq, r12, r1", "eq_r12_r1"},
- {{eq, r12, r2}, "eq, r12, r2", "eq_r12_r2"},
- {{eq, r12, r3}, "eq, r12, r3", "eq_r12_r3"},
- {{eq, r12, r4}, "eq, r12, r4", "eq_r12_r4"},
- {{eq, r12, r5}, "eq, r12, r5", "eq_r12_r5"},
- {{eq, r12, r6}, "eq, r12, r6", "eq_r12_r6"},
- {{eq, r12, r7}, "eq, r12, r7", "eq_r12_r7"},
- {{eq, r12, r8}, "eq, r12, r8", "eq_r12_r8"},
- {{eq, r12, r9}, "eq, r12, r9", "eq_r12_r9"},
- {{eq, r12, r10}, "eq, r12, r10", "eq_r12_r10"},
- {{eq, r12, r11}, "eq, r12, r11", "eq_r12_r11"},
- {{eq, r12, r12}, "eq, r12, r12", "eq_r12_r12"},
- {{eq, r12, r13}, "eq, r12, r13", "eq_r12_r13"},
- {{eq, r12, r14}, "eq, r12, r14", "eq_r12_r14"},
- {{eq, r13, r0}, "eq, r13, r0", "eq_r13_r0"},
- {{eq, r13, r1}, "eq, r13, r1", "eq_r13_r1"},
- {{eq, r13, r2}, "eq, r13, r2", "eq_r13_r2"},
- {{eq, r13, r3}, "eq, r13, r3", "eq_r13_r3"},
- {{eq, r13, r4}, "eq, r13, r4", "eq_r13_r4"},
- {{eq, r13, r5}, "eq, r13, r5", "eq_r13_r5"},
- {{eq, r13, r6}, "eq, r13, r6", "eq_r13_r6"},
- {{eq, r13, r7}, "eq, r13, r7", "eq_r13_r7"},
- {{eq, r13, r8}, "eq, r13, r8", "eq_r13_r8"},
- {{eq, r13, r9}, "eq, r13, r9", "eq_r13_r9"},
- {{eq, r13, r10}, "eq, r13, r10", "eq_r13_r10"},
- {{eq, r13, r11}, "eq, r13, r11", "eq_r13_r11"},
- {{eq, r13, r12}, "eq, r13, r12", "eq_r13_r12"},
- {{eq, r13, r13}, "eq, r13, r13", "eq_r13_r13"},
- {{eq, r13, r14}, "eq, r13, r14", "eq_r13_r14"},
- {{eq, r14, r0}, "eq, r14, r0", "eq_r14_r0"},
- {{eq, r14, r1}, "eq, r14, r1", "eq_r14_r1"},
- {{eq, r14, r2}, "eq, r14, r2", "eq_r14_r2"},
- {{eq, r14, r3}, "eq, r14, r3", "eq_r14_r3"},
- {{eq, r14, r4}, "eq, r14, r4", "eq_r14_r4"},
- {{eq, r14, r5}, "eq, r14, r5", "eq_r14_r5"},
- {{eq, r14, r6}, "eq, r14, r6", "eq_r14_r6"},
- {{eq, r14, r7}, "eq, r14, r7", "eq_r14_r7"},
- {{eq, r14, r8}, "eq, r14, r8", "eq_r14_r8"},
- {{eq, r14, r9}, "eq, r14, r9", "eq_r14_r9"},
- {{eq, r14, r10}, "eq, r14, r10", "eq_r14_r10"},
- {{eq, r14, r11}, "eq, r14, r11", "eq_r14_r11"},
- {{eq, r14, r12}, "eq, r14, r12", "eq_r14_r12"},
- {{eq, r14, r13}, "eq, r14, r13", "eq_r14_r13"},
- {{eq, r14, r14}, "eq, r14, r14", "eq_r14_r14"},
- {{ne, r0, r0}, "ne, r0, r0", "ne_r0_r0"},
- {{ne, r0, r1}, "ne, r0, r1", "ne_r0_r1"},
- {{ne, r0, r2}, "ne, r0, r2", "ne_r0_r2"},
- {{ne, r0, r3}, "ne, r0, r3", "ne_r0_r3"},
- {{ne, r0, r4}, "ne, r0, r4", "ne_r0_r4"},
- {{ne, r0, r5}, "ne, r0, r5", "ne_r0_r5"},
- {{ne, r0, r6}, "ne, r0, r6", "ne_r0_r6"},
- {{ne, r0, r7}, "ne, r0, r7", "ne_r0_r7"},
- {{ne, r0, r8}, "ne, r0, r8", "ne_r0_r8"},
- {{ne, r0, r9}, "ne, r0, r9", "ne_r0_r9"},
- {{ne, r0, r10}, "ne, r0, r10", "ne_r0_r10"},
- {{ne, r0, r11}, "ne, r0, r11", "ne_r0_r11"},
- {{ne, r0, r12}, "ne, r0, r12", "ne_r0_r12"},
- {{ne, r0, r13}, "ne, r0, r13", "ne_r0_r13"},
- {{ne, r0, r14}, "ne, r0, r14", "ne_r0_r14"},
- {{ne, r1, r0}, "ne, r1, r0", "ne_r1_r0"},
- {{ne, r1, r1}, "ne, r1, r1", "ne_r1_r1"},
- {{ne, r1, r2}, "ne, r1, r2", "ne_r1_r2"},
- {{ne, r1, r3}, "ne, r1, r3", "ne_r1_r3"},
- {{ne, r1, r4}, "ne, r1, r4", "ne_r1_r4"},
- {{ne, r1, r5}, "ne, r1, r5", "ne_r1_r5"},
- {{ne, r1, r6}, "ne, r1, r6", "ne_r1_r6"},
- {{ne, r1, r7}, "ne, r1, r7", "ne_r1_r7"},
- {{ne, r1, r8}, "ne, r1, r8", "ne_r1_r8"},
- {{ne, r1, r9}, "ne, r1, r9", "ne_r1_r9"},
- {{ne, r1, r10}, "ne, r1, r10", "ne_r1_r10"},
- {{ne, r1, r11}, "ne, r1, r11", "ne_r1_r11"},
- {{ne, r1, r12}, "ne, r1, r12", "ne_r1_r12"},
- {{ne, r1, r13}, "ne, r1, r13", "ne_r1_r13"},
- {{ne, r1, r14}, "ne, r1, r14", "ne_r1_r14"},
- {{ne, r2, r0}, "ne, r2, r0", "ne_r2_r0"},
- {{ne, r2, r1}, "ne, r2, r1", "ne_r2_r1"},
- {{ne, r2, r2}, "ne, r2, r2", "ne_r2_r2"},
- {{ne, r2, r3}, "ne, r2, r3", "ne_r2_r3"},
- {{ne, r2, r4}, "ne, r2, r4", "ne_r2_r4"},
- {{ne, r2, r5}, "ne, r2, r5", "ne_r2_r5"},
- {{ne, r2, r6}, "ne, r2, r6", "ne_r2_r6"},
- {{ne, r2, r7}, "ne, r2, r7", "ne_r2_r7"},
- {{ne, r2, r8}, "ne, r2, r8", "ne_r2_r8"},
- {{ne, r2, r9}, "ne, r2, r9", "ne_r2_r9"},
- {{ne, r2, r10}, "ne, r2, r10", "ne_r2_r10"},
- {{ne, r2, r11}, "ne, r2, r11", "ne_r2_r11"},
- {{ne, r2, r12}, "ne, r2, r12", "ne_r2_r12"},
- {{ne, r2, r13}, "ne, r2, r13", "ne_r2_r13"},
- {{ne, r2, r14}, "ne, r2, r14", "ne_r2_r14"},
- {{ne, r3, r0}, "ne, r3, r0", "ne_r3_r0"},
- {{ne, r3, r1}, "ne, r3, r1", "ne_r3_r1"},
- {{ne, r3, r2}, "ne, r3, r2", "ne_r3_r2"},
- {{ne, r3, r3}, "ne, r3, r3", "ne_r3_r3"},
- {{ne, r3, r4}, "ne, r3, r4", "ne_r3_r4"},
- {{ne, r3, r5}, "ne, r3, r5", "ne_r3_r5"},
- {{ne, r3, r6}, "ne, r3, r6", "ne_r3_r6"},
- {{ne, r3, r7}, "ne, r3, r7", "ne_r3_r7"},
- {{ne, r3, r8}, "ne, r3, r8", "ne_r3_r8"},
- {{ne, r3, r9}, "ne, r3, r9", "ne_r3_r9"},
- {{ne, r3, r10}, "ne, r3, r10", "ne_r3_r10"},
- {{ne, r3, r11}, "ne, r3, r11", "ne_r3_r11"},
- {{ne, r3, r12}, "ne, r3, r12", "ne_r3_r12"},
- {{ne, r3, r13}, "ne, r3, r13", "ne_r3_r13"},
- {{ne, r3, r14}, "ne, r3, r14", "ne_r3_r14"},
- {{ne, r4, r0}, "ne, r4, r0", "ne_r4_r0"},
- {{ne, r4, r1}, "ne, r4, r1", "ne_r4_r1"},
- {{ne, r4, r2}, "ne, r4, r2", "ne_r4_r2"},
- {{ne, r4, r3}, "ne, r4, r3", "ne_r4_r3"},
- {{ne, r4, r4}, "ne, r4, r4", "ne_r4_r4"},
- {{ne, r4, r5}, "ne, r4, r5", "ne_r4_r5"},
- {{ne, r4, r6}, "ne, r4, r6", "ne_r4_r6"},
- {{ne, r4, r7}, "ne, r4, r7", "ne_r4_r7"},
- {{ne, r4, r8}, "ne, r4, r8", "ne_r4_r8"},
- {{ne, r4, r9}, "ne, r4, r9", "ne_r4_r9"},
- {{ne, r4, r10}, "ne, r4, r10", "ne_r4_r10"},
- {{ne, r4, r11}, "ne, r4, r11", "ne_r4_r11"},
- {{ne, r4, r12}, "ne, r4, r12", "ne_r4_r12"},
- {{ne, r4, r13}, "ne, r4, r13", "ne_r4_r13"},
- {{ne, r4, r14}, "ne, r4, r14", "ne_r4_r14"},
- {{ne, r5, r0}, "ne, r5, r0", "ne_r5_r0"},
- {{ne, r5, r1}, "ne, r5, r1", "ne_r5_r1"},
- {{ne, r5, r2}, "ne, r5, r2", "ne_r5_r2"},
- {{ne, r5, r3}, "ne, r5, r3", "ne_r5_r3"},
- {{ne, r5, r4}, "ne, r5, r4", "ne_r5_r4"},
- {{ne, r5, r5}, "ne, r5, r5", "ne_r5_r5"},
- {{ne, r5, r6}, "ne, r5, r6", "ne_r5_r6"},
- {{ne, r5, r7}, "ne, r5, r7", "ne_r5_r7"},
- {{ne, r5, r8}, "ne, r5, r8", "ne_r5_r8"},
- {{ne, r5, r9}, "ne, r5, r9", "ne_r5_r9"},
- {{ne, r5, r10}, "ne, r5, r10", "ne_r5_r10"},
- {{ne, r5, r11}, "ne, r5, r11", "ne_r5_r11"},
- {{ne, r5, r12}, "ne, r5, r12", "ne_r5_r12"},
- {{ne, r5, r13}, "ne, r5, r13", "ne_r5_r13"},
- {{ne, r5, r14}, "ne, r5, r14", "ne_r5_r14"},
- {{ne, r6, r0}, "ne, r6, r0", "ne_r6_r0"},
- {{ne, r6, r1}, "ne, r6, r1", "ne_r6_r1"},
- {{ne, r6, r2}, "ne, r6, r2", "ne_r6_r2"},
- {{ne, r6, r3}, "ne, r6, r3", "ne_r6_r3"},
- {{ne, r6, r4}, "ne, r6, r4", "ne_r6_r4"},
- {{ne, r6, r5}, "ne, r6, r5", "ne_r6_r5"},
- {{ne, r6, r6}, "ne, r6, r6", "ne_r6_r6"},
- {{ne, r6, r7}, "ne, r6, r7", "ne_r6_r7"},
- {{ne, r6, r8}, "ne, r6, r8", "ne_r6_r8"},
- {{ne, r6, r9}, "ne, r6, r9", "ne_r6_r9"},
- {{ne, r6, r10}, "ne, r6, r10", "ne_r6_r10"},
- {{ne, r6, r11}, "ne, r6, r11", "ne_r6_r11"},
- {{ne, r6, r12}, "ne, r6, r12", "ne_r6_r12"},
- {{ne, r6, r13}, "ne, r6, r13", "ne_r6_r13"},
- {{ne, r6, r14}, "ne, r6, r14", "ne_r6_r14"},
- {{ne, r7, r0}, "ne, r7, r0", "ne_r7_r0"},
- {{ne, r7, r1}, "ne, r7, r1", "ne_r7_r1"},
- {{ne, r7, r2}, "ne, r7, r2", "ne_r7_r2"},
- {{ne, r7, r3}, "ne, r7, r3", "ne_r7_r3"},
- {{ne, r7, r4}, "ne, r7, r4", "ne_r7_r4"},
- {{ne, r7, r5}, "ne, r7, r5", "ne_r7_r5"},
- {{ne, r7, r6}, "ne, r7, r6", "ne_r7_r6"},
- {{ne, r7, r7}, "ne, r7, r7", "ne_r7_r7"},
- {{ne, r7, r8}, "ne, r7, r8", "ne_r7_r8"},
- {{ne, r7, r9}, "ne, r7, r9", "ne_r7_r9"},
- {{ne, r7, r10}, "ne, r7, r10", "ne_r7_r10"},
- {{ne, r7, r11}, "ne, r7, r11", "ne_r7_r11"},
- {{ne, r7, r12}, "ne, r7, r12", "ne_r7_r12"},
- {{ne, r7, r13}, "ne, r7, r13", "ne_r7_r13"},
- {{ne, r7, r14}, "ne, r7, r14", "ne_r7_r14"},
- {{ne, r8, r0}, "ne, r8, r0", "ne_r8_r0"},
- {{ne, r8, r1}, "ne, r8, r1", "ne_r8_r1"},
- {{ne, r8, r2}, "ne, r8, r2", "ne_r8_r2"},
- {{ne, r8, r3}, "ne, r8, r3", "ne_r8_r3"},
+const TestData kTests[] = {{{cs, r12, r1}, "cs, r12, r1", "cs_r12_r1"},
+ {{hi, r6, r12}, "hi, r6, r12", "hi_r6_r12"},
+ {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
+ {{vs, r10, r8}, "vs, r10, r8", "vs_r10_r8"},
+ {{pl, r5, r8}, "pl, r5, r8", "pl_r5_r8"},
+ {{ls, r14, r14}, "ls, r14, r14", "ls_r14_r14"},
+ {{gt, r8, r6}, "gt, r8, r6", "gt_r8_r6"},
+ {{vc, r7, r11}, "vc, r7, r11", "vc_r7_r11"},
+ {{pl, r4, r12}, "pl, r4, r12", "pl_r4_r12"},
+ {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
{{ne, r8, r4}, "ne, r8, r4", "ne_r8_r4"},
- {{ne, r8, r5}, "ne, r8, r5", "ne_r8_r5"},
- {{ne, r8, r6}, "ne, r8, r6", "ne_r8_r6"},
- {{ne, r8, r7}, "ne, r8, r7", "ne_r8_r7"},
- {{ne, r8, r8}, "ne, r8, r8", "ne_r8_r8"},
- {{ne, r8, r9}, "ne, r8, r9", "ne_r8_r9"},
- {{ne, r8, r10}, "ne, r8, r10", "ne_r8_r10"},
- {{ne, r8, r11}, "ne, r8, r11", "ne_r8_r11"},
- {{ne, r8, r12}, "ne, r8, r12", "ne_r8_r12"},
- {{ne, r8, r13}, "ne, r8, r13", "ne_r8_r13"},
- {{ne, r8, r14}, "ne, r8, r14", "ne_r8_r14"},
- {{ne, r9, r0}, "ne, r9, r0", "ne_r9_r0"},
- {{ne, r9, r1}, "ne, r9, r1", "ne_r9_r1"},
- {{ne, r9, r2}, "ne, r9, r2", "ne_r9_r2"},
- {{ne, r9, r3}, "ne, r9, r3", "ne_r9_r3"},
- {{ne, r9, r4}, "ne, r9, r4", "ne_r9_r4"},
- {{ne, r9, r5}, "ne, r9, r5", "ne_r9_r5"},
- {{ne, r9, r6}, "ne, r9, r6", "ne_r9_r6"},
- {{ne, r9, r7}, "ne, r9, r7", "ne_r9_r7"},
- {{ne, r9, r8}, "ne, r9, r8", "ne_r9_r8"},
+ {{le, r1, r11}, "le, r1, r11", "le_r1_r11"},
+ {{cc, r4, r10}, "cc, r4, r10", "cc_r4_r10"},
+ {{gt, r14, r0}, "gt, r14, r0", "gt_r14_r0"},
+ {{cs, r2, r11}, "cs, r2, r11", "cs_r2_r11"},
+ {{al, r3, r12}, "al, r3, r12", "al_r3_r12"},
+ {{hi, r6, r0}, "hi, r6, r0", "hi_r6_r0"},
+ {{ls, r10, r10}, "ls, r10, r10", "ls_r10_r10"},
+ {{ls, r4, r8}, "ls, r4, r8", "ls_r4_r8"},
+ {{le, r8, r0}, "le, r8, r0", "le_r8_r0"},
+ {{pl, r5, r3}, "pl, r5, r3", "pl_r5_r3"},
+ {{ls, r8, r5}, "ls, r8, r5", "ls_r8_r5"},
+ {{ge, r0, r10}, "ge, r0, r10", "ge_r0_r10"},
+ {{lt, r10, r6}, "lt, r10, r6", "lt_r10_r6"},
{{ne, r9, r9}, "ne, r9, r9", "ne_r9_r9"},
- {{ne, r9, r10}, "ne, r9, r10", "ne_r9_r10"},
- {{ne, r9, r11}, "ne, r9, r11", "ne_r9_r11"},
- {{ne, r9, r12}, "ne, r9, r12", "ne_r9_r12"},
- {{ne, r9, r13}, "ne, r9, r13", "ne_r9_r13"},
- {{ne, r9, r14}, "ne, r9, r14", "ne_r9_r14"},
- {{ne, r10, r0}, "ne, r10, r0", "ne_r10_r0"},
- {{ne, r10, r1}, "ne, r10, r1", "ne_r10_r1"},
- {{ne, r10, r2}, "ne, r10, r2", "ne_r10_r2"},
- {{ne, r10, r3}, "ne, r10, r3", "ne_r10_r3"},
- {{ne, r10, r4}, "ne, r10, r4", "ne_r10_r4"},
- {{ne, r10, r5}, "ne, r10, r5", "ne_r10_r5"},
- {{ne, r10, r6}, "ne, r10, r6", "ne_r10_r6"},
- {{ne, r10, r7}, "ne, r10, r7", "ne_r10_r7"},
- {{ne, r10, r8}, "ne, r10, r8", "ne_r10_r8"},
- {{ne, r10, r9}, "ne, r10, r9", "ne_r10_r9"},
- {{ne, r10, r10}, "ne, r10, r10", "ne_r10_r10"},
- {{ne, r10, r11}, "ne, r10, r11", "ne_r10_r11"},
- {{ne, r10, r12}, "ne, r10, r12", "ne_r10_r12"},
- {{ne, r10, r13}, "ne, r10, r13", "ne_r10_r13"},
- {{ne, r10, r14}, "ne, r10, r14", "ne_r10_r14"},
- {{ne, r11, r0}, "ne, r11, r0", "ne_r11_r0"},
- {{ne, r11, r1}, "ne, r11, r1", "ne_r11_r1"},
- {{ne, r11, r2}, "ne, r11, r2", "ne_r11_r2"},
- {{ne, r11, r3}, "ne, r11, r3", "ne_r11_r3"},
- {{ne, r11, r4}, "ne, r11, r4", "ne_r11_r4"},
- {{ne, r11, r5}, "ne, r11, r5", "ne_r11_r5"},
- {{ne, r11, r6}, "ne, r11, r6", "ne_r11_r6"},
- {{ne, r11, r7}, "ne, r11, r7", "ne_r11_r7"},
- {{ne, r11, r8}, "ne, r11, r8", "ne_r11_r8"},
- {{ne, r11, r9}, "ne, r11, r9", "ne_r11_r9"},
- {{ne, r11, r10}, "ne, r11, r10", "ne_r11_r10"},
- {{ne, r11, r11}, "ne, r11, r11", "ne_r11_r11"},
- {{ne, r11, r12}, "ne, r11, r12", "ne_r11_r12"},
- {{ne, r11, r13}, "ne, r11, r13", "ne_r11_r13"},
- {{ne, r11, r14}, "ne, r11, r14", "ne_r11_r14"},
- {{ne, r12, r0}, "ne, r12, r0", "ne_r12_r0"},
- {{ne, r12, r1}, "ne, r12, r1", "ne_r12_r1"},
- {{ne, r12, r2}, "ne, r12, r2", "ne_r12_r2"},
- {{ne, r12, r3}, "ne, r12, r3", "ne_r12_r3"},
- {{ne, r12, r4}, "ne, r12, r4", "ne_r12_r4"},
- {{ne, r12, r5}, "ne, r12, r5", "ne_r12_r5"},
- {{ne, r12, r6}, "ne, r12, r6", "ne_r12_r6"},
- {{ne, r12, r7}, "ne, r12, r7", "ne_r12_r7"},
- {{ne, r12, r8}, "ne, r12, r8", "ne_r12_r8"},
- {{ne, r12, r9}, "ne, r12, r9", "ne_r12_r9"},
- {{ne, r12, r10}, "ne, r12, r10", "ne_r12_r10"},
- {{ne, r12, r11}, "ne, r12, r11", "ne_r12_r11"},
- {{ne, r12, r12}, "ne, r12, r12", "ne_r12_r12"},
- {{ne, r12, r13}, "ne, r12, r13", "ne_r12_r13"},
- {{ne, r12, r14}, "ne, r12, r14", "ne_r12_r14"},
- {{ne, r13, r0}, "ne, r13, r0", "ne_r13_r0"},
- {{ne, r13, r1}, "ne, r13, r1", "ne_r13_r1"},
- {{ne, r13, r2}, "ne, r13, r2", "ne_r13_r2"},
- {{ne, r13, r3}, "ne, r13, r3", "ne_r13_r3"},
- {{ne, r13, r4}, "ne, r13, r4", "ne_r13_r4"},
- {{ne, r13, r5}, "ne, r13, r5", "ne_r13_r5"},
- {{ne, r13, r6}, "ne, r13, r6", "ne_r13_r6"},
- {{ne, r13, r7}, "ne, r13, r7", "ne_r13_r7"},
- {{ne, r13, r8}, "ne, r13, r8", "ne_r13_r8"},
+ {{hi, r5, r0}, "hi, r5, r0", "hi_r5_r0"},
+ {{pl, r10, r6}, "pl, r10, r6", "pl_r10_r6"},
+ {{vs, r1, r3}, "vs, r1, r3", "vs_r1_r3"},
+ {{vs, r9, r8}, "vs, r9, r8", "vs_r9_r8"},
+ {{cc, r2, r10}, "cc, r2, r10", "cc_r2_r10"},
+ {{cs, r11, r3}, "cs, r11, r3", "cs_r11_r3"},
+ {{hi, r8, r2}, "hi, r8, r2", "hi_r8_r2"},
+ {{pl, r6, r0}, "pl, r6, r0", "pl_r6_r0"},
+ {{hi, r9, r2}, "hi, r9, r2", "hi_r9_r2"},
+ {{al, r14, r11}, "al, r14, r11", "al_r14_r11"},
+ {{eq, r8, r13}, "eq, r8, r13", "eq_r8_r13"},
+ {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"},
+ {{cc, r2, r6}, "cc, r2, r6", "cc_r2_r6"},
{{ne, r13, r9}, "ne, r13, r9", "ne_r13_r9"},
{{ne, r13, r10}, "ne, r13, r10", "ne_r13_r10"},
- {{ne, r13, r11}, "ne, r13, r11", "ne_r13_r11"},
- {{ne, r13, r12}, "ne, r13, r12", "ne_r13_r12"},
- {{ne, r13, r13}, "ne, r13, r13", "ne_r13_r13"},
- {{ne, r13, r14}, "ne, r13, r14", "ne_r13_r14"},
- {{ne, r14, r0}, "ne, r14, r0", "ne_r14_r0"},
- {{ne, r14, r1}, "ne, r14, r1", "ne_r14_r1"},
- {{ne, r14, r2}, "ne, r14, r2", "ne_r14_r2"},
- {{ne, r14, r3}, "ne, r14, r3", "ne_r14_r3"},
- {{ne, r14, r4}, "ne, r14, r4", "ne_r14_r4"},
- {{ne, r14, r5}, "ne, r14, r5", "ne_r14_r5"},
- {{ne, r14, r6}, "ne, r14, r6", "ne_r14_r6"},
- {{ne, r14, r7}, "ne, r14, r7", "ne_r14_r7"},
- {{ne, r14, r8}, "ne, r14, r8", "ne_r14_r8"},
- {{ne, r14, r9}, "ne, r14, r9", "ne_r14_r9"},
- {{ne, r14, r10}, "ne, r14, r10", "ne_r14_r10"},
- {{ne, r14, r11}, "ne, r14, r11", "ne_r14_r11"},
- {{ne, r14, r12}, "ne, r14, r12", "ne_r14_r12"},
- {{ne, r14, r13}, "ne, r14, r13", "ne_r14_r13"},
- {{ne, r14, r14}, "ne, r14, r14", "ne_r14_r14"},
- {{cs, r0, r0}, "cs, r0, r0", "cs_r0_r0"},
- {{cs, r0, r1}, "cs, r0, r1", "cs_r0_r1"},
- {{cs, r0, r2}, "cs, r0, r2", "cs_r0_r2"},
- {{cs, r0, r3}, "cs, r0, r3", "cs_r0_r3"},
- {{cs, r0, r4}, "cs, r0, r4", "cs_r0_r4"},
- {{cs, r0, r5}, "cs, r0, r5", "cs_r0_r5"},
- {{cs, r0, r6}, "cs, r0, r6", "cs_r0_r6"},
- {{cs, r0, r7}, "cs, r0, r7", "cs_r0_r7"},
- {{cs, r0, r8}, "cs, r0, r8", "cs_r0_r8"},
- {{cs, r0, r9}, "cs, r0, r9", "cs_r0_r9"},
- {{cs, r0, r10}, "cs, r0, r10", "cs_r0_r10"},
- {{cs, r0, r11}, "cs, r0, r11", "cs_r0_r11"},
- {{cs, r0, r12}, "cs, r0, r12", "cs_r0_r12"},
- {{cs, r0, r13}, "cs, r0, r13", "cs_r0_r13"},
- {{cs, r0, r14}, "cs, r0, r14", "cs_r0_r14"},
- {{cs, r1, r0}, "cs, r1, r0", "cs_r1_r0"},
- {{cs, r1, r1}, "cs, r1, r1", "cs_r1_r1"},
- {{cs, r1, r2}, "cs, r1, r2", "cs_r1_r2"},
- {{cs, r1, r3}, "cs, r1, r3", "cs_r1_r3"},
- {{cs, r1, r4}, "cs, r1, r4", "cs_r1_r4"},
- {{cs, r1, r5}, "cs, r1, r5", "cs_r1_r5"},
- {{cs, r1, r6}, "cs, r1, r6", "cs_r1_r6"},
- {{cs, r1, r7}, "cs, r1, r7", "cs_r1_r7"},
- {{cs, r1, r8}, "cs, r1, r8", "cs_r1_r8"},
- {{cs, r1, r9}, "cs, r1, r9", "cs_r1_r9"},
- {{cs, r1, r10}, "cs, r1, r10", "cs_r1_r10"},
- {{cs, r1, r11}, "cs, r1, r11", "cs_r1_r11"},
- {{cs, r1, r12}, "cs, r1, r12", "cs_r1_r12"},
- {{cs, r1, r13}, "cs, r1, r13", "cs_r1_r13"},
- {{cs, r1, r14}, "cs, r1, r14", "cs_r1_r14"},
- {{cs, r2, r0}, "cs, r2, r0", "cs_r2_r0"},
- {{cs, r2, r1}, "cs, r2, r1", "cs_r2_r1"},
- {{cs, r2, r2}, "cs, r2, r2", "cs_r2_r2"},
- {{cs, r2, r3}, "cs, r2, r3", "cs_r2_r3"},
- {{cs, r2, r4}, "cs, r2, r4", "cs_r2_r4"},
- {{cs, r2, r5}, "cs, r2, r5", "cs_r2_r5"},
- {{cs, r2, r6}, "cs, r2, r6", "cs_r2_r6"},
- {{cs, r2, r7}, "cs, r2, r7", "cs_r2_r7"},
- {{cs, r2, r8}, "cs, r2, r8", "cs_r2_r8"},
- {{cs, r2, r9}, "cs, r2, r9", "cs_r2_r9"},
- {{cs, r2, r10}, "cs, r2, r10", "cs_r2_r10"},
- {{cs, r2, r11}, "cs, r2, r11", "cs_r2_r11"},
- {{cs, r2, r12}, "cs, r2, r12", "cs_r2_r12"},
- {{cs, r2, r13}, "cs, r2, r13", "cs_r2_r13"},
- {{cs, r2, r14}, "cs, r2, r14", "cs_r2_r14"},
- {{cs, r3, r0}, "cs, r3, r0", "cs_r3_r0"},
- {{cs, r3, r1}, "cs, r3, r1", "cs_r3_r1"},
- {{cs, r3, r2}, "cs, r3, r2", "cs_r3_r2"},
- {{cs, r3, r3}, "cs, r3, r3", "cs_r3_r3"},
- {{cs, r3, r4}, "cs, r3, r4", "cs_r3_r4"},
- {{cs, r3, r5}, "cs, r3, r5", "cs_r3_r5"},
- {{cs, r3, r6}, "cs, r3, r6", "cs_r3_r6"},
- {{cs, r3, r7}, "cs, r3, r7", "cs_r3_r7"},
- {{cs, r3, r8}, "cs, r3, r8", "cs_r3_r8"},
- {{cs, r3, r9}, "cs, r3, r9", "cs_r3_r9"},
- {{cs, r3, r10}, "cs, r3, r10", "cs_r3_r10"},
- {{cs, r3, r11}, "cs, r3, r11", "cs_r3_r11"},
- {{cs, r3, r12}, "cs, r3, r12", "cs_r3_r12"},
- {{cs, r3, r13}, "cs, r3, r13", "cs_r3_r13"},
- {{cs, r3, r14}, "cs, r3, r14", "cs_r3_r14"},
- {{cs, r4, r0}, "cs, r4, r0", "cs_r4_r0"},
- {{cs, r4, r1}, "cs, r4, r1", "cs_r4_r1"},
- {{cs, r4, r2}, "cs, r4, r2", "cs_r4_r2"},
- {{cs, r4, r3}, "cs, r4, r3", "cs_r4_r3"},
- {{cs, r4, r4}, "cs, r4, r4", "cs_r4_r4"},
- {{cs, r4, r5}, "cs, r4, r5", "cs_r4_r5"},
- {{cs, r4, r6}, "cs, r4, r6", "cs_r4_r6"},
- {{cs, r4, r7}, "cs, r4, r7", "cs_r4_r7"},
- {{cs, r4, r8}, "cs, r4, r8", "cs_r4_r8"},
- {{cs, r4, r9}, "cs, r4, r9", "cs_r4_r9"},
- {{cs, r4, r10}, "cs, r4, r10", "cs_r4_r10"},
- {{cs, r4, r11}, "cs, r4, r11", "cs_r4_r11"},
- {{cs, r4, r12}, "cs, r4, r12", "cs_r4_r12"},
- {{cs, r4, r13}, "cs, r4, r13", "cs_r4_r13"},
- {{cs, r4, r14}, "cs, r4, r14", "cs_r4_r14"},
- {{cs, r5, r0}, "cs, r5, r0", "cs_r5_r0"},
- {{cs, r5, r1}, "cs, r5, r1", "cs_r5_r1"},
- {{cs, r5, r2}, "cs, r5, r2", "cs_r5_r2"},
- {{cs, r5, r3}, "cs, r5, r3", "cs_r5_r3"},
- {{cs, r5, r4}, "cs, r5, r4", "cs_r5_r4"},
- {{cs, r5, r5}, "cs, r5, r5", "cs_r5_r5"},
- {{cs, r5, r6}, "cs, r5, r6", "cs_r5_r6"},
- {{cs, r5, r7}, "cs, r5, r7", "cs_r5_r7"},
- {{cs, r5, r8}, "cs, r5, r8", "cs_r5_r8"},
- {{cs, r5, r9}, "cs, r5, r9", "cs_r5_r9"},
- {{cs, r5, r10}, "cs, r5, r10", "cs_r5_r10"},
- {{cs, r5, r11}, "cs, r5, r11", "cs_r5_r11"},
- {{cs, r5, r12}, "cs, r5, r12", "cs_r5_r12"},
- {{cs, r5, r13}, "cs, r5, r13", "cs_r5_r13"},
- {{cs, r5, r14}, "cs, r5, r14", "cs_r5_r14"},
- {{cs, r6, r0}, "cs, r6, r0", "cs_r6_r0"},
- {{cs, r6, r1}, "cs, r6, r1", "cs_r6_r1"},
- {{cs, r6, r2}, "cs, r6, r2", "cs_r6_r2"},
- {{cs, r6, r3}, "cs, r6, r3", "cs_r6_r3"},
- {{cs, r6, r4}, "cs, r6, r4", "cs_r6_r4"},
- {{cs, r6, r5}, "cs, r6, r5", "cs_r6_r5"},
- {{cs, r6, r6}, "cs, r6, r6", "cs_r6_r6"},
- {{cs, r6, r7}, "cs, r6, r7", "cs_r6_r7"},
- {{cs, r6, r8}, "cs, r6, r8", "cs_r6_r8"},
- {{cs, r6, r9}, "cs, r6, r9", "cs_r6_r9"},
- {{cs, r6, r10}, "cs, r6, r10", "cs_r6_r10"},
- {{cs, r6, r11}, "cs, r6, r11", "cs_r6_r11"},
- {{cs, r6, r12}, "cs, r6, r12", "cs_r6_r12"},
- {{cs, r6, r13}, "cs, r6, r13", "cs_r6_r13"},
- {{cs, r6, r14}, "cs, r6, r14", "cs_r6_r14"},
- {{cs, r7, r0}, "cs, r7, r0", "cs_r7_r0"},
- {{cs, r7, r1}, "cs, r7, r1", "cs_r7_r1"},
- {{cs, r7, r2}, "cs, r7, r2", "cs_r7_r2"},
- {{cs, r7, r3}, "cs, r7, r3", "cs_r7_r3"},
- {{cs, r7, r4}, "cs, r7, r4", "cs_r7_r4"},
- {{cs, r7, r5}, "cs, r7, r5", "cs_r7_r5"},
- {{cs, r7, r6}, "cs, r7, r6", "cs_r7_r6"},
- {{cs, r7, r7}, "cs, r7, r7", "cs_r7_r7"},
- {{cs, r7, r8}, "cs, r7, r8", "cs_r7_r8"},
- {{cs, r7, r9}, "cs, r7, r9", "cs_r7_r9"},
- {{cs, r7, r10}, "cs, r7, r10", "cs_r7_r10"},
- {{cs, r7, r11}, "cs, r7, r11", "cs_r7_r11"},
- {{cs, r7, r12}, "cs, r7, r12", "cs_r7_r12"},
- {{cs, r7, r13}, "cs, r7, r13", "cs_r7_r13"},
- {{cs, r7, r14}, "cs, r7, r14", "cs_r7_r14"},
- {{cs, r8, r0}, "cs, r8, r0", "cs_r8_r0"},
- {{cs, r8, r1}, "cs, r8, r1", "cs_r8_r1"},
- {{cs, r8, r2}, "cs, r8, r2", "cs_r8_r2"},
- {{cs, r8, r3}, "cs, r8, r3", "cs_r8_r3"},
- {{cs, r8, r4}, "cs, r8, r4", "cs_r8_r4"},
- {{cs, r8, r5}, "cs, r8, r5", "cs_r8_r5"},
- {{cs, r8, r6}, "cs, r8, r6", "cs_r8_r6"},
- {{cs, r8, r7}, "cs, r8, r7", "cs_r8_r7"},
- {{cs, r8, r8}, "cs, r8, r8", "cs_r8_r8"},
- {{cs, r8, r9}, "cs, r8, r9", "cs_r8_r9"},
- {{cs, r8, r10}, "cs, r8, r10", "cs_r8_r10"},
- {{cs, r8, r11}, "cs, r8, r11", "cs_r8_r11"},
- {{cs, r8, r12}, "cs, r8, r12", "cs_r8_r12"},
- {{cs, r8, r13}, "cs, r8, r13", "cs_r8_r13"},
- {{cs, r8, r14}, "cs, r8, r14", "cs_r8_r14"},
- {{cs, r9, r0}, "cs, r9, r0", "cs_r9_r0"},
- {{cs, r9, r1}, "cs, r9, r1", "cs_r9_r1"},
- {{cs, r9, r2}, "cs, r9, r2", "cs_r9_r2"},
- {{cs, r9, r3}, "cs, r9, r3", "cs_r9_r3"},
- {{cs, r9, r4}, "cs, r9, r4", "cs_r9_r4"},
- {{cs, r9, r5}, "cs, r9, r5", "cs_r9_r5"},
- {{cs, r9, r6}, "cs, r9, r6", "cs_r9_r6"},
- {{cs, r9, r7}, "cs, r9, r7", "cs_r9_r7"},
- {{cs, r9, r8}, "cs, r9, r8", "cs_r9_r8"},
- {{cs, r9, r9}, "cs, r9, r9", "cs_r9_r9"},
- {{cs, r9, r10}, "cs, r9, r10", "cs_r9_r10"},
- {{cs, r9, r11}, "cs, r9, r11", "cs_r9_r11"},
- {{cs, r9, r12}, "cs, r9, r12", "cs_r9_r12"},
- {{cs, r9, r13}, "cs, r9, r13", "cs_r9_r13"},
- {{cs, r9, r14}, "cs, r9, r14", "cs_r9_r14"},
- {{cs, r10, r0}, "cs, r10, r0", "cs_r10_r0"},
- {{cs, r10, r1}, "cs, r10, r1", "cs_r10_r1"},
- {{cs, r10, r2}, "cs, r10, r2", "cs_r10_r2"},
- {{cs, r10, r3}, "cs, r10, r3", "cs_r10_r3"},
- {{cs, r10, r4}, "cs, r10, r4", "cs_r10_r4"},
- {{cs, r10, r5}, "cs, r10, r5", "cs_r10_r5"},
- {{cs, r10, r6}, "cs, r10, r6", "cs_r10_r6"},
- {{cs, r10, r7}, "cs, r10, r7", "cs_r10_r7"},
- {{cs, r10, r8}, "cs, r10, r8", "cs_r10_r8"},
- {{cs, r10, r9}, "cs, r10, r9", "cs_r10_r9"},
- {{cs, r10, r10}, "cs, r10, r10", "cs_r10_r10"},
- {{cs, r10, r11}, "cs, r10, r11", "cs_r10_r11"},
- {{cs, r10, r12}, "cs, r10, r12", "cs_r10_r12"},
- {{cs, r10, r13}, "cs, r10, r13", "cs_r10_r13"},
- {{cs, r10, r14}, "cs, r10, r14", "cs_r10_r14"},
- {{cs, r11, r0}, "cs, r11, r0", "cs_r11_r0"},
- {{cs, r11, r1}, "cs, r11, r1", "cs_r11_r1"},
- {{cs, r11, r2}, "cs, r11, r2", "cs_r11_r2"},
- {{cs, r11, r3}, "cs, r11, r3", "cs_r11_r3"},
- {{cs, r11, r4}, "cs, r11, r4", "cs_r11_r4"},
- {{cs, r11, r5}, "cs, r11, r5", "cs_r11_r5"},
- {{cs, r11, r6}, "cs, r11, r6", "cs_r11_r6"},
- {{cs, r11, r7}, "cs, r11, r7", "cs_r11_r7"},
- {{cs, r11, r8}, "cs, r11, r8", "cs_r11_r8"},
- {{cs, r11, r9}, "cs, r11, r9", "cs_r11_r9"},
- {{cs, r11, r10}, "cs, r11, r10", "cs_r11_r10"},
- {{cs, r11, r11}, "cs, r11, r11", "cs_r11_r11"},
- {{cs, r11, r12}, "cs, r11, r12", "cs_r11_r12"},
- {{cs, r11, r13}, "cs, r11, r13", "cs_r11_r13"},
- {{cs, r11, r14}, "cs, r11, r14", "cs_r11_r14"},
- {{cs, r12, r0}, "cs, r12, r0", "cs_r12_r0"},
- {{cs, r12, r1}, "cs, r12, r1", "cs_r12_r1"},
- {{cs, r12, r2}, "cs, r12, r2", "cs_r12_r2"},
- {{cs, r12, r3}, "cs, r12, r3", "cs_r12_r3"},
- {{cs, r12, r4}, "cs, r12, r4", "cs_r12_r4"},
- {{cs, r12, r5}, "cs, r12, r5", "cs_r12_r5"},
- {{cs, r12, r6}, "cs, r12, r6", "cs_r12_r6"},
- {{cs, r12, r7}, "cs, r12, r7", "cs_r12_r7"},
- {{cs, r12, r8}, "cs, r12, r8", "cs_r12_r8"},
- {{cs, r12, r9}, "cs, r12, r9", "cs_r12_r9"},
- {{cs, r12, r10}, "cs, r12, r10", "cs_r12_r10"},
- {{cs, r12, r11}, "cs, r12, r11", "cs_r12_r11"},
- {{cs, r12, r12}, "cs, r12, r12", "cs_r12_r12"},
- {{cs, r12, r13}, "cs, r12, r13", "cs_r12_r13"},
- {{cs, r12, r14}, "cs, r12, r14", "cs_r12_r14"},
- {{cs, r13, r0}, "cs, r13, r0", "cs_r13_r0"},
- {{cs, r13, r1}, "cs, r13, r1", "cs_r13_r1"},
- {{cs, r13, r2}, "cs, r13, r2", "cs_r13_r2"},
- {{cs, r13, r3}, "cs, r13, r3", "cs_r13_r3"},
- {{cs, r13, r4}, "cs, r13, r4", "cs_r13_r4"},
- {{cs, r13, r5}, "cs, r13, r5", "cs_r13_r5"},
- {{cs, r13, r6}, "cs, r13, r6", "cs_r13_r6"},
- {{cs, r13, r7}, "cs, r13, r7", "cs_r13_r7"},
- {{cs, r13, r8}, "cs, r13, r8", "cs_r13_r8"},
- {{cs, r13, r9}, "cs, r13, r9", "cs_r13_r9"},
- {{cs, r13, r10}, "cs, r13, r10", "cs_r13_r10"},
- {{cs, r13, r11}, "cs, r13, r11", "cs_r13_r11"},
- {{cs, r13, r12}, "cs, r13, r12", "cs_r13_r12"},
- {{cs, r13, r13}, "cs, r13, r13", "cs_r13_r13"},
- {{cs, r13, r14}, "cs, r13, r14", "cs_r13_r14"},
- {{cs, r14, r0}, "cs, r14, r0", "cs_r14_r0"},
- {{cs, r14, r1}, "cs, r14, r1", "cs_r14_r1"},
- {{cs, r14, r2}, "cs, r14, r2", "cs_r14_r2"},
- {{cs, r14, r3}, "cs, r14, r3", "cs_r14_r3"},
- {{cs, r14, r4}, "cs, r14, r4", "cs_r14_r4"},
- {{cs, r14, r5}, "cs, r14, r5", "cs_r14_r5"},
- {{cs, r14, r6}, "cs, r14, r6", "cs_r14_r6"},
- {{cs, r14, r7}, "cs, r14, r7", "cs_r14_r7"},
- {{cs, r14, r8}, "cs, r14, r8", "cs_r14_r8"},
- {{cs, r14, r9}, "cs, r14, r9", "cs_r14_r9"},
- {{cs, r14, r10}, "cs, r14, r10", "cs_r14_r10"},
- {{cs, r14, r11}, "cs, r14, r11", "cs_r14_r11"},
- {{cs, r14, r12}, "cs, r14, r12", "cs_r14_r12"},
- {{cs, r14, r13}, "cs, r14, r13", "cs_r14_r13"},
- {{cs, r14, r14}, "cs, r14, r14", "cs_r14_r14"},
- {{cc, r0, r0}, "cc, r0, r0", "cc_r0_r0"},
- {{cc, r0, r1}, "cc, r0, r1", "cc_r0_r1"},
- {{cc, r0, r2}, "cc, r0, r2", "cc_r0_r2"},
- {{cc, r0, r3}, "cc, r0, r3", "cc_r0_r3"},
- {{cc, r0, r4}, "cc, r0, r4", "cc_r0_r4"},
- {{cc, r0, r5}, "cc, r0, r5", "cc_r0_r5"},
- {{cc, r0, r6}, "cc, r0, r6", "cc_r0_r6"},
- {{cc, r0, r7}, "cc, r0, r7", "cc_r0_r7"},
- {{cc, r0, r8}, "cc, r0, r8", "cc_r0_r8"},
- {{cc, r0, r9}, "cc, r0, r9", "cc_r0_r9"},
- {{cc, r0, r10}, "cc, r0, r10", "cc_r0_r10"},
- {{cc, r0, r11}, "cc, r0, r11", "cc_r0_r11"},
- {{cc, r0, r12}, "cc, r0, r12", "cc_r0_r12"},
- {{cc, r0, r13}, "cc, r0, r13", "cc_r0_r13"},
- {{cc, r0, r14}, "cc, r0, r14", "cc_r0_r14"},
- {{cc, r1, r0}, "cc, r1, r0", "cc_r1_r0"},
- {{cc, r1, r1}, "cc, r1, r1", "cc_r1_r1"},
- {{cc, r1, r2}, "cc, r1, r2", "cc_r1_r2"},
- {{cc, r1, r3}, "cc, r1, r3", "cc_r1_r3"},
- {{cc, r1, r4}, "cc, r1, r4", "cc_r1_r4"},
- {{cc, r1, r5}, "cc, r1, r5", "cc_r1_r5"},
- {{cc, r1, r6}, "cc, r1, r6", "cc_r1_r6"},
- {{cc, r1, r7}, "cc, r1, r7", "cc_r1_r7"},
- {{cc, r1, r8}, "cc, r1, r8", "cc_r1_r8"},
- {{cc, r1, r9}, "cc, r1, r9", "cc_r1_r9"},
- {{cc, r1, r10}, "cc, r1, r10", "cc_r1_r10"},
- {{cc, r1, r11}, "cc, r1, r11", "cc_r1_r11"},
- {{cc, r1, r12}, "cc, r1, r12", "cc_r1_r12"},
- {{cc, r1, r13}, "cc, r1, r13", "cc_r1_r13"},
- {{cc, r1, r14}, "cc, r1, r14", "cc_r1_r14"},
- {{cc, r2, r0}, "cc, r2, r0", "cc_r2_r0"},
- {{cc, r2, r1}, "cc, r2, r1", "cc_r2_r1"},
- {{cc, r2, r2}, "cc, r2, r2", "cc_r2_r2"},
- {{cc, r2, r3}, "cc, r2, r3", "cc_r2_r3"},
- {{cc, r2, r4}, "cc, r2, r4", "cc_r2_r4"},
- {{cc, r2, r5}, "cc, r2, r5", "cc_r2_r5"},
- {{cc, r2, r6}, "cc, r2, r6", "cc_r2_r6"},
- {{cc, r2, r7}, "cc, r2, r7", "cc_r2_r7"},
- {{cc, r2, r8}, "cc, r2, r8", "cc_r2_r8"},
- {{cc, r2, r9}, "cc, r2, r9", "cc_r2_r9"},
- {{cc, r2, r10}, "cc, r2, r10", "cc_r2_r10"},
- {{cc, r2, r11}, "cc, r2, r11", "cc_r2_r11"},
- {{cc, r2, r12}, "cc, r2, r12", "cc_r2_r12"},
- {{cc, r2, r13}, "cc, r2, r13", "cc_r2_r13"},
- {{cc, r2, r14}, "cc, r2, r14", "cc_r2_r14"},
- {{cc, r3, r0}, "cc, r3, r0", "cc_r3_r0"},
- {{cc, r3, r1}, "cc, r3, r1", "cc_r3_r1"},
- {{cc, r3, r2}, "cc, r3, r2", "cc_r3_r2"},
- {{cc, r3, r3}, "cc, r3, r3", "cc_r3_r3"},
- {{cc, r3, r4}, "cc, r3, r4", "cc_r3_r4"},
- {{cc, r3, r5}, "cc, r3, r5", "cc_r3_r5"},
- {{cc, r3, r6}, "cc, r3, r6", "cc_r3_r6"},
- {{cc, r3, r7}, "cc, r3, r7", "cc_r3_r7"},
- {{cc, r3, r8}, "cc, r3, r8", "cc_r3_r8"},
- {{cc, r3, r9}, "cc, r3, r9", "cc_r3_r9"},
- {{cc, r3, r10}, "cc, r3, r10", "cc_r3_r10"},
- {{cc, r3, r11}, "cc, r3, r11", "cc_r3_r11"},
- {{cc, r3, r12}, "cc, r3, r12", "cc_r3_r12"},
- {{cc, r3, r13}, "cc, r3, r13", "cc_r3_r13"},
- {{cc, r3, r14}, "cc, r3, r14", "cc_r3_r14"},
- {{cc, r4, r0}, "cc, r4, r0", "cc_r4_r0"},
- {{cc, r4, r1}, "cc, r4, r1", "cc_r4_r1"},
- {{cc, r4, r2}, "cc, r4, r2", "cc_r4_r2"},
- {{cc, r4, r3}, "cc, r4, r3", "cc_r4_r3"},
- {{cc, r4, r4}, "cc, r4, r4", "cc_r4_r4"},
- {{cc, r4, r5}, "cc, r4, r5", "cc_r4_r5"},
- {{cc, r4, r6}, "cc, r4, r6", "cc_r4_r6"},
- {{cc, r4, r7}, "cc, r4, r7", "cc_r4_r7"},
- {{cc, r4, r8}, "cc, r4, r8", "cc_r4_r8"},
- {{cc, r4, r9}, "cc, r4, r9", "cc_r4_r9"},
- {{cc, r4, r10}, "cc, r4, r10", "cc_r4_r10"},
- {{cc, r4, r11}, "cc, r4, r11", "cc_r4_r11"},
- {{cc, r4, r12}, "cc, r4, r12", "cc_r4_r12"},
- {{cc, r4, r13}, "cc, r4, r13", "cc_r4_r13"},
- {{cc, r4, r14}, "cc, r4, r14", "cc_r4_r14"},
- {{cc, r5, r0}, "cc, r5, r0", "cc_r5_r0"},
- {{cc, r5, r1}, "cc, r5, r1", "cc_r5_r1"},
- {{cc, r5, r2}, "cc, r5, r2", "cc_r5_r2"},
- {{cc, r5, r3}, "cc, r5, r3", "cc_r5_r3"},
- {{cc, r5, r4}, "cc, r5, r4", "cc_r5_r4"},
- {{cc, r5, r5}, "cc, r5, r5", "cc_r5_r5"},
- {{cc, r5, r6}, "cc, r5, r6", "cc_r5_r6"},
- {{cc, r5, r7}, "cc, r5, r7", "cc_r5_r7"},
- {{cc, r5, r8}, "cc, r5, r8", "cc_r5_r8"},
- {{cc, r5, r9}, "cc, r5, r9", "cc_r5_r9"},
- {{cc, r5, r10}, "cc, r5, r10", "cc_r5_r10"},
- {{cc, r5, r11}, "cc, r5, r11", "cc_r5_r11"},
- {{cc, r5, r12}, "cc, r5, r12", "cc_r5_r12"},
- {{cc, r5, r13}, "cc, r5, r13", "cc_r5_r13"},
- {{cc, r5, r14}, "cc, r5, r14", "cc_r5_r14"},
- {{cc, r6, r0}, "cc, r6, r0", "cc_r6_r0"},
- {{cc, r6, r1}, "cc, r6, r1", "cc_r6_r1"},
- {{cc, r6, r2}, "cc, r6, r2", "cc_r6_r2"},
- {{cc, r6, r3}, "cc, r6, r3", "cc_r6_r3"},
- {{cc, r6, r4}, "cc, r6, r4", "cc_r6_r4"},
- {{cc, r6, r5}, "cc, r6, r5", "cc_r6_r5"},
- {{cc, r6, r6}, "cc, r6, r6", "cc_r6_r6"},
- {{cc, r6, r7}, "cc, r6, r7", "cc_r6_r7"},
- {{cc, r6, r8}, "cc, r6, r8", "cc_r6_r8"},
- {{cc, r6, r9}, "cc, r6, r9", "cc_r6_r9"},
- {{cc, r6, r10}, "cc, r6, r10", "cc_r6_r10"},
- {{cc, r6, r11}, "cc, r6, r11", "cc_r6_r11"},
- {{cc, r6, r12}, "cc, r6, r12", "cc_r6_r12"},
- {{cc, r6, r13}, "cc, r6, r13", "cc_r6_r13"},
- {{cc, r6, r14}, "cc, r6, r14", "cc_r6_r14"},
- {{cc, r7, r0}, "cc, r7, r0", "cc_r7_r0"},
- {{cc, r7, r1}, "cc, r7, r1", "cc_r7_r1"},
- {{cc, r7, r2}, "cc, r7, r2", "cc_r7_r2"},
- {{cc, r7, r3}, "cc, r7, r3", "cc_r7_r3"},
- {{cc, r7, r4}, "cc, r7, r4", "cc_r7_r4"},
- {{cc, r7, r5}, "cc, r7, r5", "cc_r7_r5"},
- {{cc, r7, r6}, "cc, r7, r6", "cc_r7_r6"},
- {{cc, r7, r7}, "cc, r7, r7", "cc_r7_r7"},
- {{cc, r7, r8}, "cc, r7, r8", "cc_r7_r8"},
- {{cc, r7, r9}, "cc, r7, r9", "cc_r7_r9"},
- {{cc, r7, r10}, "cc, r7, r10", "cc_r7_r10"},
- {{cc, r7, r11}, "cc, r7, r11", "cc_r7_r11"},
- {{cc, r7, r12}, "cc, r7, r12", "cc_r7_r12"},
- {{cc, r7, r13}, "cc, r7, r13", "cc_r7_r13"},
- {{cc, r7, r14}, "cc, r7, r14", "cc_r7_r14"},
- {{cc, r8, r0}, "cc, r8, r0", "cc_r8_r0"},
- {{cc, r8, r1}, "cc, r8, r1", "cc_r8_r1"},
- {{cc, r8, r2}, "cc, r8, r2", "cc_r8_r2"},
- {{cc, r8, r3}, "cc, r8, r3", "cc_r8_r3"},
- {{cc, r8, r4}, "cc, r8, r4", "cc_r8_r4"},
- {{cc, r8, r5}, "cc, r8, r5", "cc_r8_r5"},
- {{cc, r8, r6}, "cc, r8, r6", "cc_r8_r6"},
- {{cc, r8, r7}, "cc, r8, r7", "cc_r8_r7"},
- {{cc, r8, r8}, "cc, r8, r8", "cc_r8_r8"},
- {{cc, r8, r9}, "cc, r8, r9", "cc_r8_r9"},
- {{cc, r8, r10}, "cc, r8, r10", "cc_r8_r10"},
- {{cc, r8, r11}, "cc, r8, r11", "cc_r8_r11"},
- {{cc, r8, r12}, "cc, r8, r12", "cc_r8_r12"},
- {{cc, r8, r13}, "cc, r8, r13", "cc_r8_r13"},
- {{cc, r8, r14}, "cc, r8, r14", "cc_r8_r14"},
- {{cc, r9, r0}, "cc, r9, r0", "cc_r9_r0"},
- {{cc, r9, r1}, "cc, r9, r1", "cc_r9_r1"},
- {{cc, r9, r2}, "cc, r9, r2", "cc_r9_r2"},
- {{cc, r9, r3}, "cc, r9, r3", "cc_r9_r3"},
- {{cc, r9, r4}, "cc, r9, r4", "cc_r9_r4"},
- {{cc, r9, r5}, "cc, r9, r5", "cc_r9_r5"},
- {{cc, r9, r6}, "cc, r9, r6", "cc_r9_r6"},
- {{cc, r9, r7}, "cc, r9, r7", "cc_r9_r7"},
- {{cc, r9, r8}, "cc, r9, r8", "cc_r9_r8"},
- {{cc, r9, r9}, "cc, r9, r9", "cc_r9_r9"},
- {{cc, r9, r10}, "cc, r9, r10", "cc_r9_r10"},
- {{cc, r9, r11}, "cc, r9, r11", "cc_r9_r11"},
- {{cc, r9, r12}, "cc, r9, r12", "cc_r9_r12"},
- {{cc, r9, r13}, "cc, r9, r13", "cc_r9_r13"},
- {{cc, r9, r14}, "cc, r9, r14", "cc_r9_r14"},
- {{cc, r10, r0}, "cc, r10, r0", "cc_r10_r0"},
- {{cc, r10, r1}, "cc, r10, r1", "cc_r10_r1"},
- {{cc, r10, r2}, "cc, r10, r2", "cc_r10_r2"},
- {{cc, r10, r3}, "cc, r10, r3", "cc_r10_r3"},
- {{cc, r10, r4}, "cc, r10, r4", "cc_r10_r4"},
- {{cc, r10, r5}, "cc, r10, r5", "cc_r10_r5"},
- {{cc, r10, r6}, "cc, r10, r6", "cc_r10_r6"},
- {{cc, r10, r7}, "cc, r10, r7", "cc_r10_r7"},
- {{cc, r10, r8}, "cc, r10, r8", "cc_r10_r8"},
- {{cc, r10, r9}, "cc, r10, r9", "cc_r10_r9"},
- {{cc, r10, r10}, "cc, r10, r10", "cc_r10_r10"},
- {{cc, r10, r11}, "cc, r10, r11", "cc_r10_r11"},
- {{cc, r10, r12}, "cc, r10, r12", "cc_r10_r12"},
- {{cc, r10, r13}, "cc, r10, r13", "cc_r10_r13"},
- {{cc, r10, r14}, "cc, r10, r14", "cc_r10_r14"},
- {{cc, r11, r0}, "cc, r11, r0", "cc_r11_r0"},
- {{cc, r11, r1}, "cc, r11, r1", "cc_r11_r1"},
- {{cc, r11, r2}, "cc, r11, r2", "cc_r11_r2"},
- {{cc, r11, r3}, "cc, r11, r3", "cc_r11_r3"},
- {{cc, r11, r4}, "cc, r11, r4", "cc_r11_r4"},
- {{cc, r11, r5}, "cc, r11, r5", "cc_r11_r5"},
- {{cc, r11, r6}, "cc, r11, r6", "cc_r11_r6"},
- {{cc, r11, r7}, "cc, r11, r7", "cc_r11_r7"},
- {{cc, r11, r8}, "cc, r11, r8", "cc_r11_r8"},
- {{cc, r11, r9}, "cc, r11, r9", "cc_r11_r9"},
- {{cc, r11, r10}, "cc, r11, r10", "cc_r11_r10"},
- {{cc, r11, r11}, "cc, r11, r11", "cc_r11_r11"},
- {{cc, r11, r12}, "cc, r11, r12", "cc_r11_r12"},
- {{cc, r11, r13}, "cc, r11, r13", "cc_r11_r13"},
- {{cc, r11, r14}, "cc, r11, r14", "cc_r11_r14"},
- {{cc, r12, r0}, "cc, r12, r0", "cc_r12_r0"},
- {{cc, r12, r1}, "cc, r12, r1", "cc_r12_r1"},
- {{cc, r12, r2}, "cc, r12, r2", "cc_r12_r2"},
- {{cc, r12, r3}, "cc, r12, r3", "cc_r12_r3"},
- {{cc, r12, r4}, "cc, r12, r4", "cc_r12_r4"},
- {{cc, r12, r5}, "cc, r12, r5", "cc_r12_r5"},
- {{cc, r12, r6}, "cc, r12, r6", "cc_r12_r6"},
- {{cc, r12, r7}, "cc, r12, r7", "cc_r12_r7"},
- {{cc, r12, r8}, "cc, r12, r8", "cc_r12_r8"},
- {{cc, r12, r9}, "cc, r12, r9", "cc_r12_r9"},
- {{cc, r12, r10}, "cc, r12, r10", "cc_r12_r10"},
- {{cc, r12, r11}, "cc, r12, r11", "cc_r12_r11"},
- {{cc, r12, r12}, "cc, r12, r12", "cc_r12_r12"},
- {{cc, r12, r13}, "cc, r12, r13", "cc_r12_r13"},
- {{cc, r12, r14}, "cc, r12, r14", "cc_r12_r14"},
- {{cc, r13, r0}, "cc, r13, r0", "cc_r13_r0"},
- {{cc, r13, r1}, "cc, r13, r1", "cc_r13_r1"},
- {{cc, r13, r2}, "cc, r13, r2", "cc_r13_r2"},
- {{cc, r13, r3}, "cc, r13, r3", "cc_r13_r3"},
- {{cc, r13, r4}, "cc, r13, r4", "cc_r13_r4"},
- {{cc, r13, r5}, "cc, r13, r5", "cc_r13_r5"},
- {{cc, r13, r6}, "cc, r13, r6", "cc_r13_r6"},
- {{cc, r13, r7}, "cc, r13, r7", "cc_r13_r7"},
- {{cc, r13, r8}, "cc, r13, r8", "cc_r13_r8"},
- {{cc, r13, r9}, "cc, r13, r9", "cc_r13_r9"},
- {{cc, r13, r10}, "cc, r13, r10", "cc_r13_r10"},
- {{cc, r13, r11}, "cc, r13, r11", "cc_r13_r11"},
- {{cc, r13, r12}, "cc, r13, r12", "cc_r13_r12"},
- {{cc, r13, r13}, "cc, r13, r13", "cc_r13_r13"},
- {{cc, r13, r14}, "cc, r13, r14", "cc_r13_r14"},
- {{cc, r14, r0}, "cc, r14, r0", "cc_r14_r0"},
- {{cc, r14, r1}, "cc, r14, r1", "cc_r14_r1"},
- {{cc, r14, r2}, "cc, r14, r2", "cc_r14_r2"},
- {{cc, r14, r3}, "cc, r14, r3", "cc_r14_r3"},
- {{cc, r14, r4}, "cc, r14, r4", "cc_r14_r4"},
- {{cc, r14, r5}, "cc, r14, r5", "cc_r14_r5"},
- {{cc, r14, r6}, "cc, r14, r6", "cc_r14_r6"},
- {{cc, r14, r7}, "cc, r14, r7", "cc_r14_r7"},
- {{cc, r14, r8}, "cc, r14, r8", "cc_r14_r8"},
- {{cc, r14, r9}, "cc, r14, r9", "cc_r14_r9"},
- {{cc, r14, r10}, "cc, r14, r10", "cc_r14_r10"},
- {{cc, r14, r11}, "cc, r14, r11", "cc_r14_r11"},
- {{cc, r14, r12}, "cc, r14, r12", "cc_r14_r12"},
- {{cc, r14, r13}, "cc, r14, r13", "cc_r14_r13"},
- {{cc, r14, r14}, "cc, r14, r14", "cc_r14_r14"},
- {{mi, r0, r0}, "mi, r0, r0", "mi_r0_r0"},
- {{mi, r0, r1}, "mi, r0, r1", "mi_r0_r1"},
- {{mi, r0, r2}, "mi, r0, r2", "mi_r0_r2"},
- {{mi, r0, r3}, "mi, r0, r3", "mi_r0_r3"},
- {{mi, r0, r4}, "mi, r0, r4", "mi_r0_r4"},
- {{mi, r0, r5}, "mi, r0, r5", "mi_r0_r5"},
- {{mi, r0, r6}, "mi, r0, r6", "mi_r0_r6"},
- {{mi, r0, r7}, "mi, r0, r7", "mi_r0_r7"},
- {{mi, r0, r8}, "mi, r0, r8", "mi_r0_r8"},
- {{mi, r0, r9}, "mi, r0, r9", "mi_r0_r9"},
- {{mi, r0, r10}, "mi, r0, r10", "mi_r0_r10"},
- {{mi, r0, r11}, "mi, r0, r11", "mi_r0_r11"},
- {{mi, r0, r12}, "mi, r0, r12", "mi_r0_r12"},
- {{mi, r0, r13}, "mi, r0, r13", "mi_r0_r13"},
- {{mi, r0, r14}, "mi, r0, r14", "mi_r0_r14"},
- {{mi, r1, r0}, "mi, r1, r0", "mi_r1_r0"},
- {{mi, r1, r1}, "mi, r1, r1", "mi_r1_r1"},
- {{mi, r1, r2}, "mi, r1, r2", "mi_r1_r2"},
- {{mi, r1, r3}, "mi, r1, r3", "mi_r1_r3"},
- {{mi, r1, r4}, "mi, r1, r4", "mi_r1_r4"},
- {{mi, r1, r5}, "mi, r1, r5", "mi_r1_r5"},
- {{mi, r1, r6}, "mi, r1, r6", "mi_r1_r6"},
- {{mi, r1, r7}, "mi, r1, r7", "mi_r1_r7"},
- {{mi, r1, r8}, "mi, r1, r8", "mi_r1_r8"},
- {{mi, r1, r9}, "mi, r1, r9", "mi_r1_r9"},
- {{mi, r1, r10}, "mi, r1, r10", "mi_r1_r10"},
- {{mi, r1, r11}, "mi, r1, r11", "mi_r1_r11"},
- {{mi, r1, r12}, "mi, r1, r12", "mi_r1_r12"},
- {{mi, r1, r13}, "mi, r1, r13", "mi_r1_r13"},
- {{mi, r1, r14}, "mi, r1, r14", "mi_r1_r14"},
- {{mi, r2, r0}, "mi, r2, r0", "mi_r2_r0"},
- {{mi, r2, r1}, "mi, r2, r1", "mi_r2_r1"},
- {{mi, r2, r2}, "mi, r2, r2", "mi_r2_r2"},
- {{mi, r2, r3}, "mi, r2, r3", "mi_r2_r3"},
- {{mi, r2, r4}, "mi, r2, r4", "mi_r2_r4"},
- {{mi, r2, r5}, "mi, r2, r5", "mi_r2_r5"},
- {{mi, r2, r6}, "mi, r2, r6", "mi_r2_r6"},
- {{mi, r2, r7}, "mi, r2, r7", "mi_r2_r7"},
- {{mi, r2, r8}, "mi, r2, r8", "mi_r2_r8"},
- {{mi, r2, r9}, "mi, r2, r9", "mi_r2_r9"},
- {{mi, r2, r10}, "mi, r2, r10", "mi_r2_r10"},
- {{mi, r2, r11}, "mi, r2, r11", "mi_r2_r11"},
- {{mi, r2, r12}, "mi, r2, r12", "mi_r2_r12"},
- {{mi, r2, r13}, "mi, r2, r13", "mi_r2_r13"},
- {{mi, r2, r14}, "mi, r2, r14", "mi_r2_r14"},
- {{mi, r3, r0}, "mi, r3, r0", "mi_r3_r0"},
- {{mi, r3, r1}, "mi, r3, r1", "mi_r3_r1"},
- {{mi, r3, r2}, "mi, r3, r2", "mi_r3_r2"},
- {{mi, r3, r3}, "mi, r3, r3", "mi_r3_r3"},
- {{mi, r3, r4}, "mi, r3, r4", "mi_r3_r4"},
- {{mi, r3, r5}, "mi, r3, r5", "mi_r3_r5"},
- {{mi, r3, r6}, "mi, r3, r6", "mi_r3_r6"},
- {{mi, r3, r7}, "mi, r3, r7", "mi_r3_r7"},
- {{mi, r3, r8}, "mi, r3, r8", "mi_r3_r8"},
- {{mi, r3, r9}, "mi, r3, r9", "mi_r3_r9"},
- {{mi, r3, r10}, "mi, r3, r10", "mi_r3_r10"},
- {{mi, r3, r11}, "mi, r3, r11", "mi_r3_r11"},
- {{mi, r3, r12}, "mi, r3, r12", "mi_r3_r12"},
- {{mi, r3, r13}, "mi, r3, r13", "mi_r3_r13"},
- {{mi, r3, r14}, "mi, r3, r14", "mi_r3_r14"},
- {{mi, r4, r0}, "mi, r4, r0", "mi_r4_r0"},
- {{mi, r4, r1}, "mi, r4, r1", "mi_r4_r1"},
- {{mi, r4, r2}, "mi, r4, r2", "mi_r4_r2"},
- {{mi, r4, r3}, "mi, r4, r3", "mi_r4_r3"},
- {{mi, r4, r4}, "mi, r4, r4", "mi_r4_r4"},
- {{mi, r4, r5}, "mi, r4, r5", "mi_r4_r5"},
- {{mi, r4, r6}, "mi, r4, r6", "mi_r4_r6"},
- {{mi, r4, r7}, "mi, r4, r7", "mi_r4_r7"},
- {{mi, r4, r8}, "mi, r4, r8", "mi_r4_r8"},
- {{mi, r4, r9}, "mi, r4, r9", "mi_r4_r9"},
- {{mi, r4, r10}, "mi, r4, r10", "mi_r4_r10"},
- {{mi, r4, r11}, "mi, r4, r11", "mi_r4_r11"},
- {{mi, r4, r12}, "mi, r4, r12", "mi_r4_r12"},
- {{mi, r4, r13}, "mi, r4, r13", "mi_r4_r13"},
- {{mi, r4, r14}, "mi, r4, r14", "mi_r4_r14"},
- {{mi, r5, r0}, "mi, r5, r0", "mi_r5_r0"},
- {{mi, r5, r1}, "mi, r5, r1", "mi_r5_r1"},
- {{mi, r5, r2}, "mi, r5, r2", "mi_r5_r2"},
- {{mi, r5, r3}, "mi, r5, r3", "mi_r5_r3"},
- {{mi, r5, r4}, "mi, r5, r4", "mi_r5_r4"},
- {{mi, r5, r5}, "mi, r5, r5", "mi_r5_r5"},
- {{mi, r5, r6}, "mi, r5, r6", "mi_r5_r6"},
- {{mi, r5, r7}, "mi, r5, r7", "mi_r5_r7"},
- {{mi, r5, r8}, "mi, r5, r8", "mi_r5_r8"},
- {{mi, r5, r9}, "mi, r5, r9", "mi_r5_r9"},
- {{mi, r5, r10}, "mi, r5, r10", "mi_r5_r10"},
- {{mi, r5, r11}, "mi, r5, r11", "mi_r5_r11"},
- {{mi, r5, r12}, "mi, r5, r12", "mi_r5_r12"},
- {{mi, r5, r13}, "mi, r5, r13", "mi_r5_r13"},
- {{mi, r5, r14}, "mi, r5, r14", "mi_r5_r14"},
- {{mi, r6, r0}, "mi, r6, r0", "mi_r6_r0"},
- {{mi, r6, r1}, "mi, r6, r1", "mi_r6_r1"},
- {{mi, r6, r2}, "mi, r6, r2", "mi_r6_r2"},
- {{mi, r6, r3}, "mi, r6, r3", "mi_r6_r3"},
- {{mi, r6, r4}, "mi, r6, r4", "mi_r6_r4"},
- {{mi, r6, r5}, "mi, r6, r5", "mi_r6_r5"},
- {{mi, r6, r6}, "mi, r6, r6", "mi_r6_r6"},
- {{mi, r6, r7}, "mi, r6, r7", "mi_r6_r7"},
- {{mi, r6, r8}, "mi, r6, r8", "mi_r6_r8"},
- {{mi, r6, r9}, "mi, r6, r9", "mi_r6_r9"},
- {{mi, r6, r10}, "mi, r6, r10", "mi_r6_r10"},
- {{mi, r6, r11}, "mi, r6, r11", "mi_r6_r11"},
- {{mi, r6, r12}, "mi, r6, r12", "mi_r6_r12"},
- {{mi, r6, r13}, "mi, r6, r13", "mi_r6_r13"},
- {{mi, r6, r14}, "mi, r6, r14", "mi_r6_r14"},
- {{mi, r7, r0}, "mi, r7, r0", "mi_r7_r0"},
- {{mi, r7, r1}, "mi, r7, r1", "mi_r7_r1"},
- {{mi, r7, r2}, "mi, r7, r2", "mi_r7_r2"},
- {{mi, r7, r3}, "mi, r7, r3", "mi_r7_r3"},
- {{mi, r7, r4}, "mi, r7, r4", "mi_r7_r4"},
- {{mi, r7, r5}, "mi, r7, r5", "mi_r7_r5"},
- {{mi, r7, r6}, "mi, r7, r6", "mi_r7_r6"},
- {{mi, r7, r7}, "mi, r7, r7", "mi_r7_r7"},
- {{mi, r7, r8}, "mi, r7, r8", "mi_r7_r8"},
- {{mi, r7, r9}, "mi, r7, r9", "mi_r7_r9"},
- {{mi, r7, r10}, "mi, r7, r10", "mi_r7_r10"},
- {{mi, r7, r11}, "mi, r7, r11", "mi_r7_r11"},
- {{mi, r7, r12}, "mi, r7, r12", "mi_r7_r12"},
- {{mi, r7, r13}, "mi, r7, r13", "mi_r7_r13"},
- {{mi, r7, r14}, "mi, r7, r14", "mi_r7_r14"},
- {{mi, r8, r0}, "mi, r8, r0", "mi_r8_r0"},
- {{mi, r8, r1}, "mi, r8, r1", "mi_r8_r1"},
- {{mi, r8, r2}, "mi, r8, r2", "mi_r8_r2"},
- {{mi, r8, r3}, "mi, r8, r3", "mi_r8_r3"},
- {{mi, r8, r4}, "mi, r8, r4", "mi_r8_r4"},
- {{mi, r8, r5}, "mi, r8, r5", "mi_r8_r5"},
- {{mi, r8, r6}, "mi, r8, r6", "mi_r8_r6"},
- {{mi, r8, r7}, "mi, r8, r7", "mi_r8_r7"},
- {{mi, r8, r8}, "mi, r8, r8", "mi_r8_r8"},
- {{mi, r8, r9}, "mi, r8, r9", "mi_r8_r9"},
- {{mi, r8, r10}, "mi, r8, r10", "mi_r8_r10"},
- {{mi, r8, r11}, "mi, r8, r11", "mi_r8_r11"},
- {{mi, r8, r12}, "mi, r8, r12", "mi_r8_r12"},
- {{mi, r8, r13}, "mi, r8, r13", "mi_r8_r13"},
- {{mi, r8, r14}, "mi, r8, r14", "mi_r8_r14"},
- {{mi, r9, r0}, "mi, r9, r0", "mi_r9_r0"},
- {{mi, r9, r1}, "mi, r9, r1", "mi_r9_r1"},
- {{mi, r9, r2}, "mi, r9, r2", "mi_r9_r2"},
- {{mi, r9, r3}, "mi, r9, r3", "mi_r9_r3"},
- {{mi, r9, r4}, "mi, r9, r4", "mi_r9_r4"},
- {{mi, r9, r5}, "mi, r9, r5", "mi_r9_r5"},
- {{mi, r9, r6}, "mi, r9, r6", "mi_r9_r6"},
- {{mi, r9, r7}, "mi, r9, r7", "mi_r9_r7"},
- {{mi, r9, r8}, "mi, r9, r8", "mi_r9_r8"},
- {{mi, r9, r9}, "mi, r9, r9", "mi_r9_r9"},
- {{mi, r9, r10}, "mi, r9, r10", "mi_r9_r10"},
- {{mi, r9, r11}, "mi, r9, r11", "mi_r9_r11"},
- {{mi, r9, r12}, "mi, r9, r12", "mi_r9_r12"},
- {{mi, r9, r13}, "mi, r9, r13", "mi_r9_r13"},
- {{mi, r9, r14}, "mi, r9, r14", "mi_r9_r14"},
- {{mi, r10, r0}, "mi, r10, r0", "mi_r10_r0"},
- {{mi, r10, r1}, "mi, r10, r1", "mi_r10_r1"},
- {{mi, r10, r2}, "mi, r10, r2", "mi_r10_r2"},
- {{mi, r10, r3}, "mi, r10, r3", "mi_r10_r3"},
- {{mi, r10, r4}, "mi, r10, r4", "mi_r10_r4"},
- {{mi, r10, r5}, "mi, r10, r5", "mi_r10_r5"},
- {{mi, r10, r6}, "mi, r10, r6", "mi_r10_r6"},
- {{mi, r10, r7}, "mi, r10, r7", "mi_r10_r7"},
- {{mi, r10, r8}, "mi, r10, r8", "mi_r10_r8"},
{{mi, r10, r9}, "mi, r10, r9", "mi_r10_r9"},
- {{mi, r10, r10}, "mi, r10, r10", "mi_r10_r10"},
- {{mi, r10, r11}, "mi, r10, r11", "mi_r10_r11"},
- {{mi, r10, r12}, "mi, r10, r12", "mi_r10_r12"},
- {{mi, r10, r13}, "mi, r10, r13", "mi_r10_r13"},
- {{mi, r10, r14}, "mi, r10, r14", "mi_r10_r14"},
- {{mi, r11, r0}, "mi, r11, r0", "mi_r11_r0"},
- {{mi, r11, r1}, "mi, r11, r1", "mi_r11_r1"},
- {{mi, r11, r2}, "mi, r11, r2", "mi_r11_r2"},
- {{mi, r11, r3}, "mi, r11, r3", "mi_r11_r3"},
- {{mi, r11, r4}, "mi, r11, r4", "mi_r11_r4"},
- {{mi, r11, r5}, "mi, r11, r5", "mi_r11_r5"},
- {{mi, r11, r6}, "mi, r11, r6", "mi_r11_r6"},
- {{mi, r11, r7}, "mi, r11, r7", "mi_r11_r7"},
- {{mi, r11, r8}, "mi, r11, r8", "mi_r11_r8"},
- {{mi, r11, r9}, "mi, r11, r9", "mi_r11_r9"},
- {{mi, r11, r10}, "mi, r11, r10", "mi_r11_r10"},
- {{mi, r11, r11}, "mi, r11, r11", "mi_r11_r11"},
- {{mi, r11, r12}, "mi, r11, r12", "mi_r11_r12"},
- {{mi, r11, r13}, "mi, r11, r13", "mi_r11_r13"},
- {{mi, r11, r14}, "mi, r11, r14", "mi_r11_r14"},
- {{mi, r12, r0}, "mi, r12, r0", "mi_r12_r0"},
- {{mi, r12, r1}, "mi, r12, r1", "mi_r12_r1"},
- {{mi, r12, r2}, "mi, r12, r2", "mi_r12_r2"},
- {{mi, r12, r3}, "mi, r12, r3", "mi_r12_r3"},
- {{mi, r12, r4}, "mi, r12, r4", "mi_r12_r4"},
- {{mi, r12, r5}, "mi, r12, r5", "mi_r12_r5"},
- {{mi, r12, r6}, "mi, r12, r6", "mi_r12_r6"},
- {{mi, r12, r7}, "mi, r12, r7", "mi_r12_r7"},
- {{mi, r12, r8}, "mi, r12, r8", "mi_r12_r8"},
- {{mi, r12, r9}, "mi, r12, r9", "mi_r12_r9"},
- {{mi, r12, r10}, "mi, r12, r10", "mi_r12_r10"},
- {{mi, r12, r11}, "mi, r12, r11", "mi_r12_r11"},
- {{mi, r12, r12}, "mi, r12, r12", "mi_r12_r12"},
- {{mi, r12, r13}, "mi, r12, r13", "mi_r12_r13"},
- {{mi, r12, r14}, "mi, r12, r14", "mi_r12_r14"},
- {{mi, r13, r0}, "mi, r13, r0", "mi_r13_r0"},
- {{mi, r13, r1}, "mi, r13, r1", "mi_r13_r1"},
- {{mi, r13, r2}, "mi, r13, r2", "mi_r13_r2"},
- {{mi, r13, r3}, "mi, r13, r3", "mi_r13_r3"},
- {{mi, r13, r4}, "mi, r13, r4", "mi_r13_r4"},
- {{mi, r13, r5}, "mi, r13, r5", "mi_r13_r5"},
- {{mi, r13, r6}, "mi, r13, r6", "mi_r13_r6"},
- {{mi, r13, r7}, "mi, r13, r7", "mi_r13_r7"},
- {{mi, r13, r8}, "mi, r13, r8", "mi_r13_r8"},
- {{mi, r13, r9}, "mi, r13, r9", "mi_r13_r9"},
- {{mi, r13, r10}, "mi, r13, r10", "mi_r13_r10"},
- {{mi, r13, r11}, "mi, r13, r11", "mi_r13_r11"},
- {{mi, r13, r12}, "mi, r13, r12", "mi_r13_r12"},
- {{mi, r13, r13}, "mi, r13, r13", "mi_r13_r13"},
- {{mi, r13, r14}, "mi, r13, r14", "mi_r13_r14"},
- {{mi, r14, r0}, "mi, r14, r0", "mi_r14_r0"},
- {{mi, r14, r1}, "mi, r14, r1", "mi_r14_r1"},
- {{mi, r14, r2}, "mi, r14, r2", "mi_r14_r2"},
- {{mi, r14, r3}, "mi, r14, r3", "mi_r14_r3"},
- {{mi, r14, r4}, "mi, r14, r4", "mi_r14_r4"},
- {{mi, r14, r5}, "mi, r14, r5", "mi_r14_r5"},
- {{mi, r14, r6}, "mi, r14, r6", "mi_r14_r6"},
- {{mi, r14, r7}, "mi, r14, r7", "mi_r14_r7"},
- {{mi, r14, r8}, "mi, r14, r8", "mi_r14_r8"},
- {{mi, r14, r9}, "mi, r14, r9", "mi_r14_r9"},
- {{mi, r14, r10}, "mi, r14, r10", "mi_r14_r10"},
- {{mi, r14, r11}, "mi, r14, r11", "mi_r14_r11"},
- {{mi, r14, r12}, "mi, r14, r12", "mi_r14_r12"},
- {{mi, r14, r13}, "mi, r14, r13", "mi_r14_r13"},
- {{mi, r14, r14}, "mi, r14, r14", "mi_r14_r14"},
- {{pl, r0, r0}, "pl, r0, r0", "pl_r0_r0"},
- {{pl, r0, r1}, "pl, r0, r1", "pl_r0_r1"},
- {{pl, r0, r2}, "pl, r0, r2", "pl_r0_r2"},
- {{pl, r0, r3}, "pl, r0, r3", "pl_r0_r3"},
- {{pl, r0, r4}, "pl, r0, r4", "pl_r0_r4"},
- {{pl, r0, r5}, "pl, r0, r5", "pl_r0_r5"},
- {{pl, r0, r6}, "pl, r0, r6", "pl_r0_r6"},
- {{pl, r0, r7}, "pl, r0, r7", "pl_r0_r7"},
- {{pl, r0, r8}, "pl, r0, r8", "pl_r0_r8"},
- {{pl, r0, r9}, "pl, r0, r9", "pl_r0_r9"},
- {{pl, r0, r10}, "pl, r0, r10", "pl_r0_r10"},
- {{pl, r0, r11}, "pl, r0, r11", "pl_r0_r11"},
- {{pl, r0, r12}, "pl, r0, r12", "pl_r0_r12"},
- {{pl, r0, r13}, "pl, r0, r13", "pl_r0_r13"},
- {{pl, r0, r14}, "pl, r0, r14", "pl_r0_r14"},
- {{pl, r1, r0}, "pl, r1, r0", "pl_r1_r0"},
- {{pl, r1, r1}, "pl, r1, r1", "pl_r1_r1"},
- {{pl, r1, r2}, "pl, r1, r2", "pl_r1_r2"},
- {{pl, r1, r3}, "pl, r1, r3", "pl_r1_r3"},
- {{pl, r1, r4}, "pl, r1, r4", "pl_r1_r4"},
- {{pl, r1, r5}, "pl, r1, r5", "pl_r1_r5"},
- {{pl, r1, r6}, "pl, r1, r6", "pl_r1_r6"},
- {{pl, r1, r7}, "pl, r1, r7", "pl_r1_r7"},
- {{pl, r1, r8}, "pl, r1, r8", "pl_r1_r8"},
- {{pl, r1, r9}, "pl, r1, r9", "pl_r1_r9"},
- {{pl, r1, r10}, "pl, r1, r10", "pl_r1_r10"},
- {{pl, r1, r11}, "pl, r1, r11", "pl_r1_r11"},
- {{pl, r1, r12}, "pl, r1, r12", "pl_r1_r12"},
- {{pl, r1, r13}, "pl, r1, r13", "pl_r1_r13"},
- {{pl, r1, r14}, "pl, r1, r14", "pl_r1_r14"},
- {{pl, r2, r0}, "pl, r2, r0", "pl_r2_r0"},
- {{pl, r2, r1}, "pl, r2, r1", "pl_r2_r1"},
- {{pl, r2, r2}, "pl, r2, r2", "pl_r2_r2"},
- {{pl, r2, r3}, "pl, r2, r3", "pl_r2_r3"},
- {{pl, r2, r4}, "pl, r2, r4", "pl_r2_r4"},
- {{pl, r2, r5}, "pl, r2, r5", "pl_r2_r5"},
- {{pl, r2, r6}, "pl, r2, r6", "pl_r2_r6"},
- {{pl, r2, r7}, "pl, r2, r7", "pl_r2_r7"},
- {{pl, r2, r8}, "pl, r2, r8", "pl_r2_r8"},
- {{pl, r2, r9}, "pl, r2, r9", "pl_r2_r9"},
- {{pl, r2, r10}, "pl, r2, r10", "pl_r2_r10"},
- {{pl, r2, r11}, "pl, r2, r11", "pl_r2_r11"},
- {{pl, r2, r12}, "pl, r2, r12", "pl_r2_r12"},
- {{pl, r2, r13}, "pl, r2, r13", "pl_r2_r13"},
- {{pl, r2, r14}, "pl, r2, r14", "pl_r2_r14"},
- {{pl, r3, r0}, "pl, r3, r0", "pl_r3_r0"},
- {{pl, r3, r1}, "pl, r3, r1", "pl_r3_r1"},
- {{pl, r3, r2}, "pl, r3, r2", "pl_r3_r2"},
- {{pl, r3, r3}, "pl, r3, r3", "pl_r3_r3"},
- {{pl, r3, r4}, "pl, r3, r4", "pl_r3_r4"},
- {{pl, r3, r5}, "pl, r3, r5", "pl_r3_r5"},
- {{pl, r3, r6}, "pl, r3, r6", "pl_r3_r6"},
- {{pl, r3, r7}, "pl, r3, r7", "pl_r3_r7"},
- {{pl, r3, r8}, "pl, r3, r8", "pl_r3_r8"},
- {{pl, r3, r9}, "pl, r3, r9", "pl_r3_r9"},
- {{pl, r3, r10}, "pl, r3, r10", "pl_r3_r10"},
- {{pl, r3, r11}, "pl, r3, r11", "pl_r3_r11"},
- {{pl, r3, r12}, "pl, r3, r12", "pl_r3_r12"},
- {{pl, r3, r13}, "pl, r3, r13", "pl_r3_r13"},
- {{pl, r3, r14}, "pl, r3, r14", "pl_r3_r14"},
- {{pl, r4, r0}, "pl, r4, r0", "pl_r4_r0"},
- {{pl, r4, r1}, "pl, r4, r1", "pl_r4_r1"},
- {{pl, r4, r2}, "pl, r4, r2", "pl_r4_r2"},
- {{pl, r4, r3}, "pl, r4, r3", "pl_r4_r3"},
- {{pl, r4, r4}, "pl, r4, r4", "pl_r4_r4"},
- {{pl, r4, r5}, "pl, r4, r5", "pl_r4_r5"},
- {{pl, r4, r6}, "pl, r4, r6", "pl_r4_r6"},
- {{pl, r4, r7}, "pl, r4, r7", "pl_r4_r7"},
- {{pl, r4, r8}, "pl, r4, r8", "pl_r4_r8"},
- {{pl, r4, r9}, "pl, r4, r9", "pl_r4_r9"},
- {{pl, r4, r10}, "pl, r4, r10", "pl_r4_r10"},
- {{pl, r4, r11}, "pl, r4, r11", "pl_r4_r11"},
- {{pl, r4, r12}, "pl, r4, r12", "pl_r4_r12"},
- {{pl, r4, r13}, "pl, r4, r13", "pl_r4_r13"},
- {{pl, r4, r14}, "pl, r4, r14", "pl_r4_r14"},
- {{pl, r5, r0}, "pl, r5, r0", "pl_r5_r0"},
- {{pl, r5, r1}, "pl, r5, r1", "pl_r5_r1"},
- {{pl, r5, r2}, "pl, r5, r2", "pl_r5_r2"},
- {{pl, r5, r3}, "pl, r5, r3", "pl_r5_r3"},
- {{pl, r5, r4}, "pl, r5, r4", "pl_r5_r4"},
- {{pl, r5, r5}, "pl, r5, r5", "pl_r5_r5"},
- {{pl, r5, r6}, "pl, r5, r6", "pl_r5_r6"},
- {{pl, r5, r7}, "pl, r5, r7", "pl_r5_r7"},
- {{pl, r5, r8}, "pl, r5, r8", "pl_r5_r8"},
- {{pl, r5, r9}, "pl, r5, r9", "pl_r5_r9"},
- {{pl, r5, r10}, "pl, r5, r10", "pl_r5_r10"},
- {{pl, r5, r11}, "pl, r5, r11", "pl_r5_r11"},
- {{pl, r5, r12}, "pl, r5, r12", "pl_r5_r12"},
- {{pl, r5, r13}, "pl, r5, r13", "pl_r5_r13"},
- {{pl, r5, r14}, "pl, r5, r14", "pl_r5_r14"},
- {{pl, r6, r0}, "pl, r6, r0", "pl_r6_r0"},
- {{pl, r6, r1}, "pl, r6, r1", "pl_r6_r1"},
- {{pl, r6, r2}, "pl, r6, r2", "pl_r6_r2"},
- {{pl, r6, r3}, "pl, r6, r3", "pl_r6_r3"},
- {{pl, r6, r4}, "pl, r6, r4", "pl_r6_r4"},
- {{pl, r6, r5}, "pl, r6, r5", "pl_r6_r5"},
- {{pl, r6, r6}, "pl, r6, r6", "pl_r6_r6"},
- {{pl, r6, r7}, "pl, r6, r7", "pl_r6_r7"},
- {{pl, r6, r8}, "pl, r6, r8", "pl_r6_r8"},
- {{pl, r6, r9}, "pl, r6, r9", "pl_r6_r9"},
- {{pl, r6, r10}, "pl, r6, r10", "pl_r6_r10"},
- {{pl, r6, r11}, "pl, r6, r11", "pl_r6_r11"},
- {{pl, r6, r12}, "pl, r6, r12", "pl_r6_r12"},
- {{pl, r6, r13}, "pl, r6, r13", "pl_r6_r13"},
- {{pl, r6, r14}, "pl, r6, r14", "pl_r6_r14"},
- {{pl, r7, r0}, "pl, r7, r0", "pl_r7_r0"},
- {{pl, r7, r1}, "pl, r7, r1", "pl_r7_r1"},
- {{pl, r7, r2}, "pl, r7, r2", "pl_r7_r2"},
- {{pl, r7, r3}, "pl, r7, r3", "pl_r7_r3"},
- {{pl, r7, r4}, "pl, r7, r4", "pl_r7_r4"},
- {{pl, r7, r5}, "pl, r7, r5", "pl_r7_r5"},
- {{pl, r7, r6}, "pl, r7, r6", "pl_r7_r6"},
- {{pl, r7, r7}, "pl, r7, r7", "pl_r7_r7"},
- {{pl, r7, r8}, "pl, r7, r8", "pl_r7_r8"},
- {{pl, r7, r9}, "pl, r7, r9", "pl_r7_r9"},
- {{pl, r7, r10}, "pl, r7, r10", "pl_r7_r10"},
- {{pl, r7, r11}, "pl, r7, r11", "pl_r7_r11"},
- {{pl, r7, r12}, "pl, r7, r12", "pl_r7_r12"},
- {{pl, r7, r13}, "pl, r7, r13", "pl_r7_r13"},
- {{pl, r7, r14}, "pl, r7, r14", "pl_r7_r14"},
- {{pl, r8, r0}, "pl, r8, r0", "pl_r8_r0"},
- {{pl, r8, r1}, "pl, r8, r1", "pl_r8_r1"},
- {{pl, r8, r2}, "pl, r8, r2", "pl_r8_r2"},
- {{pl, r8, r3}, "pl, r8, r3", "pl_r8_r3"},
- {{pl, r8, r4}, "pl, r8, r4", "pl_r8_r4"},
- {{pl, r8, r5}, "pl, r8, r5", "pl_r8_r5"},
- {{pl, r8, r6}, "pl, r8, r6", "pl_r8_r6"},
- {{pl, r8, r7}, "pl, r8, r7", "pl_r8_r7"},
- {{pl, r8, r8}, "pl, r8, r8", "pl_r8_r8"},
- {{pl, r8, r9}, "pl, r8, r9", "pl_r8_r9"},
- {{pl, r8, r10}, "pl, r8, r10", "pl_r8_r10"},
- {{pl, r8, r11}, "pl, r8, r11", "pl_r8_r11"},
- {{pl, r8, r12}, "pl, r8, r12", "pl_r8_r12"},
- {{pl, r8, r13}, "pl, r8, r13", "pl_r8_r13"},
- {{pl, r8, r14}, "pl, r8, r14", "pl_r8_r14"},
- {{pl, r9, r0}, "pl, r9, r0", "pl_r9_r0"},
- {{pl, r9, r1}, "pl, r9, r1", "pl_r9_r1"},
- {{pl, r9, r2}, "pl, r9, r2", "pl_r9_r2"},
- {{pl, r9, r3}, "pl, r9, r3", "pl_r9_r3"},
- {{pl, r9, r4}, "pl, r9, r4", "pl_r9_r4"},
- {{pl, r9, r5}, "pl, r9, r5", "pl_r9_r5"},
- {{pl, r9, r6}, "pl, r9, r6", "pl_r9_r6"},
- {{pl, r9, r7}, "pl, r9, r7", "pl_r9_r7"},
- {{pl, r9, r8}, "pl, r9, r8", "pl_r9_r8"},
- {{pl, r9, r9}, "pl, r9, r9", "pl_r9_r9"},
- {{pl, r9, r10}, "pl, r9, r10", "pl_r9_r10"},
- {{pl, r9, r11}, "pl, r9, r11", "pl_r9_r11"},
- {{pl, r9, r12}, "pl, r9, r12", "pl_r9_r12"},
- {{pl, r9, r13}, "pl, r9, r13", "pl_r9_r13"},
- {{pl, r9, r14}, "pl, r9, r14", "pl_r9_r14"},
- {{pl, r10, r0}, "pl, r10, r0", "pl_r10_r0"},
- {{pl, r10, r1}, "pl, r10, r1", "pl_r10_r1"},
- {{pl, r10, r2}, "pl, r10, r2", "pl_r10_r2"},
- {{pl, r10, r3}, "pl, r10, r3", "pl_r10_r3"},
- {{pl, r10, r4}, "pl, r10, r4", "pl_r10_r4"},
- {{pl, r10, r5}, "pl, r10, r5", "pl_r10_r5"},
- {{pl, r10, r6}, "pl, r10, r6", "pl_r10_r6"},
- {{pl, r10, r7}, "pl, r10, r7", "pl_r10_r7"},
- {{pl, r10, r8}, "pl, r10, r8", "pl_r10_r8"},
- {{pl, r10, r9}, "pl, r10, r9", "pl_r10_r9"},
- {{pl, r10, r10}, "pl, r10, r10", "pl_r10_r10"},
- {{pl, r10, r11}, "pl, r10, r11", "pl_r10_r11"},
- {{pl, r10, r12}, "pl, r10, r12", "pl_r10_r12"},
- {{pl, r10, r13}, "pl, r10, r13", "pl_r10_r13"},
- {{pl, r10, r14}, "pl, r10, r14", "pl_r10_r14"},
- {{pl, r11, r0}, "pl, r11, r0", "pl_r11_r0"},
- {{pl, r11, r1}, "pl, r11, r1", "pl_r11_r1"},
- {{pl, r11, r2}, "pl, r11, r2", "pl_r11_r2"},
- {{pl, r11, r3}, "pl, r11, r3", "pl_r11_r3"},
- {{pl, r11, r4}, "pl, r11, r4", "pl_r11_r4"},
- {{pl, r11, r5}, "pl, r11, r5", "pl_r11_r5"},
- {{pl, r11, r6}, "pl, r11, r6", "pl_r11_r6"},
- {{pl, r11, r7}, "pl, r11, r7", "pl_r11_r7"},
- {{pl, r11, r8}, "pl, r11, r8", "pl_r11_r8"},
- {{pl, r11, r9}, "pl, r11, r9", "pl_r11_r9"},
- {{pl, r11, r10}, "pl, r11, r10", "pl_r11_r10"},
- {{pl, r11, r11}, "pl, r11, r11", "pl_r11_r11"},
- {{pl, r11, r12}, "pl, r11, r12", "pl_r11_r12"},
- {{pl, r11, r13}, "pl, r11, r13", "pl_r11_r13"},
- {{pl, r11, r14}, "pl, r11, r14", "pl_r11_r14"},
- {{pl, r12, r0}, "pl, r12, r0", "pl_r12_r0"},
- {{pl, r12, r1}, "pl, r12, r1", "pl_r12_r1"},
- {{pl, r12, r2}, "pl, r12, r2", "pl_r12_r2"},
- {{pl, r12, r3}, "pl, r12, r3", "pl_r12_r3"},
- {{pl, r12, r4}, "pl, r12, r4", "pl_r12_r4"},
- {{pl, r12, r5}, "pl, r12, r5", "pl_r12_r5"},
- {{pl, r12, r6}, "pl, r12, r6", "pl_r12_r6"},
- {{pl, r12, r7}, "pl, r12, r7", "pl_r12_r7"},
- {{pl, r12, r8}, "pl, r12, r8", "pl_r12_r8"},
- {{pl, r12, r9}, "pl, r12, r9", "pl_r12_r9"},
- {{pl, r12, r10}, "pl, r12, r10", "pl_r12_r10"},
- {{pl, r12, r11}, "pl, r12, r11", "pl_r12_r11"},
- {{pl, r12, r12}, "pl, r12, r12", "pl_r12_r12"},
- {{pl, r12, r13}, "pl, r12, r13", "pl_r12_r13"},
- {{pl, r12, r14}, "pl, r12, r14", "pl_r12_r14"},
- {{pl, r13, r0}, "pl, r13, r0", "pl_r13_r0"},
- {{pl, r13, r1}, "pl, r13, r1", "pl_r13_r1"},
- {{pl, r13, r2}, "pl, r13, r2", "pl_r13_r2"},
- {{pl, r13, r3}, "pl, r13, r3", "pl_r13_r3"},
- {{pl, r13, r4}, "pl, r13, r4", "pl_r13_r4"},
- {{pl, r13, r5}, "pl, r13, r5", "pl_r13_r5"},
- {{pl, r13, r6}, "pl, r13, r6", "pl_r13_r6"},
- {{pl, r13, r7}, "pl, r13, r7", "pl_r13_r7"},
- {{pl, r13, r8}, "pl, r13, r8", "pl_r13_r8"},
- {{pl, r13, r9}, "pl, r13, r9", "pl_r13_r9"},
- {{pl, r13, r10}, "pl, r13, r10", "pl_r13_r10"},
- {{pl, r13, r11}, "pl, r13, r11", "pl_r13_r11"},
- {{pl, r13, r12}, "pl, r13, r12", "pl_r13_r12"},
- {{pl, r13, r13}, "pl, r13, r13", "pl_r13_r13"},
- {{pl, r13, r14}, "pl, r13, r14", "pl_r13_r14"},
- {{pl, r14, r0}, "pl, r14, r0", "pl_r14_r0"},
- {{pl, r14, r1}, "pl, r14, r1", "pl_r14_r1"},
- {{pl, r14, r2}, "pl, r14, r2", "pl_r14_r2"},
- {{pl, r14, r3}, "pl, r14, r3", "pl_r14_r3"},
- {{pl, r14, r4}, "pl, r14, r4", "pl_r14_r4"},
- {{pl, r14, r5}, "pl, r14, r5", "pl_r14_r5"},
- {{pl, r14, r6}, "pl, r14, r6", "pl_r14_r6"},
- {{pl, r14, r7}, "pl, r14, r7", "pl_r14_r7"},
- {{pl, r14, r8}, "pl, r14, r8", "pl_r14_r8"},
- {{pl, r14, r9}, "pl, r14, r9", "pl_r14_r9"},
- {{pl, r14, r10}, "pl, r14, r10", "pl_r14_r10"},
- {{pl, r14, r11}, "pl, r14, r11", "pl_r14_r11"},
- {{pl, r14, r12}, "pl, r14, r12", "pl_r14_r12"},
- {{pl, r14, r13}, "pl, r14, r13", "pl_r14_r13"},
- {{pl, r14, r14}, "pl, r14, r14", "pl_r14_r14"},
- {{vs, r0, r0}, "vs, r0, r0", "vs_r0_r0"},
- {{vs, r0, r1}, "vs, r0, r1", "vs_r0_r1"},
- {{vs, r0, r2}, "vs, r0, r2", "vs_r0_r2"},
- {{vs, r0, r3}, "vs, r0, r3", "vs_r0_r3"},
- {{vs, r0, r4}, "vs, r0, r4", "vs_r0_r4"},
- {{vs, r0, r5}, "vs, r0, r5", "vs_r0_r5"},
- {{vs, r0, r6}, "vs, r0, r6", "vs_r0_r6"},
- {{vs, r0, r7}, "vs, r0, r7", "vs_r0_r7"},
- {{vs, r0, r8}, "vs, r0, r8", "vs_r0_r8"},
- {{vs, r0, r9}, "vs, r0, r9", "vs_r0_r9"},
- {{vs, r0, r10}, "vs, r0, r10", "vs_r0_r10"},
- {{vs, r0, r11}, "vs, r0, r11", "vs_r0_r11"},
- {{vs, r0, r12}, "vs, r0, r12", "vs_r0_r12"},
- {{vs, r0, r13}, "vs, r0, r13", "vs_r0_r13"},
- {{vs, r0, r14}, "vs, r0, r14", "vs_r0_r14"},
- {{vs, r1, r0}, "vs, r1, r0", "vs_r1_r0"},
- {{vs, r1, r1}, "vs, r1, r1", "vs_r1_r1"},
- {{vs, r1, r2}, "vs, r1, r2", "vs_r1_r2"},
- {{vs, r1, r3}, "vs, r1, r3", "vs_r1_r3"},
- {{vs, r1, r4}, "vs, r1, r4", "vs_r1_r4"},
- {{vs, r1, r5}, "vs, r1, r5", "vs_r1_r5"},
- {{vs, r1, r6}, "vs, r1, r6", "vs_r1_r6"},
- {{vs, r1, r7}, "vs, r1, r7", "vs_r1_r7"},
- {{vs, r1, r8}, "vs, r1, r8", "vs_r1_r8"},
- {{vs, r1, r9}, "vs, r1, r9", "vs_r1_r9"},
- {{vs, r1, r10}, "vs, r1, r10", "vs_r1_r10"},
- {{vs, r1, r11}, "vs, r1, r11", "vs_r1_r11"},
- {{vs, r1, r12}, "vs, r1, r12", "vs_r1_r12"},
- {{vs, r1, r13}, "vs, r1, r13", "vs_r1_r13"},
- {{vs, r1, r14}, "vs, r1, r14", "vs_r1_r14"},
- {{vs, r2, r0}, "vs, r2, r0", "vs_r2_r0"},
- {{vs, r2, r1}, "vs, r2, r1", "vs_r2_r1"},
- {{vs, r2, r2}, "vs, r2, r2", "vs_r2_r2"},
- {{vs, r2, r3}, "vs, r2, r3", "vs_r2_r3"},
- {{vs, r2, r4}, "vs, r2, r4", "vs_r2_r4"},
- {{vs, r2, r5}, "vs, r2, r5", "vs_r2_r5"},
- {{vs, r2, r6}, "vs, r2, r6", "vs_r2_r6"},
- {{vs, r2, r7}, "vs, r2, r7", "vs_r2_r7"},
- {{vs, r2, r8}, "vs, r2, r8", "vs_r2_r8"},
- {{vs, r2, r9}, "vs, r2, r9", "vs_r2_r9"},
- {{vs, r2, r10}, "vs, r2, r10", "vs_r2_r10"},
- {{vs, r2, r11}, "vs, r2, r11", "vs_r2_r11"},
- {{vs, r2, r12}, "vs, r2, r12", "vs_r2_r12"},
- {{vs, r2, r13}, "vs, r2, r13", "vs_r2_r13"},
- {{vs, r2, r14}, "vs, r2, r14", "vs_r2_r14"},
- {{vs, r3, r0}, "vs, r3, r0", "vs_r3_r0"},
- {{vs, r3, r1}, "vs, r3, r1", "vs_r3_r1"},
- {{vs, r3, r2}, "vs, r3, r2", "vs_r3_r2"},
- {{vs, r3, r3}, "vs, r3, r3", "vs_r3_r3"},
- {{vs, r3, r4}, "vs, r3, r4", "vs_r3_r4"},
- {{vs, r3, r5}, "vs, r3, r5", "vs_r3_r5"},
- {{vs, r3, r6}, "vs, r3, r6", "vs_r3_r6"},
- {{vs, r3, r7}, "vs, r3, r7", "vs_r3_r7"},
- {{vs, r3, r8}, "vs, r3, r8", "vs_r3_r8"},
- {{vs, r3, r9}, "vs, r3, r9", "vs_r3_r9"},
- {{vs, r3, r10}, "vs, r3, r10", "vs_r3_r10"},
- {{vs, r3, r11}, "vs, r3, r11", "vs_r3_r11"},
- {{vs, r3, r12}, "vs, r3, r12", "vs_r3_r12"},
- {{vs, r3, r13}, "vs, r3, r13", "vs_r3_r13"},
- {{vs, r3, r14}, "vs, r3, r14", "vs_r3_r14"},
- {{vs, r4, r0}, "vs, r4, r0", "vs_r4_r0"},
- {{vs, r4, r1}, "vs, r4, r1", "vs_r4_r1"},
- {{vs, r4, r2}, "vs, r4, r2", "vs_r4_r2"},
- {{vs, r4, r3}, "vs, r4, r3", "vs_r4_r3"},
- {{vs, r4, r4}, "vs, r4, r4", "vs_r4_r4"},
- {{vs, r4, r5}, "vs, r4, r5", "vs_r4_r5"},
- {{vs, r4, r6}, "vs, r4, r6", "vs_r4_r6"},
- {{vs, r4, r7}, "vs, r4, r7", "vs_r4_r7"},
- {{vs, r4, r8}, "vs, r4, r8", "vs_r4_r8"},
- {{vs, r4, r9}, "vs, r4, r9", "vs_r4_r9"},
- {{vs, r4, r10}, "vs, r4, r10", "vs_r4_r10"},
- {{vs, r4, r11}, "vs, r4, r11", "vs_r4_r11"},
- {{vs, r4, r12}, "vs, r4, r12", "vs_r4_r12"},
- {{vs, r4, r13}, "vs, r4, r13", "vs_r4_r13"},
- {{vs, r4, r14}, "vs, r4, r14", "vs_r4_r14"},
- {{vs, r5, r0}, "vs, r5, r0", "vs_r5_r0"},
- {{vs, r5, r1}, "vs, r5, r1", "vs_r5_r1"},
- {{vs, r5, r2}, "vs, r5, r2", "vs_r5_r2"},
- {{vs, r5, r3}, "vs, r5, r3", "vs_r5_r3"},
- {{vs, r5, r4}, "vs, r5, r4", "vs_r5_r4"},
- {{vs, r5, r5}, "vs, r5, r5", "vs_r5_r5"},
- {{vs, r5, r6}, "vs, r5, r6", "vs_r5_r6"},
- {{vs, r5, r7}, "vs, r5, r7", "vs_r5_r7"},
- {{vs, r5, r8}, "vs, r5, r8", "vs_r5_r8"},
- {{vs, r5, r9}, "vs, r5, r9", "vs_r5_r9"},
- {{vs, r5, r10}, "vs, r5, r10", "vs_r5_r10"},
- {{vs, r5, r11}, "vs, r5, r11", "vs_r5_r11"},
- {{vs, r5, r12}, "vs, r5, r12", "vs_r5_r12"},
- {{vs, r5, r13}, "vs, r5, r13", "vs_r5_r13"},
- {{vs, r5, r14}, "vs, r5, r14", "vs_r5_r14"},
- {{vs, r6, r0}, "vs, r6, r0", "vs_r6_r0"},
- {{vs, r6, r1}, "vs, r6, r1", "vs_r6_r1"},
- {{vs, r6, r2}, "vs, r6, r2", "vs_r6_r2"},
- {{vs, r6, r3}, "vs, r6, r3", "vs_r6_r3"},
- {{vs, r6, r4}, "vs, r6, r4", "vs_r6_r4"},
- {{vs, r6, r5}, "vs, r6, r5", "vs_r6_r5"},
- {{vs, r6, r6}, "vs, r6, r6", "vs_r6_r6"},
- {{vs, r6, r7}, "vs, r6, r7", "vs_r6_r7"},
- {{vs, r6, r8}, "vs, r6, r8", "vs_r6_r8"},
- {{vs, r6, r9}, "vs, r6, r9", "vs_r6_r9"},
- {{vs, r6, r10}, "vs, r6, r10", "vs_r6_r10"},
- {{vs, r6, r11}, "vs, r6, r11", "vs_r6_r11"},
- {{vs, r6, r12}, "vs, r6, r12", "vs_r6_r12"},
- {{vs, r6, r13}, "vs, r6, r13", "vs_r6_r13"},
- {{vs, r6, r14}, "vs, r6, r14", "vs_r6_r14"},
- {{vs, r7, r0}, "vs, r7, r0", "vs_r7_r0"},
- {{vs, r7, r1}, "vs, r7, r1", "vs_r7_r1"},
- {{vs, r7, r2}, "vs, r7, r2", "vs_r7_r2"},
- {{vs, r7, r3}, "vs, r7, r3", "vs_r7_r3"},
- {{vs, r7, r4}, "vs, r7, r4", "vs_r7_r4"},
- {{vs, r7, r5}, "vs, r7, r5", "vs_r7_r5"},
- {{vs, r7, r6}, "vs, r7, r6", "vs_r7_r6"},
- {{vs, r7, r7}, "vs, r7, r7", "vs_r7_r7"},
- {{vs, r7, r8}, "vs, r7, r8", "vs_r7_r8"},
- {{vs, r7, r9}, "vs, r7, r9", "vs_r7_r9"},
- {{vs, r7, r10}, "vs, r7, r10", "vs_r7_r10"},
- {{vs, r7, r11}, "vs, r7, r11", "vs_r7_r11"},
- {{vs, r7, r12}, "vs, r7, r12", "vs_r7_r12"},
- {{vs, r7, r13}, "vs, r7, r13", "vs_r7_r13"},
- {{vs, r7, r14}, "vs, r7, r14", "vs_r7_r14"},
- {{vs, r8, r0}, "vs, r8, r0", "vs_r8_r0"},
- {{vs, r8, r1}, "vs, r8, r1", "vs_r8_r1"},
- {{vs, r8, r2}, "vs, r8, r2", "vs_r8_r2"},
- {{vs, r8, r3}, "vs, r8, r3", "vs_r8_r3"},
- {{vs, r8, r4}, "vs, r8, r4", "vs_r8_r4"},
- {{vs, r8, r5}, "vs, r8, r5", "vs_r8_r5"},
- {{vs, r8, r6}, "vs, r8, r6", "vs_r8_r6"},
- {{vs, r8, r7}, "vs, r8, r7", "vs_r8_r7"},
- {{vs, r8, r8}, "vs, r8, r8", "vs_r8_r8"},
- {{vs, r8, r9}, "vs, r8, r9", "vs_r8_r9"},
- {{vs, r8, r10}, "vs, r8, r10", "vs_r8_r10"},
- {{vs, r8, r11}, "vs, r8, r11", "vs_r8_r11"},
- {{vs, r8, r12}, "vs, r8, r12", "vs_r8_r12"},
- {{vs, r8, r13}, "vs, r8, r13", "vs_r8_r13"},
- {{vs, r8, r14}, "vs, r8, r14", "vs_r8_r14"},
- {{vs, r9, r0}, "vs, r9, r0", "vs_r9_r0"},
- {{vs, r9, r1}, "vs, r9, r1", "vs_r9_r1"},
- {{vs, r9, r2}, "vs, r9, r2", "vs_r9_r2"},
- {{vs, r9, r3}, "vs, r9, r3", "vs_r9_r3"},
- {{vs, r9, r4}, "vs, r9, r4", "vs_r9_r4"},
- {{vs, r9, r5}, "vs, r9, r5", "vs_r9_r5"},
- {{vs, r9, r6}, "vs, r9, r6", "vs_r9_r6"},
- {{vs, r9, r7}, "vs, r9, r7", "vs_r9_r7"},
- {{vs, r9, r8}, "vs, r9, r8", "vs_r9_r8"},
- {{vs, r9, r9}, "vs, r9, r9", "vs_r9_r9"},
- {{vs, r9, r10}, "vs, r9, r10", "vs_r9_r10"},
- {{vs, r9, r11}, "vs, r9, r11", "vs_r9_r11"},
- {{vs, r9, r12}, "vs, r9, r12", "vs_r9_r12"},
- {{vs, r9, r13}, "vs, r9, r13", "vs_r9_r13"},
- {{vs, r9, r14}, "vs, r9, r14", "vs_r9_r14"},
- {{vs, r10, r0}, "vs, r10, r0", "vs_r10_r0"},
- {{vs, r10, r1}, "vs, r10, r1", "vs_r10_r1"},
- {{vs, r10, r2}, "vs, r10, r2", "vs_r10_r2"},
- {{vs, r10, r3}, "vs, r10, r3", "vs_r10_r3"},
- {{vs, r10, r4}, "vs, r10, r4", "vs_r10_r4"},
- {{vs, r10, r5}, "vs, r10, r5", "vs_r10_r5"},
- {{vs, r10, r6}, "vs, r10, r6", "vs_r10_r6"},
- {{vs, r10, r7}, "vs, r10, r7", "vs_r10_r7"},
- {{vs, r10, r8}, "vs, r10, r8", "vs_r10_r8"},
- {{vs, r10, r9}, "vs, r10, r9", "vs_r10_r9"},
- {{vs, r10, r10}, "vs, r10, r10", "vs_r10_r10"},
- {{vs, r10, r11}, "vs, r10, r11", "vs_r10_r11"},
- {{vs, r10, r12}, "vs, r10, r12", "vs_r10_r12"},
- {{vs, r10, r13}, "vs, r10, r13", "vs_r10_r13"},
- {{vs, r10, r14}, "vs, r10, r14", "vs_r10_r14"},
- {{vs, r11, r0}, "vs, r11, r0", "vs_r11_r0"},
- {{vs, r11, r1}, "vs, r11, r1", "vs_r11_r1"},
- {{vs, r11, r2}, "vs, r11, r2", "vs_r11_r2"},
- {{vs, r11, r3}, "vs, r11, r3", "vs_r11_r3"},
- {{vs, r11, r4}, "vs, r11, r4", "vs_r11_r4"},
- {{vs, r11, r5}, "vs, r11, r5", "vs_r11_r5"},
- {{vs, r11, r6}, "vs, r11, r6", "vs_r11_r6"},
- {{vs, r11, r7}, "vs, r11, r7", "vs_r11_r7"},
- {{vs, r11, r8}, "vs, r11, r8", "vs_r11_r8"},
- {{vs, r11, r9}, "vs, r11, r9", "vs_r11_r9"},
- {{vs, r11, r10}, "vs, r11, r10", "vs_r11_r10"},
- {{vs, r11, r11}, "vs, r11, r11", "vs_r11_r11"},
- {{vs, r11, r12}, "vs, r11, r12", "vs_r11_r12"},
- {{vs, r11, r13}, "vs, r11, r13", "vs_r11_r13"},
- {{vs, r11, r14}, "vs, r11, r14", "vs_r11_r14"},
- {{vs, r12, r0}, "vs, r12, r0", "vs_r12_r0"},
- {{vs, r12, r1}, "vs, r12, r1", "vs_r12_r1"},
- {{vs, r12, r2}, "vs, r12, r2", "vs_r12_r2"},
- {{vs, r12, r3}, "vs, r12, r3", "vs_r12_r3"},
- {{vs, r12, r4}, "vs, r12, r4", "vs_r12_r4"},
- {{vs, r12, r5}, "vs, r12, r5", "vs_r12_r5"},
- {{vs, r12, r6}, "vs, r12, r6", "vs_r12_r6"},
- {{vs, r12, r7}, "vs, r12, r7", "vs_r12_r7"},
- {{vs, r12, r8}, "vs, r12, r8", "vs_r12_r8"},
- {{vs, r12, r9}, "vs, r12, r9", "vs_r12_r9"},
- {{vs, r12, r10}, "vs, r12, r10", "vs_r12_r10"},
- {{vs, r12, r11}, "vs, r12, r11", "vs_r12_r11"},
- {{vs, r12, r12}, "vs, r12, r12", "vs_r12_r12"},
- {{vs, r12, r13}, "vs, r12, r13", "vs_r12_r13"},
- {{vs, r12, r14}, "vs, r12, r14", "vs_r12_r14"},
- {{vs, r13, r0}, "vs, r13, r0", "vs_r13_r0"},
- {{vs, r13, r1}, "vs, r13, r1", "vs_r13_r1"},
- {{vs, r13, r2}, "vs, r13, r2", "vs_r13_r2"},
- {{vs, r13, r3}, "vs, r13, r3", "vs_r13_r3"},
- {{vs, r13, r4}, "vs, r13, r4", "vs_r13_r4"},
- {{vs, r13, r5}, "vs, r13, r5", "vs_r13_r5"},
- {{vs, r13, r6}, "vs, r13, r6", "vs_r13_r6"},
- {{vs, r13, r7}, "vs, r13, r7", "vs_r13_r7"},
- {{vs, r13, r8}, "vs, r13, r8", "vs_r13_r8"},
- {{vs, r13, r9}, "vs, r13, r9", "vs_r13_r9"},
- {{vs, r13, r10}, "vs, r13, r10", "vs_r13_r10"},
- {{vs, r13, r11}, "vs, r13, r11", "vs_r13_r11"},
- {{vs, r13, r12}, "vs, r13, r12", "vs_r13_r12"},
- {{vs, r13, r13}, "vs, r13, r13", "vs_r13_r13"},
- {{vs, r13, r14}, "vs, r13, r14", "vs_r13_r14"},
- {{vs, r14, r0}, "vs, r14, r0", "vs_r14_r0"},
- {{vs, r14, r1}, "vs, r14, r1", "vs_r14_r1"},
- {{vs, r14, r2}, "vs, r14, r2", "vs_r14_r2"},
- {{vs, r14, r3}, "vs, r14, r3", "vs_r14_r3"},
- {{vs, r14, r4}, "vs, r14, r4", "vs_r14_r4"},
- {{vs, r14, r5}, "vs, r14, r5", "vs_r14_r5"},
- {{vs, r14, r6}, "vs, r14, r6", "vs_r14_r6"},
- {{vs, r14, r7}, "vs, r14, r7", "vs_r14_r7"},
- {{vs, r14, r8}, "vs, r14, r8", "vs_r14_r8"},
- {{vs, r14, r9}, "vs, r14, r9", "vs_r14_r9"},
- {{vs, r14, r10}, "vs, r14, r10", "vs_r14_r10"},
- {{vs, r14, r11}, "vs, r14, r11", "vs_r14_r11"},
- {{vs, r14, r12}, "vs, r14, r12", "vs_r14_r12"},
- {{vs, r14, r13}, "vs, r14, r13", "vs_r14_r13"},
- {{vs, r14, r14}, "vs, r14, r14", "vs_r14_r14"},
- {{vc, r0, r0}, "vc, r0, r0", "vc_r0_r0"},
- {{vc, r0, r1}, "vc, r0, r1", "vc_r0_r1"},
- {{vc, r0, r2}, "vc, r0, r2", "vc_r0_r2"},
- {{vc, r0, r3}, "vc, r0, r3", "vc_r0_r3"},
- {{vc, r0, r4}, "vc, r0, r4", "vc_r0_r4"},
- {{vc, r0, r5}, "vc, r0, r5", "vc_r0_r5"},
- {{vc, r0, r6}, "vc, r0, r6", "vc_r0_r6"},
- {{vc, r0, r7}, "vc, r0, r7", "vc_r0_r7"},
- {{vc, r0, r8}, "vc, r0, r8", "vc_r0_r8"},
- {{vc, r0, r9}, "vc, r0, r9", "vc_r0_r9"},
- {{vc, r0, r10}, "vc, r0, r10", "vc_r0_r10"},
- {{vc, r0, r11}, "vc, r0, r11", "vc_r0_r11"},
- {{vc, r0, r12}, "vc, r0, r12", "vc_r0_r12"},
- {{vc, r0, r13}, "vc, r0, r13", "vc_r0_r13"},
- {{vc, r0, r14}, "vc, r0, r14", "vc_r0_r14"},
- {{vc, r1, r0}, "vc, r1, r0", "vc_r1_r0"},
- {{vc, r1, r1}, "vc, r1, r1", "vc_r1_r1"},
- {{vc, r1, r2}, "vc, r1, r2", "vc_r1_r2"},
- {{vc, r1, r3}, "vc, r1, r3", "vc_r1_r3"},
- {{vc, r1, r4}, "vc, r1, r4", "vc_r1_r4"},
- {{vc, r1, r5}, "vc, r1, r5", "vc_r1_r5"},
- {{vc, r1, r6}, "vc, r1, r6", "vc_r1_r6"},
- {{vc, r1, r7}, "vc, r1, r7", "vc_r1_r7"},
- {{vc, r1, r8}, "vc, r1, r8", "vc_r1_r8"},
- {{vc, r1, r9}, "vc, r1, r9", "vc_r1_r9"},
- {{vc, r1, r10}, "vc, r1, r10", "vc_r1_r10"},
- {{vc, r1, r11}, "vc, r1, r11", "vc_r1_r11"},
- {{vc, r1, r12}, "vc, r1, r12", "vc_r1_r12"},
- {{vc, r1, r13}, "vc, r1, r13", "vc_r1_r13"},
- {{vc, r1, r14}, "vc, r1, r14", "vc_r1_r14"},
- {{vc, r2, r0}, "vc, r2, r0", "vc_r2_r0"},
- {{vc, r2, r1}, "vc, r2, r1", "vc_r2_r1"},
- {{vc, r2, r2}, "vc, r2, r2", "vc_r2_r2"},
- {{vc, r2, r3}, "vc, r2, r3", "vc_r2_r3"},
- {{vc, r2, r4}, "vc, r2, r4", "vc_r2_r4"},
- {{vc, r2, r5}, "vc, r2, r5", "vc_r2_r5"},
- {{vc, r2, r6}, "vc, r2, r6", "vc_r2_r6"},
- {{vc, r2, r7}, "vc, r2, r7", "vc_r2_r7"},
- {{vc, r2, r8}, "vc, r2, r8", "vc_r2_r8"},
- {{vc, r2, r9}, "vc, r2, r9", "vc_r2_r9"},
- {{vc, r2, r10}, "vc, r2, r10", "vc_r2_r10"},
- {{vc, r2, r11}, "vc, r2, r11", "vc_r2_r11"},
- {{vc, r2, r12}, "vc, r2, r12", "vc_r2_r12"},
- {{vc, r2, r13}, "vc, r2, r13", "vc_r2_r13"},
- {{vc, r2, r14}, "vc, r2, r14", "vc_r2_r14"},
- {{vc, r3, r0}, "vc, r3, r0", "vc_r3_r0"},
- {{vc, r3, r1}, "vc, r3, r1", "vc_r3_r1"},
- {{vc, r3, r2}, "vc, r3, r2", "vc_r3_r2"},
- {{vc, r3, r3}, "vc, r3, r3", "vc_r3_r3"},
- {{vc, r3, r4}, "vc, r3, r4", "vc_r3_r4"},
- {{vc, r3, r5}, "vc, r3, r5", "vc_r3_r5"},
- {{vc, r3, r6}, "vc, r3, r6", "vc_r3_r6"},
- {{vc, r3, r7}, "vc, r3, r7", "vc_r3_r7"},
- {{vc, r3, r8}, "vc, r3, r8", "vc_r3_r8"},
- {{vc, r3, r9}, "vc, r3, r9", "vc_r3_r9"},
- {{vc, r3, r10}, "vc, r3, r10", "vc_r3_r10"},
- {{vc, r3, r11}, "vc, r3, r11", "vc_r3_r11"},
- {{vc, r3, r12}, "vc, r3, r12", "vc_r3_r12"},
- {{vc, r3, r13}, "vc, r3, r13", "vc_r3_r13"},
- {{vc, r3, r14}, "vc, r3, r14", "vc_r3_r14"},
- {{vc, r4, r0}, "vc, r4, r0", "vc_r4_r0"},
- {{vc, r4, r1}, "vc, r4, r1", "vc_r4_r1"},
- {{vc, r4, r2}, "vc, r4, r2", "vc_r4_r2"},
- {{vc, r4, r3}, "vc, r4, r3", "vc_r4_r3"},
- {{vc, r4, r4}, "vc, r4, r4", "vc_r4_r4"},
- {{vc, r4, r5}, "vc, r4, r5", "vc_r4_r5"},
- {{vc, r4, r6}, "vc, r4, r6", "vc_r4_r6"},
- {{vc, r4, r7}, "vc, r4, r7", "vc_r4_r7"},
- {{vc, r4, r8}, "vc, r4, r8", "vc_r4_r8"},
- {{vc, r4, r9}, "vc, r4, r9", "vc_r4_r9"},
- {{vc, r4, r10}, "vc, r4, r10", "vc_r4_r10"},
- {{vc, r4, r11}, "vc, r4, r11", "vc_r4_r11"},
- {{vc, r4, r12}, "vc, r4, r12", "vc_r4_r12"},
- {{vc, r4, r13}, "vc, r4, r13", "vc_r4_r13"},
- {{vc, r4, r14}, "vc, r4, r14", "vc_r4_r14"},
- {{vc, r5, r0}, "vc, r5, r0", "vc_r5_r0"},
- {{vc, r5, r1}, "vc, r5, r1", "vc_r5_r1"},
- {{vc, r5, r2}, "vc, r5, r2", "vc_r5_r2"},
- {{vc, r5, r3}, "vc, r5, r3", "vc_r5_r3"},
- {{vc, r5, r4}, "vc, r5, r4", "vc_r5_r4"},
- {{vc, r5, r5}, "vc, r5, r5", "vc_r5_r5"},
- {{vc, r5, r6}, "vc, r5, r6", "vc_r5_r6"},
- {{vc, r5, r7}, "vc, r5, r7", "vc_r5_r7"},
- {{vc, r5, r8}, "vc, r5, r8", "vc_r5_r8"},
- {{vc, r5, r9}, "vc, r5, r9", "vc_r5_r9"},
- {{vc, r5, r10}, "vc, r5, r10", "vc_r5_r10"},
- {{vc, r5, r11}, "vc, r5, r11", "vc_r5_r11"},
- {{vc, r5, r12}, "vc, r5, r12", "vc_r5_r12"},
- {{vc, r5, r13}, "vc, r5, r13", "vc_r5_r13"},
- {{vc, r5, r14}, "vc, r5, r14", "vc_r5_r14"},
- {{vc, r6, r0}, "vc, r6, r0", "vc_r6_r0"},
- {{vc, r6, r1}, "vc, r6, r1", "vc_r6_r1"},
- {{vc, r6, r2}, "vc, r6, r2", "vc_r6_r2"},
- {{vc, r6, r3}, "vc, r6, r3", "vc_r6_r3"},
- {{vc, r6, r4}, "vc, r6, r4", "vc_r6_r4"},
- {{vc, r6, r5}, "vc, r6, r5", "vc_r6_r5"},
- {{vc, r6, r6}, "vc, r6, r6", "vc_r6_r6"},
- {{vc, r6, r7}, "vc, r6, r7", "vc_r6_r7"},
- {{vc, r6, r8}, "vc, r6, r8", "vc_r6_r8"},
- {{vc, r6, r9}, "vc, r6, r9", "vc_r6_r9"},
- {{vc, r6, r10}, "vc, r6, r10", "vc_r6_r10"},
- {{vc, r6, r11}, "vc, r6, r11", "vc_r6_r11"},
- {{vc, r6, r12}, "vc, r6, r12", "vc_r6_r12"},
- {{vc, r6, r13}, "vc, r6, r13", "vc_r6_r13"},
- {{vc, r6, r14}, "vc, r6, r14", "vc_r6_r14"},
- {{vc, r7, r0}, "vc, r7, r0", "vc_r7_r0"},
- {{vc, r7, r1}, "vc, r7, r1", "vc_r7_r1"},
- {{vc, r7, r2}, "vc, r7, r2", "vc_r7_r2"},
- {{vc, r7, r3}, "vc, r7, r3", "vc_r7_r3"},
- {{vc, r7, r4}, "vc, r7, r4", "vc_r7_r4"},
- {{vc, r7, r5}, "vc, r7, r5", "vc_r7_r5"},
- {{vc, r7, r6}, "vc, r7, r6", "vc_r7_r6"},
- {{vc, r7, r7}, "vc, r7, r7", "vc_r7_r7"},
- {{vc, r7, r8}, "vc, r7, r8", "vc_r7_r8"},
- {{vc, r7, r9}, "vc, r7, r9", "vc_r7_r9"},
- {{vc, r7, r10}, "vc, r7, r10", "vc_r7_r10"},
- {{vc, r7, r11}, "vc, r7, r11", "vc_r7_r11"},
- {{vc, r7, r12}, "vc, r7, r12", "vc_r7_r12"},
- {{vc, r7, r13}, "vc, r7, r13", "vc_r7_r13"},
- {{vc, r7, r14}, "vc, r7, r14", "vc_r7_r14"},
- {{vc, r8, r0}, "vc, r8, r0", "vc_r8_r0"},
- {{vc, r8, r1}, "vc, r8, r1", "vc_r8_r1"},
- {{vc, r8, r2}, "vc, r8, r2", "vc_r8_r2"},
- {{vc, r8, r3}, "vc, r8, r3", "vc_r8_r3"},
- {{vc, r8, r4}, "vc, r8, r4", "vc_r8_r4"},
- {{vc, r8, r5}, "vc, r8, r5", "vc_r8_r5"},
- {{vc, r8, r6}, "vc, r8, r6", "vc_r8_r6"},
- {{vc, r8, r7}, "vc, r8, r7", "vc_r8_r7"},
- {{vc, r8, r8}, "vc, r8, r8", "vc_r8_r8"},
- {{vc, r8, r9}, "vc, r8, r9", "vc_r8_r9"},
- {{vc, r8, r10}, "vc, r8, r10", "vc_r8_r10"},
- {{vc, r8, r11}, "vc, r8, r11", "vc_r8_r11"},
- {{vc, r8, r12}, "vc, r8, r12", "vc_r8_r12"},
- {{vc, r8, r13}, "vc, r8, r13", "vc_r8_r13"},
- {{vc, r8, r14}, "vc, r8, r14", "vc_r8_r14"},
- {{vc, r9, r0}, "vc, r9, r0", "vc_r9_r0"},
- {{vc, r9, r1}, "vc, r9, r1", "vc_r9_r1"},
- {{vc, r9, r2}, "vc, r9, r2", "vc_r9_r2"},
- {{vc, r9, r3}, "vc, r9, r3", "vc_r9_r3"},
- {{vc, r9, r4}, "vc, r9, r4", "vc_r9_r4"},
- {{vc, r9, r5}, "vc, r9, r5", "vc_r9_r5"},
- {{vc, r9, r6}, "vc, r9, r6", "vc_r9_r6"},
- {{vc, r9, r7}, "vc, r9, r7", "vc_r9_r7"},
- {{vc, r9, r8}, "vc, r9, r8", "vc_r9_r8"},
- {{vc, r9, r9}, "vc, r9, r9", "vc_r9_r9"},
- {{vc, r9, r10}, "vc, r9, r10", "vc_r9_r10"},
- {{vc, r9, r11}, "vc, r9, r11", "vc_r9_r11"},
- {{vc, r9, r12}, "vc, r9, r12", "vc_r9_r12"},
- {{vc, r9, r13}, "vc, r9, r13", "vc_r9_r13"},
- {{vc, r9, r14}, "vc, r9, r14", "vc_r9_r14"},
- {{vc, r10, r0}, "vc, r10, r0", "vc_r10_r0"},
- {{vc, r10, r1}, "vc, r10, r1", "vc_r10_r1"},
- {{vc, r10, r2}, "vc, r10, r2", "vc_r10_r2"},
- {{vc, r10, r3}, "vc, r10, r3", "vc_r10_r3"},
- {{vc, r10, r4}, "vc, r10, r4", "vc_r10_r4"},
- {{vc, r10, r5}, "vc, r10, r5", "vc_r10_r5"},
- {{vc, r10, r6}, "vc, r10, r6", "vc_r10_r6"},
- {{vc, r10, r7}, "vc, r10, r7", "vc_r10_r7"},
- {{vc, r10, r8}, "vc, r10, r8", "vc_r10_r8"},
- {{vc, r10, r9}, "vc, r10, r9", "vc_r10_r9"},
- {{vc, r10, r10}, "vc, r10, r10", "vc_r10_r10"},
- {{vc, r10, r11}, "vc, r10, r11", "vc_r10_r11"},
- {{vc, r10, r12}, "vc, r10, r12", "vc_r10_r12"},
- {{vc, r10, r13}, "vc, r10, r13", "vc_r10_r13"},
- {{vc, r10, r14}, "vc, r10, r14", "vc_r10_r14"},
- {{vc, r11, r0}, "vc, r11, r0", "vc_r11_r0"},
- {{vc, r11, r1}, "vc, r11, r1", "vc_r11_r1"},
- {{vc, r11, r2}, "vc, r11, r2", "vc_r11_r2"},
- {{vc, r11, r3}, "vc, r11, r3", "vc_r11_r3"},
- {{vc, r11, r4}, "vc, r11, r4", "vc_r11_r4"},
- {{vc, r11, r5}, "vc, r11, r5", "vc_r11_r5"},
- {{vc, r11, r6}, "vc, r11, r6", "vc_r11_r6"},
- {{vc, r11, r7}, "vc, r11, r7", "vc_r11_r7"},
- {{vc, r11, r8}, "vc, r11, r8", "vc_r11_r8"},
- {{vc, r11, r9}, "vc, r11, r9", "vc_r11_r9"},
- {{vc, r11, r10}, "vc, r11, r10", "vc_r11_r10"},
- {{vc, r11, r11}, "vc, r11, r11", "vc_r11_r11"},
- {{vc, r11, r12}, "vc, r11, r12", "vc_r11_r12"},
- {{vc, r11, r13}, "vc, r11, r13", "vc_r11_r13"},
- {{vc, r11, r14}, "vc, r11, r14", "vc_r11_r14"},
- {{vc, r12, r0}, "vc, r12, r0", "vc_r12_r0"},
- {{vc, r12, r1}, "vc, r12, r1", "vc_r12_r1"},
- {{vc, r12, r2}, "vc, r12, r2", "vc_r12_r2"},
- {{vc, r12, r3}, "vc, r12, r3", "vc_r12_r3"},
- {{vc, r12, r4}, "vc, r12, r4", "vc_r12_r4"},
- {{vc, r12, r5}, "vc, r12, r5", "vc_r12_r5"},
- {{vc, r12, r6}, "vc, r12, r6", "vc_r12_r6"},
- {{vc, r12, r7}, "vc, r12, r7", "vc_r12_r7"},
- {{vc, r12, r8}, "vc, r12, r8", "vc_r12_r8"},
- {{vc, r12, r9}, "vc, r12, r9", "vc_r12_r9"},
- {{vc, r12, r10}, "vc, r12, r10", "vc_r12_r10"},
- {{vc, r12, r11}, "vc, r12, r11", "vc_r12_r11"},
- {{vc, r12, r12}, "vc, r12, r12", "vc_r12_r12"},
- {{vc, r12, r13}, "vc, r12, r13", "vc_r12_r13"},
- {{vc, r12, r14}, "vc, r12, r14", "vc_r12_r14"},
- {{vc, r13, r0}, "vc, r13, r0", "vc_r13_r0"},
- {{vc, r13, r1}, "vc, r13, r1", "vc_r13_r1"},
- {{vc, r13, r2}, "vc, r13, r2", "vc_r13_r2"},
- {{vc, r13, r3}, "vc, r13, r3", "vc_r13_r3"},
- {{vc, r13, r4}, "vc, r13, r4", "vc_r13_r4"},
- {{vc, r13, r5}, "vc, r13, r5", "vc_r13_r5"},
- {{vc, r13, r6}, "vc, r13, r6", "vc_r13_r6"},
- {{vc, r13, r7}, "vc, r13, r7", "vc_r13_r7"},
- {{vc, r13, r8}, "vc, r13, r8", "vc_r13_r8"},
- {{vc, r13, r9}, "vc, r13, r9", "vc_r13_r9"},
- {{vc, r13, r10}, "vc, r13, r10", "vc_r13_r10"},
- {{vc, r13, r11}, "vc, r13, r11", "vc_r13_r11"},
- {{vc, r13, r12}, "vc, r13, r12", "vc_r13_r12"},
- {{vc, r13, r13}, "vc, r13, r13", "vc_r13_r13"},
- {{vc, r13, r14}, "vc, r13, r14", "vc_r13_r14"},
- {{vc, r14, r0}, "vc, r14, r0", "vc_r14_r0"},
- {{vc, r14, r1}, "vc, r14, r1", "vc_r14_r1"},
- {{vc, r14, r2}, "vc, r14, r2", "vc_r14_r2"},
- {{vc, r14, r3}, "vc, r14, r3", "vc_r14_r3"},
- {{vc, r14, r4}, "vc, r14, r4", "vc_r14_r4"},
- {{vc, r14, r5}, "vc, r14, r5", "vc_r14_r5"},
- {{vc, r14, r6}, "vc, r14, r6", "vc_r14_r6"},
- {{vc, r14, r7}, "vc, r14, r7", "vc_r14_r7"},
- {{vc, r14, r8}, "vc, r14, r8", "vc_r14_r8"},
- {{vc, r14, r9}, "vc, r14, r9", "vc_r14_r9"},
- {{vc, r14, r10}, "vc, r14, r10", "vc_r14_r10"},
- {{vc, r14, r11}, "vc, r14, r11", "vc_r14_r11"},
- {{vc, r14, r12}, "vc, r14, r12", "vc_r14_r12"},
- {{vc, r14, r13}, "vc, r14, r13", "vc_r14_r13"},
- {{vc, r14, r14}, "vc, r14, r14", "vc_r14_r14"},
- {{hi, r0, r0}, "hi, r0, r0", "hi_r0_r0"},
- {{hi, r0, r1}, "hi, r0, r1", "hi_r0_r1"},
- {{hi, r0, r2}, "hi, r0, r2", "hi_r0_r2"},
- {{hi, r0, r3}, "hi, r0, r3", "hi_r0_r3"},
- {{hi, r0, r4}, "hi, r0, r4", "hi_r0_r4"},
- {{hi, r0, r5}, "hi, r0, r5", "hi_r0_r5"},
- {{hi, r0, r6}, "hi, r0, r6", "hi_r0_r6"},
- {{hi, r0, r7}, "hi, r0, r7", "hi_r0_r7"},
- {{hi, r0, r8}, "hi, r0, r8", "hi_r0_r8"},
- {{hi, r0, r9}, "hi, r0, r9", "hi_r0_r9"},
- {{hi, r0, r10}, "hi, r0, r10", "hi_r0_r10"},
- {{hi, r0, r11}, "hi, r0, r11", "hi_r0_r11"},
- {{hi, r0, r12}, "hi, r0, r12", "hi_r0_r12"},
- {{hi, r0, r13}, "hi, r0, r13", "hi_r0_r13"},
- {{hi, r0, r14}, "hi, r0, r14", "hi_r0_r14"},
- {{hi, r1, r0}, "hi, r1, r0", "hi_r1_r0"},
- {{hi, r1, r1}, "hi, r1, r1", "hi_r1_r1"},
- {{hi, r1, r2}, "hi, r1, r2", "hi_r1_r2"},
- {{hi, r1, r3}, "hi, r1, r3", "hi_r1_r3"},
- {{hi, r1, r4}, "hi, r1, r4", "hi_r1_r4"},
- {{hi, r1, r5}, "hi, r1, r5", "hi_r1_r5"},
- {{hi, r1, r6}, "hi, r1, r6", "hi_r1_r6"},
- {{hi, r1, r7}, "hi, r1, r7", "hi_r1_r7"},
- {{hi, r1, r8}, "hi, r1, r8", "hi_r1_r8"},
- {{hi, r1, r9}, "hi, r1, r9", "hi_r1_r9"},
- {{hi, r1, r10}, "hi, r1, r10", "hi_r1_r10"},
- {{hi, r1, r11}, "hi, r1, r11", "hi_r1_r11"},
- {{hi, r1, r12}, "hi, r1, r12", "hi_r1_r12"},
- {{hi, r1, r13}, "hi, r1, r13", "hi_r1_r13"},
- {{hi, r1, r14}, "hi, r1, r14", "hi_r1_r14"},
- {{hi, r2, r0}, "hi, r2, r0", "hi_r2_r0"},
- {{hi, r2, r1}, "hi, r2, r1", "hi_r2_r1"},
- {{hi, r2, r2}, "hi, r2, r2", "hi_r2_r2"},
- {{hi, r2, r3}, "hi, r2, r3", "hi_r2_r3"},
- {{hi, r2, r4}, "hi, r2, r4", "hi_r2_r4"},
- {{hi, r2, r5}, "hi, r2, r5", "hi_r2_r5"},
- {{hi, r2, r6}, "hi, r2, r6", "hi_r2_r6"},
- {{hi, r2, r7}, "hi, r2, r7", "hi_r2_r7"},
- {{hi, r2, r8}, "hi, r2, r8", "hi_r2_r8"},
- {{hi, r2, r9}, "hi, r2, r9", "hi_r2_r9"},
- {{hi, r2, r10}, "hi, r2, r10", "hi_r2_r10"},
- {{hi, r2, r11}, "hi, r2, r11", "hi_r2_r11"},
- {{hi, r2, r12}, "hi, r2, r12", "hi_r2_r12"},
- {{hi, r2, r13}, "hi, r2, r13", "hi_r2_r13"},
- {{hi, r2, r14}, "hi, r2, r14", "hi_r2_r14"},
- {{hi, r3, r0}, "hi, r3, r0", "hi_r3_r0"},
- {{hi, r3, r1}, "hi, r3, r1", "hi_r3_r1"},
- {{hi, r3, r2}, "hi, r3, r2", "hi_r3_r2"},
- {{hi, r3, r3}, "hi, r3, r3", "hi_r3_r3"},
- {{hi, r3, r4}, "hi, r3, r4", "hi_r3_r4"},
- {{hi, r3, r5}, "hi, r3, r5", "hi_r3_r5"},
- {{hi, r3, r6}, "hi, r3, r6", "hi_r3_r6"},
- {{hi, r3, r7}, "hi, r3, r7", "hi_r3_r7"},
- {{hi, r3, r8}, "hi, r3, r8", "hi_r3_r8"},
- {{hi, r3, r9}, "hi, r3, r9", "hi_r3_r9"},
- {{hi, r3, r10}, "hi, r3, r10", "hi_r3_r10"},
- {{hi, r3, r11}, "hi, r3, r11", "hi_r3_r11"},
- {{hi, r3, r12}, "hi, r3, r12", "hi_r3_r12"},
- {{hi, r3, r13}, "hi, r3, r13", "hi_r3_r13"},
- {{hi, r3, r14}, "hi, r3, r14", "hi_r3_r14"},
- {{hi, r4, r0}, "hi, r4, r0", "hi_r4_r0"},
- {{hi, r4, r1}, "hi, r4, r1", "hi_r4_r1"},
- {{hi, r4, r2}, "hi, r4, r2", "hi_r4_r2"},
- {{hi, r4, r3}, "hi, r4, r3", "hi_r4_r3"},
- {{hi, r4, r4}, "hi, r4, r4", "hi_r4_r4"},
- {{hi, r4, r5}, "hi, r4, r5", "hi_r4_r5"},
- {{hi, r4, r6}, "hi, r4, r6", "hi_r4_r6"},
- {{hi, r4, r7}, "hi, r4, r7", "hi_r4_r7"},
- {{hi, r4, r8}, "hi, r4, r8", "hi_r4_r8"},
- {{hi, r4, r9}, "hi, r4, r9", "hi_r4_r9"},
- {{hi, r4, r10}, "hi, r4, r10", "hi_r4_r10"},
- {{hi, r4, r11}, "hi, r4, r11", "hi_r4_r11"},
- {{hi, r4, r12}, "hi, r4, r12", "hi_r4_r12"},
- {{hi, r4, r13}, "hi, r4, r13", "hi_r4_r13"},
- {{hi, r4, r14}, "hi, r4, r14", "hi_r4_r14"},
- {{hi, r5, r0}, "hi, r5, r0", "hi_r5_r0"},
- {{hi, r5, r1}, "hi, r5, r1", "hi_r5_r1"},
- {{hi, r5, r2}, "hi, r5, r2", "hi_r5_r2"},
- {{hi, r5, r3}, "hi, r5, r3", "hi_r5_r3"},
- {{hi, r5, r4}, "hi, r5, r4", "hi_r5_r4"},
- {{hi, r5, r5}, "hi, r5, r5", "hi_r5_r5"},
- {{hi, r5, r6}, "hi, r5, r6", "hi_r5_r6"},
- {{hi, r5, r7}, "hi, r5, r7", "hi_r5_r7"},
- {{hi, r5, r8}, "hi, r5, r8", "hi_r5_r8"},
- {{hi, r5, r9}, "hi, r5, r9", "hi_r5_r9"},
- {{hi, r5, r10}, "hi, r5, r10", "hi_r5_r10"},
- {{hi, r5, r11}, "hi, r5, r11", "hi_r5_r11"},
- {{hi, r5, r12}, "hi, r5, r12", "hi_r5_r12"},
- {{hi, r5, r13}, "hi, r5, r13", "hi_r5_r13"},
- {{hi, r5, r14}, "hi, r5, r14", "hi_r5_r14"},
- {{hi, r6, r0}, "hi, r6, r0", "hi_r6_r0"},
- {{hi, r6, r1}, "hi, r6, r1", "hi_r6_r1"},
- {{hi, r6, r2}, "hi, r6, r2", "hi_r6_r2"},
- {{hi, r6, r3}, "hi, r6, r3", "hi_r6_r3"},
- {{hi, r6, r4}, "hi, r6, r4", "hi_r6_r4"},
- {{hi, r6, r5}, "hi, r6, r5", "hi_r6_r5"},
- {{hi, r6, r6}, "hi, r6, r6", "hi_r6_r6"},
- {{hi, r6, r7}, "hi, r6, r7", "hi_r6_r7"},
- {{hi, r6, r8}, "hi, r6, r8", "hi_r6_r8"},
- {{hi, r6, r9}, "hi, r6, r9", "hi_r6_r9"},
- {{hi, r6, r10}, "hi, r6, r10", "hi_r6_r10"},
- {{hi, r6, r11}, "hi, r6, r11", "hi_r6_r11"},
- {{hi, r6, r12}, "hi, r6, r12", "hi_r6_r12"},
- {{hi, r6, r13}, "hi, r6, r13", "hi_r6_r13"},
- {{hi, r6, r14}, "hi, r6, r14", "hi_r6_r14"},
- {{hi, r7, r0}, "hi, r7, r0", "hi_r7_r0"},
- {{hi, r7, r1}, "hi, r7, r1", "hi_r7_r1"},
- {{hi, r7, r2}, "hi, r7, r2", "hi_r7_r2"},
- {{hi, r7, r3}, "hi, r7, r3", "hi_r7_r3"},
- {{hi, r7, r4}, "hi, r7, r4", "hi_r7_r4"},
- {{hi, r7, r5}, "hi, r7, r5", "hi_r7_r5"},
- {{hi, r7, r6}, "hi, r7, r6", "hi_r7_r6"},
- {{hi, r7, r7}, "hi, r7, r7", "hi_r7_r7"},
- {{hi, r7, r8}, "hi, r7, r8", "hi_r7_r8"},
- {{hi, r7, r9}, "hi, r7, r9", "hi_r7_r9"},
- {{hi, r7, r10}, "hi, r7, r10", "hi_r7_r10"},
- {{hi, r7, r11}, "hi, r7, r11", "hi_r7_r11"},
- {{hi, r7, r12}, "hi, r7, r12", "hi_r7_r12"},
- {{hi, r7, r13}, "hi, r7, r13", "hi_r7_r13"},
- {{hi, r7, r14}, "hi, r7, r14", "hi_r7_r14"},
- {{hi, r8, r0}, "hi, r8, r0", "hi_r8_r0"},
- {{hi, r8, r1}, "hi, r8, r1", "hi_r8_r1"},
- {{hi, r8, r2}, "hi, r8, r2", "hi_r8_r2"},
- {{hi, r8, r3}, "hi, r8, r3", "hi_r8_r3"},
- {{hi, r8, r4}, "hi, r8, r4", "hi_r8_r4"},
- {{hi, r8, r5}, "hi, r8, r5", "hi_r8_r5"},
- {{hi, r8, r6}, "hi, r8, r6", "hi_r8_r6"},
- {{hi, r8, r7}, "hi, r8, r7", "hi_r8_r7"},
- {{hi, r8, r8}, "hi, r8, r8", "hi_r8_r8"},
- {{hi, r8, r9}, "hi, r8, r9", "hi_r8_r9"},
- {{hi, r8, r10}, "hi, r8, r10", "hi_r8_r10"},
- {{hi, r8, r11}, "hi, r8, r11", "hi_r8_r11"},
- {{hi, r8, r12}, "hi, r8, r12", "hi_r8_r12"},
- {{hi, r8, r13}, "hi, r8, r13", "hi_r8_r13"},
- {{hi, r8, r14}, "hi, r8, r14", "hi_r8_r14"},
- {{hi, r9, r0}, "hi, r9, r0", "hi_r9_r0"},
- {{hi, r9, r1}, "hi, r9, r1", "hi_r9_r1"},
- {{hi, r9, r2}, "hi, r9, r2", "hi_r9_r2"},
- {{hi, r9, r3}, "hi, r9, r3", "hi_r9_r3"},
- {{hi, r9, r4}, "hi, r9, r4", "hi_r9_r4"},
- {{hi, r9, r5}, "hi, r9, r5", "hi_r9_r5"},
- {{hi, r9, r6}, "hi, r9, r6", "hi_r9_r6"},
- {{hi, r9, r7}, "hi, r9, r7", "hi_r9_r7"},
- {{hi, r9, r8}, "hi, r9, r8", "hi_r9_r8"},
- {{hi, r9, r9}, "hi, r9, r9", "hi_r9_r9"},
- {{hi, r9, r10}, "hi, r9, r10", "hi_r9_r10"},
- {{hi, r9, r11}, "hi, r9, r11", "hi_r9_r11"},
- {{hi, r9, r12}, "hi, r9, r12", "hi_r9_r12"},
- {{hi, r9, r13}, "hi, r9, r13", "hi_r9_r13"},
- {{hi, r9, r14}, "hi, r9, r14", "hi_r9_r14"},
- {{hi, r10, r0}, "hi, r10, r0", "hi_r10_r0"},
- {{hi, r10, r1}, "hi, r10, r1", "hi_r10_r1"},
- {{hi, r10, r2}, "hi, r10, r2", "hi_r10_r2"},
- {{hi, r10, r3}, "hi, r10, r3", "hi_r10_r3"},
- {{hi, r10, r4}, "hi, r10, r4", "hi_r10_r4"},
- {{hi, r10, r5}, "hi, r10, r5", "hi_r10_r5"},
- {{hi, r10, r6}, "hi, r10, r6", "hi_r10_r6"},
- {{hi, r10, r7}, "hi, r10, r7", "hi_r10_r7"},
- {{hi, r10, r8}, "hi, r10, r8", "hi_r10_r8"},
- {{hi, r10, r9}, "hi, r10, r9", "hi_r10_r9"},
- {{hi, r10, r10}, "hi, r10, r10", "hi_r10_r10"},
- {{hi, r10, r11}, "hi, r10, r11", "hi_r10_r11"},
- {{hi, r10, r12}, "hi, r10, r12", "hi_r10_r12"},
- {{hi, r10, r13}, "hi, r10, r13", "hi_r10_r13"},
- {{hi, r10, r14}, "hi, r10, r14", "hi_r10_r14"},
- {{hi, r11, r0}, "hi, r11, r0", "hi_r11_r0"},
- {{hi, r11, r1}, "hi, r11, r1", "hi_r11_r1"},
- {{hi, r11, r2}, "hi, r11, r2", "hi_r11_r2"},
- {{hi, r11, r3}, "hi, r11, r3", "hi_r11_r3"},
- {{hi, r11, r4}, "hi, r11, r4", "hi_r11_r4"},
- {{hi, r11, r5}, "hi, r11, r5", "hi_r11_r5"},
- {{hi, r11, r6}, "hi, r11, r6", "hi_r11_r6"},
- {{hi, r11, r7}, "hi, r11, r7", "hi_r11_r7"},
- {{hi, r11, r8}, "hi, r11, r8", "hi_r11_r8"},
- {{hi, r11, r9}, "hi, r11, r9", "hi_r11_r9"},
- {{hi, r11, r10}, "hi, r11, r10", "hi_r11_r10"},
- {{hi, r11, r11}, "hi, r11, r11", "hi_r11_r11"},
- {{hi, r11, r12}, "hi, r11, r12", "hi_r11_r12"},
- {{hi, r11, r13}, "hi, r11, r13", "hi_r11_r13"},
- {{hi, r11, r14}, "hi, r11, r14", "hi_r11_r14"},
- {{hi, r12, r0}, "hi, r12, r0", "hi_r12_r0"},
- {{hi, r12, r1}, "hi, r12, r1", "hi_r12_r1"},
- {{hi, r12, r2}, "hi, r12, r2", "hi_r12_r2"},
- {{hi, r12, r3}, "hi, r12, r3", "hi_r12_r3"},
- {{hi, r12, r4}, "hi, r12, r4", "hi_r12_r4"},
- {{hi, r12, r5}, "hi, r12, r5", "hi_r12_r5"},
- {{hi, r12, r6}, "hi, r12, r6", "hi_r12_r6"},
- {{hi, r12, r7}, "hi, r12, r7", "hi_r12_r7"},
- {{hi, r12, r8}, "hi, r12, r8", "hi_r12_r8"},
- {{hi, r12, r9}, "hi, r12, r9", "hi_r12_r9"},
- {{hi, r12, r10}, "hi, r12, r10", "hi_r12_r10"},
- {{hi, r12, r11}, "hi, r12, r11", "hi_r12_r11"},
- {{hi, r12, r12}, "hi, r12, r12", "hi_r12_r12"},
- {{hi, r12, r13}, "hi, r12, r13", "hi_r12_r13"},
- {{hi, r12, r14}, "hi, r12, r14", "hi_r12_r14"},
- {{hi, r13, r0}, "hi, r13, r0", "hi_r13_r0"},
- {{hi, r13, r1}, "hi, r13, r1", "hi_r13_r1"},
- {{hi, r13, r2}, "hi, r13, r2", "hi_r13_r2"},
- {{hi, r13, r3}, "hi, r13, r3", "hi_r13_r3"},
- {{hi, r13, r4}, "hi, r13, r4", "hi_r13_r4"},
- {{hi, r13, r5}, "hi, r13, r5", "hi_r13_r5"},
- {{hi, r13, r6}, "hi, r13, r6", "hi_r13_r6"},
- {{hi, r13, r7}, "hi, r13, r7", "hi_r13_r7"},
- {{hi, r13, r8}, "hi, r13, r8", "hi_r13_r8"},
- {{hi, r13, r9}, "hi, r13, r9", "hi_r13_r9"},
- {{hi, r13, r10}, "hi, r13, r10", "hi_r13_r10"},
- {{hi, r13, r11}, "hi, r13, r11", "hi_r13_r11"},
- {{hi, r13, r12}, "hi, r13, r12", "hi_r13_r12"},
- {{hi, r13, r13}, "hi, r13, r13", "hi_r13_r13"},
- {{hi, r13, r14}, "hi, r13, r14", "hi_r13_r14"},
- {{hi, r14, r0}, "hi, r14, r0", "hi_r14_r0"},
- {{hi, r14, r1}, "hi, r14, r1", "hi_r14_r1"},
- {{hi, r14, r2}, "hi, r14, r2", "hi_r14_r2"},
- {{hi, r14, r3}, "hi, r14, r3", "hi_r14_r3"},
- {{hi, r14, r4}, "hi, r14, r4", "hi_r14_r4"},
- {{hi, r14, r5}, "hi, r14, r5", "hi_r14_r5"},
- {{hi, r14, r6}, "hi, r14, r6", "hi_r14_r6"},
- {{hi, r14, r7}, "hi, r14, r7", "hi_r14_r7"},
- {{hi, r14, r8}, "hi, r14, r8", "hi_r14_r8"},
- {{hi, r14, r9}, "hi, r14, r9", "hi_r14_r9"},
- {{hi, r14, r10}, "hi, r14, r10", "hi_r14_r10"},
- {{hi, r14, r11}, "hi, r14, r11", "hi_r14_r11"},
- {{hi, r14, r12}, "hi, r14, r12", "hi_r14_r12"},
- {{hi, r14, r13}, "hi, r14, r13", "hi_r14_r13"},
- {{hi, r14, r14}, "hi, r14, r14", "hi_r14_r14"},
- {{ls, r0, r0}, "ls, r0, r0", "ls_r0_r0"},
- {{ls, r0, r1}, "ls, r0, r1", "ls_r0_r1"},
- {{ls, r0, r2}, "ls, r0, r2", "ls_r0_r2"},
- {{ls, r0, r3}, "ls, r0, r3", "ls_r0_r3"},
- {{ls, r0, r4}, "ls, r0, r4", "ls_r0_r4"},
- {{ls, r0, r5}, "ls, r0, r5", "ls_r0_r5"},
- {{ls, r0, r6}, "ls, r0, r6", "ls_r0_r6"},
- {{ls, r0, r7}, "ls, r0, r7", "ls_r0_r7"},
- {{ls, r0, r8}, "ls, r0, r8", "ls_r0_r8"},
- {{ls, r0, r9}, "ls, r0, r9", "ls_r0_r9"},
- {{ls, r0, r10}, "ls, r0, r10", "ls_r0_r10"},
- {{ls, r0, r11}, "ls, r0, r11", "ls_r0_r11"},
- {{ls, r0, r12}, "ls, r0, r12", "ls_r0_r12"},
- {{ls, r0, r13}, "ls, r0, r13", "ls_r0_r13"},
- {{ls, r0, r14}, "ls, r0, r14", "ls_r0_r14"},
- {{ls, r1, r0}, "ls, r1, r0", "ls_r1_r0"},
- {{ls, r1, r1}, "ls, r1, r1", "ls_r1_r1"},
- {{ls, r1, r2}, "ls, r1, r2", "ls_r1_r2"},
- {{ls, r1, r3}, "ls, r1, r3", "ls_r1_r3"},
- {{ls, r1, r4}, "ls, r1, r4", "ls_r1_r4"},
- {{ls, r1, r5}, "ls, r1, r5", "ls_r1_r5"},
- {{ls, r1, r6}, "ls, r1, r6", "ls_r1_r6"},
- {{ls, r1, r7}, "ls, r1, r7", "ls_r1_r7"},
- {{ls, r1, r8}, "ls, r1, r8", "ls_r1_r8"},
- {{ls, r1, r9}, "ls, r1, r9", "ls_r1_r9"},
- {{ls, r1, r10}, "ls, r1, r10", "ls_r1_r10"},
- {{ls, r1, r11}, "ls, r1, r11", "ls_r1_r11"},
- {{ls, r1, r12}, "ls, r1, r12", "ls_r1_r12"},
- {{ls, r1, r13}, "ls, r1, r13", "ls_r1_r13"},
- {{ls, r1, r14}, "ls, r1, r14", "ls_r1_r14"},
- {{ls, r2, r0}, "ls, r2, r0", "ls_r2_r0"},
- {{ls, r2, r1}, "ls, r2, r1", "ls_r2_r1"},
- {{ls, r2, r2}, "ls, r2, r2", "ls_r2_r2"},
- {{ls, r2, r3}, "ls, r2, r3", "ls_r2_r3"},
- {{ls, r2, r4}, "ls, r2, r4", "ls_r2_r4"},
- {{ls, r2, r5}, "ls, r2, r5", "ls_r2_r5"},
- {{ls, r2, r6}, "ls, r2, r6", "ls_r2_r6"},
- {{ls, r2, r7}, "ls, r2, r7", "ls_r2_r7"},
- {{ls, r2, r8}, "ls, r2, r8", "ls_r2_r8"},
- {{ls, r2, r9}, "ls, r2, r9", "ls_r2_r9"},
- {{ls, r2, r10}, "ls, r2, r10", "ls_r2_r10"},
- {{ls, r2, r11}, "ls, r2, r11", "ls_r2_r11"},
- {{ls, r2, r12}, "ls, r2, r12", "ls_r2_r12"},
- {{ls, r2, r13}, "ls, r2, r13", "ls_r2_r13"},
- {{ls, r2, r14}, "ls, r2, r14", "ls_r2_r14"},
- {{ls, r3, r0}, "ls, r3, r0", "ls_r3_r0"},
- {{ls, r3, r1}, "ls, r3, r1", "ls_r3_r1"},
- {{ls, r3, r2}, "ls, r3, r2", "ls_r3_r2"},
- {{ls, r3, r3}, "ls, r3, r3", "ls_r3_r3"},
- {{ls, r3, r4}, "ls, r3, r4", "ls_r3_r4"},
- {{ls, r3, r5}, "ls, r3, r5", "ls_r3_r5"},
- {{ls, r3, r6}, "ls, r3, r6", "ls_r3_r6"},
- {{ls, r3, r7}, "ls, r3, r7", "ls_r3_r7"},
- {{ls, r3, r8}, "ls, r3, r8", "ls_r3_r8"},
- {{ls, r3, r9}, "ls, r3, r9", "ls_r3_r9"},
- {{ls, r3, r10}, "ls, r3, r10", "ls_r3_r10"},
- {{ls, r3, r11}, "ls, r3, r11", "ls_r3_r11"},
- {{ls, r3, r12}, "ls, r3, r12", "ls_r3_r12"},
- {{ls, r3, r13}, "ls, r3, r13", "ls_r3_r13"},
- {{ls, r3, r14}, "ls, r3, r14", "ls_r3_r14"},
- {{ls, r4, r0}, "ls, r4, r0", "ls_r4_r0"},
- {{ls, r4, r1}, "ls, r4, r1", "ls_r4_r1"},
- {{ls, r4, r2}, "ls, r4, r2", "ls_r4_r2"},
- {{ls, r4, r3}, "ls, r4, r3", "ls_r4_r3"},
- {{ls, r4, r4}, "ls, r4, r4", "ls_r4_r4"},
- {{ls, r4, r5}, "ls, r4, r5", "ls_r4_r5"},
- {{ls, r4, r6}, "ls, r4, r6", "ls_r4_r6"},
- {{ls, r4, r7}, "ls, r4, r7", "ls_r4_r7"},
- {{ls, r4, r8}, "ls, r4, r8", "ls_r4_r8"},
- {{ls, r4, r9}, "ls, r4, r9", "ls_r4_r9"},
- {{ls, r4, r10}, "ls, r4, r10", "ls_r4_r10"},
- {{ls, r4, r11}, "ls, r4, r11", "ls_r4_r11"},
- {{ls, r4, r12}, "ls, r4, r12", "ls_r4_r12"},
- {{ls, r4, r13}, "ls, r4, r13", "ls_r4_r13"},
- {{ls, r4, r14}, "ls, r4, r14", "ls_r4_r14"},
- {{ls, r5, r0}, "ls, r5, r0", "ls_r5_r0"},
- {{ls, r5, r1}, "ls, r5, r1", "ls_r5_r1"},
- {{ls, r5, r2}, "ls, r5, r2", "ls_r5_r2"},
- {{ls, r5, r3}, "ls, r5, r3", "ls_r5_r3"},
- {{ls, r5, r4}, "ls, r5, r4", "ls_r5_r4"},
- {{ls, r5, r5}, "ls, r5, r5", "ls_r5_r5"},
- {{ls, r5, r6}, "ls, r5, r6", "ls_r5_r6"},
- {{ls, r5, r7}, "ls, r5, r7", "ls_r5_r7"},
- {{ls, r5, r8}, "ls, r5, r8", "ls_r5_r8"},
- {{ls, r5, r9}, "ls, r5, r9", "ls_r5_r9"},
- {{ls, r5, r10}, "ls, r5, r10", "ls_r5_r10"},
- {{ls, r5, r11}, "ls, r5, r11", "ls_r5_r11"},
- {{ls, r5, r12}, "ls, r5, r12", "ls_r5_r12"},
- {{ls, r5, r13}, "ls, r5, r13", "ls_r5_r13"},
- {{ls, r5, r14}, "ls, r5, r14", "ls_r5_r14"},
- {{ls, r6, r0}, "ls, r6, r0", "ls_r6_r0"},
- {{ls, r6, r1}, "ls, r6, r1", "ls_r6_r1"},
- {{ls, r6, r2}, "ls, r6, r2", "ls_r6_r2"},
- {{ls, r6, r3}, "ls, r6, r3", "ls_r6_r3"},
- {{ls, r6, r4}, "ls, r6, r4", "ls_r6_r4"},
- {{ls, r6, r5}, "ls, r6, r5", "ls_r6_r5"},
- {{ls, r6, r6}, "ls, r6, r6", "ls_r6_r6"},
- {{ls, r6, r7}, "ls, r6, r7", "ls_r6_r7"},
- {{ls, r6, r8}, "ls, r6, r8", "ls_r6_r8"},
- {{ls, r6, r9}, "ls, r6, r9", "ls_r6_r9"},
- {{ls, r6, r10}, "ls, r6, r10", "ls_r6_r10"},
- {{ls, r6, r11}, "ls, r6, r11", "ls_r6_r11"},
- {{ls, r6, r12}, "ls, r6, r12", "ls_r6_r12"},
- {{ls, r6, r13}, "ls, r6, r13", "ls_r6_r13"},
- {{ls, r6, r14}, "ls, r6, r14", "ls_r6_r14"},
- {{ls, r7, r0}, "ls, r7, r0", "ls_r7_r0"},
- {{ls, r7, r1}, "ls, r7, r1", "ls_r7_r1"},
- {{ls, r7, r2}, "ls, r7, r2", "ls_r7_r2"},
- {{ls, r7, r3}, "ls, r7, r3", "ls_r7_r3"},
- {{ls, r7, r4}, "ls, r7, r4", "ls_r7_r4"},
- {{ls, r7, r5}, "ls, r7, r5", "ls_r7_r5"},
- {{ls, r7, r6}, "ls, r7, r6", "ls_r7_r6"},
- {{ls, r7, r7}, "ls, r7, r7", "ls_r7_r7"},
- {{ls, r7, r8}, "ls, r7, r8", "ls_r7_r8"},
- {{ls, r7, r9}, "ls, r7, r9", "ls_r7_r9"},
- {{ls, r7, r10}, "ls, r7, r10", "ls_r7_r10"},
- {{ls, r7, r11}, "ls, r7, r11", "ls_r7_r11"},
- {{ls, r7, r12}, "ls, r7, r12", "ls_r7_r12"},
- {{ls, r7, r13}, "ls, r7, r13", "ls_r7_r13"},
- {{ls, r7, r14}, "ls, r7, r14", "ls_r7_r14"},
- {{ls, r8, r0}, "ls, r8, r0", "ls_r8_r0"},
- {{ls, r8, r1}, "ls, r8, r1", "ls_r8_r1"},
- {{ls, r8, r2}, "ls, r8, r2", "ls_r8_r2"},
- {{ls, r8, r3}, "ls, r8, r3", "ls_r8_r3"},
- {{ls, r8, r4}, "ls, r8, r4", "ls_r8_r4"},
- {{ls, r8, r5}, "ls, r8, r5", "ls_r8_r5"},
- {{ls, r8, r6}, "ls, r8, r6", "ls_r8_r6"},
- {{ls, r8, r7}, "ls, r8, r7", "ls_r8_r7"},
- {{ls, r8, r8}, "ls, r8, r8", "ls_r8_r8"},
- {{ls, r8, r9}, "ls, r8, r9", "ls_r8_r9"},
- {{ls, r8, r10}, "ls, r8, r10", "ls_r8_r10"},
- {{ls, r8, r11}, "ls, r8, r11", "ls_r8_r11"},
- {{ls, r8, r12}, "ls, r8, r12", "ls_r8_r12"},
- {{ls, r8, r13}, "ls, r8, r13", "ls_r8_r13"},
- {{ls, r8, r14}, "ls, r8, r14", "ls_r8_r14"},
- {{ls, r9, r0}, "ls, r9, r0", "ls_r9_r0"},
- {{ls, r9, r1}, "ls, r9, r1", "ls_r9_r1"},
- {{ls, r9, r2}, "ls, r9, r2", "ls_r9_r2"},
- {{ls, r9, r3}, "ls, r9, r3", "ls_r9_r3"},
- {{ls, r9, r4}, "ls, r9, r4", "ls_r9_r4"},
- {{ls, r9, r5}, "ls, r9, r5", "ls_r9_r5"},
- {{ls, r9, r6}, "ls, r9, r6", "ls_r9_r6"},
- {{ls, r9, r7}, "ls, r9, r7", "ls_r9_r7"},
- {{ls, r9, r8}, "ls, r9, r8", "ls_r9_r8"},
- {{ls, r9, r9}, "ls, r9, r9", "ls_r9_r9"},
- {{ls, r9, r10}, "ls, r9, r10", "ls_r9_r10"},
- {{ls, r9, r11}, "ls, r9, r11", "ls_r9_r11"},
- {{ls, r9, r12}, "ls, r9, r12", "ls_r9_r12"},
- {{ls, r9, r13}, "ls, r9, r13", "ls_r9_r13"},
- {{ls, r9, r14}, "ls, r9, r14", "ls_r9_r14"},
- {{ls, r10, r0}, "ls, r10, r0", "ls_r10_r0"},
- {{ls, r10, r1}, "ls, r10, r1", "ls_r10_r1"},
- {{ls, r10, r2}, "ls, r10, r2", "ls_r10_r2"},
- {{ls, r10, r3}, "ls, r10, r3", "ls_r10_r3"},
- {{ls, r10, r4}, "ls, r10, r4", "ls_r10_r4"},
- {{ls, r10, r5}, "ls, r10, r5", "ls_r10_r5"},
- {{ls, r10, r6}, "ls, r10, r6", "ls_r10_r6"},
- {{ls, r10, r7}, "ls, r10, r7", "ls_r10_r7"},
- {{ls, r10, r8}, "ls, r10, r8", "ls_r10_r8"},
- {{ls, r10, r9}, "ls, r10, r9", "ls_r10_r9"},
- {{ls, r10, r10}, "ls, r10, r10", "ls_r10_r10"},
- {{ls, r10, r11}, "ls, r10, r11", "ls_r10_r11"},
- {{ls, r10, r12}, "ls, r10, r12", "ls_r10_r12"},
- {{ls, r10, r13}, "ls, r10, r13", "ls_r10_r13"},
- {{ls, r10, r14}, "ls, r10, r14", "ls_r10_r14"},
- {{ls, r11, r0}, "ls, r11, r0", "ls_r11_r0"},
- {{ls, r11, r1}, "ls, r11, r1", "ls_r11_r1"},
- {{ls, r11, r2}, "ls, r11, r2", "ls_r11_r2"},
- {{ls, r11, r3}, "ls, r11, r3", "ls_r11_r3"},
- {{ls, r11, r4}, "ls, r11, r4", "ls_r11_r4"},
- {{ls, r11, r5}, "ls, r11, r5", "ls_r11_r5"},
- {{ls, r11, r6}, "ls, r11, r6", "ls_r11_r6"},
- {{ls, r11, r7}, "ls, r11, r7", "ls_r11_r7"},
- {{ls, r11, r8}, "ls, r11, r8", "ls_r11_r8"},
- {{ls, r11, r9}, "ls, r11, r9", "ls_r11_r9"},
- {{ls, r11, r10}, "ls, r11, r10", "ls_r11_r10"},
- {{ls, r11, r11}, "ls, r11, r11", "ls_r11_r11"},
- {{ls, r11, r12}, "ls, r11, r12", "ls_r11_r12"},
- {{ls, r11, r13}, "ls, r11, r13", "ls_r11_r13"},
- {{ls, r11, r14}, "ls, r11, r14", "ls_r11_r14"},
- {{ls, r12, r0}, "ls, r12, r0", "ls_r12_r0"},
- {{ls, r12, r1}, "ls, r12, r1", "ls_r12_r1"},
- {{ls, r12, r2}, "ls, r12, r2", "ls_r12_r2"},
- {{ls, r12, r3}, "ls, r12, r3", "ls_r12_r3"},
- {{ls, r12, r4}, "ls, r12, r4", "ls_r12_r4"},
- {{ls, r12, r5}, "ls, r12, r5", "ls_r12_r5"},
- {{ls, r12, r6}, "ls, r12, r6", "ls_r12_r6"},
- {{ls, r12, r7}, "ls, r12, r7", "ls_r12_r7"},
- {{ls, r12, r8}, "ls, r12, r8", "ls_r12_r8"},
- {{ls, r12, r9}, "ls, r12, r9", "ls_r12_r9"},
- {{ls, r12, r10}, "ls, r12, r10", "ls_r12_r10"},
- {{ls, r12, r11}, "ls, r12, r11", "ls_r12_r11"},
- {{ls, r12, r12}, "ls, r12, r12", "ls_r12_r12"},
- {{ls, r12, r13}, "ls, r12, r13", "ls_r12_r13"},
- {{ls, r12, r14}, "ls, r12, r14", "ls_r12_r14"},
- {{ls, r13, r0}, "ls, r13, r0", "ls_r13_r0"},
- {{ls, r13, r1}, "ls, r13, r1", "ls_r13_r1"},
- {{ls, r13, r2}, "ls, r13, r2", "ls_r13_r2"},
- {{ls, r13, r3}, "ls, r13, r3", "ls_r13_r3"},
- {{ls, r13, r4}, "ls, r13, r4", "ls_r13_r4"},
- {{ls, r13, r5}, "ls, r13, r5", "ls_r13_r5"},
- {{ls, r13, r6}, "ls, r13, r6", "ls_r13_r6"},
- {{ls, r13, r7}, "ls, r13, r7", "ls_r13_r7"},
- {{ls, r13, r8}, "ls, r13, r8", "ls_r13_r8"},
- {{ls, r13, r9}, "ls, r13, r9", "ls_r13_r9"},
- {{ls, r13, r10}, "ls, r13, r10", "ls_r13_r10"},
- {{ls, r13, r11}, "ls, r13, r11", "ls_r13_r11"},
- {{ls, r13, r12}, "ls, r13, r12", "ls_r13_r12"},
- {{ls, r13, r13}, "ls, r13, r13", "ls_r13_r13"},
- {{ls, r13, r14}, "ls, r13, r14", "ls_r13_r14"},
- {{ls, r14, r0}, "ls, r14, r0", "ls_r14_r0"},
- {{ls, r14, r1}, "ls, r14, r1", "ls_r14_r1"},
- {{ls, r14, r2}, "ls, r14, r2", "ls_r14_r2"},
- {{ls, r14, r3}, "ls, r14, r3", "ls_r14_r3"},
- {{ls, r14, r4}, "ls, r14, r4", "ls_r14_r4"},
- {{ls, r14, r5}, "ls, r14, r5", "ls_r14_r5"},
- {{ls, r14, r6}, "ls, r14, r6", "ls_r14_r6"},
- {{ls, r14, r7}, "ls, r14, r7", "ls_r14_r7"},
- {{ls, r14, r8}, "ls, r14, r8", "ls_r14_r8"},
- {{ls, r14, r9}, "ls, r14, r9", "ls_r14_r9"},
- {{ls, r14, r10}, "ls, r14, r10", "ls_r14_r10"},
- {{ls, r14, r11}, "ls, r14, r11", "ls_r14_r11"},
- {{ls, r14, r12}, "ls, r14, r12", "ls_r14_r12"},
- {{ls, r14, r13}, "ls, r14, r13", "ls_r14_r13"},
- {{ls, r14, r14}, "ls, r14, r14", "ls_r14_r14"},
- {{ge, r0, r0}, "ge, r0, r0", "ge_r0_r0"},
- {{ge, r0, r1}, "ge, r0, r1", "ge_r0_r1"},
- {{ge, r0, r2}, "ge, r0, r2", "ge_r0_r2"},
- {{ge, r0, r3}, "ge, r0, r3", "ge_r0_r3"},
- {{ge, r0, r4}, "ge, r0, r4", "ge_r0_r4"},
- {{ge, r0, r5}, "ge, r0, r5", "ge_r0_r5"},
- {{ge, r0, r6}, "ge, r0, r6", "ge_r0_r6"},
- {{ge, r0, r7}, "ge, r0, r7", "ge_r0_r7"},
- {{ge, r0, r8}, "ge, r0, r8", "ge_r0_r8"},
- {{ge, r0, r9}, "ge, r0, r9", "ge_r0_r9"},
- {{ge, r0, r10}, "ge, r0, r10", "ge_r0_r10"},
- {{ge, r0, r11}, "ge, r0, r11", "ge_r0_r11"},
- {{ge, r0, r12}, "ge, r0, r12", "ge_r0_r12"},
- {{ge, r0, r13}, "ge, r0, r13", "ge_r0_r13"},
- {{ge, r0, r14}, "ge, r0, r14", "ge_r0_r14"},
- {{ge, r1, r0}, "ge, r1, r0", "ge_r1_r0"},
- {{ge, r1, r1}, "ge, r1, r1", "ge_r1_r1"},
- {{ge, r1, r2}, "ge, r1, r2", "ge_r1_r2"},
- {{ge, r1, r3}, "ge, r1, r3", "ge_r1_r3"},
- {{ge, r1, r4}, "ge, r1, r4", "ge_r1_r4"},
- {{ge, r1, r5}, "ge, r1, r5", "ge_r1_r5"},
- {{ge, r1, r6}, "ge, r1, r6", "ge_r1_r6"},
- {{ge, r1, r7}, "ge, r1, r7", "ge_r1_r7"},
- {{ge, r1, r8}, "ge, r1, r8", "ge_r1_r8"},
- {{ge, r1, r9}, "ge, r1, r9", "ge_r1_r9"},
- {{ge, r1, r10}, "ge, r1, r10", "ge_r1_r10"},
- {{ge, r1, r11}, "ge, r1, r11", "ge_r1_r11"},
- {{ge, r1, r12}, "ge, r1, r12", "ge_r1_r12"},
- {{ge, r1, r13}, "ge, r1, r13", "ge_r1_r13"},
- {{ge, r1, r14}, "ge, r1, r14", "ge_r1_r14"},
- {{ge, r2, r0}, "ge, r2, r0", "ge_r2_r0"},
- {{ge, r2, r1}, "ge, r2, r1", "ge_r2_r1"},
- {{ge, r2, r2}, "ge, r2, r2", "ge_r2_r2"},
- {{ge, r2, r3}, "ge, r2, r3", "ge_r2_r3"},
- {{ge, r2, r4}, "ge, r2, r4", "ge_r2_r4"},
- {{ge, r2, r5}, "ge, r2, r5", "ge_r2_r5"},
- {{ge, r2, r6}, "ge, r2, r6", "ge_r2_r6"},
- {{ge, r2, r7}, "ge, r2, r7", "ge_r2_r7"},
- {{ge, r2, r8}, "ge, r2, r8", "ge_r2_r8"},
- {{ge, r2, r9}, "ge, r2, r9", "ge_r2_r9"},
- {{ge, r2, r10}, "ge, r2, r10", "ge_r2_r10"},
- {{ge, r2, r11}, "ge, r2, r11", "ge_r2_r11"},
- {{ge, r2, r12}, "ge, r2, r12", "ge_r2_r12"},
- {{ge, r2, r13}, "ge, r2, r13", "ge_r2_r13"},
- {{ge, r2, r14}, "ge, r2, r14", "ge_r2_r14"},
- {{ge, r3, r0}, "ge, r3, r0", "ge_r3_r0"},
- {{ge, r3, r1}, "ge, r3, r1", "ge_r3_r1"},
- {{ge, r3, r2}, "ge, r3, r2", "ge_r3_r2"},
- {{ge, r3, r3}, "ge, r3, r3", "ge_r3_r3"},
- {{ge, r3, r4}, "ge, r3, r4", "ge_r3_r4"},
- {{ge, r3, r5}, "ge, r3, r5", "ge_r3_r5"},
- {{ge, r3, r6}, "ge, r3, r6", "ge_r3_r6"},
- {{ge, r3, r7}, "ge, r3, r7", "ge_r3_r7"},
- {{ge, r3, r8}, "ge, r3, r8", "ge_r3_r8"},
- {{ge, r3, r9}, "ge, r3, r9", "ge_r3_r9"},
- {{ge, r3, r10}, "ge, r3, r10", "ge_r3_r10"},
- {{ge, r3, r11}, "ge, r3, r11", "ge_r3_r11"},
- {{ge, r3, r12}, "ge, r3, r12", "ge_r3_r12"},
- {{ge, r3, r13}, "ge, r3, r13", "ge_r3_r13"},
- {{ge, r3, r14}, "ge, r3, r14", "ge_r3_r14"},
- {{ge, r4, r0}, "ge, r4, r0", "ge_r4_r0"},
- {{ge, r4, r1}, "ge, r4, r1", "ge_r4_r1"},
- {{ge, r4, r2}, "ge, r4, r2", "ge_r4_r2"},
- {{ge, r4, r3}, "ge, r4, r3", "ge_r4_r3"},
- {{ge, r4, r4}, "ge, r4, r4", "ge_r4_r4"},
- {{ge, r4, r5}, "ge, r4, r5", "ge_r4_r5"},
- {{ge, r4, r6}, "ge, r4, r6", "ge_r4_r6"},
- {{ge, r4, r7}, "ge, r4, r7", "ge_r4_r7"},
- {{ge, r4, r8}, "ge, r4, r8", "ge_r4_r8"},
- {{ge, r4, r9}, "ge, r4, r9", "ge_r4_r9"},
- {{ge, r4, r10}, "ge, r4, r10", "ge_r4_r10"},
- {{ge, r4, r11}, "ge, r4, r11", "ge_r4_r11"},
- {{ge, r4, r12}, "ge, r4, r12", "ge_r4_r12"},
- {{ge, r4, r13}, "ge, r4, r13", "ge_r4_r13"},
- {{ge, r4, r14}, "ge, r4, r14", "ge_r4_r14"},
- {{ge, r5, r0}, "ge, r5, r0", "ge_r5_r0"},
- {{ge, r5, r1}, "ge, r5, r1", "ge_r5_r1"},
- {{ge, r5, r2}, "ge, r5, r2", "ge_r5_r2"},
- {{ge, r5, r3}, "ge, r5, r3", "ge_r5_r3"},
- {{ge, r5, r4}, "ge, r5, r4", "ge_r5_r4"},
- {{ge, r5, r5}, "ge, r5, r5", "ge_r5_r5"},
- {{ge, r5, r6}, "ge, r5, r6", "ge_r5_r6"},
- {{ge, r5, r7}, "ge, r5, r7", "ge_r5_r7"},
- {{ge, r5, r8}, "ge, r5, r8", "ge_r5_r8"},
- {{ge, r5, r9}, "ge, r5, r9", "ge_r5_r9"},
- {{ge, r5, r10}, "ge, r5, r10", "ge_r5_r10"},
- {{ge, r5, r11}, "ge, r5, r11", "ge_r5_r11"},
- {{ge, r5, r12}, "ge, r5, r12", "ge_r5_r12"},
- {{ge, r5, r13}, "ge, r5, r13", "ge_r5_r13"},
- {{ge, r5, r14}, "ge, r5, r14", "ge_r5_r14"},
- {{ge, r6, r0}, "ge, r6, r0", "ge_r6_r0"},
- {{ge, r6, r1}, "ge, r6, r1", "ge_r6_r1"},
- {{ge, r6, r2}, "ge, r6, r2", "ge_r6_r2"},
- {{ge, r6, r3}, "ge, r6, r3", "ge_r6_r3"},
- {{ge, r6, r4}, "ge, r6, r4", "ge_r6_r4"},
- {{ge, r6, r5}, "ge, r6, r5", "ge_r6_r5"},
- {{ge, r6, r6}, "ge, r6, r6", "ge_r6_r6"},
- {{ge, r6, r7}, "ge, r6, r7", "ge_r6_r7"},
- {{ge, r6, r8}, "ge, r6, r8", "ge_r6_r8"},
- {{ge, r6, r9}, "ge, r6, r9", "ge_r6_r9"},
- {{ge, r6, r10}, "ge, r6, r10", "ge_r6_r10"},
- {{ge, r6, r11}, "ge, r6, r11", "ge_r6_r11"},
- {{ge, r6, r12}, "ge, r6, r12", "ge_r6_r12"},
- {{ge, r6, r13}, "ge, r6, r13", "ge_r6_r13"},
- {{ge, r6, r14}, "ge, r6, r14", "ge_r6_r14"},
- {{ge, r7, r0}, "ge, r7, r0", "ge_r7_r0"},
- {{ge, r7, r1}, "ge, r7, r1", "ge_r7_r1"},
- {{ge, r7, r2}, "ge, r7, r2", "ge_r7_r2"},
- {{ge, r7, r3}, "ge, r7, r3", "ge_r7_r3"},
- {{ge, r7, r4}, "ge, r7, r4", "ge_r7_r4"},
- {{ge, r7, r5}, "ge, r7, r5", "ge_r7_r5"},
- {{ge, r7, r6}, "ge, r7, r6", "ge_r7_r6"},
- {{ge, r7, r7}, "ge, r7, r7", "ge_r7_r7"},
- {{ge, r7, r8}, "ge, r7, r8", "ge_r7_r8"},
- {{ge, r7, r9}, "ge, r7, r9", "ge_r7_r9"},
- {{ge, r7, r10}, "ge, r7, r10", "ge_r7_r10"},
- {{ge, r7, r11}, "ge, r7, r11", "ge_r7_r11"},
- {{ge, r7, r12}, "ge, r7, r12", "ge_r7_r12"},
- {{ge, r7, r13}, "ge, r7, r13", "ge_r7_r13"},
- {{ge, r7, r14}, "ge, r7, r14", "ge_r7_r14"},
- {{ge, r8, r0}, "ge, r8, r0", "ge_r8_r0"},
- {{ge, r8, r1}, "ge, r8, r1", "ge_r8_r1"},
- {{ge, r8, r2}, "ge, r8, r2", "ge_r8_r2"},
- {{ge, r8, r3}, "ge, r8, r3", "ge_r8_r3"},
- {{ge, r8, r4}, "ge, r8, r4", "ge_r8_r4"},
- {{ge, r8, r5}, "ge, r8, r5", "ge_r8_r5"},
- {{ge, r8, r6}, "ge, r8, r6", "ge_r8_r6"},
- {{ge, r8, r7}, "ge, r8, r7", "ge_r8_r7"},
- {{ge, r8, r8}, "ge, r8, r8", "ge_r8_r8"},
- {{ge, r8, r9}, "ge, r8, r9", "ge_r8_r9"},
- {{ge, r8, r10}, "ge, r8, r10", "ge_r8_r10"},
- {{ge, r8, r11}, "ge, r8, r11", "ge_r8_r11"},
- {{ge, r8, r12}, "ge, r8, r12", "ge_r8_r12"},
- {{ge, r8, r13}, "ge, r8, r13", "ge_r8_r13"},
- {{ge, r8, r14}, "ge, r8, r14", "ge_r8_r14"},
- {{ge, r9, r0}, "ge, r9, r0", "ge_r9_r0"},
- {{ge, r9, r1}, "ge, r9, r1", "ge_r9_r1"},
- {{ge, r9, r2}, "ge, r9, r2", "ge_r9_r2"},
- {{ge, r9, r3}, "ge, r9, r3", "ge_r9_r3"},
- {{ge, r9, r4}, "ge, r9, r4", "ge_r9_r4"},
- {{ge, r9, r5}, "ge, r9, r5", "ge_r9_r5"},
- {{ge, r9, r6}, "ge, r9, r6", "ge_r9_r6"},
- {{ge, r9, r7}, "ge, r9, r7", "ge_r9_r7"},
- {{ge, r9, r8}, "ge, r9, r8", "ge_r9_r8"},
- {{ge, r9, r9}, "ge, r9, r9", "ge_r9_r9"},
- {{ge, r9, r10}, "ge, r9, r10", "ge_r9_r10"},
- {{ge, r9, r11}, "ge, r9, r11", "ge_r9_r11"},
- {{ge, r9, r12}, "ge, r9, r12", "ge_r9_r12"},
- {{ge, r9, r13}, "ge, r9, r13", "ge_r9_r13"},
- {{ge, r9, r14}, "ge, r9, r14", "ge_r9_r14"},
- {{ge, r10, r0}, "ge, r10, r0", "ge_r10_r0"},
- {{ge, r10, r1}, "ge, r10, r1", "ge_r10_r1"},
- {{ge, r10, r2}, "ge, r10, r2", "ge_r10_r2"},
- {{ge, r10, r3}, "ge, r10, r3", "ge_r10_r3"},
- {{ge, r10, r4}, "ge, r10, r4", "ge_r10_r4"},
- {{ge, r10, r5}, "ge, r10, r5", "ge_r10_r5"},
- {{ge, r10, r6}, "ge, r10, r6", "ge_r10_r6"},
- {{ge, r10, r7}, "ge, r10, r7", "ge_r10_r7"},
- {{ge, r10, r8}, "ge, r10, r8", "ge_r10_r8"},
- {{ge, r10, r9}, "ge, r10, r9", "ge_r10_r9"},
- {{ge, r10, r10}, "ge, r10, r10", "ge_r10_r10"},
- {{ge, r10, r11}, "ge, r10, r11", "ge_r10_r11"},
- {{ge, r10, r12}, "ge, r10, r12", "ge_r10_r12"},
- {{ge, r10, r13}, "ge, r10, r13", "ge_r10_r13"},
- {{ge, r10, r14}, "ge, r10, r14", "ge_r10_r14"},
- {{ge, r11, r0}, "ge, r11, r0", "ge_r11_r0"},
- {{ge, r11, r1}, "ge, r11, r1", "ge_r11_r1"},
- {{ge, r11, r2}, "ge, r11, r2", "ge_r11_r2"},
- {{ge, r11, r3}, "ge, r11, r3", "ge_r11_r3"},
- {{ge, r11, r4}, "ge, r11, r4", "ge_r11_r4"},
- {{ge, r11, r5}, "ge, r11, r5", "ge_r11_r5"},
- {{ge, r11, r6}, "ge, r11, r6", "ge_r11_r6"},
- {{ge, r11, r7}, "ge, r11, r7", "ge_r11_r7"},
- {{ge, r11, r8}, "ge, r11, r8", "ge_r11_r8"},
- {{ge, r11, r9}, "ge, r11, r9", "ge_r11_r9"},
- {{ge, r11, r10}, "ge, r11, r10", "ge_r11_r10"},
- {{ge, r11, r11}, "ge, r11, r11", "ge_r11_r11"},
- {{ge, r11, r12}, "ge, r11, r12", "ge_r11_r12"},
- {{ge, r11, r13}, "ge, r11, r13", "ge_r11_r13"},
- {{ge, r11, r14}, "ge, r11, r14", "ge_r11_r14"},
- {{ge, r12, r0}, "ge, r12, r0", "ge_r12_r0"},
- {{ge, r12, r1}, "ge, r12, r1", "ge_r12_r1"},
- {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"},
- {{ge, r12, r3}, "ge, r12, r3", "ge_r12_r3"},
- {{ge, r12, r4}, "ge, r12, r4", "ge_r12_r4"},
- {{ge, r12, r5}, "ge, r12, r5", "ge_r12_r5"},
- {{ge, r12, r6}, "ge, r12, r6", "ge_r12_r6"},
- {{ge, r12, r7}, "ge, r12, r7", "ge_r12_r7"},
- {{ge, r12, r8}, "ge, r12, r8", "ge_r12_r8"},
- {{ge, r12, r9}, "ge, r12, r9", "ge_r12_r9"},
- {{ge, r12, r10}, "ge, r12, r10", "ge_r12_r10"},
- {{ge, r12, r11}, "ge, r12, r11", "ge_r12_r11"},
- {{ge, r12, r12}, "ge, r12, r12", "ge_r12_r12"},
- {{ge, r12, r13}, "ge, r12, r13", "ge_r12_r13"},
- {{ge, r12, r14}, "ge, r12, r14", "ge_r12_r14"},
- {{ge, r13, r0}, "ge, r13, r0", "ge_r13_r0"},
- {{ge, r13, r1}, "ge, r13, r1", "ge_r13_r1"},
- {{ge, r13, r2}, "ge, r13, r2", "ge_r13_r2"},
- {{ge, r13, r3}, "ge, r13, r3", "ge_r13_r3"},
- {{ge, r13, r4}, "ge, r13, r4", "ge_r13_r4"},
- {{ge, r13, r5}, "ge, r13, r5", "ge_r13_r5"},
- {{ge, r13, r6}, "ge, r13, r6", "ge_r13_r6"},
- {{ge, r13, r7}, "ge, r13, r7", "ge_r13_r7"},
- {{ge, r13, r8}, "ge, r13, r8", "ge_r13_r8"},
- {{ge, r13, r9}, "ge, r13, r9", "ge_r13_r9"},
- {{ge, r13, r10}, "ge, r13, r10", "ge_r13_r10"},
- {{ge, r13, r11}, "ge, r13, r11", "ge_r13_r11"},
- {{ge, r13, r12}, "ge, r13, r12", "ge_r13_r12"},
- {{ge, r13, r13}, "ge, r13, r13", "ge_r13_r13"},
- {{ge, r13, r14}, "ge, r13, r14", "ge_r13_r14"},
- {{ge, r14, r0}, "ge, r14, r0", "ge_r14_r0"},
- {{ge, r14, r1}, "ge, r14, r1", "ge_r14_r1"},
- {{ge, r14, r2}, "ge, r14, r2", "ge_r14_r2"},
- {{ge, r14, r3}, "ge, r14, r3", "ge_r14_r3"},
- {{ge, r14, r4}, "ge, r14, r4", "ge_r14_r4"},
- {{ge, r14, r5}, "ge, r14, r5", "ge_r14_r5"},
- {{ge, r14, r6}, "ge, r14, r6", "ge_r14_r6"},
- {{ge, r14, r7}, "ge, r14, r7", "ge_r14_r7"},
- {{ge, r14, r8}, "ge, r14, r8", "ge_r14_r8"},
- {{ge, r14, r9}, "ge, r14, r9", "ge_r14_r9"},
- {{ge, r14, r10}, "ge, r14, r10", "ge_r14_r10"},
- {{ge, r14, r11}, "ge, r14, r11", "ge_r14_r11"},
- {{ge, r14, r12}, "ge, r14, r12", "ge_r14_r12"},
- {{ge, r14, r13}, "ge, r14, r13", "ge_r14_r13"},
- {{ge, r14, r14}, "ge, r14, r14", "ge_r14_r14"},
- {{lt, r0, r0}, "lt, r0, r0", "lt_r0_r0"},
- {{lt, r0, r1}, "lt, r0, r1", "lt_r0_r1"},
- {{lt, r0, r2}, "lt, r0, r2", "lt_r0_r2"},
- {{lt, r0, r3}, "lt, r0, r3", "lt_r0_r3"},
- {{lt, r0, r4}, "lt, r0, r4", "lt_r0_r4"},
- {{lt, r0, r5}, "lt, r0, r5", "lt_r0_r5"},
- {{lt, r0, r6}, "lt, r0, r6", "lt_r0_r6"},
- {{lt, r0, r7}, "lt, r0, r7", "lt_r0_r7"},
- {{lt, r0, r8}, "lt, r0, r8", "lt_r0_r8"},
- {{lt, r0, r9}, "lt, r0, r9", "lt_r0_r9"},
- {{lt, r0, r10}, "lt, r0, r10", "lt_r0_r10"},
- {{lt, r0, r11}, "lt, r0, r11", "lt_r0_r11"},
- {{lt, r0, r12}, "lt, r0, r12", "lt_r0_r12"},
- {{lt, r0, r13}, "lt, r0, r13", "lt_r0_r13"},
- {{lt, r0, r14}, "lt, r0, r14", "lt_r0_r14"},
- {{lt, r1, r0}, "lt, r1, r0", "lt_r1_r0"},
- {{lt, r1, r1}, "lt, r1, r1", "lt_r1_r1"},
- {{lt, r1, r2}, "lt, r1, r2", "lt_r1_r2"},
- {{lt, r1, r3}, "lt, r1, r3", "lt_r1_r3"},
- {{lt, r1, r4}, "lt, r1, r4", "lt_r1_r4"},
- {{lt, r1, r5}, "lt, r1, r5", "lt_r1_r5"},
- {{lt, r1, r6}, "lt, r1, r6", "lt_r1_r6"},
- {{lt, r1, r7}, "lt, r1, r7", "lt_r1_r7"},
- {{lt, r1, r8}, "lt, r1, r8", "lt_r1_r8"},
- {{lt, r1, r9}, "lt, r1, r9", "lt_r1_r9"},
- {{lt, r1, r10}, "lt, r1, r10", "lt_r1_r10"},
- {{lt, r1, r11}, "lt, r1, r11", "lt_r1_r11"},
- {{lt, r1, r12}, "lt, r1, r12", "lt_r1_r12"},
- {{lt, r1, r13}, "lt, r1, r13", "lt_r1_r13"},
- {{lt, r1, r14}, "lt, r1, r14", "lt_r1_r14"},
- {{lt, r2, r0}, "lt, r2, r0", "lt_r2_r0"},
- {{lt, r2, r1}, "lt, r2, r1", "lt_r2_r1"},
- {{lt, r2, r2}, "lt, r2, r2", "lt_r2_r2"},
- {{lt, r2, r3}, "lt, r2, r3", "lt_r2_r3"},
- {{lt, r2, r4}, "lt, r2, r4", "lt_r2_r4"},
- {{lt, r2, r5}, "lt, r2, r5", "lt_r2_r5"},
- {{lt, r2, r6}, "lt, r2, r6", "lt_r2_r6"},
- {{lt, r2, r7}, "lt, r2, r7", "lt_r2_r7"},
- {{lt, r2, r8}, "lt, r2, r8", "lt_r2_r8"},
- {{lt, r2, r9}, "lt, r2, r9", "lt_r2_r9"},
- {{lt, r2, r10}, "lt, r2, r10", "lt_r2_r10"},
- {{lt, r2, r11}, "lt, r2, r11", "lt_r2_r11"},
- {{lt, r2, r12}, "lt, r2, r12", "lt_r2_r12"},
- {{lt, r2, r13}, "lt, r2, r13", "lt_r2_r13"},
- {{lt, r2, r14}, "lt, r2, r14", "lt_r2_r14"},
- {{lt, r3, r0}, "lt, r3, r0", "lt_r3_r0"},
- {{lt, r3, r1}, "lt, r3, r1", "lt_r3_r1"},
- {{lt, r3, r2}, "lt, r3, r2", "lt_r3_r2"},
- {{lt, r3, r3}, "lt, r3, r3", "lt_r3_r3"},
- {{lt, r3, r4}, "lt, r3, r4", "lt_r3_r4"},
- {{lt, r3, r5}, "lt, r3, r5", "lt_r3_r5"},
- {{lt, r3, r6}, "lt, r3, r6", "lt_r3_r6"},
- {{lt, r3, r7}, "lt, r3, r7", "lt_r3_r7"},
- {{lt, r3, r8}, "lt, r3, r8", "lt_r3_r8"},
- {{lt, r3, r9}, "lt, r3, r9", "lt_r3_r9"},
- {{lt, r3, r10}, "lt, r3, r10", "lt_r3_r10"},
- {{lt, r3, r11}, "lt, r3, r11", "lt_r3_r11"},
- {{lt, r3, r12}, "lt, r3, r12", "lt_r3_r12"},
- {{lt, r3, r13}, "lt, r3, r13", "lt_r3_r13"},
- {{lt, r3, r14}, "lt, r3, r14", "lt_r3_r14"},
- {{lt, r4, r0}, "lt, r4, r0", "lt_r4_r0"},
- {{lt, r4, r1}, "lt, r4, r1", "lt_r4_r1"},
- {{lt, r4, r2}, "lt, r4, r2", "lt_r4_r2"},
- {{lt, r4, r3}, "lt, r4, r3", "lt_r4_r3"},
- {{lt, r4, r4}, "lt, r4, r4", "lt_r4_r4"},
- {{lt, r4, r5}, "lt, r4, r5", "lt_r4_r5"},
- {{lt, r4, r6}, "lt, r4, r6", "lt_r4_r6"},
- {{lt, r4, r7}, "lt, r4, r7", "lt_r4_r7"},
- {{lt, r4, r8}, "lt, r4, r8", "lt_r4_r8"},
- {{lt, r4, r9}, "lt, r4, r9", "lt_r4_r9"},
- {{lt, r4, r10}, "lt, r4, r10", "lt_r4_r10"},
- {{lt, r4, r11}, "lt, r4, r11", "lt_r4_r11"},
- {{lt, r4, r12}, "lt, r4, r12", "lt_r4_r12"},
- {{lt, r4, r13}, "lt, r4, r13", "lt_r4_r13"},
- {{lt, r4, r14}, "lt, r4, r14", "lt_r4_r14"},
- {{lt, r5, r0}, "lt, r5, r0", "lt_r5_r0"},
- {{lt, r5, r1}, "lt, r5, r1", "lt_r5_r1"},
- {{lt, r5, r2}, "lt, r5, r2", "lt_r5_r2"},
- {{lt, r5, r3}, "lt, r5, r3", "lt_r5_r3"},
- {{lt, r5, r4}, "lt, r5, r4", "lt_r5_r4"},
- {{lt, r5, r5}, "lt, r5, r5", "lt_r5_r5"},
- {{lt, r5, r6}, "lt, r5, r6", "lt_r5_r6"},
- {{lt, r5, r7}, "lt, r5, r7", "lt_r5_r7"},
- {{lt, r5, r8}, "lt, r5, r8", "lt_r5_r8"},
- {{lt, r5, r9}, "lt, r5, r9", "lt_r5_r9"},
- {{lt, r5, r10}, "lt, r5, r10", "lt_r5_r10"},
- {{lt, r5, r11}, "lt, r5, r11", "lt_r5_r11"},
- {{lt, r5, r12}, "lt, r5, r12", "lt_r5_r12"},
- {{lt, r5, r13}, "lt, r5, r13", "lt_r5_r13"},
- {{lt, r5, r14}, "lt, r5, r14", "lt_r5_r14"},
- {{lt, r6, r0}, "lt, r6, r0", "lt_r6_r0"},
- {{lt, r6, r1}, "lt, r6, r1", "lt_r6_r1"},
- {{lt, r6, r2}, "lt, r6, r2", "lt_r6_r2"},
- {{lt, r6, r3}, "lt, r6, r3", "lt_r6_r3"},
- {{lt, r6, r4}, "lt, r6, r4", "lt_r6_r4"},
- {{lt, r6, r5}, "lt, r6, r5", "lt_r6_r5"},
- {{lt, r6, r6}, "lt, r6, r6", "lt_r6_r6"},
- {{lt, r6, r7}, "lt, r6, r7", "lt_r6_r7"},
- {{lt, r6, r8}, "lt, r6, r8", "lt_r6_r8"},
- {{lt, r6, r9}, "lt, r6, r9", "lt_r6_r9"},
- {{lt, r6, r10}, "lt, r6, r10", "lt_r6_r10"},
- {{lt, r6, r11}, "lt, r6, r11", "lt_r6_r11"},
- {{lt, r6, r12}, "lt, r6, r12", "lt_r6_r12"},
- {{lt, r6, r13}, "lt, r6, r13", "lt_r6_r13"},
- {{lt, r6, r14}, "lt, r6, r14", "lt_r6_r14"},
- {{lt, r7, r0}, "lt, r7, r0", "lt_r7_r0"},
- {{lt, r7, r1}, "lt, r7, r1", "lt_r7_r1"},
- {{lt, r7, r2}, "lt, r7, r2", "lt_r7_r2"},
- {{lt, r7, r3}, "lt, r7, r3", "lt_r7_r3"},
- {{lt, r7, r4}, "lt, r7, r4", "lt_r7_r4"},
- {{lt, r7, r5}, "lt, r7, r5", "lt_r7_r5"},
- {{lt, r7, r6}, "lt, r7, r6", "lt_r7_r6"},
- {{lt, r7, r7}, "lt, r7, r7", "lt_r7_r7"},
- {{lt, r7, r8}, "lt, r7, r8", "lt_r7_r8"},
- {{lt, r7, r9}, "lt, r7, r9", "lt_r7_r9"},
- {{lt, r7, r10}, "lt, r7, r10", "lt_r7_r10"},
- {{lt, r7, r11}, "lt, r7, r11", "lt_r7_r11"},
- {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
- {{lt, r7, r13}, "lt, r7, r13", "lt_r7_r13"},
- {{lt, r7, r14}, "lt, r7, r14", "lt_r7_r14"},
- {{lt, r8, r0}, "lt, r8, r0", "lt_r8_r0"},
- {{lt, r8, r1}, "lt, r8, r1", "lt_r8_r1"},
- {{lt, r8, r2}, "lt, r8, r2", "lt_r8_r2"},
- {{lt, r8, r3}, "lt, r8, r3", "lt_r8_r3"},
- {{lt, r8, r4}, "lt, r8, r4", "lt_r8_r4"},
- {{lt, r8, r5}, "lt, r8, r5", "lt_r8_r5"},
- {{lt, r8, r6}, "lt, r8, r6", "lt_r8_r6"},
- {{lt, r8, r7}, "lt, r8, r7", "lt_r8_r7"},
- {{lt, r8, r8}, "lt, r8, r8", "lt_r8_r8"},
- {{lt, r8, r9}, "lt, r8, r9", "lt_r8_r9"},
- {{lt, r8, r10}, "lt, r8, r10", "lt_r8_r10"},
- {{lt, r8, r11}, "lt, r8, r11", "lt_r8_r11"},
- {{lt, r8, r12}, "lt, r8, r12", "lt_r8_r12"},
- {{lt, r8, r13}, "lt, r8, r13", "lt_r8_r13"},
- {{lt, r8, r14}, "lt, r8, r14", "lt_r8_r14"},
- {{lt, r9, r0}, "lt, r9, r0", "lt_r9_r0"},
- {{lt, r9, r1}, "lt, r9, r1", "lt_r9_r1"},
- {{lt, r9, r2}, "lt, r9, r2", "lt_r9_r2"},
- {{lt, r9, r3}, "lt, r9, r3", "lt_r9_r3"},
- {{lt, r9, r4}, "lt, r9, r4", "lt_r9_r4"},
- {{lt, r9, r5}, "lt, r9, r5", "lt_r9_r5"},
- {{lt, r9, r6}, "lt, r9, r6", "lt_r9_r6"},
- {{lt, r9, r7}, "lt, r9, r7", "lt_r9_r7"},
- {{lt, r9, r8}, "lt, r9, r8", "lt_r9_r8"},
- {{lt, r9, r9}, "lt, r9, r9", "lt_r9_r9"},
- {{lt, r9, r10}, "lt, r9, r10", "lt_r9_r10"},
- {{lt, r9, r11}, "lt, r9, r11", "lt_r9_r11"},
- {{lt, r9, r12}, "lt, r9, r12", "lt_r9_r12"},
- {{lt, r9, r13}, "lt, r9, r13", "lt_r9_r13"},
- {{lt, r9, r14}, "lt, r9, r14", "lt_r9_r14"},
- {{lt, r10, r0}, "lt, r10, r0", "lt_r10_r0"},
- {{lt, r10, r1}, "lt, r10, r1", "lt_r10_r1"},
- {{lt, r10, r2}, "lt, r10, r2", "lt_r10_r2"},
- {{lt, r10, r3}, "lt, r10, r3", "lt_r10_r3"},
- {{lt, r10, r4}, "lt, r10, r4", "lt_r10_r4"},
- {{lt, r10, r5}, "lt, r10, r5", "lt_r10_r5"},
- {{lt, r10, r6}, "lt, r10, r6", "lt_r10_r6"},
- {{lt, r10, r7}, "lt, r10, r7", "lt_r10_r7"},
- {{lt, r10, r8}, "lt, r10, r8", "lt_r10_r8"},
- {{lt, r10, r9}, "lt, r10, r9", "lt_r10_r9"},
- {{lt, r10, r10}, "lt, r10, r10", "lt_r10_r10"},
- {{lt, r10, r11}, "lt, r10, r11", "lt_r10_r11"},
- {{lt, r10, r12}, "lt, r10, r12", "lt_r10_r12"},
- {{lt, r10, r13}, "lt, r10, r13", "lt_r10_r13"},
- {{lt, r10, r14}, "lt, r10, r14", "lt_r10_r14"},
- {{lt, r11, r0}, "lt, r11, r0", "lt_r11_r0"},
- {{lt, r11, r1}, "lt, r11, r1", "lt_r11_r1"},
- {{lt, r11, r2}, "lt, r11, r2", "lt_r11_r2"},
- {{lt, r11, r3}, "lt, r11, r3", "lt_r11_r3"},
- {{lt, r11, r4}, "lt, r11, r4", "lt_r11_r4"},
- {{lt, r11, r5}, "lt, r11, r5", "lt_r11_r5"},
- {{lt, r11, r6}, "lt, r11, r6", "lt_r11_r6"},
- {{lt, r11, r7}, "lt, r11, r7", "lt_r11_r7"},
- {{lt, r11, r8}, "lt, r11, r8", "lt_r11_r8"},
- {{lt, r11, r9}, "lt, r11, r9", "lt_r11_r9"},
- {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
- {{lt, r11, r11}, "lt, r11, r11", "lt_r11_r11"},
- {{lt, r11, r12}, "lt, r11, r12", "lt_r11_r12"},
- {{lt, r11, r13}, "lt, r11, r13", "lt_r11_r13"},
- {{lt, r11, r14}, "lt, r11, r14", "lt_r11_r14"},
- {{lt, r12, r0}, "lt, r12, r0", "lt_r12_r0"},
- {{lt, r12, r1}, "lt, r12, r1", "lt_r12_r1"},
- {{lt, r12, r2}, "lt, r12, r2", "lt_r12_r2"},
- {{lt, r12, r3}, "lt, r12, r3", "lt_r12_r3"},
- {{lt, r12, r4}, "lt, r12, r4", "lt_r12_r4"},
- {{lt, r12, r5}, "lt, r12, r5", "lt_r12_r5"},
- {{lt, r12, r6}, "lt, r12, r6", "lt_r12_r6"},
- {{lt, r12, r7}, "lt, r12, r7", "lt_r12_r7"},
- {{lt, r12, r8}, "lt, r12, r8", "lt_r12_r8"},
- {{lt, r12, r9}, "lt, r12, r9", "lt_r12_r9"},
- {{lt, r12, r10}, "lt, r12, r10", "lt_r12_r10"},
- {{lt, r12, r11}, "lt, r12, r11", "lt_r12_r11"},
- {{lt, r12, r12}, "lt, r12, r12", "lt_r12_r12"},
- {{lt, r12, r13}, "lt, r12, r13", "lt_r12_r13"},
- {{lt, r12, r14}, "lt, r12, r14", "lt_r12_r14"},
- {{lt, r13, r0}, "lt, r13, r0", "lt_r13_r0"},
- {{lt, r13, r1}, "lt, r13, r1", "lt_r13_r1"},
- {{lt, r13, r2}, "lt, r13, r2", "lt_r13_r2"},
- {{lt, r13, r3}, "lt, r13, r3", "lt_r13_r3"},
- {{lt, r13, r4}, "lt, r13, r4", "lt_r13_r4"},
- {{lt, r13, r5}, "lt, r13, r5", "lt_r13_r5"},
- {{lt, r13, r6}, "lt, r13, r6", "lt_r13_r6"},
- {{lt, r13, r7}, "lt, r13, r7", "lt_r13_r7"},
- {{lt, r13, r8}, "lt, r13, r8", "lt_r13_r8"},
- {{lt, r13, r9}, "lt, r13, r9", "lt_r13_r9"},
- {{lt, r13, r10}, "lt, r13, r10", "lt_r13_r10"},
- {{lt, r13, r11}, "lt, r13, r11", "lt_r13_r11"},
{{lt, r13, r12}, "lt, r13, r12", "lt_r13_r12"},
- {{lt, r13, r13}, "lt, r13, r13", "lt_r13_r13"},
- {{lt, r13, r14}, "lt, r13, r14", "lt_r13_r14"},
- {{lt, r14, r0}, "lt, r14, r0", "lt_r14_r0"},
- {{lt, r14, r1}, "lt, r14, r1", "lt_r14_r1"},
- {{lt, r14, r2}, "lt, r14, r2", "lt_r14_r2"},
{{lt, r14, r3}, "lt, r14, r3", "lt_r14_r3"},
- {{lt, r14, r4}, "lt, r14, r4", "lt_r14_r4"},
- {{lt, r14, r5}, "lt, r14, r5", "lt_r14_r5"},
- {{lt, r14, r6}, "lt, r14, r6", "lt_r14_r6"},
- {{lt, r14, r7}, "lt, r14, r7", "lt_r14_r7"},
- {{lt, r14, r8}, "lt, r14, r8", "lt_r14_r8"},
- {{lt, r14, r9}, "lt, r14, r9", "lt_r14_r9"},
- {{lt, r14, r10}, "lt, r14, r10", "lt_r14_r10"},
- {{lt, r14, r11}, "lt, r14, r11", "lt_r14_r11"},
- {{lt, r14, r12}, "lt, r14, r12", "lt_r14_r12"},
- {{lt, r14, r13}, "lt, r14, r13", "lt_r14_r13"},
- {{lt, r14, r14}, "lt, r14, r14", "lt_r14_r14"},
- {{gt, r0, r0}, "gt, r0, r0", "gt_r0_r0"},
- {{gt, r0, r1}, "gt, r0, r1", "gt_r0_r1"},
- {{gt, r0, r2}, "gt, r0, r2", "gt_r0_r2"},
- {{gt, r0, r3}, "gt, r0, r3", "gt_r0_r3"},
- {{gt, r0, r4}, "gt, r0, r4", "gt_r0_r4"},
- {{gt, r0, r5}, "gt, r0, r5", "gt_r0_r5"},
- {{gt, r0, r6}, "gt, r0, r6", "gt_r0_r6"},
- {{gt, r0, r7}, "gt, r0, r7", "gt_r0_r7"},
- {{gt, r0, r8}, "gt, r0, r8", "gt_r0_r8"},
- {{gt, r0, r9}, "gt, r0, r9", "gt_r0_r9"},
- {{gt, r0, r10}, "gt, r0, r10", "gt_r0_r10"},
- {{gt, r0, r11}, "gt, r0, r11", "gt_r0_r11"},
- {{gt, r0, r12}, "gt, r0, r12", "gt_r0_r12"},
- {{gt, r0, r13}, "gt, r0, r13", "gt_r0_r13"},
- {{gt, r0, r14}, "gt, r0, r14", "gt_r0_r14"},
- {{gt, r1, r0}, "gt, r1, r0", "gt_r1_r0"},
- {{gt, r1, r1}, "gt, r1, r1", "gt_r1_r1"},
- {{gt, r1, r2}, "gt, r1, r2", "gt_r1_r2"},
- {{gt, r1, r3}, "gt, r1, r3", "gt_r1_r3"},
- {{gt, r1, r4}, "gt, r1, r4", "gt_r1_r4"},
- {{gt, r1, r5}, "gt, r1, r5", "gt_r1_r5"},
- {{gt, r1, r6}, "gt, r1, r6", "gt_r1_r6"},
- {{gt, r1, r7}, "gt, r1, r7", "gt_r1_r7"},
- {{gt, r1, r8}, "gt, r1, r8", "gt_r1_r8"},
- {{gt, r1, r9}, "gt, r1, r9", "gt_r1_r9"},
- {{gt, r1, r10}, "gt, r1, r10", "gt_r1_r10"},
- {{gt, r1, r11}, "gt, r1, r11", "gt_r1_r11"},
- {{gt, r1, r12}, "gt, r1, r12", "gt_r1_r12"},
- {{gt, r1, r13}, "gt, r1, r13", "gt_r1_r13"},
- {{gt, r1, r14}, "gt, r1, r14", "gt_r1_r14"},
- {{gt, r2, r0}, "gt, r2, r0", "gt_r2_r0"},
- {{gt, r2, r1}, "gt, r2, r1", "gt_r2_r1"},
- {{gt, r2, r2}, "gt, r2, r2", "gt_r2_r2"},
- {{gt, r2, r3}, "gt, r2, r3", "gt_r2_r3"},
- {{gt, r2, r4}, "gt, r2, r4", "gt_r2_r4"},
- {{gt, r2, r5}, "gt, r2, r5", "gt_r2_r5"},
- {{gt, r2, r6}, "gt, r2, r6", "gt_r2_r6"},
- {{gt, r2, r7}, "gt, r2, r7", "gt_r2_r7"},
- {{gt, r2, r8}, "gt, r2, r8", "gt_r2_r8"},
- {{gt, r2, r9}, "gt, r2, r9", "gt_r2_r9"},
- {{gt, r2, r10}, "gt, r2, r10", "gt_r2_r10"},
- {{gt, r2, r11}, "gt, r2, r11", "gt_r2_r11"},
- {{gt, r2, r12}, "gt, r2, r12", "gt_r2_r12"},
- {{gt, r2, r13}, "gt, r2, r13", "gt_r2_r13"},
- {{gt, r2, r14}, "gt, r2, r14", "gt_r2_r14"},
- {{gt, r3, r0}, "gt, r3, r0", "gt_r3_r0"},
- {{gt, r3, r1}, "gt, r3, r1", "gt_r3_r1"},
- {{gt, r3, r2}, "gt, r3, r2", "gt_r3_r2"},
- {{gt, r3, r3}, "gt, r3, r3", "gt_r3_r3"},
- {{gt, r3, r4}, "gt, r3, r4", "gt_r3_r4"},
- {{gt, r3, r5}, "gt, r3, r5", "gt_r3_r5"},
- {{gt, r3, r6}, "gt, r3, r6", "gt_r3_r6"},
- {{gt, r3, r7}, "gt, r3, r7", "gt_r3_r7"},
- {{gt, r3, r8}, "gt, r3, r8", "gt_r3_r8"},
- {{gt, r3, r9}, "gt, r3, r9", "gt_r3_r9"},
- {{gt, r3, r10}, "gt, r3, r10", "gt_r3_r10"},
- {{gt, r3, r11}, "gt, r3, r11", "gt_r3_r11"},
- {{gt, r3, r12}, "gt, r3, r12", "gt_r3_r12"},
- {{gt, r3, r13}, "gt, r3, r13", "gt_r3_r13"},
- {{gt, r3, r14}, "gt, r3, r14", "gt_r3_r14"},
- {{gt, r4, r0}, "gt, r4, r0", "gt_r4_r0"},
- {{gt, r4, r1}, "gt, r4, r1", "gt_r4_r1"},
- {{gt, r4, r2}, "gt, r4, r2", "gt_r4_r2"},
- {{gt, r4, r3}, "gt, r4, r3", "gt_r4_r3"},
- {{gt, r4, r4}, "gt, r4, r4", "gt_r4_r4"},
- {{gt, r4, r5}, "gt, r4, r5", "gt_r4_r5"},
- {{gt, r4, r6}, "gt, r4, r6", "gt_r4_r6"},
- {{gt, r4, r7}, "gt, r4, r7", "gt_r4_r7"},
- {{gt, r4, r8}, "gt, r4, r8", "gt_r4_r8"},
- {{gt, r4, r9}, "gt, r4, r9", "gt_r4_r9"},
- {{gt, r4, r10}, "gt, r4, r10", "gt_r4_r10"},
- {{gt, r4, r11}, "gt, r4, r11", "gt_r4_r11"},
- {{gt, r4, r12}, "gt, r4, r12", "gt_r4_r12"},
- {{gt, r4, r13}, "gt, r4, r13", "gt_r4_r13"},
- {{gt, r4, r14}, "gt, r4, r14", "gt_r4_r14"},
- {{gt, r5, r0}, "gt, r5, r0", "gt_r5_r0"},
- {{gt, r5, r1}, "gt, r5, r1", "gt_r5_r1"},
- {{gt, r5, r2}, "gt, r5, r2", "gt_r5_r2"},
- {{gt, r5, r3}, "gt, r5, r3", "gt_r5_r3"},
- {{gt, r5, r4}, "gt, r5, r4", "gt_r5_r4"},
- {{gt, r5, r5}, "gt, r5, r5", "gt_r5_r5"},
- {{gt, r5, r6}, "gt, r5, r6", "gt_r5_r6"},
- {{gt, r5, r7}, "gt, r5, r7", "gt_r5_r7"},
- {{gt, r5, r8}, "gt, r5, r8", "gt_r5_r8"},
- {{gt, r5, r9}, "gt, r5, r9", "gt_r5_r9"},
- {{gt, r5, r10}, "gt, r5, r10", "gt_r5_r10"},
- {{gt, r5, r11}, "gt, r5, r11", "gt_r5_r11"},
- {{gt, r5, r12}, "gt, r5, r12", "gt_r5_r12"},
- {{gt, r5, r13}, "gt, r5, r13", "gt_r5_r13"},
- {{gt, r5, r14}, "gt, r5, r14", "gt_r5_r14"},
- {{gt, r6, r0}, "gt, r6, r0", "gt_r6_r0"},
- {{gt, r6, r1}, "gt, r6, r1", "gt_r6_r1"},
- {{gt, r6, r2}, "gt, r6, r2", "gt_r6_r2"},
- {{gt, r6, r3}, "gt, r6, r3", "gt_r6_r3"},
- {{gt, r6, r4}, "gt, r6, r4", "gt_r6_r4"},
- {{gt, r6, r5}, "gt, r6, r5", "gt_r6_r5"},
- {{gt, r6, r6}, "gt, r6, r6", "gt_r6_r6"},
- {{gt, r6, r7}, "gt, r6, r7", "gt_r6_r7"},
- {{gt, r6, r8}, "gt, r6, r8", "gt_r6_r8"},
- {{gt, r6, r9}, "gt, r6, r9", "gt_r6_r9"},
- {{gt, r6, r10}, "gt, r6, r10", "gt_r6_r10"},
- {{gt, r6, r11}, "gt, r6, r11", "gt_r6_r11"},
- {{gt, r6, r12}, "gt, r6, r12", "gt_r6_r12"},
- {{gt, r6, r13}, "gt, r6, r13", "gt_r6_r13"},
- {{gt, r6, r14}, "gt, r6, r14", "gt_r6_r14"},
- {{gt, r7, r0}, "gt, r7, r0", "gt_r7_r0"},
- {{gt, r7, r1}, "gt, r7, r1", "gt_r7_r1"},
- {{gt, r7, r2}, "gt, r7, r2", "gt_r7_r2"},
- {{gt, r7, r3}, "gt, r7, r3", "gt_r7_r3"},
- {{gt, r7, r4}, "gt, r7, r4", "gt_r7_r4"},
- {{gt, r7, r5}, "gt, r7, r5", "gt_r7_r5"},
- {{gt, r7, r6}, "gt, r7, r6", "gt_r7_r6"},
- {{gt, r7, r7}, "gt, r7, r7", "gt_r7_r7"},
- {{gt, r7, r8}, "gt, r7, r8", "gt_r7_r8"},
- {{gt, r7, r9}, "gt, r7, r9", "gt_r7_r9"},
- {{gt, r7, r10}, "gt, r7, r10", "gt_r7_r10"},
- {{gt, r7, r11}, "gt, r7, r11", "gt_r7_r11"},
- {{gt, r7, r12}, "gt, r7, r12", "gt_r7_r12"},
- {{gt, r7, r13}, "gt, r7, r13", "gt_r7_r13"},
- {{gt, r7, r14}, "gt, r7, r14", "gt_r7_r14"},
- {{gt, r8, r0}, "gt, r8, r0", "gt_r8_r0"},
- {{gt, r8, r1}, "gt, r8, r1", "gt_r8_r1"},
- {{gt, r8, r2}, "gt, r8, r2", "gt_r8_r2"},
- {{gt, r8, r3}, "gt, r8, r3", "gt_r8_r3"},
- {{gt, r8, r4}, "gt, r8, r4", "gt_r8_r4"},
- {{gt, r8, r5}, "gt, r8, r5", "gt_r8_r5"},
- {{gt, r8, r6}, "gt, r8, r6", "gt_r8_r6"},
- {{gt, r8, r7}, "gt, r8, r7", "gt_r8_r7"},
- {{gt, r8, r8}, "gt, r8, r8", "gt_r8_r8"},
- {{gt, r8, r9}, "gt, r8, r9", "gt_r8_r9"},
- {{gt, r8, r10}, "gt, r8, r10", "gt_r8_r10"},
- {{gt, r8, r11}, "gt, r8, r11", "gt_r8_r11"},
- {{gt, r8, r12}, "gt, r8, r12", "gt_r8_r12"},
- {{gt, r8, r13}, "gt, r8, r13", "gt_r8_r13"},
- {{gt, r8, r14}, "gt, r8, r14", "gt_r8_r14"},
- {{gt, r9, r0}, "gt, r9, r0", "gt_r9_r0"},
- {{gt, r9, r1}, "gt, r9, r1", "gt_r9_r1"},
- {{gt, r9, r2}, "gt, r9, r2", "gt_r9_r2"},
- {{gt, r9, r3}, "gt, r9, r3", "gt_r9_r3"},
- {{gt, r9, r4}, "gt, r9, r4", "gt_r9_r4"},
- {{gt, r9, r5}, "gt, r9, r5", "gt_r9_r5"},
- {{gt, r9, r6}, "gt, r9, r6", "gt_r9_r6"},
- {{gt, r9, r7}, "gt, r9, r7", "gt_r9_r7"},
- {{gt, r9, r8}, "gt, r9, r8", "gt_r9_r8"},
- {{gt, r9, r9}, "gt, r9, r9", "gt_r9_r9"},
- {{gt, r9, r10}, "gt, r9, r10", "gt_r9_r10"},
- {{gt, r9, r11}, "gt, r9, r11", "gt_r9_r11"},
- {{gt, r9, r12}, "gt, r9, r12", "gt_r9_r12"},
- {{gt, r9, r13}, "gt, r9, r13", "gt_r9_r13"},
- {{gt, r9, r14}, "gt, r9, r14", "gt_r9_r14"},
- {{gt, r10, r0}, "gt, r10, r0", "gt_r10_r0"},
- {{gt, r10, r1}, "gt, r10, r1", "gt_r10_r1"},
- {{gt, r10, r2}, "gt, r10, r2", "gt_r10_r2"},
- {{gt, r10, r3}, "gt, r10, r3", "gt_r10_r3"},
- {{gt, r10, r4}, "gt, r10, r4", "gt_r10_r4"},
- {{gt, r10, r5}, "gt, r10, r5", "gt_r10_r5"},
- {{gt, r10, r6}, "gt, r10, r6", "gt_r10_r6"},
- {{gt, r10, r7}, "gt, r10, r7", "gt_r10_r7"},
- {{gt, r10, r8}, "gt, r10, r8", "gt_r10_r8"},
+ {{mi, r12, r14}, "mi, r12, r14", "mi_r12_r14"},
+ {{vs, r11, r2}, "vs, r11, r2", "vs_r11_r2"},
+ {{ls, r11, r0}, "ls, r11, r0", "ls_r11_r0"},
{{gt, r10, r9}, "gt, r10, r9", "gt_r10_r9"},
- {{gt, r10, r10}, "gt, r10, r10", "gt_r10_r10"},
- {{gt, r10, r11}, "gt, r10, r11", "gt_r10_r11"},
- {{gt, r10, r12}, "gt, r10, r12", "gt_r10_r12"},
- {{gt, r10, r13}, "gt, r10, r13", "gt_r10_r13"},
- {{gt, r10, r14}, "gt, r10, r14", "gt_r10_r14"},
- {{gt, r11, r0}, "gt, r11, r0", "gt_r11_r0"},
- {{gt, r11, r1}, "gt, r11, r1", "gt_r11_r1"},
- {{gt, r11, r2}, "gt, r11, r2", "gt_r11_r2"},
- {{gt, r11, r3}, "gt, r11, r3", "gt_r11_r3"},
- {{gt, r11, r4}, "gt, r11, r4", "gt_r11_r4"},
- {{gt, r11, r5}, "gt, r11, r5", "gt_r11_r5"},
- {{gt, r11, r6}, "gt, r11, r6", "gt_r11_r6"},
- {{gt, r11, r7}, "gt, r11, r7", "gt_r11_r7"},
- {{gt, r11, r8}, "gt, r11, r8", "gt_r11_r8"},
- {{gt, r11, r9}, "gt, r11, r9", "gt_r11_r9"},
- {{gt, r11, r10}, "gt, r11, r10", "gt_r11_r10"},
- {{gt, r11, r11}, "gt, r11, r11", "gt_r11_r11"},
- {{gt, r11, r12}, "gt, r11, r12", "gt_r11_r12"},
- {{gt, r11, r13}, "gt, r11, r13", "gt_r11_r13"},
- {{gt, r11, r14}, "gt, r11, r14", "gt_r11_r14"},
- {{gt, r12, r0}, "gt, r12, r0", "gt_r12_r0"},
- {{gt, r12, r1}, "gt, r12, r1", "gt_r12_r1"},
- {{gt, r12, r2}, "gt, r12, r2", "gt_r12_r2"},
- {{gt, r12, r3}, "gt, r12, r3", "gt_r12_r3"},
- {{gt, r12, r4}, "gt, r12, r4", "gt_r12_r4"},
- {{gt, r12, r5}, "gt, r12, r5", "gt_r12_r5"},
- {{gt, r12, r6}, "gt, r12, r6", "gt_r12_r6"},
- {{gt, r12, r7}, "gt, r12, r7", "gt_r12_r7"},
- {{gt, r12, r8}, "gt, r12, r8", "gt_r12_r8"},
- {{gt, r12, r9}, "gt, r12, r9", "gt_r12_r9"},
- {{gt, r12, r10}, "gt, r12, r10", "gt_r12_r10"},
- {{gt, r12, r11}, "gt, r12, r11", "gt_r12_r11"},
- {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
- {{gt, r12, r13}, "gt, r12, r13", "gt_r12_r13"},
- {{gt, r12, r14}, "gt, r12, r14", "gt_r12_r14"},
- {{gt, r13, r0}, "gt, r13, r0", "gt_r13_r0"},
- {{gt, r13, r1}, "gt, r13, r1", "gt_r13_r1"},
- {{gt, r13, r2}, "gt, r13, r2", "gt_r13_r2"},
- {{gt, r13, r3}, "gt, r13, r3", "gt_r13_r3"},
- {{gt, r13, r4}, "gt, r13, r4", "gt_r13_r4"},
- {{gt, r13, r5}, "gt, r13, r5", "gt_r13_r5"},
- {{gt, r13, r6}, "gt, r13, r6", "gt_r13_r6"},
- {{gt, r13, r7}, "gt, r13, r7", "gt_r13_r7"},
- {{gt, r13, r8}, "gt, r13, r8", "gt_r13_r8"},
- {{gt, r13, r9}, "gt, r13, r9", "gt_r13_r9"},
- {{gt, r13, r10}, "gt, r13, r10", "gt_r13_r10"},
- {{gt, r13, r11}, "gt, r13, r11", "gt_r13_r11"},
- {{gt, r13, r12}, "gt, r13, r12", "gt_r13_r12"},
- {{gt, r13, r13}, "gt, r13, r13", "gt_r13_r13"},
- {{gt, r13, r14}, "gt, r13, r14", "gt_r13_r14"},
- {{gt, r14, r0}, "gt, r14, r0", "gt_r14_r0"},
- {{gt, r14, r1}, "gt, r14, r1", "gt_r14_r1"},
- {{gt, r14, r2}, "gt, r14, r2", "gt_r14_r2"},
- {{gt, r14, r3}, "gt, r14, r3", "gt_r14_r3"},
- {{gt, r14, r4}, "gt, r14, r4", "gt_r14_r4"},
- {{gt, r14, r5}, "gt, r14, r5", "gt_r14_r5"},
- {{gt, r14, r6}, "gt, r14, r6", "gt_r14_r6"},
- {{gt, r14, r7}, "gt, r14, r7", "gt_r14_r7"},
- {{gt, r14, r8}, "gt, r14, r8", "gt_r14_r8"},
- {{gt, r14, r9}, "gt, r14, r9", "gt_r14_r9"},
- {{gt, r14, r10}, "gt, r14, r10", "gt_r14_r10"},
- {{gt, r14, r11}, "gt, r14, r11", "gt_r14_r11"},
- {{gt, r14, r12}, "gt, r14, r12", "gt_r14_r12"},
- {{gt, r14, r13}, "gt, r14, r13", "gt_r14_r13"},
- {{gt, r14, r14}, "gt, r14, r14", "gt_r14_r14"},
- {{le, r0, r0}, "le, r0, r0", "le_r0_r0"},
- {{le, r0, r1}, "le, r0, r1", "le_r0_r1"},
- {{le, r0, r2}, "le, r0, r2", "le_r0_r2"},
- {{le, r0, r3}, "le, r0, r3", "le_r0_r3"},
- {{le, r0, r4}, "le, r0, r4", "le_r0_r4"},
- {{le, r0, r5}, "le, r0, r5", "le_r0_r5"},
- {{le, r0, r6}, "le, r0, r6", "le_r0_r6"},
- {{le, r0, r7}, "le, r0, r7", "le_r0_r7"},
- {{le, r0, r8}, "le, r0, r8", "le_r0_r8"},
- {{le, r0, r9}, "le, r0, r9", "le_r0_r9"},
- {{le, r0, r10}, "le, r0, r10", "le_r0_r10"},
- {{le, r0, r11}, "le, r0, r11", "le_r0_r11"},
- {{le, r0, r12}, "le, r0, r12", "le_r0_r12"},
- {{le, r0, r13}, "le, r0, r13", "le_r0_r13"},
- {{le, r0, r14}, "le, r0, r14", "le_r0_r14"},
- {{le, r1, r0}, "le, r1, r0", "le_r1_r0"},
- {{le, r1, r1}, "le, r1, r1", "le_r1_r1"},
- {{le, r1, r2}, "le, r1, r2", "le_r1_r2"},
- {{le, r1, r3}, "le, r1, r3", "le_r1_r3"},
- {{le, r1, r4}, "le, r1, r4", "le_r1_r4"},
- {{le, r1, r5}, "le, r1, r5", "le_r1_r5"},
- {{le, r1, r6}, "le, r1, r6", "le_r1_r6"},
- {{le, r1, r7}, "le, r1, r7", "le_r1_r7"},
- {{le, r1, r8}, "le, r1, r8", "le_r1_r8"},
- {{le, r1, r9}, "le, r1, r9", "le_r1_r9"},
- {{le, r1, r10}, "le, r1, r10", "le_r1_r10"},
- {{le, r1, r11}, "le, r1, r11", "le_r1_r11"},
- {{le, r1, r12}, "le, r1, r12", "le_r1_r12"},
- {{le, r1, r13}, "le, r1, r13", "le_r1_r13"},
- {{le, r1, r14}, "le, r1, r14", "le_r1_r14"},
- {{le, r2, r0}, "le, r2, r0", "le_r2_r0"},
- {{le, r2, r1}, "le, r2, r1", "le_r2_r1"},
- {{le, r2, r2}, "le, r2, r2", "le_r2_r2"},
- {{le, r2, r3}, "le, r2, r3", "le_r2_r3"},
- {{le, r2, r4}, "le, r2, r4", "le_r2_r4"},
- {{le, r2, r5}, "le, r2, r5", "le_r2_r5"},
- {{le, r2, r6}, "le, r2, r6", "le_r2_r6"},
- {{le, r2, r7}, "le, r2, r7", "le_r2_r7"},
- {{le, r2, r8}, "le, r2, r8", "le_r2_r8"},
- {{le, r2, r9}, "le, r2, r9", "le_r2_r9"},
- {{le, r2, r10}, "le, r2, r10", "le_r2_r10"},
- {{le, r2, r11}, "le, r2, r11", "le_r2_r11"},
- {{le, r2, r12}, "le, r2, r12", "le_r2_r12"},
- {{le, r2, r13}, "le, r2, r13", "le_r2_r13"},
- {{le, r2, r14}, "le, r2, r14", "le_r2_r14"},
- {{le, r3, r0}, "le, r3, r0", "le_r3_r0"},
- {{le, r3, r1}, "le, r3, r1", "le_r3_r1"},
- {{le, r3, r2}, "le, r3, r2", "le_r3_r2"},
- {{le, r3, r3}, "le, r3, r3", "le_r3_r3"},
- {{le, r3, r4}, "le, r3, r4", "le_r3_r4"},
- {{le, r3, r5}, "le, r3, r5", "le_r3_r5"},
- {{le, r3, r6}, "le, r3, r6", "le_r3_r6"},
- {{le, r3, r7}, "le, r3, r7", "le_r3_r7"},
- {{le, r3, r8}, "le, r3, r8", "le_r3_r8"},
- {{le, r3, r9}, "le, r3, r9", "le_r3_r9"},
- {{le, r3, r10}, "le, r3, r10", "le_r3_r10"},
- {{le, r3, r11}, "le, r3, r11", "le_r3_r11"},
- {{le, r3, r12}, "le, r3, r12", "le_r3_r12"},
- {{le, r3, r13}, "le, r3, r13", "le_r3_r13"},
- {{le, r3, r14}, "le, r3, r14", "le_r3_r14"},
- {{le, r4, r0}, "le, r4, r0", "le_r4_r0"},
- {{le, r4, r1}, "le, r4, r1", "le_r4_r1"},
- {{le, r4, r2}, "le, r4, r2", "le_r4_r2"},
- {{le, r4, r3}, "le, r4, r3", "le_r4_r3"},
- {{le, r4, r4}, "le, r4, r4", "le_r4_r4"},
- {{le, r4, r5}, "le, r4, r5", "le_r4_r5"},
- {{le, r4, r6}, "le, r4, r6", "le_r4_r6"},
- {{le, r4, r7}, "le, r4, r7", "le_r4_r7"},
- {{le, r4, r8}, "le, r4, r8", "le_r4_r8"},
- {{le, r4, r9}, "le, r4, r9", "le_r4_r9"},
- {{le, r4, r10}, "le, r4, r10", "le_r4_r10"},
- {{le, r4, r11}, "le, r4, r11", "le_r4_r11"},
- {{le, r4, r12}, "le, r4, r12", "le_r4_r12"},
- {{le, r4, r13}, "le, r4, r13", "le_r4_r13"},
- {{le, r4, r14}, "le, r4, r14", "le_r4_r14"},
- {{le, r5, r0}, "le, r5, r0", "le_r5_r0"},
- {{le, r5, r1}, "le, r5, r1", "le_r5_r1"},
- {{le, r5, r2}, "le, r5, r2", "le_r5_r2"},
- {{le, r5, r3}, "le, r5, r3", "le_r5_r3"},
- {{le, r5, r4}, "le, r5, r4", "le_r5_r4"},
- {{le, r5, r5}, "le, r5, r5", "le_r5_r5"},
- {{le, r5, r6}, "le, r5, r6", "le_r5_r6"},
- {{le, r5, r7}, "le, r5, r7", "le_r5_r7"},
- {{le, r5, r8}, "le, r5, r8", "le_r5_r8"},
- {{le, r5, r9}, "le, r5, r9", "le_r5_r9"},
- {{le, r5, r10}, "le, r5, r10", "le_r5_r10"},
- {{le, r5, r11}, "le, r5, r11", "le_r5_r11"},
- {{le, r5, r12}, "le, r5, r12", "le_r5_r12"},
- {{le, r5, r13}, "le, r5, r13", "le_r5_r13"},
- {{le, r5, r14}, "le, r5, r14", "le_r5_r14"},
- {{le, r6, r0}, "le, r6, r0", "le_r6_r0"},
- {{le, r6, r1}, "le, r6, r1", "le_r6_r1"},
- {{le, r6, r2}, "le, r6, r2", "le_r6_r2"},
- {{le, r6, r3}, "le, r6, r3", "le_r6_r3"},
- {{le, r6, r4}, "le, r6, r4", "le_r6_r4"},
- {{le, r6, r5}, "le, r6, r5", "le_r6_r5"},
- {{le, r6, r6}, "le, r6, r6", "le_r6_r6"},
- {{le, r6, r7}, "le, r6, r7", "le_r6_r7"},
- {{le, r6, r8}, "le, r6, r8", "le_r6_r8"},
- {{le, r6, r9}, "le, r6, r9", "le_r6_r9"},
- {{le, r6, r10}, "le, r6, r10", "le_r6_r10"},
- {{le, r6, r11}, "le, r6, r11", "le_r6_r11"},
- {{le, r6, r12}, "le, r6, r12", "le_r6_r12"},
- {{le, r6, r13}, "le, r6, r13", "le_r6_r13"},
- {{le, r6, r14}, "le, r6, r14", "le_r6_r14"},
- {{le, r7, r0}, "le, r7, r0", "le_r7_r0"},
- {{le, r7, r1}, "le, r7, r1", "le_r7_r1"},
- {{le, r7, r2}, "le, r7, r2", "le_r7_r2"},
- {{le, r7, r3}, "le, r7, r3", "le_r7_r3"},
- {{le, r7, r4}, "le, r7, r4", "le_r7_r4"},
- {{le, r7, r5}, "le, r7, r5", "le_r7_r5"},
- {{le, r7, r6}, "le, r7, r6", "le_r7_r6"},
- {{le, r7, r7}, "le, r7, r7", "le_r7_r7"},
- {{le, r7, r8}, "le, r7, r8", "le_r7_r8"},
- {{le, r7, r9}, "le, r7, r9", "le_r7_r9"},
- {{le, r7, r10}, "le, r7, r10", "le_r7_r10"},
- {{le, r7, r11}, "le, r7, r11", "le_r7_r11"},
- {{le, r7, r12}, "le, r7, r12", "le_r7_r12"},
- {{le, r7, r13}, "le, r7, r13", "le_r7_r13"},
- {{le, r7, r14}, "le, r7, r14", "le_r7_r14"},
- {{le, r8, r0}, "le, r8, r0", "le_r8_r0"},
- {{le, r8, r1}, "le, r8, r1", "le_r8_r1"},
- {{le, r8, r2}, "le, r8, r2", "le_r8_r2"},
- {{le, r8, r3}, "le, r8, r3", "le_r8_r3"},
- {{le, r8, r4}, "le, r8, r4", "le_r8_r4"},
- {{le, r8, r5}, "le, r8, r5", "le_r8_r5"},
- {{le, r8, r6}, "le, r8, r6", "le_r8_r6"},
- {{le, r8, r7}, "le, r8, r7", "le_r8_r7"},
- {{le, r8, r8}, "le, r8, r8", "le_r8_r8"},
- {{le, r8, r9}, "le, r8, r9", "le_r8_r9"},
- {{le, r8, r10}, "le, r8, r10", "le_r8_r10"},
- {{le, r8, r11}, "le, r8, r11", "le_r8_r11"},
- {{le, r8, r12}, "le, r8, r12", "le_r8_r12"},
- {{le, r8, r13}, "le, r8, r13", "le_r8_r13"},
- {{le, r8, r14}, "le, r8, r14", "le_r8_r14"},
- {{le, r9, r0}, "le, r9, r0", "le_r9_r0"},
- {{le, r9, r1}, "le, r9, r1", "le_r9_r1"},
- {{le, r9, r2}, "le, r9, r2", "le_r9_r2"},
- {{le, r9, r3}, "le, r9, r3", "le_r9_r3"},
- {{le, r9, r4}, "le, r9, r4", "le_r9_r4"},
- {{le, r9, r5}, "le, r9, r5", "le_r9_r5"},
- {{le, r9, r6}, "le, r9, r6", "le_r9_r6"},
- {{le, r9, r7}, "le, r9, r7", "le_r9_r7"},
- {{le, r9, r8}, "le, r9, r8", "le_r9_r8"},
- {{le, r9, r9}, "le, r9, r9", "le_r9_r9"},
- {{le, r9, r10}, "le, r9, r10", "le_r9_r10"},
- {{le, r9, r11}, "le, r9, r11", "le_r9_r11"},
- {{le, r9, r12}, "le, r9, r12", "le_r9_r12"},
- {{le, r9, r13}, "le, r9, r13", "le_r9_r13"},
- {{le, r9, r14}, "le, r9, r14", "le_r9_r14"},
- {{le, r10, r0}, "le, r10, r0", "le_r10_r0"},
- {{le, r10, r1}, "le, r10, r1", "le_r10_r1"},
- {{le, r10, r2}, "le, r10, r2", "le_r10_r2"},
- {{le, r10, r3}, "le, r10, r3", "le_r10_r3"},
- {{le, r10, r4}, "le, r10, r4", "le_r10_r4"},
- {{le, r10, r5}, "le, r10, r5", "le_r10_r5"},
- {{le, r10, r6}, "le, r10, r6", "le_r10_r6"},
- {{le, r10, r7}, "le, r10, r7", "le_r10_r7"},
- {{le, r10, r8}, "le, r10, r8", "le_r10_r8"},
- {{le, r10, r9}, "le, r10, r9", "le_r10_r9"},
- {{le, r10, r10}, "le, r10, r10", "le_r10_r10"},
- {{le, r10, r11}, "le, r10, r11", "le_r10_r11"},
{{le, r10, r12}, "le, r10, r12", "le_r10_r12"},
- {{le, r10, r13}, "le, r10, r13", "le_r10_r13"},
- {{le, r10, r14}, "le, r10, r14", "le_r10_r14"},
- {{le, r11, r0}, "le, r11, r0", "le_r11_r0"},
- {{le, r11, r1}, "le, r11, r1", "le_r11_r1"},
- {{le, r11, r2}, "le, r11, r2", "le_r11_r2"},
- {{le, r11, r3}, "le, r11, r3", "le_r11_r3"},
- {{le, r11, r4}, "le, r11, r4", "le_r11_r4"},
- {{le, r11, r5}, "le, r11, r5", "le_r11_r5"},
- {{le, r11, r6}, "le, r11, r6", "le_r11_r6"},
- {{le, r11, r7}, "le, r11, r7", "le_r11_r7"},
- {{le, r11, r8}, "le, r11, r8", "le_r11_r8"},
- {{le, r11, r9}, "le, r11, r9", "le_r11_r9"},
- {{le, r11, r10}, "le, r11, r10", "le_r11_r10"},
- {{le, r11, r11}, "le, r11, r11", "le_r11_r11"},
- {{le, r11, r12}, "le, r11, r12", "le_r11_r12"},
- {{le, r11, r13}, "le, r11, r13", "le_r11_r13"},
- {{le, r11, r14}, "le, r11, r14", "le_r11_r14"},
- {{le, r12, r0}, "le, r12, r0", "le_r12_r0"},
- {{le, r12, r1}, "le, r12, r1", "le_r12_r1"},
- {{le, r12, r2}, "le, r12, r2", "le_r12_r2"},
- {{le, r12, r3}, "le, r12, r3", "le_r12_r3"},
- {{le, r12, r4}, "le, r12, r4", "le_r12_r4"},
- {{le, r12, r5}, "le, r12, r5", "le_r12_r5"},
- {{le, r12, r6}, "le, r12, r6", "le_r12_r6"},
- {{le, r12, r7}, "le, r12, r7", "le_r12_r7"},
- {{le, r12, r8}, "le, r12, r8", "le_r12_r8"},
- {{le, r12, r9}, "le, r12, r9", "le_r12_r9"},
- {{le, r12, r10}, "le, r12, r10", "le_r12_r10"},
- {{le, r12, r11}, "le, r12, r11", "le_r12_r11"},
- {{le, r12, r12}, "le, r12, r12", "le_r12_r12"},
- {{le, r12, r13}, "le, r12, r13", "le_r12_r13"},
- {{le, r12, r14}, "le, r12, r14", "le_r12_r14"},
- {{le, r13, r0}, "le, r13, r0", "le_r13_r0"},
- {{le, r13, r1}, "le, r13, r1", "le_r13_r1"},
- {{le, r13, r2}, "le, r13, r2", "le_r13_r2"},
- {{le, r13, r3}, "le, r13, r3", "le_r13_r3"},
- {{le, r13, r4}, "le, r13, r4", "le_r13_r4"},
- {{le, r13, r5}, "le, r13, r5", "le_r13_r5"},
- {{le, r13, r6}, "le, r13, r6", "le_r13_r6"},
- {{le, r13, r7}, "le, r13, r7", "le_r13_r7"},
- {{le, r13, r8}, "le, r13, r8", "le_r13_r8"},
- {{le, r13, r9}, "le, r13, r9", "le_r13_r9"},
- {{le, r13, r10}, "le, r13, r10", "le_r13_r10"},
- {{le, r13, r11}, "le, r13, r11", "le_r13_r11"},
- {{le, r13, r12}, "le, r13, r12", "le_r13_r12"},
- {{le, r13, r13}, "le, r13, r13", "le_r13_r13"},
- {{le, r13, r14}, "le, r13, r14", "le_r13_r14"},
- {{le, r14, r0}, "le, r14, r0", "le_r14_r0"},
- {{le, r14, r1}, "le, r14, r1", "le_r14_r1"},
- {{le, r14, r2}, "le, r14, r2", "le_r14_r2"},
- {{le, r14, r3}, "le, r14, r3", "le_r14_r3"},
- {{le, r14, r4}, "le, r14, r4", "le_r14_r4"},
- {{le, r14, r5}, "le, r14, r5", "le_r14_r5"},
- {{le, r14, r6}, "le, r14, r6", "le_r14_r6"},
- {{le, r14, r7}, "le, r14, r7", "le_r14_r7"},
- {{le, r14, r8}, "le, r14, r8", "le_r14_r8"},
- {{le, r14, r9}, "le, r14, r9", "le_r14_r9"},
- {{le, r14, r10}, "le, r14, r10", "le_r14_r10"},
- {{le, r14, r11}, "le, r14, r11", "le_r14_r11"},
- {{le, r14, r12}, "le, r14, r12", "le_r14_r12"},
- {{le, r14, r13}, "le, r14, r13", "le_r14_r13"},
- {{le, r14, r14}, "le, r14, r14", "le_r14_r14"},
- {{al, r0, r0}, "al, r0, r0", "al_r0_r0"},
- {{al, r0, r1}, "al, r0, r1", "al_r0_r1"},
- {{al, r0, r2}, "al, r0, r2", "al_r0_r2"},
- {{al, r0, r3}, "al, r0, r3", "al_r0_r3"},
- {{al, r0, r4}, "al, r0, r4", "al_r0_r4"},
- {{al, r0, r5}, "al, r0, r5", "al_r0_r5"},
- {{al, r0, r6}, "al, r0, r6", "al_r0_r6"},
- {{al, r0, r7}, "al, r0, r7", "al_r0_r7"},
- {{al, r0, r8}, "al, r0, r8", "al_r0_r8"},
- {{al, r0, r9}, "al, r0, r9", "al_r0_r9"},
- {{al, r0, r10}, "al, r0, r10", "al_r0_r10"},
- {{al, r0, r11}, "al, r0, r11", "al_r0_r11"},
- {{al, r0, r12}, "al, r0, r12", "al_r0_r12"},
- {{al, r0, r13}, "al, r0, r13", "al_r0_r13"},
- {{al, r0, r14}, "al, r0, r14", "al_r0_r14"},
- {{al, r1, r0}, "al, r1, r0", "al_r1_r0"},
- {{al, r1, r1}, "al, r1, r1", "al_r1_r1"},
- {{al, r1, r2}, "al, r1, r2", "al_r1_r2"},
- {{al, r1, r3}, "al, r1, r3", "al_r1_r3"},
- {{al, r1, r4}, "al, r1, r4", "al_r1_r4"},
- {{al, r1, r5}, "al, r1, r5", "al_r1_r5"},
- {{al, r1, r6}, "al, r1, r6", "al_r1_r6"},
- {{al, r1, r7}, "al, r1, r7", "al_r1_r7"},
- {{al, r1, r8}, "al, r1, r8", "al_r1_r8"},
- {{al, r1, r9}, "al, r1, r9", "al_r1_r9"},
- {{al, r1, r10}, "al, r1, r10", "al_r1_r10"},
- {{al, r1, r11}, "al, r1, r11", "al_r1_r11"},
- {{al, r1, r12}, "al, r1, r12", "al_r1_r12"},
- {{al, r1, r13}, "al, r1, r13", "al_r1_r13"},
- {{al, r1, r14}, "al, r1, r14", "al_r1_r14"},
- {{al, r2, r0}, "al, r2, r0", "al_r2_r0"},
- {{al, r2, r1}, "al, r2, r1", "al_r2_r1"},
- {{al, r2, r2}, "al, r2, r2", "al_r2_r2"},
- {{al, r2, r3}, "al, r2, r3", "al_r2_r3"},
- {{al, r2, r4}, "al, r2, r4", "al_r2_r4"},
- {{al, r2, r5}, "al, r2, r5", "al_r2_r5"},
- {{al, r2, r6}, "al, r2, r6", "al_r2_r6"},
- {{al, r2, r7}, "al, r2, r7", "al_r2_r7"},
- {{al, r2, r8}, "al, r2, r8", "al_r2_r8"},
- {{al, r2, r9}, "al, r2, r9", "al_r2_r9"},
- {{al, r2, r10}, "al, r2, r10", "al_r2_r10"},
- {{al, r2, r11}, "al, r2, r11", "al_r2_r11"},
- {{al, r2, r12}, "al, r2, r12", "al_r2_r12"},
- {{al, r2, r13}, "al, r2, r13", "al_r2_r13"},
- {{al, r2, r14}, "al, r2, r14", "al_r2_r14"},
- {{al, r3, r0}, "al, r3, r0", "al_r3_r0"},
- {{al, r3, r1}, "al, r3, r1", "al_r3_r1"},
- {{al, r3, r2}, "al, r3, r2", "al_r3_r2"},
- {{al, r3, r3}, "al, r3, r3", "al_r3_r3"},
- {{al, r3, r4}, "al, r3, r4", "al_r3_r4"},
- {{al, r3, r5}, "al, r3, r5", "al_r3_r5"},
- {{al, r3, r6}, "al, r3, r6", "al_r3_r6"},
- {{al, r3, r7}, "al, r3, r7", "al_r3_r7"},
- {{al, r3, r8}, "al, r3, r8", "al_r3_r8"},
- {{al, r3, r9}, "al, r3, r9", "al_r3_r9"},
- {{al, r3, r10}, "al, r3, r10", "al_r3_r10"},
- {{al, r3, r11}, "al, r3, r11", "al_r3_r11"},
- {{al, r3, r12}, "al, r3, r12", "al_r3_r12"},
- {{al, r3, r13}, "al, r3, r13", "al_r3_r13"},
- {{al, r3, r14}, "al, r3, r14", "al_r3_r14"},
- {{al, r4, r0}, "al, r4, r0", "al_r4_r0"},
- {{al, r4, r1}, "al, r4, r1", "al_r4_r1"},
- {{al, r4, r2}, "al, r4, r2", "al_r4_r2"},
- {{al, r4, r3}, "al, r4, r3", "al_r4_r3"},
- {{al, r4, r4}, "al, r4, r4", "al_r4_r4"},
- {{al, r4, r5}, "al, r4, r5", "al_r4_r5"},
- {{al, r4, r6}, "al, r4, r6", "al_r4_r6"},
- {{al, r4, r7}, "al, r4, r7", "al_r4_r7"},
- {{al, r4, r8}, "al, r4, r8", "al_r4_r8"},
- {{al, r4, r9}, "al, r4, r9", "al_r4_r9"},
- {{al, r4, r10}, "al, r4, r10", "al_r4_r10"},
- {{al, r4, r11}, "al, r4, r11", "al_r4_r11"},
- {{al, r4, r12}, "al, r4, r12", "al_r4_r12"},
- {{al, r4, r13}, "al, r4, r13", "al_r4_r13"},
- {{al, r4, r14}, "al, r4, r14", "al_r4_r14"},
- {{al, r5, r0}, "al, r5, r0", "al_r5_r0"},
- {{al, r5, r1}, "al, r5, r1", "al_r5_r1"},
- {{al, r5, r2}, "al, r5, r2", "al_r5_r2"},
- {{al, r5, r3}, "al, r5, r3", "al_r5_r3"},
- {{al, r5, r4}, "al, r5, r4", "al_r5_r4"},
- {{al, r5, r5}, "al, r5, r5", "al_r5_r5"},
- {{al, r5, r6}, "al, r5, r6", "al_r5_r6"},
- {{al, r5, r7}, "al, r5, r7", "al_r5_r7"},
- {{al, r5, r8}, "al, r5, r8", "al_r5_r8"},
- {{al, r5, r9}, "al, r5, r9", "al_r5_r9"},
- {{al, r5, r10}, "al, r5, r10", "al_r5_r10"},
- {{al, r5, r11}, "al, r5, r11", "al_r5_r11"},
- {{al, r5, r12}, "al, r5, r12", "al_r5_r12"},
- {{al, r5, r13}, "al, r5, r13", "al_r5_r13"},
- {{al, r5, r14}, "al, r5, r14", "al_r5_r14"},
- {{al, r6, r0}, "al, r6, r0", "al_r6_r0"},
- {{al, r6, r1}, "al, r6, r1", "al_r6_r1"},
- {{al, r6, r2}, "al, r6, r2", "al_r6_r2"},
- {{al, r6, r3}, "al, r6, r3", "al_r6_r3"},
- {{al, r6, r4}, "al, r6, r4", "al_r6_r4"},
- {{al, r6, r5}, "al, r6, r5", "al_r6_r5"},
- {{al, r6, r6}, "al, r6, r6", "al_r6_r6"},
- {{al, r6, r7}, "al, r6, r7", "al_r6_r7"},
- {{al, r6, r8}, "al, r6, r8", "al_r6_r8"},
- {{al, r6, r9}, "al, r6, r9", "al_r6_r9"},
- {{al, r6, r10}, "al, r6, r10", "al_r6_r10"},
- {{al, r6, r11}, "al, r6, r11", "al_r6_r11"},
- {{al, r6, r12}, "al, r6, r12", "al_r6_r12"},
- {{al, r6, r13}, "al, r6, r13", "al_r6_r13"},
- {{al, r6, r14}, "al, r6, r14", "al_r6_r14"},
- {{al, r7, r0}, "al, r7, r0", "al_r7_r0"},
- {{al, r7, r1}, "al, r7, r1", "al_r7_r1"},
- {{al, r7, r2}, "al, r7, r2", "al_r7_r2"},
- {{al, r7, r3}, "al, r7, r3", "al_r7_r3"},
- {{al, r7, r4}, "al, r7, r4", "al_r7_r4"},
- {{al, r7, r5}, "al, r7, r5", "al_r7_r5"},
- {{al, r7, r6}, "al, r7, r6", "al_r7_r6"},
- {{al, r7, r7}, "al, r7, r7", "al_r7_r7"},
- {{al, r7, r8}, "al, r7, r8", "al_r7_r8"},
- {{al, r7, r9}, "al, r7, r9", "al_r7_r9"},
- {{al, r7, r10}, "al, r7, r10", "al_r7_r10"},
- {{al, r7, r11}, "al, r7, r11", "al_r7_r11"},
- {{al, r7, r12}, "al, r7, r12", "al_r7_r12"},
- {{al, r7, r13}, "al, r7, r13", "al_r7_r13"},
- {{al, r7, r14}, "al, r7, r14", "al_r7_r14"},
- {{al, r8, r0}, "al, r8, r0", "al_r8_r0"},
- {{al, r8, r1}, "al, r8, r1", "al_r8_r1"},
- {{al, r8, r2}, "al, r8, r2", "al_r8_r2"},
- {{al, r8, r3}, "al, r8, r3", "al_r8_r3"},
- {{al, r8, r4}, "al, r8, r4", "al_r8_r4"},
- {{al, r8, r5}, "al, r8, r5", "al_r8_r5"},
- {{al, r8, r6}, "al, r8, r6", "al_r8_r6"},
- {{al, r8, r7}, "al, r8, r7", "al_r8_r7"},
- {{al, r8, r8}, "al, r8, r8", "al_r8_r8"},
- {{al, r8, r9}, "al, r8, r9", "al_r8_r9"},
- {{al, r8, r10}, "al, r8, r10", "al_r8_r10"},
- {{al, r8, r11}, "al, r8, r11", "al_r8_r11"},
- {{al, r8, r12}, "al, r8, r12", "al_r8_r12"},
- {{al, r8, r13}, "al, r8, r13", "al_r8_r13"},
- {{al, r8, r14}, "al, r8, r14", "al_r8_r14"},
- {{al, r9, r0}, "al, r9, r0", "al_r9_r0"},
- {{al, r9, r1}, "al, r9, r1", "al_r9_r1"},
- {{al, r9, r2}, "al, r9, r2", "al_r9_r2"},
- {{al, r9, r3}, "al, r9, r3", "al_r9_r3"},
- {{al, r9, r4}, "al, r9, r4", "al_r9_r4"},
- {{al, r9, r5}, "al, r9, r5", "al_r9_r5"},
+ {{ge, r0, r14}, "ge, r0, r14", "ge_r0_r14"},
+ {{mi, r5, r8}, "mi, r5, r8", "mi_r5_r8"},
+ {{vs, r4, r11}, "vs, r4, r11", "vs_r4_r11"},
+ {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
+ {{gt, r2, r8}, "gt, r2, r8", "gt_r2_r8"},
+ {{gt, r5, r7}, "gt, r5, r7", "gt_r5_r7"},
+ {{pl, r6, r3}, "pl, r6, r3", "pl_r6_r3"},
+ {{ne, r2, r12}, "ne, r2, r12", "ne_r2_r12"},
+ {{hi, r11, r11}, "hi, r11, r11", "hi_r11_r11"},
+ {{vs, r4, r14}, "vs, r4, r14", "vs_r4_r14"},
+ {{vs, r13, r1}, "vs, r13, r1", "vs_r13_r1"},
+ {{cs, r4, r3}, "cs, r4, r3", "cs_r4_r3"},
+ {{eq, r13, r6}, "eq, r13, r6", "eq_r13_r6"},
+ {{gt, r11, r14}, "gt, r11, r14", "gt_r11_r14"},
+ {{vc, r14, r4}, "vc, r14, r4", "vc_r14_r4"},
+ {{vc, r1, r10}, "vc, r1, r10", "vc_r1_r10"},
+ {{mi, r10, r3}, "mi, r10, r3", "mi_r10_r3"},
+ {{vs, r9, r3}, "vs, r9, r3", "vs_r9_r3"},
+ {{vc, r14, r5}, "vc, r14, r5", "vc_r14_r5"},
+ {{ne, r9, r1}, "ne, r9, r1", "ne_r9_r1"},
{{al, r9, r6}, "al, r9, r6", "al_r9_r6"},
- {{al, r9, r7}, "al, r9, r7", "al_r9_r7"},
- {{al, r9, r8}, "al, r9, r8", "al_r9_r8"},
- {{al, r9, r9}, "al, r9, r9", "al_r9_r9"},
- {{al, r9, r10}, "al, r9, r10", "al_r9_r10"},
- {{al, r9, r11}, "al, r9, r11", "al_r9_r11"},
- {{al, r9, r12}, "al, r9, r12", "al_r9_r12"},
- {{al, r9, r13}, "al, r9, r13", "al_r9_r13"},
- {{al, r9, r14}, "al, r9, r14", "al_r9_r14"},
+ {{vc, r7, r8}, "vc, r7, r8", "vc_r7_r8"},
+ {{ls, r6, r9}, "ls, r6, r9", "ls_r6_r9"},
+ {{le, r14, r2}, "le, r14, r2", "le_r14_r2"},
+ {{ls, r9, r13}, "ls, r9, r13", "ls_r9_r13"},
+ {{eq, r1, r5}, "eq, r1, r5", "eq_r1_r5"},
+ {{le, r9, r2}, "le, r9, r2", "le_r9_r2"},
+ {{eq, r2, r1}, "eq, r2, r1", "eq_r2_r1"},
+ {{ls, r9, r11}, "ls, r9, r11", "ls_r9_r11"},
+ {{lt, r7, r13}, "lt, r7, r13", "lt_r7_r13"},
+ {{cc, r8, r7}, "cc, r8, r7", "cc_r8_r7"},
+ {{ls, r5, r1}, "ls, r5, r1", "ls_r5_r1"},
+ {{le, r1, r9}, "le, r1, r9", "le_r1_r9"},
+ {{ls, r8, r14}, "ls, r8, r14", "ls_r8_r14"},
+ {{le, r9, r1}, "le, r9, r1", "le_r9_r1"},
+ {{gt, r1, r6}, "gt, r1, r6", "gt_r1_r6"},
+ {{gt, r11, r10}, "gt, r11, r10", "gt_r11_r10"},
+ {{hi, r0, r12}, "hi, r0, r12", "hi_r0_r12"},
+ {{gt, r1, r7}, "gt, r1, r7", "gt_r1_r7"},
+ {{mi, r7, r1}, "mi, r7, r1", "mi_r7_r1"},
+ {{mi, r7, r0}, "mi, r7, r0", "mi_r7_r0"},
+ {{ls, r1, r3}, "ls, r1, r3", "ls_r1_r3"},
+ {{mi, r13, r3}, "mi, r13, r3", "mi_r13_r3"},
+ {{eq, r4, r3}, "eq, r4, r3", "eq_r4_r3"},
+ {{vc, r14, r9}, "vc, r14, r9", "vc_r14_r9"},
+ {{pl, r3, r1}, "pl, r3, r1", "pl_r3_r1"},
+ {{mi, r0, r2}, "mi, r0, r2", "mi_r0_r2"},
+ {{hi, r2, r7}, "hi, r2, r7", "hi_r2_r7"},
+ {{hi, r13, r12}, "hi, r13, r12", "hi_r13_r12"},
+ {{ls, r12, r8}, "ls, r12, r8", "ls_r12_r8"},
+ {{ne, r5, r6}, "ne, r5, r6", "ne_r5_r6"},
+ {{pl, r5, r4}, "pl, r5, r4", "pl_r5_r4"},
+ {{ge, r1, r6}, "ge, r1, r6", "ge_r1_r6"},
+ {{eq, r8, r10}, "eq, r8, r10", "eq_r8_r10"},
+ {{cs, r5, r4}, "cs, r5, r4", "cs_r5_r4"},
+ {{eq, r11, r6}, "eq, r11, r6", "eq_r11_r6"},
+ {{cs, r13, r3}, "cs, r13, r3", "cs_r13_r3"},
+ {{pl, r2, r8}, "pl, r2, r8", "pl_r2_r8"},
+ {{gt, r10, r0}, "gt, r10, r0", "gt_r10_r0"},
+ {{lt, r4, r10}, "lt, r4, r10", "lt_r4_r10"},
+ {{vs, r14, r14}, "vs, r14, r14", "vs_r14_r14"},
+ {{hi, r0, r7}, "hi, r0, r7", "hi_r0_r7"},
+ {{cc, r9, r6}, "cc, r9, r6", "cc_r9_r6"},
+ {{ne, r7, r13}, "ne, r7, r13", "ne_r7_r13"},
+ {{eq, r2, r6}, "eq, r2, r6", "eq_r2_r6"},
+ {{cs, r12, r12}, "cs, r12, r12", "cs_r12_r12"},
+ {{mi, r3, r10}, "mi, r3, r10", "mi_r3_r10"},
+ {{le, r6, r13}, "le, r6, r13", "le_r6_r13"},
+ {{al, r2, r1}, "al, r2, r1", "al_r2_r1"},
+ {{le, r3, r4}, "le, r3, r4", "le_r3_r4"},
+ {{pl, r4, r4}, "pl, r4, r4", "pl_r4_r4"},
+ {{lt, r12, r3}, "lt, r12, r3", "lt_r12_r3"},
+ {{ls, r7, r4}, "ls, r7, r4", "ls_r7_r4"},
+ {{le, r9, r4}, "le, r9, r4", "le_r9_r4"},
+ {{vc, r13, r3}, "vc, r13, r3", "vc_r13_r3"},
+ {{vc, r8, r8}, "vc, r8, r8", "vc_r8_r8"},
+ {{ge, r2, r8}, "ge, r2, r8", "ge_r2_r8"},
+ {{le, r11, r13}, "le, r11, r13", "le_r11_r13"},
+ {{le, r1, r5}, "le, r1, r5", "le_r1_r5"},
+ {{ge, r9, r12}, "ge, r9, r12", "ge_r9_r12"},
+ {{cs, r14, r14}, "cs, r14, r14", "cs_r14_r14"},
+ {{cc, r1, r0}, "cc, r1, r0", "cc_r1_r0"},
+ {{ge, r3, r0}, "ge, r3, r0", "ge_r3_r0"},
{{al, r10, r0}, "al, r10, r0", "al_r10_r0"},
- {{al, r10, r1}, "al, r10, r1", "al_r10_r1"},
- {{al, r10, r2}, "al, r10, r2", "al_r10_r2"},
- {{al, r10, r3}, "al, r10, r3", "al_r10_r3"},
- {{al, r10, r4}, "al, r10, r4", "al_r10_r4"},
- {{al, r10, r5}, "al, r10, r5", "al_r10_r5"},
- {{al, r10, r6}, "al, r10, r6", "al_r10_r6"},
- {{al, r10, r7}, "al, r10, r7", "al_r10_r7"},
- {{al, r10, r8}, "al, r10, r8", "al_r10_r8"},
- {{al, r10, r9}, "al, r10, r9", "al_r10_r9"},
- {{al, r10, r10}, "al, r10, r10", "al_r10_r10"},
- {{al, r10, r11}, "al, r10, r11", "al_r10_r11"},
- {{al, r10, r12}, "al, r10, r12", "al_r10_r12"},
- {{al, r10, r13}, "al, r10, r13", "al_r10_r13"},
- {{al, r10, r14}, "al, r10, r14", "al_r10_r14"},
- {{al, r11, r0}, "al, r11, r0", "al_r11_r0"},
- {{al, r11, r1}, "al, r11, r1", "al_r11_r1"},
- {{al, r11, r2}, "al, r11, r2", "al_r11_r2"},
- {{al, r11, r3}, "al, r11, r3", "al_r11_r3"},
- {{al, r11, r4}, "al, r11, r4", "al_r11_r4"},
+ {{cc, r11, r10}, "cc, r11, r10", "cc_r11_r10"},
+ {{mi, r11, r11}, "mi, r11, r11", "mi_r11_r11"},
+ {{ne, r12, r7}, "ne, r12, r7", "ne_r12_r7"},
+ {{lt, r4, r12}, "lt, r4, r12", "lt_r4_r12"},
+ {{gt, r14, r5}, "gt, r14, r5", "gt_r14_r5"},
+ {{ge, r1, r7}, "ge, r1, r7", "ge_r1_r7"},
+ {{al, r7, r0}, "al, r7, r0", "al_r7_r0"},
+ {{ls, r2, r0}, "ls, r2, r0", "ls_r2_r0"},
+ {{pl, r6, r11}, "pl, r6, r11", "pl_r6_r11"},
+ {{vc, r0, r6}, "vc, r0, r6", "vc_r0_r6"},
+ {{pl, r6, r9}, "pl, r6, r9", "pl_r6_r9"},
+ {{vs, r8, r1}, "vs, r8, r1", "vs_r8_r1"},
+ {{cs, r1, r6}, "cs, r1, r6", "cs_r1_r6"},
+ {{hi, r4, r11}, "hi, r4, r11", "hi_r4_r11"},
+ {{gt, r5, r5}, "gt, r5, r5", "gt_r5_r5"},
+ {{al, r3, r4}, "al, r3, r4", "al_r3_r4"},
+ {{ge, r11, r12}, "ge, r11, r12", "ge_r11_r12"},
+ {{cc, r14, r2}, "cc, r14, r2", "cc_r14_r2"},
+ {{ge, r2, r4}, "ge, r2, r4", "ge_r2_r4"},
+ {{lt, r5, r11}, "lt, r5, r11", "lt_r5_r11"},
+ {{mi, r11, r14}, "mi, r11, r14", "mi_r11_r14"},
+ {{ne, r3, r3}, "ne, r3, r3", "ne_r3_r3"},
+ {{pl, r14, r0}, "pl, r14, r0", "pl_r14_r0"},
+ {{vc, r4, r10}, "vc, r4, r10", "vc_r4_r10"},
+ {{vs, r6, r8}, "vs, r6, r8", "vs_r6_r8"},
+ {{vc, r4, r7}, "vc, r4, r7", "vc_r4_r7"},
+ {{cs, r11, r10}, "cs, r11, r10", "cs_r11_r10"},
+ {{eq, r11, r8}, "eq, r11, r8", "eq_r11_r8"},
+ {{ne, r9, r2}, "ne, r9, r2", "ne_r9_r2"},
+ {{hi, r9, r7}, "hi, r9, r7", "hi_r9_r7"},
+ {{lt, r0, r6}, "lt, r0, r6", "lt_r0_r6"},
+ {{vc, r5, r8}, "vc, r5, r8", "vc_r5_r8"},
+ {{gt, r3, r1}, "gt, r3, r1", "gt_r3_r1"},
+ {{pl, r3, r5}, "pl, r3, r5", "pl_r3_r5"},
{{al, r11, r5}, "al, r11, r5", "al_r11_r5"},
- {{al, r11, r6}, "al, r11, r6", "al_r11_r6"},
- {{al, r11, r7}, "al, r11, r7", "al_r11_r7"},
- {{al, r11, r8}, "al, r11, r8", "al_r11_r8"},
- {{al, r11, r9}, "al, r11, r9", "al_r11_r9"},
- {{al, r11, r10}, "al, r11, r10", "al_r11_r10"},
- {{al, r11, r11}, "al, r11, r11", "al_r11_r11"},
- {{al, r11, r12}, "al, r11, r12", "al_r11_r12"},
- {{al, r11, r13}, "al, r11, r13", "al_r11_r13"},
- {{al, r11, r14}, "al, r11, r14", "al_r11_r14"},
- {{al, r12, r0}, "al, r12, r0", "al_r12_r0"},
- {{al, r12, r1}, "al, r12, r1", "al_r12_r1"},
- {{al, r12, r2}, "al, r12, r2", "al_r12_r2"},
- {{al, r12, r3}, "al, r12, r3", "al_r12_r3"},
- {{al, r12, r4}, "al, r12, r4", "al_r12_r4"},
- {{al, r12, r5}, "al, r12, r5", "al_r12_r5"},
- {{al, r12, r6}, "al, r12, r6", "al_r12_r6"},
- {{al, r12, r7}, "al, r12, r7", "al_r12_r7"},
- {{al, r12, r8}, "al, r12, r8", "al_r12_r8"},
+ {{hi, r8, r14}, "hi, r8, r14", "hi_r8_r14"},
+ {{le, r5, r4}, "le, r5, r4", "le_r5_r4"},
+ {{ge, r13, r3}, "ge, r13, r3", "ge_r13_r3"},
+ {{pl, r7, r14}, "pl, r7, r14", "pl_r7_r14"},
+ {{cs, r6, r9}, "cs, r6, r9", "cs_r6_r9"},
+ {{lt, r8, r12}, "lt, r8, r12", "lt_r8_r12"},
+ {{cc, r12, r0}, "cc, r12, r0", "cc_r12_r0"},
+ {{mi, r14, r13}, "mi, r14, r13", "mi_r14_r13"},
+ {{pl, r12, r13}, "pl, r12, r13", "pl_r12_r13"},
+ {{al, r4, r8}, "al, r4, r8", "al_r4_r8"},
+ {{ls, r5, r11}, "ls, r5, r11", "ls_r5_r11"},
+ {{ge, r11, r3}, "ge, r11, r3", "ge_r11_r3"},
+ {{le, r1, r0}, "le, r1, r0", "le_r1_r0"},
+ {{gt, r14, r4}, "gt, r14, r4", "gt_r14_r4"},
+ {{ne, r3, r14}, "ne, r3, r14", "ne_r3_r14"},
+ {{cc, r3, r8}, "cc, r3, r8", "cc_r3_r8"},
+ {{eq, r7, r10}, "eq, r7, r10", "eq_r7_r10"},
+ {{pl, r0, r10}, "pl, r0, r10", "pl_r0_r10"},
+ {{mi, r6, r13}, "mi, r6, r13", "mi_r6_r13"},
+ {{gt, r10, r5}, "gt, r10, r5", "gt_r10_r5"},
+ {{ne, r0, r1}, "ne, r0, r1", "ne_r0_r1"},
+ {{ge, r4, r8}, "ge, r4, r8", "ge_r4_r8"},
+ {{cs, r3, r7}, "cs, r3, r7", "cs_r3_r7"},
+ {{pl, r2, r12}, "pl, r2, r12", "pl_r2_r12"},
+ {{ls, r9, r12}, "ls, r9, r12", "ls_r9_r12"},
+ {{ge, r4, r9}, "ge, r4, r9", "ge_r4_r9"},
+ {{lt, r7, r2}, "lt, r7, r2", "lt_r7_r2"},
+ {{hi, r10, r10}, "hi, r10, r10", "hi_r10_r10"},
+ {{ls, r1, r7}, "ls, r1, r7", "ls_r1_r7"},
+ {{vs, r1, r12}, "vs, r1, r12", "vs_r1_r12"},
+ {{ge, r9, r14}, "ge, r9, r14", "ge_r9_r14"},
+ {{pl, r6, r4}, "pl, r6, r4", "pl_r6_r4"},
+ {{ls, r3, r2}, "ls, r3, r2", "ls_r3_r2"},
+ {{cs, r4, r4}, "cs, r4, r4", "cs_r4_r4"},
+ {{eq, r6, r2}, "eq, r6, r2", "eq_r6_r2"},
+ {{ge, r14, r0}, "ge, r14, r0", "ge_r14_r0"},
+ {{le, r11, r6}, "le, r11, r6", "le_r11_r6"},
+ {{vs, r0, r0}, "vs, r0, r0", "vs_r0_r0"},
+ {{vs, r4, r6}, "vs, r4, r6", "vs_r4_r6"},
+ {{gt, r6, r10}, "gt, r6, r10", "gt_r6_r10"},
+ {{vc, r12, r7}, "vc, r12, r7", "vc_r12_r7"},
+ {{gt, r8, r3}, "gt, r8, r3", "gt_r8_r3"},
+ {{hi, r14, r4}, "hi, r14, r4", "hi_r14_r4"},
+ {{hi, r9, r14}, "hi, r9, r14", "hi_r9_r14"},
+ {{vs, r6, r1}, "vs, r6, r1", "vs_r6_r1"},
+ {{hi, r5, r4}, "hi, r5, r4", "hi_r5_r4"},
+ {{lt, r10, r14}, "lt, r10, r14", "lt_r10_r14"},
+ {{cc, r8, r10}, "cc, r8, r10", "cc_r8_r10"},
+ {{lt, r11, r0}, "lt, r11, r0", "lt_r11_r0"},
+ {{ge, r4, r12}, "ge, r4, r12", "ge_r4_r12"},
+ {{cc, r5, r7}, "cc, r5, r7", "cc_r5_r7"},
+ {{gt, r3, r9}, "gt, r3, r9", "gt_r3_r9"},
+ {{vc, r11, r5}, "vc, r11, r5", "vc_r11_r5"},
+ {{lt, r7, r1}, "lt, r7, r1", "lt_r7_r1"},
+ {{lt, r1, r8}, "lt, r1, r8", "lt_r1_r8"},
+ {{hi, r11, r13}, "hi, r11, r13", "hi_r11_r13"},
+ {{vs, r10, r2}, "vs, r10, r2", "vs_r10_r2"},
+ {{ne, r1, r10}, "ne, r1, r10", "ne_r1_r10"},
+ {{vc, r10, r0}, "vc, r10, r0", "vc_r10_r0"},
+ {{al, r2, r2}, "al, r2, r2", "al_r2_r2"},
+ {{ne, r7, r8}, "ne, r7, r8", "ne_r7_r8"},
+ {{hi, r11, r14}, "hi, r11, r14", "hi_r11_r14"},
+ {{ne, r6, r14}, "ne, r6, r14", "ne_r6_r14"},
+ {{ge, r8, r5}, "ge, r8, r5", "ge_r8_r5"},
+ {{vs, r7, r3}, "vs, r7, r3", "vs_r7_r3"},
+ {{ne, r14, r13}, "ne, r14, r13", "ne_r14_r13"},
+ {{hi, r12, r11}, "hi, r12, r11", "hi_r12_r11"},
+ {{ls, r11, r9}, "ls, r11, r9", "ls_r11_r9"},
+ {{mi, r12, r7}, "mi, r12, r7", "mi_r12_r7"},
+ {{cc, r8, r8}, "cc, r8, r8", "cc_r8_r8"},
+ {{ls, r14, r12}, "ls, r14, r12", "ls_r14_r12"},
+ {{ls, r3, r6}, "ls, r3, r6", "ls_r3_r6"},
+ {{hi, r7, r8}, "hi, r7, r8", "hi_r7_r8"},
+ {{vs, r4, r10}, "vs, r4, r10", "vs_r4_r10"},
+ {{ne, r12, r1}, "ne, r12, r1", "ne_r12_r1"},
+ {{vs, r12, r4}, "vs, r12, r4", "vs_r12_r4"},
+ {{hi, r5, r5}, "hi, r5, r5", "hi_r5_r5"},
+ {{gt, r8, r8}, "gt, r8, r8", "gt_r8_r8"},
+ {{lt, r10, r10}, "lt, r10, r10", "lt_r10_r10"},
+ {{vs, r13, r4}, "vs, r13, r4", "vs_r13_r4"},
+ {{mi, r8, r3}, "mi, r8, r3", "mi_r8_r3"},
+ {{eq, r6, r13}, "eq, r6, r13", "eq_r6_r13"},
+ {{al, r2, r0}, "al, r2, r0", "al_r2_r0"},
+ {{ls, r6, r12}, "ls, r6, r12", "ls_r6_r12"},
+ {{vs, r1, r4}, "vs, r1, r4", "vs_r1_r4"},
+ {{vc, r11, r1}, "vc, r11, r1", "vc_r11_r1"},
+ {{ne, r9, r10}, "ne, r9, r10", "ne_r9_r10"},
+ {{ne, r3, r10}, "ne, r3, r10", "ne_r3_r10"},
+ {{hi, r7, r10}, "hi, r7, r10", "hi_r7_r10"},
+ {{pl, r4, r10}, "pl, r4, r10", "pl_r4_r10"},
+ {{le, r7, r1}, "le, r7, r1", "le_r7_r1"},
+ {{gt, r13, r10}, "gt, r13, r10", "gt_r13_r10"},
+ {{lt, r4, r14}, "lt, r4, r14", "lt_r4_r14"},
+ {{al, r10, r1}, "al, r10, r1", "al_r10_r1"},
+ {{mi, r6, r12}, "mi, r6, r12", "mi_r6_r12"},
+ {{eq, r13, r9}, "eq, r13, r9", "eq_r13_r9"},
+ {{ge, r11, r4}, "ge, r11, r4", "ge_r11_r4"},
+ {{hi, r1, r12}, "hi, r1, r12", "hi_r1_r12"},
+ {{ge, r0, r1}, "ge, r0, r1", "ge_r0_r1"},
+ {{lt, r2, r3}, "lt, r2, r3", "lt_r2_r3"},
{{al, r12, r9}, "al, r12, r9", "al_r12_r9"},
- {{al, r12, r10}, "al, r12, r10", "al_r12_r10"},
- {{al, r12, r11}, "al, r12, r11", "al_r12_r11"},
- {{al, r12, r12}, "al, r12, r12", "al_r12_r12"},
- {{al, r12, r13}, "al, r12, r13", "al_r12_r13"},
- {{al, r12, r14}, "al, r12, r14", "al_r12_r14"},
- {{al, r13, r0}, "al, r13, r0", "al_r13_r0"},
- {{al, r13, r1}, "al, r13, r1", "al_r13_r1"},
- {{al, r13, r2}, "al, r13, r2", "al_r13_r2"},
- {{al, r13, r3}, "al, r13, r3", "al_r13_r3"},
- {{al, r13, r4}, "al, r13, r4", "al_r13_r4"},
- {{al, r13, r5}, "al, r13, r5", "al_r13_r5"},
- {{al, r13, r6}, "al, r13, r6", "al_r13_r6"},
- {{al, r13, r7}, "al, r13, r7", "al_r13_r7"},
+ {{hi, r2, r10}, "hi, r2, r10", "hi_r2_r10"},
+ {{mi, r14, r11}, "mi, r14, r11", "mi_r14_r11"},
+ {{pl, r3, r10}, "pl, r3, r10", "pl_r3_r10"},
+ {{vs, r1, r6}, "vs, r1, r6", "vs_r1_r6"},
+ {{al, r7, r6}, "al, r7, r6", "al_r7_r6"},
+ {{ge, r6, r8}, "ge, r6, r8", "ge_r6_r8"},
+ {{eq, r3, r3}, "eq, r3, r3", "eq_r3_r3"},
+ {{ne, r14, r4}, "ne, r14, r4", "ne_r14_r4"},
+ {{vc, r13, r10}, "vc, r13, r10", "vc_r13_r10"},
+ {{mi, r3, r12}, "mi, r3, r12", "mi_r3_r12"},
+ {{pl, r9, r1}, "pl, r9, r1", "pl_r9_r1"},
+ {{hi, r14, r14}, "hi, r14, r14", "hi_r14_r14"},
+ {{ne, r0, r9}, "ne, r0, r9", "ne_r0_r9"},
+ {{mi, r1, r1}, "mi, r1, r1", "mi_r1_r1"},
+ {{hi, r7, r2}, "hi, r7, r2", "hi_r7_r2"},
+ {{gt, r2, r3}, "gt, r2, r3", "gt_r2_r3"},
+ {{eq, r2, r0}, "eq, r2, r0", "eq_r2_r0"},
+ {{vs, r10, r12}, "vs, r10, r12", "vs_r10_r12"},
+ {{gt, r11, r7}, "gt, r11, r7", "gt_r11_r7"},
+ {{vs, r13, r2}, "vs, r13, r2", "vs_r13_r2"},
+ {{ls, r11, r12}, "ls, r11, r12", "ls_r11_r12"},
+ {{al, r8, r8}, "al, r8, r8", "al_r8_r8"},
+ {{hi, r6, r10}, "hi, r6, r10", "hi_r6_r10"},
+ {{vs, r5, r1}, "vs, r5, r1", "vs_r5_r1"},
+ {{ls, r0, r10}, "ls, r0, r10", "ls_r0_r10"},
+ {{gt, r0, r1}, "gt, r0, r1", "gt_r0_r1"},
+ {{ne, r11, r12}, "ne, r11, r12", "ne_r11_r12"},
+ {{ne, r13, r5}, "ne, r13, r5", "ne_r13_r5"},
+ {{mi, r0, r12}, "mi, r0, r12", "mi_r0_r12"},
+ {{lt, r11, r6}, "lt, r11, r6", "lt_r11_r6"},
+ {{eq, r11, r14}, "eq, r11, r14", "eq_r11_r14"},
+ {{vc, r11, r10}, "vc, r11, r10", "vc_r11_r10"},
+ {{cs, r3, r3}, "cs, r3, r3", "cs_r3_r3"},
+ {{le, r12, r2}, "le, r12, r2", "le_r12_r2"},
+ {{hi, r13, r8}, "hi, r13, r8", "hi_r13_r8"},
+ {{pl, r6, r6}, "pl, r6, r6", "pl_r6_r6"},
+ {{al, r4, r5}, "al, r4, r5", "al_r4_r5"},
+ {{hi, r1, r0}, "hi, r1, r0", "hi_r1_r0"},
+ {{ls, r10, r11}, "ls, r10, r11", "ls_r10_r11"},
+ {{al, r8, r7}, "al, r8, r7", "al_r8_r7"},
+ {{vc, r7, r1}, "vc, r7, r1", "vc_r7_r1"},
+ {{ne, r7, r14}, "ne, r7, r14", "ne_r7_r14"},
+ {{lt, r5, r9}, "lt, r5, r9", "lt_r5_r9"},
{{al, r13, r8}, "al, r13, r8", "al_r13_r8"},
- {{al, r13, r9}, "al, r13, r9", "al_r13_r9"},
- {{al, r13, r10}, "al, r13, r10", "al_r13_r10"},
+ {{ls, r6, r14}, "ls, r6, r14", "ls_r6_r14"},
+ {{eq, r12, r0}, "eq, r12, r0", "eq_r12_r0"},
+ {{mi, r8, r14}, "mi, r8, r14", "mi_r8_r14"},
+ {{hi, r13, r2}, "hi, r13, r2", "hi_r13_r2"},
+ {{al, r13, r2}, "al, r13, r2", "al_r13_r2"},
+ {{vs, r8, r9}, "vs, r8, r9", "vs_r8_r9"},
+ {{cc, r6, r2}, "cc, r6, r2", "cc_r6_r2"},
+ {{lt, r8, r0}, "lt, r8, r0", "lt_r8_r0"},
+ {{ls, r3, r13}, "ls, r3, r13", "ls_r3_r13"},
+ {{gt, r10, r14}, "gt, r10, r14", "gt_r10_r14"},
+ {{pl, r9, r8}, "pl, r9, r8", "pl_r9_r8"},
+ {{pl, r14, r11}, "pl, r14, r11", "pl_r14_r11"},
+ {{lt, r9, r3}, "lt, r9, r3", "lt_r9_r3"},
+ {{hi, r9, r0}, "hi, r9, r0", "hi_r9_r0"},
+ {{cc, r9, r3}, "cc, r9, r3", "cc_r9_r3"},
+ {{ge, r10, r14}, "ge, r10, r14", "ge_r10_r14"},
+ {{vs, r2, r1}, "vs, r2, r1", "vs_r2_r1"},
+ {{vc, r4, r13}, "vc, r4, r13", "vc_r4_r13"},
+ {{ls, r1, r9}, "ls, r1, r9", "ls_r1_r9"},
+ {{lt, r13, r11}, "lt, r13, r11", "lt_r13_r11"},
+ {{cs, r2, r10}, "cs, r2, r10", "cs_r2_r10"},
+ {{le, r0, r13}, "le, r0, r13", "le_r0_r13"},
{{al, r13, r11}, "al, r13, r11", "al_r13_r11"},
- {{al, r13, r12}, "al, r13, r12", "al_r13_r12"},
- {{al, r13, r13}, "al, r13, r13", "al_r13_r13"},
- {{al, r13, r14}, "al, r13, r14", "al_r13_r14"},
- {{al, r14, r0}, "al, r14, r0", "al_r14_r0"},
- {{al, r14, r1}, "al, r14, r1", "al_r14_r1"},
- {{al, r14, r2}, "al, r14, r2", "al_r14_r2"},
- {{al, r14, r3}, "al, r14, r3", "al_r14_r3"},
- {{al, r14, r4}, "al, r14, r4", "al_r14_r4"},
- {{al, r14, r5}, "al, r14, r5", "al_r14_r5"},
- {{al, r14, r6}, "al, r14, r6", "al_r14_r6"},
- {{al, r14, r7}, "al, r14, r7", "al_r14_r7"},
- {{al, r14, r8}, "al, r14, r8", "al_r14_r8"},
- {{al, r14, r9}, "al, r14, r9", "al_r14_r9"},
- {{al, r14, r10}, "al, r14, r10", "al_r14_r10"},
- {{al, r14, r11}, "al, r14, r11", "al_r14_r11"},
- {{al, r14, r12}, "al, r14, r12", "al_r14_r12"},
- {{al, r14, r13}, "al, r14, r13", "al_r14_r13"},
- {{al, r14, r14}, "al, r14, r14", "al_r14_r14"}};
+ {{eq, r5, r2}, "eq, r5, r2", "eq_r5_r2"},
+ {{vs, r5, r12}, "vs, r5, r12", "vs_r5_r12"},
+ {{al, r12, r0}, "al, r12, r0", "al_r12_r0"},
+ {{le, r13, r9}, "le, r13, r9", "le_r13_r9"},
+ {{cs, r14, r4}, "cs, r14, r4", "cs_r14_r4"},
+ {{ne, r5, r7}, "ne, r5, r7", "ne_r5_r7"},
+ {{al, r6, r6}, "al, r6, r6", "al_r6_r6"},
+ {{gt, r4, r8}, "gt, r4, r8", "gt_r4_r8"},
+ {{gt, r12, r8}, "gt, r12, r8", "gt_r12_r8"},
+ {{eq, r4, r12}, "eq, r4, r12", "eq_r4_r12"},
+ {{cs, r7, r13}, "cs, r7, r13", "cs_r7_r13"},
+ {{cs, r2, r4}, "cs, r2, r4", "cs_r2_r4"},
+ {{al, r10, r3}, "al, r10, r3", "al_r10_r3"},
+ {{cs, r8, r9}, "cs, r8, r9", "cs_r8_r9"},
+ {{cs, r1, r12}, "cs, r1, r12", "cs_r1_r12"},
+ {{gt, r13, r0}, "gt, r13, r0", "gt_r13_r0"},
+ {{vc, r13, r12}, "vc, r13, r12", "vc_r13_r12"},
+ {{lt, r12, r14}, "lt, r12, r14", "lt_r12_r14"},
+ {{lt, r0, r1}, "lt, r0, r1", "lt_r0_r1"},
+ {{cc, r10, r2}, "cc, r10, r2", "cc_r10_r2"},
+ {{le, r3, r5}, "le, r3, r5", "le_r3_r5"},
+ {{eq, r2, r11}, "eq, r2, r11", "eq_r2_r11"},
+ {{al, r12, r4}, "al, r12, r4", "al_r12_r4"},
+ {{cs, r6, r5}, "cs, r6, r5", "cs_r6_r5"},
+ {{hi, r13, r10}, "hi, r13, r10", "hi_r13_r10"},
+ {{vs, r4, r3}, "vs, r4, r3", "vs_r4_r3"},
+ {{ls, r7, r9}, "ls, r7, r9", "ls_r7_r9"},
+ {{vs, r14, r8}, "vs, r14, r8", "vs_r14_r8"},
+ {{cs, r1, r0}, "cs, r1, r0", "cs_r1_r0"},
+ {{mi, r10, r8}, "mi, r10, r8", "mi_r10_r8"},
+ {{ge, r10, r4}, "ge, r10, r4", "ge_r10_r4"},
+ {{cc, r5, r4}, "cc, r5, r4", "cc_r5_r4"},
+ {{lt, r0, r7}, "lt, r0, r7", "lt_r0_r7"},
+ {{mi, r14, r10}, "mi, r14, r10", "mi_r14_r10"},
+ {{mi, r0, r14}, "mi, r0, r14", "mi_r0_r14"},
+ {{eq, r14, r10}, "eq, r14, r10", "eq_r14_r10"},
+ {{ls, r4, r4}, "ls, r4, r4", "ls_r4_r4"},
+ {{pl, r14, r1}, "pl, r14, r1", "pl_r14_r1"},
+ {{eq, r10, r8}, "eq, r10, r8", "eq_r10_r8"},
+ {{cs, r10, r6}, "cs, r10, r6", "cs_r10_r6"},
+ {{al, r12, r2}, "al, r12, r2", "al_r12_r2"},
+ {{ls, r12, r1}, "ls, r12, r1", "ls_r12_r1"},
+ {{eq, r12, r11}, "eq, r12, r11", "eq_r12_r11"},
+ {{vc, r4, r1}, "vc, r4, r1", "vc_r4_r1"},
+ {{vs, r12, r2}, "vs, r12, r2", "vs_r12_r2"},
+ {{al, r11, r8}, "al, r11, r8", "al_r11_r8"},
+ {{hi, r6, r13}, "hi, r6, r13", "hi_r6_r13"},
+ {{eq, r2, r8}, "eq, r2, r8", "eq_r2_r8"},
+ {{cc, r9, r5}, "cc, r9, r5", "cc_r9_r5"},
+ {{cc, r9, r7}, "cc, r9, r7", "cc_r9_r7"},
+ {{lt, r4, r6}, "lt, r4, r6", "lt_r4_r6"},
+ {{cc, r14, r13}, "cc, r14, r13", "cc_r14_r13"},
+ {{vc, r3, r2}, "vc, r3, r2", "vc_r3_r2"},
+ {{al, r6, r13}, "al, r6, r13", "al_r6_r13"},
+ {{vs, r10, r10}, "vs, r10, r10", "vs_r10_r10"},
+ {{cs, r6, r10}, "cs, r6, r10", "cs_r6_r10"},
+ {{cc, r8, r12}, "cc, r8, r12", "cc_r8_r12"},
+ {{vs, r7, r5}, "vs, r7, r5", "vs_r7_r5"},
+ {{pl, r14, r10}, "pl, r14, r10", "pl_r14_r10"},
+ {{hi, r1, r14}, "hi, r1, r14", "hi_r1_r14"},
+ {{vc, r8, r12}, "vc, r8, r12", "vc_r8_r12"},
+ {{ls, r2, r4}, "ls, r2, r4", "ls_r2_r4"},
+ {{mi, r5, r12}, "mi, r5, r12", "mi_r5_r12"},
+ {{eq, r6, r12}, "eq, r6, r12", "eq_r6_r12"},
+ {{lt, r14, r9}, "lt, r14, r9", "lt_r14_r9"},
+ {{lt, r11, r9}, "lt, r11, r9", "lt_r11_r9"},
+ {{ne, r1, r9}, "ne, r1, r9", "ne_r1_r9"},
+ {{pl, r11, r8}, "pl, r11, r8", "pl_r11_r8"},
+ {{ne, r0, r6}, "ne, r0, r6", "ne_r0_r6"},
+ {{vs, r4, r4}, "vs, r4, r4", "vs_r4_r4"},
+ {{ls, r12, r9}, "ls, r12, r9", "ls_r12_r9"},
+ {{cs, r9, r7}, "cs, r9, r7", "cs_r9_r7"},
+ {{ne, r7, r2}, "ne, r7, r2", "ne_r7_r2"},
+ {{hi, r9, r10}, "hi, r9, r10", "hi_r9_r10"},
+ {{gt, r5, r2}, "gt, r5, r2", "gt_r5_r2"},
+ {{pl, r4, r6}, "pl, r4, r6", "pl_r4_r6"},
+ {{lt, r11, r8}, "lt, r11, r8", "lt_r11_r8"},
+ {{hi, r13, r4}, "hi, r13, r4", "hi_r13_r4"},
+ {{le, r1, r10}, "le, r1, r10", "le_r1_r10"},
+ {{le, r11, r3}, "le, r11, r3", "le_r11_r3"},
+ {{pl, r0, r11}, "pl, r0, r11", "pl_r0_r11"},
+ {{le, r7, r4}, "le, r7, r4", "le_r7_r4"},
+ {{le, r2, r11}, "le, r2, r11", "le_r2_r11"},
+ {{cc, r1, r10}, "cc, r1, r10", "cc_r1_r10"},
+ {{gt, r13, r14}, "gt, r13, r14", "gt_r13_r14"},
+ {{ls, r10, r6}, "ls, r10, r6", "ls_r10_r6"},
+ {{ls, r13, r4}, "ls, r13, r4", "ls_r13_r4"},
+ {{gt, r12, r13}, "gt, r12, r13", "gt_r12_r13"},
+ {{pl, r13, r7}, "pl, r13, r7", "pl_r13_r7"},
+ {{le, r14, r0}, "le, r14, r0", "le_r14_r0"},
+ {{gt, r1, r4}, "gt, r1, r4", "gt_r1_r4"},
+ {{mi, r3, r5}, "mi, r3, r5", "mi_r3_r5"},
+ {{vc, r4, r0}, "vc, r4, r0", "vc_r4_r0"},
+ {{gt, r4, r11}, "gt, r4, r11", "gt_r4_r11"},
+ {{vc, r5, r3}, "vc, r5, r3", "vc_r5_r3"},
+ {{pl, r4, r7}, "pl, r4, r7", "pl_r4_r7"},
+ {{al, r12, r6}, "al, r12, r6", "al_r12_r6"},
+ {{mi, r2, r3}, "mi, r2, r3", "mi_r2_r3"},
+ {{lt, r12, r4}, "lt, r12, r4", "lt_r12_r4"},
+ {{lt, r10, r4}, "lt, r10, r4", "lt_r10_r4"},
+ {{hi, r10, r8}, "hi, r10, r8", "hi_r10_r8"},
+ {{al, r0, r14}, "al, r0, r14", "al_r0_r14"},
+ {{cc, r3, r3}, "cc, r3, r3", "cc_r3_r3"},
+ {{pl, r10, r13}, "pl, r10, r13", "pl_r10_r13"},
+ {{lt, r7, r8}, "lt, r7, r8", "lt_r7_r8"},
+ {{le, r12, r7}, "le, r12, r7", "le_r12_r7"},
+ {{ge, r11, r8}, "ge, r11, r8", "ge_r11_r8"},
+ {{ls, r10, r8}, "ls, r10, r8", "ls_r10_r8"},
+ {{vs, r9, r1}, "vs, r9, r1", "vs_r9_r1"},
+ {{ne, r10, r10}, "ne, r10, r10", "ne_r10_r10"},
+ {{al, r6, r4}, "al, r6, r4", "al_r6_r4"},
+ {{ls, r10, r0}, "ls, r10, r0", "ls_r10_r0"},
+ {{eq, r7, r1}, "eq, r7, r1", "eq_r7_r1"},
+ {{al, r11, r6}, "al, r11, r6", "al_r11_r6"},
+ {{ge, r5, r10}, "ge, r5, r10", "ge_r5_r10"},
+ {{vs, r0, r8}, "vs, r0, r8", "vs_r0_r8"},
+ {{lt, r2, r1}, "lt, r2, r1", "lt_r2_r1"},
+ {{le, r13, r2}, "le, r13, r2", "le_r13_r2"},
+ {{al, r13, r6}, "al, r13, r6", "al_r13_r6"},
+ {{lt, r12, r10}, "lt, r12, r10", "lt_r12_r10"},
+ {{al, r13, r1}, "al, r13, r1", "al_r13_r1"},
+ {{ge, r8, r14}, "ge, r8, r14", "ge_r8_r14"},
+ {{mi, r11, r6}, "mi, r11, r6", "mi_r11_r6"},
+ {{pl, r12, r14}, "pl, r12, r14", "pl_r12_r14"},
+ {{ne, r14, r9}, "ne, r14, r9", "ne_r14_r9"},
+ {{cc, r3, r1}, "cc, r3, r1", "cc_r3_r1"},
+ {{ge, r0, r8}, "ge, r0, r8", "ge_r0_r8"},
+ {{vc, r7, r9}, "vc, r7, r9", "vc_r7_r9"},
+ {{gt, r11, r4}, "gt, r11, r4", "gt_r11_r4"},
+ {{mi, r4, r0}, "mi, r4, r0", "mi_r4_r0"},
+ {{ls, r3, r11}, "ls, r3, r11", "ls_r3_r11"},
+ {{le, r14, r5}, "le, r14, r5", "le_r14_r5"},
+ {{ls, r6, r7}, "ls, r6, r7", "ls_r6_r7"},
+ {{ne, r4, r6}, "ne, r4, r6", "ne_r4_r6"},
+ {{cc, r1, r14}, "cc, r1, r14", "cc_r1_r14"},
+ {{pl, r11, r7}, "pl, r11, r7", "pl_r11_r7"},
+ {{vc, r6, r5}, "vc, r6, r5", "vc_r6_r5"},
+ {{al, r1, r11}, "al, r1, r11", "al_r1_r11"},
+ {{ne, r2, r13}, "ne, r2, r13", "ne_r2_r13"},
+ {{vc, r14, r6}, "vc, r14, r6", "vc_r14_r6"},
+ {{gt, r3, r8}, "gt, r3, r8", "gt_r3_r8"},
+ {{pl, r1, r8}, "pl, r1, r8", "pl_r1_r8"},
+ {{vc, r2, r14}, "vc, r2, r14", "vc_r2_r14"},
+ {{pl, r12, r3}, "pl, r12, r3", "pl_r12_r3"},
+ {{ls, r0, r12}, "ls, r0, r12", "ls_r0_r12"},
+ {{le, r2, r1}, "le, r2, r1", "le_r2_r1"},
+ {{eq, r13, r5}, "eq, r13, r5", "eq_r13_r5"},
+ {{al, r11, r11}, "al, r11, r11", "al_r11_r11"},
+ {{ls, r9, r3}, "ls, r9, r3", "ls_r9_r3"},
+ {{ne, r7, r12}, "ne, r7, r12", "ne_r7_r12"},
+ {{al, r6, r2}, "al, r6, r2", "al_r6_r2"},
+ {{ne, r7, r4}, "ne, r7, r4", "ne_r7_r4"},
+ {{vc, r7, r5}, "vc, r7, r5", "vc_r7_r5"},
+ {{ne, r7, r1}, "ne, r7, r1", "ne_r7_r1"},
+ {{eq, r5, r3}, "eq, r5, r3", "eq_r5_r3"},
+ {{cs, r3, r5}, "cs, r3, r5", "cs_r3_r5"},
+ {{lt, r7, r4}, "lt, r7, r4", "lt_r7_r4"},
+ {{ls, r4, r5}, "ls, r4, r5", "ls_r4_r5"},
+ {{eq, r11, r2}, "eq, r11, r2", "eq_r11_r2"},
+ {{hi, r2, r6}, "hi, r2, r6", "hi_r2_r6"},
+ {{vc, r2, r3}, "vc, r2, r3", "vc_r2_r3"},
+ {{ls, r12, r12}, "ls, r12, r12", "ls_r12_r12"},
+ {{lt, r8, r2}, "lt, r8, r2", "lt_r8_r2"},
+ {{cc, r14, r8}, "cc, r14, r8", "cc_r14_r8"},
+ {{ge, r12, r8}, "ge, r12, r8", "ge_r12_r8"}};
typedef void (MacroAssembler::*Fn)(Condition cond, Register rd, Register rn);
@@ -3550,6 +676,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-macro-assembler-cond-rd-rn-pc-a32.cc b/test/aarch32/test-macro-assembler-cond-rd-rn-pc-a32.cc
index a9e489a..c9597db 100644
--- a/test/aarch32/test-macro-assembler-cond-rd-rn-pc-a32.cc
+++ b/test/aarch32/test-macro-assembler-cond-rd-rn-pc-a32.cc
@@ -61,6 +61,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -633,6 +634,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-macro-assembler-cond-rd-rn-t32.cc b/test/aarch32/test-macro-assembler-cond-rd-rn-t32.cc
index af84716..6b04a5b 100644
--- a/test/aarch32/test-macro-assembler-cond-rd-rn-t32.cc
+++ b/test/aarch32/test-macro-assembler-cond-rd-rn-t32.cc
@@ -68,6 +68,7 @@
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -90,3381 +91,506 @@
};
// Each element of this array produce one instruction encoding.
-const TestData kTests[] = {{{eq, r0, r0}, "eq, r0, r0", "eq_r0_r0"},
- {{eq, r0, r1}, "eq, r0, r1", "eq_r0_r1"},
- {{eq, r0, r2}, "eq, r0, r2", "eq_r0_r2"},
- {{eq, r0, r3}, "eq, r0, r3", "eq_r0_r3"},
- {{eq, r0, r4}, "eq, r0, r4", "eq_r0_r4"},
- {{eq, r0, r5}, "eq, r0, r5", "eq_r0_r5"},
- {{eq, r0, r6}, "eq, r0, r6", "eq_r0_r6"},
- {{eq, r0, r7}, "eq, r0, r7", "eq_r0_r7"},
- {{eq, r0, r8}, "eq, r0, r8", "eq_r0_r8"},
- {{eq, r0, r9}, "eq, r0, r9", "eq_r0_r9"},
- {{eq, r0, r10}, "eq, r0, r10", "eq_r0_r10"},
- {{eq, r0, r11}, "eq, r0, r11", "eq_r0_r11"},
- {{eq, r0, r12}, "eq, r0, r12", "eq_r0_r12"},
- {{eq, r0, r13}, "eq, r0, r13", "eq_r0_r13"},
- {{eq, r0, r14}, "eq, r0, r14", "eq_r0_r14"},
- {{eq, r1, r0}, "eq, r1, r0", "eq_r1_r0"},
- {{eq, r1, r1}, "eq, r1, r1", "eq_r1_r1"},
- {{eq, r1, r2}, "eq, r1, r2", "eq_r1_r2"},
- {{eq, r1, r3}, "eq, r1, r3", "eq_r1_r3"},
- {{eq, r1, r4}, "eq, r1, r4", "eq_r1_r4"},
- {{eq, r1, r5}, "eq, r1, r5", "eq_r1_r5"},
- {{eq, r1, r6}, "eq, r1, r6", "eq_r1_r6"},
- {{eq, r1, r7}, "eq, r1, r7", "eq_r1_r7"},
- {{eq, r1, r8}, "eq, r1, r8", "eq_r1_r8"},
- {{eq, r1, r9}, "eq, r1, r9", "eq_r1_r9"},
- {{eq, r1, r10}, "eq, r1, r10", "eq_r1_r10"},
- {{eq, r1, r11}, "eq, r1, r11", "eq_r1_r11"},
- {{eq, r1, r12}, "eq, r1, r12", "eq_r1_r12"},
- {{eq, r1, r13}, "eq, r1, r13", "eq_r1_r13"},
- {{eq, r1, r14}, "eq, r1, r14", "eq_r1_r14"},
- {{eq, r2, r0}, "eq, r2, r0", "eq_r2_r0"},
- {{eq, r2, r1}, "eq, r2, r1", "eq_r2_r1"},
- {{eq, r2, r2}, "eq, r2, r2", "eq_r2_r2"},
- {{eq, r2, r3}, "eq, r2, r3", "eq_r2_r3"},
- {{eq, r2, r4}, "eq, r2, r4", "eq_r2_r4"},
- {{eq, r2, r5}, "eq, r2, r5", "eq_r2_r5"},
- {{eq, r2, r6}, "eq, r2, r6", "eq_r2_r6"},
- {{eq, r2, r7}, "eq, r2, r7", "eq_r2_r7"},
- {{eq, r2, r8}, "eq, r2, r8", "eq_r2_r8"},
- {{eq, r2, r9}, "eq, r2, r9", "eq_r2_r9"},
- {{eq, r2, r10}, "eq, r2, r10", "eq_r2_r10"},
- {{eq, r2, r11}, "eq, r2, r11", "eq_r2_r11"},
- {{eq, r2, r12}, "eq, r2, r12", "eq_r2_r12"},
- {{eq, r2, r13}, "eq, r2, r13", "eq_r2_r13"},
- {{eq, r2, r14}, "eq, r2, r14", "eq_r2_r14"},
- {{eq, r3, r0}, "eq, r3, r0", "eq_r3_r0"},
- {{eq, r3, r1}, "eq, r3, r1", "eq_r3_r1"},
- {{eq, r3, r2}, "eq, r3, r2", "eq_r3_r2"},
- {{eq, r3, r3}, "eq, r3, r3", "eq_r3_r3"},
- {{eq, r3, r4}, "eq, r3, r4", "eq_r3_r4"},
- {{eq, r3, r5}, "eq, r3, r5", "eq_r3_r5"},
- {{eq, r3, r6}, "eq, r3, r6", "eq_r3_r6"},
- {{eq, r3, r7}, "eq, r3, r7", "eq_r3_r7"},
- {{eq, r3, r8}, "eq, r3, r8", "eq_r3_r8"},
- {{eq, r3, r9}, "eq, r3, r9", "eq_r3_r9"},
- {{eq, r3, r10}, "eq, r3, r10", "eq_r3_r10"},
- {{eq, r3, r11}, "eq, r3, r11", "eq_r3_r11"},
- {{eq, r3, r12}, "eq, r3, r12", "eq_r3_r12"},
- {{eq, r3, r13}, "eq, r3, r13", "eq_r3_r13"},
- {{eq, r3, r14}, "eq, r3, r14", "eq_r3_r14"},
- {{eq, r4, r0}, "eq, r4, r0", "eq_r4_r0"},
- {{eq, r4, r1}, "eq, r4, r1", "eq_r4_r1"},
- {{eq, r4, r2}, "eq, r4, r2", "eq_r4_r2"},
- {{eq, r4, r3}, "eq, r4, r3", "eq_r4_r3"},
- {{eq, r4, r4}, "eq, r4, r4", "eq_r4_r4"},
- {{eq, r4, r5}, "eq, r4, r5", "eq_r4_r5"},
- {{eq, r4, r6}, "eq, r4, r6", "eq_r4_r6"},
- {{eq, r4, r7}, "eq, r4, r7", "eq_r4_r7"},
- {{eq, r4, r8}, "eq, r4, r8", "eq_r4_r8"},
- {{eq, r4, r9}, "eq, r4, r9", "eq_r4_r9"},
- {{eq, r4, r10}, "eq, r4, r10", "eq_r4_r10"},
- {{eq, r4, r11}, "eq, r4, r11", "eq_r4_r11"},
- {{eq, r4, r12}, "eq, r4, r12", "eq_r4_r12"},
- {{eq, r4, r13}, "eq, r4, r13", "eq_r4_r13"},
- {{eq, r4, r14}, "eq, r4, r14", "eq_r4_r14"},
- {{eq, r5, r0}, "eq, r5, r0", "eq_r5_r0"},
- {{eq, r5, r1}, "eq, r5, r1", "eq_r5_r1"},
- {{eq, r5, r2}, "eq, r5, r2", "eq_r5_r2"},
- {{eq, r5, r3}, "eq, r5, r3", "eq_r5_r3"},
- {{eq, r5, r4}, "eq, r5, r4", "eq_r5_r4"},
- {{eq, r5, r5}, "eq, r5, r5", "eq_r5_r5"},
- {{eq, r5, r6}, "eq, r5, r6", "eq_r5_r6"},
- {{eq, r5, r7}, "eq, r5, r7", "eq_r5_r7"},
- {{eq, r5, r8}, "eq, r5, r8", "eq_r5_r8"},
- {{eq, r5, r9}, "eq, r5, r9", "eq_r5_r9"},
- {{eq, r5, r10}, "eq, r5, r10", "eq_r5_r10"},
- {{eq, r5, r11}, "eq, r5, r11", "eq_r5_r11"},
- {{eq, r5, r12}, "eq, r5, r12", "eq_r5_r12"},
- {{eq, r5, r13}, "eq, r5, r13", "eq_r5_r13"},
- {{eq, r5, r14}, "eq, r5, r14", "eq_r5_r14"},
- {{eq, r6, r0}, "eq, r6, r0", "eq_r6_r0"},
- {{eq, r6, r1}, "eq, r6, r1", "eq_r6_r1"},
- {{eq, r6, r2}, "eq, r6, r2", "eq_r6_r2"},
- {{eq, r6, r3}, "eq, r6, r3", "eq_r6_r3"},
- {{eq, r6, r4}, "eq, r6, r4", "eq_r6_r4"},
- {{eq, r6, r5}, "eq, r6, r5", "eq_r6_r5"},
- {{eq, r6, r6}, "eq, r6, r6", "eq_r6_r6"},
- {{eq, r6, r7}, "eq, r6, r7", "eq_r6_r7"},
- {{eq, r6, r8}, "eq, r6, r8", "eq_r6_r8"},
- {{eq, r6, r9}, "eq, r6, r9", "eq_r6_r9"},
- {{eq, r6, r10}, "eq, r6, r10", "eq_r6_r10"},
- {{eq, r6, r11}, "eq, r6, r11", "eq_r6_r11"},
- {{eq, r6, r12}, "eq, r6, r12", "eq_r6_r12"},
- {{eq, r6, r13}, "eq, r6, r13", "eq_r6_r13"},
- {{eq, r6, r14}, "eq, r6, r14", "eq_r6_r14"},
- {{eq, r7, r0}, "eq, r7, r0", "eq_r7_r0"},
- {{eq, r7, r1}, "eq, r7, r1", "eq_r7_r1"},
- {{eq, r7, r2}, "eq, r7, r2", "eq_r7_r2"},
- {{eq, r7, r3}, "eq, r7, r3", "eq_r7_r3"},
- {{eq, r7, r4}, "eq, r7, r4", "eq_r7_r4"},
- {{eq, r7, r5}, "eq, r7, r5", "eq_r7_r5"},
- {{eq, r7, r6}, "eq, r7, r6", "eq_r7_r6"},
- {{eq, r7, r7}, "eq, r7, r7", "eq_r7_r7"},
- {{eq, r7, r8}, "eq, r7, r8", "eq_r7_r8"},
- {{eq, r7, r9}, "eq, r7, r9", "eq_r7_r9"},
- {{eq, r7, r10}, "eq, r7, r10", "eq_r7_r10"},
- {{eq, r7, r11}, "eq, r7, r11", "eq_r7_r11"},
- {{eq, r7, r12}, "eq, r7, r12", "eq_r7_r12"},
- {{eq, r7, r13}, "eq, r7, r13", "eq_r7_r13"},
- {{eq, r7, r14}, "eq, r7, r14", "eq_r7_r14"},
- {{eq, r8, r0}, "eq, r8, r0", "eq_r8_r0"},
- {{eq, r8, r1}, "eq, r8, r1", "eq_r8_r1"},
- {{eq, r8, r2}, "eq, r8, r2", "eq_r8_r2"},
- {{eq, r8, r3}, "eq, r8, r3", "eq_r8_r3"},
- {{eq, r8, r4}, "eq, r8, r4", "eq_r8_r4"},
- {{eq, r8, r5}, "eq, r8, r5", "eq_r8_r5"},
- {{eq, r8, r6}, "eq, r8, r6", "eq_r8_r6"},
- {{eq, r8, r7}, "eq, r8, r7", "eq_r8_r7"},
- {{eq, r8, r8}, "eq, r8, r8", "eq_r8_r8"},
- {{eq, r8, r9}, "eq, r8, r9", "eq_r8_r9"},
- {{eq, r8, r10}, "eq, r8, r10", "eq_r8_r10"},
- {{eq, r8, r11}, "eq, r8, r11", "eq_r8_r11"},
- {{eq, r8, r12}, "eq, r8, r12", "eq_r8_r12"},
- {{eq, r8, r13}, "eq, r8, r13", "eq_r8_r13"},
- {{eq, r8, r14}, "eq, r8, r14", "eq_r8_r14"},
- {{eq, r9, r0}, "eq, r9, r0", "eq_r9_r0"},
- {{eq, r9, r1}, "eq, r9, r1", "eq_r9_r1"},
- {{eq, r9, r2}, "eq, r9, r2", "eq_r9_r2"},
- {{eq, r9, r3}, "eq, r9, r3", "eq_r9_r3"},
- {{eq, r9, r4}, "eq, r9, r4", "eq_r9_r4"},
- {{eq, r9, r5}, "eq, r9, r5", "eq_r9_r5"},
- {{eq, r9, r6}, "eq, r9, r6", "eq_r9_r6"},
- {{eq, r9, r7}, "eq, r9, r7", "eq_r9_r7"},
- {{eq, r9, r8}, "eq, r9, r8", "eq_r9_r8"},
- {{eq, r9, r9}, "eq, r9, r9", "eq_r9_r9"},
- {{eq, r9, r10}, "eq, r9, r10", "eq_r9_r10"},
- {{eq, r9, r11}, "eq, r9, r11", "eq_r9_r11"},
- {{eq, r9, r12}, "eq, r9, r12", "eq_r9_r12"},
- {{eq, r9, r13}, "eq, r9, r13", "eq_r9_r13"},
- {{eq, r9, r14}, "eq, r9, r14", "eq_r9_r14"},
- {{eq, r10, r0}, "eq, r10, r0", "eq_r10_r0"},
- {{eq, r10, r1}, "eq, r10, r1", "eq_r10_r1"},
- {{eq, r10, r2}, "eq, r10, r2", "eq_r10_r2"},
- {{eq, r10, r3}, "eq, r10, r3", "eq_r10_r3"},
- {{eq, r10, r4}, "eq, r10, r4", "eq_r10_r4"},
- {{eq, r10, r5}, "eq, r10, r5", "eq_r10_r5"},
- {{eq, r10, r6}, "eq, r10, r6", "eq_r10_r6"},
- {{eq, r10, r7}, "eq, r10, r7", "eq_r10_r7"},
- {{eq, r10, r8}, "eq, r10, r8", "eq_r10_r8"},
- {{eq, r10, r9}, "eq, r10, r9", "eq_r10_r9"},
- {{eq, r10, r10}, "eq, r10, r10", "eq_r10_r10"},
- {{eq, r10, r11}, "eq, r10, r11", "eq_r10_r11"},
- {{eq, r10, r12}, "eq, r10, r12", "eq_r10_r12"},
- {{eq, r10, r13}, "eq, r10, r13", "eq_r10_r13"},
- {{eq, r10, r14}, "eq, r10, r14", "eq_r10_r14"},
- {{eq, r11, r0}, "eq, r11, r0", "eq_r11_r0"},
- {{eq, r11, r1}, "eq, r11, r1", "eq_r11_r1"},
- {{eq, r11, r2}, "eq, r11, r2", "eq_r11_r2"},
- {{eq, r11, r3}, "eq, r11, r3", "eq_r11_r3"},
- {{eq, r11, r4}, "eq, r11, r4", "eq_r11_r4"},
- {{eq, r11, r5}, "eq, r11, r5", "eq_r11_r5"},
- {{eq, r11, r6}, "eq, r11, r6", "eq_r11_r6"},
- {{eq, r11, r7}, "eq, r11, r7", "eq_r11_r7"},
- {{eq, r11, r8}, "eq, r11, r8", "eq_r11_r8"},
- {{eq, r11, r9}, "eq, r11, r9", "eq_r11_r9"},
- {{eq, r11, r10}, "eq, r11, r10", "eq_r11_r10"},
- {{eq, r11, r11}, "eq, r11, r11", "eq_r11_r11"},
- {{eq, r11, r12}, "eq, r11, r12", "eq_r11_r12"},
- {{eq, r11, r13}, "eq, r11, r13", "eq_r11_r13"},
- {{eq, r11, r14}, "eq, r11, r14", "eq_r11_r14"},
- {{eq, r12, r0}, "eq, r12, r0", "eq_r12_r0"},
- {{eq, r12, r1}, "eq, r12, r1", "eq_r12_r1"},
- {{eq, r12, r2}, "eq, r12, r2", "eq_r12_r2"},
- {{eq, r12, r3}, "eq, r12, r3", "eq_r12_r3"},
- {{eq, r12, r4}, "eq, r12, r4", "eq_r12_r4"},
- {{eq, r12, r5}, "eq, r12, r5", "eq_r12_r5"},
- {{eq, r12, r6}, "eq, r12, r6", "eq_r12_r6"},
- {{eq, r12, r7}, "eq, r12, r7", "eq_r12_r7"},
- {{eq, r12, r8}, "eq, r12, r8", "eq_r12_r8"},
- {{eq, r12, r9}, "eq, r12, r9", "eq_r12_r9"},
- {{eq, r12, r10}, "eq, r12, r10", "eq_r12_r10"},
- {{eq, r12, r11}, "eq, r12, r11", "eq_r12_r11"},
- {{eq, r12, r12}, "eq, r12, r12", "eq_r12_r12"},
- {{eq, r12, r13}, "eq, r12, r13", "eq_r12_r13"},
- {{eq, r12, r14}, "eq, r12, r14", "eq_r12_r14"},
- {{eq, r13, r0}, "eq, r13, r0", "eq_r13_r0"},
- {{eq, r13, r1}, "eq, r13, r1", "eq_r13_r1"},
- {{eq, r13, r2}, "eq, r13, r2", "eq_r13_r2"},
- {{eq, r13, r3}, "eq, r13, r3", "eq_r13_r3"},
- {{eq, r13, r4}, "eq, r13, r4", "eq_r13_r4"},
- {{eq, r13, r5}, "eq, r13, r5", "eq_r13_r5"},
- {{eq, r13, r6}, "eq, r13, r6", "eq_r13_r6"},
- {{eq, r13, r7}, "eq, r13, r7", "eq_r13_r7"},
- {{eq, r13, r8}, "eq, r13, r8", "eq_r13_r8"},
- {{eq, r13, r9}, "eq, r13, r9", "eq_r13_r9"},
- {{eq, r13, r10}, "eq, r13, r10", "eq_r13_r10"},
- {{eq, r13, r11}, "eq, r13, r11", "eq_r13_r11"},
- {{eq, r13, r12}, "eq, r13, r12", "eq_r13_r12"},
- {{eq, r13, r13}, "eq, r13, r13", "eq_r13_r13"},
- {{eq, r13, r14}, "eq, r13, r14", "eq_r13_r14"},
- {{eq, r14, r0}, "eq, r14, r0", "eq_r14_r0"},
- {{eq, r14, r1}, "eq, r14, r1", "eq_r14_r1"},
- {{eq, r14, r2}, "eq, r14, r2", "eq_r14_r2"},
- {{eq, r14, r3}, "eq, r14, r3", "eq_r14_r3"},
- {{eq, r14, r4}, "eq, r14, r4", "eq_r14_r4"},
- {{eq, r14, r5}, "eq, r14, r5", "eq_r14_r5"},
- {{eq, r14, r6}, "eq, r14, r6", "eq_r14_r6"},
- {{eq, r14, r7}, "eq, r14, r7", "eq_r14_r7"},
- {{eq, r14, r8}, "eq, r14, r8", "eq_r14_r8"},
- {{eq, r14, r9}, "eq, r14, r9", "eq_r14_r9"},
- {{eq, r14, r10}, "eq, r14, r10", "eq_r14_r10"},
- {{eq, r14, r11}, "eq, r14, r11", "eq_r14_r11"},
- {{eq, r14, r12}, "eq, r14, r12", "eq_r14_r12"},
- {{eq, r14, r13}, "eq, r14, r13", "eq_r14_r13"},
- {{eq, r14, r14}, "eq, r14, r14", "eq_r14_r14"},
- {{ne, r0, r0}, "ne, r0, r0", "ne_r0_r0"},
- {{ne, r0, r1}, "ne, r0, r1", "ne_r0_r1"},
- {{ne, r0, r2}, "ne, r0, r2", "ne_r0_r2"},
- {{ne, r0, r3}, "ne, r0, r3", "ne_r0_r3"},
- {{ne, r0, r4}, "ne, r0, r4", "ne_r0_r4"},
- {{ne, r0, r5}, "ne, r0, r5", "ne_r0_r5"},
- {{ne, r0, r6}, "ne, r0, r6", "ne_r0_r6"},
- {{ne, r0, r7}, "ne, r0, r7", "ne_r0_r7"},
- {{ne, r0, r8}, "ne, r0, r8", "ne_r0_r8"},
- {{ne, r0, r9}, "ne, r0, r9", "ne_r0_r9"},
- {{ne, r0, r10}, "ne, r0, r10", "ne_r0_r10"},
- {{ne, r0, r11}, "ne, r0, r11", "ne_r0_r11"},
- {{ne, r0, r12}, "ne, r0, r12", "ne_r0_r12"},
- {{ne, r0, r13}, "ne, r0, r13", "ne_r0_r13"},
- {{ne, r0, r14}, "ne, r0, r14", "ne_r0_r14"},
- {{ne, r1, r0}, "ne, r1, r0", "ne_r1_r0"},
- {{ne, r1, r1}, "ne, r1, r1", "ne_r1_r1"},
- {{ne, r1, r2}, "ne, r1, r2", "ne_r1_r2"},
- {{ne, r1, r3}, "ne, r1, r3", "ne_r1_r3"},
- {{ne, r1, r4}, "ne, r1, r4", "ne_r1_r4"},
- {{ne, r1, r5}, "ne, r1, r5", "ne_r1_r5"},
- {{ne, r1, r6}, "ne, r1, r6", "ne_r1_r6"},
- {{ne, r1, r7}, "ne, r1, r7", "ne_r1_r7"},
- {{ne, r1, r8}, "ne, r1, r8", "ne_r1_r8"},
- {{ne, r1, r9}, "ne, r1, r9", "ne_r1_r9"},
- {{ne, r1, r10}, "ne, r1, r10", "ne_r1_r10"},
- {{ne, r1, r11}, "ne, r1, r11", "ne_r1_r11"},
- {{ne, r1, r12}, "ne, r1, r12", "ne_r1_r12"},
- {{ne, r1, r13}, "ne, r1, r13", "ne_r1_r13"},
- {{ne, r1, r14}, "ne, r1, r14", "ne_r1_r14"},
- {{ne, r2, r0}, "ne, r2, r0", "ne_r2_r0"},
- {{ne, r2, r1}, "ne, r2, r1", "ne_r2_r1"},
- {{ne, r2, r2}, "ne, r2, r2", "ne_r2_r2"},
- {{ne, r2, r3}, "ne, r2, r3", "ne_r2_r3"},
- {{ne, r2, r4}, "ne, r2, r4", "ne_r2_r4"},
- {{ne, r2, r5}, "ne, r2, r5", "ne_r2_r5"},
- {{ne, r2, r6}, "ne, r2, r6", "ne_r2_r6"},
- {{ne, r2, r7}, "ne, r2, r7", "ne_r2_r7"},
- {{ne, r2, r8}, "ne, r2, r8", "ne_r2_r8"},
- {{ne, r2, r9}, "ne, r2, r9", "ne_r2_r9"},
- {{ne, r2, r10}, "ne, r2, r10", "ne_r2_r10"},
- {{ne, r2, r11}, "ne, r2, r11", "ne_r2_r11"},
- {{ne, r2, r12}, "ne, r2, r12", "ne_r2_r12"},
- {{ne, r2, r13}, "ne, r2, r13", "ne_r2_r13"},
- {{ne, r2, r14}, "ne, r2, r14", "ne_r2_r14"},
- {{ne, r3, r0}, "ne, r3, r0", "ne_r3_r0"},
- {{ne, r3, r1}, "ne, r3, r1", "ne_r3_r1"},
- {{ne, r3, r2}, "ne, r3, r2", "ne_r3_r2"},
- {{ne, r3, r3}, "ne, r3, r3", "ne_r3_r3"},
- {{ne, r3, r4}, "ne, r3, r4", "ne_r3_r4"},
- {{ne, r3, r5}, "ne, r3, r5", "ne_r3_r5"},
- {{ne, r3, r6}, "ne, r3, r6", "ne_r3_r6"},
- {{ne, r3, r7}, "ne, r3, r7", "ne_r3_r7"},
- {{ne, r3, r8}, "ne, r3, r8", "ne_r3_r8"},
- {{ne, r3, r9}, "ne, r3, r9", "ne_r3_r9"},
- {{ne, r3, r10}, "ne, r3, r10", "ne_r3_r10"},
- {{ne, r3, r11}, "ne, r3, r11", "ne_r3_r11"},
- {{ne, r3, r12}, "ne, r3, r12", "ne_r3_r12"},
- {{ne, r3, r13}, "ne, r3, r13", "ne_r3_r13"},
- {{ne, r3, r14}, "ne, r3, r14", "ne_r3_r14"},
- {{ne, r4, r0}, "ne, r4, r0", "ne_r4_r0"},
- {{ne, r4, r1}, "ne, r4, r1", "ne_r4_r1"},
- {{ne, r4, r2}, "ne, r4, r2", "ne_r4_r2"},
- {{ne, r4, r3}, "ne, r4, r3", "ne_r4_r3"},
- {{ne, r4, r4}, "ne, r4, r4", "ne_r4_r4"},
- {{ne, r4, r5}, "ne, r4, r5", "ne_r4_r5"},
- {{ne, r4, r6}, "ne, r4, r6", "ne_r4_r6"},
- {{ne, r4, r7}, "ne, r4, r7", "ne_r4_r7"},
- {{ne, r4, r8}, "ne, r4, r8", "ne_r4_r8"},
- {{ne, r4, r9}, "ne, r4, r9", "ne_r4_r9"},
- {{ne, r4, r10}, "ne, r4, r10", "ne_r4_r10"},
- {{ne, r4, r11}, "ne, r4, r11", "ne_r4_r11"},
- {{ne, r4, r12}, "ne, r4, r12", "ne_r4_r12"},
- {{ne, r4, r13}, "ne, r4, r13", "ne_r4_r13"},
- {{ne, r4, r14}, "ne, r4, r14", "ne_r4_r14"},
- {{ne, r5, r0}, "ne, r5, r0", "ne_r5_r0"},
- {{ne, r5, r1}, "ne, r5, r1", "ne_r5_r1"},
- {{ne, r5, r2}, "ne, r5, r2", "ne_r5_r2"},
- {{ne, r5, r3}, "ne, r5, r3", "ne_r5_r3"},
- {{ne, r5, r4}, "ne, r5, r4", "ne_r5_r4"},
- {{ne, r5, r5}, "ne, r5, r5", "ne_r5_r5"},
- {{ne, r5, r6}, "ne, r5, r6", "ne_r5_r6"},
- {{ne, r5, r7}, "ne, r5, r7", "ne_r5_r7"},
- {{ne, r5, r8}, "ne, r5, r8", "ne_r5_r8"},
- {{ne, r5, r9}, "ne, r5, r9", "ne_r5_r9"},
- {{ne, r5, r10}, "ne, r5, r10", "ne_r5_r10"},
- {{ne, r5, r11}, "ne, r5, r11", "ne_r5_r11"},
- {{ne, r5, r12}, "ne, r5, r12", "ne_r5_r12"},
- {{ne, r5, r13}, "ne, r5, r13", "ne_r5_r13"},
- {{ne, r5, r14}, "ne, r5, r14", "ne_r5_r14"},
- {{ne, r6, r0}, "ne, r6, r0", "ne_r6_r0"},
- {{ne, r6, r1}, "ne, r6, r1", "ne_r6_r1"},
- {{ne, r6, r2}, "ne, r6, r2", "ne_r6_r2"},
- {{ne, r6, r3}, "ne, r6, r3", "ne_r6_r3"},
- {{ne, r6, r4}, "ne, r6, r4", "ne_r6_r4"},
- {{ne, r6, r5}, "ne, r6, r5", "ne_r6_r5"},
- {{ne, r6, r6}, "ne, r6, r6", "ne_r6_r6"},
- {{ne, r6, r7}, "ne, r6, r7", "ne_r6_r7"},
- {{ne, r6, r8}, "ne, r6, r8", "ne_r6_r8"},
- {{ne, r6, r9}, "ne, r6, r9", "ne_r6_r9"},
- {{ne, r6, r10}, "ne, r6, r10", "ne_r6_r10"},
- {{ne, r6, r11}, "ne, r6, r11", "ne_r6_r11"},
- {{ne, r6, r12}, "ne, r6, r12", "ne_r6_r12"},
- {{ne, r6, r13}, "ne, r6, r13", "ne_r6_r13"},
- {{ne, r6, r14}, "ne, r6, r14", "ne_r6_r14"},
- {{ne, r7, r0}, "ne, r7, r0", "ne_r7_r0"},
- {{ne, r7, r1}, "ne, r7, r1", "ne_r7_r1"},
- {{ne, r7, r2}, "ne, r7, r2", "ne_r7_r2"},
- {{ne, r7, r3}, "ne, r7, r3", "ne_r7_r3"},
- {{ne, r7, r4}, "ne, r7, r4", "ne_r7_r4"},
- {{ne, r7, r5}, "ne, r7, r5", "ne_r7_r5"},
- {{ne, r7, r6}, "ne, r7, r6", "ne_r7_r6"},
- {{ne, r7, r7}, "ne, r7, r7", "ne_r7_r7"},
- {{ne, r7, r8}, "ne, r7, r8", "ne_r7_r8"},
- {{ne, r7, r9}, "ne, r7, r9", "ne_r7_r9"},
- {{ne, r7, r10}, "ne, r7, r10", "ne_r7_r10"},
- {{ne, r7, r11}, "ne, r7, r11", "ne_r7_r11"},
- {{ne, r7, r12}, "ne, r7, r12", "ne_r7_r12"},
- {{ne, r7, r13}, "ne, r7, r13", "ne_r7_r13"},
- {{ne, r7, r14}, "ne, r7, r14", "ne_r7_r14"},
- {{ne, r8, r0}, "ne, r8, r0", "ne_r8_r0"},
- {{ne, r8, r1}, "ne, r8, r1", "ne_r8_r1"},
- {{ne, r8, r2}, "ne, r8, r2", "ne_r8_r2"},
- {{ne, r8, r3}, "ne, r8, r3", "ne_r8_r3"},
+const TestData kTests[] = {{{cs, r12, r1}, "cs, r12, r1", "cs_r12_r1"},
+ {{hi, r6, r12}, "hi, r6, r12", "hi_r6_r12"},
+ {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
+ {{vs, r10, r8}, "vs, r10, r8", "vs_r10_r8"},
+ {{pl, r5, r8}, "pl, r5, r8", "pl_r5_r8"},
+ {{ls, r14, r14}, "ls, r14, r14", "ls_r14_r14"},
+ {{gt, r8, r6}, "gt, r8, r6", "gt_r8_r6"},
+ {{vc, r7, r11}, "vc, r7, r11", "vc_r7_r11"},
+ {{pl, r4, r12}, "pl, r4, r12", "pl_r4_r12"},
+ {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
{{ne, r8, r4}, "ne, r8, r4", "ne_r8_r4"},
- {{ne, r8, r5}, "ne, r8, r5", "ne_r8_r5"},
- {{ne, r8, r6}, "ne, r8, r6", "ne_r8_r6"},
- {{ne, r8, r7}, "ne, r8, r7", "ne_r8_r7"},
- {{ne, r8, r8}, "ne, r8, r8", "ne_r8_r8"},
- {{ne, r8, r9}, "ne, r8, r9", "ne_r8_r9"},
- {{ne, r8, r10}, "ne, r8, r10", "ne_r8_r10"},
- {{ne, r8, r11}, "ne, r8, r11", "ne_r8_r11"},
- {{ne, r8, r12}, "ne, r8, r12", "ne_r8_r12"},
- {{ne, r8, r13}, "ne, r8, r13", "ne_r8_r13"},
- {{ne, r8, r14}, "ne, r8, r14", "ne_r8_r14"},
- {{ne, r9, r0}, "ne, r9, r0", "ne_r9_r0"},
- {{ne, r9, r1}, "ne, r9, r1", "ne_r9_r1"},
- {{ne, r9, r2}, "ne, r9, r2", "ne_r9_r2"},
- {{ne, r9, r3}, "ne, r9, r3", "ne_r9_r3"},
- {{ne, r9, r4}, "ne, r9, r4", "ne_r9_r4"},
- {{ne, r9, r5}, "ne, r9, r5", "ne_r9_r5"},
- {{ne, r9, r6}, "ne, r9, r6", "ne_r9_r6"},
- {{ne, r9, r7}, "ne, r9, r7", "ne_r9_r7"},
- {{ne, r9, r8}, "ne, r9, r8", "ne_r9_r8"},
+ {{le, r1, r11}, "le, r1, r11", "le_r1_r11"},
+ {{cc, r4, r10}, "cc, r4, r10", "cc_r4_r10"},
+ {{gt, r14, r0}, "gt, r14, r0", "gt_r14_r0"},
+ {{cs, r2, r11}, "cs, r2, r11", "cs_r2_r11"},
+ {{al, r3, r12}, "al, r3, r12", "al_r3_r12"},
+ {{hi, r6, r0}, "hi, r6, r0", "hi_r6_r0"},
+ {{ls, r10, r10}, "ls, r10, r10", "ls_r10_r10"},
+ {{ls, r4, r8}, "ls, r4, r8", "ls_r4_r8"},
+ {{le, r8, r0}, "le, r8, r0", "le_r8_r0"},
+ {{pl, r5, r3}, "pl, r5, r3", "pl_r5_r3"},
+ {{ls, r8, r5}, "ls, r8, r5", "ls_r8_r5"},
+ {{ge, r0, r10}, "ge, r0, r10", "ge_r0_r10"},
+ {{lt, r10, r6}, "lt, r10, r6", "lt_r10_r6"},
{{ne, r9, r9}, "ne, r9, r9", "ne_r9_r9"},
- {{ne, r9, r10}, "ne, r9, r10", "ne_r9_r10"},
- {{ne, r9, r11}, "ne, r9, r11", "ne_r9_r11"},
- {{ne, r9, r12}, "ne, r9, r12", "ne_r9_r12"},
- {{ne, r9, r13}, "ne, r9, r13", "ne_r9_r13"},
- {{ne, r9, r14}, "ne, r9, r14", "ne_r9_r14"},
- {{ne, r10, r0}, "ne, r10, r0", "ne_r10_r0"},
- {{ne, r10, r1}, "ne, r10, r1", "ne_r10_r1"},
- {{ne, r10, r2}, "ne, r10, r2", "ne_r10_r2"},
- {{ne, r10, r3}, "ne, r10, r3", "ne_r10_r3"},
- {{ne, r10, r4}, "ne, r10, r4", "ne_r10_r4"},
- {{ne, r10, r5}, "ne, r10, r5", "ne_r10_r5"},
- {{ne, r10, r6}, "ne, r10, r6", "ne_r10_r6"},
- {{ne, r10, r7}, "ne, r10, r7", "ne_r10_r7"},
- {{ne, r10, r8}, "ne, r10, r8", "ne_r10_r8"},
- {{ne, r10, r9}, "ne, r10, r9", "ne_r10_r9"},
- {{ne, r10, r10}, "ne, r10, r10", "ne_r10_r10"},
- {{ne, r10, r11}, "ne, r10, r11", "ne_r10_r11"},
- {{ne, r10, r12}, "ne, r10, r12", "ne_r10_r12"},
- {{ne, r10, r13}, "ne, r10, r13", "ne_r10_r13"},
- {{ne, r10, r14}, "ne, r10, r14", "ne_r10_r14"},
- {{ne, r11, r0}, "ne, r11, r0", "ne_r11_r0"},
- {{ne, r11, r1}, "ne, r11, r1", "ne_r11_r1"},
- {{ne, r11, r2}, "ne, r11, r2", "ne_r11_r2"},
- {{ne, r11, r3}, "ne, r11, r3", "ne_r11_r3"},
- {{ne, r11, r4}, "ne, r11, r4", "ne_r11_r4"},
- {{ne, r11, r5}, "ne, r11, r5", "ne_r11_r5"},
- {{ne, r11, r6}, "ne, r11, r6", "ne_r11_r6"},
- {{ne, r11, r7}, "ne, r11, r7", "ne_r11_r7"},
- {{ne, r11, r8}, "ne, r11, r8", "ne_r11_r8"},
- {{ne, r11, r9}, "ne, r11, r9", "ne_r11_r9"},
- {{ne, r11, r10}, "ne, r11, r10", "ne_r11_r10"},
- {{ne, r11, r11}, "ne, r11, r11", "ne_r11_r11"},
- {{ne, r11, r12}, "ne, r11, r12", "ne_r11_r12"},
- {{ne, r11, r13}, "ne, r11, r13", "ne_r11_r13"},
- {{ne, r11, r14}, "ne, r11, r14", "ne_r11_r14"},
- {{ne, r12, r0}, "ne, r12, r0", "ne_r12_r0"},
- {{ne, r12, r1}, "ne, r12, r1", "ne_r12_r1"},
- {{ne, r12, r2}, "ne, r12, r2", "ne_r12_r2"},
- {{ne, r12, r3}, "ne, r12, r3", "ne_r12_r3"},
- {{ne, r12, r4}, "ne, r12, r4", "ne_r12_r4"},
- {{ne, r12, r5}, "ne, r12, r5", "ne_r12_r5"},
- {{ne, r12, r6}, "ne, r12, r6", "ne_r12_r6"},
- {{ne, r12, r7}, "ne, r12, r7", "ne_r12_r7"},
- {{ne, r12, r8}, "ne, r12, r8", "ne_r12_r8"},
- {{ne, r12, r9}, "ne, r12, r9", "ne_r12_r9"},
- {{ne, r12, r10}, "ne, r12, r10", "ne_r12_r10"},
- {{ne, r12, r11}, "ne, r12, r11", "ne_r12_r11"},
- {{ne, r12, r12}, "ne, r12, r12", "ne_r12_r12"},
- {{ne, r12, r13}, "ne, r12, r13", "ne_r12_r13"},
- {{ne, r12, r14}, "ne, r12, r14", "ne_r12_r14"},
- {{ne, r13, r0}, "ne, r13, r0", "ne_r13_r0"},
- {{ne, r13, r1}, "ne, r13, r1", "ne_r13_r1"},
- {{ne, r13, r2}, "ne, r13, r2", "ne_r13_r2"},
- {{ne, r13, r3}, "ne, r13, r3", "ne_r13_r3"},
- {{ne, r13, r4}, "ne, r13, r4", "ne_r13_r4"},
- {{ne, r13, r5}, "ne, r13, r5", "ne_r13_r5"},
- {{ne, r13, r6}, "ne, r13, r6", "ne_r13_r6"},
- {{ne, r13, r7}, "ne, r13, r7", "ne_r13_r7"},
- {{ne, r13, r8}, "ne, r13, r8", "ne_r13_r8"},
+ {{hi, r5, r0}, "hi, r5, r0", "hi_r5_r0"},
+ {{pl, r10, r6}, "pl, r10, r6", "pl_r10_r6"},
+ {{vs, r1, r3}, "vs, r1, r3", "vs_r1_r3"},
+ {{vs, r9, r8}, "vs, r9, r8", "vs_r9_r8"},
+ {{cc, r2, r10}, "cc, r2, r10", "cc_r2_r10"},
+ {{cs, r11, r3}, "cs, r11, r3", "cs_r11_r3"},
+ {{hi, r8, r2}, "hi, r8, r2", "hi_r8_r2"},
+ {{pl, r6, r0}, "pl, r6, r0", "pl_r6_r0"},
+ {{hi, r9, r2}, "hi, r9, r2", "hi_r9_r2"},
+ {{al, r14, r11}, "al, r14, r11", "al_r14_r11"},
+ {{eq, r8, r13}, "eq, r8, r13", "eq_r8_r13"},
+ {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"},
+ {{cc, r2, r6}, "cc, r2, r6", "cc_r2_r6"},
{{ne, r13, r9}, "ne, r13, r9", "ne_r13_r9"},
{{ne, r13, r10}, "ne, r13, r10", "ne_r13_r10"},
- {{ne, r13, r11}, "ne, r13, r11", "ne_r13_r11"},
- {{ne, r13, r12}, "ne, r13, r12", "ne_r13_r12"},
- {{ne, r13, r13}, "ne, r13, r13", "ne_r13_r13"},
- {{ne, r13, r14}, "ne, r13, r14", "ne_r13_r14"},
- {{ne, r14, r0}, "ne, r14, r0", "ne_r14_r0"},
- {{ne, r14, r1}, "ne, r14, r1", "ne_r14_r1"},
- {{ne, r14, r2}, "ne, r14, r2", "ne_r14_r2"},
- {{ne, r14, r3}, "ne, r14, r3", "ne_r14_r3"},
- {{ne, r14, r4}, "ne, r14, r4", "ne_r14_r4"},
- {{ne, r14, r5}, "ne, r14, r5", "ne_r14_r5"},
- {{ne, r14, r6}, "ne, r14, r6", "ne_r14_r6"},
- {{ne, r14, r7}, "ne, r14, r7", "ne_r14_r7"},
- {{ne, r14, r8}, "ne, r14, r8", "ne_r14_r8"},
- {{ne, r14, r9}, "ne, r14, r9", "ne_r14_r9"},
- {{ne, r14, r10}, "ne, r14, r10", "ne_r14_r10"},
- {{ne, r14, r11}, "ne, r14, r11", "ne_r14_r11"},
- {{ne, r14, r12}, "ne, r14, r12", "ne_r14_r12"},
- {{ne, r14, r13}, "ne, r14, r13", "ne_r14_r13"},
- {{ne, r14, r14}, "ne, r14, r14", "ne_r14_r14"},
- {{cs, r0, r0}, "cs, r0, r0", "cs_r0_r0"},
- {{cs, r0, r1}, "cs, r0, r1", "cs_r0_r1"},
- {{cs, r0, r2}, "cs, r0, r2", "cs_r0_r2"},
- {{cs, r0, r3}, "cs, r0, r3", "cs_r0_r3"},
- {{cs, r0, r4}, "cs, r0, r4", "cs_r0_r4"},
- {{cs, r0, r5}, "cs, r0, r5", "cs_r0_r5"},
- {{cs, r0, r6}, "cs, r0, r6", "cs_r0_r6"},
- {{cs, r0, r7}, "cs, r0, r7", "cs_r0_r7"},
- {{cs, r0, r8}, "cs, r0, r8", "cs_r0_r8"},
- {{cs, r0, r9}, "cs, r0, r9", "cs_r0_r9"},
- {{cs, r0, r10}, "cs, r0, r10", "cs_r0_r10"},
- {{cs, r0, r11}, "cs, r0, r11", "cs_r0_r11"},
- {{cs, r0, r12}, "cs, r0, r12", "cs_r0_r12"},
- {{cs, r0, r13}, "cs, r0, r13", "cs_r0_r13"},
- {{cs, r0, r14}, "cs, r0, r14", "cs_r0_r14"},
- {{cs, r1, r0}, "cs, r1, r0", "cs_r1_r0"},
- {{cs, r1, r1}, "cs, r1, r1", "cs_r1_r1"},
- {{cs, r1, r2}, "cs, r1, r2", "cs_r1_r2"},
- {{cs, r1, r3}, "cs, r1, r3", "cs_r1_r3"},
- {{cs, r1, r4}, "cs, r1, r4", "cs_r1_r4"},
- {{cs, r1, r5}, "cs, r1, r5", "cs_r1_r5"},
- {{cs, r1, r6}, "cs, r1, r6", "cs_r1_r6"},
- {{cs, r1, r7}, "cs, r1, r7", "cs_r1_r7"},
- {{cs, r1, r8}, "cs, r1, r8", "cs_r1_r8"},
- {{cs, r1, r9}, "cs, r1, r9", "cs_r1_r9"},
- {{cs, r1, r10}, "cs, r1, r10", "cs_r1_r10"},
- {{cs, r1, r11}, "cs, r1, r11", "cs_r1_r11"},
- {{cs, r1, r12}, "cs, r1, r12", "cs_r1_r12"},
- {{cs, r1, r13}, "cs, r1, r13", "cs_r1_r13"},
- {{cs, r1, r14}, "cs, r1, r14", "cs_r1_r14"},
- {{cs, r2, r0}, "cs, r2, r0", "cs_r2_r0"},
- {{cs, r2, r1}, "cs, r2, r1", "cs_r2_r1"},
- {{cs, r2, r2}, "cs, r2, r2", "cs_r2_r2"},
- {{cs, r2, r3}, "cs, r2, r3", "cs_r2_r3"},
- {{cs, r2, r4}, "cs, r2, r4", "cs_r2_r4"},
- {{cs, r2, r5}, "cs, r2, r5", "cs_r2_r5"},
- {{cs, r2, r6}, "cs, r2, r6", "cs_r2_r6"},
- {{cs, r2, r7}, "cs, r2, r7", "cs_r2_r7"},
- {{cs, r2, r8}, "cs, r2, r8", "cs_r2_r8"},
- {{cs, r2, r9}, "cs, r2, r9", "cs_r2_r9"},
- {{cs, r2, r10}, "cs, r2, r10", "cs_r2_r10"},
- {{cs, r2, r11}, "cs, r2, r11", "cs_r2_r11"},
- {{cs, r2, r12}, "cs, r2, r12", "cs_r2_r12"},
- {{cs, r2, r13}, "cs, r2, r13", "cs_r2_r13"},
- {{cs, r2, r14}, "cs, r2, r14", "cs_r2_r14"},
- {{cs, r3, r0}, "cs, r3, r0", "cs_r3_r0"},
- {{cs, r3, r1}, "cs, r3, r1", "cs_r3_r1"},
- {{cs, r3, r2}, "cs, r3, r2", "cs_r3_r2"},
- {{cs, r3, r3}, "cs, r3, r3", "cs_r3_r3"},
- {{cs, r3, r4}, "cs, r3, r4", "cs_r3_r4"},
- {{cs, r3, r5}, "cs, r3, r5", "cs_r3_r5"},
- {{cs, r3, r6}, "cs, r3, r6", "cs_r3_r6"},
- {{cs, r3, r7}, "cs, r3, r7", "cs_r3_r7"},
- {{cs, r3, r8}, "cs, r3, r8", "cs_r3_r8"},
- {{cs, r3, r9}, "cs, r3, r9", "cs_r3_r9"},
- {{cs, r3, r10}, "cs, r3, r10", "cs_r3_r10"},
- {{cs, r3, r11}, "cs, r3, r11", "cs_r3_r11"},
- {{cs, r3, r12}, "cs, r3, r12", "cs_r3_r12"},
- {{cs, r3, r13}, "cs, r3, r13", "cs_r3_r13"},
- {{cs, r3, r14}, "cs, r3, r14", "cs_r3_r14"},
- {{cs, r4, r0}, "cs, r4, r0", "cs_r4_r0"},
- {{cs, r4, r1}, "cs, r4, r1", "cs_r4_r1"},
- {{cs, r4, r2}, "cs, r4, r2", "cs_r4_r2"},
- {{cs, r4, r3}, "cs, r4, r3", "cs_r4_r3"},
- {{cs, r4, r4}, "cs, r4, r4", "cs_r4_r4"},
- {{cs, r4, r5}, "cs, r4, r5", "cs_r4_r5"},
- {{cs, r4, r6}, "cs, r4, r6", "cs_r4_r6"},
- {{cs, r4, r7}, "cs, r4, r7", "cs_r4_r7"},
- {{cs, r4, r8}, "cs, r4, r8", "cs_r4_r8"},
- {{cs, r4, r9}, "cs, r4, r9", "cs_r4_r9"},
- {{cs, r4, r10}, "cs, r4, r10", "cs_r4_r10"},
- {{cs, r4, r11}, "cs, r4, r11", "cs_r4_r11"},
- {{cs, r4, r12}, "cs, r4, r12", "cs_r4_r12"},
- {{cs, r4, r13}, "cs, r4, r13", "cs_r4_r13"},
- {{cs, r4, r14}, "cs, r4, r14", "cs_r4_r14"},
- {{cs, r5, r0}, "cs, r5, r0", "cs_r5_r0"},
- {{cs, r5, r1}, "cs, r5, r1", "cs_r5_r1"},
- {{cs, r5, r2}, "cs, r5, r2", "cs_r5_r2"},
- {{cs, r5, r3}, "cs, r5, r3", "cs_r5_r3"},
- {{cs, r5, r4}, "cs, r5, r4", "cs_r5_r4"},
- {{cs, r5, r5}, "cs, r5, r5", "cs_r5_r5"},
- {{cs, r5, r6}, "cs, r5, r6", "cs_r5_r6"},
- {{cs, r5, r7}, "cs, r5, r7", "cs_r5_r7"},
- {{cs, r5, r8}, "cs, r5, r8", "cs_r5_r8"},
- {{cs, r5, r9}, "cs, r5, r9", "cs_r5_r9"},
- {{cs, r5, r10}, "cs, r5, r10", "cs_r5_r10"},
- {{cs, r5, r11}, "cs, r5, r11", "cs_r5_r11"},
- {{cs, r5, r12}, "cs, r5, r12", "cs_r5_r12"},
- {{cs, r5, r13}, "cs, r5, r13", "cs_r5_r13"},
- {{cs, r5, r14}, "cs, r5, r14", "cs_r5_r14"},
- {{cs, r6, r0}, "cs, r6, r0", "cs_r6_r0"},
- {{cs, r6, r1}, "cs, r6, r1", "cs_r6_r1"},
- {{cs, r6, r2}, "cs, r6, r2", "cs_r6_r2"},
- {{cs, r6, r3}, "cs, r6, r3", "cs_r6_r3"},
- {{cs, r6, r4}, "cs, r6, r4", "cs_r6_r4"},
- {{cs, r6, r5}, "cs, r6, r5", "cs_r6_r5"},
- {{cs, r6, r6}, "cs, r6, r6", "cs_r6_r6"},
- {{cs, r6, r7}, "cs, r6, r7", "cs_r6_r7"},
- {{cs, r6, r8}, "cs, r6, r8", "cs_r6_r8"},
- {{cs, r6, r9}, "cs, r6, r9", "cs_r6_r9"},
- {{cs, r6, r10}, "cs, r6, r10", "cs_r6_r10"},
- {{cs, r6, r11}, "cs, r6, r11", "cs_r6_r11"},
- {{cs, r6, r12}, "cs, r6, r12", "cs_r6_r12"},
- {{cs, r6, r13}, "cs, r6, r13", "cs_r6_r13"},
- {{cs, r6, r14}, "cs, r6, r14", "cs_r6_r14"},
- {{cs, r7, r0}, "cs, r7, r0", "cs_r7_r0"},
- {{cs, r7, r1}, "cs, r7, r1", "cs_r7_r1"},
- {{cs, r7, r2}, "cs, r7, r2", "cs_r7_r2"},
- {{cs, r7, r3}, "cs, r7, r3", "cs_r7_r3"},
- {{cs, r7, r4}, "cs, r7, r4", "cs_r7_r4"},
- {{cs, r7, r5}, "cs, r7, r5", "cs_r7_r5"},
- {{cs, r7, r6}, "cs, r7, r6", "cs_r7_r6"},
- {{cs, r7, r7}, "cs, r7, r7", "cs_r7_r7"},
- {{cs, r7, r8}, "cs, r7, r8", "cs_r7_r8"},
- {{cs, r7, r9}, "cs, r7, r9", "cs_r7_r9"},
- {{cs, r7, r10}, "cs, r7, r10", "cs_r7_r10"},
- {{cs, r7, r11}, "cs, r7, r11", "cs_r7_r11"},
- {{cs, r7, r12}, "cs, r7, r12", "cs_r7_r12"},
- {{cs, r7, r13}, "cs, r7, r13", "cs_r7_r13"},
- {{cs, r7, r14}, "cs, r7, r14", "cs_r7_r14"},
- {{cs, r8, r0}, "cs, r8, r0", "cs_r8_r0"},
- {{cs, r8, r1}, "cs, r8, r1", "cs_r8_r1"},
- {{cs, r8, r2}, "cs, r8, r2", "cs_r8_r2"},
- {{cs, r8, r3}, "cs, r8, r3", "cs_r8_r3"},
- {{cs, r8, r4}, "cs, r8, r4", "cs_r8_r4"},
- {{cs, r8, r5}, "cs, r8, r5", "cs_r8_r5"},
- {{cs, r8, r6}, "cs, r8, r6", "cs_r8_r6"},
- {{cs, r8, r7}, "cs, r8, r7", "cs_r8_r7"},
- {{cs, r8, r8}, "cs, r8, r8", "cs_r8_r8"},
- {{cs, r8, r9}, "cs, r8, r9", "cs_r8_r9"},
- {{cs, r8, r10}, "cs, r8, r10", "cs_r8_r10"},
- {{cs, r8, r11}, "cs, r8, r11", "cs_r8_r11"},
- {{cs, r8, r12}, "cs, r8, r12", "cs_r8_r12"},
- {{cs, r8, r13}, "cs, r8, r13", "cs_r8_r13"},
- {{cs, r8, r14}, "cs, r8, r14", "cs_r8_r14"},
- {{cs, r9, r0}, "cs, r9, r0", "cs_r9_r0"},
- {{cs, r9, r1}, "cs, r9, r1", "cs_r9_r1"},
- {{cs, r9, r2}, "cs, r9, r2", "cs_r9_r2"},
- {{cs, r9, r3}, "cs, r9, r3", "cs_r9_r3"},
- {{cs, r9, r4}, "cs, r9, r4", "cs_r9_r4"},
- {{cs, r9, r5}, "cs, r9, r5", "cs_r9_r5"},
- {{cs, r9, r6}, "cs, r9, r6", "cs_r9_r6"},
- {{cs, r9, r7}, "cs, r9, r7", "cs_r9_r7"},
- {{cs, r9, r8}, "cs, r9, r8", "cs_r9_r8"},
- {{cs, r9, r9}, "cs, r9, r9", "cs_r9_r9"},
- {{cs, r9, r10}, "cs, r9, r10", "cs_r9_r10"},
- {{cs, r9, r11}, "cs, r9, r11", "cs_r9_r11"},
- {{cs, r9, r12}, "cs, r9, r12", "cs_r9_r12"},
- {{cs, r9, r13}, "cs, r9, r13", "cs_r9_r13"},
- {{cs, r9, r14}, "cs, r9, r14", "cs_r9_r14"},
- {{cs, r10, r0}, "cs, r10, r0", "cs_r10_r0"},
- {{cs, r10, r1}, "cs, r10, r1", "cs_r10_r1"},
- {{cs, r10, r2}, "cs, r10, r2", "cs_r10_r2"},
- {{cs, r10, r3}, "cs, r10, r3", "cs_r10_r3"},
- {{cs, r10, r4}, "cs, r10, r4", "cs_r10_r4"},
- {{cs, r10, r5}, "cs, r10, r5", "cs_r10_r5"},
- {{cs, r10, r6}, "cs, r10, r6", "cs_r10_r6"},
- {{cs, r10, r7}, "cs, r10, r7", "cs_r10_r7"},
- {{cs, r10, r8}, "cs, r10, r8", "cs_r10_r8"},
- {{cs, r10, r9}, "cs, r10, r9", "cs_r10_r9"},
- {{cs, r10, r10}, "cs, r10, r10", "cs_r10_r10"},
- {{cs, r10, r11}, "cs, r10, r11", "cs_r10_r11"},
- {{cs, r10, r12}, "cs, r10, r12", "cs_r10_r12"},
- {{cs, r10, r13}, "cs, r10, r13", "cs_r10_r13"},
- {{cs, r10, r14}, "cs, r10, r14", "cs_r10_r14"},
- {{cs, r11, r0}, "cs, r11, r0", "cs_r11_r0"},
- {{cs, r11, r1}, "cs, r11, r1", "cs_r11_r1"},
- {{cs, r11, r2}, "cs, r11, r2", "cs_r11_r2"},
- {{cs, r11, r3}, "cs, r11, r3", "cs_r11_r3"},
- {{cs, r11, r4}, "cs, r11, r4", "cs_r11_r4"},
- {{cs, r11, r5}, "cs, r11, r5", "cs_r11_r5"},
- {{cs, r11, r6}, "cs, r11, r6", "cs_r11_r6"},
- {{cs, r11, r7}, "cs, r11, r7", "cs_r11_r7"},
- {{cs, r11, r8}, "cs, r11, r8", "cs_r11_r8"},
- {{cs, r11, r9}, "cs, r11, r9", "cs_r11_r9"},
- {{cs, r11, r10}, "cs, r11, r10", "cs_r11_r10"},
- {{cs, r11, r11}, "cs, r11, r11", "cs_r11_r11"},
- {{cs, r11, r12}, "cs, r11, r12", "cs_r11_r12"},
- {{cs, r11, r13}, "cs, r11, r13", "cs_r11_r13"},
- {{cs, r11, r14}, "cs, r11, r14", "cs_r11_r14"},
- {{cs, r12, r0}, "cs, r12, r0", "cs_r12_r0"},
- {{cs, r12, r1}, "cs, r12, r1", "cs_r12_r1"},
- {{cs, r12, r2}, "cs, r12, r2", "cs_r12_r2"},
- {{cs, r12, r3}, "cs, r12, r3", "cs_r12_r3"},
- {{cs, r12, r4}, "cs, r12, r4", "cs_r12_r4"},
- {{cs, r12, r5}, "cs, r12, r5", "cs_r12_r5"},
- {{cs, r12, r6}, "cs, r12, r6", "cs_r12_r6"},
- {{cs, r12, r7}, "cs, r12, r7", "cs_r12_r7"},
- {{cs, r12, r8}, "cs, r12, r8", "cs_r12_r8"},
- {{cs, r12, r9}, "cs, r12, r9", "cs_r12_r9"},
- {{cs, r12, r10}, "cs, r12, r10", "cs_r12_r10"},
- {{cs, r12, r11}, "cs, r12, r11", "cs_r12_r11"},
- {{cs, r12, r12}, "cs, r12, r12", "cs_r12_r12"},
- {{cs, r12, r13}, "cs, r12, r13", "cs_r12_r13"},
- {{cs, r12, r14}, "cs, r12, r14", "cs_r12_r14"},
- {{cs, r13, r0}, "cs, r13, r0", "cs_r13_r0"},
- {{cs, r13, r1}, "cs, r13, r1", "cs_r13_r1"},
- {{cs, r13, r2}, "cs, r13, r2", "cs_r13_r2"},
- {{cs, r13, r3}, "cs, r13, r3", "cs_r13_r3"},
- {{cs, r13, r4}, "cs, r13, r4", "cs_r13_r4"},
- {{cs, r13, r5}, "cs, r13, r5", "cs_r13_r5"},
- {{cs, r13, r6}, "cs, r13, r6", "cs_r13_r6"},
- {{cs, r13, r7}, "cs, r13, r7", "cs_r13_r7"},
- {{cs, r13, r8}, "cs, r13, r8", "cs_r13_r8"},
- {{cs, r13, r9}, "cs, r13, r9", "cs_r13_r9"},
- {{cs, r13, r10}, "cs, r13, r10", "cs_r13_r10"},
- {{cs, r13, r11}, "cs, r13, r11", "cs_r13_r11"},
- {{cs, r13, r12}, "cs, r13, r12", "cs_r13_r12"},
- {{cs, r13, r13}, "cs, r13, r13", "cs_r13_r13"},
- {{cs, r13, r14}, "cs, r13, r14", "cs_r13_r14"},
- {{cs, r14, r0}, "cs, r14, r0", "cs_r14_r0"},
- {{cs, r14, r1}, "cs, r14, r1", "cs_r14_r1"},
- {{cs, r14, r2}, "cs, r14, r2", "cs_r14_r2"},
- {{cs, r14, r3}, "cs, r14, r3", "cs_r14_r3"},
- {{cs, r14, r4}, "cs, r14, r4", "cs_r14_r4"},
- {{cs, r14, r5}, "cs, r14, r5", "cs_r14_r5"},
- {{cs, r14, r6}, "cs, r14, r6", "cs_r14_r6"},
- {{cs, r14, r7}, "cs, r14, r7", "cs_r14_r7"},
- {{cs, r14, r8}, "cs, r14, r8", "cs_r14_r8"},
- {{cs, r14, r9}, "cs, r14, r9", "cs_r14_r9"},
- {{cs, r14, r10}, "cs, r14, r10", "cs_r14_r10"},
- {{cs, r14, r11}, "cs, r14, r11", "cs_r14_r11"},
- {{cs, r14, r12}, "cs, r14, r12", "cs_r14_r12"},
- {{cs, r14, r13}, "cs, r14, r13", "cs_r14_r13"},
- {{cs, r14, r14}, "cs, r14, r14", "cs_r14_r14"},
- {{cc, r0, r0}, "cc, r0, r0", "cc_r0_r0"},
- {{cc, r0, r1}, "cc, r0, r1", "cc_r0_r1"},
- {{cc, r0, r2}, "cc, r0, r2", "cc_r0_r2"},
- {{cc, r0, r3}, "cc, r0, r3", "cc_r0_r3"},
- {{cc, r0, r4}, "cc, r0, r4", "cc_r0_r4"},
- {{cc, r0, r5}, "cc, r0, r5", "cc_r0_r5"},
- {{cc, r0, r6}, "cc, r0, r6", "cc_r0_r6"},
- {{cc, r0, r7}, "cc, r0, r7", "cc_r0_r7"},
- {{cc, r0, r8}, "cc, r0, r8", "cc_r0_r8"},
- {{cc, r0, r9}, "cc, r0, r9", "cc_r0_r9"},
- {{cc, r0, r10}, "cc, r0, r10", "cc_r0_r10"},
- {{cc, r0, r11}, "cc, r0, r11", "cc_r0_r11"},
- {{cc, r0, r12}, "cc, r0, r12", "cc_r0_r12"},
- {{cc, r0, r13}, "cc, r0, r13", "cc_r0_r13"},
- {{cc, r0, r14}, "cc, r0, r14", "cc_r0_r14"},
- {{cc, r1, r0}, "cc, r1, r0", "cc_r1_r0"},
- {{cc, r1, r1}, "cc, r1, r1", "cc_r1_r1"},
- {{cc, r1, r2}, "cc, r1, r2", "cc_r1_r2"},
- {{cc, r1, r3}, "cc, r1, r3", "cc_r1_r3"},
- {{cc, r1, r4}, "cc, r1, r4", "cc_r1_r4"},
- {{cc, r1, r5}, "cc, r1, r5", "cc_r1_r5"},
- {{cc, r1, r6}, "cc, r1, r6", "cc_r1_r6"},
- {{cc, r1, r7}, "cc, r1, r7", "cc_r1_r7"},
- {{cc, r1, r8}, "cc, r1, r8", "cc_r1_r8"},
- {{cc, r1, r9}, "cc, r1, r9", "cc_r1_r9"},
- {{cc, r1, r10}, "cc, r1, r10", "cc_r1_r10"},
- {{cc, r1, r11}, "cc, r1, r11", "cc_r1_r11"},
- {{cc, r1, r12}, "cc, r1, r12", "cc_r1_r12"},
- {{cc, r1, r13}, "cc, r1, r13", "cc_r1_r13"},
- {{cc, r1, r14}, "cc, r1, r14", "cc_r1_r14"},
- {{cc, r2, r0}, "cc, r2, r0", "cc_r2_r0"},
- {{cc, r2, r1}, "cc, r2, r1", "cc_r2_r1"},
- {{cc, r2, r2}, "cc, r2, r2", "cc_r2_r2"},
- {{cc, r2, r3}, "cc, r2, r3", "cc_r2_r3"},
- {{cc, r2, r4}, "cc, r2, r4", "cc_r2_r4"},
- {{cc, r2, r5}, "cc, r2, r5", "cc_r2_r5"},
- {{cc, r2, r6}, "cc, r2, r6", "cc_r2_r6"},
- {{cc, r2, r7}, "cc, r2, r7", "cc_r2_r7"},
- {{cc, r2, r8}, "cc, r2, r8", "cc_r2_r8"},
- {{cc, r2, r9}, "cc, r2, r9", "cc_r2_r9"},
- {{cc, r2, r10}, "cc, r2, r10", "cc_r2_r10"},
- {{cc, r2, r11}, "cc, r2, r11", "cc_r2_r11"},
- {{cc, r2, r12}, "cc, r2, r12", "cc_r2_r12"},
- {{cc, r2, r13}, "cc, r2, r13", "cc_r2_r13"},
- {{cc, r2, r14}, "cc, r2, r14", "cc_r2_r14"},
- {{cc, r3, r0}, "cc, r3, r0", "cc_r3_r0"},
- {{cc, r3, r1}, "cc, r3, r1", "cc_r3_r1"},
- {{cc, r3, r2}, "cc, r3, r2", "cc_r3_r2"},
- {{cc, r3, r3}, "cc, r3, r3", "cc_r3_r3"},
- {{cc, r3, r4}, "cc, r3, r4", "cc_r3_r4"},
- {{cc, r3, r5}, "cc, r3, r5", "cc_r3_r5"},
- {{cc, r3, r6}, "cc, r3, r6", "cc_r3_r6"},
- {{cc, r3, r7}, "cc, r3, r7", "cc_r3_r7"},
- {{cc, r3, r8}, "cc, r3, r8", "cc_r3_r8"},
- {{cc, r3, r9}, "cc, r3, r9", "cc_r3_r9"},
- {{cc, r3, r10}, "cc, r3, r10", "cc_r3_r10"},
- {{cc, r3, r11}, "cc, r3, r11", "cc_r3_r11"},
- {{cc, r3, r12}, "cc, r3, r12", "cc_r3_r12"},
- {{cc, r3, r13}, "cc, r3, r13", "cc_r3_r13"},
- {{cc, r3, r14}, "cc, r3, r14", "cc_r3_r14"},
- {{cc, r4, r0}, "cc, r4, r0", "cc_r4_r0"},
- {{cc, r4, r1}, "cc, r4, r1", "cc_r4_r1"},
- {{cc, r4, r2}, "cc, r4, r2", "cc_r4_r2"},
- {{cc, r4, r3}, "cc, r4, r3", "cc_r4_r3"},
- {{cc, r4, r4}, "cc, r4, r4", "cc_r4_r4"},
- {{cc, r4, r5}, "cc, r4, r5", "cc_r4_r5"},
- {{cc, r4, r6}, "cc, r4, r6", "cc_r4_r6"},
- {{cc, r4, r7}, "cc, r4, r7", "cc_r4_r7"},
- {{cc, r4, r8}, "cc, r4, r8", "cc_r4_r8"},
- {{cc, r4, r9}, "cc, r4, r9", "cc_r4_r9"},
- {{cc, r4, r10}, "cc, r4, r10", "cc_r4_r10"},
- {{cc, r4, r11}, "cc, r4, r11", "cc_r4_r11"},
- {{cc, r4, r12}, "cc, r4, r12", "cc_r4_r12"},
- {{cc, r4, r13}, "cc, r4, r13", "cc_r4_r13"},
- {{cc, r4, r14}, "cc, r4, r14", "cc_r4_r14"},
- {{cc, r5, r0}, "cc, r5, r0", "cc_r5_r0"},
- {{cc, r5, r1}, "cc, r5, r1", "cc_r5_r1"},
- {{cc, r5, r2}, "cc, r5, r2", "cc_r5_r2"},
- {{cc, r5, r3}, "cc, r5, r3", "cc_r5_r3"},
- {{cc, r5, r4}, "cc, r5, r4", "cc_r5_r4"},
- {{cc, r5, r5}, "cc, r5, r5", "cc_r5_r5"},
- {{cc, r5, r6}, "cc, r5, r6", "cc_r5_r6"},
- {{cc, r5, r7}, "cc, r5, r7", "cc_r5_r7"},
- {{cc, r5, r8}, "cc, r5, r8", "cc_r5_r8"},
- {{cc, r5, r9}, "cc, r5, r9", "cc_r5_r9"},
- {{cc, r5, r10}, "cc, r5, r10", "cc_r5_r10"},
- {{cc, r5, r11}, "cc, r5, r11", "cc_r5_r11"},
- {{cc, r5, r12}, "cc, r5, r12", "cc_r5_r12"},
- {{cc, r5, r13}, "cc, r5, r13", "cc_r5_r13"},
- {{cc, r5, r14}, "cc, r5, r14", "cc_r5_r14"},
- {{cc, r6, r0}, "cc, r6, r0", "cc_r6_r0"},
- {{cc, r6, r1}, "cc, r6, r1", "cc_r6_r1"},
- {{cc, r6, r2}, "cc, r6, r2", "cc_r6_r2"},
- {{cc, r6, r3}, "cc, r6, r3", "cc_r6_r3"},
- {{cc, r6, r4}, "cc, r6, r4", "cc_r6_r4"},
- {{cc, r6, r5}, "cc, r6, r5", "cc_r6_r5"},
- {{cc, r6, r6}, "cc, r6, r6", "cc_r6_r6"},
- {{cc, r6, r7}, "cc, r6, r7", "cc_r6_r7"},
- {{cc, r6, r8}, "cc, r6, r8", "cc_r6_r8"},
- {{cc, r6, r9}, "cc, r6, r9", "cc_r6_r9"},
- {{cc, r6, r10}, "cc, r6, r10", "cc_r6_r10"},
- {{cc, r6, r11}, "cc, r6, r11", "cc_r6_r11"},
- {{cc, r6, r12}, "cc, r6, r12", "cc_r6_r12"},
- {{cc, r6, r13}, "cc, r6, r13", "cc_r6_r13"},
- {{cc, r6, r14}, "cc, r6, r14", "cc_r6_r14"},
- {{cc, r7, r0}, "cc, r7, r0", "cc_r7_r0"},
- {{cc, r7, r1}, "cc, r7, r1", "cc_r7_r1"},
- {{cc, r7, r2}, "cc, r7, r2", "cc_r7_r2"},
- {{cc, r7, r3}, "cc, r7, r3", "cc_r7_r3"},
- {{cc, r7, r4}, "cc, r7, r4", "cc_r7_r4"},
- {{cc, r7, r5}, "cc, r7, r5", "cc_r7_r5"},
- {{cc, r7, r6}, "cc, r7, r6", "cc_r7_r6"},
- {{cc, r7, r7}, "cc, r7, r7", "cc_r7_r7"},
- {{cc, r7, r8}, "cc, r7, r8", "cc_r7_r8"},
- {{cc, r7, r9}, "cc, r7, r9", "cc_r7_r9"},
- {{cc, r7, r10}, "cc, r7, r10", "cc_r7_r10"},
- {{cc, r7, r11}, "cc, r7, r11", "cc_r7_r11"},
- {{cc, r7, r12}, "cc, r7, r12", "cc_r7_r12"},
- {{cc, r7, r13}, "cc, r7, r13", "cc_r7_r13"},
- {{cc, r7, r14}, "cc, r7, r14", "cc_r7_r14"},
- {{cc, r8, r0}, "cc, r8, r0", "cc_r8_r0"},
- {{cc, r8, r1}, "cc, r8, r1", "cc_r8_r1"},
- {{cc, r8, r2}, "cc, r8, r2", "cc_r8_r2"},
- {{cc, r8, r3}, "cc, r8, r3", "cc_r8_r3"},
- {{cc, r8, r4}, "cc, r8, r4", "cc_r8_r4"},
- {{cc, r8, r5}, "cc, r8, r5", "cc_r8_r5"},
- {{cc, r8, r6}, "cc, r8, r6", "cc_r8_r6"},
- {{cc, r8, r7}, "cc, r8, r7", "cc_r8_r7"},
- {{cc, r8, r8}, "cc, r8, r8", "cc_r8_r8"},
- {{cc, r8, r9}, "cc, r8, r9", "cc_r8_r9"},
- {{cc, r8, r10}, "cc, r8, r10", "cc_r8_r10"},
- {{cc, r8, r11}, "cc, r8, r11", "cc_r8_r11"},
- {{cc, r8, r12}, "cc, r8, r12", "cc_r8_r12"},
- {{cc, r8, r13}, "cc, r8, r13", "cc_r8_r13"},
- {{cc, r8, r14}, "cc, r8, r14", "cc_r8_r14"},
- {{cc, r9, r0}, "cc, r9, r0", "cc_r9_r0"},
- {{cc, r9, r1}, "cc, r9, r1", "cc_r9_r1"},
- {{cc, r9, r2}, "cc, r9, r2", "cc_r9_r2"},
- {{cc, r9, r3}, "cc, r9, r3", "cc_r9_r3"},
- {{cc, r9, r4}, "cc, r9, r4", "cc_r9_r4"},
- {{cc, r9, r5}, "cc, r9, r5", "cc_r9_r5"},
- {{cc, r9, r6}, "cc, r9, r6", "cc_r9_r6"},
- {{cc, r9, r7}, "cc, r9, r7", "cc_r9_r7"},
- {{cc, r9, r8}, "cc, r9, r8", "cc_r9_r8"},
- {{cc, r9, r9}, "cc, r9, r9", "cc_r9_r9"},
- {{cc, r9, r10}, "cc, r9, r10", "cc_r9_r10"},
- {{cc, r9, r11}, "cc, r9, r11", "cc_r9_r11"},
- {{cc, r9, r12}, "cc, r9, r12", "cc_r9_r12"},
- {{cc, r9, r13}, "cc, r9, r13", "cc_r9_r13"},
- {{cc, r9, r14}, "cc, r9, r14", "cc_r9_r14"},
- {{cc, r10, r0}, "cc, r10, r0", "cc_r10_r0"},
- {{cc, r10, r1}, "cc, r10, r1", "cc_r10_r1"},
- {{cc, r10, r2}, "cc, r10, r2", "cc_r10_r2"},
- {{cc, r10, r3}, "cc, r10, r3", "cc_r10_r3"},
- {{cc, r10, r4}, "cc, r10, r4", "cc_r10_r4"},
- {{cc, r10, r5}, "cc, r10, r5", "cc_r10_r5"},
- {{cc, r10, r6}, "cc, r10, r6", "cc_r10_r6"},
- {{cc, r10, r7}, "cc, r10, r7", "cc_r10_r7"},
- {{cc, r10, r8}, "cc, r10, r8", "cc_r10_r8"},
- {{cc, r10, r9}, "cc, r10, r9", "cc_r10_r9"},
- {{cc, r10, r10}, "cc, r10, r10", "cc_r10_r10"},
- {{cc, r10, r11}, "cc, r10, r11", "cc_r10_r11"},
- {{cc, r10, r12}, "cc, r10, r12", "cc_r10_r12"},
- {{cc, r10, r13}, "cc, r10, r13", "cc_r10_r13"},
- {{cc, r10, r14}, "cc, r10, r14", "cc_r10_r14"},
- {{cc, r11, r0}, "cc, r11, r0", "cc_r11_r0"},
- {{cc, r11, r1}, "cc, r11, r1", "cc_r11_r1"},
- {{cc, r11, r2}, "cc, r11, r2", "cc_r11_r2"},
- {{cc, r11, r3}, "cc, r11, r3", "cc_r11_r3"},
- {{cc, r11, r4}, "cc, r11, r4", "cc_r11_r4"},
- {{cc, r11, r5}, "cc, r11, r5", "cc_r11_r5"},
- {{cc, r11, r6}, "cc, r11, r6", "cc_r11_r6"},
- {{cc, r11, r7}, "cc, r11, r7", "cc_r11_r7"},
- {{cc, r11, r8}, "cc, r11, r8", "cc_r11_r8"},
- {{cc, r11, r9}, "cc, r11, r9", "cc_r11_r9"},
- {{cc, r11, r10}, "cc, r11, r10", "cc_r11_r10"},
- {{cc, r11, r11}, "cc, r11, r11", "cc_r11_r11"},
- {{cc, r11, r12}, "cc, r11, r12", "cc_r11_r12"},
- {{cc, r11, r13}, "cc, r11, r13", "cc_r11_r13"},
- {{cc, r11, r14}, "cc, r11, r14", "cc_r11_r14"},
- {{cc, r12, r0}, "cc, r12, r0", "cc_r12_r0"},
- {{cc, r12, r1}, "cc, r12, r1", "cc_r12_r1"},
- {{cc, r12, r2}, "cc, r12, r2", "cc_r12_r2"},
- {{cc, r12, r3}, "cc, r12, r3", "cc_r12_r3"},
- {{cc, r12, r4}, "cc, r12, r4", "cc_r12_r4"},
- {{cc, r12, r5}, "cc, r12, r5", "cc_r12_r5"},
- {{cc, r12, r6}, "cc, r12, r6", "cc_r12_r6"},
- {{cc, r12, r7}, "cc, r12, r7", "cc_r12_r7"},
- {{cc, r12, r8}, "cc, r12, r8", "cc_r12_r8"},
- {{cc, r12, r9}, "cc, r12, r9", "cc_r12_r9"},
- {{cc, r12, r10}, "cc, r12, r10", "cc_r12_r10"},
- {{cc, r12, r11}, "cc, r12, r11", "cc_r12_r11"},
- {{cc, r12, r12}, "cc, r12, r12", "cc_r12_r12"},
- {{cc, r12, r13}, "cc, r12, r13", "cc_r12_r13"},
- {{cc, r12, r14}, "cc, r12, r14", "cc_r12_r14"},
- {{cc, r13, r0}, "cc, r13, r0", "cc_r13_r0"},
- {{cc, r13, r1}, "cc, r13, r1", "cc_r13_r1"},
- {{cc, r13, r2}, "cc, r13, r2", "cc_r13_r2"},
- {{cc, r13, r3}, "cc, r13, r3", "cc_r13_r3"},
- {{cc, r13, r4}, "cc, r13, r4", "cc_r13_r4"},
- {{cc, r13, r5}, "cc, r13, r5", "cc_r13_r5"},
- {{cc, r13, r6}, "cc, r13, r6", "cc_r13_r6"},
- {{cc, r13, r7}, "cc, r13, r7", "cc_r13_r7"},
- {{cc, r13, r8}, "cc, r13, r8", "cc_r13_r8"},
- {{cc, r13, r9}, "cc, r13, r9", "cc_r13_r9"},
- {{cc, r13, r10}, "cc, r13, r10", "cc_r13_r10"},
- {{cc, r13, r11}, "cc, r13, r11", "cc_r13_r11"},
- {{cc, r13, r12}, "cc, r13, r12", "cc_r13_r12"},
- {{cc, r13, r13}, "cc, r13, r13", "cc_r13_r13"},
- {{cc, r13, r14}, "cc, r13, r14", "cc_r13_r14"},
- {{cc, r14, r0}, "cc, r14, r0", "cc_r14_r0"},
- {{cc, r14, r1}, "cc, r14, r1", "cc_r14_r1"},
- {{cc, r14, r2}, "cc, r14, r2", "cc_r14_r2"},
- {{cc, r14, r3}, "cc, r14, r3", "cc_r14_r3"},
- {{cc, r14, r4}, "cc, r14, r4", "cc_r14_r4"},
- {{cc, r14, r5}, "cc, r14, r5", "cc_r14_r5"},
- {{cc, r14, r6}, "cc, r14, r6", "cc_r14_r6"},
- {{cc, r14, r7}, "cc, r14, r7", "cc_r14_r7"},
- {{cc, r14, r8}, "cc, r14, r8", "cc_r14_r8"},
- {{cc, r14, r9}, "cc, r14, r9", "cc_r14_r9"},
- {{cc, r14, r10}, "cc, r14, r10", "cc_r14_r10"},
- {{cc, r14, r11}, "cc, r14, r11", "cc_r14_r11"},
- {{cc, r14, r12}, "cc, r14, r12", "cc_r14_r12"},
- {{cc, r14, r13}, "cc, r14, r13", "cc_r14_r13"},
- {{cc, r14, r14}, "cc, r14, r14", "cc_r14_r14"},
- {{mi, r0, r0}, "mi, r0, r0", "mi_r0_r0"},
- {{mi, r0, r1}, "mi, r0, r1", "mi_r0_r1"},
- {{mi, r0, r2}, "mi, r0, r2", "mi_r0_r2"},
- {{mi, r0, r3}, "mi, r0, r3", "mi_r0_r3"},
- {{mi, r0, r4}, "mi, r0, r4", "mi_r0_r4"},
- {{mi, r0, r5}, "mi, r0, r5", "mi_r0_r5"},
- {{mi, r0, r6}, "mi, r0, r6", "mi_r0_r6"},
- {{mi, r0, r7}, "mi, r0, r7", "mi_r0_r7"},
- {{mi, r0, r8}, "mi, r0, r8", "mi_r0_r8"},
- {{mi, r0, r9}, "mi, r0, r9", "mi_r0_r9"},
- {{mi, r0, r10}, "mi, r0, r10", "mi_r0_r10"},
- {{mi, r0, r11}, "mi, r0, r11", "mi_r0_r11"},
- {{mi, r0, r12}, "mi, r0, r12", "mi_r0_r12"},
- {{mi, r0, r13}, "mi, r0, r13", "mi_r0_r13"},
- {{mi, r0, r14}, "mi, r0, r14", "mi_r0_r14"},
- {{mi, r1, r0}, "mi, r1, r0", "mi_r1_r0"},
- {{mi, r1, r1}, "mi, r1, r1", "mi_r1_r1"},
- {{mi, r1, r2}, "mi, r1, r2", "mi_r1_r2"},
- {{mi, r1, r3}, "mi, r1, r3", "mi_r1_r3"},
- {{mi, r1, r4}, "mi, r1, r4", "mi_r1_r4"},
- {{mi, r1, r5}, "mi, r1, r5", "mi_r1_r5"},
- {{mi, r1, r6}, "mi, r1, r6", "mi_r1_r6"},
- {{mi, r1, r7}, "mi, r1, r7", "mi_r1_r7"},
- {{mi, r1, r8}, "mi, r1, r8", "mi_r1_r8"},
- {{mi, r1, r9}, "mi, r1, r9", "mi_r1_r9"},
- {{mi, r1, r10}, "mi, r1, r10", "mi_r1_r10"},
- {{mi, r1, r11}, "mi, r1, r11", "mi_r1_r11"},
- {{mi, r1, r12}, "mi, r1, r12", "mi_r1_r12"},
- {{mi, r1, r13}, "mi, r1, r13", "mi_r1_r13"},
- {{mi, r1, r14}, "mi, r1, r14", "mi_r1_r14"},
- {{mi, r2, r0}, "mi, r2, r0", "mi_r2_r0"},
- {{mi, r2, r1}, "mi, r2, r1", "mi_r2_r1"},
- {{mi, r2, r2}, "mi, r2, r2", "mi_r2_r2"},
- {{mi, r2, r3}, "mi, r2, r3", "mi_r2_r3"},
- {{mi, r2, r4}, "mi, r2, r4", "mi_r2_r4"},
- {{mi, r2, r5}, "mi, r2, r5", "mi_r2_r5"},
- {{mi, r2, r6}, "mi, r2, r6", "mi_r2_r6"},
- {{mi, r2, r7}, "mi, r2, r7", "mi_r2_r7"},
- {{mi, r2, r8}, "mi, r2, r8", "mi_r2_r8"},
- {{mi, r2, r9}, "mi, r2, r9", "mi_r2_r9"},
- {{mi, r2, r10}, "mi, r2, r10", "mi_r2_r10"},
- {{mi, r2, r11}, "mi, r2, r11", "mi_r2_r11"},
- {{mi, r2, r12}, "mi, r2, r12", "mi_r2_r12"},
- {{mi, r2, r13}, "mi, r2, r13", "mi_r2_r13"},
- {{mi, r2, r14}, "mi, r2, r14", "mi_r2_r14"},
- {{mi, r3, r0}, "mi, r3, r0", "mi_r3_r0"},
- {{mi, r3, r1}, "mi, r3, r1", "mi_r3_r1"},
- {{mi, r3, r2}, "mi, r3, r2", "mi_r3_r2"},
- {{mi, r3, r3}, "mi, r3, r3", "mi_r3_r3"},
- {{mi, r3, r4}, "mi, r3, r4", "mi_r3_r4"},
- {{mi, r3, r5}, "mi, r3, r5", "mi_r3_r5"},
- {{mi, r3, r6}, "mi, r3, r6", "mi_r3_r6"},
- {{mi, r3, r7}, "mi, r3, r7", "mi_r3_r7"},
- {{mi, r3, r8}, "mi, r3, r8", "mi_r3_r8"},
- {{mi, r3, r9}, "mi, r3, r9", "mi_r3_r9"},
- {{mi, r3, r10}, "mi, r3, r10", "mi_r3_r10"},
- {{mi, r3, r11}, "mi, r3, r11", "mi_r3_r11"},
- {{mi, r3, r12}, "mi, r3, r12", "mi_r3_r12"},
- {{mi, r3, r13}, "mi, r3, r13", "mi_r3_r13"},
- {{mi, r3, r14}, "mi, r3, r14", "mi_r3_r14"},
- {{mi, r4, r0}, "mi, r4, r0", "mi_r4_r0"},
- {{mi, r4, r1}, "mi, r4, r1", "mi_r4_r1"},
- {{mi, r4, r2}, "mi, r4, r2", "mi_r4_r2"},
- {{mi, r4, r3}, "mi, r4, r3", "mi_r4_r3"},
- {{mi, r4, r4}, "mi, r4, r4", "mi_r4_r4"},
- {{mi, r4, r5}, "mi, r4, r5", "mi_r4_r5"},
- {{mi, r4, r6}, "mi, r4, r6", "mi_r4_r6"},
- {{mi, r4, r7}, "mi, r4, r7", "mi_r4_r7"},
- {{mi, r4, r8}, "mi, r4, r8", "mi_r4_r8"},
- {{mi, r4, r9}, "mi, r4, r9", "mi_r4_r9"},
- {{mi, r4, r10}, "mi, r4, r10", "mi_r4_r10"},
- {{mi, r4, r11}, "mi, r4, r11", "mi_r4_r11"},
- {{mi, r4, r12}, "mi, r4, r12", "mi_r4_r12"},
- {{mi, r4, r13}, "mi, r4, r13", "mi_r4_r13"},
- {{mi, r4, r14}, "mi, r4, r14", "mi_r4_r14"},
- {{mi, r5, r0}, "mi, r5, r0", "mi_r5_r0"},
- {{mi, r5, r1}, "mi, r5, r1", "mi_r5_r1"},
- {{mi, r5, r2}, "mi, r5, r2", "mi_r5_r2"},
- {{mi, r5, r3}, "mi, r5, r3", "mi_r5_r3"},
- {{mi, r5, r4}, "mi, r5, r4", "mi_r5_r4"},
- {{mi, r5, r5}, "mi, r5, r5", "mi_r5_r5"},
- {{mi, r5, r6}, "mi, r5, r6", "mi_r5_r6"},
- {{mi, r5, r7}, "mi, r5, r7", "mi_r5_r7"},
- {{mi, r5, r8}, "mi, r5, r8", "mi_r5_r8"},
- {{mi, r5, r9}, "mi, r5, r9", "mi_r5_r9"},
- {{mi, r5, r10}, "mi, r5, r10", "mi_r5_r10"},
- {{mi, r5, r11}, "mi, r5, r11", "mi_r5_r11"},
- {{mi, r5, r12}, "mi, r5, r12", "mi_r5_r12"},
- {{mi, r5, r13}, "mi, r5, r13", "mi_r5_r13"},
- {{mi, r5, r14}, "mi, r5, r14", "mi_r5_r14"},
- {{mi, r6, r0}, "mi, r6, r0", "mi_r6_r0"},
- {{mi, r6, r1}, "mi, r6, r1", "mi_r6_r1"},
- {{mi, r6, r2}, "mi, r6, r2", "mi_r6_r2"},
- {{mi, r6, r3}, "mi, r6, r3", "mi_r6_r3"},
- {{mi, r6, r4}, "mi, r6, r4", "mi_r6_r4"},
- {{mi, r6, r5}, "mi, r6, r5", "mi_r6_r5"},
- {{mi, r6, r6}, "mi, r6, r6", "mi_r6_r6"},
- {{mi, r6, r7}, "mi, r6, r7", "mi_r6_r7"},
- {{mi, r6, r8}, "mi, r6, r8", "mi_r6_r8"},
- {{mi, r6, r9}, "mi, r6, r9", "mi_r6_r9"},
- {{mi, r6, r10}, "mi, r6, r10", "mi_r6_r10"},
- {{mi, r6, r11}, "mi, r6, r11", "mi_r6_r11"},
- {{mi, r6, r12}, "mi, r6, r12", "mi_r6_r12"},
- {{mi, r6, r13}, "mi, r6, r13", "mi_r6_r13"},
- {{mi, r6, r14}, "mi, r6, r14", "mi_r6_r14"},
- {{mi, r7, r0}, "mi, r7, r0", "mi_r7_r0"},
- {{mi, r7, r1}, "mi, r7, r1", "mi_r7_r1"},
- {{mi, r7, r2}, "mi, r7, r2", "mi_r7_r2"},
- {{mi, r7, r3}, "mi, r7, r3", "mi_r7_r3"},
- {{mi, r7, r4}, "mi, r7, r4", "mi_r7_r4"},
- {{mi, r7, r5}, "mi, r7, r5", "mi_r7_r5"},
- {{mi, r7, r6}, "mi, r7, r6", "mi_r7_r6"},
- {{mi, r7, r7}, "mi, r7, r7", "mi_r7_r7"},
- {{mi, r7, r8}, "mi, r7, r8", "mi_r7_r8"},
- {{mi, r7, r9}, "mi, r7, r9", "mi_r7_r9"},
- {{mi, r7, r10}, "mi, r7, r10", "mi_r7_r10"},
- {{mi, r7, r11}, "mi, r7, r11", "mi_r7_r11"},
- {{mi, r7, r12}, "mi, r7, r12", "mi_r7_r12"},
- {{mi, r7, r13}, "mi, r7, r13", "mi_r7_r13"},
- {{mi, r7, r14}, "mi, r7, r14", "mi_r7_r14"},
- {{mi, r8, r0}, "mi, r8, r0", "mi_r8_r0"},
- {{mi, r8, r1}, "mi, r8, r1", "mi_r8_r1"},
- {{mi, r8, r2}, "mi, r8, r2", "mi_r8_r2"},
- {{mi, r8, r3}, "mi, r8, r3", "mi_r8_r3"},
- {{mi, r8, r4}, "mi, r8, r4", "mi_r8_r4"},
- {{mi, r8, r5}, "mi, r8, r5", "mi_r8_r5"},
- {{mi, r8, r6}, "mi, r8, r6", "mi_r8_r6"},
- {{mi, r8, r7}, "mi, r8, r7", "mi_r8_r7"},
- {{mi, r8, r8}, "mi, r8, r8", "mi_r8_r8"},
- {{mi, r8, r9}, "mi, r8, r9", "mi_r8_r9"},
- {{mi, r8, r10}, "mi, r8, r10", "mi_r8_r10"},
- {{mi, r8, r11}, "mi, r8, r11", "mi_r8_r11"},
- {{mi, r8, r12}, "mi, r8, r12", "mi_r8_r12"},
- {{mi, r8, r13}, "mi, r8, r13", "mi_r8_r13"},
- {{mi, r8, r14}, "mi, r8, r14", "mi_r8_r14"},
- {{mi, r9, r0}, "mi, r9, r0", "mi_r9_r0"},
- {{mi, r9, r1}, "mi, r9, r1", "mi_r9_r1"},
- {{mi, r9, r2}, "mi, r9, r2", "mi_r9_r2"},
- {{mi, r9, r3}, "mi, r9, r3", "mi_r9_r3"},
- {{mi, r9, r4}, "mi, r9, r4", "mi_r9_r4"},
- {{mi, r9, r5}, "mi, r9, r5", "mi_r9_r5"},
- {{mi, r9, r6}, "mi, r9, r6", "mi_r9_r6"},
- {{mi, r9, r7}, "mi, r9, r7", "mi_r9_r7"},
- {{mi, r9, r8}, "mi, r9, r8", "mi_r9_r8"},
- {{mi, r9, r9}, "mi, r9, r9", "mi_r9_r9"},
- {{mi, r9, r10}, "mi, r9, r10", "mi_r9_r10"},
- {{mi, r9, r11}, "mi, r9, r11", "mi_r9_r11"},
- {{mi, r9, r12}, "mi, r9, r12", "mi_r9_r12"},
- {{mi, r9, r13}, "mi, r9, r13", "mi_r9_r13"},
- {{mi, r9, r14}, "mi, r9, r14", "mi_r9_r14"},
- {{mi, r10, r0}, "mi, r10, r0", "mi_r10_r0"},
- {{mi, r10, r1}, "mi, r10, r1", "mi_r10_r1"},
- {{mi, r10, r2}, "mi, r10, r2", "mi_r10_r2"},
- {{mi, r10, r3}, "mi, r10, r3", "mi_r10_r3"},
- {{mi, r10, r4}, "mi, r10, r4", "mi_r10_r4"},
- {{mi, r10, r5}, "mi, r10, r5", "mi_r10_r5"},
- {{mi, r10, r6}, "mi, r10, r6", "mi_r10_r6"},
- {{mi, r10, r7}, "mi, r10, r7", "mi_r10_r7"},
- {{mi, r10, r8}, "mi, r10, r8", "mi_r10_r8"},
{{mi, r10, r9}, "mi, r10, r9", "mi_r10_r9"},
- {{mi, r10, r10}, "mi, r10, r10", "mi_r10_r10"},
- {{mi, r10, r11}, "mi, r10, r11", "mi_r10_r11"},
- {{mi, r10, r12}, "mi, r10, r12", "mi_r10_r12"},
- {{mi, r10, r13}, "mi, r10, r13", "mi_r10_r13"},
- {{mi, r10, r14}, "mi, r10, r14", "mi_r10_r14"},
- {{mi, r11, r0}, "mi, r11, r0", "mi_r11_r0"},
- {{mi, r11, r1}, "mi, r11, r1", "mi_r11_r1"},
- {{mi, r11, r2}, "mi, r11, r2", "mi_r11_r2"},
- {{mi, r11, r3}, "mi, r11, r3", "mi_r11_r3"},
- {{mi, r11, r4}, "mi, r11, r4", "mi_r11_r4"},
- {{mi, r11, r5}, "mi, r11, r5", "mi_r11_r5"},
- {{mi, r11, r6}, "mi, r11, r6", "mi_r11_r6"},
- {{mi, r11, r7}, "mi, r11, r7", "mi_r11_r7"},
- {{mi, r11, r8}, "mi, r11, r8", "mi_r11_r8"},
- {{mi, r11, r9}, "mi, r11, r9", "mi_r11_r9"},
- {{mi, r11, r10}, "mi, r11, r10", "mi_r11_r10"},
- {{mi, r11, r11}, "mi, r11, r11", "mi_r11_r11"},
- {{mi, r11, r12}, "mi, r11, r12", "mi_r11_r12"},
- {{mi, r11, r13}, "mi, r11, r13", "mi_r11_r13"},
- {{mi, r11, r14}, "mi, r11, r14", "mi_r11_r14"},
- {{mi, r12, r0}, "mi, r12, r0", "mi_r12_r0"},
- {{mi, r12, r1}, "mi, r12, r1", "mi_r12_r1"},
- {{mi, r12, r2}, "mi, r12, r2", "mi_r12_r2"},
- {{mi, r12, r3}, "mi, r12, r3", "mi_r12_r3"},
- {{mi, r12, r4}, "mi, r12, r4", "mi_r12_r4"},
- {{mi, r12, r5}, "mi, r12, r5", "mi_r12_r5"},
- {{mi, r12, r6}, "mi, r12, r6", "mi_r12_r6"},
- {{mi, r12, r7}, "mi, r12, r7", "mi_r12_r7"},
- {{mi, r12, r8}, "mi, r12, r8", "mi_r12_r8"},
- {{mi, r12, r9}, "mi, r12, r9", "mi_r12_r9"},
- {{mi, r12, r10}, "mi, r12, r10", "mi_r12_r10"},
- {{mi, r12, r11}, "mi, r12, r11", "mi_r12_r11"},
- {{mi, r12, r12}, "mi, r12, r12", "mi_r12_r12"},
- {{mi, r12, r13}, "mi, r12, r13", "mi_r12_r13"},
- {{mi, r12, r14}, "mi, r12, r14", "mi_r12_r14"},
- {{mi, r13, r0}, "mi, r13, r0", "mi_r13_r0"},
- {{mi, r13, r1}, "mi, r13, r1", "mi_r13_r1"},
- {{mi, r13, r2}, "mi, r13, r2", "mi_r13_r2"},
- {{mi, r13, r3}, "mi, r13, r3", "mi_r13_r3"},
- {{mi, r13, r4}, "mi, r13, r4", "mi_r13_r4"},
- {{mi, r13, r5}, "mi, r13, r5", "mi_r13_r5"},
- {{mi, r13, r6}, "mi, r13, r6", "mi_r13_r6"},
- {{mi, r13, r7}, "mi, r13, r7", "mi_r13_r7"},
- {{mi, r13, r8}, "mi, r13, r8", "mi_r13_r8"},
- {{mi, r13, r9}, "mi, r13, r9", "mi_r13_r9"},
- {{mi, r13, r10}, "mi, r13, r10", "mi_r13_r10"},
- {{mi, r13, r11}, "mi, r13, r11", "mi_r13_r11"},
- {{mi, r13, r12}, "mi, r13, r12", "mi_r13_r12"},
- {{mi, r13, r13}, "mi, r13, r13", "mi_r13_r13"},
- {{mi, r13, r14}, "mi, r13, r14", "mi_r13_r14"},
- {{mi, r14, r0}, "mi, r14, r0", "mi_r14_r0"},
- {{mi, r14, r1}, "mi, r14, r1", "mi_r14_r1"},
- {{mi, r14, r2}, "mi, r14, r2", "mi_r14_r2"},
- {{mi, r14, r3}, "mi, r14, r3", "mi_r14_r3"},
- {{mi, r14, r4}, "mi, r14, r4", "mi_r14_r4"},
- {{mi, r14, r5}, "mi, r14, r5", "mi_r14_r5"},
- {{mi, r14, r6}, "mi, r14, r6", "mi_r14_r6"},
- {{mi, r14, r7}, "mi, r14, r7", "mi_r14_r7"},
- {{mi, r14, r8}, "mi, r14, r8", "mi_r14_r8"},
- {{mi, r14, r9}, "mi, r14, r9", "mi_r14_r9"},
- {{mi, r14, r10}, "mi, r14, r10", "mi_r14_r10"},
- {{mi, r14, r11}, "mi, r14, r11", "mi_r14_r11"},
- {{mi, r14, r12}, "mi, r14, r12", "mi_r14_r12"},
- {{mi, r14, r13}, "mi, r14, r13", "mi_r14_r13"},
- {{mi, r14, r14}, "mi, r14, r14", "mi_r14_r14"},
- {{pl, r0, r0}, "pl, r0, r0", "pl_r0_r0"},
- {{pl, r0, r1}, "pl, r0, r1", "pl_r0_r1"},
- {{pl, r0, r2}, "pl, r0, r2", "pl_r0_r2"},
- {{pl, r0, r3}, "pl, r0, r3", "pl_r0_r3"},
- {{pl, r0, r4}, "pl, r0, r4", "pl_r0_r4"},
- {{pl, r0, r5}, "pl, r0, r5", "pl_r0_r5"},
- {{pl, r0, r6}, "pl, r0, r6", "pl_r0_r6"},
- {{pl, r0, r7}, "pl, r0, r7", "pl_r0_r7"},
- {{pl, r0, r8}, "pl, r0, r8", "pl_r0_r8"},
- {{pl, r0, r9}, "pl, r0, r9", "pl_r0_r9"},
- {{pl, r0, r10}, "pl, r0, r10", "pl_r0_r10"},
- {{pl, r0, r11}, "pl, r0, r11", "pl_r0_r11"},
- {{pl, r0, r12}, "pl, r0, r12", "pl_r0_r12"},
- {{pl, r0, r13}, "pl, r0, r13", "pl_r0_r13"},
- {{pl, r0, r14}, "pl, r0, r14", "pl_r0_r14"},
- {{pl, r1, r0}, "pl, r1, r0", "pl_r1_r0"},
- {{pl, r1, r1}, "pl, r1, r1", "pl_r1_r1"},
- {{pl, r1, r2}, "pl, r1, r2", "pl_r1_r2"},
- {{pl, r1, r3}, "pl, r1, r3", "pl_r1_r3"},
- {{pl, r1, r4}, "pl, r1, r4", "pl_r1_r4"},
- {{pl, r1, r5}, "pl, r1, r5", "pl_r1_r5"},
- {{pl, r1, r6}, "pl, r1, r6", "pl_r1_r6"},
- {{pl, r1, r7}, "pl, r1, r7", "pl_r1_r7"},
- {{pl, r1, r8}, "pl, r1, r8", "pl_r1_r8"},
- {{pl, r1, r9}, "pl, r1, r9", "pl_r1_r9"},
- {{pl, r1, r10}, "pl, r1, r10", "pl_r1_r10"},
- {{pl, r1, r11}, "pl, r1, r11", "pl_r1_r11"},
- {{pl, r1, r12}, "pl, r1, r12", "pl_r1_r12"},
- {{pl, r1, r13}, "pl, r1, r13", "pl_r1_r13"},
- {{pl, r1, r14}, "pl, r1, r14", "pl_r1_r14"},
- {{pl, r2, r0}, "pl, r2, r0", "pl_r2_r0"},
- {{pl, r2, r1}, "pl, r2, r1", "pl_r2_r1"},
- {{pl, r2, r2}, "pl, r2, r2", "pl_r2_r2"},
- {{pl, r2, r3}, "pl, r2, r3", "pl_r2_r3"},
- {{pl, r2, r4}, "pl, r2, r4", "pl_r2_r4"},
- {{pl, r2, r5}, "pl, r2, r5", "pl_r2_r5"},
- {{pl, r2, r6}, "pl, r2, r6", "pl_r2_r6"},
- {{pl, r2, r7}, "pl, r2, r7", "pl_r2_r7"},
- {{pl, r2, r8}, "pl, r2, r8", "pl_r2_r8"},
- {{pl, r2, r9}, "pl, r2, r9", "pl_r2_r9"},
- {{pl, r2, r10}, "pl, r2, r10", "pl_r2_r10"},
- {{pl, r2, r11}, "pl, r2, r11", "pl_r2_r11"},
- {{pl, r2, r12}, "pl, r2, r12", "pl_r2_r12"},
- {{pl, r2, r13}, "pl, r2, r13", "pl_r2_r13"},
- {{pl, r2, r14}, "pl, r2, r14", "pl_r2_r14"},
- {{pl, r3, r0}, "pl, r3, r0", "pl_r3_r0"},
- {{pl, r3, r1}, "pl, r3, r1", "pl_r3_r1"},
- {{pl, r3, r2}, "pl, r3, r2", "pl_r3_r2"},
- {{pl, r3, r3}, "pl, r3, r3", "pl_r3_r3"},
- {{pl, r3, r4}, "pl, r3, r4", "pl_r3_r4"},
- {{pl, r3, r5}, "pl, r3, r5", "pl_r3_r5"},
- {{pl, r3, r6}, "pl, r3, r6", "pl_r3_r6"},
- {{pl, r3, r7}, "pl, r3, r7", "pl_r3_r7"},
- {{pl, r3, r8}, "pl, r3, r8", "pl_r3_r8"},
- {{pl, r3, r9}, "pl, r3, r9", "pl_r3_r9"},
- {{pl, r3, r10}, "pl, r3, r10", "pl_r3_r10"},
- {{pl, r3, r11}, "pl, r3, r11", "pl_r3_r11"},
- {{pl, r3, r12}, "pl, r3, r12", "pl_r3_r12"},
- {{pl, r3, r13}, "pl, r3, r13", "pl_r3_r13"},
- {{pl, r3, r14}, "pl, r3, r14", "pl_r3_r14"},
- {{pl, r4, r0}, "pl, r4, r0", "pl_r4_r0"},
- {{pl, r4, r1}, "pl, r4, r1", "pl_r4_r1"},
- {{pl, r4, r2}, "pl, r4, r2", "pl_r4_r2"},
- {{pl, r4, r3}, "pl, r4, r3", "pl_r4_r3"},
- {{pl, r4, r4}, "pl, r4, r4", "pl_r4_r4"},
- {{pl, r4, r5}, "pl, r4, r5", "pl_r4_r5"},
- {{pl, r4, r6}, "pl, r4, r6", "pl_r4_r6"},
- {{pl, r4, r7}, "pl, r4, r7", "pl_r4_r7"},
- {{pl, r4, r8}, "pl, r4, r8", "pl_r4_r8"},
- {{pl, r4, r9}, "pl, r4, r9", "pl_r4_r9"},
- {{pl, r4, r10}, "pl, r4, r10", "pl_r4_r10"},
- {{pl, r4, r11}, "pl, r4, r11", "pl_r4_r11"},
- {{pl, r4, r12}, "pl, r4, r12", "pl_r4_r12"},
- {{pl, r4, r13}, "pl, r4, r13", "pl_r4_r13"},
- {{pl, r4, r14}, "pl, r4, r14", "pl_r4_r14"},
- {{pl, r5, r0}, "pl, r5, r0", "pl_r5_r0"},
- {{pl, r5, r1}, "pl, r5, r1", "pl_r5_r1"},
- {{pl, r5, r2}, "pl, r5, r2", "pl_r5_r2"},
- {{pl, r5, r3}, "pl, r5, r3", "pl_r5_r3"},
- {{pl, r5, r4}, "pl, r5, r4", "pl_r5_r4"},
- {{pl, r5, r5}, "pl, r5, r5", "pl_r5_r5"},
- {{pl, r5, r6}, "pl, r5, r6", "pl_r5_r6"},
- {{pl, r5, r7}, "pl, r5, r7", "pl_r5_r7"},
- {{pl, r5, r8}, "pl, r5, r8", "pl_r5_r8"},
- {{pl, r5, r9}, "pl, r5, r9", "pl_r5_r9"},
- {{pl, r5, r10}, "pl, r5, r10", "pl_r5_r10"},
- {{pl, r5, r11}, "pl, r5, r11", "pl_r5_r11"},
- {{pl, r5, r12}, "pl, r5, r12", "pl_r5_r12"},
- {{pl, r5, r13}, "pl, r5, r13", "pl_r5_r13"},
- {{pl, r5, r14}, "pl, r5, r14", "pl_r5_r14"},
- {{pl, r6, r0}, "pl, r6, r0", "pl_r6_r0"},
- {{pl, r6, r1}, "pl, r6, r1", "pl_r6_r1"},
- {{pl, r6, r2}, "pl, r6, r2", "pl_r6_r2"},
- {{pl, r6, r3}, "pl, r6, r3", "pl_r6_r3"},
- {{pl, r6, r4}, "pl, r6, r4", "pl_r6_r4"},
- {{pl, r6, r5}, "pl, r6, r5", "pl_r6_r5"},
- {{pl, r6, r6}, "pl, r6, r6", "pl_r6_r6"},
- {{pl, r6, r7}, "pl, r6, r7", "pl_r6_r7"},
- {{pl, r6, r8}, "pl, r6, r8", "pl_r6_r8"},
- {{pl, r6, r9}, "pl, r6, r9", "pl_r6_r9"},
- {{pl, r6, r10}, "pl, r6, r10", "pl_r6_r10"},
- {{pl, r6, r11}, "pl, r6, r11", "pl_r6_r11"},
- {{pl, r6, r12}, "pl, r6, r12", "pl_r6_r12"},
- {{pl, r6, r13}, "pl, r6, r13", "pl_r6_r13"},
- {{pl, r6, r14}, "pl, r6, r14", "pl_r6_r14"},
- {{pl, r7, r0}, "pl, r7, r0", "pl_r7_r0"},
- {{pl, r7, r1}, "pl, r7, r1", "pl_r7_r1"},
- {{pl, r7, r2}, "pl, r7, r2", "pl_r7_r2"},
- {{pl, r7, r3}, "pl, r7, r3", "pl_r7_r3"},
- {{pl, r7, r4}, "pl, r7, r4", "pl_r7_r4"},
- {{pl, r7, r5}, "pl, r7, r5", "pl_r7_r5"},
- {{pl, r7, r6}, "pl, r7, r6", "pl_r7_r6"},
- {{pl, r7, r7}, "pl, r7, r7", "pl_r7_r7"},
- {{pl, r7, r8}, "pl, r7, r8", "pl_r7_r8"},
- {{pl, r7, r9}, "pl, r7, r9", "pl_r7_r9"},
- {{pl, r7, r10}, "pl, r7, r10", "pl_r7_r10"},
- {{pl, r7, r11}, "pl, r7, r11", "pl_r7_r11"},
- {{pl, r7, r12}, "pl, r7, r12", "pl_r7_r12"},
- {{pl, r7, r13}, "pl, r7, r13", "pl_r7_r13"},
- {{pl, r7, r14}, "pl, r7, r14", "pl_r7_r14"},
- {{pl, r8, r0}, "pl, r8, r0", "pl_r8_r0"},
- {{pl, r8, r1}, "pl, r8, r1", "pl_r8_r1"},
- {{pl, r8, r2}, "pl, r8, r2", "pl_r8_r2"},
- {{pl, r8, r3}, "pl, r8, r3", "pl_r8_r3"},
- {{pl, r8, r4}, "pl, r8, r4", "pl_r8_r4"},
- {{pl, r8, r5}, "pl, r8, r5", "pl_r8_r5"},
- {{pl, r8, r6}, "pl, r8, r6", "pl_r8_r6"},
- {{pl, r8, r7}, "pl, r8, r7", "pl_r8_r7"},
- {{pl, r8, r8}, "pl, r8, r8", "pl_r8_r8"},
- {{pl, r8, r9}, "pl, r8, r9", "pl_r8_r9"},
- {{pl, r8, r10}, "pl, r8, r10", "pl_r8_r10"},
- {{pl, r8, r11}, "pl, r8, r11", "pl_r8_r11"},
- {{pl, r8, r12}, "pl, r8, r12", "pl_r8_r12"},
- {{pl, r8, r13}, "pl, r8, r13", "pl_r8_r13"},
- {{pl, r8, r14}, "pl, r8, r14", "pl_r8_r14"},
- {{pl, r9, r0}, "pl, r9, r0", "pl_r9_r0"},
- {{pl, r9, r1}, "pl, r9, r1", "pl_r9_r1"},
- {{pl, r9, r2}, "pl, r9, r2", "pl_r9_r2"},
- {{pl, r9, r3}, "pl, r9, r3", "pl_r9_r3"},
- {{pl, r9, r4}, "pl, r9, r4", "pl_r9_r4"},
- {{pl, r9, r5}, "pl, r9, r5", "pl_r9_r5"},
- {{pl, r9, r6}, "pl, r9, r6", "pl_r9_r6"},
- {{pl, r9, r7}, "pl, r9, r7", "pl_r9_r7"},
- {{pl, r9, r8}, "pl, r9, r8", "pl_r9_r8"},
- {{pl, r9, r9}, "pl, r9, r9", "pl_r9_r9"},
- {{pl, r9, r10}, "pl, r9, r10", "pl_r9_r10"},
- {{pl, r9, r11}, "pl, r9, r11", "pl_r9_r11"},
- {{pl, r9, r12}, "pl, r9, r12", "pl_r9_r12"},
- {{pl, r9, r13}, "pl, r9, r13", "pl_r9_r13"},
- {{pl, r9, r14}, "pl, r9, r14", "pl_r9_r14"},
- {{pl, r10, r0}, "pl, r10, r0", "pl_r10_r0"},
- {{pl, r10, r1}, "pl, r10, r1", "pl_r10_r1"},
- {{pl, r10, r2}, "pl, r10, r2", "pl_r10_r2"},
- {{pl, r10, r3}, "pl, r10, r3", "pl_r10_r3"},
- {{pl, r10, r4}, "pl, r10, r4", "pl_r10_r4"},
- {{pl, r10, r5}, "pl, r10, r5", "pl_r10_r5"},
- {{pl, r10, r6}, "pl, r10, r6", "pl_r10_r6"},
- {{pl, r10, r7}, "pl, r10, r7", "pl_r10_r7"},
- {{pl, r10, r8}, "pl, r10, r8", "pl_r10_r8"},
- {{pl, r10, r9}, "pl, r10, r9", "pl_r10_r9"},
- {{pl, r10, r10}, "pl, r10, r10", "pl_r10_r10"},
- {{pl, r10, r11}, "pl, r10, r11", "pl_r10_r11"},
- {{pl, r10, r12}, "pl, r10, r12", "pl_r10_r12"},
- {{pl, r10, r13}, "pl, r10, r13", "pl_r10_r13"},
- {{pl, r10, r14}, "pl, r10, r14", "pl_r10_r14"},
- {{pl, r11, r0}, "pl, r11, r0", "pl_r11_r0"},
- {{pl, r11, r1}, "pl, r11, r1", "pl_r11_r1"},
- {{pl, r11, r2}, "pl, r11, r2", "pl_r11_r2"},
- {{pl, r11, r3}, "pl, r11, r3", "pl_r11_r3"},
- {{pl, r11, r4}, "pl, r11, r4", "pl_r11_r4"},
- {{pl, r11, r5}, "pl, r11, r5", "pl_r11_r5"},
- {{pl, r11, r6}, "pl, r11, r6", "pl_r11_r6"},
- {{pl, r11, r7}, "pl, r11, r7", "pl_r11_r7"},
- {{pl, r11, r8}, "pl, r11, r8", "pl_r11_r8"},
- {{pl, r11, r9}, "pl, r11, r9", "pl_r11_r9"},
- {{pl, r11, r10}, "pl, r11, r10", "pl_r11_r10"},
- {{pl, r11, r11}, "pl, r11, r11", "pl_r11_r11"},
- {{pl, r11, r12}, "pl, r11, r12", "pl_r11_r12"},
- {{pl, r11, r13}, "pl, r11, r13", "pl_r11_r13"},
- {{pl, r11, r14}, "pl, r11, r14", "pl_r11_r14"},
- {{pl, r12, r0}, "pl, r12, r0", "pl_r12_r0"},
- {{pl, r12, r1}, "pl, r12, r1", "pl_r12_r1"},
- {{pl, r12, r2}, "pl, r12, r2", "pl_r12_r2"},
- {{pl, r12, r3}, "pl, r12, r3", "pl_r12_r3"},
- {{pl, r12, r4}, "pl, r12, r4", "pl_r12_r4"},
- {{pl, r12, r5}, "pl, r12, r5", "pl_r12_r5"},
- {{pl, r12, r6}, "pl, r12, r6", "pl_r12_r6"},
- {{pl, r12, r7}, "pl, r12, r7", "pl_r12_r7"},
- {{pl, r12, r8}, "pl, r12, r8", "pl_r12_r8"},
- {{pl, r12, r9}, "pl, r12, r9", "pl_r12_r9"},
- {{pl, r12, r10}, "pl, r12, r10", "pl_r12_r10"},
- {{pl, r12, r11}, "pl, r12, r11", "pl_r12_r11"},
- {{pl, r12, r12}, "pl, r12, r12", "pl_r12_r12"},
- {{pl, r12, r13}, "pl, r12, r13", "pl_r12_r13"},
- {{pl, r12, r14}, "pl, r12, r14", "pl_r12_r14"},
- {{pl, r13, r0}, "pl, r13, r0", "pl_r13_r0"},
- {{pl, r13, r1}, "pl, r13, r1", "pl_r13_r1"},
- {{pl, r13, r2}, "pl, r13, r2", "pl_r13_r2"},
- {{pl, r13, r3}, "pl, r13, r3", "pl_r13_r3"},
- {{pl, r13, r4}, "pl, r13, r4", "pl_r13_r4"},
- {{pl, r13, r5}, "pl, r13, r5", "pl_r13_r5"},
- {{pl, r13, r6}, "pl, r13, r6", "pl_r13_r6"},
- {{pl, r13, r7}, "pl, r13, r7", "pl_r13_r7"},
- {{pl, r13, r8}, "pl, r13, r8", "pl_r13_r8"},
- {{pl, r13, r9}, "pl, r13, r9", "pl_r13_r9"},
- {{pl, r13, r10}, "pl, r13, r10", "pl_r13_r10"},
- {{pl, r13, r11}, "pl, r13, r11", "pl_r13_r11"},
- {{pl, r13, r12}, "pl, r13, r12", "pl_r13_r12"},
- {{pl, r13, r13}, "pl, r13, r13", "pl_r13_r13"},
- {{pl, r13, r14}, "pl, r13, r14", "pl_r13_r14"},
- {{pl, r14, r0}, "pl, r14, r0", "pl_r14_r0"},
- {{pl, r14, r1}, "pl, r14, r1", "pl_r14_r1"},
- {{pl, r14, r2}, "pl, r14, r2", "pl_r14_r2"},
- {{pl, r14, r3}, "pl, r14, r3", "pl_r14_r3"},
- {{pl, r14, r4}, "pl, r14, r4", "pl_r14_r4"},
- {{pl, r14, r5}, "pl, r14, r5", "pl_r14_r5"},
- {{pl, r14, r6}, "pl, r14, r6", "pl_r14_r6"},
- {{pl, r14, r7}, "pl, r14, r7", "pl_r14_r7"},
- {{pl, r14, r8}, "pl, r14, r8", "pl_r14_r8"},
- {{pl, r14, r9}, "pl, r14, r9", "pl_r14_r9"},
- {{pl, r14, r10}, "pl, r14, r10", "pl_r14_r10"},
- {{pl, r14, r11}, "pl, r14, r11", "pl_r14_r11"},
- {{pl, r14, r12}, "pl, r14, r12", "pl_r14_r12"},
- {{pl, r14, r13}, "pl, r14, r13", "pl_r14_r13"},
- {{pl, r14, r14}, "pl, r14, r14", "pl_r14_r14"},
- {{vs, r0, r0}, "vs, r0, r0", "vs_r0_r0"},
- {{vs, r0, r1}, "vs, r0, r1", "vs_r0_r1"},
- {{vs, r0, r2}, "vs, r0, r2", "vs_r0_r2"},
- {{vs, r0, r3}, "vs, r0, r3", "vs_r0_r3"},
- {{vs, r0, r4}, "vs, r0, r4", "vs_r0_r4"},
- {{vs, r0, r5}, "vs, r0, r5", "vs_r0_r5"},
- {{vs, r0, r6}, "vs, r0, r6", "vs_r0_r6"},
- {{vs, r0, r7}, "vs, r0, r7", "vs_r0_r7"},
- {{vs, r0, r8}, "vs, r0, r8", "vs_r0_r8"},
- {{vs, r0, r9}, "vs, r0, r9", "vs_r0_r9"},
- {{vs, r0, r10}, "vs, r0, r10", "vs_r0_r10"},
- {{vs, r0, r11}, "vs, r0, r11", "vs_r0_r11"},
- {{vs, r0, r12}, "vs, r0, r12", "vs_r0_r12"},
- {{vs, r0, r13}, "vs, r0, r13", "vs_r0_r13"},
- {{vs, r0, r14}, "vs, r0, r14", "vs_r0_r14"},
- {{vs, r1, r0}, "vs, r1, r0", "vs_r1_r0"},
- {{vs, r1, r1}, "vs, r1, r1", "vs_r1_r1"},
- {{vs, r1, r2}, "vs, r1, r2", "vs_r1_r2"},
- {{vs, r1, r3}, "vs, r1, r3", "vs_r1_r3"},
- {{vs, r1, r4}, "vs, r1, r4", "vs_r1_r4"},
- {{vs, r1, r5}, "vs, r1, r5", "vs_r1_r5"},
- {{vs, r1, r6}, "vs, r1, r6", "vs_r1_r6"},
- {{vs, r1, r7}, "vs, r1, r7", "vs_r1_r7"},
- {{vs, r1, r8}, "vs, r1, r8", "vs_r1_r8"},
- {{vs, r1, r9}, "vs, r1, r9", "vs_r1_r9"},
- {{vs, r1, r10}, "vs, r1, r10", "vs_r1_r10"},
- {{vs, r1, r11}, "vs, r1, r11", "vs_r1_r11"},
- {{vs, r1, r12}, "vs, r1, r12", "vs_r1_r12"},
- {{vs, r1, r13}, "vs, r1, r13", "vs_r1_r13"},
- {{vs, r1, r14}, "vs, r1, r14", "vs_r1_r14"},
- {{vs, r2, r0}, "vs, r2, r0", "vs_r2_r0"},
- {{vs, r2, r1}, "vs, r2, r1", "vs_r2_r1"},
- {{vs, r2, r2}, "vs, r2, r2", "vs_r2_r2"},
- {{vs, r2, r3}, "vs, r2, r3", "vs_r2_r3"},
- {{vs, r2, r4}, "vs, r2, r4", "vs_r2_r4"},
- {{vs, r2, r5}, "vs, r2, r5", "vs_r2_r5"},
- {{vs, r2, r6}, "vs, r2, r6", "vs_r2_r6"},
- {{vs, r2, r7}, "vs, r2, r7", "vs_r2_r7"},
- {{vs, r2, r8}, "vs, r2, r8", "vs_r2_r8"},
- {{vs, r2, r9}, "vs, r2, r9", "vs_r2_r9"},
- {{vs, r2, r10}, "vs, r2, r10", "vs_r2_r10"},
- {{vs, r2, r11}, "vs, r2, r11", "vs_r2_r11"},
- {{vs, r2, r12}, "vs, r2, r12", "vs_r2_r12"},
- {{vs, r2, r13}, "vs, r2, r13", "vs_r2_r13"},
- {{vs, r2, r14}, "vs, r2, r14", "vs_r2_r14"},
- {{vs, r3, r0}, "vs, r3, r0", "vs_r3_r0"},
- {{vs, r3, r1}, "vs, r3, r1", "vs_r3_r1"},
- {{vs, r3, r2}, "vs, r3, r2", "vs_r3_r2"},
- {{vs, r3, r3}, "vs, r3, r3", "vs_r3_r3"},
- {{vs, r3, r4}, "vs, r3, r4", "vs_r3_r4"},
- {{vs, r3, r5}, "vs, r3, r5", "vs_r3_r5"},
- {{vs, r3, r6}, "vs, r3, r6", "vs_r3_r6"},
- {{vs, r3, r7}, "vs, r3, r7", "vs_r3_r7"},
- {{vs, r3, r8}, "vs, r3, r8", "vs_r3_r8"},
- {{vs, r3, r9}, "vs, r3, r9", "vs_r3_r9"},
- {{vs, r3, r10}, "vs, r3, r10", "vs_r3_r10"},
- {{vs, r3, r11}, "vs, r3, r11", "vs_r3_r11"},
- {{vs, r3, r12}, "vs, r3, r12", "vs_r3_r12"},
- {{vs, r3, r13}, "vs, r3, r13", "vs_r3_r13"},
- {{vs, r3, r14}, "vs, r3, r14", "vs_r3_r14"},
- {{vs, r4, r0}, "vs, r4, r0", "vs_r4_r0"},
- {{vs, r4, r1}, "vs, r4, r1", "vs_r4_r1"},
- {{vs, r4, r2}, "vs, r4, r2", "vs_r4_r2"},
- {{vs, r4, r3}, "vs, r4, r3", "vs_r4_r3"},
- {{vs, r4, r4}, "vs, r4, r4", "vs_r4_r4"},
- {{vs, r4, r5}, "vs, r4, r5", "vs_r4_r5"},
- {{vs, r4, r6}, "vs, r4, r6", "vs_r4_r6"},
- {{vs, r4, r7}, "vs, r4, r7", "vs_r4_r7"},
- {{vs, r4, r8}, "vs, r4, r8", "vs_r4_r8"},
- {{vs, r4, r9}, "vs, r4, r9", "vs_r4_r9"},
- {{vs, r4, r10}, "vs, r4, r10", "vs_r4_r10"},
- {{vs, r4, r11}, "vs, r4, r11", "vs_r4_r11"},
- {{vs, r4, r12}, "vs, r4, r12", "vs_r4_r12"},
- {{vs, r4, r13}, "vs, r4, r13", "vs_r4_r13"},
- {{vs, r4, r14}, "vs, r4, r14", "vs_r4_r14"},
- {{vs, r5, r0}, "vs, r5, r0", "vs_r5_r0"},
- {{vs, r5, r1}, "vs, r5, r1", "vs_r5_r1"},
- {{vs, r5, r2}, "vs, r5, r2", "vs_r5_r2"},
- {{vs, r5, r3}, "vs, r5, r3", "vs_r5_r3"},
- {{vs, r5, r4}, "vs, r5, r4", "vs_r5_r4"},
- {{vs, r5, r5}, "vs, r5, r5", "vs_r5_r5"},
- {{vs, r5, r6}, "vs, r5, r6", "vs_r5_r6"},
- {{vs, r5, r7}, "vs, r5, r7", "vs_r5_r7"},
- {{vs, r5, r8}, "vs, r5, r8", "vs_r5_r8"},
- {{vs, r5, r9}, "vs, r5, r9", "vs_r5_r9"},
- {{vs, r5, r10}, "vs, r5, r10", "vs_r5_r10"},
- {{vs, r5, r11}, "vs, r5, r11", "vs_r5_r11"},
- {{vs, r5, r12}, "vs, r5, r12", "vs_r5_r12"},
- {{vs, r5, r13}, "vs, r5, r13", "vs_r5_r13"},
- {{vs, r5, r14}, "vs, r5, r14", "vs_r5_r14"},
- {{vs, r6, r0}, "vs, r6, r0", "vs_r6_r0"},
- {{vs, r6, r1}, "vs, r6, r1", "vs_r6_r1"},
- {{vs, r6, r2}, "vs, r6, r2", "vs_r6_r2"},
- {{vs, r6, r3}, "vs, r6, r3", "vs_r6_r3"},
- {{vs, r6, r4}, "vs, r6, r4", "vs_r6_r4"},
- {{vs, r6, r5}, "vs, r6, r5", "vs_r6_r5"},
- {{vs, r6, r6}, "vs, r6, r6", "vs_r6_r6"},
- {{vs, r6, r7}, "vs, r6, r7", "vs_r6_r7"},
- {{vs, r6, r8}, "vs, r6, r8", "vs_r6_r8"},
- {{vs, r6, r9}, "vs, r6, r9", "vs_r6_r9"},
- {{vs, r6, r10}, "vs, r6, r10", "vs_r6_r10"},
- {{vs, r6, r11}, "vs, r6, r11", "vs_r6_r11"},
- {{vs, r6, r12}, "vs, r6, r12", "vs_r6_r12"},
- {{vs, r6, r13}, "vs, r6, r13", "vs_r6_r13"},
- {{vs, r6, r14}, "vs, r6, r14", "vs_r6_r14"},
- {{vs, r7, r0}, "vs, r7, r0", "vs_r7_r0"},
- {{vs, r7, r1}, "vs, r7, r1", "vs_r7_r1"},
- {{vs, r7, r2}, "vs, r7, r2", "vs_r7_r2"},
- {{vs, r7, r3}, "vs, r7, r3", "vs_r7_r3"},
- {{vs, r7, r4}, "vs, r7, r4", "vs_r7_r4"},
- {{vs, r7, r5}, "vs, r7, r5", "vs_r7_r5"},
- {{vs, r7, r6}, "vs, r7, r6", "vs_r7_r6"},
- {{vs, r7, r7}, "vs, r7, r7", "vs_r7_r7"},
- {{vs, r7, r8}, "vs, r7, r8", "vs_r7_r8"},
- {{vs, r7, r9}, "vs, r7, r9", "vs_r7_r9"},
- {{vs, r7, r10}, "vs, r7, r10", "vs_r7_r10"},
- {{vs, r7, r11}, "vs, r7, r11", "vs_r7_r11"},
- {{vs, r7, r12}, "vs, r7, r12", "vs_r7_r12"},
- {{vs, r7, r13}, "vs, r7, r13", "vs_r7_r13"},
- {{vs, r7, r14}, "vs, r7, r14", "vs_r7_r14"},
- {{vs, r8, r0}, "vs, r8, r0", "vs_r8_r0"},
- {{vs, r8, r1}, "vs, r8, r1", "vs_r8_r1"},
- {{vs, r8, r2}, "vs, r8, r2", "vs_r8_r2"},
- {{vs, r8, r3}, "vs, r8, r3", "vs_r8_r3"},
- {{vs, r8, r4}, "vs, r8, r4", "vs_r8_r4"},
- {{vs, r8, r5}, "vs, r8, r5", "vs_r8_r5"},
- {{vs, r8, r6}, "vs, r8, r6", "vs_r8_r6"},
- {{vs, r8, r7}, "vs, r8, r7", "vs_r8_r7"},
- {{vs, r8, r8}, "vs, r8, r8", "vs_r8_r8"},
- {{vs, r8, r9}, "vs, r8, r9", "vs_r8_r9"},
- {{vs, r8, r10}, "vs, r8, r10", "vs_r8_r10"},
- {{vs, r8, r11}, "vs, r8, r11", "vs_r8_r11"},
- {{vs, r8, r12}, "vs, r8, r12", "vs_r8_r12"},
- {{vs, r8, r13}, "vs, r8, r13", "vs_r8_r13"},
- {{vs, r8, r14}, "vs, r8, r14", "vs_r8_r14"},
- {{vs, r9, r0}, "vs, r9, r0", "vs_r9_r0"},
- {{vs, r9, r1}, "vs, r9, r1", "vs_r9_r1"},
- {{vs, r9, r2}, "vs, r9, r2", "vs_r9_r2"},
- {{vs, r9, r3}, "vs, r9, r3", "vs_r9_r3"},
- {{vs, r9, r4}, "vs, r9, r4", "vs_r9_r4"},
- {{vs, r9, r5}, "vs, r9, r5", "vs_r9_r5"},
- {{vs, r9, r6}, "vs, r9, r6", "vs_r9_r6"},
- {{vs, r9, r7}, "vs, r9, r7", "vs_r9_r7"},
- {{vs, r9, r8}, "vs, r9, r8", "vs_r9_r8"},
- {{vs, r9, r9}, "vs, r9, r9", "vs_r9_r9"},
- {{vs, r9, r10}, "vs, r9, r10", "vs_r9_r10"},
- {{vs, r9, r11}, "vs, r9, r11", "vs_r9_r11"},
- {{vs, r9, r12}, "vs, r9, r12", "vs_r9_r12"},
- {{vs, r9, r13}, "vs, r9, r13", "vs_r9_r13"},
- {{vs, r9, r14}, "vs, r9, r14", "vs_r9_r14"},
- {{vs, r10, r0}, "vs, r10, r0", "vs_r10_r0"},
- {{vs, r10, r1}, "vs, r10, r1", "vs_r10_r1"},
- {{vs, r10, r2}, "vs, r10, r2", "vs_r10_r2"},
- {{vs, r10, r3}, "vs, r10, r3", "vs_r10_r3"},
- {{vs, r10, r4}, "vs, r10, r4", "vs_r10_r4"},
- {{vs, r10, r5}, "vs, r10, r5", "vs_r10_r5"},
- {{vs, r10, r6}, "vs, r10, r6", "vs_r10_r6"},
- {{vs, r10, r7}, "vs, r10, r7", "vs_r10_r7"},
- {{vs, r10, r8}, "vs, r10, r8", "vs_r10_r8"},
- {{vs, r10, r9}, "vs, r10, r9", "vs_r10_r9"},
- {{vs, r10, r10}, "vs, r10, r10", "vs_r10_r10"},
- {{vs, r10, r11}, "vs, r10, r11", "vs_r10_r11"},
- {{vs, r10, r12}, "vs, r10, r12", "vs_r10_r12"},
- {{vs, r10, r13}, "vs, r10, r13", "vs_r10_r13"},
- {{vs, r10, r14}, "vs, r10, r14", "vs_r10_r14"},
- {{vs, r11, r0}, "vs, r11, r0", "vs_r11_r0"},
- {{vs, r11, r1}, "vs, r11, r1", "vs_r11_r1"},
- {{vs, r11, r2}, "vs, r11, r2", "vs_r11_r2"},
- {{vs, r11, r3}, "vs, r11, r3", "vs_r11_r3"},
- {{vs, r11, r4}, "vs, r11, r4", "vs_r11_r4"},
- {{vs, r11, r5}, "vs, r11, r5", "vs_r11_r5"},
- {{vs, r11, r6}, "vs, r11, r6", "vs_r11_r6"},
- {{vs, r11, r7}, "vs, r11, r7", "vs_r11_r7"},
- {{vs, r11, r8}, "vs, r11, r8", "vs_r11_r8"},
- {{vs, r11, r9}, "vs, r11, r9", "vs_r11_r9"},
- {{vs, r11, r10}, "vs, r11, r10", "vs_r11_r10"},
- {{vs, r11, r11}, "vs, r11, r11", "vs_r11_r11"},
- {{vs, r11, r12}, "vs, r11, r12", "vs_r11_r12"},
- {{vs, r11, r13}, "vs, r11, r13", "vs_r11_r13"},
- {{vs, r11, r14}, "vs, r11, r14", "vs_r11_r14"},
- {{vs, r12, r0}, "vs, r12, r0", "vs_r12_r0"},
- {{vs, r12, r1}, "vs, r12, r1", "vs_r12_r1"},
- {{vs, r12, r2}, "vs, r12, r2", "vs_r12_r2"},
- {{vs, r12, r3}, "vs, r12, r3", "vs_r12_r3"},
- {{vs, r12, r4}, "vs, r12, r4", "vs_r12_r4"},
- {{vs, r12, r5}, "vs, r12, r5", "vs_r12_r5"},
- {{vs, r12, r6}, "vs, r12, r6", "vs_r12_r6"},
- {{vs, r12, r7}, "vs, r12, r7", "vs_r12_r7"},
- {{vs, r12, r8}, "vs, r12, r8", "vs_r12_r8"},
- {{vs, r12, r9}, "vs, r12, r9", "vs_r12_r9"},
- {{vs, r12, r10}, "vs, r12, r10", "vs_r12_r10"},
- {{vs, r12, r11}, "vs, r12, r11", "vs_r12_r11"},
- {{vs, r12, r12}, "vs, r12, r12", "vs_r12_r12"},
- {{vs, r12, r13}, "vs, r12, r13", "vs_r12_r13"},
- {{vs, r12, r14}, "vs, r12, r14", "vs_r12_r14"},
- {{vs, r13, r0}, "vs, r13, r0", "vs_r13_r0"},
- {{vs, r13, r1}, "vs, r13, r1", "vs_r13_r1"},
- {{vs, r13, r2}, "vs, r13, r2", "vs_r13_r2"},
- {{vs, r13, r3}, "vs, r13, r3", "vs_r13_r3"},
- {{vs, r13, r4}, "vs, r13, r4", "vs_r13_r4"},
- {{vs, r13, r5}, "vs, r13, r5", "vs_r13_r5"},
- {{vs, r13, r6}, "vs, r13, r6", "vs_r13_r6"},
- {{vs, r13, r7}, "vs, r13, r7", "vs_r13_r7"},
- {{vs, r13, r8}, "vs, r13, r8", "vs_r13_r8"},
- {{vs, r13, r9}, "vs, r13, r9", "vs_r13_r9"},
- {{vs, r13, r10}, "vs, r13, r10", "vs_r13_r10"},
- {{vs, r13, r11}, "vs, r13, r11", "vs_r13_r11"},
- {{vs, r13, r12}, "vs, r13, r12", "vs_r13_r12"},
- {{vs, r13, r13}, "vs, r13, r13", "vs_r13_r13"},
- {{vs, r13, r14}, "vs, r13, r14", "vs_r13_r14"},
- {{vs, r14, r0}, "vs, r14, r0", "vs_r14_r0"},
- {{vs, r14, r1}, "vs, r14, r1", "vs_r14_r1"},
- {{vs, r14, r2}, "vs, r14, r2", "vs_r14_r2"},
- {{vs, r14, r3}, "vs, r14, r3", "vs_r14_r3"},
- {{vs, r14, r4}, "vs, r14, r4", "vs_r14_r4"},
- {{vs, r14, r5}, "vs, r14, r5", "vs_r14_r5"},
- {{vs, r14, r6}, "vs, r14, r6", "vs_r14_r6"},
- {{vs, r14, r7}, "vs, r14, r7", "vs_r14_r7"},
- {{vs, r14, r8}, "vs, r14, r8", "vs_r14_r8"},
- {{vs, r14, r9}, "vs, r14, r9", "vs_r14_r9"},
- {{vs, r14, r10}, "vs, r14, r10", "vs_r14_r10"},
- {{vs, r14, r11}, "vs, r14, r11", "vs_r14_r11"},
- {{vs, r14, r12}, "vs, r14, r12", "vs_r14_r12"},
- {{vs, r14, r13}, "vs, r14, r13", "vs_r14_r13"},
- {{vs, r14, r14}, "vs, r14, r14", "vs_r14_r14"},
- {{vc, r0, r0}, "vc, r0, r0", "vc_r0_r0"},
- {{vc, r0, r1}, "vc, r0, r1", "vc_r0_r1"},
- {{vc, r0, r2}, "vc, r0, r2", "vc_r0_r2"},
- {{vc, r0, r3}, "vc, r0, r3", "vc_r0_r3"},
- {{vc, r0, r4}, "vc, r0, r4", "vc_r0_r4"},
- {{vc, r0, r5}, "vc, r0, r5", "vc_r0_r5"},
- {{vc, r0, r6}, "vc, r0, r6", "vc_r0_r6"},
- {{vc, r0, r7}, "vc, r0, r7", "vc_r0_r7"},
- {{vc, r0, r8}, "vc, r0, r8", "vc_r0_r8"},
- {{vc, r0, r9}, "vc, r0, r9", "vc_r0_r9"},
- {{vc, r0, r10}, "vc, r0, r10", "vc_r0_r10"},
- {{vc, r0, r11}, "vc, r0, r11", "vc_r0_r11"},
- {{vc, r0, r12}, "vc, r0, r12", "vc_r0_r12"},
- {{vc, r0, r13}, "vc, r0, r13", "vc_r0_r13"},
- {{vc, r0, r14}, "vc, r0, r14", "vc_r0_r14"},
- {{vc, r1, r0}, "vc, r1, r0", "vc_r1_r0"},
- {{vc, r1, r1}, "vc, r1, r1", "vc_r1_r1"},
- {{vc, r1, r2}, "vc, r1, r2", "vc_r1_r2"},
- {{vc, r1, r3}, "vc, r1, r3", "vc_r1_r3"},
- {{vc, r1, r4}, "vc, r1, r4", "vc_r1_r4"},
- {{vc, r1, r5}, "vc, r1, r5", "vc_r1_r5"},
- {{vc, r1, r6}, "vc, r1, r6", "vc_r1_r6"},
- {{vc, r1, r7}, "vc, r1, r7", "vc_r1_r7"},
- {{vc, r1, r8}, "vc, r1, r8", "vc_r1_r8"},
- {{vc, r1, r9}, "vc, r1, r9", "vc_r1_r9"},
- {{vc, r1, r10}, "vc, r1, r10", "vc_r1_r10"},
- {{vc, r1, r11}, "vc, r1, r11", "vc_r1_r11"},
- {{vc, r1, r12}, "vc, r1, r12", "vc_r1_r12"},
- {{vc, r1, r13}, "vc, r1, r13", "vc_r1_r13"},
- {{vc, r1, r14}, "vc, r1, r14", "vc_r1_r14"},
- {{vc, r2, r0}, "vc, r2, r0", "vc_r2_r0"},
- {{vc, r2, r1}, "vc, r2, r1", "vc_r2_r1"},
- {{vc, r2, r2}, "vc, r2, r2", "vc_r2_r2"},
- {{vc, r2, r3}, "vc, r2, r3", "vc_r2_r3"},
- {{vc, r2, r4}, "vc, r2, r4", "vc_r2_r4"},
- {{vc, r2, r5}, "vc, r2, r5", "vc_r2_r5"},
- {{vc, r2, r6}, "vc, r2, r6", "vc_r2_r6"},
- {{vc, r2, r7}, "vc, r2, r7", "vc_r2_r7"},
- {{vc, r2, r8}, "vc, r2, r8", "vc_r2_r8"},
- {{vc, r2, r9}, "vc, r2, r9", "vc_r2_r9"},
- {{vc, r2, r10}, "vc, r2, r10", "vc_r2_r10"},
- {{vc, r2, r11}, "vc, r2, r11", "vc_r2_r11"},
- {{vc, r2, r12}, "vc, r2, r12", "vc_r2_r12"},
- {{vc, r2, r13}, "vc, r2, r13", "vc_r2_r13"},
- {{vc, r2, r14}, "vc, r2, r14", "vc_r2_r14"},
- {{vc, r3, r0}, "vc, r3, r0", "vc_r3_r0"},
- {{vc, r3, r1}, "vc, r3, r1", "vc_r3_r1"},
- {{vc, r3, r2}, "vc, r3, r2", "vc_r3_r2"},
- {{vc, r3, r3}, "vc, r3, r3", "vc_r3_r3"},
- {{vc, r3, r4}, "vc, r3, r4", "vc_r3_r4"},
- {{vc, r3, r5}, "vc, r3, r5", "vc_r3_r5"},
- {{vc, r3, r6}, "vc, r3, r6", "vc_r3_r6"},
- {{vc, r3, r7}, "vc, r3, r7", "vc_r3_r7"},
- {{vc, r3, r8}, "vc, r3, r8", "vc_r3_r8"},
- {{vc, r3, r9}, "vc, r3, r9", "vc_r3_r9"},
- {{vc, r3, r10}, "vc, r3, r10", "vc_r3_r10"},
- {{vc, r3, r11}, "vc, r3, r11", "vc_r3_r11"},
- {{vc, r3, r12}, "vc, r3, r12", "vc_r3_r12"},
- {{vc, r3, r13}, "vc, r3, r13", "vc_r3_r13"},
- {{vc, r3, r14}, "vc, r3, r14", "vc_r3_r14"},
- {{vc, r4, r0}, "vc, r4, r0", "vc_r4_r0"},
- {{vc, r4, r1}, "vc, r4, r1", "vc_r4_r1"},
- {{vc, r4, r2}, "vc, r4, r2", "vc_r4_r2"},
- {{vc, r4, r3}, "vc, r4, r3", "vc_r4_r3"},
- {{vc, r4, r4}, "vc, r4, r4", "vc_r4_r4"},
- {{vc, r4, r5}, "vc, r4, r5", "vc_r4_r5"},
- {{vc, r4, r6}, "vc, r4, r6", "vc_r4_r6"},
- {{vc, r4, r7}, "vc, r4, r7", "vc_r4_r7"},
- {{vc, r4, r8}, "vc, r4, r8", "vc_r4_r8"},
- {{vc, r4, r9}, "vc, r4, r9", "vc_r4_r9"},
- {{vc, r4, r10}, "vc, r4, r10", "vc_r4_r10"},
- {{vc, r4, r11}, "vc, r4, r11", "vc_r4_r11"},
- {{vc, r4, r12}, "vc, r4, r12", "vc_r4_r12"},
- {{vc, r4, r13}, "vc, r4, r13", "vc_r4_r13"},
- {{vc, r4, r14}, "vc, r4, r14", "vc_r4_r14"},
- {{vc, r5, r0}, "vc, r5, r0", "vc_r5_r0"},
- {{vc, r5, r1}, "vc, r5, r1", "vc_r5_r1"},
- {{vc, r5, r2}, "vc, r5, r2", "vc_r5_r2"},
- {{vc, r5, r3}, "vc, r5, r3", "vc_r5_r3"},
- {{vc, r5, r4}, "vc, r5, r4", "vc_r5_r4"},
- {{vc, r5, r5}, "vc, r5, r5", "vc_r5_r5"},
- {{vc, r5, r6}, "vc, r5, r6", "vc_r5_r6"},
- {{vc, r5, r7}, "vc, r5, r7", "vc_r5_r7"},
- {{vc, r5, r8}, "vc, r5, r8", "vc_r5_r8"},
- {{vc, r5, r9}, "vc, r5, r9", "vc_r5_r9"},
- {{vc, r5, r10}, "vc, r5, r10", "vc_r5_r10"},
- {{vc, r5, r11}, "vc, r5, r11", "vc_r5_r11"},
- {{vc, r5, r12}, "vc, r5, r12", "vc_r5_r12"},
- {{vc, r5, r13}, "vc, r5, r13", "vc_r5_r13"},
- {{vc, r5, r14}, "vc, r5, r14", "vc_r5_r14"},
- {{vc, r6, r0}, "vc, r6, r0", "vc_r6_r0"},
- {{vc, r6, r1}, "vc, r6, r1", "vc_r6_r1"},
- {{vc, r6, r2}, "vc, r6, r2", "vc_r6_r2"},
- {{vc, r6, r3}, "vc, r6, r3", "vc_r6_r3"},
- {{vc, r6, r4}, "vc, r6, r4", "vc_r6_r4"},
- {{vc, r6, r5}, "vc, r6, r5", "vc_r6_r5"},
- {{vc, r6, r6}, "vc, r6, r6", "vc_r6_r6"},
- {{vc, r6, r7}, "vc, r6, r7", "vc_r6_r7"},
- {{vc, r6, r8}, "vc, r6, r8", "vc_r6_r8"},
- {{vc, r6, r9}, "vc, r6, r9", "vc_r6_r9"},
- {{vc, r6, r10}, "vc, r6, r10", "vc_r6_r10"},
- {{vc, r6, r11}, "vc, r6, r11", "vc_r6_r11"},
- {{vc, r6, r12}, "vc, r6, r12", "vc_r6_r12"},
- {{vc, r6, r13}, "vc, r6, r13", "vc_r6_r13"},
- {{vc, r6, r14}, "vc, r6, r14", "vc_r6_r14"},
- {{vc, r7, r0}, "vc, r7, r0", "vc_r7_r0"},
- {{vc, r7, r1}, "vc, r7, r1", "vc_r7_r1"},
- {{vc, r7, r2}, "vc, r7, r2", "vc_r7_r2"},
- {{vc, r7, r3}, "vc, r7, r3", "vc_r7_r3"},
- {{vc, r7, r4}, "vc, r7, r4", "vc_r7_r4"},
- {{vc, r7, r5}, "vc, r7, r5", "vc_r7_r5"},
- {{vc, r7, r6}, "vc, r7, r6", "vc_r7_r6"},
- {{vc, r7, r7}, "vc, r7, r7", "vc_r7_r7"},
- {{vc, r7, r8}, "vc, r7, r8", "vc_r7_r8"},
- {{vc, r7, r9}, "vc, r7, r9", "vc_r7_r9"},
- {{vc, r7, r10}, "vc, r7, r10", "vc_r7_r10"},
- {{vc, r7, r11}, "vc, r7, r11", "vc_r7_r11"},
- {{vc, r7, r12}, "vc, r7, r12", "vc_r7_r12"},
- {{vc, r7, r13}, "vc, r7, r13", "vc_r7_r13"},
- {{vc, r7, r14}, "vc, r7, r14", "vc_r7_r14"},
- {{vc, r8, r0}, "vc, r8, r0", "vc_r8_r0"},
- {{vc, r8, r1}, "vc, r8, r1", "vc_r8_r1"},
- {{vc, r8, r2}, "vc, r8, r2", "vc_r8_r2"},
- {{vc, r8, r3}, "vc, r8, r3", "vc_r8_r3"},
- {{vc, r8, r4}, "vc, r8, r4", "vc_r8_r4"},
- {{vc, r8, r5}, "vc, r8, r5", "vc_r8_r5"},
- {{vc, r8, r6}, "vc, r8, r6", "vc_r8_r6"},
- {{vc, r8, r7}, "vc, r8, r7", "vc_r8_r7"},
- {{vc, r8, r8}, "vc, r8, r8", "vc_r8_r8"},
- {{vc, r8, r9}, "vc, r8, r9", "vc_r8_r9"},
- {{vc, r8, r10}, "vc, r8, r10", "vc_r8_r10"},
- {{vc, r8, r11}, "vc, r8, r11", "vc_r8_r11"},
- {{vc, r8, r12}, "vc, r8, r12", "vc_r8_r12"},
- {{vc, r8, r13}, "vc, r8, r13", "vc_r8_r13"},
- {{vc, r8, r14}, "vc, r8, r14", "vc_r8_r14"},
- {{vc, r9, r0}, "vc, r9, r0", "vc_r9_r0"},
- {{vc, r9, r1}, "vc, r9, r1", "vc_r9_r1"},
- {{vc, r9, r2}, "vc, r9, r2", "vc_r9_r2"},
- {{vc, r9, r3}, "vc, r9, r3", "vc_r9_r3"},
- {{vc, r9, r4}, "vc, r9, r4", "vc_r9_r4"},
- {{vc, r9, r5}, "vc, r9, r5", "vc_r9_r5"},
- {{vc, r9, r6}, "vc, r9, r6", "vc_r9_r6"},
- {{vc, r9, r7}, "vc, r9, r7", "vc_r9_r7"},
- {{vc, r9, r8}, "vc, r9, r8", "vc_r9_r8"},
- {{vc, r9, r9}, "vc, r9, r9", "vc_r9_r9"},
- {{vc, r9, r10}, "vc, r9, r10", "vc_r9_r10"},
- {{vc, r9, r11}, "vc, r9, r11", "vc_r9_r11"},
- {{vc, r9, r12}, "vc, r9, r12", "vc_r9_r12"},
- {{vc, r9, r13}, "vc, r9, r13", "vc_r9_r13"},
- {{vc, r9, r14}, "vc, r9, r14", "vc_r9_r14"},
- {{vc, r10, r0}, "vc, r10, r0", "vc_r10_r0"},
- {{vc, r10, r1}, "vc, r10, r1", "vc_r10_r1"},
- {{vc, r10, r2}, "vc, r10, r2", "vc_r10_r2"},
- {{vc, r10, r3}, "vc, r10, r3", "vc_r10_r3"},
- {{vc, r10, r4}, "vc, r10, r4", "vc_r10_r4"},
- {{vc, r10, r5}, "vc, r10, r5", "vc_r10_r5"},
- {{vc, r10, r6}, "vc, r10, r6", "vc_r10_r6"},
- {{vc, r10, r7}, "vc, r10, r7", "vc_r10_r7"},
- {{vc, r10, r8}, "vc, r10, r8", "vc_r10_r8"},
- {{vc, r10, r9}, "vc, r10, r9", "vc_r10_r9"},
- {{vc, r10, r10}, "vc, r10, r10", "vc_r10_r10"},
- {{vc, r10, r11}, "vc, r10, r11", "vc_r10_r11"},
- {{vc, r10, r12}, "vc, r10, r12", "vc_r10_r12"},
- {{vc, r10, r13}, "vc, r10, r13", "vc_r10_r13"},
- {{vc, r10, r14}, "vc, r10, r14", "vc_r10_r14"},
- {{vc, r11, r0}, "vc, r11, r0", "vc_r11_r0"},
- {{vc, r11, r1}, "vc, r11, r1", "vc_r11_r1"},
- {{vc, r11, r2}, "vc, r11, r2", "vc_r11_r2"},
- {{vc, r11, r3}, "vc, r11, r3", "vc_r11_r3"},
- {{vc, r11, r4}, "vc, r11, r4", "vc_r11_r4"},
- {{vc, r11, r5}, "vc, r11, r5", "vc_r11_r5"},
- {{vc, r11, r6}, "vc, r11, r6", "vc_r11_r6"},
- {{vc, r11, r7}, "vc, r11, r7", "vc_r11_r7"},
- {{vc, r11, r8}, "vc, r11, r8", "vc_r11_r8"},
- {{vc, r11, r9}, "vc, r11, r9", "vc_r11_r9"},
- {{vc, r11, r10}, "vc, r11, r10", "vc_r11_r10"},
- {{vc, r11, r11}, "vc, r11, r11", "vc_r11_r11"},
- {{vc, r11, r12}, "vc, r11, r12", "vc_r11_r12"},
- {{vc, r11, r13}, "vc, r11, r13", "vc_r11_r13"},
- {{vc, r11, r14}, "vc, r11, r14", "vc_r11_r14"},
- {{vc, r12, r0}, "vc, r12, r0", "vc_r12_r0"},
- {{vc, r12, r1}, "vc, r12, r1", "vc_r12_r1"},
- {{vc, r12, r2}, "vc, r12, r2", "vc_r12_r2"},
- {{vc, r12, r3}, "vc, r12, r3", "vc_r12_r3"},
- {{vc, r12, r4}, "vc, r12, r4", "vc_r12_r4"},
- {{vc, r12, r5}, "vc, r12, r5", "vc_r12_r5"},
- {{vc, r12, r6}, "vc, r12, r6", "vc_r12_r6"},
- {{vc, r12, r7}, "vc, r12, r7", "vc_r12_r7"},
- {{vc, r12, r8}, "vc, r12, r8", "vc_r12_r8"},
- {{vc, r12, r9}, "vc, r12, r9", "vc_r12_r9"},
- {{vc, r12, r10}, "vc, r12, r10", "vc_r12_r10"},
- {{vc, r12, r11}, "vc, r12, r11", "vc_r12_r11"},
- {{vc, r12, r12}, "vc, r12, r12", "vc_r12_r12"},
- {{vc, r12, r13}, "vc, r12, r13", "vc_r12_r13"},
- {{vc, r12, r14}, "vc, r12, r14", "vc_r12_r14"},
- {{vc, r13, r0}, "vc, r13, r0", "vc_r13_r0"},
- {{vc, r13, r1}, "vc, r13, r1", "vc_r13_r1"},
- {{vc, r13, r2}, "vc, r13, r2", "vc_r13_r2"},
- {{vc, r13, r3}, "vc, r13, r3", "vc_r13_r3"},
- {{vc, r13, r4}, "vc, r13, r4", "vc_r13_r4"},
- {{vc, r13, r5}, "vc, r13, r5", "vc_r13_r5"},
- {{vc, r13, r6}, "vc, r13, r6", "vc_r13_r6"},
- {{vc, r13, r7}, "vc, r13, r7", "vc_r13_r7"},
- {{vc, r13, r8}, "vc, r13, r8", "vc_r13_r8"},
- {{vc, r13, r9}, "vc, r13, r9", "vc_r13_r9"},
- {{vc, r13, r10}, "vc, r13, r10", "vc_r13_r10"},
- {{vc, r13, r11}, "vc, r13, r11", "vc_r13_r11"},
- {{vc, r13, r12}, "vc, r13, r12", "vc_r13_r12"},
- {{vc, r13, r13}, "vc, r13, r13", "vc_r13_r13"},
- {{vc, r13, r14}, "vc, r13, r14", "vc_r13_r14"},
- {{vc, r14, r0}, "vc, r14, r0", "vc_r14_r0"},
- {{vc, r14, r1}, "vc, r14, r1", "vc_r14_r1"},
- {{vc, r14, r2}, "vc, r14, r2", "vc_r14_r2"},
- {{vc, r14, r3}, "vc, r14, r3", "vc_r14_r3"},
- {{vc, r14, r4}, "vc, r14, r4", "vc_r14_r4"},
- {{vc, r14, r5}, "vc, r14, r5", "vc_r14_r5"},
- {{vc, r14, r6}, "vc, r14, r6", "vc_r14_r6"},
- {{vc, r14, r7}, "vc, r14, r7", "vc_r14_r7"},
- {{vc, r14, r8}, "vc, r14, r8", "vc_r14_r8"},
- {{vc, r14, r9}, "vc, r14, r9", "vc_r14_r9"},
- {{vc, r14, r10}, "vc, r14, r10", "vc_r14_r10"},
- {{vc, r14, r11}, "vc, r14, r11", "vc_r14_r11"},
- {{vc, r14, r12}, "vc, r14, r12", "vc_r14_r12"},
- {{vc, r14, r13}, "vc, r14, r13", "vc_r14_r13"},
- {{vc, r14, r14}, "vc, r14, r14", "vc_r14_r14"},
- {{hi, r0, r0}, "hi, r0, r0", "hi_r0_r0"},
- {{hi, r0, r1}, "hi, r0, r1", "hi_r0_r1"},
- {{hi, r0, r2}, "hi, r0, r2", "hi_r0_r2"},
- {{hi, r0, r3}, "hi, r0, r3", "hi_r0_r3"},
- {{hi, r0, r4}, "hi, r0, r4", "hi_r0_r4"},
- {{hi, r0, r5}, "hi, r0, r5", "hi_r0_r5"},
- {{hi, r0, r6}, "hi, r0, r6", "hi_r0_r6"},
- {{hi, r0, r7}, "hi, r0, r7", "hi_r0_r7"},
- {{hi, r0, r8}, "hi, r0, r8", "hi_r0_r8"},
- {{hi, r0, r9}, "hi, r0, r9", "hi_r0_r9"},
- {{hi, r0, r10}, "hi, r0, r10", "hi_r0_r10"},
- {{hi, r0, r11}, "hi, r0, r11", "hi_r0_r11"},
- {{hi, r0, r12}, "hi, r0, r12", "hi_r0_r12"},
- {{hi, r0, r13}, "hi, r0, r13", "hi_r0_r13"},
- {{hi, r0, r14}, "hi, r0, r14", "hi_r0_r14"},
- {{hi, r1, r0}, "hi, r1, r0", "hi_r1_r0"},
- {{hi, r1, r1}, "hi, r1, r1", "hi_r1_r1"},
- {{hi, r1, r2}, "hi, r1, r2", "hi_r1_r2"},
- {{hi, r1, r3}, "hi, r1, r3", "hi_r1_r3"},
- {{hi, r1, r4}, "hi, r1, r4", "hi_r1_r4"},
- {{hi, r1, r5}, "hi, r1, r5", "hi_r1_r5"},
- {{hi, r1, r6}, "hi, r1, r6", "hi_r1_r6"},
- {{hi, r1, r7}, "hi, r1, r7", "hi_r1_r7"},
- {{hi, r1, r8}, "hi, r1, r8", "hi_r1_r8"},
- {{hi, r1, r9}, "hi, r1, r9", "hi_r1_r9"},
- {{hi, r1, r10}, "hi, r1, r10", "hi_r1_r10"},
- {{hi, r1, r11}, "hi, r1, r11", "hi_r1_r11"},
- {{hi, r1, r12}, "hi, r1, r12", "hi_r1_r12"},
- {{hi, r1, r13}, "hi, r1, r13", "hi_r1_r13"},
- {{hi, r1, r14}, "hi, r1, r14", "hi_r1_r14"},
- {{hi, r2, r0}, "hi, r2, r0", "hi_r2_r0"},
- {{hi, r2, r1}, "hi, r2, r1", "hi_r2_r1"},
- {{hi, r2, r2}, "hi, r2, r2", "hi_r2_r2"},
- {{hi, r2, r3}, "hi, r2, r3", "hi_r2_r3"},
- {{hi, r2, r4}, "hi, r2, r4", "hi_r2_r4"},
- {{hi, r2, r5}, "hi, r2, r5", "hi_r2_r5"},
- {{hi, r2, r6}, "hi, r2, r6", "hi_r2_r6"},
- {{hi, r2, r7}, "hi, r2, r7", "hi_r2_r7"},
- {{hi, r2, r8}, "hi, r2, r8", "hi_r2_r8"},
- {{hi, r2, r9}, "hi, r2, r9", "hi_r2_r9"},
- {{hi, r2, r10}, "hi, r2, r10", "hi_r2_r10"},
- {{hi, r2, r11}, "hi, r2, r11", "hi_r2_r11"},
- {{hi, r2, r12}, "hi, r2, r12", "hi_r2_r12"},
- {{hi, r2, r13}, "hi, r2, r13", "hi_r2_r13"},
- {{hi, r2, r14}, "hi, r2, r14", "hi_r2_r14"},
- {{hi, r3, r0}, "hi, r3, r0", "hi_r3_r0"},
- {{hi, r3, r1}, "hi, r3, r1", "hi_r3_r1"},
- {{hi, r3, r2}, "hi, r3, r2", "hi_r3_r2"},
- {{hi, r3, r3}, "hi, r3, r3", "hi_r3_r3"},
- {{hi, r3, r4}, "hi, r3, r4", "hi_r3_r4"},
- {{hi, r3, r5}, "hi, r3, r5", "hi_r3_r5"},
- {{hi, r3, r6}, "hi, r3, r6", "hi_r3_r6"},
- {{hi, r3, r7}, "hi, r3, r7", "hi_r3_r7"},
- {{hi, r3, r8}, "hi, r3, r8", "hi_r3_r8"},
- {{hi, r3, r9}, "hi, r3, r9", "hi_r3_r9"},
- {{hi, r3, r10}, "hi, r3, r10", "hi_r3_r10"},
- {{hi, r3, r11}, "hi, r3, r11", "hi_r3_r11"},
- {{hi, r3, r12}, "hi, r3, r12", "hi_r3_r12"},
- {{hi, r3, r13}, "hi, r3, r13", "hi_r3_r13"},
- {{hi, r3, r14}, "hi, r3, r14", "hi_r3_r14"},
- {{hi, r4, r0}, "hi, r4, r0", "hi_r4_r0"},
- {{hi, r4, r1}, "hi, r4, r1", "hi_r4_r1"},
- {{hi, r4, r2}, "hi, r4, r2", "hi_r4_r2"},
- {{hi, r4, r3}, "hi, r4, r3", "hi_r4_r3"},
- {{hi, r4, r4}, "hi, r4, r4", "hi_r4_r4"},
- {{hi, r4, r5}, "hi, r4, r5", "hi_r4_r5"},
- {{hi, r4, r6}, "hi, r4, r6", "hi_r4_r6"},
- {{hi, r4, r7}, "hi, r4, r7", "hi_r4_r7"},
- {{hi, r4, r8}, "hi, r4, r8", "hi_r4_r8"},
- {{hi, r4, r9}, "hi, r4, r9", "hi_r4_r9"},
- {{hi, r4, r10}, "hi, r4, r10", "hi_r4_r10"},
- {{hi, r4, r11}, "hi, r4, r11", "hi_r4_r11"},
- {{hi, r4, r12}, "hi, r4, r12", "hi_r4_r12"},
- {{hi, r4, r13}, "hi, r4, r13", "hi_r4_r13"},
- {{hi, r4, r14}, "hi, r4, r14", "hi_r4_r14"},
- {{hi, r5, r0}, "hi, r5, r0", "hi_r5_r0"},
- {{hi, r5, r1}, "hi, r5, r1", "hi_r5_r1"},
- {{hi, r5, r2}, "hi, r5, r2", "hi_r5_r2"},
- {{hi, r5, r3}, "hi, r5, r3", "hi_r5_r3"},
- {{hi, r5, r4}, "hi, r5, r4", "hi_r5_r4"},
- {{hi, r5, r5}, "hi, r5, r5", "hi_r5_r5"},
- {{hi, r5, r6}, "hi, r5, r6", "hi_r5_r6"},
- {{hi, r5, r7}, "hi, r5, r7", "hi_r5_r7"},
- {{hi, r5, r8}, "hi, r5, r8", "hi_r5_r8"},
- {{hi, r5, r9}, "hi, r5, r9", "hi_r5_r9"},
- {{hi, r5, r10}, "hi, r5, r10", "hi_r5_r10"},
- {{hi, r5, r11}, "hi, r5, r11", "hi_r5_r11"},
- {{hi, r5, r12}, "hi, r5, r12", "hi_r5_r12"},
- {{hi, r5, r13}, "hi, r5, r13", "hi_r5_r13"},
- {{hi, r5, r14}, "hi, r5, r14", "hi_r5_r14"},
- {{hi, r6, r0}, "hi, r6, r0", "hi_r6_r0"},
- {{hi, r6, r1}, "hi, r6, r1", "hi_r6_r1"},
- {{hi, r6, r2}, "hi, r6, r2", "hi_r6_r2"},
- {{hi, r6, r3}, "hi, r6, r3", "hi_r6_r3"},
- {{hi, r6, r4}, "hi, r6, r4", "hi_r6_r4"},
- {{hi, r6, r5}, "hi, r6, r5", "hi_r6_r5"},
- {{hi, r6, r6}, "hi, r6, r6", "hi_r6_r6"},
- {{hi, r6, r7}, "hi, r6, r7", "hi_r6_r7"},
- {{hi, r6, r8}, "hi, r6, r8", "hi_r6_r8"},
- {{hi, r6, r9}, "hi, r6, r9", "hi_r6_r9"},
- {{hi, r6, r10}, "hi, r6, r10", "hi_r6_r10"},
- {{hi, r6, r11}, "hi, r6, r11", "hi_r6_r11"},
- {{hi, r6, r12}, "hi, r6, r12", "hi_r6_r12"},
- {{hi, r6, r13}, "hi, r6, r13", "hi_r6_r13"},
- {{hi, r6, r14}, "hi, r6, r14", "hi_r6_r14"},
- {{hi, r7, r0}, "hi, r7, r0", "hi_r7_r0"},
- {{hi, r7, r1}, "hi, r7, r1", "hi_r7_r1"},
- {{hi, r7, r2}, "hi, r7, r2", "hi_r7_r2"},
- {{hi, r7, r3}, "hi, r7, r3", "hi_r7_r3"},
- {{hi, r7, r4}, "hi, r7, r4", "hi_r7_r4"},
- {{hi, r7, r5}, "hi, r7, r5", "hi_r7_r5"},
- {{hi, r7, r6}, "hi, r7, r6", "hi_r7_r6"},
- {{hi, r7, r7}, "hi, r7, r7", "hi_r7_r7"},
- {{hi, r7, r8}, "hi, r7, r8", "hi_r7_r8"},
- {{hi, r7, r9}, "hi, r7, r9", "hi_r7_r9"},
- {{hi, r7, r10}, "hi, r7, r10", "hi_r7_r10"},
- {{hi, r7, r11}, "hi, r7, r11", "hi_r7_r11"},
- {{hi, r7, r12}, "hi, r7, r12", "hi_r7_r12"},
- {{hi, r7, r13}, "hi, r7, r13", "hi_r7_r13"},
- {{hi, r7, r14}, "hi, r7, r14", "hi_r7_r14"},
- {{hi, r8, r0}, "hi, r8, r0", "hi_r8_r0"},
- {{hi, r8, r1}, "hi, r8, r1", "hi_r8_r1"},
- {{hi, r8, r2}, "hi, r8, r2", "hi_r8_r2"},
- {{hi, r8, r3}, "hi, r8, r3", "hi_r8_r3"},
- {{hi, r8, r4}, "hi, r8, r4", "hi_r8_r4"},
- {{hi, r8, r5}, "hi, r8, r5", "hi_r8_r5"},
- {{hi, r8, r6}, "hi, r8, r6", "hi_r8_r6"},
- {{hi, r8, r7}, "hi, r8, r7", "hi_r8_r7"},
- {{hi, r8, r8}, "hi, r8, r8", "hi_r8_r8"},
- {{hi, r8, r9}, "hi, r8, r9", "hi_r8_r9"},
- {{hi, r8, r10}, "hi, r8, r10", "hi_r8_r10"},
- {{hi, r8, r11}, "hi, r8, r11", "hi_r8_r11"},
- {{hi, r8, r12}, "hi, r8, r12", "hi_r8_r12"},
- {{hi, r8, r13}, "hi, r8, r13", "hi_r8_r13"},
- {{hi, r8, r14}, "hi, r8, r14", "hi_r8_r14"},
- {{hi, r9, r0}, "hi, r9, r0", "hi_r9_r0"},
- {{hi, r9, r1}, "hi, r9, r1", "hi_r9_r1"},
- {{hi, r9, r2}, "hi, r9, r2", "hi_r9_r2"},
- {{hi, r9, r3}, "hi, r9, r3", "hi_r9_r3"},
- {{hi, r9, r4}, "hi, r9, r4", "hi_r9_r4"},
- {{hi, r9, r5}, "hi, r9, r5", "hi_r9_r5"},
- {{hi, r9, r6}, "hi, r9, r6", "hi_r9_r6"},
- {{hi, r9, r7}, "hi, r9, r7", "hi_r9_r7"},
- {{hi, r9, r8}, "hi, r9, r8", "hi_r9_r8"},
- {{hi, r9, r9}, "hi, r9, r9", "hi_r9_r9"},
- {{hi, r9, r10}, "hi, r9, r10", "hi_r9_r10"},
- {{hi, r9, r11}, "hi, r9, r11", "hi_r9_r11"},
- {{hi, r9, r12}, "hi, r9, r12", "hi_r9_r12"},
- {{hi, r9, r13}, "hi, r9, r13", "hi_r9_r13"},
- {{hi, r9, r14}, "hi, r9, r14", "hi_r9_r14"},
- {{hi, r10, r0}, "hi, r10, r0", "hi_r10_r0"},
- {{hi, r10, r1}, "hi, r10, r1", "hi_r10_r1"},
- {{hi, r10, r2}, "hi, r10, r2", "hi_r10_r2"},
- {{hi, r10, r3}, "hi, r10, r3", "hi_r10_r3"},
- {{hi, r10, r4}, "hi, r10, r4", "hi_r10_r4"},
- {{hi, r10, r5}, "hi, r10, r5", "hi_r10_r5"},
- {{hi, r10, r6}, "hi, r10, r6", "hi_r10_r6"},
- {{hi, r10, r7}, "hi, r10, r7", "hi_r10_r7"},
- {{hi, r10, r8}, "hi, r10, r8", "hi_r10_r8"},
- {{hi, r10, r9}, "hi, r10, r9", "hi_r10_r9"},
- {{hi, r10, r10}, "hi, r10, r10", "hi_r10_r10"},
- {{hi, r10, r11}, "hi, r10, r11", "hi_r10_r11"},
- {{hi, r10, r12}, "hi, r10, r12", "hi_r10_r12"},
- {{hi, r10, r13}, "hi, r10, r13", "hi_r10_r13"},
- {{hi, r10, r14}, "hi, r10, r14", "hi_r10_r14"},
- {{hi, r11, r0}, "hi, r11, r0", "hi_r11_r0"},
- {{hi, r11, r1}, "hi, r11, r1", "hi_r11_r1"},
- {{hi, r11, r2}, "hi, r11, r2", "hi_r11_r2"},
- {{hi, r11, r3}, "hi, r11, r3", "hi_r11_r3"},
- {{hi, r11, r4}, "hi, r11, r4", "hi_r11_r4"},
- {{hi, r11, r5}, "hi, r11, r5", "hi_r11_r5"},
- {{hi, r11, r6}, "hi, r11, r6", "hi_r11_r6"},
- {{hi, r11, r7}, "hi, r11, r7", "hi_r11_r7"},
- {{hi, r11, r8}, "hi, r11, r8", "hi_r11_r8"},
- {{hi, r11, r9}, "hi, r11, r9", "hi_r11_r9"},
- {{hi, r11, r10}, "hi, r11, r10", "hi_r11_r10"},
- {{hi, r11, r11}, "hi, r11, r11", "hi_r11_r11"},
- {{hi, r11, r12}, "hi, r11, r12", "hi_r11_r12"},
- {{hi, r11, r13}, "hi, r11, r13", "hi_r11_r13"},
- {{hi, r11, r14}, "hi, r11, r14", "hi_r11_r14"},
- {{hi, r12, r0}, "hi, r12, r0", "hi_r12_r0"},
- {{hi, r12, r1}, "hi, r12, r1", "hi_r12_r1"},
- {{hi, r12, r2}, "hi, r12, r2", "hi_r12_r2"},
- {{hi, r12, r3}, "hi, r12, r3", "hi_r12_r3"},
- {{hi, r12, r4}, "hi, r12, r4", "hi_r12_r4"},
- {{hi, r12, r5}, "hi, r12, r5", "hi_r12_r5"},
- {{hi, r12, r6}, "hi, r12, r6", "hi_r12_r6"},
- {{hi, r12, r7}, "hi, r12, r7", "hi_r12_r7"},
- {{hi, r12, r8}, "hi, r12, r8", "hi_r12_r8"},
- {{hi, r12, r9}, "hi, r12, r9", "hi_r12_r9"},
- {{hi, r12, r10}, "hi, r12, r10", "hi_r12_r10"},
- {{hi, r12, r11}, "hi, r12, r11", "hi_r12_r11"},
- {{hi, r12, r12}, "hi, r12, r12", "hi_r12_r12"},
- {{hi, r12, r13}, "hi, r12, r13", "hi_r12_r13"},
- {{hi, r12, r14}, "hi, r12, r14", "hi_r12_r14"},
- {{hi, r13, r0}, "hi, r13, r0", "hi_r13_r0"},
- {{hi, r13, r1}, "hi, r13, r1", "hi_r13_r1"},
- {{hi, r13, r2}, "hi, r13, r2", "hi_r13_r2"},
- {{hi, r13, r3}, "hi, r13, r3", "hi_r13_r3"},
- {{hi, r13, r4}, "hi, r13, r4", "hi_r13_r4"},
- {{hi, r13, r5}, "hi, r13, r5", "hi_r13_r5"},
- {{hi, r13, r6}, "hi, r13, r6", "hi_r13_r6"},
- {{hi, r13, r7}, "hi, r13, r7", "hi_r13_r7"},
- {{hi, r13, r8}, "hi, r13, r8", "hi_r13_r8"},
- {{hi, r13, r9}, "hi, r13, r9", "hi_r13_r9"},
- {{hi, r13, r10}, "hi, r13, r10", "hi_r13_r10"},
- {{hi, r13, r11}, "hi, r13, r11", "hi_r13_r11"},
- {{hi, r13, r12}, "hi, r13, r12", "hi_r13_r12"},
- {{hi, r13, r13}, "hi, r13, r13", "hi_r13_r13"},
- {{hi, r13, r14}, "hi, r13, r14", "hi_r13_r14"},
- {{hi, r14, r0}, "hi, r14, r0", "hi_r14_r0"},
- {{hi, r14, r1}, "hi, r14, r1", "hi_r14_r1"},
- {{hi, r14, r2}, "hi, r14, r2", "hi_r14_r2"},
- {{hi, r14, r3}, "hi, r14, r3", "hi_r14_r3"},
- {{hi, r14, r4}, "hi, r14, r4", "hi_r14_r4"},
- {{hi, r14, r5}, "hi, r14, r5", "hi_r14_r5"},
- {{hi, r14, r6}, "hi, r14, r6", "hi_r14_r6"},
- {{hi, r14, r7}, "hi, r14, r7", "hi_r14_r7"},
- {{hi, r14, r8}, "hi, r14, r8", "hi_r14_r8"},
- {{hi, r14, r9}, "hi, r14, r9", "hi_r14_r9"},
- {{hi, r14, r10}, "hi, r14, r10", "hi_r14_r10"},
- {{hi, r14, r11}, "hi, r14, r11", "hi_r14_r11"},
- {{hi, r14, r12}, "hi, r14, r12", "hi_r14_r12"},
- {{hi, r14, r13}, "hi, r14, r13", "hi_r14_r13"},
- {{hi, r14, r14}, "hi, r14, r14", "hi_r14_r14"},
- {{ls, r0, r0}, "ls, r0, r0", "ls_r0_r0"},
- {{ls, r0, r1}, "ls, r0, r1", "ls_r0_r1"},
- {{ls, r0, r2}, "ls, r0, r2", "ls_r0_r2"},
- {{ls, r0, r3}, "ls, r0, r3", "ls_r0_r3"},
- {{ls, r0, r4}, "ls, r0, r4", "ls_r0_r4"},
- {{ls, r0, r5}, "ls, r0, r5", "ls_r0_r5"},
- {{ls, r0, r6}, "ls, r0, r6", "ls_r0_r6"},
- {{ls, r0, r7}, "ls, r0, r7", "ls_r0_r7"},
- {{ls, r0, r8}, "ls, r0, r8", "ls_r0_r8"},
- {{ls, r0, r9}, "ls, r0, r9", "ls_r0_r9"},
- {{ls, r0, r10}, "ls, r0, r10", "ls_r0_r10"},
- {{ls, r0, r11}, "ls, r0, r11", "ls_r0_r11"},
- {{ls, r0, r12}, "ls, r0, r12", "ls_r0_r12"},
- {{ls, r0, r13}, "ls, r0, r13", "ls_r0_r13"},
- {{ls, r0, r14}, "ls, r0, r14", "ls_r0_r14"},
- {{ls, r1, r0}, "ls, r1, r0", "ls_r1_r0"},
- {{ls, r1, r1}, "ls, r1, r1", "ls_r1_r1"},
- {{ls, r1, r2}, "ls, r1, r2", "ls_r1_r2"},
- {{ls, r1, r3}, "ls, r1, r3", "ls_r1_r3"},
- {{ls, r1, r4}, "ls, r1, r4", "ls_r1_r4"},
- {{ls, r1, r5}, "ls, r1, r5", "ls_r1_r5"},
- {{ls, r1, r6}, "ls, r1, r6", "ls_r1_r6"},
- {{ls, r1, r7}, "ls, r1, r7", "ls_r1_r7"},
- {{ls, r1, r8}, "ls, r1, r8", "ls_r1_r8"},
- {{ls, r1, r9}, "ls, r1, r9", "ls_r1_r9"},
- {{ls, r1, r10}, "ls, r1, r10", "ls_r1_r10"},
- {{ls, r1, r11}, "ls, r1, r11", "ls_r1_r11"},
- {{ls, r1, r12}, "ls, r1, r12", "ls_r1_r12"},
- {{ls, r1, r13}, "ls, r1, r13", "ls_r1_r13"},
- {{ls, r1, r14}, "ls, r1, r14", "ls_r1_r14"},
- {{ls, r2, r0}, "ls, r2, r0", "ls_r2_r0"},
- {{ls, r2, r1}, "ls, r2, r1", "ls_r2_r1"},
- {{ls, r2, r2}, "ls, r2, r2", "ls_r2_r2"},
- {{ls, r2, r3}, "ls, r2, r3", "ls_r2_r3"},
- {{ls, r2, r4}, "ls, r2, r4", "ls_r2_r4"},
- {{ls, r2, r5}, "ls, r2, r5", "ls_r2_r5"},
- {{ls, r2, r6}, "ls, r2, r6", "ls_r2_r6"},
- {{ls, r2, r7}, "ls, r2, r7", "ls_r2_r7"},
- {{ls, r2, r8}, "ls, r2, r8", "ls_r2_r8"},
- {{ls, r2, r9}, "ls, r2, r9", "ls_r2_r9"},
- {{ls, r2, r10}, "ls, r2, r10", "ls_r2_r10"},
- {{ls, r2, r11}, "ls, r2, r11", "ls_r2_r11"},
- {{ls, r2, r12}, "ls, r2, r12", "ls_r2_r12"},
- {{ls, r2, r13}, "ls, r2, r13", "ls_r2_r13"},
- {{ls, r2, r14}, "ls, r2, r14", "ls_r2_r14"},
- {{ls, r3, r0}, "ls, r3, r0", "ls_r3_r0"},
- {{ls, r3, r1}, "ls, r3, r1", "ls_r3_r1"},
- {{ls, r3, r2}, "ls, r3, r2", "ls_r3_r2"},
- {{ls, r3, r3}, "ls, r3, r3", "ls_r3_r3"},
- {{ls, r3, r4}, "ls, r3, r4", "ls_r3_r4"},
- {{ls, r3, r5}, "ls, r3, r5", "ls_r3_r5"},
- {{ls, r3, r6}, "ls, r3, r6", "ls_r3_r6"},
- {{ls, r3, r7}, "ls, r3, r7", "ls_r3_r7"},
- {{ls, r3, r8}, "ls, r3, r8", "ls_r3_r8"},
- {{ls, r3, r9}, "ls, r3, r9", "ls_r3_r9"},
- {{ls, r3, r10}, "ls, r3, r10", "ls_r3_r10"},
- {{ls, r3, r11}, "ls, r3, r11", "ls_r3_r11"},
- {{ls, r3, r12}, "ls, r3, r12", "ls_r3_r12"},
- {{ls, r3, r13}, "ls, r3, r13", "ls_r3_r13"},
- {{ls, r3, r14}, "ls, r3, r14", "ls_r3_r14"},
- {{ls, r4, r0}, "ls, r4, r0", "ls_r4_r0"},
- {{ls, r4, r1}, "ls, r4, r1", "ls_r4_r1"},
- {{ls, r4, r2}, "ls, r4, r2", "ls_r4_r2"},
- {{ls, r4, r3}, "ls, r4, r3", "ls_r4_r3"},
- {{ls, r4, r4}, "ls, r4, r4", "ls_r4_r4"},
- {{ls, r4, r5}, "ls, r4, r5", "ls_r4_r5"},
- {{ls, r4, r6}, "ls, r4, r6", "ls_r4_r6"},
- {{ls, r4, r7}, "ls, r4, r7", "ls_r4_r7"},
- {{ls, r4, r8}, "ls, r4, r8", "ls_r4_r8"},
- {{ls, r4, r9}, "ls, r4, r9", "ls_r4_r9"},
- {{ls, r4, r10}, "ls, r4, r10", "ls_r4_r10"},
- {{ls, r4, r11}, "ls, r4, r11", "ls_r4_r11"},
- {{ls, r4, r12}, "ls, r4, r12", "ls_r4_r12"},
- {{ls, r4, r13}, "ls, r4, r13", "ls_r4_r13"},
- {{ls, r4, r14}, "ls, r4, r14", "ls_r4_r14"},
- {{ls, r5, r0}, "ls, r5, r0", "ls_r5_r0"},
- {{ls, r5, r1}, "ls, r5, r1", "ls_r5_r1"},
- {{ls, r5, r2}, "ls, r5, r2", "ls_r5_r2"},
- {{ls, r5, r3}, "ls, r5, r3", "ls_r5_r3"},
- {{ls, r5, r4}, "ls, r5, r4", "ls_r5_r4"},
- {{ls, r5, r5}, "ls, r5, r5", "ls_r5_r5"},
- {{ls, r5, r6}, "ls, r5, r6", "ls_r5_r6"},
- {{ls, r5, r7}, "ls, r5, r7", "ls_r5_r7"},
- {{ls, r5, r8}, "ls, r5, r8", "ls_r5_r8"},
- {{ls, r5, r9}, "ls, r5, r9", "ls_r5_r9"},
- {{ls, r5, r10}, "ls, r5, r10", "ls_r5_r10"},
- {{ls, r5, r11}, "ls, r5, r11", "ls_r5_r11"},
- {{ls, r5, r12}, "ls, r5, r12", "ls_r5_r12"},
- {{ls, r5, r13}, "ls, r5, r13", "ls_r5_r13"},
- {{ls, r5, r14}, "ls, r5, r14", "ls_r5_r14"},
- {{ls, r6, r0}, "ls, r6, r0", "ls_r6_r0"},
- {{ls, r6, r1}, "ls, r6, r1", "ls_r6_r1"},
- {{ls, r6, r2}, "ls, r6, r2", "ls_r6_r2"},
- {{ls, r6, r3}, "ls, r6, r3", "ls_r6_r3"},
- {{ls, r6, r4}, "ls, r6, r4", "ls_r6_r4"},
- {{ls, r6, r5}, "ls, r6, r5", "ls_r6_r5"},
- {{ls, r6, r6}, "ls, r6, r6", "ls_r6_r6"},
- {{ls, r6, r7}, "ls, r6, r7", "ls_r6_r7"},
- {{ls, r6, r8}, "ls, r6, r8", "ls_r6_r8"},
- {{ls, r6, r9}, "ls, r6, r9", "ls_r6_r9"},
- {{ls, r6, r10}, "ls, r6, r10", "ls_r6_r10"},
- {{ls, r6, r11}, "ls, r6, r11", "ls_r6_r11"},
- {{ls, r6, r12}, "ls, r6, r12", "ls_r6_r12"},
- {{ls, r6, r13}, "ls, r6, r13", "ls_r6_r13"},
- {{ls, r6, r14}, "ls, r6, r14", "ls_r6_r14"},
- {{ls, r7, r0}, "ls, r7, r0", "ls_r7_r0"},
- {{ls, r7, r1}, "ls, r7, r1", "ls_r7_r1"},
- {{ls, r7, r2}, "ls, r7, r2", "ls_r7_r2"},
- {{ls, r7, r3}, "ls, r7, r3", "ls_r7_r3"},
- {{ls, r7, r4}, "ls, r7, r4", "ls_r7_r4"},
- {{ls, r7, r5}, "ls, r7, r5", "ls_r7_r5"},
- {{ls, r7, r6}, "ls, r7, r6", "ls_r7_r6"},
- {{ls, r7, r7}, "ls, r7, r7", "ls_r7_r7"},
- {{ls, r7, r8}, "ls, r7, r8", "ls_r7_r8"},
- {{ls, r7, r9}, "ls, r7, r9", "ls_r7_r9"},
- {{ls, r7, r10}, "ls, r7, r10", "ls_r7_r10"},
- {{ls, r7, r11}, "ls, r7, r11", "ls_r7_r11"},
- {{ls, r7, r12}, "ls, r7, r12", "ls_r7_r12"},
- {{ls, r7, r13}, "ls, r7, r13", "ls_r7_r13"},
- {{ls, r7, r14}, "ls, r7, r14", "ls_r7_r14"},
- {{ls, r8, r0}, "ls, r8, r0", "ls_r8_r0"},
- {{ls, r8, r1}, "ls, r8, r1", "ls_r8_r1"},
- {{ls, r8, r2}, "ls, r8, r2", "ls_r8_r2"},
- {{ls, r8, r3}, "ls, r8, r3", "ls_r8_r3"},
- {{ls, r8, r4}, "ls, r8, r4", "ls_r8_r4"},
- {{ls, r8, r5}, "ls, r8, r5", "ls_r8_r5"},
- {{ls, r8, r6}, "ls, r8, r6", "ls_r8_r6"},
- {{ls, r8, r7}, "ls, r8, r7", "ls_r8_r7"},
- {{ls, r8, r8}, "ls, r8, r8", "ls_r8_r8"},
- {{ls, r8, r9}, "ls, r8, r9", "ls_r8_r9"},
- {{ls, r8, r10}, "ls, r8, r10", "ls_r8_r10"},
- {{ls, r8, r11}, "ls, r8, r11", "ls_r8_r11"},
- {{ls, r8, r12}, "ls, r8, r12", "ls_r8_r12"},
- {{ls, r8, r13}, "ls, r8, r13", "ls_r8_r13"},
- {{ls, r8, r14}, "ls, r8, r14", "ls_r8_r14"},
- {{ls, r9, r0}, "ls, r9, r0", "ls_r9_r0"},
- {{ls, r9, r1}, "ls, r9, r1", "ls_r9_r1"},
- {{ls, r9, r2}, "ls, r9, r2", "ls_r9_r2"},
- {{ls, r9, r3}, "ls, r9, r3", "ls_r9_r3"},
- {{ls, r9, r4}, "ls, r9, r4", "ls_r9_r4"},
- {{ls, r9, r5}, "ls, r9, r5", "ls_r9_r5"},
- {{ls, r9, r6}, "ls, r9, r6", "ls_r9_r6"},
- {{ls, r9, r7}, "ls, r9, r7", "ls_r9_r7"},
- {{ls, r9, r8}, "ls, r9, r8", "ls_r9_r8"},
- {{ls, r9, r9}, "ls, r9, r9", "ls_r9_r9"},
- {{ls, r9, r10}, "ls, r9, r10", "ls_r9_r10"},
- {{ls, r9, r11}, "ls, r9, r11", "ls_r9_r11"},
- {{ls, r9, r12}, "ls, r9, r12", "ls_r9_r12"},
- {{ls, r9, r13}, "ls, r9, r13", "ls_r9_r13"},
- {{ls, r9, r14}, "ls, r9, r14", "ls_r9_r14"},
- {{ls, r10, r0}, "ls, r10, r0", "ls_r10_r0"},
- {{ls, r10, r1}, "ls, r10, r1", "ls_r10_r1"},
- {{ls, r10, r2}, "ls, r10, r2", "ls_r10_r2"},
- {{ls, r10, r3}, "ls, r10, r3", "ls_r10_r3"},
- {{ls, r10, r4}, "ls, r10, r4", "ls_r10_r4"},
- {{ls, r10, r5}, "ls, r10, r5", "ls_r10_r5"},
- {{ls, r10, r6}, "ls, r10, r6", "ls_r10_r6"},
- {{ls, r10, r7}, "ls, r10, r7", "ls_r10_r7"},
- {{ls, r10, r8}, "ls, r10, r8", "ls_r10_r8"},
- {{ls, r10, r9}, "ls, r10, r9", "ls_r10_r9"},
- {{ls, r10, r10}, "ls, r10, r10", "ls_r10_r10"},
- {{ls, r10, r11}, "ls, r10, r11", "ls_r10_r11"},
- {{ls, r10, r12}, "ls, r10, r12", "ls_r10_r12"},
- {{ls, r10, r13}, "ls, r10, r13", "ls_r10_r13"},
- {{ls, r10, r14}, "ls, r10, r14", "ls_r10_r14"},
- {{ls, r11, r0}, "ls, r11, r0", "ls_r11_r0"},
- {{ls, r11, r1}, "ls, r11, r1", "ls_r11_r1"},
- {{ls, r11, r2}, "ls, r11, r2", "ls_r11_r2"},
- {{ls, r11, r3}, "ls, r11, r3", "ls_r11_r3"},
- {{ls, r11, r4}, "ls, r11, r4", "ls_r11_r4"},
- {{ls, r11, r5}, "ls, r11, r5", "ls_r11_r5"},
- {{ls, r11, r6}, "ls, r11, r6", "ls_r11_r6"},
- {{ls, r11, r7}, "ls, r11, r7", "ls_r11_r7"},
- {{ls, r11, r8}, "ls, r11, r8", "ls_r11_r8"},
- {{ls, r11, r9}, "ls, r11, r9", "ls_r11_r9"},
- {{ls, r11, r10}, "ls, r11, r10", "ls_r11_r10"},
- {{ls, r11, r11}, "ls, r11, r11", "ls_r11_r11"},
- {{ls, r11, r12}, "ls, r11, r12", "ls_r11_r12"},
- {{ls, r11, r13}, "ls, r11, r13", "ls_r11_r13"},
- {{ls, r11, r14}, "ls, r11, r14", "ls_r11_r14"},
- {{ls, r12, r0}, "ls, r12, r0", "ls_r12_r0"},
- {{ls, r12, r1}, "ls, r12, r1", "ls_r12_r1"},
- {{ls, r12, r2}, "ls, r12, r2", "ls_r12_r2"},
- {{ls, r12, r3}, "ls, r12, r3", "ls_r12_r3"},
- {{ls, r12, r4}, "ls, r12, r4", "ls_r12_r4"},
- {{ls, r12, r5}, "ls, r12, r5", "ls_r12_r5"},
- {{ls, r12, r6}, "ls, r12, r6", "ls_r12_r6"},
- {{ls, r12, r7}, "ls, r12, r7", "ls_r12_r7"},
- {{ls, r12, r8}, "ls, r12, r8", "ls_r12_r8"},
- {{ls, r12, r9}, "ls, r12, r9", "ls_r12_r9"},
- {{ls, r12, r10}, "ls, r12, r10", "ls_r12_r10"},
- {{ls, r12, r11}, "ls, r12, r11", "ls_r12_r11"},
- {{ls, r12, r12}, "ls, r12, r12", "ls_r12_r12"},
- {{ls, r12, r13}, "ls, r12, r13", "ls_r12_r13"},
- {{ls, r12, r14}, "ls, r12, r14", "ls_r12_r14"},
- {{ls, r13, r0}, "ls, r13, r0", "ls_r13_r0"},
- {{ls, r13, r1}, "ls, r13, r1", "ls_r13_r1"},
- {{ls, r13, r2}, "ls, r13, r2", "ls_r13_r2"},
- {{ls, r13, r3}, "ls, r13, r3", "ls_r13_r3"},
- {{ls, r13, r4}, "ls, r13, r4", "ls_r13_r4"},
- {{ls, r13, r5}, "ls, r13, r5", "ls_r13_r5"},
- {{ls, r13, r6}, "ls, r13, r6", "ls_r13_r6"},
- {{ls, r13, r7}, "ls, r13, r7", "ls_r13_r7"},
- {{ls, r13, r8}, "ls, r13, r8", "ls_r13_r8"},
- {{ls, r13, r9}, "ls, r13, r9", "ls_r13_r9"},
- {{ls, r13, r10}, "ls, r13, r10", "ls_r13_r10"},
- {{ls, r13, r11}, "ls, r13, r11", "ls_r13_r11"},
- {{ls, r13, r12}, "ls, r13, r12", "ls_r13_r12"},
- {{ls, r13, r13}, "ls, r13, r13", "ls_r13_r13"},
- {{ls, r13, r14}, "ls, r13, r14", "ls_r13_r14"},
- {{ls, r14, r0}, "ls, r14, r0", "ls_r14_r0"},
- {{ls, r14, r1}, "ls, r14, r1", "ls_r14_r1"},
- {{ls, r14, r2}, "ls, r14, r2", "ls_r14_r2"},
- {{ls, r14, r3}, "ls, r14, r3", "ls_r14_r3"},
- {{ls, r14, r4}, "ls, r14, r4", "ls_r14_r4"},
- {{ls, r14, r5}, "ls, r14, r5", "ls_r14_r5"},
- {{ls, r14, r6}, "ls, r14, r6", "ls_r14_r6"},
- {{ls, r14, r7}, "ls, r14, r7", "ls_r14_r7"},
- {{ls, r14, r8}, "ls, r14, r8", "ls_r14_r8"},
- {{ls, r14, r9}, "ls, r14, r9", "ls_r14_r9"},
- {{ls, r14, r10}, "ls, r14, r10", "ls_r14_r10"},
- {{ls, r14, r11}, "ls, r14, r11", "ls_r14_r11"},
- {{ls, r14, r12}, "ls, r14, r12", "ls_r14_r12"},
- {{ls, r14, r13}, "ls, r14, r13", "ls_r14_r13"},
- {{ls, r14, r14}, "ls, r14, r14", "ls_r14_r14"},
- {{ge, r0, r0}, "ge, r0, r0", "ge_r0_r0"},
- {{ge, r0, r1}, "ge, r0, r1", "ge_r0_r1"},
- {{ge, r0, r2}, "ge, r0, r2", "ge_r0_r2"},
- {{ge, r0, r3}, "ge, r0, r3", "ge_r0_r3"},
- {{ge, r0, r4}, "ge, r0, r4", "ge_r0_r4"},
- {{ge, r0, r5}, "ge, r0, r5", "ge_r0_r5"},
- {{ge, r0, r6}, "ge, r0, r6", "ge_r0_r6"},
- {{ge, r0, r7}, "ge, r0, r7", "ge_r0_r7"},
- {{ge, r0, r8}, "ge, r0, r8", "ge_r0_r8"},
- {{ge, r0, r9}, "ge, r0, r9", "ge_r0_r9"},
- {{ge, r0, r10}, "ge, r0, r10", "ge_r0_r10"},
- {{ge, r0, r11}, "ge, r0, r11", "ge_r0_r11"},
- {{ge, r0, r12}, "ge, r0, r12", "ge_r0_r12"},
- {{ge, r0, r13}, "ge, r0, r13", "ge_r0_r13"},
- {{ge, r0, r14}, "ge, r0, r14", "ge_r0_r14"},
- {{ge, r1, r0}, "ge, r1, r0", "ge_r1_r0"},
- {{ge, r1, r1}, "ge, r1, r1", "ge_r1_r1"},
- {{ge, r1, r2}, "ge, r1, r2", "ge_r1_r2"},
- {{ge, r1, r3}, "ge, r1, r3", "ge_r1_r3"},
- {{ge, r1, r4}, "ge, r1, r4", "ge_r1_r4"},
- {{ge, r1, r5}, "ge, r1, r5", "ge_r1_r5"},
- {{ge, r1, r6}, "ge, r1, r6", "ge_r1_r6"},
- {{ge, r1, r7}, "ge, r1, r7", "ge_r1_r7"},
- {{ge, r1, r8}, "ge, r1, r8", "ge_r1_r8"},
- {{ge, r1, r9}, "ge, r1, r9", "ge_r1_r9"},
- {{ge, r1, r10}, "ge, r1, r10", "ge_r1_r10"},
- {{ge, r1, r11}, "ge, r1, r11", "ge_r1_r11"},
- {{ge, r1, r12}, "ge, r1, r12", "ge_r1_r12"},
- {{ge, r1, r13}, "ge, r1, r13", "ge_r1_r13"},
- {{ge, r1, r14}, "ge, r1, r14", "ge_r1_r14"},
- {{ge, r2, r0}, "ge, r2, r0", "ge_r2_r0"},
- {{ge, r2, r1}, "ge, r2, r1", "ge_r2_r1"},
- {{ge, r2, r2}, "ge, r2, r2", "ge_r2_r2"},
- {{ge, r2, r3}, "ge, r2, r3", "ge_r2_r3"},
- {{ge, r2, r4}, "ge, r2, r4", "ge_r2_r4"},
- {{ge, r2, r5}, "ge, r2, r5", "ge_r2_r5"},
- {{ge, r2, r6}, "ge, r2, r6", "ge_r2_r6"},
- {{ge, r2, r7}, "ge, r2, r7", "ge_r2_r7"},
- {{ge, r2, r8}, "ge, r2, r8", "ge_r2_r8"},
- {{ge, r2, r9}, "ge, r2, r9", "ge_r2_r9"},
- {{ge, r2, r10}, "ge, r2, r10", "ge_r2_r10"},
- {{ge, r2, r11}, "ge, r2, r11", "ge_r2_r11"},
- {{ge, r2, r12}, "ge, r2, r12", "ge_r2_r12"},
- {{ge, r2, r13}, "ge, r2, r13", "ge_r2_r13"},
- {{ge, r2, r14}, "ge, r2, r14", "ge_r2_r14"},
- {{ge, r3, r0}, "ge, r3, r0", "ge_r3_r0"},
- {{ge, r3, r1}, "ge, r3, r1", "ge_r3_r1"},
- {{ge, r3, r2}, "ge, r3, r2", "ge_r3_r2"},
- {{ge, r3, r3}, "ge, r3, r3", "ge_r3_r3"},
- {{ge, r3, r4}, "ge, r3, r4", "ge_r3_r4"},
- {{ge, r3, r5}, "ge, r3, r5", "ge_r3_r5"},
- {{ge, r3, r6}, "ge, r3, r6", "ge_r3_r6"},
- {{ge, r3, r7}, "ge, r3, r7", "ge_r3_r7"},
- {{ge, r3, r8}, "ge, r3, r8", "ge_r3_r8"},
- {{ge, r3, r9}, "ge, r3, r9", "ge_r3_r9"},
- {{ge, r3, r10}, "ge, r3, r10", "ge_r3_r10"},
- {{ge, r3, r11}, "ge, r3, r11", "ge_r3_r11"},
- {{ge, r3, r12}, "ge, r3, r12", "ge_r3_r12"},
- {{ge, r3, r13}, "ge, r3, r13", "ge_r3_r13"},
- {{ge, r3, r14}, "ge, r3, r14", "ge_r3_r14"},
- {{ge, r4, r0}, "ge, r4, r0", "ge_r4_r0"},
- {{ge, r4, r1}, "ge, r4, r1", "ge_r4_r1"},
- {{ge, r4, r2}, "ge, r4, r2", "ge_r4_r2"},
- {{ge, r4, r3}, "ge, r4, r3", "ge_r4_r3"},
- {{ge, r4, r4}, "ge, r4, r4", "ge_r4_r4"},
- {{ge, r4, r5}, "ge, r4, r5", "ge_r4_r5"},
- {{ge, r4, r6}, "ge, r4, r6", "ge_r4_r6"},
- {{ge, r4, r7}, "ge, r4, r7", "ge_r4_r7"},
- {{ge, r4, r8}, "ge, r4, r8", "ge_r4_r8"},
- {{ge, r4, r9}, "ge, r4, r9", "ge_r4_r9"},
- {{ge, r4, r10}, "ge, r4, r10", "ge_r4_r10"},
- {{ge, r4, r11}, "ge, r4, r11", "ge_r4_r11"},
- {{ge, r4, r12}, "ge, r4, r12", "ge_r4_r12"},
- {{ge, r4, r13}, "ge, r4, r13", "ge_r4_r13"},
- {{ge, r4, r14}, "ge, r4, r14", "ge_r4_r14"},
- {{ge, r5, r0}, "ge, r5, r0", "ge_r5_r0"},
- {{ge, r5, r1}, "ge, r5, r1", "ge_r5_r1"},
- {{ge, r5, r2}, "ge, r5, r2", "ge_r5_r2"},
- {{ge, r5, r3}, "ge, r5, r3", "ge_r5_r3"},
- {{ge, r5, r4}, "ge, r5, r4", "ge_r5_r4"},
- {{ge, r5, r5}, "ge, r5, r5", "ge_r5_r5"},
- {{ge, r5, r6}, "ge, r5, r6", "ge_r5_r6"},
- {{ge, r5, r7}, "ge, r5, r7", "ge_r5_r7"},
- {{ge, r5, r8}, "ge, r5, r8", "ge_r5_r8"},
- {{ge, r5, r9}, "ge, r5, r9", "ge_r5_r9"},
- {{ge, r5, r10}, "ge, r5, r10", "ge_r5_r10"},
- {{ge, r5, r11}, "ge, r5, r11", "ge_r5_r11"},
- {{ge, r5, r12}, "ge, r5, r12", "ge_r5_r12"},
- {{ge, r5, r13}, "ge, r5, r13", "ge_r5_r13"},
- {{ge, r5, r14}, "ge, r5, r14", "ge_r5_r14"},
- {{ge, r6, r0}, "ge, r6, r0", "ge_r6_r0"},
- {{ge, r6, r1}, "ge, r6, r1", "ge_r6_r1"},
- {{ge, r6, r2}, "ge, r6, r2", "ge_r6_r2"},
- {{ge, r6, r3}, "ge, r6, r3", "ge_r6_r3"},
- {{ge, r6, r4}, "ge, r6, r4", "ge_r6_r4"},
- {{ge, r6, r5}, "ge, r6, r5", "ge_r6_r5"},
- {{ge, r6, r6}, "ge, r6, r6", "ge_r6_r6"},
- {{ge, r6, r7}, "ge, r6, r7", "ge_r6_r7"},
- {{ge, r6, r8}, "ge, r6, r8", "ge_r6_r8"},
- {{ge, r6, r9}, "ge, r6, r9", "ge_r6_r9"},
- {{ge, r6, r10}, "ge, r6, r10", "ge_r6_r10"},
- {{ge, r6, r11}, "ge, r6, r11", "ge_r6_r11"},
- {{ge, r6, r12}, "ge, r6, r12", "ge_r6_r12"},
- {{ge, r6, r13}, "ge, r6, r13", "ge_r6_r13"},
- {{ge, r6, r14}, "ge, r6, r14", "ge_r6_r14"},
- {{ge, r7, r0}, "ge, r7, r0", "ge_r7_r0"},
- {{ge, r7, r1}, "ge, r7, r1", "ge_r7_r1"},
- {{ge, r7, r2}, "ge, r7, r2", "ge_r7_r2"},
- {{ge, r7, r3}, "ge, r7, r3", "ge_r7_r3"},
- {{ge, r7, r4}, "ge, r7, r4", "ge_r7_r4"},
- {{ge, r7, r5}, "ge, r7, r5", "ge_r7_r5"},
- {{ge, r7, r6}, "ge, r7, r6", "ge_r7_r6"},
- {{ge, r7, r7}, "ge, r7, r7", "ge_r7_r7"},
- {{ge, r7, r8}, "ge, r7, r8", "ge_r7_r8"},
- {{ge, r7, r9}, "ge, r7, r9", "ge_r7_r9"},
- {{ge, r7, r10}, "ge, r7, r10", "ge_r7_r10"},
- {{ge, r7, r11}, "ge, r7, r11", "ge_r7_r11"},
- {{ge, r7, r12}, "ge, r7, r12", "ge_r7_r12"},
- {{ge, r7, r13}, "ge, r7, r13", "ge_r7_r13"},
- {{ge, r7, r14}, "ge, r7, r14", "ge_r7_r14"},
- {{ge, r8, r0}, "ge, r8, r0", "ge_r8_r0"},
- {{ge, r8, r1}, "ge, r8, r1", "ge_r8_r1"},
- {{ge, r8, r2}, "ge, r8, r2", "ge_r8_r2"},
- {{ge, r8, r3}, "ge, r8, r3", "ge_r8_r3"},
- {{ge, r8, r4}, "ge, r8, r4", "ge_r8_r4"},
- {{ge, r8, r5}, "ge, r8, r5", "ge_r8_r5"},
- {{ge, r8, r6}, "ge, r8, r6", "ge_r8_r6"},
- {{ge, r8, r7}, "ge, r8, r7", "ge_r8_r7"},
- {{ge, r8, r8}, "ge, r8, r8", "ge_r8_r8"},
- {{ge, r8, r9}, "ge, r8, r9", "ge_r8_r9"},
- {{ge, r8, r10}, "ge, r8, r10", "ge_r8_r10"},
- {{ge, r8, r11}, "ge, r8, r11", "ge_r8_r11"},
- {{ge, r8, r12}, "ge, r8, r12", "ge_r8_r12"},
- {{ge, r8, r13}, "ge, r8, r13", "ge_r8_r13"},
- {{ge, r8, r14}, "ge, r8, r14", "ge_r8_r14"},
- {{ge, r9, r0}, "ge, r9, r0", "ge_r9_r0"},
- {{ge, r9, r1}, "ge, r9, r1", "ge_r9_r1"},
- {{ge, r9, r2}, "ge, r9, r2", "ge_r9_r2"},
- {{ge, r9, r3}, "ge, r9, r3", "ge_r9_r3"},
- {{ge, r9, r4}, "ge, r9, r4", "ge_r9_r4"},
- {{ge, r9, r5}, "ge, r9, r5", "ge_r9_r5"},
- {{ge, r9, r6}, "ge, r9, r6", "ge_r9_r6"},
- {{ge, r9, r7}, "ge, r9, r7", "ge_r9_r7"},
- {{ge, r9, r8}, "ge, r9, r8", "ge_r9_r8"},
- {{ge, r9, r9}, "ge, r9, r9", "ge_r9_r9"},
- {{ge, r9, r10}, "ge, r9, r10", "ge_r9_r10"},
- {{ge, r9, r11}, "ge, r9, r11", "ge_r9_r11"},
- {{ge, r9, r12}, "ge, r9, r12", "ge_r9_r12"},
- {{ge, r9, r13}, "ge, r9, r13", "ge_r9_r13"},
- {{ge, r9, r14}, "ge, r9, r14", "ge_r9_r14"},
- {{ge, r10, r0}, "ge, r10, r0", "ge_r10_r0"},
- {{ge, r10, r1}, "ge, r10, r1", "ge_r10_r1"},
- {{ge, r10, r2}, "ge, r10, r2", "ge_r10_r2"},
- {{ge, r10, r3}, "ge, r10, r3", "ge_r10_r3"},
- {{ge, r10, r4}, "ge, r10, r4", "ge_r10_r4"},
- {{ge, r10, r5}, "ge, r10, r5", "ge_r10_r5"},
- {{ge, r10, r6}, "ge, r10, r6", "ge_r10_r6"},
- {{ge, r10, r7}, "ge, r10, r7", "ge_r10_r7"},
- {{ge, r10, r8}, "ge, r10, r8", "ge_r10_r8"},
- {{ge, r10, r9}, "ge, r10, r9", "ge_r10_r9"},
- {{ge, r10, r10}, "ge, r10, r10", "ge_r10_r10"},
- {{ge, r10, r11}, "ge, r10, r11", "ge_r10_r11"},
- {{ge, r10, r12}, "ge, r10, r12", "ge_r10_r12"},
- {{ge, r10, r13}, "ge, r10, r13", "ge_r10_r13"},
- {{ge, r10, r14}, "ge, r10, r14", "ge_r10_r14"},
- {{ge, r11, r0}, "ge, r11, r0", "ge_r11_r0"},
- {{ge, r11, r1}, "ge, r11, r1", "ge_r11_r1"},
- {{ge, r11, r2}, "ge, r11, r2", "ge_r11_r2"},
- {{ge, r11, r3}, "ge, r11, r3", "ge_r11_r3"},
- {{ge, r11, r4}, "ge, r11, r4", "ge_r11_r4"},
- {{ge, r11, r5}, "ge, r11, r5", "ge_r11_r5"},
- {{ge, r11, r6}, "ge, r11, r6", "ge_r11_r6"},
- {{ge, r11, r7}, "ge, r11, r7", "ge_r11_r7"},
- {{ge, r11, r8}, "ge, r11, r8", "ge_r11_r8"},
- {{ge, r11, r9}, "ge, r11, r9", "ge_r11_r9"},
- {{ge, r11, r10}, "ge, r11, r10", "ge_r11_r10"},
- {{ge, r11, r11}, "ge, r11, r11", "ge_r11_r11"},
- {{ge, r11, r12}, "ge, r11, r12", "ge_r11_r12"},
- {{ge, r11, r13}, "ge, r11, r13", "ge_r11_r13"},
- {{ge, r11, r14}, "ge, r11, r14", "ge_r11_r14"},
- {{ge, r12, r0}, "ge, r12, r0", "ge_r12_r0"},
- {{ge, r12, r1}, "ge, r12, r1", "ge_r12_r1"},
- {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"},
- {{ge, r12, r3}, "ge, r12, r3", "ge_r12_r3"},
- {{ge, r12, r4}, "ge, r12, r4", "ge_r12_r4"},
- {{ge, r12, r5}, "ge, r12, r5", "ge_r12_r5"},
- {{ge, r12, r6}, "ge, r12, r6", "ge_r12_r6"},
- {{ge, r12, r7}, "ge, r12, r7", "ge_r12_r7"},
- {{ge, r12, r8}, "ge, r12, r8", "ge_r12_r8"},
- {{ge, r12, r9}, "ge, r12, r9", "ge_r12_r9"},
- {{ge, r12, r10}, "ge, r12, r10", "ge_r12_r10"},
- {{ge, r12, r11}, "ge, r12, r11", "ge_r12_r11"},
- {{ge, r12, r12}, "ge, r12, r12", "ge_r12_r12"},
- {{ge, r12, r13}, "ge, r12, r13", "ge_r12_r13"},
- {{ge, r12, r14}, "ge, r12, r14", "ge_r12_r14"},
- {{ge, r13, r0}, "ge, r13, r0", "ge_r13_r0"},
- {{ge, r13, r1}, "ge, r13, r1", "ge_r13_r1"},
- {{ge, r13, r2}, "ge, r13, r2", "ge_r13_r2"},
- {{ge, r13, r3}, "ge, r13, r3", "ge_r13_r3"},
- {{ge, r13, r4}, "ge, r13, r4", "ge_r13_r4"},
- {{ge, r13, r5}, "ge, r13, r5", "ge_r13_r5"},
- {{ge, r13, r6}, "ge, r13, r6", "ge_r13_r6"},
- {{ge, r13, r7}, "ge, r13, r7", "ge_r13_r7"},
- {{ge, r13, r8}, "ge, r13, r8", "ge_r13_r8"},
- {{ge, r13, r9}, "ge, r13, r9", "ge_r13_r9"},
- {{ge, r13, r10}, "ge, r13, r10", "ge_r13_r10"},
- {{ge, r13, r11}, "ge, r13, r11", "ge_r13_r11"},
- {{ge, r13, r12}, "ge, r13, r12", "ge_r13_r12"},
- {{ge, r13, r13}, "ge, r13, r13", "ge_r13_r13"},
- {{ge, r13, r14}, "ge, r13, r14", "ge_r13_r14"},
- {{ge, r14, r0}, "ge, r14, r0", "ge_r14_r0"},
- {{ge, r14, r1}, "ge, r14, r1", "ge_r14_r1"},
- {{ge, r14, r2}, "ge, r14, r2", "ge_r14_r2"},
- {{ge, r14, r3}, "ge, r14, r3", "ge_r14_r3"},
- {{ge, r14, r4}, "ge, r14, r4", "ge_r14_r4"},
- {{ge, r14, r5}, "ge, r14, r5", "ge_r14_r5"},
- {{ge, r14, r6}, "ge, r14, r6", "ge_r14_r6"},
- {{ge, r14, r7}, "ge, r14, r7", "ge_r14_r7"},
- {{ge, r14, r8}, "ge, r14, r8", "ge_r14_r8"},
- {{ge, r14, r9}, "ge, r14, r9", "ge_r14_r9"},
- {{ge, r14, r10}, "ge, r14, r10", "ge_r14_r10"},
- {{ge, r14, r11}, "ge, r14, r11", "ge_r14_r11"},
- {{ge, r14, r12}, "ge, r14, r12", "ge_r14_r12"},
- {{ge, r14, r13}, "ge, r14, r13", "ge_r14_r13"},
- {{ge, r14, r14}, "ge, r14, r14", "ge_r14_r14"},
- {{lt, r0, r0}, "lt, r0, r0", "lt_r0_r0"},
- {{lt, r0, r1}, "lt, r0, r1", "lt_r0_r1"},
- {{lt, r0, r2}, "lt, r0, r2", "lt_r0_r2"},
- {{lt, r0, r3}, "lt, r0, r3", "lt_r0_r3"},
- {{lt, r0, r4}, "lt, r0, r4", "lt_r0_r4"},
- {{lt, r0, r5}, "lt, r0, r5", "lt_r0_r5"},
- {{lt, r0, r6}, "lt, r0, r6", "lt_r0_r6"},
- {{lt, r0, r7}, "lt, r0, r7", "lt_r0_r7"},
- {{lt, r0, r8}, "lt, r0, r8", "lt_r0_r8"},
- {{lt, r0, r9}, "lt, r0, r9", "lt_r0_r9"},
- {{lt, r0, r10}, "lt, r0, r10", "lt_r0_r10"},
- {{lt, r0, r11}, "lt, r0, r11", "lt_r0_r11"},
- {{lt, r0, r12}, "lt, r0, r12", "lt_r0_r12"},
- {{lt, r0, r13}, "lt, r0, r13", "lt_r0_r13"},
- {{lt, r0, r14}, "lt, r0, r14", "lt_r0_r14"},
- {{lt, r1, r0}, "lt, r1, r0", "lt_r1_r0"},
- {{lt, r1, r1}, "lt, r1, r1", "lt_r1_r1"},
- {{lt, r1, r2}, "lt, r1, r2", "lt_r1_r2"},
- {{lt, r1, r3}, "lt, r1, r3", "lt_r1_r3"},
- {{lt, r1, r4}, "lt, r1, r4", "lt_r1_r4"},
- {{lt, r1, r5}, "lt, r1, r5", "lt_r1_r5"},
- {{lt, r1, r6}, "lt, r1, r6", "lt_r1_r6"},
- {{lt, r1, r7}, "lt, r1, r7", "lt_r1_r7"},
- {{lt, r1, r8}, "lt, r1, r8", "lt_r1_r8"},
- {{lt, r1, r9}, "lt, r1, r9", "lt_r1_r9"},
- {{lt, r1, r10}, "lt, r1, r10", "lt_r1_r10"},
- {{lt, r1, r11}, "lt, r1, r11", "lt_r1_r11"},
- {{lt, r1, r12}, "lt, r1, r12", "lt_r1_r12"},
- {{lt, r1, r13}, "lt, r1, r13", "lt_r1_r13"},
- {{lt, r1, r14}, "lt, r1, r14", "lt_r1_r14"},
- {{lt, r2, r0}, "lt, r2, r0", "lt_r2_r0"},
- {{lt, r2, r1}, "lt, r2, r1", "lt_r2_r1"},
- {{lt, r2, r2}, "lt, r2, r2", "lt_r2_r2"},
- {{lt, r2, r3}, "lt, r2, r3", "lt_r2_r3"},
- {{lt, r2, r4}, "lt, r2, r4", "lt_r2_r4"},
- {{lt, r2, r5}, "lt, r2, r5", "lt_r2_r5"},
- {{lt, r2, r6}, "lt, r2, r6", "lt_r2_r6"},
- {{lt, r2, r7}, "lt, r2, r7", "lt_r2_r7"},
- {{lt, r2, r8}, "lt, r2, r8", "lt_r2_r8"},
- {{lt, r2, r9}, "lt, r2, r9", "lt_r2_r9"},
- {{lt, r2, r10}, "lt, r2, r10", "lt_r2_r10"},
- {{lt, r2, r11}, "lt, r2, r11", "lt_r2_r11"},
- {{lt, r2, r12}, "lt, r2, r12", "lt_r2_r12"},
- {{lt, r2, r13}, "lt, r2, r13", "lt_r2_r13"},
- {{lt, r2, r14}, "lt, r2, r14", "lt_r2_r14"},
- {{lt, r3, r0}, "lt, r3, r0", "lt_r3_r0"},
- {{lt, r3, r1}, "lt, r3, r1", "lt_r3_r1"},
- {{lt, r3, r2}, "lt, r3, r2", "lt_r3_r2"},
- {{lt, r3, r3}, "lt, r3, r3", "lt_r3_r3"},
- {{lt, r3, r4}, "lt, r3, r4", "lt_r3_r4"},
- {{lt, r3, r5}, "lt, r3, r5", "lt_r3_r5"},
- {{lt, r3, r6}, "lt, r3, r6", "lt_r3_r6"},
- {{lt, r3, r7}, "lt, r3, r7", "lt_r3_r7"},
- {{lt, r3, r8}, "lt, r3, r8", "lt_r3_r8"},
- {{lt, r3, r9}, "lt, r3, r9", "lt_r3_r9"},
- {{lt, r3, r10}, "lt, r3, r10", "lt_r3_r10"},
- {{lt, r3, r11}, "lt, r3, r11", "lt_r3_r11"},
- {{lt, r3, r12}, "lt, r3, r12", "lt_r3_r12"},
- {{lt, r3, r13}, "lt, r3, r13", "lt_r3_r13"},
- {{lt, r3, r14}, "lt, r3, r14", "lt_r3_r14"},
- {{lt, r4, r0}, "lt, r4, r0", "lt_r4_r0"},
- {{lt, r4, r1}, "lt, r4, r1", "lt_r4_r1"},
- {{lt, r4, r2}, "lt, r4, r2", "lt_r4_r2"},
- {{lt, r4, r3}, "lt, r4, r3", "lt_r4_r3"},
- {{lt, r4, r4}, "lt, r4, r4", "lt_r4_r4"},
- {{lt, r4, r5}, "lt, r4, r5", "lt_r4_r5"},
- {{lt, r4, r6}, "lt, r4, r6", "lt_r4_r6"},
- {{lt, r4, r7}, "lt, r4, r7", "lt_r4_r7"},
- {{lt, r4, r8}, "lt, r4, r8", "lt_r4_r8"},
- {{lt, r4, r9}, "lt, r4, r9", "lt_r4_r9"},
- {{lt, r4, r10}, "lt, r4, r10", "lt_r4_r10"},
- {{lt, r4, r11}, "lt, r4, r11", "lt_r4_r11"},
- {{lt, r4, r12}, "lt, r4, r12", "lt_r4_r12"},
- {{lt, r4, r13}, "lt, r4, r13", "lt_r4_r13"},
- {{lt, r4, r14}, "lt, r4, r14", "lt_r4_r14"},
- {{lt, r5, r0}, "lt, r5, r0", "lt_r5_r0"},
- {{lt, r5, r1}, "lt, r5, r1", "lt_r5_r1"},
- {{lt, r5, r2}, "lt, r5, r2", "lt_r5_r2"},
- {{lt, r5, r3}, "lt, r5, r3", "lt_r5_r3"},
- {{lt, r5, r4}, "lt, r5, r4", "lt_r5_r4"},
- {{lt, r5, r5}, "lt, r5, r5", "lt_r5_r5"},
- {{lt, r5, r6}, "lt, r5, r6", "lt_r5_r6"},
- {{lt, r5, r7}, "lt, r5, r7", "lt_r5_r7"},
- {{lt, r5, r8}, "lt, r5, r8", "lt_r5_r8"},
- {{lt, r5, r9}, "lt, r5, r9", "lt_r5_r9"},
- {{lt, r5, r10}, "lt, r5, r10", "lt_r5_r10"},
- {{lt, r5, r11}, "lt, r5, r11", "lt_r5_r11"},
- {{lt, r5, r12}, "lt, r5, r12", "lt_r5_r12"},
- {{lt, r5, r13}, "lt, r5, r13", "lt_r5_r13"},
- {{lt, r5, r14}, "lt, r5, r14", "lt_r5_r14"},
- {{lt, r6, r0}, "lt, r6, r0", "lt_r6_r0"},
- {{lt, r6, r1}, "lt, r6, r1", "lt_r6_r1"},
- {{lt, r6, r2}, "lt, r6, r2", "lt_r6_r2"},
- {{lt, r6, r3}, "lt, r6, r3", "lt_r6_r3"},
- {{lt, r6, r4}, "lt, r6, r4", "lt_r6_r4"},
- {{lt, r6, r5}, "lt, r6, r5", "lt_r6_r5"},
- {{lt, r6, r6}, "lt, r6, r6", "lt_r6_r6"},
- {{lt, r6, r7}, "lt, r6, r7", "lt_r6_r7"},
- {{lt, r6, r8}, "lt, r6, r8", "lt_r6_r8"},
- {{lt, r6, r9}, "lt, r6, r9", "lt_r6_r9"},
- {{lt, r6, r10}, "lt, r6, r10", "lt_r6_r10"},
- {{lt, r6, r11}, "lt, r6, r11", "lt_r6_r11"},
- {{lt, r6, r12}, "lt, r6, r12", "lt_r6_r12"},
- {{lt, r6, r13}, "lt, r6, r13", "lt_r6_r13"},
- {{lt, r6, r14}, "lt, r6, r14", "lt_r6_r14"},
- {{lt, r7, r0}, "lt, r7, r0", "lt_r7_r0"},
- {{lt, r7, r1}, "lt, r7, r1", "lt_r7_r1"},
- {{lt, r7, r2}, "lt, r7, r2", "lt_r7_r2"},
- {{lt, r7, r3}, "lt, r7, r3", "lt_r7_r3"},
- {{lt, r7, r4}, "lt, r7, r4", "lt_r7_r4"},
- {{lt, r7, r5}, "lt, r7, r5", "lt_r7_r5"},
- {{lt, r7, r6}, "lt, r7, r6", "lt_r7_r6"},
- {{lt, r7, r7}, "lt, r7, r7", "lt_r7_r7"},
- {{lt, r7, r8}, "lt, r7, r8", "lt_r7_r8"},
- {{lt, r7, r9}, "lt, r7, r9", "lt_r7_r9"},
- {{lt, r7, r10}, "lt, r7, r10", "lt_r7_r10"},
- {{lt, r7, r11}, "lt, r7, r11", "lt_r7_r11"},
- {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
- {{lt, r7, r13}, "lt, r7, r13", "lt_r7_r13"},
- {{lt, r7, r14}, "lt, r7, r14", "lt_r7_r14"},
- {{lt, r8, r0}, "lt, r8, r0", "lt_r8_r0"},
- {{lt, r8, r1}, "lt, r8, r1", "lt_r8_r1"},
- {{lt, r8, r2}, "lt, r8, r2", "lt_r8_r2"},
- {{lt, r8, r3}, "lt, r8, r3", "lt_r8_r3"},
- {{lt, r8, r4}, "lt, r8, r4", "lt_r8_r4"},
- {{lt, r8, r5}, "lt, r8, r5", "lt_r8_r5"},
- {{lt, r8, r6}, "lt, r8, r6", "lt_r8_r6"},
- {{lt, r8, r7}, "lt, r8, r7", "lt_r8_r7"},
- {{lt, r8, r8}, "lt, r8, r8", "lt_r8_r8"},
- {{lt, r8, r9}, "lt, r8, r9", "lt_r8_r9"},
- {{lt, r8, r10}, "lt, r8, r10", "lt_r8_r10"},
- {{lt, r8, r11}, "lt, r8, r11", "lt_r8_r11"},
- {{lt, r8, r12}, "lt, r8, r12", "lt_r8_r12"},
- {{lt, r8, r13}, "lt, r8, r13", "lt_r8_r13"},
- {{lt, r8, r14}, "lt, r8, r14", "lt_r8_r14"},
- {{lt, r9, r0}, "lt, r9, r0", "lt_r9_r0"},
- {{lt, r9, r1}, "lt, r9, r1", "lt_r9_r1"},
- {{lt, r9, r2}, "lt, r9, r2", "lt_r9_r2"},
- {{lt, r9, r3}, "lt, r9, r3", "lt_r9_r3"},
- {{lt, r9, r4}, "lt, r9, r4", "lt_r9_r4"},
- {{lt, r9, r5}, "lt, r9, r5", "lt_r9_r5"},
- {{lt, r9, r6}, "lt, r9, r6", "lt_r9_r6"},
- {{lt, r9, r7}, "lt, r9, r7", "lt_r9_r7"},
- {{lt, r9, r8}, "lt, r9, r8", "lt_r9_r8"},
- {{lt, r9, r9}, "lt, r9, r9", "lt_r9_r9"},
- {{lt, r9, r10}, "lt, r9, r10", "lt_r9_r10"},
- {{lt, r9, r11}, "lt, r9, r11", "lt_r9_r11"},
- {{lt, r9, r12}, "lt, r9, r12", "lt_r9_r12"},
- {{lt, r9, r13}, "lt, r9, r13", "lt_r9_r13"},
- {{lt, r9, r14}, "lt, r9, r14", "lt_r9_r14"},
- {{lt, r10, r0}, "lt, r10, r0", "lt_r10_r0"},
- {{lt, r10, r1}, "lt, r10, r1", "lt_r10_r1"},
- {{lt, r10, r2}, "lt, r10, r2", "lt_r10_r2"},
- {{lt, r10, r3}, "lt, r10, r3", "lt_r10_r3"},
- {{lt, r10, r4}, "lt, r10, r4", "lt_r10_r4"},
- {{lt, r10, r5}, "lt, r10, r5", "lt_r10_r5"},
- {{lt, r10, r6}, "lt, r10, r6", "lt_r10_r6"},
- {{lt, r10, r7}, "lt, r10, r7", "lt_r10_r7"},
- {{lt, r10, r8}, "lt, r10, r8", "lt_r10_r8"},
- {{lt, r10, r9}, "lt, r10, r9", "lt_r10_r9"},
- {{lt, r10, r10}, "lt, r10, r10", "lt_r10_r10"},
- {{lt, r10, r11}, "lt, r10, r11", "lt_r10_r11"},
- {{lt, r10, r12}, "lt, r10, r12", "lt_r10_r12"},
- {{lt, r10, r13}, "lt, r10, r13", "lt_r10_r13"},
- {{lt, r10, r14}, "lt, r10, r14", "lt_r10_r14"},
- {{lt, r11, r0}, "lt, r11, r0", "lt_r11_r0"},
- {{lt, r11, r1}, "lt, r11, r1", "lt_r11_r1"},
- {{lt, r11, r2}, "lt, r11, r2", "lt_r11_r2"},
- {{lt, r11, r3}, "lt, r11, r3", "lt_r11_r3"},
- {{lt, r11, r4}, "lt, r11, r4", "lt_r11_r4"},
- {{lt, r11, r5}, "lt, r11, r5", "lt_r11_r5"},
- {{lt, r11, r6}, "lt, r11, r6", "lt_r11_r6"},
- {{lt, r11, r7}, "lt, r11, r7", "lt_r11_r7"},
- {{lt, r11, r8}, "lt, r11, r8", "lt_r11_r8"},
- {{lt, r11, r9}, "lt, r11, r9", "lt_r11_r9"},
- {{lt, r11, r10}, "lt, r11, r10", "lt_r11_r10"},
- {{lt, r11, r11}, "lt, r11, r11", "lt_r11_r11"},
- {{lt, r11, r12}, "lt, r11, r12", "lt_r11_r12"},
- {{lt, r11, r13}, "lt, r11, r13", "lt_r11_r13"},
- {{lt, r11, r14}, "lt, r11, r14", "lt_r11_r14"},
- {{lt, r12, r0}, "lt, r12, r0", "lt_r12_r0"},
- {{lt, r12, r1}, "lt, r12, r1", "lt_r12_r1"},
- {{lt, r12, r2}, "lt, r12, r2", "lt_r12_r2"},
- {{lt, r12, r3}, "lt, r12, r3", "lt_r12_r3"},
- {{lt, r12, r4}, "lt, r12, r4", "lt_r12_r4"},
- {{lt, r12, r5}, "lt, r12, r5", "lt_r12_r5"},
- {{lt, r12, r6}, "lt, r12, r6", "lt_r12_r6"},
- {{lt, r12, r7}, "lt, r12, r7", "lt_r12_r7"},
- {{lt, r12, r8}, "lt, r12, r8", "lt_r12_r8"},
- {{lt, r12, r9}, "lt, r12, r9", "lt_r12_r9"},
- {{lt, r12, r10}, "lt, r12, r10", "lt_r12_r10"},
- {{lt, r12, r11}, "lt, r12, r11", "lt_r12_r11"},
- {{lt, r12, r12}, "lt, r12, r12", "lt_r12_r12"},
- {{lt, r12, r13}, "lt, r12, r13", "lt_r12_r13"},
- {{lt, r12, r14}, "lt, r12, r14", "lt_r12_r14"},
- {{lt, r13, r0}, "lt, r13, r0", "lt_r13_r0"},
- {{lt, r13, r1}, "lt, r13, r1", "lt_r13_r1"},
- {{lt, r13, r2}, "lt, r13, r2", "lt_r13_r2"},
- {{lt, r13, r3}, "lt, r13, r3", "lt_r13_r3"},
- {{lt, r13, r4}, "lt, r13, r4", "lt_r13_r4"},
- {{lt, r13, r5}, "lt, r13, r5", "lt_r13_r5"},
- {{lt, r13, r6}, "lt, r13, r6", "lt_r13_r6"},
- {{lt, r13, r7}, "lt, r13, r7", "lt_r13_r7"},
- {{lt, r13, r8}, "lt, r13, r8", "lt_r13_r8"},
- {{lt, r13, r9}, "lt, r13, r9", "lt_r13_r9"},
- {{lt, r13, r10}, "lt, r13, r10", "lt_r13_r10"},
- {{lt, r13, r11}, "lt, r13, r11", "lt_r13_r11"},
{{lt, r13, r12}, "lt, r13, r12", "lt_r13_r12"},
- {{lt, r13, r13}, "lt, r13, r13", "lt_r13_r13"},
- {{lt, r13, r14}, "lt, r13, r14", "lt_r13_r14"},
- {{lt, r14, r0}, "lt, r14, r0", "lt_r14_r0"},
- {{lt, r14, r1}, "lt, r14, r1", "lt_r14_r1"},
- {{lt, r14, r2}, "lt, r14, r2", "lt_r14_r2"},
{{lt, r14, r3}, "lt, r14, r3", "lt_r14_r3"},
- {{lt, r14, r4}, "lt, r14, r4", "lt_r14_r4"},
- {{lt, r14, r5}, "lt, r14, r5", "lt_r14_r5"},
- {{lt, r14, r6}, "lt, r14, r6", "lt_r14_r6"},
- {{lt, r14, r7}, "lt, r14, r7", "lt_r14_r7"},
- {{lt, r14, r8}, "lt, r14, r8", "lt_r14_r8"},
- {{lt, r14, r9}, "lt, r14, r9", "lt_r14_r9"},
- {{lt, r14, r10}, "lt, r14, r10", "lt_r14_r10"},
- {{lt, r14, r11}, "lt, r14, r11", "lt_r14_r11"},
- {{lt, r14, r12}, "lt, r14, r12", "lt_r14_r12"},
- {{lt, r14, r13}, "lt, r14, r13", "lt_r14_r13"},
- {{lt, r14, r14}, "lt, r14, r14", "lt_r14_r14"},
- {{gt, r0, r0}, "gt, r0, r0", "gt_r0_r0"},
- {{gt, r0, r1}, "gt, r0, r1", "gt_r0_r1"},
- {{gt, r0, r2}, "gt, r0, r2", "gt_r0_r2"},
- {{gt, r0, r3}, "gt, r0, r3", "gt_r0_r3"},
- {{gt, r0, r4}, "gt, r0, r4", "gt_r0_r4"},
- {{gt, r0, r5}, "gt, r0, r5", "gt_r0_r5"},
- {{gt, r0, r6}, "gt, r0, r6", "gt_r0_r6"},
- {{gt, r0, r7}, "gt, r0, r7", "gt_r0_r7"},
- {{gt, r0, r8}, "gt, r0, r8", "gt_r0_r8"},
- {{gt, r0, r9}, "gt, r0, r9", "gt_r0_r9"},
- {{gt, r0, r10}, "gt, r0, r10", "gt_r0_r10"},
- {{gt, r0, r11}, "gt, r0, r11", "gt_r0_r11"},
- {{gt, r0, r12}, "gt, r0, r12", "gt_r0_r12"},
- {{gt, r0, r13}, "gt, r0, r13", "gt_r0_r13"},
- {{gt, r0, r14}, "gt, r0, r14", "gt_r0_r14"},
- {{gt, r1, r0}, "gt, r1, r0", "gt_r1_r0"},
- {{gt, r1, r1}, "gt, r1, r1", "gt_r1_r1"},
- {{gt, r1, r2}, "gt, r1, r2", "gt_r1_r2"},
- {{gt, r1, r3}, "gt, r1, r3", "gt_r1_r3"},
- {{gt, r1, r4}, "gt, r1, r4", "gt_r1_r4"},
- {{gt, r1, r5}, "gt, r1, r5", "gt_r1_r5"},
- {{gt, r1, r6}, "gt, r1, r6", "gt_r1_r6"},
- {{gt, r1, r7}, "gt, r1, r7", "gt_r1_r7"},
- {{gt, r1, r8}, "gt, r1, r8", "gt_r1_r8"},
- {{gt, r1, r9}, "gt, r1, r9", "gt_r1_r9"},
- {{gt, r1, r10}, "gt, r1, r10", "gt_r1_r10"},
- {{gt, r1, r11}, "gt, r1, r11", "gt_r1_r11"},
- {{gt, r1, r12}, "gt, r1, r12", "gt_r1_r12"},
- {{gt, r1, r13}, "gt, r1, r13", "gt_r1_r13"},
- {{gt, r1, r14}, "gt, r1, r14", "gt_r1_r14"},
- {{gt, r2, r0}, "gt, r2, r0", "gt_r2_r0"},
- {{gt, r2, r1}, "gt, r2, r1", "gt_r2_r1"},
- {{gt, r2, r2}, "gt, r2, r2", "gt_r2_r2"},
- {{gt, r2, r3}, "gt, r2, r3", "gt_r2_r3"},
- {{gt, r2, r4}, "gt, r2, r4", "gt_r2_r4"},
- {{gt, r2, r5}, "gt, r2, r5", "gt_r2_r5"},
- {{gt, r2, r6}, "gt, r2, r6", "gt_r2_r6"},
- {{gt, r2, r7}, "gt, r2, r7", "gt_r2_r7"},
- {{gt, r2, r8}, "gt, r2, r8", "gt_r2_r8"},
- {{gt, r2, r9}, "gt, r2, r9", "gt_r2_r9"},
- {{gt, r2, r10}, "gt, r2, r10", "gt_r2_r10"},
- {{gt, r2, r11}, "gt, r2, r11", "gt_r2_r11"},
- {{gt, r2, r12}, "gt, r2, r12", "gt_r2_r12"},
- {{gt, r2, r13}, "gt, r2, r13", "gt_r2_r13"},
- {{gt, r2, r14}, "gt, r2, r14", "gt_r2_r14"},
- {{gt, r3, r0}, "gt, r3, r0", "gt_r3_r0"},
- {{gt, r3, r1}, "gt, r3, r1", "gt_r3_r1"},
- {{gt, r3, r2}, "gt, r3, r2", "gt_r3_r2"},
- {{gt, r3, r3}, "gt, r3, r3", "gt_r3_r3"},
- {{gt, r3, r4}, "gt, r3, r4", "gt_r3_r4"},
- {{gt, r3, r5}, "gt, r3, r5", "gt_r3_r5"},
- {{gt, r3, r6}, "gt, r3, r6", "gt_r3_r6"},
- {{gt, r3, r7}, "gt, r3, r7", "gt_r3_r7"},
- {{gt, r3, r8}, "gt, r3, r8", "gt_r3_r8"},
- {{gt, r3, r9}, "gt, r3, r9", "gt_r3_r9"},
- {{gt, r3, r10}, "gt, r3, r10", "gt_r3_r10"},
- {{gt, r3, r11}, "gt, r3, r11", "gt_r3_r11"},
- {{gt, r3, r12}, "gt, r3, r12", "gt_r3_r12"},
- {{gt, r3, r13}, "gt, r3, r13", "gt_r3_r13"},
- {{gt, r3, r14}, "gt, r3, r14", "gt_r3_r14"},
- {{gt, r4, r0}, "gt, r4, r0", "gt_r4_r0"},
- {{gt, r4, r1}, "gt, r4, r1", "gt_r4_r1"},
- {{gt, r4, r2}, "gt, r4, r2", "gt_r4_r2"},
- {{gt, r4, r3}, "gt, r4, r3", "gt_r4_r3"},
- {{gt, r4, r4}, "gt, r4, r4", "gt_r4_r4"},
- {{gt, r4, r5}, "gt, r4, r5", "gt_r4_r5"},
- {{gt, r4, r6}, "gt, r4, r6", "gt_r4_r6"},
- {{gt, r4, r7}, "gt, r4, r7", "gt_r4_r7"},
- {{gt, r4, r8}, "gt, r4, r8", "gt_r4_r8"},
- {{gt, r4, r9}, "gt, r4, r9", "gt_r4_r9"},
- {{gt, r4, r10}, "gt, r4, r10", "gt_r4_r10"},
- {{gt, r4, r11}, "gt, r4, r11", "gt_r4_r11"},
- {{gt, r4, r12}, "gt, r4, r12", "gt_r4_r12"},
- {{gt, r4, r13}, "gt, r4, r13", "gt_r4_r13"},
- {{gt, r4, r14}, "gt, r4, r14", "gt_r4_r14"},
- {{gt, r5, r0}, "gt, r5, r0", "gt_r5_r0"},
- {{gt, r5, r1}, "gt, r5, r1", "gt_r5_r1"},
- {{gt, r5, r2}, "gt, r5, r2", "gt_r5_r2"},
- {{gt, r5, r3}, "gt, r5, r3", "gt_r5_r3"},
- {{gt, r5, r4}, "gt, r5, r4", "gt_r5_r4"},
- {{gt, r5, r5}, "gt, r5, r5", "gt_r5_r5"},
- {{gt, r5, r6}, "gt, r5, r6", "gt_r5_r6"},
- {{gt, r5, r7}, "gt, r5, r7", "gt_r5_r7"},
- {{gt, r5, r8}, "gt, r5, r8", "gt_r5_r8"},
- {{gt, r5, r9}, "gt, r5, r9", "gt_r5_r9"},
- {{gt, r5, r10}, "gt, r5, r10", "gt_r5_r10"},
- {{gt, r5, r11}, "gt, r5, r11", "gt_r5_r11"},
- {{gt, r5, r12}, "gt, r5, r12", "gt_r5_r12"},
- {{gt, r5, r13}, "gt, r5, r13", "gt_r5_r13"},
- {{gt, r5, r14}, "gt, r5, r14", "gt_r5_r14"},
- {{gt, r6, r0}, "gt, r6, r0", "gt_r6_r0"},
- {{gt, r6, r1}, "gt, r6, r1", "gt_r6_r1"},
- {{gt, r6, r2}, "gt, r6, r2", "gt_r6_r2"},
- {{gt, r6, r3}, "gt, r6, r3", "gt_r6_r3"},
- {{gt, r6, r4}, "gt, r6, r4", "gt_r6_r4"},
- {{gt, r6, r5}, "gt, r6, r5", "gt_r6_r5"},
- {{gt, r6, r6}, "gt, r6, r6", "gt_r6_r6"},
- {{gt, r6, r7}, "gt, r6, r7", "gt_r6_r7"},
- {{gt, r6, r8}, "gt, r6, r8", "gt_r6_r8"},
- {{gt, r6, r9}, "gt, r6, r9", "gt_r6_r9"},
- {{gt, r6, r10}, "gt, r6, r10", "gt_r6_r10"},
- {{gt, r6, r11}, "gt, r6, r11", "gt_r6_r11"},
- {{gt, r6, r12}, "gt, r6, r12", "gt_r6_r12"},
- {{gt, r6, r13}, "gt, r6, r13", "gt_r6_r13"},
- {{gt, r6, r14}, "gt, r6, r14", "gt_r6_r14"},
- {{gt, r7, r0}, "gt, r7, r0", "gt_r7_r0"},
- {{gt, r7, r1}, "gt, r7, r1", "gt_r7_r1"},
- {{gt, r7, r2}, "gt, r7, r2", "gt_r7_r2"},
- {{gt, r7, r3}, "gt, r7, r3", "gt_r7_r3"},
- {{gt, r7, r4}, "gt, r7, r4", "gt_r7_r4"},
- {{gt, r7, r5}, "gt, r7, r5", "gt_r7_r5"},
- {{gt, r7, r6}, "gt, r7, r6", "gt_r7_r6"},
- {{gt, r7, r7}, "gt, r7, r7", "gt_r7_r7"},
- {{gt, r7, r8}, "gt, r7, r8", "gt_r7_r8"},
- {{gt, r7, r9}, "gt, r7, r9", "gt_r7_r9"},
- {{gt, r7, r10}, "gt, r7, r10", "gt_r7_r10"},
- {{gt, r7, r11}, "gt, r7, r11", "gt_r7_r11"},
- {{gt, r7, r12}, "gt, r7, r12", "gt_r7_r12"},
- {{gt, r7, r13}, "gt, r7, r13", "gt_r7_r13"},
- {{gt, r7, r14}, "gt, r7, r14", "gt_r7_r14"},
- {{gt, r8, r0}, "gt, r8, r0", "gt_r8_r0"},
- {{gt, r8, r1}, "gt, r8, r1", "gt_r8_r1"},
- {{gt, r8, r2}, "gt, r8, r2", "gt_r8_r2"},
- {{gt, r8, r3}, "gt, r8, r3", "gt_r8_r3"},
- {{gt, r8, r4}, "gt, r8, r4", "gt_r8_r4"},
- {{gt, r8, r5}, "gt, r8, r5", "gt_r8_r5"},
- {{gt, r8, r6}, "gt, r8, r6", "gt_r8_r6"},
- {{gt, r8, r7}, "gt, r8, r7", "gt_r8_r7"},
- {{gt, r8, r8}, "gt, r8, r8", "gt_r8_r8"},
- {{gt, r8, r9}, "gt, r8, r9", "gt_r8_r9"},
- {{gt, r8, r10}, "gt, r8, r10", "gt_r8_r10"},
- {{gt, r8, r11}, "gt, r8, r11", "gt_r8_r11"},
- {{gt, r8, r12}, "gt, r8, r12", "gt_r8_r12"},
- {{gt, r8, r13}, "gt, r8, r13", "gt_r8_r13"},
- {{gt, r8, r14}, "gt, r8, r14", "gt_r8_r14"},
- {{gt, r9, r0}, "gt, r9, r0", "gt_r9_r0"},
- {{gt, r9, r1}, "gt, r9, r1", "gt_r9_r1"},
- {{gt, r9, r2}, "gt, r9, r2", "gt_r9_r2"},
- {{gt, r9, r3}, "gt, r9, r3", "gt_r9_r3"},
- {{gt, r9, r4}, "gt, r9, r4", "gt_r9_r4"},
- {{gt, r9, r5}, "gt, r9, r5", "gt_r9_r5"},
- {{gt, r9, r6}, "gt, r9, r6", "gt_r9_r6"},
- {{gt, r9, r7}, "gt, r9, r7", "gt_r9_r7"},
- {{gt, r9, r8}, "gt, r9, r8", "gt_r9_r8"},
- {{gt, r9, r9}, "gt, r9, r9", "gt_r9_r9"},
- {{gt, r9, r10}, "gt, r9, r10", "gt_r9_r10"},
- {{gt, r9, r11}, "gt, r9, r11", "gt_r9_r11"},
- {{gt, r9, r12}, "gt, r9, r12", "gt_r9_r12"},
- {{gt, r9, r13}, "gt, r9, r13", "gt_r9_r13"},
- {{gt, r9, r14}, "gt, r9, r14", "gt_r9_r14"},
- {{gt, r10, r0}, "gt, r10, r0", "gt_r10_r0"},
- {{gt, r10, r1}, "gt, r10, r1", "gt_r10_r1"},
- {{gt, r10, r2}, "gt, r10, r2", "gt_r10_r2"},
- {{gt, r10, r3}, "gt, r10, r3", "gt_r10_r3"},
- {{gt, r10, r4}, "gt, r10, r4", "gt_r10_r4"},
- {{gt, r10, r5}, "gt, r10, r5", "gt_r10_r5"},
- {{gt, r10, r6}, "gt, r10, r6", "gt_r10_r6"},
- {{gt, r10, r7}, "gt, r10, r7", "gt_r10_r7"},
- {{gt, r10, r8}, "gt, r10, r8", "gt_r10_r8"},
+ {{mi, r12, r14}, "mi, r12, r14", "mi_r12_r14"},
+ {{vs, r11, r2}, "vs, r11, r2", "vs_r11_r2"},
+ {{ls, r11, r0}, "ls, r11, r0", "ls_r11_r0"},
{{gt, r10, r9}, "gt, r10, r9", "gt_r10_r9"},
- {{gt, r10, r10}, "gt, r10, r10", "gt_r10_r10"},
- {{gt, r10, r11}, "gt, r10, r11", "gt_r10_r11"},
- {{gt, r10, r12}, "gt, r10, r12", "gt_r10_r12"},
- {{gt, r10, r13}, "gt, r10, r13", "gt_r10_r13"},
- {{gt, r10, r14}, "gt, r10, r14", "gt_r10_r14"},
- {{gt, r11, r0}, "gt, r11, r0", "gt_r11_r0"},
- {{gt, r11, r1}, "gt, r11, r1", "gt_r11_r1"},
- {{gt, r11, r2}, "gt, r11, r2", "gt_r11_r2"},
- {{gt, r11, r3}, "gt, r11, r3", "gt_r11_r3"},
- {{gt, r11, r4}, "gt, r11, r4", "gt_r11_r4"},
- {{gt, r11, r5}, "gt, r11, r5", "gt_r11_r5"},
- {{gt, r11, r6}, "gt, r11, r6", "gt_r11_r6"},
- {{gt, r11, r7}, "gt, r11, r7", "gt_r11_r7"},
- {{gt, r11, r8}, "gt, r11, r8", "gt_r11_r8"},
- {{gt, r11, r9}, "gt, r11, r9", "gt_r11_r9"},
- {{gt, r11, r10}, "gt, r11, r10", "gt_r11_r10"},
- {{gt, r11, r11}, "gt, r11, r11", "gt_r11_r11"},
- {{gt, r11, r12}, "gt, r11, r12", "gt_r11_r12"},
- {{gt, r11, r13}, "gt, r11, r13", "gt_r11_r13"},
- {{gt, r11, r14}, "gt, r11, r14", "gt_r11_r14"},
- {{gt, r12, r0}, "gt, r12, r0", "gt_r12_r0"},
- {{gt, r12, r1}, "gt, r12, r1", "gt_r12_r1"},
- {{gt, r12, r2}, "gt, r12, r2", "gt_r12_r2"},
- {{gt, r12, r3}, "gt, r12, r3", "gt_r12_r3"},
- {{gt, r12, r4}, "gt, r12, r4", "gt_r12_r4"},
- {{gt, r12, r5}, "gt, r12, r5", "gt_r12_r5"},
- {{gt, r12, r6}, "gt, r12, r6", "gt_r12_r6"},
- {{gt, r12, r7}, "gt, r12, r7", "gt_r12_r7"},
- {{gt, r12, r8}, "gt, r12, r8", "gt_r12_r8"},
- {{gt, r12, r9}, "gt, r12, r9", "gt_r12_r9"},
- {{gt, r12, r10}, "gt, r12, r10", "gt_r12_r10"},
- {{gt, r12, r11}, "gt, r12, r11", "gt_r12_r11"},
- {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
- {{gt, r12, r13}, "gt, r12, r13", "gt_r12_r13"},
- {{gt, r12, r14}, "gt, r12, r14", "gt_r12_r14"},
- {{gt, r13, r0}, "gt, r13, r0", "gt_r13_r0"},
- {{gt, r13, r1}, "gt, r13, r1", "gt_r13_r1"},
- {{gt, r13, r2}, "gt, r13, r2", "gt_r13_r2"},
- {{gt, r13, r3}, "gt, r13, r3", "gt_r13_r3"},
- {{gt, r13, r4}, "gt, r13, r4", "gt_r13_r4"},
- {{gt, r13, r5}, "gt, r13, r5", "gt_r13_r5"},
- {{gt, r13, r6}, "gt, r13, r6", "gt_r13_r6"},
- {{gt, r13, r7}, "gt, r13, r7", "gt_r13_r7"},
- {{gt, r13, r8}, "gt, r13, r8", "gt_r13_r8"},
- {{gt, r13, r9}, "gt, r13, r9", "gt_r13_r9"},
- {{gt, r13, r10}, "gt, r13, r10", "gt_r13_r10"},
- {{gt, r13, r11}, "gt, r13, r11", "gt_r13_r11"},
- {{gt, r13, r12}, "gt, r13, r12", "gt_r13_r12"},
- {{gt, r13, r13}, "gt, r13, r13", "gt_r13_r13"},
- {{gt, r13, r14}, "gt, r13, r14", "gt_r13_r14"},
- {{gt, r14, r0}, "gt, r14, r0", "gt_r14_r0"},
- {{gt, r14, r1}, "gt, r14, r1", "gt_r14_r1"},
- {{gt, r14, r2}, "gt, r14, r2", "gt_r14_r2"},
- {{gt, r14, r3}, "gt, r14, r3", "gt_r14_r3"},
- {{gt, r14, r4}, "gt, r14, r4", "gt_r14_r4"},
- {{gt, r14, r5}, "gt, r14, r5", "gt_r14_r5"},
- {{gt, r14, r6}, "gt, r14, r6", "gt_r14_r6"},
- {{gt, r14, r7}, "gt, r14, r7", "gt_r14_r7"},
- {{gt, r14, r8}, "gt, r14, r8", "gt_r14_r8"},
- {{gt, r14, r9}, "gt, r14, r9", "gt_r14_r9"},
- {{gt, r14, r10}, "gt, r14, r10", "gt_r14_r10"},
- {{gt, r14, r11}, "gt, r14, r11", "gt_r14_r11"},
- {{gt, r14, r12}, "gt, r14, r12", "gt_r14_r12"},
- {{gt, r14, r13}, "gt, r14, r13", "gt_r14_r13"},
- {{gt, r14, r14}, "gt, r14, r14", "gt_r14_r14"},
- {{le, r0, r0}, "le, r0, r0", "le_r0_r0"},
- {{le, r0, r1}, "le, r0, r1", "le_r0_r1"},
- {{le, r0, r2}, "le, r0, r2", "le_r0_r2"},
- {{le, r0, r3}, "le, r0, r3", "le_r0_r3"},
- {{le, r0, r4}, "le, r0, r4", "le_r0_r4"},
- {{le, r0, r5}, "le, r0, r5", "le_r0_r5"},
- {{le, r0, r6}, "le, r0, r6", "le_r0_r6"},
- {{le, r0, r7}, "le, r0, r7", "le_r0_r7"},
- {{le, r0, r8}, "le, r0, r8", "le_r0_r8"},
- {{le, r0, r9}, "le, r0, r9", "le_r0_r9"},
- {{le, r0, r10}, "le, r0, r10", "le_r0_r10"},
- {{le, r0, r11}, "le, r0, r11", "le_r0_r11"},
- {{le, r0, r12}, "le, r0, r12", "le_r0_r12"},
- {{le, r0, r13}, "le, r0, r13", "le_r0_r13"},
- {{le, r0, r14}, "le, r0, r14", "le_r0_r14"},
- {{le, r1, r0}, "le, r1, r0", "le_r1_r0"},
- {{le, r1, r1}, "le, r1, r1", "le_r1_r1"},
- {{le, r1, r2}, "le, r1, r2", "le_r1_r2"},
- {{le, r1, r3}, "le, r1, r3", "le_r1_r3"},
- {{le, r1, r4}, "le, r1, r4", "le_r1_r4"},
- {{le, r1, r5}, "le, r1, r5", "le_r1_r5"},
- {{le, r1, r6}, "le, r1, r6", "le_r1_r6"},
- {{le, r1, r7}, "le, r1, r7", "le_r1_r7"},
- {{le, r1, r8}, "le, r1, r8", "le_r1_r8"},
- {{le, r1, r9}, "le, r1, r9", "le_r1_r9"},
- {{le, r1, r10}, "le, r1, r10", "le_r1_r10"},
- {{le, r1, r11}, "le, r1, r11", "le_r1_r11"},
- {{le, r1, r12}, "le, r1, r12", "le_r1_r12"},
- {{le, r1, r13}, "le, r1, r13", "le_r1_r13"},
- {{le, r1, r14}, "le, r1, r14", "le_r1_r14"},
- {{le, r2, r0}, "le, r2, r0", "le_r2_r0"},
- {{le, r2, r1}, "le, r2, r1", "le_r2_r1"},
- {{le, r2, r2}, "le, r2, r2", "le_r2_r2"},
- {{le, r2, r3}, "le, r2, r3", "le_r2_r3"},
- {{le, r2, r4}, "le, r2, r4", "le_r2_r4"},
- {{le, r2, r5}, "le, r2, r5", "le_r2_r5"},
- {{le, r2, r6}, "le, r2, r6", "le_r2_r6"},
- {{le, r2, r7}, "le, r2, r7", "le_r2_r7"},
- {{le, r2, r8}, "le, r2, r8", "le_r2_r8"},
- {{le, r2, r9}, "le, r2, r9", "le_r2_r9"},
- {{le, r2, r10}, "le, r2, r10", "le_r2_r10"},
- {{le, r2, r11}, "le, r2, r11", "le_r2_r11"},
- {{le, r2, r12}, "le, r2, r12", "le_r2_r12"},
- {{le, r2, r13}, "le, r2, r13", "le_r2_r13"},
- {{le, r2, r14}, "le, r2, r14", "le_r2_r14"},
- {{le, r3, r0}, "le, r3, r0", "le_r3_r0"},
- {{le, r3, r1}, "le, r3, r1", "le_r3_r1"},
- {{le, r3, r2}, "le, r3, r2", "le_r3_r2"},
- {{le, r3, r3}, "le, r3, r3", "le_r3_r3"},
- {{le, r3, r4}, "le, r3, r4", "le_r3_r4"},
- {{le, r3, r5}, "le, r3, r5", "le_r3_r5"},
- {{le, r3, r6}, "le, r3, r6", "le_r3_r6"},
- {{le, r3, r7}, "le, r3, r7", "le_r3_r7"},
- {{le, r3, r8}, "le, r3, r8", "le_r3_r8"},
- {{le, r3, r9}, "le, r3, r9", "le_r3_r9"},
- {{le, r3, r10}, "le, r3, r10", "le_r3_r10"},
- {{le, r3, r11}, "le, r3, r11", "le_r3_r11"},
- {{le, r3, r12}, "le, r3, r12", "le_r3_r12"},
- {{le, r3, r13}, "le, r3, r13", "le_r3_r13"},
- {{le, r3, r14}, "le, r3, r14", "le_r3_r14"},
- {{le, r4, r0}, "le, r4, r0", "le_r4_r0"},
- {{le, r4, r1}, "le, r4, r1", "le_r4_r1"},
- {{le, r4, r2}, "le, r4, r2", "le_r4_r2"},
- {{le, r4, r3}, "le, r4, r3", "le_r4_r3"},
- {{le, r4, r4}, "le, r4, r4", "le_r4_r4"},
- {{le, r4, r5}, "le, r4, r5", "le_r4_r5"},
- {{le, r4, r6}, "le, r4, r6", "le_r4_r6"},
- {{le, r4, r7}, "le, r4, r7", "le_r4_r7"},
- {{le, r4, r8}, "le, r4, r8", "le_r4_r8"},
- {{le, r4, r9}, "le, r4, r9", "le_r4_r9"},
- {{le, r4, r10}, "le, r4, r10", "le_r4_r10"},
- {{le, r4, r11}, "le, r4, r11", "le_r4_r11"},
- {{le, r4, r12}, "le, r4, r12", "le_r4_r12"},
- {{le, r4, r13}, "le, r4, r13", "le_r4_r13"},
- {{le, r4, r14}, "le, r4, r14", "le_r4_r14"},
- {{le, r5, r0}, "le, r5, r0", "le_r5_r0"},
- {{le, r5, r1}, "le, r5, r1", "le_r5_r1"},
- {{le, r5, r2}, "le, r5, r2", "le_r5_r2"},
- {{le, r5, r3}, "le, r5, r3", "le_r5_r3"},
- {{le, r5, r4}, "le, r5, r4", "le_r5_r4"},
- {{le, r5, r5}, "le, r5, r5", "le_r5_r5"},
- {{le, r5, r6}, "le, r5, r6", "le_r5_r6"},
- {{le, r5, r7}, "le, r5, r7", "le_r5_r7"},
- {{le, r5, r8}, "le, r5, r8", "le_r5_r8"},
- {{le, r5, r9}, "le, r5, r9", "le_r5_r9"},
- {{le, r5, r10}, "le, r5, r10", "le_r5_r10"},
- {{le, r5, r11}, "le, r5, r11", "le_r5_r11"},
- {{le, r5, r12}, "le, r5, r12", "le_r5_r12"},
- {{le, r5, r13}, "le, r5, r13", "le_r5_r13"},
- {{le, r5, r14}, "le, r5, r14", "le_r5_r14"},
- {{le, r6, r0}, "le, r6, r0", "le_r6_r0"},
- {{le, r6, r1}, "le, r6, r1", "le_r6_r1"},
- {{le, r6, r2}, "le, r6, r2", "le_r6_r2"},
- {{le, r6, r3}, "le, r6, r3", "le_r6_r3"},
- {{le, r6, r4}, "le, r6, r4", "le_r6_r4"},
- {{le, r6, r5}, "le, r6, r5", "le_r6_r5"},
- {{le, r6, r6}, "le, r6, r6", "le_r6_r6"},
- {{le, r6, r7}, "le, r6, r7", "le_r6_r7"},
- {{le, r6, r8}, "le, r6, r8", "le_r6_r8"},
- {{le, r6, r9}, "le, r6, r9", "le_r6_r9"},
- {{le, r6, r10}, "le, r6, r10", "le_r6_r10"},
- {{le, r6, r11}, "le, r6, r11", "le_r6_r11"},
- {{le, r6, r12}, "le, r6, r12", "le_r6_r12"},
- {{le, r6, r13}, "le, r6, r13", "le_r6_r13"},
- {{le, r6, r14}, "le, r6, r14", "le_r6_r14"},
- {{le, r7, r0}, "le, r7, r0", "le_r7_r0"},
- {{le, r7, r1}, "le, r7, r1", "le_r7_r1"},
- {{le, r7, r2}, "le, r7, r2", "le_r7_r2"},
- {{le, r7, r3}, "le, r7, r3", "le_r7_r3"},
- {{le, r7, r4}, "le, r7, r4", "le_r7_r4"},
- {{le, r7, r5}, "le, r7, r5", "le_r7_r5"},
- {{le, r7, r6}, "le, r7, r6", "le_r7_r6"},
- {{le, r7, r7}, "le, r7, r7", "le_r7_r7"},
- {{le, r7, r8}, "le, r7, r8", "le_r7_r8"},
- {{le, r7, r9}, "le, r7, r9", "le_r7_r9"},
- {{le, r7, r10}, "le, r7, r10", "le_r7_r10"},
- {{le, r7, r11}, "le, r7, r11", "le_r7_r11"},
- {{le, r7, r12}, "le, r7, r12", "le_r7_r12"},
- {{le, r7, r13}, "le, r7, r13", "le_r7_r13"},
- {{le, r7, r14}, "le, r7, r14", "le_r7_r14"},
- {{le, r8, r0}, "le, r8, r0", "le_r8_r0"},
- {{le, r8, r1}, "le, r8, r1", "le_r8_r1"},
- {{le, r8, r2}, "le, r8, r2", "le_r8_r2"},
- {{le, r8, r3}, "le, r8, r3", "le_r8_r3"},
- {{le, r8, r4}, "le, r8, r4", "le_r8_r4"},
- {{le, r8, r5}, "le, r8, r5", "le_r8_r5"},
- {{le, r8, r6}, "le, r8, r6", "le_r8_r6"},
- {{le, r8, r7}, "le, r8, r7", "le_r8_r7"},
- {{le, r8, r8}, "le, r8, r8", "le_r8_r8"},
- {{le, r8, r9}, "le, r8, r9", "le_r8_r9"},
- {{le, r8, r10}, "le, r8, r10", "le_r8_r10"},
- {{le, r8, r11}, "le, r8, r11", "le_r8_r11"},
- {{le, r8, r12}, "le, r8, r12", "le_r8_r12"},
- {{le, r8, r13}, "le, r8, r13", "le_r8_r13"},
- {{le, r8, r14}, "le, r8, r14", "le_r8_r14"},
- {{le, r9, r0}, "le, r9, r0", "le_r9_r0"},
- {{le, r9, r1}, "le, r9, r1", "le_r9_r1"},
- {{le, r9, r2}, "le, r9, r2", "le_r9_r2"},
- {{le, r9, r3}, "le, r9, r3", "le_r9_r3"},
- {{le, r9, r4}, "le, r9, r4", "le_r9_r4"},
- {{le, r9, r5}, "le, r9, r5", "le_r9_r5"},
- {{le, r9, r6}, "le, r9, r6", "le_r9_r6"},
- {{le, r9, r7}, "le, r9, r7", "le_r9_r7"},
- {{le, r9, r8}, "le, r9, r8", "le_r9_r8"},
- {{le, r9, r9}, "le, r9, r9", "le_r9_r9"},
- {{le, r9, r10}, "le, r9, r10", "le_r9_r10"},
- {{le, r9, r11}, "le, r9, r11", "le_r9_r11"},
- {{le, r9, r12}, "le, r9, r12", "le_r9_r12"},
- {{le, r9, r13}, "le, r9, r13", "le_r9_r13"},
- {{le, r9, r14}, "le, r9, r14", "le_r9_r14"},
- {{le, r10, r0}, "le, r10, r0", "le_r10_r0"},
- {{le, r10, r1}, "le, r10, r1", "le_r10_r1"},
- {{le, r10, r2}, "le, r10, r2", "le_r10_r2"},
- {{le, r10, r3}, "le, r10, r3", "le_r10_r3"},
- {{le, r10, r4}, "le, r10, r4", "le_r10_r4"},
- {{le, r10, r5}, "le, r10, r5", "le_r10_r5"},
- {{le, r10, r6}, "le, r10, r6", "le_r10_r6"},
- {{le, r10, r7}, "le, r10, r7", "le_r10_r7"},
- {{le, r10, r8}, "le, r10, r8", "le_r10_r8"},
- {{le, r10, r9}, "le, r10, r9", "le_r10_r9"},
- {{le, r10, r10}, "le, r10, r10", "le_r10_r10"},
- {{le, r10, r11}, "le, r10, r11", "le_r10_r11"},
{{le, r10, r12}, "le, r10, r12", "le_r10_r12"},
- {{le, r10, r13}, "le, r10, r13", "le_r10_r13"},
- {{le, r10, r14}, "le, r10, r14", "le_r10_r14"},
- {{le, r11, r0}, "le, r11, r0", "le_r11_r0"},
- {{le, r11, r1}, "le, r11, r1", "le_r11_r1"},
- {{le, r11, r2}, "le, r11, r2", "le_r11_r2"},
- {{le, r11, r3}, "le, r11, r3", "le_r11_r3"},
- {{le, r11, r4}, "le, r11, r4", "le_r11_r4"},
- {{le, r11, r5}, "le, r11, r5", "le_r11_r5"},
- {{le, r11, r6}, "le, r11, r6", "le_r11_r6"},
- {{le, r11, r7}, "le, r11, r7", "le_r11_r7"},
- {{le, r11, r8}, "le, r11, r8", "le_r11_r8"},
- {{le, r11, r9}, "le, r11, r9", "le_r11_r9"},
- {{le, r11, r10}, "le, r11, r10", "le_r11_r10"},
- {{le, r11, r11}, "le, r11, r11", "le_r11_r11"},
- {{le, r11, r12}, "le, r11, r12", "le_r11_r12"},
- {{le, r11, r13}, "le, r11, r13", "le_r11_r13"},
- {{le, r11, r14}, "le, r11, r14", "le_r11_r14"},
- {{le, r12, r0}, "le, r12, r0", "le_r12_r0"},
- {{le, r12, r1}, "le, r12, r1", "le_r12_r1"},
- {{le, r12, r2}, "le, r12, r2", "le_r12_r2"},
- {{le, r12, r3}, "le, r12, r3", "le_r12_r3"},
- {{le, r12, r4}, "le, r12, r4", "le_r12_r4"},
- {{le, r12, r5}, "le, r12, r5", "le_r12_r5"},
- {{le, r12, r6}, "le, r12, r6", "le_r12_r6"},
- {{le, r12, r7}, "le, r12, r7", "le_r12_r7"},
- {{le, r12, r8}, "le, r12, r8", "le_r12_r8"},
- {{le, r12, r9}, "le, r12, r9", "le_r12_r9"},
- {{le, r12, r10}, "le, r12, r10", "le_r12_r10"},
- {{le, r12, r11}, "le, r12, r11", "le_r12_r11"},
- {{le, r12, r12}, "le, r12, r12", "le_r12_r12"},
- {{le, r12, r13}, "le, r12, r13", "le_r12_r13"},
- {{le, r12, r14}, "le, r12, r14", "le_r12_r14"},
- {{le, r13, r0}, "le, r13, r0", "le_r13_r0"},
- {{le, r13, r1}, "le, r13, r1", "le_r13_r1"},
- {{le, r13, r2}, "le, r13, r2", "le_r13_r2"},
- {{le, r13, r3}, "le, r13, r3", "le_r13_r3"},
- {{le, r13, r4}, "le, r13, r4", "le_r13_r4"},
- {{le, r13, r5}, "le, r13, r5", "le_r13_r5"},
- {{le, r13, r6}, "le, r13, r6", "le_r13_r6"},
- {{le, r13, r7}, "le, r13, r7", "le_r13_r7"},
- {{le, r13, r8}, "le, r13, r8", "le_r13_r8"},
- {{le, r13, r9}, "le, r13, r9", "le_r13_r9"},
- {{le, r13, r10}, "le, r13, r10", "le_r13_r10"},
- {{le, r13, r11}, "le, r13, r11", "le_r13_r11"},
- {{le, r13, r12}, "le, r13, r12", "le_r13_r12"},
- {{le, r13, r13}, "le, r13, r13", "le_r13_r13"},
- {{le, r13, r14}, "le, r13, r14", "le_r13_r14"},
- {{le, r14, r0}, "le, r14, r0", "le_r14_r0"},
- {{le, r14, r1}, "le, r14, r1", "le_r14_r1"},
- {{le, r14, r2}, "le, r14, r2", "le_r14_r2"},
- {{le, r14, r3}, "le, r14, r3", "le_r14_r3"},
- {{le, r14, r4}, "le, r14, r4", "le_r14_r4"},
- {{le, r14, r5}, "le, r14, r5", "le_r14_r5"},
- {{le, r14, r6}, "le, r14, r6", "le_r14_r6"},
- {{le, r14, r7}, "le, r14, r7", "le_r14_r7"},
- {{le, r14, r8}, "le, r14, r8", "le_r14_r8"},
- {{le, r14, r9}, "le, r14, r9", "le_r14_r9"},
- {{le, r14, r10}, "le, r14, r10", "le_r14_r10"},
- {{le, r14, r11}, "le, r14, r11", "le_r14_r11"},
- {{le, r14, r12}, "le, r14, r12", "le_r14_r12"},
- {{le, r14, r13}, "le, r14, r13", "le_r14_r13"},
- {{le, r14, r14}, "le, r14, r14", "le_r14_r14"},
- {{al, r0, r0}, "al, r0, r0", "al_r0_r0"},
- {{al, r0, r1}, "al, r0, r1", "al_r0_r1"},
- {{al, r0, r2}, "al, r0, r2", "al_r0_r2"},
- {{al, r0, r3}, "al, r0, r3", "al_r0_r3"},
- {{al, r0, r4}, "al, r0, r4", "al_r0_r4"},
- {{al, r0, r5}, "al, r0, r5", "al_r0_r5"},
- {{al, r0, r6}, "al, r0, r6", "al_r0_r6"},
- {{al, r0, r7}, "al, r0, r7", "al_r0_r7"},
- {{al, r0, r8}, "al, r0, r8", "al_r0_r8"},
- {{al, r0, r9}, "al, r0, r9", "al_r0_r9"},
- {{al, r0, r10}, "al, r0, r10", "al_r0_r10"},
- {{al, r0, r11}, "al, r0, r11", "al_r0_r11"},
- {{al, r0, r12}, "al, r0, r12", "al_r0_r12"},
- {{al, r0, r13}, "al, r0, r13", "al_r0_r13"},
- {{al, r0, r14}, "al, r0, r14", "al_r0_r14"},
- {{al, r1, r0}, "al, r1, r0", "al_r1_r0"},
- {{al, r1, r1}, "al, r1, r1", "al_r1_r1"},
- {{al, r1, r2}, "al, r1, r2", "al_r1_r2"},
- {{al, r1, r3}, "al, r1, r3", "al_r1_r3"},
- {{al, r1, r4}, "al, r1, r4", "al_r1_r4"},
- {{al, r1, r5}, "al, r1, r5", "al_r1_r5"},
- {{al, r1, r6}, "al, r1, r6", "al_r1_r6"},
- {{al, r1, r7}, "al, r1, r7", "al_r1_r7"},
- {{al, r1, r8}, "al, r1, r8", "al_r1_r8"},
- {{al, r1, r9}, "al, r1, r9", "al_r1_r9"},
- {{al, r1, r10}, "al, r1, r10", "al_r1_r10"},
- {{al, r1, r11}, "al, r1, r11", "al_r1_r11"},
- {{al, r1, r12}, "al, r1, r12", "al_r1_r12"},
- {{al, r1, r13}, "al, r1, r13", "al_r1_r13"},
- {{al, r1, r14}, "al, r1, r14", "al_r1_r14"},
- {{al, r2, r0}, "al, r2, r0", "al_r2_r0"},
- {{al, r2, r1}, "al, r2, r1", "al_r2_r1"},
- {{al, r2, r2}, "al, r2, r2", "al_r2_r2"},
- {{al, r2, r3}, "al, r2, r3", "al_r2_r3"},
- {{al, r2, r4}, "al, r2, r4", "al_r2_r4"},
- {{al, r2, r5}, "al, r2, r5", "al_r2_r5"},
- {{al, r2, r6}, "al, r2, r6", "al_r2_r6"},
- {{al, r2, r7}, "al, r2, r7", "al_r2_r7"},
- {{al, r2, r8}, "al, r2, r8", "al_r2_r8"},
- {{al, r2, r9}, "al, r2, r9", "al_r2_r9"},
- {{al, r2, r10}, "al, r2, r10", "al_r2_r10"},
- {{al, r2, r11}, "al, r2, r11", "al_r2_r11"},
- {{al, r2, r12}, "al, r2, r12", "al_r2_r12"},
- {{al, r2, r13}, "al, r2, r13", "al_r2_r13"},
- {{al, r2, r14}, "al, r2, r14", "al_r2_r14"},
- {{al, r3, r0}, "al, r3, r0", "al_r3_r0"},
- {{al, r3, r1}, "al, r3, r1", "al_r3_r1"},
- {{al, r3, r2}, "al, r3, r2", "al_r3_r2"},
- {{al, r3, r3}, "al, r3, r3", "al_r3_r3"},
- {{al, r3, r4}, "al, r3, r4", "al_r3_r4"},
- {{al, r3, r5}, "al, r3, r5", "al_r3_r5"},
- {{al, r3, r6}, "al, r3, r6", "al_r3_r6"},
- {{al, r3, r7}, "al, r3, r7", "al_r3_r7"},
- {{al, r3, r8}, "al, r3, r8", "al_r3_r8"},
- {{al, r3, r9}, "al, r3, r9", "al_r3_r9"},
- {{al, r3, r10}, "al, r3, r10", "al_r3_r10"},
- {{al, r3, r11}, "al, r3, r11", "al_r3_r11"},
- {{al, r3, r12}, "al, r3, r12", "al_r3_r12"},
- {{al, r3, r13}, "al, r3, r13", "al_r3_r13"},
- {{al, r3, r14}, "al, r3, r14", "al_r3_r14"},
- {{al, r4, r0}, "al, r4, r0", "al_r4_r0"},
- {{al, r4, r1}, "al, r4, r1", "al_r4_r1"},
- {{al, r4, r2}, "al, r4, r2", "al_r4_r2"},
- {{al, r4, r3}, "al, r4, r3", "al_r4_r3"},
- {{al, r4, r4}, "al, r4, r4", "al_r4_r4"},
- {{al, r4, r5}, "al, r4, r5", "al_r4_r5"},
- {{al, r4, r6}, "al, r4, r6", "al_r4_r6"},
- {{al, r4, r7}, "al, r4, r7", "al_r4_r7"},
- {{al, r4, r8}, "al, r4, r8", "al_r4_r8"},
- {{al, r4, r9}, "al, r4, r9", "al_r4_r9"},
- {{al, r4, r10}, "al, r4, r10", "al_r4_r10"},
- {{al, r4, r11}, "al, r4, r11", "al_r4_r11"},
- {{al, r4, r12}, "al, r4, r12", "al_r4_r12"},
- {{al, r4, r13}, "al, r4, r13", "al_r4_r13"},
- {{al, r4, r14}, "al, r4, r14", "al_r4_r14"},
- {{al, r5, r0}, "al, r5, r0", "al_r5_r0"},
- {{al, r5, r1}, "al, r5, r1", "al_r5_r1"},
- {{al, r5, r2}, "al, r5, r2", "al_r5_r2"},
- {{al, r5, r3}, "al, r5, r3", "al_r5_r3"},
- {{al, r5, r4}, "al, r5, r4", "al_r5_r4"},
- {{al, r5, r5}, "al, r5, r5", "al_r5_r5"},
- {{al, r5, r6}, "al, r5, r6", "al_r5_r6"},
- {{al, r5, r7}, "al, r5, r7", "al_r5_r7"},
- {{al, r5, r8}, "al, r5, r8", "al_r5_r8"},
- {{al, r5, r9}, "al, r5, r9", "al_r5_r9"},
- {{al, r5, r10}, "al, r5, r10", "al_r5_r10"},
- {{al, r5, r11}, "al, r5, r11", "al_r5_r11"},
- {{al, r5, r12}, "al, r5, r12", "al_r5_r12"},
- {{al, r5, r13}, "al, r5, r13", "al_r5_r13"},
- {{al, r5, r14}, "al, r5, r14", "al_r5_r14"},
- {{al, r6, r0}, "al, r6, r0", "al_r6_r0"},
- {{al, r6, r1}, "al, r6, r1", "al_r6_r1"},
- {{al, r6, r2}, "al, r6, r2", "al_r6_r2"},
- {{al, r6, r3}, "al, r6, r3", "al_r6_r3"},
- {{al, r6, r4}, "al, r6, r4", "al_r6_r4"},
- {{al, r6, r5}, "al, r6, r5", "al_r6_r5"},
- {{al, r6, r6}, "al, r6, r6", "al_r6_r6"},
- {{al, r6, r7}, "al, r6, r7", "al_r6_r7"},
- {{al, r6, r8}, "al, r6, r8", "al_r6_r8"},
- {{al, r6, r9}, "al, r6, r9", "al_r6_r9"},
- {{al, r6, r10}, "al, r6, r10", "al_r6_r10"},
- {{al, r6, r11}, "al, r6, r11", "al_r6_r11"},
- {{al, r6, r12}, "al, r6, r12", "al_r6_r12"},
- {{al, r6, r13}, "al, r6, r13", "al_r6_r13"},
- {{al, r6, r14}, "al, r6, r14", "al_r6_r14"},
- {{al, r7, r0}, "al, r7, r0", "al_r7_r0"},
- {{al, r7, r1}, "al, r7, r1", "al_r7_r1"},
- {{al, r7, r2}, "al, r7, r2", "al_r7_r2"},
- {{al, r7, r3}, "al, r7, r3", "al_r7_r3"},
- {{al, r7, r4}, "al, r7, r4", "al_r7_r4"},
- {{al, r7, r5}, "al, r7, r5", "al_r7_r5"},
- {{al, r7, r6}, "al, r7, r6", "al_r7_r6"},
- {{al, r7, r7}, "al, r7, r7", "al_r7_r7"},
- {{al, r7, r8}, "al, r7, r8", "al_r7_r8"},
- {{al, r7, r9}, "al, r7, r9", "al_r7_r9"},
- {{al, r7, r10}, "al, r7, r10", "al_r7_r10"},
- {{al, r7, r11}, "al, r7, r11", "al_r7_r11"},
- {{al, r7, r12}, "al, r7, r12", "al_r7_r12"},
- {{al, r7, r13}, "al, r7, r13", "al_r7_r13"},
- {{al, r7, r14}, "al, r7, r14", "al_r7_r14"},
- {{al, r8, r0}, "al, r8, r0", "al_r8_r0"},
- {{al, r8, r1}, "al, r8, r1", "al_r8_r1"},
- {{al, r8, r2}, "al, r8, r2", "al_r8_r2"},
- {{al, r8, r3}, "al, r8, r3", "al_r8_r3"},
- {{al, r8, r4}, "al, r8, r4", "al_r8_r4"},
- {{al, r8, r5}, "al, r8, r5", "al_r8_r5"},
- {{al, r8, r6}, "al, r8, r6", "al_r8_r6"},
- {{al, r8, r7}, "al, r8, r7", "al_r8_r7"},
- {{al, r8, r8}, "al, r8, r8", "al_r8_r8"},
- {{al, r8, r9}, "al, r8, r9", "al_r8_r9"},
- {{al, r8, r10}, "al, r8, r10", "al_r8_r10"},
- {{al, r8, r11}, "al, r8, r11", "al_r8_r11"},
- {{al, r8, r12}, "al, r8, r12", "al_r8_r12"},
- {{al, r8, r13}, "al, r8, r13", "al_r8_r13"},
- {{al, r8, r14}, "al, r8, r14", "al_r8_r14"},
- {{al, r9, r0}, "al, r9, r0", "al_r9_r0"},
- {{al, r9, r1}, "al, r9, r1", "al_r9_r1"},
- {{al, r9, r2}, "al, r9, r2", "al_r9_r2"},
- {{al, r9, r3}, "al, r9, r3", "al_r9_r3"},
- {{al, r9, r4}, "al, r9, r4", "al_r9_r4"},
- {{al, r9, r5}, "al, r9, r5", "al_r9_r5"},
+ {{ge, r0, r14}, "ge, r0, r14", "ge_r0_r14"},
+ {{mi, r5, r8}, "mi, r5, r8", "mi_r5_r8"},
+ {{vs, r4, r11}, "vs, r4, r11", "vs_r4_r11"},
+ {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
+ {{gt, r2, r8}, "gt, r2, r8", "gt_r2_r8"},
+ {{gt, r5, r7}, "gt, r5, r7", "gt_r5_r7"},
+ {{pl, r6, r3}, "pl, r6, r3", "pl_r6_r3"},
+ {{ne, r2, r12}, "ne, r2, r12", "ne_r2_r12"},
+ {{hi, r11, r11}, "hi, r11, r11", "hi_r11_r11"},
+ {{vs, r4, r14}, "vs, r4, r14", "vs_r4_r14"},
+ {{vs, r13, r1}, "vs, r13, r1", "vs_r13_r1"},
+ {{cs, r4, r3}, "cs, r4, r3", "cs_r4_r3"},
+ {{eq, r13, r6}, "eq, r13, r6", "eq_r13_r6"},
+ {{gt, r11, r14}, "gt, r11, r14", "gt_r11_r14"},
+ {{vc, r14, r4}, "vc, r14, r4", "vc_r14_r4"},
+ {{vc, r1, r10}, "vc, r1, r10", "vc_r1_r10"},
+ {{mi, r10, r3}, "mi, r10, r3", "mi_r10_r3"},
+ {{vs, r9, r3}, "vs, r9, r3", "vs_r9_r3"},
+ {{vc, r14, r5}, "vc, r14, r5", "vc_r14_r5"},
+ {{ne, r9, r1}, "ne, r9, r1", "ne_r9_r1"},
{{al, r9, r6}, "al, r9, r6", "al_r9_r6"},
- {{al, r9, r7}, "al, r9, r7", "al_r9_r7"},
- {{al, r9, r8}, "al, r9, r8", "al_r9_r8"},
- {{al, r9, r9}, "al, r9, r9", "al_r9_r9"},
- {{al, r9, r10}, "al, r9, r10", "al_r9_r10"},
- {{al, r9, r11}, "al, r9, r11", "al_r9_r11"},
- {{al, r9, r12}, "al, r9, r12", "al_r9_r12"},
- {{al, r9, r13}, "al, r9, r13", "al_r9_r13"},
- {{al, r9, r14}, "al, r9, r14", "al_r9_r14"},
+ {{vc, r7, r8}, "vc, r7, r8", "vc_r7_r8"},
+ {{ls, r6, r9}, "ls, r6, r9", "ls_r6_r9"},
+ {{le, r14, r2}, "le, r14, r2", "le_r14_r2"},
+ {{ls, r9, r13}, "ls, r9, r13", "ls_r9_r13"},
+ {{eq, r1, r5}, "eq, r1, r5", "eq_r1_r5"},
+ {{le, r9, r2}, "le, r9, r2", "le_r9_r2"},
+ {{eq, r2, r1}, "eq, r2, r1", "eq_r2_r1"},
+ {{ls, r9, r11}, "ls, r9, r11", "ls_r9_r11"},
+ {{lt, r7, r13}, "lt, r7, r13", "lt_r7_r13"},
+ {{cc, r8, r7}, "cc, r8, r7", "cc_r8_r7"},
+ {{ls, r5, r1}, "ls, r5, r1", "ls_r5_r1"},
+ {{le, r1, r9}, "le, r1, r9", "le_r1_r9"},
+ {{ls, r8, r14}, "ls, r8, r14", "ls_r8_r14"},
+ {{le, r9, r1}, "le, r9, r1", "le_r9_r1"},
+ {{gt, r1, r6}, "gt, r1, r6", "gt_r1_r6"},
+ {{gt, r11, r10}, "gt, r11, r10", "gt_r11_r10"},
+ {{hi, r0, r12}, "hi, r0, r12", "hi_r0_r12"},
+ {{gt, r1, r7}, "gt, r1, r7", "gt_r1_r7"},
+ {{mi, r7, r1}, "mi, r7, r1", "mi_r7_r1"},
+ {{mi, r7, r0}, "mi, r7, r0", "mi_r7_r0"},
+ {{ls, r1, r3}, "ls, r1, r3", "ls_r1_r3"},
+ {{mi, r13, r3}, "mi, r13, r3", "mi_r13_r3"},
+ {{eq, r4, r3}, "eq, r4, r3", "eq_r4_r3"},
+ {{vc, r14, r9}, "vc, r14, r9", "vc_r14_r9"},
+ {{pl, r3, r1}, "pl, r3, r1", "pl_r3_r1"},
+ {{mi, r0, r2}, "mi, r0, r2", "mi_r0_r2"},
+ {{hi, r2, r7}, "hi, r2, r7", "hi_r2_r7"},
+ {{hi, r13, r12}, "hi, r13, r12", "hi_r13_r12"},
+ {{ls, r12, r8}, "ls, r12, r8", "ls_r12_r8"},
+ {{ne, r5, r6}, "ne, r5, r6", "ne_r5_r6"},
+ {{pl, r5, r4}, "pl, r5, r4", "pl_r5_r4"},
+ {{ge, r1, r6}, "ge, r1, r6", "ge_r1_r6"},
+ {{eq, r8, r10}, "eq, r8, r10", "eq_r8_r10"},
+ {{cs, r5, r4}, "cs, r5, r4", "cs_r5_r4"},
+ {{eq, r11, r6}, "eq, r11, r6", "eq_r11_r6"},
+ {{cs, r13, r3}, "cs, r13, r3", "cs_r13_r3"},
+ {{pl, r2, r8}, "pl, r2, r8", "pl_r2_r8"},
+ {{gt, r10, r0}, "gt, r10, r0", "gt_r10_r0"},
+ {{lt, r4, r10}, "lt, r4, r10", "lt_r4_r10"},
+ {{vs, r14, r14}, "vs, r14, r14", "vs_r14_r14"},
+ {{hi, r0, r7}, "hi, r0, r7", "hi_r0_r7"},
+ {{cc, r9, r6}, "cc, r9, r6", "cc_r9_r6"},
+ {{ne, r7, r13}, "ne, r7, r13", "ne_r7_r13"},
+ {{eq, r2, r6}, "eq, r2, r6", "eq_r2_r6"},
+ {{cs, r12, r12}, "cs, r12, r12", "cs_r12_r12"},
+ {{mi, r3, r10}, "mi, r3, r10", "mi_r3_r10"},
+ {{le, r6, r13}, "le, r6, r13", "le_r6_r13"},
+ {{al, r2, r1}, "al, r2, r1", "al_r2_r1"},
+ {{le, r3, r4}, "le, r3, r4", "le_r3_r4"},
+ {{pl, r4, r4}, "pl, r4, r4", "pl_r4_r4"},
+ {{lt, r12, r3}, "lt, r12, r3", "lt_r12_r3"},
+ {{ls, r7, r4}, "ls, r7, r4", "ls_r7_r4"},
+ {{le, r9, r4}, "le, r9, r4", "le_r9_r4"},
+ {{vc, r13, r3}, "vc, r13, r3", "vc_r13_r3"},
+ {{vc, r8, r8}, "vc, r8, r8", "vc_r8_r8"},
+ {{ge, r2, r8}, "ge, r2, r8", "ge_r2_r8"},
+ {{le, r11, r13}, "le, r11, r13", "le_r11_r13"},
+ {{le, r1, r5}, "le, r1, r5", "le_r1_r5"},
+ {{ge, r9, r12}, "ge, r9, r12", "ge_r9_r12"},
+ {{cs, r14, r14}, "cs, r14, r14", "cs_r14_r14"},
+ {{cc, r1, r0}, "cc, r1, r0", "cc_r1_r0"},
+ {{ge, r3, r0}, "ge, r3, r0", "ge_r3_r0"},
{{al, r10, r0}, "al, r10, r0", "al_r10_r0"},
- {{al, r10, r1}, "al, r10, r1", "al_r10_r1"},
- {{al, r10, r2}, "al, r10, r2", "al_r10_r2"},
- {{al, r10, r3}, "al, r10, r3", "al_r10_r3"},
- {{al, r10, r4}, "al, r10, r4", "al_r10_r4"},
- {{al, r10, r5}, "al, r10, r5", "al_r10_r5"},
- {{al, r10, r6}, "al, r10, r6", "al_r10_r6"},
- {{al, r10, r7}, "al, r10, r7", "al_r10_r7"},
- {{al, r10, r8}, "al, r10, r8", "al_r10_r8"},
- {{al, r10, r9}, "al, r10, r9", "al_r10_r9"},
- {{al, r10, r10}, "al, r10, r10", "al_r10_r10"},
- {{al, r10, r11}, "al, r10, r11", "al_r10_r11"},
- {{al, r10, r12}, "al, r10, r12", "al_r10_r12"},
- {{al, r10, r13}, "al, r10, r13", "al_r10_r13"},
- {{al, r10, r14}, "al, r10, r14", "al_r10_r14"},
- {{al, r11, r0}, "al, r11, r0", "al_r11_r0"},
- {{al, r11, r1}, "al, r11, r1", "al_r11_r1"},
- {{al, r11, r2}, "al, r11, r2", "al_r11_r2"},
- {{al, r11, r3}, "al, r11, r3", "al_r11_r3"},
- {{al, r11, r4}, "al, r11, r4", "al_r11_r4"},
+ {{cc, r11, r10}, "cc, r11, r10", "cc_r11_r10"},
+ {{mi, r11, r11}, "mi, r11, r11", "mi_r11_r11"},
+ {{ne, r12, r7}, "ne, r12, r7", "ne_r12_r7"},
+ {{lt, r4, r12}, "lt, r4, r12", "lt_r4_r12"},
+ {{gt, r14, r5}, "gt, r14, r5", "gt_r14_r5"},
+ {{ge, r1, r7}, "ge, r1, r7", "ge_r1_r7"},
+ {{al, r7, r0}, "al, r7, r0", "al_r7_r0"},
+ {{ls, r2, r0}, "ls, r2, r0", "ls_r2_r0"},
+ {{pl, r6, r11}, "pl, r6, r11", "pl_r6_r11"},
+ {{vc, r0, r6}, "vc, r0, r6", "vc_r0_r6"},
+ {{pl, r6, r9}, "pl, r6, r9", "pl_r6_r9"},
+ {{vs, r8, r1}, "vs, r8, r1", "vs_r8_r1"},
+ {{cs, r1, r6}, "cs, r1, r6", "cs_r1_r6"},
+ {{hi, r4, r11}, "hi, r4, r11", "hi_r4_r11"},
+ {{gt, r5, r5}, "gt, r5, r5", "gt_r5_r5"},
+ {{al, r3, r4}, "al, r3, r4", "al_r3_r4"},
+ {{ge, r11, r12}, "ge, r11, r12", "ge_r11_r12"},
+ {{cc, r14, r2}, "cc, r14, r2", "cc_r14_r2"},
+ {{ge, r2, r4}, "ge, r2, r4", "ge_r2_r4"},
+ {{lt, r5, r11}, "lt, r5, r11", "lt_r5_r11"},
+ {{mi, r11, r14}, "mi, r11, r14", "mi_r11_r14"},
+ {{ne, r3, r3}, "ne, r3, r3", "ne_r3_r3"},
+ {{pl, r14, r0}, "pl, r14, r0", "pl_r14_r0"},
+ {{vc, r4, r10}, "vc, r4, r10", "vc_r4_r10"},
+ {{vs, r6, r8}, "vs, r6, r8", "vs_r6_r8"},
+ {{vc, r4, r7}, "vc, r4, r7", "vc_r4_r7"},
+ {{cs, r11, r10}, "cs, r11, r10", "cs_r11_r10"},
+ {{eq, r11, r8}, "eq, r11, r8", "eq_r11_r8"},
+ {{ne, r9, r2}, "ne, r9, r2", "ne_r9_r2"},
+ {{hi, r9, r7}, "hi, r9, r7", "hi_r9_r7"},
+ {{lt, r0, r6}, "lt, r0, r6", "lt_r0_r6"},
+ {{vc, r5, r8}, "vc, r5, r8", "vc_r5_r8"},
+ {{gt, r3, r1}, "gt, r3, r1", "gt_r3_r1"},
+ {{pl, r3, r5}, "pl, r3, r5", "pl_r3_r5"},
{{al, r11, r5}, "al, r11, r5", "al_r11_r5"},
- {{al, r11, r6}, "al, r11, r6", "al_r11_r6"},
- {{al, r11, r7}, "al, r11, r7", "al_r11_r7"},
- {{al, r11, r8}, "al, r11, r8", "al_r11_r8"},
- {{al, r11, r9}, "al, r11, r9", "al_r11_r9"},
- {{al, r11, r10}, "al, r11, r10", "al_r11_r10"},
- {{al, r11, r11}, "al, r11, r11", "al_r11_r11"},
- {{al, r11, r12}, "al, r11, r12", "al_r11_r12"},
- {{al, r11, r13}, "al, r11, r13", "al_r11_r13"},
- {{al, r11, r14}, "al, r11, r14", "al_r11_r14"},
- {{al, r12, r0}, "al, r12, r0", "al_r12_r0"},
- {{al, r12, r1}, "al, r12, r1", "al_r12_r1"},
- {{al, r12, r2}, "al, r12, r2", "al_r12_r2"},
- {{al, r12, r3}, "al, r12, r3", "al_r12_r3"},
- {{al, r12, r4}, "al, r12, r4", "al_r12_r4"},
- {{al, r12, r5}, "al, r12, r5", "al_r12_r5"},
- {{al, r12, r6}, "al, r12, r6", "al_r12_r6"},
- {{al, r12, r7}, "al, r12, r7", "al_r12_r7"},
- {{al, r12, r8}, "al, r12, r8", "al_r12_r8"},
+ {{hi, r8, r14}, "hi, r8, r14", "hi_r8_r14"},
+ {{le, r5, r4}, "le, r5, r4", "le_r5_r4"},
+ {{ge, r13, r3}, "ge, r13, r3", "ge_r13_r3"},
+ {{pl, r7, r14}, "pl, r7, r14", "pl_r7_r14"},
+ {{cs, r6, r9}, "cs, r6, r9", "cs_r6_r9"},
+ {{lt, r8, r12}, "lt, r8, r12", "lt_r8_r12"},
+ {{cc, r12, r0}, "cc, r12, r0", "cc_r12_r0"},
+ {{mi, r14, r13}, "mi, r14, r13", "mi_r14_r13"},
+ {{pl, r12, r13}, "pl, r12, r13", "pl_r12_r13"},
+ {{al, r4, r8}, "al, r4, r8", "al_r4_r8"},
+ {{ls, r5, r11}, "ls, r5, r11", "ls_r5_r11"},
+ {{ge, r11, r3}, "ge, r11, r3", "ge_r11_r3"},
+ {{le, r1, r0}, "le, r1, r0", "le_r1_r0"},
+ {{gt, r14, r4}, "gt, r14, r4", "gt_r14_r4"},
+ {{ne, r3, r14}, "ne, r3, r14", "ne_r3_r14"},
+ {{cc, r3, r8}, "cc, r3, r8", "cc_r3_r8"},
+ {{eq, r7, r10}, "eq, r7, r10", "eq_r7_r10"},
+ {{pl, r0, r10}, "pl, r0, r10", "pl_r0_r10"},
+ {{mi, r6, r13}, "mi, r6, r13", "mi_r6_r13"},
+ {{gt, r10, r5}, "gt, r10, r5", "gt_r10_r5"},
+ {{ne, r0, r1}, "ne, r0, r1", "ne_r0_r1"},
+ {{ge, r4, r8}, "ge, r4, r8", "ge_r4_r8"},
+ {{cs, r3, r7}, "cs, r3, r7", "cs_r3_r7"},
+ {{pl, r2, r12}, "pl, r2, r12", "pl_r2_r12"},
+ {{ls, r9, r12}, "ls, r9, r12", "ls_r9_r12"},
+ {{ge, r4, r9}, "ge, r4, r9", "ge_r4_r9"},
+ {{lt, r7, r2}, "lt, r7, r2", "lt_r7_r2"},
+ {{hi, r10, r10}, "hi, r10, r10", "hi_r10_r10"},
+ {{ls, r1, r7}, "ls, r1, r7", "ls_r1_r7"},
+ {{vs, r1, r12}, "vs, r1, r12", "vs_r1_r12"},
+ {{ge, r9, r14}, "ge, r9, r14", "ge_r9_r14"},
+ {{pl, r6, r4}, "pl, r6, r4", "pl_r6_r4"},
+ {{ls, r3, r2}, "ls, r3, r2", "ls_r3_r2"},
+ {{cs, r4, r4}, "cs, r4, r4", "cs_r4_r4"},
+ {{eq, r6, r2}, "eq, r6, r2", "eq_r6_r2"},
+ {{ge, r14, r0}, "ge, r14, r0", "ge_r14_r0"},
+ {{le, r11, r6}, "le, r11, r6", "le_r11_r6"},
+ {{vs, r0, r0}, "vs, r0, r0", "vs_r0_r0"},
+ {{vs, r4, r6}, "vs, r4, r6", "vs_r4_r6"},
+ {{gt, r6, r10}, "gt, r6, r10", "gt_r6_r10"},
+ {{vc, r12, r7}, "vc, r12, r7", "vc_r12_r7"},
+ {{gt, r8, r3}, "gt, r8, r3", "gt_r8_r3"},
+ {{hi, r14, r4}, "hi, r14, r4", "hi_r14_r4"},
+ {{hi, r9, r14}, "hi, r9, r14", "hi_r9_r14"},
+ {{vs, r6, r1}, "vs, r6, r1", "vs_r6_r1"},
+ {{hi, r5, r4}, "hi, r5, r4", "hi_r5_r4"},
+ {{lt, r10, r14}, "lt, r10, r14", "lt_r10_r14"},
+ {{cc, r8, r10}, "cc, r8, r10", "cc_r8_r10"},
+ {{lt, r11, r0}, "lt, r11, r0", "lt_r11_r0"},
+ {{ge, r4, r12}, "ge, r4, r12", "ge_r4_r12"},
+ {{cc, r5, r7}, "cc, r5, r7", "cc_r5_r7"},
+ {{gt, r3, r9}, "gt, r3, r9", "gt_r3_r9"},
+ {{vc, r11, r5}, "vc, r11, r5", "vc_r11_r5"},
+ {{lt, r7, r1}, "lt, r7, r1", "lt_r7_r1"},
+ {{lt, r1, r8}, "lt, r1, r8", "lt_r1_r8"},
+ {{hi, r11, r13}, "hi, r11, r13", "hi_r11_r13"},
+ {{vs, r10, r2}, "vs, r10, r2", "vs_r10_r2"},
+ {{ne, r1, r10}, "ne, r1, r10", "ne_r1_r10"},
+ {{vc, r10, r0}, "vc, r10, r0", "vc_r10_r0"},
+ {{al, r2, r2}, "al, r2, r2", "al_r2_r2"},
+ {{ne, r7, r8}, "ne, r7, r8", "ne_r7_r8"},
+ {{hi, r11, r14}, "hi, r11, r14", "hi_r11_r14"},
+ {{ne, r6, r14}, "ne, r6, r14", "ne_r6_r14"},
+ {{ge, r8, r5}, "ge, r8, r5", "ge_r8_r5"},
+ {{vs, r7, r3}, "vs, r7, r3", "vs_r7_r3"},
+ {{ne, r14, r13}, "ne, r14, r13", "ne_r14_r13"},
+ {{hi, r12, r11}, "hi, r12, r11", "hi_r12_r11"},
+ {{ls, r11, r9}, "ls, r11, r9", "ls_r11_r9"},
+ {{mi, r12, r7}, "mi, r12, r7", "mi_r12_r7"},
+ {{cc, r8, r8}, "cc, r8, r8", "cc_r8_r8"},
+ {{ls, r14, r12}, "ls, r14, r12", "ls_r14_r12"},
+ {{ls, r3, r6}, "ls, r3, r6", "ls_r3_r6"},
+ {{hi, r7, r8}, "hi, r7, r8", "hi_r7_r8"},
+ {{vs, r4, r10}, "vs, r4, r10", "vs_r4_r10"},
+ {{ne, r12, r1}, "ne, r12, r1", "ne_r12_r1"},
+ {{vs, r12, r4}, "vs, r12, r4", "vs_r12_r4"},
+ {{hi, r5, r5}, "hi, r5, r5", "hi_r5_r5"},
+ {{gt, r8, r8}, "gt, r8, r8", "gt_r8_r8"},
+ {{lt, r10, r10}, "lt, r10, r10", "lt_r10_r10"},
+ {{vs, r13, r4}, "vs, r13, r4", "vs_r13_r4"},
+ {{mi, r8, r3}, "mi, r8, r3", "mi_r8_r3"},
+ {{eq, r6, r13}, "eq, r6, r13", "eq_r6_r13"},
+ {{al, r2, r0}, "al, r2, r0", "al_r2_r0"},
+ {{ls, r6, r12}, "ls, r6, r12", "ls_r6_r12"},
+ {{vs, r1, r4}, "vs, r1, r4", "vs_r1_r4"},
+ {{vc, r11, r1}, "vc, r11, r1", "vc_r11_r1"},
+ {{ne, r9, r10}, "ne, r9, r10", "ne_r9_r10"},
+ {{ne, r3, r10}, "ne, r3, r10", "ne_r3_r10"},
+ {{hi, r7, r10}, "hi, r7, r10", "hi_r7_r10"},
+ {{pl, r4, r10}, "pl, r4, r10", "pl_r4_r10"},
+ {{le, r7, r1}, "le, r7, r1", "le_r7_r1"},
+ {{gt, r13, r10}, "gt, r13, r10", "gt_r13_r10"},
+ {{lt, r4, r14}, "lt, r4, r14", "lt_r4_r14"},
+ {{al, r10, r1}, "al, r10, r1", "al_r10_r1"},
+ {{mi, r6, r12}, "mi, r6, r12", "mi_r6_r12"},
+ {{eq, r13, r9}, "eq, r13, r9", "eq_r13_r9"},
+ {{ge, r11, r4}, "ge, r11, r4", "ge_r11_r4"},
+ {{hi, r1, r12}, "hi, r1, r12", "hi_r1_r12"},
+ {{ge, r0, r1}, "ge, r0, r1", "ge_r0_r1"},
+ {{lt, r2, r3}, "lt, r2, r3", "lt_r2_r3"},
{{al, r12, r9}, "al, r12, r9", "al_r12_r9"},
- {{al, r12, r10}, "al, r12, r10", "al_r12_r10"},
- {{al, r12, r11}, "al, r12, r11", "al_r12_r11"},
- {{al, r12, r12}, "al, r12, r12", "al_r12_r12"},
- {{al, r12, r13}, "al, r12, r13", "al_r12_r13"},
- {{al, r12, r14}, "al, r12, r14", "al_r12_r14"},
- {{al, r13, r0}, "al, r13, r0", "al_r13_r0"},
- {{al, r13, r1}, "al, r13, r1", "al_r13_r1"},
- {{al, r13, r2}, "al, r13, r2", "al_r13_r2"},
- {{al, r13, r3}, "al, r13, r3", "al_r13_r3"},
- {{al, r13, r4}, "al, r13, r4", "al_r13_r4"},
- {{al, r13, r5}, "al, r13, r5", "al_r13_r5"},
- {{al, r13, r6}, "al, r13, r6", "al_r13_r6"},
- {{al, r13, r7}, "al, r13, r7", "al_r13_r7"},
+ {{hi, r2, r10}, "hi, r2, r10", "hi_r2_r10"},
+ {{mi, r14, r11}, "mi, r14, r11", "mi_r14_r11"},
+ {{pl, r3, r10}, "pl, r3, r10", "pl_r3_r10"},
+ {{vs, r1, r6}, "vs, r1, r6", "vs_r1_r6"},
+ {{al, r7, r6}, "al, r7, r6", "al_r7_r6"},
+ {{ge, r6, r8}, "ge, r6, r8", "ge_r6_r8"},
+ {{eq, r3, r3}, "eq, r3, r3", "eq_r3_r3"},
+ {{ne, r14, r4}, "ne, r14, r4", "ne_r14_r4"},
+ {{vc, r13, r10}, "vc, r13, r10", "vc_r13_r10"},
+ {{mi, r3, r12}, "mi, r3, r12", "mi_r3_r12"},
+ {{pl, r9, r1}, "pl, r9, r1", "pl_r9_r1"},
+ {{hi, r14, r14}, "hi, r14, r14", "hi_r14_r14"},
+ {{ne, r0, r9}, "ne, r0, r9", "ne_r0_r9"},
+ {{mi, r1, r1}, "mi, r1, r1", "mi_r1_r1"},
+ {{hi, r7, r2}, "hi, r7, r2", "hi_r7_r2"},
+ {{gt, r2, r3}, "gt, r2, r3", "gt_r2_r3"},
+ {{eq, r2, r0}, "eq, r2, r0", "eq_r2_r0"},
+ {{vs, r10, r12}, "vs, r10, r12", "vs_r10_r12"},
+ {{gt, r11, r7}, "gt, r11, r7", "gt_r11_r7"},
+ {{vs, r13, r2}, "vs, r13, r2", "vs_r13_r2"},
+ {{ls, r11, r12}, "ls, r11, r12", "ls_r11_r12"},
+ {{al, r8, r8}, "al, r8, r8", "al_r8_r8"},
+ {{hi, r6, r10}, "hi, r6, r10", "hi_r6_r10"},
+ {{vs, r5, r1}, "vs, r5, r1", "vs_r5_r1"},
+ {{ls, r0, r10}, "ls, r0, r10", "ls_r0_r10"},
+ {{gt, r0, r1}, "gt, r0, r1", "gt_r0_r1"},
+ {{ne, r11, r12}, "ne, r11, r12", "ne_r11_r12"},
+ {{ne, r13, r5}, "ne, r13, r5", "ne_r13_r5"},
+ {{mi, r0, r12}, "mi, r0, r12", "mi_r0_r12"},
+ {{lt, r11, r6}, "lt, r11, r6", "lt_r11_r6"},
+ {{eq, r11, r14}, "eq, r11, r14", "eq_r11_r14"},
+ {{vc, r11, r10}, "vc, r11, r10", "vc_r11_r10"},
+ {{cs, r3, r3}, "cs, r3, r3", "cs_r3_r3"},
+ {{le, r12, r2}, "le, r12, r2", "le_r12_r2"},
+ {{hi, r13, r8}, "hi, r13, r8", "hi_r13_r8"},
+ {{pl, r6, r6}, "pl, r6, r6", "pl_r6_r6"},
+ {{al, r4, r5}, "al, r4, r5", "al_r4_r5"},
+ {{hi, r1, r0}, "hi, r1, r0", "hi_r1_r0"},
+ {{ls, r10, r11}, "ls, r10, r11", "ls_r10_r11"},
+ {{al, r8, r7}, "al, r8, r7", "al_r8_r7"},
+ {{vc, r7, r1}, "vc, r7, r1", "vc_r7_r1"},
+ {{ne, r7, r14}, "ne, r7, r14", "ne_r7_r14"},
+ {{lt, r5, r9}, "lt, r5, r9", "lt_r5_r9"},
{{al, r13, r8}, "al, r13, r8", "al_r13_r8"},
- {{al, r13, r9}, "al, r13, r9", "al_r13_r9"},
- {{al, r13, r10}, "al, r13, r10", "al_r13_r10"},
+ {{ls, r6, r14}, "ls, r6, r14", "ls_r6_r14"},
+ {{eq, r12, r0}, "eq, r12, r0", "eq_r12_r0"},
+ {{mi, r8, r14}, "mi, r8, r14", "mi_r8_r14"},
+ {{hi, r13, r2}, "hi, r13, r2", "hi_r13_r2"},
+ {{al, r13, r2}, "al, r13, r2", "al_r13_r2"},
+ {{vs, r8, r9}, "vs, r8, r9", "vs_r8_r9"},
+ {{cc, r6, r2}, "cc, r6, r2", "cc_r6_r2"},
+ {{lt, r8, r0}, "lt, r8, r0", "lt_r8_r0"},
+ {{ls, r3, r13}, "ls, r3, r13", "ls_r3_r13"},
+ {{gt, r10, r14}, "gt, r10, r14", "gt_r10_r14"},
+ {{pl, r9, r8}, "pl, r9, r8", "pl_r9_r8"},
+ {{pl, r14, r11}, "pl, r14, r11", "pl_r14_r11"},
+ {{lt, r9, r3}, "lt, r9, r3", "lt_r9_r3"},
+ {{hi, r9, r0}, "hi, r9, r0", "hi_r9_r0"},
+ {{cc, r9, r3}, "cc, r9, r3", "cc_r9_r3"},
+ {{ge, r10, r14}, "ge, r10, r14", "ge_r10_r14"},
+ {{vs, r2, r1}, "vs, r2, r1", "vs_r2_r1"},
+ {{vc, r4, r13}, "vc, r4, r13", "vc_r4_r13"},
+ {{ls, r1, r9}, "ls, r1, r9", "ls_r1_r9"},
+ {{lt, r13, r11}, "lt, r13, r11", "lt_r13_r11"},
+ {{cs, r2, r10}, "cs, r2, r10", "cs_r2_r10"},
+ {{le, r0, r13}, "le, r0, r13", "le_r0_r13"},
{{al, r13, r11}, "al, r13, r11", "al_r13_r11"},
- {{al, r13, r12}, "al, r13, r12", "al_r13_r12"},
- {{al, r13, r13}, "al, r13, r13", "al_r13_r13"},
- {{al, r13, r14}, "al, r13, r14", "al_r13_r14"},
- {{al, r14, r0}, "al, r14, r0", "al_r14_r0"},
- {{al, r14, r1}, "al, r14, r1", "al_r14_r1"},
- {{al, r14, r2}, "al, r14, r2", "al_r14_r2"},
- {{al, r14, r3}, "al, r14, r3", "al_r14_r3"},
- {{al, r14, r4}, "al, r14, r4", "al_r14_r4"},
- {{al, r14, r5}, "al, r14, r5", "al_r14_r5"},
- {{al, r14, r6}, "al, r14, r6", "al_r14_r6"},
- {{al, r14, r7}, "al, r14, r7", "al_r14_r7"},
- {{al, r14, r8}, "al, r14, r8", "al_r14_r8"},
- {{al, r14, r9}, "al, r14, r9", "al_r14_r9"},
- {{al, r14, r10}, "al, r14, r10", "al_r14_r10"},
- {{al, r14, r11}, "al, r14, r11", "al_r14_r11"},
- {{al, r14, r12}, "al, r14, r12", "al_r14_r12"},
- {{al, r14, r13}, "al, r14, r13", "al_r14_r13"},
- {{al, r14, r14}, "al, r14, r14", "al_r14_r14"}};
+ {{eq, r5, r2}, "eq, r5, r2", "eq_r5_r2"},
+ {{vs, r5, r12}, "vs, r5, r12", "vs_r5_r12"},
+ {{al, r12, r0}, "al, r12, r0", "al_r12_r0"},
+ {{le, r13, r9}, "le, r13, r9", "le_r13_r9"},
+ {{cs, r14, r4}, "cs, r14, r4", "cs_r14_r4"},
+ {{ne, r5, r7}, "ne, r5, r7", "ne_r5_r7"},
+ {{al, r6, r6}, "al, r6, r6", "al_r6_r6"},
+ {{gt, r4, r8}, "gt, r4, r8", "gt_r4_r8"},
+ {{gt, r12, r8}, "gt, r12, r8", "gt_r12_r8"},
+ {{eq, r4, r12}, "eq, r4, r12", "eq_r4_r12"},
+ {{cs, r7, r13}, "cs, r7, r13", "cs_r7_r13"},
+ {{cs, r2, r4}, "cs, r2, r4", "cs_r2_r4"},
+ {{al, r10, r3}, "al, r10, r3", "al_r10_r3"},
+ {{cs, r8, r9}, "cs, r8, r9", "cs_r8_r9"},
+ {{cs, r1, r12}, "cs, r1, r12", "cs_r1_r12"},
+ {{gt, r13, r0}, "gt, r13, r0", "gt_r13_r0"},
+ {{vc, r13, r12}, "vc, r13, r12", "vc_r13_r12"},
+ {{lt, r12, r14}, "lt, r12, r14", "lt_r12_r14"},
+ {{lt, r0, r1}, "lt, r0, r1", "lt_r0_r1"},
+ {{cc, r10, r2}, "cc, r10, r2", "cc_r10_r2"},
+ {{le, r3, r5}, "le, r3, r5", "le_r3_r5"},
+ {{eq, r2, r11}, "eq, r2, r11", "eq_r2_r11"},
+ {{al, r12, r4}, "al, r12, r4", "al_r12_r4"},
+ {{cs, r6, r5}, "cs, r6, r5", "cs_r6_r5"},
+ {{hi, r13, r10}, "hi, r13, r10", "hi_r13_r10"},
+ {{vs, r4, r3}, "vs, r4, r3", "vs_r4_r3"},
+ {{ls, r7, r9}, "ls, r7, r9", "ls_r7_r9"},
+ {{vs, r14, r8}, "vs, r14, r8", "vs_r14_r8"},
+ {{cs, r1, r0}, "cs, r1, r0", "cs_r1_r0"},
+ {{mi, r10, r8}, "mi, r10, r8", "mi_r10_r8"},
+ {{ge, r10, r4}, "ge, r10, r4", "ge_r10_r4"},
+ {{cc, r5, r4}, "cc, r5, r4", "cc_r5_r4"},
+ {{lt, r0, r7}, "lt, r0, r7", "lt_r0_r7"},
+ {{mi, r14, r10}, "mi, r14, r10", "mi_r14_r10"},
+ {{mi, r0, r14}, "mi, r0, r14", "mi_r0_r14"},
+ {{eq, r14, r10}, "eq, r14, r10", "eq_r14_r10"},
+ {{ls, r4, r4}, "ls, r4, r4", "ls_r4_r4"},
+ {{pl, r14, r1}, "pl, r14, r1", "pl_r14_r1"},
+ {{eq, r10, r8}, "eq, r10, r8", "eq_r10_r8"},
+ {{cs, r10, r6}, "cs, r10, r6", "cs_r10_r6"},
+ {{al, r12, r2}, "al, r12, r2", "al_r12_r2"},
+ {{ls, r12, r1}, "ls, r12, r1", "ls_r12_r1"},
+ {{eq, r12, r11}, "eq, r12, r11", "eq_r12_r11"},
+ {{vc, r4, r1}, "vc, r4, r1", "vc_r4_r1"},
+ {{vs, r12, r2}, "vs, r12, r2", "vs_r12_r2"},
+ {{al, r11, r8}, "al, r11, r8", "al_r11_r8"},
+ {{hi, r6, r13}, "hi, r6, r13", "hi_r6_r13"},
+ {{eq, r2, r8}, "eq, r2, r8", "eq_r2_r8"},
+ {{cc, r9, r5}, "cc, r9, r5", "cc_r9_r5"},
+ {{cc, r9, r7}, "cc, r9, r7", "cc_r9_r7"},
+ {{lt, r4, r6}, "lt, r4, r6", "lt_r4_r6"},
+ {{cc, r14, r13}, "cc, r14, r13", "cc_r14_r13"},
+ {{vc, r3, r2}, "vc, r3, r2", "vc_r3_r2"},
+ {{al, r6, r13}, "al, r6, r13", "al_r6_r13"},
+ {{vs, r10, r10}, "vs, r10, r10", "vs_r10_r10"},
+ {{cs, r6, r10}, "cs, r6, r10", "cs_r6_r10"},
+ {{cc, r8, r12}, "cc, r8, r12", "cc_r8_r12"},
+ {{vs, r7, r5}, "vs, r7, r5", "vs_r7_r5"},
+ {{pl, r14, r10}, "pl, r14, r10", "pl_r14_r10"},
+ {{hi, r1, r14}, "hi, r1, r14", "hi_r1_r14"},
+ {{vc, r8, r12}, "vc, r8, r12", "vc_r8_r12"},
+ {{ls, r2, r4}, "ls, r2, r4", "ls_r2_r4"},
+ {{mi, r5, r12}, "mi, r5, r12", "mi_r5_r12"},
+ {{eq, r6, r12}, "eq, r6, r12", "eq_r6_r12"},
+ {{lt, r14, r9}, "lt, r14, r9", "lt_r14_r9"},
+ {{lt, r11, r9}, "lt, r11, r9", "lt_r11_r9"},
+ {{ne, r1, r9}, "ne, r1, r9", "ne_r1_r9"},
+ {{pl, r11, r8}, "pl, r11, r8", "pl_r11_r8"},
+ {{ne, r0, r6}, "ne, r0, r6", "ne_r0_r6"},
+ {{vs, r4, r4}, "vs, r4, r4", "vs_r4_r4"},
+ {{ls, r12, r9}, "ls, r12, r9", "ls_r12_r9"},
+ {{cs, r9, r7}, "cs, r9, r7", "cs_r9_r7"},
+ {{ne, r7, r2}, "ne, r7, r2", "ne_r7_r2"},
+ {{hi, r9, r10}, "hi, r9, r10", "hi_r9_r10"},
+ {{gt, r5, r2}, "gt, r5, r2", "gt_r5_r2"},
+ {{pl, r4, r6}, "pl, r4, r6", "pl_r4_r6"},
+ {{lt, r11, r8}, "lt, r11, r8", "lt_r11_r8"},
+ {{hi, r13, r4}, "hi, r13, r4", "hi_r13_r4"},
+ {{le, r1, r10}, "le, r1, r10", "le_r1_r10"},
+ {{le, r11, r3}, "le, r11, r3", "le_r11_r3"},
+ {{pl, r0, r11}, "pl, r0, r11", "pl_r0_r11"},
+ {{le, r7, r4}, "le, r7, r4", "le_r7_r4"},
+ {{le, r2, r11}, "le, r2, r11", "le_r2_r11"},
+ {{cc, r1, r10}, "cc, r1, r10", "cc_r1_r10"},
+ {{gt, r13, r14}, "gt, r13, r14", "gt_r13_r14"},
+ {{ls, r10, r6}, "ls, r10, r6", "ls_r10_r6"},
+ {{ls, r13, r4}, "ls, r13, r4", "ls_r13_r4"},
+ {{gt, r12, r13}, "gt, r12, r13", "gt_r12_r13"},
+ {{pl, r13, r7}, "pl, r13, r7", "pl_r13_r7"},
+ {{le, r14, r0}, "le, r14, r0", "le_r14_r0"},
+ {{gt, r1, r4}, "gt, r1, r4", "gt_r1_r4"},
+ {{mi, r3, r5}, "mi, r3, r5", "mi_r3_r5"},
+ {{vc, r4, r0}, "vc, r4, r0", "vc_r4_r0"},
+ {{gt, r4, r11}, "gt, r4, r11", "gt_r4_r11"},
+ {{vc, r5, r3}, "vc, r5, r3", "vc_r5_r3"},
+ {{pl, r4, r7}, "pl, r4, r7", "pl_r4_r7"},
+ {{al, r12, r6}, "al, r12, r6", "al_r12_r6"},
+ {{mi, r2, r3}, "mi, r2, r3", "mi_r2_r3"},
+ {{lt, r12, r4}, "lt, r12, r4", "lt_r12_r4"},
+ {{lt, r10, r4}, "lt, r10, r4", "lt_r10_r4"},
+ {{hi, r10, r8}, "hi, r10, r8", "hi_r10_r8"},
+ {{al, r0, r14}, "al, r0, r14", "al_r0_r14"},
+ {{cc, r3, r3}, "cc, r3, r3", "cc_r3_r3"},
+ {{pl, r10, r13}, "pl, r10, r13", "pl_r10_r13"},
+ {{lt, r7, r8}, "lt, r7, r8", "lt_r7_r8"},
+ {{le, r12, r7}, "le, r12, r7", "le_r12_r7"},
+ {{ge, r11, r8}, "ge, r11, r8", "ge_r11_r8"},
+ {{ls, r10, r8}, "ls, r10, r8", "ls_r10_r8"},
+ {{vs, r9, r1}, "vs, r9, r1", "vs_r9_r1"},
+ {{ne, r10, r10}, "ne, r10, r10", "ne_r10_r10"},
+ {{al, r6, r4}, "al, r6, r4", "al_r6_r4"},
+ {{ls, r10, r0}, "ls, r10, r0", "ls_r10_r0"},
+ {{eq, r7, r1}, "eq, r7, r1", "eq_r7_r1"},
+ {{al, r11, r6}, "al, r11, r6", "al_r11_r6"},
+ {{ge, r5, r10}, "ge, r5, r10", "ge_r5_r10"},
+ {{vs, r0, r8}, "vs, r0, r8", "vs_r0_r8"},
+ {{lt, r2, r1}, "lt, r2, r1", "lt_r2_r1"},
+ {{le, r13, r2}, "le, r13, r2", "le_r13_r2"},
+ {{al, r13, r6}, "al, r13, r6", "al_r13_r6"},
+ {{lt, r12, r10}, "lt, r12, r10", "lt_r12_r10"},
+ {{al, r13, r1}, "al, r13, r1", "al_r13_r1"},
+ {{ge, r8, r14}, "ge, r8, r14", "ge_r8_r14"},
+ {{mi, r11, r6}, "mi, r11, r6", "mi_r11_r6"},
+ {{pl, r12, r14}, "pl, r12, r14", "pl_r12_r14"},
+ {{ne, r14, r9}, "ne, r14, r9", "ne_r14_r9"},
+ {{cc, r3, r1}, "cc, r3, r1", "cc_r3_r1"},
+ {{ge, r0, r8}, "ge, r0, r8", "ge_r0_r8"},
+ {{vc, r7, r9}, "vc, r7, r9", "vc_r7_r9"},
+ {{gt, r11, r4}, "gt, r11, r4", "gt_r11_r4"},
+ {{mi, r4, r0}, "mi, r4, r0", "mi_r4_r0"},
+ {{ls, r3, r11}, "ls, r3, r11", "ls_r3_r11"},
+ {{le, r14, r5}, "le, r14, r5", "le_r14_r5"},
+ {{ls, r6, r7}, "ls, r6, r7", "ls_r6_r7"},
+ {{ne, r4, r6}, "ne, r4, r6", "ne_r4_r6"},
+ {{cc, r1, r14}, "cc, r1, r14", "cc_r1_r14"},
+ {{pl, r11, r7}, "pl, r11, r7", "pl_r11_r7"},
+ {{vc, r6, r5}, "vc, r6, r5", "vc_r6_r5"},
+ {{al, r1, r11}, "al, r1, r11", "al_r1_r11"},
+ {{ne, r2, r13}, "ne, r2, r13", "ne_r2_r13"},
+ {{vc, r14, r6}, "vc, r14, r6", "vc_r14_r6"},
+ {{gt, r3, r8}, "gt, r3, r8", "gt_r3_r8"},
+ {{pl, r1, r8}, "pl, r1, r8", "pl_r1_r8"},
+ {{vc, r2, r14}, "vc, r2, r14", "vc_r2_r14"},
+ {{pl, r12, r3}, "pl, r12, r3", "pl_r12_r3"},
+ {{ls, r0, r12}, "ls, r0, r12", "ls_r0_r12"},
+ {{le, r2, r1}, "le, r2, r1", "le_r2_r1"},
+ {{eq, r13, r5}, "eq, r13, r5", "eq_r13_r5"},
+ {{al, r11, r11}, "al, r11, r11", "al_r11_r11"},
+ {{ls, r9, r3}, "ls, r9, r3", "ls_r9_r3"},
+ {{ne, r7, r12}, "ne, r7, r12", "ne_r7_r12"},
+ {{al, r6, r2}, "al, r6, r2", "al_r6_r2"},
+ {{ne, r7, r4}, "ne, r7, r4", "ne_r7_r4"},
+ {{vc, r7, r5}, "vc, r7, r5", "vc_r7_r5"},
+ {{ne, r7, r1}, "ne, r7, r1", "ne_r7_r1"},
+ {{eq, r5, r3}, "eq, r5, r3", "eq_r5_r3"},
+ {{cs, r3, r5}, "cs, r3, r5", "cs_r3_r5"},
+ {{lt, r7, r4}, "lt, r7, r4", "lt_r7_r4"},
+ {{ls, r4, r5}, "ls, r4, r5", "ls_r4_r5"},
+ {{eq, r11, r2}, "eq, r11, r2", "eq_r11_r2"},
+ {{hi, r2, r6}, "hi, r2, r6", "hi_r2_r6"},
+ {{vc, r2, r3}, "vc, r2, r3", "vc_r2_r3"},
+ {{ls, r12, r12}, "ls, r12, r12", "ls_r12_r12"},
+ {{lt, r8, r2}, "lt, r8, r2", "lt_r8_r2"},
+ {{cc, r14, r8}, "cc, r14, r8", "cc_r14_r8"},
+ {{ge, r12, r8}, "ge, r12, r8", "ge_r12_r8"}};
typedef void (MacroAssembler::*Fn)(Condition cond, Register rd, Register rn);
@@ -3550,6 +676,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-memop-immediate-512-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-immediate-512-a32.cc
index fbff988..bf97c6e 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-immediate-512-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-immediate-512-a32.cc
@@ -128,6 +128,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3656,6 +3657,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-memop-immediate-8192-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-immediate-8192-a32.cc
index 85374d3..ffe90e2 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-immediate-8192-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-immediate-8192-a32.cc
@@ -128,6 +128,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3656,6 +3657,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-memop-rs-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-rs-a32.cc
index c4510eb..485b76f 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-rs-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-rs-a32.cc
@@ -132,6 +132,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3679,6 +3680,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc
index 9d7dfbe..f14d4d5 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc
@@ -128,6 +128,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3677,6 +3678,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc
index 10f0b27..02e7ad1 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc
@@ -128,6 +128,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -3677,6 +3678,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-const-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-const-a32.cc
index 4bc418c..4fee497 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-const-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-const-a32.cc
@@ -132,6 +132,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -678,6 +679,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-const-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-const-t32.cc
index 98e9005..1905e06 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-const-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-const-t32.cc
@@ -132,6 +132,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -793,6 +794,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-imm16-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-imm16-t32.cc
index 7491aed..d804e10 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-imm16-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-imm16-t32.cc
@@ -126,6 +126,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -631,6 +632,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-a32.cc
index bacbb7c..dc18df6 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-a32.cc
@@ -138,6 +138,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -820,6 +821,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc
index 4151844..99ac11d 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc
@@ -130,6 +130,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -901,6 +902,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc
index 86004b9..0e4518e 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc
@@ -130,6 +130,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -901,6 +902,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc
index 48d9d65..b59209e 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc
@@ -132,6 +132,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1197,6 +1198,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc
index c6e9251..4685698 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc
@@ -132,6 +132,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1197,6 +1198,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc
index 73bc9f5..5fd66e2 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc
@@ -132,6 +132,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1207,6 +1208,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc
index d13c616..739de36 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc
@@ -132,6 +132,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1207,6 +1208,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc
index 22141c4..3a6c9ac 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc
@@ -132,6 +132,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1913,6 +1914,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc
index 4715541..10d6ebd 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc
@@ -126,6 +126,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1901,6 +1902,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-t32.cc
index 762c1b8..6a42db3 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-t32.cc
@@ -138,6 +138,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -820,6 +821,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-a32.cc
index ae2040a..de83dd2 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-a32.cc
@@ -131,6 +131,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1533,6 +1534,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-const-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-const-a32.cc
index c1e9d73..c9d08f3 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-const-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-const-a32.cc
@@ -144,6 +144,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1814,6 +1815,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-const-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-const-t32.cc
index 56b5b11..ce15a30 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-const-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-const-t32.cc
@@ -144,6 +144,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1838,6 +1839,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-imm12-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-imm12-t32.cc
index db4d598..95ff2dc 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-imm12-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-imm12-t32.cc
@@ -126,6 +126,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1590,6 +1591,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-a32.cc
index b0e9f7f..4cff9e1 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-a32.cc
@@ -158,6 +158,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1322,6 +1323,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc
index 43d3cfc..2bdb318 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc
@@ -130,6 +130,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1323,6 +1324,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc
index ed4acca..2d0fa06 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc
@@ -130,6 +130,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1323,6 +1324,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
index d52e074..b5c8b1e 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
@@ -144,6 +144,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1643,6 +1644,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
index 65a4769..e9be29f 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
@@ -144,6 +144,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1643,6 +1644,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
index 6709626..a3dc602 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
@@ -144,6 +144,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1653,6 +1654,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
index 333e6c6..a4b860e 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
@@ -144,6 +144,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1653,6 +1654,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc
index 68a52fa..d85e9af 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc
@@ -144,6 +144,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -2360,6 +2361,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-t32.cc
index d3c3d3a..ed99e44 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-t32.cc
@@ -158,6 +158,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1322,6 +1323,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-a32-ge.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-a32-ge.cc
index 9f215a6..06fa9da 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-a32-ge.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-a32-ge.cc
@@ -136,6 +136,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -694,6 +695,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-a32-q.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-a32-q.cc
index 574597a..0ed78eb 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-a32-q.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-a32-q.cc
@@ -128,6 +128,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -678,6 +679,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-a32-sel.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-a32-sel.cc
index b5b5880..dd282a6 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-a32-sel.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-a32-sel.cc
@@ -124,6 +124,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -671,6 +672,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-a32.cc
index aedb6bd..4f5fc03 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-a32.cc
@@ -182,6 +182,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1782,6 +1783,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-t32-ge.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-t32-ge.cc
index 38549d4..05aea89 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-t32-ge.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-t32-ge.cc
@@ -136,6 +136,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -694,6 +695,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-t32-q.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-t32-q.cc
index ee1a70a..03a42a7 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-t32-q.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-t32-q.cc
@@ -128,6 +128,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -678,6 +679,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-t32-sel.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-t32-sel.cc
index 9aef13b..b3448eb 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-t32-sel.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-t32-sel.cc
@@ -124,6 +124,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -671,6 +672,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-t32.cc
index 6cd2ff7..2dbf2a5 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-t32.cc
@@ -181,6 +181,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1780,6 +1781,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rd-rn-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-t32.cc
index 8b47a52..3d9ca6e 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-t32.cc
@@ -131,6 +131,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1533,6 +1534,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rdlow-operand-imm8-t32.cc b/test/aarch32/test-simulator-cond-rdlow-operand-imm8-t32.cc
index 2767fcd..f939706 100644
--- a/test/aarch32/test-simulator-cond-rdlow-operand-imm8-t32.cc
+++ b/test/aarch32/test-simulator-cond-rdlow-operand-imm8-t32.cc
@@ -127,6 +127,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1783,6 +1784,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc b/test/aarch32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc
index 67b0302..f588914 100644
--- a/test/aarch32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc
+++ b/test/aarch32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc
@@ -130,6 +130,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1607,6 +1608,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc b/test/aarch32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc
index baf51a7..70265ed 100644
--- a/test/aarch32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc
+++ b/test/aarch32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc
@@ -126,6 +126,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -1105,6 +1106,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-rd-rn-rm-a32.cc b/test/aarch32/test-simulator-rd-rn-rm-a32.cc
index 7d1a8aa..902301a 100644
--- a/test/aarch32/test-simulator-rd-rn-rm-a32.cc
+++ b/test/aarch32/test-simulator-rd-rn-rm-a32.cc
@@ -130,6 +130,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_A32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -858,6 +859,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/aarch32/test-simulator-rd-rn-rm-t32.cc b/test/aarch32/test-simulator-rd-rn-rm-t32.cc
index 6ae3b34..56f4569 100644
--- a/test/aarch32/test-simulator-rd-rn-rm-t32.cc
+++ b/test/aarch32/test-simulator-rd-rn-rm-t32.cc
@@ -130,6 +130,7 @@
// `Inputs` have various layouts across generated tests so they absolutely
// cannot be shared.
+#ifdef VIXL_INCLUDE_TARGET_T32
namespace {
// Values to be passed to the assembler to produce the instruction under test.
@@ -858,6 +859,7 @@
#undef TEST
} // namespace
+#endif
} // namespace aarch32
} // namespace vixl
diff --git a/test/test-code-generation-scopes.cc b/test/test-code-generation-scopes.cc
index a88ad8d..3b312e9 100644
--- a/test/test-code-generation-scopes.cc
+++ b/test/test-code-generation-scopes.cc
@@ -35,6 +35,14 @@
#endif
#define TEST(name) TEST_(SCOPES_##name)
+
+#ifdef VIXL_INCLUDE_TARGET_A32
+#define TEST_A32(name) TEST(name)
+#else
+// Do not add this test to the harness.
+#define TEST_A32(name) void Test##name()
+#endif
+
#define __ masm.
namespace vixl {
@@ -332,7 +340,7 @@
#define ASSERT_LITERAL_POOL_SIZE_32(expected) \
VIXL_CHECK((expected) == masm.GetLiteralPoolSize())
-TEST(EmissionCheckScope_emit_pool_32) {
+TEST_A32(EmissionCheckScope_emit_pool_32) {
aarch32::MacroAssembler masm;
// Make sure the pool is empty;
@@ -408,7 +416,7 @@
#ifdef VIXL_INCLUDE_TARGET_AARCH32
-TEST(EmissionCheckScope_emit_pool_on_Open_32) {
+TEST_A32(EmissionCheckScope_emit_pool_on_Open_32) {
aarch32::MacroAssembler masm;
// Make sure the pool is empty;
@@ -481,7 +489,7 @@
#ifdef VIXL_INCLUDE_TARGET_AARCH32
-TEST(ExactAssemblyScope_basic_32) {
+TEST_A32(ExactAssemblyScope_basic_32) {
aarch32::MacroAssembler masm;
{
@@ -509,7 +517,7 @@
#ifdef VIXL_INCLUDE_TARGET_AARCH32
-TEST(ExactAssemblyScope_Open_32) {
+TEST_A32(ExactAssemblyScope_Open_32) {
aarch32::MacroAssembler masm;
{
@@ -541,7 +549,7 @@
#ifdef VIXL_INCLUDE_TARGET_AARCH32
-TEST(ExactAssemblyScope_Close_32) {
+TEST_A32(ExactAssemblyScope_Close_32) {
aarch32::MacroAssembler masm;
{
@@ -573,7 +581,7 @@
#ifdef VIXL_INCLUDE_TARGET_AARCH32
-TEST(ExactAssemblyScope_Open_Close_32) {
+TEST_A32(ExactAssemblyScope_Open_Close_32) {
aarch32::MacroAssembler masm;
{
@@ -609,7 +617,7 @@
#ifdef VIXL_INCLUDE_TARGET_AARCH32
-TEST(ExactAssemblyScope_32) {
+TEST_A32(ExactAssemblyScope_32) {
aarch32::MacroAssembler masm;
// By default macro instructions are allowed.
@@ -669,7 +677,7 @@
#ifdef VIXL_INCLUDE_TARGET_AARCH32
-TEST(ExactAssemblyScope_scope_with_pools_32) {
+TEST_A32(ExactAssemblyScope_scope_with_pools_32) {
aarch32::MacroAssembler masm;
ASSERT_LITERAL_POOL_SIZE_32(0);
@@ -735,66 +743,6 @@
}
#endif // VIXL_INCLUDE_TARGET_AARCH64
-#ifdef VIXL_INCLUDE_TARGET_AARCH32
-TEST(AssemblerAllowUnpredictable_32) {
- aarch32::Assembler assembler(aarch32::T32);
-
- {
- CodeBufferCheckScope scope(&assembler,
- aarch32::k16BitT32InstructionSizeInBytes);
- aarch32::AllowUnpredictableScope allow_broken_code(&assembler);
- // This instruction is UNPREDICTABLE
- assembler.add(aarch32::pc, aarch32::pc, aarch32::pc);
- }
-
- assembler.FinalizeCode();
-}
-
-TEST(MacroAssemblerAllowUnpredictable_32) {
- aarch32::MacroAssembler masm(aarch32::T32);
-
- {
- ExactAssemblyScope scope(&masm, aarch32::k16BitT32InstructionSizeInBytes);
- aarch32::AllowUnpredictableScope allow_broken_code(&masm);
- // This instruction is UNPREDICTABLE
- __ add(aarch32::pc, aarch32::pc, aarch32::pc);
- }
-
- masm.FinalizeCode();
-}
-
-TEST(AssemblerAllowStronglyDiscouraged_32) {
- aarch32::Assembler assembler(aarch32::T32);
-
- {
- CodeBufferCheckScope scope(&assembler, 6);
- aarch32::AllowStronglyDiscouragedScope allow_discouraged(&assembler);
- // Conditional T32 NEON instructions are discouraged.
- assembler.it(aarch32::ne);
- assembler.vadd(aarch32::ne,
- aarch32::F32,
- aarch32::d0,
- aarch32::d1,
- aarch32::d2);
- }
-
- assembler.FinalizeCode();
-}
-
-TEST(MacroAssemblerAllowStronglyDiscouraged_32) {
- aarch32::MacroAssembler masm(aarch32::T32);
-
- {
- ExactAssemblyScope scope(&masm, 6);
- aarch32::AllowStronglyDiscouragedScope allow_discouraged(&masm);
- // Conditional T32 NEON instructions are discouraged.
- __ it(aarch32::ne);
- __ vadd(aarch32::ne, aarch32::F32, aarch32::d0, aarch32::d1, aarch32::d2);
- }
-
- masm.FinalizeCode();
-}
-#endif
} // namespace vixl
diff --git a/test/test-utils.cc b/test/test-utils.cc
index c480c13..4abcf56 100644
--- a/test/test-utils.cc
+++ b/test/test-utils.cc
@@ -57,7 +57,8 @@
#if defined(__aarch64__) && defined(VIXL_INCLUDE_TARGET_AARCH64)
aarch64::CPU::EnsureIAndDCacheCoherency(buffer, size);
-#elif defined(__arm__) && defined(VIXL_INCLUDE_TARGET_AARCH32)
+#elif defined(__arm__) && \
+ (defined(VIXL_INCLUDE_TARGET_A32) || defined(VIXL_INCLUDE_TARGET_T32))
// TODO: Do not use __builtin___clear_cache and instead implement
// `CPU::EnsureIAndDCacheCoherency` for aarch32.
__builtin___clear_cache(buffer, reinterpret_cast<char*>(buffer) + size);
diff --git a/tools/config.py b/tools/config.py
index 1eb3cbe..7137ec3 100644
--- a/tools/config.py
+++ b/tools/config.py
@@ -43,9 +43,9 @@
# The full list of available build modes.
build_options_modes = ['release', 'debug']
-# The list of target_arch options to test with. Do not list 'both' as an option
-# since it is the default.
-build_options_target_arch = ['aarch32', 'aarch64']
+# The list of target arch/isa options to test with. Do not list 'all' as an
+# option since it is the default.
+build_options_target = ['a32', 't32', 'a32,t32', 'a64', 'a64,a32', 'a64,t32']
# Negative testing is off by default, so do not list 'off' as an option.
build_options_negative_testing = ['on']
# The list of C++ standard to test for.
diff --git a/tools/generate_tests.py b/tools/generate_tests.py
index 342c21f..4a8ac76 100755
--- a/tools/generate_tests.py
+++ b/tools/generate_tests.py
@@ -751,7 +751,8 @@
'check_print_expected': generator.CheckPrintExpected(),
'check_print_found': generator.CheckPrintFound(),
- 'test_name': generator.TestName()
+ 'test_name': generator.TestName(),
+ 'isa_guard': generator.GetIsaGuard()
})
# Create the test case and pipe it through `clang-format` before writing it.
with open(
diff --git a/tools/test.py b/tools/test.py
index d1500d0..7806eed 100755
--- a/tools/test.py
+++ b/tools/test.py
@@ -160,9 +160,9 @@
BuildOption('std', 'Test with the specified C++ standard.',
val_test_choices=['all'] + config.tested_cpp_standards,
strict_choices = False)
-build_option_target_arch = \
- BuildOption('target_arch', 'Test with the specified architectures enabled.',
- val_test_choices=['all'] + config.build_options_target_arch,
+build_option_target = \
+ BuildOption('target', 'Test with the specified isa enabled.',
+ val_test_choices=['all'] + config.build_options_target,
strict_choices = False, test_independently = True)
build_option_negative_testing = \
BuildOption('negative_testing', 'Test with negative testing enabled.',
@@ -171,7 +171,7 @@
test_build_options = [
build_option_mode,
build_option_standard,
- build_option_target_arch,
+ build_option_target,
build_option_negative_testing
]
@@ -351,15 +351,52 @@
return RunCommand(scons_command, list(environment_options))
-def RunBenchmarks(args):
+# Work out if the given options or args allow to run on the specified arch.
+# * arches is a list of ISA/architecture (a64, aarch32, etc)
+# * options are test.py's command line options if any.
+# * args are the arguments given to the build script.
+def CanRunOn(arches, options, args):
+ # First we check in the build specific options.
+ for option in options:
+ if 'target' in option:
+ # The option format is 'target=x,y,z'.
+ for target in (option.split('='))[1].split(','):
+ if target in arches:
+ return True
+
+ # There was a target build option but it didn't include the target arch.
+ return False
+
+ # No specific build option, check the script arguments.
+ # The meaning of 'all' will depend on the platform, e.g. 32-bit compilers
+ # cannot handle Aarch64 while 64-bit compiler can handle Aarch32. To avoid
+ # any issues no benchmarks are run for target='all'.
+ if args.target == 'all': return False
+
+ for target in args.target[0].split(','):
+ if target in arches:
+ return True
+
+ return False
+
+
+def CanRunAarch64(options, args):
+ return CanRunOn(['aarch64', 'a64'], options, args)
+
+
+def CanRunAarch32(options, args):
+ return CanRunOn(['aarch32', 'a32', 't32'], options, args)
+
+
+def RunBenchmarks(options, args):
rc = 0
- if args.target_arch in ['both', 'aarch32']:
+ if CanRunAarch32(options, args):
benchmark_names = util.ListCCFilesWithoutExt(config.dir_aarch32_benchmarks)
for bench in benchmark_names:
rc |= RunCommand(
[os.path.realpath(
join(config.dir_build_latest, 'benchmarks/aarch32', bench))])
- if args.target_arch in ['both', 'aarch64']:
+ if CanRunAarch64(options, args):
benchmark_names = util.ListCCFilesWithoutExt(config.dir_aarch64_benchmarks)
for bench in benchmark_names:
rc |= RunCommand(
@@ -469,7 +506,7 @@
MaybeExitEarly(rc)
if not args.nobench:
- rc |= RunBenchmarks(args)
+ rc |= RunBenchmarks(build_options, args)
MaybeExitEarly(rc)
PrintStatus(rc == 0)
diff --git a/tools/test_generator/generator.py b/tools/test_generator/generator.py
index 6b2ad53..70ca2a5 100644
--- a/tools/test_generator/generator.py
+++ b/tools/test_generator/generator.py
@@ -689,3 +689,14 @@
"w") as f:
code = "static const TestResult *kReference{} = NULL;\n"
f.write(code.format(self.MnemonicToMethodName(mnemonic)))
+
+ def GetIsaGuard(self):
+ """
+ This guard ensure the ISA of the test is enabled.
+ """
+ if 'A32' in self.TestName():
+ return 'VIXL_INCLUDE_TARGET_A32'
+ else:
+ assert 'T32' in self.TestName()
+ return 'VIXL_INCLUDE_TARGET_T32'
+
